From 24b3e8c0ae1c9722b54951f6d5962bafd85f40b6 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Tue, 23 Aug 2016 15:18:18 +0200
Subject: [PATCH 01/89] Enable TLS entropy in targets.json for STM32L4 and
 STM32L0 products

---
 targets/targets.json | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/targets/targets.json b/targets/targets.json
index 5b265b6bff8..eadc38d79f3 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -919,8 +919,7 @@
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "inherits": ["Target"],
         "detect_code": ["0760"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "release_versions": ["2", "5"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
         "device_name": "STM32L073RZ"
     },
     "NUCLEO_L152RE": {
@@ -943,8 +942,8 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0770"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "CAN", "STDIO_MESSAGES"],
-        "release_versions": ["2", "5"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "CAN", "STDIO_MESSAGES", "TRNG"],
+
         "device_name" : "STM32L432KC"
     },
     "NUCLEO_L476RG": {
@@ -955,8 +954,7 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0765"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "release_versions": ["2", "5"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
         "device_name": "stm32l476rg"
     },
     "STM32F3XX": {
@@ -1100,8 +1098,7 @@
         "extra_labels": ["STM", "STM32L4", "STM32L476VG"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "detect_code": ["0820"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "release_versions": ["2", "5"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
         "device_name": "stm32l476vg"
     },
     "MTS_MDOT_F405RG": {

From 0c7a2b5f58ae79469c66e1f9ffdd2a1d4c42af3b Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Thu, 25 Aug 2016 11:52:41 +0200
Subject: [PATCH 02/89] Add random generator for stm32L0 + stm32L4

---
 .../TARGET_STM32L0/entropy_hardware_poll.c    | 83 +++++++++++++++++++
 .../TARGET_STM32L4/entropy_hardware_poll.c    | 80 ++++++++++++++++++
 targets/targets.json                          |  2 +-
 3 files changed, 164 insertions(+), 1 deletion(-)
 create mode 100644 hal/targets/hal/TARGET_STM/TARGET_STM32L0/entropy_hardware_poll.c
 create mode 100644 hal/targets/hal/TARGET_STM/TARGET_STM32L4/entropy_hardware_poll.c

diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/entropy_hardware_poll.c b/hal/targets/hal/TARGET_STM/TARGET_STM32L0/entropy_hardware_poll.c
new file mode 100644
index 00000000000..611a5e3ff1e
--- /dev/null
+++ b/hal/targets/hal/TARGET_STM/TARGET_STM32L0/entropy_hardware_poll.c
@@ -0,0 +1,83 @@
+/*
+ *  Hardware entropy collector for the STM32L0 family
+ *
+ *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ */
+
+
+#if defined (TARGET_STM32L052xx) || defined (TARGET_STM32L053xx) || defined (TARGET_STM32L062xx) ||  defined (TARGET_STM32L063xx) || \
+    defined (TARGET_STM32L072xx) || defined (TARGET_STM32L073xx) || defined (TARGET_STM32L082xx) ||  defined (TARGET_STM32L083xx)
+
+#include <stdlib.h>
+#include "cmsis.h"
+
+/* RNG handler declaration */
+RNG_HandleTypeDef RngHandle;
+
+
+/** rng_get_byte
+ *  @brief Get one byte of entropy from the RNG, assuming it is up and running.
+ *  @param pointer to the hardware generated random byte.
+ */
+static void rng_get_byte( unsigned char *byte )
+{
+    *byte = (unsigned char)HAL_RNG_GetRandomNumber(&RngHandle);
+}
+
+
+/** mbedtls_hardware_poll
+ *  @brief Get len bytes of entropy from the hardware RNG.
+ *  @param data pointer will be NULL
+ *  @param output pointer to the random generated bytes buffer
+ *  @param len input is the requested length of bytes to be generated
+ *  @param olen is the pointer to the length of bytes effectively generated
+ *  @returns 0 if the generation went well. -1 in case of error
+ */
+int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t *olen )
+{
+    int ret;
+    ((void) data);
+
+    /* RNG Peripheral clock enable */
+    __HAL_RCC_RNG_CLK_ENABLE();
+
+    /* Initialize RNG instance */
+    RngHandle.Instance = RNG;
+    HAL_RNG_Init(&RngHandle);
+
+    /* Get Random byte */
+    for( uint32_t i = 0; i < len; i++ ){
+        rng_get_byte( output + i );
+
+    }
+    *olen = len;
+    /* Just be extra sure that we didn't do it wrong */
+    if( ( __HAL_RNG_GET_FLAG(&RngHandle, (RNG_FLAG_CECS|RNG_FLAG_SECS)) ) != 0 ) {
+        ret = -1;
+    } else {
+        ret = 0;
+    }
+    /*Disable the RNG peripheral */
+    HAL_RNG_DeInit(&RngHandle);
+    /* RNG Peripheral clock disable - assume we're the only users of RNG  */
+    __HAL_RCC_RNG_CLK_DISABLE();
+
+
+    return( ret );
+}
+#endif /* STM32L073RZ */
+
diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/entropy_hardware_poll.c b/hal/targets/hal/TARGET_STM/TARGET_STM32L4/entropy_hardware_poll.c
new file mode 100644
index 00000000000..cdae897347b
--- /dev/null
+++ b/hal/targets/hal/TARGET_STM/TARGET_STM32L4/entropy_hardware_poll.c
@@ -0,0 +1,80 @@
+/*
+ *  Hardware entropy collector for the STM32L4 family
+ *
+ *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ */
+
+
+#include <stdlib.h>
+#include "cmsis.h"
+
+/* RNG handler declaration */
+RNG_HandleTypeDef RngHandle;
+
+
+/** rng_get_byte
+ *  @brief Get one byte of entropy from the RNG, assuming it is up and running.
+ *  @param pointer to the hardware generated random byte.
+ */
+static void rng_get_byte( unsigned char *byte )
+{
+    *byte = (unsigned char)HAL_RNG_GetRandomNumber(&RngHandle);
+}
+
+
+/** mbedtls_hardware_poll
+ *  @brief Get len bytes of entropy from the hardware RNG.
+ *  @param data pointer will be NULL
+ *  @param output pointer to the random generated bytes buffer
+ *  @param len input is the requested length of bytes to be generated
+ *  @param olen is the pointer to the length of bytes effectively generated
+ *  @returns 0 if the generation went well. -1 in case of error
+ */
+int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t *olen )
+{
+    int ret;
+    ((void) data);
+
+    /* RNG Peripheral clock enable */
+    __HAL_RCC_RNG_CLK_ENABLE();
+
+    /* Initialize RNG instance */
+    RngHandle.Instance = RNG;
+    HAL_RNG_Init(&RngHandle);
+
+    /* Get Random byte */
+    for( uint32_t i = 0; i < len; i++ ){
+        rng_get_byte( output + i );
+
+    }
+    *olen = len;
+    /* Just be extra sure that we didn't do it wrong */
+    if( ( __HAL_RNG_GET_FLAG(&RngHandle, (RNG_FLAG_CECS|RNG_FLAG_SECS)) ) != 0 ) {
+        ret = -1;
+    } else {
+        ret = 0;
+    }
+    /*Disable the RNG peripheral */
+    HAL_RNG_DeInit(&RngHandle);
+    /* RNG Peripheral clock disable - assume we're the only users of RNG  */
+    __HAL_RCC_RNG_CLK_DISABLE();
+
+
+    return( ret );
+}
+
+
diff --git a/targets/targets.json b/targets/targets.json
index eadc38d79f3..9f78f3319b8 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -915,7 +915,7 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M0+",
         "default_toolchain": "ARM",
-        "extra_labels": ["STM", "STM32L0", "STM32L073RZ"],
+        "extra_labels": ["STM", "STM32L0", "STM32L073RZ", "STM32L073xx"],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "inherits": ["Target"],
         "detect_code": ["0760"],

From 16bc80ef813d8c1d1e049353f57d6487936cd191 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 29 Aug 2016 11:43:51 +0200
Subject: [PATCH 03/89] Add Periphclock enable for L476 products

---
 .../hal/TARGET_STM/TARGET_STM32L4/entropy_hardware_poll.c  | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/entropy_hardware_poll.c b/hal/targets/hal/TARGET_STM/TARGET_STM32L4/entropy_hardware_poll.c
index cdae897347b..e7a880f44ba 100644
--- a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/entropy_hardware_poll.c
+++ b/hal/targets/hal/TARGET_STM/TARGET_STM32L4/entropy_hardware_poll.c
@@ -48,6 +48,12 @@ int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t
 {
     int ret;
     ((void) data);
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+    /*Select PLLQ output as RNG clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
+    PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL;
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 
     /* RNG Peripheral clock enable */
     __HAL_RCC_RNG_CLK_ENABLE();
@@ -73,7 +79,6 @@ int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t
     /* RNG Peripheral clock disable - assume we're the only users of RNG  */
     __HAL_RCC_RNG_CLK_DISABLE();
 
-
     return( ret );
 }
 

From 7864a4f9d58149d7a68de38b96d6bdc16aa8933d Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Thu, 29 Sep 2016 12:16:27 +0200
Subject: [PATCH 04/89] Change MBEDTLS_ENTROPY_ALT to device has TRNG update
 code accordingly

---
 .../{entropy_hardware_poll.c => trng_api.c}   | 61 +++++++++----------
 .../{entropy_hardware_poll.c => trng_api.c}   | 59 +++++++++---------
 targets/TARGET_STM/TARGET_STM32F7/trng_api.c  |  1 +
 .../TARGET_DISCO_L053C8/objects.h             |  4 ++
 .../TARGET_DISCO_L476VG/objects.h             |  4 ++
 .../TARGET_NUCLEO_L432KC/objects.h            |  4 ++
 .../TARGET_NUCLEO_L476RG/objects.h            |  4 ++
 targets/targets.json                          |  5 +-
 8 files changed, 79 insertions(+), 63 deletions(-)
 rename hal/targets/hal/TARGET_STM/TARGET_STM32L0/{entropy_hardware_poll.c => trng_api.c} (63%)
 rename hal/targets/hal/TARGET_STM/TARGET_STM32L4/{entropy_hardware_poll.c => trng_api.c} (63%)

diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/entropy_hardware_poll.c b/hal/targets/hal/TARGET_STM/TARGET_STM32L0/trng_api.c
similarity index 63%
rename from hal/targets/hal/TARGET_STM/TARGET_STM32L0/entropy_hardware_poll.c
rename to hal/targets/hal/TARGET_STM/TARGET_STM32L0/trng_api.c
index 611a5e3ff1e..c8fd7dbe5f7 100644
--- a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/entropy_hardware_poll.c
+++ b/hal/targets/hal/TARGET_STM/TARGET_STM32L0/trng_api.c
@@ -18,66 +18,63 @@
  *
  */
 
+#if defined(DEVICE_TRNG)
 
 #if defined (TARGET_STM32L052xx) || defined (TARGET_STM32L053xx) || defined (TARGET_STM32L062xx) ||  defined (TARGET_STM32L063xx) || \
     defined (TARGET_STM32L072xx) || defined (TARGET_STM32L073xx) || defined (TARGET_STM32L082xx) ||  defined (TARGET_STM32L083xx)
 
 #include <stdlib.h>
 #include "cmsis.h"
+#include "trng_api.h"
 
-/* RNG handler declaration */
-RNG_HandleTypeDef RngHandle;
-
-
-/** rng_get_byte
+/** trng_get_byte
  *  @brief Get one byte of entropy from the RNG, assuming it is up and running.
+ *  @param obj TRNG obj
  *  @param pointer to the hardware generated random byte.
  */
-static void rng_get_byte( unsigned char *byte )
+static void trng_get_byte(trng_t *obj, unsigned char *byte )
 {
-    *byte = (unsigned char)HAL_RNG_GetRandomNumber(&RngHandle);
+    *byte = (unsigned char)HAL_RNG_GetRandomNumber(&obj->handle);
 }
 
-
-/** mbedtls_hardware_poll
- *  @brief Get len bytes of entropy from the hardware RNG.
- *  @param data pointer will be NULL
- *  @param output pointer to the random generated bytes buffer
- *  @param len input is the requested length of bytes to be generated
- *  @param olen is the pointer to the length of bytes effectively generated
- *  @returns 0 if the generation went well. -1 in case of error
- */
-int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t *olen )
+void trng_init(trng_t *obj)
 {
-    int ret;
-    ((void) data);
-
     /* RNG Peripheral clock enable */
     __HAL_RCC_RNG_CLK_ENABLE();
 
     /* Initialize RNG instance */
-    RngHandle.Instance = RNG;
-    HAL_RNG_Init(&RngHandle);
+    obj->handle.Instance = RNG;
+    HAL_RNG_Init(&obj->handle);
 
-    /* Get Random byte */
-    for( uint32_t i = 0; i < len; i++ ){
-        rng_get_byte( output + i );
+}
 
+void trng_free(trng_t *obj)
+{
+    /*Disable the RNG peripheral */
+    HAL_RNG_DeInit(&obj->handle);
+    /* RNG Peripheral clock disable - assume we're the only users of RNG  */
+    __HAL_RCC_RNG_CLK_DISABLE();
+}
+
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
+{
+    int ret;
+
+    /* Get Random byte */
+    for( uint32_t i = 0; i < length; i++ ){
+        trng_get_byte(obj, output + i );
     }
-    *olen = len;
+
+    *output_length = length;
     /* Just be extra sure that we didn't do it wrong */
-    if( ( __HAL_RNG_GET_FLAG(&RngHandle, (RNG_FLAG_CECS|RNG_FLAG_SECS)) ) != 0 ) {
+    if( ( __HAL_RNG_GET_FLAG(&obj->handle, (RNG_FLAG_CECS | RNG_FLAG_SECS)) ) != 0 ) {
         ret = -1;
     } else {
         ret = 0;
     }
-    /*Disable the RNG peripheral */
-    HAL_RNG_DeInit(&RngHandle);
-    /* RNG Peripheral clock disable - assume we're the only users of RNG  */
-    __HAL_RCC_RNG_CLK_DISABLE();
-
 
     return( ret );
 }
 #endif /* STM32L073RZ */
 
+#endif
diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/entropy_hardware_poll.c b/hal/targets/hal/TARGET_STM/TARGET_STM32L4/trng_api.c
similarity index 63%
rename from hal/targets/hal/TARGET_STM/TARGET_STM32L4/entropy_hardware_poll.c
rename to hal/targets/hal/TARGET_STM/TARGET_STM32L4/trng_api.c
index e7a880f44ba..64483b8f12b 100644
--- a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/entropy_hardware_poll.c
+++ b/hal/targets/hal/TARGET_STM/TARGET_STM32L4/trng_api.c
@@ -18,36 +18,24 @@
  *
  */
 
+#if defined(DEVICE_TRNG)
 
 #include <stdlib.h>
 #include "cmsis.h"
+#include "trng_api.h"
 
-/* RNG handler declaration */
-RNG_HandleTypeDef RngHandle;
-
-
-/** rng_get_byte
+/** trng_get_byte
  *  @brief Get one byte of entropy from the RNG, assuming it is up and running.
+ *  @param obj TRNG obj
  *  @param pointer to the hardware generated random byte.
  */
-static void rng_get_byte( unsigned char *byte )
+static void trng_get_byte(trng_t *obj, unsigned char *byte )
 {
-    *byte = (unsigned char)HAL_RNG_GetRandomNumber(&RngHandle);
+    *byte = (unsigned char)HAL_RNG_GetRandomNumber(&obj->handle);
 }
 
-
-/** mbedtls_hardware_poll
- *  @brief Get len bytes of entropy from the hardware RNG.
- *  @param data pointer will be NULL
- *  @param output pointer to the random generated bytes buffer
- *  @param len input is the requested length of bytes to be generated
- *  @param olen is the pointer to the length of bytes effectively generated
- *  @returns 0 if the generation went well. -1 in case of error
- */
-int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t *olen )
+void trng_init(trng_t *obj)
 {
-    int ret;
-    ((void) data);
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
 
     /*Select PLLQ output as RNG clock source */
@@ -59,27 +47,38 @@ int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t
     __HAL_RCC_RNG_CLK_ENABLE();
 
     /* Initialize RNG instance */
-    RngHandle.Instance = RNG;
-    HAL_RNG_Init(&RngHandle);
+    obj->handle.Instance = RNG;
+    HAL_RNG_Init(&obj->handle);
 
-    /* Get Random byte */
-    for( uint32_t i = 0; i < len; i++ ){
-        rng_get_byte( output + i );
+}
 
+void trng_free(trng_t *obj)
+{
+    /*Disable the RNG peripheral */
+    HAL_RNG_DeInit(&obj->handle);
+    /* RNG Peripheral clock disable - assume we're the only users of RNG  */
+    __HAL_RCC_RNG_CLK_DISABLE();
+}
+
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
+{
+    int ret;
+
+    /* Get Random byte */
+    for( uint32_t i = 0; i < length; i++ ){
+        trng_get_byte(obj, output + i );
     }
-    *olen = len;
+
+    *output_length = length;
     /* Just be extra sure that we didn't do it wrong */
-    if( ( __HAL_RNG_GET_FLAG(&RngHandle, (RNG_FLAG_CECS|RNG_FLAG_SECS)) ) != 0 ) {
+    if( ( __HAL_RNG_GET_FLAG(&obj->handle, (RNG_FLAG_CECS | RNG_FLAG_SECS)) ) != 0 ) {
         ret = -1;
     } else {
         ret = 0;
     }
-    /*Disable the RNG peripheral */
-    HAL_RNG_DeInit(&RngHandle);
-    /* RNG Peripheral clock disable - assume we're the only users of RNG  */
-    __HAL_RCC_RNG_CLK_DISABLE();
 
     return( ret );
 }
 
 
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F7/trng_api.c b/targets/TARGET_STM/TARGET_STM32F7/trng_api.c
index ef3595e9b14..f435798f36d 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/trng_api.c
+++ b/targets/TARGET_STM/TARGET_STM32F7/trng_api.c
@@ -26,6 +26,7 @@
 
 /** trng_get_byte
  *  @brief Get one byte of entropy from the RNG, assuming it is up and running.
+ *  @param obj TRNG obj
  *  @param pointer to the hardware generated random byte.
  */
 static void trng_get_byte(trng_t *obj, unsigned char *byte )
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h
index b464a5f2e79..3932d461284 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h
@@ -84,6 +84,10 @@ struct i2c_s {
     I2CName  i2c;
 };
 
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
+
 #include "common_objects.h"
 #include "gpio_object.h"
 
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/objects.h
index 7f1ca3c87d6..20556881d81 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/objects.h
@@ -90,6 +90,10 @@ struct can_s {
     int index;
 };
 
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
+
 #include "common_objects.h"
 #include "gpio_object.h"
 
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/objects.h
index 3aa688ef3a0..c3407b008d6 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/objects.h
@@ -90,6 +90,10 @@ struct can_s {
     int index;
 };
 
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
+
 #include "gpio_object.h"
 #include "common_objects.h"
 
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/objects.h
index 7f1ca3c87d6..20556881d81 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/objects.h
@@ -90,6 +90,10 @@ struct can_s {
     int index;
 };
 
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
+
 #include "common_objects.h"
 #include "gpio_object.h"
 
diff --git a/targets/targets.json b/targets/targets.json
index 9f78f3319b8..45d1be0ea44 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -920,6 +920,7 @@
         "inherits": ["Target"],
         "detect_code": ["0760"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "release_versions": ["2", "5"]
         "device_name": "STM32L073RZ"
     },
     "NUCLEO_L152RE": {
@@ -943,7 +944,7 @@
         "inherits": ["Target"],
         "detect_code": ["0770"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "CAN", "STDIO_MESSAGES", "TRNG"],
-
+        "release_versions": ["2", "5"]
         "device_name" : "STM32L432KC"
     },
     "NUCLEO_L476RG": {
@@ -955,6 +956,7 @@
         "inherits": ["Target"],
         "detect_code": ["0765"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "release_versions": ["2", "5"]
         "device_name": "stm32l476rg"
     },
     "STM32F3XX": {
@@ -1099,6 +1101,7 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "detect_code": ["0820"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "release_versions": ["2", "5"]
         "device_name": "stm32l476vg"
     },
     "MTS_MDOT_F405RG": {

From c8b358877702ba81e3f8ced2cd7a8096672b543a Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Thu, 6 Oct 2016 10:51:33 +0200
Subject: [PATCH 05/89] rework after directory moves

---
 .../hal/TARGET_STM/TARGET_STM32L0/trng_api.c  | 80 ------------------
 targets/TARGET_STM/TARGET_STM32F4/trng_api.c  | 82 -------------------
 targets/TARGET_STM/TARGET_STM32F7/trng_api.c  | 76 -----------------
 .../TARGET_STM}/trng_api.c                    |  8 +-
 4 files changed, 6 insertions(+), 240 deletions(-)
 delete mode 100644 hal/targets/hal/TARGET_STM/TARGET_STM32L0/trng_api.c
 delete mode 100644 targets/TARGET_STM/TARGET_STM32F4/trng_api.c
 delete mode 100644 targets/TARGET_STM/TARGET_STM32F7/trng_api.c
 rename {hal/targets/hal/TARGET_STM/TARGET_STM32L4 => targets/TARGET_STM}/trng_api.c (91%)

diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/trng_api.c b/hal/targets/hal/TARGET_STM/TARGET_STM32L0/trng_api.c
deleted file mode 100644
index c8fd7dbe5f7..00000000000
--- a/hal/targets/hal/TARGET_STM/TARGET_STM32L0/trng_api.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *  Hardware entropy collector for the STM32L0 family
- *
- *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- */
-
-#if defined(DEVICE_TRNG)
-
-#if defined (TARGET_STM32L052xx) || defined (TARGET_STM32L053xx) || defined (TARGET_STM32L062xx) ||  defined (TARGET_STM32L063xx) || \
-    defined (TARGET_STM32L072xx) || defined (TARGET_STM32L073xx) || defined (TARGET_STM32L082xx) ||  defined (TARGET_STM32L083xx)
-
-#include <stdlib.h>
-#include "cmsis.h"
-#include "trng_api.h"
-
-/** trng_get_byte
- *  @brief Get one byte of entropy from the RNG, assuming it is up and running.
- *  @param obj TRNG obj
- *  @param pointer to the hardware generated random byte.
- */
-static void trng_get_byte(trng_t *obj, unsigned char *byte )
-{
-    *byte = (unsigned char)HAL_RNG_GetRandomNumber(&obj->handle);
-}
-
-void trng_init(trng_t *obj)
-{
-    /* RNG Peripheral clock enable */
-    __HAL_RCC_RNG_CLK_ENABLE();
-
-    /* Initialize RNG instance */
-    obj->handle.Instance = RNG;
-    HAL_RNG_Init(&obj->handle);
-
-}
-
-void trng_free(trng_t *obj)
-{
-    /*Disable the RNG peripheral */
-    HAL_RNG_DeInit(&obj->handle);
-    /* RNG Peripheral clock disable - assume we're the only users of RNG  */
-    __HAL_RCC_RNG_CLK_DISABLE();
-}
-
-int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
-{
-    int ret;
-
-    /* Get Random byte */
-    for( uint32_t i = 0; i < length; i++ ){
-        trng_get_byte(obj, output + i );
-    }
-
-    *output_length = length;
-    /* Just be extra sure that we didn't do it wrong */
-    if( ( __HAL_RNG_GET_FLAG(&obj->handle, (RNG_FLAG_CECS | RNG_FLAG_SECS)) ) != 0 ) {
-        ret = -1;
-    } else {
-        ret = 0;
-    }
-
-    return( ret );
-}
-#endif /* STM32L073RZ */
-
-#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/trng_api.c b/targets/TARGET_STM/TARGET_STM32F4/trng_api.c
deleted file mode 100644
index 54ac041e534..00000000000
--- a/targets/TARGET_STM/TARGET_STM32F4/trng_api.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- *  Hardware entropy collector for the STM32F4 family
- *
- *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- */
-
-#if defined(DEVICE_TRNG)
-
-#if defined(TARGET_STM32F405xx) || defined(TARGET_STM32F415xx) || defined(TARGET_STM32F407xx) || defined(TARGET_STM32F417xx) ||\
-    defined(TARGET_STM32F427xx) || defined(TARGET_STM32F437xx) || defined(TARGET_STM32F429xx) || defined(TARGET_STM32F439xx) ||\
-    defined(TARGET_STM32F410Tx) || defined(TARGET_STM32F410Cx) || defined(TARGET_STM32F410Rx) || defined(TARGET_STM32F469xx) ||\
-    defined(TARGET_STM32F479xx)
-#include <stdlib.h>
-#include "cmsis.h"
-#include "trng_api.h"
-
-/** trng_get_byte
- *  @brief Get one byte of entropy from the RNG, assuming it is up and running.
- *  @param obj TRNG obj
- *  @param pointer to the hardware generated random byte.
- */
-static void trng_get_byte(trng_t *obj, unsigned char *byte )
-{
-    *byte = (unsigned char)HAL_RNG_GetRandomNumber(&obj->handle);
-}
-
-void trng_init(trng_t *obj)
-{
-    /* RNG Peripheral clock enable */
-    __HAL_RCC_RNG_CLK_ENABLE();
-
-    /* Initialize RNG instance */
-    obj->handle.Instance = RNG;
-    HAL_RNG_Init(&obj->handle);
-
-}
-
-void trng_free(trng_t *obj)
-{
-    /*Disable the RNG peripheral */
-    HAL_RNG_DeInit(&obj->handle);
-    /* RNG Peripheral clock disable - assume we're the only users of RNG  */
-    __HAL_RCC_RNG_CLK_DISABLE();
-}
-
-int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
-{
-    int ret;
-
-    /* Get Random byte */
-    for( uint32_t i = 0; i < length; i++ ){
-        trng_get_byte(obj, output + i );
-    }
-
-    *output_length = length;
-    /* Just be extra sure that we didn't do it wrong */
-    if( ( __HAL_RNG_GET_FLAG(&obj->handle, (RNG_FLAG_CECS | RNG_FLAG_SECS)) ) != 0 ) {
-        ret = -1;
-    } else {
-        ret = 0;
-    }
-
-    return( ret );
-}
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
-          STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx */
-
-#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F7/trng_api.c b/targets/TARGET_STM/TARGET_STM32F7/trng_api.c
deleted file mode 100644
index f435798f36d..00000000000
--- a/targets/TARGET_STM/TARGET_STM32F7/trng_api.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- *  Hardware entropy collector for the STM32F7 family
- *
- *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- */
-
-#if defined(DEVICE_TRNG)
-
-#include <stdlib.h>
-#include "cmsis.h"
-#include "trng_api.h"
-
-/** trng_get_byte
- *  @brief Get one byte of entropy from the RNG, assuming it is up and running.
- *  @param obj TRNG obj
- *  @param pointer to the hardware generated random byte.
- */
-static void trng_get_byte(trng_t *obj, unsigned char *byte )
-{
-    *byte = (unsigned char)HAL_RNG_GetRandomNumber(&obj->handle);
-}
-
-void trng_init(trng_t *obj)
-{
-    /* RNG Peripheral clock enable */
-    __HAL_RCC_RNG_CLK_ENABLE();
-
-    /* Initialize RNG instance */
-    obj->handle.Instance = RNG;
-    HAL_RNG_Init(&obj->handle);
-
-}
-
-void trng_free(trng_t *obj)
-{
-    /*Disable the RNG peripheral */
-    HAL_RNG_DeInit(&obj->handle);
-    /* RNG Peripheral clock disable - assume we're the only users of RNG  */
-    __HAL_RCC_RNG_CLK_DISABLE();
-}
-
-int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
-{
-    int ret;
-
-    /* Get Random byte */
-    for( uint32_t i = 0; i < length; i++ ){
-        trng_get_byte(obj, output + i );
-    }
-
-    *output_length = length;
-    /* Just be extra sure that we didn't do it wrong */
-    if( ( __HAL_RNG_GET_FLAG(&obj->handle, (RNG_FLAG_CECS | RNG_FLAG_SECS)) ) != 0 ) {
-        ret = -1;
-    } else {
-        ret = 0;
-    }
-
-    return( ret );
-}
-
-#endif
diff --git a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/trng_api.c b/targets/TARGET_STM/trng_api.c
similarity index 91%
rename from hal/targets/hal/TARGET_STM/TARGET_STM32L4/trng_api.c
rename to targets/TARGET_STM/trng_api.c
index 64483b8f12b..f10bf69e06e 100644
--- a/hal/targets/hal/TARGET_STM/TARGET_STM32L4/trng_api.c
+++ b/targets/TARGET_STM/trng_api.c
@@ -1,5 +1,5 @@
 /*
- *  Hardware entropy collector for the STM32L4 family
+ *  Hardware entropy collector for the STM32 families
  *
  *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
  *  SPDX-License-Identifier: Apache-2.0
@@ -36,12 +36,14 @@ static void trng_get_byte(trng_t *obj, unsigned char *byte )
 
 void trng_init(trng_t *obj)
 {
+#if defined(TARGET_STM32L4)
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
 
     /*Select PLLQ output as RNG clock source */
     PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
     PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL;
     HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+#endif
 
     /* RNG Peripheral clock enable */
     __HAL_RCC_RNG_CLK_ENABLE();
@@ -50,6 +52,9 @@ void trng_init(trng_t *obj)
     obj->handle.Instance = RNG;
     HAL_RNG_Init(&obj->handle);
 
+    /* first random number generated after setting the RNGEN bit should not be used */
+    HAL_RNG_GetRandomNumber(&obj->handle);
+
 }
 
 void trng_free(trng_t *obj)
@@ -80,5 +85,4 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l
     return( ret );
 }
 
-
 #endif

From 8d207b1eb7eec3bdae4e2508a60c4eea715525f7 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Thu, 6 Oct 2016 13:49:40 +0200
Subject: [PATCH 06/89] Add objects.h for L073

---
 .../TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h  | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h
index b464a5f2e79..3932d461284 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h
@@ -84,6 +84,10 @@ struct i2c_s {
     I2CName  i2c;
 };
 
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
+
 #include "common_objects.h"
 #include "gpio_object.h"
 

From 33000299fcaedfd1d6ee7d4efa05daab1b545c96 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 10 Oct 2016 17:06:57 +0200
Subject: [PATCH 07/89] Fix typo

---
 targets/targets.json | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/targets/targets.json b/targets/targets.json
index 45d1be0ea44..a6520b94cd6 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -920,7 +920,7 @@
         "inherits": ["Target"],
         "detect_code": ["0760"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
-        "release_versions": ["2", "5"]
+        "release_versions": ["2", "5"],
         "device_name": "STM32L073RZ"
     },
     "NUCLEO_L152RE": {
@@ -944,7 +944,7 @@
         "inherits": ["Target"],
         "detect_code": ["0770"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "CAN", "STDIO_MESSAGES", "TRNG"],
-        "release_versions": ["2", "5"]
+        "release_versions": ["2", "5"],
         "device_name" : "STM32L432KC"
     },
     "NUCLEO_L476RG": {
@@ -956,7 +956,7 @@
         "inherits": ["Target"],
         "detect_code": ["0765"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
-        "release_versions": ["2", "5"]
+        "release_versions": ["2", "5"],
         "device_name": "stm32l476rg"
     },
     "STM32F3XX": {
@@ -1101,7 +1101,7 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "detect_code": ["0820"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
-        "release_versions": ["2", "5"]
+        "release_versions": ["2", "5"],
         "device_name": "stm32l476vg"
     },
     "MTS_MDOT_F405RG": {

From a2fe7c76cd18b53221ff16d749169f28a2c9d2bd Mon Sep 17 00:00:00 2001
From: Kevin Gillespie <kgills@gmail.com>
Date: Fri, 9 Sep 2016 10:53:44 -0500
Subject: [PATCH 08/89] Cleanup with formatting script.

---
 .../TARGET_MAX32620/PeripheralPins.c          |  60 +++++-----
 .../TARGET_Maxim/TARGET_MAX32620/PortNames.h  |   2 +-
 .../TARGET_MAX32620HSP/PinNames.h             |   2 +-
 .../TARGET_MAX32620/analogin_api.c            |   4 +-
 targets/TARGET_Maxim/TARGET_MAX32620/device.h |   2 +-
 .../device/TOOLCHAIN_ARM_STD/MAX32620.sct     |   2 +-
 .../device/TOOLCHAIN_ARM_STD/sys.cpp          |   7 +-
 .../TARGET_MAX32620/device/cmsis.h            |   2 +-
 .../TARGET_MAX32620/device/cmsis_nvic.c       |   2 +-
 .../TARGET_MAX32620/device/ioman_regs.h       | 108 ++++++------------
 .../TARGET_MAX32620/device/pmu_regs.h         |  20 ++--
 .../TARGET_MAX32620/device/system_max32620.c  |   8 +-
 .../TARGET_Maxim/TARGET_MAX32620/gpio_api.c   |   7 +-
 .../TARGET_MAX32620/gpio_irq_api.c            |   2 +-
 .../TARGET_MAX32620/gpio_object.h             |   5 +-
 .../TARGET_Maxim/TARGET_MAX32620/i2c_api.c    |  84 +++++++-------
 targets/TARGET_Maxim/TARGET_MAX32620/pinmap.c |   2 +-
 .../TARGET_Maxim/TARGET_MAX32620/port_api.c   |   4 +-
 .../TARGET_Maxim/TARGET_MAX32620/pwmout_api.c |   6 +-
 .../TARGET_Maxim/TARGET_MAX32620/rtc_api.c    |   6 +-
 .../TARGET_Maxim/TARGET_MAX32620/serial_api.c |  12 +-
 targets/TARGET_Maxim/TARGET_MAX32620/sleep.c  |   8 +-
 .../TARGET_Maxim/TARGET_MAX32620/spi_api.c    |  22 ++--
 .../TARGET_Maxim/TARGET_MAX32620/us_ticker.c  |  21 ++--
 24 files changed, 182 insertions(+), 216 deletions(-)

diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.c b/targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.c
index de32811a768..4e312ea7802 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/PeripheralPins.c
@@ -68,14 +68,14 @@ const PinMap PinMap_I2C_SCL[] = {
 /*
 */
 const PinMap PinMap_UART_TX[] = {
-	{ P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
-	{ P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
-	{ P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
-	{ P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
-	{ P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
-	{ P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
-	{ P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
-	{ P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
+    { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
+    { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
+    { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
+    { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
+    { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
+    { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
+    { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
+    { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_REQ_IO_REQ), (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)}) },
     { NC,   NC,     0 }
 };
 
@@ -157,30 +157,30 @@ const PinMap PinMap_SPI_QUAD[] = {
 
 /************PWM***************/
 const PinMap PinMap_PWM[] = {
-	{ P0_0, PWM_0,  1 }, { P2_0, PWM_0,  1 }, { P4_0, PWM_0,  1 }, {P6_0, PWM_0, 1},
-	{ P0_1, PWM_1,  1 }, { P2_1, PWM_1,  1 }, { P4_1, PWM_1,  1 },
-	{ P0_2, PWM_2,  1 }, { P2_2, PWM_2,  1 }, { P4_2, PWM_2,  1 },
-	{ P0_3, PWM_3,  1 }, { P2_3, PWM_3,  1 }, { P4_3, PWM_3,  1 },
-	{ P0_4, PWM_4,  1 }, { P2_4, PWM_4,  1 }, { P4_4, PWM_4,  1 },
-	{ P0_5, PWM_5,  1 }, { P2_5, PWM_5,  1 }, { P4_5, PWM_5,  1 },
-	{ P0_6, PWM_6,  1 }, { P2_6, PWM_6,  1 }, { P4_6, PWM_6,  1 },
-	{ P0_7, PWM_7,  1 }, { P2_7, PWM_7,  1 }, { P4_7, PWM_7,  1 },
-	{ P1_0, PWM_8,  1 }, { P3_0, PWM_8,  1 }, { P5_0, PWM_8,  1 },
-	{ P1_1, PWM_9,  1 }, { P3_1, PWM_9,  1 }, { P5_1, PWM_9,  1 },
-	{ P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 },
-	{ P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 },
-	{ P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 },
-	{ P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 },
-	{ P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 },
-	{ P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 },
-	{ NC,   NC,    0 }
+    { P0_0, PWM_0,  1 }, { P2_0, PWM_0,  1 }, { P4_0, PWM_0,  1 }, {P6_0, PWM_0, 1},
+    { P0_1, PWM_1,  1 }, { P2_1, PWM_1,  1 }, { P4_1, PWM_1,  1 },
+    { P0_2, PWM_2,  1 }, { P2_2, PWM_2,  1 }, { P4_2, PWM_2,  1 },
+    { P0_3, PWM_3,  1 }, { P2_3, PWM_3,  1 }, { P4_3, PWM_3,  1 },
+    { P0_4, PWM_4,  1 }, { P2_4, PWM_4,  1 }, { P4_4, PWM_4,  1 },
+    { P0_5, PWM_5,  1 }, { P2_5, PWM_5,  1 }, { P4_5, PWM_5,  1 },
+    { P0_6, PWM_6,  1 }, { P2_6, PWM_6,  1 }, { P4_6, PWM_6,  1 },
+    { P0_7, PWM_7,  1 }, { P2_7, PWM_7,  1 }, { P4_7, PWM_7,  1 },
+    { P1_0, PWM_8,  1 }, { P3_0, PWM_8,  1 }, { P5_0, PWM_8,  1 },
+    { P1_1, PWM_9,  1 }, { P3_1, PWM_9,  1 }, { P5_1, PWM_9,  1 },
+    { P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 },
+    { P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 },
+    { P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 },
+    { P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 },
+    { P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 },
+    { P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 },
+    { NC,   NC,    0 }
 };
 
 /************ADC***************/
 const PinMap PinMap_ADC[] = {
-	{ AIN_0, ADC, 0 },
-	{ AIN_1, ADC, 0 },
-	{ AIN_2, ADC, 0 },
-	{ AIN_3, ADC, 0 },
-	{ NC,    NC,  0 }
+    { AIN_0, ADC, 0 },
+    { AIN_1, ADC, 0 },
+    { AIN_2, ADC, 0 },
+    { AIN_3, ADC, 0 },
+    { NC,    NC,  0 }
 };
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/PortNames.h b/targets/TARGET_Maxim/TARGET_MAX32620/PortNames.h
index 56100a806af..e44f78c4c39 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/PortNames.h
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/PortNames.h
@@ -30,7 +30,7 @@
  * ownership rights.
  *******************************************************************************
  */
- 
+
 #ifndef MBED_PORTNAMES_H
 #define MBED_PORTNAMES_H
 
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PinNames.h b/targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PinNames.h
index 0ba72913b5d..559730a359b 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PinNames.h
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/TARGET_MAX32620HSP/PinNames.h
@@ -116,7 +116,7 @@ typedef enum {
     AIN_3 = (0xA << PORT_SHIFT) | 3,
 
     // LEDs
-	LED_RED = P2_0,
+    LED_RED = P2_0,
     LED1 = LED_RED,
     LED2 = NOT_CONNECTED,
     LED3 = NOT_CONNECTED,
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/analogin_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/analogin_api.c
index 2a397e0e2ad..84f34c73973 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/analogin_api.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/analogin_api.c
@@ -49,7 +49,7 @@
 
 // Only allow initialization once
 static int initialized = 0;
- 
+
 //******************************************************************************
 void analogin_init(analogin_t *obj, PinName pin)
 {
@@ -86,7 +86,7 @@ void analogin_init(analogin_t *obj, PinName pin)
 
         // Enable ADC power bypass the buffer
         obj->adc->ctrl |= (MXC_F_ADC_CTRL_ADC_PU | MXC_F_ADC_CTRL_ADC_REFBUF_PU |
-                        MXC_F_ADC_CTRL_ADC_CHGPUMP_PU | MXC_F_ADC_CTRL_BUF_BYPASS);
+                           MXC_F_ADC_CTRL_ADC_CHGPUMP_PU | MXC_F_ADC_CTRL_BUF_BYPASS);
 
         // Wait for ADC ready
         while (!(obj->adc->intr & MXC_F_ADC_INTR_ADC_REF_READY_IF));
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device.h b/targets/TARGET_Maxim/TARGET_MAX32620/device.h
index af8fe76bb02..aff47659247 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device.h
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device.h
@@ -32,7 +32,7 @@
  * ownership rights.
  *******************************************************************************
  */
- 
+
 #ifndef MBED_DEVICE_H
 #define MBED_DEVICE_H
 #include "objects.h"
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/MAX32620.sct b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/MAX32620.sct
index 9be03baf111..77c2cb1a5c0 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/MAX32620.sct
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/MAX32620.sct
@@ -14,7 +14,7 @@ LR_IROM1 0x00000000 0x200000  {    ; load region size_region
     }
 
     ; [RAM] Vector table dynamic copy: 65 vectors * 4 bytes = 260 (0x104) + 4
-	; for 8 byte alignment
+    ; for 8 byte alignment
     RW_IRAM1 (0x20000000+0x108) (0x40000-0x108)  {  ; RW data
         .ANY (+RW +ZI)
     }
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/sys.cpp
index b6c24b38364..18b451c0e0d 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/sys.cpp
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/sys.cpp
@@ -36,11 +36,12 @@
 
 #ifdef __cplusplus
 extern "C" {
-#endif 
+#endif
 
 extern char Image$$RW_IRAM1$$ZI$$Limit[];
 
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
     uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
     uint32_t sp_limit = __current_sp();
 
@@ -54,4 +55,4 @@ extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_
 
 #ifdef __cplusplus
 }
-#endif 
+#endif
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis.h
index 075790296e7..6bd3ab1b358 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis.h
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis.h
@@ -30,7 +30,7 @@
  * ownership rights.
  *******************************************************************************
  */
- 
+
 #ifndef MBED_CMSIS_H
 #define MBED_CMSIS_H
 
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis_nvic.c b/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis_nvic.c
index 98cfd205a6f..22b7e08ed01 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis_nvic.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/cmsis_nvic.c
@@ -30,7 +30,7 @@
  * ownership rights.
  *******************************************************************************
  */
- 
+
 #include "cmsis_nvic.h"
 
 #if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM_STD)
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/ioman_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/ioman_regs.h
index c20930418a4..427ca5e4dad 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/ioman_regs.h
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/ioman_regs.h
@@ -72,72 +72,63 @@ typedef enum {
     Bitfield structs for registers in this module
 */
 
-typedef struct
-{
+typedef struct {
     uint32_t wud_req_p0 : 8;
     uint32_t wud_req_p1 : 8;
     uint32_t wud_req_p2 : 8;
     uint32_t wud_req_p3 : 8;
 } mxc_ioman_wud_req0_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t wud_req_p4 : 8;
     uint32_t wud_req_p5 : 8;
     uint32_t wud_req_p6 : 1;
     uint32_t            : 15;
 } mxc_ioman_wud_req1_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t wud_ack_p0 : 8;
     uint32_t wud_ack_p1 : 8;
     uint32_t wud_ack_p2 : 8;
     uint32_t wud_ack_p3 : 8;
 } mxc_ioman_wud_ack0_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t wud_ack_p4 : 8;
     uint32_t wud_ack_p5 : 8;
     uint32_t wud_ack_p6 : 1;
     uint32_t            : 15;
 } mxc_ioman_wud_ack1_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t ali_req_p0 : 8;
     uint32_t ali_req_p1 : 8;
     uint32_t ali_req_p2 : 8;
     uint32_t ali_req_p3 : 8;
 } mxc_ioman_ali_req0_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t ali_req_p4 : 8;
     uint32_t ali_req_p5 : 8;
     uint32_t ali_req_p6 : 1;
     uint32_t            : 15;
 } mxc_ioman_ali_req1_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t ali_ack_p0 : 8;
     uint32_t ali_ack_p1 : 8;
     uint32_t ali_ack_p2 : 8;
     uint32_t ali_ack_p3 : 8;
 } mxc_ioman_ali_ack0_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t ali_ack_p4 : 8;
     uint32_t ali_ack_p5 : 8;
     uint32_t ali_ack_p6 : 1;
     uint32_t            : 15;
 } mxc_ioman_ali_ack1_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t core_io_req : 1;
     uint32_t             : 3;
@@ -151,8 +142,7 @@ typedef struct
     uint32_t             : 15;
 } mxc_ioman_spix_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t core_io_ack : 1;
     uint32_t             : 3;
@@ -166,8 +156,7 @@ typedef struct
     uint32_t             : 15;
 } mxc_ioman_spix_ack_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t io_map     : 1;
     uint32_t cts_map    : 1;
     uint32_t rts_map    : 1;
@@ -178,8 +167,7 @@ typedef struct
     uint32_t            : 25;
 } mxc_ioman_uart0_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t io_map     : 1;
     uint32_t cts_map    : 1;
     uint32_t rts_map    : 1;
@@ -190,8 +178,7 @@ typedef struct
     uint32_t            : 25;
 } mxc_ioman_uart0_ack_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t io_map     : 1;
     uint32_t cts_map    : 1;
     uint32_t rts_map    : 1;
@@ -202,8 +189,7 @@ typedef struct
     uint32_t            : 25;
 } mxc_ioman_uart1_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t io_map     : 1;
     uint32_t cts_map    : 1;
     uint32_t rts_map    : 1;
@@ -214,8 +200,7 @@ typedef struct
     uint32_t            : 25;
 } mxc_ioman_uart1_ack_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t io_map     : 1;
     uint32_t cts_map    : 1;
     uint32_t rts_map    : 1;
@@ -226,8 +211,7 @@ typedef struct
     uint32_t            : 25;
 } mxc_ioman_uart2_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t io_map     : 1;
     uint32_t cts_map    : 1;
     uint32_t rts_map    : 1;
@@ -238,8 +222,7 @@ typedef struct
     uint32_t            : 25;
 } mxc_ioman_uart2_ack_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t io_map     : 1;
     uint32_t cts_map    : 1;
     uint32_t rts_map    : 1;
@@ -250,8 +233,7 @@ typedef struct
     uint32_t            : 25;
 } mxc_ioman_uart3_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t io_map     : 1;
     uint32_t cts_map    : 1;
     uint32_t rts_map    : 1;
@@ -262,66 +244,57 @@ typedef struct
     uint32_t            : 25;
 } mxc_ioman_uart3_ack_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t mapping_req : 1;
     uint32_t             : 27;
 } mxc_ioman_i2cm0_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t mapping_ack : 1;
     uint32_t             : 27;
 } mxc_ioman_i2cm0_ack_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t mapping_req : 1;
     uint32_t             : 27;
 } mxc_ioman_i2cm1_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t mapping_ack : 1;
     uint32_t             : 27;
 } mxc_ioman_i2cm1_ack_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t mapping_req : 1;
     uint32_t             : 27;
 } mxc_ioman_i2cm2_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t mapping_ack : 1;
     uint32_t             : 27;
 } mxc_ioman_i2cm2_ack_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t io_sel      : 2;
     uint32_t             : 2;
     uint32_t mapping_req : 1;
     uint32_t             : 27;
 } mxc_ioman_i2cs_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t io_sel      : 2;
     uint32_t             : 2;
     uint32_t mapping_ack : 1;
     uint32_t             : 27;
 } mxc_ioman_i2cs_ack_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t core_io_req : 1;
     uint32_t             : 3;
@@ -337,8 +310,7 @@ typedef struct
     uint32_t             : 7;
 } mxc_ioman_spim0_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t core_io_ack : 1;
     uint32_t             : 3;
@@ -354,8 +326,7 @@ typedef struct
     uint32_t             : 7;
 } mxc_ioman_spim0_ack_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t core_io_req : 1;
     uint32_t             : 3;
@@ -369,8 +340,7 @@ typedef struct
     uint32_t             : 7;
 } mxc_ioman_spim1_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t core_io_ack : 1;
     uint32_t             : 3;
@@ -384,8 +354,7 @@ typedef struct
     uint32_t             : 7;
 } mxc_ioman_spim1_ack_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t mapping_req : 1;
     uint32_t             : 3;
     uint32_t core_io_req : 1;
@@ -403,8 +372,7 @@ typedef struct
     uint32_t             : 7;
 } mxc_ioman_spim2_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t mapping_ack : 1;
     uint32_t             : 3;
     uint32_t core_io_ack : 1;
@@ -422,8 +390,7 @@ typedef struct
     uint32_t             : 7;
 } mxc_ioman_spim2_ack_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t core_io_req : 1;
     uint32_t             : 3;
@@ -433,8 +400,7 @@ typedef struct
     uint32_t             : 19;
 } mxc_ioman_spib_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t core_io_ack : 1;
     uint32_t             : 3;
@@ -444,16 +410,14 @@ typedef struct
     uint32_t             : 19;
 } mxc_ioman_spib_ack_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t mapping_req : 1;
     uint32_t epu_io_req  : 1;
     uint32_t             : 26;
 } mxc_ioman_owm_req_t;
 
-typedef struct
-{
+typedef struct {
     uint32_t             : 4;
     uint32_t mapping_ack : 1;
     uint32_t epu_io_ack  : 1;
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/pmu_regs.h b/targets/TARGET_Maxim/TARGET_MAX32620/device/pmu_regs.h
index 2c75d236cfd..2055a9684a1 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/pmu_regs.h
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/pmu_regs.h
@@ -57,20 +57,20 @@ extern "C" {
 typedef struct {
     __IO uint32_t start_opcode[32];
     __IO uint32_t enable;
-    __IO uint32_t rsvd0; 
+    __IO uint32_t rsvd0;
     __IO uint32_t ll_stopped;
-    __IO uint32_t manual; 
-    __IO uint32_t bus_error; 
-    __IO uint32_t rsvd1; 
-    __IO uint32_t to_stat; 
-    __IO uint32_t rsvd2[4]; 
-    __IO uint32_t to_sel[3]; 
+    __IO uint32_t manual;
+    __IO uint32_t bus_error;
+    __IO uint32_t rsvd1;
+    __IO uint32_t to_stat;
+    __IO uint32_t rsvd2[4];
+    __IO uint32_t to_sel[3];
     __IO uint32_t ps_sel[2];
-    __IO uint32_t interrupt; 
+    __IO uint32_t interrupt;
     __IO uint32_t int_enable;
-    __IO uint32_t rsvd3[6]; 
+    __IO uint32_t rsvd3[6];
     __IO uint32_t burst_size[5];
-    __IO uint32_t rsvd4[3];  
+    __IO uint32_t rsvd4[3];
     __IO uint32_t padding[192]; /* Offset to next channel */
 } mxc_pmu_bits_t;
 
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c b/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c
index 461e50d0d62..d3e6b77e147 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c
@@ -58,7 +58,7 @@ uint32_t SystemCoreClock = RO_FREQ;
 void SystemCoreClockUpdate(void)
 {
     switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) {
-             
+
         case MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2:
         default:
             SystemCoreClock = RO_FREQ / 2;
@@ -187,11 +187,11 @@ void SystemInit(void)
     // Clear all unused wakeup sources
     // Beware! Do not change any flag not mentioned here, as they will gate important power sequencer signals
     MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP |
-			       MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP);
+                               MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP);
 
     // RTC sources are inverted, so a 1 will disable them
     MXC_PWRSEQ->msk_flags |= (MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 |
-			      MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP);
+                              MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP);
 
     /* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */
     MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
@@ -206,7 +206,7 @@ void SystemInit(void)
     SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
     __DSB();
     __ISB();
-#endif  
+#endif
 
     // Trim ring oscillator
     Trim_ROAtomic();
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/gpio_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/gpio_api.c
index 2f745d7d9cb..b4f988fd2e2 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/gpio_api.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/gpio_api.c
@@ -85,11 +85,10 @@ void pin_dir(PinName name, PinDirection direction)
     if (direction == PIN_INPUT) {
         /* Set requested output mode */
         MXC_GPIO->out_mode[port] = (MXC_GPIO->out_mode[port] & ~(0xF << (4 * pin))) | (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * pin));
-        
+
         /* Enable default input weak pull-up by setting corresponding output */
         MXC_GPIO->out_val[port] |= 1 << pin;
-    }
-    else {
+    } else {
         /* Set requested output mode */
         MXC_GPIO->out_mode[port] = (MXC_GPIO->out_mode[port] & ~(0xF << (4 * pin))) | (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * pin));
     }
@@ -97,5 +96,5 @@ void pin_dir(PinName name, PinDirection direction)
 
 void gpio_dir(gpio_t *obj, PinDirection direction)
 {
-   pin_dir(obj->name, direction);
+    pin_dir(obj->name, direction);
 }
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c
index 07bf71e5fc3..dd00bea21d3 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c
@@ -233,7 +233,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint3
 
 void gpio_irq_free(gpio_irq_t *obj)
 {
-   /* disable interrupt */
+    /* disable interrupt */
     MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
     MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
     objs[obj->port][obj->pin] = NULL;
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/gpio_object.h b/targets/TARGET_Maxim/TARGET_MAX32620/gpio_object.h
index 01107a86afb..8281590e770 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/gpio_object.h
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/gpio_object.h
@@ -30,7 +30,7 @@
  * ownership rights.
  *******************************************************************************
  */
- 
+
 #ifndef MBED_GPIO_OBJECT_H
 #define MBED_GPIO_OBJECT_H
 
@@ -60,7 +60,8 @@ static inline int gpio_read(gpio_t *obj)
 
 void pin_dir(PinName name, PinDirection direction);
 
-static inline int gpio_is_connected(const gpio_t *obj) {
+static inline int gpio_is_connected(const gpio_t *obj)
+{
     return obj->name != (PinName)NC;
 }
 
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/i2c_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/i2c_api.c
index 2c5916485fc..ac25d699b01 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/i2c_api.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/i2c_api.c
@@ -60,42 +60,42 @@ typedef enum {
 static const uint32_t clk_div_table[2][8] = {
     /* MXC_E_I2CM_SPEED_100KHZ */
     {
-		/* 0: 12MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
-				(17 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
-				(72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
-		/* 1: 24MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
-				(38 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
-				(144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
-		/* 2:       */ 0, /* not supported */
-		/* 3: 48MHz */ ((24 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
-				(80 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
-				(288 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
-		/* 4:       */ 0, /* not supported */
-		/* 5:       */ 0, /* not supported */
-		/* 6:       */ 0, /* not supported */
-		/* 7: 96MHz */ ((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
-				(164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
-				(576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
-	},
-	/* MXC_E_I2CM_SPEED_400KHZ */
-	{
-		/* 0: 12MHz */ ((2 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
-				(1 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
-				(18 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
-		/* 1: 24MHz */ ((3 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
-				(5 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
-				(36 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
-		/* 2:       */ 0, /* not supported */
-		/* 3: 48MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
-				(15 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
-				(72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
-		/* 4:       */ 0, /* not supported */
-		/* 5:       */ 0, /* not supported */
-		/* 6:       */ 0, /* not supported */
-		/* 7: 96MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
-				(33 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
-				(144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
-	},
+        /* 0: 12MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+                        (17 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+                        (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+        /* 1: 24MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+                        (38 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+                        (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+        /* 2:       */ 0, /* not supported */
+        /* 3: 48MHz */ ((24 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+                        (80 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+                        (288 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+        /* 4:       */ 0, /* not supported */
+        /* 5:       */ 0, /* not supported */
+        /* 6:       */ 0, /* not supported */
+        /* 7: 96MHz */ ((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+                        (164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+                        (576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+    },
+    /* MXC_E_I2CM_SPEED_400KHZ */
+    {
+        /* 0: 12MHz */ ((2 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+                        (1 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+                        (18 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+        /* 1: 24MHz */ ((3 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+                        (5 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+                        (36 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+        /* 2:       */ 0, /* not supported */
+        /* 3: 48MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+                        (15 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+                        (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+        /* 4:       */ 0, /* not supported */
+        /* 5:       */ 0, /* not supported */
+        /* 6:       */ 0, /* not supported */
+        /* 7: 96MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+                        (33 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+                        (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+    },
 };
 
 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
@@ -109,7 +109,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
     obj->i2c = i2c;
     obj->fifos = (mxc_i2cm_fifo_regs_t*)MXC_I2CM_GET_BASE_FIFO(MXC_I2CM_GET_IDX(i2c));
     obj->start_pending = 0;
-	obj->stop_pending = 0;
+    obj->stop_pending = 0;
 
     // configure the pins
     pinmap_pinout(sda, PinMap_I2C_SDA);
@@ -135,10 +135,10 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
 void i2c_frequency(i2c_t *obj, int hz)
 {
     // compute clock array index
-	// (96Mhz/12M) -1 = 7
-	// (48Mhz/12M) -1 = 3
-	// (24Mhz/12M) -1 = 1
-	// (12Mhz/12M) -1 = 0
+    // (96Mhz/12M) -1 = 7
+    // (48Mhz/12M) -1 = 3
+    // (24Mhz/12M) -1 = 1
+    // (12Mhz/12M) -1 = 0
     int clki = (SystemCoreClock / 12000000) - 1;
 
     // get clock divider settings from lookup table
@@ -318,7 +318,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
     }
 
     if (stop) {
-		obj->stop_pending = 0;
+        obj->stop_pending = 0;
         if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
             retval = (retval ? retval : err);
         }
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/pinmap.c b/targets/TARGET_Maxim/TARGET_MAX32620/pinmap.c
index 2b0b75bfdf8..e10b0fb5b99 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/pinmap.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/pinmap.c
@@ -30,7 +30,7 @@
  * ownership rights.
  *******************************************************************************
  */
- 
+
 #include "mbed_assert.h"
 #include "pinmap.h"
 #include "objects.h"
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/port_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/port_api.c
index 58dc6bbbf45..2c72603bb7c 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/port_api.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/port_api.c
@@ -30,7 +30,7 @@
  * ownership rights.
  *******************************************************************************
  */
- 
+
 #include "port_api.h"
 #include "pinmap.h"
 #include "gpio_api.h"
@@ -50,7 +50,7 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
     obj->reg_in  = &MXC_GPIO->in_val[port];
 
     /* Ensure that the GPIO clock is enabled */
-	MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
+    MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
 
     uint32_t i;
     // The function is set per pin: reuse gpio logic
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/pwmout_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/pwmout_api.c
index 5e6c8f14724..fa424ceda9a 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/pwmout_api.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/pwmout_api.c
@@ -79,7 +79,7 @@ void pwmout_init(pwmout_t* obj, PinName pin)
     obj->pwm = (mxc_pt_regs_t*)pwm.peripheral;
 
     // Initialize object period and pulse width
-    obj->period = -1; 
+    obj->period = -1;
     obj->pulse_width = -1;
 
     // Disable the output
@@ -114,7 +114,7 @@ static void pwmout_update(pwmout_t* obj)
 {
     // Calculate and set the divider ratio
     int div = (obj->period * (SystemCoreClock/1000000))/32;
-    if (div < 2){
+    if (div < 2) {
         div = 2;
     }
     MXC_SET_FIELD(&obj->pwm->rate_length, MXC_F_PT_RATE_LENGTH_RATE_CONTROL, div);
@@ -142,7 +142,7 @@ void pwmout_write(pwmout_t* obj, float percent)
 float pwmout_read(pwmout_t* obj)
 {
     // Check for when pulsewidth or period equals 0
-    if ((obj->pulse_width == 0) || (obj->period == 0)){
+    if ((obj->pulse_width == 0) || (obj->period == 0)) {
         return 0;
     }
 
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c
index dd9c402fc65..bf50d87b7fe 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c
@@ -83,7 +83,7 @@ static uint64_t rtc_read64(void);
 //******************************************************************************
 static void overflow_handler(void)
 {
-    MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS; 
+    MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
     overflow_cnt++;
 
     // Wait for pending transactions
@@ -271,7 +271,7 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
     }
 
     MXC_RTCTMR->comp[0] = comp_value;
-    MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS; 
+    MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
     MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; // enable the interrupt
 
     // Enable wakeup from RTC
@@ -290,7 +290,7 @@ inline void lp_ticker_disable_interrupt(void)
 //******************************************************************************
 inline void lp_ticker_clear_interrupt(void)
 {
-    MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS; 
+    MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
 
     // Wait for pending transactions
     while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/serial_api.c
index 105449bb7bf..82f5da39231 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/serial_api.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/serial_api.c
@@ -92,7 +92,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
     // To support the most common baud rates, 9600 and 115200, we need to
     // scale down the uart input clock.
     if (!(MXC_CLKMAN->sys_clk_ctrl_8_uart & MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE)) {
-         
+
         switch (SystemCoreClock) {
             case RO_FREQ:
                 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
@@ -134,7 +134,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
         stdio_uart_inited = 1;
         memcpy(&stdio_uart, obj, sizeof(serial_t));
     }
-    
+
     // Enable UART
     obj->uart->ctrl |= MXC_F_UART_CTRL_UART_EN;
 }
@@ -311,7 +311,7 @@ void serial_putc(serial_t *obj, int c)
 {
     // Wait for TXFIFO to not be full
     while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
-                >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
+            >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
             >= MXC_UART_FIFO_DEPTH );
 
     // Must clear before every write to the buffer to know that the fifo
@@ -330,8 +330,8 @@ int serial_readable(serial_t *obj)
 int serial_writable(serial_t *obj)
 {
     return ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) 
-                >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
-                < MXC_UART_FIFO_DEPTH );
+             >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
+             < MXC_UART_FIFO_DEPTH );
 }
 
 //******************************************************************************
@@ -348,7 +348,7 @@ void serial_break_set(serial_t *obj)
 {
     // Make sure that nothing is being sent
     while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
-                >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) > 0);
+            >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) > 0);
     while (!(obj->uart->intfl & MXC_F_UART_INTFL_TX_DONE));
 
     // Configure the GPIO to output 0
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c b/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c
index 311325d932c..146c20c9e12 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c
@@ -86,8 +86,7 @@ static void usb_sleep(void)
         MXC_USB->dev_cn = 0;
         MXC_USB->cn = 0;
         restore_usb = 1;   // USB should be restored upon wakeup
-    }
-    else {
+    } else {
         restore_usb = 0;
     }
 }
@@ -124,7 +123,7 @@ void deepsleep(void)
 
     // Wait for all STDIO characters to be sent. The UART clock will stop.
     while ((stdio_uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) ||
-           !(stdio_uart->intfl & MXC_F_UART_INTFL_TX_DONE));
+            !(stdio_uart->intfl & MXC_F_UART_INTFL_TX_DONE));
 
     __disable_irq();
 
@@ -187,8 +186,7 @@ void deepsleep(void)
         __SEV();
         __WFE();
         __WFI();
-    }
-    else {
+    } else {
         // Note: ARM deep-sleep requires a specific sequence to clear event latches,
         //  otherwise the CPU will not enter sleep.
         __SEV();
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c b/targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c
index b99d63b6cdf..8c5675d6dbd 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c
@@ -69,7 +69,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
     // Give the application the option to manually control Slave Select
     if ((SPIName)spi_ssel != (SPIName)NC) {
         spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-        // Slave select is currently limited to slave select zero. If others are 
+        // Slave select is currently limited to slave select zero. If others are
         // to be supported a function to map PinName to a value suitable for use
         // in mstr_cfg.slave_sel will be required.
         obj->spi.ssel = 0;
@@ -352,7 +352,7 @@ static uint32_t spi_master_transfer_handler(spi_t *obj)
 
         // Set the transaction configuration in the header
         header = ((write | (read << 1)) << MXC_F_SPI_FIFO_DIR_POS) | (req->width << MXC_F_SPI_FIFO_WIDTH_POS);
-        
+
         if (remain >= SPI_MAX_BYTE_LEN) {
 
             // Send a 32 byte header
@@ -367,7 +367,7 @@ static uint32_t spi_master_transfer_handler(spi_t *obj)
                 // Send in increments of 32 byte pages
                 header |= MXC_S_SPI_FIFO_UNIT_PAGES;
                 pages = remain / SPI_MAX_PAGE_LEN;
-                
+
                 if (pages >= 32) {
                     // 0 maps to 32 in the header
                     bytes = 32 * SPI_MAX_PAGE_LEN;
@@ -380,7 +380,7 @@ static uint32_t spi_master_transfer_handler(spi_t *obj)
                 if ((remain - bytes) == 0) {
                     header |= MXC_F_SPI_FIFO_DASS;
                 }
-            }   
+            }
 
             fifo->trans_16[0] = header;
 
@@ -414,7 +414,7 @@ static uint32_t spi_master_transfer_handler(spi_t *obj)
             }
 
             // Only memcpy even numbers
-            length = ((length / 2) * 2); 
+            length = ((length / 2) * 2);
 
             memcpy((void*)fifo->trans_32, &(req->tx_data[req->write_num]), length);
 
@@ -450,8 +450,8 @@ static uint32_t spi_master_transfer_handler(spi_t *obj)
     }
 
     // Check to see if we've finished reading and writing
-    if (((read && (req->read_num == req->len)) || !read) && 
-        ((req->write_num == req->len) || !write)) {
+    if (((read && (req->read_num == req->len)) || !read) &&
+            ((req->write_num == req->len) || !write)) {
 
         // Disable interrupts
         spim->inten = 0;
@@ -469,7 +469,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
 
     // Save object reference for callback
     state[obj->spi.index] = &obj->spi;
-    
+
     // Initialize request info
     obj->spi.tx_data = tx;
     obj->spi.rx_data = rx;
@@ -491,7 +491,7 @@ uint32_t spi_irq_handler_asynch(spi_t *obj)
 {
     mxc_spi_regs_t *spim = obj->spi.spi;
     uint32_t flags;
-    
+
     // Clear the interrupt flags
     spim->inten = 0;
     flags = spim->intfl;
@@ -503,7 +503,7 @@ uint32_t spi_irq_handler_asynch(spi_t *obj)
             return 0;
         }
     }
-    
+
     state[obj->spi.index] = NULL;
 
     return SPI_EVENT_COMPLETE;
@@ -516,7 +516,7 @@ uint8_t spi_active(spi_t *obj)
 
     // Check to see if there are any ongoing transactions
     if ((state[obj->spi.index] == NULL) &&
-        !(spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED)) {
+            !(spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED)) {
         return 0;
     }
 
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c b/targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c
index 747243e1e76..3cd72785bff 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c
@@ -72,7 +72,8 @@ static volatile uint64_t event_cnt;     // Holds the value of the next event
 #define MAX_TICK_VAL    ((uint64_t)0xFFFFFFFF * ticks_per_us)
 
 //******************************************************************************
-static inline void inc_current_cnt(uint32_t inc) {
+static inline void inc_current_cnt(uint32_t inc)
+{
 
     // Overflow the ticker when the us ticker overflows
     current_cnt += inc;
@@ -82,14 +83,15 @@ static inline void inc_current_cnt(uint32_t inc) {
 }
 
 //******************************************************************************
-static inline int event_passed(uint64_t current, uint64_t event) {
+static inline int event_passed(uint64_t current, uint64_t event)
+{
 
     // Determine if the event has already happened.
     // If the event is behind the current ticker, within a window,
     // then the event has already happened.
-    if (((current < tick_win) && ((event < current) || 
-        (event > (MAX_TICK_VAL - (tick_win - current))))) || 
-        ((event < current) && (event > (current - tick_win)))) {
+    if (((current < tick_win) && ((event < current) ||
+                                  (event > (MAX_TICK_VAL - (tick_win - current))))) ||
+            ((event < current) && (event > (current - tick_win)))) {
         return 1;
     }
 
@@ -97,7 +99,8 @@ static inline int event_passed(uint64_t current, uint64_t event) {
 }
 
 //******************************************************************************
-static inline uint64_t event_diff(uint64_t current, uint64_t event) {
+static inline uint64_t event_diff(uint64_t current, uint64_t event)
+{
 
     // Check to see if the ticker will overflow before the event
     if(current <= event) {
@@ -129,7 +132,7 @@ static void tmr_handler(void)
             US_TIMER->term_cnt32 = diff;
 
             // Since the timer keeps counting after the terminal value is reached, it is possible that the new
-            // terminal value is in the past.    
+            // terminal value is in the past.
             if (US_TIMER->term_cnt32 < US_TIMER->count32) {
                 // the timestamp has expired
                 US_TIMER->term_cnt32 = 0xFFFFFFFF;  // reset to max value to prevent further interrupts
@@ -239,7 +242,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
     inc_current_cnt(US_TIMER->count32);
     US_TIMER->count32 = 0;
 
-    // add the number of cycles that the timer is disabled here for 
+    // add the number of cycles that the timer is disabled here for
     inc_current_cnt(200);
 
     event_cnt = (uint64_t)timestamp * ticks_per_us;
@@ -251,7 +254,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
             // the event occurs before the next overflow
             US_TIMER->term_cnt32 = diff;
         } else {
-            // the event occurs after the next overflow 
+            // the event occurs after the next overflow
             US_TIMER->term_cnt32 = 0xFFFFFFFF;  // set to max
         }
     } else {

From 43576fc931d9b4be84b6615e5de1b850ec6cbd33 Mon Sep 17 00:00:00 2001
From: Jeremy Brodt <jeremy.brodt@maximintegrated.com>
Date: Fri, 9 Sep 2016 11:51:14 -0500
Subject: [PATCH 09/89] Fixed INITIAL_SP value.

---
 targets/TARGET_Maxim/mbed_rtx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/targets/TARGET_Maxim/mbed_rtx.h b/targets/TARGET_Maxim/mbed_rtx.h
index 61a24f8b6d9..d719cae00ea 100644
--- a/targets/TARGET_Maxim/mbed_rtx.h
+++ b/targets/TARGET_Maxim/mbed_rtx.h
@@ -50,7 +50,7 @@
 #elif defined(TARGET_MAX32620)
 
 #ifndef INITIAL_SP
-#define INITIAL_SP              (0x20008000UL)
+#define INITIAL_SP              (0x20040000UL)
 #endif
 #ifndef OS_TASKCNT
 #define OS_TASKCNT              14

From 137a0dd3da618113623c56e633d7005da76f6c42 Mon Sep 17 00:00:00 2001
From: Jeremy Brodt <jeremy.brodt@maximintegrated.com>
Date: Tue, 13 Sep 2016 14:32:49 -0500
Subject: [PATCH 10/89] Fixed SysTick_Handler name.

---
 .../device/TOOLCHAIN_ARM_STD/startup_MAX32600.S           | 8 ++++----
 .../device/TOOLCHAIN_IAR/startup_MAX32600.S               | 8 ++++----
 .../device/TOOLCHAIN_ARM_STD/startup_MAX32610.S           | 8 ++++----
 .../device/TOOLCHAIN_IAR/startup_MAX32610.S               | 8 ++++----
 .../device/TOOLCHAIN_ARM_STD/startup_MAX32620.S           | 8 ++++----
 .../device/TOOLCHAIN_IAR/startup_MAX32620.S               | 8 ++++----
 6 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_ARM_STD/startup_MAX32600.S b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_ARM_STD/startup_MAX32600.S
index 02ece3a3cc0..e81ff572383 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_ARM_STD/startup_MAX32600.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_ARM_STD/startup_MAX32600.S
@@ -58,7 +58,7 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     DebugMon_Handler          ; Debug Monitor Handler
                 DCD     0                         ; Reserved
                 DCD     DefaultIRQ_Handler        ; PendSV Handler
-                DCD     SysTick_IRQHandler        ; SysTick Handler
+                DCD     SysTick_Handler           ; SysTick Handler
 
                 ; Maxim 32600 Externals interrupts
                 DCD     UART0_IRQHandler          ; 16: 1 UART0
@@ -146,9 +146,9 @@ DebugMon_Handler        PROC
                         B       DebugMon_Handler
                         ENDP
 
-SysTick_IRQHandler      PROC
-                        EXPORT SysTick_IRQHandler               [WEAK]             
-                        B       SysTick_IRQHandler
+SysTick_Handler         PROC
+                        EXPORT SysTick_Handler                  [WEAK]             
+                        B       SysTick_Handler
                         ENDP
 
 Default_Handler PROC
diff --git a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/startup_MAX32600.S b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/startup_MAX32600.S
index 740a9150b01..b68a1384f7c 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/startup_MAX32600.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/startup_MAX32600.S
@@ -58,7 +58,7 @@ __vector_table  DCD     sfe(CSTACK)               /* Top of Stack */
                 DCD     DebugMon_Handler          /* Debug Monitor Handler */
                 DCD     0                         /* Reserved */
                 DCD     DefaultIRQ_Handler        /* PendSV Handler */
-                DCD     SysTick_IRQHandler        /* SysTick Handler */
+                DCD     SysTick_Handler           /* SysTick Handler */
 
                 /* Maxim 32600 Externals interrupts */
                 DCD     UART0_IRQHandler          /* 16: 1 UART0 */
@@ -140,10 +140,10 @@ DefaultIRQ_Handler
 DebugMon_Handler
                 B       DebugMon_Handler
 
-                PUBWEAK SysTick_IRQHandler
+                PUBWEAK SysTick_Handler
                 SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_IRQHandler
-                B       SysTick_IRQHandler
+SysTick_Handler
+                B       SysTick_Handler
       
                 PUBWEAK UART0_IRQHandler
                 SECTION .text:CODE:REORDER:NOROOT(1)
diff --git a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_ARM_STD/startup_MAX32610.S b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_ARM_STD/startup_MAX32610.S
index e3c52cae9d2..f275aec5756 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_ARM_STD/startup_MAX32610.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_ARM_STD/startup_MAX32610.S
@@ -58,7 +58,7 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     DebugMon_Handler          ; Debug Monitor Handler 
                 DCD     0                         ; Reserved 
                 DCD     DefaultIRQ_Handler        ; PendSV Handler 
-                DCD     SysTick_IRQHandler        ; SysTick Handler 
+                DCD     SysTick_Handler           ; SysTick Handler 
 
                 ; Maxim 32610 Externals interrupts 
                 DCD     UART0_IRQHandler          ; 16: 1 UART0 
@@ -146,9 +146,9 @@ DebugMon_Handler        PROC
                         B       DebugMon_Handler
                         ENDP
 
-SysTick_IRQHandler      PROC
-                        EXPORT SysTick_IRQHandler               [WEAK]             
-                        B       SysTick_IRQHandler
+SysTick_Handler         PROC
+                        EXPORT SysTick_Handler                  [WEAK]             
+                        B       SysTick_Handler
                         ENDP
 
 Default_Handler PROC
diff --git a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/startup_MAX32610.S b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/startup_MAX32610.S
index 518756c0b45..1a4c9f48627 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/startup_MAX32610.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/startup_MAX32610.S
@@ -58,7 +58,7 @@ __vector_table  DCD     sfe(CSTACK)               /* Top of Stack */
                 DCD     DebugMon_Handler          /* Debug Monitor Handler */
                 DCD     0                         /* Reserved */
                 DCD     DefaultIRQ_Handler        /* PendSV Handler */
-                DCD     SysTick_IRQHandler        /* SysTick Handler */
+                DCD     SysTick_Handler           /* SysTick Handler */
 
                 /* Maxim 32610 Externals interrupts */
                 DCD     UART0_IRQHandler          /* 16: 1 UART0 */
@@ -140,10 +140,10 @@ DefaultIRQ_Handler
 DebugMon_Handler
                 B       DebugMon_Handler
 
-                PUBWEAK SysTick_IRQHandler
+                PUBWEAK SysTick_Handler
                 SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_IRQHandler
-                B       SysTick_IRQHandler
+SysTick_Handler
+                B       SysTick_Handler
       
                 PUBWEAK UART0_IRQHandler
                 SECTION .text:CODE:REORDER:NOROOT(1)
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/startup_MAX32620.S b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/startup_MAX32620.S
index c9742a0eacd..f5e5a88edb5 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/startup_MAX32620.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/startup_MAX32620.S
@@ -58,7 +58,7 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     DebugMon_Handler          ; Debug Monitor Handler
                 DCD     0                         ; Reserved
                 DCD     DefaultIRQ_Handler        ; PendSV Handler
-                DCD     SysTick_IRQHandler        ; SysTick Handler
+                DCD     SysTick_Handler           ; SysTick Handler
 
                 ; Maxim 32620 Externals interrupts
                 DCD CLKMAN_IRQHandler         /* 16:01 CLKMAN */ 
@@ -149,9 +149,9 @@ DebugMon_Handler        PROC
                         B       DebugMon_Handler
                         ENDP
 
-SysTick_IRQHandler      PROC
-                        EXPORT SysTick_IRQHandler               [WEAK]             
-                        B       SysTick_IRQHandler
+SysTick_Handler         PROC
+                        EXPORT SysTick_Handler                  [WEAK]             
+                        B       SysTick_Handler
                         ENDP
 
 Default_Handler PROC
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/startup_MAX32620.S b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/startup_MAX32620.S
index 000a28e7ea0..4126ca15d18 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/startup_MAX32620.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/startup_MAX32620.S
@@ -58,7 +58,7 @@ __vector_table  DCD     sfe(CSTACK)               /* Top of Stack */
                 DCD     DebugMon_Handler          /* Debug Monitor Handler */
                 DCD     0                         /* Reserved */
                 DCD     DefaultIRQ_Handler        /* PendSV Handler */
-                DCD     SysTick_IRQHandler        /* SysTick Handler */
+                DCD     SysTick_Handler           /* SysTick Handler */
 
                 /* Maxim 32620 NVIC Index */
                 DCD CLKMAN_IRQHandler         /* 16:01 CLKMAN */ 
@@ -147,10 +147,10 @@ DefaultIRQ_Handler
 DebugMon_Handler
                 B       DebugMon_Handler
 
-                PUBWEAK SysTick_IRQHandler
+                PUBWEAK SysTick_Handler
                 SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_IRQHandler
-                B       SysTick_IRQHandler
+SysTick_Handler
+                B       SysTick_Handler
       
 			PUBWEAK CLKMAN_IRQHandler
 			SECTION .text:CODE:REORDER:NOROOT(1)

From c801dc6cf81753e42eca5e6e89bd4a60b70daa09 Mon Sep 17 00:00:00 2001
From: Jeremy Brodt <jeremy.brodt@maximintegrated.com>
Date: Mon, 26 Sep 2016 16:41:56 -0500
Subject: [PATCH 11/89] Fixed default handler implementations for ARM and IAR.

---
 .../TOOLCHAIN_ARM_STD/startup_MAX32600.S      |  36 +++-
 .../device/TOOLCHAIN_IAR/startup_MAX32600.S   |  36 +++-
 .../TOOLCHAIN_ARM_STD/startup_MAX32610.S      | 156 ++++++++++--------
 .../device/TOOLCHAIN_IAR/startup_MAX32610.S   |  36 +++-
 .../TOOLCHAIN_ARM_STD/startup_MAX32620.S      |  36 +++-
 .../device/TOOLCHAIN_IAR/startup_MAX32620.S   |  36 +++-
 6 files changed, 228 insertions(+), 108 deletions(-)

diff --git a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_ARM_STD/startup_MAX32600.S b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_ARM_STD/startup_MAX32600.S
index e81ff572383..a68ff008e27 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_ARM_STD/startup_MAX32600.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_ARM_STD/startup_MAX32600.S
@@ -47,17 +47,17 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     Reset_Handler             ; Reset Handler
                 DCD     NMI_Handler               ; NMI Handler
                 DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     DefaultIRQ_Handler        ; MPU Fault Handler
-                DCD     DefaultIRQ_Handler        ; Bus Fault Handler
-                DCD     DefaultIRQ_Handler        ; Usage Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
                 DCD     0                         ; Reserved
                 DCD     0                         ; Reserved
                 DCD     0                         ; Reserved
                 DCD     0                         ; Reserved
-                DCD     DefaultIRQ_Handler        ; SVCall Handler
+                DCD     SVC_Handler               ; SVCall Handler
                 DCD     DebugMon_Handler          ; Debug Monitor Handler
                 DCD     0                         ; Reserved
-                DCD     DefaultIRQ_Handler        ; PendSV Handler
+                DCD     PendSV_Handler            ; PendSV Handler
                 DCD     SysTick_Handler           ; SysTick Handler
 
                 ; Maxim 32600 Externals interrupts
@@ -136,9 +136,24 @@ HardFault_Handler       PROC
                         B       HardFault_Handler
                         ENDP
 
-DefaultIRQ_Handler      PROC
-                        EXPORT DefaultIRQ_Handler               [WEAK]             
-                        B       DefaultIRQ_Handler
+MemManage_Handler       PROC
+                        EXPORT MemManage_Handler                [WEAK]             
+                        B       MemManage_Handler
+                        ENDP
+
+BusFault_Handler        PROC
+                        EXPORT BusFault_Handler                 [WEAK]             
+                        B       BusFault_Handler
+                        ENDP
+
+UsageFault_Handler      PROC
+                        EXPORT UsageFault_Handler               [WEAK]             
+                        B       UsageFault_Handler
+                        ENDP
+
+SVC_Handler             PROC
+                        EXPORT SVC_Handler                      [WEAK]             
+                        B       SVC_Handler
                         ENDP
 
 DebugMon_Handler        PROC
@@ -146,6 +161,11 @@ DebugMon_Handler        PROC
                         B       DebugMon_Handler
                         ENDP
 
+PendSV_Handler          PROC
+                        EXPORT PendSV_Handler                   [WEAK]             
+                        B       PendSV_Handler
+                        ENDP
+
 SysTick_Handler         PROC
                         EXPORT SysTick_Handler                  [WEAK]             
                         B       SysTick_Handler
diff --git a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/startup_MAX32600.S b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/startup_MAX32600.S
index b68a1384f7c..15f2688348b 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/startup_MAX32600.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/startup_MAX32600.S
@@ -47,17 +47,17 @@ __vector_table  DCD     sfe(CSTACK)               /* Top of Stack */
                 DCD     Reset_Handler             /* Reset Handler */
                 DCD     NMI_Handler               /* NMI Handler */
                 DCD     HardFault_Handler         /* Hard Fault Handler */
-                DCD     DefaultIRQ_Handler        /* MPU Fault Handler */
-                DCD     DefaultIRQ_Handler        /* Bus Fault Handler */
-                DCD     DefaultIRQ_Handler        /* Usage Fault Handler */
+                DCD     MemManage_Handler         /* MPU Fault Handler */
+                DCD     BusFault_Handler          /* Bus Fault Handler */
+                DCD     UsageFault_Handler        /* Usage Fault Handler */
                 DCD     0                         /* Reserved */
                 DCD     0                         /* Reserved */
                 DCD     0                         /* Reserved */
                 DCD     0                         /* Reserved */
-                DCD     DefaultIRQ_Handler        /* SVCall Handler */
+                DCD     SVC_Handler               /* SVCall Handler */
                 DCD     DebugMon_Handler          /* Debug Monitor Handler */
                 DCD     0                         /* Reserved */
-                DCD     DefaultIRQ_Handler        /* PendSV Handler */
+                DCD     PendSV_Handler            /* PendSV Handler */
                 DCD     SysTick_Handler           /* SysTick Handler */
 
                 /* Maxim 32600 Externals interrupts */
@@ -130,16 +130,36 @@ NMI_Handler
 HardFault_Handler
                 B       HardFault_Handler
 
-                PUBWEAK DefaultIRQ_Handler
+                PUBWEAK MemManage_Handler
                 SECTION .text:CODE:REORDER:NOROOT(1)
-DefaultIRQ_Handler
-                B       DefaultIRQ_Handler
+MemManage_Handler
+                B       MemManage_Handler
+
+                PUBWEAK BusFault_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+                B       BusFault_Handler
+
+                PUBWEAK UsageFault_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+                B       UsageFault_Handler
+
+                PUBWEAK SVC_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+                B       SVC_Handler
                    
                 PUBWEAK DebugMon_Handler
                 SECTION .text:CODE:REORDER:NOROOT(1)
 DebugMon_Handler
                 B       DebugMon_Handler
 
+                PUBWEAK PendSV_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+                B       PendSV_Handler
+
                 PUBWEAK SysTick_Handler
                 SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler
diff --git a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_ARM_STD/startup_MAX32610.S b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_ARM_STD/startup_MAX32610.S
index f275aec5756..46700b23ae4 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_ARM_STD/startup_MAX32610.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_ARM_STD/startup_MAX32610.S
@@ -43,71 +43,71 @@ __initial_sp        EQU     0x20008000  ; Top of RAM
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
 
-__Vectors       DCD     __initial_sp              ; Top of Stack 
-                DCD     Reset_Handler             ; Reset Handler 
-                DCD     NMI_Handler               ; NMI Handler 
-                DCD     HardFault_Handler         ; Hard Fault Handler 
-                DCD     DefaultIRQ_Handler        ; MPU Fault Handler 
-                DCD     DefaultIRQ_Handler        ; Bus Fault Handler 
-                DCD     DefaultIRQ_Handler        ; Usage Fault Handler 
-                DCD     0                         ; Reserved 
-                DCD     0                         ; Reserved 
-                DCD     0                         ; Reserved 
-                DCD     0                         ; Reserved 
-                DCD     DefaultIRQ_Handler        ; SVCall Handler 
-                DCD     DebugMon_Handler          ; Debug Monitor Handler 
-                DCD     0                         ; Reserved 
-                DCD     DefaultIRQ_Handler        ; PendSV Handler 
-                DCD     SysTick_Handler           ; SysTick Handler 
-
-                ; Maxim 32610 Externals interrupts 
-                DCD     UART0_IRQHandler          ; 16: 1 UART0 
-                DCD     UART1_IRQHandler          ; 17: 2 UART1 
-                DCD     I2CM0_IRQHandler          ; 18: 3 I2C Master 0 
-                DCD     I2CS_IRQHandler           ; 19: 4 I2C Slave 
-                DCD     USB_IRQHandler            ; 20: 5 USB 
-                DCD     PMU_IRQHandler            ; 21: 6 DMA 
-                DCD     AFE_IRQHandler            ; 22: 7 AFE 
-                DCD     MAA_IRQHandler            ; 23: 8 MAA 
-                DCD     AES_IRQHandler            ; 24: 9 AES 
-                DCD     SPI0_IRQHandler           ; 25:10 SPI0 
-                DCD     SPI1_IRQHandler           ; 26:11 SPI1 
-                DCD     SPI2_IRQHandler           ; 27:12 SPI2 
-                DCD     TMR0_IRQHandler           ; 28:13 Timer32-0 
-                DCD     TMR1_IRQHandler           ; 29:14 Timer32-1 
-                DCD     TMR2_IRQHandler           ; 30:15 Timer32-1 
-                DCD     TMR3_IRQHandler           ; 31:16 Timer32-2 
-                DCD     RSVD0_IRQHandler          ; 32:17 RSVD 
-                DCD     RSVD1_IRQHandler          ; 33:18 RSVD 
-                DCD     DAC0_IRQHandler           ; 34:19 DAC0  (12-bit DAC)   
-                DCD     DAC1_IRQHandler           ; 35:20 DAC1  (12-bit DAC)   
-                DCD     DAC2_IRQHandler           ; 36:21 DAC2  (8-bit DAC) 
-                DCD     DAC3_IRQHandler           ; 37:22 DAC3  (8-bit DAC) 
-                DCD     ADC_IRQHandler            ; 38:23 ADC 
-                DCD     FLC_IRQHandler            ; 39:24 Flash Controller 
-                DCD     PWRMAN_IRQHandler         ; 40:25 PWRMAN 
-                DCD     CLKMAN_IRQHandler         ; 41:26 CLKMAN 
-                DCD     RTC0_IRQHandler           ; 42:27 RTC INT0 
-                DCD     RTC1_IRQHandler           ; 43:28 RTC INT1 
-                DCD     RTC2_IRQHandler           ; 44:29 RTC INT2 
-                DCD     RTC3_IRQHandler           ; 45:30 RTC INT3 
-                DCD     WDT0_IRQHandler           ; 46:31 WATCHDOG0 
-                DCD     WDT0_P_IRQHandler         ; 47:32 WATCHDOG0 PRE-WINDOW 
-                DCD     WDT1_IRQHandler           ; 48:33 WATCHDOG1 
-                DCD     WDT1_P_IRQHandler         ; 49:34 WATCHDOG1 PRE-WINDOW 
-                DCD     GPIO_P0_IRQHandler        ; 50:35 GPIO Port 0  
-                DCD     GPIO_P1_IRQHandler        ; 51:36 GPIO Port 1  
-                DCD     GPIO_P2_IRQHandler        ; 52:37 GPIO Port 2  
-                DCD     GPIO_P3_IRQHandler        ; 53:38 GPIO Port 3  
-                DCD     GPIO_P4_IRQHandler        ; 54:39 GPIO Port 4  
-                DCD     GPIO_P5_IRQHandler        ; 55:40 GPIO Port 5  
-                DCD     GPIO_P6_IRQHandler        ; 56:41 GPIO Port 6  
-                DCD     GPIO_P7_IRQHandler        ; 57:42 GPIO Port 7  
-                DCD     TMR16_0_IRQHandler        ; 58:43 Timer16-s0 
-                DCD     TMR16_1_IRQHandler        ; 59:44 Timer16-s1 
-                DCD     TMR16_2_IRQHandler        ; 60:45 Timer16-s2 
-                DCD     TMR16_3_IRQHandler        ; 61:46 Timer16-s3 
-                DCD     I2CM1_IRQHandler          ; 62:47 I2C Master 1 
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; Maxim 32610 Externals interrupts
+                DCD     UART0_IRQHandler          ; 16: 1 UART0
+                DCD     UART1_IRQHandler          ; 17: 2 UART1
+                DCD     I2CM0_IRQHandler          ; 18: 3 I2C Master 0
+                DCD     I2CS_IRQHandler           ; 19: 4 I2C Slave
+                DCD     USB_IRQHandler            ; 20: 5 USB
+                DCD     PMU_IRQHandler            ; 21: 6 DMA
+                DCD     AFE_IRQHandler            ; 22: 7 AFE
+                DCD     MAA_IRQHandler            ; 23: 8 MAA
+                DCD     AES_IRQHandler            ; 24: 9 AES
+                DCD     SPI0_IRQHandler           ; 25:10 SPI0
+                DCD     SPI1_IRQHandler           ; 26:11 SPI1
+                DCD     SPI2_IRQHandler           ; 27:12 SPI2
+                DCD     TMR0_IRQHandler           ; 28:13 Timer32-0
+                DCD     TMR1_IRQHandler           ; 29:14 Timer32-1
+                DCD     TMR2_IRQHandler           ; 30:15 Timer32-1
+                DCD     TMR3_IRQHandler           ; 31:16 Timer32-2
+                DCD     RSVD0_IRQHandler          ; 32:17 RSVD
+                DCD     RSVD1_IRQHandler          ; 33:18 RSVD
+                DCD     DAC0_IRQHandler           ; 34:19 DAC0  (12-bit DAC)  
+                DCD     DAC1_IRQHandler           ; 35:20 DAC1  (12-bit DAC)  
+                DCD     DAC2_IRQHandler           ; 36:21 DAC2  (8-bit DAC)
+                DCD     DAC3_IRQHandler           ; 37:22 DAC3  (8-bit DAC)
+                DCD     ADC_IRQHandler            ; 38:23 ADC
+                DCD     FLC_IRQHandler            ; 39:24 Flash Controller
+                DCD     PWRMAN_IRQHandler         ; 40:25 PWRMAN
+                DCD     CLKMAN_IRQHandler         ; 41:26 CLKMAN
+                DCD     RTC0_IRQHandler           ; 42:27 RTC INT0
+                DCD     RTC1_IRQHandler           ; 43:28 RTC INT1
+                DCD     RTC2_IRQHandler           ; 44:29 RTC INT2
+                DCD     RTC3_IRQHandler           ; 45:30 RTC INT3
+                DCD     WDT0_IRQHandler           ; 46:31 WATCHDOG0
+                DCD     WDT0_P_IRQHandler         ; 47:32 WATCHDOG0 PRE-WINDOW
+                DCD     WDT1_IRQHandler           ; 48:33 WATCHDOG1
+                DCD     WDT1_P_IRQHandler         ; 49:34 WATCHDOG1 PRE-WINDOW
+                DCD     GPIO_P0_IRQHandler        ; 50:35 GPIO Port 0 
+                DCD     GPIO_P1_IRQHandler        ; 51:36 GPIO Port 1 
+                DCD     GPIO_P2_IRQHandler        ; 52:37 GPIO Port 2 
+                DCD     GPIO_P3_IRQHandler        ; 53:38 GPIO Port 3 
+                DCD     GPIO_P4_IRQHandler        ; 54:39 GPIO Port 4 
+                DCD     GPIO_P5_IRQHandler        ; 55:40 GPIO Port 5 
+                DCD     GPIO_P6_IRQHandler        ; 56:41 GPIO Port 6 
+                DCD     GPIO_P7_IRQHandler        ; 57:42 GPIO Port 7 
+                DCD     TMR16_0_IRQHandler        ; 58:43 Timer16-s0
+                DCD     TMR16_1_IRQHandler        ; 59:44 Timer16-s1
+                DCD     TMR16_2_IRQHandler        ; 60:45 Timer16-s2
+                DCD     TMR16_3_IRQHandler        ; 61:46 Timer16-s3
+                DCD     I2CM1_IRQHandler          ; 62:47 I2C Master 1
 __Vectors_End
 
 __Vectors_Size  EQU  __Vectors_End - __Vectors
@@ -136,9 +136,24 @@ HardFault_Handler       PROC
                         B       HardFault_Handler
                         ENDP
 
-DefaultIRQ_Handler      PROC
-                        EXPORT DefaultIRQ_Handler               [WEAK]             
-                        B       DefaultIRQ_Handler
+MemManage_Handler       PROC
+                        EXPORT MemManage_Handler                [WEAK]             
+                        B       MemManage_Handler
+                        ENDP
+
+BusFault_Handler        PROC
+                        EXPORT BusFault_Handler                 [WEAK]             
+                        B       BusFault_Handler
+                        ENDP
+
+UsageFault_Handler      PROC
+                        EXPORT UsageFault_Handler               [WEAK]             
+                        B       UsageFault_Handler
+                        ENDP
+
+SVC_Handler             PROC
+                        EXPORT SVC_Handler                      [WEAK]             
+                        B       SVC_Handler
                         ENDP
 
 DebugMon_Handler        PROC
@@ -146,6 +161,11 @@ DebugMon_Handler        PROC
                         B       DebugMon_Handler
                         ENDP
 
+PendSV_Handler          PROC
+                        EXPORT PendSV_Handler                   [WEAK]             
+                        B       PendSV_Handler
+                        ENDP
+
 SysTick_Handler         PROC
                         EXPORT SysTick_Handler                  [WEAK]             
                         B       SysTick_Handler
diff --git a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/startup_MAX32610.S b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/startup_MAX32610.S
index 1a4c9f48627..a350a9b46d7 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/startup_MAX32610.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/startup_MAX32610.S
@@ -47,17 +47,17 @@ __vector_table  DCD     sfe(CSTACK)               /* Top of Stack */
                 DCD     Reset_Handler             /* Reset Handler */
                 DCD     NMI_Handler               /* NMI Handler */
                 DCD     HardFault_Handler         /* Hard Fault Handler */
-                DCD     DefaultIRQ_Handler        /* MPU Fault Handler */
-                DCD     DefaultIRQ_Handler        /* Bus Fault Handler */
-                DCD     DefaultIRQ_Handler        /* Usage Fault Handler */
+                DCD     MemManage_Handler         /* MPU Fault Handler */
+                DCD     BusFault_Handler          /* Bus Fault Handler */
+                DCD     UsageFault_Handler        /* Usage Fault Handler */
                 DCD     0                         /* Reserved */
                 DCD     0                         /* Reserved */
                 DCD     0                         /* Reserved */
                 DCD     0                         /* Reserved */
-                DCD     DefaultIRQ_Handler        /* SVCall Handler */
+                DCD     SVC_Handler               /* SVCall Handler */
                 DCD     DebugMon_Handler          /* Debug Monitor Handler */
                 DCD     0                         /* Reserved */
-                DCD     DefaultIRQ_Handler        /* PendSV Handler */
+                DCD     PendSV_Handler            /* PendSV Handler */
                 DCD     SysTick_Handler           /* SysTick Handler */
 
                 /* Maxim 32610 Externals interrupts */
@@ -130,16 +130,36 @@ NMI_Handler
 HardFault_Handler
                 B       HardFault_Handler
 
-                PUBWEAK DefaultIRQ_Handler
+                PUBWEAK MemManage_Handler
                 SECTION .text:CODE:REORDER:NOROOT(1)
-DefaultIRQ_Handler
-                B       DefaultIRQ_Handler
+MemManage_Handler
+                B       MemManage_Handler
+
+                PUBWEAK BusFault_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+                B       BusFault_Handler
+
+                PUBWEAK UsageFault_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+                B       UsageFault_Handler
+
+                PUBWEAK SVC_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+                B       SVC_Handler
                    
                 PUBWEAK DebugMon_Handler
                 SECTION .text:CODE:REORDER:NOROOT(1)
 DebugMon_Handler
                 B       DebugMon_Handler
 
+                PUBWEAK PendSV_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+                B       PendSV_Handler
+
                 PUBWEAK SysTick_Handler
                 SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/startup_MAX32620.S b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/startup_MAX32620.S
index f5e5a88edb5..31eaa0fc258 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/startup_MAX32620.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_ARM_STD/startup_MAX32620.S
@@ -47,17 +47,17 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     Reset_Handler             ; Reset Handler
                 DCD     NMI_Handler               ; NMI Handler
                 DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     DefaultIRQ_Handler        ; MPU Fault Handler
-                DCD     DefaultIRQ_Handler        ; Bus Fault Handler
-                DCD     DefaultIRQ_Handler        ; Usage Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
                 DCD     0                         ; Reserved
                 DCD     0                         ; Reserved
                 DCD     0                         ; Reserved
                 DCD     0                         ; Reserved
-                DCD     DefaultIRQ_Handler        ; SVCall Handler
+                DCD     SVC_Handler               ; SVCall Handler
                 DCD     DebugMon_Handler          ; Debug Monitor Handler
                 DCD     0                         ; Reserved
-                DCD     DefaultIRQ_Handler        ; PendSV Handler
+                DCD     PendSV_Handler            ; PendSV Handler
                 DCD     SysTick_Handler           ; SysTick Handler
 
                 ; Maxim 32620 Externals interrupts
@@ -139,9 +139,24 @@ HardFault_Handler       PROC
                         B       HardFault_Handler
                         ENDP
 
-DefaultIRQ_Handler      PROC
-                        EXPORT DefaultIRQ_Handler               [WEAK]             
-                        B       DefaultIRQ_Handler
+MemManage_Handler       PROC
+                        EXPORT MemManage_Handler                [WEAK]             
+                        B       MemManage_Handler
+                        ENDP
+
+BusFault_Handler        PROC
+                        EXPORT BusFault_Handler                 [WEAK]             
+                        B       BusFault_Handler
+                        ENDP
+
+UsageFault_Handler      PROC
+                        EXPORT UsageFault_Handler               [WEAK]             
+                        B       UsageFault_Handler
+                        ENDP
+
+SVC_Handler             PROC
+                        EXPORT SVC_Handler                      [WEAK]             
+                        B       SVC_Handler
                         ENDP
 
 DebugMon_Handler        PROC
@@ -149,6 +164,11 @@ DebugMon_Handler        PROC
                         B       DebugMon_Handler
                         ENDP
 
+PendSV_Handler          PROC
+                        EXPORT PendSV_Handler                   [WEAK]             
+                        B       PendSV_Handler
+                        ENDP
+
 SysTick_Handler         PROC
                         EXPORT SysTick_Handler                  [WEAK]             
                         B       SysTick_Handler
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/startup_MAX32620.S b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/startup_MAX32620.S
index 4126ca15d18..6e465e3be00 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/startup_MAX32620.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/startup_MAX32620.S
@@ -47,17 +47,17 @@ __vector_table  DCD     sfe(CSTACK)               /* Top of Stack */
                 DCD     Reset_Handler             /* Reset Handler */
                 DCD     NMI_Handler               /* NMI Handler */
                 DCD     HardFault_Handler         /* Hard Fault Handler */
-                DCD     DefaultIRQ_Handler        /* MPU Fault Handler */
-                DCD     DefaultIRQ_Handler        /* Bus Fault Handler */
-                DCD     DefaultIRQ_Handler        /* Usage Fault Handler */
+                DCD     MemManage_Handler         /* MPU Fault Handler */
+                DCD     BusFault_Handler          /* Bus Fault Handler */
+                DCD     UsageFault_Handler        /* Usage Fault Handler */
                 DCD     0                         /* Reserved */
                 DCD     0                         /* Reserved */
                 DCD     0                         /* Reserved */
                 DCD     0                         /* Reserved */
-                DCD     DefaultIRQ_Handler        /* SVCall Handler */
+                DCD     SVC_Handler               /* SVCall Handler */
                 DCD     DebugMon_Handler          /* Debug Monitor Handler */
                 DCD     0                         /* Reserved */
-                DCD     DefaultIRQ_Handler        /* PendSV Handler */
+                DCD     PendSV_Handler            /* PendSV Handler */
                 DCD     SysTick_Handler           /* SysTick Handler */
 
                 /* Maxim 32620 NVIC Index */
@@ -137,16 +137,36 @@ NMI_Handler
 HardFault_Handler
                 B       HardFault_Handler
 
-                PUBWEAK DefaultIRQ_Handler
+                PUBWEAK MemManage_Handler
                 SECTION .text:CODE:REORDER:NOROOT(1)
-DefaultIRQ_Handler
-                B       DefaultIRQ_Handler
+MemManage_Handler
+                B       MemManage_Handler
+
+                PUBWEAK BusFault_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+                B       BusFault_Handler
+
+                PUBWEAK UsageFault_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+                B       UsageFault_Handler
+
+                PUBWEAK SVC_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+                B       SVC_Handler
                    
                 PUBWEAK DebugMon_Handler
                 SECTION .text:CODE:REORDER:NOROOT(1)
 DebugMon_Handler
                 B       DebugMon_Handler
 
+                PUBWEAK PendSV_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+                B       PendSV_Handler
+
                 PUBWEAK SysTick_Handler
                 SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler

From a72f8207fa602c2d13025cf34f8a1ec41890bd03 Mon Sep 17 00:00:00 2001
From: Jeremy Brodt <jeremy.brodt@maximintegrated.com>
Date: Mon, 26 Sep 2016 16:48:52 -0500
Subject: [PATCH 12/89] Updated BLE libraries.

---
 .../TOOLCHAIN_ARM_STD/exactLE.ar              | Bin 0 -> 2802216 bytes
 .../TOOLCHAIN_GCC_ARM/libexactLE.a            | Bin 970456 -> 1187986 bytes
 .../TARGET_MAX32620/TOOLCHAIN_IAR/exactLE.a   | Bin 0 -> 2799426 bytes
 3 files changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_ARM_STD/exactLE.ar
 create mode 100644 targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_IAR/exactLE.a

diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_ARM_STD/exactLE.ar b/targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_ARM_STD/exactLE.ar
new file mode 100644
index 0000000000000000000000000000000000000000..552ae00492cdbc1ae00aa692ebc212895b939282
GIT binary patch
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diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_GCC_ARM/libexactLE.a b/targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_GCC_ARM/libexactLE.a
index 89004fdddb9fe5ccf707969977b892955010019c..9a2c2f8fbaa52272d499b72c54d21f2ce5a77c9e 100644
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zdD2=G25Ft%<g-E};^2ljjB;F`^o@^nNJ>7k<&vW796?$yla`NMqsTYuN8x6Th|{7G
zaavWw=X2ii)I&wdVG=6n1oEh$aiplY6G>4~`J|{Q`FMc~$4@>}KRP25ynwiq<YdzE
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zjTg{PRNd%E>iH@31eU+7OD$)EeH;xh75o-0W7(sMUG_$yf)>fj)JmGLJndvwqb*#B
z2JH<fBA4DC2+(}`gc({-wkI4v3q8VOnUJOrW`QzY6ZHbh+{97E9DDU%PEhZ63F^I;
zpx&F%TS&)rF#gR4k7nkSbs^de7q^?xpB|_4OrQ;hc=oodDEYTPd#5L;=TFc-lNQaI
z<9Po06HM3GIGVjrTTk{y+DBtMUOpNV%*WFS>ZwjpDVuZ`fn~clRlxRA5XT<6VAu6l
z13hDd>gE_-t?N3fg`OSEwH-`QuPH&j4GHSuUg^pQ{rfIt-f$-b##hE2f*x)IeZoDE
z*xgtQ`exQIFQxHXo7d9!@w4?dL9ZD~)br!VKs|4|uT9a@hEgN;$D8i?xDl9iP5s5Q
z*8;uEVrHBpuf4Y{d+2Iph-dF(=p|AvA>5;kf5`d~?R7(Mla9BE*S|kl_E1DJ#Pjbk
z^l%&Q6TJ2!r^WokDKf;fw+(u&eXOYgs$IYDTK1;(WA9Lc_F7=XlwVOl_BKH;k@EYK
zWe>vz8RF$P4FiZC9d8qF`E7!p@z0DY;@P`8L3>0gH1^7L!tw0oKrfN{*lgM3LkdGY
zd)Gh@!?!-co8Lp0y}4RDp1olhfF$DICg|nB4*LUh-;8JP>ICh5VA(sPAO8lS@)Pkd
z0zKnjc|Z2HC1~$m%ih9%>>WzbUdzmwe~bFDw+VW^I^HJU`u(G2uc{w=J~Z}j+mJr?
z+S>p<Q+|srdq2l9?!BGH#1+t6X&8&Xf@8aX`7QL+n@atxgm|`>w>)}p;Nr=HjO{8L
yKL+ak89&?JU!iCG8%rew>K(?<z7Gz;02ocHPZ$a%+ul6r$%jv9F4fw!m-T-hqYt(K

literal 0
HcmV?d00001


From ed603ee3052029fc7bb68127bb0891c3c39078d9 Mon Sep 17 00:00:00 2001
From: Jeremy Brodt <jeremy.brodt@maximintegrated.com>
Date: Tue, 27 Sep 2016 10:47:40 -0500
Subject: [PATCH 13/89] Increased default stack and heap sizes.

---
 .../device/TOOLCHAIN_GCC_ARM/startup_max32600.S               | 2 +-
 .../TARGET_MAX32600/device/TOOLCHAIN_IAR/MAX32600.icf         | 4 ++--
 .../device/TOOLCHAIN_GCC_ARM/startup_max32610.S               | 2 +-
 .../TARGET_MAX32610/device/TOOLCHAIN_IAR/MAX32610.icf         | 4 ++--
 .../device/TOOLCHAIN_GCC_ARM/startup_max32620.S               | 4 ++--
 .../TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf         | 4 ++--
 6 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_GCC_ARM/startup_max32600.S b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_GCC_ARM/startup_max32600.S
index cda4da904bc..227ecb3565d 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_GCC_ARM/startup_max32600.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_GCC_ARM/startup_max32600.S
@@ -66,7 +66,7 @@ __StackTop:
 #ifdef __HEAP_SIZE
     .equ    Heap_Size, __HEAP_SIZE
 #else
-    .equ    Heap_Size, 0x00000C00
+    .equ    Heap_Size, 0x00004000
 #endif
     .globl    __HeapBase
     .globl    __HeapLimit
diff --git a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/MAX32600.icf b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/MAX32600.icf
index 9147f7160e7..3e0cd5e85f0 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/MAX32600.icf
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/MAX32600.icf
@@ -15,8 +15,8 @@ define region ROM_region      = mem:[from __region_ROM_start__   to __region_ROM
 define region RAM_region      = mem:[from __region_RAM_start__   to __region_RAM_end__];
 
 /* Stack and Heap */
-define symbol __size_cstack__ = 0x800;
-define symbol __size_heap__   = 0x800;
+define symbol __size_cstack__ = 0x1000;
+define symbol __size_heap__   = 0x4000;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };
 
diff --git a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_GCC_ARM/startup_max32610.S b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_GCC_ARM/startup_max32610.S
index cda4da904bc..227ecb3565d 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_GCC_ARM/startup_max32610.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_GCC_ARM/startup_max32610.S
@@ -66,7 +66,7 @@ __StackTop:
 #ifdef __HEAP_SIZE
     .equ    Heap_Size, __HEAP_SIZE
 #else
-    .equ    Heap_Size, 0x00000C00
+    .equ    Heap_Size, 0x00004000
 #endif
     .globl    __HeapBase
     .globl    __HeapLimit
diff --git a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/MAX32610.icf b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/MAX32610.icf
index 9147f7160e7..3e0cd5e85f0 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/MAX32610.icf
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/MAX32610.icf
@@ -15,8 +15,8 @@ define region ROM_region      = mem:[from __region_ROM_start__   to __region_ROM
 define region RAM_region      = mem:[from __region_RAM_start__   to __region_RAM_end__];
 
 /* Stack and Heap */
-define symbol __size_cstack__ = 0x800;
-define symbol __size_heap__   = 0x800;
+define symbol __size_cstack__ = 0x1000;
+define symbol __size_heap__   = 0x4000;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };
 
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/startup_max32620.S b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/startup_max32620.S
index 730788d41e2..12006b3247b 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/startup_max32620.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/startup_max32620.S
@@ -51,7 +51,7 @@
 #ifdef __STACK_SIZE
     .equ    Stack_Size, __STACK_SIZE
 #else
-    .equ    Stack_Size, 0x00001000
+    .equ    Stack_Size, 0x00002000
 #endif
     .globl    __StackTop
     .globl    __StackLimit
@@ -66,7 +66,7 @@ __StackTop:
 #ifdef __HEAP_SIZE
     .equ    Heap_Size, __HEAP_SIZE
 #else
-    .equ    Heap_Size, 0x00000C00
+    .equ    Heap_Size, 0x00004000
 #endif
     .globl    __HeapBase
     .globl    __HeapLimit
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf
index 31545799e4a..203c221868c 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf
@@ -15,8 +15,8 @@ define region ROM_region      = mem:[from __region_ROM_start__   to __region_ROM
 define region RAM_region      = mem:[from __region_RAM_start__   to __region_RAM_end__];
 
 /* Stack and Heap */
-define symbol __size_cstack__ = 0x800;
-define symbol __size_heap__   = 0x800;
+define symbol __size_cstack__ = 0x2000;
+define symbol __size_heap__   = 0x4000;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };
 

From c824d523d187c3712f0ee7c899ef7cd1bb999d1f Mon Sep 17 00:00:00 2001
From: Jeremy Brodt <jeremy.brodt@maximintegrated.com>
Date: Tue, 27 Sep 2016 14:51:13 -0500
Subject: [PATCH 14/89] Fixed deepsleep issue using IAR.

---
 targets/TARGET_Maxim/TARGET_MAX32620/sleep.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c b/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c
index 146c20c9e12..81874b0f2a4 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c
@@ -32,14 +32,12 @@
  */
 
 #include "sleep_api.h"
-#include "cmsis.h"
 #include "pwrman_regs.h"
 #include "pwrseq_regs.h"
 #include "clkman_regs.h"
 #include "ioman_regs.h"
 #include "rtc_regs.h"
 #include "usb_regs.h"
-#include "wait_api.h"
 
 #define REVISION_A3 2
 #define REVISION_A4 3
@@ -178,7 +176,7 @@ void deepsleep(void)
     MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
 
     // Dummy read to make sure SSB writes are complete
-    MXC_PWRSEQ->reg0;
+    MXC_PWRSEQ->reg0 = MXC_PWRSEQ->reg0;
 
     if (part_rev == REVISION_A4) {
         // Note: ARM deep-sleep requires a specific sequence to clear event latches,

From 3e51eb427fa5402d4b23ceced55f256f60e01bfc Mon Sep 17 00:00:00 2001
From: Jeremy Brodt <jeremy.brodt@maximintegrated.com>
Date: Wed, 5 Oct 2016 16:20:44 -0500
Subject: [PATCH 15/89] Added support for FEATURE_BLE. Integrated MaximBLE
 library.

---
 .../targets/TARGET_Maxim/MaximBLE.cpp         |  326 +++++
 .../targets/TARGET_Maxim/MaximBLE.h           |   92 ++
 .../targets/TARGET_Maxim/MaximGap.cpp         |  261 ++++
 .../targets/TARGET_Maxim/MaximGap.h           |  112 ++
 .../targets/TARGET_Maxim/MaximGattClient.h    |   58 +
 .../targets/TARGET_Maxim/MaximGattServer.cpp  |  439 ++++++
 .../targets/TARGET_Maxim/MaximGattServer.h    |   84 ++
 .../TARGET_Maxim/MaximSecurityManager.h       |   55 +
 ...RE-20767-ARM-Permissive-Binary-License.txt |   49 +
 .../TARGET_Maxim/exactLE/hci/maxwsn/hci_drv.h |  114 ++
 .../TARGET_Maxim/exactLE/hci/maxwsn/hci_vs.h  |   59 +
 .../exactLE/stack/cfg/cfg_stack.h             |   71 +
 .../exactLE/stack/include/att_api.h           |  942 +++++++++++++
 .../exactLE/stack/include/att_defs.h          |  221 +++
 .../exactLE/stack/include/att_handler.h       |   67 +
 .../exactLE/stack/include/att_uuid.h          |  431 ++++++
 .../exactLE/stack/include/dm_api.h            | 1235 +++++++++++++++++
 .../exactLE/stack/include/dm_handler.h        |   67 +
 .../exactLE/stack/include/hci_api.h           |  375 +++++
 .../exactLE/stack/include/hci_defs.h          |  462 ++++++
 .../exactLE/stack/include/hci_handler.h       |   67 +
 .../exactLE/stack/include/l2c_api.h           |  173 +++
 .../exactLE/stack/include/l2c_defs.h          |   76 +
 .../exactLE/stack/include/l2c_handler.h       |   66 +
 .../exactLE/stack/include/smp_api.h           |  195 +++
 .../exactLE/stack/include/smp_defs.h          |  122 ++
 .../exactLE/stack/include/smp_handler.h       |   67 +
 .../targets/TARGET_Maxim/exactLE/util/bda.h   |  109 ++
 .../exactLE/wsf/generic/wsf_os_int.h          |  105 ++
 .../exactLE/wsf/generic/wsf_types.h           |   61 +
 .../exactLE/wsf/include/wsf_buf.h             |  137 ++
 .../exactLE/wsf/include/wsf_msg.h             |  123 ++
 .../TARGET_Maxim/exactLE/wsf/include/wsf_os.h |  147 ++
 .../exactLE/wsf/include/wsf_queue.h           |  155 +++
 .../exactLE/wsf/include/wsf_sec.h             |  111 ++
 .../exactLE/wsf/include/wsf_timer.h           |  161 +++
 .../TOOLCHAIN_ARM_STD/exactLE.ar              |  Bin 2802216 -> 3274448 bytes
 .../TOOLCHAIN_GCC_ARM/libexactLE.a            |  Bin 1187986 -> 1189568 bytes
 .../TARGET_MAX32620/TOOLCHAIN_IAR/exactLE.a   |  Bin 2799426 -> 3278636 bytes
 targets/targets.json                          |    2 +
 40 files changed, 7397 insertions(+)
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/MaximBLE.cpp
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/MaximBLE.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/MaximGap.cpp
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/MaximGap.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/MaximGattClient.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/MaximGattServer.cpp
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/MaximGattServer.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/MaximSecurityManager.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/LES-PRE-20767-ARM-Permissive-Binary-License.txt
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/hci/maxwsn/hci_drv.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/hci/maxwsn/hci_vs.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/cfg/cfg_stack.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_api.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_defs.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_handler.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_uuid.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/dm_api.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/dm_handler.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/hci_api.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/hci_defs.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/hci_handler.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/l2c_api.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/l2c_defs.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/l2c_handler.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/smp_api.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/smp_defs.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/smp_handler.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/util/bda.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/generic/wsf_os_int.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/generic/wsf_types.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_buf.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_msg.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_os.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_queue.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_sec.h
 create mode 100644 features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_timer.h

diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/MaximBLE.cpp b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximBLE.cpp
new file mode 100644
index 00000000000..5d442d70c3a
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximBLE.cpp
@@ -0,0 +1,326 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "mbed.h"
+#include "us_ticker_api.h"
+#include "MaximBLE.h"
+#include "wsf_types.h"
+#include "wsf_msg.h"
+#include "wsf_os.h"
+#include "wsf_buf.h"
+#include "wsf_sec.h"
+#include "wsf_timer.h"
+#include "hci_handler.h"
+#include "dm_handler.h"
+#include "l2c_handler.h"
+#include "att_handler.h"
+#include "smp_handler.h"
+#include "l2c_api.h"
+#include "att_api.h"
+#include "smp_api.h"
+#include "hci_drv.h"
+#include "hci_vs.h"
+
+/* Number of WSF buffer pools */
+#define WSF_BUF_POOLS               4
+
+/*! Free memory for pool buffers. */
+static uint8_t mainBufMem[768];
+
+/*! Default pool descriptor. */
+static wsfBufPoolDesc_t mainPoolDesc[WSF_BUF_POOLS] =
+{
+  {  16,  8 },
+  {  32,  4 },
+  {  64,  2 },
+  { 128,  2 }
+};
+
+/*! WSF handler ID */
+wsfHandlerId_t maximHandlerId;
+static volatile int reset_complete;
+
+/* Current mbed SPI API does not support HW slave selects. Configured in HCI driver. */
+static DigitalOut _csn(HCI_CSN, 1);
+static SPI _spi(HCI_MOSI, HCI_MISO, HCI_SCK, HCI_CSN);
+static DigitalOut _rst(HCI_RST, 0);
+static InterruptIn _irq(HCI_IRQ);
+
+/**
+ * The singleton which represents the MaximBLE transport for the BLE.
+ */
+static MaximBLE deviceInstance;
+
+/**
+ * BLE-API requires an implementation of the following function in order to
+ * obtain its transport handle.
+ */
+BLEInstanceBase *createBLEInstance(void)
+{
+    return (&deviceInstance);
+}
+
+MaximBLE::MaximBLE(void) : initialized(false), instanceID(BLE::DEFAULT_INSTANCE)
+{
+}
+
+MaximBLE::~MaximBLE(void)
+{
+}
+
+const char *MaximBLE::getVersion(void)
+{
+    static char versionString[32];
+
+    strncpy(versionString, "unknown", sizeof(versionString));
+
+    return versionString;
+}
+
+static void DmCback(dmEvt_t *pDmEvt)
+{
+    dmEvt_t *pMsg;
+
+    if ((pMsg = (dmEvt_t*)WsfMsgAlloc(sizeof(dmEvt_t))) != NULL)
+    {
+        memcpy(pMsg, pDmEvt, sizeof(dmEvt_t));
+        WsfMsgSend(maximHandlerId, pMsg);
+    }
+}
+
+static void maximHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg)
+{
+    if (pMsg != NULL)
+    {
+        switch(pMsg->event)
+        {
+            case DM_RESET_CMPL_IND:
+                reset_complete = 1;
+                break;
+            case DM_ADV_START_IND:
+                break;
+            case DM_ADV_STOP_IND:
+                MaximGap::getInstance().advertisingStopped();
+                break;
+            case DM_SCAN_REPORT_IND:
+                {
+                    hciLeAdvReportEvt_t *scanReport = (hciLeAdvReportEvt_t*)pMsg;
+                    MaximGap::getInstance().processAdvertisementReport( scanReport->addr,
+                                                                        scanReport->rssi,
+                                                                        (scanReport->eventType == DM_ADV_SCAN_RESPONSE) ? true : false,
+                                                                        (GapAdvertisingParams::AdvertisingType_t)scanReport->eventType,
+                                                                        scanReport->len,
+                                                                        scanReport->pData);
+                }
+                break;
+            case DM_CONN_OPEN_IND:
+                {
+                    hciLeConnCmplEvt_t *connOpen = (hciLeConnCmplEvt_t*)pMsg;
+                    MaximGap::getInstance().setConnectionHandle(connOpen->handle);
+                    Gap::ConnectionParams_t params = { connOpen->connInterval, connOpen->connInterval, connOpen->connLatency, connOpen->supTimeout };
+                    Gap::AddressType_t ownAddrType;
+                    Gap::Address_t ownAddr;
+                    MaximGap::getInstance().getAddress(&ownAddrType, ownAddr);
+                    MaximGap::getInstance().processConnectionEvent(connOpen->handle,
+                                                                   Gap::PERIPHERAL,
+                                                                   (Gap::AddressType_t)connOpen->addrType,
+                                                                   connOpen->peerAddr,
+                                                                   ownAddrType,
+                                                                   ownAddr,
+                                                                   &params);
+                }
+                break;
+            case DM_CONN_CLOSE_IND:
+                {
+                    hciDisconnectCmplEvt_t *connClose = (hciDisconnectCmplEvt_t*)pMsg;
+                    MaximGap::getInstance().setConnectionHandle(DM_CONN_ID_NONE);
+                    MaximGap::getInstance().processDisconnectionEvent(connClose->handle, (Gap::DisconnectionReason_t)connClose->reason);
+                }
+                break;
+            case DM_HW_ERROR_IND:
+                {
+                    hciHwErrorEvt_t *error = (hciHwErrorEvt_t*)pMsg;
+                    printf("HCI Hardware Error 0x%02x occurred\n", error->code);
+                }
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+static void AppServerConnCback(dmEvt_t *pDmEvt)
+{
+  dmConnId_t connId = (dmConnId_t)pDmEvt->hdr.param;
+
+  switch (pDmEvt->hdr.event)
+  {
+    case DM_CONN_OPEN_IND:
+      /* set up CCC table with uninitialized (all zero) values */
+      AttsCccInitTable(connId, NULL);
+      break;
+    case DM_CONN_CLOSE_IND:
+      /* clear CCC table on connection close */
+      AttsCccClearTable(connId);
+      break;
+    default:
+      break;
+  }
+}
+
+ble_error_t MaximBLE::init(BLE::InstanceID_t instanceID, FunctionPointerWithContext<BLE::InitializationCompleteCallbackContext *> initCallback)
+{
+    wsfHandlerId_t handlerId;
+
+    /* init OS subsystems */
+    WsfTimerInit(1);
+    WsfBufInit(sizeof(mainBufMem), mainBufMem, WSF_BUF_POOLS, mainPoolDesc);
+    WsfSecInit();
+
+    /* init stack */
+    handlerId = WsfOsSetNextHandler(HciHandler);
+    HciHandlerInit(handlerId);
+
+    handlerId = WsfOsSetNextHandler(DmHandler);
+    DmAdvInit();
+    DmScanInit();
+    DmConnInit();
+    DmConnSlaveInit();
+    DmSecInit();
+    DmHandlerInit(handlerId);
+
+    handlerId = WsfOsSetNextHandler(L2cSlaveHandler);
+    L2cSlaveHandlerInit(handlerId);
+    L2cInit();
+    L2cMasterInit();
+    L2cSlaveInit();
+
+    handlerId = WsfOsSetNextHandler(AttHandler);
+    AttHandlerInit(handlerId);
+    AttsInit();
+    AttsIndInit();
+    AttcInit();
+
+    handlerId = WsfOsSetNextHandler(SmpHandler);
+    SmpHandlerInit(handlerId);
+    SmpiInit();
+    SmprInit();
+
+    /* store handler ID */
+    maximHandlerId = WsfOsSetNextHandler(maximHandler);
+
+    /* init HCI */
+    _irq.disable_irq();
+    _irq.rise(hciDrvIsr);
+    _irq.fall(NULL);
+    hciDrvInit(HCI_CSN, HCI_RST, HCI_IRQ);
+
+    /* Register for stack callbacks */
+    DmRegister(DmCback);
+    DmConnRegister(DM_CLIENT_ID_APP, DmCback);
+    AttConnRegister(AppServerConnCback);
+
+    /* Reset the device */
+    reset_complete = 0;
+    DmDevReset();
+
+    while (!reset_complete) {
+        callDispatcher();
+    }
+
+    initialized = true;
+    BLE::InitializationCompleteCallbackContext context = {
+        BLE::Instance(instanceID),
+        BLE_ERROR_NONE
+    };
+    initCallback.call(&context);
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t MaximBLE::shutdown(void)
+{
+    return BLE_ERROR_NOT_IMPLEMENTED;
+}
+
+void MaximBLE::waitForEvent(void)
+{
+    static LowPowerTimeout nextTimeout;
+    timestamp_t nextTimestamp;
+    bool_t pTimerRunning;
+
+    callDispatcher();
+
+    if (wsfOsReadyToSleep()) {
+        // setup an mbed timer for the next Wicentric timeout
+        nextTimestamp = (timestamp_t)WsfTimerNextExpiration(&pTimerRunning) * 1000;
+        if (pTimerRunning) {
+            nextTimeout.attach_us(timeoutCallback, nextTimestamp);
+        }
+
+        // go to sleep
+        if (hciDrvReadyToSleep()) {
+            // go to deep sleep
+            deepsleep();
+            hciDrvResume();
+        }
+        else {
+            sleep();
+        }
+    }
+}
+
+void MaximBLE::processEvents()
+{
+    callDispatcher();
+}
+
+void MaximBLE::timeoutCallback(void)
+{
+    // do nothing. just an interrupt for wake up.
+}
+
+void MaximBLE::callDispatcher(void)
+{
+    static uint32_t lastTimeUs = us_ticker_read();
+    uint32_t currTimeUs, deltaTimeMs;
+
+    // Update the current Wicentric time
+    currTimeUs = us_ticker_read();
+    deltaTimeMs = (currTimeUs - lastTimeUs) / 1000;
+    if (deltaTimeMs > 0) {
+        WsfTimerUpdate(deltaTimeMs);
+        lastTimeUs += deltaTimeMs * 1000;
+    }
+
+    wsfOsDispatcher();
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/MaximBLE.h b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximBLE.h
new file mode 100644
index 00000000000..a36cea96bcd
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximBLE.h
@@ -0,0 +1,92 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MAXIMBLE_H_
+#define _MAXIMBLE_H_
+
+#include "ble/BLE.h"
+#include "ble/blecommon.h"
+#include "ble/BLEInstanceBase.h"
+
+#include "MaximGap.h"
+#include "MaximGattServer.h"
+#include "MaximGattClient.h"
+#include "MaximSecurityManager.h"
+
+class MaximBLE : public BLEInstanceBase
+{
+public:
+    MaximBLE(void);
+    virtual ~MaximBLE(void);
+
+    virtual ble_error_t init(BLE::InstanceID_t instanceID, FunctionPointerWithContext<BLE::InitializationCompleteCallbackContext *> initCallback);
+    virtual bool        hasInitialized(void) const {
+        return initialized;
+    }
+    virtual ble_error_t shutdown(void);
+    virtual const char *getVersion(void);
+
+    virtual Gap &getGap() {
+        return MaximGap::getInstance();
+    };
+    virtual const Gap &getGap() const {
+        return MaximGap::getInstance();
+    };
+    virtual GattServer &getGattServer() {
+        return MaximGattServer::getInstance();
+    };
+    virtual const GattServer &getGattServer() const {
+        return MaximGattServer::getInstance();
+    };
+    virtual GattClient &getGattClient() {
+        return MaximGattClient::getInstance();
+    };
+    virtual SecurityManager &getSecurityManager() {
+        return MaximSecurityManager::getInstance();
+    };
+    virtual const SecurityManager &getSecurityManager() const {
+        return MaximSecurityManager::getInstance();
+    };
+
+    virtual void waitForEvent(void);
+    virtual void processEvents(void);
+
+private:
+    bool              initialized;
+    BLE::InstanceID_t instanceID;
+
+    static void timeoutCallback(void);
+    void callDispatcher(void);
+};
+
+#endif /* _MAXIMBLE_H_ */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGap.cpp b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGap.cpp
new file mode 100644
index 00000000000..e6cb24d43a6
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGap.cpp
@@ -0,0 +1,261 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "MaximGap.h"
+#include "mbed.h"
+#include "hci_vs.h"
+
+MaximGap &MaximGap::getInstance() {
+    static MaximGap m_instance;
+    return m_instance;
+}
+
+ble_error_t MaximGap::setAdvertisingData(const GapAdvertisingData &advData, const GapAdvertisingData &scanResponse)
+{
+    /* Make sure we don't exceed the advertising payload length */
+    if (advData.getPayloadLen() > GAP_ADVERTISING_DATA_MAX_PAYLOAD) {
+        return BLE_ERROR_BUFFER_OVERFLOW;
+    }
+
+    /* Make sure we have a payload! */
+    if (advData.getPayloadLen() == 0) {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+
+    /* save advertising and scan response data */
+    advDataLen = advData.getPayloadLen();
+    scanResponseLen = scanResponse.getPayloadLen();
+    memcpy((void*)advDataCache, (void*)advData.getPayload(), advDataLen);
+    memcpy((void*)advDataCache, (void*)advData.getPayload(), scanResponseLen);
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t MaximGap::startAdvertising(const GapAdvertisingParams &params)
+{
+    /* Make sure we support the advertising type */
+    if (params.getAdvertisingType() == GapAdvertisingParams::ADV_CONNECTABLE_DIRECTED) {
+        /* ToDo: This requires a proper security implementation, etc. */
+        return BLE_ERROR_NOT_IMPLEMENTED;
+    }
+
+    /* Check interval range */
+    if (params.getAdvertisingType() == GapAdvertisingParams::ADV_NON_CONNECTABLE_UNDIRECTED) {
+        /* Min delay is slightly longer for unconnectable devices */
+        if ((params.getInterval() < GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MIN_NONCON) ||
+            (params.getInterval() > GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MAX)) {
+            return BLE_ERROR_PARAM_OUT_OF_RANGE;
+        }
+    } else {
+        if ((params.getInterval() < GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MIN) ||
+            (params.getInterval() > GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MAX)) {
+            return BLE_ERROR_PARAM_OUT_OF_RANGE;
+        }
+    }
+
+    /* Check timeout is zero for Connectable Directed */
+    if ((params.getAdvertisingType() == GapAdvertisingParams::ADV_CONNECTABLE_DIRECTED) && (params.getTimeout() != 0)) {
+        /* Timeout must be 0 with this type, although we'll never get here */
+        /* since this isn't implemented yet anyway */
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+
+    /* Check timeout for other advertising types */
+    if ((params.getAdvertisingType() != GapAdvertisingParams::ADV_CONNECTABLE_DIRECTED) &&
+        (params.getTimeout() > GapAdvertisingParams::GAP_ADV_PARAMS_TIMEOUT_MAX)) {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+
+    /* set advertising and scan response data for discoverable mode */
+    DmAdvSetData(DM_DATA_LOC_ADV, advDataLen, advDataCache);
+    DmAdvSetData(DM_DATA_LOC_SCAN, scanResponseLen, scanResponseCache);
+
+    DmAdvSetInterval(params.getInterval(), params.getInterval());
+    DmAdvStart(params.getAdvertisingType(), params.getTimeout());
+
+    state.advertising = 1;
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t MaximGap::stopAdvertising(void)
+{
+    DmAdvStop();
+
+    state.advertising = 0;
+
+    return BLE_ERROR_NONE;
+}
+
+void MaximGap::advertisingStopped(void)
+{
+    /* If advertising stopped due to a call to stopAdvertising(), state.advertising will
+     * be '0.' Otherwise, advertising must have stopped due to a timeout
+     */
+    if (state.advertising) {
+        processTimeoutEvent(Gap::TIMEOUT_SRC_ADVERTISING);
+    }
+}
+
+ble_error_t MaximGap::disconnect(DisconnectionReason_t reason)
+{
+    DmConnClose(DM_CLIENT_ID_APP, m_connectionHandle, reason);
+
+    state.advertising = 0;
+    state.connected = 0;
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t MaximGap::disconnect(Handle_t connectionHandle, DisconnectionReason_t reason)
+{
+    DmConnClose(DM_CLIENT_ID_APP, connectionHandle, reason);
+
+    state.advertising = 0;
+    state.connected = 0;
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t MaximGap::getPreferredConnectionParams(ConnectionParams_t *params)
+{
+    return BLE_ERROR_NOT_IMPLEMENTED;
+}
+
+ble_error_t MaximGap::setPreferredConnectionParams(const ConnectionParams_t *params)
+{
+    return BLE_ERROR_NOT_IMPLEMENTED;
+}
+
+ble_error_t MaximGap::updateConnectionParams(Handle_t handle, const ConnectionParams_t *newParams)
+{
+    if (DmConnCheckIdle(handle) != 0) {
+        return BLE_STACK_BUSY;
+    }
+
+    hciConnSpec_t connSpec;
+    connSpec.connIntervalMin = newParams->minConnectionInterval;
+    connSpec.connIntervalMax = newParams->maxConnectionInterval;
+    connSpec.connLatency = newParams->slaveLatency;
+    connSpec.supTimeout = newParams->connectionSupervisionTimeout;
+    DmConnUpdate(handle, &connSpec);
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t MaximGap::startRadioScan(const GapScanningParams &scanningParams)
+{
+    DmScanSetInterval(scanningParams.getInterval(), scanningParams.getWindow());
+
+    uint8_t scanType = scanningParams.getActiveScanning() ? DM_SCAN_TYPE_ACTIVE : DM_SCAN_TYPE_PASSIVE;
+    uint32_t duration = (uint32_t)scanningParams.getTimeout() * 1000;
+    if (duration > 0xFFFF) {
+        // saturate to 16-bits
+        duration = 0xFFFF;
+    }
+
+    DmScanStart(DM_DISC_MODE_NONE, scanType, TRUE, duration);
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t MaximGap::stopScan(void)
+{
+    DmScanStop();
+    return BLE_ERROR_NONE;
+}
+
+void MaximGap::setConnectionHandle(uint16_t connectionHandle)
+{
+    m_connectionHandle = connectionHandle;
+}
+
+uint16_t MaximGap::getConnectionHandle(void)
+{
+    return m_connectionHandle;
+}
+
+ble_error_t MaximGap::setAddress(AddressType_t type, const Address_t address)
+{
+    if ((type != BLEProtocol::AddressType::PUBLIC) && (type != BLEProtocol::AddressType::RANDOM_STATIC)) {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+
+    m_type = type;
+    HciVsSetPublicAddr((uint8_t*)address);
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t MaximGap::getAddress(AddressType_t *typeP, Address_t address)
+{
+    *typeP = m_type;
+    BdaCpy(address, HciGetBdAddr());
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t MaximGap::setDeviceName(const uint8_t *deviceName)
+{
+    return BLE_ERROR_NOT_IMPLEMENTED;
+}
+
+ble_error_t MaximGap::getDeviceName(uint8_t *deviceName, unsigned *lengthP)
+{
+    return BLE_ERROR_NOT_IMPLEMENTED;
+}
+
+ble_error_t MaximGap::setAppearance(GapAdvertisingData::Appearance appearance)
+{
+    return BLE_ERROR_NOT_IMPLEMENTED;
+}
+
+ble_error_t MaximGap::getAppearance(GapAdvertisingData::Appearance *appearanceP)
+{
+    return BLE_ERROR_NOT_IMPLEMENTED;
+}
+
+ble_error_t MaximGap::setTxPower(int8_t txPower)
+{
+    HciVsSetTxPower(txPower);
+    return BLE_ERROR_NONE;
+}
+
+void MaximGap::getPermittedTxPowerValues(const int8_t **valueArrayPP, size_t *countP)
+{
+    static const int8_t permittedTxValues[] = {
+        -18, -15, -12, -9, -6, -3, 0, 3
+    };
+
+    *valueArrayPP = permittedTxValues;
+    *countP = sizeof(permittedTxValues) / sizeof(int8_t);
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGap.h b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGap.h
new file mode 100644
index 00000000000..d126bc9069d
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGap.h
@@ -0,0 +1,112 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MAXIM_GAP_H_
+#define _MAXIM_GAP_H_
+
+#include "mbed.h"
+#include "ble/blecommon.h"
+#include "ble/GapAdvertisingParams.h"
+#include "ble/GapAdvertisingData.h"
+#include "ble/Gap.h"
+#include "ble/GapScanningParams.h"
+#include "dm_api.h"
+#include "att_api.h"
+
+/**************************************************************************/
+/*!
+    \brief
+
+*/
+/**************************************************************************/
+class MaximGap : public Gap
+{
+public:
+    static MaximGap &getInstance();
+
+    /* Functions that must be implemented from Gap */
+    virtual ble_error_t setAddress(AddressType_t  type,  const Address_t address);
+    virtual ble_error_t getAddress(AddressType_t *typeP, Address_t address);
+    virtual ble_error_t setAdvertisingData(const GapAdvertisingData &, const GapAdvertisingData &);
+
+    #define BLE_GAP_ADV_INTERVAL_MIN        0x0020 /**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */
+    #define BLE_GAP_ADV_NONCON_INTERVAL_MIN 0x00A0 /**< Minimum Advertising interval in 625 us units for non connectable mode, i.e. 100 ms. */
+    #define BLE_GAP_ADV_INTERVAL_MAX        0x4000 /**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */
+
+    virtual uint16_t getMinAdvertisingInterval(void) const { return BLE_GAP_ADV_INTERVAL_MIN; }
+    virtual uint16_t getMinNonConnectableAdvertisingInterval(void) const { return BLE_GAP_ADV_NONCON_INTERVAL_MIN; }
+    virtual uint16_t getMaxAdvertisingInterval(void) const { return BLE_GAP_ADV_INTERVAL_MAX; }
+
+    virtual ble_error_t startAdvertising(const GapAdvertisingParams &);
+    virtual ble_error_t stopAdvertising(void);
+    virtual ble_error_t disconnect(Handle_t connectionHandle, DisconnectionReason_t reason);
+    virtual ble_error_t disconnect(DisconnectionReason_t reason);
+
+    virtual ble_error_t setDeviceName(const uint8_t *deviceName);
+    virtual ble_error_t getDeviceName(uint8_t *deviceName, unsigned *lengthP);
+    virtual ble_error_t setAppearance(GapAdvertisingData::Appearance appearance);
+    virtual ble_error_t getAppearance(GapAdvertisingData::Appearance *appearanceP);
+
+    virtual ble_error_t setTxPower(int8_t txPower);
+    virtual void        getPermittedTxPowerValues(const int8_t **valueArrayPP, size_t *countP);
+
+    void     setConnectionHandle(uint16_t m_connectionHandle);
+    uint16_t getConnectionHandle(void);
+
+    virtual ble_error_t getPreferredConnectionParams(ConnectionParams_t *params);
+    virtual ble_error_t setPreferredConnectionParams(const ConnectionParams_t *params);
+    virtual ble_error_t updateConnectionParams(Handle_t handle, const ConnectionParams_t *params);
+
+    virtual ble_error_t startRadioScan(const GapScanningParams &scanningParams);
+    virtual ble_error_t stopScan(void);
+
+    void     advertisingStopped(void);
+
+private:
+    uint16_t m_connectionHandle;
+    addr_type_t m_type;
+    MaximGap() {
+        m_connectionHandle = DM_CONN_ID_NONE;
+        m_type = BLEProtocol::AddressType::RANDOM_STATIC;
+    }
+
+    MaximGap(MaximGap const &);
+    void operator=(MaximGap const &);
+    
+    uint8_t advDataCache[HCI_LEN_LE_SET_ADV_DATA];
+    uint8_t scanResponseCache[HCI_LEN_LE_SET_SCAN_RESP_DATA];
+    int advDataLen;
+    int scanResponseLen;
+};
+
+#endif /* _MAXIM_GAP_H_ */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGattClient.h b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGattClient.h
new file mode 100644
index 00000000000..5b78091471c
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGattClient.h
@@ -0,0 +1,58 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MAXIM_GATT_CLIENT_H_
+#define _MAXIM_GATT_CLIENT_H_
+
+#include <stddef.h>
+
+#include "ble/GattClient.h"
+
+class MaximGattClient : public GattClient
+{
+public:
+    static MaximGattClient &getInstance() {
+        static MaximGattClient m_instance;
+        return m_instance;
+    }
+
+public:
+    MaximGattClient() {
+        /* empty */
+    }
+
+private:
+
+};
+
+#endif /* _MAXIM_GATT_CLIENT_H_ */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGattServer.cpp b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGattServer.cpp
new file mode 100644
index 00000000000..c381e733f55
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGattServer.cpp
@@ -0,0 +1,439 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "MaximGattServer.h"
+#include "mbed.h"
+#include "MaximGap.h"
+#include "wsf_types.h"
+#include "att_api.h"
+
+typedef struct mxmChar_s {
+    uint16_t descLen;
+    mxmChar_s() {}
+} mxmChar_t;
+
+typedef struct mxmService_s mxmService_t;
+struct mxmService_s {
+    uint16_t uuidLen;
+    mxmChar_t *chars;
+    attsGroup_t *attGroup;
+    mxmService_t *next;
+    mxmService_s() {}
+};
+
+static uint16_t currentHandle = 0x20;
+
+static UUID cccUUID(BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG);
+static const uint16_t cccSize = sizeof(uint16_t);
+
+MaximGattServer &MaximGattServer::getInstance() {
+    static MaximGattServer m_instance;
+    return m_instance;
+}
+
+ble_error_t MaximGattServer::addService(GattService &service)
+{
+    currentHandle = (currentHandle + 0xF) & ~0xF;
+    uint16_t startHandle = currentHandle;
+
+    mxmService_t *mxmSvc = new mxmService_t;
+
+    // Create WiCentric attribute group
+    mxmSvc->attGroup = new attsGroup_t;
+
+    // Determine the attribute list length
+    unsigned int attListLen = 1;
+    for (int i = 0; i < service.getCharacteristicCount(); i++) {
+        attListLen += 2;
+        GattCharacteristic *p_char = service.getCharacteristic(i);
+
+        if (p_char->getProperties() & (GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY | GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_INDICATE)) {
+            // add a CCCD
+            attListLen++;
+        }
+    }
+
+    // Create WiCentric attribute list
+    mxmSvc->attGroup->pAttr = (attsAttr_t*)malloc(attListLen * sizeof(attsAttr_t));;
+    if (mxmSvc->attGroup->pAttr == NULL) {
+        return BLE_ERROR_BUFFER_OVERFLOW;
+    }
+
+    // Create characteristics
+    mxmSvc->chars = new mxmChar_t [service.getCharacteristicCount()];
+
+    attsAttr_t *currAtt = mxmSvc->attGroup->pAttr;
+
+    /* Service */
+    currAtt->pUuid = attPrimSvcUuid;
+    if (service.getUUID().shortOrLong() == UUID::UUID_TYPE_LONG) {
+        mxmSvc->uuidLen = UUID::LENGTH_OF_LONG_UUID;
+    } else {
+        mxmSvc->uuidLen = sizeof(UUID::ShortUUIDBytes_t);
+    }
+    currAtt->pValue = (uint8_t*)malloc(mxmSvc->uuidLen);
+    memcpy(currAtt->pValue, service.getUUID().getBaseUUID(), mxmSvc->uuidLen);
+    currAtt->maxLen = mxmSvc->uuidLen;
+    currAtt->pLen = &mxmSvc->uuidLen;
+    currAtt->settings = 0;
+    currAtt->permissions = ATTS_PERMIT_READ;
+
+    currAtt++;
+
+    /* Add characteristics to the service */
+    for (int i = 0; i < service.getCharacteristicCount(); i++) {
+        GattCharacteristic *p_char = service.getCharacteristic(i);
+
+        /* Skip any incompletely defined, read-only characteristics. */
+        if ((p_char->getValueAttribute().getValuePtr() == NULL) &&
+            (p_char->getValueAttribute().getLength() == 0) &&
+            (p_char->getProperties() == GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_READ)) {
+            continue;
+        }
+
+        // Create Characteristic Attribute
+        currentHandle += 2;
+        currAtt->pUuid = attChUuid;
+
+        p_char->getValueAttribute().setHandle(currentHandle);
+        mxmSvc->chars[i].descLen = 1 + sizeof(currentHandle) + p_char->getValueAttribute().getUUID().getLen();
+        currAtt->pValue = (uint8_t*)malloc(mxmSvc->chars[i].descLen);
+        uint8_t *pValue = currAtt->pValue;
+        *pValue++ = p_char->getProperties();
+        memcpy(pValue, &currentHandle, sizeof(currentHandle));
+        pValue += sizeof(currentHandle);
+        memcpy(pValue, p_char->getValueAttribute().getUUID().getBaseUUID(), p_char->getValueAttribute().getUUID().getLen());
+
+        currAtt->pLen = &mxmSvc->chars[i].descLen;
+        currAtt->maxLen = mxmSvc->chars[i].descLen;
+        currAtt->settings = 0;
+        currAtt->permissions = ATTS_PERMIT_READ;
+        currAtt++;
+
+        // Create Value Attribute
+        currAtt->pUuid = p_char->getValueAttribute().getUUID().getBaseUUID();
+        currAtt->pValue = p_char->getValueAttribute().getValuePtr();
+        currAtt->pLen = p_char->getValueAttribute().getLengthPtr();
+        currAtt->maxLen = p_char->getValueAttribute().getMaxLength();
+        currAtt->settings = ATTS_SET_WRITE_CBACK | ATTS_SET_READ_CBACK;
+        if (p_char->getValueAttribute().getUUID().shortOrLong() == UUID::UUID_TYPE_LONG) {
+            currAtt->settings |= ATTS_SET_UUID_128;
+        }
+        currAtt->permissions = 0;
+        if (p_char->getProperties() & GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_READ)  { currAtt->permissions |= ATTS_PERMIT_READ; }
+        if (p_char->getProperties() & GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_WRITE) { currAtt->permissions |= ATTS_PERMIT_WRITE; }
+        currAtt++;
+
+        bool cccCreated = false;
+
+        for (int i = 0; i < p_char->getDescriptorCount(); i++) {
+            GattAttribute *p_att = p_char->getDescriptor(i);
+
+            currentHandle++;
+
+            currAtt->pUuid = p_att->getUUID().getBaseUUID();
+            currAtt->pValue = p_att->getValuePtr();
+            currAtt->pLen = p_att->getLengthPtr();
+            currAtt->maxLen = p_att->getMaxLength();
+            currAtt->settings = 0;
+            currAtt->permissions = 0;
+            if (p_att->getUUID().shortOrLong() == UUID::UUID_TYPE_LONG) {
+                currAtt->settings |= ATTS_SET_UUID_128;
+            }
+            if (p_att->getUUID() == UUID(BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG)) {
+                cccCreated = true;
+                currAtt->settings |= ATTS_SET_CCC;
+                currAtt->permissions |= ATTS_PERMIT_READ;
+                currAtt->permissions |= ATTS_PERMIT_WRITE;
+
+                if (cccCnt < MAX_CCC_CNT) {
+                    cccSet[cccCnt].handle = currentHandle;
+                    cccSet[cccCnt].valueRange = 0;
+                    if (p_char->getProperties() & GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY) {
+                        cccSet[cccCnt].valueRange |= ATT_CLIENT_CFG_NOTIFY;
+                    }
+                    if (p_char->getProperties() & GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_INDICATE) {
+                        cccSet[cccCnt].valueRange |= ATT_CLIENT_CFG_INDICATE;
+                    }
+                    cccSet[cccCnt].secLevel = DM_SEC_LEVEL_NONE;
+                    cccHandles[cccCnt] = p_char->getValueAttribute().getHandle();
+                    cccCnt++;
+                } else {
+                    return BLE_ERROR_PARAM_OUT_OF_RANGE;
+                }
+            }
+            currAtt++;
+        }
+
+        if (!cccCreated && (p_char->getProperties() & (GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY | GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_INDICATE))) {
+            /* There was not a CCCD included in the descriptors, but this
+             * characteristic is notifiable and/or indicatable. A CCCD is
+             * required so create one now.
+             */
+            if (cccCnt >= MAX_CCC_CNT) {
+                return BLE_ERROR_PARAM_OUT_OF_RANGE;
+            }
+
+            currentHandle++;
+
+            currAtt->pUuid = cccUUID.getBaseUUID();
+            currAtt->pValue = (uint8_t*)&cccValues[cccCnt];
+            currAtt->pLen = (uint16_t*)&cccSize;
+            currAtt->maxLen = sizeof(uint16_t);
+            currAtt->settings = ATTS_SET_CCC;
+            currAtt->permissions = (ATTS_PERMIT_READ | ATTS_PERMIT_WRITE);
+
+            cccSet[cccCnt].handle = currentHandle;
+            cccSet[cccCnt].valueRange = 0;
+            if (p_char->getProperties() & GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY) {
+                cccSet[cccCnt].valueRange |= ATT_CLIENT_CFG_NOTIFY;
+            }
+            if (p_char->getProperties() & GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_INDICATE) {
+                cccSet[cccCnt].valueRange |= ATT_CLIENT_CFG_INDICATE;
+            }
+            cccSet[cccCnt].secLevel = DM_SEC_LEVEL_NONE;
+            cccHandles[cccCnt] = p_char->getValueAttribute().getHandle();
+
+            cccCnt++;
+            currAtt++;
+        }
+    }
+
+    mxmSvc->attGroup->pNext = NULL;
+    mxmSvc->attGroup->readCback = attsReadCback;
+    mxmSvc->attGroup->writeCback = attsWriteCback;
+    mxmSvc->attGroup->startHandle = startHandle;
+    mxmSvc->attGroup->endHandle = currentHandle;
+    AttsAddGroup(mxmSvc->attGroup);
+
+    AttRegister(attCback);
+    AttsCccRegister(cccCnt, (attsCccSet_t*)cccSet, cccCback);
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t MaximGattServer::read(GattAttribute::Handle_t attributeHandle, uint8_t buffer[], uint16_t *const lengthP)
+{
+    if (AttsGetAttr(attributeHandle, lengthP, &buffer) != ATT_SUCCESS) {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t MaximGattServer::read(Gap::Handle_t connectionHandle, GattAttribute::Handle_t attributeHandle, uint8_t buffer[], uint16_t *lengthP)
+{
+    // Check to see if this is a CCCD
+    uint8_t idx;
+    for (idx = 0; idx < cccCnt; idx++) {
+        if (attributeHandle == cccSet[idx].handle) {
+            if (connectionHandle == DM_CONN_ID_NONE) { // CCCDs are always 16 bits
+                return BLE_ERROR_PARAM_OUT_OF_RANGE;
+            }
+            *((uint16_t*)buffer) = AttsCccGet(connectionHandle, idx);
+            *lengthP = 2;   // CCCDs are always 16 bits
+            return BLE_ERROR_NONE;
+        }
+    }
+
+    // This is not a CCCD. Use the non-connection specific update method.
+    return read(attributeHandle, buffer, lengthP);
+}
+
+ble_error_t MaximGattServer::write(GattAttribute::Handle_t attributeHandle, const uint8_t buffer[], uint16_t len, bool localOnly)
+{
+    uint16_t connectionHandle = MaximGap::getInstance().getConnectionHandle();
+
+    if (AttsSetAttr(attributeHandle, len, (uint8_t*)buffer) != ATT_SUCCESS) {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+
+    if (!localOnly) {
+        if (connectionHandle != DM_CONN_ID_NONE) {
+
+            // Check to see if this characteristic has a CCCD attribute
+            uint8_t idx;
+            for (idx = 0; idx < cccCnt; idx++) {
+                if (attributeHandle == cccHandles[idx]) {
+                    break;
+                }
+            }
+            if (idx < cccCnt) {
+                // This characteristic has a CCCD attribute. Handle notifications and indications.
+                uint16_t cccEnabled = AttsCccEnabled(connectionHandle, idx);
+                if (cccEnabled & ATT_CLIENT_CFG_NOTIFY) {
+                    AttsHandleValueNtf(connectionHandle, attributeHandle, len, (uint8_t*)buffer);
+                }
+                if (cccEnabled & ATT_CLIENT_CFG_INDICATE) {
+                    AttsHandleValueInd(connectionHandle, attributeHandle, len, (uint8_t*)buffer);
+                }
+            }
+        }
+    }
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t MaximGattServer::write(Gap::Handle_t connectionHandle, GattAttribute::Handle_t attributeHandle, const uint8_t buffer[], uint16_t len, bool localOnly)
+{
+    // Check to see if this is a CCCD
+    uint8_t idx;
+    for (idx = 0; idx < cccCnt; idx++) {
+        if (attributeHandle == cccSet[idx].handle) {
+            if ((connectionHandle == DM_CONN_ID_NONE) || (len != 2)) { // CCCDs are always 16 bits
+                return BLE_ERROR_PARAM_OUT_OF_RANGE;
+            }
+            AttsCccSet(connectionHandle, idx, *((uint16_t*)buffer));
+            return BLE_ERROR_NONE;
+        }
+    }
+
+    // This is not a CCCD. Use the non-connection specific update method.
+    return write(attributeHandle, buffer, len, localOnly);
+}
+
+ble_error_t MaximGattServer::areUpdatesEnabled(const GattCharacteristic &characteristic, bool *enabledP)
+{
+    uint16_t connectionHandle = MaximGap::getInstance().getConnectionHandle();
+
+    if (connectionHandle != DM_CONN_ID_NONE) {
+        uint8_t idx;
+        for (idx = 0; idx < cccCnt; idx++) {
+            if (characteristic.getValueHandle() == cccHandles[idx]) {
+                uint16_t cccValue = AttsCccGet(connectionHandle, idx);
+                if (cccValue & ATT_CLIENT_CFG_NOTIFY) {
+                    *enabledP = true;
+                } else {
+                    *enabledP = false;
+                }
+                return BLE_ERROR_NONE;
+            }
+        }
+    }
+
+    return BLE_ERROR_PARAM_OUT_OF_RANGE;
+}
+
+ble_error_t MaximGattServer::areUpdatesEnabled(Gap::Handle_t connectionHandle, const GattCharacteristic &characteristic, bool *enabledP)
+{
+    if (connectionHandle != DM_CONN_ID_NONE) {
+        uint8_t idx;
+        for (idx = 0; idx < cccCnt; idx++) {
+            if (characteristic.getValueHandle() == cccHandles[idx]) {
+                uint16_t cccValue = AttsCccGet(connectionHandle, idx);
+                if (cccValue & ATT_CLIENT_CFG_NOTIFY) {
+                    *enabledP = true;
+                } else {
+                    *enabledP = false;
+                }
+                return BLE_ERROR_NONE;
+            }
+        }
+    }
+
+    return BLE_ERROR_PARAM_OUT_OF_RANGE;
+}
+
+void MaximGattServer::cccCback(attsCccEvt_t *pEvt)
+{
+    if (pEvt->value & (ATT_CLIENT_CFG_NOTIFY | ATT_CLIENT_CFG_INDICATE)) {
+        getInstance().handleEvent(GattServerEvents::GATT_EVENT_UPDATES_ENABLED, pEvt->handle);
+    } else {
+        getInstance().handleEvent(GattServerEvents::GATT_EVENT_UPDATES_DISABLED, pEvt->handle);
+    }
+}
+
+void MaximGattServer::attCback(attEvt_t *pEvt)
+{
+    if (pEvt->hdr.status == ATT_SUCCESS) {
+        getInstance().handleEvent(GattServerEvents::GATT_EVENT_DATA_SENT, pEvt->handle);
+    }
+}
+
+uint8_t MaximGattServer::attsReadCback(dmConnId_t connId, uint16_t handle, uint8_t operation, uint16_t offset, attsAttr_t *pAttr)
+{
+    GattReadCallbackParams cbParams = {
+        .connHandle = connId,
+        .handle     = handle,
+        .offset     = offset,
+        .len        = *pAttr->pLen,
+        .data       = pAttr->pValue
+    };
+    getInstance().handleDataReadEvent(&cbParams);
+
+    return ATT_SUCCESS;
+}
+
+uint8_t MaximGattServer::attsWriteCback(dmConnId_t connId, uint16_t handle, uint8_t operation, uint16_t offset, uint16_t len, uint8_t *pValue, attsAttr_t *pAttr)
+{
+    uint8_t err;
+
+    /* TODO: offset is not handled properly */
+    if ((err = AttsSetAttr(handle, len, pValue)) != ATT_SUCCESS) {
+        return err;
+    }
+
+    GattWriteCallbackParams::WriteOp_t writeOp;
+    switch (operation) {
+        case ATT_PDU_WRITE_REQ:
+            writeOp = GattWriteCallbackParams::OP_WRITE_REQ;
+            break;
+        case ATT_PDU_WRITE_CMD:
+            writeOp = GattWriteCallbackParams::OP_WRITE_CMD;
+            break;
+        case ATT_PDU_SIGNED_WRITE_CMD:
+            writeOp = GattWriteCallbackParams::OP_SIGN_WRITE_CMD;
+            break;
+        case ATT_PDU_PREP_WRITE_REQ:
+            writeOp = GattWriteCallbackParams::OP_PREP_WRITE_REQ;
+            break;
+        case ATT_PDU_EXEC_WRITE_REQ:
+            writeOp = GattWriteCallbackParams::OP_EXEC_WRITE_REQ_NOW;
+            break;
+        default:
+            writeOp = GattWriteCallbackParams::OP_INVALID;
+            break;
+    }
+
+    GattWriteCallbackParams cbParams = {
+        .connHandle = connId,
+        .handle     = handle,
+        .writeOp    = writeOp,
+        .offset     = offset,
+        .len        = len,
+        .data       = pValue
+    };
+    getInstance().handleDataWrittenEvent(&cbParams);
+
+    return ATT_SUCCESS;
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGattServer.h b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGattServer.h
new file mode 100644
index 00000000000..faed713d61a
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximGattServer.h
@@ -0,0 +1,84 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MAXIM_GATT_SERVER_H_
+#define _MAXIM_GATT_SERVER_H_
+
+#include <stddef.h>
+
+#include "ble/blecommon.h"
+#include "ble/GattServer.h"
+#include "wsf_types.h"
+#include "att_api.h"
+
+class MaximGattServer : public GattServer
+{
+public:
+    static MaximGattServer &getInstance();
+
+    /* Functions that must be implemented from GattServer */
+    virtual ble_error_t addService(GattService &);
+
+    virtual ble_error_t read(GattAttribute::Handle_t attributeHandle, uint8_t buffer[], uint16_t *lengthP);
+    virtual ble_error_t read(Gap::Handle_t connectionHandle, GattAttribute::Handle_t attributeHandle, uint8_t buffer[], uint16_t *lengthP);
+    virtual ble_error_t write(GattAttribute::Handle_t, const uint8_t[], uint16_t, bool localOnly = false);
+    virtual ble_error_t write(Gap::Handle_t connectionHandle, GattAttribute::Handle_t, const uint8_t[], uint16_t, bool localOnly = false);
+
+    virtual ble_error_t areUpdatesEnabled(const GattCharacteristic &characteristic, bool *enabledP);
+    virtual ble_error_t areUpdatesEnabled(Gap::Handle_t connectionHandle, const GattCharacteristic &characteristic, bool *enabledP);
+
+    virtual bool isOnDataReadAvailable() const { return true; }
+
+private:
+    static void cccCback(attsCccEvt_t *pEvt);
+    static void attCback(attEvt_t *pEvt);
+    static uint8_t attsReadCback(dmConnId_t connId, uint16_t handle, uint8_t operation, uint16_t offset, attsAttr_t *pAttr);
+    static uint8_t attsWriteCback(dmConnId_t connId, uint16_t handle, uint8_t operation, uint16_t offset, uint16_t len, uint8_t *pValue, attsAttr_t *pAttr);
+
+    /*! client characteristic configuration descriptors settings */
+    #define MAX_CCC_CNT 20
+    attsCccSet_t cccSet[MAX_CCC_CNT];
+    uint16_t cccValues[MAX_CCC_CNT];
+    uint16_t cccHandles[MAX_CCC_CNT];
+    uint8_t cccCnt;
+
+private:
+    MaximGattServer() : GattServer(), cccSet(), cccValues(), cccHandles(), cccCnt(0) {
+        /* empty */
+    }
+
+    MaximGattServer(const MaximGattServer &);
+    const MaximGattServer& operator=(const MaximGattServer &);
+};
+
+#endif /* _MAXIM_GATT_SERVER_H_ */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/MaximSecurityManager.h b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximSecurityManager.h
new file mode 100644
index 00000000000..b6f06189f07
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/MaximSecurityManager.h
@@ -0,0 +1,55 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MAXIM_SECURITY_MANAGER_H_
+#define _MAXIM_SECURITY_MANAGER_H_
+
+#include <stddef.h>
+
+#include "ble/SecurityManager.h"
+
+class MaximSecurityManager : public SecurityManager
+{
+public:
+    static MaximSecurityManager &getInstance() {
+        static MaximSecurityManager m_instance;
+        return m_instance;
+    }
+
+public:
+    MaximSecurityManager() {
+        /* empty */
+    }
+};
+
+#endif /* _MAXIM_SECURITY_MANAGER_H_ */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/LES-PRE-20767-ARM-Permissive-Binary-License.txt b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/LES-PRE-20767-ARM-Permissive-Binary-License.txt
new file mode 100644
index 00000000000..7830ef04fd0
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/LES-PRE-20767-ARM-Permissive-Binary-License.txt
@@ -0,0 +1,49 @@
+Permissive Binary License
+
+Copyright (c) 2016, ARM, Ltd. All rights reserved.
+
+Redistribution.  Redistribution and use in binary form, without
+modification, are permitted provided that the following conditions are
+met:
+
+1) Redistributions must reproduce the above copyright notice and the
+   following disclaimer in the documentation and/or other materials
+   provided with the distribution.
+
+2) Unless to the extent explicitly permitted by law, no reverse
+   engineering, decompilation, or disassembly of this software is
+   permitted.
+
+3) Redistribution as part of a software development kit must include the
+   accompanying file named �DEPENDENCIES� and any dependencies listed in
+   that file.
+
+4) Neither the name of the copyright holder nor the names of its
+   contributors may be used to endorse or promote products derived from
+   this software without specific prior written permission.
+
+Limited patent license. The copyright holders (and contributors) grant a
+worldwide, non-exclusive, no-charge, royalty-free patent license to
+make, have made, use, offer to sell, sell, import, and otherwise
+transfer this software, where such license applies only to those patent
+claims licensable by the copyright holders (and contributors) that are
+necessarily infringed by this software. This patent license shall not
+apply to any combinations that include this software.  No hardware is
+licensed hereunder.
+
+If you institute patent litigation against any entity (including a
+cross-claim or counterclaim in a lawsuit) alleging that the software
+itself infringes your patent(s), then your rights granted under this
+license shall terminate as of the date such litigation is filed.
+
+DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
+NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\ No newline at end of file
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/hci/maxwsn/hci_drv.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/hci/maxwsn/hci_drv.h
new file mode 100644
index 00000000000..6623cc1755c
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/hci/maxwsn/hci_drv.h
@@ -0,0 +1,114 @@
+/*************************************************************************************************/
+/*!
+ *  \file   hci_drv.h
+ *
+ *  \brief  HCI driver interface.
+ *
+ *          $Date: 2013-01-02 22:19:17 -0800 (Wed, 02 Jan 2013) $
+ *          $Revision: 405 $
+ *
+ *  Copyright (c) 2012-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef HCI_DRV_H
+#define HCI_DRV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "PinNames.h"
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     hciDrvInit
+ *
+ *  \brief  Initialize the driver.
+ *
+ *  \param  csn      name of the pin connected to CSN
+ *  \param  irq      name of the pin conntected to IRQ
+ */
+/*************************************************************************************************/
+void hciDrvInit(PinName csn, PinName rst, PinName irq);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     hciDrvWrite
+ *
+ *  \brief  Write data to the driver.
+ *
+ *  \param  type     HCI packet type
+ *  \param  len      Number of bytes to write.
+ *  \param  pData    Byte array to write.
+ *
+ *  \return Return actual number of data bytes written.
+ *
+ *  \note   The type parameter allows the driver layer to prepend the data with a header on the
+ *          same write transaction.
+ */
+/*************************************************************************************************/
+uint16_t hciDrvWrite(uint8_t type, uint16_t len, uint8_t *pData);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     hciDrvRead
+ *
+ *  \brief  Read data bytes from the driver.
+ *
+ *  \param  len      Number of bytes to read.
+ *  \param  pData    Byte array to store data.
+ *
+ *  \return Return actual number of data bytes read.
+ */
+/*************************************************************************************************/
+uint16_t hciDrvRead(uint16_t len, uint8_t *pData, bool_t last);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     hciDrvIsr
+ *
+ *  \brief  Interrupt service routine for IRQ
+ */
+/*************************************************************************************************/
+void hciDrvIsr(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     hciDrvReadyToSleep
+ *
+ *  \brief  Returns TRUE if driver allows MCU to enter low power sleep mode.
+ *
+ *  \return TRUE if ready to sleep, FALSE otherwise.
+ */
+/*************************************************************************************************/
+bool_t hciDrvReadyToSleep(void);
+
+void hciDrvResume(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     hciDrvReset
+ *
+ *  \brief  Resets the controller
+ */
+/*************************************************************************************************/
+void hciDrvReset(void);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* HCI_DRV_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/hci/maxwsn/hci_vs.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/hci/maxwsn/hci_vs.h
new file mode 100644
index 00000000000..36abb15f13b
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/hci/maxwsn/hci_vs.h
@@ -0,0 +1,59 @@
+/*************************************************************************************************/
+/*!
+ *  \file   hci_drv.h
+ *
+ *  \brief  HCI vendor specific functions for EM Microelectronic.
+ *
+ *          $Date: 2013-01-02 22:19:17 -0800 (Wed, 02 Jan 2013) $
+ *          $Revision: 405 $
+ *
+ *  Copyright (c) 2012-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef HCI_VS_H
+#define HCI_VS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*************************************************************************************************/
+/*!
+ *  \fn     HciVsSetPublicAddr
+ *        
+ *  \brief  Vendor-specific set public address function.
+ *
+ *  \param  param    public address
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void HciVsSetPublicAddr(uint8_t *bdAddr);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     HciVsSetTxPower
+ *        
+ *  \brief  Vendor-specific set RF output power function
+ *
+ *  \param  param    output power in dB
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void HciVsSetTxPower(int txPower);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* HCI_VS_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/cfg/cfg_stack.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/cfg/cfg_stack.h
new file mode 100644
index 00000000000..3055a8ca077
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/cfg/cfg_stack.h
@@ -0,0 +1,71 @@
+/*************************************************************************************************/
+/*!
+ *  \file   cfg_stack.h
+ *
+ *  \brief  Stack configuration.
+ *
+ *          $Date: 2011-10-14 21:35:03 -0700 (Fri, 14 Oct 2011) $
+ *          $Revision: 191 $
+ *
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+
+ */
+/*************************************************************************************************/
+#ifndef CFG_STACK_H
+#define CFG_STACK_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  HCI
+**************************************************************************************************/
+
+/*! Vendor specific targets */
+#define HCI_VS_GENERIC        0
+#define HCI_VS_EMM            1
+
+/*! Vendor specific target configuration */
+#ifndef HCI_VS_TARGET
+#define HCI_VS_TARGET HCI_VS_GENERIC
+#endif
+
+/**************************************************************************************************
+  DM
+**************************************************************************************************/
+
+/*! Maximum number of connections */
+#ifndef DM_CONN_MAX
+#define DM_CONN_MAX 3
+#endif
+
+/**************************************************************************************************
+  L2C
+**************************************************************************************************/
+
+/**************************************************************************************************
+  ATT
+**************************************************************************************************/
+
+/**************************************************************************************************
+  SMP
+**************************************************************************************************/
+
+
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* CFG_STACK_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_api.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_api.h
new file mode 100644
index 00000000000..9b455f8d4c6
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_api.h
@@ -0,0 +1,942 @@
+/*************************************************************************************************/
+/*!
+ *  \file   att_api.h
+ *        
+ *  \brief  Attribute protocol client and server API.
+ *
+ *          $Date: 2012-05-07 19:54:28 -0700 (Mon, 07 May 2012) $
+ *          $Revision: 315 $
+ *  
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef ATT_API_H
+#define ATT_API_H
+
+#include "wsf_timer.h"
+#include "att_defs.h"
+#include "att_uuid.h"
+#include "dm_api.h"
+#include "cfg_stack.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/*! ATT server attribute settings */
+#define ATTS_SET_UUID_128           0x01    /*! Set if the UUID is 128 bits in length */
+#define ATTS_SET_WRITE_CBACK        0x02    /*! Set if the group callback is executed when
+                                                this attribute is written by a client device */
+#define ATTS_SET_READ_CBACK         0x04    /*! Set if the group callback is executed when
+                                                this attribute is read by a client device */
+#define ATTS_SET_VARIABLE_LEN       0x08    /*! Set if the attribute has a variable length */
+#define ATTS_SET_ALLOW_OFFSET       0x10    /*! Set if writes are allowed with an offset */
+#define ATTS_SET_CCC                0x20    /*! Set if the attribute is a client characteristic
+                                                configuration descriptor */
+#define ATTS_SET_ALLOW_SIGNED       0x40    /*! Set if signed writes are allowed */
+#define ATTS_SET_REQ_SIGNED         0x80    /*! Set if signed writes are required if link
+                                                is not encrypted */
+                                               
+/*! ATT server attribute permissions */
+#define ATTS_PERMIT_READ            0x01    /*! Set if attribute can be read */
+#define ATTS_PERMIT_READ_AUTH       0x02    /*! Set if attribute read requires authentication */
+#define ATTS_PERMIT_READ_AUTHORIZ   0x04    /*! Set if attribute read requires authorization */
+#define ATTS_PERMIT_READ_ENC        0x08    /*! Set if attribute read requires encryption */
+#define ATTS_PERMIT_WRITE           0x10    /*! Set if attribute can be written */
+#define ATTS_PERMIT_WRITE_AUTH      0x20    /*! Set if attribute write requires authentication */
+#define ATTS_PERMIT_WRITE_AUTHORIZ  0x40    /*! Set if attribute write requires authorization */
+#define ATTS_PERMIT_WRITE_ENC       0x80    /*! Set if attribute write requires encryption */
+
+/*! ATT client characteristic discovery and configuration settings */
+#define ATTC_SET_UUID_128           0x01    /*! Set if the UUID is 128 bits in length */
+#define ATTC_SET_REQUIRED           0x02    /*! Set if characteristic must be discovered */
+#define ATTC_SET_DESCRIPTOR         0x04    /*! Set if this is a characteristic descriptor */
+
+/*! ATT callback events */
+#define ATT_CBACK_START             0x02    /*! ATT callback event starting value */
+enum                                        /*! Internal note: event values match method values */
+{
+  /*! ATT client callback events */
+  ATTC_FIND_INFO_RSP = ATT_CBACK_START,     /*! Find information response */
+  ATTC_FIND_BY_TYPE_VALUE_RSP,              /*! Find by type value response */
+  ATTC_READ_BY_TYPE_RSP,                    /*! Read by type value response */
+  ATTC_READ_RSP,                            /*! Read response */
+  ATTC_READ_LONG_RSP,                       /*! Read long response */
+  ATTC_READ_MULTIPLE_RSP,                   /*! Read multiple response */
+  ATTC_READ_BY_GROUP_TYPE_RSP,              /*! Read group type response */
+  ATTC_WRITE_RSP,                           /*! Write response */
+  ATTC_WRITE_CMD_RSP,                       /*! Write command response */
+  ATTC_PREPARE_WRITE_RSP,                   /*! Prepare write response */
+  ATTC_EXECUTE_WRITE_RSP,                   /*! Execute write response */
+  ATTC_HANDLE_VALUE_NTF,                    /*! Handle value notification */
+  ATTC_HANDLE_VALUE_IND,                    /*! Handle value indication */
+  /*! ATT server callback events */
+  ATTS_HANDLE_VALUE_CNF,                    /*! Handle value confirmation */
+  ATTS_CCC_STATE_IND                        /*! Client chracteristic configuration state change */
+};
+
+/*! ATT callback events */
+#define ATT_CBACK_END               ATTS_CCC_STATE_IND  /*! ATT callback event ending value */
+
+/*! Base value for HCI error status values passed through ATT */
+#define ATT_HCI_ERR_BASE            0x20
+
+/**************************************************************************************************
+  Data Types
+**************************************************************************************************/
+
+/*! Configurable parameters */
+typedef struct
+{
+  wsfTimerTicks_t   discIdleTimeout;  /*! ATT server service discovery connection idle timeout in seconds */
+  uint16_t          mtu;              /*! desired ATT MTU */
+  uint8_t           transTimeout;     /*! transcation timeout in seconds */
+  uint8_t           numPrepWrites;    /*! number of queued prepare writes supported by server */
+} attCfg_t;
+
+/*!
+ * Attribute server data types
+ */
+  
+/*! Attribute structure */
+typedef struct
+{
+  uint8_t const     *pUuid;           /*! Pointer to the attribute�s UUID */
+  uint8_t           *pValue;          /*! Pointer to the attribute�s value */
+  uint16_t          *pLen;            /*! Pointer to the length of the attribute�s value */
+  uint16_t          maxLen;           /*! Maximum length of attribute�s value */
+  uint8_t           settings;         /*! Attribute settings */
+  uint8_t           permissions;      /*! Attribute permissions */
+} attsAttr_t;
+
+/*! Attribute group read callback */
+typedef uint8_t (*attsReadCback_t)(dmConnId_t connId, uint16_t handle, uint8_t operation,
+                                   uint16_t offset, attsAttr_t *pAttr);
+
+/*! Attribute group write callback */
+typedef uint8_t (*attsWriteCback_t)(dmConnId_t connId, uint16_t handle, uint8_t operation,
+                                    uint16_t offset, uint16_t len, uint8_t *pValue,
+                                    attsAttr_t *pAttr);
+
+/*! Attribute group */
+typedef struct attsGroup_tag
+{
+  struct attsGroup_tag  *pNext;       /*! For internal use only */
+  attsAttr_t            *pAttr;       /*! Pointer to attribute list for this group */
+  attsReadCback_t       readCback;    /*! Read callback function */
+  attsWriteCback_t      writeCback;   /*! Write callback function */
+  uint16_t              startHandle;  /*! The handle of the first attribute in this group */
+  uint16_t              endHandle;    /*! The handle of the last attribute in this group */
+} attsGroup_t;
+
+/*! Client characteristc configuration settings */
+typedef struct
+{
+  uint16_t          handle;           /*! Client characteristc configuration descriptor handle */
+  uint16_t          valueRange;       /*! Acceptable value range of the descriptor value */
+  uint8_t           secLevel;         /*! Security level of characteristic value */ 
+} attsCccSet_t;
+
+/*! ATT client structure for characteristic and descriptor discovery */
+typedef struct attcDiscChar_tag
+{
+  uint8_t const           *pUuid;       /*! Pointer to UUID */
+  uint8_t                 settings;     /*! Characteristic discovery settings */
+} attcDiscChar_t;
+
+/*! ATT client structure for characteristic and descriptor configuration */
+typedef struct
+{
+  uint8_t const         *pValue;      /*! Pointer to default value or NULL */
+  uint8_t               valueLen;     /*! Default value length */
+  uint8_t               hdlIdx;       /*! Index of its handle in handle list */
+} attcDiscCfg_t;
+
+/*! ATT client discovery control block */
+typedef struct
+{
+  attcDiscChar_t        **pCharList;  /*! Characterisic list for discovery */
+  uint16_t              *pHdlList;    /*! Characteristic handle list */
+  attcDiscCfg_t         *pCfgList;    /*! Characterisic list for configuration */
+  uint8_t               charListLen;  /*! Characteristic and handle list length */
+  uint8_t               cfgListLen;   /*! Configuration list length */
+  
+  /* the following are for internal use only */
+  uint16_t              svcStartHdl;
+  uint16_t              svcEndHdl;  
+  uint8_t               charListIdx;
+  uint8_t               endHdlIdx;  
+} attcDiscCb_t;
+
+/*!
+ * ATT callback parameters:
+ *
+ * \param hdr.event     Callback event
+ * \param hdr.param     DM connection ID
+ * \param hdr.status    Event status:  ATT_SUCCESS or error status
+ * \param pValue        Pointer to value data, valid if valueLen > 0
+ * \param valueLen      Length of value data
+ * \param handle        Attribute handle
+ */
+typedef struct
+{
+  wsfMsgHdr_t           hdr;          /*! Header structure */
+  uint8_t               *pValue;      /*! Value */
+  uint16_t              valueLen;     /*! Value length */
+  uint16_t              handle;       /*! Attribute handle */
+  bool_t                continuing;   /*! TRUE if more response packets expected */
+} attEvt_t;
+
+/*! ATTS client characteristic configuration callback structure */
+typedef struct
+{
+  wsfMsgHdr_t           hdr;          /*! Header structure */
+  uint16_t              handle;       /*! CCCD handle */
+  uint16_t              value;        /*! CCCD value */
+  uint8_t               idx;          /*! CCCD settings index */
+} attsCccEvt_t;
+
+/*! ATT callback type */
+typedef void (*attCback_t)(attEvt_t *pEvt);
+
+/*! ATTS authorization callback type */
+typedef uint8_t (*attsAuthorCback_t)(dmConnId_t connId, uint8_t permit, uint16_t handle);
+
+/*! ATTS client characteristic configuration callback */
+typedef void (*attsCccCback_t)(attsCccEvt_t *pEvt);
+
+/**************************************************************************************************
+  Global Variables
+**************************************************************************************************/
+
+/*! Configuration pointer */
+extern attCfg_t *pAttCfg;
+                                                          
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttRegister
+ *        
+ *  \brief  Register a callback with ATT.
+ *
+ *  \param  cback  Client callback function.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttRegister(attCback_t cback);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttConnRegister
+ *        
+ *  \brief  Register a connection callback with ATT.  The callback is typically used to
+ *          manage the attribute server database.
+ *
+ *  \param  cback  Client callback function.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttConnRegister(dmCback_t cback);
+
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttGetMtu
+ *        
+ *  \brief  Get the attribute protocol MTU of a connection.
+ *
+ *  \param  connId    DM connection ID.
+ *
+ *  \return MTU of the connection.
+ */
+/*************************************************************************************************/
+uint16_t AttGetMtu(dmConnId_t connId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsInit
+ *        
+ *  \brief  Initialize ATT server.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsIndInit
+ *        
+ *  \brief  Initialize ATT server for indications/notifications.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsIndInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsSignInit
+ *        
+ *  \brief  Initialize ATT server for data signing.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsSignInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsAuthorRegister
+ *        
+ *  \brief  Register an authorization callback with the attribute server.
+ *
+ *  \param  cback  Client callback function.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsAuthorRegister(attsAuthorCback_t cback);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsAddGroup
+ *        
+ *  \brief  Add an attribute group to the attribute server.
+ *
+ *  \param  pGroup    Pointer to an attribute group structure.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsAddGroup(attsGroup_t *pGroup);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsRemoveGroup
+ *        
+ *  \brief  Remove an attribute group from the attribute server.
+ *
+ *  \param  startHandle  Start handle of attribute group to be removed.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsRemoveGroup(uint16_t startHandle);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsSetAttr
+ *        
+ *  \brief  Set an attribute value in the attribute server.
+ *
+ *  \param  handle    Attribute handle.
+ *  \param  valueLen  Attribute length.
+ *  \param  pValue    Attribute value.
+ *
+ *  \return ATT_SUCCESS if successful otherwise error.
+ */
+/*************************************************************************************************/
+uint8_t AttsSetAttr(uint16_t handle, uint16_t valueLen, uint8_t *pValue);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsGetAttr
+ *        
+ *  \brief  Get an attribute value in the attribute server.
+ *
+ *  \param  handle    Attribute handle.
+ *  \param  pLen      Returned attribute length pointer.
+ *  \param  pValue    Returned attribute value pointer.
+ *
+ *  \return ATT_SUCCESS if successful otherwise error.
+ *  \return This function returns the attribute length in pLen and a pointer to the attribute
+ *          value in pValue.
+ */
+/*************************************************************************************************/
+uint8_t AttsGetAttr(uint16_t handle, uint16_t *pLen, uint8_t **pValue);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsHandleValueInd
+ *        
+ *  \brief  Send an attribute protocol Handle Value Indication.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  handle      Attribute handle. 
+ *  \param  valueLen    Length of value data.
+ *  \param  pValue      Pointer to value data.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsHandleValueInd(dmConnId_t connId, uint16_t handle, uint16_t valueLen, uint8_t *pValue);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsHandleValueNtf
+ *        
+ *  \brief  Send an attribute protocol Handle Value Notification.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  handle      Attribute handle. 
+ *  \param  valueLen    Length of value data.
+ *  \param  pValue      Pointer to value data.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsHandleValueNtf(dmConnId_t connId, uint16_t handle, uint16_t valueLen, uint8_t *pValue);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsCccRegister
+ *        
+ *  \brief  Register the utility service for managing client characteristic
+ *          configuration descriptors.  This function is typically called once on
+ *          system initialization.
+ *
+ *  \param  setLen  Length of settings array.
+ *  \param  pSet    Array of CCC descriptor settings.
+ *  \param  cback   Client callback function.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsCccRegister(uint8_t setLen, attsCccSet_t *pSet, attsCccCback_t cback);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsCccInitTable
+ *        
+ *  \brief  Initialize the client characteristic configuration descriptor value table for a
+ *          connection.  The table is initialized with the values from pCccTbl.  If pCccTbl
+ *          is NULL the table will be initialized to zero.
+ * 
+ *          This function must be called when a connection is established or when a
+ *          device is bonded.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  pCccTbl     Pointer to the descriptor value array.  The length of the array
+ *                      must equal the value of setLen passed to AttsCccRegister().
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsCccInitTable(dmConnId_t connId, uint16_t *pCccTbl);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsCccClearTable
+ *        
+ *  \brief  Clear and deallocate the client characteristic configuration descriptor value
+ *          table for a connection.  This function must be called when a connection is closed.
+ *
+ *  \param  connId      DM connection ID.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsCccClearTable(dmConnId_t connId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsCccGet
+ *        
+ *  \brief  Get the value of a client characteristic configuration descriptor by its index.
+ *          If not found, return zero.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  idx         Index of descriptor in CCC descriptor handle table. 
+ *
+ *  \return Value of the descriptor.
+ */
+/*************************************************************************************************/
+uint16_t AttsCccGet(dmConnId_t connId, uint8_t idx);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsCccSet
+ *        
+ *  \brief  Set the value of a client characteristic configuration descriptor by its index.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  idx         Index of descriptor in CCC descriptor handle table. 
+ *  \param  value       Value of the descriptor. 
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsCccSet(dmConnId_t connId, uint8_t idx, uint16_t value);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsCccEnabled
+ *        
+ *  \brief  Check if a client characteristic configuration descriptor is enabled and if
+ *          the characteristic's security level has been met.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  idx         Index of descriptor in CCC descriptor handle table. 
+ *
+ *  \return Value of the descriptor if security level is met, otherwise zero.
+ */
+/*************************************************************************************************/
+uint16_t AttsCccEnabled(dmConnId_t connId, uint8_t idx);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsSetCsrk
+ *        
+ *  \brief  Set the peer's data signing key on this connection.  This function
+ *          is typically called from the ATT connection callback when the connection is
+ *          established.  The caller is responsible for maintaining the memory that
+ *          contains the key.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  pCsrk       Pointer to data signing key (CSRK). 
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsSetCsrk(dmConnId_t connId, uint8_t *pCsrk);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsSetSignCounter
+ *        
+ *  \brief  Set the peer's sign counter on this connection.  This function
+ *          is typically called from the ATT connection callback when the connection is
+ *          established.  ATT maintains the value of the sign counter internally and
+ *          sets the value when a signed packet is successfully received.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  signCounter Sign counter. 
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsSetSignCounter(dmConnId_t connId, uint32_t signCounter);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsGetSignCounter
+ *        
+ *  \brief  Get the current value peer's sign counter on this connection.  This function
+ *          is typically called from the ATT connection callback when the connection is
+ *          closed so the application can store the sign counter for use on future
+ *          connections.
+ *
+ *  \param  connId      DM connection ID.
+ *
+ *  \return Sign counter.
+ */
+/*************************************************************************************************/
+uint32_t AttsGetSignCounter(dmConnId_t connId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcInit
+ *        
+ *  \brief  Initialize ATT client.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcSignInit
+ *        
+ *  \brief  Initialize ATT client for data signing.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcSignInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcFindInfoReq
+ *        
+ *  \brief  Initiate an attribute protocol Find Information Request.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  startHandle Attribute start handle. 
+ *  \param  endHandle   Attribute end handle. 
+ *  \param  continuing  TRUE if ATTC continues sending requests until complete.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcFindInfoReq(dmConnId_t connId, uint16_t startHandle, uint16_t endHandle, bool_t continuing);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcFindByTypeValueReq
+ *        
+ *  \brief  Initiate an attribute protocol Find By Type Value Request.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  startHandle Attribute start handle. 
+ *  \param  endHandle   Attribute end handle. 
+ *  \param  uuid16      16-bit UUID to find.
+ *  \param  valueLen    Length of value data.
+ *  \param  pValue      Pointer to value data.
+ *  \param  continuing  TRUE if ATTC continues sending requests until complete.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcFindByTypeValueReq(dmConnId_t connId, uint16_t startHandle, uint16_t endHandle,
+                            uint16_t uuid16, uint16_t valueLen, uint8_t *pValue, bool_t continuing);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcReadByTypeReq
+ *        
+ *  \brief  Initiate an attribute protocol Read By Type Request.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  startHandle Attribute start handle. 
+ *  \param  endHandle   Attribute end handle. 
+ *  \param  uuidLen     Length of UUID (2 or 16).
+ *  \param  pUuid       Pointer to UUID data.
+ *  \param  continuing  TRUE if ATTC continues sending requests until complete.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcReadByTypeReq(dmConnId_t connId, uint16_t startHandle, uint16_t endHandle,
+                       uint8_t uuidLen, uint8_t *pUuid, bool_t continuing);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcReadReq
+ *        
+ *  \brief  Initiate an attribute protocol Read Request.
+ *
+ *  \param  connId    DM connection ID.
+ *  \param  handle    Attribute handle.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcReadReq(dmConnId_t connId, uint16_t handle);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcReadLongReq
+ *        
+ *  \brief  Initiate an attribute protocol Read Long Request.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  handle      Attribute handle.
+ *  \param  offset      Read attribute data starting at this offset.
+ *  \param  continuing  TRUE if ATTC continues sending requests until complete.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcReadLongReq(dmConnId_t connId, uint16_t handle, uint16_t offset, bool_t continuing);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcReadMultipleReq
+ *        
+ *  \brief  Initiate an attribute protocol Read Multiple Request.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  numHandles  Number of handles in attribute handle list.
+ *  \param  pHandles    List of attribute handles.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcReadMultipleReq(dmConnId_t connId, uint8_t numHandles, uint16_t *pHandles);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcReadByGroupTypeReq
+ *        
+ *  \brief  Initiate an attribute protocol Read By Group Type Request.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  startHandle Attribute start handle. 
+ *  \param  endHandle   Attribute end handle. 
+ *  \param  uuidLen     Length of UUID (2 or 16).
+ *  \param  pUuid       Pointer to UUID data.
+ *  \param  continuing  TRUE if ATTC continues sending requests until complete.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcReadByGroupTypeReq(dmConnId_t connId, uint16_t startHandle, uint16_t endHandle,
+                            uint8_t uuidLen, uint8_t *pUuid, bool_t continuing);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcWriteReq
+ *        
+ *  \brief  Initiate an attribute protocol Write Request.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  handle      Attribute handle. 
+ *  \param  valueLen    Length of value data.
+ *  \param  pValue      Pointer to value data.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcWriteReq(dmConnId_t connId, uint16_t handle, uint16_t valueLen, uint8_t *pValue);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcWriteCmd
+ *        
+ *  \brief  Initiate an attribute protocol Write Command.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  handle      Attribute handle. 
+ *  \param  valueLen    Length of value data.
+ *  \param  pValue      Pointer to value data.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcWriteCmd(dmConnId_t connId, uint16_t handle, uint16_t valueLen, uint8_t *pValue);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcSignedWriteCmd
+ *        
+ *  \brief  Initiate an attribute protocol signed Write Command.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  handle      Attribute handle. 
+ *  \param  signCounter Value of the sign counter.
+ *  \param  valueLen    Length of value data.
+ *  \param  pValue      Pointer to value data.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcSignedWriteCmd(dmConnId_t connId, uint16_t handle, uint32_t signCounter,
+                        uint16_t valueLen, uint8_t *pValue);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcPrepareWriteReq
+ *        
+ *  \brief  Initiate an attribute protocol Prepare Write Request.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  handle      Attribute handle. 
+ *  \param  offset      Write attribute data starting at this offset.
+ *  \param  valueLen    Length of value data.
+ *  \param  pValue      Pointer to value data.
+ *  \param  valueByRef  TRUE if pValue data is accessed by reference rather than copied.
+ *  \param  continuing  TRUE if ATTC continues sending requests until complete.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcPrepareWriteReq(dmConnId_t connId, uint16_t handle, uint16_t offset, uint16_t valueLen,
+                         uint8_t *pValue, bool_t valueByRef, bool_t continuing);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcExecuteWriteReq
+ *        
+ *  \brief  Initiate an attribute protocol Execute Write Request.
+ *
+ *  \param  connId    DM connection ID.
+ *  \param  writeAll  TRUE to write all queued writes, FALSE to cancel all queued writes.    
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcExecuteWriteReq(dmConnId_t connId, bool_t writeAll);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcCancelReq
+ *        
+ *  \brief  Cancel an attribute protocol request in progress.
+ *
+ *  \param  connId    DM connection ID.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcCancelReq(dmConnId_t connId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcDiscService
+ *        
+ *  \brief  This utility function discovers the given service on a peer device.  Function
+ *          AttcFindByTypeValueReq() is called to initiate the discovery procedure.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  pCb         Pointer to discovery control block.
+ *  \param  uuidLen     Length of service UUID (2 or 16).
+ *  \param  pUuid       Pointer to service UUID.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcDiscService(dmConnId_t connId, attcDiscCb_t *pCb, uint8_t uuidLen, uint8_t *pUuid);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcDiscServiceCmpl
+ *        
+ *  \brief  This utility function processes a service discovery result.  It should be called
+ *          when an ATTC_FIND_BY_TYPE_VALUE_RSP callback event is received after service
+ *          discovery is initiated by calling AttcDiscService().
+ *
+ *  \param  pCb         Pointer to discovery control block.
+ *  \param  pMsg        ATT callback event message.
+ *
+ *  \return ATT_SUCCESS if successful otherwise error.
+ */
+/*************************************************************************************************/
+uint8_t AttcDiscServiceCmpl(attcDiscCb_t *pCb, attEvt_t *pMsg);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcDiscCharStart
+ *        
+ *  \brief  This utility function starts characteristic and characteristic descriptor
+ *          discovery for a service on a peer device.  The service must have been previously
+ *          discovered by calling AttcDiscService() and AttcDiscServiceCmpl().
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  pCb         Pointer to discovery control block.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcDiscCharStart(dmConnId_t connId, attcDiscCb_t *pCb);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcDiscCharCmpl
+ *        
+ *  \brief  This utility function processes a characteristic discovery result.  It should be
+ *          called when an ATTC_READ_BY_TYPE_RSP or ATTC_FIND_INFO_RSP callback event is 
+ *          received after characteristic discovery is initiated by calling AttcDiscCharStart().
+ *
+ *  \param  pCb         Pointer to discovery control block.
+ *  \param  pMsg        ATT callback event message.
+ *
+ *  \return ATT_CONTINUING if successful and the discovery procedure is continuing.
+ *          ATT_SUCCESS if the discovery procedure completed successfully.
+ *          Otherwise the discovery procedure failed.
+ */
+/*************************************************************************************************/
+uint8_t AttcDiscCharCmpl(attcDiscCb_t *pCb, attEvt_t *pMsg);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcDiscConfigStart
+ *        
+ *  \brief  This utility function starts characteristic configuration for characteristics on a
+ *          peer device.  The characteristics must have been previously discovered by calling
+ *          AttcDiscCharStart() and AttcDiscCharCmpl().
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  pCb         Pointer to discovery control block.
+ *
+ *  \return ATT_CONTINUING if successful and configuration procedure is continuing.
+ *          ATT_SUCCESS if nothing to configure.
+ */
+/*************************************************************************************************/
+uint8_t AttcDiscConfigStart(dmConnId_t connId, attcDiscCb_t *pCb);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcDiscConfigCmpl
+ *        
+ *  \brief  This utility function initiates the next characteristic configuration procedure.
+ *          It should be called when an ATTC_READ_RSP or ATTC_WRITE_RSP callback event is received
+ *          after characteristic configuration is initiated by calling AttcDiscConfigStart().
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  pCb         Pointer to discovery control block.
+ *
+ *  \return ATT_CONTINUING if successful and configuration procedure is continuing.
+ *          ATT_SUCCESS if configuration procedure completed successfully.
+ */
+/*************************************************************************************************/
+uint8_t AttcDiscConfigCmpl(dmConnId_t connId, attcDiscCb_t *pCb);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcDiscConfigResume
+ *        
+ *  \brief  This utility function resumes the characteristic configuration procedure.  It can
+ *          be called when an ATTC_READ_RSP or ATTC_WRITE_RSP callback event is received
+ *          with failure status to attempt the read or write procedure again.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  pCb         Pointer to discovery control block.
+ *
+ *  \return ATT_CONTINUING if successful and configuration procedure is continuing.
+ *          ATT_SUCCESS if configuration procedure completed successfully.
+ */
+/*************************************************************************************************/
+uint8_t AttcDiscConfigResume(dmConnId_t connId, attcDiscCb_t *pCb);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttcMtuReq
+ *        
+ *  \brief  For internal use only.
+ *
+ *  \param  connId    DM connection ID.
+ *  \param  mtu       Attribute protocol MTU.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttcMtuReq(dmConnId_t connId, uint16_t mtu);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttsErrorTest
+ *        
+ *  \brief  For testing purposes only.
+ *
+ *  \param  status    ATT status
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttsErrorTest(uint8_t status);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* ATT_API_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_defs.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_defs.h
new file mode 100644
index 00000000000..0146a064b91
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_defs.h
@@ -0,0 +1,221 @@
+/*************************************************************************************************/
+/*!
+ *  \file   att_defs.h
+ *        
+ *  \brief  Attribute protocol constants and definitions from the Bluetooth specification.
+ *
+ *          $Date: 2012-09-11 16:18:57 -0700 (Tue, 11 Sep 2012) $
+ *          $Revision: 349 $
+ *  
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef ATT_DEFS_H
+#define ATT_DEFS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/*! Attribute PDU format */
+#define ATT_HDR_LEN                   1         /*! Attribute PDU header length */
+#define ATT_AUTH_SIG_LEN              12        /*! Authentication signature length */
+#define ATT_DEFAULT_MTU               23        /*! Default value of ATT_MTU */
+#define ATT_MAX_MTU                   517       /*! Maximum value of ATT_MTU */
+#define ATT_DEFAULT_PAYLOAD_LEN       20        /*! Default maximum payload length for most PDUs */
+
+/*! Attribute value parameters */
+#define ATT_VALUE_MAX_LEN             512       /*! Maximum attribute value length */
+#define ATT_VALUE_MAX_OFFSET          511       /*! Maximum attribute value offset */
+
+/*! Transaction timeout */
+#define ATT_MAX_TRANS_TIMEOUT         30        /*! Maximum transaction timeout in seconds */
+
+/*! Error codes */
+#define ATT_SUCCESS                   0x00      /*! Operation successful */
+#define ATT_ERR_HANDLE                0x01      /*! Invalid handle */
+#define ATT_ERR_READ                  0x02      /*! Read not permitted */
+#define ATT_ERR_WRITE                 0x03      /*! Write not permitted */
+#define ATT_ERR_INVALID_PDU           0x04      /*! Invalid pdu */
+#define ATT_ERR_AUTH                  0x05      /*! Insufficient authentication */
+#define ATT_ERR_NOT_SUP               0x06      /*! Request not supported */
+#define ATT_ERR_OFFSET                0x07      /*! Invalid offset */
+#define ATT_ERR_AUTHOR                0x08      /*! Insufficient authorization */
+#define ATT_ERR_QUEUE_FULL            0x09      /*! Prepare queue full */
+#define ATT_ERR_NOT_FOUND             0x0A      /*! Attribute not found */
+#define ATT_ERR_NOT_LONG              0x0B      /*! Attribute not long */
+#define ATT_ERR_KEY_SIZE              0x0C      /*! Insufficient encryption key size */
+#define ATT_ERR_LENGTH                0x0D      /*! Invalid attribute value length */
+#define ATT_ERR_UNLIKELY              0x0E      /*! Other unlikely error */
+#define ATT_ERR_ENC                   0x0F      /*! Insufficient encryption */
+#define ATT_ERR_GROUP_TYPE            0x10      /*! Unsupported group type */
+#define ATT_ERR_RESOURCES             0x11      /*! Insufficient resources */
+#define ATT_ERR_CCCD                  0xFD      /*! CCCD improperly configured */
+#define ATT_ERR_IN_PROGRESS           0xFE      /*! Procedure already in progress */
+#define ATT_ERR_RANGE                 0xFF      /*! Value out of range */
+
+/*! Proprietary internal error codes */
+#define ATT_ERR_MEMORY                0x70      /*! Out of memory */
+#define ATT_ERR_TIMEOUT               0x71      /*! Transaction timeout */
+#define ATT_ERR_OVERFLOW              0x72      /*! Transaction overflow */
+#define ATT_ERR_INVALID_RSP           0x73      /*! Invalid response PDU */
+#define ATT_ERR_CANCELLED             0x74      /*! Request cancelled */
+#define ATT_ERR_UNDEFINED             0x75      /*! Other undefined error */
+#define ATT_ERR_REQ_NOT_FOUND         0x76      /*! Required characteristic not found */
+#define ATT_CONTINUING                0x77      /*! Procedure continuing */
+
+/*! Application error codes */
+#define ATT_ERR_VALUE_RANGE           0x80      /*! Value out of range */
+
+/*! PDU types */
+#define ATT_PDU_ERR_RSP               0x01      /*! Error response */
+#define ATT_PDU_MTU_REQ               0x02      /*! Exchange mtu request */
+#define ATT_PDU_MTU_RSP               0x03      /*! Exchange mtu response */
+#define ATT_PDU_FIND_INFO_REQ         0x04      /*! Find information request */
+#define ATT_PDU_FIND_INFO_RSP         0x05      /*! Find information response */
+#define ATT_PDU_FIND_TYPE_REQ         0x06      /*! Find by type value request */
+#define ATT_PDU_FIND_TYPE_RSP         0x07      /*! Find by type value response */
+#define ATT_PDU_READ_TYPE_REQ         0x08      /*! Read by type request */
+#define ATT_PDU_READ_TYPE_RSP         0x09      /*! Read by type response */
+#define ATT_PDU_READ_REQ              0x0A      /*! Read request */
+#define ATT_PDU_READ_RSP              0x0B      /*! Read response */
+#define ATT_PDU_READ_BLOB_REQ         0x0C      /*! Read blob request */
+#define ATT_PDU_READ_BLOB_RSP         0x0D      /*! Read blob response */
+#define ATT_PDU_READ_MULT_REQ         0x0E      /*! Read multiple request */
+#define ATT_PDU_READ_MULT_RSP         0x0F      /*! Read multiple response */
+#define ATT_PDU_READ_GROUP_TYPE_REQ   0x10      /*! Read by group type request */
+#define ATT_PDU_READ_GROUP_TYPE_RSP   0x11      /*! Read by group type response */
+#define ATT_PDU_WRITE_REQ             0x12      /*! Write request */
+#define ATT_PDU_WRITE_RSP             0x13      /*! Write response */
+#define ATT_PDU_WRITE_CMD             0x52      /*! Write command */
+#define ATT_PDU_SIGNED_WRITE_CMD      0xD2      /*! Signed write command */
+#define ATT_PDU_PREP_WRITE_REQ        0x16      /*! Prepare write request */
+#define ATT_PDU_PREP_WRITE_RSP        0x17      /*! Prepare write response */
+#define ATT_PDU_EXEC_WRITE_REQ        0x18      /*! Execute write request */
+#define ATT_PDU_EXEC_WRITE_RSP        0x19      /*! Execute write response */
+#define ATT_PDU_VALUE_NTF             0x1B      /*! Handle value notification */
+#define ATT_PDU_VALUE_IND             0x1D      /*! Handle value indication */
+#define ATT_PDU_VALUE_CNF             0x1E      /*! Handle value confirmation */
+#define ATT_PDU_MAX                   0x1F      /*! PDU Maximum */
+
+/*! Length of PDU fixed length fields */
+#define ATT_ERR_RSP_LEN               5
+#define ATT_MTU_REQ_LEN               3
+#define ATT_MTU_RSP_LEN               3
+#define ATT_FIND_INFO_REQ_LEN         5
+#define ATT_FIND_INFO_RSP_LEN         2
+#define ATT_FIND_TYPE_REQ_LEN         7
+#define ATT_FIND_TYPE_RSP_LEN         1
+#define ATT_READ_TYPE_REQ_LEN         5
+#define ATT_READ_TYPE_RSP_LEN         2
+#define ATT_READ_REQ_LEN              3
+#define ATT_READ_RSP_LEN              1
+#define ATT_READ_BLOB_REQ_LEN         5
+#define ATT_READ_BLOB_RSP_LEN         1
+#define ATT_READ_MULT_REQ_LEN         1
+#define ATT_READ_MULT_RSP_LEN         1
+#define ATT_READ_GROUP_TYPE_REQ_LEN   5
+#define ATT_READ_GROUP_TYPE_RSP_LEN   2
+#define ATT_WRITE_REQ_LEN             3
+#define ATT_WRITE_RSP_LEN             1
+#define ATT_WRITE_CMD_LEN             3
+#define ATT_SIGNED_WRITE_CMD_LEN      (ATT_WRITE_CMD_LEN + ATT_AUTH_SIG_LEN)
+#define ATT_PREP_WRITE_REQ_LEN        5
+#define ATT_PREP_WRITE_RSP_LEN        5
+#define ATT_EXEC_WRITE_REQ_LEN        2
+#define ATT_EXEC_WRITE_RSP_LEN        1
+#define ATT_VALUE_NTF_LEN             3
+#define ATT_VALUE_IND_LEN             3
+#define ATT_VALUE_CNF_LEN             1
+
+/*! Find information response format */
+#define ATT_FIND_HANDLE_16_UUID       0x01      /*! Handle and 16 bit UUID */
+#define ATT_FIND_HANDLE_128_UUID      0x02      /*! Handle and 128 bit UUID */
+
+/*! Execute write request flags */
+#define ATT_EXEC_WRITE_CANCEL         0x00      /*! Cancel all prepared writes */
+#define ATT_EXEC_WRITE_ALL            0x01      /*! Write all pending prepared writes */
+
+/*! PDU masks */
+#define ATT_PDU_MASK_SERVER           0x01      /*! Server bit mask */
+#define ATT_PDU_MASK_COMMAND          0x40      /*! Command bit mask */
+#define ATT_PDU_MASK_SIGNED           0x80      /*! Auth signature bit mask */
+
+/*! Handles */
+#define ATT_HANDLE_NONE               0x0000
+#define ATT_HANDLE_START              0x0001
+#define ATT_HANDLE_MAX                0xFFFF
+
+/*! UUID lengths */
+#define ATT_NO_UUID_LEN               0         /*! Length when no UUID is present ;-) */
+#define ATT_16_UUID_LEN               2         /*! Length in bytes of a 16 bit UUID */
+#define ATT_128_UUID_LEN              16        /*! Length in bytes of a 128 bit UUID */
+
+/*! GATT characteristic properties */
+#define ATT_PROP_BROADCAST            0x01      /*! Permit broadcasts */
+#define ATT_PROP_READ                 0x02      /*! Permit reads */
+#define ATT_PROP_WRITE_NO_RSP         0x04      /*! Permit writes without response */
+#define ATT_PROP_WRITE                0x08      /*! Permit writes with response */
+#define ATT_PROP_NOTIFY               0x10      /*! Permit notifications */
+#define ATT_PROP_INDICATE             0x20      /*! Permit indications */
+#define ATT_PROP_AUTHENTICATED        0x40      /*! Permit signed writes */
+#define ATT_PROP_EXTENDED             0x80      /*! More properties defined in extended properties */
+
+/*! GATT characteristic extended properties */
+#define ATT_EXT_PROP_RELIABLE_WRITE   0x0001    /*! Permit reliable writes */
+#define ATT_EXT_PROP_WRITEABLE_AUX    0x0002    /*! Permit write to characteristic descriptor */
+
+/*! GATT client characteristic configuration */
+#define ATT_CLIENT_CFG_NOTIFY         0x0001    /*! Notify the value */
+#define ATT_CLIENT_CFG_INDICATE       0x0002    /*! Indicate the value */
+
+/*! GATT server characteristic configuration */
+#define ATT_SERVER_CFG_BROADCAST      0x0001    /*! Broadcast the value */
+
+/*! GATT characteristic format */
+#define ATT_FORMAT_BOOLEAN            0x01      /*! Boolean */
+#define ATT_FORMAT_2BIT               0x02      /*! Unsigned 2 bit integer */
+#define ATT_FORMAT_NIBBLE             0x03      /*! Unsigned 4 bit integer */
+#define ATT_FORMAT_UINT8              0x04      /*! Unsigned 8 bit integer */
+#define ATT_FORMAT_UINT12             0x05      /*! Unsigned 12 bit integer */
+#define ATT_FORMAT_UINT16             0x06      /*! Unsigned 16 bit integer */
+#define ATT_FORMAT_UINT24             0x07      /*! Unsigned 24 bit integer */
+#define ATT_FORMAT_UINT32             0x08      /*! Unsigned 32 bit integer */
+#define ATT_FORMAT_UINT48             0x09      /*! Unsigned 48 bit integer */
+#define ATT_FORMAT_UINT64             0x0A      /*! Unsigned 64 bit integer */
+#define ATT_FORMAT_UINT128            0x0B      /*! Unsigned 128 bit integer */
+#define ATT_FORMAT_SINT8              0x0C      /*! Signed 8 bit integer */
+#define ATT_FORMAT_SINT12             0x0D      /*! Signed 12 bit integer */
+#define ATT_FORMAT_SINT16             0x0E      /*! Signed 16 bit integer */
+#define ATT_FORMAT_SINT24             0x0F      /*! Signed 24 bit integer */
+#define ATT_FORMAT_SINT32             0x10      /*! Signed 32 bit integer */
+#define ATT_FORMAT_SINT48             0x11      /*! Signed 48 bit integer */
+#define ATT_FORMAT_SINT64             0x12      /*! Signed 64 bit integer */
+#define ATT_FORMAT_SINT128            0x13      /*! Signed 128 bit integer */
+#define ATT_FORMAT_FLOAT32            0x14      /*! IEEE-754 32 bit floating point */
+#define ATT_FORMAT_FLOAT64            0x15      /*! IEEE-754 64 bit floating point */
+#define ATT_FORMAT_SFLOAT             0x16      /*! IEEE-11073 16 bit SFLOAT */
+#define ATT_FORMAT_FLOAT              0x17      /*! IEEE-11073 32 bit FLOAT */
+#define ATT_FORMAT_DUINT16            0x18      /*! IEEE-20601 format */
+#define ATT_FORMAT_UTF8               0x19      /*! UTF-8 string */
+#define ATT_FORMAT_UTF16              0x1A      /*! UTF-16 string */
+#define ATT_FORMAT_STRUCT             0x1B      /*! Opaque structure */
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* ATT_DEFS_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_handler.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_handler.h
new file mode 100644
index 00000000000..4c2bf5ae551
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_handler.h
@@ -0,0 +1,67 @@
+/*************************************************************************************************/
+/*!
+ *  \file   att_handler.h
+ *
+ *  \brief  Interface to ATT event handler.
+ *
+ *          $Date: 2012-03-29 13:24:04 -0700 (Thu, 29 Mar 2012) $
+ *          $Revision: 287 $
+ *
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef ATT_HANDLER_H
+#define ATT_HANDLER_H
+
+#include "wsf_os.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttHandlerInit
+ *        
+ *  \brief  ATT handler init function called during system initialization.
+ *
+ *  \param  handlerID  WSF handler ID for ATT.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttHandlerInit(wsfHandlerId_t handlerId);
+
+
+/*************************************************************************************************/
+/*!
+ *  \fn     AttHandler
+ *        
+ *  \brief  WSF event handler for ATT.
+ *
+ *  \param  event   WSF event mask.
+ *  \param  pMsg    WSF message.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void AttHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* ATT_HANDLER_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_uuid.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_uuid.h
new file mode 100644
index 00000000000..0e08d20209b
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/att_uuid.h
@@ -0,0 +1,431 @@
+/*************************************************************************************************/
+/*!
+ *  \file   att_uuid.h
+ *        
+ *  \brief  Attribute protocol UUIDs from the Bluetooth specification.
+ *
+ *          $Date: 2014-08-11 17:41:56 -0500 (Mon, 11 Aug 2014) $
+ *          $Revision: 14613 $
+ *  
+ *  Copyright (c) 2011-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef ATT_UUID_H
+#define ATT_UUID_H
+
+#include "att_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/*! Service UUIDs */
+#define ATT_UUID_GAP_SERVICE                0x1800    /*! Generic Access Profile Service */
+#define ATT_UUID_GATT_SERVICE               0x1801    /*! Generic Attribute Profile Service */
+#define ATT_UUID_IMMEDIATE_ALERT_SERVICE    0x1802    /*! Immediate Alert Service */
+#define ATT_UUID_LINK_LOSS_SERVICE          0x1803    /*! Link Loss Service */
+#define ATT_UUID_TX_POWER_SERVICE           0x1804    /*! Tx Power Service */
+#define ATT_UUID_CURRENT_TIME_SERVICE       0x1805    /*! Current Time Service */
+#define ATT_UUID_REF_TIME_UPDATE_SERVICE    0x1806    /*! Reference Time Update Service */
+#define ATT_UUID_DST_CHANGE_SERVICE         0x1807    /*! Next DST Change Service */
+#define ATT_UUID_GLUCOSE_SERVICE            0x1808    /*! Glucose Service */
+#define ATT_UUID_HEALTH_THERM_SERVICE       0x1809    /*! Health Thermometer Service */
+#define ATT_UUID_DEVICE_INFO_SERVICE        0x180A    /*! Device Information Service */
+#define ATT_UUID_NETWORK_AVAIL_SERVICE      0x180B    /*! Network Availability Service */
+#define ATT_UUID_WATCHDOG_SERVICE           0x180C    /*! Watchdog Service */
+#define ATT_UUID_HEART_RATE_SERVICE         0x180D    /*! Heart Rate Service */
+#define ATT_UUID_PHONE_ALERT_SERVICE        0x180E    /*! Phone Alert Status Service */
+#define ATT_UUID_BATTERY_SERVICE            0x180F    /*! Battery Service */
+#define ATT_UUID_BLOOD_PRESSURE_SERVICE     0x1810    /*! Blood Pressure Service */
+#define ATT_UUID_ALERT_NOTIF_SERVICE        0x1811    /*! Alert Notification Service */
+#define ATT_UUID_HID_SERVICE                0x1812    /*! Human Interface Device Service */
+#define ATT_UUID_SCAN_PARAM_SERVICE         0x1813    /*! Scan Parameter Service */
+#define ATT_UUID_WEIGHT_SCALE_SERVICE       0x181D    /*! Weight Scale Service */
+
+/*! GATT UUIDs */
+#define ATT_UUID_PRIMARY_SERVICE            0x2800    /*! Primary Service */
+#define ATT_UUID_SECONDARY_SERVICE          0x2801    /*! Secondary Service */
+#define ATT_UUID_INCLUDE                    0x2802    /*! Include */
+#define ATT_UUID_CHARACTERISTIC             0x2803    /*! Characteristic */
+
+/*! Descriptor UUIDs */
+#define ATT_UUID_CHARACTERISTIC_EXT         0x2900    /*! Characteristic Extended Properties */
+#define ATT_UUID_CHAR_USER_DESC             0x2901    /*! Characteristic User Description */
+#define ATT_UUID_CLIENT_CHAR_CONFIG         0x2902    /*! Client Characteristic Configuration */
+#define ATT_UUID_SERVER_CHAR_CONFIG         0x2903    /*! Server Characteristic Configuration */
+#define ATT_UUID_CHAR_PRES_FORMAT           0x2904    /*! Characteristic Presentation Format */
+#define ATT_UUID_AGGREGATE_FORMAT           0x2905    /*! Characteristic Aggregate Format */
+#define ATT_UUID_VALID_RANGE                0x2906    /*! Valid Range */
+#define ATT_UUID_HID_REPORT_ID_MAPPING      0x2908    /*! HID Report ID Mapping */
+
+/*! Characteristic UUIDs */
+#define ATT_UUID_DEVICE_NAME                0x2A00    /*! Device Name */
+#define ATT_UUID_APPEARANCE                 0x2A01    /*! Appearance */
+#define ATT_UUID_PERIPH_PRIVACY_FLAG        0x2A02    /*! Peripheral Privacy Flag */
+#define ATT_UUID_RECONN_ADDR                0x2A03    /*! Reconnection Address */
+#define ATT_UUID_PREF_CONN_PARAM            0x2A04    /*! Peripheral Preferred Connection Parameters */
+#define ATT_UUID_SERVICE_CHANGED            0x2A05    /*! Service Changed */
+#define ATT_UUID_ALERT_LEVEL                0x2A06    /*! Alert Level */
+#define ATT_UUID_TX_POWER_LEVEL             0x2A07    /*! Tx Power Level */
+#define ATT_UUID_DATE_TIME                  0x2A08    /*! Date Time */
+#define ATT_UUID_DAY_OF_WEEK                0x2A09    /*! Day of Week */
+#define ATT_UUID_DAY_DATE_TIME              0x2A0A    /*! Day Date Time */
+#define ATT_UUID_EXACT_TIME_100             0x2A0B    /*! Exact Time 100 */
+#define ATT_UUID_EXACT_TIME_256             0x2A0C    /*! Exact Time 256 */
+#define ATT_UUID_DST_OFFSET                 0x2A0D    /*! DST Offset */
+#define ATT_UUID_TIME_ZONE                  0x2A0E    /*! Time Zone */
+#define ATT_UUID_LOCAL_TIME_INFO            0x2A0F    /*! Local Time Information */
+#define ATT_UUID_SECONDARY_TIME_ZONE        0x2A10    /*! Secondary Time Zone */
+#define ATT_UUID_TIME_WITH_DST              0x2A11    /*! Time with DST */
+#define ATT_UUID_TIME_ACCURACY              0x2A12    /*! Time Accuracy */
+#define ATT_UUID_TIME_SOURCE                0x2A13    /*! Time Source */
+#define ATT_UUID_REFERENCE_TIME_INFO        0x2A14    /*! Reference Time Information */
+#define ATT_UUID_TIME_BROADCAST             0x2A15    /*! Time Broadcast */
+#define ATT_UUID_TIME_UPDATE_CP             0x2A16    /*! Time Update Control Point */
+#define ATT_UUID_TIME_UPDATE_STATE          0x2A17    /*! Time Update State */
+#define ATT_UUID_GLUCOSE_MEAS               0x2A18    /*! Glucose Measurement */
+#define ATT_UUID_BATTERY_LEVEL              0x2A19    /*! Battery Level */
+#define ATT_UUID_BATTERY_POWER_STATE        0x2A1A    /*! Battery Power State */
+#define ATT_UUID_BATTERY_LEVEL_STATE        0x2A1B    /*! Battery Level State */
+#define ATT_UUID_TEMP_MEAS                  0x2A1C    /*! Temperature Measurement */
+#define ATT_UUID_TEMP_TYPE                  0x2A1D    /*! Temperature Type */
+#define ATT_UUID_INTERMEDIATE_TEMP          0x2A1E    /*! Intermediate Temperature */
+#define ATT_UUID_TEMP_C                     0x2A1F    /*! Temperature Celsius */
+#define ATT_UUID_TEMP_F                     0x2A20    /*! Temperature Fahrenheit */
+#define ATT_UUID_MEAS_INTERVAL              0x2A21    /*! Measurement Interval */
+#define ATT_UUID_HID_BOOT_REPORT_MAP        0x2A22    /*! HID Boot Report Mapping */
+#define ATT_UUID_SYSTEM_ID                  0x2A23    /*! System ID */
+#define ATT_UUID_MODEL_NUMBER               0x2A24    /*! Model Number String */
+#define ATT_UUID_SERIAL_NUMBER              0x2A25    /*! Serial Number String */
+#define ATT_UUID_FIRMWARE_REV               0x2A26    /*! Firmware Revision String */
+#define ATT_UUID_HARDWARE_REV               0x2A27    /*! Hardware Revision String */
+#define ATT_UUID_SOFTWARE_REV               0x2A28    /*! Software Revision String */
+#define ATT_UUID_MANUFACTURER_NAME          0x2A29    /*! Manufacturer Name String */
+#define ATT_UUID_11073_CERT_DATA            0x2A2A    /*! IEEE 11073-20601 Regulatory Certification Data List */
+#define ATT_UUID_CURRENT_TIME               0x2A2B    /*! Current Time */
+#define ATT_UUID_ELEVATION                  0x2A2C    /*! Elevation */
+#define ATT_UUID_LATITUDE                   0x2A2D    /*! Latitude */
+#define ATT_UUID_LONGITUDE                  0x2A2E    /*! Longitude */
+#define ATT_UUID_POSITION_2D                0x2A2F    /*! Position 2D */
+#define ATT_UUID_POSITION_3D                0x2A30    /*! Position 3D */
+#define ATT_UUID_VENDOR_ID                  0x2A31    /*! Vendor ID */
+#define ATT_UUID_PRODUCT_ID                 0x2A32    /*! Product ID */
+#define ATT_UUID_HID_VERSION                0x2A33    /*! HID Version */
+#define ATT_UUID_GLUCOSE_MEAS_CONTEXT       0x2A34    /*! Glucose Measurement Context */
+#define ATT_UUID_BP_MEAS                    0x2A35    /*! Blood Pressure Measurement */
+#define ATT_UUID_INTERMEDIATE_BP            0x2A36    /*! Intermediate Cuff Pressure */
+#define ATT_UUID_HR_MEAS                    0x2A37    /*! Heart Rate Measurement */
+#define ATT_UUID_HR_SENSOR_LOC              0x2A38    /*! Body Sensor Location */
+#define ATT_UUID_HR_CP                      0x2A39    /*! Heart Rate Control Point */
+#define ATT_UUID_REMOVABLE                  0x2A3A    /*! Removable */
+#define ATT_UUID_SERVICE_REQ                0x2A3B    /*! Service Required */
+#define ATT_UUID_SCI_TEMP_C                 0x2A3C    /*! Scientific Temperature in Celsius */
+#define ATT_UUID_STRING                     0x2A3D    /*! String */
+#define ATT_UUID_NETWORK_AVAIL              0x2A3E    /*! Network Availability */
+#define ATT_UUID_ALERT_STATUS               0x2A3F    /*! Alert Status */
+#define ATT_UUID_RINGER_CP                  0x2A40    /*! Ringer Control Point */
+#define ATT_UUID_RINGER_SETTING             0x2A41    /*! Ringer Setting */
+#define ATT_UUID_ALERT_CAT_ID_MASK          0x2A42    /*! Alert Category ID Bit Mask */
+#define ATT_UUID_ALERT_CAT_ID               0x2A43    /*! Alert Category ID */
+#define ATT_UUID_ALERT_NOTIF_CP             0x2A44    /*! Alert Notification Control Point */
+#define ATT_UUID_UNREAD_ALERT_STATUS        0x2A45    /*! Unread Alert Status */
+#define ATT_UUID_NEW_ALERT                  0x2A46    /*! New Alert */
+#define ATT_UUID_SUP_NEW_ALERT_CAT          0x2A47    /*! Supported New Alert Category */
+#define ATT_UUID_SUP_UNREAD_ALERT_CAT       0x2A48    /*! Supported Unread Alert Category */
+#define ATT_UUID_BP_FEATURE                 0x2A49    /*! Blood Pressure Feature */
+#define ATT_UUID_HID_INFO                   0x2A4A    /*! HID Information */            
+#define ATT_UUID_REPORT_MAP                 0x2A4B    /*! Report Map */                
+#define ATT_UUID_HID_CP                     0x2A4C    /*! HID Control Point */          
+#define ATT_UUID_REPORT                     0x2A4D    /*! Report */                    
+#define ATT_UUID_PROTOCOL_MODE              0x2A4E    /*! Protocol Mode */              
+#define ATT_UUID_SCAN_INT_WIND              0x2A4F    /*! Scan Interval Window */       
+#define ATT_UUID_PNP_ID                     0x2A50    /*! PnP ID */                     
+#define ATT_UUID_GLUCOSE_FEATURE            0x2A51    /*! Glucose Feature */            
+#define ATT_UUID_RACP                       0x2A52    /*! Record Access Control Point */
+#define ATT_UUID_WEIGHT_MEAS                0x2A9D    /*! Weight Measurement */
+#define ATT_UUID_WEIGHT_SCALE_FEATURE       0x2A9E    /*! Weight Scale Feature */
+
+/* remove when adopted */
+#define ATT_UUID_GENERIC_CTRL_SERVICE       0xF011
+#define ATT_UUID_COMMAND_ENUM               0xE010    /*! Command Enumeration */
+#define ATT_UUID_GENERIC_COMMAND_CP         0xE011    /*! Generic Command Control Point */
+
+/*! Unit UUIDs */
+#define ATT_UUID_UNITLESS                   0x2700    /*! unitless */
+#define ATT_UUID_LENGTH_M                   0x2701    /*! length metre */
+#define ATT_UUID_MASS_KG                    0x2702    /*! mass kilogram */
+#define ATT_UUID_TIME_SEC                   0x2703    /*! time second */
+#define ATT_UUID_ELECTRIC_CURRENT_AMP       0x2704    /*! electric current ampere */
+#define ATT_UUID_THERMO_TEMP_K              0x2705    /*! thermodynamic temperature kelvin */
+#define ATT_UUID_AMOUNT_OF_SUBSTANCE_MOLE   0x2706    /*! amount of substance mole */
+#define ATT_UUID_LUMINOUS_INTENSITY_CAND    0x2707    /*! luminous intensity candela */
+#define ATT_UUID_AREA_SQ_M                  0x2710    /*! area square metres */
+#define ATT_UUID_VOLUME_CU_M                0x2711    /*! volume cubic metres */
+#define ATT_UUID_VELOCITY_MPS               0x2712    /*! velocity metres per second */
+#define ATT_UUID_ACCELERATION_MPS_SQ        0x2713    /*! acceleration metres per second squared */
+#define ATT_UUID_WAVENUMBER_RECIPROCAL_M    0x2714    /*! wavenumber reciprocal metre */
+#define ATT_UUID_DENSITY_KG_PER_CU_M        0x2715    /*! density kilogram per cubic metre */
+#define ATT_UUID_SURFACE_DENS_KG_PER_SQ_M   0x2716    /*! surface density kilogram per square metre */
+#define ATT_UUID_SPECIFIC_VOL_CU_M_PER_KG   0x2717    /*! specific volume cubic metre per kilogram */
+#define ATT_UUID_CURRENT_DENS_AMP_PER_SQ_M  0x2718    /*! current density ampere per square metre */
+#define ATT_UUID_MAG_FIELD_STR_AMP_PER_M    0x2719    /*! magnetic field strength ampere per metre */
+#define ATT_UUID_AMOUNT_CONC_MOLE_PER_CU_M  0x271A    /*! amount concentration mole per cubic metre */
+#define ATT_UUID_MASS_CONC_KG_PER_CU_M      0x271B    /*! mass concentration kilogram per cubic metre */
+#define ATT_UUID_LUM_CAND_PER_SQ_M          0x271C    /*! luminance candela per square metre */
+#define ATT_UUID_REFRACTIVE_INDEX           0x271D    /*! refractive index */
+#define ATT_UUID_RELATIVE_PERMEABILITY      0x271E    /*! relative permeability */
+#define ATT_UUID_PLANE_ANGLE_R              0x2720    /*! plane angle radian */
+#define ATT_UUID_SOLID_ANGLE_STER           0x2721    /*! solid angle steradian */
+#define ATT_UUID_FREQUENCY_HERTZ            0x2722    /*! frequency hertz */
+#define ATT_UUID_FORCE_NEWT                 0x2723    /*! force newton */
+#define ATT_UUID_PRESSURE_PASCAL            0x2724    /*! pressure pascal */
+#define ATT_UUID_ENERGY_J                   0x2725    /*! energy joule */
+#define ATT_UUID_POWER_W                    0x2726    /*! power watt */
+#define ATT_UUID_ELECTRIC_CHG_C             0x2727    /*! electric charge coulomb */
+#define ATT_UUID_ELECTRIC_POTENTIAL_VOLT    0x2728    /*! electric potential difference volt */
+#define ATT_UUID_CAPACITANCE_F              0x2729    /*! capacitance farad */
+#define ATT_UUID_ELECTRIC_RESISTANCE_OHM    0x272A    /*! electric resistance ohm */
+#define ATT_UUID_ELECTRIC_COND_SIEMENS      0x272B    /*! electric conductance siemens */
+#define ATT_UUID_MAGNETIC_FLEX_WEBER        0x272C    /*! magnetic flex weber */
+#define ATT_UUID_MAGNETIC_FLEX_DENS_TESLA   0x272D    /*! magnetic flex density tesla */
+#define ATT_UUID_INDUCTANCE_H               0x272E    /*! inductance henry */
+#define ATT_UUID_C_TEMP_DEG_C               0x272F    /*! Celsius temperature degree Celsius */
+#define ATT_UUID_LUMINOUS_FLUX_LUMEN        0x2730    /*! luminous flux lumen */
+#define ATT_UUID_ILLUMINANCE_LUX            0x2731    /*! illuminance lux */
+#define ATT_UUID_RADIONUCLIDE_BECQUEREL     0x2732    /*! activity referred to a radionuclide becquerel */
+#define ATT_UUID_ABSORBED_DOSE_GRAY         0x2733    /*! absorbed dose gray */
+#define ATT_UUID_DOSE_EQUIVALENT_SIEVERT    0x2734    /*! dose equivalent sievert */
+#define ATT_UUID_CATALYTIC_ACTIVITY_KATAL   0x2735    /*! catalytic activity katal */
+#define ATT_UUID_DYNAMIC_VISC_PASCAL_SEC    0x2740    /*! dynamic viscosity pascal second */
+#define ATT_UUID_MOMENT_OF_FORCE_NEWT_M     0x2741    /*! moment of force newton metre */
+#define ATT_UUID_SURFACE_TENSION_NEWT_PER_M 0x2742    /*! surface tension newton per metre */
+#define ATT_UUID_ANG_VELOCITY_R_PER_SEC     0x2743    /*! angular velocity radian per second */
+#define ATT_UUID_ANG_ACCEL_R_PER_SEC_SQD    0x2744    /*! angular acceleration radian per second squared */
+#define ATT_UUID_HEAT_FLUX_DEN_W_PER_SQ_M   0x2745    /*! heat flux density watt per square metre */
+#define ATT_UUID_HEAT_CAP_J_PER_K           0x2746    /*! heat capacity joule per kelvin */
+#define ATT_UUID_SPEC_HEAT_CAP_J_PER_KG_K   0x2747    /*! specific heat capacity joule per kilogram kelvin */
+#define ATT_UUID_SPEC_ENERGY_J_PER_KG       0x2748    /*! specific energy joule per kilogram */
+#define ATT_UUID_THERMAL_COND_W_PER_M_K     0x2749    /*! thermal conductivity watt per metre kelvin */
+#define ATT_UUID_ENERGY_DENSITY_J_PER_CU_M  0x274A    /*! energy density joule per cubic metre */
+#define ATT_UUID_ELEC_FIELD_STR_VOLT_PER_M  0x274B    /*! electric field strength volt per metre */
+#define ATT_UUID_ELEC_CHG_DENS_C_PER_CU_M   0x274C    /*! electric charge density coulomb per cubic metre */
+#define ATT_UUID_SURF_CHG_DENS_C_PER_SQ_M   0x274D    /*! surface charge density coulomb per square metre */
+#define ATT_UUID_ELEC_FLUX_DENS_C_PER_SQ_M  0x274E    /*! electric flux density coulomb per square metre */
+#define ATT_UUID_PERMITTIVITY_F_PER_M       0x274F    /*! permittivity farad per metre */
+#define ATT_UUID_PERMEABILITY_H_PER_M       0x2750    /*! permeability henry per metre */
+#define ATT_UUID_MOLAR_ENERGY_J_PER_MOLE    0x2751    /*! molar energy joule per mole */
+#define ATT_UUID_MOLAR_ENTROPY_J_PER_MOLE_K 0x2752    /*! molar entropy joule per mole kelvin */
+#define ATT_UUID_EXPOSURE_C_PER_KG          0x2753    /*! exposure coulomb per kilogram */
+#define ATT_UUID_DOSE_RATE_GRAY_PER_SEC     0x2754    /*! absorbed dose rate gray per second */
+#define ATT_UUID_RT_INTENSITY_W_PER_STER    0x2755    /*! radiant intensity watt per steradian */
+#define ATT_UUID_RCE_W_PER_SQ_METER_STER    0x2756    /*! radiance watt per square meter steradian */
+#define ATT_UUID_CATALYTIC_KATAL_PER_CU_M   0x2757    /*! catalytic activity concentration katal per cubic metre */
+#define ATT_UUID_TIME_MIN                   0x2760    /*! time minute */
+#define ATT_UUID_TIME_HR                    0x2761    /*! time hour */
+#define ATT_UUID_TIME_DAY                   0x2762    /*! time day */
+#define ATT_UUID_PLANE_ANGLE_DEG            0x2763    /*! plane angle degree */
+#define ATT_UUID_PLANE_ANGLE_MIN            0x2764    /*! plane angle minute */
+#define ATT_UUID_PLANE_ANGLE_SEC            0x2765    /*! plane angle second */
+#define ATT_UUID_AREA_HECTARE               0x2766    /*! area hectare */
+#define ATT_UUID_VOLUME_L                   0x2767    /*! volume litre */
+#define ATT_UUID_MASS_TONNE                 0x2768    /*! mass tonne */
+#define ATT_UUID_PRESSURE_BAR               0x2780    /*! pressure bar */
+#define ATT_UUID_PRESSURE_MM                0x2781    /*! pressure millimetre of mercury */
+#define ATT_UUID_LENGTH_ANGSTROM            0x2782    /*! length angstrom */
+#define ATT_UUID_LENGTH_NAUTICAL_MILE       0x2783    /*! length nautical mile */
+#define ATT_UUID_AREA_BARN                  0x2784    /*! area barn */
+#define ATT_UUID_VELOCITY_KNOT              0x2785    /*! velocity knot */
+#define ATT_UUID_LOG_RADIO_QUANT_NEPER      0x2786    /*! logarithmic radio quantity neper */
+#define ATT_UUID_LOG_RADIO_QUANT_BEL        0x2787    /*! logarithmic radio quantity bel */
+#define ATT_UUID_LOG_RADIO_QUANT_DB         0x2788    /*! logarithmic radio quantity decibel */
+#define ATT_UUID_LENGTH_YARD                0x27A0    /*! length yard */
+#define ATT_UUID_LENGTH_PARSEC              0x27A1    /*! length parsec */
+#define ATT_UUID_LENGTH_IN                  0x27A2    /*! length inch */
+#define ATT_UUID_LENGTH_FOOT                0x27A3    /*! length foot */
+#define ATT_UUID_LENGTH_MILE                0x27A4    /*! length mile */
+#define ATT_UUID_PRESSURE_POUND_PER_SQ_IN   0x27A5    /*! pressure pound-force per square inch */
+#define ATT_UUID_VELOCITY_KPH               0x27A6    /*! velocity kilometre per hour */
+#define ATT_UUID_VELOCITY_MPH               0x27A7    /*! velocity mile per hour */
+#define ATT_UUID_ANG_VELOCITY_RPM           0x27A8    /*! angular velocity revolution per minute */
+#define ATT_UUID_ENERGY_GRAM_CALORIE        0x27A9    /*! energy gram calorie */
+#define ATT_UUID_ENERGY_KG_CALORIE          0x27AA    /*! energy kilogram calorie */
+#define ATT_UUID_ENERGY_KILOWATT_HR         0x27AB    /*! energy kilowatt hour */
+#define ATT_UUID_THERM_TEMP_F               0x27AC    /*! thermodynamic temperature degree Fahrenheit */
+#define ATT_UUID_PERCENTAGE                 0x27AD    /*! percentage */
+#define ATT_UUID_PER_MILLE                  0x27AE    /*! per mille */
+#define ATT_UUID_PERIOD_BEATS_PER_MIN       0x27AF    /*! period beats per minute */
+#define ATT_UUID_ELECTRIC_CHG_AMP_HRS       0x27B0    /*! electric charge ampere hours */
+#define ATT_UUID_MASS_DENSITY_MG_PER_DL     0x27B1    /*! mass density milligram per decilitre */
+#define ATT_UUID_MASS_DENSITY_MMOLE_PER_L   0x27B2    /*! mass density millimole per litre */
+#define ATT_UUID_TIME_YEAR                  0x27B3    /*! time year */
+#define ATT_UUID_TIME_MONTH                 0x27B4    /*! time month */
+
+/*! Wicentric proprietary UUIDs */
+
+/*! Base UUID:  E0262760-08C2-11E1-9073-0E8AC72EXXXX */
+#define ATT_UUID_WICENTRIC_BASE             0x2E, 0xC7, 0x8A, 0x0E, 0x73, 0x90, \
+                                            0xE1, 0x11, 0xC2, 0x08, 0x60, 0x27, 0x26, 0xE0
+
+/*! Macro for building Wicentric UUIDs */
+#define ATT_UUID_WICENTRIC_BUILD(part)      UINT16_TO_BYTES(part), ATT_UUID_WICENTRIC_BASE
+
+/*! Partial proprietary service UUIDs */
+#define ATT_UUID_P1_SERVICE_PART            0x1001   /*! Proprietary service P1 */
+
+/*! Partial proprietary characteristic UUIDs */
+#define ATT_UUID_D1_DATA_PART               0x0001    /*! Proprietary data D1 */
+
+/* Proprietary services */
+#define ATT_UUID_P1_SERVICE                 ATT_UUID_WICENTRIC_BUILD(ATT_UUID_P1_SERVICE_PART)
+
+/* Proprietary characteristics */
+#define ATT_UUID_D1_DATA                    ATT_UUID_WICENTRIC_BUILD(ATT_UUID_D1_DATA_PART)
+
+/**************************************************************************************************
+  Global Variables
+**************************************************************************************************/
+
+/*! Service UUIDs */
+extern const uint8_t attGapSvcUuid[ATT_16_UUID_LEN];     /*! Generic Access Profile Service */
+extern const uint8_t attGattSvcUuid[ATT_16_UUID_LEN];    /*! Generic Attribute Profile Service */
+extern const uint8_t attIasSvcUuid[ATT_16_UUID_LEN];     /*! Immediate Alert Service */
+extern const uint8_t attLlsSvcUuid[ATT_16_UUID_LEN];     /*! Link Loss Service */
+extern const uint8_t attTpsSvcUuid[ATT_16_UUID_LEN];     /*! Tx Power Service */
+extern const uint8_t attCtsSvcUuid[ATT_16_UUID_LEN];     /*! Current Time Service */
+extern const uint8_t attRtusSvcUuid[ATT_16_UUID_LEN];    /*! Reference Time Update Service */
+extern const uint8_t attNdcsSvcUuid[ATT_16_UUID_LEN];    /*! Next DST Change Service */
+extern const uint8_t attGlsSvcUuid[ATT_16_UUID_LEN];     /*! Glucose Service */
+extern const uint8_t attHtsSvcUuid[ATT_16_UUID_LEN];     /*! Health Thermometer Service */
+extern const uint8_t attDisSvcUuid[ATT_16_UUID_LEN];     /*! Device Information Service */
+extern const uint8_t attNwaSvcUuid[ATT_16_UUID_LEN];     /*! Network Availability Service */
+extern const uint8_t attWdsSvcUuid[ATT_16_UUID_LEN];     /*! Watchdog Service */
+extern const uint8_t attHrsSvcUuid[ATT_16_UUID_LEN];     /*! Heart Rate Service */
+extern const uint8_t attPassSvcUuid[ATT_16_UUID_LEN];    /*! Phone Alert Status Service */
+extern const uint8_t attBasSvcUuid[ATT_16_UUID_LEN];     /*! Battery Service */
+extern const uint8_t attBpsSvcUuid[ATT_16_UUID_LEN];     /*! Blood Pressure Service */
+extern const uint8_t attAnsSvcUuid[ATT_16_UUID_LEN];     /*! Alert Notification Service */
+extern const uint8_t attHidSvcUuid[ATT_16_UUID_LEN];     /*! Human Interface Device Service */
+extern const uint8_t attSpsSvcUuid[ATT_16_UUID_LEN];     /*! Scan Parameter Service */
+extern const uint8_t attWssSvcUuid[ATT_16_UUID_LEN];     /*! Weight scale service */
+
+/*! GATT UUIDs */
+extern const uint8_t attPrimSvcUuid[ATT_16_UUID_LEN];    /*! Primary Service */
+extern const uint8_t attSecSvcUuid[ATT_16_UUID_LEN];     /*! Secondary Service */
+extern const uint8_t attIncUuid[ATT_16_UUID_LEN];        /*! Include */
+extern const uint8_t attChUuid[ATT_16_UUID_LEN];         /*! Characteristic */
+                                                         
+/*! Descriptor UUIDs */                                  
+extern const uint8_t attChExtUuid[ATT_16_UUID_LEN];      /*! Characteristic Extended Properties */
+extern const uint8_t attChUserDescUuid[ATT_16_UUID_LEN]; /*! Characteristic User Description */
+extern const uint8_t attCliChCfgUuid[ATT_16_UUID_LEN];   /*! Client Characteristic Configuration */
+extern const uint8_t attSrvChCfgUuid[ATT_16_UUID_LEN];   /*! Server Characteristic Configuration */
+extern const uint8_t attChPresFmtUuid[ATT_16_UUID_LEN];  /*! Characteristic Presentation Format */
+extern const uint8_t attAggFmtUuid[ATT_16_UUID_LEN];     /*! Characteristic Aggregate Format */
+extern const uint8_t attValRangeUuid[ATT_16_UUID_LEN];   /*! Valid Range */
+extern const uint8_t attHidRimUuid[ATT_16_UUID_LEN];     /*! HID Report ID Mapping */
+
+/*! Characteristic UUIDs */
+extern const uint8_t attDnChUuid[ATT_16_UUID_LEN];       /*! Device Name */
+extern const uint8_t attApChUuid[ATT_16_UUID_LEN];       /*! Appearance */
+extern const uint8_t attPpfChUuid[ATT_16_UUID_LEN];      /*! Peripheral Privacy Flag */
+extern const uint8_t attRaChUuid[ATT_16_UUID_LEN];	     /*! Reconnection Address */
+extern const uint8_t attPpcpChUuid[ATT_16_UUID_LEN];     /*! Peripheral Preferred Connection Parameters */
+extern const uint8_t attScChUuid[ATT_16_UUID_LEN];       /*! Service Changed */
+extern const uint8_t attAlChUuid[ATT_16_UUID_LEN];       /*! Alert Level */
+extern const uint8_t attTxpChUuid[ATT_16_UUID_LEN];      /*! Tx Power Level */
+extern const uint8_t attDtChUuid[ATT_16_UUID_LEN];       /*! Date Time */
+extern const uint8_t attDwChUuid[ATT_16_UUID_LEN];       /*! Day of Week */
+extern const uint8_t attDdtChUuid[ATT_16_UUID_LEN];      /*! Day Date Time */
+extern const uint8_t attEt100ChUuid[ATT_16_UUID_LEN];    /*! Exact Time 100 */
+extern const uint8_t attEt256ChUuid[ATT_16_UUID_LEN];    /*! Exact Time 256 */
+extern const uint8_t attDstoChUuid[ATT_16_UUID_LEN];     /*! DST Offset */
+extern const uint8_t attTzChUuid[ATT_16_UUID_LEN];       /*! Time Zone */
+extern const uint8_t attLtiChUuid[ATT_16_UUID_LEN];      /*! Local Time Information */
+extern const uint8_t attStzChUuid[ATT_16_UUID_LEN];      /*! Secondary Time Zone */
+extern const uint8_t attTdstChUuid[ATT_16_UUID_LEN];     /*! Time with DST */
+extern const uint8_t attTaChUuid[ATT_16_UUID_LEN];       /*! Time Accuracy */
+extern const uint8_t attTsChUuid[ATT_16_UUID_LEN];       /*! Time Source */
+extern const uint8_t attRtiChUuid[ATT_16_UUID_LEN];      /*! Reference Time Information */
+extern const uint8_t attTbChUuid[ATT_16_UUID_LEN];       /*! Time Broadcast */
+extern const uint8_t attTucpChUuid[ATT_16_UUID_LEN];     /*! Time Update Control Point */
+extern const uint8_t attTusChUuid[ATT_16_UUID_LEN];      /*! Time Update State */
+extern const uint8_t attGlmChUuid[ATT_16_UUID_LEN];      /*! Glucose Measurement */
+extern const uint8_t attBlChUuid[ATT_16_UUID_LEN];       /*! Battery Level */
+extern const uint8_t attBpsChUuid[ATT_16_UUID_LEN];      /*! Battery Power State */
+extern const uint8_t attBlsChUuid[ATT_16_UUID_LEN];      /*! Battery Level State */
+extern const uint8_t attTmChUuid[ATT_16_UUID_LEN];       /*! Temperature Measurement */
+extern const uint8_t attTtChUuid[ATT_16_UUID_LEN];       /*! Temperature Type */
+extern const uint8_t attItChUuid[ATT_16_UUID_LEN];       /*! Intermediate Temperature */
+extern const uint8_t attTcelChUuid[ATT_16_UUID_LEN];     /*! Temperature Celsius */
+extern const uint8_t attTfahChUuid[ATT_16_UUID_LEN];     /*! Temperature Fahrenheit */
+extern const uint8_t attMiChUuid[ATT_16_UUID_LEN];       /*! Measurement Interval */
+extern const uint8_t attHbrpChUuid[ATT_16_UUID_LEN];     /*! HID Boot Report Mapping */
+extern const uint8_t attSidChUuid[ATT_16_UUID_LEN];      /*! System ID */
+extern const uint8_t attMnsChUuid[ATT_16_UUID_LEN];      /*! Model Number String */
+extern const uint8_t attSnsChUuid[ATT_16_UUID_LEN];      /*! Serial Number String */
+extern const uint8_t attFrsChUuid[ATT_16_UUID_LEN];      /*! Firmware Revision String */
+extern const uint8_t attHrsChUuid[ATT_16_UUID_LEN];      /*! Hardware Revision String */
+extern const uint8_t attSrsChUuid[ATT_16_UUID_LEN];      /*! Software Revision String */
+extern const uint8_t attMfnsChUuid[ATT_16_UUID_LEN];     /*! Manufacturer Name String */
+extern const uint8_t attIeeeChUuid[ATT_16_UUID_LEN];     /*! IEEE 11073-20601 Regulatory Certification Data List */
+extern const uint8_t attCtChUuid[ATT_16_UUID_LEN];       /*! Current Time */
+extern const uint8_t attElChUuid[ATT_16_UUID_LEN];       /*! Elevation */
+extern const uint8_t attLatChUuid[ATT_16_UUID_LEN];      /*! Latitude */
+extern const uint8_t attLongChUuid[ATT_16_UUID_LEN];     /*! Longitude */
+extern const uint8_t attP2dChUuid[ATT_16_UUID_LEN];      /*! Position 2D */
+extern const uint8_t attP3dChUuid[ATT_16_UUID_LEN];      /*! Position 3D */
+extern const uint8_t attVidChUuid[ATT_16_UUID_LEN];      /*! Vendor ID */
+extern const uint8_t attPidChUuid[ATT_16_UUID_LEN];      /*! Product ID */
+extern const uint8_t attHidvChUuid[ATT_16_UUID_LEN];     /*! HID Version */
+extern const uint8_t attGlmcChUuid[ATT_16_UUID_LEN];     /*! Glucose Measurement Context */
+extern const uint8_t attBpmChUuid[ATT_16_UUID_LEN];      /*! Blood Pressure Measurement */
+extern const uint8_t attIcpChUuid[ATT_16_UUID_LEN];      /*! Intermediate Cuff Pressure */
+extern const uint8_t attHrmChUuid[ATT_16_UUID_LEN];      /*! Heart Rate Measurement */
+extern const uint8_t attBslChUuid[ATT_16_UUID_LEN];      /*! Body Sensor Location */
+extern const uint8_t attHrcpChUuid[ATT_16_UUID_LEN];     /*! Heart Rate Control Point */
+extern const uint8_t attRemChUuid[ATT_16_UUID_LEN];      /*! Removable */
+extern const uint8_t attSrChUuid[ATT_16_UUID_LEN];       /*! Service Required */
+extern const uint8_t attStcChUuid[ATT_16_UUID_LEN];      /*! Scientific Temperature in Celsius */
+extern const uint8_t attStrChUuid[ATT_16_UUID_LEN];      /*! String */
+extern const uint8_t attNwaChUuid[ATT_16_UUID_LEN];      /*! Network Availability */
+extern const uint8_t attAsChUuid[ATT_16_UUID_LEN];       /*! Alert Status */
+extern const uint8_t attRcpChUuid[ATT_16_UUID_LEN];      /*! Ringer Control Point */
+extern const uint8_t attRsChUuid[ATT_16_UUID_LEN];       /*! Ringer Setting */
+extern const uint8_t attAcbmChUuid[ATT_16_UUID_LEN];     /*! Alert Category ID Bit Mask */
+extern const uint8_t attAcChUuid[ATT_16_UUID_LEN];       /*! Alert Category ID */
+extern const uint8_t attAncpChUuid[ATT_16_UUID_LEN];     /*! Alert Notification Control Point */
+extern const uint8_t attUasChUuid[ATT_16_UUID_LEN];      /*! Unread Alert Status */
+extern const uint8_t attNaChUuid[ATT_16_UUID_LEN];       /*! New Alert */
+extern const uint8_t attSnacChUuid[ATT_16_UUID_LEN];     /*! Supported New Alert Category */
+extern const uint8_t attSuacChUuid[ATT_16_UUID_LEN];     /*! Supported Unread Alert Category */
+extern const uint8_t attBpfChUuid[ATT_16_UUID_LEN];      /*! Blood Pressure Feature */
+extern const uint8_t attHidiChUuid[ATT_16_UUID_LEN];     /*! HID Information */            
+extern const uint8_t attRmChUuid[ATT_16_UUID_LEN];       /*! Report Map */                
+extern const uint8_t attHidcpChUuid[ATT_16_UUID_LEN];    /*! HID Control Point */          
+extern const uint8_t attRepChUuid[ATT_16_UUID_LEN];      /*! Report */                    
+extern const uint8_t attPmChUuid[ATT_16_UUID_LEN];       /*! Protocol Mode */              
+extern const uint8_t attSiwChUuid[ATT_16_UUID_LEN];      /*! Scan Interval Window */       
+extern const uint8_t attPnpChUuid[ATT_16_UUID_LEN];      /*! PnP ID */                     
+extern const uint8_t attGlfChUuid[ATT_16_UUID_LEN];      /*! Glucose Feature */            
+extern const uint8_t attRacpChUuid[ATT_16_UUID_LEN];     /*! Record Access Control Point */
+extern const uint8_t attWmChUuid[ATT_16_UUID_LEN];       /*! Weight measurement */
+extern const uint8_t attWsfChUuid[ATT_16_UUID_LEN];      /*! Weight scale feature */
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* ATT_UUID_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/dm_api.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/dm_api.h
new file mode 100644
index 00000000000..64ddd6b8155
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/dm_api.h
@@ -0,0 +1,1235 @@
+/*************************************************************************************************/
+/*!
+ *  \file   dm_api.h
+ *        
+ *  \brief  Device Manager subsystem API.
+ *
+ *          $Date: 2012-09-11 16:18:57 -0700 (Tue, 11 Sep 2012) $
+ *          $Revision: 349 $
+ *  
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef DM_API_H
+#define DM_API_H
+
+#include "hci_api.h"
+#include "cfg_stack.h"
+#include "smp_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/*! Device role */
+#define DM_ROLE_MASTER              HCI_ROLE_MASTER  /*! Role is master */
+#define DM_ROLE_SLAVE               HCI_ROLE_SLAVE   /*! Role is slave */
+
+/*! The GAP discovery mode */
+#define DM_DISC_MODE_NONE           0     /*! GAP non-discoverable */
+#define DM_DISC_MODE_LIMITED        1     /*! GAP limited discoverable mode */
+#define DM_DISC_MODE_GENERAL        2     /*! GAP general discoverable mode */
+
+/*! The type of connectable or discoverable of advertising */
+#define DM_ADV_CONN_UNDIRECT        0     /*! Connectable undirected advertising */
+#define DM_ADV_CONN_DIRECT          1     /*! Connectable directed advertising */
+#define DM_ADV_DISC_UNDIRECT        2     /*! Discoverable undirected advertising */
+#define DM_ADV_NONCONN_UNDIRECT     3     /*! Non-connectable undirected advertising */
+#define DM_ADV_SCAN_RESPONSE        4     /*! Scan response */
+#define DM_ADV_NONE                 255   /*! For internal use only */
+
+/*! Whether data is located in the advertising data or the scan response data */
+#define DM_DATA_LOC_ADV             0     /*! Locate data in the advertising data */
+#define DM_DATA_LOC_SCAN            1     /*! Locate data in the scan response data */
+
+/*! The scan type */
+#define DM_SCAN_TYPE_PASSIVE        0     /*! Passive scan */
+#define DM_SCAN_TYPE_ACTIVE         1     /*! Active scan */
+
+/*! Advertising channel map */
+#define DM_ADV_CHAN_37              HCI_ADV_CHAN_37  /*! Advertising channel 37 */
+#define DM_ADV_CHAN_38              HCI_ADV_CHAN_38  /*! Advertising channel 38 */
+#define DM_ADV_CHAN_39              HCI_ADV_CHAN_39  /*! Advertising channel 39 */
+#define DM_ADV_CHAN_ALL             (HCI_ADV_CHAN_37 | HCI_ADV_CHAN_38 | HCI_ADV_CHAN_39)
+
+/*! The client ID parameter to function DmConnRegister() */
+#define DM_CLIENT_ID_ATT            0     /*! Identifier for attribute protocol, for internal use only */
+#define DM_CLIENT_ID_SMP            1     /*! Identifier for security manager protocol, for internal use only */
+#define DM_CLIENT_ID_DM             2     /*! Identifier for device manager, for internal use only */
+#define DM_CLIENT_ID_APP            3     /*! Identifier for the application */
+#define DM_CLIENT_ID_MAX            4     /*! For internal use only */
+
+/*! Unknown connection ID or other error */
+#define DM_CONN_ID_NONE             0
+
+/*! The address type */
+#define DM_ADDR_PUBLIC              0     /*! Public address */
+#define DM_ADDR_RANDOM              1     /*! Random address */
+
+/*! Advertising data types */
+#define DM_ADV_TYPE_FLAGS           0x01  /*! Flag bits */
+#define DM_ADV_TYPE_16_UUID_PART    0x02  /*! Partial list of 16 bit UUIDs */
+#define DM_ADV_TYPE_16_UUID         0x03  /*! Complete list of 16 bit UUIDs */
+#define DM_ADV_TYPE_128_UUID_PART   0x06  /*! Partial list of 128 bit UUIDs */
+#define DM_ADV_TYPE_128_UUID        0x07  /*! Complete list of 128 bit UUIDs */
+#define DM_ADV_TYPE_SHORT_NAME      0x08  /*! Shortened local name */
+#define DM_ADV_TYPE_LOCAL_NAME      0x09  /*! Complete local name */
+#define DM_ADV_TYPE_TX_POWER        0x0A  /*! TX power level */
+#define DM_ADV_TYPE_CONN_INTERVAL   0x12  /*! Slave preferred connection interval */
+#define DM_ADV_TYPE_SIGNED_DATA     0x13  /*! Signed data */
+#define DM_ADV_TYPE_16_SOLICIT      0x14  /*! Service soliticiation list of 16 bit UUIDs */
+#define DM_ADV_TYPE_128_SOLICIT     0x15  /*! Service soliticiation list of 128 bit UUIDs */
+#define DM_ADV_TYPE_SERVICE_DATA    0x16  /*! Service data */
+#define DM_ADV_TYPE_PUBLIC_TARGET   0x17  /*! Public target address */
+#define DM_ADV_TYPE_RANDOM_TARGET   0x18  /*! Random target address */
+#define DM_ADV_TYPE_APPEARANCE      0x19  /*! Device appearance */
+#define DM_ADV_TYPE_MANUFACTURER    0xFF  /*! Manufacturer specific data */
+
+/*! Bit mask for flags advertising data type */
+#define DM_FLAG_LE_LIMITED_DISC     0x01  /*! Limited discoverable flag */
+#define DM_FLAG_LE_GENERAL_DISC     0x02  /*! General discoverable flag */
+#define DM_FLAG_LE_BREDR_NOT_SUP    0x04  /*! BR/EDR not supported flag */
+
+/*! Advertising data element indexes */
+#define DM_AD_LEN_IDX               0     /*! Advertising data element len */
+#define DM_AD_TYPE_IDX              1     /*! Advertising data element type */
+#define DM_AD_DATA_IDX              2     /*! Advertising data element data */
+
+/*! Timeouts defined by the GAP specification; in units of milliseconds */
+#define DM_GAP_LIM_ADV_TIMEOUT      180000  /*! Maximum advertising duration in limited discoverable mode */
+#define DM_GAP_GEN_DISC_SCAN_MIN    10240   /*! Minimum scan duration for general discovery */
+#define DM_GAP_LIM_DISC_SCAN_MIN    10240   /*! Minimum scan duration for limited discovery */
+#define DM_GAP_CONN_PARAM_TIMEOUT   30000   /*! Connection parameter update timeout */
+#define DM_GAP_SCAN_FAST_PERIOD     30720   /*! Minimum time to perform scanning when user initiated */
+#define DM_GAP_ADV_FAST_PERIOD      30000   /*! Minimum time to perform advertising when user initiated */
+
+/*!
+ * Advertising, scanning, and connection parameters defined in the GAP specification.
+ * In units of 625 microseconds.
+ */
+#define DM_GAP_SCAN_FAST_INT_MIN    48      /*! Minimum scan interval when user initiated */
+#define DM_GAP_SCAN_FAST_INT_MAX    96      /*! Maximum scan interval when user initiated */
+#define DM_GAP_SCAN_FAST_WINDOW     48      /*! Scan window when user initiated */
+#define DM_GAP_SCAN_SLOW_INT_1      2048    /*! Scan interval 1 when background scannning */
+#define DM_GAP_SCAN_SLOW_WINDOW_1   18      /*! Scan window 1 when background scanning */
+#define DM_GAP_SCAN_SLOW_INT_2      4096    /*! Scan interval 2 when background scannning */
+#define DM_GAP_SCAN_SLOW_WINDOW_2   18      /*! Scan window 2 when background scanning */
+#define DM_GAP_ADV_FAST_INT_MIN     48      /*! Minimum advertising interval when user initiated */
+#define DM_GAP_ADV_FAST_INT_MAX     96      /*! Maximum advertising interval when user initiated */
+#define DM_GAP_ADV_SLOW_INT_MIN     1600    /*! Minimum advertising interval when background advertising */
+#define DM_GAP_ADV_SLOW_INT_MAX     1920    /*! Maximum advertising interval when background advertising */
+
+/*! GAP connection establishment latency */
+#define DM_GAP_CONN_EST_LATENCY     0
+
+/*! GAP connection intervals in 1.25ms units */
+#define DM_GAP_INITIAL_CONN_INT_MIN 24      /*! Minimum initial connection interval */
+#define DM_GAP_INITIAL_CONN_INT_MAX 40      /*! Maximum initial onnection interval */
+
+/*! GAP connection establishment minimum and maximum connection event lengths */
+#define DM_GAP_CONN_EST_MIN_CE_LEN  0
+#define DM_GAP_CONN_EST_MAX_CE_LEN  0
+
+/*! GAP peripheral privacy flag characteristic values */
+#define DM_GAP_PRIV_DISABLED        0
+#define DM_GAP_PRIV_ENABLED         1
+
+/*! Connection establishment supervision timeout default, in 10ms units */
+#define DM_DEFAULT_EST_SUP_TIMEOUT  2000
+
+/*! Pairing authentication/security properties bit mask */
+#define DM_AUTH_BOND_FLAG           SMP_AUTH_BOND_FLAG  /*! Bonding requested */
+#define DM_AUTH_MITM_FLAG           SMP_AUTH_MITM_FLAG  /*! MITM (authenticated pairing) requested */
+
+/*! Key distribution bit mask */
+#define DM_KEY_DIST_LTK             SMP_KEY_DIST_ENC   /*! Distribute LTK used for encryption */
+#define DM_KEY_DIST_IRK             SMP_KEY_DIST_ID    /*! Distribute IRK used for privacy */
+#define DM_KEY_DIST_CSRK            SMP_KEY_DIST_SIGN  /*! Distribute CSRK used for signed data */
+
+/*! Key type used in DM_SEC_KEY_IND */
+#define DM_KEY_LOCAL_LTK            0x01  /*! LTK generated locally for this device */
+#define DM_KEY_PEER_LTK             0x02  /*! LTK received from peer device */
+#define DM_KEY_IRK                  0x04  /*! IRK and identity info of peer device */
+#define DM_KEY_CSRK                 0x08  /*! CSRK of peer device */
+
+/*! Base value for HCI error status values for DM_SEC_PAIR_CMPL_IND */
+#define DM_SEC_HCI_ERR_BASE         0x20
+
+#define DM_SEC_LEVEL_NONE           0     /*! Connection has no security */
+#define DM_SEC_LEVEL_ENC            1     /*! Connection is encrypted with unauthenticated key */
+#define DM_SEC_LEVEL_ENC_AUTH       2     /*! Connection is encrypted with authenticated key */
+
+/*! Random address types */
+#define DM_RAND_ADDR_STATIC         0xC0  /*! Static address */
+#define DM_RAND_ADDR_RESOLV         0x80  /*! Resolvable private address */
+#define DM_RAND_ADDR_NONRESOLV      0x00  /*! Non-resolvable private address */
+
+/*! Get the type of random address */
+#define DM_RAND_ADDR_GET(addr)          ((addr)[5] & 0xC0)
+
+/*! Set the type of random address */
+#define DM_RAND_ADDR_SET(addr, type)    {(addr)[5] = ((addr)[5] & 0x3F) | (type);}
+
+/*! Connection busy/idle state */
+#define DM_CONN_IDLE                0     /*! Connection is idle */
+#define DM_CONN_BUSY                1     /*! Connection is busy */
+
+/*! Connection busy/idle state bitmask */
+#define DM_IDLE_SMP_PAIR            0x0001  /*! SMP pairing in progress */
+#define DM_IDLE_DM_ENC              0x0002  /*! DM Encryption setup in progress */
+#define DM_IDLE_ATTS_DISC           0x0004  /*! ATTS service discovery in progress */
+#define DM_IDLE_APP_DISC            0x0008  /*! App framework service discovery in progress */
+#define DM_IDLE_USER_1              0x0010  /*! For use by user application */
+#define DM_IDLE_USER_2              0x0020  /*! For use by user application */
+#define DM_IDLE_USER_3              0x0040  /*! For use by user application */
+#define DM_IDLE_USER_4              0x0080  /*! For use by user application */
+
+/*! DM callback events */
+#define DM_CBACK_START              0x20  /*! DM callback event starting value */
+enum
+{
+  DM_RESET_CMPL_IND = DM_CBACK_START,     /*! Reset complete */
+  DM_ADV_START_IND,                       /*! Advertising started */
+  DM_ADV_STOP_IND,                        /*! Advertising stopped */
+  DM_ADV_NEW_ADDR_IND,                    /*! New resolvable address has been generated */
+  DM_SCAN_START_IND,                      /*! Scanning started */
+  DM_SCAN_STOP_IND,                       /*! Scanning stopped */
+  DM_SCAN_REPORT_IND,                     /*! Scan data received from peer device */
+  DM_CONN_OPEN_IND,                       /*! Connection opened */
+  DM_CONN_CLOSE_IND,                      /*! Connection closed */
+  DM_CONN_UPDATE_IND,                     /*! Connection update complete */
+  DM_SEC_PAIR_CMPL_IND,                   /*! Pairing completed successfully */
+  DM_SEC_PAIR_FAIL_IND,                   /*! Pairing failed or other security failure */
+  DM_SEC_ENCRYPT_IND,                     /*! Connection encrypted */
+  DM_SEC_ENCRYPT_FAIL_IND,                /*! Encryption failed */
+  DM_SEC_AUTH_REQ_IND,                    /*! PIN or OOB data requested for pairing */
+  DM_SEC_KEY_IND,                         /*! Security key indication */
+  DM_SEC_LTK_REQ_IND,                     /*! LTK requested for encyption */
+  DM_SEC_PAIR_IND,                        /*! Incoming pairing request from master */
+  DM_SEC_SLAVE_REQ_IND,                   /*! Incoming security request from slave */
+  DM_PRIV_RESOLVED_ADDR_IND,              /*! Private address resolved */
+  DM_HW_ERROR_IND,                        /*! Hardware Error */
+  DM_VENDOR_SPEC_IND,                     /*! Vendor specific event */
+};
+
+#define DM_CBACK_END                DM_VENDOR_SPEC_IND  /*! DM callback event ending value */
+
+/**************************************************************************************************
+  Data Types
+**************************************************************************************************/
+
+/*! Connection identifier */
+typedef uint8_t dmConnId_t;
+
+/*! Configuration structure */
+typedef struct
+{
+  uint8_t dummy;
+} dmCfg_t;
+
+/*! LTK data type */
+typedef struct
+{
+  uint8_t                   key[SMP_KEY_LEN];
+  uint8_t                   rand[SMP_RAND8_LEN];
+  uint16_t                  ediv;
+} dmSecLtk_t;
+
+/*! IRK data type */
+typedef struct
+{
+  uint8_t                   key[SMP_KEY_LEN];
+  bdAddr_t                  bdAddr;
+  uint8_t                   addrType;
+} dmSecIrk_t;
+
+/*! CSRK data type */
+typedef struct
+{
+  uint8_t                   key[SMP_KEY_LEN];
+} dmSecCsrk_t;
+
+/*! union of key types */
+typedef union
+{
+  dmSecLtk_t                ltk;
+  dmSecIrk_t                irk;
+  dmSecCsrk_t               csrk;
+} dmSecKey_t;
+
+/*! Data type for DM_SEC_PAIR_CMPL_IND */
+typedef struct
+{
+  wsfMsgHdr_t               hdr;          /*! Header */
+  uint8_t                   auth;         /*! Authentication and bonding flags */
+} dmSecPairCmplIndEvt_t;
+
+/*! Data type for DM_SEC_ENCRYPT_IND */
+typedef struct
+{
+  wsfMsgHdr_t               hdr;          /*! Header */
+  bool_t                    usingLtk;     /*! TRUE if connection encrypted with LTK */
+} dmSecEncryptIndEvt_t;
+
+/*! Data type for DM_SEC_AUTH_REQ_IND */
+typedef struct
+{
+  wsfMsgHdr_t               hdr;          /*! Header */
+  bool_t                    oob;          /*! Out-of-band data requested */
+  bool_t                    display;      /*! TRUE if pin is to be displayed */
+} dmSecAuthReqIndEvt_t;
+
+/*! Data type for DM_SEC_PAIR_IND */
+typedef struct
+{
+  wsfMsgHdr_t               hdr;          /*! Header */
+  uint8_t                   auth;         /*! Authentication and bonding flags */
+  bool_t                    oob;          /*! Out-of-band pairing data present or not present */
+  uint8_t                   iKeyDist;     /*! Initiator key distribution flags */
+  uint8_t                   rKeyDist;     /*! Responder key distribution flags */
+} dmSecPairIndEvt_t;
+
+/*! Data type for DM_SEC_SLAVE_REQ_IND */
+typedef struct
+{
+  wsfMsgHdr_t               hdr;          /*! Header */
+  uint8_t                   auth;         /*! Authentication and bonding flags */
+} dmSecSlaveIndEvt_t;
+
+/*! Data type for DM_SEC_KEY_IND */
+typedef struct
+{
+  wsfMsgHdr_t               hdr;          /*! Header */
+  dmSecKey_t                keyData;      /*! Key data */
+  uint8_t                   type;         /*! Key type */
+  uint8_t                   secLevel;     /*! Security level of pairing when key was exchanged */
+  uint8_t                   encKeyLen;    /*! Length of encryption key used when data was transferred */
+} dmSecKeyIndEvt_t;
+
+/*! Data type for DM_ADV_NEW_ADDR_IND */
+typedef struct
+{
+  wsfMsgHdr_t               hdr;          /*! Header */
+  bdAddr_t                  addr;         /*! New resolvable private address */
+  bool_t                    firstTime;    /*! TRUE when address is generated for the first time */
+} dmAdvNewAddrIndEvt_t;
+
+/*! Union of DM callback event data types */
+typedef union
+{
+  wsfMsgHdr_t               hdr;
+  hciLeAdvReportEvt_t       scanReport;
+  hciLeConnCmplEvt_t        connOpen;
+  hciLeConnUpdateCmplEvt_t  connUpdate;
+  hciDisconnectCmplEvt_t    connClose;
+  dmSecPairCmplIndEvt_t     pairCmpl;
+  dmSecEncryptIndEvt_t      encryptInd;
+  dmSecAuthReqIndEvt_t      authReq;
+  dmSecPairIndEvt_t         pairInd;
+  dmSecSlaveIndEvt_t        slaveInd;
+  dmSecKeyIndEvt_t          keyInd;
+  hciLeLtkReqEvt_t          ltkReqInd;
+  hciVendorSpecEvt_t        vendorSpec;
+  dmAdvNewAddrIndEvt_t      advNewAddr;
+} dmEvt_t;
+
+/*! Callback type */
+typedef void (*dmCback_t)(dmEvt_t *pDmEvt);
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmRegister
+ *        
+ *  \brief  Register a callback with DM for scan and advertising events.
+ *
+ *  \param  cback  Client callback function.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmRegister(dmCback_t cback);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmFindAdType
+ *        
+ *  \brief  Find an advertising data element in the given advertising or scan response data.
+ *
+ *  \param  adType  Advertising data element type to find.
+ *  \param  dataLen Data length.
+ *  \param  pData   Pointer to advertising or scan response data.
+ *
+ *  \return Pointer to the advertising data element byte array or NULL if not found.
+ */
+/*************************************************************************************************/
+uint8_t *DmFindAdType(uint8_t adType, uint8_t dataLen, uint8_t *pData);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmAdvInit
+ *        
+ *  \brief  Initialize DM advertising.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmAdvInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmAdvStart
+ *        
+ *  \brief  Start advertising using the given advertising type and duration.
+ *
+ *  \param  advType   Advertising type.
+ *  \param  duration  The advertising duration, in milliseconds.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmAdvStart(uint8_t advType, uint16_t duration);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmAdvStop
+ *        
+ *  \brief  Stop advertising.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmAdvStop(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmAdvSetInterval
+ *        
+ *  \brief  Set the minimum and maximum advertising intervals.
+ *
+ *  \param  intervalMin Minimum advertising interval.
+ *  \param  intervalMax Maximum advertising interval.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmAdvSetInterval(uint16_t intervalMin, uint16_t intervalMax);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmAdvSetChannelMap
+ *        
+ *  \brief  Include or exclude certain channels from the advertising channel map.
+ *
+ *  \param  channelMap  Advertising channel map. 
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmAdvSetChannelMap(uint8_t channelMap);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmAdvSetData
+ *        
+ *  \brief  Set the advertising or scan response data to the given data.
+ *
+ *  \param  location  Data location.
+ *  \param  len       Length of the data.  Maximum length is 31 bytes.
+ *  \param  pData     Pointer to the data.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmAdvSetData(uint8_t location, uint8_t len, uint8_t *pData);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmAdvSetAddrType
+ *        
+ *  \brief  Set the local address type used while advertising.  This function can be used to
+ *          configure advertising to use a random address.
+ *
+ *  \param  addrType  Address type.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmAdvSetAddrType(uint8_t addrType);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmAdvSetAdValue
+ *        
+ *  \brief  Set the value of an advertising data element in the given advertising or
+ *          scan response data.  If the element already exists in the data then it is replaced
+ *          with the new value.  If the element does not exist in the data it is appended
+ *          to it, space permitting.
+ *
+ *  \param  adType       Advertising data element type. 
+ *  \param  len          Length of the value.  Maximum length is 29 bytes.
+ *  \param  pValue       Pointer to the value.
+ *  \param  pAdvDataLen  Advertising or scan response data length.  The new length is returned
+ *                       in this parameter.
+ *  \param  pAdvData     Pointer to advertising or scan response data.
+ *
+ *  \return TRUE if the element was successfully added to the data, FALSE otherwise.
+ */
+/*************************************************************************************************/
+bool_t DmAdvSetAdValue(uint8_t adType, uint8_t len, uint8_t *pValue, uint8_t *pAdvDataLen,
+                       uint8_t *pAdvData);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmAdvSetName
+ *        
+ *  \brief  Set the device name in the given advertising or scan response data.  If the
+ *          name can only fit in the data if it is shortened, the name is shortened
+ *          and the AD type is changed to DM_ADV_TYPE_SHORT_NAME.
+ *
+ *  \param  len          Length of the name.  Maximum length is 29 bytes.
+ *  \param  pValue       Pointer to the name in UTF-8 format.
+ *  \param  pAdvDataLen  Advertising or scan response data length.  The new length is returned
+ *                       in this parameter.
+ *  \param  pAdvData     Pointer to advertising or scan response data.
+ *
+ *  \return TRUE if the element was successfully added to the data, FALSE otherwise.
+ */
+/*************************************************************************************************/
+bool_t DmAdvSetName(uint8_t len, uint8_t *pValue, uint8_t *pAdvDataLen, uint8_t *pAdvData);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmAdvPrivInit
+ *        
+ *  \brief  Initialize private advertising.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmAdvPrivInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmAdvPrivStart
+ *        
+ *  \brief  Start using a private resolvable address.
+ *
+ *  \param  changeInterval  Interval between automatic address changes, in seconds.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmAdvPrivStart(uint16_t changeInterval);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmAdvPrivStop
+ *        
+ *  \brief  Stop using a private resolvable address.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmAdvPrivStop(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmScanInit
+ *        
+ *  \brief  Initialize DM scanning.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmScanInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmScanStart
+ *        
+ *  \brief  Start scanning.
+ *
+ *  \param  mode      Discoverability mode.
+ *  \param  scanType  Scan type.
+ *  \param  filterDup Filter duplicates.  Set to TRUE to filter duplicate responses received
+ *                    from the same device.  Set to FALSE to receive all responses.
+ *  \param  duration  The scan duration, in milliseconds.  If set to zero, scanning will
+ *                    continue until DmScanStop() is called.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmScanStart(uint8_t mode, uint8_t scanType, bool_t filterDup, uint16_t duration);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmScanStop
+ *        
+ *  \brief  Stop scanning.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmScanStop(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmScanSetInterval
+ *        
+ *  \brief  Set the scan interval and window.
+ *
+ *  \param  scanInterval  The scan interval.
+ *  \param  scanWindow    The scan window.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmScanSetInterval(uint16_t scanInterval, uint16_t scanWindow);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmScanSetAddrType
+ *        
+ *  \brief  Set the local address type used while scanning.  This function can be used to
+ *          configure scanning to use a random address.
+ *
+ *  \param  addrType  Address type.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmScanSetAddrType(uint8_t addrType);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnInit
+ *        
+ *  \brief  Initialize DM connection manager.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmConnInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnMasterInit
+ *        
+ *  \brief  Initialize DM connection manager for operation as master.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmConnMasterInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnSlaveInit
+ *        
+ *  \brief  Initialize DM connection manager for operation as slave.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmConnSlaveInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnRegister
+ *        
+ *  \brief  Register with the DM connection manager.
+ *
+ *  \param  clientId  The client identifier.
+ *  \param  cback     Client callback function.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmConnRegister(uint8_t clientId, dmCback_t cback);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnOpen
+ *        
+ *  \brief  Open a connection to a peer device with the given address.
+ *
+ *  \param  clientId  The client identifier.
+ *  \param  addrType  Address type.
+ *  \param  pAddr     Peer device address.
+ *
+ *  \return Connection identifier.
+ */
+/*************************************************************************************************/
+dmConnId_t DmConnOpen(uint8_t clientId, uint8_t addrType, uint8_t *pAddr);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnClose
+ *        
+ *  \brief  Close the connection with the give connection identifier.
+ *
+ *  \param  clientId  The client identifier.
+ *  \param  connId    Connection identifier.
+ *  \param  reason    Reason connection is being closed.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmConnClose(uint8_t clientId, dmConnId_t connId, uint8_t reason);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnAccept
+ *        
+ *  \brief  Accept a connection from the given peer device by initiating directed advertising.
+ *
+ *  \param  clientId  The client identifier.
+ *  \param  addrType  Address type.
+ *  \param  pAddr     Peer device address.
+ *
+ *  \return Connection identifier.
+ */
+/*************************************************************************************************/
+dmConnId_t DmConnAccept(uint8_t clientId, uint8_t addrType, uint8_t *pAddr);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnUpdate
+ *        
+ *  \brief  Update the connection parameters of an open connection
+ *
+ *  \param  connId      Connection identifier.
+ *  \param  pConnSpec   Connection specification.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmConnUpdate(dmConnId_t connId, hciConnSpec_t *pConnSpec);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnSetScanInterval
+ *        
+ *  \brief  Set the scan interval and window for created connections created with DmConnOpen().
+ *
+ *  \param  scanInterval  The scan interval.
+ *  \param  scanWindow    The scan window.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmConnSetScanInterval(uint16_t scanInterval, uint16_t scanWindow);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnSetConnSpec
+ *        
+ *  \brief  Set the connection specification parameters for connections created with DmConnOpen().
+ *
+ *  \param  pConnSpec   Connection spec parameters.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmConnSetConnSpec(hciConnSpec_t *pConnSpec);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnSetAddrType
+ *        
+ *  \brief  Set the local address type used for connections created with DmConnOpen().
+ *
+ *  \param  addrType  Address type.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmConnSetAddrType(uint8_t addrType);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnSetIdle
+ *        
+ *  \brief  Configure a bit in the connection idle state mask as busy or idle.
+ *
+ *  \param  connId      Connection identifier.
+ *  \param  idleMask    Bit in the idle state mask to configure.
+ *  \param  idle        DM_CONN_BUSY or DM_CONN_IDLE.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmConnSetIdle(dmConnId_t connId, uint16_t idleMask, uint8_t idle);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnCheckIdle
+ *        
+ *  \brief  Check if a connection is idle.
+ *
+ *  \param  connId      Connection identifier.
+ *
+ *  \return Zero if connection is idle, nonzero if busy.
+ */
+/*************************************************************************************************/
+uint16_t DmConnCheckIdle(dmConnId_t connId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmDevReset
+ *        
+ *  \brief  Reset the device.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmDevReset(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmDevRole
+ *        
+ *  \brief  Return the device role indicating master or slave.
+ *
+ *  \return Device role.
+ */
+/*************************************************************************************************/
+uint8_t DmDevRole(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmDevSetRandAddr
+ *        
+ *  \brief  Set the random address to be used by the local device.
+ *
+ *  \param  pAddr     Random address.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmDevSetRandAddr(uint8_t *pAddr);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmDevWhiteListAdd
+ *        
+ *  \brief  Add a peer device to the white list.  Note that this function cannot be called
+ *          while advertising, scanning, or connecting with white list filtering active.
+ *
+ *  \param  addrType  Address type.
+ *  \param  pAddr     Peer device address.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmDevWhiteListAdd(uint8_t addrType, uint8_t *pAddr);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmDevWhiteListRemove
+ *        
+ *  \brief  Remove a peer device from the white list.  Note that this function cannot be called
+ *          while advertising, scanning, or connecting with white list filtering active.
+ *
+ *  \param  addrType  Address type.
+ *  \param  pAddr     Peer device address.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmDevWhiteListRemove(uint8_t addrType, uint8_t *pAddr);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmDevWhiteListClear
+ *        
+ *  \brief  Clear the white list.  Note that this function cannot be called while
+ *          advertising, scanning, or connecting with white list filtering active.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmDevWhiteListClear(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmDevVsInit
+ *        
+ *  \brief  Vendor-specific controller initialization function.
+ *
+ *  \param  param    Vendor-specific parameter.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmDevVsInit(uint8_t param);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSecInit
+ *        
+ *  \brief  Initialize DM security.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmSecInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSecPairReq
+ *        
+ *  \brief  This function is called by a master device to initiate pairing.
+ *
+ *  \param  connId    DM connection ID.
+ *  \param  oob       Out-of-band pairing data present or not present.
+ *  \param  auth      Authentication and bonding flags.
+ *  \param  iKeyDist  Initiator key distribution flags.
+ *  \param  rKeyDist  Responder key distribution flags.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmSecPairReq(dmConnId_t connId, bool_t oob, uint8_t auth, uint8_t iKeyDist, uint8_t rKeyDist);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSecPairRsp
+ *        
+ *  \brief  This function is called by a slave device to proceed with pairing after a
+ *          DM_SEC_PAIR_IND event is received.
+ *
+ *  \param  connId    DM connection ID.
+ *  \param  oob       Out-of-band pairing data present or not present.
+ *  \param  auth      Authentication and bonding flags.
+ *  \param  iKeyDist  Initiator key distribution flags.
+ *  \param  rKeyDist  Responder key distribution flags.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmSecPairRsp(dmConnId_t connId, bool_t oob, uint8_t auth, uint8_t iKeyDist, uint8_t rKeyDist);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSecCancelReq
+ *        
+ *  \brief  This function is called to cancel the pairing process.
+ *
+ *  \param  connId    DM connection ID.
+ *  \param  reason    Failure reason.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmSecCancelReq(dmConnId_t connId, uint8_t reason);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSecAuthRsp
+ *        
+ *  \brief  This function is called in response to a DM_SEC_AUTH_REQ_IND event to provide
+ *          PIN or OOB data during pairing.
+ *
+ *  \param  connId      DM connection ID.
+ *  \param  authDataLen Length of PIN or OOB data.
+ *  \param  pAuthData   pointer to PIN or OOB data.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmSecAuthRsp(dmConnId_t connId, uint8_t authDataLen, uint8_t *pAuthData);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSecSlaveReq
+ *        
+ *  \brief  This function is called by a slave device to request that the master initiates
+ *          pairing or link encryption.
+ *
+ *  \param  connId    DM connection ID.
+ *  \param  auth      Authentication flags.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmSecSlaveReq(dmConnId_t connId, uint8_t auth);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSecEncryptReq
+ *        
+ *  \brief  This function is called by a master device to initiate link encryption.
+ *
+ *  \param  connId    DM connection ID.
+ *  \param  secLevel  Security level of pairing when LTK was exchanged.
+ *  \param  pLtk      Pointer to LTK parameter structure.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmSecEncryptReq(dmConnId_t connId, uint8_t secLevel, dmSecLtk_t *pLtk);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSecLtkRsp
+ *        
+ *  \brief  This function is called by a slave in response to a DM_SEC_LTK_REQ_IND event 
+ *          to provide the long term key used for encryption.  
+ *
+ *  \param  connId    DM connection ID.
+ *  \param  keyFound  TRUE if key found.
+ *  \param  secLevel  Security level of pairing when key was exchanged.
+ *  \param  pKey      Pointer to the key, if found.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmSecLtkRsp(dmConnId_t connId, bool_t keyFound, uint8_t secLevel, uint8_t *pKey);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSecSetLocalCsrk
+ *        
+ *  \brief  This function sets the local CSRK used by the device.  
+ *
+ *  \param  pCsrk     Pointer to CSRK.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmSecSetLocalCsrk(uint8_t *pCsrk);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSecSetLocalIrk
+ *        
+ *  \brief  This function sets the local IRK used by the device.  
+ *
+ *  \param  pCsrk     Pointer to IRK.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmSecSetLocalIrk(uint8_t *pIrk);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmPrivInit
+ *        
+ *  \brief  Initialize DM privacy module.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmPrivInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmPrivResolveAddr
+ *        
+ *  \brief  Resolve a private resolvable address.  When complete the client's callback function
+ *          is called with a DM_PRIV_RESOLVED_ADDR_IND event.  The client must wait to receive
+ *          this event before executing this function again.
+ *
+ *  \param  pAddr     Peer device address.
+ *  \param  pIrk      The peer's identity resolving key.
+ *  \param  param     Client-defined parameter returned with callback event.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmPrivResolveAddr(uint8_t *pAddr, uint8_t *pIrk, uint16_t param);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmL2cConnUpdateCnf
+ *        
+ *  \brief  For internal use only.  L2C calls this function to send the result of an L2CAP
+ *          connection update response to DM.
+ *
+ *  \param  handle  Connection handle.
+ *  \param  reason  Connection update response reason code.
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmL2cConnUpdateCnf(uint16_t handle, uint16_t reason);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmL2cConnUpdateInd
+ *        
+ *  \brief  For internal use only.  L2C calls this function when it receives a connection update
+ *          request from a peer device.
+ *
+ *  \param  identifier  Identifier value.
+ *  \param  handle      Connection handle.
+ *  \param  pConnSpec   Connection spec parameters.
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmL2cConnUpdateInd(uint8_t identifier, uint16_t handle, hciConnSpec_t *pConnSpec);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnIdByHandle
+ *        
+ *  \brief  For internal use only.  Find the connection ID with matching handle.
+ *
+ *  \param  handle  Handle to find.
+ *
+ *  \return Connection ID or DM_CONN_ID_NONE if error.
+ */
+/*************************************************************************************************/
+dmConnId_t DmConnIdByHandle(uint16_t handle);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnInUse
+ *        
+ *  \brief  For internal use only.  Return TRUE if the connection is in use.
+ *
+ *  \param  connId  Connection ID.
+ *
+ *  \return TRUE if the connection is in use, FALSE otherwise.
+ */
+/*************************************************************************************************/
+bool_t DmConnInUse(dmConnId_t connId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnPeerAddrType
+ *        
+ *  \brief  For internal use only.  Return the peer address type.
+ *
+ *  \param  connId  Connection ID.
+ *
+ *  \return Peer address type.
+ */
+/*************************************************************************************************/
+uint8_t DmConnPeerAddrType(dmConnId_t connId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnPeerAddr
+ *        
+ *  \brief  For internal use only.  Return the peer device address.
+ *
+ *  \param  connId  Connection ID.
+ *
+ *  \return Pointer to peer device address.
+ */
+/*************************************************************************************************/
+uint8_t *DmConnPeerAddr(dmConnId_t connId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnLocalAddrType
+ *        
+ *  \brief  For internal use only.  Return the local address type.
+ *
+ *  \param  connId  Connection ID.
+ *
+ *  \return Local address type.
+ */
+/*************************************************************************************************/
+uint8_t DmConnLocalAddrType(dmConnId_t connId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnLocalAddr
+ *        
+ *  \brief  For internal use only.  Return the local address.
+ *
+ *  \param  connId  Connection ID.
+ *
+ *  \return Pointer to local address.
+ */
+/*************************************************************************************************/
+uint8_t *DmConnLocalAddr(dmConnId_t connId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmConnSecLevel
+ *        
+ *  \brief  For internal use only.  Return the security level of the connection.
+ *
+ *  \param  connId  Connection ID.
+ *
+ *  \return Security level of the connection.
+ */
+/*************************************************************************************************/
+uint8_t DmConnSecLevel(dmConnId_t connId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSmpEncryptReq
+ *        
+ *  \brief  For internal use only.  This function is called by SMP to request encryption.
+ *
+ *  \param  connId    DM connection ID.
+ *  \param  secLevel  Security level of pairing when key was exchanged.
+ *  \param  pKey      Pointer to key.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmSmpEncryptReq(dmConnId_t connId, uint8_t secLevel, uint8_t *pKey);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSmpCbackExec
+ *        
+ *  \brief  For internal use only.  Execute DM callback from SMP procedures.
+ *
+ *  \param  pDmEvt    Pointer to callback event data.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmSmpCbackExec(dmEvt_t *pDmEvt);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSecGetLocalCsrk
+ *        
+ *  \brief  For internal use only.  This function gets the local CSRK used by the device.  
+ *
+ *  \return Pointer to CSRK.
+ */
+/*************************************************************************************************/
+uint8_t *DmSecGetLocalCsrk(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmSecGetLocalIrk
+ *        
+ *  \brief  For internal use only.  This function gets the local IRK used by the device.  
+ *
+ *  \return Pointer to IRK.
+ */
+/*************************************************************************************************/
+uint8_t *DmSecGetLocalIrk(void);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* DM_API_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/dm_handler.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/dm_handler.h
new file mode 100644
index 00000000000..231bbd06a70
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/dm_handler.h
@@ -0,0 +1,67 @@
+/*************************************************************************************************/
+/*!
+ *  \file   dm_handler.h
+ *
+ *  \brief  Interface to DM event handler.
+ *
+ *          $Date: 2012-03-29 13:24:04 -0700 (Thu, 29 Mar 2012) $
+ *          $Revision: 287 $
+ *
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef DM_HANDLER_H
+#define DM_HANDLER_H
+
+#include "wsf_os.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmHandlerInit
+ *        
+ *  \brief  DM handler init function called during system initialization.
+ *
+ *  \param  handlerID  WSF handler ID for DM.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmHandlerInit(wsfHandlerId_t handlerId);
+
+
+/*************************************************************************************************/
+/*!
+ *  \fn     DmHandler
+ *        
+ *  \brief  WSF event handler for DM.
+ *
+ *  \param  event   WSF event mask.
+ *  \param  pMsg    WSF message.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void DmHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* DM_HANDLER_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/hci_api.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/hci_api.h
new file mode 100644
index 00000000000..a9a89e95048
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/hci_api.h
@@ -0,0 +1,375 @@
+/*************************************************************************************************/
+/*!
+ *  \file   hci_api.h
+ *
+ *  \brief  HCI subsystem API.
+ *
+ *          $Date: 2011-10-14 21:35:03 -0700 (Fri, 14 Oct 2011) $
+ *          $Revision: 191 $
+ *
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef HCI_API_H
+#define HCI_API_H
+
+#include "wsf_types.h"
+#include "hci_defs.h"
+#include "wsf_os.h"
+#include "bda.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/*! Internal event values for the HCI event and sec callbacks */
+#define HCI_RESET_SEQ_CMPL_CBACK_EVT                    0   /*! Reset sequence complete */
+#define HCI_LE_CONN_CMPL_CBACK_EVT                      1   /*! LE connection complete */
+#define HCI_DISCONNECT_CMPL_CBACK_EVT                   2   /*! LE disconnect complete */
+#define HCI_LE_CONN_UPDATE_CMPL_CBACK_EVT               3   /*! LE connection update complete */
+#define HCI_LE_CREATE_CONN_CANCEL_CMD_CMPL_CBACK_EVT    4   /*! LE create connection cancel command complete */
+#define HCI_LE_ADV_REPORT_CBACK_EVT                     5   /*! LE advertising report */
+#define HCI_READ_RSSI_CMD_CMPL_CBACK_EVT                6   /*! Read RSSI command complete */
+#define HCI_LE_READ_CHAN_MAP_CMD_CMPL_CBACK_EVT         7   /*! LE Read channel map command complete */
+#define HCI_READ_TX_PWR_LVL_CMD_CMPL_CBACK_EVT          8   /*! Read transmit power level command complete */
+#define HCI_READ_REMOTE_VER_INFO_CMPL_CBACK_EVT         9   /*! Read remote version information complete */
+#define HCI_LE_READ_REMOTE_FEAT_CMPL_CBACK_EVT          10  /*! LE read remote features complete */
+#define HCI_LE_LTK_REQ_REPL_CMD_CMPL_CBACK_EVT          11  /*! LE LTK request reply command complete */
+#define HCI_LE_LTK_REQ_NEG_REPL_CMD_CMPL_CBACK_EVT      12  /*! LE LTK request negative reply command complete */
+#define HCI_ENC_KEY_REFRESH_CMPL_CBACK_EVT              13  /*! Encryption key refresh complete */
+#define HCI_ENC_CHANGE_CBACK_EVT                        14  /*! Encryption change */
+#define HCI_LE_LTK_REQ_CBACK_EVT                        15  /*! LE LTK request */
+#define HCI_VENDOR_SPEC_CMD_STATUS_CBACK_EVT            16  /*! Vendor specific command status */
+#define HCI_VENDOR_SPEC_CMD_CMPL_CBACK_EVT              17  /*! Vendor specific command complete */
+#define HCI_VENDOR_SPEC_CBACK_EVT                       18  /*! Vendor specific */
+#define HCI_HW_ERROR_CBACK_EVT                          19  /*! Hardware error */
+#define HCI_LE_ENCRYPT_CMD_CMPL_CBACK_EVT               20  /*! LE encrypt command complete */
+#define HCI_LE_RAND_CMD_CMPL_CBACK_EVT                  21  /*! LE rand command complete */
+
+/**************************************************************************************************
+  Data Types
+**************************************************************************************************/
+
+/*! Connection specification type */
+typedef struct
+{
+  uint16_t            connIntervalMin;
+  uint16_t            connIntervalMax;
+  uint16_t            connLatency;
+  uint16_t            supTimeout;
+  uint16_t            minCeLen;
+  uint16_t            maxCeLen;
+} hciConnSpec_t;
+
+/*! LE connection complete event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             status;
+  uint16_t            handle;
+  uint8_t             role;
+  uint8_t             addrType;
+  bdAddr_t            peerAddr;
+  uint16_t            connInterval;
+  uint16_t            connLatency;
+  uint16_t            supTimeout;
+  uint8_t             clockAccuracy;
+} hciLeConnCmplEvt_t;
+
+/*! Disconnect complete event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             status;
+  uint16_t            handle;
+  uint8_t             reason;
+} hciDisconnectCmplEvt_t;
+
+/*! LE connection update complete event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             status;
+  uint16_t            handle;
+  uint16_t            connInterval;
+  uint16_t            connLatency;
+  uint16_t            supTimeout;
+} hciLeConnUpdateCmplEvt_t;
+
+/*! LE create connection cancel command complete event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             status;
+} hciLeCreateConnCancelCmdCmplEvt_t;
+
+/*! LE advertising report event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             *pData;
+  uint8_t             len;
+  int8_t              rssi;
+  uint8_t             eventType;
+  uint8_t             addrType;
+  bdAddr_t            addr;
+} hciLeAdvReportEvt_t;
+
+/*! Read RSSI command complete event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             status;
+  uint8_t             handle;
+  int8_t              rssi;
+} hciReadRssiCmdCmplEvt_t;
+
+/*! LE Read channel map command complete event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             status;
+  uint16_t            handle;
+  uint8_t             chanMap[HCI_CHAN_MAP_LEN];
+} hciReadChanMapCmdCmplEvt_t;
+
+/*! Read transmit power level command complete event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             status;
+  uint8_t             handle;
+  int8_t              pwrLvl;
+} hciReadTxPwrLvlCmdCmplEvt_t;
+
+/*! Read remote version information complete event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             status;
+  uint16_t            handle;
+  uint8_t             version;
+  uint16_t            mfrName;
+  uint16_t            subversion; 
+} hciReadRemoteVerInfoCmplEvt_t;
+
+/*! LE read remote features complete event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             status;
+  uint16_t            handle;
+  uint8_t             features[HCI_FEAT_LEN];
+} hciLeReadRemoteFeatCmplEvt_t;
+
+/*! LE LTK request reply command complete event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             status;
+  uint16_t            handle;
+} hciLeLtkReqReplCmdCmplEvt_t;
+
+/*! LE LTK request negative reply command complete event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             status;
+  uint16_t            handle;
+} hciLeLtkReqNegReplCmdCmplEvt_t;
+
+/*! Encryption key refresh complete event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             status;
+  uint16_t            handle;
+} hciEncKeyRefreshCmpl_t;
+
+/*! Encryption change event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             status;
+  uint16_t            handle;
+  uint8_t             enabled;
+} hciEncChangeEvt_t;
+
+/*! LE LTK request event */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint16_t            handle;
+  uint8_t             randNum[HCI_RAND_LEN];
+  uint16_t            encDiversifier;
+} hciLeLtkReqEvt_t;
+
+/*! Vendor specific command status event */
+typedef struct
+{
+  wsfMsgHdr_t        hdr;
+  uint16_t           opcode;
+} hciVendorSpecCmdStatusEvt_t;
+
+/*! Vendor specific command complete event */
+typedef struct
+{
+  wsfMsgHdr_t        hdr;
+  uint16_t           opcode;
+  uint8_t            param[1];
+} hciVendorSpecCmdCmplEvt_t;
+
+/*! Vendor specific event */
+typedef struct
+{
+  wsfMsgHdr_t        hdr;
+  uint8_t            param[1];
+} hciVendorSpecEvt_t;
+
+/*! Hardware error event */
+typedef struct
+{
+  wsfMsgHdr_t        hdr;
+  uint8_t            code;
+} hciHwErrorEvt_t;
+
+/*! LE encrypt command complete event */
+typedef struct
+{
+  wsfMsgHdr_t        hdr;
+  uint8_t            status;
+  uint8_t            data[HCI_ENCRYPT_DATA_LEN];
+} hciLeEncryptCmdCmplEvt_t;
+
+/*! LE rand command complete event */
+typedef struct
+{
+  wsfMsgHdr_t        hdr;
+  uint8_t            status;
+  uint8_t            randNum[HCI_RAND_LEN];
+} hciLeRandCmdCmplEvt_t;
+
+
+/*! Union of all event types */
+typedef union
+{
+  wsfMsgHdr_t                       hdr;
+  wsfMsgHdr_t                       resetSeqCmpl;
+  hciLeConnCmplEvt_t                leConnCmpl;
+  hciDisconnectCmplEvt_t            disconnectCmpl;
+  hciLeConnUpdateCmplEvt_t          leConnUpdateCmpl;
+  hciLeCreateConnCancelCmdCmplEvt_t leCreateConnCancelCmdCmpl;
+  hciLeAdvReportEvt_t               leAdvReport;
+  hciReadRssiCmdCmplEvt_t           readRssiCmdCmpl;
+  hciReadChanMapCmdCmplEvt_t        readChanMapCmdCmpl;    
+  hciReadTxPwrLvlCmdCmplEvt_t       readTxPwrLvlCmdCmpl;   
+  hciReadRemoteVerInfoCmplEvt_t     readRemoteVerInfoCmpl;  
+  hciLeReadRemoteFeatCmplEvt_t      leReadRemoteFeatCmpl;  
+  hciLeLtkReqReplCmdCmplEvt_t       leLtkReqReplCmdCmpl;   
+  hciLeLtkReqNegReplCmdCmplEvt_t    leLtkReqNegReplCmdCmpl;
+  hciEncKeyRefreshCmpl_t            encKeyRefreshCmpl;       
+  hciEncChangeEvt_t                 encChange;             
+  hciLeLtkReqEvt_t                  leLtkReq;                 
+  hciVendorSpecCmdStatusEvt_t       vendorSpecCmdStatus;   
+  hciVendorSpecCmdCmplEvt_t         vendorSpecCmdCmpl;     
+  hciVendorSpecEvt_t                vendorSpec;            
+  hciHwErrorEvt_t                   hwError;
+  hciLeEncryptCmdCmplEvt_t          leEncryptCmdCmpl;
+  hciLeRandCmdCmplEvt_t             leRandCmdCmpl;
+} hciEvt_t;
+
+/**************************************************************************************************
+  Callback Function Types
+**************************************************************************************************/
+
+typedef void (*hciEvtCback_t)(hciEvt_t *pEvent);
+typedef void (*hciSecCback_t)(hciEvt_t *pEvent);
+typedef void (*hciAclCback_t)(uint8_t *pData);
+typedef void (*hciFlowCback_t)(uint16_t handle, bool_t flowDisabled);
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*! Initialization, registration, and reset */
+void HciEvtRegister(hciEvtCback_t evtCback);
+void HciSecRegister(hciSecCback_t secCback);
+void HciAclRegister(hciAclCback_t aclCback, hciFlowCback_t flowCback);
+void HciResetSequence(void);
+void HciVsInit(uint8_t param);
+
+/*! Optimization interface */
+uint8_t *HciGetBdAddr(void);
+uint8_t HciGetWhiteListSize(void);
+int8_t HciGetAdvTxPwr(void);
+uint16_t HciGetBufSize(void);
+uint8_t HciGetNumBufs(void);
+uint8_t *HciGetSupStates(void);
+uint8_t HciGetLeSupFeat(void);
+
+/*! ACL data interface */
+void HciSendAclData(uint8_t *pAclData);
+
+/*! Command interface */
+void HciDisconnectCmd(uint16_t handle, uint8_t reason);
+void HciLeAddDevWhiteListCmd(uint8_t addrType, uint8_t *pAddr);
+void HciLeClearWhiteListCmd(void);
+void HciLeConnUpdateCmd(uint16_t handle, hciConnSpec_t *pConnSpec);
+void HciLeCreateConnCmd(uint16_t scanInterval, uint16_t scanWindow, uint8_t filterPolicy,
+                        uint8_t peerAddrType, uint8_t *pPeerAddr, uint8_t ownAddrType,
+                        hciConnSpec_t *pConnSpec);
+void HciLeCreateConnCancelCmd(void);
+void HciLeEncryptCmd(uint8_t *pKey, uint8_t *pData);
+void HciLeLtkReqNegReplCmd(uint16_t handle);
+void HciLeLtkReqReplCmd(uint16_t handle, uint8_t *pKey);
+void HciLeRandCmd(void);
+void HciLeReadAdvTXPowerCmd(void);
+void HciLeReadBufSizeCmd(void);
+void HciLeReadChanMapCmd(uint16_t handle);
+void HciLeReadLocalSupFeatCmd(void);
+void HciLeReadRemoteFeatCmd(uint16_t handle);
+void HciLeReadSupStatesCmd(void);
+void HciLeReadWhiteListSizeCmd(void);
+void HciLeRemoveDevWhiteListCmd(uint8_t addrType, uint8_t *pAddr);
+void HciLeSetAdvEnableCmd(uint8_t enable);
+void HciLeSetAdvDataCmd(uint8_t len, uint8_t *pData);
+void HciLeSetAdvParamCmd(uint16_t advIntervalMin, uint16_t advIntervalMax, uint8_t advType,
+                         uint8_t ownAddrType, uint8_t directAddrType, uint8_t *pDirectAddr,
+                         uint8_t advChanMap, uint8_t advFiltPolicy);
+void HciLeSetEventMaskCmd(uint8_t *pLeEventMask);
+void HciLeSetHostChanClassCmd(uint8_t *pChanMap);
+void HciLeSetRandAddrCmd(uint8_t *pAddr);
+void HciLeSetScanEnableCmd(uint8_t enable, uint8_t filterDup);
+void HciLeSetScanParamCmd(uint8_t scanType, uint16_t scanInterval, uint16_t scanWindow,
+                          uint8_t ownAddrType, uint8_t scanFiltPolicy);
+void HciLeSetScanRespDataCmd(uint8_t len, uint8_t *pData);
+void HciLeStartEncryptionCmd(uint16_t handle, uint8_t *pRand, uint16_t diversifier, uint8_t *pKey);
+void HciReadBdAddrCmd(void);
+void HciReadBufSizeCmd(void);
+void HciReadLocalSupFeatCmd(void);
+void HciReadLocalVerInfoCmd(void);
+void HciReadRemoteVerInfoCmd(uint16_t handle);
+void HciReadRssiCmd(uint16_t handle);
+void HciReadTxPwrLvlCmd(uint16_t handle, uint8_t type);
+void HciResetCmd(void);
+void HciSetEventMaskCmd(uint8_t *pEventMask);
+void HciVendorSpecificCmd(uint16_t opcode, uint8_t len, uint8_t *pData);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* HCI_API_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/hci_defs.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/hci_defs.h
new file mode 100644
index 00000000000..acd2c60f7f4
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/hci_defs.h
@@ -0,0 +1,462 @@
+/*************************************************************************************************/
+/*!
+ *  \file   hci_defs.h
+ *        
+ *  \brief  HCI constants and definitions from the Bluetooth specification.
+ *
+ *          $Date: 2012-06-26 21:53:53 -0700 (Tue, 26 Jun 2012) $
+ *          $Revision: 337 $
+ *  
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef HCI_DEFS_H
+#define HCI_DEFS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! Packet definitions */
+#define HCI_CMD_HDR_LEN                   3       /*! Command packet header length */
+#define HCI_ACL_HDR_LEN                   4       /*! ACL packet header length */
+#define HCI_EVT_HDR_LEN                   2       /*! Event packet header length */
+#define HCI_EVT_PARAM_MAX_LEN             255     /*! Maximum length of event packet parameters */
+#define HCI_PB_FLAG_MASK                  0x1000  /*! ACL packet boundary flag mask */
+#define HCI_PB_START                      0x0000  /*! Packet boundary flag, start */
+#define HCI_PB_CONTINUE                   0x1000  /*! Packet boundary flag, continue */
+#define HCI_HANDLE_MASK                   0x0FFF  /*! Mask for handle bits in ACL packet */
+#define HCI_HANDLE_NONE                   0xFFFF  /*! Value for invalid handle */
+
+/*! Packet types */
+#define HCI_CMD_TYPE                      1       /*! HCI command packet */
+#define HCI_ACL_TYPE                      2       /*! HCI ACL data packet */
+#define HCI_EVT_TYPE                      4       /*! HCI event packet */
+
+/*! Error codes */
+#define HCI_SUCCESS                       0x00    /*! Success */
+#define HCI_ERR_UNKNOWN_CMD               0x01    /*! Unknown HCI command */
+#define HCI_ERR_UNKNOWN_HANDLE            0x02    /*! Unknown connection identifier */
+#define HCI_ERR_HARDWARE_FAILURE          0x03    /*! Hardware failure */
+#define HCI_ERR_PAGE_TIMEOUT              0x04    /*! Page timeout */
+#define HCI_ERR_AUTH_FAILURE              0x05    /*! Authentication failure */
+#define HCI_ERR_KEY_MISSING               0x06    /*! PIN or key missing */
+#define HCI_ERR_MEMORY_EXCEEDED           0x07    /*! Memory capacity exceeded */
+#define HCI_ERR_CONN_TIMEOUT              0x08    /*! Connection timeout */
+#define HCI_ERR_CONN_LIMIT                0x09    /*! Connection limit exceeded */
+#define HCI_ERR_SYNCH_CONN_LIMIT          0x0A    /*! Synchronous connection limit exceeded */
+#define HCI_ERR_ACL_CONN_EXISTS           0x0B    /*! ACL connection already exists */
+#define HCI_ERR_CMD_DISALLOWED            0x0C    /*! Command disallowed */
+#define HCI_ERR_REJ_RESOURCES             0x0D    /*! Connection rejected limited resources */
+#define HCI_ERR_REJ_SECURITY              0x0E    /*! Connection rejected security reasons */
+#define HCI_ERR_REJ_BD_ADDR               0x0F    /*! Connection rejected unacceptable BD_ADDR */
+#define HCI_ERR_ACCEPT_TIMEOUT            0x10    /*! Connection accept timeout exceeded */
+#define HCI_ERR_UNSUP_FEAT                0x11    /*! Unsupported feature or parameter value */
+#define HCI_ERR_INVALID_PARAM             0x12    /*! Invalid HCI command parameters */
+#define HCI_ERR_REMOTE_TERMINATED         0x13    /*! Remote user terminated connection */
+#define HCI_ERR_REMOTE_RESOURCES          0x14    /*! Remote device low resources */
+#define HCI_ERR_REMOTE_POWER_OFF          0x15    /*! Remote device power off */
+#define HCI_ERR_LOCAL_TERMINATED          0x16    /*! Connection terminated by local host */
+#define HCI_ERR_REPEATED_ATTEMPTS         0x17    /*! Repeated attempts */
+#define HCI_ERR_PAIRING_NOT_ALLOWED       0x18    /*! Pairing not allowed */
+#define HCI_ERR_UNKNOWN_LMP_PDU           0x19    /*! Unknown LMP PDU */
+#define HCI_ERR_UNSUP_REMOTE_FEAT         0x1A    /*! Unsupported remote feature */
+#define HCI_ERR_SCO_OFFSET                0x1B    /*! SCO offset rejected */
+#define HCI_ERR_SCO_INTERVAL              0x1C    /*! SCO interval rejected */
+#define HCI_ERR_SCO_MODE                  0x1D    /*! SCO air mode rejected */
+#define HCI_ERR_LMP_PARAM                 0x1E    /*! Invalid LMP parameters */
+#define HCI_ERR_UNSPECIFIED               0x1F    /*! Unspecified error */
+#define HCI_ERR_UNSUP_LMP_PARAM           0x20    /*! Unsupported LMP parameter value */
+#define HCI_ERR_ROLE_CHANGE               0x21    /*! Role change not allowed */
+#define HCI_ERR_LL_RESP_TIMEOUT           0x22    /*! LL response timeout */
+#define HCI_ERR_LMP_COLLISION             0x23    /*! LMP error transaction collision */
+#define HCI_ERR_LMP_PDU                   0x24    /*! LMP pdu not allowed */
+#define HCI_ERR_ENCRYPT_MODE              0x25    /*! Encryption mode not acceptable */
+#define HCI_ERR_LINK_KEY                  0x26    /*! Link key can not be changed */
+#define HCI_ERR_UNSUP_QOS                 0x27    /*! Requested qos not supported */
+#define HCI_ERR_INSTANT_PASSED            0x28    /*! Instant passed */
+#define HCI_ERR_UNSUP_UNIT_KEY            0x29    /*! Pairing with unit key not supported */
+#define HCI_ERR_TRANSACT_COLLISION        0x2A    /*! Different transaction collision */
+#define HCI_ERR_CHANNEL_CLASS             0x2E    /*! Channel classification not supported */
+#define HCI_ERR_MEMORY                    0x2F    /*! Insufficient security */
+#define HCI_ERR_PARAMETER_RANGE           0x30    /*! Parameter out of mandatory range */
+#define HCI_ERR_ROLE_SWITCH_PEND          0x32    /*! Role switch pending */
+#define HCI_ERR_RESERVED_SLOT             0x34    /*! Reserved slot violation */
+#define HCI_ERR_ROLE_SWITCH               0x35    /*! Role switch failed */
+#define HCI_ERR_INQ_TOO_LARGE             0x36    /*! Extended inquiry response too large */
+#define HCI_ERR_UNSUP_SSP                 0x37    /*! Secure simple pairing not supported by host */
+#define HCI_ERR_HOST_BUSY_PAIRING         0x38    /*! Host busy - pairing */
+#define HCI_ERR_NO_CHANNEL                0x39    /*! Connection rejected no suitable channel */
+#define HCI_ERR_CONTROLLER_BUSY           0x3A    /*! Controller busy */
+#define HCI_ERR_CONN_INTERVAL             0x3B    /*! Unacceptable connection interval */
+#define HCI_ERR_ADV_TIMEOUT               0x3C    /*! Directed advertising timeout */
+#define HCI_ERR_MIC_FAILURE               0x3D    /*! Connection terminated due to MIC failure */
+#define HCI_ERR_CONN_FAIL                 0x3E    /*! Connection failed to be established */
+#define HCI_ERR_MAC_CONN_FAIL             0x3F    /*! MAC connection failed */
+
+/*! Command groups */
+#define HCI_OGF_NOP                       0x00    /*! No operation */
+#define HCI_OGF_LINK_CONTROL              0x01    /*! Link control */
+#define HCI_OGF_LINK_POLICY               0x02    /*! Link policy */
+#define HCI_OGF_CONTROLLER                0x03    /*! Controller and baseband */
+#define HCI_OGF_INFORMATIONAL             0x04    /*! Informational parameters */
+#define HCI_OGF_STATUS                    0x05    /*! Status parameters */
+#define HCI_OGF_TESTING                   0x06    /*! Testing */
+#define HCI_OGF_LE_CONTROLLER             0x08    /*! LE controller */
+#define HCI_OGF_VENDOR_SPEC               0x3F    /*! Vendor specific */
+
+/*! NOP command */
+#define HCI_OCF_NOP                       0x00
+
+/*! Link control commands */
+#define HCI_OCF_DISCONNECT                0x06
+#define HCI_OCF_READ_REMOTE_VER_INFO      0x1D
+
+/*! Link policy commands (none used for LE) */
+
+/*! Controller and baseband commands */
+#define HCI_OCF_SET_EVENT_MASK            0x01
+#define HCI_OCF_RESET                     0x03
+#define HCI_OCF_READ_TX_PWR_LVL           0x2D
+#define HCI_OCF_SET_CONTROLLER_TO_HOST_FC 0x31
+#define HCI_OCF_HOST_BUFFER_SIZE          0x33
+#define HCI_OCF_HOST_NUM_CMPL_PKTS        0x35
+
+/*! Informational commands */
+#define HCI_OCF_READ_LOCAL_VER_INFO       0x01
+#define HCI_OCF_READ_LOCAL_SUP_CMDS       0x02
+#define HCI_OCF_READ_LOCAL_SUP_FEAT       0x03
+#define HCI_OCF_READ_BUF_SIZE             0x05
+#define HCI_OCF_READ_BD_ADDR              0x09
+
+/*! Status commands */
+#define HCI_OCF_READ_RSSI                 0x05
+
+/*! LE controller commands */
+#define HCI_OCF_LE_SET_EVENT_MASK         0x01
+#define HCI_OCF_LE_READ_BUF_SIZE          0x02
+#define HCI_OCF_LE_READ_LOCAL_SUP_FEAT    0x03
+#define HCI_OCF_LE_SET_RAND_ADDR          0x05
+#define HCI_OCF_LE_SET_ADV_PARAM          0x06
+#define HCI_OCF_LE_READ_ADV_TX_POWER      0x07
+#define HCI_OCF_LE_SET_ADV_DATA           0x08
+#define HCI_OCF_LE_SET_SCAN_RESP_DATA     0x09
+#define HCI_OCF_LE_SET_ADV_ENABLE         0x0A
+#define HCI_OCF_LE_SET_SCAN_PARAM         0x0B
+#define HCI_OCF_LE_SET_SCAN_ENABLE        0x0C
+#define HCI_OCF_LE_CREATE_CONN            0x0D
+#define HCI_OCF_LE_CREATE_CONN_CANCEL     0x0E
+#define HCI_OCF_LE_READ_WHITE_LIST_SIZE   0x0F
+#define HCI_OCF_LE_CLEAR_WHITE_LIST       0x10
+#define HCI_OCF_LE_ADD_DEV_WHITE_LIST     0x11
+#define HCI_OCF_LE_REMOVE_DEV_WHITE_LIST  0x12
+#define HCI_OCF_LE_CONN_UPDATE            0x13
+#define HCI_OCF_LE_SET_HOST_CHAN_CLASS    0x14
+#define HCI_OCF_LE_READ_CHAN_MAP          0x15
+#define HCI_OCF_LE_READ_REMOTE_FEAT       0x16
+#define HCI_OCF_LE_ENCRYPT                0x17
+#define HCI_OCF_LE_RAND                   0x18
+#define HCI_OCF_LE_START_ENCRYPTION       0x19
+#define HCI_OCF_LE_LTK_REQ_REPL           0x1A
+#define HCI_OCF_LE_LTK_REQ_NEG_REPL       0x1B
+#define HCI_OCF_LE_READ_SUP_STATES        0x1C
+#define HCI_OCF_LE_RECEIVER_TEST          0x1D
+#define HCI_OCF_LE_TRANSMITTER_TEST       0x1E
+#define HCI_OCF_LE_TEST_END               0x1F
+
+/*! Opcode manipulation macros */
+#define HCI_OPCODE(ogf, ocf)              (((ogf) << 10) + (ocf))
+#define HCI_OGF(opcode)                   ((opcode) >> 10)
+#define HCI_OCF(opcode)                   ((opcode) & 0x03FF)
+
+/*! Command opcodes */
+#define HCI_OPCODE_NOP                       HCI_OPCODE(HCI_OGF_NOP, HCI_OCF_NOP)
+
+#define HCI_OPCODE_DISCONNECT                HCI_OPCODE(HCI_OGF_LINK_CONTROL, HCI_OCF_DISCONNECT)
+#define HCI_OPCODE_READ_REMOTE_VER_INFO      HCI_OPCODE(HCI_OGF_LINK_CONTROL, HCI_OCF_READ_REMOTE_VER_INFO)
+
+#define HCI_OPCODE_SET_EVENT_MASK            HCI_OPCODE(HCI_OGF_CONTROLLER, HCI_OCF_SET_EVENT_MASK)
+#define HCI_OPCODE_RESET                     HCI_OPCODE(HCI_OGF_CONTROLLER, HCI_OCF_RESET)
+#define HCI_OPCODE_READ_TX_PWR_LVL           HCI_OPCODE(HCI_OGF_CONTROLLER, HCI_OCF_READ_TX_PWR_LVL)
+#define HCI_OPCODE_SET_CONTROLLER_TO_HOST_FC HCI_OPCODE(HCI_OGF_CONTROLLER, HCI_OCF_SET_CONTROLLER_TO_HOST_FC)
+#define HCI_OPCODE_HOST_BUFFER_SIZE          HCI_OPCODE(HCI_OGF_CONTROLLER, HCI_OCF_HOST_BUFFER_SIZE)
+#define HCI_OPCODE_HOST_NUM_CMPL_PKTS        HCI_OPCODE(HCI_OGF_CONTROLLER, HCI_OCF_HOST_NUM_CMPL_PKTS)
+
+#define HCI_OPCODE_READ_LOCAL_VER_INFO       HCI_OPCODE(HCI_OGF_INFORMATIONAL, HCI_OCF_READ_LOCAL_VER_INFO)
+#define HCI_OPCODE_READ_LOCAL_SUP_CMDS       HCI_OPCODE(HCI_OGF_INFORMATIONAL, HCI_OCF_READ_LOCAL_SUP_CMDS)
+#define HCI_OPCODE_READ_LOCAL_SUP_FEAT       HCI_OPCODE(HCI_OGF_INFORMATIONAL, HCI_OCF_READ_LOCAL_SUP_FEAT)
+#define HCI_OPCODE_READ_BUF_SIZE             HCI_OPCODE(HCI_OGF_INFORMATIONAL, HCI_OCF_READ_BUF_SIZE)
+#define HCI_OPCODE_READ_BD_ADDR              HCI_OPCODE(HCI_OGF_INFORMATIONAL, HCI_OCF_READ_BD_ADDR)
+
+#define HCI_OPCODE_READ_RSSI                 HCI_OPCODE(HCI_OGF_STATUS, HCI_OCF_READ_RSSI)
+
+#define HCI_OPCODE_LE_SET_EVENT_MASK         HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_SET_EVENT_MASK)
+#define HCI_OPCODE_LE_READ_BUF_SIZE          HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_READ_BUF_SIZE)
+#define HCI_OPCODE_LE_READ_LOCAL_SUP_FEAT    HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_READ_LOCAL_SUP_FEAT)
+#define HCI_OPCODE_LE_SET_RAND_ADDR          HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_SET_RAND_ADDR)
+#define HCI_OPCODE_LE_SET_ADV_PARAM          HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_SET_ADV_PARAM)
+#define HCI_OPCODE_LE_READ_ADV_TX_POWER      HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_READ_ADV_TX_POWER)
+#define HCI_OPCODE_LE_SET_ADV_DATA           HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_SET_ADV_DATA)
+#define HCI_OPCODE_LE_SET_SCAN_RESP_DATA     HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_SET_SCAN_RESP_DATA)
+#define HCI_OPCODE_LE_SET_ADV_ENABLE         HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_SET_ADV_ENABLE)
+#define HCI_OPCODE_LE_SET_SCAN_PARAM         HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_SET_SCAN_PARAM)
+#define HCI_OPCODE_LE_SET_SCAN_ENABLE        HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_SET_SCAN_ENABLE)
+#define HCI_OPCODE_LE_CREATE_CONN            HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_CREATE_CONN)
+#define HCI_OPCODE_LE_CREATE_CONN_CANCEL     HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_CREATE_CONN_CANCEL)
+#define HCI_OPCODE_LE_READ_WHITE_LIST_SIZE   HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_READ_WHITE_LIST_SIZE)
+#define HCI_OPCODE_LE_CLEAR_WHITE_LIST       HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_CLEAR_WHITE_LIST)
+#define HCI_OPCODE_LE_ADD_DEV_WHITE_LIST     HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_ADD_DEV_WHITE_LIST)
+#define HCI_OPCODE_LE_REMOVE_DEV_WHITE_LIST  HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_REMOVE_DEV_WHITE_LIST)
+#define HCI_OPCODE_LE_CONN_UPDATE            HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_CONN_UPDATE)
+#define HCI_OPCODE_LE_SET_HOST_CHAN_CLASS    HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_SET_HOST_CHAN_CLASS)
+#define HCI_OPCODE_LE_READ_CHAN_MAP          HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_READ_CHAN_MAP)
+#define HCI_OPCODE_LE_READ_REMOTE_FEAT       HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_READ_REMOTE_FEAT)
+#define HCI_OPCODE_LE_ENCRYPT                HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_ENCRYPT)
+#define HCI_OPCODE_LE_RAND                   HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_RAND)
+#define HCI_OPCODE_LE_START_ENCRYPTION       HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_START_ENCRYPTION)
+#define HCI_OPCODE_LE_LTK_REQ_REPL           HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_LTK_REQ_REPL)
+#define HCI_OPCODE_LE_LTK_REQ_NEG_REPL       HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_LTK_REQ_NEG_REPL)
+#define HCI_OPCODE_LE_READ_SUP_STATES        HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_READ_SUP_STATES)
+#define HCI_OPCODE_LE_RECEIVER_TEST          HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_RECEIVER_TEST)
+#define HCI_OPCODE_LE_TRANSMITTER_TEST       HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_TRANSMITTER_TEST)
+#define HCI_OPCODE_LE_TEST_END               HCI_OPCODE(HCI_OGF_LE_CONTROLLER, HCI_OCF_LE_TEST_END)
+
+/*! Command parameter lengths */
+#define HCI_LEN_NOP                       0
+
+#define HCI_LEN_DISCONNECT                3
+#define HCI_LEN_READ_REMOTE_VER_INFO      2
+
+#define HCI_LEN_SET_EVENT_MASK            8
+#define HCI_LEN_RESET                     0
+#define HCI_LEN_READ_TX_PWR_LVL           3
+#define HCI_LEN_SET_CONTROLLER_TO_HOST_FC 1
+#define HCI_LEN_HOST_BUFFER_SIZE          8
+#define HCI_LEN_HOST_NUM_CMPL_PKTS        1
+
+#define HCI_LEN_READ_LOCAL_VER_INFO       0
+#define HCI_LEN_READ_LOCAL_SUP_CMDS       0
+#define HCI_LEN_READ_LOCAL_SUP_FEAT       0
+#define HCI_LEN_READ_BUF_SIZE             0
+#define HCI_LEN_READ_BD_ADDR              0
+
+#define HCI_LEN_READ_RSSI                 2
+
+#define HCI_LEN_LE_SET_EVENT_MASK         8
+#define HCI_LEN_LE_READ_BUF_SIZE          0
+#define HCI_LEN_LE_READ_LOCAL_SUP_FEAT    0
+#define HCI_LEN_LE_SET_RAND_ADDR          6
+#define HCI_LEN_LE_SET_ADV_PARAM          15
+#define HCI_LEN_LE_READ_ADV_TX_POWER      0
+#define HCI_LEN_LE_SET_ADV_DATA           32
+#define HCI_LEN_LE_SET_SCAN_RESP_DATA     32
+#define HCI_LEN_LE_SET_ADV_ENABLE         1
+#define HCI_LEN_LE_SET_SCAN_PARAM         7
+#define HCI_LEN_LE_SET_SCAN_ENABLE        2
+#define HCI_LEN_LE_CREATE_CONN            25
+#define HCI_LEN_LE_CREATE_CONN_CANCEL     0
+#define HCI_LEN_LE_READ_WHITE_LIST_SIZE   0
+#define HCI_LEN_LE_CLEAR_WHITE_LIST       0
+#define HCI_LEN_LE_ADD_DEV_WHITE_LIST     7
+#define HCI_LEN_LE_REMOVE_DEV_WHITE_LIST  7
+#define HCI_LEN_LE_CONN_UPDATE            14
+#define HCI_LEN_LE_SET_HOST_CHAN_CLASS    5
+#define HCI_LEN_LE_READ_CHAN_MAP          2
+#define HCI_LEN_LE_READ_REMOTE_FEAT       2
+#define HCI_LEN_LE_ENCRYPT                32
+#define HCI_LEN_LE_RAND                   0
+#define HCI_LEN_LE_START_ENCRYPTION       28
+#define HCI_LEN_LE_LTK_REQ_REPL           18
+#define HCI_LEN_LE_LTK_REQ_NEG_REPL       2
+#define HCI_LEN_LE_READ_SUP_STATES        0
+#define HCI_LEN_LE_RECEIVER_TEST          1
+#define HCI_LEN_LE_TRANSMITTER_TEST       3
+#define HCI_LEN_LE_TEST_END               0
+
+/*! Events */
+#define HCI_DISCONNECT_CMPL_EVT           0x05
+#define HCI_ENC_CHANGE_EVT                0x08
+#define HCI_READ_REMOTE_VER_INFO_CMPL_EVT 0x0C
+#define HCI_CMD_CMPL_EVT                  0x0E
+#define HCI_CMD_STATUS_EVT                0x0F
+#define HCI_HW_ERROR_EVT                  0x10
+#define HCI_NUM_CMPL_PKTS_EVT             0x13
+#define HCI_DATA_BUF_OVERFLOW_EVT         0x1A
+#define HCI_ENC_KEY_REFRESH_CMPL_EVT      0x30
+#define HCI_LE_META_EVT                   0x3E
+#define HCI_VENDOR_SPEC_EVT               0xFF
+
+/*! LE Subevents */
+#define HCI_LE_CONN_CMPL_EVT              0x01
+#define HCI_LE_ADV_REPORT_EVT             0x02
+#define HCI_LE_CONN_UPDATE_CMPL_EVT       0x03
+#define HCI_LE_READ_REMOTE_FEAT_CMPL_EVT  0x04
+#define HCI_LE_LTK_REQ_EVT                0x05
+
+/*! Event parameter lengths */
+#define HCI_LEN_DISCONNECT_CMPL           4
+#define HCI_LEN_ENC_CHANGE                5
+#define HCI_LEN_LE_CONN_CMPL              19
+#define HCI_LEN_LE_CONN_UPDATE_CMPL       9
+#define HCI_LEN_LE_READ_REMOTE_FEAT_CMPL  12
+#define HCI_LEN_LE_LTK_REQ                13
+
+/*! Supported commands */
+#define HCI_SUP_DISCONNECT                0x20      /*! Byte 0 */
+#define HCI_SUP_READ_REMOTE_VER_INFO      0x80      /*! Byte 2 */
+#define HCI_SUP_SET_EVENT_MASK            0x40      /*! Byte 5 */
+#define HCI_SUP_RESET                     0x80      /*! Byte 5 */
+#define HCI_SUP_READ_TX_PWR_LVL           0x04      /*! Byte 10 */
+#define HCI_SUP_SET_CONTROLLER_TO_HOST_FC 0x20      /*! Byte 10 */
+#define HCI_SUP_HOST_BUFFER_SIZE          0x40      /*! Byte 10 */
+#define HCI_SUP_HOST_NUM_CMPL_PKTS        0x80      /*! Byte 10 */
+#define HCI_SUP_READ_LOCAL_VER_INFO       0x08      /*! Byte 14 */
+#define HCI_SUP_READ_LOCAL_SUP_FEAT       0x20      /*! Byte 14 */
+#define HCI_SUP_READ_BD_ADDR              0x02      /*! Byte 15 */
+#define HCI_SUP_READ_RSSI                 0x20      /*! Byte 15 */
+#define HCI_SUP_LE_SET_EVENT_MASK         0x01      /*! Byte 25 */
+#define HCI_SUP_LE_READ_BUF_SIZE          0x02      /*! Byte 25 */
+#define HCI_SUP_LE_READ_LOCAL_SUP_FEAT    0x04      /*! Byte 25 */
+#define HCI_SUP_LE_SET_RAND_ADDR          0x10      /*! Byte 25 */
+#define HCI_SUP_LE_SET_ADV_PARAM          0x20      /*! Byte 25 */
+#define HCI_SUP_LE_READ_ADV_TX_POWER      0x40      /*! Byte 25 */
+#define HCI_SUP_LE_SET_ADV_DATA           0x80      /*! Byte 25 */
+#define HCI_SUP_LE_SET_SCAN_RESP_DATA     0x01      /*! Byte 26 */
+#define HCI_SUP_LE_SET_ADV_ENABLE         0x02      /*! Byte 26 */
+#define HCI_SUP_LE_SET_SCAN_PARAM         0x04      /*! Byte 26 */
+#define HCI_SUP_LE_SET_SCAN_ENABLE        0x08      /*! Byte 26 */
+#define HCI_SUP_LE_CREATE_CONN            0x10      /*! Byte 26 */
+#define HCI_SUP_LE_CREATE_CONN_CANCEL     0x20      /*! Byte 26 */
+#define HCI_SUP_LE_READ_WHITE_LIST_SIZE   0x40      /*! Byte 26 */
+#define HCI_SUP_LE_CLEAR_WHITE_LIST       0x80      /*! Byte 26 */
+#define HCI_SUP_LE_ADD_DEV_WHITE_LIST     0x01      /*! Byte 27 */
+#define HCI_SUP_LE_REMOVE_DEV_WHITE_LIST  0x02      /*! Byte 27 */
+#define HCI_SUP_LE_CONN_UPDATE            0x04      /*! Byte 27 */
+#define HCI_SUP_LE_SET_HOST_CHAN_CLASS    0x08      /*! Byte 27 */
+#define HCI_SUP_LE_READ_CHAN_MAP          0x10      /*! Byte 27 */
+#define HCI_SUP_LE_READ_REMOTE_FEAT       0x20      /*! Byte 27 */
+#define HCI_SUP_LE_ENCRYPT                0x40      /*! Byte 27 */
+#define HCI_SUP_LE_RAND                   0x80      /*! Byte 27 */
+#define HCI_SUP_LE_START_ENCRYPTION       0x01      /*! Byte 28 */
+#define HCI_SUP_LE_LTK_REQ_REPL           0x02      /*! Byte 28 */
+#define HCI_SUP_LE_LTK_REQ_NEG_REPL       0x04      /*! Byte 28 */
+#define HCI_SUP_LE_READ_SUP_STATES        0x08      /*! Byte 28 */
+#define HCI_SUP_LE_RECEIVER_TEST          0x10      /*! Byte 28 */
+#define HCI_SUP_LE_TRANSMITTER_TEST       0x20      /*! Byte 28 */
+#define HCI_SUP_LE_TEST_END               0x40      /*! Byte 28 */
+
+/*! Event mask */
+#define HCI_EVT_MASK_DISCONNECT_CMPL            0x10   /*! Byte 0 */
+#define HCI_EVT_MASK_ENC_CHANGE                 0x80   /*! Byte 0 */
+#define HCI_EVT_MASK_READ_REMOTE_VER_INFO_CMPL  0x08   /*! Byte 1 */
+#define HCI_EVT_MASK_HW_ERROR                   0x80   /*! Byte 1 */
+#define HCI_EVT_MASK_DATA_BUF_OVERFLOW          0x02   /*! Byte 3 */
+#define HCI_EVT_MASK_ENC_KEY_REFRESH_CMPL       0x80   /*! Byte 5 */
+#define HCI_EVT_MASK_LE_META                    0x20   /*! Byte 7 */
+
+/*! LE event mask */
+#define HCI_EVT_MASK_LE_CONN_CMPL_EVT              0x01   /*! Byte 0 */
+#define HCI_EVT_MASK_LE_ADV_REPORT_EVT             0x02   /*! Byte 0 */
+#define HCI_EVT_MASK_LE_CONN_UPDATE_CMPL_EVT       0x04   /*! Byte 0 */
+#define HCI_EVT_MASK_LE_READ_REMOTE_FEAT_CMPL_EVT  0x08   /*! Byte 0 */
+#define HCI_EVT_MASK_LE_LTK_REQ_EVT                0x10   /*! Byte 0 */
+
+/*! LE supported features */
+#define HCI_LE_SUP_FEAT_ENCRYPTION        0x01
+
+/*! Advertising command parameters */
+#define HCI_ADV_MIN_INTERVAL              0x0020    /*! Minimum advertising interval */
+#define HCI_ADV_NONCONN_MIN_INTERVAL      0x00A0    /*! Minimum nonconnectable adv. interval */
+#define HCI_ADV_MAX_INTERVAL              0x4000    /*! Maximum advertising interval */
+#define HCI_ADV_TYPE_CONN_UNDIRECT        0x00      /*! Connectable undirected advertising */
+#define HCI_ADV_TYPE_CONN_DIRECT          0x01      /*! Connectable directed advertising */
+#define HCI_ADV_TYPE_DISC_UNDIRECT        0x02      /*! Discoverable undirected advertising */
+#define HCI_ADV_TYPE_NONCONN_UNDIRECT     0x03      /*! Nonconnectable undirected advertising */
+#define HCI_ADV_CHAN_37                   0x01      /*! Advertising channel 37 */
+#define HCI_ADV_CHAN_38                   0x02      /*! Advertising channel 38 */
+#define HCI_ADV_CHAN_39                   0x04      /*! Advertising channel 39 */
+#define HCI_ADV_FILT_NONE                 0x00      /*! No scan request or connection filtering */
+#define HCI_ADV_FILT_SCAN                 0x01      /*! White list filters scan requests */
+#define HCI_ADV_FILT_CONN                 0x02      /*! White list filters connections */
+#define HCI_ADV_FILT_ALL                  0x03      /*! White list filters scan req. and conn. */
+
+/*! Scan command parameters */
+#define HCI_SCAN_TYPE_PASSIVE             0         /*! Passive scan */
+#define HCI_SCAN_TYPE_ACTIVE              1         /*! Active scan */
+#define HCI_SCAN_INTERVAL_MIN             0x0004    /*! Minimum scan interval */
+#define HCI_SCAN_INTERVAL_MAX             0x4000    /*! Maximum scan interval */
+#define HCI_SCAN_INTERVAL_DEFAULT         0x0010    /*! Default scan interval */
+#define HCI_SCAN_WINDOW_MIN               0x0004    /*! Minimum scan window */
+#define HCI_SCAN_WINDOW_MAX               0x4000    /*! Maximum scan window */
+#define HCI_SCAN_WINDOW_DEFAULT           0x0010    /*! Default scan window */
+
+/*! Connection command parameters */
+#define HCI_CONN_INTERVAL_MIN             0x0006    /*! Minimum connection interval */
+#define HCI_CONN_INTERVAL_MAX             0x0C80    /*! Maximum connection interval */
+#define HCI_CONN_LATENCY_MAX              0x01F3    /*! Maximum connection latency */
+#define HCI_SUP_TIMEOUT_MIN               0x000A    /*! Minimum supervision timeout */
+#define HCI_SUP_TIMEOUT_MAX               0x0C80    /*! Maximum supervision timeout */
+
+/*! Connection event parameters */
+#define HCI_ROLE_MASTER                   0         /*! Role is master */
+#define HCI_ROLE_SLAVE                    1         /*! Role is slave */
+#define HCI_CLOCK_500PPM                  0x00      /*! 500 ppm clock accuracy */
+#define HCI_CLOCK_250PPM                  0x01      /*! 250 ppm clock accuracy */
+#define HCI_CLOCK_150PPM                  0x02      /*! 150 ppm clock accuracy */
+#define HCI_CLOCK_100PPM                  0x03      /*! 100 ppm clock accuracy */
+#define HCI_CLOCK_75PPM                   0x04      /*! 75 ppm clock accuracy */
+#define HCI_CLOCK_50PPM                   0x05      /*! 50 ppm clock accuracy */
+#define HCI_CLOCK_30PPM                   0x06      /*! 30 ppm clock accuracy */
+#define HCI_CLOCK_20PPM                   0x07      /*! 20 ppm clock accuracy */
+
+/*! Advertising report event parameters */
+#define HCI_ADV_CONN_UNDIRECT             0x00      /*! Connectable undirected advertising */
+#define HCI_ADV_CONN_DIRECT               0x01      /*! Connectable directed advertising */
+#define HCI_ADV_DISC_UNDIRECT             0x02      /*! Discoverable undirected advertising */
+#define HCI_ADV_NONCONN_UNDIRECT          0x03      /*! Non-connectable undirected advertising */
+#define HCI_ADV_SCAN_RESPONSE             0x04      /*! Scan response */
+
+/*! Misc command parameters */
+#define HCI_READ_TX_PWR_CURRENT           0         /*! Read current tx power */
+#define HCI_READ_TX_PWR_MAX               1         /*! Read maximum tx power */
+#define HCI_TX_PWR_MIN                    -30       /*! Minimum tx power dBm */
+#define HCI_TX_PWR_MAX                    20        /*! Maximum tx power dBm */
+#define HCI_VERSION                       6         /*! HCI specification version */
+#define HCI_RSSI_MIN                      -127      /*! Minimum RSSI dBm */
+#define HCI_RSSI_MAX                      20        /*! Maximum RSSI dBm */
+#define HCI_ADDR_TYPE_PUBLIC              0         /*! Public device address */
+#define HCI_ADDR_TYPE_RANDOM              1         /*! Random device address */
+#define HCI_FILT_NONE                     0         /*! No white list filtering */
+#define HCI_FILT_WHITE_LIST               1         /*! White list filtering */
+#define HCI_ROLE_MASTER                   0         /*! Role is master */
+#define HCI_ROLE_SLAVE                    1         /*! Role is slave */
+
+/*! Parameter lengths */
+#define HCI_EVT_MASK_LEN                  8         /*! Length of event mask byte array */
+#define HCI_LE_EVT_MASK_LEN               8         /*! Length of LE event mask byte array */
+#define HCI_FEAT_LEN                      8         /*! Length of features byte array */
+#define HCI_ADV_DATA_LEN                  31        /*! Length of advertising data */
+#define HCI_SCAN_DATA_LEN                 31        /*! Length of scan response data */
+#define HCI_CHAN_MAP_LEN                  5         /*! Length of channel map byte array */
+#define HCI_KEY_LEN                       16        /*! Length of encryption key */
+#define HCI_ENCRYPT_DATA_LEN              16        /*! Length of data used in encryption */
+#define HCI_RAND_LEN                      8         /*! Length of random number */
+#define HCI_LE_STATES_LEN                 8         /*! Length of LE states byte array */
+
+/*! Wicentric company ID */
+#define HCI_ID_WICENTRIC                  0x005F
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* HCI_DEFS_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/hci_handler.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/hci_handler.h
new file mode 100644
index 00000000000..49a4e79cbd2
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/hci_handler.h
@@ -0,0 +1,67 @@
+/*************************************************************************************************/
+/*!
+ *  \file   hci_handler.h
+ *
+ *  \brief  Interface to HCI event handler.
+ *
+ *          $Date: 2012-03-29 13:24:04 -0700 (Thu, 29 Mar 2012) $
+ *          $Revision: 287 $
+ *
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef HCI_HANDLER_H
+#define HCI_HANDLER_H
+
+#include "wsf_os.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     HciHandlerInit
+ *        
+ *  \brief  HCI handler init function called during system initialization.
+ *
+ *  \param  handlerID  WSF handler ID for HCI.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void HciHandlerInit(wsfHandlerId_t handlerId);
+
+
+/*************************************************************************************************/
+/*!
+ *  \fn     HciHandler
+ *        
+ *  \brief  WSF event handler for HCI.
+ *
+ *  \param  event   WSF event mask.
+ *  \param  pMsg    WSF message.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void HciHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* HCI_HANDLER_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/l2c_api.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/l2c_api.h
new file mode 100644
index 00000000000..0143647e510
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/l2c_api.h
@@ -0,0 +1,173 @@
+/*************************************************************************************************/
+/*!
+ *  \file   l2c_api.h
+ *        
+ *  \brief  L2CAP subsystem API.
+ *
+ *          $Date: 2012-03-07 22:32:20 -0800 (Wed, 07 Mar 2012) $
+ *          $Revision: 268 $
+ *  
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef L2C_API_H
+#define L2C_API_H
+
+#include "hci_api.h"
+#include "l2c_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/*! Control callback message events */
+#define L2C_CTRL_FLOW_ENABLE_IND          0         /*! Data flow enabled */
+#define L2C_CTRL_FLOW_DISABLE_IND         1         /*! Data flow disabled */
+
+/**************************************************************************************************
+  Callback Function Types
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     l2cDataCback_t
+ *        
+ *  \brief  This callback function sends a received L2CAP packet to the client.
+ *
+ *  \param  handle    The connection handle.
+ *  \param  len       The length of the L2CAP payload data in pPacket.
+ *  \param  pPacket   A buffer containing the packet.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+typedef void (*l2cDataCback_t)(uint16_t handle, uint16_t len, uint8_t *pPacket);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     l2cCtrlCback_t
+ *        
+ *  \brief  This callback function sends control messages to the client.
+ *
+ *  \param  pMsg    Pointer to message structure.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+typedef void (*l2cCtrlCback_t)(wsfMsgHdr_t *pMsg);
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     L2cInit
+ *        
+ *  \brief  Initialize L2C subsystem.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void L2cInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     L2cMasterInit
+ *        
+ *  \brief  Initialize L2C for operation as a Bluetooth LE master.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void L2cMasterInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     L2cSlaveInit
+ *        
+ *  \brief  Initialize L2C for operation as a Bluetooth LE slave.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void L2cSlaveInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     L2cRegister
+ *        
+ *  \brief  called by the L2C client, such as ATT or SMP, to register for the given CID.
+ *
+ *  \param  cid       channel identifier.
+ *  \param  dataCback Callback function for L2CAP data received for this CID.
+ *  \param  ctrlCback Callback function for control events for this CID.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void L2cRegister(uint16_t cid, l2cDataCback_t dataCback, l2cCtrlCback_t ctrlCback);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     L2cDataReq
+ *        
+ *  \brief  Send an L2CAP data packet on the given CID.
+ *
+ *  \param  cid       The channel identifier.
+ *  \param  handle    The connection handle.  The client receives this handle from DM.
+ *  \param  len       The length of the payload data in pPacket.
+ *  \param  pPacket   A buffer containing the packet. 
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void L2cDataReq(uint16_t cid, uint16_t handle, uint16_t len, uint8_t *pL2cPacket);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     L2cDmConnUpdateReq
+ *        
+ *  \brief  This function is called by DM to send an L2CAP connection update request.
+ *
+ *  \param  handle      The connection handle.
+ *  \param  pConnSpec   Pointer to the connection specification structure.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void L2cDmConnUpdateReq(uint16_t handle, hciConnSpec_t *pConnSpec);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     L2cDmConnUpdateRsp
+ *        
+ *  \brief  This function is called by DM to send an L2CAP connection update response.
+ *
+ *  \param  identifier  Identifier value previously passed from L2C to DM.
+ *  \param  handle      The connection handle.
+ *  \param  result      Connection update response result.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void L2cDmConnUpdateRsp(uint8_t identifier, uint16_t handle, uint16_t result);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* L2C_API_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/l2c_defs.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/l2c_defs.h
new file mode 100644
index 00000000000..3cddf36e476
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/l2c_defs.h
@@ -0,0 +1,76 @@
+/*************************************************************************************************/
+/*!
+ *  \file   l2c_defs.h
+ *        
+ *  \brief  L2CAP constants and definitions from the Bluetooth specification.
+ *
+ *          $Date: 2011-10-14 21:35:03 -0700 (Fri, 14 Oct 2011) $
+ *          $Revision: 191 $
+ *  
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef L2C_DEFS_H
+#define L2C_DEFS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/*! Packet definitions */
+#define L2C_HDR_LEN                   4         /*! L2CAP packet header length */
+#define L2C_MIN_MTU                   23        /*! Minimum packet payload MTU for LE */
+#define L2C_SIG_HDR_LEN               4         /*! L2CAP signaling command header length */
+
+/*! Start of L2CAP payload in an HCI ACL packet buffer */
+#define L2C_PAYLOAD_START             (HCI_ACL_HDR_LEN + L2C_HDR_LEN)
+
+/*! L2CAP signaling packet base length, including HCI header */
+#define L2C_SIG_PKT_BASE_LEN          (HCI_ACL_HDR_LEN + L2C_HDR_LEN + L2C_SIG_HDR_LEN)
+
+/*! Signaling packet parameter lengths */
+#define L2C_SIG_CONN_UPDATE_REQ_LEN   8
+#define L2C_SIG_CONN_UPDATE_RSP_LEN   2
+#define L2C_SIG_CMD_REJ_LEN           2
+
+/*! Connection identifiers */
+#define L2C_CID_ATT                   0x0004    /*! CID for attribute protocol */
+#define L2C_CID_LE_SIGNALING          0x0005    /*! CID for LE signaling */
+#define L2C_CID_SMP                   0x0006    /*! CID for security manager protocol */
+
+/*! Signaling codes */
+#define L2C_SIG_CMD_REJ               0x01      /*! Comand reject */
+#define L2C_SIG_CONN_UPDATE_REQ       0x12      /*! Connection parameter update request */
+#define L2C_SIG_CONN_UPDATE_RSP       0x13      /*! Connection parameter update response */
+
+/*! Signaling response code flag */
+#define L2C_SIG_RSP_FLAG              0x01
+
+/*! Command reject reason codes */
+#define L2C_REJ_NOT_UNDERSTOOD        0x0000    /*! Command not understood */
+#define L2C_REJ_MTU_EXCEEDED          0x0001    /*! Signaling MTU exceeded */
+#define L2C_REJ_INVALID_CID           0x0002    /*! Invalid CID in request */
+
+/*! Connection parameter update result */
+#define L2C_CONN_PARAM_ACCEPTED       0x0000    /*! Connection parameters accepted */
+#define L2C_CONN_PARAM_REJECTED       0x0001    /*! Connection parameters rejected */
+
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* L2C_DEFS_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/l2c_handler.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/l2c_handler.h
new file mode 100644
index 00000000000..e94006e8582
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/l2c_handler.h
@@ -0,0 +1,66 @@
+/*************************************************************************************************/
+/*!
+ *  \file   l2c_handler.h
+ *        
+ *  \brief  L2CAP handler interface.
+ *
+ *          $Date $
+ *          $Revision $
+ *  
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef L2C_HANDLER_H
+#define L2C_HANDLER_H
+
+#include "wsf_os.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     L2cSlaveHandlerInit
+ *        
+ *  \brief  Event handler initialization function for L2C when operating as a slave.
+ *
+ *  \param  handlerId  ID for this event handler.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void L2cSlaveHandlerInit(wsfHandlerId_t handlerId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     L2cSlaveHandler
+ *        
+ *  \brief  The WSF event handler for L2C when operating as a slave.
+ *
+ *  \param  event   Event mask.
+ *  \param  pMsg    Pointer to message.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void L2cSlaveHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* L2C_HANDLER_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/smp_api.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/smp_api.h
new file mode 100644
index 00000000000..b40add0b5b5
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/smp_api.h
@@ -0,0 +1,195 @@
+/*************************************************************************************************/
+/*!
+ *  \file   smp_api.h
+ *        
+ *  \brief  SMP subsystem API.
+ *
+ *          $Date: 2011-10-14 21:35:03 -0700 (Fri, 14 Oct 2011) $
+ *          $Revision: 191 $
+ *  
+ *  Copyright (c) 2010-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef SMP_API_H
+#define SMP_API_H
+
+#include "wsf_os.h"
+#include "smp_defs.h"
+#include "dm_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/*! Event handler messages for SMP state machines */
+enum
+{
+  SMP_MSG_API_PAIR_REQ = 1,               /*! API pairing request */
+  SMP_MSG_API_PAIR_RSP,                   /*! API pairing response */
+  SMP_MSG_API_CANCEL_REQ,                 /*! API cancel request */
+  SMP_MSG_API_AUTH_RSP,                   /*! API pin response */
+  SMP_MSG_API_SECURITY_REQ,               /*! API security request */
+  SMP_MSG_CMD_PKT,                        /*! SMP command packet received */
+  SMP_MSG_CMD_PAIRING_FAILED,             /*! SMP pairing failed packet received */
+  SMP_MSG_DM_ENCRYPT_CMPL,                /*! Link encrypted */
+  SMP_MSG_DM_ENCRYPT_FAILED,              /*! Link encryption failed */
+  SMP_MSG_DM_CONN_CLOSE,                  /*! Connection closed */
+  SMP_MSG_WSF_AES_CMPL,                   /*! AES calculation complete */
+  SMP_MSG_INT_SEND_NEXT_KEY,              /*! Send next key to be distributed */
+  SMP_MSG_INT_MAX_ATTEMPTS,               /*! Maximum pairing attempts reached */
+  SMP_MSG_INT_PAIRING_CMPL,               /*! Pairing complete */
+  SMP_MSG_INT_TIMEOUT,                    /*! Pairing protocol timeout */
+  SMP_NUM_MSGS
+};
+
+/**************************************************************************************************
+  Data Types
+**************************************************************************************************/
+
+/*! Configurable parameters */
+typedef struct
+{
+  uint16_t            attemptTimeout;     /*! 'Repeated attempts' timeout in msec */
+  uint8_t             ioCap;              /*! I/O Capability */
+  uint8_t             minKeyLen;          /*! Minimum encryption key length */
+  uint8_t             maxKeyLen;          /*! Maximum encryption key length */
+  uint8_t             maxAttempts;        /*! Attempts to trigger 'repeated attempts' timeout */
+  uint8_t             auth;               /*! Device authentication requirements */
+} smpCfg_t;
+
+/*! Data type for SMP_MSG_API_PAIR_REQ and SMP_MSG_API_PAIR_RSP */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             oob;
+  uint8_t             auth;
+  uint8_t             iKeyDist;
+  uint8_t             rKeyDist;
+} smpDmPair_t;
+
+/*! Data type for SMP_MSG_API_AUTH_RSP */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             authData[SMP_OOB_LEN];
+  uint8_t             authDataLen;
+} smpDmAuthRsp_t;
+
+/*! Data type for SMP_MSG_API_SECURITY_REQ */
+typedef struct
+{
+  wsfMsgHdr_t         hdr;
+  uint8_t             auth;
+} smpDmSecurityReq_t;
+
+/*! Union SMP DM message data types */
+typedef union
+{
+  wsfMsgHdr_t         hdr;
+  smpDmPair_t         pair;
+  smpDmAuthRsp_t      authRsp;
+  smpDmSecurityReq_t  securityReq;
+} smpDmMsg_t;
+
+/**************************************************************************************************
+  Global Variables;
+**************************************************************************************************/
+
+/*! Configuration pointer */
+extern smpCfg_t *pSmpCfg;
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     SmpiInit
+ *        
+ *  \brief  Initialize SMP initiator role.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void SmpiInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     SmprInit
+ *        
+ *  \brief  Initialize SMP responder role.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void SmprInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     SmpNonInit
+ *        
+ *  \brief  Use this SMP init function when SMP is not supported.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void SmpNonInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     SmpDmMsgSend
+ *        
+ *  \brief  This function is called by DM to send a message to SMP.
+ *
+ *  \param  pMsg      Pointer to message structure.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void SmpDmMsgSend(smpDmMsg_t *pMsg);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     SmpDmEncryptInd
+ *        
+ *  \brief  This function is called by DM to notify SMP of encrypted link status.
+ *
+ *  \param  pMsg    Pointer to HCI message structure.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void SmpDmEncryptInd(wsfMsgHdr_t *pMsg);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     SmpDmGetStk
+ *        
+ *  \brief  Return the STK for the given connection.
+ *
+ *  \param  connId    Connection identifier.
+ *  \param  pSecLevel Returns the security level of pairing when STK was created.
+ *
+ *  \return Pointer to STK or NULL if not available.
+ */
+/*************************************************************************************************/
+uint8_t *SmpDmGetStk(dmConnId_t connId, uint8_t *pSecLevel);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* SMP_API_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/smp_defs.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/smp_defs.h
new file mode 100644
index 00000000000..91362248fb6
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/smp_defs.h
@@ -0,0 +1,122 @@
+/*************************************************************************************************/
+/*!
+ *  \file   smp_defs.h
+ *        
+ *  \brief  Security manager constants and definitions from the Bluetooth specification.
+ *
+ *          $Date: 2011-10-14 21:35:03 -0700 (Fri, 14 Oct 2011) $
+ *          $Revision: 191 $
+ *  
+ *  Copyright (c) 2010-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef SMP_DEFS_H
+#define SMP_DEFS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/*! PDU format */
+#define SMP_HDR_LEN                   1         /*! Attribute PDU header length */
+
+/*! Protocol timeout */
+#define SMP_TIMEOUT                   30        /*! Protocol timeout in seconds */
+
+/*! Encryption key size */
+#define SMP_KEY_SIZE_MAX              16        /*! Maximum encryption key size */
+#define SMP_KEY_SIZE_MIN              7         /*! Minimum encryption key size */
+
+/*! OOB and PIN data lengths in bytes */
+#define SMP_OOB_LEN                   16
+#define SMP_PIN_LEN                   3
+
+/*! Error codes */
+#define SMP_ERR_PASSKEY_ENTRY         0x01      /*! User input of passkey failed */
+#define SMP_ERR_OOB                   0x02      /*! OOB data is not available */
+#define SMP_ERR_AUTH_REQ              0x03      /*! Authentication requirements cannot be met */
+#define SMP_ERR_CONFIRM_VALUE         0x04      /*! Confirm value does not match */
+#define SMP_ERR_PAIRING_NOT_SUP       0x05      /*! Pairing is not supported by the device */
+#define SMP_ERR_ENC_KEY_SIZE          0x06      /*! Insufficient encryption key size */
+#define SMP_ERR_COMMAND_NOT_SUP       0x07      /*! Command not supported */
+#define SMP_ERR_UNSPECIFIED           0x08      /*! Unspecified reason */
+#define SMP_ERR_ATTEMPTS              0x09      /*! Repeated attempts */
+#define SMP_ERR_INVALID_PARAM         0x0A      /*! Invalid parameter or command length */
+
+/*! Proprietary internal error codes */
+#define SMP_ERR_MEMORY                0xE0      /*! Out of memory */
+#define SMP_ERR_TIMEOUT               0xE1      /*! Transaction timeout */
+
+/*! Command codes */
+#define SMP_CMD_PAIR_REQ              0x01      /*! Pairing Request */
+#define SMP_CMD_PAIR_RSP              0x02      /*! Pairing Response */
+#define SMP_CMD_PAIR_CNF              0x03      /*! Pairing Confirm */
+#define SMP_CMD_PAIR_RAND             0x04      /*! Pairing Random */
+#define SMP_CMD_PAIR_FAIL             0x05      /*! Pairing Failed */
+#define SMP_CMD_ENC_INFO              0x06      /*! Encryption Information */
+#define SMP_CMD_MASTER_ID             0x07      /*! Master Identification */
+#define SMP_CMD_ID_INFO               0x08      /*! Identity Information */
+#define SMP_CMD_ID_ADDR_INFO          0x09      /*! Identity Address Information */
+#define SMP_CMD_SIGN_INFO             0x0A      /*! Signing Information */
+#define SMP_CMD_SECURITY_REQ          0x0B      /*! Security Request */
+#define SMP_CMD_MAX                   0x0C      /*! Command code maximum */
+
+/*! Command packet lengths */
+#define SMP_PAIR_REQ_LEN              7
+#define SMP_PAIR_RSP_LEN              7
+#define SMP_PAIR_CNF_LEN              17
+#define SMP_PAIR_RAND_LEN             17
+#define SMP_PAIR_FAIL_LEN             2
+#define SMP_ENC_INFO_LEN              17
+#define SMP_MASTER_ID_LEN             11
+#define SMP_ID_INFO_LEN               17
+#define SMP_ID_ADDR_INFO_LEN          8
+#define SMP_SIGN_INFO_LEN             17
+#define SMP_SECURITY_REQ_LEN          2
+
+/*! I/O capabilities */
+#define SMP_IO_DISP_ONLY              0x00      /*! DisplayOnly */
+#define SMP_IO_DISP_YES_NO            0x01      /*! DisplayYesNo */
+#define SMP_IO_KEY_ONLY               0x02      /*! KeyboardOnly */
+#define SMP_IO_NO_IN_NO_OUT           0x03      /*! NoInputNoOutput */
+#define SMP_IO_KEY_DISP               0x04      /*! KeyboardDisplay */
+
+/*! OOB data present */
+#define SMP_OOB_DATA_NONE             0x00
+#define SMP_OOB_DATA_PRESENT          0x01
+
+/*! Authentication/security properties bit mask */
+#define SMP_AUTH_BOND_MASK            0x03      /*! Mask for bonding bits */
+#define SMP_AUTH_BOND_FLAG            0x01      /*! Bonding requested */
+#define SMP_AUTH_MITM_FLAG            0x04      /*! MITM (authenticated pairing) requested */
+
+/*! Key distribution bit mask */
+#define SMP_KEY_DIST_ENC              0x01      /*! Distribute LTK */
+#define SMP_KEY_DIST_ID               0x02      /*! Distribute IRK */
+#define SMP_KEY_DIST_SIGN             0x04      /*! Distribute CSRK */
+#define SMP_KEY_DIST_MASK             (SMP_KEY_DIST_ENC | SMP_KEY_DIST_ID | SMP_KEY_DIST_SIGN)
+
+/*! Various parameter lengths */
+#define SMP_RAND_LEN                  16
+#define SMP_CONFIRM_LEN               16
+#define SMP_KEY_LEN                   16
+#define SMP_RAND8_LEN                 8
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* SMP_DEFS_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/smp_handler.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/smp_handler.h
new file mode 100644
index 00000000000..d96fa41d496
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/stack/include/smp_handler.h
@@ -0,0 +1,67 @@
+/*************************************************************************************************/
+/*!
+ *  \file   smp_handler.h
+ *
+ *  \brief  Interface to SMP event handler.
+ *
+ *          $Date: 2012-03-29 13:24:04 -0700 (Thu, 29 Mar 2012) $
+ *          $Revision: 287 $
+ *
+ *  Copyright (c) 2010-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef SMP_HANDLER_H
+#define SMP_HANDLER_H
+
+#include "wsf_os.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     SmpHandlerInit
+ *        
+ *  \brief  SMP handler init function called during system initialization.
+ *
+ *  \param  handlerID  WSF handler ID for SMP.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void SmpHandlerInit(wsfHandlerId_t handlerId);
+
+
+/*************************************************************************************************/
+/*!
+ *  \fn     SmpHandler
+ *        
+ *  \brief  WSF event handler for SMP.
+ *
+ *  \param  event   WSF event mask.
+ *  \param  pMsg    WSF message.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void SmpHandler(wsfEventMask_t event, wsfMsgHdr_t *pMsg);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* SMP_HANDLER_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/util/bda.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/util/bda.h
new file mode 100644
index 00000000000..5bd96bad0af
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/util/bda.h
@@ -0,0 +1,109 @@
+/*************************************************************************************************/
+/*!
+ *  \file   bda.h
+ *
+ *  \brief  Bluetooth device address utilities.
+ *
+ *          $Date: 2012-05-08 10:58:07 -0700 (Tue, 08 May 2012) $
+ *          $Revision: 316 $
+ *
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef BDA_H
+#define BDA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/*! BD address length */
+#define BDA_ADDR_LEN         6
+
+/*! BD address string length */
+#define BDA_ADDR_STR_LEN    (BDA_ADDR_LEN * 2)
+
+/**************************************************************************************************
+  Data Types
+**************************************************************************************************/
+
+/*! BD address data type */
+typedef uint8_t bdAddr_t[BDA_ADDR_LEN];
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     BdaCpy
+ *        
+ *  \brief  Copy a BD address from source to destination.
+ *
+ *  \param  pDst    Pointer to destination.
+ *  \param  pSrc    Pointer to source.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void BdaCpy(uint8_t *pDst, uint8_t *pSrc);
+
+
+/*************************************************************************************************/
+/*!
+ *  \fn     BdaCmp
+ *        
+ *  \brief  Compare two BD addresses.
+ *
+ *  \param  pAddr1  First address.
+ *  \param  pAddr2  Second address.
+ *
+ *  \return TRUE if addresses match, FALSE otherwise.
+ */
+/*************************************************************************************************/
+bool_t BdaCmp(uint8_t *pAddr1, uint8_t *pAddr2);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     BdaClr
+ *        
+ *  \brief  Set a BD address to all zeros.
+ *
+ *  \param  pDst    Pointer to destination.
+ *
+ *  \return pDst + BDA_ADDR_LEN
+ */
+/*************************************************************************************************/
+uint8_t *BdaClr(uint8_t *pDst);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     Bda2Str
+ *        
+ *  \brief  Convert a BD address to a string.
+ *
+ *  \param  pAddr    Pointer to BD address.
+ *
+ *  \return Pointer to string.
+ */
+/*************************************************************************************************/
+char *Bda2Str(uint8_t *pAddr);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* BDA_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/generic/wsf_os_int.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/generic/wsf_os_int.h
new file mode 100644
index 00000000000..25a4d31a619
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/generic/wsf_os_int.h
@@ -0,0 +1,105 @@
+/*************************************************************************************************/
+/*!
+ *  \file   wsf_os_int.h
+ *        
+ *  \brief  Software foundation OS platform-specific interface file.
+ *
+ *          $Date: 2012-10-01 13:53:07 -0700 (Mon, 01 Oct 2012) $
+ *          $Revision: 357 $
+ *  
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef WSF_OS_INT_H
+#define WSF_OS_INT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/* Task events */
+#define WSF_MSG_QUEUE_EVENT   0x01        /* Message queued for event handler */
+#define WSF_TIMER_EVENT       0x02        /* Timer expired for event handler */
+#define WSF_HANDLER_EVENT     0x04        /* Event set for event handler */
+
+/* Derive task from handler ID */
+#define WSF_TASK_FROM_ID(handlerID)       (((handlerID) >> 4) & 0x0F)
+
+/* Derive handler from handler ID */
+#define WSF_HANDLER_FROM_ID(handlerID)    ((handlerID) & 0x0F)
+
+/**************************************************************************************************
+  Data Types
+**************************************************************************************************/
+
+/* Event handler ID data type */
+typedef uint8_t  wsfHandlerId_t;
+
+/* Event handler event mask data type */
+typedef uint8_t  wsfEventMask_t;
+
+/* Task ID data type */
+typedef wsfHandlerId_t  wsfTaskId_t;
+
+/* Task event mask data type */
+typedef uint8_t wsfTaskEvent_t;
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     wsfOsReadyToSleep
+ *        
+ *  \brief  Check if WSF is ready to sleep.
+ *
+ *  \param  None.
+ *
+ *  \return Return TRUE if there are no pending WSF task events set, FALSE otherwise.
+ */
+/*************************************************************************************************/
+bool_t wsfOsReadyToSleep(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     wsfOsDispatcher
+ *        
+ *  \brief  Event dispatched.  Designed to be called repeatedly from infinite loop.
+ *
+ *  \param  None.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void wsfOsDispatcher(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfOsShutdown
+ *        
+ *  \brief  Shutdown OS.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfOsShutdown(void);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* WSF_OS_INT_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/generic/wsf_types.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/generic/wsf_types.h
new file mode 100644
index 00000000000..421ee6db43f
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/generic/wsf_types.h
@@ -0,0 +1,61 @@
+/*************************************************************************************************/
+/*!
+ *  \file   wsf_types.h
+ *        
+ *  \brief  Platform-independent data types.
+ *
+ *          $Date: 2012-04-28 22:02:14 -0700 (Sat, 28 Apr 2012) $
+ *          $Revision: 306 $
+ *  
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef WSF_TYPES_H
+#define WSF_TYPES_H
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+#ifndef NULL
+#define NULL  0
+#endif
+
+#ifndef TRUE
+#define TRUE  1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/**************************************************************************************************
+  Data Types
+**************************************************************************************************/
+
+/* Integer data types */
+#if ((defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)) && \
+    (__ICC8051__ == 0)) || defined(__CC_ARM) || defined(__IAR_SYSTEMS_ICC__)
+#include <stdint.h>
+#else
+typedef signed char int8_t;
+typedef unsigned char uint8_t;
+typedef signed short int16_t;
+typedef unsigned short uint16_t;
+typedef signed long int32_t;
+typedef unsigned long uint32_t;
+#endif
+
+/* Boolean data type */
+typedef uint8_t bool_t;
+
+#endif /* WSF_TYPES_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_buf.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_buf.h
new file mode 100644
index 00000000000..5dfe19cb4e1
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_buf.h
@@ -0,0 +1,137 @@
+/*************************************************************************************************/
+/*!
+ *  \file   wsf_buf.h
+ *        
+ *  \brief  Buffer pool service.
+ *
+ *          $Date: 2013-05-13 15:20:24 -0700 (Mon, 13 May 2013) $
+ *          $Revision: 612 $
+ *  
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef WSF_BUF_H
+#define WSF_BUF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/*! Length of the buffer statistics array */
+#define WSF_BUF_STATS_MAX_LEN       128
+
+/**************************************************************************************************
+  Data Types
+**************************************************************************************************/
+
+/*! Buffer pool descriptor structure */
+typedef struct
+{
+  uint16_t   len;                  /*! length of buffers in pool */
+  uint8_t    num;                  /*! number of buffers in pool */
+} wsfBufPoolDesc_t;
+
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfBufInit
+ *        
+ *  \brief  Initialize the buffer pool service.  This function should only be called once
+ *          upon system initialization.
+ *
+ *  \param  bufMemLen Length in bytes of memory pointed to by pBufMem.
+ *  \param  pBufMem   Memory in which to store the pools used by the buffer pool service.
+ *  \param  numPools  Number of buffer pools.
+ *  \param  pDesc     Array of buffer pool descriptors, one for each pool.
+ *
+ *  \return TRUE if initialization was successful, FALSE otherwise.
+ */
+/*************************************************************************************************/
+bool_t WsfBufInit(uint16_t bufMemLen, uint8_t *pBufMem, uint8_t numPools, wsfBufPoolDesc_t *pDesc);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfBufAlloc
+ *        
+ *  \brief  Allocate a buffer.
+ *
+ *  \param  len     Length of buffer to allocate.
+ *
+ *  \return Pointer to allocated buffer or NULL if allocation fails.
+ */
+/*************************************************************************************************/
+void *WsfBufAlloc(uint16_t len);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfBufFree
+ *        
+ *  \brief  Free a buffer.
+ *
+ *  \param  pBuf    Buffer to free.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfBufFree(void *pBuf);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfBufGetMaxAlloc
+ *        
+ *  \brief  Diagnostic function to get maximum allocated buffers from a pool.
+ *
+ *  \param  pool    Buffer pool number.
+ *
+ *  \return Number of allocated buffers.
+ */
+/*************************************************************************************************/
+uint8_t WsfBufGetMaxAlloc(uint8_t pool);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfBufGetNumAlloc
+ *        
+ *  \brief  Diagnostic function to get the number of currently allocated buffers in a pool.
+ *
+ *  \param  pool    Buffer pool number.
+ *
+ *  \return Number of allocated buffers.
+ */
+/*************************************************************************************************/
+uint8_t WsfBufGetNumAlloc(uint8_t pool);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfBufGetAllocStats
+ *        
+ *  \brief  Diagnostic function to get the buffer allocation statistics.
+ *
+ *  \return Buffer allocation statistics array.
+ */
+/*************************************************************************************************/
+uint8_t *WsfBufGetAllocStats(void);
+
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* WSF_BUF_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_msg.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_msg.h
new file mode 100644
index 00000000000..f579562e81d
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_msg.h
@@ -0,0 +1,123 @@
+/*************************************************************************************************/
+/*!
+ *  \file   wsf_msg.h
+ *
+ *  \brief  Message passing service.
+ *
+ *          $Date: 2013-07-02 15:08:09 -0700 (Tue, 02 Jul 2013) $
+ *          $Revision: 779 $
+ *
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef WSF_MSG_H
+#define WSF_MSG_H
+
+#include "wsf_queue.h"
+#include "wsf_os.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfMsgAlloc
+ *
+ *  \brief  Allocate a message buffer to be sent with WsfMsgSend().
+ *
+ *  \param  len   Message length in bytes.
+ *
+ *  \return Pointer to message buffer or NULL if allocation failed.
+ */
+/*************************************************************************************************/
+void *WsfMsgAlloc(uint16_t len);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfMsgFree
+ *
+ *  \brief  Free a message buffer allocated with WsfMsgAlloc().
+ *
+ *  \param  pMsg  Pointer to message buffer.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfMsgFree(void *pMsg);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfMsgSend
+ *
+ *  \brief  Send a message to an event handler.
+ *
+ *  \param  handlerId   Event handler ID.
+ *  \param  pMsg        Pointer to message buffer.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfMsgSend(wsfHandlerId_t handlerId, void *pMsg);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfMsgEnq
+ *
+ *  \brief  Enqueue a message.
+ *
+ *  \param  pQueue    Pointer to queue.
+ *  \param  handerId  Set message handler ID to this value.
+ *  \param  pElem     Pointer to message buffer.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfMsgEnq(wsfQueue_t *pQueue, wsfHandlerId_t handlerId, void *pMsg);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfMsgDeq
+ *
+ *  \brief  Dequeue a message.
+ *
+ *  \param  pQueue      Pointer to queue.
+ *  \param  pHandlerId  Handler ID of returned message; this is a return parameter.
+ *
+ *  \return Pointer to message that has been dequeued or NULL if queue is empty.
+ */
+/*************************************************************************************************/
+void *WsfMsgDeq(wsfQueue_t *pQueue, wsfHandlerId_t *pHandlerId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfMsgPeek
+ *
+ *  \brief  Get the next message without removing it from the queue.
+ *
+ *  \param  pQueue      Pointer to queue.
+ *  \param  pHandlerId  Handler ID of returned message; this is a return parameter.
+ *
+ *  \return Pointer to the next message on the queue or NULL if queue is empty.
+ */
+/*************************************************************************************************/
+void *WsfMsgPeek(wsfQueue_t *pQueue, wsfHandlerId_t *pHandlerId);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* WSF_MSG_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_os.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_os.h
new file mode 100644
index 00000000000..c755e5ad1b3
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_os.h
@@ -0,0 +1,147 @@
+/*************************************************************************************************/
+/*!
+ *  \file   wsf_os.h
+ *        
+ *  \brief  Software foundation OS API.
+ *
+ *          $Date: 2012-10-22 14:09:36 -0700 (Mon, 22 Oct 2012) $
+ *          $Revision: 359 $
+ *  
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef WSF_OS_H
+#define WSF_OS_H
+
+#include "wsf_os_int.h"
+#include "wsf_queue.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Data Types
+**************************************************************************************************/
+
+/*! Common message structure passed to event handler */
+typedef struct
+{
+  uint16_t        param;          /*! General purpose parameter passed to event handler */
+  uint8_t         event;          /*! General purpose event value passed to event handler */
+  uint8_t         status;         /*! General purpose status value passed to event handler */
+} wsfMsgHdr_t;
+
+/**************************************************************************************************
+  Callback Function Types
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     wsfEventHandler_t
+ *        
+ *  \brief  Event handler callback function.
+ *
+ *  \param  event    Mask of events set for the event handler.
+ *  \param  pMsg     Pointer to message for the event handler.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+typedef void (*wsfEventHandler_t)(wsfEventMask_t event, wsfMsgHdr_t *pMsg);
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfSetEvent
+ *        
+ *  \brief  Set an event for an event handler.
+ *
+ *  \param  handlerId   Handler ID.
+ *  \param  event       Event or events to set.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfSetEvent(wsfHandlerId_t handlerId, wsfEventMask_t event);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfTaskLock
+ *        
+ *  \brief  Lock task scheduling.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfTaskLock(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfTaskUnlock
+ *        
+ *  \brief  Unlock task scheduling.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfTaskUnlock(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfTaskSetReady
+ *        
+ *  \brief  Set the task used by the given handler as ready to run.
+ *
+ *  \param  handlerId   Event handler ID.
+ *  \param  event       Task event mask.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfTaskSetReady(wsfHandlerId_t handlerId, wsfTaskEvent_t event);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfTaskMsgQueue
+ *        
+ *  \brief  Return the task message queue used by the given handler.
+ *
+ *  \param  handlerId   Event handler ID.
+ *
+ *  \return Task message queue.
+ */
+/*************************************************************************************************/
+wsfQueue_t *WsfTaskMsgQueue(wsfHandlerId_t handlerId);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfOsSetNextHandler
+ *        
+ *  \brief  Set the next WSF handler function in the WSF OS handler array.  This function
+ *          should only be called as part of the OS initialization procedure.
+ *
+ *  \param  handler    WSF handler function.
+ *
+ *  \return WSF handler ID for this handler.
+ */
+/*************************************************************************************************/
+wsfHandlerId_t WsfOsSetNextHandler(wsfEventHandler_t handler);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* WSF_OS_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_queue.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_queue.h
new file mode 100644
index 00000000000..c3a607298e9
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_queue.h
@@ -0,0 +1,155 @@
+/*************************************************************************************************/
+/*!
+ *  \file   wsf_queue.h
+ *        
+ *  \brief  General purpose queue service.
+ *
+ *          $Date: 2011-10-14 21:35:03 -0700 (Fri, 14 Oct 2011) $
+ *          $Revision: 191 $
+ *  
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef WSF_QUEUE_H
+#define WSF_QUEUE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/*! Initialize a queue */
+#define WSF_QUEUE_INIT(pQueue)          {(pQueue)->pHead = NULL; (pQueue)->pTail = NULL;}
+
+/**************************************************************************************************
+  Data Types
+**************************************************************************************************/
+
+/*! Queue structure */
+typedef struct
+{
+  void      *pHead;         /*! head of queue */
+  void      *pTail;         /*! tail of queue */
+} wsfQueue_t;
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfQueueEnq
+ *        
+ *  \brief  Enqueue an element to the tail of a queue.
+ *
+ *  \param  pQueue    Pointer to queue.
+ *  \param  pElem     Pointer to element.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfQueueEnq(wsfQueue_t *pQueue, void *pElem);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfQueueDeq
+ *        
+ *  \brief  Dequeue an element from the head of a queue.
+ *
+ *  \param  pQueue    Pointer to queue.
+ *
+ *  \return Pointer to element that has been dequeued or NULL if queue is empty.
+ */
+/*************************************************************************************************/
+void *WsfQueueDeq(wsfQueue_t *pQueue);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfQueuePush
+ *        
+ *  \brief  Push an element to the head of a queue.
+ *
+ *  \param  pQueue    Pointer to queue.
+ *  \param  pElem     Pointer to element.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfQueuePush(wsfQueue_t *pQueue, void *pElem);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfQueueInsert
+ *        
+ *  \brief  Insert an element into a queue.  This function is typically used when iterating
+ *          over a queue.
+ *
+ *  \param  pQueue    Pointer to queue.
+ *  \param  pElem     Pointer to element to be inserted.
+ *  \param  pPrev     Pointer to previous element in the queue before element to be inserted.
+ *                    Note:  set pPrev to NULL if pElem is first element in queue.
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfQueueInsert(wsfQueue_t *pQueue, void *pElem, void *pPrev);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfQueueRemove
+ *        
+ *  \brief  Remove an element from a queue.  This function is typically used when iterating
+ *          over a queue.
+ *
+ *  \param  pQueue    Pointer to queue.
+ *  \param  pElem     Pointer to element to be removed.
+ *  \param  pPrev     Pointer to previous element in the queue before element to be removed.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfQueueRemove(wsfQueue_t *pQueue, void *pElem, void *pPrev);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfQueueCount
+ *        
+ *  \brief  Count the number of elements in a queue.
+ *
+ *  \param  pQueue    Pointer to queue.
+ *
+ *  \return Number of elements in queue.
+ */
+/*************************************************************************************************/
+uint16_t WsfQueueCount(wsfQueue_t *pQueue);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfQueueEmpty
+ *        
+ *  \brief  Return TRUE if queue is empty.
+ *
+ *  \param  pQueue    Pointer to queue.
+ *
+ *  \return TRUE if queue is empty, FALSE otherwise.
+ */
+/*************************************************************************************************/
+bool_t WsfQueueEmpty(wsfQueue_t *pQueue);
+
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* WSF_QUEUE_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_sec.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_sec.h
new file mode 100644
index 00000000000..d25a50c566d
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_sec.h
@@ -0,0 +1,111 @@
+/*************************************************************************************************/
+/*!
+ *  \file   wsf_sec.h
+ *        
+ *  \brief  AES and random number security service API.
+ *
+ *          $Date: 2011-10-14 21:35:03 -0700 (Fri, 14 Oct 2011) $
+ *          $Revision: 191 $
+ *  
+ *  Copyright (c) 2010-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+
+ */
+/*************************************************************************************************/
+#ifndef WSF_SEC_H
+#define WSF_SEC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Data Types
+**************************************************************************************************/
+
+/*! AES callback parameters structure */
+typedef struct
+{
+  wsfMsgHdr_t   hdr;              /*! header */
+  uint8_t       *pCiphertext;     /*! pointer to 16 bytes of ciphertext data */
+} wsfSecAes_t;
+
+/*! AES callback function type */
+typedef void (*wsfSecAesCback_t)(wsfSecAes_t *pMsg);
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfSecInit
+ *        
+ *  \brief  Initialize the security service.  This function should only be called once
+ *          upon system initialization.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfSecInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfSecRandInit
+ *        
+ *  \brief  Initialize the random number service.  This function should only be called once
+ *          upon system initialization.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfSecRandInit(void);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfSecAes
+ *        
+ *  \brief  Execute an AES calculation.  When the calculation completes, a WSF message will be
+ *          sent to the specified handler.  This function returns a token value that
+ *          the client can use to match calls to this function with messages.
+ *
+ *  \param  pKey        Pointer to 16 byte key.
+ *  \param  pPlaintext  Pointer to 16 byte plaintext.
+ *  \param  handlerId   WSF handler ID.
+ *  \param  param       Client-defined parameter returned in message.
+ *  \param  event       Event for client's WSF handler.
+ *
+ *  \return Token value.
+ */
+/*************************************************************************************************/
+uint8_t WsfSecAes(uint8_t *pKey, uint8_t *pPlaintext, wsfHandlerId_t handlerId,
+                  uint16_t param, uint8_t event);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfSecRand
+ *        
+ *  \brief  This function returns up to 16 bytes of random data to a buffer provided by the
+ *          client.
+ *
+ *  \param  pRand       Pointer to returned random data.
+ *  \param  randLen     Length of random data.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfSecRand(uint8_t *pRand, uint8_t randLen);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* WSF_SEC_H */
diff --git a/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_timer.h b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_timer.h
new file mode 100644
index 00000000000..c849d7a70e2
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_Maxim/exactLE/wsf/include/wsf_timer.h
@@ -0,0 +1,161 @@
+/*************************************************************************************************/
+/*!
+ *  \file   wsf_timer.h
+ *
+ *  \brief  Timer service.
+ *
+ *          $Date: 2013-07-19 17:17:05 -0700 (Fri, 19 Jul 2013) $
+ *          $Revision: 843 $
+ *
+ *  Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: LicenseRef-PBL
+ *
+ *  Licensed under the Permissive Binary License, Version 1.0 (the "License"); you may not use
+ *  this file except in compliance with the License.  You may obtain a copy of the License at
+ *
+ *  https://www.mbed.com/licenses/PBL-1.0
+ *
+ *  See the License for the specific language governing permissions and limitations under the License.
+ */
+/*************************************************************************************************/
+#ifndef WSF_TIMER_H
+#define WSF_TIMER_H
+
+#include "wsf_os.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************************************
+  Macros
+**************************************************************************************************/
+
+/**************************************************************************************************
+  Data Types
+**************************************************************************************************/
+
+/*! Timer ticks data type */
+typedef uint16_t wsfTimerTicks_t;
+
+/*! Timer structure */
+typedef struct wsfTimer_tag
+{
+  struct wsfTimer_tag *pNext;             /*! pointer to next timer in queue */
+  wsfTimerTicks_t     ticks;              /*! number of ticks until expiration */
+  wsfHandlerId_t      handlerId;          /*! event handler for this timer */
+  bool_t              isStarted;          /*! TRUE if timer has been started */
+  wsfMsgHdr_t         msg;                /*! application-defined timer event parameters */
+} wsfTimer_t;
+
+
+/**************************************************************************************************
+  Function Declarations
+**************************************************************************************************/
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfTimerInit
+ *
+ *  \brief  Initialize the timer service.  This function should only be called once
+ *          upon system initialization.
+ *
+ *  \param  msPerTick   Sets the number of milliseconds per timer tick.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfTimerInit(uint8_t msPerTick);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfTimerStartSec
+ *
+ *  \brief  Start a timer in units of seconds.  Before this function is called parameter
+ *          pTimer->handlerId must be set to the event handler for this timer and parameter
+ *          pTimer->msg must be set to any application-defined timer event parameters.
+ *
+ *  \param  pTimer  Pointer to timer.
+ *  \param  sec     Seconds until expiration.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfTimerStartSec(wsfTimer_t *pTimer, wsfTimerTicks_t sec);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfTimerStartMs
+ *
+ *  \brief  Start a timer in units of milliseconds.
+ *
+ *  \param  pTimer  Pointer to timer.
+ *  \param  ms      Milliseconds until expiration.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfTimerStartMs(wsfTimer_t *pTimer, wsfTimerTicks_t ms);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfTimerStop
+ *
+ *  \brief  Stop a timer.
+ *
+ *  \param  pTimer  Pointer to timer.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfTimerStop(wsfTimer_t *pTimer);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfTimerUpdate
+ *
+ *  \brief  Update the timer service with the number of elapsed ticks.  This function is
+ *          typically called only from timer porting code.
+ *
+ *  \param  ticks  Number of ticks since last update.
+ *
+ *  \return None.
+ */
+/*************************************************************************************************/
+void WsfTimerUpdate(wsfTimerTicks_t ticks);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfTimerNextExpiration
+ *
+ *  \brief  Return the number of ticks until the next timer expiration.  Note that this
+ *          function can return zero even if a timer is running, indicating the timer
+ *          has expired but has not yet been serviced.
+ *
+ *  \param  pTimerRunning   Returns TRUE if a timer is running, FALSE if no timers running.
+ *
+ *  \return The number of ticks until the next timer expiration.
+ */
+/*************************************************************************************************/
+wsfTimerTicks_t WsfTimerNextExpiration(bool_t *pTimerRunning);
+
+/*************************************************************************************************/
+/*!
+ *  \fn     WsfTimerServiceExpired
+ *
+ *  \brief  Service expired timers for the given task.  This function is typically called only
+ *          WSF OS porting code.
+ *
+ *  \param  taskId      OS Task ID of task servicing timers.
+ *
+ *  \return Pointer to next expired timer or NULL if there are no expired timers.
+ */
+/*************************************************************************************************/
+wsfTimer_t *WsfTimerServiceExpired(wsfTaskId_t taskId);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif /* WSF_TIMER_H */
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_ARM_STD/exactLE.ar b/targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_ARM_STD/exactLE.ar
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diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_GCC_ARM/libexactLE.a b/targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_GCC_ARM/libexactLE.a
index 9a2c2f8fbaa52272d499b72c54d21f2ce5a77c9e..ecc6df531e513aa5aea9e033c7ebc8ccc480f2ed 100644
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Dd=^gn

diff --git a/targets/targets.json b/targets/targets.json
index a6520b94cd6..e2b2f7f56ac 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -1705,6 +1705,7 @@
         "extra_labels": ["Maxim", "MAX32610"],
         "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+        "features": ["BLE"],
         "release_versions": ["2", "5"]
     },
     "MAX32600MBED": {
@@ -1723,6 +1724,7 @@
         "extra_labels": ["Maxim", "MAX32620"],
         "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
         "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "features": ["BLE"],
         "release_versions": ["2", "5"]
     },
     "EFM32GG_STK3700": {

From 29eb75c0b568c68eb887b263c1d72b1b2dc5a5e4 Mon Sep 17 00:00:00 2001
From: Jeremy Brodt <jeremy.brodt@maximintegrated.com>
Date: Thu, 6 Oct 2016 10:21:43 -0500
Subject: [PATCH 16/89] Reduced system clock speed due to SPI issue.

---
 .../TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c    | 5 ++---
 targets/TARGET_Maxim/mbed_rtx.h                              | 2 +-
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c b/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c
index d3e6b77e147..0e46ae3bbf5 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c
@@ -53,7 +53,7 @@ static uint8_t running;
 // NOTE: Setting the CMSIS SystemCoreClock value to the actual value it will
 // be AFTER SystemInit() runs.  This is required so the hal drivers will have
 // the correct value when the DATA sections are initialized.
-uint32_t SystemCoreClock = RO_FREQ;
+uint32_t SystemCoreClock = RO_FREQ / 2;
 
 void SystemCoreClockUpdate(void)
 {
@@ -147,10 +147,9 @@ void SystemInit(void)
 
     low_level_init();
 
-    // Select 96MHz ring oscillator as clock source
+    // Select 48MHz ring oscillator as clock source
     uint32_t reg = MXC_CLKMAN->clk_ctrl;
     reg &= ~MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT;
-    reg |= 1 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS;
     MXC_CLKMAN->clk_ctrl = reg;
 
     // Copy trim information from shadow registers into power manager registers
diff --git a/targets/TARGET_Maxim/mbed_rtx.h b/targets/TARGET_Maxim/mbed_rtx.h
index d719cae00ea..f8ad272f5fc 100644
--- a/targets/TARGET_Maxim/mbed_rtx.h
+++ b/targets/TARGET_Maxim/mbed_rtx.h
@@ -59,7 +59,7 @@
 #define OS_MAINSTKSIZE          256
 #endif
 #ifndef OS_CLOCK
-#define OS_CLOCK                96000000
+#define OS_CLOCK                48000000
 #endif
 
 #endif

From 5221345b4c6a6dd65943d1c7af64bae433f1cdc8 Mon Sep 17 00:00:00 2001
From: Jeremy Brodt <jeremy.brodt@maximintegrated.com>
Date: Mon, 10 Oct 2016 08:50:07 -0500
Subject: [PATCH 17/89] Updated BLE library and stack/heap size.

---
 .../TOOLCHAIN_ARM_STD/exactLE.ar              | Bin 429522 -> 3108484 bytes
 .../TOOLCHAIN_GCC_ARM/libexactLE.a            | Bin 966844 -> 1173804 bytes
 .../TARGET_MAX32610/TOOLCHAIN_IAR/exactLE.a   | Bin 424398 -> 3116108 bytes
 .../TOOLCHAIN_GCC_ARM/startup_max32610.S      |   4 ++--
 .../device/TOOLCHAIN_IAR/MAX32610.icf         |   4 ++--
 5 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/targets/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/exactLE.ar b/targets/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/exactLE.ar
index 54828bf2ff3bc8eee184d4fc6e7d6375b5ee12c1..3df62abfba94aa9e59f80c2f3c1fce73f7142689 100644
GIT binary patch
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diff --git a/targets/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/libexactLE.a b/targets/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/libexactLE.a
index 996a08ba8f2d099c40f4a121713fcb411d576c98..7ac5141b89d6ca15664797c917ad7cf2c066c72c 100644
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Wzqji_$8f*%Z|Qeg{7idby8j11(j~$G

diff --git a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_GCC_ARM/startup_max32610.S b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_GCC_ARM/startup_max32610.S
index 227ecb3565d..31af57d3158 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_GCC_ARM/startup_max32610.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_GCC_ARM/startup_max32610.S
@@ -51,7 +51,7 @@
 #ifdef __STACK_SIZE
     .equ    Stack_Size, __STACK_SIZE
 #else
-    .equ    Stack_Size, 0x00001000
+    .equ    Stack_Size, 0x00000800
 #endif
     .globl    __StackTop
     .globl    __StackLimit
@@ -66,7 +66,7 @@ __StackTop:
 #ifdef __HEAP_SIZE
     .equ    Heap_Size, __HEAP_SIZE
 #else
-    .equ    Heap_Size, 0x00004000
+    .equ    Heap_Size, 0x00003000
 #endif
     .globl    __HeapBase
     .globl    __HeapLimit
diff --git a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/MAX32610.icf b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/MAX32610.icf
index 3e0cd5e85f0..96d5c1555b1 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/MAX32610.icf
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/device/TOOLCHAIN_IAR/MAX32610.icf
@@ -15,8 +15,8 @@ define region ROM_region      = mem:[from __region_ROM_start__   to __region_ROM
 define region RAM_region      = mem:[from __region_RAM_start__   to __region_RAM_end__];
 
 /* Stack and Heap */
-define symbol __size_cstack__ = 0x1000;
-define symbol __size_heap__   = 0x4000;
+define symbol __size_cstack__ = 0x0800;
+define symbol __size_heap__   = 0x3000;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };
 

From 21ab8682a66684739634eec799dddace8ea68b5b Mon Sep 17 00:00:00 2001
From: Jeremy Brodt <jeremy.brodt@maximintegrated.com>
Date: Wed, 12 Oct 2016 09:07:03 -0500
Subject: [PATCH 18/89] Reduced stack/heap size due to mbed test failures.

---
 .../device/TOOLCHAIN_GCC_ARM/startup_max32600.S               | 4 ++--
 .../TARGET_MAX32600/device/TOOLCHAIN_IAR/MAX32600.icf         | 4 ++--
 .../device/TOOLCHAIN_GCC_ARM/startup_max32620.S               | 2 +-
 .../TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf         | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_GCC_ARM/startup_max32600.S b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_GCC_ARM/startup_max32600.S
index 227ecb3565d..31af57d3158 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_GCC_ARM/startup_max32600.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_GCC_ARM/startup_max32600.S
@@ -51,7 +51,7 @@
 #ifdef __STACK_SIZE
     .equ    Stack_Size, __STACK_SIZE
 #else
-    .equ    Stack_Size, 0x00001000
+    .equ    Stack_Size, 0x00000800
 #endif
     .globl    __StackTop
     .globl    __StackLimit
@@ -66,7 +66,7 @@ __StackTop:
 #ifdef __HEAP_SIZE
     .equ    Heap_Size, __HEAP_SIZE
 #else
-    .equ    Heap_Size, 0x00004000
+    .equ    Heap_Size, 0x00003000
 #endif
     .globl    __HeapBase
     .globl    __HeapLimit
diff --git a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/MAX32600.icf b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/MAX32600.icf
index 3e0cd5e85f0..96d5c1555b1 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/MAX32600.icf
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/device/TOOLCHAIN_IAR/MAX32600.icf
@@ -15,8 +15,8 @@ define region ROM_region      = mem:[from __region_ROM_start__   to __region_ROM
 define region RAM_region      = mem:[from __region_RAM_start__   to __region_RAM_end__];
 
 /* Stack and Heap */
-define symbol __size_cstack__ = 0x1000;
-define symbol __size_heap__   = 0x4000;
+define symbol __size_cstack__ = 0x0800;
+define symbol __size_heap__   = 0x3000;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };
 
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/startup_max32620.S b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/startup_max32620.S
index 12006b3247b..d844878c8b7 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/startup_max32620.S
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_GCC_ARM/startup_max32620.S
@@ -51,7 +51,7 @@
 #ifdef __STACK_SIZE
     .equ    Stack_Size, __STACK_SIZE
 #else
-    .equ    Stack_Size, 0x00002000
+    .equ    Stack_Size, 0x00001000
 #endif
     .globl    __StackTop
     .globl    __StackLimit
diff --git a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf
index 203c221868c..7edf37819cb 100644
--- a/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/device/TOOLCHAIN_IAR/MAX32620.icf
@@ -15,7 +15,7 @@ define region ROM_region      = mem:[from __region_ROM_start__   to __region_ROM
 define region RAM_region      = mem:[from __region_RAM_start__   to __region_RAM_end__];
 
 /* Stack and Heap */
-define symbol __size_cstack__ = 0x2000;
+define symbol __size_cstack__ = 0x1000;
 define symbol __size_heap__   = 0x4000;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };

From 69c2feb512ea00b00183f4d44d82d698fd9de7a4 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Wed, 3 Aug 2016 14:06:44 +0800
Subject: [PATCH 19/89] Add NUC472 support for USBH

---
 .../USBHost/USBHost/USBHostTypes.h            |   3 +
 .../USBHost/USBHost/USBHALHost_NUC472.cpp     | 361 ++++++++++++++++++
 .../device/StdDriver/nuc472_clk.h             |   4 +-
 3 files changed, 366 insertions(+), 2 deletions(-)
 create mode 100644 libraries/USBHost/USBHost/USBHALHost_NUC472.cpp

diff --git a/features/unsupported/USBHost/USBHost/USBHostTypes.h b/features/unsupported/USBHost/USBHost/USBHostTypes.h
index 23daefaf55b..5d9dd22968f 100644
--- a/features/unsupported/USBHost/USBHost/USBHostTypes.h
+++ b/features/unsupported/USBHost/USBHost/USBHostTypes.h
@@ -72,7 +72,10 @@ enum ENDPOINT_TYPE {
 #define  OR_CONTROL_CLE                 0x00000010
 #define  OR_CONTROL_BLE                 0x00000020
 #define  OR_CONTROL_HCFS                0x000000C0
+#define  OR_CONTROL_HC_RSET             0x00000000
+#define  OR_CONTROL_HC_RES              0x00000040
 #define  OR_CONTROL_HC_OPER             0x00000080
+#define  OR_CONTROL_HC_SUSP             0x000000C0
 // ----------------- HcCommandStatus Register -----------------
 #define  OR_CMD_STATUS_HCR              0x00000001
 #define  OR_CMD_STATUS_CLF              0x00000002
diff --git a/libraries/USBHost/USBHost/USBHALHost_NUC472.cpp b/libraries/USBHost/USBHost/USBHALHost_NUC472.cpp
new file mode 100644
index 00000000000..e0fdca2c170
--- /dev/null
+++ b/libraries/USBHost/USBHost/USBHALHost_NUC472.cpp
@@ -0,0 +1,361 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(TARGET_NUC472)
+
+#include "mbed.h"
+#include "USBHALHost.h"
+#include "dbg.h"
+#include "pinmap.h"
+
+#define HCCA_SIZE   sizeof(HCCA)
+#define ED_SIZE     sizeof(HCED)
+#define TD_SIZE     sizeof(HCTD)
+
+#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
+
+static volatile MBED_ALIGN(256) uint8_t usb_buf[TOTAL_SIZE];  // 256 bytes aligned!
+
+USBHALHost * USBHALHost::instHost;
+
+USBHALHost::USBHALHost()
+{
+    instHost = this;
+    memInit();
+    memset((void*)usb_hcca, 0, HCCA_SIZE);
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        edBufAlloc[i] = false;
+    }
+    for (int i = 0; i < MAX_TD; i++) {
+        tdBufAlloc[i] = false;
+    }
+}
+
+void USBHALHost::init()
+{
+    // Unlock protected registers
+    SYS_UnlockReg();
+    
+    // NOTE: Configure as OTG device first; otherwise, program will trap in wait loop CLK_STATUS_PLL2STB_Msk below.
+    SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk | SYS_USBPHY_USBROLE_ON_THE_GO;
+    
+    // NOTE: Enable OTG here; otherwise, program will trap in wait loop CLK_STATUS_PLL2STB_Msk below.
+    CLK_EnableModuleClock(OTG_MODULE);
+    OTG->PHYCTL = (OTG->PHYCTL | OTG_PHYCTL_OTGPHYEN_Msk) & ~OTG_PHYCTL_IDDETEN_Msk;
+    //OTG->CTL |= OTG_CTL_OTGEN_Msk | OTG_CTL_BUSREQ_Msk;
+    
+    // PB.0: USB0 external VBUS regulator status
+    // USB_OC
+    // PB.1: USB0 external VBUS regulator enable
+    // NCT3520U low active (USB_PWR_EN)
+    pin_function(PB_0, SYS_GPB_MFPL_PB0MFP_USB0_OTG5V_ST);
+    pin_function(PB_1, SYS_GPB_MFPL_PB1MFP_USB0_OTG5V_EN);
+
+    // PB.2: USB1 differential signal D-
+    // PB.3: USB1 differential signal D+
+    //pin_function(PB_2, SYS_GPB_MFPL_PB2MFP_USB1_D_N);
+    //pin_function(PB_3, SYS_GPB_MFPL_PB3MFP_USB1_D_P);
+
+    // Set PB.4 output high to enable USB power
+    //gpio_t gpio;
+    //gpio_init_out_ex(&gpio, PB_4, 1);
+    
+    // NOTE:
+    // 1. Set USBH clock source to PLL2; otherwise, program will trap in wait loop CLK_STATUS_PLL2STB_Msk below.
+    // 2. Don't set CLK_PLL2CTL_PLL2CKEN_Msk. USBH will work abnormally with it enabled.
+    CLK->CLKSEL0 &= ~CLK_CLKSEL0_USBHSEL_Msk;
+    // Enable PLL2, 480 MHz / 2 / (1+4) => 48 MHz output
+    CLK->PLL2CTL = /*CLK_PLL2CTL_PLL2CKEN_Msk | */ (4 << CLK_PLL2CTL_PLL2DIV_Pos);
+    // Wait PLL2 stable ...
+    while (!(CLK->STATUS & CLK_STATUS_PLL2STB_Msk));
+    
+    // Select USB Host clock source from PLL2, clock divied by 1
+    CLK_SetModuleClock(USBH_MODULE, CLK_CLKSEL0_USBHSEL_PLL2, CLK_CLKDIV0_USB(1));
+    
+    // Enable USB Host clock
+    CLK_EnableModuleClock(USBH_MODULE);
+    
+    // Lock protected registers
+    SYS_LockReg();
+    
+    // Overcurrent flag is high active
+    USBH->HcMiscControl &= ~USBH_HcMiscControl_OCAL_Msk;
+    
+    // Disable HC interrupts
+    USBH->HcInterruptDisable = OR_INTR_ENABLE_MIE;
+
+    // Needed by some controllers
+    USBH->HcControl = 0;
+
+    // Software reset
+    USBH->HcCommandStatus = OR_CMD_STATUS_HCR;
+    while (USBH->HcCommandStatus & OR_CMD_STATUS_HCR);
+
+    // Put HC in reset state
+    USBH->HcControl = (USBH->HcControl & ~OR_CONTROL_HCFS) | OR_CONTROL_HC_RSET;
+    // HCD must wait 10ms for HC reset complete
+    wait_ms(100);
+    
+    USBH->HcControlHeadED = 0;                      // Initialize Control ED list head to 0
+    USBH->HcBulkHeadED = 0;                         // Initialize Bulk ED list head to 0
+    USBH->HcHCCA = (uint32_t) usb_hcca;
+
+    USBH->HcFmInterval = DEFAULT_FMINTERVAL;        // Frame interval = 12000 - 1
+                                                    // MPS = 10,104
+    USBH->HcPeriodicStart = FI * 90 / 100;          // 90% of frame interval
+    USBH->HcLSThreshold = 0x628;                    // Low speed threshold
+
+    // Put HC in operational state
+    USBH->HcControl  = (USBH->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
+
+    // FIXME: Ports are power switched. All ports are powered at the same time. Doesn't match BSP sample.
+    USBH->HcRhDescriptorA = USBH->HcRhDescriptorA & ~USBH_HcRhDescriptorA_NPS_Msk & ~USBH_HcRhDescriptorA_PSM_Msk;
+    // Issue SetGlobalPower command
+    USBH->HcRhStatus = USBH_HcRhStatus_LPSC_Msk;
+    // Power On To Power Good Time, in 2 ms units
+    wait_ms(((USBH->HcRhDescriptorA & USBH_HcRhDescriptorA_POTPGT_Msk) >> USBH_HcRhDescriptorA_POTPGT_Pos) * 2);
+    
+    // Clear Interrrupt Status
+    USBH->HcInterruptStatus |= USBH->HcInterruptStatus;
+    // Enable interrupts we care about
+    USBH->HcInterruptEnable  = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
+
+
+    // Unlock protected registers
+    SYS_UnlockReg();
+    
+    // NOTE: Configure as USB host after USBH init above; otherwise system will crash.
+    SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | SYS_USBPHY_USBROLE_STD_USBH;
+    
+    // Lock protected registers
+    SYS_LockReg();
+    
+    NVIC_SetVector(USBH_IRQn, (uint32_t)(_usbisr));
+    NVIC_EnableIRQ(USBH_IRQn);
+    
+    // Check for any connected devices
+    if (USBH->HcRhPortStatus[0] & OR_RH_PORT_CCS) {
+        // Device connected
+        wait_ms(150);
+        deviceConnected(0, 1, USBH->HcRhPortStatus[0] & OR_RH_PORT_LSDA);
+    }
+}
+
+uint32_t USBHALHost::controlHeadED()
+{
+    return USBH->HcControlHeadED;
+}
+
+uint32_t USBHALHost::bulkHeadED()
+{
+    return USBH->HcBulkHeadED;
+}
+
+uint32_t USBHALHost::interruptHeadED()
+{
+    // FIXME: Only support one INT ED?
+    return usb_hcca->IntTable[0];
+}
+
+void USBHALHost::updateBulkHeadED(uint32_t addr)
+{
+    USBH->HcBulkHeadED = addr;
+}
+
+
+void USBHALHost::updateControlHeadED(uint32_t addr)
+{
+    USBH->HcControlHeadED = addr;
+}
+
+void USBHALHost::updateInterruptHeadED(uint32_t addr)
+{
+    // FIXME: Only support one INT ED?
+    usb_hcca->IntTable[0] = addr;
+}
+
+
+void USBHALHost::enableList(ENDPOINT_TYPE type)
+{
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            USBH->HcCommandStatus = OR_CMD_STATUS_CLF;
+            USBH->HcControl |= OR_CONTROL_CLE;
+            break;
+        case ISOCHRONOUS_ENDPOINT:
+            // FIXME
+            break;
+        case BULK_ENDPOINT:
+            USBH->HcCommandStatus = OR_CMD_STATUS_BLF;
+            USBH->HcControl |= OR_CONTROL_BLE;
+            break;
+        case INTERRUPT_ENDPOINT:
+            USBH->HcControl |= OR_CONTROL_PLE;
+            break;
+    }
+}
+
+
+bool USBHALHost::disableList(ENDPOINT_TYPE type)
+{
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            if(USBH->HcControl & OR_CONTROL_CLE) {
+                USBH->HcControl &= ~OR_CONTROL_CLE;
+                return true;
+            }
+            return false;
+        case ISOCHRONOUS_ENDPOINT:
+            // FIXME
+            return false;
+        case BULK_ENDPOINT:
+            if(USBH->HcControl & OR_CONTROL_BLE){
+                USBH->HcControl &= ~OR_CONTROL_BLE;
+                return true;
+            }
+            return false;
+        case INTERRUPT_ENDPOINT:
+            if(USBH->HcControl & OR_CONTROL_PLE) {
+                USBH->HcControl &= ~OR_CONTROL_PLE;
+                return true;
+            }
+            return false;
+    }
+    return false;
+}
+
+
+void USBHALHost::memInit()
+{
+    usb_hcca = (volatile HCCA *)usb_buf;
+    usb_edBuf = usb_buf + HCCA_SIZE;
+    usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
+}
+
+volatile uint8_t * USBHALHost::getED()
+{
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        if ( !edBufAlloc[i] ) {
+            edBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
+        }
+    }
+    perror("Could not allocate ED\r\n");
+    return NULL; //Could not alloc ED
+}
+
+volatile uint8_t * USBHALHost::getTD()
+{
+    int i;
+    for (i = 0; i < MAX_TD; i++) {
+        if ( !tdBufAlloc[i] ) {
+            tdBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
+        }
+    }
+    perror("Could not allocate TD\r\n");
+    return NULL; //Could not alloc TD
+}
+
+
+void USBHALHost::freeED(volatile uint8_t * ed)
+{
+    int i;
+    i = (ed - usb_edBuf) / ED_SIZE;
+    edBufAlloc[i] = false;
+}
+
+void USBHALHost::freeTD(volatile uint8_t * td)
+{
+    int i;
+    i = (td - usb_tdBuf) / TD_SIZE;
+    tdBufAlloc[i] = false;
+}
+
+
+void USBHALHost::resetRootHub()
+{
+    // Reset port1
+    USBH->HcRhPortStatus[0] = OR_RH_PORT_PRS;
+    while (USBH->HcRhPortStatus[0] & OR_RH_PORT_PRS);
+    USBH->HcRhPortStatus[0] = OR_RH_PORT_PRSC;
+}
+
+
+void USBHALHost::_usbisr(void)
+{
+    if (instHost) {
+        instHost->UsbIrqhandler();
+    }
+}
+
+void USBHALHost::UsbIrqhandler()
+{
+    uint32_t ints = USBH->HcInterruptStatus;
+    
+    // Root hub status change interrupt
+    if (ints & OR_INTR_STATUS_RHSC) {
+        uint32_t ints_roothub = USBH->HcRhStatus;
+        uint32_t ints_port1 = USBH->HcRhPortStatus[0];
+        
+        if (ints_port1 & OR_RH_PORT_CSC) {
+            if (ints_roothub & OR_RH_STATUS_DRWE) {
+                // When DRWE is on, Connect Status Change means a remote wakeup event.
+            } else {
+                if (ints_port1 & OR_RH_PORT_CCS) {
+                    // Root device connected
+                    
+                    // wait 150ms to avoid bounce
+                    wait_ms(150);
+
+                    //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
+                    deviceConnected(0, 1, ints_port1 & OR_RH_PORT_LSDA);
+                } else {
+                    // Root device disconnected
+                    
+                    if (!(ints & OR_INTR_STATUS_WDH)) {
+                        usb_hcca->DoneHead = 0;
+                    }
+
+                    // wait 200ms to avoid bounce
+                    wait_ms(200);
+
+                    deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
+
+                    if (ints & OR_INTR_STATUS_WDH) {
+                        usb_hcca->DoneHead = 0;
+                        USBH->HcInterruptStatus = OR_INTR_STATUS_WDH;
+                    }
+                }
+            }
+            USBH->HcRhPortStatus[0] = OR_RH_PORT_CSC;
+        }
+        
+        // Reset completed
+        if (ints_port1 & OR_RH_PORT_PRSC) {
+            USBH->HcRhPortStatus[0] = OR_RH_PORT_PRSC;
+        }
+        
+        USBH->HcInterruptStatus = OR_INTR_STATUS_RHSC;
+    }
+
+    // Writeback Done Head interrupt
+    if (ints & OR_INTR_STATUS_WDH) {
+        transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
+        USBH->HcInterruptStatus = OR_INTR_STATUS_WDH;
+    }
+}
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_clk.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_clk.h
index df51c2159f7..23ccf398226 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_clk.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_clk.h
@@ -92,8 +92,8 @@ extern "C"
 #define CLK_CLKSEL0_PCLKSEL_HCLK   (0x00UL<<CLK_CLKSEL0_PCLKSEL_Pos)    /*!< Setting clock source as HCLK  \hideinitializer */
 #define CLK_CLKSEL0_PCLKSEL_HCLK_DIV2  (0x01UL<<CLK_CLKSEL0_PCLKSEL_Pos)    /*!< Setting clock source as HCLK/2  \hideinitializer */
 
-#define CLK_CLKSEL0_USBHSEL_PLL   (0x00UL<<CLK_CLKSEL0_USBH_Pos)    /*!< Setting clock source as PLL   \hideinitializer */
-#define CLK_CLKSEL0_USBHSEL_PLL2    (0x01UL<<CLK_CLKSEL0_USBH_Pos)    /*!< Setting clock source as PLL2  \hideinitializer */
+#define CLK_CLKSEL0_USBHSEL_PLL2   (0x00UL<<CLK_CLKSEL0_USBHSEL_Pos)    /*!< Setting clock source as PLL2   \hideinitializer */
+#define CLK_CLKSEL0_USBHSEL_PLL    (0x01UL<<CLK_CLKSEL0_USBHSEL_Pos)    /*!< Setting clock source as PLL  \hideinitializer */
 
 #define CLK_CLKSEL0_EMACSEL_PLL   (0x01UL<<10)    /*!< Setting clock source as PLL  \hideinitializer */
 

From 7acc4f2c16b2b54537ddeae145a4d325440c4a59 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Fri, 5 Aug 2016 14:27:42 +0800
Subject: [PATCH 20/89] Remove sal-stack-lwip.a from IAR linker configuration
 file

Locate *lwip_* in XRAM to fix IRAM OOM
---
 .../TARGET_NUC472/device/TOOLCHAIN_IAR/NUC472_442.icf           | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/NUC472_442.icf b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/NUC472_442.icf
index 9addb2df098..479e48eef88 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/NUC472_442.icf
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/NUC472_442.icf
@@ -26,7 +26,7 @@ define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
 /* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
 define block IRAMVEC   with alignment = 1024, size = 4 * (16 + 142)         { };
 /* Move non-critical libraries to external SRAM while internal SRAM is insufficient. */
-define block XRAM_NC   with alignment = 8                                   { readwrite object sal-stack-lwip.a };
+define block XRAM_NC   with alignment = 8                                   { zeroinit object *lwip_* };
 
 
 initialize by copy { readwrite };

From f90c6ebea0ccb02ae630c78e22d2152a78e9f213 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Tue, 9 Aug 2016 09:58:33 +0800
Subject: [PATCH 21/89] Support NUMAKER_PFM_M453

---
 platform/retarget.cpp                         |     2 +-
 .../TARGET_NUMAKER_PFM_M453/PeripheralNames.h |   117 +
 .../TARGET_NUMAKER_PFM_M453/PeripheralPins.c  |   361 +
 .../TARGET_NUMAKER_PFM_M453/PeripheralPins.h  |    62 +
 .../TARGET_NUMAKER_PFM_M453/PinNames.h        |   113 +
 .../TARGET_NUMAKER_PFM_M453/PortNames.h       |    36 +
 .../TARGET_NUMAKER_PFM_M453/device.h          |    65 +
 .../TARGET_NUMAKER_PFM_M453/mbed_overrides.c  |    83 +
 .../TARGET_NUMAKER_PFM_M453/objects.h         |   132 +
 .../TARGET_NUVOTON/TARGET_M451/analogin_api.c |   160 +
 targets/TARGET_NUVOTON/TARGET_M451/dma.h      |    40 +
 targets/TARGET_NUVOTON/TARGET_M451/dma_api.c  |   178 +
 targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c |    86 +
 .../TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c |   205 +
 .../TARGET_NUVOTON/TARGET_M451/gpio_object.h  |    57 +
 targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c  |  1025 +
 .../TARGET_NUVOTON/TARGET_M451/lp_ticker.c    |   208 +
 targets/TARGET_NUVOTON/TARGET_M451/pinmap.c   |    83 +
 targets/TARGET_NUVOTON/TARGET_M451/port_api.c |    99 +
 .../TARGET_NUVOTON/TARGET_M451/pwmout_api.c   |   204 +
 targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c  |   121 +
 .../TARGET_NUVOTON/TARGET_M451/serial_api.c   |  1053 +
 targets/TARGET_NUVOTON/TARGET_M451/sleep.c    |   118 +
 targets/TARGET_NUVOTON/TARGET_M451/spi_api.c  |   775 +
 .../TARGET_NUVOTON/TARGET_M451/us_ticker.c    |   268 +
 targets/TARGET_NUVOTON/mbed_rtx.h             |    36 +
 .../TARGET_NUVOTON/TARGET_M451/M451Series.h   | 17150 ++++++++++++++++
 .../TARGET_M451/StdDriver/m451_acmp.c         |    84 +
 .../TARGET_M451/StdDriver/m451_acmp.h         |   333 +
 .../TARGET_M451/StdDriver/m451_can.c          |  1004 +
 .../TARGET_M451/StdDriver/m451_can.h          |   175 +
 .../TARGET_M451/StdDriver/m451_clk.c          |   751 +
 .../TARGET_M451/StdDriver/m451_clk.h          |   447 +
 .../TARGET_M451/StdDriver/m451_crc.c          |    93 +
 .../TARGET_M451/StdDriver/m451_crc.h          |   112 +
 .../TARGET_M451/StdDriver/m451_dac.c          |    94 +
 .../TARGET_M451/StdDriver/m451_dac.h          |   245 +
 .../TARGET_M451/StdDriver/m451_eadc.c         |   159 +
 .../TARGET_M451/StdDriver/m451_eadc.h         |   569 +
 .../TARGET_M451/StdDriver/m451_ebi.c          |   178 +
 .../TARGET_M451/StdDriver/m451_ebi.h          |   235 +
 .../TARGET_M451/StdDriver/m451_fmc.c          |   320 +
 .../TARGET_M451/StdDriver/m451_fmc.h          |   605 +
 .../TARGET_M451/StdDriver/m451_gpio.c         |   102 +
 .../TARGET_M451/StdDriver/m451_gpio.h         |   439 +
 .../TARGET_M451/StdDriver/m451_i2c.c          |   612 +
 .../TARGET_M451/StdDriver/m451_i2c.h          |   415 +
 .../TARGET_M451/StdDriver/m451_otg.h          |   260 +
 .../TARGET_M451/StdDriver/m451_pdma.c         |   389 +
 .../TARGET_M451/StdDriver/m451_pdma.h         |   300 +
 .../TARGET_M451/StdDriver/m451_pwm.c          |  1375 ++
 .../TARGET_M451/StdDriver/m451_pwm.h          |   560 +
 .../TARGET_M451/StdDriver/m451_rtc.c          |   789 +
 .../TARGET_M451/StdDriver/m451_rtc.h          |   272 +
 .../TARGET_M451/StdDriver/m451_sc.c           |   299 +
 .../TARGET_M451/StdDriver/m451_sc.h           |   269 +
 .../TARGET_M451/StdDriver/m451_scuart.c       |   223 +
 .../TARGET_M451/StdDriver/m451_scuart.h       |   279 +
 .../TARGET_M451/StdDriver/m451_spi.c          |  1154 ++
 .../TARGET_M451/StdDriver/m451_spi.h          |   630 +
 .../TARGET_M451/StdDriver/m451_sys.c          |   213 +
 .../TARGET_M451/StdDriver/m451_sys.h          |   970 +
 .../TARGET_M451/StdDriver/m451_timer.c        |   292 +
 .../TARGET_M451/StdDriver/m451_timer.h        |   415 +
 .../TARGET_M451/StdDriver/m451_tk.c           |   265 +
 .../TARGET_M451/StdDriver/m451_tk.h           |   302 +
 .../TARGET_M451/StdDriver/m451_uart.c         |   512 +
 .../TARGET_M451/StdDriver/m451_uart.h         |   460 +
 .../TARGET_M451/StdDriver/m451_usbd.c         |   728 +
 .../TARGET_M451/StdDriver/m451_usbd.h         |   664 +
 .../TARGET_M451/StdDriver/m451_wdt.c          |    71 +
 .../TARGET_M451/StdDriver/m451_wdt.h          |   201 +
 .../TARGET_M451/StdDriver/m451_wwdt.c         |    71 +
 .../TARGET_M451/StdDriver/m451_wwdt.h         |   148 +
 .../TOOLCHAIN_ARM_MICRO/M453.sct              |    28 +
 .../TOOLCHAIN_ARM_MICRO/sys.cpp               |    28 +
 .../TOOLCHAIN_ARM_STD/M453.sct                |    28 +
 .../TOOLCHAIN_ARM_STD/sys.cpp                 |    28 +
 .../TOOLCHAIN_GCC_ARM/M453.ld                 |   255 +
 .../TOOLCHAIN_GCC_ARM/retarget.c              |    35 +
 .../TOOLCHAIN_IAR/M453.icf                    |    36 +
 .../startup_M451Series.c                      |   326 +
 .../cmsis/TARGET_NUVOTON/TARGET_M451/cmsis.h  |    33 +
 .../TARGET_NUVOTON/TARGET_M451/cmsis_nvic.c   |    39 +
 .../TARGET_NUVOTON/TARGET_M451/cmsis_nvic.h   |    63 +
 .../TARGET_M451/system_M451Series.c           |   111 +
 .../TARGET_M451/system_M451Series.h           |    75 +
 targets/targets.json                          |    13 +-
 88 files changed, 43016 insertions(+), 2 deletions(-)
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.h
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PortNames.h
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/device.h
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/mbed_overrides.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/analogin_api.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/dma.h
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/dma_api.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/gpio_object.h
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/pinmap.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/port_api.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/serial_api.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/sleep.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/spi_api.c
 create mode 100644 targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/M451Series.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_acmp.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_acmp.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_can.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_can.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_clk.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_clk.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_crc.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_crc.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_dac.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_dac.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_eadc.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_eadc.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_ebi.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_ebi.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_fmc.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_fmc.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_gpio.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_gpio.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_i2c.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_i2c.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_otg.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pdma.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pdma.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pwm.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pwm.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_rtc.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_rtc.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sc.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sc.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_scuart.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_scuart.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_spi.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_spi.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sys.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sys.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_timer.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_timer.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_tk.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_tk.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_uart.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_uart.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_usbd.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_usbd.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wdt.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wdt.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wwdt.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wwdt.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_MICRO/M453.sct
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_MICRO/sys.cpp
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_STD/M453.sct
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_STD/sys.cpp
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/M453.ld
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_IAR/M453.icf
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/startup_M451Series.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.h
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/system_M451Series.c
 create mode 100644 targets/cmsis/TARGET_NUVOTON/TARGET_M451/system_M451Series.h

diff --git a/platform/retarget.cpp b/platform/retarget.cpp
index 3a1d3aef9ec..2bc1027139a 100644
--- a/platform/retarget.cpp
+++ b/platform/retarget.cpp
@@ -573,7 +573,7 @@ extern "C" int errno;
 register unsigned char * stack_ptr __asm ("sp");
 
 // Dynamic memory allocation related syscall.
-#if defined(TARGET_NUMAKER_PFM_NUC472)
+#if defined(TARGET_NUMAKER_PFM_NUC472) || defined(TARGET_NUMAKER_PFM_M453)
 // Overwrite _sbrk() to support two region model.
 extern "C" void *__wrap__sbrk(int incr);
 extern "C" caddr_t _sbrk(int incr) {
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h
new file mode 100644
index 00000000000..c08e2cef5a0
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h
@@ -0,0 +1,117 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// NOTE: TIMER0_BASE=(APBPERIPH_BASE + 0x10000)
+//       TIMER1_BASE=(APBPERIPH_BASE + 0x10020)
+#define NU_MODNAME(MODBASE, SUBINDEX)   ((MODBASE) | (SUBINDEX))
+#define NU_MODBASE(MODNAME)             ((MODNAME) & 0xFFFFFFE0)
+#define NU_MODSUBINDEX(MODNAME)         ((MODNAME) & 0x0000001F)
+
+#if 0
+typedef enum {
+    GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0),
+    GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 0),
+    GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 0),
+    GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 0),
+    GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 0),
+    GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 0)
+} GPIOName;
+#endif
+
+typedef enum {
+    ADC_0_0 = (int) NU_MODNAME(EADC0_BASE, 0),
+    ADC_0_1 = (int) NU_MODNAME(EADC0_BASE, 1),
+    ADC_0_2 = (int) NU_MODNAME(EADC0_BASE, 2),
+    ADC_0_3 = (int) NU_MODNAME(EADC0_BASE, 3),
+    ADC_0_4 = (int) NU_MODNAME(EADC0_BASE, 4),
+    ADC_0_5 = (int) NU_MODNAME(EADC0_BASE, 5),
+    ADC_0_6 = (int) NU_MODNAME(EADC0_BASE, 6),
+    ADC_0_7 = (int) NU_MODNAME(EADC0_BASE, 7),
+    ADC_0_8 = (int) NU_MODNAME(EADC0_BASE, 8),
+    ADC_0_9 = (int) NU_MODNAME(EADC0_BASE, 9),
+    ADC_0_10 = (int) NU_MODNAME(EADC0_BASE, 10),
+    ADC_0_11 = (int) NU_MODNAME(EADC0_BASE, 11),
+    ADC_0_12 = (int) NU_MODNAME(EADC0_BASE, 12),
+    ADC_0_13 = (int) NU_MODNAME(EADC0_BASE, 13),
+    ADC_0_14 = (int) NU_MODNAME(EADC0_BASE, 14),
+    ADC_0_15 = (int) NU_MODNAME(EADC0_BASE, 15)
+} ADCName;
+
+typedef enum {
+    UART_0 = (int) NU_MODNAME(UART0_BASE, 0),
+    UART_1 = (int) NU_MODNAME(UART1_BASE, 0),
+    UART_2 = (int) NU_MODNAME(UART2_BASE, 0),
+    UART_3 = (int) NU_MODNAME(UART3_BASE, 0),
+    // FIXME: board-specific
+    STDIO_UART  = UART_3
+} UARTName;
+
+typedef enum {
+    SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0),
+    SPI_1 = (int) NU_MODNAME(SPI1_BASE, 0),
+    SPI_2 = (int) NU_MODNAME(SPI2_BASE, 0)
+} SPIName;
+
+typedef enum {
+    I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0),
+    I2C_1 = (int) NU_MODNAME(I2C1_BASE, 0)
+} I2CName;
+
+typedef enum {
+    PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0),
+    PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 1),
+    PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 2),
+    PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 3),
+    PWM_0_4 = (int) NU_MODNAME(PWM0_BASE, 4),
+    PWM_0_5 = (int) NU_MODNAME(PWM0_BASE, 5),
+    
+    PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 0),
+    PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1),
+    PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 2),
+    PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 3),
+    PWM_1_4 = (int) NU_MODNAME(PWM1_BASE, 4),
+    PWM_1_5 = (int) NU_MODNAME(PWM1_BASE, 5)
+} PWMName;
+
+typedef enum {
+    TIMER_0  = (int) NU_MODNAME(TMR01_BASE, 0),
+    TIMER_1  = (int) NU_MODNAME(TMR01_BASE + 0x20, 0),
+    TIMER_2  = (int) NU_MODNAME(TMR23_BASE, 0),
+    TIMER_3  = (int) NU_MODNAME(TMR23_BASE + 0x20, 0),
+} TIMERName;
+
+typedef enum {
+    RTC_0 = (int) NU_MODNAME(RTC_BASE, 0)
+} RTCName;
+
+typedef enum {
+    DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0)
+} DMAName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c
new file mode 100644
index 00000000000..971bef3dbf2
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c
@@ -0,0 +1,361 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+//       If you change them, you will have also to modify the corresponding xxx_api.c file
+//       for pwmout, analogin, analogout, ...
+// =====
+
+#if 0
+//*** GPIO ***
+const PinMap PinMap_GPIO[] = {
+    // GPIO A MFPL
+    {PA_0, GPIO_A, SYS_GPA_MFPL_PA0MFP_GPIO},
+    {PA_1, GPIO_A, SYS_GPA_MFPL_PA1MFP_GPIO},
+    {PA_2, GPIO_A, SYS_GPA_MFPL_PA2MFP_GPIO},
+    {PA_3, GPIO_A, SYS_GPA_MFPL_PA3MFP_GPIO},
+    {PA_4, GPIO_A, SYS_GPA_MFPL_PA4MFP_GPIO},
+    {PA_5, GPIO_A, SYS_GPA_MFPL_PA5MFP_GPIO},
+    {PA_6, GPIO_A, SYS_GPA_MFPL_PA6MFP_GPIO},
+    {PA_7, GPIO_A, SYS_GPA_MFPL_PA7MFP_GPIO},
+    // GPIO A MFPH
+    {PA_8, GPIO_A, SYS_GPA_MFPH_PA8MFP_GPIO},
+    {PA_9, GPIO_A, SYS_GPA_MFPH_PA9MFP_GPIO},
+    {PA_10, GPIO_A, SYS_GPA_MFPH_PA10MFP_GPIO},
+    {PA_11, GPIO_A, SYS_GPA_MFPH_PA11MFP_GPIO},
+    {PA_12, GPIO_A, SYS_GPA_MFPH_PA12MFP_GPIO},
+    {PA_13, GPIO_A, SYS_GPA_MFPH_PA13MFP_GPIO},
+    {PA_14, GPIO_A, SYS_GPA_MFPH_PA14MFP_GPIO},
+    {PA_15, GPIO_A, SYS_GPA_MFPH_PA15MFP_GPIO},
+    
+    // GPIO B MFPL
+    {PB_0, GPIO_B, SYS_GPB_MFPL_PB0MFP_GPIO},
+    {PB_1, GPIO_B, SYS_GPB_MFPL_PB1MFP_GPIO},
+    {PB_2, GPIO_B, SYS_GPB_MFPL_PB2MFP_GPIO},
+    {PB_3, GPIO_B, SYS_GPB_MFPL_PB3MFP_GPIO},
+    {PB_4, GPIO_B, SYS_GPB_MFPL_PB4MFP_GPIO},
+    {PB_5, GPIO_B, SYS_GPB_MFPL_PB5MFP_GPIO},
+    {PB_6, GPIO_B, SYS_GPB_MFPL_PB6MFP_GPIO},
+    {PB_7, GPIO_B, SYS_GPB_MFPL_PB7MFP_GPIO},
+    // GPIO B MFPH
+    {PB_8, GPIO_B, SYS_GPB_MFPH_PB8MFP_GPIO},
+    {PB_9, GPIO_B, SYS_GPB_MFPH_PB9MFP_GPIO},
+    {PB_10, GPIO_B, SYS_GPB_MFPH_PB10MFP_GPIO},
+    {PB_11, GPIO_B, SYS_GPB_MFPH_PB11MFP_GPIO},
+    {PB_12, GPIO_B, SYS_GPB_MFPH_PB12MFP_GPIO},
+    {PB_13, GPIO_B, SYS_GPB_MFPH_PB13MFP_GPIO},
+    {PB_14, GPIO_B, SYS_GPB_MFPH_PB14MFP_GPIO},
+    {PB_15, GPIO_B, SYS_GPB_MFPH_PB15MFP_GPIO},
+    
+    // GPIO C MFPL
+    {PC_0, GPIO_C, SYS_GPC_MFPL_PC0MFP_GPIO},
+    {PC_1, GPIO_C, SYS_GPC_MFPL_PC1MFP_GPIO},
+    {PC_2, GPIO_C, SYS_GPC_MFPL_PC2MFP_GPIO},
+    {PC_3, GPIO_C, SYS_GPC_MFPL_PC3MFP_GPIO},
+    {PC_4, GPIO_C, SYS_GPC_MFPL_PC4MFP_GPIO},
+    {PC_5, GPIO_C, SYS_GPC_MFPL_PC5MFP_GPIO},
+    {PC_6, GPIO_C, SYS_GPC_MFPL_PC6MFP_GPIO},
+    {PC_7, GPIO_C, SYS_GPC_MFPL_PC7MFP_GPIO},
+    // GPIO C MFPH
+    {PC_8, GPIO_C, SYS_GPC_MFPH_PC8MFP_GPIO},
+    {PC_9, GPIO_C, SYS_GPC_MFPH_PC9MFP_GPIO},
+    {PC_10, GPIO_C, SYS_GPC_MFPH_PC10MFP_GPIO},
+    {PC_11, GPIO_C, SYS_GPC_MFPH_PC11MFP_GPIO},
+    {PC_12, GPIO_C, SYS_GPC_MFPH_PC12MFP_GPIO},
+    {PC_13, GPIO_C, SYS_GPC_MFPH_PC13MFP_GPIO},
+    {PC_14, GPIO_C, SYS_GPC_MFPH_PC14MFP_GPIO},
+    {PC_15, GPIO_C, SYS_GPC_MFPH_PC15MFP_GPIO},
+    
+    // GPIO D MFPL
+    {PD_0, GPIO_D, SYS_GPD_MFPL_PD0MFP_GPIO},
+    {PD_1, GPIO_D, SYS_GPD_MFPL_PD1MFP_GPIO},
+    {PD_2, GPIO_D, SYS_GPD_MFPL_PD2MFP_GPIO},
+    {PD_3, GPIO_D, SYS_GPD_MFPL_PD3MFP_GPIO},
+    {PD_4, GPIO_D, SYS_GPD_MFPL_PD4MFP_GPIO},
+    {PD_5, GPIO_D, SYS_GPD_MFPL_PD5MFP_GPIO},
+    {PD_6, GPIO_D, SYS_GPD_MFPL_PD6MFP_GPIO},
+    {PD_7, GPIO_D, SYS_GPD_MFPL_PD7MFP_GPIO},
+    // GPIO D MFPH
+    {PD_8, GPIO_D, SYS_GPD_MFPH_PD8MFP_GPIO},
+    {PD_9, GPIO_D, SYS_GPD_MFPH_PD9MFP_GPIO},
+    {PD_10, GPIO_D, SYS_GPD_MFPH_PD10MFP_GPIO},
+    {PD_11, GPIO_D, SYS_GPD_MFPH_PD11MFP_GPIO},
+    {PD_12, GPIO_D, SYS_GPD_MFPH_PD12MFP_GPIO},
+    {PD_13, GPIO_D, SYS_GPD_MFPH_PD13MFP_GPIO},
+    {PD_14, GPIO_D, SYS_GPD_MFPH_PD14MFP_GPIO},
+    {PD_15, GPIO_D, SYS_GPD_MFPH_PD15MFP_GPIO},
+    
+    // GPIO E MFPL
+    {PE_0, GPIO_E, SYS_GPE_MFPL_PE0MFP_GPIO},
+    {PE_1, GPIO_E, SYS_GPE_MFPL_PE1MFP_GPIO},
+    {PE_2, GPIO_E, SYS_GPE_MFPL_PE2MFP_GPIO},
+    {PE_3, GPIO_E, SYS_GPE_MFPL_PE3MFP_GPIO},
+    {PE_4, GPIO_E, SYS_GPE_MFPL_PE4MFP_GPIO},
+    {PE_5, GPIO_E, SYS_GPE_MFPL_PE5MFP_GPIO},
+    {PE_6, GPIO_E, SYS_GPE_MFPL_PE6MFP_GPIO},
+    {PE_7, GPIO_E, SYS_GPE_MFPL_PE7MFP_GPIO},
+    // GPIO E MFPH
+    {PE_8, GPIO_E, SYS_GPE_MFPH_PE8MFP_GPIO},
+    {PE_9, GPIO_E, SYS_GPE_MFPH_PE9MFP_GPIO},
+    {PE_10, GPIO_E, SYS_GPE_MFPH_PE10MFP_GPIO},
+    {PE_11, GPIO_E, SYS_GPE_MFPH_PE11MFP_GPIO},
+    {PE_12, GPIO_E, SYS_GPE_MFPH_PE12MFP_GPIO},
+    {PE_13, GPIO_E, SYS_GPE_MFPH_PE13MFP_GPIO},
+    {PE_14, GPIO_E, SYS_GPE_MFPH_PE14MFP_GPIO},
+    
+    // GPIO F MFPL
+    {PF_0, GPIO_F, SYS_GPF_MFPL_PF0MFP_GPIO},
+    {PF_1, GPIO_F, SYS_GPF_MFPL_PF1MFP_GPIO},
+    {PF_2, GPIO_F, SYS_GPF_MFPL_PF2MFP_GPIO},
+    {PF_3, GPIO_F, SYS_GPF_MFPL_PF3MFP_GPIO},
+    {PF_4, GPIO_F, SYS_GPF_MFPL_PF4MFP_GPIO},
+    {PF_5, GPIO_F, SYS_GPF_MFPL_PF5MFP_GPIO},
+    {PF_6, GPIO_F, SYS_GPF_MFPL_PF6MFP_GPIO},
+    {PF_7, GPIO_F, SYS_GPF_MFPL_PF7MFP_GPIO},
+};
+#endif
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PB_0, ADC_0_0, SYS_GPB_MFPL_PB0MFP_EADC_CH0},
+    {PB_1, ADC_0_1, SYS_GPB_MFPL_PB1MFP_EADC_CH1},
+    {PB_2, ADC_0_2, SYS_GPB_MFPL_PB2MFP_EADC_CH2},
+    {PB_3, ADC_0_3, SYS_GPB_MFPL_PB3MFP_EADC_CH3},
+    {PB_4, ADC_0_4, SYS_GPB_MFPL_PB4MFP_EADC_CH4},
+    {PB_5, ADC_0_13, SYS_GPB_MFPL_PB5MFP_EADC_CH13},
+    {PB_6, ADC_0_14, SYS_GPB_MFPL_PB6MFP_EADC_CH14},
+    {PB_7, ADC_0_15, SYS_GPB_MFPL_PB7MFP_EADC_CH15},
+    {PB_8, ADC_0_5, SYS_GPB_MFPH_PB8MFP_EADC_CH5},
+    {PB_9, ADC_0_6, SYS_GPB_MFPH_PB9MFP_EADC_CH6},
+    {PB_10, ADC_0_7, SYS_GPB_MFPH_PB10MFP_EADC_CH7},
+    {PB_11, ADC_0_8, SYS_GPB_MFPH_PB11MFP_EADC_CH8},
+    {PB_12, ADC_0_9, SYS_GPB_MFPH_PB12MFP_EADC_CH9},
+    {PB_13, ADC_0_10, SYS_GPB_MFPH_PB13MFP_EADC_CH10},
+    {PB_14, ADC_0_11, SYS_GPB_MFPH_PB14MFP_EADC_CH11},
+    {PB_15, ADC_0_12, SYS_GPB_MFPH_PB15MFP_EADC_CH12},
+    {PD_0, ADC_0_6, SYS_GPD_MFPL_PD0MFP_EADC_CH6},
+    {PD_1, ADC_0_11, SYS_GPD_MFPL_PD1MFP_EADC_CH11},
+    {PD_8, ADC_0_7, SYS_GPD_MFPH_PD8MFP_EADC_CH7},
+    {PD_9, ADC_0_10, SYS_GPD_MFPH_PD9MFP_EADC_CH10},
+    
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PA_2,  I2C_0, SYS_GPA_MFPL_PA2MFP_I2C0_SDA},
+    {PD_4,  I2C_0, SYS_GPD_MFPL_PD4MFP_I2C0_SDA},
+    {PE_0, I2C_1, SYS_GPE_MFPL_PE0MFP_I2C1_SDA},
+    {PE_5, I2C_1, SYS_GPE_MFPL_PE5MFP_I2C1_SDA},
+    {PE_9, I2C_1, SYS_GPE_MFPH_PE9MFP_I2C1_SDA},
+    {PE_11, I2C_1, SYS_GPE_MFPH_PE11MFP_I2C1_SDA},
+    {PE_13, I2C_0, SYS_GPE_MFPH_PE13MFP_I2C0_SDA},
+    {PF_4, I2C_1, SYS_GPF_MFPL_PF4MFP_I2C1_SDA},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PA_3, I2C_0, SYS_GPA_MFPL_PA3MFP_I2C0_SCL},
+    {PC_4, I2C_1, SYS_GPC_MFPL_PC4MFP_I2C1_SCL},
+    {PD_5, I2C_0, SYS_GPD_MFPL_PD5MFP_I2C0_SCL},
+    {PE_4, I2C_1, SYS_GPE_MFPL_PE4MFP_I2C1_SCL},
+    {PE_8, I2C_1, SYS_GPE_MFPH_PE8MFP_I2C1_SCL},
+    {PE_10, I2C_1, SYS_GPE_MFPH_PE10MFP_I2C1_SCL},
+    {PE_12, I2C_0, SYS_GPE_MFPH_PE12MFP_I2C0_SCL},
+    {PF_3, I2C_1, SYS_GPF_MFPL_PF3MFP_I2C1_SCL},
+   
+    
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+const PinMap PinMap_PWM[] = {
+    {PA_0, PWM_1_5, SYS_GPA_MFPL_PA0MFP_PWM1_CH5},
+    {PA_1, PWM_1_4, SYS_GPA_MFPL_PA1MFP_PWM1_CH4},
+    {PA_2, PWM_1_3, SYS_GPA_MFPL_PA2MFP_PWM1_CH3},
+    {PA_3, PWM_1_2, SYS_GPA_MFPL_PA3MFP_PWM1_CH2},
+    {PB_8, PWM_0_2, SYS_GPB_MFPH_PB8MFP_PWM0_CH2},
+    {PC_0, PWM_0_0, SYS_GPC_MFPL_PC0MFP_PWM0_CH0},
+    {PC_1, PWM_0_1, SYS_GPC_MFPL_PC1MFP_PWM0_CH1},
+    {PC_2, PWM_0_2, SYS_GPC_MFPL_PC2MFP_PWM0_CH2},
+    {PC_3, PWM_0_3, SYS_GPC_MFPL_PC3MFP_PWM0_CH3},
+    {PC_4, PWM_0_4, SYS_GPC_MFPL_PC4MFP_PWM0_CH4},
+    {PC_5, PWM_0_5, SYS_GPC_MFPL_PC5MFP_PWM0_CH5},
+    {PC_6, PWM_1_0, SYS_GPC_MFPL_PC6MFP_PWM1_CH0},
+    {PC_7, PWM_1_1, SYS_GPC_MFPL_PC7MFP_PWM1_CH1},
+    {PC_9, PWM_1_0, SYS_GPC_MFPH_PC9MFP_PWM1_CH0},
+    {PC_10, PWM_1_1, SYS_GPC_MFPH_PC10MFP_PWM1_CH1},
+    {PC_11, PWM_1_2, SYS_GPC_MFPH_PC11MFP_PWM1_CH2},
+    {PC_12, PWM_1_3, SYS_GPC_MFPH_PC12MFP_PWM1_CH3},
+    {PC_13, PWM_1_4, SYS_GPC_MFPH_PC13MFP_PWM1_CH4},
+    {PC_14, PWM_1_5, SYS_GPC_MFPH_PC14MFP_PWM1_CH5},
+    {PC_15, PWM_1_0, SYS_GPC_MFPH_PC15MFP_PWM1_CH0},
+    {PD_6, PWM_0_5, SYS_GPD_MFPL_PD6MFP_PWM0_CH5},
+    {PD_7, PWM_0_5, SYS_GPD_MFPL_PD7MFP_PWM0_CH5},
+    {PD_12, PWM_1_0, SYS_GPD_MFPH_PD12MFP_PWM1_CH0},
+    {PD_13, PWM_1_1, SYS_GPD_MFPH_PD13MFP_PWM1_CH1},
+    {PD_14, PWM_1_2, SYS_GPD_MFPH_PD14MFP_PWM1_CH2},
+    {PD_15, PWM_1_3, SYS_GPD_MFPH_PD15MFP_PWM1_CH3},
+    {PE_0, PWM_0_0, SYS_GPE_MFPL_PE0MFP_PWM0_CH0},
+    {PE_1, PWM_0_1, SYS_GPE_MFPL_PE1MFP_PWM0_CH1},
+    {PE_2, PWM_1_1, SYS_GPE_MFPL_PE2MFP_PWM1_CH1},
+    {PE_3, PWM_0_3, SYS_GPE_MFPL_PE3MFP_PWM0_CH3},
+
+    {NC,    NC,    0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_0, UART_1, SYS_GPA_MFPL_PA0MFP_UART1_TXD},
+    {PA_2, UART_0, SYS_GPA_MFPL_PA2MFP_UART0_TXD},
+    {PA_8, UART_3, SYS_GPA_MFPH_PA8MFP_UART3_TXD},
+    {PB_1, UART_2, SYS_GPB_MFPL_PB1MFP_UART2_TXD},
+    {PB_3, UART_1, SYS_GPB_MFPL_PB3MFP_UART1_TXD},
+    {PB_3, UART_3, SYS_GPB_MFPL_PB3MFP_UART3_TXD},
+    {PB_4, UART_2, SYS_GPB_MFPL_PB4MFP_UART2_TXD},
+    {PC_0, UART_3, SYS_GPC_MFPL_PC0MFP_UART3_TXD},
+    {PC_2, UART_2, SYS_GPC_MFPL_PC2MFP_UART2_TXD},
+    {PC_6, UART_0, SYS_GPC_MFPL_PC6MFP_UART0_TXD},
+    {PD_1, UART_0, SYS_GPD_MFPL_PD1MFP_UART0_TXD},
+    {PD_12, UART_3, SYS_GPD_MFPH_PD12MFP_UART3_TXD},
+    {PE_8, UART_1, SYS_GPE_MFPH_PE8MFP_UART1_TXD},
+    {PE_10, UART_3, SYS_GPE_MFPH_PE10MFP_UART3_TXD},
+    {PE_12, UART_1, SYS_GPE_MFPH_PE12MFP_UART1_TXD},
+    
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_1, UART_1, SYS_GPA_MFPL_PA1MFP_UART1_RXD},
+    {PA_3, UART_0, SYS_GPA_MFPL_PA3MFP_UART0_RXD},
+    {PA_9, UART_3, SYS_GPA_MFPH_PA9MFP_UART3_RXD},
+    {PB_0, UART_2, SYS_GPB_MFPL_PB0MFP_UART2_RXD},
+    {PB_2, UART_1, SYS_GPB_MFPL_PB2MFP_UART1_RXD},
+    {PB_2, UART_3, SYS_GPB_MFPL_PB2MFP_UART3_RXD},
+    {PB_5, UART_2, SYS_GPB_MFPL_PB5MFP_UART2_RXD},
+    {PC_1, UART_3, SYS_GPC_MFPL_PC1MFP_UART3_RXD},
+    {PC_3, UART_2, SYS_GPC_MFPL_PC3MFP_UART2_RXD},
+    {PC_7, UART_0, SYS_GPC_MFPL_PC7MFP_UART0_RXD},
+    {PD_0, UART_0, SYS_GPD_MFPL_PD0MFP_UART0_RXD},
+    {PD_6, UART_0, SYS_GPD_MFPL_PD6MFP_UART0_RXD},
+    {PD_13, UART_3, SYS_GPD_MFPH_PD13MFP_UART3_RXD},
+    {PE_9, UART_1, SYS_GPE_MFPH_PE9MFP_UART1_RXD},
+    {PE_11, UART_3, SYS_GPE_MFPH_PE11MFP_UART3_RXD},
+    {PE_13, UART_1, SYS_GPE_MFPH_PE13MFP_UART1_RXD},
+    
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_1, UART_1, SYS_GPA_MFPL_PA1MFP_UART1_nRTS},
+    {PA_3, UART_0, SYS_GPA_MFPL_PA3MFP_UART0_nRTS},
+    {PA_11, UART_3, SYS_GPA_MFPH_PA11MFP_UART3_nRTS},
+    {PA_15, UART_2, SYS_GPA_MFPH_PA15MFP_UART2_nRTS},
+    {PB_8, UART_1, SYS_GPB_MFPH_PB8MFP_UART1_nRTS},
+    {PC_1, UART_2, SYS_GPC_MFPL_PC1MFP_UART2_nRTS},
+    {PD_15, UART_3, SYS_GPD_MFPH_PD15MFP_UART3_nRTS},
+    {PE_11, UART_1, SYS_GPE_MFPH_PE11MFP_UART1_nRTS},
+    
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0, UART_1, SYS_GPA_MFPL_PA0MFP_UART1_nCTS},
+    {PA_2, UART_0, SYS_GPA_MFPL_PA2MFP_UART0_nCTS},
+    {PA_10, UART_3, SYS_GPA_MFPH_PA10MFP_UART3_nCTS},
+    {PA_14, UART_2, SYS_GPA_MFPH_PA14MFP_UART2_nCTS},
+    {PB_4, UART_1, SYS_GPB_MFPL_PB4MFP_UART1_nCTS},
+    {PC_0, UART_2, SYS_GPC_MFPL_PC0MFP_UART2_nCTS},
+    {PD_14, UART_3, SYS_GPD_MFPH_PD14MFP_UART3_nCTS},
+    {PE_10, UART_1, SYS_GPE_MFPH_PE10MFP_UART1_nCTS},
+    
+    {NC,    NC,     0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_5, SPI_1, SYS_GPA_MFPL_PA5MFP_SPI1_MOSI},
+    {PB_0, SPI_0, SYS_GPB_MFPL_PB0MFP_SPI0_MOSI1},
+    {PB_5, SPI_0, SYS_GPB_MFPL_PB5MFP_SPI0_MOSI0},
+    {PB_5, SPI_1, SYS_GPB_MFPL_PB5MFP_SPI1_MOSI},
+    {PC_3, SPI_2, SYS_GPC_MFPL_PC3MFP_SPI2_MOSI},
+    {PC_10, SPI_2, SYS_GPC_MFPH_PC10MFP_SPI2_MOSI},
+    {PD_13, SPI_2, SYS_GPD_MFPH_PD13MFP_SPI2_MOSI},
+    {PE_3, SPI_1, SYS_GPE_MFPL_PE3MFP_SPI1_MOSI},
+    {PE_9, SPI_0, SYS_GPE_MFPH_PE9MFP_SPI0_MOSI1},
+    {PE_11, SPI_1, SYS_GPE_MFPH_PE11MFP_SPI1_MOSI},
+    {PE_11, SPI_0, SYS_GPE_MFPH_PE11MFP_SPI0_MOSI0},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6, SPI_1, SYS_GPA_MFPL_PA6MFP_SPI1_MISO},
+    {PB_1, SPI_0, SYS_GPB_MFPL_PB1MFP_SPI0_MISO1},
+    {PB_3, SPI_0, SYS_GPB_MFPL_PB3MFP_SPI0_MISO0},
+    {PB_3, SPI_1, SYS_GPB_MFPL_PB3MFP_SPI1_MISO},
+    {PB_6, SPI_0, SYS_GPB_MFPL_PB6MFP_SPI0_MISO0},
+    {PB_6, SPI_1, SYS_GPB_MFPL_PB6MFP_SPI1_MISO},
+    {PC_4, SPI_2, SYS_GPC_MFPL_PC4MFP_SPI2_MISO},
+    {PC_11, SPI_2, SYS_GPC_MFPH_PC11MFP_SPI2_MISO},
+    {PD_5, SPI_1, SYS_GPD_MFPL_PD5MFP_SPI1_MISO},
+    {PD_14, SPI_2, SYS_GPD_MFPH_PD14MFP_SPI2_MISO},
+    {PE_8, SPI_0, SYS_GPE_MFPH_PE8MFP_SPI0_MISO1},
+    {PE_10, SPI_1, SYS_GPE_MFPH_PE10MFP_SPI1_MISO},
+    {PE_10, SPI_0, SYS_GPE_MFPH_PE10MFP_SPI0_MISO0},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_7, SPI_1, SYS_GPA_MFPL_PA7MFP_SPI1_CLK},
+    {PB_2, SPI_0, SYS_GPB_MFPL_PB2MFP_SPI0_CLK},
+    {PB_2, SPI_1, SYS_GPB_MFPL_PB2MFP_SPI1_CLK},
+    {PB_7, SPI_0, SYS_GPB_MFPL_PB7MFP_SPI0_CLK},
+    {PB_7, SPI_1, SYS_GPB_MFPL_PB7MFP_SPI1_CLK},
+    {PC_0, SPI_2, SYS_GPC_MFPL_PC0MFP_SPI2_CLK},
+    {PC_12, SPI_2, SYS_GPC_MFPH_PC12MFP_SPI2_CLK},
+    {PD_4, SPI_1, SYS_GPD_MFPL_PD4MFP_SPI1_CLK},
+    {PD_15, SPI_2, SYS_GPD_MFPH_PD15MFP_SPI2_CLK},
+    {PE_0, SPI_2, SYS_GPE_MFPL_PE0MFP_SPI2_CLK},
+    {PE_13, SPI_1, SYS_GPE_MFPH_PE13MFP_SPI1_CLK},
+    {PE_13, SPI_0, SYS_GPE_MFPH_PE13MFP_SPI0_CLK},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4, SPI_1, SYS_GPA_MFPL_PA4MFP_SPI1_SS},
+    {PB_4, SPI_0, SYS_GPB_MFPL_PB4MFP_SPI0_SS},
+    {PB_4, SPI_1, SYS_GPB_MFPL_PB4MFP_SPI1_SS},
+    {PC_2, SPI_2, SYS_GPC_MFPL_PC2MFP_SPI2_SS},
+    {PC_13, SPI_2, SYS_GPC_MFPH_PC13MFP_SPI2_SS},
+    {PD_6, SPI_1, SYS_GPD_MFPL_PD6MFP_SPI1_SS},
+    {PD_12, SPI_2, SYS_GPD_MFPH_PD12MFP_SPI2_SS},
+    {PE_12, SPI_1, SYS_GPE_MFPH_PE12MFP_SPI1_SS},
+    {PE_12, SPI_0, SYS_GPE_MFPH_PE12MFP_SPI0_SS},
+    
+    {NC,    NC,    0}
+};
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.h
new file mode 100644
index 00000000000..5b1a453de9d
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.h
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//*** GPIO ***
+
+extern const PinMap PinMap_GPIO[];
+
+//*** ADC ***
+
+extern const PinMap PinMap_ADC[];
+
+//*** I2C ***
+
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+
+//*** PWM ***
+
+extern const PinMap PinMap_PWM[];
+
+//*** SERIAL ***
+
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+extern const PinMap PinMap_UART_RTS[];
+extern const PinMap PinMap_UART_CTS[];
+
+//*** SPI ***
+
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_SSEL[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h
new file mode 100644
index 00000000000..4e042cd6aca
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NU_PORT_SHIFT  12
+#define NU_PINNAME_TO_PORT(name)            ((unsigned int)(name) >> NU_PORT_SHIFT)
+#define NU_PINNAME_TO_PIN(name)             ((unsigned int)(name) & ~(0xFFFFFFFF << NU_PORT_SHIFT))
+#define NU_PORT_N_PIN_TO_PINNAME(port, pin) ((((unsigned int) (port)) << (NU_PORT_SHIFT)) | ((unsigned int) (pin)))
+#define NU_PORT_BASE(port)                  ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port))
+#define NU_MFP_POS(pin)                     ((pin % 8) * 4)
+#define NU_MFP_MSK(pin)                     (0xful << NU_MFP_POS(pin))
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+    PullNone = 0,
+    PullDown,
+    PullUp,
+    
+    PushPull,
+    OpenDrain,
+    Quasi,
+    
+    PullDefault = PullUp,
+} PinMode;
+
+typedef enum {
+    // Not connected
+    NC = (int)0xFFFFFFFF,
+    
+    // Generic naming
+    PA_0    = NU_PORT_N_PIN_TO_PINNAME(0, 0), PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7, PA_8, PA_9, PA_10, PA_11, PA_12, PA_13, PA_14, PA_15,
+    PB_0    = NU_PORT_N_PIN_TO_PINNAME(1, 0), PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PB_10, PB_11, PB_12, PB_13, PB_14, PB_15,
+    PC_0    = NU_PORT_N_PIN_TO_PINNAME(2, 0), PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7, PC_8, PC_9, PC_10, PC_11, PC_12, PC_13, PC_14, PC_15,
+    PD_0    = NU_PORT_N_PIN_TO_PINNAME(3, 0), PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7, PD_8, PD_9, PD_10, PD_11, PD_12, PD_13, PD_14, PD_15,
+    PE_0    = NU_PORT_N_PIN_TO_PINNAME(4, 0), PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, PE_7, PE_8, PE_9, PE_10, PE_11, PE_12, PE_13, PE_14,
+    PF_0    = NU_PORT_N_PIN_TO_PINNAME(5, 0), PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PF_7,
+    
+    // Arduino UNO naming
+    A0 = PB_0,
+    A1 = PB_1,
+    A2 = PB_2,
+    A3 = PB_3,
+    A4 = PB_4,
+    A5 = PB_8,
+    A6 = PB_9,
+    A7 = PB_10,
+
+    D0 = PD_6,
+    D1 = PD_1,
+    D2 = PC_6,
+    D3 = PC_7,
+    D4 = PC_11,
+    D5 = PC_12,
+    D6 = PC_13,
+    D7 = PC_14,
+    D8 = PC_0,
+    D9 = PC_1,
+    D10 = PC_2,
+    D11 = PC_3,
+    D12 = PC_4,
+    D13 = PC_5,
+    D14 = PE_5,
+    D15 = PE_4,
+    
+    // FIXME: other board-specific naming
+    // UART naming
+    USBTX = PA_8,
+    USBRX = PA_9,
+    STDIO_UART_TX   = USBTX,
+    STDIO_UART_RX   = USBRX,
+    // LED naming
+    LED1 = PD_2,
+    LED2 = PD_3,
+    LED3 = PD_7,
+    LED4 = D0,  // No real LED. Just for passing ATS.
+    LED_RED = LED2,
+    LED_GREEN = LED3,
+    LED_BLUE = LED1,
+    // Button naming
+    SW1 = PA_15,
+    SW2 = PA_14,
+    
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MBED_PINNAMES_H
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PortNames.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PortNames.h
new file mode 100644
index 00000000000..3adf2f8a53a
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PortNames.h
@@ -0,0 +1,36 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PortA = 0,
+    PortB = 1,
+    PortC = 2,
+    PortD = 3,
+    PortE = 4,
+    PortF = 5
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/device.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/device.h
new file mode 100644
index 00000000000..89e12ecd417
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/device.h
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        0
+
+#define DEVICE_SERIAL           1
+#define DEVICE_SERIAL_FC        1
+#define DEVICE_SERIAL_ASYNCH    1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         1
+#define DEVICE_I2C_ASYNCH       1
+
+#define DEVICE_SPI              1
+#define DEVICE_SPI_ASYNCH       1
+#define DEVICE_SPISLAVE         1
+
+#define DEVICE_CAN              0
+
+#define DEVICE_RTC              1
+
+#define DEVICE_ETHERNET         0
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_SEMIHOST         0
+#define DEVICE_LOCALFILESYSTEM  0
+#define DEVICE_ID_LENGTH       24
+
+#define DEVICE_SLEEP            1
+
+#define DEVICE_DEBUG_AWARENESS  0
+
+#define DEVICE_STDIO_MESSAGES   1
+
+#define DEVICE_ERROR_RED        0
+
+#define DEVICE_LOWPOWERTIMER    1
+
+#include "objects.h"
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/mbed_overrides.c b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/mbed_overrides.c
new file mode 100644
index 00000000000..67f7b9dbb89
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/mbed_overrides.c
@@ -0,0 +1,83 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "analogin_api.h"
+
+// NOTE: Ensurce mbed_sdk_init() will get called before C++ global object constructor.
+#if defined(__CC_ARM) || defined(__GNUC__)
+void mbed_sdk_init_forced(void) __attribute__((constructor(101)));
+#elif defined(__ICCARM__)
+    // FIXME: How to achieve it in IAR?
+#endif
+
+
+void mbed_sdk_init(void)
+{
+    // NOTE: Support singleton semantics to be called from other init functions
+    static int inited = 0;
+    if (inited) {
+        return;
+    }
+    inited = 1;
+    
+    /*---------------------------------------------------------------------------------------------------------*/
+    /* Init System Clock                                                                                       */
+    /*---------------------------------------------------------------------------------------------------------*/
+    /* Unlock protected registers */
+    SYS_UnlockReg();
+
+    /* Enable HIRC clock (Internal RC 22.1184MHz) */
+    CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
+    /* Enable HXT clock (external XTAL 12MHz) */
+    CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
+    /* Enable LIRC for lp_ticker */
+    CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
+    /* Enable LXT for RTC */
+    CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
+
+    /* Wait for HIRC clock ready */
+    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+    /* Wait for HXT clock ready */
+    CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+    /* Wait for LIRC clock ready */
+    CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
+    /* Wait for LXT clock ready */
+    CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
+
+    /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */
+    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
+    
+    /* Set core clock as 72000000 from PLL */
+    CLK_SetCoreClock(72000000);
+
+#if DEVICE_ANALOGIN
+    // FIXME: Check voltage reference for EADC
+    /* Vref connect to AVDD */
+    //SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_AVDD;
+#endif
+    
+    /* Update System Core Clock */
+    /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
+    SystemCoreClockUpdate();
+
+    /* Lock protected registers */
+    SYS_LockReg();
+}
+
+void mbed_sdk_init_forced(void)
+{
+    mbed_sdk_init();
+}
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h
new file mode 100644
index 00000000000..e06ff861eb7
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h
@@ -0,0 +1,132 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "dma_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    //IRQn_Type irq_n;
+    //uint32_t irq_index;
+    //uint32_t event;
+    
+    PinName     pin;
+    uint32_t    irq_handler;
+    uint32_t    irq_id;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+};
+
+struct analogin_s {
+    ADCName adc;
+    //PinName pin;
+};
+
+struct serial_s {
+    UARTName uart;
+    PinName pin_tx;
+    PinName pin_rx;
+    
+    uint32_t baudrate;
+    uint32_t databits;
+    uint32_t parity;
+    uint32_t stopbits;
+    
+    void        (*vec)(void);
+    uint32_t    irq_handler;
+    uint32_t    irq_id;
+    uint32_t    inten_msk;
+    
+    // Async transfer related fields
+    DMAUsage    dma_usage_tx;
+    DMAUsage    dma_usage_rx;
+    int         dma_chn_id_tx;
+    int         dma_chn_id_rx;
+    uint32_t    event;
+    void        (*irq_handler_tx_async)(void);
+    void        (*irq_handler_rx_async)(void);
+};
+
+struct spi_s {
+    SPIName spi;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+    
+    //void        (*vec)(void);
+    
+    // Async transfer related fields
+    DMAUsage    dma_usage;
+    int         dma_chn_id_tx;
+    int         dma_chn_id_rx;
+    uint32_t    event;
+    //void        (*irq_handler_tx_async)(void);
+    //void        (*irq_handler_rx_async)(void);
+};
+
+struct i2c_s {
+    I2CName     i2c;
+    //void        (*vec)(void);
+    int         slaveaddr_state;
+    
+    uint32_t    tran_ctrl;
+    char *      tran_beg;
+    char *      tran_pos;
+    char *      tran_end;
+    int         inten;
+
+    // Async transfer related fields
+    DMAUsage    dma_usage;
+    uint32_t    event;
+    int         stop;
+    uint32_t    address;
+};
+
+struct pwmout_s {
+    PWMName pwm;
+    //PinName pin;
+    uint32_t period_us;
+    uint32_t pulsewidth_us;
+};
+
+struct sleep_s {
+    uint32_t start_us;
+    uint32_t end_us;
+    uint32_t period_us;
+    int powerdown;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#include "gpio_object.h"
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M451/analogin_api.c
new file mode 100644
index 00000000000..6ea0173958c
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/analogin_api.c
@@ -0,0 +1,160 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+
+struct nu_adc_var {
+    uint32_t    en_msk;
+};
+
+static struct nu_adc_var adc0_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc1_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc2_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc3_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc4_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc5_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc6_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc7_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc8_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc9_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc10_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc11_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc12_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc13_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc14_var = {
+    .en_msk = 0
+};
+static struct nu_adc_var adc15_var = {
+    .en_msk = 0
+};
+
+static const struct nu_modinit_s adc_modinit_tab[] = {
+    {ADC_0_0, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc0_var},
+    {ADC_0_1, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc1_var},
+    {ADC_0_2, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc2_var},
+    {ADC_0_3, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc3_var},
+    {ADC_0_4, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc4_var},
+    {ADC_0_5, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc5_var},
+    {ADC_0_6, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc6_var},
+    {ADC_0_7, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc7_var},
+    {ADC_0_8, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc8_var},
+    {ADC_0_9, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc9_var},
+    {ADC_0_10, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc10_var},
+    {ADC_0_11, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc11_var},
+    {ADC_0_12, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc12_var},
+    {ADC_0_13, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc13_var},
+    {ADC_0_14, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc14_var},
+    {ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc15_var},
+};
+
+void analogin_init(analogin_t *obj, PinName pin)
+{   
+    obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC);
+    MBED_ASSERT(obj->adc != (ADCName) NC);
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->adc);
+    
+    EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
+    
+    // NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module.
+    if (! ((struct nu_adc_var *) modinit->var)->en_msk) {
+        // Reset this module if no channel enabled
+        SYS_ResetModule(modinit->rsetidx);
+        
+        // Select clock source of paired channels
+        CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
+        // Enable clock of paired channels
+        CLK_EnableModuleClock(modinit->clkidx);
+        
+        // Power on ADC
+        //ADC_POWER_ON(ADC);
+        
+        // Set the ADC internal sampling time, input mode as single-end and enable the A/D converter
+        EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END);
+        EADC_SetInternalSampleTime(eadc_base, 6);
+    }
+    
+    uint32_t chn =  NU_MODSUBINDEX(obj->adc);
+    
+    // Wire pinout
+    pinmap_pinout(pin, PinMap_ADC);
+    
+    // Configure the sample module Nmod for analog input channel Nch and software trigger source
+    EADC_ConfigSampleModule(EADC, chn, EADC_SOFTWARE_TRIGGER, chn);
+    
+    ((struct nu_adc_var *) modinit->var)->en_msk |= 1 << chn;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
+    uint32_t chn =  NU_MODSUBINDEX(obj->adc);
+    
+    EADC_START_CONV(eadc_base, 1 << chn);
+    while (EADC_GET_PENDING_CONV(eadc_base) & (1 << chn));
+    uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn);
+    // Just 12 bits are effective. Convert to 16 bits.
+    // conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0
+    // conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8
+    uint16_t conv_res_16 = (conv_res_12 << 4) | (conv_res_12 >> 8);
+    
+    return conv_res_16;
+}
+
+float analogin_read(analogin_t *obj)
+{
+    uint16_t value = analogin_read_u16(obj);
+    return (float) value * (1.0f / (float) 0xFFFF);
+}
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/dma.h b/targets/TARGET_NUVOTON/TARGET_M451/dma.h
new file mode 100644
index 00000000000..1faf3c05813
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/dma.h
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_DMA_H
+#define MBED_DMA_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DMA_CAP_NONE    (0 << 0)
+
+#define DMA_EVENT_ABORT             (1 << 0)
+#define DMA_EVENT_TRANSFER_DONE     (1 << 1)
+#define DMA_EVENT_TIMEOUT           (1 << 2)
+#define DMA_EVENT_ALL               (DMA_EVENT_ABORT | DMA_EVENT_TRANSFER_DONE | DMA_EVENT_TIMEOUT)
+#define DMA_EVENT_MASK              DMA_EVENT_ALL
+
+void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/dma_api.c b/targets/TARGET_NUVOTON/TARGET_M451/dma_api.c
new file mode 100644
index 00000000000..ddecc9ca634
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/dma_api.c
@@ -0,0 +1,178 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "dma_api.h"
+#include "string.h"
+#include "cmsis.h"
+#include "mbed_assert.h"
+#include "PeripheralNames.h"
+#include "nu_modutil.h"
+#include "nu_bitutil.h"
+#include "dma.h"
+
+struct nu_dma_chn_s {
+    void        (*handler)(uint32_t, uint32_t);
+    uint32_t    id;
+    uint32_t    event;
+};
+
+static int dma_inited = 0;
+static uint32_t dma_chn_mask = 0;
+static struct nu_dma_chn_s dma_chn_arr[PDMA_CH_MAX];
+
+static void pdma_vec(void);
+static const struct nu_modinit_s dma_modinit = {DMA_0, PDMA_MODULE, 0, 0, PDMA_RST, PDMA_IRQn, (void *) pdma_vec};
+
+
+void dma_init(void)
+{
+    if (dma_inited) {
+        return;
+    }
+    
+    dma_inited = 1;
+    dma_chn_mask = 0;
+    memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr));
+    
+    // Reset this module
+    SYS_ResetModule(dma_modinit.rsetidx);
+    
+    // Enable IP clock
+    CLK_EnableModuleClock(dma_modinit.clkidx);
+    
+    PDMA_Open(0);
+    
+    NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
+    NVIC_EnableIRQ(dma_modinit.irq_n);
+}
+
+int dma_channel_allocate(uint32_t capabilities)
+{
+    if (! dma_inited) {
+        dma_init();
+    }
+    
+#if 1
+    int i = nu_cto(dma_chn_mask);
+    if (i != 32) {
+         dma_chn_mask |= 1 << i;
+         memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s));
+         return i;
+    }
+#else
+    int i;
+    
+    for (i = 0; i < PDMA_CH_MAX; i ++) {
+        if ((dma_chn_mask & (1 << i)) == 0) {
+            // Channel available
+            dma_chn_mask |= 1 << i;
+            memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s));
+            return i;
+        }
+    }
+#endif
+
+    // No channel available
+    return DMA_ERROR_OUT_OF_CHANNELS;
+}
+
+int dma_channel_free(int channelid)
+{
+    if (channelid != DMA_ERROR_OUT_OF_CHANNELS) {
+        dma_chn_mask &= ~(1 << channelid);
+    }
+    
+    return 0;
+}
+
+void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event)
+{
+    MBED_ASSERT(dma_chn_mask & (1 << channelid));
+    
+    dma_chn_arr[channelid].handler = (void (*)(uint32_t, uint32_t)) handler;
+    dma_chn_arr[channelid].id = id;
+    dma_chn_arr[channelid].event = event;
+    
+    // Set interrupt vector if someone has removed it.
+    NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
+    NVIC_EnableIRQ(dma_modinit.irq_n);
+}
+
+static void pdma_vec(void)
+{
+    uint32_t intsts = PDMA_GET_INT_STATUS();
+    
+    // Abort
+    if (intsts & PDMA_INTSTS_ABTIF_Msk) {
+        uint32_t abtsts = PDMA_GET_ABORT_STS();
+        // Clear all Abort flags
+        PDMA_CLR_ABORT_FLAG(abtsts);
+        
+        while (abtsts) {
+            int chn_id = nu_ctz(abtsts);
+            if (dma_chn_mask & (1 << chn_id)) {
+                struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
+                if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) {
+                    dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT);
+                }
+            }
+            abtsts &= ~(1 << chn_id);
+        }
+    }
+    
+    // Transfer done
+    if (intsts & PDMA_INTSTS_TDIF_Msk) {
+        uint32_t tdsts = PDMA_GET_TD_STS();    
+        // Clear all transfer done flags
+        PDMA_CLR_TD_FLAG(tdsts);
+        
+        while (tdsts) {
+            int chn_id = nu_ctz(tdsts);
+            if (dma_chn_mask & (1 << chn_id)) {
+                struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
+                if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) {
+                    dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE);
+                }
+            }
+            tdsts &= ~(1 << chn_id);
+        }
+    }
+    
+    // Table empty
+    if (intsts & PDMA_INTSTS_TEIF_Msk) {
+        uint32_t scatsts = PDMA_GET_EMPTY_STS();    
+        // Clear all table empty flags
+        PDMA_CLR_EMPTY_FLAG(scatsts);
+    }
+    
+    // Timeout
+    uint32_t reqto = intsts & PDMA_INTSTS_REQTOFn_Msk;
+    if (reqto) {
+        // Clear all Timeout flags
+        PDMA->INTSTS = reqto;
+        
+        while (reqto) {
+            int chn_id = nu_ctz(reqto) >> PDMA_INTSTS_REQTOFn_Pos;
+            if (dma_chn_mask & (1 << chn_id)) {
+                struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
+                if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) {
+                    dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT);
+                }
+            }
+            reqto &= ~(1 << (chn_id + PDMA_INTSTS_REQTOFn_Pos));
+        }
+    }
+}
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c
new file mode 100644
index 00000000000..39f4e8e30ba
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "gpio_api.h"
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+uint32_t gpio_set(PinName pin)
+{
+    if (pin == (PinName) NC) {
+        return 0;
+    }
+    
+    uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
+    
+#if 1
+    pin_function(pin, 0 << NU_MFP_POS(pin_index));
+#else
+    pinmap_pinout(pin, PinMap_GPIO);
+#endif
+
+    return (uint32_t)(1 << pin_index);    // Return the pin mask
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+    obj->pin = pin;
+    
+    if (obj->pin == (PinName) NC) {
+        return;
+    }
+
+    obj->mask = gpio_set(pin);
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+    if (obj->pin == (PinName) NC) {
+        return;
+    }
+    
+    pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+    if (obj->pin == (PinName) NC) {
+        return;
+    }
+    
+    uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+    GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+    
+    uint32_t mode_intern = GPIO_MODE_INPUT;
+    
+    switch (direction) {
+        case PIN_INPUT:
+            mode_intern = GPIO_MODE_INPUT;
+            break;
+        
+        case PIN_OUTPUT:
+            mode_intern = GPIO_MODE_OUTPUT;
+            break;
+            
+        default:
+            return;
+    }
+    
+    GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+}
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c
new file mode 100644
index 00000000000..c2adef9954b
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c
@@ -0,0 +1,205 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "gpio_irq_api.h"
+
+#if DEVICE_INTERRUPTIN
+
+#include "gpio_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_bitutil.h"
+
+#define NU_MAX_PIN_PER_PORT     16
+
+struct nu_gpio_irq_var {
+    gpio_irq_t *    obj_arr[NU_MAX_PIN_PER_PORT];
+    IRQn_Type       irq_n;
+    void            (*vec)(void);
+};
+
+static void gpio_irq_0_vec(void);
+static void gpio_irq_1_vec(void);
+static void gpio_irq_2_vec(void);
+static void gpio_irq_3_vec(void);
+static void gpio_irq_4_vec(void);
+static void gpio_irq_5_vec(void);
+static void gpio_irq(struct nu_gpio_irq_var *var);
+
+//EINT0_IRQn
+static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
+    {{NULL}, GPA_IRQn, gpio_irq_0_vec},
+    {{NULL}, GPB_IRQn, gpio_irq_1_vec},
+    {{NULL}, GPC_IRQn, gpio_irq_2_vec},
+    {{NULL}, GPD_IRQn, gpio_irq_3_vec},
+    {{NULL}, GPE_IRQn, gpio_irq_4_vec},
+    {{NULL}, GPF_IRQn, gpio_irq_5_vec}
+};
+
+#define NU_MAX_PORT     (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+    if (pin == NC) {
+        return -1;
+    }
+    
+    uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(pin);
+    if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) {
+        return -1;
+    }
+    
+    obj->pin = pin;
+    obj->irq_handler = (uint32_t) handler;
+    obj->irq_id = id;
+
+    //gpio_set(pin);
+    
+    // Configure de-bounce clock source and sampling cycle time
+    GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_16);
+    
+    struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
+    
+    MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
+    var->obj_arr[pin_index] = obj;
+    
+    // NOTE: InterruptIn requires IRQ enabled by default.
+    gpio_irq_enable(obj);
+    
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+    uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+    struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
+    
+    NVIC_DisableIRQ(var->irq_n);
+    NU_PORT_BASE(port_index)->INTEN = 0;
+    
+    MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
+    var->obj_arr[pin_index] = NULL;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+    uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+    GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+    
+    switch (event) {
+        case IRQ_RISE:
+            if (enable) {
+                GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
+                GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
+            }
+            else {
+                gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index);
+            }
+            break;
+        
+        case IRQ_FALL:
+            if (enable) {
+                GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
+                GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
+            }
+            else {
+                gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index);
+            }
+            break;
+    }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+    //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+    struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
+    
+    NVIC_SetVector(var->irq_n, (uint32_t) var->vec);
+    NVIC_EnableIRQ(var->irq_n);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+    //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+    struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
+    
+    NVIC_DisableIRQ(var->irq_n);
+}
+
+static void gpio_irq_0_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 0);
+}
+static void gpio_irq_1_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 1);
+}
+static void gpio_irq_2_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 2);
+}
+static void gpio_irq_3_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 3);
+}
+static void gpio_irq_4_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 4);
+}
+static void gpio_irq_5_vec(void)
+{
+    gpio_irq(gpio_irq_var_arr + 5);
+}
+
+static void gpio_irq(struct nu_gpio_irq_var *var)
+{
+    uint32_t port_index = var->irq_n - GPA_IRQn;
+    GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+    
+    uint32_t intsrc = gpio_base->INTSRC;
+    uint32_t inten = gpio_base->INTEN;
+    while (intsrc) {
+        int pin_index = nu_ctz(intsrc);
+        gpio_irq_t *obj = var->obj_arr[pin_index];
+        if (inten & (GPIO_INT_RISING << pin_index)) {
+            if (GPIO_PIN_DATA(port_index, pin_index)) {
+                if (obj->irq_handler) {
+                    ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE);
+                }
+            }
+        }
+        
+        if (inten & (GPIO_INT_FALLING << pin_index)) {   
+            if (! GPIO_PIN_DATA(port_index, pin_index)) {
+                if (obj->irq_handler) {
+                    ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL);
+                }
+            }
+        }
+        
+        intsrc &= ~(1 << pin_index);
+    }
+    // Clear all interrupt flags
+    gpio_base->INTSRC = gpio_base->INTSRC;
+}
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/gpio_object.h b/targets/TARGET_NUVOTON/TARGET_M451/gpio_object.h
new file mode 100644
index 00000000000..282bae437b7
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/gpio_object.h
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName  pin;
+    uint32_t mask;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);    
+    uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+    
+    GPIO_PIN_DATA(port_index, pin_index) = value ? 1 : 0;
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
+    
+    return (GPIO_PIN_DATA(port_index, pin_index) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c
new file mode 100644
index 00000000000..92b5c7a9f0f
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c
@@ -0,0 +1,1025 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "nu_bitutil.h"
+#include "critical.h"
+
+#define NU_I2C_DEBUG    0
+
+#if NU_I2C_DEBUG
+struct i2c_s MY_I2C;
+struct i2c_s MY_I2C_2;
+char MY_I2C_STATUS[64];
+int MY_I2C_STATUS_POS = 0;
+uint32_t MY_I2C_TIMEOUT;
+uint32_t MY_I2C_ELAPSED;
+uint32_t MY_I2C_T1;
+uint32_t MY_I2C_T2;
+#endif
+
+struct nu_i2c_var {
+    i2c_t *     obj;
+    void        (*vec)(void);
+};
+
+static void i2c0_vec(void);
+static void i2c1_vec(void);
+static void i2c_irq(i2c_t *obj);
+static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl);
+
+static struct nu_i2c_var i2c0_var = {
+    .obj                =   NULL,
+    .vec                =   i2c0_vec,
+};
+static struct nu_i2c_var i2c1_var = {
+    .obj                =   NULL,
+    .vec                =   i2c1_vec,
+};
+
+static uint32_t i2c_modinit_mask = 0;
+
+static const struct nu_modinit_s i2c_modinit_tab[] = {
+    {I2C_0, I2C0_MODULE, 0, 0, I2C0_RST, I2C0_IRQn, &i2c0_var},
+    {I2C_1, I2C1_MODULE, 0, 0, I2C1_RST, I2C1_IRQn, &i2c1_var},
+    
+    {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata);
+static int i2c_do_write(i2c_t *obj, char data, int naklastdata);
+static int i2c_do_read(i2c_t *obj, char *data, int naklastdata);
+static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
+#define NU_I2C_TIMEOUT_STAT_INT     500000
+#define NU_I2C_TIMEOUT_STOP         500000
+static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout);
+static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout);
+static int i2c_is_stat_int(i2c_t *obj);
+static int i2c_is_stop_det(i2c_t *obj);
+static int i2c_is_trsn_done(i2c_t *obj);
+static int i2c_is_tran_started(i2c_t *obj);
+static int i2c_addr2data(int address, int read);
+#if DEVICE_I2CSLAVE
+// Convert mbed address to BSP address.
+static int i2c_addr2bspaddr(int address);
+#endif  // #if DEVICE_I2CSLAVE
+static void i2c_enable_int(i2c_t *obj);
+static void i2c_disable_int(i2c_t *obj);
+static int i2c_set_int(i2c_t *obj, int inten);
+
+
+#if DEVICE_I2C_ASYNCH
+static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
+static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable);
+static void i2c_rollback_vector_interrupt(i2c_t *obj);
+#endif
+
+#define TRANCTRL_STARTED        (1)
+#define TRANCTRL_NAKLASTDATA    (1 << 1)
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+    uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
+    uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
+    obj->i2c.i2c = (I2CName) pinmap_merge(i2c_sda, i2c_scl);
+    MBED_ASSERT((int)obj->i2c.i2c != NC);
+    
+    const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->i2c.i2c);
+    
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+    
+    // Enable IP clock
+    CLK_EnableModuleClock(modinit->clkidx);
+
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+    
+#if DEVICE_I2C_ASYNCH
+    obj->i2c.dma_usage = DMA_USAGE_NEVER;
+    obj->i2c.event = 0;
+    obj->i2c.stop = 0;
+    obj->i2c.address = 0;
+#endif
+
+    // NOTE: Setting I2C bus clock to 100 KHz is required. See I2C::I2C in common/I2C.cpp.
+    I2C_Open((I2C_T *) NU_MODBASE(obj->i2c.i2c), 100000);
+    // NOTE: INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL. We cannot control interrupt through 
+    //       INTEN bit without impacting FSM control bits. Use NVIC_EnableIRQ/NVIC_DisableIRQ instead for interrupt control.
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    i2c_base->CTL |= (I2C_CTL_INTEN_Msk | I2C_CTL_I2CEN_Msk);
+
+    // Enable sync-moce vector interrupt.
+    struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
+    var->obj = obj;
+    obj->i2c.tran_ctrl = 0;
+    obj->i2c.stop = 0;
+    i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
+    
+    // Mark this module to be inited.
+    int i = modinit - i2c_modinit_tab;
+    i2c_modinit_mask |= 1 << i;
+}
+
+int i2c_start(i2c_t *obj)
+{
+    return i2c_do_trsn(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk, 1);
+}
+
+int i2c_stop(i2c_t *obj)
+{
+    return i2c_do_trsn(obj, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk, 1);
+}
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+    I2C_SetBusClockFreq((I2C_T *) NU_MODBASE(obj->i2c.i2c), hz);
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+    int i;
+
+    if (i2c_start(obj)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+
+    if (i2c_do_write(obj, i2c_addr2data(address, 1), 0)) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    // Read in bytes
+    length = i2c_do_tran(obj, data, length, 1, 1);
+
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+
+    return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+    int i;
+
+    if (i2c_start(obj)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+
+    if (i2c_do_write(obj, i2c_addr2data(address, 0), 0)) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    // Write out bytes
+    length = i2c_do_tran(obj, (char *) data, length, 0, 1);
+
+    if (stop) {
+        i2c_stop(obj);
+    }
+
+    return length;
+}
+
+void i2c_reset(i2c_t *obj)
+{
+    i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+    char data = 0;
+    
+    i2c_do_read(obj, &data, last);
+    return data;
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+    return i2c_do_write(obj, (data & 0xFF), 0);
+}
+
+#if DEVICE_I2CSLAVE
+
+// See I2CSlave.h
+#define NoData         0    // the slave has not been addressed
+#define ReadAddressed  1    // the master has requested a read from this slave (slave = transmitter)
+#define WriteGeneral   2    // the master is writing to all slave
+#define WriteAddressed 3    // the master is writing to this slave (slave = receiver)
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    
+    i2c_disable_int(obj);
+
+    obj->i2c.slaveaddr_state = NoData;
+    
+    // Switch to not addressed mode
+    I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
+    
+    i2c_enable_int(obj);
+}
+
+int i2c_slave_receive(i2c_t *obj)
+{
+    int slaveaddr_state;
+    
+    i2c_disable_int(obj);
+    slaveaddr_state = obj->i2c.slaveaddr_state;
+    i2c_enable_int(obj);
+    
+    return slaveaddr_state;
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length)
+{
+    return i2c_do_tran(obj, data, length, 1, 1);
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length)
+{
+    return i2c_do_tran(obj, (char *) data, length, 0, 1);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    
+    i2c_disable_int(obj);
+    
+    I2C_SetSlaveAddr(i2c_base, 0, i2c_addr2bspaddr(address), I2C_GCMODE_ENABLE);
+    
+    i2c_enable_int(obj);
+}
+
+static int i2c_addr2bspaddr(int address)
+{
+    return (address >> 1);
+}
+
+#endif // #if DEVICE_I2CSLAVE
+
+static void i2c_enable_int(i2c_t *obj)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+    
+    core_util_critical_section_enter();
+    
+    // Enable I2C interrupt
+    NVIC_EnableIRQ(modinit->irq_n);
+    obj->i2c.inten = 1;
+    
+    core_util_critical_section_exit();
+}
+
+static void i2c_disable_int(i2c_t *obj)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+    
+    core_util_critical_section_enter();
+    
+    // Disable I2C interrupt
+    NVIC_DisableIRQ(modinit->irq_n);
+    obj->i2c.inten = 0;
+    
+    core_util_critical_section_exit();
+}
+
+static int i2c_set_int(i2c_t *obj, int inten)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    int inten_back;
+    
+    core_util_critical_section_enter();
+    
+    inten_back = obj->i2c.inten;
+    
+    core_util_critical_section_exit();
+    
+    if (inten) {
+        i2c_enable_int(obj);
+    }
+    else {
+        i2c_disable_int(obj);
+    }
+    
+    return inten_back;
+}
+
+int i2c_allow_powerdown(void)
+{
+    uint32_t modinit_mask = i2c_modinit_mask;
+    while (modinit_mask) {
+        int i2c_idx = nu_ctz(modinit_mask);
+        const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx;
+        struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
+        if (var->obj) {
+            // Disallow entering power-down mode if I2C transfer is enabled.
+            if (i2c_active(var->obj)) {
+                return 0;
+            }
+        }
+        modinit_mask &= ~(1 << i2c_idx);
+    }
+    
+    return 1;
+}
+
+static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    int err = 0;
+    int tran_len = 0;
+    
+    i2c_disable_int(obj);
+    obj->i2c.tran_ctrl = naklastdata ? (TRANCTRL_STARTED | TRANCTRL_NAKLASTDATA) : TRANCTRL_STARTED;
+    obj->i2c.tran_beg = buf;
+    obj->i2c.tran_pos = buf;
+    obj->i2c.tran_end = buf + length;
+    i2c_enable_int(obj);
+    
+    if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) {
+        err = I2C_ERROR_BUS_BUSY;
+#if NU_I2C_DEBUG
+        MY_I2C_2 = obj->i2c;
+        while (1);
+#endif
+    }
+    else {
+        i2c_disable_int(obj);
+        obj->i2c.tran_ctrl = 0;
+        tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg;
+        obj->i2c.tran_beg = NULL;
+        obj->i2c.tran_pos = NULL;
+        obj->i2c.tran_end = NULL;
+        i2c_enable_int(obj);
+    }
+    
+    return tran_len;
+}
+
+static int i2c_do_write(i2c_t *obj, char data, int naklastdata)
+{
+    char data_[1];
+    data_[0] = data;
+    return i2c_do_tran(obj, data_, 1, 0, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
+}
+
+static int i2c_do_read(i2c_t *obj, char *data, int naklastdata)
+{
+    return i2c_do_tran(obj, data, 1, 1, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
+}
+
+static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    int err = 0;
+    
+    i2c_disable_int(obj);
+
+    if (i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
+        err = I2C_ERROR_BUS_BUSY;
+#if NU_I2C_DEBUG
+        MY_I2C_2 = obj->i2c;
+        while (1);
+#endif
+    }
+    else {
+#if 1
+        // NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error.
+        uint32_t status = I2C_GET_STATUS(i2c_base);
+        
+        switch (status) {
+        case 0x08:  // Start
+        case 0x10:  // Master Repeat Start
+            if (i2c_ctl & I2C_CTL_STA_Msk) {
+                return 0;
+            }
+            else {
+                break;
+            }
+        case 0xF8:  // Bus Released
+            if (i2c_ctl & (I2C_CTL_STA_Msk | I2C_CTL_STO_Msk) == I2C_CTL_STO_Msk) {
+                return 0;
+            }
+            else {
+                break;
+            }
+        }
+#endif        
+        I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
+        if (sync && i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
+            err = I2C_ERROR_BUS_BUSY;
+#if NU_I2C_DEBUG
+            MY_I2C_2 = obj->i2c;
+            while (1);
+#endif
+        }
+    }
+
+    i2c_enable_int(obj);
+    
+    return err;
+}
+
+static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout)
+{
+    uint32_t t1, t2, elapsed = 0;
+    int status_assert = 0;
+    
+    t1 = us_ticker_read();
+    while (1) {
+        status_assert = is_status(obj);
+        if (status_assert) {
+            break;
+        }
+        
+        t2 = us_ticker_read();
+        elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
+        if (elapsed >= timeout) {
+#if NU_I2C_DEBUG
+            MY_I2C_T1 = t1;
+            MY_I2C_T2 = t2;
+            MY_I2C_ELAPSED = elapsed;
+            MY_I2C_TIMEOUT = timeout;
+            MY_I2C_2 = obj->i2c;
+            while (1);
+#endif
+            break;
+        }
+    }
+    
+    return (elapsed >= timeout);
+}
+
+static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
+{
+    uint32_t t1, t2, elapsed = 0;
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    int tran_started;
+    char *tran_pos = NULL;
+    char *tran_pos2 = NULL;
+    
+    i2c_disable_int(obj);
+    tran_pos = obj->i2c.tran_pos;
+    i2c_enable_int(obj);
+    t1 = us_ticker_read();
+    while (1) {
+        i2c_disable_int(obj);
+        tran_started = i2c_is_tran_started(obj);
+        i2c_enable_int(obj);
+        if (! tran_started) {    // Transfer completed or stopped
+            break;
+        }
+        
+        i2c_disable_int(obj);
+        tran_pos2 = obj->i2c.tran_pos;
+        i2c_enable_int(obj);
+        t2 = us_ticker_read();
+        if (tran_pos2 != tran_pos) {    // Transfer on-going
+            t1 = t2;
+            tran_pos = tran_pos2;
+            continue;
+        }
+        
+        elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
+        if (elapsed >= timeout) {   // Transfer idle
+#if NU_I2C_DEBUG
+            MY_I2C = obj->i2c;
+            MY_I2C_T1 = t1;
+            MY_I2C_T2 = t2;
+            MY_I2C_ELAPSED = elapsed;
+            MY_I2C_TIMEOUT = timeout;
+            MY_I2C_2 = obj->i2c;
+            while (1);
+#endif
+            break;
+        }
+    }
+    
+    return (elapsed >= timeout);
+}
+static int i2c_is_stat_int(i2c_t *obj)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+
+    return !! (i2c_base->CTL & I2C_CTL_SI_Msk);
+}
+
+static int i2c_is_stop_det(i2c_t *obj)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+
+    return ! (i2c_base->CTL & I2C_CTL_STO_Msk);
+}
+
+static int i2c_is_trsn_done(i2c_t *obj)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    int i2c_int;
+    uint32_t status;
+    int inten_back;
+    
+    inten_back = i2c_set_int(obj, 0);
+    i2c_int = !! (i2c_base->CTL & I2C_CTL_SI_Msk);
+    status = I2C_GET_STATUS(i2c_base);
+    i2c_set_int(obj, inten_back);
+    
+    return (i2c_int || status == 0xF8);
+}
+
+static int i2c_is_tran_started(i2c_t *obj)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    int started;
+    int inten_back;
+    
+    inten_back = i2c_set_int(obj, 0);
+    started = !! (obj->i2c.tran_ctrl & TRANCTRL_STARTED);
+    i2c_set_int(obj, inten_back);
+    
+    return started;
+}
+
+static int i2c_addr2data(int address, int read)
+{
+    return read ? (address | 1) : (address & 0xFE);
+}
+
+static void i2c0_vec(void)
+{
+    i2c_irq(i2c0_var.obj);
+}
+static void i2c1_vec(void)
+{
+    i2c_irq(i2c1_var.obj);
+}
+
+static void i2c_irq(i2c_t *obj)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    uint32_t status;
+    int data_recv = 0;
+    
+    if (I2C_GET_TIMEOUT_FLAG(i2c_base)) {
+        I2C_ClearTimeoutFlag(i2c_base);
+        return;
+    }
+    
+    status = I2C_GET_STATUS(i2c_base);
+#if NU_I2C_DEBUG
+    if (MY_I2C_STATUS_POS < (sizeof (MY_I2C_STATUS) / sizeof (MY_I2C_STATUS[0]))) {
+        MY_I2C_STATUS[MY_I2C_STATUS_POS ++] = status;
+    }
+    else {
+        memset(MY_I2C_STATUS, 0x00, sizeof (MY_I2C_STATUS));
+        MY_I2C_STATUS_POS = 0;
+    }
+#endif
+    
+    switch (status) {
+        // Master Transmit
+        case 0x28:  // Master Transmit Data ACK
+        case 0x18:  // Master Transmit Address ACK
+        case 0x08:  // Start
+        case 0x10:  // Master Repeat Start
+            if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+                if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+                    I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
+                    I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
+                }
+                else {
+                    if (status == 0x18) {
+                        obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+                        i2c_disable_int(obj);
+                        break;
+                    }
+                    // Go Master Repeat Start
+                    i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
+                }
+            }
+            else {
+                i2c_disable_int(obj);
+            }
+            break;
+        case 0x30:  // Master Transmit Data NACK
+        case 0x20:  // Master Transmit Address NACK
+            // Go Master Repeat Start
+            i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
+            break;
+        case 0x38:  // Master Arbitration Lost
+            i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
+            break;
+        
+        case 0x48:  // Master Receive Address NACK
+            // Go Master Repeat Start
+            i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
+            break;
+        case 0x40:  // Master Receive Address ACK
+        case 0x50:  // Master Receive Data ACK
+        case 0x58:  // Master Receive Data NACK
+            if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+                if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+                    if (status == 0x50 || status == 0x58) {
+                        *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
+                    }
+                    
+                    if (status == 0x58) {
+#if NU_I2C_DEBUG
+                        if (obj->i2c.tran_pos != obj->i2c.tran_end) {
+                            MY_I2C = obj->i2c;
+                            while (1);
+                        }
+#endif
+                        // Go Master Repeat Start
+                        i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
+                    }
+                    else {
+                        uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
+                        if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
+                            obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
+                            // Last data
+                            i2c_ctl &= ~I2C_CTL_AA_Msk;
+                        }
+                        I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
+                    }
+                }
+                else {
+                    obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+                    i2c_disable_int(obj);
+                    break;
+                }
+            }
+            else {
+                i2c_disable_int(obj);
+            }
+            break;
+            
+        //case 0x00:  // Bus error
+        
+        // Slave Transmit
+        case 0xB8:  // Slave Transmit Data ACK
+        case 0xA8:  // Slave Transmit Address ACK
+        case 0xB0:  // Slave Transmit Arbitration Lost
+            if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+                if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+                    uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
+                    
+                    I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
+                    if (obj->i2c.tran_pos == obj->i2c.tran_end &&
+                        obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
+                        // Last data
+                        i2c_ctl &= ~I2C_CTL_AA_Msk;
+                    }
+                    I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
+                }
+                else {
+                    obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+                    i2c_disable_int(obj);
+                    break;
+                }
+            }
+            else {
+                i2c_disable_int(obj);
+            }
+            obj->i2c.slaveaddr_state = ReadAddressed;
+            break;
+        //case 0xA0:  // Slave Transmit Repeat Start or Stop
+        case 0xC0:  // Slave Transmit Data NACK
+        case 0xC8:  // Slave Transmit Last Data ACK
+            obj->i2c.slaveaddr_state = NoData;
+            i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
+            break;
+        
+        // Slave Receive
+        case 0x80:  // Slave Receive Data ACK
+        case 0x88:  // Slave Receive Data NACK
+        case 0x60:  // Slave Receive Address ACK    
+        case 0x68:  // Slave Receive Arbitration Lost
+            obj->i2c.slaveaddr_state = WriteAddressed;
+            if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+                if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+                    if (status == 0x80 || status == 0x88) {
+                        *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
+                    }
+                    
+                    if (status == 0x88) {
+#if NU_I2C_DEBUG
+                        if (obj->i2c.tran_pos != obj->i2c.tran_end) {
+                            MY_I2C = obj->i2c;
+                            while (1);
+                        }
+#endif
+                        obj->i2c.slaveaddr_state = NoData;
+                        i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
+                    }
+                    else {
+                        uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
+                        if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
+                            obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
+                            // Last data
+                            i2c_ctl &= ~I2C_CTL_AA_Msk;
+                        }
+                        I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
+                    }
+                }
+                else {
+                    obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+                    i2c_disable_int(obj);
+                    break;
+                }
+            }
+            else {
+                i2c_disable_int(obj);
+            }
+            break;
+        //case 0xA0:  // Slave Receive Repeat Start or Stop
+        
+        // GC mode
+        //case 0xA0:  // GC mode Repeat Start or Stop
+        case 0x90:  // GC mode Data ACK
+        case 0x98:  // GC mode Data NACK
+        case 0x70:  // GC mode Address ACK
+        case 0x78:  // GC mode Arbitration Lost
+            obj->i2c.slaveaddr_state = WriteAddressed;
+            if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
+                if (obj->i2c.tran_pos < obj->i2c.tran_end) {
+                    if (status == 0x90 || status == 0x98) {
+                        *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
+                    }
+                    
+                    if (status == 0x98) {
+#if NU_I2C_DEBUG
+                        if (obj->i2c.tran_pos != obj->i2c.tran_end) {
+                            MY_I2C = obj->i2c;
+                            while (1);
+                        }
+#endif
+                        obj->i2c.slaveaddr_state = NoData;
+                        i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
+                    }
+                    else {
+                        uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
+                        if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
+                            obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
+                            // Last data
+                            i2c_ctl &= ~I2C_CTL_AA_Msk;
+                        }
+                        I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
+                    }
+                }
+                else {
+                    obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
+                    i2c_disable_int(obj);
+                    break;
+                }
+            }
+            else {
+                i2c_disable_int(obj);
+            }
+            break;
+        
+        case 0xF8:  // Bus Released
+            break;
+            
+        default:
+            i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
+    }
+}
+
+static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl)
+{
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+
+    obj->i2c.stop = 0;
+    
+    obj->i2c.tran_ctrl = 0;
+            
+    I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
+    obj->i2c.slaveaddr_state = NoData;
+}
+
+#if DEVICE_I2C_ASYNCH
+
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+    // NOTE: M451 I2C only supports 7-bit slave address. The mbed I2C address passed in is shifted left by 1 bit (7-bit addr << 1).
+    MBED_ASSERT((address & 0xFFFFFF00) == 0);
+    
+    // NOTE: First transmit and then receive.
+    
+    (void) hint;
+    obj->i2c.dma_usage = DMA_USAGE_NEVER;
+    obj->i2c.stop = stop;
+    obj->i2c.address = address;
+    obj->i2c.event = event;
+    i2c_buffer_set(obj, tx, tx_length, rx, rx_length);
+
+    //I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    
+    i2c_enable_vector_interrupt(obj, handler, 1);
+    i2c_start(obj);
+}
+
+uint32_t i2c_irq_handler_asynch(i2c_t *obj)
+{
+    int event = 0;
+
+    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
+    uint32_t status = I2C_GET_STATUS(i2c_base);
+    switch (status) {
+        case 0x08:  // Start
+        case 0x10: {// Master Repeat Start
+            if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
+                I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0)));
+                I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
+            }
+            else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+                I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1)));
+                I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
+            }
+            else {
+                event = I2C_EVENT_TRANSFER_COMPLETE;
+                if (obj->i2c.stop) {
+                    I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
+                }
+            }
+            break;
+        }
+        
+        case 0x18:  // Master Transmit Address ACK
+        case 0x28:  // Master Transmit Data ACK
+            if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
+                uint8_t *tx = (uint8_t *)obj->tx_buff.buffer;
+                I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]);
+                I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
+            }
+            else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+                I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
+            }
+            else {
+                event = I2C_EVENT_TRANSFER_COMPLETE;
+                if (obj->i2c.stop) {
+                    I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
+                }
+            }
+            break;
+            
+        case 0x20:  // Master Transmit Address NACK
+            event = I2C_EVENT_ERROR_NO_SLAVE;
+            if (obj->i2c.stop) {
+                I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
+            }
+            break;
+            
+        case 0x30:  // Master Transmit Data NACK
+            if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
+                event = I2C_EVENT_TRANSFER_EARLY_NACK;
+                I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
+            }
+            else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+                I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
+            }
+            else {
+                event = I2C_EVENT_TRANSFER_COMPLETE;
+                if (obj->i2c.stop) {
+                    I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
+                }
+            }
+            break;
+                
+        case 0x38:  // Master Arbitration Lost
+            I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);  // Enter not addressed SLV mode
+            event = I2C_EVENT_ERROR;
+            break;
+            
+        case 0x50:  // Master Receive Data ACK
+            if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+                uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
+                rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
+            }
+        case 0x40:  // Master Receive Address ACK
+            I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | ((obj->rx_buff.pos != obj->rx_buff.length - 1) ? I2C_CTL_AA_Msk : 0));
+            break;
+            
+        case 0x48:  // Master Receive Address NACK    
+            event = I2C_EVENT_ERROR_NO_SLAVE;
+            if (obj->i2c.stop) {
+                I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
+            }
+            break;
+            
+        case 0x58:  // Master Receive Data NACK
+            if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
+                uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
+                rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
+            }
+            I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
+            break;
+            
+        case 0x00:  // Bus error
+            event = I2C_EVENT_ERROR;
+            i2c_reset(obj);
+            break;
+            
+        default:
+            event = I2C_EVENT_ERROR;
+            if (obj->i2c.stop) {
+                I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
+            }
+    }
+    
+    if (event) {
+        i2c_rollback_vector_interrupt(obj);
+    }
+
+    return (event & obj->i2c.event);
+}
+
+uint8_t i2c_active(i2c_t *obj)
+{   
+    const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->i2c.i2c);
+    
+    // Vector will be changed for async transfer. Use it to judge if async transfer is on-going.
+    uint32_t vec = NVIC_GetVector(modinit->irq_n);
+    struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
+    return (vec && vec != (uint32_t) var->vec);
+}
+
+void i2c_abort_asynch(i2c_t *obj)
+{
+    i2c_rollback_vector_interrupt(obj);
+    i2c_stop(obj);
+}
+
+static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
+{
+    obj->tx_buff.buffer = (void *) tx;
+    obj->tx_buff.length = tx_length;
+    obj->tx_buff.pos = 0;
+    obj->rx_buff.buffer = rx;
+    obj->rx_buff.length = rx_length;
+    obj->rx_buff.pos = 0;
+}
+
+static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->i2c.i2c);
+    
+    if (enable) {
+        NVIC_SetVector(modinit->irq_n, handler);
+        i2c_enable_int(obj);
+    }
+    else {
+        i2c_disable_int(obj);
+    }
+
+}
+
+static void i2c_rollback_vector_interrupt(i2c_t *obj)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->i2c.i2c);
+    
+    struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
+    i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
+}
+
+#endif
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
new file mode 100644
index 00000000000..3e510fc9eef
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
@@ -0,0 +1,208 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "lp_ticker_api.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "sleep_api.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "critical.h"
+
+// lp_ticker tick = us = timestamp
+// clock of timer peripheral = ms
+#define US_PER_TICK         (1)
+
+#define MS_PER_TMR2_INT     (1000 * 10)
+#define TMR2_FIRE_FREQ      (1000 / MS_PER_TMR2_INT)
+#define MS_PER_TMR2_CLK     1
+#define TMR2_CLK_FREQ       (1000 / MS_PER_TMR2_CLK)
+
+#define MS_PER_TMR3_CLK     1
+#define TMR3_CLK_FREQ       (1000 / MS_PER_TMR3_CLK)
+
+static void tmr2_vec(void);
+static void tmr3_vec(void);
+static void lp_ticker_arm_cd(void);
+
+static int lp_ticker_inited = 0;
+static volatile uint32_t counter_major = 0;
+static volatile int cd_major_minor_ms = 0;
+static volatile int cd_minor_ms = 0;
+static volatile uint32_t wakeup_tick = (uint32_t) -1;
+
+// NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
+// NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
+static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec};
+static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec};
+
+#define TMR_CMP_MIN         2
+#define TMR_CMP_MAX         0xFFFFFFu
+
+void lp_ticker_init(void)
+{
+    if (lp_ticker_inited) {
+        return;
+    }
+    lp_ticker_inited = 1;
+    
+    counter_major = 0;
+    cd_major_minor_ms = 0;
+    cd_minor_ms = 0;
+    wakeup_tick = (uint32_t) -1;
+
+    // Reset module
+    SYS_ResetModule(timer2_modinit.rsetidx);
+    SYS_ResetModule(timer3_modinit.rsetidx);
+    
+    // Select IP clock source
+    CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
+    CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
+    // Enable IP clock
+    CLK_EnableModuleClock(timer2_modinit.clkidx);
+    CLK_EnableModuleClock(timer3_modinit.clkidx);
+
+    // Configure clock
+    uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+    uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_FREQ - 1;
+    MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
+    uint32_t cmp_timer2 = MS_PER_TMR2_INT / MS_PER_TMR2_CLK;
+    MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
+    // Continuous mode
+    // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
+    ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2/* | TIMER_CTL_CNTDATEN_Msk*/;
+    ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
+    
+    // Set vector
+    NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
+    NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
+    
+    NVIC_EnableIRQ(timer2_modinit.irq_n);
+    NVIC_EnableIRQ(timer3_modinit.irq_n);
+    
+    TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+    TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+    
+    // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
+    lp_ticker_set_interrupt(wakeup_tick);
+    
+    // Start timer
+    TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+}
+
+timestamp_t lp_ticker_read()
+{    
+    if (! lp_ticker_inited) {
+        lp_ticker_init();
+    }
+    
+    TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
+    
+    do {
+        uint64_t major_minor_ms;
+        uint32_t minor_ms;
+        
+        // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
+        // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
+        do {
+            core_util_critical_section_enter();
+        
+            // NOTE: Order of reading minor_us/carry here is significant.
+            minor_ms = TIMER_GetCounter(timer2_base) * MS_PER_TMR2_CLK;
+            uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
+            // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
+            if (carry && minor_ms > (MS_PER_TMR2_INT / 2)) {
+                major_minor_ms = (counter_major + 1) * MS_PER_TMR2_INT;
+            }
+            else {
+                major_minor_ms = (counter_major + carry) * MS_PER_TMR2_INT + minor_ms;
+            }
+            
+            core_util_critical_section_exit();
+        }
+        while (minor_ms == 0 || minor_ms == MS_PER_TMR2_INT);
+
+        // Add power-down compensation
+        return (major_minor_ms * 1000 / US_PER_TICK);
+    }
+    while (0);
+}
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+    uint32_t now = lp_ticker_read();
+    wakeup_tick = timestamp;
+    
+    TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+    
+    int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
+    // NOTE: If this event was in the past, arm an interrupt to be triggered immediately.
+    cd_major_minor_ms = delta * US_PER_TICK / 1000;
+
+    lp_ticker_arm_cd();
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+    TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+    TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+}
+
+static void tmr2_vec(void)
+{
+    TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+    TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+    counter_major ++;
+}
+
+static void tmr3_vec(void)
+{
+    TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+    TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+    cd_major_minor_ms -= cd_minor_ms;
+    if (cd_major_minor_ms > 0) {
+        lp_ticker_arm_cd();
+    }
+}
+
+static void lp_ticker_arm_cd(void)
+{
+    TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
+    
+    // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
+    timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk;
+    // One-shot mode, Clock = 1 KHz 
+    uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+    uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_FREQ - 1;
+    MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
+    // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
+    timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
+    timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/;
+    
+    cd_minor_ms = cd_major_minor_ms;
+    cd_minor_ms = NU_CLAMP(cd_minor_ms, TMR_CMP_MIN * MS_PER_TMR3_CLK, TMR_CMP_MAX * MS_PER_TMR3_CLK);
+    timer3_base->CMP = cd_minor_ms / MS_PER_TMR3_CLK;
+    
+    TIMER_EnableInt(timer3_base);
+    TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+    TIMER_Start(timer3_base);
+}
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/pinmap.c b/targets/TARGET_NUVOTON/TARGET_M451/pinmap.c
new file mode 100644
index 00000000000..274c07fe256
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/pinmap.c
@@ -0,0 +1,83 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "PortNames.h"
+#include "mbed_error.h"
+
+/**
+ * Configure pin multi-function
+ */
+void pin_function(PinName pin, int data)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+    uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(pin);
+    __IO uint32_t *GPx_MFPx = ((__IO uint32_t *) &SYS->GPA_MFPL) + port_index * 2 + (pin_index / 8);
+    //uint32_t MFP_Pos = NU_MFP_POS(pin_index);
+    uint32_t MFP_Msk = NU_MFP_MSK(pin_index);
+    
+    // E.g.: SYS->GPA_MFPL  = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0MFP_SC0_CD  ;
+    *GPx_MFPx  = (*GPx_MFPx & (~MFP_Msk)) | data;
+    
+    // [TODO] Disconnect JTAG-DP + SW-DP signals.
+    // Warning: Need to reconnect under reset
+    //if ((pin == PA_13) || (pin == PA_14)) {
+    //
+    //}
+    //if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
+    //
+    //}
+}
+
+/**
+ * Configure pin pull-up/pull-down
+ */
+void pin_mode(PinName pin, PinMode mode)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+    uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
+    uint32_t port_index = NU_PINNAME_TO_PORT(pin);
+    GPIO_T *gpio_base = NU_PORT_BASE(port_index);
+    
+    uint32_t mode_intern = GPIO_MODE_INPUT;
+    
+    switch (mode) {
+        case PullUp:
+            mode_intern = GPIO_MODE_INPUT;
+            break;
+            
+        case PullDown:
+        case PullNone:
+            // NOTE: Not support
+            return;
+        
+        case PushPull:
+            mode_intern = GPIO_MODE_OUTPUT;
+            break;
+            
+        case OpenDrain:
+            mode_intern = GPIO_MODE_OPEN_DRAIN;
+            break;
+            
+        case Quasi:
+            mode_intern = GPIO_MODE_QUASI;
+            break;
+    }
+    
+    GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
+}
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/port_api.c b/targets/TARGET_NUVOTON/TARGET_M451/port_api.c
new file mode 100644
index 00000000000..84278d0dbb1
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/port_api.c
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "port_api.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT
+
+PinName port_pin(PortName port, int pin_n)
+{
+    return (PinName) NU_PORT_N_PIN_TO_PINNAME(port, pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+    obj->port      = port;
+    obj->mask      = mask;
+    obj->direction = dir;
+
+    uint32_t i;
+    obj->direction = dir;
+    for (i = 0; i < GPIO_PIN_MAX; i++) {
+        if (obj->mask & (1 << i)) {
+            gpio_set(port_pin(port, i));
+        }
+    }
+    
+    port_dir(obj, dir);
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+    uint32_t i;
+    obj->direction = dir;
+    for (i = 0; i < GPIO_PIN_MAX; i++) {
+        if (obj->mask & (1 << i)) {
+            if (dir == PIN_OUTPUT) {
+                GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_OUTPUT);
+            } else { // PIN_INPUT
+                GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_INPUT);
+            }
+        }
+    }
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+    uint32_t i;
+    
+    for (i = 0; i < GPIO_PIN_MAX; i++) {
+        if (obj->mask & (1 << i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_write(port_t *obj, int value)
+{
+    uint32_t i;
+    uint32_t port_index = obj->port;
+    
+    for (i = 0; i < GPIO_PIN_MAX; i++) {
+        if (obj->mask & (1 << i)) {
+            GPIO_PIN_DATA(port_index, i) = (value & obj->mask) ? 1 : 0;
+        }
+    }
+}
+
+int port_read(port_t *obj)
+{
+    uint32_t i;
+    uint32_t port_index = obj->port;
+    int value = 0;
+    
+    for (i = 0; i < GPIO_PIN_MAX; i++) {
+        if (obj->mask & (1 << i)) {
+            value = value | (GPIO_PIN_DATA(port_index, i) << i);
+        }
+    }
+    
+    return value;
+}
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c
new file mode 100644
index 00000000000..f89dc4f6a00
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c
@@ -0,0 +1,204 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "pwmout_api.h"
+
+#if DEVICE_PWMOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "nu_bitutil.h"
+
+struct nu_pwm_var {
+    uint32_t    en_msk;
+};
+
+static struct nu_pwm_var pwm0_var = {
+    .en_msk = 0
+};
+
+static struct nu_pwm_var pwm1_var = {
+    .en_msk = 0
+};
+
+static uint32_t pwm_modinit_mask = 0;
+
+static const struct nu_modinit_s pwm_modinit_tab[] = {
+    {PWM_0_0, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0P0_IRQn, &pwm0_var},
+    {PWM_0_1, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0P0_IRQn, &pwm0_var},
+    {PWM_0_2, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0P1_IRQn, &pwm0_var},
+    {PWM_0_3, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0P1_IRQn, &pwm0_var},
+    {PWM_0_4, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0P2_IRQn, &pwm0_var},
+    {PWM_0_5, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0P2_IRQn, &pwm0_var},
+    
+    {PWM_1_0, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1P0_IRQn, &pwm1_var},
+    {PWM_1_1, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1P0_IRQn, &pwm1_var},
+    {PWM_1_2, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1P1_IRQn, &pwm1_var},
+    {PWM_1_3, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1P1_IRQn, &pwm1_var},
+    {PWM_1_4, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1P2_IRQn, &pwm1_var},
+    {PWM_1_5, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1P2_IRQn, &pwm1_var},
+    
+    {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+static void pwmout_config(pwmout_t* obj);
+
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
+    obj->pwm = (PWMName) pinmap_peripheral(pin, PinMap_PWM);
+    MBED_ASSERT((int) obj->pwm != NC);
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->pwm);
+    
+    // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module.
+    if (! ((struct nu_pwm_var *) modinit->var)->en_msk) {
+        // Reset this module if no channel enabled
+        SYS_ResetModule(modinit->rsetidx);
+    }
+    
+    PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
+    uint32_t chn =  NU_MODSUBINDEX(obj->pwm);
+        
+    // NOTE: Channels 0/1/2/3/4/5 share a clock source.
+    if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) {
+        // Select clock source of paired channels
+        CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
+        // Enable clock of paired channels
+        CLK_EnableModuleClock(modinit->clkidx);
+    }
+    
+    // Wire pinout
+    pinmap_pinout(pin, PinMap_PWM);
+    
+    // Default: period = 10 ms, pulse width = 0 ms
+    obj->period_us = 1000 * 10;
+    obj->pulsewidth_us = 0;
+    pwmout_config(obj);
+    
+    // Enable output of the specified PWM channel
+    PWM_EnableOutput(pwm_base, 1 << chn);
+    PWM_Start(pwm_base, 1 << chn);
+    
+    ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn;
+    
+    // Mark this module to be inited.
+    int i = modinit - pwm_modinit_tab;
+    pwm_modinit_mask |= 1 << i;
+}
+
+void pwmout_free(pwmout_t* obj)
+{
+    PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
+    uint32_t chn =  NU_MODSUBINDEX(obj->pwm);
+    PWM_ForceStop(pwm_base, 1 << chn);
+    
+    const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->pwm);
+    ((struct nu_pwm_var *) modinit->var)->en_msk &= ~(1 << chn);
+    
+    
+    if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) {
+        CLK_DisableModuleClock(modinit->clkidx);
+    }
+    
+    // Mark this module to be deinited.
+    int i = modinit - pwm_modinit_tab;
+    pwm_modinit_mask &= ~(1 << i);
+}
+
+void pwmout_write(pwmout_t* obj, float value)
+{
+    obj->pulsewidth_us = NU_CLAMP((uint32_t) (value * obj->period_us), 0, obj->period_us);
+    pwmout_config(obj);
+}
+
+float pwmout_read(pwmout_t* obj)
+{
+    return NU_CLAMP((((float) obj->pulsewidth_us) / obj->period_us), 0.0f, 1.0f);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds)
+{
+    pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
+    pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us)
+{
+    uint32_t period_us_old = obj->period_us;
+    uint32_t pulsewidth_us_old = obj->pulsewidth_us;
+    obj->period_us = us;
+    obj->pulsewidth_us = NU_CLAMP(obj->period_us * pulsewidth_us_old / period_us_old, 0, obj->period_us);
+    pwmout_config(obj);
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
+    obj->pulsewidth_us = NU_CLAMP(us, 0, obj->period_us);
+    pwmout_config(obj);
+}
+
+int pwmout_allow_powerdown(void)
+{
+    uint32_t modinit_mask = pwm_modinit_mask;
+    while (modinit_mask) {
+        int pwm_idx = nu_ctz(modinit_mask);
+        const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx;
+        if (modinit->modname != NC) {
+            PWM_T *pwm_base = (PWM_T *) NU_MODBASE(modinit->modname);
+            uint32_t chn = NU_MODSUBINDEX(modinit->modname);
+            // Disallow entering power-down mode if PWM counter is enabled.
+            if ((pwm_base->CNTEN & (1 << chn)) && pwm_base->CMPDAT[chn]) {
+                return 0;
+            }
+        }
+        modinit_mask &= ~(1 << pwm_idx);
+    }
+    
+    return 1;
+}
+
+static void pwmout_config(pwmout_t* obj)
+{
+    PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
+    uint32_t chn = NU_MODSUBINDEX(obj->pwm);
+    // NOTE: Support period < 1s
+    //PWM_ConfigOutputChannel(pwm_base, chn, 1000 * 1000 / obj->period_us, obj->pulsewidth_us * 100 / obj->period_us);
+    PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
+}
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c
new file mode 100644
index 00000000000..9ee5dfd1385
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c
@@ -0,0 +1,121 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "rtc_api.h"
+
+#if DEVICE_RTC
+
+#include "wait_api.h"
+#include "mbed_error.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+
+#define YEAR0       1900
+//#define EPOCH_YR    1970
+static int rtc_inited = 0;
+
+static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
+
+void rtc_init(void)
+{
+    if (rtc_inited) {
+        return;
+    }
+    rtc_inited = 1;
+    
+    // Enable IP clock
+    CLK_EnableModuleClock(rtc_modinit.clkidx);
+    
+    RTC_Open(NULL);
+}
+
+void rtc_free(void)
+{
+    // FIXME
+}
+
+int rtc_isenabled(void)
+{
+    return rtc_inited;
+}
+
+/*
+ struct tm
+   tm_sec      seconds after the minute 0-61
+   tm_min      minutes after the hour 0-59
+   tm_hour     hours since midnight 0-23
+   tm_mday     day of the month 1-31
+   tm_mon      months since January 0-11
+   tm_year     years since 1900
+   tm_wday     days since Sunday 0-6
+   tm_yday     days since January 1 0-365
+   tm_isdst    Daylight Saving Time flag
+*/
+
+time_t rtc_read(void)
+{
+    if (! rtc_inited) {
+        rtc_init();
+    }
+    
+    S_RTC_TIME_DATA_T rtc_datetime;
+    RTC_GetDateAndTime(&rtc_datetime);
+    
+    struct tm timeinfo;
+
+    // Convert struct tm to S_RTC_TIME_DATA_T
+    timeinfo.tm_year = rtc_datetime.u32Year - YEAR0;
+    timeinfo.tm_mon  = rtc_datetime.u32Month - 1;
+    timeinfo.tm_mday = rtc_datetime.u32Day;
+    timeinfo.tm_wday = rtc_datetime.u32DayOfWeek;
+    timeinfo.tm_hour = rtc_datetime.u32Hour;
+    timeinfo.tm_min  = rtc_datetime.u32Minute;
+    timeinfo.tm_sec  = rtc_datetime.u32Second;
+
+    // Convert to timestamp
+    time_t t = mktime(&timeinfo);
+
+    return t;
+}
+
+void rtc_write(time_t t)
+{
+    if (! rtc_inited) {
+        rtc_init();
+    }
+    
+    // Convert timestamp to struct tm
+    struct tm *timeinfo = localtime(&t);
+
+    S_RTC_TIME_DATA_T rtc_datetime;
+    
+    // Convert S_RTC_TIME_DATA_T to struct tm
+    rtc_datetime.u32Year        = timeinfo->tm_year + YEAR0;
+    rtc_datetime.u32Month       = timeinfo->tm_mon + 1;
+    rtc_datetime.u32Day         = timeinfo->tm_mday;
+    rtc_datetime.u32DayOfWeek   = timeinfo->tm_wday;
+    rtc_datetime.u32Hour        = timeinfo->tm_hour;
+    rtc_datetime.u32Minute      = timeinfo->tm_min;
+    rtc_datetime.u32Second      = timeinfo->tm_sec;
+    rtc_datetime.u32TimeScale   = RTC_CLOCK_24;
+    
+    // NOTE: Timing issue with write to RTC registers. This delay is empirical, not rational.
+    RTC_SetDateAndTime(&rtc_datetime);
+    //nu_nop(6000);
+    wait_us(100);
+}
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c
new file mode 100644
index 00000000000..274828c91c1
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c
@@ -0,0 +1,1053 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+#include "cmsis.h"
+#include "mbed_error.h"
+#include "mbed_assert.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+#include "nu_bitutil.h"
+
+#if DEVICE_SERIAL_ASYNCH
+#include "dma_api.h"
+#include "dma.h"
+#endif
+
+struct nu_uart_var {
+    serial_t *  obj;
+    uint32_t    fifo_size_tx;
+    uint32_t    fifo_size_rx;
+    void        (*vec)(void);
+#if DEVICE_SERIAL_ASYNCH
+    void        (*vec_async)(void);
+    uint8_t     pdma_perp_tx;
+    uint8_t     pdma_perp_rx;
+#endif
+};
+
+static void uart0_vec(void);
+static void uart1_vec(void);
+static void uart2_vec(void);
+static void uart3_vec(void);
+static void uart_irq(serial_t *obj);
+
+#if DEVICE_SERIAL_ASYNCH
+static void uart0_vec_async(void);
+static void uart1_vec_async(void);
+static void uart2_vec_async(void);
+static void uart3_vec_async(void);
+static void uart_irq_async(serial_t *obj);
+
+static void uart_dma_handler_tx(uint32_t id, uint32_t event);
+static void uart_dma_handler_rx(uint32_t id, uint32_t event);
+
+static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
+static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
+static int serial_write_async(serial_t *obj);
+static int serial_read_async(serial_t *obj);
+
+static uint32_t serial_rx_event_check(serial_t *obj);
+static uint32_t serial_tx_event_check(serial_t *obj);
+
+static int serial_is_tx_complete(serial_t *obj);
+static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
+
+static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
+static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
+static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
+static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
+static int serial_is_rx_complete(serial_t *obj);
+
+static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
+static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
+#endif
+
+static struct nu_uart_var uart0_var = {
+    .obj                =   NULL,
+    .fifo_size_tx       =   16,
+    .fifo_size_rx       =   16,
+    .vec                =   uart0_vec,
+#if DEVICE_SERIAL_ASYNCH
+    .vec_async          =   uart0_vec_async,
+    .pdma_perp_tx       =   PDMA_UART0_TX,
+    .pdma_perp_rx       =   PDMA_UART0_RX
+#endif
+};
+static struct nu_uart_var uart1_var = {
+    .obj                =   NULL,
+    .fifo_size_tx       =   16,
+    .fifo_size_rx       =   16,
+    .vec                =   uart1_vec,
+#if DEVICE_SERIAL_ASYNCH
+    .vec_async          =   uart1_vec_async,
+    .pdma_perp_tx       =   PDMA_UART1_TX,
+    .pdma_perp_rx       =   PDMA_UART1_RX
+#endif
+};
+static struct nu_uart_var uart2_var = {
+    .obj                =   NULL,
+    .fifo_size_tx       =   16,
+    .fifo_size_rx       =   16,
+    .vec                =   uart2_vec,
+#if DEVICE_SERIAL_ASYNCH
+    .vec_async          =   uart2_vec_async,
+    .pdma_perp_tx       =   PDMA_UART2_TX,
+    .pdma_perp_rx       =   PDMA_UART2_RX
+#endif
+};
+static struct nu_uart_var uart3_var = {
+    .obj                =   NULL,
+    .fifo_size_tx       =   16,
+    .fifo_size_rx       =   16,
+    .vec                =   uart3_vec,
+#if DEVICE_SERIAL_ASYNCH
+    .vec_async          =   uart3_vec_async,
+    .pdma_perp_tx       =   PDMA_UART3_TX,
+    .pdma_perp_rx       =   PDMA_UART3_RX
+#endif
+};
+
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+static uint32_t uart_modinit_mask = 0;
+
+static const struct nu_modinit_s uart_modinit_tab[] = {
+    {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var},
+    {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var},
+    {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var},
+    {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var},
+    
+    {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+extern void mbed_sdk_init(void);
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+    // NOTE: serial_init() gets called from _sys_open() timing of which is before main()/mbed_hal_init().
+    mbed_sdk_init();
+    
+    // Determine which UART_x the pins are used for
+    uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
+    uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
+    // Get the peripheral name (UART_x) from the pins and assign it to the object
+    obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
+    MBED_ASSERT((int)obj->serial.uart != NC);
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->serial.uart);
+    
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+    
+    // Select IP clock source
+    CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
+    // Enable IP clock
+    CLK_EnableModuleClock(modinit->clkidx);
+
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+    // FIXME: Why PullUp?
+    //if (tx != NC) {
+    //    pin_mode(tx, PullUp);
+    //}
+    //if (rx != NC) {
+    //    pin_mode(rx, PullUp);
+    //}
+    obj->serial.pin_tx = tx;
+    obj->serial.pin_rx = rx;
+    
+    // Configure the UART module and set its baudrate
+    serial_baud(obj, 9600);
+    // Configure data bits, parity, and stop bits
+    serial_format(obj, 8, ParityNone, 1);
+    
+    obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
+    
+#if DEVICE_SERIAL_ASYNCH
+    obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
+    obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
+    obj->serial.event = 0;
+    obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+    obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+#endif
+
+    // For stdio management
+    if (obj == &stdio_uart) {
+        stdio_uart_inited = 1;
+        /* NOTE: Not required anymore because stdio_uart will be manually initialized in mbed-drivers/source/retarget.cpp from mbed beta */
+        //memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+    
+    // Mark this module to be inited.
+    int i = modinit - uart_modinit_tab;
+    uart_modinit_mask |= 1 << i;
+}
+
+void serial_free(serial_t *obj)
+{
+#if DEVICE_SERIAL_ASYNCH
+    if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
+        dma_channel_free(obj->serial.dma_chn_id_tx);
+        obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+    if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
+        dma_channel_free(obj->serial.dma_chn_id_rx);
+        obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+#endif
+
+    UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
+    
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->serial.uart);
+    
+    UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+    NVIC_DisableIRQ(modinit->irq_n);
+    
+    // Disable IP clock
+    CLK_DisableModuleClock(modinit->clkidx);
+    
+    ((struct nu_uart_var *) modinit->var)->obj = NULL;
+    
+    if (obj == &stdio_uart) {
+        stdio_uart_inited = 0;
+    }
+    
+    // Mark this module to be deinited.
+    int i = modinit - uart_modinit_tab;
+    uart_modinit_mask &= ~(1 << i);
+}
+
+void serial_baud(serial_t *obj, int baudrate) {
+    // Flush Tx FIFO. Otherwise, output data may get lost on this change.
+    while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
+    
+    obj->serial.baudrate = baudrate;
+    UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+    // Flush Tx FIFO. Otherwise, output data may get lost on this change.
+    while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
+    
+    // TODO: Assert for not supported parity and data bits
+    obj->serial.databits = data_bits;
+    obj->serial.parity = parity;
+    obj->serial.stopbits = stop_bits;
+    
+    uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
+        (data_bits == 6) ? UART_WORD_LEN_6 :
+        (data_bits == 7) ? UART_WORD_LEN_7 : 
+        UART_WORD_LEN_8;
+    uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
+        (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
+        UART_PARITY_NONE;
+    uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
+    UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart), 
+        0,  // Don't change baudrate 
+        databits_intern, 
+        parity_intern, 
+        stopbits_intern);
+}
+
+#if DEVICE_SERIAL_FC
+
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
+{
+    UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+    
+    // First, disable flow control completely.
+    uart_base->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
+
+    if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) {
+        // Check if RTS pin matches.
+        uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
+        MBED_ASSERT(uart_rts == obj->serial.uart);
+        // Enable the pin for RTS function
+        pinmap_pinout(rxflow, PinMap_UART_RTS);
+        // nRTS pin output is high level active
+        uart_base->MODEM = (uart_base->MODEM & ~UART_MODEM_RTSACTLV_Msk);
+        uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
+        // Enable RTS
+        uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
+    }
+    
+    if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC)  {
+        // Check if CTS pin matches.
+        uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
+        MBED_ASSERT(uart_cts == obj->serial.uart);
+        // Enable the pin for CTS function
+        pinmap_pinout(txflow, PinMap_UART_CTS);
+        // nCTS pin input is high level active
+        uart_base->MODEMSTS = (uart_base->MODEMSTS & ~UART_MODEMSTS_CTSACTLV_Msk);
+        // Enable CTS
+        uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
+    }
+}
+
+#endif  //DEVICE_SERIAL_FC
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+    // Flush Tx FIFO. Otherwise, output data may get lost on this change.
+    while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
+    
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->serial.uart);
+    
+    ((struct nu_uart_var *) modinit->var)->obj = obj;
+    obj->serial.irq_handler = (uint32_t) handler;
+    obj->serial.irq_id = id;
+    
+    // Restore sync-mode vector
+    obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+    if (enable) {
+        const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+        MBED_ASSERT(modinit != NULL);
+        MBED_ASSERT(modinit->modname == obj->serial.uart);
+    
+        NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
+        NVIC_EnableIRQ(modinit->irq_n);
+        
+        switch (irq) {
+            // NOTE: Setting inten_msk first to avoid race condition
+            case RxIrq:
+                obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
+                UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+                break;
+            case TxIrq:
+                obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
+                UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
+                break;
+        }
+    } else { // disable
+        switch (irq) {
+            case RxIrq:
+                UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+                obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
+                break;
+            case TxIrq:
+                UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
+                obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
+                break;
+        }
+    }
+}
+
+int serial_getc(serial_t *obj)
+{
+    // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.    
+    while (! serial_readable(obj));
+    int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+    
+    // Simulate clear of the interrupt flag
+    if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
+        UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+    }
+    
+    return c;
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+    // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
+    while (! serial_writable(obj));
+    UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
+    
+    // Simulate clear of the interrupt flag
+    if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
+        UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
+    }
+}
+
+int serial_readable(serial_t *obj)
+{
+    //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
+    return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
+}
+
+int serial_writable(serial_t *obj)
+{
+    return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
+}
+
+void serial_pinout_tx(PinName tx)
+{
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj)
+{
+    ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
+}
+
+void serial_break_clear(serial_t *obj)
+{
+    ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
+}
+
+static void uart0_vec(void)
+{
+    uart_irq(uart0_var.obj);
+}
+
+static void uart1_vec(void)
+{
+    uart_irq(uart1_var.obj);
+}
+
+static void uart2_vec(void)
+{
+    uart_irq(uart2_var.obj);
+}
+
+static void uart3_vec(void)
+{
+    uart_irq(uart3_var.obj);
+}
+
+static void uart_irq(serial_t *obj)
+{
+    UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+
+    if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
+        // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
+        UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+        if (obj->serial.irq_handler) {
+            ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
+        }
+    }
+    
+    if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
+        // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
+        UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
+        if (obj->serial.irq_handler) {
+            ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
+        }
+    }
+    
+    // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
+    uart_base->INTSTS = uart_base->INTSTS;
+    uart_base->FIFOSTS = uart_base->FIFOSTS;
+}
+
+
+#if DEVICE_SERIAL_ASYNCH
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+    // NOTE: tx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
+    tx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
+    
+    MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
+
+    obj->serial.dma_usage_tx = hint;
+    serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
+    
+    // UART IRQ is necessary for both interrupt way and DMA way
+    serial_tx_enable_event(obj, event, 1);
+    serial_tx_buffer_set(obj, tx, tx_length, tx_width);
+    //UART_HAL_DisableTransmitter(obj->serial.address);
+    //UART_HAL_FlushTxFifo(obj->serial.address);
+    //UART_HAL_EnableTransmitter(obj->serial.address);
+            
+    int n_word = 0;
+    if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
+        // Interrupt way
+        n_word = serial_write_async(obj);
+        serial_tx_enable_interrupt(obj, handler, 1);
+    } else {
+        // DMA way
+        const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+        MBED_ASSERT(modinit != NULL);
+        MBED_ASSERT(modinit->modname == obj->serial.uart);
+    
+        PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_tx;  // Enable this DMA channel
+        PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
+            ((struct nu_uart_var *) modinit->var)->pdma_perp_tx,    // Peripheral connected to this PDMA
+            0,  // Scatter-gather disabled
+            0); // Scatter-gather descriptor address
+        PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx, 
+            (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, 
+            tx_length);
+        PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
+            (uint32_t) tx,  // NOTE:
+                            // NUC472: End of source address
+                            // M451: Start of source address
+            PDMA_SAR_INC,   // Source address incremental
+            (uint32_t) obj->serial.uart,    // Destination address
+            PDMA_DAR_FIX);  // Destination address fixed
+        PDMA_SetBurstType(obj->serial.dma_chn_id_tx, 
+            PDMA_REQ_SINGLE,    // Single mode
+            0); // Burst size
+        PDMA_EnableInt(obj->serial.dma_chn_id_tx,
+            PDMA_INT_TRANS_DONE); // Interrupt type
+        // Register DMA event handler
+        dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
+        serial_tx_enable_interrupt(obj, handler, 1);
+        ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk;  // Start DMA transfer
+    }
+    
+    return n_word;
+}
+
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
+{
+    // NOTE: rx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
+    rx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
+    
+    MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
+
+    obj->serial.dma_usage_rx = hint;
+    serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
+    // DMA doesn't support char match, so fall back to IRQ if it is requested.
+    if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER && 
+        (event & SERIAL_EVENT_RX_CHARACTER_MATCH) && 
+        char_match != SERIAL_RESERVED_CHAR_MATCH) {
+        obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
+        dma_channel_free(obj->serial.dma_chn_id_rx);
+        obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+    
+    // UART IRQ is necessary for both interrupt way and DMA way
+    serial_rx_enable_event(obj, event, 1);
+    serial_rx_buffer_set(obj, rx, rx_length, rx_width);
+    serial_rx_set_char_match(obj, char_match);
+    //UART_HAL_DisableReceiver(obj->serial.address);
+    //UART_HAL_FlushRxFifo(obj->serial.address);
+    //UART_HAL_EnableReceiver(obj->serial.address);
+        
+    if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
+        // Interrupt way
+        serial_rx_enable_interrupt(obj, handler, 1);
+    } else {
+        // DMA way
+        const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+        MBED_ASSERT(modinit != NULL);
+        MBED_ASSERT(modinit->modname == obj->serial.uart);
+    
+        PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_rx;  // Enable this DMA channel
+        PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
+            ((struct nu_uart_var *) modinit->var)->pdma_perp_rx,    // Peripheral connected to this PDMA
+            0,  // Scatter-gather disabled
+            0); // Scatter-gather descriptor address
+        PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx, 
+            (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, 
+            rx_length);
+        PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
+            (uint32_t) obj->serial.uart,    // Source address
+            PDMA_SAR_FIX,   // Source address fixed
+            (uint32_t) rx,  // NOTE: 
+                            // NUC472: End of destination address
+                            // M451: Start of destination address
+            PDMA_DAR_INC);  // Destination address incremental
+        PDMA_SetBurstType(obj->serial.dma_chn_id_rx, 
+            PDMA_REQ_SINGLE,    // Single mode
+            0); // Burst size
+        PDMA_EnableInt(obj->serial.dma_chn_id_rx,
+            PDMA_INT_TRANS_DONE); // Interrupt type
+        // Register DMA event handler
+        dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
+        serial_rx_enable_interrupt(obj, handler, 1);
+        ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk;  // Start DMA transfer
+    }
+}
+
+void serial_tx_abort_asynch(serial_t *obj)
+{
+    // Flush Tx FIFO. Otherwise, output data may get lost on this change.
+    while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
+    
+    if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
+        if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
+            PDMA_DisableInt(obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
+            // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
+            //PDMA_STOP(obj->serial.dma_chn_id_tx);
+            PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
+        }
+        UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
+    }
+    
+    // Necessary for both interrupt way and DMA way
+    serial_irq_set(obj, TxIrq, 0);
+    // FIXME: more complete abort operation
+    //UART_HAL_DisableTransmitter(obj->serial.serial.address);
+    //UART_HAL_FlushTxFifo(obj->serial.serial.address);
+}
+
+void serial_rx_abort_asynch(serial_t *obj)
+{
+    if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
+        if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
+            PDMA_DisableInt(obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
+            // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
+            //PDMA_STOP(obj->serial.dma_chn_id_rx);
+            PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
+        }
+        UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
+    }
+    
+    // Necessary for both interrupt way and DMA way
+    serial_irq_set(obj, RxIrq, 0);
+    // FIXME: more complete abort operation
+    //UART_HAL_DisableReceiver(obj->serial.serial.address);
+    //UART_HAL_FlushRxFifo(obj->serial.serial.address);
+}
+
+uint8_t serial_tx_active(serial_t *obj)
+{
+    return serial_is_irq_en(obj, TxIrq);
+}
+
+uint8_t serial_rx_active(serial_t *obj)
+{
+    return serial_is_irq_en(obj, RxIrq);
+}
+
+int serial_irq_handler_asynch(serial_t *obj)
+{
+    int event_rx = 0;
+    int event_tx = 0;
+    
+    // Necessary for both interrup way and DMA way
+    if (serial_is_irq_en(obj, RxIrq)) {
+        event_rx = serial_rx_event_check(obj);
+        if (event_rx) {
+            serial_rx_abort_asynch(obj);
+        }
+    }
+        
+    if (serial_is_irq_en(obj, TxIrq)) {
+        event_tx = serial_tx_event_check(obj);
+        if (event_tx) {
+            serial_tx_abort_asynch(obj);
+        }
+    }
+        
+    return (obj->serial.event & (event_rx | event_tx));
+}
+
+int serial_allow_powerdown(void)
+{
+    uint32_t modinit_mask = uart_modinit_mask;
+    while (modinit_mask) {
+        int uart_idx = nu_ctz(modinit_mask);
+        const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
+        if (modinit->modname != NC) {
+            UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
+            // Disallow entering power-down mode if Tx FIFO has data to flush
+            if (! UART_IS_TX_EMPTY((uart_base))) {
+                return 0;
+            }
+            // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
+            if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
+                return 0;
+            }
+            // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
+            if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
+                return 0;
+            }
+        }
+        modinit_mask &= ~(1 << uart_idx);
+    }
+    
+    return 1;
+}
+
+static void uart0_vec_async(void)
+{
+    uart_irq_async(uart0_var.obj);
+}
+
+static void uart1_vec_async(void)
+{
+    uart_irq_async(uart1_var.obj);
+}
+
+static void uart2_vec_async(void)
+{
+    uart_irq_async(uart2_var.obj);
+}
+
+static void uart3_vec_async(void)
+{
+    uart_irq_async(uart3_var.obj);
+}
+
+static void uart_irq_async(serial_t *obj)
+{
+    if (serial_is_irq_en(obj, RxIrq)) {
+        (*obj->serial.irq_handler_rx_async)();
+    }
+    if (serial_is_irq_en(obj, TxIrq)) {
+        (*obj->serial.irq_handler_tx_async)();
+    }
+}
+
+static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
+{
+    obj->char_match = char_match;
+    obj->char_found = 0;
+}
+
+static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
+{
+    obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
+    obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
+    
+    //if (event & SERIAL_EVENT_TX_COMPLETE) {
+    //}
+}
+
+static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
+{
+    obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
+    obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
+    
+    //if (event & SERIAL_EVENT_RX_COMPLETE) {
+    //}
+    //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+    //}
+    if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
+        UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
+    }
+    if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
+        UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
+    }
+    if (event & SERIAL_EVENT_RX_OVERFLOW) {
+        UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
+    }
+    //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
+    //}
+}
+
+static int serial_is_tx_complete(serial_t *obj)
+{
+    // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
+    //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
+    // FIXME: Premature abort???
+    return (obj->tx_buff.pos == obj->tx_buff.length);
+}
+
+static int serial_is_rx_complete(serial_t *obj)
+{
+    //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
+    return (obj->rx_buff.pos == obj->rx_buff.length);
+}
+
+static uint32_t serial_tx_event_check(serial_t *obj)
+{
+    UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+    
+    if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
+        // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
+        UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
+    }
+    
+    uint32_t event = 0;
+    
+    if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
+        serial_write_async(obj);
+    }
+    
+    if (serial_is_tx_complete(obj)) {
+        event |= SERIAL_EVENT_TX_COMPLETE;
+    }
+    
+    return event;
+}
+
+static uint32_t serial_rx_event_check(serial_t *obj)
+{
+    UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+    
+    if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
+        // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
+        UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+    }
+    
+    uint32_t event = 0;
+    
+    if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
+        uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
+    }
+    if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
+        uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
+        event |= SERIAL_EVENT_RX_FRAMING_ERROR;
+    }
+    if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
+        uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
+        event |= SERIAL_EVENT_RX_PARITY_ERROR;
+    }
+    
+    if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
+        uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
+        event |= SERIAL_EVENT_RX_OVERFLOW;
+    }
+
+    if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
+        serial_read_async(obj);
+    }
+    
+    if (serial_is_rx_complete(obj)) {
+        event |= SERIAL_EVENT_RX_COMPLETE;
+    }
+    if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
+        event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
+        // FIXME: Timing to reset char_found?
+        //obj->char_found = 0;
+    }
+    
+    return event;
+}
+
+static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
+{
+    serial_t *obj = (serial_t *) id;
+    
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_ABORT) {
+    }
+    // Expect UART IRQ will catch this transfer done event
+    if (event_dma & DMA_EVENT_TRANSFER_DONE) {
+        obj->tx_buff.pos = obj->tx_buff.length;
+    }
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_TIMEOUT) {
+    }
+    
+    uart_irq_async(obj);
+}
+
+static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
+{
+    serial_t *obj = (serial_t *) id;
+    
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_ABORT) {
+    }
+    // Expect UART IRQ will catch this transfer done event
+    if (event_dma & DMA_EVENT_TRANSFER_DONE) {
+        obj->rx_buff.pos = obj->rx_buff.length;
+    }
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_TIMEOUT) {
+    }
+    
+    uart_irq_async(obj);
+}
+
+static int serial_write_async(serial_t *obj)
+{   
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->serial.uart);
+    
+    UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
+    
+    uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
+    uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
+    if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
+        tx_fifo_busy = tx_fifo_max;
+    }
+    uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
+    if (tx_fifo_free == 0) {
+        // Simulate clear of the interrupt flag
+        if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
+            UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
+        }
+        return 0;
+    }
+    
+    uint32_t bytes_per_word = obj->tx_buff.width / 8;
+    
+    uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
+    int n_words = 0;
+    while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
+        switch (bytes_per_word) {
+            case 4:
+                UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
+                UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
+            case 2:
+                UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
+            case 1:
+                UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
+        }
+        
+        n_words ++;
+        tx_fifo_free -= bytes_per_word;
+        obj->tx_buff.pos ++;
+    }
+    
+    if (n_words) {
+        // Simulate clear of the interrupt flag
+        if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
+            UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
+        }
+    }
+    
+    return n_words;
+}
+
+static int serial_read_async(serial_t *obj)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->serial.uart);
+    
+    uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
+    //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
+    //if (rx_fifo_free == 0) {
+    //    return 0;
+    //}
+    
+    uint32_t bytes_per_word = obj->rx_buff.width / 8;
+    
+    uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
+    int n_words = 0;
+    while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
+        switch (bytes_per_word) {
+            case 4:
+                *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+                *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+            case 2:
+                *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+            case 1:
+                *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
+        }
+        
+        n_words ++;
+        rx_fifo_busy -= bytes_per_word;
+        obj->rx_buff.pos ++;
+        
+        if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
+            obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
+            uint8_t *rx_cmp = rx;
+            switch (bytes_per_word) {
+                case 4:
+                    rx_cmp -= 2;
+                case 2:
+                    rx_cmp --;
+                case 1:
+                    rx_cmp --;
+            }
+            if (*rx_cmp == obj->char_match) {
+                obj->char_found = 1;
+                break;
+            }
+        }
+    }
+    
+    if (n_words) {
+        // Simulate clear of the interrupt flag
+        if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
+            UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
+        }
+    }
+    
+    return n_words;
+}
+
+static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
+{
+    obj->tx_buff.buffer = (void *) tx;
+    obj->tx_buff.length = length;
+    obj->tx_buff.pos = 0;
+    obj->tx_buff.width = width;
+}
+
+static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
+{
+    obj->rx_buff.buffer = rx;
+    obj->rx_buff.length = length;
+    obj->rx_buff.pos = 0;
+    obj->rx_buff.width = width;
+}
+
+static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->serial.uart);
+    
+    // Necessary for both interrupt way and DMA way
+    ((struct nu_uart_var *) modinit->var)->obj = obj;
+    // With our own async vector, tx/rx handlers can be different.
+    obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec_async;
+    obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
+    serial_irq_set(obj, TxIrq, enable);
+}
+
+static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->serial.uart);
+    
+    // Necessary for both interrupt way and DMA way
+    ((struct nu_uart_var *) modinit->var)->obj = obj;
+    // With our own async vector, tx/rx handlers can be different.
+    obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec_async;
+    obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
+    serial_irq_set(obj, RxIrq, enable);
+}
+
+static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
+{
+    if (*dma_usage != DMA_USAGE_NEVER) {
+        if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
+            *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
+        }
+        if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
+            *dma_usage = DMA_USAGE_NEVER;
+        }
+    }
+    else {
+        dma_channel_free(*dma_ch);
+        *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+}
+
+static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
+{
+    int inten_msk = 0;
+    
+    switch (irq) {
+        case RxIrq:
+            inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
+            break;
+        case TxIrq:
+            inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
+            break;
+    }
+    
+    return !! inten_msk;
+}
+
+#endif  // #if DEVICE_SERIAL_ASYNCH
+#endif  // #if DEVICE_SERIAL
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/sleep.c b/targets/TARGET_NUVOTON/TARGET_M451/sleep.c
new file mode 100644
index 00000000000..bd6f08fcd44
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/sleep.c
@@ -0,0 +1,118 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "sleep_api.h"
+#include "serial_api.h"
+#include "lp_ticker_api.h"
+
+#if DEVICE_SLEEP
+
+#include "cmsis.h"
+#include "device.h"
+#include "objects.h"
+#include "PeripheralPins.h"
+
+void us_ticker_prepare_sleep(struct sleep_s *obj);
+void us_ticker_wakeup_from_sleep(struct sleep_s *obj);
+static void mbed_enter_sleep(struct sleep_s *obj);
+static void mbed_exit_sleep(struct sleep_s *obj);
+
+int serial_allow_powerdown(void);
+int spi_allow_powerdown(void);
+int i2c_allow_powerdown(void);
+int pwmout_allow_powerdown(void);
+
+/**
+ * Enter Idle mode.
+ */
+void sleep(void)
+{
+    struct sleep_s sleep_obj;
+    sleep_obj.powerdown = 0;
+    mbed_enter_sleep(&sleep_obj);
+    mbed_exit_sleep(&sleep_obj);
+}
+
+/**
+ * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode.
+ */
+void deepsleep(void)
+{
+    struct sleep_s sleep_obj;
+    sleep_obj.powerdown = 1;
+    mbed_enter_sleep(&sleep_obj);
+    mbed_exit_sleep(&sleep_obj);
+}
+
+
+void mbed_enter_sleep(struct sleep_s *obj)
+{
+    // Check if serial allows entering power-down mode
+    if (obj->powerdown) {
+        obj->powerdown = serial_allow_powerdown();
+    }
+    // Check if spi allows entering power-down mode
+    if (obj->powerdown) {
+        obj->powerdown = spi_allow_powerdown();
+    }
+    // Check if i2c allows entering power-down mode
+    if (obj->powerdown) {
+        obj->powerdown = i2c_allow_powerdown();
+    }
+    // Check if pwmout allows entering power-down mode
+    if (obj->powerdown) {
+        obj->powerdown = pwmout_allow_powerdown();
+    }
+    // TODO: Check if other peripherals allow entering power-down mode
+    
+    obj->start_us = lp_ticker_read();
+    // Let us_ticker prepare for power-down or reject it.
+    us_ticker_prepare_sleep(obj);
+    
+    // NOTE(STALE): To pass mbed-drivers test, timer requires to be fine-grained, so its implementation needs HIRC rather than LIRC/LXT as its clock source.
+    //       But as CLK_PowerDown()/CLK_Idle() is called, HIRC will be disabled and timer cannot keep counting and alarm. To overcome the dilemma, 
+    //       just make CPU halt and compromise power saving.
+    // NOTE: As CLK_PowerDown()/CLK_Idle() is called, HIRC/HXT will be disabled in normal mode, but not in ICE mode. This may cause confusion in development.
+
+    if (obj->powerdown) {   // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled)
+        SYS_UnlockReg();
+        CLK_PowerDown();
+        SYS_LockReg();
+    }
+    else {  // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
+        SYS_UnlockReg();
+        CLK_Idle();
+        SYS_LockReg();
+    }
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+    
+    obj->end_us = lp_ticker_read();
+    obj->period_us = (obj->end_us > obj->start_us) ? (obj->end_us - obj->start_us) : (uint32_t) ((uint64_t) obj->end_us + 0xFFFFFFFFu - obj->start_us);
+    // Let us_ticker recover from power-down.
+    us_ticker_wakeup_from_sleep(obj);
+}
+
+void mbed_exit_sleep(struct sleep_s *obj)
+{
+    // TODO: TO BE CONTINUED
+    
+    (void)obj;
+}
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c
new file mode 100644
index 00000000000..fb2c28d39c8
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c
@@ -0,0 +1,775 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "nu_bitutil.h"
+
+#if DEVICE_SPI_ASYNCH
+#include "dma_api.h"
+#include "dma.h"
+#endif
+
+#define NU_SPI_FRAME_MIN    8
+#define NU_SPI_FRAME_MAX    32
+#define NU_SPI_FIFO_DEPTH   8
+
+struct nu_spi_var {
+#if DEVICE_SPI_ASYNCH
+    uint8_t     pdma_perp_tx;
+    uint8_t     pdma_perp_rx;
+#endif
+};
+
+static struct nu_spi_var spi0_var = {
+#if DEVICE_SPI_ASYNCH
+    .pdma_perp_tx       =   PDMA_SPI0_TX,
+    .pdma_perp_rx       =   PDMA_SPI0_RX
+#endif
+};
+static struct nu_spi_var spi1_var = {
+#if DEVICE_SPI_ASYNCH
+    .pdma_perp_tx       =   PDMA_SPI1_TX,
+    .pdma_perp_rx       =   PDMA_SPI1_RX
+#endif
+};
+static struct nu_spi_var spi2_var = {
+#if DEVICE_SPI_ASYNCH
+    .pdma_perp_tx       =   PDMA_SPI2_TX,
+    .pdma_perp_rx       =   PDMA_SPI2_RX
+#endif
+};
+
+#if DEVICE_SPI_ASYNCH
+static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable);
+static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable);
+static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit);
+static uint32_t spi_master_read_asynch(spi_t *obj);
+static uint32_t spi_event_check(spi_t *obj);
+static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable);
+static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
+static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx);
+static uint8_t spi_get_data_width(spi_t *obj);
+static int spi_is_tx_complete(spi_t *obj);
+static int spi_is_rx_complete(spi_t *obj);
+static int spi_writeable(spi_t * obj);
+static int spi_readable(spi_t * obj);
+static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma);
+static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma);
+#endif
+
+static uint32_t spi_modinit_mask = 0;
+
+static const struct nu_modinit_s spi_modinit_tab[] = {
+    {SPI_0, SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK0, MODULE_NoMsk, SPI0_RST, SPI0_IRQn, &spi0_var},
+    {SPI_1, SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PCLK1, MODULE_NoMsk, SPI1_RST, SPI1_IRQn, &spi1_var},
+    {SPI_2, SPI2_MODULE, CLK_CLKSEL2_SPI2SEL_PCLK0, MODULE_NoMsk, SPI2_RST, SPI2_IRQn, &spi2_var},
+    
+    {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    // Determine which SPI_x the pins are used for
+    uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
+    uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
+    uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
+    obj->spi.spi = (SPIName) pinmap_merge(spi_data, spi_cntl);
+    MBED_ASSERT((int)obj->spi.spi != NC);
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->spi.spi);
+    
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+    
+    // Select IP clock source
+    CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
+    // Enable IP clock
+    CLK_EnableModuleClock(modinit->clkidx);
+
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+        
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    
+    obj->spi.pin_mosi = mosi;
+    obj->spi.pin_miso = miso;
+    obj->spi.pin_sclk = sclk;
+    obj->spi.pin_ssel = ssel;
+
+    
+    // Configure the SPI data format and frequency
+    //spi_format(obj, 8, 0, SPI_MSB); // 8 bits, mode 0
+    //spi_frequency(obj, 1000000);
+    
+#if DEVICE_SPI_ASYNCH
+    obj->spi.dma_usage = DMA_USAGE_NEVER;
+    obj->spi.event = 0;
+    obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+    obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+#endif
+
+    // Mark this module to be inited.
+    int i = modinit - spi_modinit_tab;
+    spi_modinit_mask |= 1 << i;
+}
+
+void spi_free(spi_t *obj)
+{
+#if DEVICE_SPI_ASYNCH
+    if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
+        dma_channel_free(obj->spi.dma_chn_id_tx);
+        obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+    if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
+        dma_channel_free(obj->spi.dma_chn_id_rx);
+        obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+#endif
+
+    SPI_Close((SPI_T *) NU_MODBASE(obj->spi.spi));
+    
+    const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->spi.spi);
+    
+    SPI_DisableInt(((SPI_T *) NU_MODBASE(obj->spi.spi)), (SPI_FIFO_RXOV_INT_MASK | SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK));
+    NVIC_DisableIRQ(modinit->irq_n);
+    
+    // Disable IP clock
+    CLK_DisableModuleClock(modinit->clkidx);
+    
+    //((struct nu_spi_var *) modinit->var)->obj = NULL;
+    
+    // Mark this module to be deinited.
+    int i = modinit - spi_modinit_tab;
+    spi_modinit_mask &= ~(1 << i);
+}
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+    MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
+    
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    
+    // NOTE 1: All configurations should be ready before enabling SPI peripheral.
+    // NOTE 2: Re-configuration is allowed only as SPI peripheral is idle.
+    while (SPI_IS_BUSY(spi_base));
+    SPI_DISABLE(spi_base);
+
+    SPI_Open(spi_base,
+        slave ? SPI_SLAVE : SPI_MASTER,
+        (mode == 0) ? SPI_MODE_0 : (mode == 1) ? SPI_MODE_1 : (mode == 2) ? SPI_MODE_2 : SPI_MODE_3,
+        bits,
+        SPI_GetBusClock(spi_base));
+    // NOTE: Hardcode to be MSB first.
+    SPI_SET_MSB_FIRST(spi_base);
+
+    if (! slave) {
+        // Master
+        if (obj->spi.pin_ssel != NC) {
+            // Configure SS as low active.            
+            SPI_EnableAutoSS(spi_base, SPI_SS, SPI_SS_ACTIVE_LOW);
+        }
+        else {
+            SPI_DisableAutoSS(spi_base);
+        }
+    }
+    else {
+        // Slave
+        // Configure SS as low active.
+        spi_base->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
+    }
+
+    // NOTE: M451's SPI_Open() will enable SPI transfer (SPI_CTL_SPIEN_Msk). This will violate judgement of spi_active(). Disable it.
+    SPI_DISABLE(spi_base);
+}
+
+void spi_frequency(spi_t *obj, int hz)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    
+    while (SPI_IS_BUSY(spi_base));
+    SPI_DISABLE(spi_base);
+
+    SPI_SetBusClock((SPI_T *) NU_MODBASE(obj->spi.spi), hz);
+}
+
+
+int spi_master_write(spi_t *obj, int value)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    
+    // NOTE: Data in receive FIFO can be read out via ICE.
+    SPI_ENABLE(spi_base);
+    
+    // Wait for tx buffer empty
+    while(! spi_writeable(obj));
+    SPI_WRITE_TX(spi_base, value);
+
+    // Wait for rx buffer full
+    while (! spi_readable(obj));
+    int value2 = SPI_READ_RX(spi_base);
+    
+    SPI_DISABLE(spi_base);
+    
+    return value2;
+}
+
+#if DEVICE_SPISLAVE
+int spi_slave_receive(spi_t *obj)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    
+    SPI_ENABLE(spi_base);
+    
+    return spi_readable(obj);
+};
+
+int spi_slave_read(spi_t *obj)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    
+    SPI_ENABLE(spi_base);
+    
+    // Wait for rx buffer full
+    while (! spi_readable(obj));
+    int value = SPI_READ_RX(spi_base);
+    return value;
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    
+    SPI_ENABLE(spi_base);
+    
+    // Wait for tx buffer empty
+    while(! spi_writeable(obj));
+    SPI_WRITE_TX(spi_base, value);
+}
+#endif
+
+#if DEVICE_SPI_ASYNCH
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+    //MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    SPI_SET_DATA_WIDTH(spi_base, bit_width);
+
+    obj->spi.dma_usage = hint;
+    spi_check_dma_usage(&obj->spi.dma_usage, &obj->spi.dma_chn_id_tx, &obj->spi.dma_chn_id_rx);
+    uint32_t data_width = spi_get_data_width(obj);
+    // Conditions to go DMA way:
+    // (1) No DMA support for non-8 multiple data width.
+    // (2) tx length >= rx length. Otherwise, as tx DMA is done, no bus activity for remaining rx.
+    if ((data_width % 8) ||
+        (tx_length < rx_length)) {
+        obj->spi.dma_usage = DMA_USAGE_NEVER;
+        dma_channel_free(obj->spi.dma_chn_id_tx);
+        obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
+        dma_channel_free(obj->spi.dma_chn_id_rx);
+        obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+    
+    // SPI IRQ is necessary for both interrupt way and DMA way
+    spi_enable_event(obj, event, 1);
+    spi_buffer_set(obj, tx, tx_length, rx, rx_length);
+            
+    SPI_ENABLE(spi_base);
+    
+    if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
+        // Interrupt way
+        spi_master_write_asynch(obj, NU_SPI_FIFO_DEPTH / 2);
+        spi_enable_vector_interrupt(obj, handler, 1);
+        spi_master_enable_interrupt(obj, 1);
+    } else {
+        // DMA way
+        const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+        MBED_ASSERT(modinit != NULL);
+        MBED_ASSERT(modinit->modname == obj->spi.spi);
+    
+        // Configure tx DMA
+        PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_tx;  // Enable this DMA channel
+        PDMA_SetTransferMode(obj->spi.dma_chn_id_tx,
+            ((struct nu_spi_var *) modinit->var)->pdma_perp_tx,    // Peripheral connected to this PDMA
+            0,  // Scatter-gather disabled
+            0); // Scatter-gather descriptor address
+        PDMA_SetTransferCnt(obj->spi.dma_chn_id_tx, 
+            (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, 
+            tx_length);
+        PDMA_SetTransferAddr(obj->spi.dma_chn_id_tx,
+            (uint32_t) tx,  // NOTE:
+                            // NUC472: End of source address
+                            // M451: Start of source address
+            PDMA_SAR_INC,   // Source address incremental
+            (uint32_t) &spi_base->TX,   // Destination address
+            PDMA_DAR_FIX);  // Destination address fixed
+        PDMA_SetBurstType(obj->spi.dma_chn_id_tx, 
+            PDMA_REQ_SINGLE,    // Single mode
+            0); // Burst size
+        PDMA_EnableInt(obj->spi.dma_chn_id_tx,
+            PDMA_INT_TRANS_DONE);   // Interrupt type
+        // Register DMA event handler
+        dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
+        
+        // Configure rx DMA
+        PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_rx;  // Enable this DMA channel
+        PDMA_SetTransferMode(obj->spi.dma_chn_id_rx,
+            ((struct nu_spi_var *) modinit->var)->pdma_perp_rx,    // Peripheral connected to this PDMA
+            0,  // Scatter-gather disabled
+            0); // Scatter-gather descriptor address
+        PDMA_SetTransferCnt(obj->spi.dma_chn_id_rx, 
+            (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, 
+            rx_length);
+        PDMA_SetTransferAddr(obj->spi.dma_chn_id_rx,
+            (uint32_t) &spi_base->RX,   // Source address
+            PDMA_SAR_FIX,   // Source address fixed
+            (uint32_t) rx,  // NOTE: 
+                            // NUC472: End of destination address
+                            // M451: Start of destination address
+            PDMA_DAR_INC);  // Destination address incremental
+        PDMA_SetBurstType(obj->spi.dma_chn_id_rx, 
+            PDMA_REQ_SINGLE,    // Single mode
+            0); // Burst size
+        PDMA_EnableInt(obj->spi.dma_chn_id_rx,
+            PDMA_INT_TRANS_DONE);   // Interrupt type
+        // Register DMA event handler
+        dma_set_handler(obj->spi.dma_chn_id_rx, (uint32_t) spi_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
+        
+        // Start tx/rx DMA transfer
+        spi_enable_vector_interrupt(obj, handler, 1);
+        // NOTE: It is safer to start rx DMA first and then tx DMA. Otherwise, receive FIFO is subject to overflow by tx DMA.
+        SPI_TRIGGER_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+        SPI_TRIGGER_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+        spi_master_enable_interrupt(obj, 1);
+    }
+}
+
+/**
+ * Abort an SPI transfer
+ * This is a helper function for event handling. When any of the events listed occurs, the HAL will abort any ongoing
+ * transfers
+ * @param[in] obj The SPI peripheral to stop
+ */
+void spi_abort_asynch(spi_t *obj)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    
+    if (obj->spi.dma_usage != DMA_USAGE_NEVER) {
+        // Receive FIFO Overrun in case of tx length > rx length on DMA way
+        if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
+            spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
+        }
+        
+        if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
+            PDMA_DisableInt(obj->spi.dma_chn_id_tx, 0);
+            // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
+            //PDMA_STOP(obj->spi.dma_chn_id_tx);
+            PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx);
+        }
+        SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+        
+        if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
+            PDMA_DisableInt(obj->spi.dma_chn_id_rx, 0);
+            // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
+            //PDMA_STOP(obj->spi.dma_chn_id_rx);
+            PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx);
+        }
+        SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+    }
+    
+    // Necessary for both interrupt way and DMA way
+    spi_enable_vector_interrupt(obj, 0, 0);
+    spi_master_enable_interrupt(obj, 0);
+
+    // FIXME: SPI H/W may get out of state without the busy check.
+    while (SPI_IS_BUSY(spi_base));
+    SPI_DISABLE(spi_base);
+    
+    SPI_ClearRxFIFO(spi_base);
+    SPI_ClearTxFIFO(spi_base);
+}
+
+/**
+ * Handle the SPI interrupt
+ * Read frames until the RX FIFO is empty.  Write at most as many frames as were read.  This way,
+ * it is unlikely that the RX FIFO will overflow.
+ * @param[in] obj The SPI peripheral that generated the interrupt
+ * @return
+ */
+uint32_t spi_irq_handler_asynch(spi_t *obj)
+{
+    // Check for SPI events
+    uint32_t event = spi_event_check(obj);
+    if (event) {
+        spi_abort_asynch(obj);
+    }
+
+    return (obj->spi.event & event) | ((event & SPI_EVENT_COMPLETE) ? SPI_EVENT_INTERNAL_TRANSFER_COMPLETE : 0);
+}
+
+uint8_t spi_active(spi_t *obj)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    // FIXME
+    /*
+    if ((obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length)
+            || (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) ){
+        return 1;
+    } else  {
+        // interrupts are disabled, all transaction have been completed
+        // TODO: checking rx fifo, it reports data eventhough RFDF is not set
+        return DSPI_HAL_GetIntMode(obj->spi.address, kDspiRxFifoDrainRequest);
+    }*/
+    
+    //return SPI_IS_BUSY(spi_base);
+    return (spi_base->CTL & SPI_CTL_SPIEN_Msk);
+}
+
+int spi_allow_powerdown(void)
+{
+    uint32_t modinit_mask = spi_modinit_mask;
+    while (modinit_mask) {
+        int spi_idx = nu_ctz(modinit_mask);
+        const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx;
+        if (modinit->modname != NC) {
+            SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname);
+            // Disallow entering power-down mode if SPI transfer is enabled.
+            if (spi_base->CTL & SPI_CTL_SPIEN_Msk) {
+                return 0;
+            }
+        }
+        modinit_mask &= ~(1 << spi_idx);
+    }
+    
+    return 1;
+}
+
+static int spi_writeable(spi_t * obj)
+{
+    // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
+    //return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)))) && (SPI_GET_RX_FIFO_COUNT(((SPI_T *) NU_MODBASE(obj->spi.spi))) < NU_SPI_FIFO_DEPTH);
+    return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
+}
+
+static int spi_readable(spi_t * obj)
+{
+    return ! SPI_GET_RX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)));
+}
+
+static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable)
+{   
+    obj->spi.event &= ~SPI_EVENT_ALL;
+    obj->spi.event |= (event & SPI_EVENT_ALL);
+    if (event & SPI_EVENT_RX_OVERFLOW) {
+        SPI_EnableInt((SPI_T *) NU_MODBASE(obj->spi.spi), SPI_FIFO_RXOV_INT_MASK);
+    }
+}
+
+static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->spi.spi);
+    
+    if (enable) {
+        NVIC_SetVector(modinit->irq_n, handler);
+        NVIC_EnableIRQ(modinit->irq_n);
+    }
+    else {
+        //NVIC_SetVector(modinit->irq_n, handler);
+        NVIC_DisableIRQ(modinit->irq_n);
+    }
+}
+
+static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable)
+{   
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    
+    if (enable) {
+        // For SPI0, it could be 0 ~ 7. For SPI1 and SPI2, it could be 0 ~ 3.
+        if (spi_base == (SPI_T *) SPI0_BASE) {
+            SPI_SetFIFO(spi_base, 4, 4);
+        }
+        else {
+            SPI_SetFIFO(spi_base, 2, 2);
+        }
+        //SPI_SET_SUSPEND_CYCLE(spi_base, 4);
+        // Enable tx/rx FIFO threshold interrupt
+        SPI_EnableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
+    }
+    else {
+        SPI_DisableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
+    }
+}
+
+static uint32_t spi_event_check(spi_t *obj)
+{
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    uint32_t event = 0;
+    
+    if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
+        uint32_t n_rec = spi_master_read_asynch(obj);
+        spi_master_write_asynch(obj, n_rec);
+    }
+    
+    if (spi_is_tx_complete(obj) && spi_is_rx_complete(obj)) {
+        event |= SPI_EVENT_COMPLETE;
+    }
+    
+    // Receive FIFO Overrun
+    if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
+        spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
+        // In case of tx length > rx length on DMA way
+        if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
+            event |= SPI_EVENT_RX_OVERFLOW;
+        }
+    }
+    
+    // Receive Time-Out
+    if (spi_base->STATUS & SPI_STATUS_RXTOIF_Msk) {
+        spi_base->STATUS = SPI_STATUS_RXTOIF_Msk;
+        //event |= SPI_EVENT_ERROR;
+    }
+    // Transmit FIFO Under-Run
+    if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) {
+        spi_base->STATUS = SPI_STATUS_TXUFIF_Msk;
+        event |= SPI_EVENT_ERROR;
+    }
+    
+    return event;
+}
+
+/**
+ * Send words from the SPI TX buffer until the send limit is reached or the TX FIFO is full
+ * tx_limit is provided to ensure that the number of SPI frames (words) in flight can be managed.
+ * @param[in] obj       The SPI object on which to operate
+ * @param[in] tx_limit  The maximum number of words to send
+ * @return The number of SPI words that have been transfered
+ */
+static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
+{
+    uint32_t n_words = 0;
+    uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
+    uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
+    uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn);
+    max_tx = NU_MIN(max_tx, tx_limit);
+    uint8_t data_width = spi_get_data_width(obj);
+    uint8_t bytes_per_word = (data_width + 7) / 8;
+    uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    
+    while ((n_words < max_tx) && spi_writeable(obj)) {
+        if (spi_is_tx_complete(obj)) {
+            // Transmit dummy as transmit buffer is empty
+            SPI_WRITE_TX(spi_base, 0);
+        }
+        else {
+            switch (bytes_per_word) {
+                case 4:
+                    SPI_WRITE_TX(spi_base, nu_get32_le(tx));
+                    tx += 4;
+                    break;
+                case 2:
+                    SPI_WRITE_TX(spi_base, nu_get16_le(tx));
+                    tx += 2;
+                    break;
+                case 1:
+                    SPI_WRITE_TX(spi_base, *((uint8_t *) tx));
+                    tx += 1;
+                    break;
+            }
+        
+            obj->tx_buff.pos ++;
+        }
+        n_words ++;
+    }
+    
+    //Return the number of words that have been sent
+    return n_words;
+}
+
+/**
+ * Read SPI words out of the RX FIFO
+ * Continues reading words out of the RX FIFO until the following condition is met:
+ * o There are no more words in the FIFO
+ * OR BOTH OF:
+ * o At least as many words as the TX buffer have been received
+ * o At least as many words as the RX buffer have been received
+ * This way, RX overflows are not generated when the TX buffer size exceeds the RX buffer size
+ * @param[in] obj The SPI object on which to operate
+ * @return Returns the number of words extracted from the RX FIFO
+ */
+static uint32_t spi_master_read_asynch(spi_t *obj)
+{
+    uint32_t n_words = 0;
+    uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
+    uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
+    uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn);
+    uint8_t data_width = spi_get_data_width(obj);
+    uint8_t bytes_per_word = (data_width + 7) / 8;
+    uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    
+    while ((n_words < max_rx) && spi_readable(obj)) {
+        if (spi_is_rx_complete(obj)) {
+            // Disregard as receive buffer is full
+            SPI_READ_RX(spi_base);
+        }
+        else {
+            switch (bytes_per_word) {
+                case 4: {
+                    uint32_t val = SPI_READ_RX(spi_base);
+                    nu_set32_le(rx, val);
+                    rx += 4;
+                    break;
+                }
+                case 2: {
+                    uint16_t val = SPI_READ_RX(spi_base);
+                    nu_set16_le(rx, val);
+                    rx += 2;
+                    break;
+                }
+                case 1:
+                    *rx ++ = SPI_READ_RX(spi_base);
+                    break;
+            }
+        
+            obj->rx_buff.pos ++;
+        }
+        n_words ++;
+    }
+    
+    // Return the number of words received
+    return n_words;
+}
+
+static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
+{
+    obj->tx_buff.buffer = (void *) tx;
+    obj->tx_buff.length = tx_length;
+    obj->tx_buff.pos = 0;
+    obj->tx_buff.width = spi_get_data_width(obj);
+    obj->rx_buff.buffer = rx;
+    obj->rx_buff.length = rx_length;
+    obj->rx_buff.pos = 0;
+    obj->rx_buff.width = spi_get_data_width(obj);
+}
+
+static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx)
+{
+    if (*dma_usage != DMA_USAGE_NEVER) {
+        if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS) {
+            *dma_ch_tx = dma_channel_allocate(DMA_CAP_NONE);
+        }
+        if (*dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
+            *dma_ch_rx = dma_channel_allocate(DMA_CAP_NONE);
+        }
+        
+        if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS || *dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
+            *dma_usage = DMA_USAGE_NEVER;
+        }
+    }
+    
+    if (*dma_usage == DMA_USAGE_NEVER) {
+        dma_channel_free(*dma_ch_tx);
+        *dma_ch_tx = DMA_ERROR_OUT_OF_CHANNELS;
+        dma_channel_free(*dma_ch_rx);
+        *dma_ch_rx = DMA_ERROR_OUT_OF_CHANNELS;
+    }
+}
+
+static uint8_t spi_get_data_width(spi_t *obj)
+{    
+    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    
+    return ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos);
+}
+
+static int spi_is_tx_complete(spi_t *obj)
+{
+    // ???: Exclude tx fifo empty check due to no such interrupt on DMA way
+    return (obj->tx_buff.pos == obj->tx_buff.length);
+    //return (obj->tx_buff.pos == obj->tx_buff.length && SPI_GET_TX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
+}
+
+static int spi_is_rx_complete(spi_t *obj)
+{
+    return (obj->rx_buff.pos == obj->rx_buff.length);
+}
+
+static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma)
+{
+    spi_t *obj = (spi_t *) id;
+    
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_ABORT) {
+    }
+    // Expect SPI IRQ will catch this transfer done event
+    if (event_dma & DMA_EVENT_TRANSFER_DONE) {
+        obj->tx_buff.pos = obj->tx_buff.length;
+    }
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_TIMEOUT) {
+    }
+    
+    const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->spi.spi);
+    
+    void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
+    vec();
+}
+
+static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma)
+{
+    spi_t *obj = (spi_t *) id;
+    
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_ABORT) {
+    }
+    // Expect SPI IRQ will catch this transfer done event
+    if (event_dma & DMA_EVENT_TRANSFER_DONE) {
+        obj->rx_buff.pos = obj->rx_buff.length;
+    }
+    // FIXME: Pass this error to caller
+    if (event_dma & DMA_EVENT_TIMEOUT) {
+    }
+    
+    const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->spi.spi);
+    
+    void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
+    vec();
+}
+
+#endif
+
+#endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c
new file mode 100644
index 00000000000..ab78dcca000
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c
@@ -0,0 +1,268 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "us_ticker_api.h"
+#include "sleep_api.h"
+#include "mbed_assert.h"
+#include "nu_modutil.h"
+#include "nu_miscutil.h"
+#include "critical.h"
+
+#define US_PER_TICK             1
+
+// NOTE: mbed-drivers-test-timeout test requires 100 us timer granularity.
+// NOTE: us_ticker will alarm the system for its counting, so make the counting period as long as possible for better power saving.
+#define US_PER_TMR0HIRES_INT    (1000 * 1000 * 10)
+#define TMR0HIRES_FIRE_FREQ     (1000 * 1000 / US_PER_TMR0HIRES_INT)
+#define US_PER_TMR0HIRES_CLK    1
+#define TMR0HIRES_CLK_FREQ      (1000 * 1000 / US_PER_TMR0HIRES_CLK)
+
+#define US_PER_TMR1LORES_CLK    100
+#define TMR1LORES_CLK_FREQ      (1000 * 1000 / US_PER_TMR1LORES_CLK)
+#define US_PER_TMR1HIRES_CLK    1
+#define TMR1HIRES_CLK_FREQ      (1000 * 1000 / US_PER_TMR1HIRES_CLK)
+
+// Determine to use lo-res/hi-res timer according to CD period
+#define CD_TMR_SEP_US       1000
+
+static void tmr0_vec(void);
+static void tmr1_vec(void);
+static void us_ticker_arm_cd(void);
+
+static int us_ticker_inited = 0;
+static volatile uint32_t counter_major = 0;
+static volatile uint32_t pd_comp_us = 0;    // Power-down compenstaion for normal counter
+static volatile int cd_major_minor_us = 0;
+static volatile int cd_minor_us = 0;
+static volatile int cd_hires_tmr_armed = 0; // Flag of armed or not of hi-res timer for CD counter
+
+// NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details.
+// NOTE: Choose clock source of timer:
+//       1. HIRC: Be the most accurate but might cause unknown HardFault.
+//       2. HXT: Less accurate and cannot pass mbed-drivers test.
+//       3. PCLK(HXT): Less accurate but can pass mbed-drivers test.
+// NOTE: TIMER_0 for normal counter, TIMER_1 for countdown.
+static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
+static const struct nu_modinit_s timer1lores_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+
+#define TMR_CMP_MIN         2
+#define TMR_CMP_MAX         0xFFFFFFu
+
+void us_ticker_init(void)
+{
+    if (us_ticker_inited) {
+        return;
+    }
+    
+    counter_major = 0;
+    pd_comp_us = 0;
+    cd_major_minor_us = 0;
+    cd_minor_us = 0;
+    cd_hires_tmr_armed = 0;
+    us_ticker_inited = 1;
+    
+    // Reset IP
+    SYS_ResetModule(timer0hires_modinit.rsetidx);
+    SYS_ResetModule(timer1lores_modinit.rsetidx);
+    
+    // Select IP clock source
+    CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv);
+    CLK_SetModuleClock(timer1lores_modinit.clkidx, timer1lores_modinit.clksrc, timer1lores_modinit.clkdiv);
+    // Enable IP clock
+    CLK_EnableModuleClock(timer0hires_modinit.clkidx);
+    CLK_EnableModuleClock(timer1lores_modinit.clkidx);
+
+    // Timer for normal counter
+    uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+    uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_FREQ - 1;
+    MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
+    uint32_t cmp_timer0 = US_PER_TMR0HIRES_INT / US_PER_TMR0HIRES_CLK;
+    MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
+    // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
+    ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0/* | TIMER_CTL_CNTDATEN_Msk*/;
+    ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0;
+    
+    NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var);
+    NVIC_SetVector(timer1lores_modinit.irq_n, (uint32_t) timer1lores_modinit.var);
+    
+    NVIC_EnableIRQ(timer0hires_modinit.irq_n);
+    NVIC_EnableIRQ(timer1lores_modinit.irq_n);
+    
+    TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+    TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+}
+
+uint32_t us_ticker_read()
+{
+    if (! us_ticker_inited) {
+        us_ticker_init();
+    }
+    
+    TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname);
+        
+    do {
+        uint32_t major_minor_us;
+        uint32_t minor_us; 
+
+        // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
+        // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
+        do {
+            core_util_critical_section_enter();
+            
+            // NOTE: Order of reading minor_us/carry here is significant.
+            minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK;
+            uint32_t carry = (timer0_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
+            // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
+            if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
+                major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
+            }
+            else {
+                major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
+            }
+            
+            core_util_critical_section_exit();
+        }
+        while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
+        
+        // Add power-down compensation
+        return (major_minor_us + pd_comp_us) / US_PER_TICK;
+    }
+    while (0);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+    TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
+}
+
+void us_ticker_clear_interrupt(void)
+{
+    TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+    TIMER_Stop((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
+    
+    int delta = (int) (timestamp - us_ticker_read());
+    // NOTE: If this event was in the past, arm an interrupt to be triggered immediately.
+    cd_major_minor_us = delta * US_PER_TICK;
+    
+    us_ticker_arm_cd();
+}
+
+void us_ticker_prepare_sleep(struct sleep_s *obj)
+{
+    // Reject power-down if hi-res timer (HIRC/HXT) is now armed for CD counter.
+    if (obj->powerdown) {
+        obj->powerdown = ! cd_hires_tmr_armed;
+    }
+    
+    core_util_critical_section_enter();
+    
+    if (obj->powerdown) {
+        // NOTE: On entering power-down mode, HIRC/HXT will be disabled in normal mode, but not in ICE mode. This may cause confusion in development.
+        // To not be inconsistent due to above, always disable clock source of normal counter, and then re-enable it and make compensation on wakeup from power-down.
+        CLK_DisableModuleClock(timer0hires_modinit.clkidx);
+    }
+    
+    core_util_critical_section_exit();
+}
+
+void us_ticker_wakeup_from_sleep(struct sleep_s *obj)
+{
+    core_util_critical_section_enter();
+    
+    if (obj->powerdown) {
+        // Calculate power-down compensation
+        pd_comp_us += obj->period_us;
+        
+        CLK_EnableModuleClock(timer0hires_modinit.clkidx);
+    }
+    
+    core_util_critical_section_exit();
+}
+
+static void tmr0_vec(void)
+{
+    TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+    counter_major ++;
+}
+
+static void tmr1_vec(void)
+{
+    TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
+    cd_major_minor_us -= cd_minor_us;
+    cd_hires_tmr_armed = 0;
+    if (cd_major_minor_us <= 0) {
+        // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
+        us_ticker_irq_handler();
+    }
+    else {
+        us_ticker_arm_cd();
+    }
+}
+
+static void us_ticker_arm_cd(void)
+{
+    TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1lores_modinit.modname);
+    uint32_t tmr1_clk_freq;
+    uint32_t us_per_tmr1_clk;
+    
+    /**
+     * Reserve CD_TMR_SEP_US-plus alarm period for hi-res timer
+     * 1. period >= CD_TMR_SEP_US * 2. Divide into two rounds:
+     *    CD_TMR_SEP_US * n (lo-res timer)
+     *    CD_TMR_SEP_US + period % CD_TMR_SEP_US (hi-res timer)
+     * 2. period < CD_TMR_SEP_US * 2. Just one round:
+     *    period (hi-res timer)
+     */
+    if (cd_major_minor_us >= CD_TMR_SEP_US * 2) {
+        cd_minor_us = cd_major_minor_us - cd_major_minor_us % CD_TMR_SEP_US - CD_TMR_SEP_US;
+        
+        CLK_SetModuleClock(timer1lores_modinit.clkidx, timer1lores_modinit.clksrc, timer1lores_modinit.clkdiv);
+        tmr1_clk_freq = TMR1LORES_CLK_FREQ;
+        us_per_tmr1_clk = US_PER_TMR1LORES_CLK;
+        
+        cd_hires_tmr_armed = 0;
+    }
+    else {
+        cd_minor_us = cd_major_minor_us;
+        
+        CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
+        tmr1_clk_freq = TMR1HIRES_CLK_FREQ;
+        us_per_tmr1_clk = US_PER_TMR1HIRES_CLK;
+        
+        cd_hires_tmr_armed = 1;
+    }
+    
+    // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
+    timer1_base->CTL |= TIMER_CTL_RSTCNT_Msk;
+    // One-shot mode, Clock = 1 MHz 
+    uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
+    uint32_t prescale_timer1 = clk_timer1 / tmr1_clk_freq - 1;
+    MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
+    // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
+    timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
+    timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1/* | TIMER_CTL_CNTDATEN_Msk*/;
+    
+    cd_minor_us = NU_CLAMP(cd_minor_us, TMR_CMP_MIN * us_per_tmr1_clk, TMR_CMP_MAX * us_per_tmr1_clk);
+    timer1_base->CMP = cd_minor_us / us_per_tmr1_clk;
+    
+    TIMER_EnableInt(timer1_base);
+    TIMER_Start(timer1_base);
+}
diff --git a/targets/TARGET_NUVOTON/mbed_rtx.h b/targets/TARGET_NUVOTON/mbed_rtx.h
index 5cbc71ae0d9..e948d3117cf 100644
--- a/targets/TARGET_NUVOTON/mbed_rtx.h
+++ b/targets/TARGET_NUVOTON/mbed_rtx.h
@@ -53,6 +53,42 @@
     #error "no toolchain defined"
 #endif
 
+#elif defined(TARGET_NUMAKER_PFM_M453)
+
+#ifndef OS_TASKCNT
+#define OS_TASKCNT              14
+#endif
+#ifndef OS_MAINSTKSIZE
+#define OS_MAINSTKSIZE          256
+#endif
+#ifndef OS_CLOCK
+#define OS_CLOCK                72000000
+#endif
+
+#if defined(__CC_ARM)
+    extern uint32_t               Image$$ARM_LIB_HEAP$$ZI$$Base[];
+    extern uint32_t               Image$$ARM_LIB_HEAP$$ZI$$Length[];
+    extern uint32_t               Image$$ARM_LIB_STACK$$ZI$$Base[];
+    extern uint32_t               Image$$ARM_LIB_STACK$$ZI$$Length[];
+    #define HEAP_START            ((unsigned char*) Image$$ARM_LIB_HEAP$$ZI$$Base)
+    #define HEAP_SIZE             ((uint32_t) Image$$ARM_LIB_HEAP$$ZI$$Length)
+    #define ISR_STACK_START       ((unsigned char*)Image$$ARM_LIB_STACK$$ZI$$Base)
+    #define ISR_STACK_SIZE        ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Length)
+#elif defined(__GNUC__)
+    extern uint32_t               __StackTop[];
+    extern uint32_t               __StackLimit[];
+    extern uint32_t               __end__[];
+    extern uint32_t               __HeapLimit[];
+    #define HEAP_START            ((unsigned char*)__end__)
+    #define HEAP_SIZE             ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START))
+    #define ISR_STACK_START       ((unsigned char*)__StackLimit)
+    #define ISR_STACK_SIZE        ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit))
+#elif defined(__ICCARM__)
+    /* No region declarations needed */
+#else
+    #error "no toolchain defined"
+#endif
+
 #endif
 
 #endif  // MBED_MBED_RTX_H
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/M451Series.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/M451Series.h
new file mode 100644
index 00000000000..516a181b6cb
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/M451Series.h
@@ -0,0 +1,17150 @@
+/******************************************************************************
+ * @file     M451Series.h
+ * @version  V3.10
+ * $Revision: 179 $
+ * $Date: 15/09/04 3:45p $
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M451 Series MCU
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+
+/**
+  \mainpage Introduction
+  *
+  *
+  * This user manual describes the usage of M451 Series MCU device driver
+  *
+  * <b>Disclaimer</b>
+  *
+  * The Software is furnished "AS IS", without warranty as to performance or results, and
+  * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
+  * warranties, express, implied or otherwise, with regard to the Software, its use, or
+  * operation, including without limitation any and all warranties of merchantability, fitness
+  * for a particular purpose, and non-infringement of intellectual property rights.
+  *
+  * <b>Copyright Notice</b>
+  *
+  * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+  */
+
+/**
+  * \page PG_REV Revision History
+  *
+  * <b>Revision 3.01.001</b>
+  * \li Added Nu-LB-M451, NuEdu and USB device sample code.
+  * \li Added a lacking macro SYS_IS_LVR_RST() to SYS driver.
+  * \li Added a sample code DAC_PDMA_ScatterGather_PWMTrigger to use PDMA scatter gather mode and trigger DAC by PWM.
+  * \li Added counter type constant definitions: PWM_UP_COUNTER, PWM_DOWN_COUNTER, and PWM_UP_DOWN_COUNTER.
+  * \li Added DAC_PDMA_PWMTrigger sample code to use PDMA and trigger DAC by PWM.
+  * \li Added a sample code EADC_PDMA_PWM_Trigger to trigger EADC with PWM and copy result by PDMA.
+  * \li Added a new function to control systick and select systick clock source CLK_EnableSysTick() and CLK_DisableSysTick() in CLK driver.
+  * \li Added 'NMIEN' and 'NMISTS' control registers to M451Series.h for NMI control.
+  * \li Added PDMA_ScatterGather_PingPongBuffer sample code to create ping-pong buffer with PDMA scatter gather mode.
+  * \li Added 'PE_DRVCTL' register of GPIO to M451Series.h for GPIO driving strength control.
+  * \li Added a sample code PWM_PDMA_Capture to transfer PWM capture data by PDMA.
+  * \li Added SCLIB_ActivateDelay API for initial SC with non-standard H/W design in SC driver
+  * \li Fixed the bug of EADC_IS_INT_FLAG_OV() that accesses the incorrect register.
+  * \li Fixed the bug of EADC_IS_SAMPLE_MODULE_OV() that accesses the incorrect register. 
+  * \li Fixed the bug of EADC_SetExtendSampleTime() for position shift error in EADC driver.
+  * \li Fixed the bug of EADC_SetTriggerDelayTime() for position shift error in EADC driver.
+  * \li Fixed the bug of PWM_ENABLE_OUTPUT_INVERTER () that output inverter function cannot be disabled.
+  * \li Fixed the bug of PWM_MASK_OUTPUT() in PWM driver that mask function cannot be disabled.
+  * \li Fixed CAN_STATUS_LEC_Msk from 0x03 to 0x07.
+  * \li Fixed the bug of CLK_SysTickDelay() that COUNTFLAG may not be cleared in CLK driver.
+  * \li Fixed CTL and PINCTL regsiter synchronize issue by waiting synchronized ready flag in SC driver.
+  * \li Fixed DAC_SetDelayTime() calculation error in DAC driver because the dac->TCTL only used 10 bits, not 14 bits.
+  * \li Fixed EADC_CMP_ADCMPIE_DISABLE definition error. 
+  * \li Fixed EADC_CMP_ADCMPIE_DISABLE definition error. 
+  * \li Fixed IAR entry point from __iar_program_start to Reset_Handler
+  * \li Fixed PWM_ConfigOutputChannel() return value bug in PWM driver.
+  * \li Fixed the bug of PWM_ConfigSyncPhase() that cannot configure synchronized source for channel2~5.
+  * \li Fixed SC_SET_STOP_BIT_LEN definition error.
+  * \li Fixed SCUART baudrate return error in SCUART_Open and SCUART_SetLineConfig API of SCUART driver.
+  * \li Fixed SCUART_PARITY_NONE/SCUART_PARITY_EVEN/SCUART_PARITY_ODD definition bug in SCUART driver.
+  * \li Fixed u32DataWidth setting error by sc->UARTCTL in SCUART_SetLineConfig API of SCUART driver.
+  * \li Fixed SMBD_Enable constant value definition error in I2C driver.
+  * \li Fixed the problem that MSC device detection is aborted due to REQUEST_SENSE command not ready.
+  * \li Fixed UART clock setting bug in UART_Open(), UART_SetLine_Config() and UART_SelectIrDAMode() of UART driver.
+  * \li Improved compatibility of USBH driver for pen driver.
+  * \li Improved EADC_ConfigSampleModule() to support rising and falling trigger at the same time.
+  * \li Improved EBI_SRAM sample code to add PDMA data transfer with EBI.
+  * \li Improved SC driver to support more than one SC port.
+  * \li Improved USBH driver to support composite HID devices
+  * \li Improved USBD driver to support more USB device sample code.
+  * \li Modified I2C_STOP() from #define to inline and add waiting STO bit clear to 0 . This modified is safe for next START coming soon.
+  * \li Removed CRC clock enabled in CRC_Open(). User should enable CRC clock in system initialization before any CRC operation.
+  * \li Removed FMC_ReadDID() in FMC driver. This function was no longer supported.
+  * \li Removed I2C_CTL_STA_STO_SI and I2C_CTL_STA_STO_SI_AA definitions to avoid STOP and START write to control bit at the same time.
+  *
+  * <b>Revision 3.00.005</b>
+  * \li Fixed EADC_CTL_DMOF_STRAIGHT_BINARY and EADC_CTL_DMOF_TWOS_COMPLEMENT definition error in EADC driver.
+  * \li Fixed EADC_FALLING_EDGE_TRIGGER definition error in EADC driver.
+  * \li Fixed EADC_RISING_EDGE_TRIGGER definition error in EADC driver.
+  * \li Fixed UART transmit data bug in UART_TEST_HANDLE() of UART_TxRxFunction sample code.
+  * \li Fixed the data missing bug when BULK IN transfer is end by max packet size packet at last packet in USBD_VCOM sample code.
+  * \li Fixed program user configuration area without erase in USBD_MassStorage_DataFlash sample code.
+  * \li Fixed the bug of switching HCLK to HIRC before enabling PLL in CLK_SetCoreClock() of CLK driver.
+  * \li Fixed isochronous transfer bugs of USB Host library.
+  * \li Fixed Clear Modem Status Interrupt flag bug in UART_ClearIntFlag() of UART driver.
+  * \li Fixed the time-out flag clear bug in I2C_ClearTimeoutFlag() of I2C driver.
+  * \li Replaced PERIOD0~5 with PERIOD[6] in PWM_T, and modified PERIOD bit field constant definition in M451Series.h.
+  * \li Replaced CMPDAT0~5 with CMPDAT0[6] in PWM_T, and modified CMPDAT bit field constant definition in M451Series.h.
+  * \li Replaced CNT0~5 with CNT[6] in PWM_T, and modified CNT bit field constant definition in M451Series.h.
+  * \li Replaced PBUF0~5 with PBUF[6] in PWM_T, and modified PBUF bit field constant definition in M451Series.h.
+  * \li Replaced CMPBUF0~5 with CMPBUF[6] in PWM_T, and modified CMPBUF bit field constant definition in M451Series.h.
+  * \li Replaced CURSCAT0~CURSCAT11 with CURSCAT[12] in PDMA_T of M451Series.h.
+  * \li Modified CLK_WaitClockReady() time-out to about 300 ms in CLK driver.
+  * \li Updated USB USBD_MassStorage_DataFlash sample code and USB Driver to pass USB-IF MSC test. (The MassStorage size must be greater than 64 KB; otherwise, Command Set test will fail in MSC test).
+  * \li Replaced old HID library file (open source) with Nuvoton HID library in USB Host library. 
+  * \li Added USBH_Audio_Class and USBH_UAC_HID sample code for USB Host to support UAC + HID device.
+  *
+  * <b>Revision 3.00.004</b>
+  * \li Fixed the time-out from 5 ms to 300 ms in CLK_WaitClockReady() of CLK driver.
+  * \li Fixed the bug of UART_ClearIntFlag() in UART driver to only clear one flag at one time.
+  * \li Fixed the missing parameter, UART clock source LXT, for CLK_SetModuleClock() in UART driver.
+  * \li Fixed the bug of clearing data and CTS wake-up flag to clear one flag at one time in UART1_IRQHandler() of UART_Wakeup sample code.
+  * \li Fixed the bug of RS485_HANDLE() in the UART_RS485_Slave sample code to only clear one flag at one time.
+  * \li Fixed the bug of clearing auto baud rate detect finished and time-out flag to clear one flag at one time in AutoBaudRate_RxTest() of UART_AutoBaudRate_Slave sample code.
+  * \li Fixed NVIC_EnableIRQ() to NVIC_DisableIRQ() after chip wake-up in I2C_Wakeup_Slave sample code.
+  * \li Fixed multi-function setting error of SC CD pin in USBD_CCID sample code.
+  * \li Fixed PD.7 (Headphone output control pin) output mode configuration in WAU8822_Setup() of USBD_Audio_NAU8822 sample code.
+  * \li Fixed wrong CLK_WaitClockReady parameter in I2C_GCMode_Slave sample code.
+  * \li Fixed UART data transfer bug of USBD_VCOM sample code.
+  * \li Updated CLK driver to avoid HIRC force enabled in CLK_SetHCLK() and CLK_SetCoreClock().
+  * \li Updated USBD driver to pass USB-IF MSC test.
+  * \li Updated USBD_MassStorage_DataFlash sample code to pass USB-IF MSC test.
+  * \li Updated driver of VCOM for win8 certification in USBD_VCOM sample code.
+  * \li Added HID Media key supporting in USBD_Audio_HID_NAU8822 sample code.
+  * \li Added new sample code USBH_UAC_HID of USB Host to support UAC + HID device.
+  * \li Added new sample code USBH_Audio_Class to support USB audio class device (UAC).
+  *
+  * <b>Revision 3.00.003</b>
+  * \li Added USBD_Audio_HID_NAU8822 sample code.
+  *
+  * <b>Revision 3.00.002</b>
+  * \li Fixed serial number code in device descriptor.
+  * \li Fixed EBI_Open API did not perform u32CSActiveLevel parameters to set CS pin polar.
+  * \li Fixed SMBus bus time-out and Clock Lo time-out API.
+  * \li Fixed I2C0,1 IP reset of SYS_IPRST1.
+  * \li Fixed include path of CMSIS.
+  * \li Fixed SPI_CLR_UNIT_TRANS_INT_FLAG( ) definition.
+  * \li Fixed USBD_INT_WAKEUP definition.
+  * \li Modified USBD driver to support USB remote wake-up function.
+  *
+  * <b>Revision 3.00.001</b>
+  * \li Initial Release.
+*/
+
+#ifndef __M451SERIES_H__
+#define __M451SERIES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************/
+/*                Processor and Core Peripherals                              */
+/******************************************************************************/
+/** @addtogroup CMSIS Device CMSIS Definitions
+  Configuration of the Cortex-M4 Processor and Core Peripherals
+  @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+    /******  Cortex-M4 Processor Exceptions Numbers ***************************************************/
+    NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
+    MemoryManagement_IRQn         = -12,      /*!<  4 Memory Management Interrupt                   */
+    BusFault_IRQn                 = -11,      /*!<  5 Bus Fault Interrupt                           */
+    UsageFault_IRQn               = -10,      /*!<  6 Usage Fault Interrupt                         */
+    SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
+    DebugMonitor_IRQn             = -4,       /*!< 12 Debug Monitor Interrupt                       */
+    PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
+    SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */
+
+    /******  M451 Specific Interrupt Numbers ********************************************************/
+
+    BOD_IRQn                      = 0,        /*!< Brown Out detection Interrupt                    */
+    IRC_IRQn                      = 1,        /*!< Internal RC Interrupt                            */
+    PWRWU_IRQn                    = 2,        /*!< Power Down Wake Up Interrupt                     */
+    RAMPE_IRQn                    = 3,        /*!< SRAM parity check failed Interrupt               */
+    CKFAIL_IRQn                   = 4,        /*!< Clock failed Interrupt                           */
+    RTC_IRQn                      = 6,        /*!< Real Time Clock Interrupt                        */
+    TAMPER_IRQn                   = 7,        /*!< Tamper detection Interrupt                       */
+    WDT_IRQn                      = 8,        /*!< Watchdog Timer Interrupt                         */
+    WWDT_IRQn                     = 9,        /*!< Window Watchdog Timer Interrupt                  */
+    EINT0_IRQn                    = 10,       /*!< External Input 0 Interrupt                       */
+    EINT1_IRQn                    = 11,       /*!< External Input 1 Interrupt                       */
+    EINT2_IRQn                    = 12,       /*!< External Input 2 Interrupt                       */
+    EINT3_IRQn                    = 13,       /*!< External Input 3 Interrupt                       */
+    EINT4_IRQn                    = 14,       /*!< External Input 4 Interrupt                       */
+    EINT5_IRQn                    = 15,       /*!< External Input 5 Interrupt                       */
+    GPA_IRQn                      = 16,       /*!< GPIO Port A Interrupt                            */
+    GPB_IRQn                      = 17,       /*!< GPIO Port B Interrupt                            */
+    GPC_IRQn                      = 18,       /*!< GPIO Port C Interrupt                            */
+    GPD_IRQn                      = 19,       /*!< GPIO Port D Interrupt                            */
+    GPE_IRQn                      = 20,       /*!< GPIO Port E Interrupt                            */
+    GPF_IRQn                      = 21,       /*!< GPIO Port F Interrupt                            */
+    SPI0_IRQn                     = 22,       /*!< SPI0 Interrupt                                   */
+    SPI1_IRQn                     = 23,       /*!< SPI1 Interrupt                                   */
+    BRAKE0_IRQn                   = 24,       /*!< BRAKE0 Interrupt                                 */
+    PWM0P0_IRQn                   = 25,       /*!< PWM0P0 Interrupt                                 */
+    PWM0P1_IRQn                   = 26,       /*!< PWM0P1 Interrupt                                 */
+    PWM0P2_IRQn                   = 27,       /*!< PWM0P2 Interrupt                                 */
+    BRAKE1_IRQn                   = 28,       /*!< BRAKE1 Interrupt                                 */
+    PWM1P0_IRQn                   = 29,       /*!< PWM1P0 Interrupt                                 */
+    PWM1P1_IRQn                   = 30,       /*!< PWM1P1 Interrupt                                 */
+    PWM1P2_IRQn                   = 31,       /*!< PWM1P2 Interrupt                                 */
+    TMR0_IRQn                     = 32,       /*!< Timer 0 Interrupt                                */
+    TMR1_IRQn                     = 33,       /*!< Timer 1 Interrupt                                */
+    TMR2_IRQn                     = 34,       /*!< Timer 2 Interrupt                                */
+    TMR3_IRQn                     = 35,       /*!< Timer 3 Interrupt                                */
+    UART0_IRQn                    = 36,       /*!< UART 0 Interrupt                                 */
+    UART1_IRQn                    = 37,       /*!< UART 1 Interrupt                                 */
+    I2C0_IRQn                     = 38,       /*!< I2C 0 Interrupt                                  */
+    I2C1_IRQn                     = 39,       /*!< I2C 1 Interrupt                                  */
+    PDMA_IRQn                     = 40,       /*!< Peripheral DMA Interrupt                         */
+    DAC_IRQn                      = 41,       /*!< DAC Interrupt                                    */
+    ADC00_IRQn                    = 42,       /*!< ADC0 Source 0 Interrupt                          */
+    ADC01_IRQn                    = 43,       /*!< ADC0 Source 1 Interrupt                          */
+    ACMP01_IRQn                   = 44,       /*!< Analog Comparator 0 and 1 Interrupt              */
+    ADC02_IRQn                    = 46,       /*!< ADC0 Source 2 Interrupt                          */
+    ADC03_IRQn                    = 47,       /*!< ADC0 Source 3 Interrupt                          */
+    UART2_IRQn                    = 48,       /*!< UART2 Interrupt                                  */
+    UART3_IRQn                    = 49,       /*!< UART3 Interrupt                                  */
+    SPI2_IRQn                     = 51,       /*!< SPI2 Interrupt                                   */
+    USBD_IRQn                     = 53,       /*!< USB device Interrupt                             */
+    USBH_IRQn                     = 54,       /*!< USB host Interrupt                               */
+    USBOTG_IRQn                   = 55,       /*!< USB OTG Interrupt                                */
+    CAN0_IRQn                     = 56,       /*!< CAN0 Interrupt                                   */
+    SC0_IRQn                      = 58,       /*!< Smart Card 0 Interrupt                           */
+    TK_IRQn                       = 63        /*!< Touch Key Interrupt                              */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M# Processor and Core Peripherals */
+#define __CM4_REV                 0x0201    /*!< Core Revision r2p1                               */
+#define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+#define __MPU_PRESENT             1         /*!< MPU present or not                               */
+#define __FPU_PRESENT             1         /*!< FPU present or not                               */
+
+/*@}*/ /* end of group CMSIS */
+
+#include "core_cm4.h"                       /* Cortex-M4 processor and core peripherals           */
+#include "system_M451Series.h"              /* M451 System include file                           */
+#include <stdint.h>
+
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Analog Comparator Controller -------------------------*/
+/**
+    @addtogroup ACMP Analog Comparator Controller(ACMP)
+    Memory Mapped Structure for ACMP Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var ACMP_T::CTL
+ * Offset: 0x00  Analog Comparator 0 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ACMPEN    |Comparator Enable Bit
+ * |        |          |0 = Comparator 0 Disabled.
+ * |        |          |1 = Comparator 0 Enabled.
+ * |[1]     |ACMPIE    |Comparator Interrupt Enable Bit
+ * |        |          |0 = Comparator 0 interrupt Disabled.
+ * |        |          |1 = Comparator 0 interrupt Enabled.
+ * |        |          |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
+ * |[2]     |HYSEN     |Comparator Hysteresis Enable Bit
+ * |        |          |0 = Comparator 0 hysteresis Disabled.
+ * |        |          |1 = Comparator 0 hysteresis Enabled.
+ * |[3]     |ACMPOINV  |Comparator Output Inverse
+ * |        |          |0 = Comparator 0 output inverse Disabled.
+ * |        |          |1 = Comparator 0 output inverse Enabled.
+ * |[5:4]   |NEGSEL    |Comparator Negative Input Selection
+ * |        |          |00 = ACMP0_N pin.
+ * |        |          |01 = Internal comparator reference voltage (CRV).
+ * |        |          |10 = Band-gap voltage.
+ * |        |          |11 = DAC output.
+ * |[7:6]   |POSSEL    |Comparator Positive Input Selection
+ * |        |          |00 = Input from ACMP0_P0.
+ * |        |          |01 = Input from ACMP0_P1.
+ * |        |          |10 = Input from ACMP0_P2.
+ * |        |          |11 = Input from ACMP0_P3.
+ * |[9:8]   |INTPOL    |Interrupt Condition Polarity Selection
+ * |        |          |ACMPIF0 will be set to 1 when comparator output edge condition is detected.
+ * |        |          |00 = Rising edge or falling edge.
+ * |        |          |01 = Rising edge.
+ * |        |          |10 = Falling edge.
+ * |        |          |11 = Reserved.
+ * |[12]    |OUTSEL    |Comparator Output Select
+ * |        |          |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.
+ * |        |          |1 = Comparator 0 output to ACMP0_O pin is from filter output.
+ * |[15:13] |FILTSEL   |Comparator Output Filter Count Selection
+ * |        |          |000 = Filter function is Disabled.
+ * |        |          |001 = ACMP0 output is sampled 1 consecutive PCLK.
+ * |        |          |010 = ACMP0 output is sampled 2 consecutive PCLKs.
+ * |        |          |011 = ACMP0 output is sampled 4 consecutive PCLKs.
+ * |        |          |100 = ACMP0 output is sampled 8 consecutive PCLKs.
+ * |        |          |101 = ACMP0 output is sampled 16 consecutive PCLKs.
+ * |        |          |110 = ACMP0 output is sampled 32 consecutive PCLKs.
+ * |        |          |111 = ACMP0 output is sampled 64 consecutive PCLKs.
+ * |[16]    |WKEN      |Power Down Wake-Up Enable Bit
+ * |        |          |0 = Wake-up function Disabled.
+ * |        |          |1 = Wake-up function Enabled.
+ * ---------------------------------------------------------------------------------------------------
+ * Offset: 0x04  Analog Comparator 1 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ACMPEN    |Comparator Enable Bit
+ * |        |          |0 = Comparator 1 Disabled.
+ * |        |          |1 = Comparator 1 Enabled.
+ * |[1]     |ACMPIE    |Comparator Interrupt Enable Bit
+ * |        |          |0 = Comparator 1 interrupt Disabled.
+ * |        |          |1 = Comparator 1 interrupt Enabled.
+ * |        |          |If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well.
+ * |[2]     |HYSEN     |Comparator Hysteresis Enable Bit
+ * |        |          |0 = Comparator 1 hysteresis Disabled.
+ * |        |          |1 = Comparator 1 hysteresis Enabled.
+ * |[3]     |ACMPOINV  |Comparator Output Inverse Control
+ * |        |          |0 = Comparator 1 output inverse Disabled.
+ * |        |          |1 = Comparator 1 output inverse Enabled.
+ * |[5:4]   |NEGSEL    |Comparator Negative Input Selection
+ * |        |          |00 = ACMP1_N pin.
+ * |        |          |01 = Internal comparator reference voltage (CRV).
+ * |        |          |10 = Band-gap voltage.
+ * |        |          |11 = DAC output.
+ * |[7:6]   |POSSEL    |Comparator Positive Input Selection
+ * |        |          |00 = Input from ACMP1_P0.
+ * |        |          |01 = Input from ACMP1_P1.
+ * |        |          |10 = Input from ACMP1_P2.
+ * |        |          |11 = Input from ACMP1_P3.
+ * |[9:8]   |INTPOL    |Interrupt Condition Polarity Selection
+ * |        |          |ACMPIF1 will be set to 1 when comparator output edge condition is detected.
+ * |        |          |00 = Rising edge or falling edge.
+ * |        |          |01 = Rising edge.
+ * |        |          |10 = Falling edge.
+ * |        |          |11 = Reserved.
+ * |[12]    |OUTSEL    |Comparator Output Select
+ * |        |          |0 = Comparator 1 output to ACMP1_O pin is unfiltered comparator output.
+ * |        |          |1 = Comparator 1 output to ACMP1_O pin is from filter output.
+ * |[15:13] |FILTSEL   |Comparator Output Filter Count Selection
+ * |        |          |000 = Filter function is Disabled.
+ * |        |          |001 = ACMP1 output is sampled 1 consecutive PCLK.
+ * |        |          |010 = ACMP1 output is sampled 2 consecutive PCLKs.
+ * |        |          |011 = ACMP1 output is sampled 4 consecutive PCLKs.
+ * |        |          |100 = ACMP1 output is sampled 8 consecutive PCLKs.
+ * |        |          |101 = ACMP1 output is sampled 16 consecutive PCLKs.
+ * |        |          |110 = ACMP1 output is sampled 32 consecutive PCLKs.
+ * |        |          |111 = ACMP1 output is sampled 64 consecutive PCLKs.
+ * |[16]    |WKEN      |Power Down Wakeup Enable Bit
+ * |        |          |0 = Wake-up function Disabled.
+ * |        |          |1 = Wake-up function Enabled.
+ * @var ACMP_T::STATUS
+ * Offset: 0x08  Analog Comparator Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ACMPIF0   |Comparator 0 Interrupt Flag
+ * |        |          |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output.
+ * |        |          |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
+ * |        |          |Note: Write 1 to clear this bit to 0.
+ * |[1]     |ACMPIF1   |Comparator 1 Interrupt Flag
+ * |        |          |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output.
+ * |        |          |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
+ * |        |          |Note: Write 1 to clear this bit to 0.
+ * |[4]     |ACMPO0    |Comparator 0 Output
+ * |        |          |Synchronized to the PCLK to allow reading by software.
+ * |        |          |Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
+ * |[5]     |ACMPO1    |Comparator 1 Output
+ * |        |          |Synchronized to the PCLK to allow reading by software.
+ * |        |          |Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
+ * |[8]     |WKIF0     |Comparator 0 Power Down Wake-Up Interrupt Flag
+ * |        |          |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
+ * |        |          |0 = No power down wake-up occurred.
+ * |        |          |1 = Power down wake-up occurred.
+ * |        |          |Note: Write 1 to clear this bit to 0.
+ * |[9]     |WKIF1     |Comparator 1 Power Down Wake-Up Interrupt Flag
+ * |        |          |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
+ * |        |          |0 = No power down wake-up occurred.
+ * |        |          |1 = Power down wake-up occurred.
+ * |        |          |Note: Write 1 to clear this bit to 0.
+ * @var ACMP_T::VREF
+ * Offset: 0x0C  Analog Comparator Reference Voltage Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |CRVCTL    |Comparator Reference Voltage Setting
+ * |        |          |CRV = CRV source voltage * (1/6+CRVCTL/24).
+ * |[6]     |CRVSSEL   |CRV Source Voltage Selection
+ * |        |          |0 = VDDA is selected as CRV source voltage.
+ * |        |          |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
+ */
+
+    __IO uint32_t CTL[2];        /* Offset: 0x00  Analog Comparator Control Register                                 */
+    __IO uint32_t STATUS;        /* Offset: 0x08  Analog Comparator Status Register                                  */
+    __IO uint32_t VREF;          /* Offset: 0x0C  Analog Comparator Reference Voltage Control Register               */
+
+} ACMP_T;
+
+
+
+/**
+    @addtogroup ACMP_CONST ACMP Bit Field Definition
+    Constant Definitions for ACMP Controller
+@{ */
+
+#define ACMP_CTL_ACMPEN_Pos              (0)                                               /*!< ACMP_T::CTL: ACMPEN Position             */
+#define ACMP_CTL_ACMPEN_Msk              (0x1ul << ACMP_CTL_ACMPEN_Pos)                    /*!< ACMP_T::CTL: ACMPEN Mask                 */
+
+#define ACMP_CTL_ACMPIE_Pos              (1)                                               /*!< ACMP_T::CTL: ACMPIE Position             */
+#define ACMP_CTL_ACMPIE_Msk              (0x1ul << ACMP_CTL_ACMPIE_Pos)                    /*!< ACMP_T::CTL: ACMPIE Mask                 */
+
+#define ACMP_CTL_HYSEN_Pos               (2)                                               /*!< ACMP_T::CTL: HYSEN Position              */
+#define ACMP_CTL_HYSEN_Msk               (0x1ul << ACMP_CTL_HYSEN_Pos)                     /*!< ACMP_T::CTL: HYSEN Mask                  */
+
+#define ACMP_CTL_ACMPOINV_Pos            (3)                                               /*!< ACMP_T::CTL: ACMPOINV Position           */
+#define ACMP_CTL_ACMPOINV_Msk            (0x1ul << ACMP_CTL_ACMPOINV_Pos)                  /*!< ACMP_T::CTL: ACMPOINV Mask               */
+
+#define ACMP_CTL_NEGSEL_Pos              (4)                                               /*!< ACMP_T::CTL: NEGSEL Position             */
+#define ACMP_CTL_NEGSEL_Msk              (0x3ul << ACMP_CTL_NEGSEL_Pos)                    /*!< ACMP_T::CTL: NEGSEL Mask                 */
+
+#define ACMP_CTL_POSSEL_Pos              (6)                                               /*!< ACMP_T::CTL: POSSEL Position             */
+#define ACMP_CTL_POSSEL_Msk              (0x3ul << ACMP_CTL_POSSEL_Pos)                    /*!< ACMP_T::CTL: POSSEL Mask                 */
+
+#define ACMP_CTL_INTPOL_Pos              (8)                                               /*!< ACMP_T::CTL: INTPOL Position             */
+#define ACMP_CTL_INTPOL_Msk              (0x3ul << ACMP_CTL_INTPOL_Pos)                    /*!< ACMP_T::CTL: INTPOL Mask                 */
+
+#define ACMP_CTL_OUTSEL_Pos              (12)                                              /*!< ACMP_T::CTL: OUTSEL Position             */
+#define ACMP_CTL_OUTSEL_Msk              (0x1ul << ACMP_CTL_OUTSEL_Pos)                    /*!< ACMP_T::CTL: OUTSEL Mask                 */
+
+#define ACMP_CTL_FILTSEL_Pos             (13)                                              /*!< ACMP_T::CTL: FILTSEL Position            */
+#define ACMP_CTL_FILTSEL_Msk             (0x7ul << ACMP_CTL_FILTSEL_Pos)                   /*!< ACMP_T::CTL: FILTSEL Mask                */
+
+#define ACMP_CTL_WKEN_Pos                (16)                                              /*!< ACMP_T::CTL: WKEN Position               */
+#define ACMP_CTL_WKEN_Msk                (0x1ul << ACMP_CTL_WKEN_Pos)                      /*!< ACMP_T::CTL: WKEN Mask                   */
+
+#define ACMP_STATUS_ACMPIF0_Pos          (0)                                               /*!< ACMP_T::STATUS: ACMPIF0 Position         */
+#define ACMP_STATUS_ACMPIF0_Msk          (0x1ul << ACMP_STATUS_ACMPIF0_Pos)                /*!< ACMP_T::STATUS: ACMPIF0 Mask             */
+
+#define ACMP_STATUS_ACMPIF1_Pos          (1)                                               /*!< ACMP_T::STATUS: ACMPIF1 Position         */
+#define ACMP_STATUS_ACMPIF1_Msk          (0x1ul << ACMP_STATUS_ACMPIF1_Pos)                /*!< ACMP_T::STATUS: ACMPIF1 Mask             */
+
+#define ACMP_STATUS_ACMPO0_Pos           (4)                                               /*!< ACMP_T::STATUS: ACMPO0 Position          */
+#define ACMP_STATUS_ACMPO0_Msk           (0x1ul << ACMP_STATUS_ACMPO0_Pos)                 /*!< ACMP_T::STATUS: ACMPO0 Mask              */
+
+#define ACMP_STATUS_ACMPO1_Pos           (5)                                               /*!< ACMP_T::STATUS: ACMPO1 Position          */
+#define ACMP_STATUS_ACMPO1_Msk           (0x1ul << ACMP_STATUS_ACMPO1_Pos)                 /*!< ACMP_T::STATUS: ACMPO1 Mask              */
+
+#define ACMP_STATUS_WKIF0_Pos            (8)                                               /*!< ACMP_T::STATUS: WKIF0 Position           */
+#define ACMP_STATUS_WKIF0_Msk            (0x1ul << ACMP_STATUS_WKIF0_Pos)                  /*!< ACMP_T::STATUS: WKIF0 Mask               */
+
+#define ACMP_STATUS_WKIF1_Pos            (9)                                               /*!< ACMP_T::STATUS: WKIF1 Position           */
+#define ACMP_STATUS_WKIF1_Msk            (0x1ul << ACMP_STATUS_WKIF1_Pos)                  /*!< ACMP_T::STATUS: WKIF1 Mask               */
+
+#define ACMP_VREF_CRVCTL_Pos             (0)                                               /*!< ACMP_T::VREF: CRVCTL Position            */
+#define ACMP_VREF_CRVCTL_Msk             (0xful << ACMP_VREF_CRVCTL_Pos)                   /*!< ACMP_T::VREF: CRVCTL Mask                */
+
+#define ACMP_VREF_CRVSSEL_Pos            (6)                                               /*!< ACMP_T::VREF: CRVSSEL Position           */
+#define ACMP_VREF_CRVSSEL_Msk            (0x1ul << ACMP_VREF_CRVSSEL_Pos)                  /*!< ACMP_T::VREF: CRVSSEL Mask               */
+
+/**@}*/ /* ACMP_CONST */
+/**@}*/ /* end of ACMP register group */
+
+
+/*---------------------- Enhanced Analog to Digital Converter -------------------------*/
+/**
+    @addtogroup Enhanced Analog to Digital Converter(EADC)
+    Memory Mapped Structure for EADC Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var EADC_T::DAT
+ * Offset: 0x00-0x48  A/D Data Register n for Sample Module n, n=0~18
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |RESULT    |A/D Conversion Result
+ * |        |          |This field contains 12 bits conversion result.
+ * |        |          |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
+ * |        |          |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
+ * |[16]    |OV        |Overrun Flag
+ * |        |          |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
+ * |        |          |0 = Data in RESULT[11:0] is recent conversion result.
+ * |        |          |1 = Data in RESULT[11:0] is overwrite.
+ * |        |          |Note: It is cleared by hardware after EADC_DAT register is read.
+ * |[17]    |VALID     |Valid Flag
+ * |        |          |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
+ * |        |          |0 = Data in RESULT[11:0] bits is not valid.
+ * |        |          |1 = Data in RESULT[11:0] bits is valid.
+ * @var EADC_T::CURDAT
+ * Offset: 0x4C  EADC PDMA Current Transfer Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[17:0]  |CURDAT    |ADC PDMA Current Transfer Data Register
+ * |        |          |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.
+ * |        |          |This is a read only register.
+ * @var EADC_T::CTL
+ * Offset: 0x50  A/D Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ADCEN     |A/D Converter Enable Bit
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |        |          |Note: Before starting A/D conversion function, this bit should be set to 1.
+ * |        |          |Clear it to 0 to disable A/D converter analog circuit power consumption.
+ * |[1]     |ADCRST    |ADC A/D Converter Control Circuits Reset
+ * |        |          |0 = No effect.
+ * |        |          |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
+ * |        |          |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
+ * |[2]     |ADCIEN0   |Specific Sample Module A/D ADINT0 Interrupt Enable Bit
+ * |        |          |The A/D converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module A/D conversion.
+ * |        |          |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
+ * |        |          |0 = Specific sample module A/D ADINT0 interrupt function Disabled.
+ * |        |          |1 = Specific sample module A/D ADINT0 interrupt function Enabled.
+ * |[3]     |ADCIEN1   |Specific Sample Module A/D ADINT1 Interrupt Enable Bit
+ * |        |          |The A/D converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module A/D conversion.
+ * |        |          |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
+ * |        |          |0 = Specific sample module A/D ADINT1 interrupt function Disabled.
+ * |        |          |1 = Specific sample module A/D ADINT1 interrupt function Enabled.
+ * |[4]     |ADCIEN2   |Specific Sample Module A/D ADINT2 Interrupt Enable Bit
+ * |        |          |The A/D converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module A/D conversion.
+ * |        |          |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
+ * |        |          |0 = Specific sample module A/D ADINT2 interrupt function Disabled.
+ * |        |          |1 = Specific sample module A/D ADINT2 interrupt function Enabled.
+ * |[5]     |ADCIEN3   |Specific Sample Module A/D ADINT3 Interrupt Enable Bit
+ * |        |          |The A/D converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module A/D conversion.
+ * |        |          |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
+ * |        |          |0 = Specific sample module A/D ADINT3 interrupt function Disabled.
+ * |        |          |1 = Specific sample module A/D ADINT3 interrupt function Enabled.
+ * |[8]     |DIFFEN    |Differential Analog Input Mode Enable Bit
+ * |        |          |0 = Single-end analog input mode.
+ * |        |          |1 = Differential analog input mode.
+ * |[9]     |DMOF      |ADC Differential Input Mode Output Format
+ * |        |          |0 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format.
+ * |        |          |1 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format.
+ * |[11]    |PDMAEN    |PDMA Transfer Enable Bit
+ * |        |          |When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
+ * |        |          |0 = PDMA data transfer Disabled.
+ * |        |          |1 = PDMA data transfer Enabled.
+ * |        |          |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
+ * |[18:16] |SMPTSEL   |ADC Internal Sampling Time Selection
+ * |        |          |ADC internal sampling cycle = SMPTSEL + 1.
+ * |        |          |000 = 1 ADC clock sampling time.
+ * |        |          |001 = 2 ADC clock sampling time.
+ * |        |          |010 = 3 ADC clock sampling time.
+ * |        |          |011 = 4 ADC clock sampling time.
+ * |        |          |100 = 5 ADC clock sampling time.
+ * |        |          |101 = 6 ADC clock sampling time.
+ * |        |          |110 = 7 ADC clock sampling time.
+ * |        |          |111 = 8 ADC clock sampling time.
+ * @var EADC_T::SWTRG
+ * Offset: 0x54  A/D Sample Module Software Start Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[18:0]  |SWTRG     |A/D Sample Module
+ * |        |          |0~18 Software Force To Start ADC Conversion
+ * |        |          |0 = No effect.
+ * |        |          |1 = Cause an ADC conversion when the priority is given to sample module.
+ * |        |          |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion.
+ * |        |          |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
+ * @var EADC_T::PENDSTS
+ * Offset: 0x58  A/D Start of Conversion Pending Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[18:0]  |STPF      |A/D Sample Module 0~18 Start Of Conversion Pending Flag
+ * |        |          |Read:
+ * |        |          |0 = There is no pending conversion for sample module.
+ * |        |          |1 = Sample module ADC start of conversion is pending.
+ * |        |          |Write:
+ * |        |          |1 = clear pending flag and cancel the conversion for sample module.
+ * |        |          |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0
+ * @var EADC_T::OVSTS
+ * Offset: 0x5C  A/D Sample Module Start of Conversion Overrun Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[18:0]  |SPOVF     |A/D SAMPLE0~18 Overrun Flag
+ * |        |          |0 = No sample module event overrun.
+ * |        |          |1 = Indicates a new sample module event is generated while an old one event is pending.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * @var EADC_T::SCTL
+ * Offset: 0x80-0x8C  A/D Sample Module n Control Register, n=0~3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |CHSEL     |A/D Sample Module Channel Selection
+ * |        |          |00H = EADC_CH0.
+ * |        |          |01H = EADC_CH1.
+ * |        |          |02H = EADC_CH2.
+ * |        |          |03H = EADC_CH3.
+ * |        |          |04H = EADC_CH4.
+ * |        |          |05H = EADC_CH5.
+ * |        |          |06H = EADC_CH6.
+ * |        |          |07H = EADC_CH7.
+ * |        |          |08H = EADC_CH8.
+ * |        |          |09H = EADC_CH9.
+ * |        |          |0AH = EADC_CH10.
+ * |        |          |0BH = EADC_CH11.
+ * |        |          |0CH = EADC_CH12.
+ * |        |          |0DH = EADC_CH13.
+ * |        |          |0EH = EADC_CH14.
+ * |        |          |0FH = EADC_CH15.
+ * |[4]     |EXTREN    |A/D External Trigger Rising Edge Enable Bit
+ * |        |          |0 = Rising edge Disabled when A/D selects STADC as trigger source.
+ * |        |          |1 = Rising edge Enabled when A/D selects STADC as trigger source.
+ * |[5]     |EXTFEN    |A/D External Trigger Falling Edge Enable Bit
+ * |        |          |0 = Falling edge Disabled when A/D selects STADC as trigger source.
+ * |        |          |1 = Falling edge Enabled when A/D selects STADC as trigger source.
+ * |[7:6]   |TRGDLYDIV |A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
+ * |        |          |Trigger delay clock frequency:
+ * |        |          |00 = ADC_CLK/1.
+ * |        |          |01 = ADC_CLK/2.
+ * |        |          |10 = ADC_CLK/4.
+ * |        |          |11 = ADC_CLK/16.
+ * |[15:8]  |TRGDLYCNT |A/D Sample Module Start Of Conversion Trigger Delay Time
+ * |        |          |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
+ * |[20:16] |TRGSEL    |A/D Sample Module Start Of Conversion Trigger Source Selection
+ * |        |          |0H = Disable trigger.
+ * |        |          |1H = External trigger from STADC pin input.
+ * |        |          |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.
+ * |        |          |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.
+ * |        |          |4H = Timer0 overflow pulse trigger.
+ * |        |          |5H = Timer1 overflow pulse trigger.
+ * |        |          |6H = Timer2 overflow pulse trigger.
+ * |        |          |7H = Timer3 overflow pulse trigger.
+ * |        |          |8H = PWM0TG0.
+ * |        |          |9H = PWM0TG1.
+ * |        |          |AH = PWM0TG2.
+ * |        |          |BH = PWM0TG3.
+ * |        |          |CH = PWM0TG4.
+ * |        |          |DH = PWM0TG5.
+ * |        |          |EH = PWM1TG0.
+ * |        |          |FH = PWM1TG1.
+ * |        |          |10H = PWM1TG2.
+ * |        |          |11H = PWM1TG3.
+ * |        |          |12H = PWM1TG4.
+ * |        |          |13H = PWM1TG5.
+ * |        |          |other = Reserved.
+ * |[22]    |INTPOS    |Interrupt Flag Position Select
+ * |        |          |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
+ * |        |          |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
+ * |[23]    |DBMEN     |Double Buffer Mode Enable Bit
+ * |        |          |0 = Sample has one sample result register. (default).
+ * |        |          |1 = Sample has two sample result registers.
+ * |[31:24] |EXTSMPT   |ADC Sampling Time Extend
+ * |        |          |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time.
+ * |        |          |The range of start delay time is from 0~255 ADC clock.
+ * @var EADC_T::SCTL
+ * Offset: 0x90-0xBC  A/D Sample Module n Control Register, n=4~15
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |CHSEL     |A/D Sample Module Channel Selection
+ * |        |          |00H = EADC_CH0.
+ * |        |          |01H = EADC_CH1.
+ * |        |          |02H = EADC_CH2.
+ * |        |          |03H = EADC_CH3.
+ * |        |          |04H = EADC_CH4.
+ * |        |          |05H = EADC_CH5.
+ * |        |          |06H = EADC_CH6.
+ * |        |          |07H = EADC_CH7.
+ * |        |          |08H = EADC_CH8.
+ * |        |          |09H = EADC_CH9.
+ * |        |          |0AH = EADC_CH10.
+ * |        |          |0BH = EADC_CH11.
+ * |        |          |0CH = EADC_CH12.
+ * |        |          |0DH = EADC_CH13.
+ * |        |          |0EH = EADC_CH14.
+ * |        |          |0FH = EADC_CH15.
+ * |[4]     |EXTREN    |A/D External Trigger Rising Edge Enable Bit
+ * |        |          |0 = Rising edge Disabled when A/D selects STADC as trigger source.
+ * |        |          |1 = Rising edge Enabled when A/D selects STADC as trigger source.
+ * |[5]     |EXTFEN    |A/D External Trigger Falling Edge Enable Bit
+ * |        |          |0 = Falling edge Disabled when A/D selects STADC as trigger source.
+ * |        |          |1 = Falling edge Enabled when A/D selects STADC as trigger source.
+ * |[7:6]   |TRGDLYDIV[1:0]|A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
+ * |        |          |Trigger delay clock frequency:
+ * |        |          |00 = ADC_CLK/1.
+ * |        |          |01 = ADC_CLK/2.
+ * |        |          |10 = ADC_CLK/4.
+ * |        |          |11 = ADC_CLK/16.
+ * |[15:8]  |TRGDLYCNT[7:0]|A/D Sample Module Start Of Conversion Trigger Delay Time
+ * |        |          |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
+ * |[20:16] |TRGSEL    |A/D Sample Module Start Of Conversion Trigger Source Selection
+ * |        |          |0H = Disable trigger.
+ * |        |          |1H = External trigger from STADC pin input.
+ * |        |          |2H = ADC ADINT0 interrupt EOC pulse trigger.
+ * |        |          |3H = ADC ADINT1 interrupt EOC pulse trigger.
+ * |        |          |4H = Timer0 overflow pulse trigger.
+ * |        |          |5H = Timer1 overflow pulse trigger.
+ * |        |          |6H = Timer2 overflow pulse trigger.
+ * |        |          |7H = Timer3 overflow pulse trigger.
+ * |        |          |8H = PWM0TG0.
+ * |        |          |9H = PWM0TG1.
+ * |        |          |AH = PWM0TG2.
+ * |        |          |BH = PWM0TG3.
+ * |        |          |CH = PWM0TG4.
+ * |        |          |DH = PWM0TG5.
+ * |        |          |EH = PWM1TG0.
+ * |        |          |FH = PWM1TG1.
+ * |        |          |10H = PWM1TG2.
+ * |        |          |11H = PWM1TG3.
+ * |        |          |12H = PWM1TG4.
+ * |        |          |13H = PWM1TG5.
+ * |        |          |other = Reserved.
+ * |[22]    |INTPOS    |Interrupt Flag Position Select
+ * |        |          |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
+ * |        |          |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
+ * |[31:24] |EXTSMPT   |ADC Sampling Time Extend
+ * |        |          |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
+ * |        |          |The range of start delay time is from 0~255 ADC clock.
+ * @var EADC_T::SCTL
+ * Offset: 0xC0~0xC8  A/D Sample Module n Control Register, n=16~18
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:24] |EXTSMPT   |ADC Sampling Time Extend
+ * |        |          |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
+ * |        |          |The range of start delay time is from 0~255 ADC clock.
+ * @var EADC_T::INTSRC
+ * Offset: 0xDC  ADC interrupt n Source Enable Control Register, n=0~3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SPLIE0    |Sample Module 0 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 0 interrupt Disabled.
+ * |        |          |1 = Sample Module 0 interrupt Enabled.
+ * |[1]     |SPLIE1    |Sample Module 1 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 1 interrupt Disabled.
+ * |        |          |1 = Sample Module 1 interrupt Enabled.
+ * |[2]     |SPLIE2    |Sample Module 2 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 2 interrupt Disabled.
+ * |        |          |1 = Sample Module 2 interrupt Enabled.
+ * |[3]     |SPLIE3    |Sample Module 3 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 3 interrupt Disabled.
+ * |        |          |1 = Sample Module 3 interrupt Enabled.
+ * |[4]     |SPLIE4    |Sample Module 4 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 4 interrupt Disabled.
+ * |        |          |1 = Sample Module 4 interrupt Enabled.
+ * |[5]     |SPLIE5    |Sample Module 5 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 5 interrupt Disabled.
+ * |        |          |1 = Sample Module 5 interrupt Enabled.
+ * |[6]     |SPLIE6    |Sample Module 6 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 6 interrupt Disabled.
+ * |        |          |1 = Sample Module 6 interrupt Enabled.
+ * |[7]     |SPLIE7    |Sample Module 7 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 7 interrupt Disabled.
+ * |        |          |1 = Sample Module 7 interrupt Enabled.
+ * |[8]     |SPLIE8    |Sample Module 8 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 8 interrupt Disabled.
+ * |        |          |1 = Sample Module 8 interrupt Enabled.
+ * |[9]     |SPLIE9    |Sample Module 9 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 9 interrupt Disabled.
+ * |        |          |1 = Sample Module 9 interrupt Enabled.
+ * |[10]    |SPLIE10   |Sample Module 10 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 10 interrupt Disabled.
+ * |        |          |1 = Sample Module 10 interrupt Enabled.
+ * |[11]    |SPLIE11   |Sample Module 11 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 11 interrupt Disabled.
+ * |        |          |1 = Sample Module 11 interrupt Enabled.
+ * |[12]    |SPLIE12   |Sample Module 12 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 12 interrupt Disabled.
+ * |        |          |1 = Sample Module 12 interrupt Enabled.
+ * |[13]    |SPLIE13   |Sample Module 13 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 13 interrupt Disabled.
+ * |        |          |1 = Sample Module 13 interrupt Enabled.
+ * |[14]    |SPLIE14   |Sample Module 14 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 14 interrupt Disabled.
+ * |        |          |1 = Sample Module 14 interrupt Enabled.
+ * |[15]    |SPLIE15   |Sample Module 15 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 15 interrupt Disabled.
+ * |        |          |1 = Sample Module 15 interrupt Enabled.
+ * |[16]    |SPLIE16   |Sample Module 16 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 16 interrupt Disabled.
+ * |        |          |1 = Sample Module 16 interrupt Enabled.
+ * |[17]    |SPLIE17   |Sample Module 17 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 17 interrupt Disabled.
+ * |        |          |1 = Sample Module 17 interrupt Enabled.
+ * |[18]    |SPLIE18   |Sample Module 18 Interrupt Enable Bit
+ * |        |          |0 = Sample Module 18 interrupt Disabled.
+ * |        |          |1 = Sample Module 18 interrupt Enabled.
+ * @var EADC_T::CMP
+ * Offset: 0xEC  A/D Result Compare Register n, n=0~3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ADCMPEN   |A/D Result Compare Enable Bit
+ * |        |          |0 = Compare Disabled.
+ * |        |          |1 = Compare Enabled.
+ * |        |          |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.
+ * |[1]     |ADCMPIE   |A/D Result Compare Interrupt Enable Bit
+ * |        |          |0 = Compare function interrupt Disabled.
+ * |        |          |1 = Compare function interrupt Enabled.
+ * |        |          |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
+ * |[2]     |CMPCOND   |Compare Condition
+ * |        |          |0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPn
+ * |        |          |[27:16]), the internal match counter will increase one.
+ * |        |          |1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
+ * |        |          |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set.
+ * |[7:3]   |CMPSPL    |Compare Sample Module Selection
+ * |        |          |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.
+ * |        |          |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.
+ * |        |          |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.
+ * |        |          |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
+ * |        |          |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.
+ * |        |          |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.
+ * |        |          |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.
+ * |        |          |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.
+ * |        |          |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.
+ * |        |          |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.
+ * |        |          |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.
+ * |        |          |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.
+ * |        |          |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.
+ * |        |          |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.
+ * |        |          |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.
+ * |        |          |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.
+ * |        |          |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.
+ * |        |          |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.
+ * |        |          |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.
+ * |[11:8]  |CMPMCNT   |Compare Match Count
+ * |        |          |When the specified A/D sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1.
+ * |        |          |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0.
+ * |        |          |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.
+ * |[15]    |CMPWEN    |Compare Window Mode Enable Bit
+ * |        |          |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched.
+ * |        |          |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched.
+ * |        |          |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
+ * |        |          |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
+ * |        |          |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
+ * |[27:16] |CMPDAT    |Comparison Data
+ * |        |          |The 12 bits data is used to compare with conversion result of specified sample module.
+ * |        |          |User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
+ * @var EADC_T::STATUS0
+ * Offset: 0xF0  A/D Status Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |VALID     |EADC_DAT0~15 Data Valid Flag
+ * |        |          |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
+ * |[31:16] |OV        |EADC_DAT0~15 Overrun Flag
+ * |        |          |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).
+ * @var EADC_T::STATUS1
+ * Offset: 0xF4  A/D Status Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[2:0]   |VALID     |EADC_DAT16~18 Data Valid Flag
+ * |        |          |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
+ * |[18:16] |OV        |EADC_DAT16~18 Overrun Flag
+ * |        |          |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).
+ * @var EADC_T::STATUS2
+ * Offset: 0xF8  A/D Status Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ADIF0     |A/D ADINT0 Interrupt Flag
+ * |        |          |0 = No ADINT0 interrupt pulse received.
+ * |        |          |1 = ADINT0 interrupt pulse has been received.
+ * |        |          |Note1: This bit is cleared by writing 1 to it.
+ * |        |          |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
+ * |[1]     |ADIF1     |A/D ADINT1 Interrupt Flag
+ * |        |          |0 = No ADINT1 interrupt pulse received.
+ * |        |          |1 = ADINT1 interrupt pulse has been received.
+ * |        |          |Note1: This bit is cleared by writing 1 to it.
+ * |        |          |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
+ * |[2]     |ADIF2     |A/D ADINT2 Interrupt Flag
+ * |        |          |0 = No ADINT2 interrupt pulse received.
+ * |        |          |1 = ADINT2 interrupt pulse has been received.
+ * |        |          |Note1: This bit is cleared by writing 1 to it.
+ * |        |          |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
+ * |[3]     |ADIF3     |A/D ADINT3 Interrupt Flag
+ * |        |          |0 = No ADINT3 interrupt pulse received.
+ * |        |          |1 = ADINT3 interrupt pulse has been received.
+ * |        |          |Note1: This bit is cleared by writing 1 to it.
+ * |        |          |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
+ * |[4]     |ADCMPF0   |ADC Compare 0 Flag
+ * |        |          |When the specific sample module A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
+ * |        |          |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.
+ * |        |          |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * |[5]     |ADCMPF1   |ADC Compare 1 Flag
+ * |        |          |When the specific sample module A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
+ * |        |          |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.
+ * |        |          |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * |[6]     |ADCMPF2   |ADC Compare 2 Flag
+ * |        |          |When the specific sample module A/D conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
+ * |        |          |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.
+ * |        |          |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * |[7]     |ADCMPF3   |ADC Compare 3 Flag
+ * |        |          |When the specific sample module A/D conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
+ * |        |          |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.
+ * |        |          |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * |[8]     |ADOVIF0   |A/D ADINT0 Interrupt Flag Overrun
+ * |        |          |0 = ADINT0 interrupt flag is not overwritten to 1.
+ * |        |          |1 = ADINT0 interrupt flag is overwritten to 1.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * |[9]     |ADOVIF1   |A/D ADINT1 Interrupt Flag Overrun
+ * |        |          |0 = ADINT1 interrupt flag is not overwritten to 1.
+ * |        |          |1 = ADINT1 interrupt flag is overwritten to 1.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * |[10]    |ADOVIF2   |A/D ADINT2 Interrupt Flag Overrun
+ * |        |          |0 = ADINT2 interrupt flag is not overwritten to 1.
+ * |        |          |1 = ADINT2 interrupt flag is s overwritten to 1.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * |[11]    |ADOVIF3   |A/D ADINT3 Interrupt Flag Overrun
+ * |        |          |0 = ADINT3 interrupt flag is not overwritten to 1.
+ * |        |          |1 = ADINT3 interrupt flag is overwritten to 1.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * |[12]    |ADCMPO0   |ADC Compare 0 Output Status
+ * |        |          |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module.
+ * |        |          |User can use it to monitor the external analog input pin voltage status.
+ * |        |          |0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
+ * |        |          |1 = Conversion result in EADC_DAT great than or equal CMPDAT0
+ * |        |          |setting.
+ * |[13]    |ADCMPO1   |ADC Compare 1 Output Status
+ * |        |          |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module.
+ * |        |          |User can use it to monitor the external analog input pin voltage status.
+ * |        |          |0 = Conversion result in EADC_DAT less than CMPDAT1 setting.
+ * |        |          |1 = Conversion result in EADC_DAT great than or equal CMPDAT1
+ * |        |          |setting.
+ * |[14]    |ADCMPO2   |ADC Compare 2 Output Status
+ * |        |          |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module.
+ * |        |          |User can use it to monitor the external analog input pin voltage status.
+ * |        |          |0 = Conversion result in EADC_DAT less than CMPDAT2 setting.
+ * |        |          |1 = Conversion result in EADC_DAT great than or equal CMPDAT2
+ * |        |          |setting.
+ * |[15]    |ADCMPO3   |ADC Compare 3 Output Status
+ * |        |          |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module.
+ * |        |          |User can use it to monitor the external analog input pin voltage status.
+ * |        |          |0 = Conversion result in EADC_DAT less than CMPDAT3 setting.
+ * |        |          |1 = Conversion result in EADC_DAT great than or equal CMPDAT3
+ * |        |          |setting.
+ * |[20:16] |CHANNEL   |Current Conversion Channel
+ * |        |          |This filed reflects ADC current conversion channel when BUSY=1.
+ * |        |          |It is read only.
+ * |        |          |00H = EADC_CH0.
+ * |        |          |01H = EADC_CH1.
+ * |        |          |02H = EADC_CH2.
+ * |        |          |03H = EADC_CH3.
+ * |        |          |04H = EADC_CH4.
+ * |        |          |05H = EADC_CH5.
+ * |        |          |06H = EADC_CH6.
+ * |        |          |07H = EADC_CH7.
+ * |        |          |08H = EADC_CH8.
+ * |        |          |09H = EADC_CH9.
+ * |        |          |0AH = EADC_CH10.
+ * |        |          |0BH = EADC_CH11.
+ * |        |          |0CH = EADC_CH12.
+ * |        |          |0DH = EADC_CH13.
+ * |        |          |0EH = EADC_CH14.
+ * |        |          |0FH = EADC_CH15.
+ * |        |          |10H = VBG.
+ * |        |          |11H = VTEMP.
+ * |        |          |12H = VBAT.
+ * |[23]    |BUSY      |Busy/Idle
+ * |        |          |0 = EADC is in idle state.
+ * |        |          |1 = EADC is busy at conversion.
+ * |        |          |Note: This bit is read only.
+ * |[24]    |ADOVIF    |All A/D Interrupt Flag Overrun Bits Check
+ * |        |          |n=0~3.
+ * |        |          |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+ * |        |          |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+ * |        |          |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
+ * |[25]    |STOVF     |For All A/D Sample Module Start Of Conversion Overrun Flags Check
+ * |        |          |n=0~18.
+ * |        |          |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+ * |        |          |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+ * |        |          |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
+ * |[26]    |AVALID    |For All Sample Module A/D Result Data Register EADC_DAT Data Valid Flag Check
+ * |        |          |n=0~18.
+ * |        |          |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+ * |        |          |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+ * |        |          |Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
+ * |[27]    |AOV       |For All Sample Module A/D Result Data Register Overrun Flags Check
+ * |        |          |n=0~18.
+ * |        |          |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+ * |        |          |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+ * |        |          |Note: This bit will keep 1 when any OVn Flag is equal to 1.
+ * @var EADC_T::STATUS3
+ * Offset: 0xFC  A/D Status Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[4:0]   |CURSPL    |ADC Current Sample Module
+ * |        |          |This register show the current ADC is controlled by which sample module control logic modules.
+ * |        |          |If the ADC is Idle, this bit filed will set to 0x1F.
+ * |        |          |This is a read only register.
+ * @var EADC_T::DDAT
+ * Offset: 0x100-0x10C  A/D Double Data Register n for Sample Module n, n=0~3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |RESULT    |A/D Conversion Results
+ * |        |          |This field contains 12 bits conversion results.
+ * |        |          |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
+ * |        |          |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
+ * |[16]    |OV        |Overrun Flag
+ * |        |          |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.
+ * |        |          |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.
+ * |        |          |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
+ * |        |          |It is cleared by hardware after EADC_DDAT register is read.
+ * |[17]    |VALID     |Valid Flag
+ * |        |          |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.
+ * |        |          |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.
+ * |        |          |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read.
+ * |        |          |(n=0~3).
+ */
+
+    __I  uint32_t DAT[19];       /* Offset: 0x00-0x48  A/D Data Register n for Sample Module n, n=0~18               */
+    __I  uint32_t CURDAT;        /* Offset: 0x4C  EADC PDMA Current Transfer Data Register                           */
+    __IO uint32_t CTL;           /* Offset: 0x50  A/D Control Register                                               */
+    __O  uint32_t SWTRG;         /* Offset: 0x54  A/D Sample Module Software Start Register                          */
+    __IO uint32_t PENDSTS;       /* Offset: 0x58  A/D Start of Conversion Pending Flag Register                      */
+    __IO uint32_t OVSTS;         /* Offset: 0x5C  A/D Sample Module Start of Conversion Overrun Flag Register        */
+    __I  uint32_t RESERVE0[8];  
+    __IO uint32_t SCTL[19];      /* Offset: 0x80-0xC8  A/D Sample Module n Control Register, n=0~3                   */
+    __I  uint32_t RESERVE1[1];  
+    __IO uint32_t INTSRC[4];     /* Offset: 0xDC  ADC interrupt n Source Enable Control Register, n=0~3              */
+    __IO uint32_t CMP[4];        /* Offset: 0xEC  A/D Result Compare Register n, n=0~3                               */
+    __I  uint32_t STATUS0;       /* Offset: 0xF0  A/D Status Register 0                                              */
+    __I  uint32_t STATUS1;       /* Offset: 0xF4  A/D Status Register 1                                              */
+    __IO uint32_t STATUS2;       /* Offset: 0xF8  A/D Status Register 2                                              */
+    __I  uint32_t STATUS3;       /* Offset: 0xFC  A/D Status Register 3                                              */
+    __I  uint32_t DDAT[4];       /* Offset: 0x100-0x10C  A/D Double Data Register n for Sample Module n, n=0~3       */
+
+} EADC_T;
+
+
+
+/**
+    @addtogroup EADC_CONST EADC Bit Field Definition
+    Constant Definitions for EADC Controller
+@{ */
+#define EADC_DAT_RESULT_Pos               (0)                                               /*!< EADC_T::DAT: RESULT Position              */
+#define EADC_DAT_RESULT_Msk               (0xfffful << EADC_DAT_RESULT_Pos)                 /*!< EADC_T::DAT: RESULT Mask                  */
+
+#define EADC_DAT_OV_Pos                   (16)                                              /*!< EADC_T::DAT: OV Position                  */
+#define EADC_DAT_OV_Msk                   (0x1ul << EADC_DAT_OV_Pos)                        /*!< EADC_T::DAT: OV Mask                      */
+
+#define EADC_DAT_VALID_Pos                (17)                                              /*!< EADC_T::DAT: VALID Position               */
+#define EADC_DAT_VALID_Msk                (0x1ul << EADC_DAT_VALID_Pos)                     /*!< EADC_T::DAT: VALID Mask                   */
+
+#define EADC_CURDAT_CURDAT_Pos            (0)                                               /*!< EADC_T::CURDAT: CURDAT Position           */
+#define EADC_CURDAT_CURDAT_Msk            (0x3fffful << EADC_CURDAT_CURDAT_Pos)             /*!< EADC_T::CURDAT: CURDAT Mask               */
+
+#define EADC_CTL_ADCEN_Pos                (0)                                               /*!< EADC_T::CTL: ADCEN Position               */
+#define EADC_CTL_ADCEN_Msk                (0x1ul << EADC_CTL_ADCEN_Pos)                     /*!< EADC_T::CTL: ADCEN Mask                   */
+
+#define EADC_CTL_ADRST_Pos                (1)                                               /*!< EADC_T::CTL: ADRST Position               */
+#define EADC_CTL_ADRST_Msk                (0x1ul << EADC_CTL_ADRST_Pos)                     /*!< EADC_T::CTL: ADRST Mask                   */
+
+#define EADC_CTL_ADCIEN0_Pos              (2)                                               /*!< EADC_T::CTL: ADCIEN0 Position             */
+#define EADC_CTL_ADCIEN0_Msk              (0x1ul << EADC_CTL_ADCIEN0_Pos)                   /*!< EADC_T::CTL: ADCIEN0 Mask                 */
+
+#define EADC_CTL_ADCIEN1_Pos              (3)                                               /*!< EADC_T::CTL: ADCIEN1 Position             */
+#define EADC_CTL_ADCIEN1_Msk              (0x1ul << EADC_CTL_ADCIEN1_Pos)                   /*!< EADC_T::CTL: ADCIEN1 Mask                 */
+
+#define EADC_CTL_ADCIEN2_Pos              (4)                                               /*!< EADC_T::CTL: ADCIEN2 Position             */
+#define EADC_CTL_ADCIEN2_Msk              (0x1ul << EADC_CTL_ADCIEN2_Pos)                   /*!< EADC_T::CTL: ADCIEN2 Mask                 */
+
+#define EADC_CTL_ADCIEN3_Pos              (5)                                               /*!< EADC_T::CTL: ADCIEN3 Position             */
+#define EADC_CTL_ADCIEN3_Msk              (0x1ul << EADC_CTL_ADCIEN3_Pos)                   /*!< EADC_T::CTL: ADCIEN3 Mask                 */
+
+#define EADC_CTL_DIFFEN_Pos               (8)                                               /*!< EADC_T::CTL: DIFFEN Position              */
+#define EADC_CTL_DIFFEN_Msk               (0x1ul << EADC_CTL_DIFFEN_Pos)                    /*!< EADC_T::CTL: DIFFEN Mask                  */
+
+#define EADC_CTL_DMOF_Pos                 (9)                                               /*!< EADC_T::CTL: DMOF Position                */
+#define EADC_CTL_DMOF_Msk                 (0x1ul << EADC_CTL_DMOF_Pos)                      /*!< EADC_T::CTL: DMOF Mask                    */
+
+#define EADC_CTL_PDMAEN_Pos               (11)                                              /*!< EADC_T::CTL: PDMAEN Position              */
+#define EADC_CTL_PDMAEN_Msk               (0x1ul << EADC_CTL_PDMAEN_Pos)                    /*!< EADC_T::CTL: PDMAEN Mask                  */
+
+#define EADC_CTL_SMPTSEL_Pos              (16)                                              /*!< EADC_T::CTL: SMPTSEL Position             */
+#define EADC_CTL_SMPTSEL_Msk              (0x7ul << EADC_CTL_SMPTSEL_Pos)                   /*!< EADC_T::CTL: SMPTSEL Mask                 */
+
+#define EADC_SWTRG_SWTRG_Pos              (0)                                               /*!< EADC_T::SWTRG: SWTRG Position             */
+#define EADC_SWTRG_SWTRG_Msk              (0x7fffful << EADC_SWTRG_SWTRG_Pos)               /*!< EADC_T::SWTRG: SWTRG Mask                 */
+
+#define EADC_PENDSTS_STPF_Pos             (0)                                               /*!< EADC_T::PENDSTS: STPF Position            */
+#define EADC_PENDSTS_STPF_Msk             (0x7fffful << EADC_PENDSTS_STPF_Pos)              /*!< EADC_T::PENDSTS: STPF Mask                */
+
+#define EADC_OVSTS_SPOVF_Pos              (0)                                               /*!< EADC_T::OVSTS: SPOVF Position             */
+#define EADC_OVSTS_SPOVF_Msk              (0x7fffful << EADC_OVSTS_SPOVF_Pos)               /*!< EADC_T::OVSTS: SPOVF Mask                 */
+
+#define EADC_SCTL_CHSEL_Pos               (0)                                               /*!< EADC_T::SCTL: CHSEL Position              */
+#define EADC_SCTL_CHSEL_Msk               (0xful << EADC_SCTL_CHSEL_Pos)                    /*!< EADC_T::SCTL: CHSEL Mask                  */
+
+#define EADC_SCTL_EXTREN_Pos              (4)                                               /*!< EADC_T::SCTL: EXTREN Position             */
+#define EADC_SCTL_EXTREN_Msk              (0x1ul << EADC_SCTL_EXTREN_Pos)                   /*!< EADC_T::SCTL: EXTREN Mask                 */
+
+#define EADC_SCTL_EXTFEN_Pos              (5)                                               /*!< EADC_T::SCTL: EXTFEN Position             */
+#define EADC_SCTL_EXTFEN_Msk              (0x1ul << EADC_SCTL_EXTFEN_Pos)                   /*!< EADC_T::SCTL: EXTFEN Mask                 */
+
+#define EADC_SCTL_TRGDLYDIV_Pos           (6)                                               /*!< EADC_T::SCTL: TRGDLYDIV Position          */
+#define EADC_SCTL_TRGDLYDIV_Msk           (0x3ul << EADC_SCTL_TRGDLYDIV_Pos)                /*!< EADC_T::SCTL: TRGDLYDIV Mask              */
+
+#define EADC_SCTL_TRGDLYCNT_Pos           (8)                                               /*!< EADC_T::SCTL: TRGDLYCNT Position          */
+#define EADC_SCTL_TRGDLYCNT_Msk           (0xfful << EADC_SCTL_TRGDLYCNT_Pos)               /*!< EADC_T::SCTL: TRGDLYCNT Mask              */
+
+#define EADC_SCTL_TRGSEL_Pos              (16)                                              /*!< EADC_T::SCTL: TRGSEL Position             */
+#define EADC_SCTL_TRGSEL_Msk              (0x1ful << EADC_SCTL_TRGSEL_Pos)                  /*!< EADC_T::SCTL: TRGSEL Mask                 */
+
+#define EADC_SCTL_INTPOS_Pos              (22)                                              /*!< EADC_T::SCTL: INTPOS Position             */
+#define EADC_SCTL_INTPOS_Msk              (0x1ul << EADC_SCTL_INTPOS_Pos)                   /*!< EADC_T::SCTL: INTPOS Mask                 */
+
+#define EADC_SCTL_DBMEN_Pos               (23)                                              /*!< EADC_T::SCTL: DBMEN Position              */
+#define EADC_SCTL_DBMEN_Msk               (0x1ul << EADC_SCTL_DBMEN_Pos)                    /*!< EADC_T::SCTL: DBMEN Mask                  */
+
+#define EADC_SCTL_EXTSMPT_Pos             (24)                                              /*!< EADC_T::SCTL: EXTSMPT Position            */
+#define EADC_SCTL_EXTSMPT_Msk             (0xfful << EADC_SCTL_EXTSMPT_Pos)                 /*!< EADC_T::SCTL: EXTSMPT Mask                */
+
+#define EADC_INTSRC_SPLIE_Pos             (0)                                               /*!< EADC_T::INTSRC: SPLIE Position            */
+#define EADC_INTSRC_SPLIE_Msk             (0x7FFFFul << EADC_INTSRC_SPLIE_Pos)              /*!< EADC_T::INTSRC: SPLIE Mask                */
+
+#define EADC_CMP_ADCMPEN_Pos              (0)                                               /*!< EADC_T::CMP: ADCMPEN Position             */
+#define EADC_CMP_ADCMPEN_Msk              (0x1ul << EADC_CMP_ADCMPEN_Pos)                   /*!< EADC_T::CMP: ADCMPEN Mask                 */
+
+#define EADC_CMP_ADCMPIE_Pos              (1)                                               /*!< EADC_T::CMP: ADCMPIE Position             */
+#define EADC_CMP_ADCMPIE_Msk              (0x1ul << EADC_CMP_ADCMPIE_Pos)                   /*!< EADC_T::CMP: ADCMPIE Mask                 */
+
+#define EADC_CMP_CMPCOND_Pos              (2)                                               /*!< EADC_T::CMP: CMPCOND Position             */
+#define EADC_CMP_CMPCOND_Msk              (0x1ul << EADC_CMP_CMPCOND_Pos)                   /*!< EADC_T::CMP: CMPCOND Mask                 */
+
+#define EADC_CMP_CMPSPL_Pos               (3)                                               /*!< EADC_T::CMP: CMPSPL Position              */
+#define EADC_CMP_CMPSPL_Msk               (0x1ful << EADC_CMP_CMPSPL_Pos)                   /*!< EADC_T::CMP: CMPSPL Mask                  */
+
+#define EADC_CMP_CMPMCNT_Pos              (8)                                               /*!< EADC_T::CMP: CMPMCNT Position             */
+#define EADC_CMP_CMPMCNT_Msk              (0xful << EADC_CMP_CMPMCNT_Pos)                   /*!< EADC_T::CMP: CMPMCNT Mask                 */
+
+#define EADC_CMP_CMPWEN_Pos               (15)                                              /*!< EADC_T::CMP: CMPWEN Position              */
+#define EADC_CMP_CMPWEN_Msk               (0x1ul << EADC_CMP_CMPWEN_Pos)                    /*!< EADC_T::CMP: CMPWEN Mask                  */
+
+#define EADC_CMP_CMPDAT_Pos               (16)                                              /*!< EADC_T::CMP: CMPDAT Position              */
+#define EADC_CMP_CMPDAT_Msk               (0xffful << EADC_CMP_CMPDAT_Pos)                  /*!< EADC_T::CMP: CMPDAT Mask                  */
+
+#define EADC_STATUS0_VALID_Pos            (0)                                               /*!< EADC_T::STATUS0: VALID Position           */
+#define EADC_STATUS0_VALID_Msk            (0xfffful << EADC_STATUS0_VALID_Pos)              /*!< EADC_T::STATUS0: VALID Mask               */
+
+#define EADC_STATUS0_OV_Pos               (16)                                              /*!< EADC_T::STATUS0: OV Position              */
+#define EADC_STATUS0_OV_Msk               (0xfffful << EADC_STATUS0_OV_Pos)                 /*!< EADC_T::STATUS0: OV Mask                  */
+
+#define EADC_STATUS1_VALID_Pos            (0)                                               /*!< EADC_T::STATUS1: VALID Position           */
+#define EADC_STATUS1_VALID_Msk            (0x7ul << EADC_STATUS1_VALID_Pos)                 /*!< EADC_T::STATUS1: VALID Mask               */
+
+#define EADC_STATUS1_OV_Pos               (16)                                              /*!< EADC_T::STATUS1: OV Position              */
+#define EADC_STATUS1_OV_Msk               (0x7ul << EADC_STATUS1_OV_Pos)                    /*!< EADC_T::STATUS1: OV Mask                  */
+
+#define EADC_STATUS2_ADIF0_Pos            (0)                                               /*!< EADC_T::STATUS2: ADIF0 Position           */
+#define EADC_STATUS2_ADIF0_Msk            (0x1ul << EADC_STATUS2_ADIF0_Pos)                 /*!< EADC_T::STATUS2: ADIF0 Mask               */
+
+#define EADC_STATUS2_ADIF1_Pos            (1)                                               /*!< EADC_T::STATUS2: ADIF1 Position           */
+#define EADC_STATUS2_ADIF1_Msk            (0x1ul << EADC_STATUS2_ADIF1_Pos)                 /*!< EADC_T::STATUS2: ADIF1 Mask               */
+
+#define EADC_STATUS2_ADIF2_Pos            (2)                                               /*!< EADC_T::STATUS2: ADIF2 Position           */
+#define EADC_STATUS2_ADIF2_Msk            (0x1ul << EADC_STATUS2_ADIF2_Pos)                 /*!< EADC_T::STATUS2: ADIF2 Mask               */
+
+#define EADC_STATUS2_ADIF3_Pos            (3)                                               /*!< EADC_T::STATUS2: ADIF3 Position           */
+#define EADC_STATUS2_ADIF3_Msk            (0x1ul << EADC_STATUS2_ADIF3_Pos)                 /*!< EADC_T::STATUS2: ADIF3 Mask               */
+
+#define EADC_STATUS2_ADCMPF0_Pos          (4)                                               /*!< EADC_T::STATUS2: ADCMPF0 Position         */
+#define EADC_STATUS2_ADCMPF0_Msk          (0x1ul << EADC_STATUS2_ADCMPF0_Pos)               /*!< EADC_T::STATUS2: ADCMPF0 Mask             */
+
+#define EADC_STATUS2_ADCMPF1_Pos          (5)                                               /*!< EADC_T::STATUS2: ADCMPF1 Position         */
+#define EADC_STATUS2_ADCMPF1_Msk          (0x1ul << EADC_STATUS2_ADCMPF1_Pos)               /*!< EADC_T::STATUS2: ADCMPF1 Mask             */
+
+#define EADC_STATUS2_ADCMPF2_Pos          (6)                                               /*!< EADC_T::STATUS2: ADCMPF2 Position         */
+#define EADC_STATUS2_ADCMPF2_Msk          (0x1ul << EADC_STATUS2_ADCMPF2_Pos)               /*!< EADC_T::STATUS2: ADCMPF2 Mask             */
+
+#define EADC_STATUS2_ADCMPF3_Pos          (7)                                               /*!< EADC_T::STATUS2: ADCMPF3 Position         */
+#define EADC_STATUS2_ADCMPF3_Msk          (0x1ul << EADC_STATUS2_ADCMPF3_Pos)               /*!< EADC_T::STATUS2: ADCMPF3 Mask             */
+
+#define EADC_STATUS2_ADOVIF0_Pos          (8)                                               /*!< EADC_T::STATUS2: ADOVIF0 Position         */
+#define EADC_STATUS2_ADOVIF0_Msk          (0x1ul << EADC_STATUS2_ADOVIF0_Pos)               /*!< EADC_T::STATUS2: ADOVIF0 Mask             */
+
+#define EADC_STATUS2_ADOVIF1_Pos          (9)                                               /*!< EADC_T::STATUS2: ADOVIF1 Position         */
+#define EADC_STATUS2_ADOVIF1_Msk          (0x1ul << EADC_STATUS2_ADOVIF1_Pos)               /*!< EADC_T::STATUS2: ADOVIF1 Mask             */
+
+#define EADC_STATUS2_ADOVIF2_Pos          (10)                                              /*!< EADC_T::STATUS2: ADOVIF2 Position         */
+#define EADC_STATUS2_ADOVIF2_Msk          (0x1ul << EADC_STATUS2_ADOVIF2_Pos)               /*!< EADC_T::STATUS2: ADOVIF2 Mask             */
+
+#define EADC_STATUS2_ADOVIF3_Pos          (11)                                              /*!< EADC_T::STATUS2: ADOVIF3 Position         */
+#define EADC_STATUS2_ADOVIF3_Msk          (0x1ul << EADC_STATUS2_ADOVIF3_Pos)               /*!< EADC_T::STATUS2: ADOVIF3 Mask             */
+
+#define EADC_STATUS2_ADCMPO0_Pos          (12)                                              /*!< EADC_T::STATUS2: ADCMPO0 Position         */
+#define EADC_STATUS2_ADCMPO0_Msk          (0x1ul << EADC_STATUS2_ADCMPO0_Pos)               /*!< EADC_T::STATUS2: ADCMPO0 Mask             */
+
+#define EADC_STATUS2_ADCMPO1_Pos          (13)                                              /*!< EADC_T::STATUS2: ADCMPO1 Position         */
+#define EADC_STATUS2_ADCMPO1_Msk          (0x1ul << EADC_STATUS2_ADCMPO1_Pos)               /*!< EADC_T::STATUS2: ADCMPO1 Mask             */
+
+#define EADC_STATUS2_ADCMPO2_Pos          (14)                                              /*!< EADC_T::STATUS2: ADCMPO2 Position         */
+#define EADC_STATUS2_ADCMPO2_Msk          (0x1ul << EADC_STATUS2_ADCMPO2_Pos)               /*!< EADC_T::STATUS2: ADCMPO2 Mask             */
+
+#define EADC_STATUS2_ADCMPO3_Pos          (15)                                              /*!< EADC_T::STATUS2: ADCMPO3 Position         */
+#define EADC_STATUS2_ADCMPO3_Msk          (0x1ul << EADC_STATUS2_ADCMPO3_Pos)               /*!< EADC_T::STATUS2: ADCMPO3 Mask             */
+
+#define EADC_STATUS2_CHANNEL_Pos          (16)                                              /*!< EADC_T::STATUS2: CHANNEL Position         */
+#define EADC_STATUS2_CHANNEL_Msk          (0x1ful << EADC_STATUS2_CHANNEL_Pos)              /*!< EADC_T::STATUS2: CHANNEL Mask             */
+
+#define EADC_STATUS2_BUSY_Pos             (23)                                              /*!< EADC_T::STATUS2: BUSY Position            */
+#define EADC_STATUS2_BUSY_Msk             (0x1ul << EADC_STATUS2_BUSY_Pos)                  /*!< EADC_T::STATUS2: BUSY Mask                */
+
+#define EADC_STATUS2_ADOVIF_Pos           (24)                                              /*!< EADC_T::STATUS2: ADOVIF Position          */
+#define EADC_STATUS2_ADOVIF_Msk           (0x1ul << EADC_STATUS2_ADOVIF_Pos)                /*!< EADC_T::STATUS2: ADOVIF Mask              */
+
+#define EADC_STATUS2_STOVF_Pos            (25)                                              /*!< EADC_T::STATUS2: STOVF Position           */
+#define EADC_STATUS2_STOVF_Msk            (0x1ul << EADC_STATUS2_STOVF_Pos)                 /*!< EADC_T::STATUS2: STOVF Mask               */
+
+#define EADC_STATUS2_AVALID_Pos           (26)                                              /*!< EADC_T::STATUS2: AVALID Position          */
+#define EADC_STATUS2_AVALID_Msk           (0x1ul << EADC_STATUS2_AVALID_Pos)                /*!< EADC_T::STATUS2: AVALID Mask              */
+
+#define EADC_STATUS2_AOV_Pos              (27)                                              /*!< EADC_T::STATUS2: AOV Position             */
+#define EADC_STATUS2_AOV_Msk              (0x1ul << EADC_STATUS2_AOV_Pos)                   /*!< EADC_T::STATUS2: AOV Mask                 */
+
+#define EADC_STATUS3_CURSPL_Pos           (0)                                               /*!< EADC_T::STATUS3: CURSPL Position          */
+#define EADC_STATUS3_CURSPL_Msk           (0x1ful << EADC_STATUS3_CURSPL_Pos)               /*!< EADC_T::STATUS3: CURSPL Mask              */
+
+#define EADC_DDAT_RESULT_Pos              (0)                                               /*!< EADC_T::DDAT: RESULT Position             */
+#define EADC_DDAT_RESULT_Msk              (0xfffful << EADC_DDAT_RESULT_Pos)                /*!< EADC_T::DDAT: RESULT Mask                 */
+
+#define EADC_DDAT_OV_Pos                  (16)                                              /*!< EADC_T::DDAT: OV Position                 */
+#define EADC_DDAT_OV_Msk                  (0x1ul << EADC_DDAT_OV_Pos)                       /*!< EADC_T::DDAT: OV Mask                     */
+
+#define EADC_DDAT_VALID_Pos               (17)                                              /*!< EADC_T::DDAT: VALID Position              */
+#define EADC_DDAT_VALID_Msk               (0x1ul << EADC_DDAT_VALID_Pos)                    /*!< EADC_T::DDAT: VALID Mask                  */
+
+
+/**@}*/ /* EADC_CONST */
+/**@}*/ /* end of EADC register group */
+
+
+/*---------------------- Controller Area Network Controller -------------------------*/
+/**
+    @addtogroup CAN Controller Area Network Controller(CAN)
+    Memory Mapped Structure for CAN Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+/**
+ * @var CAN_IF_T::CREQ
+ * Offset: 0x20, 0x80  IFn (Register Map Note 2) Command Request Registers
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |MessageNumber|Message Number
+ * |        |          |0x01-0x20: Valid Message Number, the Message Object in the Message
+ * |        |          |RAM is selected for data transfer.
+ * |        |          |0x00: Not a valid Message Number, interpreted as 0x20.
+ * |        |          |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
+ * |[15]    |Busy      |Busy Flag
+ * |        |          |0 = Read/write action has finished.
+ * |        |          |1 = Writing to the IFn Command Request Register is in progress.
+ * |        |          |This bit can only be read by the software.
+ * @var CAN_IF_T::CMASK
+ * Offset: 0x24, 0x84  IFn Command Mask Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |DAT_B     |Access Data Bytes [7:4]
+ * |        |          |Write Operation:
+ * |        |          |0 = Data Bytes [7:4] unchanged.
+ * |        |          |1 = Transfer Data Bytes [7:4] to Message Object.
+ * |        |          |Read Operation:
+ * |        |          |0 = Data Bytes [7:4] unchanged.
+ * |        |          |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
+ * |[1]     |DAT_A     |Access Data Bytes [3:0]
+ * |        |          |Write Operation:
+ * |        |          |0 = Data Bytes [3:0] unchanged.
+ * |        |          |1 = Transfer Data Bytes [3:0] to Message Object.
+ * |        |          |Read Operation:
+ * |        |          |0 = Data Bytes [3:0] unchanged.
+ * |        |          |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
+ * |[2]     |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
+ * |        |          |0 = TxRqst bit unchanged.
+ * |        |          |1 = Set TxRqst bit.
+ * |        |          |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
+ * |        |          |Access New Data Bit when Read Operation.
+ * |        |          |0 = NewDat bit remains unchanged.
+ * |        |          |1 = Clear NewDat bit in the Message Object.
+ * |        |          |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.
+ * |        |          |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
+ * |[3]     |ClrIntPnd |Clear Interrupt Pending Bit
+ * |        |          |Write Operation:
+ * |        |          |When writing to a Message Object, this bit is ignored.
+ * |        |          |Read Operation:
+ * |        |          |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
+ * |        |          |1 = Clear IntPnd bit in the Message Object.
+ * |[4]     |Control   |Control Access Control Bits
+ * |        |          |Write Operation:
+ * |        |          |0 = Control Bits unchanged.
+ * |        |          |1 = Transfer Control Bits to Message Object.
+ * |        |          |Read Operation:
+ * |        |          |0 = Control Bits unchanged.
+ * |        |          |1 = Transfer Control Bits to IFn Message Buffer Register.
+ * |[5]     |Arb       |Access Arbitration Bits
+ * |        |          |Write Operation:
+ * |        |          |0 = Arbitration bits unchanged.
+ * |        |          |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.
+ * |        |          |Read Operation:
+ * |        |          |0 = Arbitration bits unchanged.
+ * |        |          |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
+ * |[6]     |Mask      |Access Mask Bits
+ * |        |          |Write Operation:
+ * |        |          |0 = Mask bits unchanged.
+ * |        |          |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
+ * |        |          |Read Operation:
+ * |        |          |0 = Mask bits unchanged.
+ * |        |          |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
+ * |[7]     |WR_RD     |Write / Read Mode
+ * |        |          |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
+ * |        |          |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
+ * @var CAN_IF_T::MASK1
+ * Offset: 0x28, 0x88  IFn Mask 1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |Msk[15:0] |Identifier Mask 15-0
+ * |        |          |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
+ * |        |          |1 = The corresponding identifier bit is used for acceptance filtering.
+ * @var CAN_IF_T::MASK2
+ * Offset: 0x2C, 0x8C  IFn Mask 2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[12:0]  |Msk[28:16]|Identifier Mask 28-16
+ * |        |          |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
+ * |        |          |1 = The corresponding identifier bit is used for acceptance filtering.
+ * |[14]    |MDir      |Mask Message Direction
+ * |        |          |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
+ * |        |          |1 = The message direction bit (Dir) is used for acceptance filtering.
+ * |[15]    |MXtd      |Mask Extended Identifier
+ * |        |          |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
+ * |        |          |1 = The extended identifier bit (IDE) is used for acceptance filtering.
+ * |        |          |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).
+ * |        |          |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
+ * @var CAN_IF_T::ARB1
+ * Offset: 0x30, 0x90  IFn Arbitration 1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |ID[15:0]  |Message Identifier 15-0
+ * |        |          |ID28 - ID0, 29-bit Identifier ("Extended Frame").
+ * |        |          |ID28 - ID18, 11-bit Identifier ("Standard Frame")
+ * @var CAN_IF_T::ARB2
+ * Offset: 0x34, 0x94  IFn Arbitration 2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[12:0]  |ID[28:16] |Message Identifier 28-16
+ * |        |          |ID28 - ID0, 29-bit Identifier ("Extended Frame").
+ * |        |          |ID28 - ID18, 11-bit Identifier ("Standard Frame")
+ * |[13]    |Dir       |Message Direction
+ * |        |          |0 = Direction is receive.
+ * |        |          |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.
+ * |        |          |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
+ * |        |          |1 = Direction is transmit.
+ * |        |          |On TxRqst, the respective Message Object is transmitted as a Data Frame.
+ * |        |          |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
+ * |[14]    |Xtd       |Extended Identifier
+ * |        |          |0 = The 11-bit ("standard") Identifier will be used for this Message Object.
+ * |        |          |1 = The 29-bit ("extended") Identifier will be used for this Message Object.
+ * |[15]    |MsgVal    |Message Valid
+ * |        |          |0 = The Message Object is ignored by the Message Handler.
+ * |        |          |1 = The Message Object is configured and should be considered by the Message Handler.
+ * |        |          |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).
+ * |        |          |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
+ * @var CAN_IF_T::MCON
+ * Offset: 0x38, 0x98  IFn Message Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |DLC       |Data Length Code
+ * |        |          |0-8: Data Frame has 0-8 data bytes.
+ * |        |          |9-15: Data Frame has 8 data bytes
+ * |        |          |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
+ * |        |          |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
+ * |        |          |Data 0: 1st data byte of a CAN Data Frame
+ * |        |          |Data 1: 2nd data byte of a CAN Data Frame
+ * |        |          |Data 2: 3rd data byte of a CAN Data Frame
+ * |        |          |Data 3: 4th data byte of a CAN Data Frame
+ * |        |          |Data 4: 5th data byte of a CAN Data Frame
+ * |        |          |Data 5: 6th data byte of a CAN Data Frame
+ * |        |          |Data 6: 7th data byte of a CAN Data Frame
+ * |        |          |Data 7 : 8th data byte of a CAN Data Frame
+ * |        |          |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.
+ * |        |          |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
+ * |        |          |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
+ * |[7]     |EoB       |End Of Buffer
+ * |        |          |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
+ * |        |          |1 = Single Message Object or last Message Object of a FIFO Buffer.
+ * |        |          |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.
+ * |        |          |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
+ * |[8]     |TxRqst    |Transmit Request
+ * |        |          |0 = This Message Object is not waiting for transmission.
+ * |        |          |1 = The transmission of this Message Object is requested and is not yet done.
+ * |[9]     |RmtEn     |Remote Enable Control
+ * |        |          |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
+ * |        |          |1 = At the reception of a Remote Frame, TxRqst is set.
+ * |[10]    |RxIE      |Receive Interrupt Enable Control
+ * |        |          |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
+ * |        |          |1 = IntPnd will be set after a successful reception of a frame.
+ * |[11]    |TxIE      |Transmit Interrupt Enable Control
+ * |        |          |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
+ * |        |          |1 = IntPnd will be set after a successful transmission of a frame.
+ * |[12]    |UMask     |Use Acceptance Mask
+ * |        |          |0 = Mask ignored.
+ * |        |          |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
+ * |        |          |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
+ * |[13]    |IntPnd    |Interrupt Pending
+ * |        |          |0 = This message object is not the source of an interrupt.
+ * |        |          |1 = This message object is the source of an interrupt.
+ * |        |          |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
+ * |[14]    |MsgLst    |Message Lost (only valid for Message Objects with direction = receive).
+ * |        |          |0 = No message lost since last time this bit was reset by the CPU.
+ * |        |          |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
+ * |[15]    |NewDat    |New Data
+ * |        |          |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
+ * |        |          |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+ * @var CAN_IF_T::DAT_A1
+ * Offset: 0x3C, 0x9C  IFn Data A1 Register (Register Map Note 3)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |Data0     |Data Byte 0
+ * |        |          |1st data byte of a CAN Data Frame
+ * |[15:8]  |Data1     |Data Byte 1
+ * |        |          |2nd data byte of a CAN Data Frame
+ * @var CAN_IF_T::DAT_A2
+ * Offset: 0x40, 0xA0  IFn Data A2 Register (Register Map Note 3)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |Data2     |Data Byte 2
+ * |        |          |3rd data byte of CAN Data Frame
+ * |[15:8]  |Data3     |Data Byte 3
+ * |        |          |4th data byte of CAN Data Frame
+ * @var CAN_IF_T::DAT_B1
+ * Offset: 0x44, 0xA4  IFn Data B1 Register (Register Map Note 3)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |Data4     |Data Byte 4
+ * |        |          |5th data byte of CAN Data Frame
+ * |[15:8]  |Data5     |Data Byte 5
+ * |        |          |6th data byte of CAN Data Frame
+ * @var CAN_IF_T::DAT_B2
+ * Offset: 0x48, 0xA8  IFn Data B2 Register (Register Map Note 3)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |Data6     |Data Byte 6
+ * |        |          |7th data byte of CAN Data Frame.
+ * |[15:8]  |Data7     |Data Byte 7
+ * |        |          |8th data byte of CAN Data Frame.
+ */
+
+    __IO uint32_t CREQ;          /* Offset: 0x20, 0x80  IFn (Register Map Note 2) Command Request Registers          */
+    __IO uint32_t CMASK;         /* Offset: 0x24, 0x84  IFn Command Mask Register                                    */
+    __IO uint32_t MASK1;         /* Offset: 0x28, 0x88  IFn Mask 1 Register                                          */
+    __IO uint32_t MASK2;         /* Offset: 0x2C, 0x8C  IFn Mask 2 Register                                          */
+    __IO uint32_t ARB1;          /* Offset: 0x30, 0x90  IFn Arbitration 1 Register                                   */
+    __IO uint32_t ARB2;          /* Offset: 0x34, 0x94  IFn Arbitration 2 Register                                   */
+    __IO uint32_t MCON;          /* Offset: 0x38, 0x98  IFn Message Control Register                                 */
+    __IO uint32_t DAT_A1;        /* Offset: 0x3C, 0x9C  IFn Data A1 Register (Register Map Note 3)                   */
+    __IO uint32_t DAT_A2;        /* Offset: 0x40, 0xA0  IFn Data A2 Register (Register Map Note 3)                   */
+    __IO uint32_t DAT_B1;        /* Offset: 0x44, 0xA4  IFn Data B1 Register (Register Map Note 3)                   */
+    __IO uint32_t DAT_B2;        /* Offset: 0x48, 0xA8  IFn Data B2 Register (Register Map Note 3)                   */
+    __I  uint32_t RESERVE0[13];
+
+} CAN_IF_T;
+
+
+
+
+typedef struct
+{
+
+
+
+/**
+ * @var CAN_T::CON
+ * Offset: 0x00  Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |Init      |Init Initialization
+ * |        |          |0 = Normal Operation.
+ * |        |          |1 = Initialization is started.
+ * |[1]     |IE        |Module Interrupt Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[2]     |SIE       |Status Change Interrupt Enable Control
+ * |        |          |0 = Disabled - No Status Change Interrupt will be generated.
+ * |        |          |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
+ * |[3]     |EIE       |Error Interrupt Enable Control
+ * |        |          |0 = Disabled - No Error Status Interrupt will be generated.
+ * |        |          |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
+ * |[5]     |DAR       |Automatic Re-Transmission Disable Control
+ * |        |          |0 = Automatic Retransmission of disturbed messages enabled.
+ * |        |          |1 = Automatic Retransmission disabled.
+ * |[6]     |CCE       |Configuration Change Enable Control
+ * |        |          |0 = No write access to the Bit Timing Register.
+ * |        |          |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
+ * |[7]     |Test      |Test Mode Enable Control
+ * |        |          |0 = Normal Operation.
+ * |        |          |1 = Test Mode.
+ * @var CAN_T::STATUS
+ * Offset: 0x04  Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[2:0]   |LEC       |Last Error Code (Type Of The Last Error To Occur On The CAN Bus)
+ * |        |          |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.
+ * |        |          |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
+ * |        |          |The unused code '7' may be written by the CPU to check for updates.
+ * |        |          |The following table describes the error code.
+ * |[3]     |TxOK      |Transmitted A Message Successfully
+ * |        |          |0 = Since this bit was reset by the CPU, no message has been successfully transmitted.
+ * |        |          |This bit is never reset by the CAN Core.
+ * |        |          |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
+ * |[4]     |RxOK      |Received A Message Successfully
+ * |        |          |0 = No message has been successfully received since this bit was last reset by the CPU.
+ * |        |          |This bit is never reset by the CAN Core.
+ * |        |          |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
+ * |[5]     |EPass     |Error Passive (Read Only)
+ * |        |          |0 = The CAN Core is error active.
+ * |        |          |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
+ * |[6]     |EWarn     |Error Warning Status (Read Only)
+ * |        |          |0 = Both error counters are below the error warning limit of 96.
+ * |        |          |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
+ * |[7]     |BOff      |Bus-Off Status (Read Only)
+ * |        |          |0 = The CAN module is not in bus-off state.
+ * |        |          |1 = The CAN module is in bus-off state.
+ * @var CAN_T::ERR
+ * Offset: 0x08  Error Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |TEC       |Transmit Error Counter
+ * |        |          |Actual state of the Transmit Error Counter. Values between 0 and 255.
+ * |[14:8]  |REC       |Receive Error Counter
+ * |        |          |Actual state of the Receive Error Counter. Values between 0 and 127.
+ * |[15]    |RP        |Receive Error Passive
+ * |        |          |0 = The Receive Error Counter is below the error passive level.
+ * |        |          |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
+ * @var CAN_T::BTIME
+ * Offset: 0x0C  Bit Timing Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |BRP       |Baud Rate Prescaler
+ * |        |          |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.
+ * |        |          |The bit time is built up from a multiple of this quanta.
+ * |        |          |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].
+ * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+ * |[7:6]   |SJW       |(Re)Synchronization Jump Width
+ * |        |          |0x0-0x3: Valid programmed values are [0 ... 3].
+ * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+ * |[11:8]  |TSeg1     |Time Segment Before The Sample Point Minus Sync_Seg
+ * |        |          |0x01-0x0F: valid values for TSeg1 are [1 ... 15].
+ * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
+ * |[14:12] |TSeg2     |Time Segment After Sample Point
+ * |        |          |0x0-0x7: Valid values for TSeg2 are [0 ... 7].
+ * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+ * @var CAN_T::IIDR
+ * Offset: 0x10  Interrupt Identifier Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |IntId     |Interrupt Identifier (Indicates The Source Of The Interrupt)
+ * |        |          |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
+ * |        |          |An interrupt remains pending until the application software has cleared it.
+ * |        |          |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.
+ * |        |          |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
+ * |        |          |The Status Interrupt has the highest priority.
+ * |        |          |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
+ * |        |          |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).
+ * |        |          |The Status Interrupt is cleared by reading the Status Register.
+ * @var CAN_T::TEST
+ * Offset: 0x14  Test Register (Register Map Note 1)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |Res       |Reserved
+ * |        |          |There are reserved bits.
+ * |        |          |These bits are always read as '0' and must always be written with '0'.
+ * |[2]     |Basic     |Basic Mode
+ * |        |          |0 = Basic Mode disabled.
+ * |        |          |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
+ * |[3]     |Silent    |Silent Mode
+ * |        |          |0 = Normal operation.
+ * |        |          |1 = The module is in Silent Mode.
+ * |[4]     |LBack     |Loop Back Mode Enable Control
+ * |        |          |0 = Loop Back Mode is disabled.
+ * |        |          |1 = Loop Back Mode is enabled.
+ * |[6:5]   |Tx10      |Tx[1:0]: Control Of CAN_TX Pin
+ * |        |          |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
+ * |        |          |01 = Sample Point can be monitored at CAN_TX pin.
+ * |        |          |10 = CAN_TX pin drives a dominant ('0') value.
+ * |        |          |11 = CAN_TX pin drives a recessive ('1') value.
+ * |[7]     |Rx        |Monitors The Actual Value Of CAN_RX Pin (Read Only)
+ * |        |          |0 = The CAN bus is dominant (CAN_RX = '0').
+ * |        |          |1 = The CAN bus is recessive (CAN_RX = '1').
+ * @var CAN_T::BRPE
+ * Offset: 0x18  Baud Rate Prescaler Extension Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |BRPE      |BRPE: Baud Rate Prescaler Extension
+ * |        |          |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.
+ * |        |          |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
+ * @var CAN_T::IF
+ * Offset: 0x20~0xFC  CAN Interface Registers
+ * ---------------------------------------------------------------------------------------------------
+ * CAN interface structure. Refer to \ref CAN_IF_T for detail information.
+     *
+ * @var CAN_T::TXREQ1
+ * Offset: 0x100  Transmission Request Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects)
+ * |        |          |0 = This Message Object is not waiting for transmission.
+ * |        |          |1 = The transmission of this Message Object is requested and is not yet done.
+ * |        |          |These bits are read only.
+ * @var CAN_T::TXREQ2
+ * Offset: 0x104  Transmission Request Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects)
+ * |        |          |0 = This Message Object is not waiting for transmission.
+ * |        |          |1 = The transmission of this Message Object is requested and is not yet done.
+ * |        |          |These bits are read only.
+ * @var CAN_T::NDAT1
+ * Offset: 0x120  New Data Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects)
+ * |        |          |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
+ * |        |          |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+ * @var CAN_T::NDAT2
+ * Offset: 0x124  New Data Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects)
+ * |        |          |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
+ * |        |          |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+ * @var CAN_T::IPND1
+ * Offset: 0x140  Interrupt Pending Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects)
+ * |        |          |0 = This message object is not the source of an interrupt.
+ * |        |          |1 = This message object is the source of an interrupt.
+ * @var CAN_T::IPND2
+ * Offset: 0x144  Interrupt Pending Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects)
+ * |        |          |0 = This message object is not the source of an interrupt.
+ * |        |          |1 = This message object is the source of an interrupt.
+ * @var CAN_T::MVLD1
+ * Offset: 0x160  Message Valid Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only)
+ * |        |          |0 = This Message Object is ignored by the Message Handler.
+ * |        |          |1 = This Message Object is configured and should be considered by the Message Handler.
+ * |        |          |Ex.
+ * |        |          |CAN_MVLD1[0] means Message object No.1 is valid or not.
+ * |        |          |If CAN_MVLD1[0] is set, message object No.1 is configured.
+ * @var CAN_T::MVLD2
+ * Offset: 0x164  Message Valid Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)
+ * |        |          |0 = This Message Object is ignored by the Message Handler.
+ * |        |          |1 = This Message Object is configured and should be considered by the Message Handler.
+ * |        |          |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.
+ * |        |          |If CAN_MVLD2[15] is set, message object No.32 is configured.
+ * @var CAN_T::WU_EN
+ * Offset: 0x168  Wake-up Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |WAKUP_EN  |Wake-Up Enable Control
+ * |        |          |0 = The wake-up function Disabled.
+ * |        |          |1 = The wake-up function Enabled.
+ * |        |          |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
+ * @var CAN_T::WU_STATUS
+ * Offset: 0x16C  Wake-up Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |WAKUP_STS |Wake-Up Status
+ * |        |          |0 = No wake-up event occurred.
+ * |        |          |1 = Wake-up event occurred.
+ * |        |          |Note: This bit can be cleared by writing '0'.
+ */
+
+    __IO uint32_t CON;           /* Offset: 0x00  Control Register                                                   */
+    __IO uint32_t STATUS;        /* Offset: 0x04  Status Register                                                    */
+    __I  uint32_t ERR;           /* Offset: 0x08  Error Counter Register                                             */
+    __IO uint32_t BTIME;         /* Offset: 0x0C  Bit Timing Register                                                */
+    __I  uint32_t IIDR;          /* Offset: 0x10  Interrupt Identifier Register                                      */
+    __IO uint32_t TEST;          /* Offset: 0x14  Test Register (Register Map Note 1)                                */
+    __IO uint32_t BRPE;          /* Offset: 0x18  Baud Rate Prescaler Extension Register                             */
+    __I  uint32_t RESERVE0[1];  
+    __IO CAN_IF_T IF[2];         /* Offset: 0x20~0xFC  CAN Interface Registers                                       */
+    __I  uint32_t RESERVE1[8];  
+    __I  uint32_t TXREQ1;        /* Offset: 0x100  Transmission Request Register 1                                   */
+    __I  uint32_t TXREQ2;        /* Offset: 0x104  Transmission Request Register 2                                   */
+    __I  uint32_t RESERVE3[6];  
+    __I  uint32_t NDAT1;         /* Offset: 0x120  New Data Register 1                                               */
+    __I  uint32_t NDAT2;         /* Offset: 0x124  New Data Register 2                                               */
+    __I  uint32_t RESERVE4[6];  
+    __I  uint32_t IPND1;         /* Offset: 0x140  Interrupt Pending Register 1                                      */
+    __I  uint32_t IPND2;         /* Offset: 0x144  Interrupt Pending Register 2                                      */
+    __I  uint32_t RESERVE5[6];  
+    __I  uint32_t MVLD1;         /* Offset: 0x160  Message Valid Register 1                                          */
+    __I  uint32_t MVLD2;         /* Offset: 0x164  Message Valid Register 2                                          */
+    __IO uint32_t WU_EN;         /* Offset: 0x168  Wake-up Enable Register                                           */
+    __IO uint32_t WU_STATUS;     /* Offset: 0x16C  Wake-up Status Register                                           */
+
+} CAN_T;
+
+
+
+/**
+    @addtogroup CAN_CONST CAN Bit Field Definition
+    Constant Definitions for CAN Controller
+@{ */
+/* CAN CON Bit Field Definitions */
+#define CAN_CON_TEST_Pos           7                                    /*!< CAN_T::CON: TEST Position */
+#define CAN_CON_TEST_Msk           (0x1ul << CAN_CON_TEST_Pos)          /*!< CAN_T::CON: TEST Mask     */
+                                                                                
+#define CAN_CON_CCE_Pos            6                                    /*!< CAN_T::CON: CCE Position  */
+#define CAN_CON_CCE_Msk            (0x1ul << CAN_CON_CCE_Pos)           /*!< CAN_T::CON: CCE Mask      */
+                                                             
+#define CAN_CON_DAR_Pos            5                                    /*!< CAN_T::CON: DAR Position  */
+#define CAN_CON_DAR_Msk            (0x1ul << CAN_CON_DAR_Pos)           /*!< CAN_T::CON: DAR Mask      */
+                                                             
+#define CAN_CON_EIE_Pos            3                                    /*!< CAN_T::CON: EIE Position  */
+#define CAN_CON_EIE_Msk            (0x1ul << CAN_CON_EIE_Pos)           /*!< CAN_T::CON: EIE Mask      */
+                                                             
+#define CAN_CON_SIE_Pos            2                                    /*!< CAN_T::CON: SIE Position  */
+#define CAN_CON_SIE_Msk            (0x1ul << CAN_CON_SIE_Pos)           /*!< CAN_T::CON: SIE Mask      */
+                                                             
+#define CAN_CON_IE_Pos             1                                    /*!< CAN_T::CON: IE Position   */
+#define CAN_CON_IE_Msk             (0x1ul << CAN_CON_IE_Pos)            /*!< CAN_T::CON: IE Mask       */
+                                                             
+#define CAN_CON_INIT_Pos           0                                    /*!< CAN_T::CON: INIT Position */
+#define CAN_CON_INIT_Msk           (0x1ul << CAN_CON_INIT_Pos)          /*!< CAN_T::CON: INIT Mask     */
+
+/* CAN STATUS Bit Field Definitions */
+#define CAN_STATUS_BOFF_Pos        7                                    /*!< CAN_T::STATUS: BOFF Position  */
+#define CAN_STATUS_BOFF_Msk        (0x1ul << CAN_STATUS_BOFF_Pos)       /*!< CAN_T::STATUS: BOFF Mask      */
+
+#define CAN_STATUS_EWARN_Pos       6                                    /*!< CAN_T::STATUS: EWARN Position */
+#define CAN_STATUS_EWARN_Msk       (0x1ul << CAN_STATUS_EWARN_Pos)      /*!< CAN_T::STATUS: EWARN Mask     */
+
+#define CAN_STATUS_EPASS_Pos       5                                    /*!< CAN_T::STATUS: EPASS Position */
+#define CAN_STATUS_EPASS_Msk       (0x1ul << CAN_STATUS_EPASS_Pos)      /*!< CAN_T::STATUS: EPASS Mask     */
+
+#define CAN_STATUS_RXOK_Pos        4                                    /*!< CAN_T::STATUS: RXOK Position  */
+#define CAN_STATUS_RXOK_Msk        (0x1ul << CAN_STATUS_RXOK_Pos)       /*!< CAN_T::STATUS: RXOK Mask      */
+
+#define CAN_STATUS_TXOK_Pos        3                                    /*!< CAN_T::STATUS: TXOK Position  */
+#define CAN_STATUS_TXOK_Msk        (0x1ul << CAN_STATUS_TXOK_Pos)       /*!< CAN_T::STATUS: TXOK Mask      */
+
+#define CAN_STATUS_LEC_Pos         0                                    /*!< CAN_T::STATUS: LEC Position   */
+#define CAN_STATUS_LEC_Msk         (0x7ul << CAN_STATUS_LEC_Pos)        /*!< CAN_T::STATUS: LEC Mask       */
+
+/* CAN ERR Bit Field Definitions */                                             
+#define CAN_ERR_RP_Pos             15                                   /*!< CAN_T::ERR: RP Position       */
+#define CAN_ERR_RP_Msk             (0x1ul << CAN_ERR_RP_Pos)            /*!< CAN_T::ERR: RP Mask           */
+
+#define CAN_ERR_REC_Pos            8                                    /*!< CAN_T::ERR: REC Position      */
+#define CAN_ERR_REC_Msk            (0x7Ful << CAN_ERR_REC_Pos)          /*!< CAN_T::ERR: REC Mask          */
+
+#define CAN_ERR_TEC_Pos            0                                    /*!< CAN_T::ERR: TEC Position      */
+#define CAN_ERR_TEC_Msk            (0xFFul << CAN_ERR_TEC_Pos)          /*!< CAN_T::ERR: TEC Mask          */
+
+/* CAN BTIME Bit Field Definitions */                                           
+#define CAN_BTIME_TSEG2_Pos        12                                   /*!< CAN_T::BTIME: TSEG2 Position  */
+#define CAN_BTIME_TSEG2_Msk        (0x7ul << CAN_BTIME_TSEG2_Pos)       /*!< CAN_T::BTIME: TSEG2 Mask      */
+
+#define CAN_BTIME_TSEG1_Pos        8                                    /*!< CAN_T::BTIME: TSEG1 Position  */
+#define CAN_BTIME_TSEG1_Msk        (0xFul << CAN_BTIME_TSEG1_Pos)       /*!< CAN_T::BTIME: TSEG1 Mask      */
+
+#define CAN_BTIME_SJW_Pos          6                                    /*!< CAN_T::BTIME: SJW Position    */
+#define CAN_BTIME_SJW_Msk          (0x3ul << CAN_BTIME_SJW_Pos)         /*!< CAN_T::BTIME: SJW Mask        */
+
+#define CAN_BTIME_BRP_Pos          0                                    /*!< CAN_T::BTIME: BRP Position    */
+#define CAN_BTIME_BRP_Msk          (0x3Ful << CAN_BTIME_BRP_Pos)        /*!< CAN_T::BTIME: BRP Mask        */
+
+/* CAN IIDR Bit Field Definitions */                                            
+#define CAN_IIDR_INTID_Pos         0                                    /*!< CAN_T::IIDR: INTID Position   */
+#define CAN_IIDR_INTID_Msk         (0xFFFFul << CAN_IIDR_INTID_Pos)     /*!< CAN_T::IIDR: INTID Mask       */
+
+/* CAN TEST Bit Field Definitions */                                            
+#define CAN_TEST_RX_Pos            7                                    /*!< CAN_T::TEST: RX Position      */
+#define CAN_TEST_RX_Msk            (0x1ul << CAN_TEST_RX_Pos)           /*!< CAN_T::TEST: RX Mask          */
+
+#define CAN_TEST_TX_Pos            5                                    /*!< CAN_T::TEST: TX Position      */
+#define CAN_TEST_TX_Msk            (0x3ul << CAN_TEST_TX_Pos)           /*!< CAN_T::TEST: TX Mask          */
+
+#define CAN_TEST_LBACK_Pos         4                                    /*!< CAN_T::TEST: LBACK Position   */
+#define CAN_TEST_LBACK_Msk         (0x1ul << CAN_TEST_LBACK_Pos)        /*!< CAN_T::TEST: LBACK Mask       */
+
+#define CAN_TEST_SILENT_Pos        3                                    /*!< CAN_T::TEST: Silent Position  */
+#define CAN_TEST_SILENT_Msk        (0x1ul << CAN_TEST_SILENT_Pos)       /*!< CAN_T::TEST: Silent Mask      */
+
+#define CAN_TEST_BASIC_Pos         2                                    /*!< CAN_T::TEST: Basic Position   */
+#define CAN_TEST_BASIC_Msk         (0x1ul << CAN_TEST_BASIC_Pos)        /*!< CAN_T::TEST: Basic Mask       */
+
+/* CAN BPRE Bit Field Definitions */                                           
+#define CAN_BRPE_BRPE_Pos          0                                    /*!< CAN_T::BRPE: BRPE Position    */
+#define CAN_BRPE_BRPE_Msk          (0xFul << CAN_BRPE_BRPE_Pos)         /*!< CAN_T::BRPE: BRPE Mask        */
+
+/* CAN IFn_CREQ Bit Field Definitions */
+#define CAN_IF_CREQ_BUSY_Pos       15                                     /*!< CAN_IF_T::CREQ: BUSY Position */
+#define CAN_IF_CREQ_BUSY_Msk       (0x1ul << CAN_IF_CREQ_BUSY_Pos)        /*!< CAN_IF_T::CREQ: BUSY Mask     */
+                                                                                  
+#define CAN_IF_CREQ_MSGNUM_Pos     0                                      /*!< CAN_IF_T::CREQ: MSGNUM Position */
+#define CAN_IF_CREQ_MSGNUM_Msk     (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos)     /*!< CAN_IF_T::CREQ: MSGNUM Mask     */
+                                                                                  
+/* CAN IFn_CMASK Bit Field Definitions */                                         
+#define CAN_IF_CMASK_WRRD_Pos      7                                      /*!< CAN_IF_T::CMASK: WRRD Position */
+#define CAN_IF_CMASK_WRRD_Msk      (0x1ul << CAN_IF_CMASK_WRRD_Pos)       /*!< CAN_IF_T::CMASK: WRRD Mask     */
+                                                                                  
+#define CAN_IF_CMASK_MASK_Pos      6                                      /*!< CAN_IF_T::CMASK: MASK Position */
+#define CAN_IF_CMASK_MASK_Msk      (0x1ul << CAN_IF_CMASK_MASK_Pos)       /*!< CAN_IF_T::CMASK: MASK Mask     */
+                                                                                  
+#define CAN_IF_CMASK_ARB_Pos       5                                      /*!< CAN_IF_T::CMASK: ARB Position  */
+#define CAN_IF_CMASK_ARB_Msk       (0x1ul << CAN_IF_CMASK_ARB_Pos)        /*!< CAN_IF_T::CMASK: ARB Mask      */
+
+#define CAN_IF_CMASK_CONTROL_Pos   4                                     /*!< CAN_IF_T::CMASK: CONTROL Position */
+#define CAN_IF_CMASK_CONTROL_Msk   (0x1ul << CAN_IF_CMASK_CONTROL_Pos)   /*!< CAN_IF_T::CMASK: CONTROL Mask */
+
+#define CAN_IF_CMASK_CLRINTPND_Pos 3                                       /*!< CAN_IF_T::CMASK: CLRINTPND Position */
+#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos)   /*!< CAN_IF_T::CMASK: CLRINTPND Mask */
+
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2                                         /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos)  /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask     */
+
+#define CAN_IF_CMASK_DATAA_Pos     1                                    /*!< CAN_IF_T::CMASK: DATAA Position */
+#define CAN_IF_CMASK_DATAA_Msk     (0x1ul << CAN_IF_CMASK_DATAA_Pos)    /*!< CAN_IF_T::CMASK: DATAA Mask     */
+
+#define CAN_IF_CMASK_DATAB_Pos     0                                    /*!< CAN_IF_T::CMASK: DATAB Position */
+#define CAN_IF_CMASK_DATAB_Msk     (0x1ul << CAN_IF_CMASK_DATAB_Pos)    /*!< CAN_IF_T::CMASK: DATAB Mask     */
+
+/* CAN IFn_MASK1 Bit Field Definitions */
+#define CAN_IF_MASK1_MSK_Pos       0                                    /*!< CAN_IF_T::MASK1: MSK Position   */
+#define CAN_IF_MASK1_MSK_Msk       (0xFFul << CAN_IF_MASK1_MSK_Pos)     /*!< CAN_IF_T::MASK1: MSK Mask       */
+
+/* CAN IFn_MASK2 Bit Field Definitions */                                       
+#define CAN_IF_MASK2_MXTD_Pos      15                                   /*!< CAN_IF_T::MASK2: MXTD Position */
+#define CAN_IF_MASK2_MXTD_Msk      (0x1ul << CAN_IF_MASK2_MXTD_Pos)     /*!< CAN_IF_T::MASK2: MXTD Mask     */
+
+#define CAN_IF_MASK2_MDIR_Pos      14                                   /*!< CAN_IF_T::MASK2: MDIR Position */
+#define CAN_IF_MASK2_MDIR_Msk      (0x1ul << CAN_IF_MASK2_MDIR_Pos)     /*!< CAN_IF_T::MASK2: MDIR Mask     */
+
+#define CAN_IF_MASK2_MSK_Pos       0                                    /*!< CAN_IF_T::MASK2: MSK Position */
+#define CAN_IF_MASK2_MSK_Msk       (0x1FFul << CAN_IF_MASK2_MSK_Pos)    /*!< CAN_IF_T::MASK2: MSK Mask     */
+
+/* CAN IFn_ARB1 Bit Field Definitions */                                        
+#define CAN_IF_ARB1_ID_Pos         0                                    /*!< CAN_IF_T::ARB1: ID Position   */
+#define CAN_IF_ARB1_ID_Msk         (0xFFFFul << CAN_IF_ARB1_ID_Pos)     /*!< CAN_IF_T::ARB1: ID Mask       */
+
+/* CAN IFn_ARB2 Bit Field Definitions */                                        
+#define CAN_IF_ARB2_MSGVAL_Pos     15                                   /*!< CAN_IF_T::ARB2: MSGVAL Position */
+#define CAN_IF_ARB2_MSGVAL_Msk     (0x1ul << CAN_IF_ARB2_MSGVAL_Pos)    /*!< CAN_IF_T::ARB2: MSGVAL Mask     */
+
+#define CAN_IF_ARB2_XTD_Pos        14                                   /*!< CAN_IF_T::ARB2: XTD Position    */
+#define CAN_IF_ARB2_XTD_Msk        (0x1ul << CAN_IF_ARB2_XTD_Pos)       /*!< CAN_IF_T::ARB2: XTD Mask        */
+
+#define CAN_IF_ARB2_DIR_Pos        13                                   /*!< CAN_IF_T::ARB2: DIR Position    */
+#define CAN_IF_ARB2_DIR_Msk        (0x1ul << CAN_IF_ARB2_DIR_Pos)       /*!< CAN_IF_T::ARB2: DIR Mask        */
+
+#define CAN_IF_ARB2_ID_Pos         0                                    /*!< CAN_IF_T::ARB2: ID Position     */
+#define CAN_IF_ARB2_ID_Msk         (0x1FFFul << CAN_IF_ARB2_ID_Pos)     /*!< CAN_IF_T::ARB2: ID Mask         */
+
+/* CAN IFn_MCON Bit Field Definitions */                                        
+#define CAN_IF_MCON_NEWDAT_Pos     15                                   /*!< CAN_IF_T::MCON: NEWDAT Position */
+#define CAN_IF_MCON_NEWDAT_Msk     (0x1ul << CAN_IF_MCON_NEWDAT_Pos)    /*!< CAN_IF_T::MCON: NEWDAT Mask     */
+
+#define CAN_IF_MCON_MSGLST_Pos     14                                   /*!< CAN_IF_T::MCON: MSGLST Position */
+#define CAN_IF_MCON_MSGLST_Msk     (0x1ul << CAN_IF_MCON_MSGLST_Pos)    /*!< CAN_IF_T::MCON: MSGLST Mask     */
+
+#define CAN_IF_MCON_INTPND_Pos     13                                   /*!< CAN_IF_T::MCON: INTPND Position */
+#define CAN_IF_MCON_INTPND_Msk     (0x1ul << CAN_IF_MCON_INTPND_Pos)    /*!< CAN_IF_T::MCON: INTPND Mask     */
+
+#define CAN_IF_MCON_UMASK_Pos      12                                   /*!< CAN_IF_T::MCON: UMASK Position  */
+#define CAN_IF_MCON_UMASK_Msk      (0x1ul << CAN_IF_MCON_UMASK_Pos)     /*!< CAN_IF_T::MCON: UMASK Mask      */
+
+#define CAN_IF_MCON_TXIE_Pos       11                                   /*!< CAN_IF_T::MCON: TXIE Position   */
+#define CAN_IF_MCON_TXIE_Msk       (0x1ul << CAN_IF_MCON_TXIE_Pos)      /*!< CAN_IF_T::MCON: TXIE Mask       */
+
+#define CAN_IF_MCON_RXIE_Pos       10                                   /*!< CAN_IF_T::MCON: RXIE Position   */
+#define CAN_IF_MCON_RXIE_Msk       (0x1ul << CAN_IF_MCON_RXIE_Pos)      /*!< CAN_IF_T::MCON: RXIE Mask       */
+
+#define CAN_IF_MCON_RMTEN_Pos      9                                    /*!< CAN_IF_T::MCON: RMTEN Position  */
+#define CAN_IF_MCON_RMTEN_Msk      (0x1ul << CAN_IF_MCON_RMTEN_Pos)     /*!< CAN_IF_T::MCON: RMTEN Mask      */
+
+#define CAN_IF_MCON_TXRQST_Pos     8                                    /*!< CAN_IF_T::MCON: TXRQST Position */
+#define CAN_IF_MCON_TXRQST_Msk     (0x1ul << CAN_IF_MCON_TXRQST_Pos)    /*!< CAN_IF_T::MCON: TXRQST Mask     */
+
+#define CAN_IF_MCON_EOB_Pos        7                                    /*!< CAN_IF_T::MCON: EOB Position    */
+#define CAN_IF_MCON_EOB_Msk        (0x1ul << CAN_IF_MCON_EOB_Pos)       /*!< CAN_IF_T::MCON: EOB Mask        */
+
+#define CAN_IF_MCON_DLC_Pos        0                                    /*!< CAN_IF_T::MCON: DLC Position    */
+#define CAN_IF_MCON_DLC_Msk        (0xFul << CAN_IF_MCON_DLC_Pos)       /*!< CAN_IF_T::MCON: DLC Mask        */
+
+/* CAN IFn_DATA_A1 Bit Field Definitions */                                     
+#define CAN_IF_DAT_A1_DATA1_Pos    8                                    /*!< CAN_IF_T::DATAA1: DATA1 Position */
+#define CAN_IF_DAT_A1_DATA1_Msk    (0xFFul << CAN_IF_DAT_A1_DATA1_Pos)  /*!< CAN_IF_T::DATAA1: DATA1 Mask     */
+
+#define CAN_IF_DAT_A1_DATA0_Pos    0                                    /*!< CAN_IF_T::DATAA1: DATA0 Position */
+#define CAN_IF_DAT_A1_DATA0_Msk    (0xFFul << CAN_IF_DAT_A1_DATA0_Pos)  /*!< CAN_IF_T::DATAA1: DATA0 Mask     */
+
+/* CAN IFn_DATA_A2 Bit Field Definitions */                                     
+#define CAN_IF_DAT_A2_DATA3_Pos    8                                    /*!< CAN_IF_T::DATAA1: DATA3 Position */
+#define CAN_IF_DAT_A2_DATA3_Msk    (0xFFul << CAN_IF_DAT_A2_DATA3_Pos)  /*!< CAN_IF_T::DATAA1: DATA3 Mask     */
+
+#define CAN_IF_DAT_A2_DATA2_Pos    0                                    /*!< CAN_IF_T::DATAA1: DATA2 Position */
+#define CAN_IF_DAT_A2_DATA2_Msk    (0xFFul << CAN_IF_DAT_A2_DATA2_Pos)  /*!< CAN_IF_T::DATAA1: DATA2 Mask     */
+
+/* CAN IFn_DATA_B1 Bit Field Definitions */                                     
+#define CAN_IF_DAT_B1_DATA5_Pos    8                                    /*!< CAN_IF_T::DATAB1: DATA5 Position */
+#define CAN_IF_DAT_B1_DATA5_Msk    (0xFFul << CAN_IF_DAT_B1_DATA5_Pos)  /*!< CAN_IF_T::DATAB1: DATA5 Mask */
+
+#define CAN_IF_DAT_B1_DATA4_Pos    0                                    /*!< CAN_IF_T::DATAB1: DATA4 Position */
+#define CAN_IF_DAT_B1_DATA4_Msk    (0xFFul << CAN_IF_DAT_B1_DATA4_Pos)  /*!< CAN_IF_T::DATAB1: DATA4 Mask */
+
+/* CAN IFn_DATA_B2 Bit Field Definitions */                                     
+#define CAN_IF_DAT_B2_DATA7_Pos    8                                    /*!< CAN_IF_T::DATAB2: DATA7 Position */
+#define CAN_IF_DAT_B2_DATA7_Msk    (0xFFul << CAN_IF_DAT_B2_DATA7_Pos)  /*!< CAN_IF_T::DATAB2: DATA7 Mask     */
+
+#define CAN_IF_DAT_B2_DATA6_Pos    0                                    /*!< CAN_IF_T::DATAB2: DATA6 Position */
+#define CAN_IF_DAT_B2_DATA6_Msk    (0xFFul << CAN_IF_DAT_B2_DATA6_Pos)  /*!< CAN_IF_T::DATAB2: DATA6 Mask     */
+
+/* CAN IFn_TXRQST1 Bit Field Definitions */
+#define CAN_TXRQST1_TXRQST_Pos  0                                        /*!< CAN_T::TXRQST1: TXRQST Position */
+#define CAN_TXRQST1_TXRQST_Msk  (0xFFFFul << CAN_TXRQST1_TXRQST_Pos)  /*!< CAN_T::TXRQST1: TXRQST Mask     */
+
+/* CAN IFn_TXRQST2 Bit Field Definitions */                                         
+#define CAN_TXRQST2_TXRQST_Pos  0                                        /*!< CAN_T::TXRQST2: TXRQST Position  */
+#define CAN_TXRQST2_TXRQST_Msk  (0xFFFFul << CAN_TXRQST2_TXRQST_Pos)  /*!< CAN_T::TXRQST2: TXRQST Mask      */
+
+/* CAN IFn_NDAT1 Bit Field Definitions */                                           
+#define CAN_NDAT1_NEWDATA_Pos   0                                        /*!< CAN_T::NDAT1: NEWDATA Position */
+#define CAN_NDAT1_NEWDATA_Msk   (0xFFFFul << CAN_NDAT1_NEWDATA_Pos)   /*!< CAN_T::NDAT1: NEWDATA Mask     */
+
+/* CAN IFn_NDAT2 Bit Field Definitions */                                          
+#define CAN_NDAT2_NEWDATA_Pos   0                                        /*!< CAN_T::NDAT2: NEWDATA Position */
+#define CAN_NDAT2_NEWDATA_Msk   (0xFFFFul << CAN_NDAT2_NEWDATA_Pos)   /*!< CAN_T::NDAT2: NEWDATA Mask     */
+
+/* CAN IFn_IPND1 Bit Field Definitions */                                          
+#define CAN_IPND1_INTPND_Pos   0                                         /*!< CAN_T::IPND1: INTPND Position */
+#define CAN_IPND1_INTPND_Msk   (0xFFFFul << CAN_IPND1_INTPND_Pos)     /*!< CAN_T::IPND1: INTPND Mask     */
+
+/* CAN IFn_IPND2 Bit Field Definitions */                                          
+#define CAN_IPND2_INTPND_Pos   0                                         /*!< CAN_T::IPND2: INTPND Position */
+#define CAN_IPND2_INTPND_Msk   (0xFFFFul << CAN_IPND2_INTPND_Pos)     /*!< CAN_T::IPND2: INTPND Mask     */
+
+/* CAN IFn_MVLD1 Bit Field Definitions */                                          
+#define CAN_MVLD1_MSGVAL_Pos   0                                         /*!< CAN_T::MVLD1: MSGVAL Position */
+#define CAN_MVLD1_MSGVAL_Msk   (0xFFFFul << CAN_MVLD1_MSGVAL_Pos)     /*!< CAN_T::MVLD1: MSGVAL Mask     */
+
+/* CAN IFn_MVLD2 Bit Field Definitions */                                           
+#define CAN_MVLD2_MSGVAL_Pos   0                                         /*!< CAN_T::MVLD2: MSGVAL Position */
+#define CAN_MVLD2_MSGVAL_Msk   (0xFFFFul << CAN_MVLD2_MSGVAL_Pos)     /*!< CAN_T::MVLD2: MSGVAL Mask     */
+
+/* CAN WUEN Bit Field Definitions */                                                
+#define CAN_WUEN_WAKUP_EN_Pos     0                                         /*!< CAN_T::WU_EN: WAKUP_EN Position */
+#define CAN_WUEN_WAKUP_EN_Msk    (0x1ul << CAN_WUEN_WAKUP_EN_Pos)           /*!< CAN_T::WU_EN: WAKUP_EN Mask     */
+
+/* CAN WUSTATUS Bit Field Definitions */
+#define CAN_WUSTATUS_WAKUP_STS_Pos     0                                      /*!< CAN_T::WU_STATUS: WAKUP_STS Position */
+#define CAN_WUSTATUS_WAKUP_STS_Msk    (0x1ul << CAN_WUSTATUS_WAKUP_STS_Pos)   /*!< CAN_T::WU_STATUS: WAKUP_STS Mask     */
+
+
+/**@}*/ /* CAN_CONST */
+/**@}*/ /* end of CAN register group */
+
+
+/*---------------------- System Clock Controller -------------------------*/
+/**
+    @addtogroup CLK System Clock Controller(CLK)
+    Memory Mapped Structure for CLK Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var CLK_T::PWRCTL
+ * Offset: 0x00  System Power-down Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |HXTEN     |External 4~24 MHz High-Speed Crystal Enable Bit (Write Protect)
+ * |        |          |The bit default value is set by flash controller user configuration register CONFIG0 [26:24].
+ * |        |          |When the default clock source is from external 4~24 MHz high-speed crystal, this bit is set to 1 automatically.
+ * |        |          |0 = External 4 ~ 24 MHz high speed crystal oscillator (HXT) Disabled.
+ * |        |          |1 = External 4 MH~ 24 z high speed crystal oscillator (HXT) Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1]     |LXTEN     |External 32.768 KHz Low-Speed Crystal Enable Bit (Write Protect)
+ * |        |          |0 = External 32.768 kHz low-speed crystal oscillator (LXT) Disabled.
+ * |        |          |1 = External 32.768 kHz low-speed crystal oscillator (LXT) Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2]     |HIRCEN    |Internal 22.1184 MHz High-Speed Oscillator Enable Bit (Write Protect)
+ * |        |          |0 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Disabled.
+ * |        |          |1 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3]     |LIRCEN    |Internal 10 KHz Low-Speed Oscillator Enable Bit (Write Protect)
+ * |        |          |0 = Internal 10 kHz low speed RC oscillator (LIRC) Disabled.
+ * |        |          |1 = Internal 10 kHz low speed RC oscillator (LIRC) Enabled.
+ * |[4]     |PDWKDLY   |Enable The Wake-Up Delay Counter (Write Protect)
+ * |        |          |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
+ * |        |          |The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high-speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high-speed oscillator.
+ * |        |          |0 = Clock cycles delay Disabled.
+ * |        |          |1 = Clock cycles delay Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5]     |PDWKIEN   |Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)
+ * |        |          |0 = Power-down Mode Wake-up Interrupt Disabled.
+ * |        |          |1 = Power-down Mode Wake-up Interrupt Enabled.
+ * |        |          |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
+ * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6]     |PDWKIF    |Power-Down Mode Wake-Up Interrupt Status
+ * |        |          |Set by "Power-down wake-up event", it indicates that resume from Power-down mode
+ * |        |          |The flag is set if the EINT0~5, GPIO, USBH, USBD, OTG, UART0~3, WDT, CAN0, ACMP01, BOD, RTC, TMR0~3, I2C0~1 or TK wake-up occurred.
+ * |        |          |Note1: Write 1 to clear the bit to 0.
+ * |        |          |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
+ * |[7]     |PDEN      |System Power-Down Enable (Write Protect)
+ * |        |          |When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit.
+ * |        |          |(a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set.(default)
+ * |        |          |(b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
+ * |        |          |When chip wakes up from Power-down mode, this bit is auto cleared.
+ * |        |          |Users need to set this bit again for next Power-down.
+ * |        |          |In Power-down mode, external 4~24 MHz high-speed crystal and the internal 22.1184 MHz high-speed oscillator will be disabled in this mode, but the external 32.768 kHz low-speed crystal and internal 10 kHz low-speed oscillator are not controlled by Power-down mode.
+ * |        |          |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection.
+ * |        |          |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from external 32.768 kHz low-speed crystal or the internal 10 kHz low-speed oscillator.
+ * |        |          |0 = Chip operating normally or chip in idle mode because of WFI command.
+ * |        |          |1 = Chip enters Power-down mode instant or wait CPU sleep command WFI.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[8]     |PDWTCPU   |This Bit Control The Power-Down Entry Condition (Write Protect)
+ * |        |          |0 = Chip enters Power-down mode when the PDEN bit is set to 1.
+ * |        |          |1 = Chip enters Power-down mode when the both PDWTCPU and PDEN bits are set to 1 and CPU run WFI instruction.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[11:10] |HXTGAIN   |4~24 MHz High-Speed Crystal Gain Control Bit
+ * |        |          |(Write Protect)
+ * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+ * |        |          |Gain control is used to enlarge the gain of crystal to make sure crystal work normally.
+ * |        |          |If gain control is enabled, crystal will consume more power than gain control off.
+ * |        |          |00 = HXT frequency is lower than from 8 MHz.
+ * |        |          |01 = HXT frequency is from 8 MHz to 12 MHz.
+ * |        |          |10 = HXT frequency is from 12 MHz to 16 MHz.
+ * |        |          |11 = HXT frequency is higher than 16 MHz.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[12]    |HXTSELTYP |4~24 MHz High-Speed Crystal Type Select Bit (Write Protect)
+ * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+ * |        |          |0 = Select INV type.
+ * |        |          |1 = Select GM type.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var CLK_T::AHBCLK
+ * Offset: 0x04  AHB Devices Clock Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1]     |PDMACKEN  |PDMA Controller Clock Enable Bit
+ * |        |          |0 = PDMA peripheral clock Disabled.
+ * |        |          |1 = PDMA peripheral clock Enabled.
+ * |[2]     |ISPCKEN   |Flash ISP Controller Clock Enable Bit
+ * |        |          |0 = Flash ISP peripheral clock Disabled.
+ * |        |          |1 = Flash ISP peripheral clock Enabled.
+ * |[3]     |EBICKEN   |EBI Controller Clock Enable Bit
+ * |        |          |0 = EBI peripheral clock Disabled.
+ * |        |          |1 = EBI peripheral clock Enabled.
+ * |[4]     |USBHCKEN  |USB HOST Controller Clock Enable Bit
+ * |        |          |0 = USB HOST peripheral clock Disabled.
+ * |        |          |1 = USB HOST peripheral clock Enabled.
+ * |[7]     |CRCCKEN   |CRC Generator Controller Clock Enable Bit
+ * |        |          |0 = CRC peripheral clock Disabled.
+ * |        |          |1 = CRC peripheral clock Enabled.
+ * |[15]    |FMCIDLE   |Flash Memory Controller Clock Enable Bit In IDLE Mode
+ * |        |          |0 = FMC peripheral clock Disabled when chip operating at IDLE mode.
+ * |        |          |1 = FMC peripheral clock Enabled when chip operating at IDLE mode.
+ * @var CLK_T::APBCLK0
+ * Offset: 0x08  APB Devices Clock Enable Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |WDTCKEN   |Watchdog Timer Clock Enable Bit (Write Protect)
+ * |        |          |0 = Watchdog Timer Clock Disabled.
+ * |        |          |1 = Watchdog Timer Clock Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1]     |RTCCKEN   |Real-Time-Clock APB Interface Clock Enable Bit
+ * |        |          |This bit is used to control the RTC APB clock only.
+ * |        |          |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]).
+ * |        |          |It can be selected to external 32.768 kHz low speed crystal or internal 10 kHz low speed oscillator.
+ * |        |          |0 = RTC Clock Disabled.
+ * |        |          |1 = RTC Clock Enabled.
+ * |[2]     |TMR0CKEN  |Timer0 Clock Enable Bit
+ * |        |          |0 = Timer0 Clock Disabled.
+ * |        |          |1 = Timer0 Clock Enabled.
+ * |[3]     |TMR1CKEN  |Timer1 Clock Enable Bit
+ * |        |          |0 = Timer1 Clock Disabled.
+ * |        |          |1 = Timer1 Clock Enabled.
+ * |[4]     |TMR2CKEN  |Timer2 Clock Enable Bit
+ * |        |          |0 = Timer2 Clock Disabled.
+ * |        |          |1 = Timer2 Clock Enabled.
+ * |[5]     |TMR3CKEN  |Timer3 Clock Enable Bit
+ * |        |          |0 = Timer3 Clock Disabled.
+ * |        |          |1 = Timer3 Clock Enabled.
+ * |[6]     |CLKOCKEN  |CLKO Clock Enable Bit
+ * |        |          |0 = CLKO Clock Disabled.
+ * |        |          |1 = CLKO Clock Enabled.
+ * |[7]     |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit
+ * |        |          |0 = Analog Comparator 0/1 Clock Disabled.
+ * |        |          |1 = Analog Comparator 0/1 Clock Enabled.
+ * |[8]     |I2C0CKEN  |I2C0 Clock Enable Bit
+ * |        |          |0 = I2C0 Clock Disabled.
+ * |        |          |1 = I2C0 Clock Enabled.
+ * |[9]     |I2C1CKEN  |I2C1 Clock Enable Bit
+ * |        |          |0 = I2C1 Clock Disabled.
+ * |        |          |1 = I2C1 Clock Enabled.
+ * |[12]    |SPI0CKEN  |SPI0 Clock Enable Bit
+ * |        |          |0 = SPI0 Clock Disabled.
+ * |        |          |1 = SPI0 Clock Enabled.
+ * |[13]    |SPI1CKEN  |SPI1 Clock Enable Bit
+ * |        |          |0 = SPI1 Clock Disabled.
+ * |        |          |1 = SPI1 Clock Enabled.
+ * |[14]    |SPI2CKEN  |SPI2 Clock Enable Bit
+ * |        |          |0 = SPI2 Clock Disabled.
+ * |        |          |1 = SPI2 Clock Enabled.
+ * |[16]    |UART0CKEN |UART0 Clock Enable Bit
+ * |        |          |0 = UART0 clock Disabled.
+ * |        |          |1 = UART0 clock Enabled.
+ * |[17]    |UART1CKEN |UART1 Clock Enable Bit
+ * |        |          |0 = UART1 clock Disabled.
+ * |        |          |1 = UART1 clock Enabled.
+ * |[18]    |UART2CKEN |UART2 Clock Enable Bit
+ * |        |          |0 = UART2 clock Disabled.
+ * |        |          |1 = UART2 clock Enabled.
+ * |[19]    |UART3CKEN |UART3 Clock Enable Bit
+ * |        |          |0 = UART3 clock Disabled.
+ * |        |          |1 = UART3 clock Enabled.
+ * |[24]    |CAN0CKEN  |CAN0 Clock Enable Bit
+ * |        |          |0 = CAN0 clock Disabled.
+ * |        |          |1 = CAN0 clock Enabled.
+ * |[26]    |OTGCKEN   |USB OTG Clock Enable Bit
+ * |        |          |0 = USB OTG clock Disabled.
+ * |        |          |1 = USB OTG clock Enabled.
+ * |[27]    |USBDCKEN  |USB Device Clock Enable Bit
+ * |        |          |0 = USB Device clock Disabled.
+ * |        |          |1 = USB Device clock Enabled.
+ * |[28]    |EADCCKEN  |Enhanced Analog-Digital-Converter (EADC) Clock Enable Bit
+ * |        |          |0 = EADC clock Disabled.
+ * |        |          |1 = EADC clock Enabled.
+ * @var CLK_T::APBCLK1
+ * Offset: 0x0C  APB Devices Clock Enable Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SC0CKEN   |SC0 Clock Enable Bit
+ * |        |          |0 = SC0 Clock Disabled.
+ * |        |          |1 = SC0 Clock Enabled.
+ * |[12]    |DACCKEN   |DAC Clock Enable Bit
+ * |        |          |0 = DAC Clock Disabled.
+ * |        |          |1 = DAC Clock Enabled.
+ * |[16]    |PWM0CKEN  |PWM0 Clock Enable Bit
+ * |        |          |0 = PWM0 Clock Disabled.
+ * |        |          |1 = PWM0 Clock Enabled.
+ * |[17]    |PWM1CKEN  |PWM1 Clock Enable Bit
+ * |        |          |0 = PWM1 Clock Disabled.
+ * |        |          |1 = PWM1 Clock Enabled.
+ * |[25]    |TKCKEN    |Touch Key Clock Enable Bit
+ * |        |          |0 = Touch Key Clock Disabled.
+ * |        |          |1 = Touch key Clock Enabled.
+ * @var CLK_T::CLKSEL0
+ * Offset: 0x10  Clock Source Select Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[2:0]   |HCLKSEL   |HCLK Clock Source Selection (Write Protect)
+ * |        |          |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
+ * |        |          |The default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset.
+ * |        |          |Therefore the default value is either 000b or 111b.
+ * |        |          |000 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * |        |          |001 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * |        |          |010 = Clock source from PLL clock.
+ * |        |          |011 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * |        |          |111= Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * |        |          |Other = Reserved.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5:3]   |STCLKSEL  |Cortex-M4 SysTick Clock Source Selection (Write Protect)
+ * |        |          |If SYST_CTRL[2]=0, SysTick uses listed clock source below.
+ * |        |          |000 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * |        |          |001 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * |        |          |010 = Clock source from external 4~24 MHz high-speed crystal clock/2.
+ * |        |          |011 = Clock source from HCLK/2.
+ * |        |          |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock/2.
+ * |        |          |Note: if SysTick clock source is not from HCLK (i.e.
+ * |        |          |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6]     |PCLK0SEL  |PCLK0 Clock Source Selection (Write Protect)
+ * |        |          |0 = APB0 BUS clock source from HCLK.
+ * |        |          |1 = APB0 BUS clock source from HCLK/2.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7]     |PCLK1SEL  |PCLK1 Clock Source Selection (Write Protect)
+ * |        |          |0 = APB1 BUS clock source from HCLK.
+ * |        |          |1 = APB1 BUS clock source from HCLK/2.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var CLK_T::CLKSEL1
+ * Offset: 0x14  Clock Source Select Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |WDTSEL    |Watchdog Timer Clock Source Selection (Write Protect)
+ * |        |          |00 = Reserved.
+ * |        |          |01 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * |        |          |10 = Clock source from PCLK0/2048 clock.
+ * |        |          |11 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * |[10:8]  |TMR0SEL   |TIMER0 Clock Source Selection
+ * |        |          |000 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * |        |          |001 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * |        |          |010 = Clock source from PCLK0.
+ * |        |          |011 = Clock source from external clock T0 pin
+ * |        |          |101 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * |        |          |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * |        |          |Others = Reserved.
+ * |[14:12] |TMR1SEL   |TIMER1 Clock Source Selection
+ * |        |          |000 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * |        |          |001 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * |        |          |010 = Clock source from PCLK0.
+ * |        |          |011 = Clock source from external clock T1 pin
+ * |        |          |101 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * |        |          |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * |        |          |Others = Reserved.
+ * |[18:16] |TMR2SEL   |TIMER2 Clock Source Selection
+ * |        |          |000 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * |        |          |001 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * |        |          |010 = Clock source from PCLK1.
+ * |        |          |011 = Clock source from external clock T2 pin
+ * |        |          |101 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * |        |          |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * |        |          |Others = Reserved.
+ * |[22:20] |TMR3SEL   |TIMER3 Clock Source Selection
+ * |        |          |000 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * |        |          |001 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * |        |          |010 = Clock source from PCLK1.
+ * |        |          |011 = Clock source from external clock T3 pin.
+ * |        |          |101 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * |        |          |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * |        |          |Others = Reserved.
+ * |[25:24] |UARTSEL   |UART Clock Source Selection
+ * |        |          |00 = Clock source from external 4~24 MHz high-speed crystal clock (HXT).
+ * |        |          |01 = Clock source from PLL clock.
+ * |        |          |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * |        |          |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock (HIRC).
+ * |[29:28] |CLKOSEL   |Clock Divider Clock Source Selection
+ * |        |          |00 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * |        |          |01 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * |        |          |10 = Clock source from HCLK.
+ * |        |          |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * |[31:30] |WWDTSEL   |Window Watchdog Timer Clock Source Selection
+ * |        |          |10 = Clock source from PCLK0/2048 clock.
+ * |        |          |11 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * |        |          |Others = Reserved.
+ * @var CLK_T::CLKSEL2
+ * Offset: 0x18  Clock Source Select Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |PWM0SEL   |PWM0 Clock Source Selection
+ * |        |          |The peripheral clock source of PWM0 is defined by PWM0SEL.
+ * |        |          |0 = Clock source from PLL clock.
+ * |        |          |1 = Clock source from PCLK0.
+ * |[1]     |PWM1SEL   |PWM1 Clock Source Selection
+ * |        |          |The peripheral clock source of PWM1 is defined by PWM1SEL.
+ * |        |          |0 = Clock source from PLL clock.
+ * |        |          |1 = Clock source from PCLK1.
+ * |[3:2]   |SPI0SEL   |SPI0 Clock Source Selection
+ * |        |          |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
+ * |        |          |01 = Clock source from PLL clock.
+ * |        |          |10 = Clock source from PCLK0.
+ * |        |          |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
+ * |[5:4]   |SPI1SEL   |SPI1 Clock Source Selection
+ * |        |          |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
+ * |        |          |01 = Clock source from PLL clock.
+ * |        |          |10 = Clock source from PCLK1.
+ * |        |          |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
+ * |[7:6]   |SPI2SEL   |SPI2 Clock Source Selection
+ * |        |          |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
+ * |        |          |01 = Clock source from PLL clock.
+ * |        |          |10 = Clock source from PCLK0.
+ * |        |          |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
+ * @var CLK_T::CLKSEL3
+ * Offset: 0x1C  Clock Source Select Control Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |SC0SEL    |SC0 Clock Source Selection
+ * |        |          |00 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * |        |          |01 = Clock source from PLL clock.
+ * |        |          |10 = Clock source from PCLK0.
+ * |        |          |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * |[8]     |RTCSEL    |RTC Clock Source Selection
+ * |        |          |0 = Clock source from external 32.768 kHz low-speed oscillator.
+ * |        |          |1 = Clock source from internal 10 kHz low speed RC oscillator.
+ * @var CLK_T::CLKDIV0
+ * Offset: 0x20  Clock Divider Number Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |HCLKDIV   |HCLK Clock Divide Number From HCLK Clock Source
+ * |        |          |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
+ * |[7:4]   |USBDIV    |USB Clock Divide Number From PLL Clock
+ * |        |          |USB clock frequency = (PLL frequency) / (USBDIV + 1).
+ * |[11:8]  |UARTDIV   |UART Clock Divide Number From UART Clock Source
+ * |        |          |UART clock frequency = (UART clock source frequency) / (UARTDIV + 1).
+ * |[23:16] |EADCDIV   |EADC Clock Divide Number From EADC Clock Source
+ * |        |          |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
+ * @var CLK_T::CLKDIV1
+ * Offset: 0x24  Clock Divider Number Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |SC0DIV    |SC0 Clock Divide Number From SC0 Clock Source
+ * |        |          |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1).
+ * @var CLK_T::PLLCTL
+ * Offset: 0x40  PLL Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[8:0]   |FBDIV     |PLL Feedback Divider Control Pins (Write Protect)
+ * |        |          |Refer to the formulas below the table.
+ * |[13:9]  |INDIV     |PLL Input Divider Control Pins (Write Protect)
+ * |        |          |Refer to the formulas below the table.
+ * |[15:14] |OUTDIV    |PLL Output Divider Control Pins (Write Protect)
+ * |        |          |Refer to the formulas below the table.
+ * |[16]    |PD        |Power-Down Mode (Write Protect)
+ * |        |          |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
+ * |        |          |0 = PLL is in normal mode.
+ * |        |          |1 = PLL is in Power-down mode (default).
+ * |[17]    |BP        |PLL Bypass Control (Write Protect)
+ * |        |          |0 = PLL is in normal mode (default).
+ * |        |          |1 = PLL clock output is same as PLL input clock FIN.
+ * |[18]    |OE        |PLL OE (FOUT Enable) Pin Control (Write Protect)
+ * |        |          |0 = PLL FOUT Enabled.
+ * |        |          |1 = PLL FOUT is fixed low.
+ * |[19]    |PLLSRC    |PLL Source Clock Selection (Write Protect)
+ * |        |          |0 = PLL source clock from external 4~24 MHz high-speed crystal (HXT).
+ * |        |          |1 = PLL source clock from internal 22.1184 MHz high-speed oscillator (HIRC).
+ * |[23]    |STBSEL    |PLL Stable Counter Selection (Write Protect)
+ * |        |          |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12MHz).
+ * |        |          |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12MHz).
+ * @var CLK_T::STATUS
+ * Offset: 0x50  Clock Status Monitor Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |HXTSTB    |External 4~24 MHz High-Speed Crystal Clock Source Stable Flag (Read Only)
+ * |        |          |0 = External 4~24 MHz high-speed crystal clock is not stable or disabled.
+ * |        |          |1 = External 4~24 MHz high-speed crystal clock is stable and enabled.
+ * |[1]     |LXTSTB    |External 32.768 kHz Low-Speed Crystal Clock Source Stable Flag (Read Only)
+ * |        |          |0 = External 32.768 kHz low-speed crystal clock is not stable or disabled.
+ * |        |          |1 = External 32.768 kHz low-speed crystal clock is stabled and enabled.
+ * |[2]     |PLLSTB    |Internal PLL Clock Source Stable Flag (Read Only)
+ * |        |          |0 = Internal PLL clock is not stable or disabled.
+ * |        |          |1 = Internal PLL clock is stable and enabled.
+ * |[3]     |LIRCSTB   |Internal 10 KHz Low-Speed Oscillator Clock Source Stable Flag (Read Only)
+ * |        |          |0 = Internal 10 kHz low-speed oscillator clock is not stable or disabled.
+ * |        |          |1 = Internal 10 kHz low-speed oscillator clock is stable and enabled.
+ * |[4]     |HIRCSTB   |Internal 22.1184 MHz High-Speed Oscillator Clock Source Stable Flag (Read Only)
+ * |        |          |0 = Internal 22.1184 MHz high-speed oscillator clock is not stable or disabled.
+ * |        |          |1 = Internal 22.1184 MHz high-speed oscillator clock is stable and enabled.
+ * |[7]     |CLKSFAIL  |Clock Switching Fail Flag (Read Only)
+ * |        |          |This bit is updated when software switches system clock source.
+ * |        |          |If switch target clock is stable, this bit will be set to 0.
+ * |        |          |If switch target clock is not stable, this bit will be set to 1.
+ * |        |          |0 = Clock switching success.
+ * |        |          |1 = Clock switching failure.
+ * |        |          |Note: Write 1 to clear the bit to 0.
+ * @var CLK_T::CLKOCTL
+ * Offset: 0x60  Clock Output Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |FREQSEL   |Clock Output Frequency Selection
+ * |        |          |The formula of output frequency is
+ * |        |          |Fout = Fin/2(N+1).
+ * |        |          |Fin is the input clock frequency.
+ * |        |          |Fout is the frequency of divider output clock.
+ * |        |          |N is the 4-bit value of FREQSEL[3:0].
+ * |[4]     |CLKOEN    |Clock Output Enable Bit
+ * |        |          |0 =Clock Output function Disabled.
+ * |        |          |1 = Clock Output function Enabled.
+ * |[5]     |DIV1EN    |Clock Output Divide One Enable Bit
+ * |        |          |0 = Clock Output will output clock with source frequency divided by FREQSEL.
+ * |        |          |1 = Clock Output will output clock with source frequency.
+ * |[6]     |CLK1HZEN  |Clock Output 1Hz Enable Bit
+ * |        |          |0 = 1 Hz clock output for 32.768kHz frequency compensation Disabled.
+ * |        |          |1 = 1 Hz clock output for 332.768kHz frequency compensation Enabled.
+ * @var CLK_T::CLKDCTL
+ * Offset: 0x70  Clock Fail Detector Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[4]     |HXTFDEN   |HXT Clock Fail Detector Enable Bit
+ * |        |          |0 = HXT clock Fail detector Disabled.
+ * |        |          |1 = HXT clock Fail detector Enabled.
+ * |[5]     |HXTFIEN   |HXT Clock Fail Interrupt Enable Bit
+ * |        |          |0 = HXT clock Fail interrupt Disabled.
+ * |        |          |1 = HXT clock Fail interrupt Enabled.
+ * |[12]    |LXTFDEN   |LXT Clock Fail Detector Enable Bit
+ * |        |          |0 = LXT clock Fail detector Disabled.
+ * |        |          |1 = LXT clock Fail detector Enabled.
+ * |[13]    |LXTFIEN   |LXT Clock Fail Interrupt Enable Bit
+ * |        |          |0 = LXT clock Fail interrupt Disabled.
+ * |        |          |1 = LXT clock Fail interrupt Enabled.
+ * |[16]    |HXTFQDEN  |HXT Clock Frequency Monitor Enable Bit
+ * |        |          |0 = HXT clock frequency monitor Disabled.
+ * |        |          |1 = HXT clock frequency monitor Enabled.
+ * |[17]    |HXTFQIEN  |HXT Clock Frequency Monitor Interrupt Enable Bit
+ * |        |          |0 = HXT clock frequency monitor fail interrupt Disabled.
+ * |        |          |1 = HXT clock frequency monitor fail interrupt Enabled.
+ * @var CLK_T::CLKDSTS
+ * Offset: 0x74  Clock Fail Detector Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |HXTFIF    |HXT Clock Fail Interrupt Flag
+ * |        |          |0 = HXT clock normal.
+ * |        |          |1 = HXT clock stop
+ * |        |          |Note: Write 1 to clear the bit to 0.
+ * |[1]     |LXTFIF    |LXT Clock Fail Interrupt Flag
+ * |        |          |0 = LXT clock normal.
+ * |        |          |1 = LXT stop
+ * |        |          |Note: Write 1 to clear the bit to 0.
+ * |[8]     |HXTFQIF   |HXT Clock Frequency Monitor Interrupt Flag
+ * |        |          |0 = HXT clock normal.
+ * |        |          |1 = HXT clock frequency abnormal
+ * |        |          |Note: Write 1 to clear the bit to 0.
+ * @var CLK_T::CDUPB
+ * Offset: 0x78  Clock Frequency Detector Upper Boundary Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[9:0]   |UPERBD    |HXT Clock Frequency Detector Upper Boundary
+ * |        |          |The bits define the high value of frequency monitor window.
+ * |        |          |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.
+ * @var CLK_T::CDLOWB
+ * Offset: 0x7C  Clock Frequency Detector Low Boundary Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[9:0]   |LOWERBD   |HXT Clock Frequency Detector Low Boundary
+ * |        |          |The bits define the low value of frequency monitor window.
+ * |        |          |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1.
+ */
+
+    __IO uint32_t PWRCTL;        /* Offset: 0x00  System Power-down Control Register                                 */
+    __IO uint32_t AHBCLK;        /* Offset: 0x04  AHB Devices Clock Enable Control Register                          */
+    __IO uint32_t APBCLK0;       /* Offset: 0x08  APB Devices Clock Enable Control Register 0                        */
+    __IO uint32_t APBCLK1;       /* Offset: 0x0C  APB Devices Clock Enable Control Register 1                        */
+    __IO uint32_t CLKSEL0;       /* Offset: 0x10  Clock Source Select Control Register 0                             */
+    __IO uint32_t CLKSEL1;       /* Offset: 0x14  Clock Source Select Control Register 1                             */
+    __IO uint32_t CLKSEL2;       /* Offset: 0x18  Clock Source Select Control Register 2                             */
+    __IO uint32_t CLKSEL3;       /* Offset: 0x1C  Clock Source Select Control Register 3                             */
+    __IO uint32_t CLKDIV0;       /* Offset: 0x20  Clock Divider Number Register 0                                    */
+    __IO uint32_t CLKDIV1;       /* Offset: 0x24  Clock Divider Number Register 1                                    */
+    __I  uint32_t RESERVE0[6];  
+    __IO uint32_t PLLCTL;        /* Offset: 0x40  PLL Control Register                                               */
+    __I  uint32_t RESERVE1[3];  
+    __I  uint32_t STATUS;        /* Offset: 0x50  Clock Status Monitor Register                                      */
+    __I  uint32_t RESERVE2[3];  
+    __IO uint32_t CLKOCTL;       /* Offset: 0x60  Clock Output Control Register                                      */
+    __I  uint32_t RESERVE3[3];  
+    __IO uint32_t CLKDCTL;       /* Offset: 0x70  Clock Fail Detector Control Register                               */
+    __IO uint32_t CLKDSTS;       /* Offset: 0x74  Clock Fail Detector Status Register                                */
+    __IO uint32_t CDUPB;         /* Offset: 0x78  Clock Frequency Detector Upper Boundary Register                   */
+    __IO uint32_t CDLOWB;        /* Offset: 0x7C  Clock Frequency Detector Low Boundary Register                     */
+
+} CLK_T;
+
+
+
+/**
+    @addtogroup CLK_CONST CLK Bit Field Definition
+    Constant Definitions for CLK Controller
+@{ */
+
+#define CLK_PWRCTL_HXTEN_Pos             (0)                                               /*!< CLK_T::PWRCTL: HXTEN Position             */
+#define CLK_PWRCTL_HXTEN_Msk             (0x1ul << CLK_PWRCTL_HXTEN_Pos)                   /*!< CLK_T::PWRCTL: HXTEN Mask                 */
+
+#define CLK_PWRCTL_LXTEN_Pos             (1)                                               /*!< CLK_T::PWRCTL: LXTEN Position             */
+#define CLK_PWRCTL_LXTEN_Msk             (0x1ul << CLK_PWRCTL_LXTEN_Pos)                   /*!< CLK_T::PWRCTL: LXTEN Mask                 */
+
+#define CLK_PWRCTL_HIRCEN_Pos            (2)                                               /*!< CLK_T::PWRCTL: HIRCEN Position            */
+#define CLK_PWRCTL_HIRCEN_Msk            (0x1ul << CLK_PWRCTL_HIRCEN_Pos)                  /*!< CLK_T::PWRCTL: HIRCEN Mask                */
+
+#define CLK_PWRCTL_LIRCEN_Pos            (3)                                               /*!< CLK_T::PWRCTL: LIRCEN Position            */
+#define CLK_PWRCTL_LIRCEN_Msk            (0x1ul << CLK_PWRCTL_LIRCEN_Pos)                  /*!< CLK_T::PWRCTL: LIRCEN Mask                */
+
+#define CLK_PWRCTL_PDWKDLY_Pos           (4)                                               /*!< CLK_T::PWRCTL: PDWKDLY Position           */
+#define CLK_PWRCTL_PDWKDLY_Msk           (0x1ul << CLK_PWRCTL_PDWKDLY_Pos)                 /*!< CLK_T::PWRCTL: PDWKDLY Mask               */
+
+#define CLK_PWRCTL_PDWKIEN_Pos           (5)                                               /*!< CLK_T::PWRCTL: PDWKIEN Position           */
+#define CLK_PWRCTL_PDWKIEN_Msk           (0x1ul << CLK_PWRCTL_PDWKIEN_Pos)                 /*!< CLK_T::PWRCTL: PDWKIEN Mask               */
+
+#define CLK_PWRCTL_PDWKIF_Pos            (6)                                               /*!< CLK_T::PWRCTL: PDWKIF Position            */
+#define CLK_PWRCTL_PDWKIF_Msk            (0x1ul << CLK_PWRCTL_PDWKIF_Pos)                  /*!< CLK_T::PWRCTL: PDWKIF Mask                */
+
+#define CLK_PWRCTL_PDEN_Pos              (7)                                               /*!< CLK_T::PWRCTL: PDEN Position              */
+#define CLK_PWRCTL_PDEN_Msk              (0x1ul << CLK_PWRCTL_PDEN_Pos)                    /*!< CLK_T::PWRCTL: PDEN Mask                  */
+
+#define CLK_PWRCTL_PDWTCPU_Pos           (8)                                               /*!< CLK_T::PWRCTL: PDWTCPU Position           */
+#define CLK_PWRCTL_PDWTCPU_Msk           (0x1ul << CLK_PWRCTL_PDWTCPU_Pos)                 /*!< CLK_T::PWRCTL: PDWTCPU Mask               */
+
+#define CLK_PWRCTL_HXTGAIN_Pos           (10)                                              /*!< CLK_T::PWRCTL: HXTGAIN Position           */
+#define CLK_PWRCTL_HXTGAIN_Msk           (0x3ul << CLK_PWRCTL_HXTGAIN_Pos)                 /*!< CLK_T::PWRCTL: HXTGAIN Mask               */
+
+#define CLK_PWRCTL_HXTSELTYP_Pos         (12)                                              /*!< CLK_T::PWRCTL: HXTSELTYP Position         */
+#define CLK_PWRCTL_HXTSELTYP_Msk         (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos)               /*!< CLK_T::PWRCTL: HXTSELTYP Mask             */
+
+#define CLK_AHBCLK_PDMACKEN_Pos          (1)                                               /*!< CLK_T::AHBCLK: PDMACKEN Position          */
+#define CLK_AHBCLK_PDMACKEN_Msk          (0x1ul << CLK_AHBCLK_PDMACKEN_Pos)                /*!< CLK_T::AHBCLK: PDMACKEN Mask              */
+
+#define CLK_AHBCLK_ISPCKEN_Pos           (2)                                               /*!< CLK_T::AHBCLK: ISPCKEN Position           */
+#define CLK_AHBCLK_ISPCKEN_Msk           (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)                 /*!< CLK_T::AHBCLK: ISPCKEN Mask               */
+
+#define CLK_AHBCLK_EBICKEN_Pos           (3)                                               /*!< CLK_T::AHBCLK: EBICKEN Position           */
+#define CLK_AHBCLK_EBICKEN_Msk           (0x1ul << CLK_AHBCLK_EBICKEN_Pos)                 /*!< CLK_T::AHBCLK: EBICKEN Mask               */
+
+#define CLK_AHBCLK_USBHCKEN_Pos          (4)                                               /*!< CLK_T::AHBCLK: USBHCKEN Position          */
+#define CLK_AHBCLK_USBHCKEN_Msk          (0x1ul << CLK_AHBCLK_USBHCKEN_Pos)                /*!< CLK_T::AHBCLK: USBHCKEN Mask              */
+
+#define CLK_AHBCLK_CRCCKEN_Pos           (7)                                               /*!< CLK_T::AHBCLK: CRCCKEN Position           */
+#define CLK_AHBCLK_CRCCKEN_Msk           (0x1ul << CLK_AHBCLK_CRCCKEN_Pos)                 /*!< CLK_T::AHBCLK: CRCCKEN Mask               */
+
+#define CLK_AHBCLK_FMCIDLE_Pos           (15)                                              /*!< CLK_T::AHBCLK: FMCIDLE Position           */
+#define CLK_AHBCLK_FMCIDLE_Msk           (0x1ul << CLK_AHBCLK_FMCIDLE_Pos)                 /*!< CLK_T::AHBCLK: FMCIDLE Mask               */
+
+#define CLK_APBCLK0_WDTCKEN_Pos          (0)                                               /*!< CLK_T::APBCLK0: WDTCKEN Position          */
+#define CLK_APBCLK0_WDTCKEN_Msk          (0x1ul << CLK_APBCLK0_WDTCKEN_Pos)                /*!< CLK_T::APBCLK0: WDTCKEN Mask              */
+
+#define CLK_APBCLK0_RTCCKEN_Pos          (1)                                               /*!< CLK_T::APBCLK0: RTCCKEN Position          */
+#define CLK_APBCLK0_RTCCKEN_Msk          (0x1ul << CLK_APBCLK0_RTCCKEN_Pos)                /*!< CLK_T::APBCLK0: RTCCKEN Mask              */
+
+#define CLK_APBCLK0_TMR0CKEN_Pos         (2)                                               /*!< CLK_T::APBCLK0: TMR0CKEN Position         */
+#define CLK_APBCLK0_TMR0CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR0CKEN Mask             */
+
+#define CLK_APBCLK0_TMR1CKEN_Pos         (3)                                               /*!< CLK_T::APBCLK0: TMR1CKEN Position         */
+#define CLK_APBCLK0_TMR1CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR1CKEN Mask             */
+
+#define CLK_APBCLK0_TMR2CKEN_Pos         (4)                                               /*!< CLK_T::APBCLK0: TMR2CKEN Position         */
+#define CLK_APBCLK0_TMR2CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR2CKEN Mask             */
+
+#define CLK_APBCLK0_TMR3CKEN_Pos         (5)                                               /*!< CLK_T::APBCLK0: TMR3CKEN Position         */
+#define CLK_APBCLK0_TMR3CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR3CKEN Mask             */
+
+#define CLK_APBCLK0_CLKOCKEN_Pos         (6)                                               /*!< CLK_T::APBCLK0: CLKOCKEN Position         */
+#define CLK_APBCLK0_CLKOCKEN_Msk         (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos)               /*!< CLK_T::APBCLK0: CLKOCKEN Mask             */
+
+#define CLK_APBCLK0_ACMP01CKEN_Pos       (7)                                               /*!< CLK_T::APBCLK0: ACMP01CKEN Position       */
+#define CLK_APBCLK0_ACMP01CKEN_Msk       (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos)             /*!< CLK_T::APBCLK0: ACMP01CKEN Mask           */
+
+#define CLK_APBCLK0_I2C0CKEN_Pos         (8)                                               /*!< CLK_T::APBCLK0: I2C0CKEN Position         */
+#define CLK_APBCLK0_I2C0CKEN_Msk         (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos)               /*!< CLK_T::APBCLK0: I2C0CKEN Mask             */
+
+#define CLK_APBCLK0_I2C1CKEN_Pos         (9)                                               /*!< CLK_T::APBCLK0: I2C1CKEN Position         */
+#define CLK_APBCLK0_I2C1CKEN_Msk         (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos)               /*!< CLK_T::APBCLK0: I2C1CKEN Mask             */
+
+#define CLK_APBCLK0_SPI0CKEN_Pos         (12)                                              /*!< CLK_T::APBCLK0: SPI0CKEN Position         */
+#define CLK_APBCLK0_SPI0CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos)               /*!< CLK_T::APBCLK0: SPI0CKEN Mask             */
+
+#define CLK_APBCLK0_SPI1CKEN_Pos         (13)                                              /*!< CLK_T::APBCLK0: SPI1CKEN Position         */
+#define CLK_APBCLK0_SPI1CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos)               /*!< CLK_T::APBCLK0: SPI1CKEN Mask             */
+
+#define CLK_APBCLK0_SPI2CKEN_Pos         (14)                                              /*!< CLK_T::APBCLK0: SPI2CKEN Position         */
+#define CLK_APBCLK0_SPI2CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos)               /*!< CLK_T::APBCLK0: SPI2CKEN Mask             */
+
+#define CLK_APBCLK0_UART0CKEN_Pos        (16)                                              /*!< CLK_T::APBCLK0: UART0CKEN Position        */
+#define CLK_APBCLK0_UART0CKEN_Msk        (0x1ul << CLK_APBCLK0_UART0CKEN_Pos)              /*!< CLK_T::APBCLK0: UART0CKEN Mask            */
+
+#define CLK_APBCLK0_UART1CKEN_Pos        (17)                                              /*!< CLK_T::APBCLK0: UART1CKEN Position        */
+#define CLK_APBCLK0_UART1CKEN_Msk        (0x1ul << CLK_APBCLK0_UART1CKEN_Pos)              /*!< CLK_T::APBCLK0: UART1CKEN Mask            */
+
+#define CLK_APBCLK0_UART2CKEN_Pos        (18)                                              /*!< CLK_T::APBCLK0: UART2CKEN Position        */
+#define CLK_APBCLK0_UART2CKEN_Msk        (0x1ul << CLK_APBCLK0_UART2CKEN_Pos)              /*!< CLK_T::APBCLK0: UART2CKEN Mask            */
+
+#define CLK_APBCLK0_UART3CKEN_Pos        (19)                                              /*!< CLK_T::APBCLK0: UART3CKEN Position        */
+#define CLK_APBCLK0_UART3CKEN_Msk        (0x1ul << CLK_APBCLK0_UART3CKEN_Pos)              /*!< CLK_T::APBCLK0: UART3CKEN Mask            */
+
+#define CLK_APBCLK0_CAN0CKEN_Pos         (24)                                              /*!< CLK_T::APBCLK0: CAN0CKEN Position         */
+#define CLK_APBCLK0_CAN0CKEN_Msk         (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos)               /*!< CLK_T::APBCLK0: CAN0CKEN Mask             */
+
+#define CLK_APBCLK0_OTGCKEN_Pos          (26)                                              /*!< CLK_T::APBCLK0: OTGCKEN Position          */
+#define CLK_APBCLK0_OTGCKEN_Msk          (0x1ul << CLK_APBCLK0_OTGCKEN_Pos)                /*!< CLK_T::APBCLK0: OTGCKEN Mask              */
+
+#define CLK_APBCLK0_USBDCKEN_Pos         (27)                                              /*!< CLK_T::APBCLK0: USBDCKEN Position         */
+#define CLK_APBCLK0_USBDCKEN_Msk         (0x1ul << CLK_APBCLK0_USBDCKEN_Pos)               /*!< CLK_T::APBCLK0: USBDCKEN Mask             */
+
+#define CLK_APBCLK0_EADCCKEN_Pos         (28)                                              /*!< CLK_T::APBCLK0: EADCCKEN Position         */
+#define CLK_APBCLK0_EADCCKEN_Msk         (0x1ul << CLK_APBCLK0_EADCCKEN_Pos)               /*!< CLK_T::APBCLK0: EADCCKEN Mask             */
+
+#define CLK_APBCLK1_SC0CKEN_Pos          (0)                                               /*!< CLK_T::APBCLK1: SC0CKEN Position          */
+#define CLK_APBCLK1_SC0CKEN_Msk          (0x1ul << CLK_APBCLK1_SC0CKEN_Pos)                /*!< CLK_T::APBCLK1: SC0CKEN Mask              */
+
+#define CLK_APBCLK1_DACCKEN_Pos          (12)                                              /*!< CLK_T::APBCLK1: DACCKEN Position          */
+#define CLK_APBCLK1_DACCKEN_Msk          (0x1ul << CLK_APBCLK1_DACCKEN_Pos)                /*!< CLK_T::APBCLK1: DACCKEN Mask              */
+
+#define CLK_APBCLK1_PWM0CKEN_Pos         (16)                                              /*!< CLK_T::APBCLK1: PWM0CKEN Position         */
+#define CLK_APBCLK1_PWM0CKEN_Msk         (0x1ul << CLK_APBCLK1_PWM0CKEN_Pos)               /*!< CLK_T::APBCLK1: PWM0CKEN Mask             */
+
+#define CLK_APBCLK1_PWM1CKEN_Pos         (17)                                              /*!< CLK_T::APBCLK1: PWM1CKEN Position         */
+#define CLK_APBCLK1_PWM1CKEN_Msk         (0x1ul << CLK_APBCLK1_PWM1CKEN_Pos)               /*!< CLK_T::APBCLK1: PWM1CKEN Mask             */
+
+#define CLK_APBCLK1_TKCKEN_Pos           (25)                                              /*!< CLK_T::APBCLK1: TKCKEN Position           */
+#define CLK_APBCLK1_TKCKEN_Msk           (0x1ul << CLK_APBCLK1_TKCKEN_Pos)                 /*!< CLK_T::APBCLK1: TKCKEN Mask               */
+
+#define CLK_CLKSEL0_HCLKSEL_Pos          (0)                                               /*!< CLK_T::CLKSEL0: HCLKSEL Position          */
+#define CLK_CLKSEL0_HCLKSEL_Msk          (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)                /*!< CLK_T::CLKSEL0: HCLKSEL Mask              */
+
+#define CLK_CLKSEL0_STCLKSEL_Pos         (3)                                               /*!< CLK_T::CLKSEL0: STCLKSEL Position         */
+#define CLK_CLKSEL0_STCLKSEL_Msk         (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos)               /*!< CLK_T::CLKSEL0: STCLKSEL Mask             */
+
+#define CLK_CLKSEL0_PCLK0SEL_Pos         (6)                                               /*!< CLK_T::CLKSEL0: PCLK0SEL Position         */
+#define CLK_CLKSEL0_PCLK0SEL_Msk         (0x1ul << CLK_CLKSEL0_PCLK0SEL_Pos)               /*!< CLK_T::CLKSEL0: PCLK0SEL Mask             */
+
+#define CLK_CLKSEL0_PCLK1SEL_Pos         (7)                                               /*!< CLK_T::CLKSEL0: PCLK1SEL Position         */
+#define CLK_CLKSEL0_PCLK1SEL_Msk         (0x1ul << CLK_CLKSEL0_PCLK1SEL_Pos)               /*!< CLK_T::CLKSEL0: PCLK1SEL Mask             */
+
+#define CLK_CLKSEL1_WDTSEL_Pos           (0)                                               /*!< CLK_T::CLKSEL1: WDTSEL Position           */
+#define CLK_CLKSEL1_WDTSEL_Msk           (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)                 /*!< CLK_T::CLKSEL1: WDTSEL Mask               */
+
+#define CLK_CLKSEL1_TMR0SEL_Pos          (8)                                               /*!< CLK_T::CLKSEL1: TMR0SEL Position          */
+#define CLK_CLKSEL1_TMR0SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR0SEL Mask              */
+
+#define CLK_CLKSEL1_TMR1SEL_Pos          (12)                                              /*!< CLK_T::CLKSEL1: TMR1SEL Position          */
+#define CLK_CLKSEL1_TMR1SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR1SEL Mask              */
+
+#define CLK_CLKSEL1_TMR2SEL_Pos          (16)                                              /*!< CLK_T::CLKSEL1: TMR2SEL Position          */
+#define CLK_CLKSEL1_TMR2SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR2SEL Mask              */
+
+#define CLK_CLKSEL1_TMR3SEL_Pos          (20)                                              /*!< CLK_T::CLKSEL1: TMR3SEL Position          */
+#define CLK_CLKSEL1_TMR3SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR3SEL Mask              */
+
+#define CLK_CLKSEL1_UARTSEL_Pos          (24)                                              /*!< CLK_T::CLKSEL1: UARTSEL Position          */
+#define CLK_CLKSEL1_UARTSEL_Msk          (0x3ul << CLK_CLKSEL1_UARTSEL_Pos)                /*!< CLK_T::CLKSEL1: UARTSEL Mask              */
+
+#define CLK_CLKSEL1_CLKOSEL_Pos          (28)                                              /*!< CLK_T::CLKSEL1: CLKOSEL Position          */
+#define CLK_CLKSEL1_CLKOSEL_Msk          (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos)                /*!< CLK_T::CLKSEL1: CLKOSEL Mask              */
+
+#define CLK_CLKSEL1_WWDTSEL_Pos          (30)                                              /*!< CLK_T::CLKSEL1: WWDTSEL Position          */
+#define CLK_CLKSEL1_WWDTSEL_Msk          (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos)                /*!< CLK_T::CLKSEL1: WWDTSEL Mask              */
+
+#define CLK_CLKSEL2_PWM0SEL_Pos          (0)                                               /*!< CLK_T::CLKSEL2: PWM0SEL Position          */
+#define CLK_CLKSEL2_PWM0SEL_Msk          (0x1ul << CLK_CLKSEL2_PWM0SEL_Pos)                /*!< CLK_T::CLKSEL2: PWM0SEL Mask              */
+
+#define CLK_CLKSEL2_PWM1SEL_Pos          (1)                                               /*!< CLK_T::CLKSEL2: PWM1SEL Position          */
+#define CLK_CLKSEL2_PWM1SEL_Msk          (0x1ul << CLK_CLKSEL2_PWM1SEL_Pos)                /*!< CLK_T::CLKSEL2: PWM1SEL Mask              */
+
+#define CLK_CLKSEL2_SPI0SEL_Pos          (2)                                               /*!< CLK_T::CLKSEL2: SPI0SEL Position          */
+#define CLK_CLKSEL2_SPI0SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI0SEL Mask              */
+
+#define CLK_CLKSEL2_SPI1SEL_Pos          (4)                                               /*!< CLK_T::CLKSEL2: SPI1SEL Position          */
+#define CLK_CLKSEL2_SPI1SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI1SEL Mask              */
+
+#define CLK_CLKSEL2_SPI2SEL_Pos          (6)                                               /*!< CLK_T::CLKSEL2: SPI2SEL Position          */
+#define CLK_CLKSEL2_SPI2SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI2SEL Mask              */
+
+#define CLK_CLKSEL3_SC0SEL_Pos           (0)                                               /*!< CLK_T::CLKSEL3: SC0SEL Position           */
+#define CLK_CLKSEL3_SC0SEL_Msk           (0x3ul << CLK_CLKSEL3_SC0SEL_Pos)                 /*!< CLK_T::CLKSEL3: SC0SEL Mask               */
+
+#define CLK_CLKSEL3_RTCSEL_Pos           (8)                                               /*!< CLK_T::CLKSEL3: RTCSEL Position           */
+#define CLK_CLKSEL3_RTCSEL_Msk           (0x1ul << CLK_CLKSEL3_RTCSEL_Pos)                 /*!< CLK_T::CLKSEL3: RTCSEL Mask               */
+
+#define CLK_CLKDIV0_HCLKDIV_Pos          (0)                                               /*!< CLK_T::CLKDIV0: HCLKDIV Position          */
+#define CLK_CLKDIV0_HCLKDIV_Msk          (0xful << CLK_CLKDIV0_HCLKDIV_Pos)                /*!< CLK_T::CLKDIV0: HCLKDIV Mask              */
+
+#define CLK_CLKDIV0_USBDIV_Pos           (4)                                               /*!< CLK_T::CLKDIV0: USBDIV Position           */
+#define CLK_CLKDIV0_USBDIV_Msk           (0xful << CLK_CLKDIV0_USBDIV_Pos)                 /*!< CLK_T::CLKDIV0: USBDIV Mask               */
+
+#define CLK_CLKDIV0_UARTDIV_Pos          (8)                                               /*!< CLK_T::CLKDIV0: UARTDIV Position          */
+#define CLK_CLKDIV0_UARTDIV_Msk          (0xful << CLK_CLKDIV0_UARTDIV_Pos)                /*!< CLK_T::CLKDIV0: UARTDIV Mask              */
+
+#define CLK_CLKDIV0_EADCDIV_Pos          (16)                                              /*!< CLK_T::CLKDIV0: EADCDIV Position          */
+#define CLK_CLKDIV0_EADCDIV_Msk          (0xfful << CLK_CLKDIV0_EADCDIV_Pos)               /*!< CLK_T::CLKDIV0: EADCDIV Mask              */
+
+#define CLK_CLKDIV1_SC0DIV_Pos           (0)                                               /*!< CLK_T::CLKDIV1: SC0DIV Position           */
+#define CLK_CLKDIV1_SC0DIV_Msk           (0xfful << CLK_CLKDIV1_SC0DIV_Pos)                /*!< CLK_T::CLKDIV1: SC0DIV Mask               */
+
+#define CLK_PLLCTL_FBDIV_Pos             (0)                                               /*!< CLK_T::PLLCTL: FBDIV Position             */
+#define CLK_PLLCTL_FBDIV_Msk             (0x1fful << CLK_PLLCTL_FBDIV_Pos)                 /*!< CLK_T::PLLCTL: FBDIV Mask                 */
+
+#define CLK_PLLCTL_INDIV_Pos             (9)                                               /*!< CLK_T::PLLCTL: INDIV Position             */
+#define CLK_PLLCTL_INDIV_Msk             (0x1ful << CLK_PLLCTL_INDIV_Pos)                  /*!< CLK_T::PLLCTL: INDIV Mask                 */
+
+#define CLK_PLLCTL_OUTDIV_Pos            (14)                                              /*!< CLK_T::PLLCTL: OUTDIV Position            */
+#define CLK_PLLCTL_OUTDIV_Msk            (0x3ul << CLK_PLLCTL_OUTDIV_Pos)                  /*!< CLK_T::PLLCTL: OUTDIV Mask                */
+
+#define CLK_PLLCTL_PD_Pos                (16)                                              /*!< CLK_T::PLLCTL: PD Position                */
+#define CLK_PLLCTL_PD_Msk                (0x1ul << CLK_PLLCTL_PD_Pos)                      /*!< CLK_T::PLLCTL: PD Mask                    */
+
+#define CLK_PLLCTL_BP_Pos                (17)                                              /*!< CLK_T::PLLCTL: BP Position                */
+#define CLK_PLLCTL_BP_Msk                (0x1ul << CLK_PLLCTL_BP_Pos)                      /*!< CLK_T::PLLCTL: BP Mask                    */
+
+#define CLK_PLLCTL_OE_Pos                (18)                                              /*!< CLK_T::PLLCTL: OE Position                */
+#define CLK_PLLCTL_OE_Msk                (0x1ul << CLK_PLLCTL_OE_Pos)                      /*!< CLK_T::PLLCTL: OE Mask                    */
+
+#define CLK_PLLCTL_PLLSRC_Pos            (19)                                              /*!< CLK_T::PLLCTL: PLLSRC Position            */
+#define CLK_PLLCTL_PLLSRC_Msk            (0x1ul << CLK_PLLCTL_PLLSRC_Pos)                  /*!< CLK_T::PLLCTL: PLLSRC Mask                */
+
+#define CLK_PLLCTL_STBSEL_Pos            (23)                                              /*!< CLK_T::PLLCTL: STBSEL Position            */
+#define CLK_PLLCTL_STBSEL_Msk            (0x1ul << CLK_PLLCTL_STBSEL_Pos)                  /*!< CLK_T::PLLCTL: STBSEL Mask                */
+
+#define CLK_STATUS_HXTSTB_Pos            (0)                                               /*!< CLK_T::STATUS: HXTSTB Position            */
+#define CLK_STATUS_HXTSTB_Msk            (0x1ul << CLK_STATUS_HXTSTB_Pos)                  /*!< CLK_T::STATUS: HXTSTB Mask                */
+
+#define CLK_STATUS_LXTSTB_Pos            (1)                                               /*!< CLK_T::STATUS: LXTSTB Position            */
+#define CLK_STATUS_LXTSTB_Msk            (0x1ul << CLK_STATUS_LXTSTB_Pos)                  /*!< CLK_T::STATUS: LXTSTB Mask                */
+
+#define CLK_STATUS_PLLSTB_Pos            (2)                                               /*!< CLK_T::STATUS: PLLSTB Position            */
+#define CLK_STATUS_PLLSTB_Msk            (0x1ul << CLK_STATUS_PLLSTB_Pos)                  /*!< CLK_T::STATUS: PLLSTB Mask                */
+
+#define CLK_STATUS_LIRCSTB_Pos           (3)                                               /*!< CLK_T::STATUS: LIRCSTB Position           */
+#define CLK_STATUS_LIRCSTB_Msk           (0x1ul << CLK_STATUS_LIRCSTB_Pos)                 /*!< CLK_T::STATUS: LIRCSTB Mask               */
+
+#define CLK_STATUS_HIRCSTB_Pos           (4)                                               /*!< CLK_T::STATUS: HIRCSTB Position           */
+#define CLK_STATUS_HIRCSTB_Msk           (0x1ul << CLK_STATUS_HIRCSTB_Pos)                 /*!< CLK_T::STATUS: HIRCSTB Mask               */
+
+#define CLK_STATUS_CLKSFAIL_Pos          (7)                                               /*!< CLK_T::STATUS: CLKSFAIL Position          */
+#define CLK_STATUS_CLKSFAIL_Msk          (0x1ul << CLK_STATUS_CLKSFAIL_Pos)                /*!< CLK_T::STATUS: CLKSFAIL Mask              */
+
+#define CLK_CLKOCTL_FREQSEL_Pos          (0)                                               /*!< CLK_T::CLKOCTL: FREQSEL Position          */
+#define CLK_CLKOCTL_FREQSEL_Msk          (0xful << CLK_CLKOCTL_FREQSEL_Pos)                /*!< CLK_T::CLKOCTL: FREQSEL Mask              */
+
+#define CLK_CLKOCTL_CLKOEN_Pos           (4)                                               /*!< CLK_T::CLKOCTL: CLKOEN Position           */
+#define CLK_CLKOCTL_CLKOEN_Msk           (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)                 /*!< CLK_T::CLKOCTL: CLKOEN Mask               */
+
+#define CLK_CLKOCTL_DIV1EN_Pos           (5)                                               /*!< CLK_T::CLKOCTL: DIV1EN Position           */
+#define CLK_CLKOCTL_DIV1EN_Msk           (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)                 /*!< CLK_T::CLKOCTL: DIV1EN Mask               */
+
+#define CLK_CLKOCTL_CLK1HZEN_Pos         (6)                                               /*!< CLK_T::CLKOCTL: CLK1HZEN Position         */
+#define CLK_CLKOCTL_CLK1HZEN_Msk         (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos)               /*!< CLK_T::CLKOCTL: CLK1HZEN Mask             */
+
+#define CLK_CLKDCTL_HXTFDEN_Pos          (4)                                               /*!< CLK_T::CLKDCTL: HXTFDEN Position          */
+#define CLK_CLKDCTL_HXTFDEN_Msk          (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos)                /*!< CLK_T::CLKDCTL: HXTFDEN Mask              */
+
+#define CLK_CLKDCTL_HXTFIEN_Pos          (5)                                               /*!< CLK_T::CLKDCTL: HXTFIEN Position          */
+#define CLK_CLKDCTL_HXTFIEN_Msk          (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos)                /*!< CLK_T::CLKDCTL: HXTFIEN Mask              */
+
+#define CLK_CLKDCTL_LXTFDEN_Pos          (12)                                              /*!< CLK_T::CLKDCTL: LXTFDEN Position          */
+#define CLK_CLKDCTL_LXTFDEN_Msk          (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos)                /*!< CLK_T::CLKDCTL: LXTFDEN Mask              */
+
+#define CLK_CLKDCTL_LXTFIEN_Pos          (13)                                              /*!< CLK_T::CLKDCTL: LXTFIEN Position          */
+#define CLK_CLKDCTL_LXTFIEN_Msk          (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos)                /*!< CLK_T::CLKDCTL: LXTFIEN Mask              */
+
+#define CLK_CLKDCTL_HXTFQDEN_Pos         (16)                                              /*!< CLK_T::CLKDCTL: HXTFQDEN Position         */
+#define CLK_CLKDCTL_HXTFQDEN_Msk         (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos)               /*!< CLK_T::CLKDCTL: HXTFQDEN Mask             */
+
+#define CLK_CLKDCTL_HXTFQIEN_Pos         (17)                                              /*!< CLK_T::CLKDCTL: HXTFQIEN Position         */
+#define CLK_CLKDCTL_HXTFQIEN_Msk         (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos)               /*!< CLK_T::CLKDCTL: HXTFQIEN Mask             */
+
+#define CLK_CLKDSTS_HXTFIF_Pos           (0)                                               /*!< CLK_T::CLKDSTS: HXTFIF Position           */
+#define CLK_CLKDSTS_HXTFIF_Msk           (0x1ul << CLK_CLKDSTS_HXTFIF_Pos)                 /*!< CLK_T::CLKDSTS: HXTFIF Mask               */
+
+#define CLK_CLKDSTS_LXTFIF_Pos           (1)                                               /*!< CLK_T::CLKDSTS: LXTFIF Position           */
+#define CLK_CLKDSTS_LXTFIF_Msk           (0x1ul << CLK_CLKDSTS_LXTFIF_Pos)                 /*!< CLK_T::CLKDSTS: LXTFIF Mask               */
+
+#define CLK_CLKDSTS_HXTFQIF_Pos          (8)                                               /*!< CLK_T::CLKDSTS: HXTFQIF Position          */
+#define CLK_CLKDSTS_HXTFQIF_Msk          (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos)                /*!< CLK_T::CLKDSTS: HXTFQIF Mask              */
+
+#define CLK_CDUPB_UPERBD_Pos             (0)                                               /*!< CLK_T::CDUPB: UPERBD Position             */
+#define CLK_CDUPB_UPERBD_Msk             (0x3fful << CLK_CDUPB_UPERBD_Pos)                 /*!< CLK_T::CDUPB: UPERBD Mask                 */
+
+#define CLK_CDLOWB_LOWERBD_Pos           (0)                                               /*!< CLK_T::CDLOWB: LOWERBD Position           */
+#define CLK_CDLOWB_LOWERBD_Msk           (0x3fful << CLK_CDLOWB_LOWERBD_Pos)               /*!< CLK_T::CDLOWB: LOWERBD Mask               */
+
+
+/**@}*/ /* CLK_CONST */
+/**@}*/ /* end of CLK register group */
+
+
+
+/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
+/**
+    @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
+    Memory Mapped Structure for CRC Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var CRC_T::CTL
+ * Offset: 0x00  CRC Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |CRCEN     |CRC Channel Enable Bit
+ * |        |          |0 = No effect.
+ * |        |          |1 = CRC operation Enabled.
+ * |[1]     |CRCRST    |CRC Engine Reset
+ * |        |          |0 = No effect.
+ * |        |          |1 = Reset the internal CRC state machine and internal buffer.
+ * |        |          |The others contents of CRC_CTL register will not be cleared.
+ * |        |          |Note1: This bit will be cleared automatically.
+ * |        |          |Note2: Setting this bit will reload the initial seed value (CRC_SEED register).
+ * |[24]    |DATREV    |Write Data Bit Order Reverse
+ * |        |          |This bit is used to enable the bit order reverse function for write data value in CRC_DAT register.
+ * |        |          |0 = Bit order reversed for CRC write data in Disabled.
+ * |        |          |1 = Bit order reversed for CRC write data in Enabled (per byte).
+ * |        |          |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
+ * |[25]    |CHKSREV   |Checksum Bit Order Reverse
+ * |        |          |This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.
+ * |        |          |0 = Bit order reverse for CRC checksum Disabled.
+ * |        |          |1 = Bit order reverse for CRC checksum Enabled.
+ * |        |          |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
+ * |[26]    |DATFMT    |Write Data 1's Complement
+ * |        |          |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
+ * |        |          |0 = 1's complement for CRC writes data in Disabled.
+ * |        |          |1 = 1's complement for CRC writes data in Enabled.
+ * |[27]    |CHKSFMT   |Checksum 1's Complement
+ * |        |          |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
+ * |        |          |0 = 1's complement for CRC checksum Disabled.
+ * |        |          |1 = 1's complement for CRC checksum Enabled.
+ * |[29:28] |DATLEN    |CPU Write Data Length
+ * |        |          |This field indicates the write data length.
+ * |        |          |00 = Data length is 8-bit mode.
+ * |        |          |01 = Data length is 16-bit mode.
+ * |        |          |1x = Data length is 32-bit mode.
+ * |        |          |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
+ * |[31:30] |CRCMODE   |CRC Polynomial Mode
+ * |        |          |This field indicates the CRC operation polynomial mode.
+ * |        |          |00 = CRC-CCITT Polynomial mode.
+ * |        |          |01 = CRC-8 Polynomial mode.
+ * |        |          |10 = CRC-16 Polynomial mode.
+ * |        |          |11 = CRC-32 Polynomial mode.
+ * @var CRC_T::DAT
+ * Offset: 0x04  CRC Write Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |DATA      |CRC Write Data Bits
+ * |        |          |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
+ * |        |          |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
+ * @var CRC_T::SEED
+ * Offset: 0x08  CRC Seed Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |SEED      |CRC Seed Value
+ * |        |          |This field indicates the CRC seed value.
+ * @var CRC_T::CHECKSUM
+ * Offset: 0x0C  CRC Checksum Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |CHECKSUM  |CRC Checksum Results
+ * |        |          |This field indicates the CRC checksum result.
+ */
+
+    __IO uint32_t CTL;           /* Offset: 0x00  CRC Control Register                                               */
+    __IO uint32_t DAT;           /* Offset: 0x04  CRC Write Data Register                                            */
+    __IO uint32_t SEED;          /* Offset: 0x08  CRC Seed Register                                                  */
+    __I  uint32_t CHECKSUM;      /* Offset: 0x0C  CRC Checksum Register                                              */
+
+} CRC_T;
+
+
+
+/**
+    @addtogroup CRC_CONST CRC Bit Field Definition
+    Constant Definitions for CRC Controller
+@{ */
+
+#define CRC_CTL_CRCEN_Pos                (0)                                               /*!< CRC_T::CTL: CRCEN Position                */
+#define CRC_CTL_CRCEN_Msk                (0x1ul << CRC_CTL_CRCEN_Pos)                      /*!< CRC_T::CTL: CRCEN Mask                    */
+
+#define CRC_CTL_CRCRST_Pos               (1)                                               /*!< CRC_T::CTL: CRCRST Position               */
+#define CRC_CTL_CRCRST_Msk               (0x1ul << CRC_CTL_CRCRST_Pos)                     /*!< CRC_T::CTL: CRCRST Mask                   */
+
+#define CRC_CTL_DATREV_Pos               (24)                                              /*!< CRC_T::CTL: DATREV Position               */
+#define CRC_CTL_DATREV_Msk               (0x1ul << CRC_CTL_DATREV_Pos)                     /*!< CRC_T::CTL: DATREV Mask                   */
+
+#define CRC_CTL_CHKSREV_Pos              (25)                                              /*!< CRC_T::CTL: CHKSREV Position              */
+#define CRC_CTL_CHKSREV_Msk              (0x1ul << CRC_CTL_CHKSREV_Pos)                    /*!< CRC_T::CTL: CHKSREV Mask                  */
+
+#define CRC_CTL_DATFMT_Pos               (26)                                              /*!< CRC_T::CTL: DATFMT Position               */
+#define CRC_CTL_DATFMT_Msk               (0x1ul << CRC_CTL_DATFMT_Pos)                     /*!< CRC_T::CTL: DATFMT Mask                   */
+
+#define CRC_CTL_CHKSFMT_Pos              (27)                                              /*!< CRC_T::CTL: CHKSFMT Position              */
+#define CRC_CTL_CHKSFMT_Msk              (0x1ul << CRC_CTL_CHKSFMT_Pos)                    /*!< CRC_T::CTL: CHKSFMT Mask                  */
+
+#define CRC_CTL_DATLEN_Pos               (28)                                              /*!< CRC_T::CTL: DATLEN Position               */
+#define CRC_CTL_DATLEN_Msk               (0x3ul << CRC_CTL_DATLEN_Pos)                     /*!< CRC_T::CTL: DATLEN Mask                   */
+
+#define CRC_CTL_CRCMODE_Pos              (30)                                              /*!< CRC_T::CTL: CRCMODE Position              */
+#define CRC_CTL_CRCMODE_Msk              (0x3ul << CRC_CTL_CRCMODE_Pos)                    /*!< CRC_T::CTL: CRCMODE Mask                  */
+
+#define CRC_DAT_DATA_Pos                 (0)                                               /*!< CRC_T::DAT: DATA Position                 */
+#define CRC_DAT_DATA_Msk                 (0xfffffffful << CRC_DAT_DATA_Pos)                /*!< CRC_T::DAT: DATA Mask                     */
+
+#define CRC_SEED_SEED_Pos                (0)                                               /*!< CRC_T::SEED: SEED Position                */
+#define CRC_SEED_SEED_Msk                (0xfffffffful << CRC_SEED_SEED_Pos)               /*!< CRC_T::SEED: SEED Mask                    */
+
+#define CRC_CHECKSUM_CHECKSUM_Pos        (0)                                               /*!< CRC_T::CHECKSUM: CHECKSUM Position        */
+#define CRC_CHECKSUM_CHECKSUM_Msk        (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos)       /*!< CRC_T::CHECKSUM: CHECKSUM Mask            */
+
+/**@}*/ /* CRC_CONST */
+/**@}*/ /* end of CRC register group */
+
+
+/*---------------------- Digital to Analog Converter -------------------------*/
+/**
+    @addtogroup DAC Digital to Analog Converter(DAC)
+    Memory Mapped Structure for DAC Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+/**
+ * @var DAC_T::CTL
+ * Offset: 0x00  DAC Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |DACEN     |DAC Enable Bit
+ * |        |          |0 = DAC is Disabled.
+ * |        |          |1 = DAC is Enabled.
+ * |[1]     |DACIEN    |DAC Interrupt Enable Bit
+ * |        |          |0 = Interrupt is Disabled.
+ * |        |          |1 = Interrupt is Enabled.
+ * |[2]     |DMAEN     |DMA Mode Enable Bit
+ * |        |          |0 = DMA mode Disabled.
+ * |        |          |1 = DMA mode Enabled.
+ * |[3]     |DMAURIEN  |DMA Under-Run Interrupt Enable Bit
+ * |        |          |0 = DMA under run interrupt Disabled.
+ * |        |          |1 = DMA under run interrupt Enabled.
+ * |[4]     |TRGEN     |Trigger Mode Enable Bit
+ * |        |          |0 = DAC event trigger mode Disabled.
+ * |        |          |1 = DAC event trigger mode Enabled.
+ * |[7:5]   |TRGSEL    |Trigger Source Selection
+ * |        |          |000 = Software trigger.
+ * |        |          |001 = External pin STDAC trigger.
+ * |        |          |010 = Timer 0 trigger.
+ * |        |          |011 = Timer 1 trigger.
+ * |        |          |100 = Timer 2 trigger.
+ * |        |          |101 = Timer 3 trigger.
+ * |        |          |110 = PWM0 trigger.
+ * |        |          |111 = PWM1 trigger.
+ * |[8]     |BYPASS    |Bypass Buffer Mode
+ * |        |          |0 = Output voltage buffer Enabled.
+ * |        |          |1 = Output voltage buffer Disabled.
+ * |[10]    |LALIGN    |DAC Data Left-Aligned Enabled Control
+ * |        |          |0 = Right alignment.
+ * |        |          |1 = Left alignment.
+ * |[13:12] |ETRGSEL   |External Pin Trigger Selection
+ * |        |          |00 = Low level trigger.
+ * |        |          |01 = High level trigger.
+ * |        |          |10 = Falling edge trigger.
+ * |        |          |11 = Rising edge trigger.
+ * @var DAC_T::SWTRG
+ * Offset: 0x04  DAC Software Trigger Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SWTRG     |Software Trigger
+ * |        |          |0 = Software trigger Disabled.
+ * |        |          |1 = Software trigger Enabled.
+ * |        |          |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
+ * @var DAC_T::DAT
+ * Offset: 0x08  DAC Data Holding Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |DAC_DAT   |DAC 12-Bit Holding Data
+ * |        |          |These bits are written by user software which specifies 12-bit conversion data for DAC output.
+ * |        |          |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
+ * |        |          |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
+ * |        |          |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
+ * @var DAC_T::DATOUT
+ * Offset: 0x0C  DAC Data Output Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |DATOUT    |DAC 12-Bit Output Data
+ * |        |          |These bits are current digital data for DAC output conversion.
+ * |        |          |It is loaded from DAC_DAT register and user cannot write it directly.
+ * @var DAC_T::STATUS
+ * Offset: 0x10  DAC Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |FINISH    |DAC Conversion Complete Finish Flag
+ * |        |          |0 = DAC is in conversion state.
+ * |        |          |1 = DAC conversion finish.
+ * |        |          |This bit set to 1 when conversion time counter counts to SETTLET.
+ * |        |          |It is cleared to 0 when DAC starts a new conversion.
+ * |        |          |User writes 1 to clear this bit to 0.
+ * |[1]     |DMAUDR    |DMA Under Run Interrupt Flag
+ * |        |          |0 = No DMA under-run error condition occurred.
+ * |        |          |1 = DMA under-run error condition occurred.
+ * |        |          |User writes 1 to clear this bit.
+ * |[8]     |BUSY      |DAC Busy Flag (Read Only)
+ * |        |          |0 = DAC is ready for next conversion.
+ * |        |          |1 = DAC is busy in conversion.
+ * |        |          |This is read only bit.
+ * @var DAC_T::TCTL
+ * Offset: 0x14  DAC Timing Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[9:0]   |SETTLET   |DAC Output Settling Time
+ * |        |          |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
+ * |        |          |For example, DAC controller clock speed is 72MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x48.
+ */
+
+    __IO uint32_t CTL;           /* Offset: 0x00  DAC Control Register                                               */
+    __IO uint32_t SWTRG;         /* Offset: 0x04  DAC Software Trigger Control Register                              */
+    __IO uint32_t DAT;           /* Offset: 0x08  DAC Data Holding Register                                          */
+    __I  uint32_t DATOUT;        /* Offset: 0x0C  DAC Data Output Register                                           */
+    __IO uint32_t STATUS;        /* Offset: 0x10  DAC Status Register                                                */
+    __IO uint32_t TCTL;          /* Offset: 0x14  DAC Timing Control Register                                        */
+
+} DAC_T;
+
+
+
+/**
+    @addtogroup DAC_CONST DAC Bit Field Definition
+    Constant Definitions for DAC Controller
+@{ */
+
+#define DAC_CTL_DACEN_Pos                (0)                                               /*!< DAC_T::CTL: DACEN Position                */
+#define DAC_CTL_DACEN_Msk                (0x1ul << DAC_CTL_DACEN_Pos)                      /*!< DAC_T::CTL: DACEN Mask                    */
+
+#define DAC_CTL_DACIEN_Pos               (1)                                               /*!< DAC_T::CTL: DACIEN Position               */
+#define DAC_CTL_DACIEN_Msk               (0x1ul << DAC_CTL_DACIEN_Pos)                     /*!< DAC_T::CTL: DACIEN Mask                   */
+
+#define DAC_CTL_DMAEN_Pos                (2)                                               /*!< DAC_T::CTL: DMAEN Position                */
+#define DAC_CTL_DMAEN_Msk                (0x1ul << DAC_CTL_DMAEN_Pos)                      /*!< DAC_T::CTL: DMAEN Mask                    */
+
+#define DAC_CTL_DMAURIEN_Pos             (3)                                               /*!< DAC_T::CTL: DMAURIEN Position             */
+#define DAC_CTL_DMAURIEN_Msk             (0x1ul << DAC_CTL_DMAURIEN_Pos)                   /*!< DAC_T::CTL: DMAURIEN Mask                 */
+
+#define DAC_CTL_TRGEN_Pos                (4)                                               /*!< DAC_T::CTL: TRGEN Position                */
+#define DAC_CTL_TRGEN_Msk                (0x1ul << DAC_CTL_TRGEN_Pos)                      /*!< DAC_T::CTL: TRGEN Mask                    */
+
+#define DAC_CTL_TRGSEL_Pos               (5)                                               /*!< DAC_T::CTL: TRGSEL Position               */
+#define DAC_CTL_TRGSEL_Msk               (0x7ul << DAC_CTL_TRGSEL_Pos)                     /*!< DAC_T::CTL: TRGSEL Mask                   */
+
+#define DAC_CTL_BYPASS_Pos               (8)                                               /*!< DAC_T::CTL: BYPASS Position               */
+#define DAC_CTL_BYPASS_Msk               (0x1ul << DAC_CTL_BYPASS_Pos)                     /*!< DAC_T::CTL: BYPASS Mask                   */
+
+#define DAC_CTL_LALIGN_Pos               (10)                                              /*!< DAC_T::CTL: LALIGN Position               */
+#define DAC_CTL_LALIGN_Msk               (0x1ul << DAC_CTL_LALIGN_Pos)                     /*!< DAC_T::CTL: LALIGN Mask                   */
+
+#define DAC_CTL_ETRGSEL_Pos              (12)                                              /*!< DAC_T::CTL: ETRGSEL Position              */
+#define DAC_CTL_ETRGSEL_Msk              (0x3ul << DAC_CTL_ETRGSEL_Pos)                    /*!< DAC_T::CTL: ETRGSEL Mask                  */
+
+#define DAC_SWTRG_SWTRG_Pos              (0)                                               /*!< DAC_T::SWTRG: SWTRG Position              */
+#define DAC_SWTRG_SWTRG_Msk              (0x1ul << DAC_SWTRG_SWTRG_Pos)                    /*!< DAC_T::SWTRG: SWTRG Mask                  */
+
+#define DAC_DAT_DAC_DAT_Pos              (0)                                               /*!< DAC_T::DAT: DAC_DAT Position              */
+#define DAC_DAT_DAC_DAT_Msk              (0xfffful << DAC_DAT_DAC_DAT_Pos)                 /*!< DAC_T::DAT: DAC_DAT Mask                  */
+
+#define DAC_DATOUT_DATOUT_Pos            (0)                                               /*!< DAC_T::DATOUT: DATOUT Position            */
+#define DAC_DATOUT_DATOUT_Msk            (0xffful << DAC_DATOUT_DATOUT_Pos)                /*!< DAC_T::DATOUT: DATOUT Mask                */
+
+#define DAC_STATUS_FINISH_Pos            (0)                                               /*!< DAC_T::STATUS: FINISH Position            */
+#define DAC_STATUS_FINISH_Msk            (0x1ul << DAC_STATUS_FINISH_Pos)                  /*!< DAC_T::STATUS: FINISH Mask                */
+
+#define DAC_STATUS_DMAUDR_Pos            (1)                                               /*!< DAC_T::STATUS: DMAUDR Position            */
+#define DAC_STATUS_DMAUDR_Msk            (0x1ul << DAC_STATUS_DMAUDR_Pos)                  /*!< DAC_T::STATUS: DMAUDR Mask                */
+
+#define DAC_STATUS_BUSY_Pos              (8)                                               /*!< DAC_T::STATUS: BUSY Position              */
+#define DAC_STATUS_BUSY_Msk              (0x1ul << DAC_STATUS_BUSY_Pos)                    /*!< DAC_T::STATUS: BUSY Mask                  */
+
+#define DAC_TCTL_SETTLET_Pos             (0)                                               /*!< DAC_T::TCTL: SETTLET Position             */
+#define DAC_TCTL_SETTLET_Msk             (0x3fful << DAC_TCTL_SETTLET_Pos)                 /*!< DAC_T::TCTL: SETTLET Mask                 */
+
+/**@}*/ /* DAC_CONST */
+/**@}*/ /* end of DAC register group */
+
+
+/*---------------------- External Bus Interface Controller -------------------------*/
+/**
+    @addtogroup EBI External Bus Interface Controller(EBI)
+    Memory Mapped Structure for EBI Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var EBI_T::CTL0
+ * Offset: 0x00  External Bus Interface Bank0 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |EN        |EBI Enable Bit
+ * |        |          |This bit is the functional enable bit for EBI.
+ * |        |          |0 = EBI function Disabled.
+ * |        |          |1 = EBI function Enabled.
+ * |[1]     |DW16      |EBI Data Width 16-Bit Select
+ * |        |          |This bit defines if the EBI data width is 8-bit or 16-bit.
+ * |        |          |0 = EBI data width is 8-bit.
+ * |        |          |1 = EBI data width is 16-bit.
+ * |[2]     |CSPOLINV  |Chip Select Pin Polar Inverse
+ * |        |          |This bit defines the active level of EBI chip select pin (EBI_nCS).
+ * |        |          |0 = Chip select pin (EBI_nCS) is active low.
+ * |        |          |1 = Chip select pin (EBI_nCS) is active high.
+ * |[10:8]  |MCLKDIV   |External Output Clock Divider
+ * |        |          |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+ * |        |          |000 = HCLK/1.
+ * |        |          |001 = HCLK/2.
+ * |        |          |010 = HCLK/4.
+ * |        |          |011 = HCLK/8.
+ * |        |          |100 = HCLK/16.
+ * |        |          |101 = HCLK/32.
+ * |        |          |110 = Reserved.
+ * |        |          |111 = Reserved.
+ * |[18:16] |TALE      |Extend Time Of ALE
+ * |        |          |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+ * |        |          |tALE = (TALE+1)*EBI_MCLK.
+ * |        |          |Note: This field only available in EBI_CTL0 register
+ * |[24]    |WBUFEN    |EBI Write Buffer Enable Bit
+ * |        |          |0 = EBI write buffer Disabled.
+ * |        |          |1 = EBI write buffer Enabled.
+ * |        |          |Note: This bit only available in EBI_CTL0 register
+ * @var EBI_T::TCTL0
+ * Offset: 0x04  External Bus Interface Bank0 Timing Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:3]   |TACC      |EBI Data Access Time
+ * |        |          |TACC define data access time (tACC).
+ * |        |          |tACC = (TACC +1) * EBI_MCLK.
+ * |[10:8]  |TAHD      |EBI Data Access Hold Time
+ * |        |          |TAHD define data access hold time (tAHD).
+ * |        |          |tAHD = (TAHD +1) * EBI_MCLK.
+ * |[15:12] |W2X       |Idle Cycle After Write
+ * |        |          |This field defines the number of W2X idle cycle.
+ * |        |          |W2X idle cycle = (W2X * EBI_MCLK).
+ * |        |          |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+ * |[22]    |RAHDOFF   |Access Hold Time Disable Control When Read
+ * |        |          |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+ * |        |          |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+ * |[23]    |WAHDOFF   |Access Hold Time Disable Control When Write
+ * |        |          |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+ * |        |          |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+ * |[27:24] |R2R       |Idle Cycle Between Read-To-Read
+ * |        |          |This field defines the number of R2R idle cycle.
+ * |        |          |R2R idle cycle = (R2R * EBI_MCLK).
+ * |        |          |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+ * @var EBI_T::CTL1
+ * Offset: 0x10  External Bus Interface Bank1 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |EN        |EBI Enable Bit
+ * |        |          |This bit is the functional enable bit for EBI.
+ * |        |          |0 = EBI function Disabled.
+ * |        |          |1 = EBI function Enabled.
+ * |[1]     |DW16      |EBI Data Width 16-Bit Select
+ * |        |          |This bit defines if the EBI data width is 8-bit or 16-bit.
+ * |        |          |0 = EBI data width is 8-bit.
+ * |        |          |1 = EBI data width is 16-bit.
+ * |[2]     |CSPOLINV  |Chip Select Pin Polar Inverse
+ * |        |          |This bit defines the active level of EBI chip select pin (EBI_nCS).
+ * |        |          |0 = Chip select pin (EBI_nCS) is active low.
+ * |        |          |1 = Chip select pin (EBI_nCS) is active high.
+ * |[10:8]  |MCLKDIV   |External Output Clock Divider
+ * |        |          |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+ * |        |          |000 = HCLK/1.
+ * |        |          |001 = HCLK/2.
+ * |        |          |010 = HCLK/4.
+ * |        |          |011 = HCLK/8.
+ * |        |          |100 = HCLK/16.
+ * |        |          |101 = HCLK/32.
+ * |        |          |110 = Reserved.
+ * |        |          |111 = Reserved.
+ * |[18:16] |TALE      |Extend Time Of ALE
+ * |        |          |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+ * |        |          |tALE = (TALE+1)*EBI_MCLK.
+ * |        |          |Note: This field only available in EBI_CTL0 register
+ * |[24]    |WBUFEN    |EBI Write Buffer Enable Bit
+ * |        |          |0 = EBI write buffer Disabled.
+ * |        |          |1 = EBI write buffer Enabled.
+ * |        |          |Note: This bit only available in EBI_CTL0 register
+ * @var EBI_T::TCTL1
+ * Offset: 0x14  External Bus Interface Bank1 Timing Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:3]   |TACC      |EBI Data Access Time
+ * |        |          |TACC define data access time (tACC).
+ * |        |          |tACC = (TACC +1) * EBI_MCLK.
+ * |[10:8]  |TAHD      |EBI Data Access Hold Time
+ * |        |          |TAHD define data access hold time (tAHD).
+ * |        |          |tAHD = (TAHD +1) * EBI_MCLK.
+ * |[15:12] |W2X       |Idle Cycle After Write
+ * |        |          |This field defines the number of W2X idle cycle.
+ * |        |          |W2X idle cycle = (W2X * EBI_MCLK).
+ * |        |          |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+ * |[22]    |RAHDOFF   |Access Hold Time Disable Control When Read
+ * |        |          |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+ * |        |          |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+ * |[23]    |WAHDOFF   |Access Hold Time Disable Control When Write
+ * |        |          |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+ * |        |          |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+ * |[27:24] |R2R       |Idle Cycle Between Read-To-Read
+ * |        |          |This field defines the number of R2R idle cycle.
+ * |        |          |R2R idle cycle = (R2R * EBI_MCLK).
+ * |        |          |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+ */
+
+    __IO uint32_t CTL0;          /* Offset: 0x00  External Bus Interface Bank0 Control Register                      */
+    __IO uint32_t TCTL0;         /* Offset: 0x04  External Bus Interface Bank0 Timing Control Register               */
+    __I  uint32_t RESERVE0[2];  
+    __IO uint32_t CTL1;          /* Offset: 0x10  External Bus Interface Bank1 Control Register                      */
+    __IO uint32_t TCTL1;         /* Offset: 0x14  External Bus Interface Bank1 Timing Control Register               */
+
+} EBI_T;
+
+
+
+/**
+    @addtogroup EBI_CONST EBI Bit Field Definition
+    Constant Definitions for EBI Controller
+@{ */
+
+#define EBI_CTL0_EN_Pos                  (0)                                               /*!< EBI_T::CTL0: EN Position                  */
+#define EBI_CTL0_EN_Msk                  (0x1ul << EBI_CTL0_EN_Pos)                        /*!< EBI_T::CTL0: EN Mask                      */
+
+#define EBI_CTL0_DW16_Pos                (1)                                               /*!< EBI_T::CTL0: DW16 Position                */
+#define EBI_CTL0_DW16_Msk                (0x1ul << EBI_CTL0_DW16_Pos)                      /*!< EBI_T::CTL0: DW16 Mask                    */
+
+#define EBI_CTL0_CSPOLINV_Pos            (2)                                               /*!< EBI_T::CTL0: CSPOLINV Position            */
+#define EBI_CTL0_CSPOLINV_Msk            (0x1ul << EBI_CTL0_CSPOLINV_Pos)                  /*!< EBI_T::CTL0: CSPOLINV Mask                */
+
+#define EBI_CTL0_MCLKDIV_Pos             (8)                                               /*!< EBI_T::CTL0: MCLKDIV Position             */
+#define EBI_CTL0_MCLKDIV_Msk             (0x7ul << EBI_CTL0_MCLKDIV_Pos)                   /*!< EBI_T::CTL0: MCLKDIV Mask                 */
+
+#define EBI_CTL0_TALE_Pos                (16)                                              /*!< EBI_T::CTL0: TALE Position                */
+#define EBI_CTL0_TALE_Msk                (0x7ul << EBI_CTL0_TALE_Pos)                      /*!< EBI_T::CTL0: TALE Mask                    */
+
+#define EBI_CTL0_WBUFEN_Pos              (24)                                              /*!< EBI_T::CTL0: WBUFEN Position              */
+#define EBI_CTL0_WBUFEN_Msk              (0x1ul << EBI_CTL0_WBUFEN_Pos)                    /*!< EBI_T::CTL0: WBUFEN Mask                  */
+
+#define EBI_TCTL0_TACC_Pos               (3)                                               /*!< EBI_T::TCTL0: TACC Position               */
+#define EBI_TCTL0_TACC_Msk               (0x1ful << EBI_TCTL0_TACC_Pos)                    /*!< EBI_T::TCTL0: TACC Mask                   */
+
+#define EBI_TCTL0_TAHD_Pos               (8)                                               /*!< EBI_T::TCTL0: TAHD Position               */
+#define EBI_TCTL0_TAHD_Msk               (0x7ul << EBI_TCTL0_TAHD_Pos)                     /*!< EBI_T::TCTL0: TAHD Mask                   */
+
+#define EBI_TCTL0_W2X_Pos                (12)                                              /*!< EBI_T::TCTL0: W2X Position                */
+#define EBI_TCTL0_W2X_Msk                (0xful << EBI_TCTL0_W2X_Pos)                      /*!< EBI_T::TCTL0: W2X Mask                    */
+
+#define EBI_TCTL0_RAHDOFF_Pos            (22)                                              /*!< EBI_T::TCTL0: RAHDOFF Position            */
+#define EBI_TCTL0_RAHDOFF_Msk            (0x1ul << EBI_TCTL0_RAHDOFF_Pos)                  /*!< EBI_T::TCTL0: RAHDOFF Mask                */
+
+#define EBI_TCTL0_WAHDOFF_Pos            (23)                                              /*!< EBI_T::TCTL0: WAHDOFF Position            */
+#define EBI_TCTL0_WAHDOFF_Msk            (0x1ul << EBI_TCTL0_WAHDOFF_Pos)                  /*!< EBI_T::TCTL0: WAHDOFF Mask                */
+
+#define EBI_TCTL0_R2R_Pos                (24)                                              /*!< EBI_T::TCTL0: R2R Position                */
+#define EBI_TCTL0_R2R_Msk                (0xful << EBI_TCTL0_R2R_Pos)                      /*!< EBI_T::TCTL0: R2R Mask                    */
+
+#define EBI_CTL1_EN_Pos                  (0)                                               /*!< EBI_T::CTL1: EN Position                  */
+#define EBI_CTL1_EN_Msk                  (0x1ul << EBI_CTL1_EN_Pos)                        /*!< EBI_T::CTL1: EN Mask                      */
+
+#define EBI_CTL1_DW16_Pos                (1)                                               /*!< EBI_T::CTL1: DW16 Position                */
+#define EBI_CTL1_DW16_Msk                (0x1ul << EBI_CTL1_DW16_Pos)                      /*!< EBI_T::CTL1: DW16 Mask                    */
+
+#define EBI_CTL1_CSPOLINV_Pos            (2)                                               /*!< EBI_T::CTL1: CSPOLINV Position            */
+#define EBI_CTL1_CSPOLINV_Msk            (0x1ul << EBI_CTL1_CSPOLINV_Pos)                  /*!< EBI_T::CTL1: CSPOLINV Mask                */
+
+#define EBI_CTL1_MCLKDIV_Pos             (8)                                               /*!< EBI_T::CTL1: MCLKDIV Position             */
+#define EBI_CTL1_MCLKDIV_Msk             (0x7ul << EBI_CTL1_MCLKDIV_Pos)                   /*!< EBI_T::CTL1: MCLKDIV Mask                 */
+
+#define EBI_CTL1_TALE_Pos                (16)                                              /*!< EBI_T::CTL1: TALE Position                */
+#define EBI_CTL1_TALE_Msk                (0x7ul << EBI_CTL1_TALE_Pos)                      /*!< EBI_T::CTL1: TALE Mask                    */
+
+#define EBI_CTL1_WBUFEN_Pos              (24)                                              /*!< EBI_T::CTL1: WBUFEN Position              */
+#define EBI_CTL1_WBUFEN_Msk              (0x1ul << EBI_CTL1_WBUFEN_Pos)                    /*!< EBI_T::CTL1: WBUFEN Mask                  */
+
+#define EBI_TCTL1_TACC_Pos               (3)                                               /*!< EBI_T::TCTL1: TACC Position               */
+#define EBI_TCTL1_TACC_Msk               (0x1ful << EBI_TCTL1_TACC_Pos)                    /*!< EBI_T::TCTL1: TACC Mask                   */
+
+#define EBI_TCTL1_TAHD_Pos               (8)                                               /*!< EBI_T::TCTL1: TAHD Position               */
+#define EBI_TCTL1_TAHD_Msk               (0x7ul << EBI_TCTL1_TAHD_Pos)                     /*!< EBI_T::TCTL1: TAHD Mask                   */
+
+#define EBI_TCTL1_W2X_Pos                (12)                                              /*!< EBI_T::TCTL1: W2X Position                */
+#define EBI_TCTL1_W2X_Msk                (0xful << EBI_TCTL1_W2X_Pos)                      /*!< EBI_T::TCTL1: W2X Mask                    */
+
+#define EBI_TCTL1_RAHDOFF_Pos            (22)                                              /*!< EBI_T::TCTL1: RAHDOFF Position            */
+#define EBI_TCTL1_RAHDOFF_Msk            (0x1ul << EBI_TCTL1_RAHDOFF_Pos)                  /*!< EBI_T::TCTL1: RAHDOFF Mask                */
+
+#define EBI_TCTL1_WAHDOFF_Pos            (23)                                              /*!< EBI_T::TCTL1: WAHDOFF Position            */
+#define EBI_TCTL1_WAHDOFF_Msk            (0x1ul << EBI_TCTL1_WAHDOFF_Pos)                  /*!< EBI_T::TCTL1: WAHDOFF Mask                */
+
+#define EBI_TCTL1_R2R_Pos                (24)                                              /*!< EBI_T::TCTL1: R2R Position                */
+#define EBI_TCTL1_R2R_Msk                (0xful << EBI_TCTL1_R2R_Pos)                      /*!< EBI_T::TCTL1: R2R Mask                    */
+
+/**@}*/ /* EBI_CONST */
+/**@}*/ /* end of EBI register group */
+
+
+/*---------------------- Flash Memory Controller -------------------------*/
+/**
+    @addtogroup FMC Flash Memory Controller(FMC)
+    Memory Mapped Structure for FMC Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var FMC_T::ISPCTL
+ * Offset: 0x00  ISP Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ISPEN     |ISP Enable Bit (Write Protect)
+ * |        |          |ISP function enable bit. Set this bit to enable ISP function.
+ * |        |          |0 = ISP function Disabled.
+ * |        |          |1 = ISP function Enabled.
+ * |[1]     |BS        |Boot Select (Write Protect)
+ * |        |          |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively.
+ * |        |          |This bit also functions as chip booting status flag, which can be used to check where chip booted from.
+ * |        |          |This bit is initiated with the inverted value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
+ * |        |          |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
+ * |        |          |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
+ * |[3]     |APUEN     |APROM Update Enable Bit (Write Protect)
+ * |        |          |0 = APROM cannot be updated when the chip runs in APROM.
+ * |        |          |1 = APROM can be updated when the chip runs in APROM.
+ * |[4]     |CFGUEN    |CONFIG Update Enable Bit (Write Protect)
+ * |        |          |0 = CONFIG cannot be updated.
+ * |        |          |1 = CONFIG can be updated.
+ * |[5]     |LDUEN     |LDROM Update Enable Bit (Write Protect)
+ * |        |          |LDROM update enable bit.
+ * |        |          |0 = LDROM cannot be updated.
+ * |        |          |1 = LDROM can be updated.
+ * |[6]     |ISPFF     |ISP Fail Flag (Write Protect)
+ * |        |          |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * |        |          |This bit needs to be cleared by writing 1 to it.
+ * |        |          |(1) APROM writes to itself if APUEN is set to 0.
+ * |        |          |(2) LDROM writes to itself if LDUEN is set to 0.
+ * |        |          |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+ * |        |          |(4) SPROM is erased/programmed if SPUEN is set to 0
+ * |        |          |(5) SPROM is programmed at SPROM secured mode.
+ * |        |          |(6) Page Erase command at LOCK mode with ICE connection
+ * |        |          |(7) Erase or Program command at brown-out detected
+ * |        |          |(8) Destination address is illegal, such as over an available range.
+ * |        |          |(9) Invalid ISP commands
+ * |[16]    |BL        |Boot Loader Booting (Write Protect)
+ * |        |          |This bit is initiated with the inverted value of MBS (CONFIG0[5]).
+ * |        |          |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded.
+ * |        |          |This bit is used to check chip boot from Boot Loader or not.
+ * |        |          |User should keep original value of this bit when updating FMC_ISPCTL register.
+ * |        |          |0 = Booting from APROM or LDROM.
+ * |        |          |1 = Booting from Boot Loader.
+ * @var FMC_T::ISPADDR
+ * Offset: 0x04  ISP Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |ISPADDR   |ISP Address
+ * |        |          |The NuMicro M451 series is equipped with embedded flash.
+ * |        |          |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation.
+ * |        |          |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
+ * |        |          |For Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 Kbytes alignment is necessary for checksum calculation.
+ * @var FMC_T::ISPDAT
+ * Offset: 0x08  ISP Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |ISPDAT    |ISP Data
+ * |        |          |Write data to this register before ISP program operation.
+ * |        |          |Read data from this register after ISP read operation.
+ * |        |          |For Run Checksum Calculation command, ISPDAT is the memory size (byte) and 2 Kbytes alignment.
+ * |        |          |For ISP Read Checksum command, ISPDAT is the checksum result.
+ * |        |          |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, (2) the memory range for checksum calculation is incorrect, or (3) all of data are 0.
+ * @var FMC_T::ISPCMD
+ * Offset: 0x0C  ISP CMD Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[6:0]   |CMD       |ISP CMD
+ * |        |          |ISP command table is shown below:
+ * |        |          |0x00= FLASH Read.
+ * |        |          |0x04= Read Unique ID.
+ * |        |          |0x0B= Read Company ID.
+ * |        |          |0x0C= Read Device ID.
+ * |        |          |0x0D= Read Checksum.
+ * |        |          |0x21= FLASH 32-bit Program.
+ * |        |          |0x22= FLASH Page Erase.
+ * |        |          |0x27= FLASH Multi-Word Program.
+ * |        |          |0x2D= Run Checksum Calculation.
+ * |        |          |0x2E= Vector Remap.
+ * |        |          |0x61= FLASH 64-bit Program.
+ * |        |          |The other commands are invalid.
+ * @var FMC_T::ISPTRG
+ * Offset: 0x10  ISP Trigger Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ISPGO     |ISP Start Trigger (Write Protect)
+ * |        |          |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
+ * |        |          |0 = ISP operation is finished.
+ * |        |          |1 = ISP is progressed.
+ * @var FMC_T::DFBA
+ * Offset: 0x14  Data Flash Base Address
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |DFBA      |Data Flash Base Address
+ * |        |          |This register indicates Data Flash start address. It is a read only register.
+ * |        |          |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
+ * |        |          |This register is valid when DFEN (CONFIG0[0]) =0 .
+ * @var FMC_T::FTCTL
+ * Offset: 0x18  Flash Access Time Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[6:4]   |FOM       |Frequency Optimization Mode (Write Protect)
+ * |        |          |The NuMicro M451 series support adjustable flash access timing to optimize the flash access cycles in different working frequency.
+ * |        |          |001 = Frequency <= 12MHz.
+ * |        |          |010 = Frequency <= 36MHz.
+ * |        |          |100 = Frequency <= 60MHz.
+ * |        |          |Others = Frequency <= 72MHz.
+ * @var FMC_T::ISPSTS
+ * Offset: 0x40  ISP Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ISPBUSY   |ISP Busy Flag (Read Only)
+ * |        |          |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
+ * |        |          |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
+ * |        |          |0 = ISP operation is finished.
+ * |        |          |1 = ISP is progressed.
+ * |[2:1]   |CBS       |Boot Selection Of CONFIG (Read Only)
+ * |        |          |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
+ * |        |          |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
+ * |        |          |00 = LDROM with IAP mode.
+ * |        |          |01 = LDROM without IAP mode.
+ * |        |          |10 = APROM with IAP mode.
+ * |        |          |11 = APROM without IAP mode.
+ * |[3]     |MBS       |Boot From Boot Loader Selection Flag (Read Only)
+ * |        |          |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
+ * |        |          |0 = Booting from Boot Loader.
+ * |        |          |1 = Booting
+ * |        |          |from LDROM/APROM.(see CBS bit setting)
+ * |[5]     |PGFF      |Flash Program With Fast Verification Flag (Read Only)
+ * |        |          |This bit is set if data is mismatched at ISP programming verification.
+ * |        |          |This bit is clear by performing ISP flash erase or ISP read CID operation.
+ * |        |          |0 = Flash Program is success.
+ * |        |          |1 = Flash Program is fail. Program data is different with data in the flash memory
+ * |[6]     |ISPFF     |ISP Fail Flag (Write Protect)
+ * |        |          |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
+ * |        |          |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * |        |          |(1) APROM writes to itself if APUEN is set to 0.
+ * |        |          |(2) LDROM writes to itself if LDUEN is set to 0.
+ * |        |          |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+ * |        |          |(4) SPROM is erased/programmed if SPUEN is set to 0
+ * |        |          |(5) SPROM is programmed at SPROM secured mode.
+ * |        |          |(6) Page Erase command at LOCK mode with ICE connection
+ * |        |          |(7) Erase or Program command at brown-out detected
+ * |        |          |(8) Destination address is illegal, such as over an available range.
+ * |        |          |(9) Invalid ISP commands
+ * |[23:9]  |VECMAP    |Vector Page Mapping Address (Read Only)
+ * |        |          |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
+ * @var FMC_T::MPDAT0
+ * Offset: 0x80  ISP Data0 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |ISPDAT0   |ISP Data 0
+ * |        |          |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
+ * @var FMC_T::MPDAT1
+ * Offset: 0x84  ISP Data1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |ISPDAT1   |ISP Data 1
+ * |        |          |This register is the second 32-bit data for 64-bit/multi-word programming.
+ * @var FMC_T::MPDAT2
+ * Offset: 0x88  ISP Data2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |ISPDAT2   |ISP Data 2
+ * |        |          |This register is the third 32-bit data for multi-word programming.
+ * @var FMC_T::MPDAT3
+ * Offset: 0x8C  ISP Data3 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |ISPDAT3   |ISP Data 3
+ * |        |          |This register is the fourth 32-bit data for multi-word programming.
+ * @var FMC_T::MPSTS
+ * Offset: 0xC0  ISP Multi-Program Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |MPBUSY    |ISP Multi-Word Program Busy Flag (Read Only)
+ * |        |          |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
+ * |        |          |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
+ * |        |          |0 = ISP Multi-Word program operation is finished.
+ * |        |          |1 = ISP Multi-Word program operation
+ * |        |          |is progressed.
+ * |[1]     |PPGO      |ISP Multi-Program Status (Read Only)
+ * |        |          |0 = ISP multi-word program operation is not active.
+ * |        |          |1 = ISP multi-word program operation is in progress.
+ * |[2]     |ISPFF     |ISP Fail Flag (Read Only)
+ * |        |          |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
+ * |        |          |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * |        |          |(1) APROM writes to itself if APUEN is set to 0.
+ * |        |          |(2) LDROM writes to itself if LDUEN is set to 0.
+ * |        |          |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+ * |        |          |(4) SPROM is erased/programmed if SPUEN is set to 0
+ * |        |          |(5) SPROM is programmed at SPROM secured mode.
+ * |        |          |(6) Page Erase command at LOCK mode with ICE connection
+ * |        |          |(7) Erase or Program command at brown-out detected
+ * |        |          |(8) Destination address is illegal, such as over an available range.
+ * |        |          |(9) Invalid ISP commands
+ * |[4]     |D0        |ISP DATA 0 Flag (Read Only)
+ * |        |          |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
+ * |        |          |0 = FMC_MPDAT0 register is empty, or program to flash complete.
+ * |        |          |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
+ * |[5]     |D1        |ISP DATA 1 Flag (Read Only)
+ * |        |          |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
+ * |        |          |0 = FMC_MPDAT1 register is empty, or program to flash complete.
+ * |        |          |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
+ * |[6]     |D2        |ISP DATA 2 Flag (Read Only)
+ * |        |          |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
+ * |        |          |0 = FMC_MPDAT2 register is empty, or program to flash complete.
+ * |        |          |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
+ * |[7]     |D3        |ISP DATA 3 Flag (Read Only)
+ * |        |          |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
+ * |        |          |0 = FMC_MPDAT3 register is empty, or program to flash complete.
+ * |        |          |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
+ * @var FMC_T::MPADDR
+ * Offset: 0xC4  ISP Multi-Program Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |MPADDR    |ISP Multi-Word Program Address
+ * |        |          |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
+ * |        |          |MPADDR will keep the final ISP address when ISP multi-word program is complete.
+    */
+
+    __IO uint32_t ISPCTL;        /* Offset: 0x00  ISP Control Register                                               */
+    __IO uint32_t ISPADDR;       /* Offset: 0x04  ISP Address Register                                               */
+    __IO uint32_t ISPDAT;        /* Offset: 0x08  ISP Data Register                                                  */
+    __IO uint32_t ISPCMD;        /* Offset: 0x0C  ISP CMD Register                                                   */
+    __IO uint32_t ISPTRG;        /* Offset: 0x10  ISP Trigger Control Register                                       */
+    __I  uint32_t DFBA;          /* Offset: 0x14  Data Flash Base Address                                            */
+    __IO uint32_t FTCTL;         /* Offset: 0x18  Flash Access Time Control Register                                 */
+    __I  uint32_t RESERVE0[9];  
+    __I  uint32_t ISPSTS;        /* Offset: 0x40  ISP Status Register                                                */
+    __I  uint32_t RESERVE1[15]; 
+    __IO uint32_t MPDAT0;        /* Offset: 0x80  ISP Data0 Register                                                 */
+    __IO uint32_t MPDAT1;        /* Offset: 0x84  ISP Data1 Register                                                 */
+    __IO uint32_t MPDAT2;        /* Offset: 0x88  ISP Data2 Register                                                 */
+    __IO uint32_t MPDAT3;        /* Offset: 0x8C  ISP Data3 Register                                                 */
+    __I  uint32_t RESERVE2[12]; 
+    __I  uint32_t MPSTS;         /* Offset: 0xC0  ISP Multi-Program Status Register                                  */
+    __I  uint32_t MPADDR;        /* Offset: 0xC4  ISP Multi-Program Address Register                                 */
+
+} FMC_T;
+
+
+
+
+/**
+    @addtogroup FMC_CONST FMC Bit Field Definition
+    Constant Definitions for FMC Controller
+@{ */
+
+#define FMC_ISPCTL_ISPEN_Pos             (0)                                               /*!< FMC_T::ISPCTL: ISPEN Position             */
+#define FMC_ISPCTL_ISPEN_Msk             (0x1ul << FMC_ISPCTL_ISPEN_Pos)                   /*!< FMC_T::ISPCTL: ISPEN Mask                 */
+
+#define FMC_ISPCTL_BS_Pos                (1)                                               /*!< FMC_T::ISPCTL: BS Position                */
+#define FMC_ISPCTL_BS_Msk                (0x1ul << FMC_ISPCTL_BS_Pos)                      /*!< FMC_T::ISPCTL: BS Mask                    */
+
+#define FMC_ISPCTL_APUEN_Pos             (3)                                               /*!< FMC_T::ISPCTL: APUEN Position             */
+#define FMC_ISPCTL_APUEN_Msk             (0x1ul << FMC_ISPCTL_APUEN_Pos)                   /*!< FMC_T::ISPCTL: APUEN Mask                 */
+
+#define FMC_ISPCTL_CFGUEN_Pos            (4)                                               /*!< FMC_T::ISPCTL: CFGUEN Position            */
+#define FMC_ISPCTL_CFGUEN_Msk            (0x1ul << FMC_ISPCTL_CFGUEN_Pos)                  /*!< FMC_T::ISPCTL: CFGUEN Mask                */
+
+#define FMC_ISPCTL_LDUEN_Pos             (5)                                               /*!< FMC_T::ISPCTL: LDUEN Position             */
+#define FMC_ISPCTL_LDUEN_Msk             (0x1ul << FMC_ISPCTL_LDUEN_Pos)                   /*!< FMC_T::ISPCTL: LDUEN Mask                 */
+
+#define FMC_ISPCTL_ISPFF_Pos             (6)                                               /*!< FMC_T::ISPCTL: ISPFF Position             */
+#define FMC_ISPCTL_ISPFF_Msk             (0x1ul << FMC_ISPCTL_ISPFF_Pos)                   /*!< FMC_T::ISPCTL: ISPFF Mask                 */
+
+#define FMC_ISPCTL_BL_Pos                (16)                                              /*!< FMC_T::ISPCTL: BL Position                */
+#define FMC_ISPCTL_BL_Msk                (0x1ul << FMC_ISPCTL_BL_Pos)                      /*!< FMC_T::ISPCTL: BL Mask                    */
+
+#define FMC_ISPADDR_ISPADDR_Pos          (0)                                               /*!< FMC_T::ISPADDR: ISPADDR Position          */
+#define FMC_ISPADDR_ISPADDR_Msk          (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)         /*!< FMC_T::ISPADDR: ISPADDR Mask              */
+
+#define FMC_ISPDAT_ISPDAT_Pos            (0)                                               /*!< FMC_T::ISPDAT: ISPDAT Position            */
+#define FMC_ISPDAT_ISPDAT_Msk            (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)           /*!< FMC_T::ISPDAT: ISPDAT Mask                */
+
+#define FMC_ISPCMD_CMD_Pos               (0)                                               /*!< FMC_T::ISPCMD: CMD Position               */
+#define FMC_ISPCMD_CMD_Msk               (0x7ful << FMC_ISPCMD_CMD_Pos)                    /*!< FMC_T::ISPCMD: CMD Mask                   */
+
+#define FMC_ISPTRG_ISPGO_Pos             (0)                                               /*!< FMC_T::ISPTRG: ISPGO Position             */
+#define FMC_ISPTRG_ISPGO_Msk             (0x1ul << FMC_ISPTRG_ISPGO_Pos)                   /*!< FMC_T::ISPTRG: ISPGO Mask                 */
+
+#define FMC_DFBA_DFBA_Pos                (0)                                               /*!< FMC_T::DFBA: DFBA Position                */
+#define FMC_DFBA_DFBA_Msk                (0xfffffffful << FMC_DFBA_DFBA_Pos)               /*!< FMC_T::DFBA: DFBA Mask                    */
+
+#define FMC_FTCTL_FOM_Pos                (4)                                               /*!< FMC_T::FTCTL: FOM Position                */
+#define FMC_FTCTL_FOM_Msk                (0x7ul << FMC_FTCTL_FOM_Pos)                      /*!< FMC_T::FTCTL: FOM Mask                    */
+
+#define FMC_ISPSTS_ISPBUSY_Pos           (0)                                               /*!< FMC_T::ISPSTS: ISPBUSY Position           */
+#define FMC_ISPSTS_ISPBUSY_Msk           (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)                 /*!< FMC_T::ISPSTS: ISPBUSY Mask               */
+
+#define FMC_ISPSTS_CBS_Pos               (1)                                               /*!< FMC_T::ISPSTS: CBS Position               */
+#define FMC_ISPSTS_CBS_Msk               (0x3ul << FMC_ISPSTS_CBS_Pos)                     /*!< FMC_T::ISPSTS: CBS Mask                   */
+
+#define FMC_ISPSTS_MBS_Pos               (3)                                               /*!< FMC_T::ISPSTS: MBS Position               */
+#define FMC_ISPSTS_MBS_Msk               (0x1ul << FMC_ISPSTS_MBS_Pos)                     /*!< FMC_T::ISPSTS: MBS Mask                   */
+
+#define FMC_ISPSTS_PGFF_Pos              (5)                                               /*!< FMC_T::ISPSTS: PGFF Position              */
+#define FMC_ISPSTS_PGFF_Msk              (0x1ul << FMC_ISPSTS_PGFF_Pos)                    /*!< FMC_T::ISPSTS: PGFF Mask                  */
+
+#define FMC_ISPSTS_ISPFF_Pos             (6)                                               /*!< FMC_T::ISPSTS: ISPFF Position             */
+#define FMC_ISPSTS_ISPFF_Msk             (0x1ul << FMC_ISPSTS_ISPFF_Pos)                   /*!< FMC_T::ISPSTS: ISPFF Mask                 */
+
+#define FMC_ISPSTS_VECMAP_Pos            (9)                                               /*!< FMC_T::ISPSTS: VECMAP Position            */
+#define FMC_ISPSTS_VECMAP_Msk            (0x7ffful << FMC_ISPSTS_VECMAP_Pos)               /*!< FMC_T::ISPSTS: VECMAP Mask                */
+
+#define FMC_MPDAT0_ISPDAT0_Pos           (0)                                               /*!< FMC_T::MPDAT0: ISPDAT0 Position           */
+#define FMC_MPDAT0_ISPDAT0_Msk           (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos)          /*!< FMC_T::MPDAT0: ISPDAT0 Mask               */
+
+#define FMC_MPDAT1_ISPDAT1_Pos           (0)                                               /*!< FMC_T::MPDAT1: ISPDAT1 Position           */
+#define FMC_MPDAT1_ISPDAT1_Msk           (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos)          /*!< FMC_T::MPDAT1: ISPDAT1 Mask               */
+
+#define FMC_MPDAT2_ISPDAT2_Pos           (0)                                               /*!< FMC_T::MPDAT2: ISPDAT2 Position           */
+#define FMC_MPDAT2_ISPDAT2_Msk           (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos)          /*!< FMC_T::MPDAT2: ISPDAT2 Mask               */
+
+#define FMC_MPDAT3_ISPDAT3_Pos           (0)                                               /*!< FMC_T::MPDAT3: ISPDAT3 Position           */
+#define FMC_MPDAT3_ISPDAT3_Msk           (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos)          /*!< FMC_T::MPDAT3: ISPDAT3 Mask               */
+
+#define FMC_MPSTS_MPBUSY_Pos             (0)                                               /*!< FMC_T::MPSTS: MPBUSY Position             */
+#define FMC_MPSTS_MPBUSY_Msk             (0x1ul << FMC_MPSTS_MPBUSY_Pos)                   /*!< FMC_T::MPSTS: MPBUSY Mask                 */
+
+#define FMC_MPSTS_PPGO_Pos               (1)                                               /*!< FMC_T::MPSTS: PPGO Position               */
+#define FMC_MPSTS_PPGO_Msk               (0x1ul << FMC_MPSTS_PPGO_Pos)                     /*!< FMC_T::MPSTS: PPGO Mask                   */
+
+#define FMC_MPSTS_ISPFF_Pos              (2)                                               /*!< FMC_T::MPSTS: ISPFF Position              */
+#define FMC_MPSTS_ISPFF_Msk              (0x1ul << FMC_MPSTS_ISPFF_Pos)                    /*!< FMC_T::MPSTS: ISPFF Mask                  */
+
+#define FMC_MPSTS_D0_Pos                 (4)                                               /*!< FMC_T::MPSTS: D0 Position                 */
+#define FMC_MPSTS_D0_Msk                 (0x1ul << FMC_MPSTS_D0_Pos)                       /*!< FMC_T::MPSTS: D0 Mask                     */
+
+#define FMC_MPSTS_D1_Pos                 (5)                                               /*!< FMC_T::MPSTS: D1 Position                 */
+#define FMC_MPSTS_D1_Msk                 (0x1ul << FMC_MPSTS_D1_Pos)                       /*!< FMC_T::MPSTS: D1 Mask                     */
+
+#define FMC_MPSTS_D2_Pos                 (6)                                               /*!< FMC_T::MPSTS: D2 Position                 */
+#define FMC_MPSTS_D2_Msk                 (0x1ul << FMC_MPSTS_D2_Pos)                       /*!< FMC_T::MPSTS: D2 Mask                     */
+
+#define FMC_MPSTS_D3_Pos                 (7)                                               /*!< FMC_T::MPSTS: D3 Position                 */
+#define FMC_MPSTS_D3_Msk                 (0x1ul << FMC_MPSTS_D3_Pos)                       /*!< FMC_T::MPSTS: D3 Mask                     */
+
+#define FMC_MPADDR_MPADDR_Pos            (0)                                               /*!< FMC_T::MPADDR: MPADDR Position            */
+#define FMC_MPADDR_MPADDR_Msk            (0xfffffffful << FMC_MPADDR_MPADDR_Pos)           /*!< FMC_T::MPADDR: MPADDR Mask                */
+
+/**@}*/ /* FMC_CONST */
+/**@}*/ /* end of FMC register group */
+
+
+/*---------------------- General Purpose Input/Output Controller -------------------------*/
+/**
+    @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
+    Memory Mapped Structure for GPIO Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+/**
+ * @var GPIO_T::MODE
+ * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140  Port A-F I/O Mode Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[2n+1:2n]|MODEn    |Port A-F I/O Pin[n] Mode Control
+ * |        |          |Determine each I/O mode of Px.n pins.
+ * |        |          |00 = Px.n is in Input mode.
+ * |        |          |01 = Px.n is in Push-pull Output mode.
+ * |        |          |10 = Px.n is in Open-drain Output mode.
+ * |        |          |11 = Px.n is in Quasi-bidirectional mode.
+ * |        |          |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
+ * |        |          |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
+ * |        |          |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
+ * |        |          |input mode after chip powered on.
+ * |        |          |Note2:
+ * |        |          |n=0~15 for port A/B/C/D.
+ * |        |          |n=0~14 for port E.
+ * |        |          |n=0~7 for port F.
+ * @var GPIO_T::DINOFF
+ * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144  Port A-F Digital Input Path Disable Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[n+16]  |DINOFFn   |Port A-F Pin[n] Digital Input Path Disable Control
+ * |        |          |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
+ * |        |          |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
+ * |        |          |0 = Px.n digital input path Enabled.
+ * |        |          |1 = Px.n digital input path Disabled (digital input tied to low).
+ * |        |          |Note:
+ * |        |          |n=0~15 for port A/B/C/D.
+ * |        |          |n=0~14 for port E.
+ * |        |          |n=0~7 for port F.
+ * @var GPIO_T::DOUT
+ * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148  Port A-F Data Output Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[n]     |DOUTn     |Port A-F Pin[n] Output Value
+ * |        |          |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
+ * |        |          |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
+ * |        |          |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
+ * |        |          |Note:
+ * |        |          |n=0~15 for port A/B/C/D.
+ * |        |          |n=0~14 for port E.
+ * |        |          |n=0~7 for port F.
+ * @var GPIO_T::DATMSK
+ * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C  Port A-F Data Output Write Mask
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[n]     |DMASKn    |Port A-F Pin[n] Data Output Write Mask
+ * |        |          |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
+ * |        |          |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
+ * |        |          |If the write signal is masked, writing data to the protect bit is ignored.
+ * |        |          |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
+ * |        |          |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
+ * |        |          |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
+ * |        |          |Note2:
+ * |        |          |n=0~15 for port A/B/C/D.
+ * |        |          |n=0~14 for port E.
+ * |        |          |n=0~7 for port F.
+ * @var GPIO_T::PIN
+ * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150  Port A-F Pin Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[n]     |PINn      |Port A-F Pin[n] Pin Value
+ * |        |          |Each bit of the register reflects the actual status of the respective Px.n pin.
+ * |        |          |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
+ * |        |          |Note:
+ * |        |          |n=0~15 for port A/B/C/D.
+ * |        |          |n=0~14 for port E.
+ * |        |          |n=0~7 for port F.
+ * @var GPIO_T::DBEN
+ * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154  Port A-F De-Bounce Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[n]     |DBENn     |Port A-F Pin[n] Input Signal De-Bounce Enable Bit
+ * |        |          |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
+ * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
+ * |        |          |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
+ * |        |          |0 = Px.n de-bounce function Disabled.
+ * |        |          |1 = Px.n de-bounce function Enabled.
+ * |        |          |The de-bounce function is valid only for edge triggered interrupt.
+ * |        |          |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+ * |        |          |Note:
+ * |        |          |n=0~15 for port A/B/C/D.
+ * |        |          |n=0~14 for port E.
+ * |        |          |n=0~7 for port F.
+ * @var GPIO_T::INTTYPE
+ * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158  Port A-F Interrupt Trigger Type Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[n]     |TYPEn     |Port A-F Pin[n] Edge Or Level Detection Interrupt Trigger Type Control
+ * |        |          |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
+ * |        |          |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
+ * |        |          |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
+ * |        |          |0 = Edge trigger interrupt.
+ * |        |          |1 = Level trigger interrupt.
+ * |        |          |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
+ * |        |          |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
+ * |        |          |The de-bounce function is valid only for edge triggered interrupt.
+ * |        |          |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+ * |        |          |Note:
+ * |        |          |n=0~15 for port A/B/C/D.
+ * |        |          |n=0~14 for port E.
+ * |        |          |n=0~7 for port F.
+ * @var GPIO_T::INTEN
+ * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C  Port A-F Interrupt Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[n]     |FLIENn    |Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
+ * |        |          |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
+ * |        |          |Set bit to 1 also enable the pin wake-up function.
+ * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
+ * |        |          |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
+ * |        |          |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
+ * |        |          |0 = Px.n level low or high to low interrupt Disabled.
+ * |        |          |1 = Px.n level low or high to low interrupt Enabled.
+ * |        |          |Note:
+ * |        |          |n=0~15 for port A/B/C/D.
+ * |        |          |n=0~14 for port E.
+ * |        |          |n=0~7 for port F.
+ * @var GPIO_T::INTSRC
+ * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160  Port A-F Interrupt Source Flag
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[n]     |INTSRCn   |Port A-F Pin[n] Interrupt Source Flag
+ * |        |          |Write Operation :
+ * |        |          |0 = No action.
+ * |        |          |1 = Clear the corresponding pending interrupt.
+ * |        |          |Read Operation :
+ * |        |          |0 = No interrupt at Px.n.
+ * |        |          |1 = Px.n generates an interrupt.
+ * |        |          |Note:
+ * |        |          |n=0~15 for port A/B/C/D.
+ * |        |          |n=0~14 for port E.
+ * |        |          |n=0~7 for port F.
+ * @var GPIO_T::SMTEN
+ * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164  Port A-F Input Schmitt Trigger Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[n]     |SMTENn    |Port A-F Pin[n] Input Schmitt Trigger Enable Bit
+ * |        |          |0 = Px.n input Schmitt trigger function Disabled.
+ * |        |          |1 = Px.n input Schmitt trigger function Enabled.
+ * |        |          |Note:
+ * |        |          |n=0~15 for port A/B/C/D.
+ * |        |          |n=0~14 for port E.
+ * |        |          |n=0~7 for port F.
+ * @var GPIO_T::SLEWCTL
+ * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168  Port A-F High Slew Rate Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[n]     |HSRENn    |Port A-F Pin[n] High Slew Rate Control
+ * |        |          |0 = Px.n output with basic slew rate.
+ * |        |          |1 = Px.n output with higher slew rate.
+ * |        |          |Note:
+ * |        |          |n=0~15 for port A/B/C/D.
+ * |        |          |n=0~14 for port E.
+ * |        |          |n=0~7 for port F.
+ * @var GPIO_T::DRVCTL
+ * Offset: 0x2C  Port E High Drive Strength Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[n]     |HDRVENn   |Port E Pin[n] Driving Strength Control
+ * |        |          |0 = Px.n output with basic driving strength.
+ * |        |          |1 = Px.n output with high driving strength.
+ * |        |          |Note:
+ * |        |          |n=8,9..13 for port E.
+ */
+
+    __IO uint32_t MODE;          /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140  Port A-F I/O Mode Control                       */
+    __IO uint32_t DINOFF;        /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144  Port A-F Digital Input Path Disable Control     */
+    __IO uint32_t DOUT;          /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148  Port A-F Data Output Value                      */
+    __IO uint32_t DATMSK;        /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C  Port A-F Data Output Write Mask                 */
+    __I  uint32_t PIN;           /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150  Port A-F Pin Value                              */
+    __IO uint32_t DBEN;          /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154  Port A-F De-Bounce Enable Control Register      */
+    __IO uint32_t INTTYPE;       /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158  Port A-F Interrupt Trigger Type Control         */
+    __IO uint32_t INTEN;         /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C  Port A-F Interrupt Enable Control Register      */
+    __IO uint32_t INTSRC;        /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160  Port A-F Interrupt Source Flag                  */
+    __IO uint32_t SMTEN;         /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164  Port A-F Input Schmitt Trigger Enable Register  */
+    __IO uint32_t SLEWCTL;       /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168  Port A-F High Slew Rate Control Register        */
+    __IO uint32_t DRVCTL;        /* Offset: 0x12C  Port E High Drive Strength Control Register                               */
+
+} GPIO_T;
+
+
+
+
+typedef struct
+{
+
+
+
+/**
+ * @var GPIO_DBCTL_T::DBCTL
+ * Offset: 0x440  Interrupt De-bounce Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |DBCLKSEL  |De-Bounce Sampling Cycle Selection
+ * |        |          |0000 = Sample interrupt input once per 1 clocks.
+ * |        |          |0001 = Sample interrupt input once per 2 clocks.
+ * |        |          |0010 = Sample interrupt input once per 4 clocks.
+ * |        |          |0011 = Sample interrupt input once per 8 clocks.
+ * |        |          |0100 = Sample interrupt input once per 16 clocks.
+ * |        |          |0101 = Sample interrupt input once per 32 clocks.
+ * |        |          |0110 = Sample interrupt input once per 64 clocks.
+ * |        |          |0111 = Sample interrupt input once per 128 clocks.
+ * |        |          |1000 = Sample interrupt input once per 256 clocks.
+ * |        |          |1001 = Sample interrupt input once per 2*256 clocks.
+ * |        |          |1010 = Sample interrupt input once per 4*256 clocks.
+ * |        |          |1011 = Sample interrupt input once per 8*256 clocks.
+ * |        |          |1100 = Sample interrupt input once per 16*256 clocks.
+ * |        |          |1101 = Sample interrupt input once per 32*256 clocks.
+ * |        |          |1110 = Sample interrupt input once per 64*256 clocks.
+ * |        |          |1111 = Sample interrupt input once per 128*256 clocks.
+ * |[4]     |DBCLKSRC  |De-Bounce Counter Clock Source Selection
+ * |        |          |0 = De-bounce counter clock source is the HCLK.
+ * |        |          |1 = De-bounce counter clock source is the internal 10 kHz internal low speed oscillator.
+ * |[5]     |ICLKON    |Interrupt Clock On Mode
+ * |        |          |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
+ * |        |          |1 = All I/O pins edge detection circuit is always active after reset.
+ * |        |          |Note: It is recommended to disable this bit to save system power if no special application concern.
+ */
+
+    __IO uint32_t DBCTL;         /* Offset: 0x440  Interrupt De-bounce Control Register                              */
+
+} GPIO_DBCTL_T;
+
+
+
+
+/**
+    @addtogroup GPIO_CONST GPIO Bit Field Definition
+    Constant Definitions for GPIO Controller
+@{ */
+
+#define GPIO_MODE_MODE0_Pos              (0)                                               /*!< GPIO_T::MODE: MODE0 Position              */
+#define GPIO_MODE_MODE0_Msk              (0x3ul << GPIO_MODE_MODE0_Pos)                    /*!< GPIO_T::MODE: MODE0 Mask                  */
+
+#define GPIO_MODE_MODE1_Pos              (2)                                               /*!< GPIO_T::MODE: MODE1 Position              */
+#define GPIO_MODE_MODE1_Msk              (0x3ul << GPIO_MODE_MODE1_Pos)                    /*!< GPIO_T::MODE: MODE1 Mask                  */
+
+#define GPIO_MODE_MODE2_Pos              (4)                                               /*!< GPIO_T::MODE: MODE2 Position              */
+#define GPIO_MODE_MODE2_Msk              (0x3ul << GPIO_MODE_MODE2_Pos)                    /*!< GPIO_T::MODE: MODE2 Mask                  */
+
+#define GPIO_MODE_MODE3_Pos              (6)                                               /*!< GPIO_T::MODE: MODE3 Position              */
+#define GPIO_MODE_MODE3_Msk              (0x3ul << GPIO_MODE_MODE3_Pos)                    /*!< GPIO_T::MODE: MODE3 Mask                  */
+
+#define GPIO_MODE_MODE4_Pos              (8)                                               /*!< GPIO_T::MODE: MODE4 Position              */
+#define GPIO_MODE_MODE4_Msk              (0x3ul << GPIO_MODE_MODE4_Pos)                    /*!< GPIO_T::MODE: MODE4 Mask                  */
+
+#define GPIO_MODE_MODE5_Pos              (10)                                              /*!< GPIO_T::MODE: MODE5 Position              */
+#define GPIO_MODE_MODE5_Msk              (0x3ul << GPIO_MODE_MODE5_Pos)                    /*!< GPIO_T::MODE: MODE5 Mask                  */
+
+#define GPIO_MODE_MODE6_Pos              (12)                                              /*!< GPIO_T::MODE: MODE6 Position              */
+#define GPIO_MODE_MODE6_Msk              (0x3ul << GPIO_MODE_MODE6_Pos)                    /*!< GPIO_T::MODE: MODE6 Mask                  */
+
+#define GPIO_MODE_MODE7_Pos              (14)                                              /*!< GPIO_T::MODE: MODE7 Position              */
+#define GPIO_MODE_MODE7_Msk              (0x3ul << GPIO_MODE_MODE7_Pos)                    /*!< GPIO_T::MODE: MODE7 Mask                  */
+
+#define GPIO_MODE_MODE8_Pos              (16)                                              /*!< GPIO_T::MODE: MODE8 Position              */
+#define GPIO_MODE_MODE8_Msk              (0x3ul << GPIO_MODE_MODE8_Pos)                    /*!< GPIO_T::MODE: MODE8 Mask                  */
+
+#define GPIO_MODE_MODE9_Pos              (18)                                              /*!< GPIO_T::MODE: MODE9 Position              */
+#define GPIO_MODE_MODE9_Msk              (0x3ul << GPIO_MODE_MODE9_Pos)                    /*!< GPIO_T::MODE: MODE9 Mask                  */
+
+#define GPIO_MODE_MODE10_Pos             (20)                                              /*!< GPIO_T::MODE: MODE10 Position             */
+#define GPIO_MODE_MODE10_Msk             (0x3ul << GPIO_MODE_MODE10_Pos)                   /*!< GPIO_T::MODE: MODE10 Mask                 */
+
+#define GPIO_MODE_MODE11_Pos             (22)                                              /*!< GPIO_T::MODE: MODE11 Position             */
+#define GPIO_MODE_MODE11_Msk             (0x3ul << GPIO_MODE_MODE11_Pos)                   /*!< GPIO_T::MODE: MODE11 Mask                 */
+
+#define GPIO_MODE_MODE12_Pos             (24)                                              /*!< GPIO_T::MODE: MODE12 Position             */
+#define GPIO_MODE_MODE12_Msk             (0x3ul << GPIO_MODE_MODE12_Pos)                   /*!< GPIO_T::MODE: MODE12 Mask                 */
+
+#define GPIO_MODE_MODE13_Pos             (26)                                              /*!< GPIO_T::MODE: MODE13 Position             */
+#define GPIO_MODE_MODE13_Msk             (0x3ul << GPIO_MODE_MODE13_Pos)                   /*!< GPIO_T::MODE: MODE13 Mask                 */
+
+#define GPIO_MODE_MODE14_Pos             (28)                                              /*!< GPIO_T::MODE: MODE14 Position             */
+#define GPIO_MODE_MODE14_Msk             (0x3ul << GPIO_MODE_MODE14_Pos)                   /*!< GPIO_T::MODE: MODE14 Mask                 */
+
+#define GPIO_MODE_MODE15_Pos             (30)                                              /*!< GPIO_T::MODE: MODE15 Position             */
+#define GPIO_MODE_MODE15_Msk             (0x3ul << GPIO_MODE_MODE15_Pos)                   /*!< GPIO_T::MODE: MODE15 Mask                 */
+
+#define GPIO_DINOFF_DINOFF0_Pos          (16)                                              /*!< GPIO_T::DINOFF: DINOFF0 Position          */
+#define GPIO_DINOFF_DINOFF0_Msk          (0x1ul << GPIO_DINOFF_DINOFF0_Pos)                /*!< GPIO_T::DINOFF: DINOFF0 Mask              */
+
+#define GPIO_DINOFF_DINOFF1_Pos          (17)                                              /*!< GPIO_T::DINOFF: DINOFF1 Position          */
+#define GPIO_DINOFF_DINOFF1_Msk          (0x1ul << GPIO_DINOFF_DINOFF1_Pos)                /*!< GPIO_T::DINOFF: DINOFF1 Mask              */
+
+#define GPIO_DINOFF_DINOFF2_Pos          (18)                                              /*!< GPIO_T::DINOFF: DINOFF2 Position          */
+#define GPIO_DINOFF_DINOFF2_Msk          (0x1ul << GPIO_DINOFF_DINOFF2_Pos)                /*!< GPIO_T::DINOFF: DINOFF2 Mask              */
+
+#define GPIO_DINOFF_DINOFF3_Pos          (19)                                              /*!< GPIO_T::DINOFF: DINOFF3 Position          */
+#define GPIO_DINOFF_DINOFF3_Msk          (0x1ul << GPIO_DINOFF_DINOFF3_Pos)                /*!< GPIO_T::DINOFF: DINOFF3 Mask              */
+
+#define GPIO_DINOFF_DINOFF4_Pos          (20)                                              /*!< GPIO_T::DINOFF: DINOFF4 Position          */
+#define GPIO_DINOFF_DINOFF4_Msk          (0x1ul << GPIO_DINOFF_DINOFF4_Pos)                /*!< GPIO_T::DINOFF: DINOFF4 Mask              */
+
+#define GPIO_DINOFF_DINOFF5_Pos          (21)                                              /*!< GPIO_T::DINOFF: DINOFF5 Position          */
+#define GPIO_DINOFF_DINOFF5_Msk          (0x1ul << GPIO_DINOFF_DINOFF5_Pos)                /*!< GPIO_T::DINOFF: DINOFF5 Mask              */
+
+#define GPIO_DINOFF_DINOFF6_Pos          (22)                                              /*!< GPIO_T::DINOFF: DINOFF6 Position          */
+#define GPIO_DINOFF_DINOFF6_Msk          (0x1ul << GPIO_DINOFF_DINOFF6_Pos)                /*!< GPIO_T::DINOFF: DINOFF6 Mask              */
+
+#define GPIO_DINOFF_DINOFF7_Pos          (23)                                              /*!< GPIO_T::DINOFF: DINOFF7 Position          */
+#define GPIO_DINOFF_DINOFF7_Msk          (0x1ul << GPIO_DINOFF_DINOFF7_Pos)                /*!< GPIO_T::DINOFF: DINOFF7 Mask              */
+
+#define GPIO_DINOFF_DINOFF8_Pos          (24)                                              /*!< GPIO_T::DINOFF: DINOFF8 Position          */
+#define GPIO_DINOFF_DINOFF8_Msk          (0x1ul << GPIO_DINOFF_DINOFF8_Pos)                /*!< GPIO_T::DINOFF: DINOFF8 Mask              */
+
+#define GPIO_DINOFF_DINOFF9_Pos          (25)                                              /*!< GPIO_T::DINOFF: DINOFF9 Position          */
+#define GPIO_DINOFF_DINOFF9_Msk          (0x1ul << GPIO_DINOFF_DINOFF9_Pos)                /*!< GPIO_T::DINOFF: DINOFF9 Mask              */
+
+#define GPIO_DINOFF_DINOFF10_Pos         (26)                                              /*!< GPIO_T::DINOFF: DINOFF10 Position         */
+#define GPIO_DINOFF_DINOFF10_Msk         (0x1ul << GPIO_DINOFF_DINOFF10_Pos)               /*!< GPIO_T::DINOFF: DINOFF10 Mask             */
+
+#define GPIO_DINOFF_DINOFF11_Pos         (27)                                              /*!< GPIO_T::DINOFF: DINOFF11 Position         */
+#define GPIO_DINOFF_DINOFF11_Msk         (0x1ul << GPIO_DINOFF_DINOFF11_Pos)               /*!< GPIO_T::DINOFF: DINOFF11 Mask             */
+
+#define GPIO_DINOFF_DINOFF12_Pos         (28)                                              /*!< GPIO_T::DINOFF: DINOFF12 Position         */
+#define GPIO_DINOFF_DINOFF12_Msk         (0x1ul << GPIO_DINOFF_DINOFF12_Pos)               /*!< GPIO_T::DINOFF: DINOFF12 Mask             */
+
+#define GPIO_DINOFF_DINOFF13_Pos         (29)                                              /*!< GPIO_T::DINOFF: DINOFF13 Position         */
+#define GPIO_DINOFF_DINOFF13_Msk         (0x1ul << GPIO_DINOFF_DINOFF13_Pos)               /*!< GPIO_T::DINOFF: DINOFF13 Mask             */
+
+#define GPIO_DINOFF_DINOFF14_Pos         (30)                                              /*!< GPIO_T::DINOFF: DINOFF14 Position         */
+#define GPIO_DINOFF_DINOFF14_Msk         (0x1ul << GPIO_DINOFF_DINOFF14_Pos)               /*!< GPIO_T::DINOFF: DINOFF14 Mask             */
+
+#define GPIO_DINOFF_DINOFF15_Pos         (31)                                              /*!< GPIO_T::DINOFF: DINOFF15 Position         */
+#define GPIO_DINOFF_DINOFF15_Msk         (0x1ul << GPIO_DINOFF_DINOFF15_Pos)               /*!< GPIO_T::DINOFF: DINOFF15 Mask             */
+
+#define GPIO_DOUT_DOUT0_Pos              (0)                                               /*!< GPIO_T::DOUT: DOUT0 Position              */
+#define GPIO_DOUT_DOUT0_Msk              (0x1ul << GPIO_DOUT_DOUT0_Pos)                    /*!< GPIO_T::DOUT: DOUT0 Mask                  */
+
+#define GPIO_DOUT_DOUT1_Pos              (1)                                               /*!< GPIO_T::DOUT: DOUT1 Position              */
+#define GPIO_DOUT_DOUT1_Msk              (0x1ul << GPIO_DOUT_DOUT1_Pos)                    /*!< GPIO_T::DOUT: DOUT1 Mask                  */
+
+#define GPIO_DOUT_DOUT2_Pos              (2)                                               /*!< GPIO_T::DOUT: DOUT2 Position              */
+#define GPIO_DOUT_DOUT2_Msk              (0x1ul << GPIO_DOUT_DOUT2_Pos)                    /*!< GPIO_T::DOUT: DOUT2 Mask                  */
+
+#define GPIO_DOUT_DOUT3_Pos              (3)                                               /*!< GPIO_T::DOUT: DOUT3 Position              */
+#define GPIO_DOUT_DOUT3_Msk              (0x1ul << GPIO_DOUT_DOUT3_Pos)                    /*!< GPIO_T::DOUT: DOUT3 Mask                  */
+
+#define GPIO_DOUT_DOUT4_Pos              (4)                                               /*!< GPIO_T::DOUT: DOUT4 Position              */
+#define GPIO_DOUT_DOUT4_Msk              (0x1ul << GPIO_DOUT_DOUT4_Pos)                    /*!< GPIO_T::DOUT: DOUT4 Mask                  */
+
+#define GPIO_DOUT_DOUT5_Pos              (5)                                               /*!< GPIO_T::DOUT: DOUT5 Position              */
+#define GPIO_DOUT_DOUT5_Msk              (0x1ul << GPIO_DOUT_DOUT5_Pos)                    /*!< GPIO_T::DOUT: DOUT5 Mask                  */
+
+#define GPIO_DOUT_DOUT6_Pos              (6)                                               /*!< GPIO_T::DOUT: DOUT6 Position              */
+#define GPIO_DOUT_DOUT6_Msk              (0x1ul << GPIO_DOUT_DOUT6_Pos)                    /*!< GPIO_T::DOUT: DOUT6 Mask                  */
+
+#define GPIO_DOUT_DOUT7_Pos              (7)                                               /*!< GPIO_T::DOUT: DOUT7 Position              */
+#define GPIO_DOUT_DOUT7_Msk              (0x1ul << GPIO_DOUT_DOUT7_Pos)                    /*!< GPIO_T::DOUT: DOUT7 Mask                  */
+
+#define GPIO_DOUT_DOUT8_Pos              (8)                                               /*!< GPIO_T::DOUT: DOUT8 Position              */
+#define GPIO_DOUT_DOUT8_Msk              (0x1ul << GPIO_DOUT_DOUT8_Pos)                    /*!< GPIO_T::DOUT: DOUT8 Mask                  */
+
+#define GPIO_DOUT_DOUT9_Pos              (9)                                               /*!< GPIO_T::DOUT: DOUT9 Position              */
+#define GPIO_DOUT_DOUT9_Msk              (0x1ul << GPIO_DOUT_DOUT9_Pos)                    /*!< GPIO_T::DOUT: DOUT9 Mask                  */
+
+#define GPIO_DOUT_DOUT10_Pos             (10)                                              /*!< GPIO_T::DOUT: DOUT10 Position             */
+#define GPIO_DOUT_DOUT10_Msk             (0x1ul << GPIO_DOUT_DOUT10_Pos)                   /*!< GPIO_T::DOUT: DOUT10 Mask                 */
+
+#define GPIO_DOUT_DOUT11_Pos             (11)                                              /*!< GPIO_T::DOUT: DOUT11 Position             */
+#define GPIO_DOUT_DOUT11_Msk             (0x1ul << GPIO_DOUT_DOUT11_Pos)                   /*!< GPIO_T::DOUT: DOUT11 Mask                 */
+
+#define GPIO_DOUT_DOUT12_Pos             (12)                                              /*!< GPIO_T::DOUT: DOUT12 Position             */
+#define GPIO_DOUT_DOUT12_Msk             (0x1ul << GPIO_DOUT_DOUT12_Pos)                   /*!< GPIO_T::DOUT: DOUT12 Mask                 */
+
+#define GPIO_DOUT_DOUT13_Pos             (13)                                              /*!< GPIO_T::DOUT: DOUT13 Position             */
+#define GPIO_DOUT_DOUT13_Msk             (0x1ul << GPIO_DOUT_DOUT13_Pos)                   /*!< GPIO_T::DOUT: DOUT13 Mask                 */
+
+#define GPIO_DOUT_DOUT14_Pos             (14)                                              /*!< GPIO_T::DOUT: DOUT14 Position             */
+#define GPIO_DOUT_DOUT14_Msk             (0x1ul << GPIO_DOUT_DOUT14_Pos)                   /*!< GPIO_T::DOUT: DOUT14 Mask                 */
+
+#define GPIO_DOUT_DOUT15_Pos             (15)                                              /*!< GPIO_T::DOUT: DOUT15 Position             */
+#define GPIO_DOUT_DOUT15_Msk             (0x1ul << GPIO_DOUT_DOUT15_Pos)                   /*!< GPIO_T::DOUT: DOUT15 Mask                 */
+
+#define GPIO_DATMSK_DMASK0_Pos           (0)                                               /*!< GPIO_T::DATMSK: DMASK0 Position           */
+#define GPIO_DATMSK_DMASK0_Msk           (0x1ul << GPIO_DATMSK_DMASK0_Pos)                 /*!< GPIO_T::DATMSK: DMASK0 Mask               */
+
+#define GPIO_DATMSK_DMASK1_Pos           (1)                                               /*!< GPIO_T::DATMSK: DMASK1 Position           */
+#define GPIO_DATMSK_DMASK1_Msk           (0x1ul << GPIO_DATMSK_DMASK1_Pos)                 /*!< GPIO_T::DATMSK: DMASK1 Mask               */
+
+#define GPIO_DATMSK_DMASK2_Pos           (2)                                               /*!< GPIO_T::DATMSK: DMASK2 Position           */
+#define GPIO_DATMSK_DMASK2_Msk           (0x1ul << GPIO_DATMSK_DMASK2_Pos)                 /*!< GPIO_T::DATMSK: DMASK2 Mask               */
+
+#define GPIO_DATMSK_DMASK3_Pos           (3)                                               /*!< GPIO_T::DATMSK: DMASK3 Position           */
+#define GPIO_DATMSK_DMASK3_Msk           (0x1ul << GPIO_DATMSK_DMASK3_Pos)                 /*!< GPIO_T::DATMSK: DMASK3 Mask               */
+
+#define GPIO_DATMSK_DMASK4_Pos           (4)                                               /*!< GPIO_T::DATMSK: DMASK4 Position           */
+#define GPIO_DATMSK_DMASK4_Msk           (0x1ul << GPIO_DATMSK_DMASK4_Pos)                 /*!< GPIO_T::DATMSK: DMASK4 Mask               */
+
+#define GPIO_DATMSK_DMASK5_Pos           (5)                                               /*!< GPIO_T::DATMSK: DMASK5 Position           */
+#define GPIO_DATMSK_DMASK5_Msk           (0x1ul << GPIO_DATMSK_DMASK5_Pos)                 /*!< GPIO_T::DATMSK: DMASK5 Mask               */
+
+#define GPIO_DATMSK_DMASK6_Pos           (6)                                               /*!< GPIO_T::DATMSK: DMASK6 Position           */
+#define GPIO_DATMSK_DMASK6_Msk           (0x1ul << GPIO_DATMSK_DMASK6_Pos)                 /*!< GPIO_T::DATMSK: DMASK6 Mask               */
+
+#define GPIO_DATMSK_DMASK7_Pos           (7)                                               /*!< GPIO_T::DATMSK: DMASK7 Position           */
+#define GPIO_DATMSK_DMASK7_Msk           (0x1ul << GPIO_DATMSK_DMASK7_Pos)                 /*!< GPIO_T::DATMSK: DMASK7 Mask               */
+
+#define GPIO_DATMSK_DMASK8_Pos           (8)                                               /*!< GPIO_T::DATMSK: DMASK8 Position           */
+#define GPIO_DATMSK_DMASK8_Msk           (0x1ul << GPIO_DATMSK_DMASK8_Pos)                 /*!< GPIO_T::DATMSK: DMASK8 Mask               */
+
+#define GPIO_DATMSK_DMASK9_Pos           (9)                                               /*!< GPIO_T::DATMSK: DMASK9 Position           */
+#define GPIO_DATMSK_DMASK9_Msk           (0x1ul << GPIO_DATMSK_DMASK9_Pos)                 /*!< GPIO_T::DATMSK: DMASK9 Mask               */
+
+#define GPIO_DATMSK_DMASK10_Pos          (10)                                              /*!< GPIO_T::DATMSK: DMASK10 Position          */
+#define GPIO_DATMSK_DMASK10_Msk          (0x1ul << GPIO_DATMSK_DMASK10_Pos)                /*!< GPIO_T::DATMSK: DMASK10 Mask              */
+
+#define GPIO_DATMSK_DMASK11_Pos          (11)                                              /*!< GPIO_T::DATMSK: DMASK11 Position          */
+#define GPIO_DATMSK_DMASK11_Msk          (0x1ul << GPIO_DATMSK_DMASK11_Pos)                /*!< GPIO_T::DATMSK: DMASK11 Mask              */
+
+#define GPIO_DATMSK_DMASK12_Pos          (12)                                              /*!< GPIO_T::DATMSK: DMASK12 Position          */
+#define GPIO_DATMSK_DMASK12_Msk          (0x1ul << GPIO_DATMSK_DMASK12_Pos)                /*!< GPIO_T::DATMSK: DMASK12 Mask              */
+
+#define GPIO_DATMSK_DMASK13_Pos          (13)                                              /*!< GPIO_T::DATMSK: DMASK13 Position          */
+#define GPIO_DATMSK_DMASK13_Msk          (0x1ul << GPIO_DATMSK_DMASK13_Pos)                /*!< GPIO_T::DATMSK: DMASK13 Mask              */
+
+#define GPIO_DATMSK_DMASK14_Pos          (14)                                              /*!< GPIO_T::DATMSK: DMASK14 Position          */
+#define GPIO_DATMSK_DMASK14_Msk          (0x1ul << GPIO_DATMSK_DMASK14_Pos)                /*!< GPIO_T::DATMSK: DMASK14 Mask              */
+
+#define GPIO_DATMSK_DMASK15_Pos          (15)                                              /*!< GPIO_T::DATMSK: DMASK15 Position          */
+#define GPIO_DATMSK_DMASK15_Msk          (0x1ul << GPIO_DATMSK_DMASK15_Pos)                /*!< GPIO_T::DATMSK: DMASK15 Mask              */
+
+#define GPIO_PIN_PIN0_Pos                (0)                                               /*!< GPIO_T::PIN: PIN0 Position                */
+#define GPIO_PIN_PIN0_Msk                (0x1ul << GPIO_PIN_PIN0_Pos)                      /*!< GPIO_T::PIN: PIN0 Mask                    */
+
+#define GPIO_PIN_PIN1_Pos                (1)                                               /*!< GPIO_T::PIN: PIN1 Position                */
+#define GPIO_PIN_PIN1_Msk                (0x1ul << GPIO_PIN_PIN1_Pos)                      /*!< GPIO_T::PIN: PIN1 Mask                    */
+
+#define GPIO_PIN_PIN2_Pos                (2)                                               /*!< GPIO_T::PIN: PIN2 Position                */
+#define GPIO_PIN_PIN2_Msk                (0x1ul << GPIO_PIN_PIN2_Pos)                      /*!< GPIO_T::PIN: PIN2 Mask                    */
+
+#define GPIO_PIN_PIN3_Pos                (3)                                               /*!< GPIO_T::PIN: PIN3 Position                */
+#define GPIO_PIN_PIN3_Msk                (0x1ul << GPIO_PIN_PIN3_Pos)                      /*!< GPIO_T::PIN: PIN3 Mask                    */
+
+#define GPIO_PIN_PIN4_Pos                (4)                                               /*!< GPIO_T::PIN: PIN4 Position                */
+#define GPIO_PIN_PIN4_Msk                (0x1ul << GPIO_PIN_PIN4_Pos)                      /*!< GPIO_T::PIN: PIN4 Mask                    */
+
+#define GPIO_PIN_PIN5_Pos                (5)                                               /*!< GPIO_T::PIN: PIN5 Position                */
+#define GPIO_PIN_PIN5_Msk                (0x1ul << GPIO_PIN_PIN5_Pos)                      /*!< GPIO_T::PIN: PIN5 Mask                    */
+
+#define GPIO_PIN_PIN6_Pos                (6)                                               /*!< GPIO_T::PIN: PIN6 Position                */
+#define GPIO_PIN_PIN6_Msk                (0x1ul << GPIO_PIN_PIN6_Pos)                      /*!< GPIO_T::PIN: PIN6 Mask                    */
+
+#define GPIO_PIN_PIN7_Pos                (7)                                               /*!< GPIO_T::PIN: PIN7 Position                */
+#define GPIO_PIN_PIN7_Msk                (0x1ul << GPIO_PIN_PIN7_Pos)                      /*!< GPIO_T::PIN: PIN7 Mask                    */
+
+#define GPIO_PIN_PIN8_Pos                (8)                                               /*!< GPIO_T::PIN: PIN8 Position                */
+#define GPIO_PIN_PIN8_Msk                (0x1ul << GPIO_PIN_PIN8_Pos)                      /*!< GPIO_T::PIN: PIN8 Mask                    */
+
+#define GPIO_PIN_PIN9_Pos                (9)                                               /*!< GPIO_T::PIN: PIN9 Position                */
+#define GPIO_PIN_PIN9_Msk                (0x1ul << GPIO_PIN_PIN9_Pos)                      /*!< GPIO_T::PIN: PIN9 Mask                    */
+
+#define GPIO_PIN_PIN10_Pos               (10)                                              /*!< GPIO_T::PIN: PIN10 Position               */
+#define GPIO_PIN_PIN10_Msk               (0x1ul << GPIO_PIN_PIN10_Pos)                     /*!< GPIO_T::PIN: PIN10 Mask                   */
+
+#define GPIO_PIN_PIN11_Pos               (11)                                              /*!< GPIO_T::PIN: PIN11 Position               */
+#define GPIO_PIN_PIN11_Msk               (0x1ul << GPIO_PIN_PIN11_Pos)                     /*!< GPIO_T::PIN: PIN11 Mask                   */
+
+#define GPIO_PIN_PIN12_Pos               (12)                                              /*!< GPIO_T::PIN: PIN12 Position               */
+#define GPIO_PIN_PIN12_Msk               (0x1ul << GPIO_PIN_PIN12_Pos)                     /*!< GPIO_T::PIN: PIN12 Mask                   */
+
+#define GPIO_PIN_PIN13_Pos               (13)                                              /*!< GPIO_T::PIN: PIN13 Position               */
+#define GPIO_PIN_PIN13_Msk               (0x1ul << GPIO_PIN_PIN13_Pos)                     /*!< GPIO_T::PIN: PIN13 Mask                   */
+
+#define GPIO_PIN_PIN14_Pos               (14)                                              /*!< GPIO_T::PIN: PIN14 Position               */
+#define GPIO_PIN_PIN14_Msk               (0x1ul << GPIO_PIN_PIN14_Pos)                     /*!< GPIO_T::PIN: PIN14 Mask                   */
+
+#define GPIO_PIN_PIN15_Pos               (15)                                              /*!< GPIO_T::PIN: PIN15 Position               */
+#define GPIO_PIN_PIN15_Msk               (0x1ul << GPIO_PIN_PIN15_Pos)                     /*!< GPIO_T::PIN: PIN15 Mask                   */
+
+#define GPIO_DBEN_DBEN0_Pos              (0)                                               /*!< GPIO_T::DBEN: DBEN0 Position              */
+#define GPIO_DBEN_DBEN0_Msk              (0x1ul << GPIO_DBEN_DBEN0_Pos)                    /*!< GPIO_T::DBEN: DBEN0 Mask                  */
+
+#define GPIO_DBEN_DBEN1_Pos              (1)                                               /*!< GPIO_T::DBEN: DBEN1 Position              */
+#define GPIO_DBEN_DBEN1_Msk              (0x1ul << GPIO_DBEN_DBEN1_Pos)                    /*!< GPIO_T::DBEN: DBEN1 Mask                  */
+
+#define GPIO_DBEN_DBEN2_Pos              (2)                                               /*!< GPIO_T::DBEN: DBEN2 Position              */
+#define GPIO_DBEN_DBEN2_Msk              (0x1ul << GPIO_DBEN_DBEN2_Pos)                    /*!< GPIO_T::DBEN: DBEN2 Mask                  */
+
+#define GPIO_DBEN_DBEN3_Pos              (3)                                               /*!< GPIO_T::DBEN: DBEN3 Position              */
+#define GPIO_DBEN_DBEN3_Msk              (0x1ul << GPIO_DBEN_DBEN3_Pos)                    /*!< GPIO_T::DBEN: DBEN3 Mask                  */
+
+#define GPIO_DBEN_DBEN4_Pos              (4)                                               /*!< GPIO_T::DBEN: DBEN4 Position              */
+#define GPIO_DBEN_DBEN4_Msk              (0x1ul << GPIO_DBEN_DBEN4_Pos)                    /*!< GPIO_T::DBEN: DBEN4 Mask                  */
+
+#define GPIO_DBEN_DBEN5_Pos              (5)                                               /*!< GPIO_T::DBEN: DBEN5 Position              */
+#define GPIO_DBEN_DBEN5_Msk              (0x1ul << GPIO_DBEN_DBEN5_Pos)                    /*!< GPIO_T::DBEN: DBEN5 Mask                  */
+
+#define GPIO_DBEN_DBEN6_Pos              (6)                                               /*!< GPIO_T::DBEN: DBEN6 Position              */
+#define GPIO_DBEN_DBEN6_Msk              (0x1ul << GPIO_DBEN_DBEN6_Pos)                    /*!< GPIO_T::DBEN: DBEN6 Mask                  */
+
+#define GPIO_DBEN_DBEN7_Pos              (7)                                               /*!< GPIO_T::DBEN: DBEN7 Position              */
+#define GPIO_DBEN_DBEN7_Msk              (0x1ul << GPIO_DBEN_DBEN7_Pos)                    /*!< GPIO_T::DBEN: DBEN7 Mask                  */
+
+#define GPIO_DBEN_DBEN8_Pos              (8)                                               /*!< GPIO_T::DBEN: DBEN8 Position              */
+#define GPIO_DBEN_DBEN8_Msk              (0x1ul << GPIO_DBEN_DBEN8_Pos)                    /*!< GPIO_T::DBEN: DBEN8 Mask                  */
+
+#define GPIO_DBEN_DBEN9_Pos              (9)                                               /*!< GPIO_T::DBEN: DBEN9 Position              */
+#define GPIO_DBEN_DBEN9_Msk              (0x1ul << GPIO_DBEN_DBEN9_Pos)                    /*!< GPIO_T::DBEN: DBEN9 Mask                  */
+
+#define GPIO_DBEN_DBEN10_Pos             (10)                                              /*!< GPIO_T::DBEN: DBEN10 Position             */
+#define GPIO_DBEN_DBEN10_Msk             (0x1ul << GPIO_DBEN_DBEN10_Pos)                   /*!< GPIO_T::DBEN: DBEN10 Mask                 */
+
+#define GPIO_DBEN_DBEN11_Pos             (11)                                              /*!< GPIO_T::DBEN: DBEN11 Position             */
+#define GPIO_DBEN_DBEN11_Msk             (0x1ul << GPIO_DBEN_DBEN11_Pos)                   /*!< GPIO_T::DBEN: DBEN11 Mask                 */
+
+#define GPIO_DBEN_DBEN12_Pos             (12)                                              /*!< GPIO_T::DBEN: DBEN12 Position             */
+#define GPIO_DBEN_DBEN12_Msk             (0x1ul << GPIO_DBEN_DBEN12_Pos)                   /*!< GPIO_T::DBEN: DBEN12 Mask                 */
+
+#define GPIO_DBEN_DBEN13_Pos             (13)                                              /*!< GPIO_T::DBEN: DBEN13 Position             */
+#define GPIO_DBEN_DBEN13_Msk             (0x1ul << GPIO_DBEN_DBEN13_Pos)                   /*!< GPIO_T::DBEN: DBEN13 Mask                 */
+
+#define GPIO_DBEN_DBEN14_Pos             (14)                                              /*!< GPIO_T::DBEN: DBEN14 Position             */
+#define GPIO_DBEN_DBEN14_Msk             (0x1ul << GPIO_DBEN_DBEN14_Pos)                   /*!< GPIO_T::DBEN: DBEN14 Mask                 */
+
+#define GPIO_DBEN_DBEN15_Pos             (15)                                              /*!< GPIO_T::DBEN: DBEN15 Position             */
+#define GPIO_DBEN_DBEN15_Msk             (0x1ul << GPIO_DBEN_DBEN15_Pos)                   /*!< GPIO_T::DBEN: DBEN15 Mask                 */
+
+#define GPIO_INTTYPE_TYPE0_Pos           (0)                                               /*!< GPIO_T::INTTYPE: TYPE0 Position           */
+#define GPIO_INTTYPE_TYPE0_Msk           (0x1ul << GPIO_INTTYPE_TYPE0_Pos)                 /*!< GPIO_T::INTTYPE: TYPE0 Mask               */
+
+#define GPIO_INTTYPE_TYPE1_Pos           (1)                                               /*!< GPIO_T::INTTYPE: TYPE1 Position           */
+#define GPIO_INTTYPE_TYPE1_Msk           (0x1ul << GPIO_INTTYPE_TYPE1_Pos)                 /*!< GPIO_T::INTTYPE: TYPE1 Mask               */
+
+#define GPIO_INTTYPE_TYPE2_Pos           (2)                                               /*!< GPIO_T::INTTYPE: TYPE2 Position           */
+#define GPIO_INTTYPE_TYPE2_Msk           (0x1ul << GPIO_INTTYPE_TYPE2_Pos)                 /*!< GPIO_T::INTTYPE: TYPE2 Mask               */
+
+#define GPIO_INTTYPE_TYPE3_Pos           (3)                                               /*!< GPIO_T::INTTYPE: TYPE3 Position           */
+#define GPIO_INTTYPE_TYPE3_Msk           (0x1ul << GPIO_INTTYPE_TYPE3_Pos)                 /*!< GPIO_T::INTTYPE: TYPE3 Mask               */
+
+#define GPIO_INTTYPE_TYPE4_Pos           (4)                                               /*!< GPIO_T::INTTYPE: TYPE4 Position           */
+#define GPIO_INTTYPE_TYPE4_Msk           (0x1ul << GPIO_INTTYPE_TYPE4_Pos)                 /*!< GPIO_T::INTTYPE: TYPE4 Mask               */
+
+#define GPIO_INTTYPE_TYPE5_Pos           (5)                                               /*!< GPIO_T::INTTYPE: TYPE5 Position           */
+#define GPIO_INTTYPE_TYPE5_Msk           (0x1ul << GPIO_INTTYPE_TYPE5_Pos)                 /*!< GPIO_T::INTTYPE: TYPE5 Mask               */
+
+#define GPIO_INTTYPE_TYPE6_Pos           (6)                                               /*!< GPIO_T::INTTYPE: TYPE6 Position           */
+#define GPIO_INTTYPE_TYPE6_Msk           (0x1ul << GPIO_INTTYPE_TYPE6_Pos)                 /*!< GPIO_T::INTTYPE: TYPE6 Mask               */
+
+#define GPIO_INTTYPE_TYPE7_Pos           (7)                                               /*!< GPIO_T::INTTYPE: TYPE7 Position           */
+#define GPIO_INTTYPE_TYPE7_Msk           (0x1ul << GPIO_INTTYPE_TYPE7_Pos)                 /*!< GPIO_T::INTTYPE: TYPE7 Mask               */
+
+#define GPIO_INTTYPE_TYPE8_Pos           (8)                                               /*!< GPIO_T::INTTYPE: TYPE8 Position           */
+#define GPIO_INTTYPE_TYPE8_Msk           (0x1ul << GPIO_INTTYPE_TYPE8_Pos)                 /*!< GPIO_T::INTTYPE: TYPE8 Mask               */
+
+#define GPIO_INTTYPE_TYPE9_Pos           (9)                                               /*!< GPIO_T::INTTYPE: TYPE9 Position           */
+#define GPIO_INTTYPE_TYPE9_Msk           (0x1ul << GPIO_INTTYPE_TYPE9_Pos)                 /*!< GPIO_T::INTTYPE: TYPE9 Mask               */
+
+#define GPIO_INTTYPE_TYPE10_Pos          (10)                                              /*!< GPIO_T::INTTYPE: TYPE10 Position          */
+#define GPIO_INTTYPE_TYPE10_Msk          (0x1ul << GPIO_INTTYPE_TYPE10_Pos)                /*!< GPIO_T::INTTYPE: TYPE10 Mask              */
+
+#define GPIO_INTTYPE_TYPE11_Pos          (11)                                              /*!< GPIO_T::INTTYPE: TYPE11 Position          */
+#define GPIO_INTTYPE_TYPE11_Msk          (0x1ul << GPIO_INTTYPE_TYPE11_Pos)                /*!< GPIO_T::INTTYPE: TYPE11 Mask              */
+
+#define GPIO_INTTYPE_TYPE12_Pos          (12)                                              /*!< GPIO_T::INTTYPE: TYPE12 Position          */
+#define GPIO_INTTYPE_TYPE12_Msk          (0x1ul << GPIO_INTTYPE_TYPE12_Pos)                /*!< GPIO_T::INTTYPE: TYPE12 Mask              */
+
+#define GPIO_INTTYPE_TYPE13_Pos          (13)                                              /*!< GPIO_T::INTTYPE: TYPE13 Position          */
+#define GPIO_INTTYPE_TYPE13_Msk          (0x1ul << GPIO_INTTYPE_TYPE13_Pos)                /*!< GPIO_T::INTTYPE: TYPE13 Mask              */
+
+#define GPIO_INTTYPE_TYPE14_Pos          (14)                                              /*!< GPIO_T::INTTYPE: TYPE14 Position          */
+#define GPIO_INTTYPE_TYPE14_Msk          (0x1ul << GPIO_INTTYPE_TYPE14_Pos)                /*!< GPIO_T::INTTYPE: TYPE14 Mask              */
+
+#define GPIO_INTTYPE_TYPE15_Pos          (15)                                              /*!< GPIO_T::INTTYPE: TYPE15 Position          */
+#define GPIO_INTTYPE_TYPE15_Msk          (0x1ul << GPIO_INTTYPE_TYPE15_Pos)                /*!< GPIO_T::INTTYPE: TYPE15 Mask              */
+
+#define GPIO_INTEN_FLIEN0_Pos            (0)                                               /*!< GPIO_T::INTEN: FLIEN0 Position            */
+#define GPIO_INTEN_FLIEN0_Msk            (0x1ul << GPIO_INTEN_FLIEN0_Pos)                  /*!< GPIO_T::INTEN: FLIEN0 Mask                */
+
+#define GPIO_INTEN_FLIEN1_Pos            (1)                                               /*!< GPIO_T::INTEN: FLIEN1 Position            */
+#define GPIO_INTEN_FLIEN1_Msk            (0x1ul << GPIO_INTEN_FLIEN1_Pos)                  /*!< GPIO_T::INTEN: FLIEN1 Mask                */
+
+#define GPIO_INTEN_FLIEN2_Pos            (2)                                               /*!< GPIO_T::INTEN: FLIEN2 Position            */
+#define GPIO_INTEN_FLIEN2_Msk            (0x1ul << GPIO_INTEN_FLIEN2_Pos)                  /*!< GPIO_T::INTEN: FLIEN2 Mask                */
+
+#define GPIO_INTEN_FLIEN3_Pos            (3)                                               /*!< GPIO_T::INTEN: FLIEN3 Position            */
+#define GPIO_INTEN_FLIEN3_Msk            (0x1ul << GPIO_INTEN_FLIEN3_Pos)                  /*!< GPIO_T::INTEN: FLIEN3 Mask                */
+
+#define GPIO_INTEN_FLIEN4_Pos            (4)                                               /*!< GPIO_T::INTEN: FLIEN4 Position            */
+#define GPIO_INTEN_FLIEN4_Msk            (0x1ul << GPIO_INTEN_FLIEN4_Pos)                  /*!< GPIO_T::INTEN: FLIEN4 Mask                */
+
+#define GPIO_INTEN_FLIEN5_Pos            (5)                                               /*!< GPIO_T::INTEN: FLIEN5 Position            */
+#define GPIO_INTEN_FLIEN5_Msk            (0x1ul << GPIO_INTEN_FLIEN5_Pos)                  /*!< GPIO_T::INTEN: FLIEN5 Mask                */
+
+#define GPIO_INTEN_FLIEN6_Pos            (6)                                               /*!< GPIO_T::INTEN: FLIEN6 Position            */
+#define GPIO_INTEN_FLIEN6_Msk            (0x1ul << GPIO_INTEN_FLIEN6_Pos)                  /*!< GPIO_T::INTEN: FLIEN6 Mask                */
+
+#define GPIO_INTEN_FLIEN7_Pos            (7)                                               /*!< GPIO_T::INTEN: FLIEN7 Position            */
+#define GPIO_INTEN_FLIEN7_Msk            (0x1ul << GPIO_INTEN_FLIEN7_Pos)                  /*!< GPIO_T::INTEN: FLIEN7 Mask                */
+
+#define GPIO_INTEN_FLIEN8_Pos            (8)                                               /*!< GPIO_T::INTEN: FLIEN8 Position            */
+#define GPIO_INTEN_FLIEN8_Msk            (0x1ul << GPIO_INTEN_FLIEN8_Pos)                  /*!< GPIO_T::INTEN: FLIEN8 Mask                */
+
+#define GPIO_INTEN_FLIEN9_Pos            (9)                                               /*!< GPIO_T::INTEN: FLIEN9 Position            */
+#define GPIO_INTEN_FLIEN9_Msk            (0x1ul << GPIO_INTEN_FLIEN9_Pos)                  /*!< GPIO_T::INTEN: FLIEN9 Mask                */
+
+#define GPIO_INTEN_FLIEN10_Pos           (10)                                              /*!< GPIO_T::INTEN: FLIEN10 Position           */
+#define GPIO_INTEN_FLIEN10_Msk           (0x1ul << GPIO_INTEN_FLIEN10_Pos)                 /*!< GPIO_T::INTEN: FLIEN10 Mask               */
+
+#define GPIO_INTEN_FLIEN11_Pos           (11)                                              /*!< GPIO_T::INTEN: FLIEN11 Position           */
+#define GPIO_INTEN_FLIEN11_Msk           (0x1ul << GPIO_INTEN_FLIEN11_Pos)                 /*!< GPIO_T::INTEN: FLIEN11 Mask               */
+
+#define GPIO_INTEN_FLIEN12_Pos           (12)                                              /*!< GPIO_T::INTEN: FLIEN12 Position           */
+#define GPIO_INTEN_FLIEN12_Msk           (0x1ul << GPIO_INTEN_FLIEN12_Pos)                 /*!< GPIO_T::INTEN: FLIEN12 Mask               */
+
+#define GPIO_INTEN_FLIEN13_Pos           (13)                                              /*!< GPIO_T::INTEN: FLIEN13 Position           */
+#define GPIO_INTEN_FLIEN13_Msk           (0x1ul << GPIO_INTEN_FLIEN13_Pos)                 /*!< GPIO_T::INTEN: FLIEN13 Mask               */
+
+#define GPIO_INTEN_FLIEN14_Pos           (14)                                              /*!< GPIO_T::INTEN: FLIEN14 Position           */
+#define GPIO_INTEN_FLIEN14_Msk           (0x1ul << GPIO_INTEN_FLIEN14_Pos)                 /*!< GPIO_T::INTEN: FLIEN14 Mask               */
+
+#define GPIO_INTEN_FLIEN15_Pos           (15)                                              /*!< GPIO_T::INTEN: FLIEN15 Position           */
+#define GPIO_INTEN_FLIEN15_Msk           (0x1ul << GPIO_INTEN_FLIEN15_Pos)                 /*!< GPIO_T::INTEN: FLIEN15 Mask               */
+
+#define GPIO_INTEN_RHIEN0_Pos            (16)                                              /*!< GPIO_T::INTEN: RHIEN0 Position            */
+#define GPIO_INTEN_RHIEN0_Msk            (0x1ul << GPIO_INTEN_RHIEN0_Pos)                  /*!< GPIO_T::INTEN: RHIEN0 Mask                */
+
+#define GPIO_INTEN_RHIEN1_Pos            (17)                                              /*!< GPIO_T::INTEN: RHIEN1 Position            */
+#define GPIO_INTEN_RHIEN1_Msk            (0x1ul << GPIO_INTEN_RHIEN1_Pos)                  /*!< GPIO_T::INTEN: RHIEN1 Mask                */
+
+#define GPIO_INTEN_RHIEN2_Pos            (18)                                              /*!< GPIO_T::INTEN: RHIEN2 Position            */
+#define GPIO_INTEN_RHIEN2_Msk            (0x1ul << GPIO_INTEN_RHIEN2_Pos)                  /*!< GPIO_T::INTEN: RHIEN2 Mask                */
+
+#define GPIO_INTEN_RHIEN3_Pos            (19)                                              /*!< GPIO_T::INTEN: RHIEN3 Position            */
+#define GPIO_INTEN_RHIEN3_Msk            (0x1ul << GPIO_INTEN_RHIEN3_Pos)                  /*!< GPIO_T::INTEN: RHIEN3 Mask                */
+
+#define GPIO_INTEN_RHIEN4_Pos            (20)                                              /*!< GPIO_T::INTEN: RHIEN4 Position            */
+#define GPIO_INTEN_RHIEN4_Msk            (0x1ul << GPIO_INTEN_RHIEN4_Pos)                  /*!< GPIO_T::INTEN: RHIEN4 Mask                */
+
+#define GPIO_INTEN_RHIEN5_Pos            (21)                                              /*!< GPIO_T::INTEN: RHIEN5 Position            */
+#define GPIO_INTEN_RHIEN5_Msk            (0x1ul << GPIO_INTEN_RHIEN5_Pos)                  /*!< GPIO_T::INTEN: RHIEN5 Mask                */
+
+#define GPIO_INTEN_RHIEN6_Pos            (22)                                              /*!< GPIO_T::INTEN: RHIEN6 Position            */
+#define GPIO_INTEN_RHIEN6_Msk            (0x1ul << GPIO_INTEN_RHIEN6_Pos)                  /*!< GPIO_T::INTEN: RHIEN6 Mask                */
+
+#define GPIO_INTEN_RHIEN7_Pos            (23)                                              /*!< GPIO_T::INTEN: RHIEN7 Position            */
+#define GPIO_INTEN_RHIEN7_Msk            (0x1ul << GPIO_INTEN_RHIEN7_Pos)                  /*!< GPIO_T::INTEN: RHIEN7 Mask                */
+
+#define GPIO_INTEN_RHIEN8_Pos            (24)                                              /*!< GPIO_T::INTEN: RHIEN8 Position            */
+#define GPIO_INTEN_RHIEN8_Msk            (0x1ul << GPIO_INTEN_RHIEN8_Pos)                  /*!< GPIO_T::INTEN: RHIEN8 Mask                */
+
+#define GPIO_INTEN_RHIEN9_Pos            (25)                                              /*!< GPIO_T::INTEN: RHIEN9 Position            */
+#define GPIO_INTEN_RHIEN9_Msk            (0x1ul << GPIO_INTEN_RHIEN9_Pos)                  /*!< GPIO_T::INTEN: RHIEN9 Mask                */
+
+#define GPIO_INTEN_RHIEN10_Pos           (26)                                              /*!< GPIO_T::INTEN: RHIEN10 Position           */
+#define GPIO_INTEN_RHIEN10_Msk           (0x1ul << GPIO_INTEN_RHIEN10_Pos)                 /*!< GPIO_T::INTEN: RHIEN10 Mask               */
+
+#define GPIO_INTEN_RHIEN11_Pos           (27)                                              /*!< GPIO_T::INTEN: RHIEN11 Position           */
+#define GPIO_INTEN_RHIEN11_Msk           (0x1ul << GPIO_INTEN_RHIEN11_Pos)                 /*!< GPIO_T::INTEN: RHIEN11 Mask               */
+
+#define GPIO_INTEN_RHIEN12_Pos           (28)                                              /*!< GPIO_T::INTEN: RHIEN12 Position           */
+#define GPIO_INTEN_RHIEN12_Msk           (0x1ul << GPIO_INTEN_RHIEN12_Pos)                 /*!< GPIO_T::INTEN: RHIEN12 Mask               */
+
+#define GPIO_INTEN_RHIEN13_Pos           (29)                                              /*!< GPIO_T::INTEN: RHIEN13 Position           */
+#define GPIO_INTEN_RHIEN13_Msk           (0x1ul << GPIO_INTEN_RHIEN13_Pos)                 /*!< GPIO_T::INTEN: RHIEN13 Mask               */
+
+#define GPIO_INTEN_RHIEN14_Pos           (30)                                              /*!< GPIO_T::INTEN: RHIEN14 Position           */
+#define GPIO_INTEN_RHIEN14_Msk           (0x1ul << GPIO_INTEN_RHIEN14_Pos)                 /*!< GPIO_T::INTEN: RHIEN14 Mask               */
+
+#define GPIO_INTEN_RHIEN15_Pos           (31)                                              /*!< GPIO_T::INTEN: RHIEN15 Position           */
+#define GPIO_INTEN_RHIEN15_Msk           (0x1ul << GPIO_INTEN_RHIEN15_Pos)                 /*!< GPIO_T::INTEN: RHIEN15 Mask               */
+
+#define GPIO_INTSRC_INTSRC0_Pos          (0)                                               /*!< GPIO_T::INTSRC: INTSRC0 Position          */
+#define GPIO_INTSRC_INTSRC0_Msk          (0x1ul << GPIO_INTSRC_INTSRC0_Pos)                /*!< GPIO_T::INTSRC: INTSRC0 Mask              */
+
+#define GPIO_INTSRC_INTSRC1_Pos          (1)                                               /*!< GPIO_T::INTSRC: INTSRC1 Position          */
+#define GPIO_INTSRC_INTSRC1_Msk          (0x1ul << GPIO_INTSRC_INTSRC1_Pos)                /*!< GPIO_T::INTSRC: INTSRC1 Mask              */
+
+#define GPIO_INTSRC_INTSRC2_Pos          (2)                                               /*!< GPIO_T::INTSRC: INTSRC2 Position          */
+#define GPIO_INTSRC_INTSRC2_Msk          (0x1ul << GPIO_INTSRC_INTSRC2_Pos)                /*!< GPIO_T::INTSRC: INTSRC2 Mask              */
+
+#define GPIO_INTSRC_INTSRC3_Pos          (3)                                               /*!< GPIO_T::INTSRC: INTSRC3 Position          */
+#define GPIO_INTSRC_INTSRC3_Msk          (0x1ul << GPIO_INTSRC_INTSRC3_Pos)                /*!< GPIO_T::INTSRC: INTSRC3 Mask              */
+
+#define GPIO_INTSRC_INTSRC4_Pos          (4)                                               /*!< GPIO_T::INTSRC: INTSRC4 Position          */
+#define GPIO_INTSRC_INTSRC4_Msk          (0x1ul << GPIO_INTSRC_INTSRC4_Pos)                /*!< GPIO_T::INTSRC: INTSRC4 Mask              */
+
+#define GPIO_INTSRC_INTSRC5_Pos          (5)                                               /*!< GPIO_T::INTSRC: INTSRC5 Position          */
+#define GPIO_INTSRC_INTSRC5_Msk          (0x1ul << GPIO_INTSRC_INTSRC5_Pos)                /*!< GPIO_T::INTSRC: INTSRC5 Mask              */
+
+#define GPIO_INTSRC_INTSRC6_Pos          (6)                                               /*!< GPIO_T::INTSRC: INTSRC6 Position          */
+#define GPIO_INTSRC_INTSRC6_Msk          (0x1ul << GPIO_INTSRC_INTSRC6_Pos)                /*!< GPIO_T::INTSRC: INTSRC6 Mask              */
+
+#define GPIO_INTSRC_INTSRC7_Pos          (7)                                               /*!< GPIO_T::INTSRC: INTSRC7 Position          */
+#define GPIO_INTSRC_INTSRC7_Msk          (0x1ul << GPIO_INTSRC_INTSRC7_Pos)                /*!< GPIO_T::INTSRC: INTSRC7 Mask              */
+
+#define GPIO_INTSRC_INTSRC8_Pos          (8)                                               /*!< GPIO_T::INTSRC: INTSRC8 Position          */
+#define GPIO_INTSRC_INTSRC8_Msk          (0x1ul << GPIO_INTSRC_INTSRC8_Pos)                /*!< GPIO_T::INTSRC: INTSRC8 Mask              */
+
+#define GPIO_INTSRC_INTSRC9_Pos          (9)                                               /*!< GPIO_T::INTSRC: INTSRC9 Position          */
+#define GPIO_INTSRC_INTSRC9_Msk          (0x1ul << GPIO_INTSRC_INTSRC9_Pos)                /*!< GPIO_T::INTSRC: INTSRC9 Mask              */
+
+#define GPIO_INTSRC_INTSRC10_Pos         (10)                                              /*!< GPIO_T::INTSRC: INTSRC10 Position         */
+#define GPIO_INTSRC_INTSRC10_Msk         (0x1ul << GPIO_INTSRC_INTSRC10_Pos)               /*!< GPIO_T::INTSRC: INTSRC10 Mask             */
+
+#define GPIO_INTSRC_INTSRC11_Pos         (11)                                              /*!< GPIO_T::INTSRC: INTSRC11 Position         */
+#define GPIO_INTSRC_INTSRC11_Msk         (0x1ul << GPIO_INTSRC_INTSRC11_Pos)               /*!< GPIO_T::INTSRC: INTSRC11 Mask             */
+
+#define GPIO_INTSRC_INTSRC12_Pos         (12)                                              /*!< GPIO_T::INTSRC: INTSRC12 Position         */
+#define GPIO_INTSRC_INTSRC12_Msk         (0x1ul << GPIO_INTSRC_INTSRC12_Pos)               /*!< GPIO_T::INTSRC: INTSRC12 Mask             */
+
+#define GPIO_INTSRC_INTSRC13_Pos         (13)                                              /*!< GPIO_T::INTSRC: INTSRC13 Position         */
+#define GPIO_INTSRC_INTSRC13_Msk         (0x1ul << GPIO_INTSRC_INTSRC13_Pos)               /*!< GPIO_T::INTSRC: INTSRC13 Mask             */
+
+#define GPIO_INTSRC_INTSRC14_Pos         (14)                                              /*!< GPIO_T::INTSRC: INTSRC14 Position         */
+#define GPIO_INTSRC_INTSRC14_Msk         (0x1ul << GPIO_INTSRC_INTSRC14_Pos)               /*!< GPIO_T::INTSRC: INTSRC14 Mask             */
+
+#define GPIO_INTSRC_INTSRC15_Pos         (15)                                              /*!< GPIO_T::INTSRC: INTSRC15 Position         */
+#define GPIO_INTSRC_INTSRC15_Msk         (0x1ul << GPIO_INTSRC_INTSRC15_Pos)               /*!< GPIO_T::INTSRC: INTSRC15 Mask             */
+
+#define GPIO_SMTEN_SMTEN0_Pos            (0)                                               /*!< GPIO_T::SMTEN: SMTEN0 Position            */
+#define GPIO_SMTEN_SMTEN0_Msk            (0x1ul << GPIO_SMTEN_SMTEN0_Pos)                  /*!< GPIO_T::SMTEN: SMTEN0 Mask                */
+
+#define GPIO_SMTEN_SMTEN1_Pos            (1)                                               /*!< GPIO_T::SMTEN: SMTEN1 Position            */
+#define GPIO_SMTEN_SMTEN1_Msk            (0x1ul << GPIO_SMTEN_SMTEN1_Pos)                  /*!< GPIO_T::SMTEN: SMTEN1 Mask                */
+
+#define GPIO_SMTEN_SMTEN2_Pos            (2)                                               /*!< GPIO_T::SMTEN: SMTEN2 Position            */
+#define GPIO_SMTEN_SMTEN2_Msk            (0x1ul << GPIO_SMTEN_SMTEN2_Pos)                  /*!< GPIO_T::SMTEN: SMTEN2 Mask                */
+
+#define GPIO_SMTEN_SMTEN3_Pos            (3)                                               /*!< GPIO_T::SMTEN: SMTEN3 Position            */
+#define GPIO_SMTEN_SMTEN3_Msk            (0x1ul << GPIO_SMTEN_SMTEN3_Pos)                  /*!< GPIO_T::SMTEN: SMTEN3 Mask                */
+
+#define GPIO_SMTEN_SMTEN4_Pos            (4)                                               /*!< GPIO_T::SMTEN: SMTEN4 Position            */
+#define GPIO_SMTEN_SMTEN4_Msk            (0x1ul << GPIO_SMTEN_SMTEN4_Pos)                  /*!< GPIO_T::SMTEN: SMTEN4 Mask                */
+
+#define GPIO_SMTEN_SMTEN5_Pos            (5)                                               /*!< GPIO_T::SMTEN: SMTEN5 Position            */
+#define GPIO_SMTEN_SMTEN5_Msk            (0x1ul << GPIO_SMTEN_SMTEN5_Pos)                  /*!< GPIO_T::SMTEN: SMTEN5 Mask                */
+
+#define GPIO_SMTEN_SMTEN6_Pos            (6)                                               /*!< GPIO_T::SMTEN: SMTEN6 Position            */
+#define GPIO_SMTEN_SMTEN6_Msk            (0x1ul << GPIO_SMTEN_SMTEN6_Pos)                  /*!< GPIO_T::SMTEN: SMTEN6 Mask                */
+
+#define GPIO_SMTEN_SMTEN7_Pos            (7)                                               /*!< GPIO_T::SMTEN: SMTEN7 Position            */
+#define GPIO_SMTEN_SMTEN7_Msk            (0x1ul << GPIO_SMTEN_SMTEN7_Pos)                  /*!< GPIO_T::SMTEN: SMTEN7 Mask                */
+
+#define GPIO_SMTEN_SMTEN8_Pos            (8)                                               /*!< GPIO_T::SMTEN: SMTEN8 Position            */
+#define GPIO_SMTEN_SMTEN8_Msk            (0x1ul << GPIO_SMTEN_SMTEN8_Pos)                  /*!< GPIO_T::SMTEN: SMTEN8 Mask                */
+
+#define GPIO_SMTEN_SMTEN9_Pos            (9)                                               /*!< GPIO_T::SMTEN: SMTEN9 Position            */
+#define GPIO_SMTEN_SMTEN9_Msk            (0x1ul << GPIO_SMTEN_SMTEN9_Pos)                  /*!< GPIO_T::SMTEN: SMTEN9 Mask                */
+
+#define GPIO_SMTEN_SMTEN10_Pos           (10)                                              /*!< GPIO_T::SMTEN: SMTEN10 Position           */
+#define GPIO_SMTEN_SMTEN10_Msk           (0x1ul << GPIO_SMTEN_SMTEN10_Pos)                 /*!< GPIO_T::SMTEN: SMTEN10 Mask               */
+
+#define GPIO_SMTEN_SMTEN11_Pos           (11)                                              /*!< GPIO_T::SMTEN: SMTEN11 Position           */
+#define GPIO_SMTEN_SMTEN11_Msk           (0x1ul << GPIO_SMTEN_SMTEN11_Pos)                 /*!< GPIO_T::SMTEN: SMTEN11 Mask               */
+
+#define GPIO_SMTEN_SMTEN12_Pos           (12)                                              /*!< GPIO_T::SMTEN: SMTEN12 Position           */
+#define GPIO_SMTEN_SMTEN12_Msk           (0x1ul << GPIO_SMTEN_SMTEN12_Pos)                 /*!< GPIO_T::SMTEN: SMTEN12 Mask               */
+
+#define GPIO_SMTEN_SMTEN13_Pos           (13)                                              /*!< GPIO_T::SMTEN: SMTEN13 Position           */
+#define GPIO_SMTEN_SMTEN13_Msk           (0x1ul << GPIO_SMTEN_SMTEN13_Pos)                 /*!< GPIO_T::SMTEN: SMTEN13 Mask               */
+
+#define GPIO_SMTEN_SMTEN14_Pos           (14)                                              /*!< GPIO_T::SMTEN: SMTEN14 Position           */
+#define GPIO_SMTEN_SMTEN14_Msk           (0x1ul << GPIO_SMTEN_SMTEN14_Pos)                 /*!< GPIO_T::SMTEN: SMTEN14 Mask               */
+
+#define GPIO_SMTEN_SMTEN15_Pos           (15)                                              /*!< GPIO_T::SMTEN: SMTEN15 Position           */
+#define GPIO_SMTEN_SMTEN15_Msk           (0x1ul << GPIO_SMTEN_SMTEN15_Pos)                 /*!< GPIO_T::SMTEN: SMTEN15 Mask               */
+
+#define GPIO_SLEWCTL_HSREN0_Pos          (0)                                               /*!< GPIO_T::SLEWCTL: HSREN0 Position          */
+#define GPIO_SLEWCTL_HSREN0_Msk          (0x1ul << GPIO_SLEWCTL_HSREN0_Pos)                /*!< GPIO_T::SLEWCTL: HSREN0 Mask              */
+
+#define GPIO_SLEWCTL_HSREN1_Pos          (1)                                               /*!< GPIO_T::SLEWCTL: HSREN1 Position          */
+#define GPIO_SLEWCTL_HSREN1_Msk          (0x1ul << GPIO_SLEWCTL_HSREN1_Pos)                /*!< GPIO_T::SLEWCTL: HSREN1 Mask              */
+
+#define GPIO_SLEWCTL_HSREN2_Pos          (2)                                               /*!< GPIO_T::SLEWCTL: HSREN2 Position          */
+#define GPIO_SLEWCTL_HSREN2_Msk          (0x1ul << GPIO_SLEWCTL_HSREN2_Pos)                /*!< GPIO_T::SLEWCTL: HSREN2 Mask              */
+
+#define GPIO_SLEWCTL_HSREN3_Pos          (3)                                               /*!< GPIO_T::SLEWCTL: HSREN3 Position          */
+#define GPIO_SLEWCTL_HSREN3_Msk          (0x1ul << GPIO_SLEWCTL_HSREN3_Pos)                /*!< GPIO_T::SLEWCTL: HSREN3 Mask              */
+
+#define GPIO_SLEWCTL_HSREN4_Pos          (4)                                               /*!< GPIO_T::SLEWCTL: HSREN4 Position          */
+#define GPIO_SLEWCTL_HSREN4_Msk          (0x1ul << GPIO_SLEWCTL_HSREN4_Pos)                /*!< GPIO_T::SLEWCTL: HSREN4 Mask              */
+
+#define GPIO_SLEWCTL_HSREN5_Pos          (5)                                               /*!< GPIO_T::SLEWCTL: HSREN5 Position          */
+#define GPIO_SLEWCTL_HSREN5_Msk          (0x1ul << GPIO_SLEWCTL_HSREN5_Pos)                /*!< GPIO_T::SLEWCTL: HSREN5 Mask              */
+
+#define GPIO_SLEWCTL_HSREN6_Pos          (6)                                               /*!< GPIO_T::SLEWCTL: HSREN6 Position          */
+#define GPIO_SLEWCTL_HSREN6_Msk          (0x1ul << GPIO_SLEWCTL_HSREN6_Pos)                /*!< GPIO_T::SLEWCTL: HSREN6 Mask              */
+
+#define GPIO_SLEWCTL_HSREN7_Pos          (7)                                               /*!< GPIO_T::SLEWCTL: HSREN7 Position          */
+#define GPIO_SLEWCTL_HSREN7_Msk          (0x1ul << GPIO_SLEWCTL_HSREN7_Pos)                /*!< GPIO_T::SLEWCTL: HSREN7 Mask              */
+
+#define GPIO_SLEWCTL_HSREN8_Pos          (8)                                               /*!< GPIO_T::SLEWCTL: HSREN8 Position          */
+#define GPIO_SLEWCTL_HSREN8_Msk          (0x1ul << GPIO_SLEWCTL_HSREN8_Pos)                /*!< GPIO_T::SLEWCTL: HSREN8 Mask              */
+
+#define GPIO_SLEWCTL_HSREN9_Pos          (9)                                               /*!< GPIO_T::SLEWCTL: HSREN9 Position          */
+#define GPIO_SLEWCTL_HSREN9_Msk          (0x1ul << GPIO_SLEWCTL_HSREN9_Pos)                /*!< GPIO_T::SLEWCTL: HSREN9 Mask              */
+
+#define GPIO_SLEWCTL_HSREN10_Pos         (10)                                              /*!< GPIO_T::SLEWCTL: HSREN10 Position         */
+#define GPIO_SLEWCTL_HSREN10_Msk         (0x1ul << GPIO_SLEWCTL_HSREN10_Pos)               /*!< GPIO_T::SLEWCTL: HSREN10 Mask             */
+
+#define GPIO_SLEWCTL_HSREN11_Pos         (11)                                              /*!< GPIO_T::SLEWCTL: HSREN11 Position         */
+#define GPIO_SLEWCTL_HSREN11_Msk         (0x1ul << GPIO_SLEWCTL_HSREN11_Pos)               /*!< GPIO_T::SLEWCTL: HSREN11 Mask             */
+
+#define GPIO_SLEWCTL_HSREN12_Pos         (12)                                              /*!< GPIO_T::SLEWCTL: HSREN12 Position         */
+#define GPIO_SLEWCTL_HSREN12_Msk         (0x1ul << GPIO_SLEWCTL_HSREN12_Pos)               /*!< GPIO_T::SLEWCTL: HSREN12 Mask             */
+
+#define GPIO_SLEWCTL_HSREN13_Pos         (13)                                              /*!< GPIO_T::SLEWCTL: HSREN13 Position         */
+#define GPIO_SLEWCTL_HSREN13_Msk         (0x1ul << GPIO_SLEWCTL_HSREN13_Pos)               /*!< GPIO_T::SLEWCTL: HSREN13 Mask             */
+
+#define GPIO_SLEWCTL_HSREN14_Pos         (14)                                              /*!< GPIO_T::SLEWCTL: HSREN14 Position         */
+#define GPIO_SLEWCTL_HSREN14_Msk         (0x1ul << GPIO_SLEWCTL_HSREN14_Pos)               /*!< GPIO_T::SLEWCTL: HSREN14 Mask             */
+
+#define GPIO_SLEWCTL_HSREN15_Pos         (15)                                              /*!< GPIO_T::SLEWCTL: HSREN15 Position         */
+#define GPIO_SLEWCTL_HSREN15_Msk         (0x1ul << GPIO_SLEWCTL_HSREN15_Pos)               /*!< GPIO_T::SLEWCTL: HSREN15 Mask             */
+
+#define GPIO_DRVCTL_HDRVEN8_Pos          (8)                                               /*!< GPIO_T::DRVCTL: HDRVEN8 Position          */
+#define GPIO_DRVCTL_HDRVEN8_Msk          (0x1ul << GPIO_DRVCTL_HDRVEN8_Pos)                /*!< GPIO_T::DRVCTL: HDRVEN8 Mask              */
+
+#define GPIO_DRVCTL_HDRVEN9_Pos          (9)                                               /*!< GPIO_T::DRVCTL: HDRVEN9 Position          */
+#define GPIO_DRVCTL_HDRVEN9_Msk          (0x1ul << GPIO_DRVCTL_HDRVEN9_Pos)                /*!< GPIO_T::DRVCTL: HDRVEN9 Mask              */
+
+#define GPIO_DRVCTL_HDRVEN10_Pos         (10)                                              /*!< GPIO_T::DRVCTL: HDRVEN10 Position         */
+#define GPIO_DRVCTL_HDRVEN10_Msk         (0x1ul << GPIO_DRVCTL_HDRVEN10_Pos)               /*!< GPIO_T::DRVCTL: HDRVEN10 Mask             */
+
+#define GPIO_DRVCTL_HDRVEN11_Pos         (11)                                              /*!< GPIO_T::DRVCTL: HDRVEN11 Position         */
+#define GPIO_DRVCTL_HDRVEN11_Msk         (0x1ul << GPIO_DRVCTL_HDRVEN11_Pos)               /*!< GPIO_T::DRVCTL: HDRVEN11 Mask             */
+
+#define GPIO_DRVCTL_HDRVEN12_Pos         (12)                                              /*!< GPIO_T::DRVCTL: HDRVEN12 Position         */
+#define GPIO_DRVCTL_HDRVEN12_Msk         (0x1ul << GPIO_DRVCTL_HDRVEN12_Pos)               /*!< GPIO_T::DRVCTL: HDRVEN12 Mask             */
+
+#define GPIO_DRVCTL_HDRVEN13_Pos         (13)                                              /*!< GPIO_T::DRVCTL: HDRVEN13 Position         */
+#define GPIO_DRVCTL_HDRVEN13_Msk         (0x1ul << GPIO_DRVCTL_HDRVEN13_Pos)               /*!< GPIO_T::DRVCTL: HDRVEN13 Mask             */
+
+#define GPIO_DBCTL_DBCLKSEL_Pos          (0)                                               /*!< GPIO_T::DBCTL: DBCLKSEL Position          */
+#define GPIO_DBCTL_DBCLKSEL_Msk          (0xFul << GPIO_DBCTL_DBCLKSEL_Pos)                /*!< GPIO_T::DBCTL: DBCLKSEL Mask              */
+
+#define GPIO_DBCTL_DBCLKSRC_Pos          (4)                                               /*!< GPIO_T::DBCTL: DBCLKSRC Position          */
+#define GPIO_DBCTL_DBCLKSRC_Msk          (1ul << GPIO_DBCTL_DBCLKSRC_Pos)                  /*!< GPIO_T::DBCTL: DBCLKSRC Mask              */
+
+#define GPIO_DBCTL_ICLKON_Pos            (5)                                               /*!< GPIO_T::DBCTL: ICLKON Position            */
+#define GPIO_DBCTL_ICLKON_Msk            (1ul << GPIO_DBCTL_ICLKON_Pos)                    /*!< GPIO_T::DBCTL: ICLKON Mask                */
+
+
+/**@}*/ /* GPIO_CONST */
+/**@}*/ /* end of GPIO register group */
+
+
+/*---------------------- Inter-IC Bus Controller -------------------------*/
+/**
+    @addtogroup I2C Inter-IC Bus Controller(I2C)
+    Memory Mapped Structure for I2C Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var I2C_T::CTL
+ * Offset: 0x00  I2C Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[2]     |AA        |Assert Acknowledge Control
+ * |        |          |When AA =1 prior to address or data is received, 
+ * |        |          |an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 
+ * |        |          |1. A slave is acknowledging the address sent from master. 
+ * |        |          |2. The receiver devices are acknowledging the data sent by transmitter.
+ * |        |          |When AA=0 prior to address or data received, 
+ * |        |          |a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
+ * |[3]     |SI        |I2C Interrupt Flag
+ * |        |          |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware.
+ * |        |          |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested.
+ * |        |          |SI must be cleared by software.
+ * |        |          |Clear SI by writing 1 to this bit.
+ * |        |          |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
+ * |[4]     |STO       |I2C STOP Control
+ * |        |          |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected.
+ * |        |          |This bit will be cleared by hardware automatically.
+ * |[5]     |STA       |I2C START Control
+ * |        |          |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
+ * |[6]     |I2CEN     |I2C Controller Enable Bit
+ * |        |          |Set to enable I2C serial function controller.
+ * |        |          |When I2CEN=1 the I2C serial function enable.
+ * |        |          |The multi-function pin function must set to SDA, and SCL of I2C function first.
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[7]     |INTEN     |Enable Interrupt
+ * |        |          |0 = I2C interrupt Disabled.
+ * |        |          |1 = I2C interrupt Enabled.
+ * @var I2C_T::ADDR0
+ * Offset: 0x04  I2C Slave Address Register0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |GC        |General Call Function
+ * |        |          |0 = General Call Function Disabled.
+ * |        |          |1 = General Call Function Enabled.
+ * |[7:1]   |ADDR      |I2C Address
+ * |        |          |The content of this register is irrelevant when I2C is in Master mode.
+ * |        |          |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
+ * |        |          |The I2C hardware will react if either of the address is matched.
+ * @var I2C_T::DAT
+ * Offset: 0x08  I2C Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |DAT       |I2C Data
+ * |        |          |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
+ * @var I2C_T::STATUS
+ * Offset: 0x0C  I2C Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |STATUS    |I2C Status
+ * |        |          |The three least significant bits are always 0.
+ * |        |          |The five most significant bits contain the status code.
+ * |        |          |There are 28 possible status codes.
+ * |        |          |When the content of I2C_STATUS is F8H, no serial interrupt is requested.
+ * |        |          |Others I2C_STATUS values correspond to defined I2C states.
+ * |        |          |When each of these states is entered, a status interrupt is requested (SI = 1).
+ * |        |          |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software.
+ * |        |          |In addition, states 00H stands for a Bus Error.
+ * |        |          |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame.
+ * |        |          |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
+ * |        |          |Note:
+ * |        |          |1.
+ * |        |          |If the BUSEN and ACKMEN are enabled in slave received mode, there is SI interrupt in the 8th clock.
+ * |        |          |The user can read the I2C_STATUS = 0xf0 for the function condition has done.
+ * |        |          |2.
+ * |        |          |If the BUSEN and PECEN are enabled, the status of PECERR, I2C_BUSSTS[3], is used to substitute for I2C_STATUS to check the ACK status in the last frame when the byte count done interrupt has active and the PEC frame has been transformed.
+ * @var I2C_T::CLKDIV
+ * Offset: 0x10  I2C Clock Divided Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |DIVIDER   |I2C Clock Divided
+ * |        |          |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
+ * |        |          |Note: The minimum value of I2C_CLKDIV is 4.
+ * @var I2C_T::TOCTL
+ * Offset: 0x14  I2C Time-out Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |TOIF      |Time-Out Flag
+ * |        |          |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
+ * |        |          |Note: Software can write 1 to clear this bit.
+ * |[1]     |TOCDIV4   |Time-Out Counter Input Clock Divided By 4
+ * |        |          |When Enabled, The time-out period is extend 4 times.
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[2]     |TOCEN     |Time-Out Counter Enable Bit
+ * |        |          |When Enabled, the 14-bit time-out counter will start counting when SI is clear.
+ * |        |          |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * @var I2C_T::ADDR1
+ * Offset: 0x18  I2C Slave Address Register1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |GC        |General Call Function
+ * |        |          |0 = General Call Function Disabled.
+ * |        |          |1 = General Call Function Enabled.
+ * |[7:1]   |ADDR      |I2C Address
+ * |        |          |The content of this register is irrelevant when I2C is in Master mode.
+ * |        |          |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
+ * |        |          |The I2C hardware will react if either of the address is matched.
+ * @var I2C_T::ADDR2
+ * Offset: 0x1C  I2C Slave Address Register2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |GC        |General Call Function
+ * |        |          |0 = General Call Function Disabled.
+ * |        |          |1 = General Call Function Enabled.
+ * |[7:1]   |ADDR      |I2C Address
+ * |        |          |The content of this register is irrelevant when I2C is in Master mode.
+ * |        |          |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
+ * |        |          |The I2C hardware will react if either of the address is matched.
+ * @var I2C_T::ADDR3
+ * Offset: 0x20  I2C Slave Address Register3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |GC        |General Call Function
+ * |        |          |0 = General Call Function Disabled.
+ * |        |          |1 = General Call Function Enabled.
+ * |[7:1]   |ADDR      |I2C Address
+ * |        |          |The content of this register is irrelevant when I2C is in Master mode.
+ * |        |          |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
+ * |        |          |The I2C hardware will react if either of the address is matched.
+ * @var I2C_T::ADDRMSK0
+ * Offset: 0x24  I2C Slave Address Mask Register0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:1]   |ADDRMSK   |I2C Address Mask
+ * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * |        |          |I2C bus controllers support multiple address recognition with four address mask register.
+ * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
+ * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * @var I2C_T::ADDRMSK1
+ * Offset: 0x28  I2C Slave Address Mask Register1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:1]   |ADDRMSK   |I2C Address Mask
+ * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * |        |          |I2C bus controllers support multiple address recognition with four address mask register.
+ * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
+ * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * @var I2C_T::ADDRMSK2
+ * Offset: 0x2C  I2C Slave Address Mask Register2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:1]   |ADDRMSK   |I2C Address Mask
+ * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * |        |          |I2C bus controllers support multiple address recognition with four address mask register.
+ * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
+ * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * @var I2C_T::ADDRMSK3
+ * Offset: 0x30  I2C Slave Address Mask Register3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:1]   |ADDRMSK   |I2C Address Mask
+ * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * |        |          |I2C bus controllers support multiple address recognition with four address mask register.
+ * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
+ * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * @var I2C_T::WKCTL
+ * Offset: 0x3C  I2C Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |WKEN      |I2C Wake-Up Enable Bit
+ * |        |          |0 = I2C wake-up function Disabled.
+ * |        |          |1= I2C wake-up function Enabled.
+ * @var I2C_T::WKSTS
+ * Offset: 0x40  I2C Wake-up Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |WKIF      |I2C Wake-Up Flag
+ * |        |          |When chip is woken up from Power-down mode by I2C, this bit is set to 1.
+ * |        |          |Software can write 1 to clear this bit.
+ * @var I2C_T::BUSCTL
+ * Offset: 0x44  I2C Bus Management Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ACKMEN    |Acknowledge Control By Manual
+ * |        |          |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
+ * |        |          |0 = Slave byte control Disabled.
+ * |        |          |1 = Slave byte control Enabled.
+ * |        |          |The 9th bit can response the ACK or NACK according the received data by user.
+ * |        |          |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
+ * |        |          |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
+ * |[1]     |PECEN     |Packet Error Checking Calculation Enable Bit
+ * |        |          |0 = Packet Error Checking Calculation Disabled.
+ * |        |          |1 = Packet Error Checking Calculation Enabled.
+ * |[2]     |BMDEN     |Bus Management Device Default Address Enable Bit
+ * |        |          |0 = Device default address Disable.
+ * |        |          |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed.
+ * |        |          |1 = Device default address Enabled.
+ * |        |          |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
+ * |[3]     |BMHEN     |Bus Management Host Enable Bit
+ * |        |          |0 = Host function Disabled.
+ * |        |          |1 = Host function Enabled and the SUSCON will be used as CONTROL function.
+ * |[4]     |ALERTEN   |Bus Management Alert Enable Bit
+ * |        |          |Device Mode (BMHEN =0).
+ * |        |          |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
+ * |        |          |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
+ * |        |          |Host Mode (BMHEN =1).
+ * |        |          |0 = BM_ALERT pin not supported.
+ * |        |          |1 = BM_ALERT pin supported.
+ * |[5]     |SCTLOSTS  |Suspend/Control Data Output Status
+ * |        |          |0 = The output of SUSCON pin is low.
+ * |        |          |1 = The output of SUSCON pin is high.
+ * |[6]     |SCTLOEN   |Suspend Or Control Pin Output Enable Bit
+ * |        |          |0 = The SUSCON pin in input.
+ * |        |          |1 = The output enable is active on the SUSCON pin.
+ * |[7]     |BUSEN     |BUS Enable Bit
+ * |        |          |0 = The system management function is Disabled.
+ * |        |          |1 = The system management function is Enable.
+ * |        |          |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
+ * |[8]     |PECTXEN   |Packet Error Checking Byte Transmission/Reception
+ * |        |          |This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address Matched is received
+ * |        |          |0 = No PEC transfer.
+ * |        |          |1 = PEC transmission/reception is requested.
+ * |        |          |Note: 1.This bit has no effect in slave mode when ACKMEN =0.
+ * |[9]     |TIDLE     |Timer Check In Idle State
+ * |        |          |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle.
+ * |        |          |This bit is used to define which condition is enabled.
+ * |        |          |0 = The BUSTOUT is used to calculate the clock low period in bus active.
+ * |        |          |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
+ * |        |          |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
+ * |[10]    |PECCLR    |PEC Clear At Repeat Start
+ * |        |          |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected.
+ * |        |          |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
+ * |        |          |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled.
+ * |        |          |1 = The PEC calculation is cleared by "Repeat Start" function is Enabled.
+ * |[11]    |ACKM9SI   |Acknowledge Manual Enable Extra SI Interrupt
+ * |        |          |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
+ * |        |          |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
+ * @var I2C_T::BUSTCTL
+ * Offset: 0x48  I2C Bus Management Timer Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |BUSTOEN   |Bus Time Out Enable Bit
+ * |        |          |0 = Indicates the bus clock low time-out detection is Disabled.
+ * |        |          |1 = Indicates the bus clock low time-out detection is Enabled 
+ * |        |          |bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1),
+ * |[1]     |CLKTOEN   |Cumulative Clock Low Time Out Enable Bit
+ * |        |          |0 = Indicates the cumulative clock low time-out detection is Disabled.
+ * |        |          |1 = Indicates the cumulative clock low time-out detection is Enabled.
+ * |        |          |For Master, it calculates the period from START to ACK
+ * |        |          |For Slave, it calculates the period from START to STOP
+ * |[2]     |BUSTOIEN  |Time-Out Interrupt Enable Bit
+ * |        |          |BUSY =1.
+ * |        |          |0 = Indicates the SCLK low time-out interrupt is Disabled.
+ * |        |          |1 = Indicates the SCLK low time-out interrupt is Enabled.
+ * |        |          |BUSY =0.
+ * |        |          |0 = Indicates the bus IDLE time-out interrupt is Disabled.
+ * |        |          |1 = Indicates the bus IDLE time-out interrupt is Enabled.
+ * |[3]     |CLKTOIEN  |Extended Clock Time Out Interrupt Enable Bit
+ * |        |          |0 = Indicates the time extended interrupt is Disabled.
+ * |        |          |1 = Indicates the time extended interrupt is Enabled.
+ * |[4]     |TORSTEN   |Time Out Reset Enable Bit
+ * |        |          |0 = Indicates the I2C state machine reset is Disable.
+ * |        |          |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
+ * |[5]     |PECIEN    |Packet Error Checking Byte Count Done Interrupt Enable Bit
+ * |        |          |0 = Indicates the byte count done interrupt is Disabled.
+ * |        |          |1 = Indicates the byte count done interrupt is Enabled.
+ * |        |          |Note: This bit is used in PECEN =1.
+ * @var I2C_T::BUSSTS
+ * Offset: 0x4C  I2C Bus Management Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |BUSY      |Bus Busy
+ * |        |          |Indicates that a communication is in progress on the bus.
+ * |        |          |It is set by hardware when a START condition is detected.
+ * |        |          |It is cleared by hardware when a STOP condition is detected.
+ * |        |          |0 = The bus is IDLE (both SCLK and SDA High).
+ * |        |          |1 = The bus is busy.
+ * |[1]     |BCDONE    |Byte Count Transmission/Receive Done
+ * |        |          |0 = Indicates the transmission/ receive is not finished when the PECEN is set.
+ * |        |          |1 = Indicates the transmission/ receive is finished when the PECEN is set.
+ * |        |          |Note: Software can write 1 to clear this bit.
+ * |[2]     |PECERR    |PEC Error In Reception
+ * |        |          |0 = Indicates the PEC value equal the received PEC data packet.
+ * |        |          |1 = Indicates the PEC value doesn't match the receive PEC data packet.
+ * |        |          |Note: Software can write 1 to clear this bit.
+ * |[3]     |ALERT     |SMBus Alert Status
+ * |        |          |Device Mode (BMHEN =0).
+ * |        |          |0 = Indicates SMALERT pin state is low.
+ * |        |          |1 = Indicates SMALERT pin state is high
+ * |        |          |Host Mode (BMHEN =1).
+ * |        |          |0 = No SMBALERT event.
+ * |        |          |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
+ * |        |          |Note: 1.
+ * |        |          |The SMALERT pin is an open-drain pin, the pull-high resistor is must in the system.
+ * |        |          |2.
+ * |        |          |Software can write 1 to clear this bit.
+ * |[4]     |SCTLDIN   |Bus Suspend Or Control Signal Input Status
+ * |        |          |0 = The input status of SUSCON pin is 0.
+ * |        |          |1 = The input status of SUSCON pin is 1.
+ * |[5]     |BUSTO     |Bus Time-out Status
+ * |        |          |0 = Indicates that there is no any time-out or external clock time-out.
+ * |        |          |1 = Indicates that a time-out or external clock time-out occurred.
+ * |        |          |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
+ * |        |          |Note: Software can write 1 to clear this bit.
+ * |[6]     |CLKTO     |Clock Low Cumulate Time-out Status
+ * |        |          |0 = Indicates that the cumulative clock low is no any time-out.
+ * |        |          |1 = Indicates that the cumulative clock low time-out occurred.
+ * |        |          |Note: Software can write 1 to clear this bit.
+ * @var I2C_T::PKTSIZE
+ * Offset: 0x50  I2C Packet Error Checking Byte Number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |PLDSIZE   |Transfer Byte Number
+ * |        |          |The transmission or receive byte number in one transaction when the PECEN is set.
+ * |        |          |The maximum transaction or receive byte is 255 Bytes.
+ * @var I2C_T::PKTCRC
+ * Offset: 0x54  I2C Packet Error Checking Byte Value Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |PECCRC    |Packet Error Checking Byte Value
+ * |        |          |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1.
+ * |        |          |I t is read only.
+ * @var I2C_T::BUSTOUT
+ * Offset: 0x58  I2C Bus Management Timer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |BUSTO     |Bus Management Time-out Value
+ * |        |          |Indicate the bus time-out value in bus is IDLE or SCLK low.
+ * |        |          |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
+ * @var I2C_T::CLKTOUT
+ * Offset: 0x5C  I2C Bus Management Clock Low Timer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |CLKTO     |Bus Clock Low Timer
+ * |        |          |The field is used to configure the cumulative clock extension time-out.
+ * |        |          |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and d clear to 0 first in the BUSEN is set.
+    */
+
+    __IO uint32_t CTL;           /* Offset: 0x00  I2C Control Register                                               */
+    __IO uint32_t ADDR0;         /* Offset: 0x04  I2C Slave Address Register0                                        */
+    __IO uint32_t DAT;           /* Offset: 0x08  I2C Data Register                                                  */
+    __I  uint32_t STATUS;        /* Offset: 0x0C  I2C Status Register                                                */
+    __IO uint32_t CLKDIV;        /* Offset: 0x10  I2C Clock Divided Register                                         */
+    __IO uint32_t TOCTL;         /* Offset: 0x14  I2C Time-out Control Register                                      */
+    __IO uint32_t ADDR1;         /* Offset: 0x18  I2C Slave Address Register1                                        */
+    __IO uint32_t ADDR2;         /* Offset: 0x1C  I2C Slave Address Register2                                        */
+    __IO uint32_t ADDR3;         /* Offset: 0x20  I2C Slave Address Register3                                        */
+    __IO uint32_t ADDRMSK0;      /* Offset: 0x24  I2C Slave Address Mask Register0                                   */
+    __IO uint32_t ADDRMSK1;      /* Offset: 0x28  I2C Slave Address Mask Register1                                   */
+    __IO uint32_t ADDRMSK2;      /* Offset: 0x2C  I2C Slave Address Mask Register2                                   */
+    __IO uint32_t ADDRMSK3;      /* Offset: 0x30  I2C Slave Address Mask Register3                                   */
+    __I  uint32_t RESERVE0[2];  
+    __IO uint32_t WKCTL;         /* Offset: 0x3C  I2C Wake-up Control Register                                       */
+    __IO uint32_t WKSTS;         /* Offset: 0x40  I2C Wake-up Status Register                                        */
+    __IO uint32_t BUSCTL;        /* Offset: 0x44  I2C Bus Management Control Register                                */
+    __IO uint32_t BUSTCTL;       /* Offset: 0x48  I2C Bus Management Timer Control Register                          */
+    __IO uint32_t BUSSTS;        /* Offset: 0x4C  I2C Bus Management Status Register                                 */
+    __IO uint32_t PKTSIZE;       /* Offset: 0x50  I2C Packet Error Checking Byte Number Register                     */
+    __I  uint32_t PKTCRC;        /* Offset: 0x54  I2C Packet Error Checking Byte Value Register                      */
+    __IO uint32_t BUSTOUT;       /* Offset: 0x58  I2C Bus Management Timer Register                                  */
+    __IO uint32_t CLKTOUT;       /* Offset: 0x5C  I2C Bus Management Clock Low Timer Register                        */
+
+} I2C_T;
+
+
+
+/**
+    @addtogroup I2C_CONST I2C Bit Field Definition
+    Constant Definitions for I2C Controller
+@{ */
+
+#define I2C_CTL_AA_Pos                   (2)                                               /*!< I2C_T::CTL: AA Position                   */
+#define I2C_CTL_AA_Msk                   (0x1ul << I2C_CTL_AA_Pos)                         /*!< I2C_T::CTL: AA Mask                       */
+
+#define I2C_CTL_SI_Pos                   (3)                                               /*!< I2C_T::CTL: SI Position                   */
+#define I2C_CTL_SI_Msk                   (0x1ul << I2C_CTL_SI_Pos)                         /*!< I2C_T::CTL: SI Mask                       */
+
+#define I2C_CTL_STO_Pos                  (4)                                               /*!< I2C_T::CTL: STO Position                  */
+#define I2C_CTL_STO_Msk                  (0x1ul << I2C_CTL_STO_Pos)                        /*!< I2C_T::CTL: STO Mask                      */
+
+#define I2C_CTL_STA_Pos                  (5)                                               /*!< I2C_T::CTL: STA Position                  */
+#define I2C_CTL_STA_Msk                  (0x1ul << I2C_CTL_STA_Pos)                        /*!< I2C_T::CTL: STA Mask                      */
+
+#define I2C_CTL_I2CEN_Pos                (6)                                               /*!< I2C_T::CTL: I2CEN Position                */
+#define I2C_CTL_I2CEN_Msk                (0x1ul << I2C_CTL_I2CEN_Pos)                      /*!< I2C_T::CTL: I2CEN Mask                    */
+
+#define I2C_CTL_INTEN_Pos                (7)                                               /*!< I2C_T::CTL: INTEN Position                */
+#define I2C_CTL_INTEN_Msk                (0x1ul << I2C_CTL_INTEN_Pos)                      /*!< I2C_T::CTL: INTEN Mask                    */
+
+#define I2C_ADDR0_GC_Pos                 (0)                                               /*!< I2C_T::ADDR0: GC Position                 */
+#define I2C_ADDR0_GC_Msk                 (0x1ul << I2C_ADDR0_GC_Pos)                       /*!< I2C_T::ADDR0: GC Mask                     */
+
+#define I2C_ADDR0_ADDR_Pos               (1)                                               /*!< I2C_T::ADDR0: ADDR Position               */
+#define I2C_ADDR0_ADDR_Msk               (0x7ful << I2C_ADDR0_ADDR_Pos)                    /*!< I2C_T::ADDR0: ADDR Mask                   */
+
+#define I2C_DAT_DAT_Pos                  (0)                                               /*!< I2C_T::DAT: DAT Position                  */
+#define I2C_DAT_DAT_Msk                  (0xfful << I2C_DAT_DAT_Pos)                       /*!< I2C_T::DAT: DAT Mask                      */
+
+#define I2C_STATUS_STATUS_Pos            (0)                                               /*!< I2C_T::STATUS: STATUS Position            */
+#define I2C_STATUS_STATUS_Msk            (0xfful << I2C_STATUS_STATUS_Pos)                 /*!< I2C_T::STATUS: STATUS Mask                */
+
+#define I2C_CLKDIV_DIVIDER_Pos           (0)                                               /*!< I2C_T::CLKDIV: DIVIDER Position           */
+#define I2C_CLKDIV_DIVIDER_Msk           (0xfful << I2C_CLKDIV_DIVIDER_Pos)                /*!< I2C_T::CLKDIV: DIVIDER Mask               */
+
+#define I2C_TOCTL_TOIF_Pos               (0)                                               /*!< I2C_T::TOCTL: TOIF Position               */
+#define I2C_TOCTL_TOIF_Msk               (0x1ul << I2C_TOCTL_TOIF_Pos)                     /*!< I2C_T::TOCTL: TOIF Mask                   */
+
+#define I2C_TOCTL_TOCDIV4_Pos            (1)                                               /*!< I2C_T::TOCTL: TOCDIV4 Position            */
+#define I2C_TOCTL_TOCDIV4_Msk            (0x1ul << I2C_TOCTL_TOCDIV4_Pos)                  /*!< I2C_T::TOCTL: TOCDIV4 Mask                */
+
+#define I2C_TOCTL_TOCEN_Pos              (2)                                               /*!< I2C_T::TOCTL: TOCEN Position              */
+#define I2C_TOCTL_TOCEN_Msk              (0x1ul << I2C_TOCTL_TOCEN_Pos)                    /*!< I2C_T::TOCTL: TOCEN Mask                  */
+
+#define I2C_ADDR1_GC_Pos                 (0)                                               /*!< I2C_T::ADDR1: GC Position                 */
+#define I2C_ADDR1_GC_Msk                 (0x1ul << I2C_ADDR1_GC_Pos)                       /*!< I2C_T::ADDR1: GC Mask                     */
+
+#define I2C_ADDR1_ADDR_Pos               (1)                                               /*!< I2C_T::ADDR1: ADDR Position               */
+#define I2C_ADDR1_ADDR_Msk               (0x7ful << I2C_ADDR1_ADDR_Pos)                    /*!< I2C_T::ADDR1: ADDR Mask                   */
+
+#define I2C_ADDR2_GC_Pos                 (0)                                               /*!< I2C_T::ADDR2: GC Position                 */
+#define I2C_ADDR2_GC_Msk                 (0x1ul << I2C_ADDR2_GC_Pos)                       /*!< I2C_T::ADDR2: GC Mask                     */
+
+#define I2C_ADDR2_ADDR_Pos               (1)                                               /*!< I2C_T::ADDR2: ADDR Position               */
+#define I2C_ADDR2_ADDR_Msk               (0x7ful << I2C_ADDR2_ADDR_Pos)                    /*!< I2C_T::ADDR2: ADDR Mask                   */
+
+#define I2C_ADDR3_GC_Pos                 (0)                                               /*!< I2C_T::ADDR3: GC Position                 */
+#define I2C_ADDR3_GC_Msk                 (0x1ul << I2C_ADDR3_GC_Pos)                       /*!< I2C_T::ADDR3: GC Mask                     */
+
+#define I2C_ADDR3_ADDR_Pos               (1)                                               /*!< I2C_T::ADDR3: ADDR Position               */
+#define I2C_ADDR3_ADDR_Msk               (0x7ful << I2C_ADDR3_ADDR_Pos)                    /*!< I2C_T::ADDR3: ADDR Mask                   */
+
+#define I2C_ADDRMSK0_ADDRMSK_Pos         (1)                                               /*!< I2C_T::ADDRMSK0: ADDRMSK Position         */
+#define I2C_ADDRMSK0_ADDRMSK_Msk         (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos)              /*!< I2C_T::ADDRMSK0: ADDRMSK Mask             */
+
+#define I2C_ADDRMSK1_ADDRMSK_Pos         (1)                                               /*!< I2C_T::ADDRMSK1: ADDRMSK Position         */
+#define I2C_ADDRMSK1_ADDRMSK_Msk         (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos)              /*!< I2C_T::ADDRMSK1: ADDRMSK Mask             */
+
+#define I2C_ADDRMSK2_ADDRMSK_Pos         (1)                                               /*!< I2C_T::ADDRMSK2: ADDRMSK Position         */
+#define I2C_ADDRMSK2_ADDRMSK_Msk         (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos)              /*!< I2C_T::ADDRMSK2: ADDRMSK Mask             */
+
+#define I2C_ADDRMSK3_ADDRMSK_Pos         (1)                                               /*!< I2C_T::ADDRMSK3: ADDRMSK Position         */
+#define I2C_ADDRMSK3_ADDRMSK_Msk         (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos)              /*!< I2C_T::ADDRMSK3: ADDRMSK Mask             */
+
+#define I2C_WKCTL_WKEN_Pos               (0)                                               /*!< I2C_T::WKCTL: WKEN Position               */
+#define I2C_WKCTL_WKEN_Msk               (0x1ul << I2C_WKCTL_WKEN_Pos)                     /*!< I2C_T::WKCTL: WKEN Mask                   */
+
+#define I2C_WKSTS_WKIF_Pos               (0)                                               /*!< I2C_T::WKSTS: WKIF Position               */
+#define I2C_WKSTS_WKIF_Msk               (0x1ul << I2C_WKSTS_WKIF_Pos)                     /*!< I2C_T::WKSTS: WKIF Mask                   */
+
+#define I2C_BUSCTL_ACKMEN_Pos            (0)                                               /*!< I2C_T::BUSCTL: ACKMEN Position            */
+#define I2C_BUSCTL_ACKMEN_Msk            (0x1ul << I2C_BUSCTL_ACKMEN_Pos)                  /*!< I2C_T::BUSCTL: ACKMEN Mask                */
+
+#define I2C_BUSCTL_PECEN_Pos             (1)                                               /*!< I2C_T::BUSCTL: PECEN Position             */
+#define I2C_BUSCTL_PECEN_Msk             (0x1ul << I2C_BUSCTL_PECEN_Pos)                   /*!< I2C_T::BUSCTL: PECEN Mask                 */
+
+#define I2C_BUSCTL_BMDEN_Pos             (2)                                               /*!< I2C_T::BUSCTL: BMDEN Position             */
+#define I2C_BUSCTL_BMDEN_Msk             (0x1ul << I2C_BUSCTL_BMDEN_Pos)                   /*!< I2C_T::BUSCTL: BMDEN Mask                 */
+
+#define I2C_BUSCTL_BMHEN_Pos             (3)                                               /*!< I2C_T::BUSCTL: BMHEN Position             */
+#define I2C_BUSCTL_BMHEN_Msk             (0x1ul << I2C_BUSCTL_BMHEN_Pos)                   /*!< I2C_T::BUSCTL: BMHEN Mask                 */
+
+#define I2C_BUSCTL_ALERTEN_Pos           (4)                                               /*!< I2C_T::BUSCTL: ALERTEN Position           */
+#define I2C_BUSCTL_ALERTEN_Msk           (0x1ul << I2C_BUSCTL_ALERTEN_Pos)                 /*!< I2C_T::BUSCTL: ALERTEN Mask               */
+
+#define I2C_BUSCTL_SCTLOSTS_Pos          (5)                                               /*!< I2C_T::BUSCTL: SCTLOSTS Position          */
+#define I2C_BUSCTL_SCTLOSTS_Msk          (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos)                /*!< I2C_T::BUSCTL: SCTLOSTS Mask              */
+
+#define I2C_BUSCTL_SCTLOEN_Pos           (6)                                               /*!< I2C_T::BUSCTL: SCTLOEN Position           */
+#define I2C_BUSCTL_SCTLOEN_Msk           (0x1ul << I2C_BUSCTL_SCTLOEN_Pos)                 /*!< I2C_T::BUSCTL: SCTLOEN Mask               */
+
+#define I2C_BUSCTL_BUSEN_Pos             (7)                                               /*!< I2C_T::BUSCTL: BUSEN Position             */
+#define I2C_BUSCTL_BUSEN_Msk             (0x1ul << I2C_BUSCTL_BUSEN_Pos)                   /*!< I2C_T::BUSCTL: BUSEN Mask                 */
+
+#define I2C_BUSCTL_PECTXEN_Pos           (8)                                               /*!< I2C_T::BUSCTL: PECTXEN Position           */
+#define I2C_BUSCTL_PECTXEN_Msk           (0x1ul << I2C_BUSCTL_PECTXEN_Pos)                 /*!< I2C_T::BUSCTL: PECTXEN Mask               */
+
+#define I2C_BUSCTL_TIDLE_Pos             (9)                                               /*!< I2C_T::BUSCTL: TIDLE Position             */
+#define I2C_BUSCTL_TIDLE_Msk             (0x1ul << I2C_BUSCTL_TIDLE_Pos)                   /*!< I2C_T::BUSCTL: TIDLE Mask                 */
+
+#define I2C_BUSCTL_PECCLR_Pos            (10)                                              /*!< I2C_T::BUSCTL: PECCLR Position            */
+#define I2C_BUSCTL_PECCLR_Msk            (0x1ul << I2C_BUSCTL_PECCLR_Pos)                  /*!< I2C_T::BUSCTL: PECCLR Mask                */
+
+#define I2C_BUSCTL_ACKM9SI_Pos           (11)                                              /*!< I2C_T::BUSCTL: ACKM9SI Position           */
+#define I2C_BUSCTL_ACKM9SI_Msk           (0x1ul << I2C_BUSCTL_ACKM9SI_Pos)                 /*!< I2C_T::BUSCTL: ACKM9SI Mask               */
+
+#define I2C_BUSTCTL_BUSTOEN_Pos          (0)                                               /*!< I2C_T::BUSTCTL: BUSTOEN Position          */
+#define I2C_BUSTCTL_BUSTOEN_Msk          (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos)                /*!< I2C_T::BUSTCTL: BUSTOEN Mask              */
+
+#define I2C_BUSTCTL_CLKTOEN_Pos          (1)                                               /*!< I2C_T::BUSTCTL: CLKTOEN Position          */
+#define I2C_BUSTCTL_CLKTOEN_Msk          (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos)                /*!< I2C_T::BUSTCTL: CLKTOEN Mask              */
+
+#define I2C_BUSTCTL_BUSTOIEN_Pos         (2)                                               /*!< I2C_T::BUSTCTL: BUSTOIEN Position         */
+#define I2C_BUSTCTL_BUSTOIEN_Msk         (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos)               /*!< I2C_T::BUSTCTL: BUSTOIEN Mask             */
+
+#define I2C_BUSTCTL_CLKTOIEN_Pos         (3)                                               /*!< I2C_T::BUSTCTL: CLKTOIEN Position         */
+#define I2C_BUSTCTL_CLKTOIEN_Msk         (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos)               /*!< I2C_T::BUSTCTL: CLKTOIEN Mask             */
+
+#define I2C_BUSTCTL_TORSTEN_Pos          (4)                                               /*!< I2C_T::BUSTCTL: TORSTEN Position          */
+#define I2C_BUSTCTL_TORSTEN_Msk          (0x1ul << I2C_BUSTCTL_TORSTEN_Pos)                /*!< I2C_T::BUSTCTL: TORSTEN Mask              */
+
+#define I2C_BUSTCTL_PECIEN_Pos           (5)                                               /*!< I2C_T::BUSTCTL: PECIEN Position           */
+#define I2C_BUSTCTL_PECIEN_Msk           (0x1ul << I2C_BUSTCTL_PECIEN_Pos)                 /*!< I2C_T::BUSTCTL: PECIEN Mask               */
+
+#define I2C_BUSSTS_BUSY_Pos              (0)                                               /*!< I2C_T::BUSSTS: BUSY Position              */
+#define I2C_BUSSTS_BUSY_Msk              (0x1ul << I2C_BUSSTS_BUSY_Pos)                    /*!< I2C_T::BUSSTS: BUSY Mask                  */
+
+#define I2C_BUSSTS_BCDONE_Pos            (1)                                               /*!< I2C_T::BUSSTS: BCDONE Position            */
+#define I2C_BUSSTS_BCDONE_Msk            (0x1ul << I2C_BUSSTS_BCDONE_Pos)                  /*!< I2C_T::BUSSTS: BCDONE Mask                */
+
+#define I2C_BUSSTS_PECERR_Pos            (2)                                               /*!< I2C_T::BUSSTS: PECERR Position            */
+#define I2C_BUSSTS_PECERR_Msk            (0x1ul << I2C_BUSSTS_PECERR_Pos)                  /*!< I2C_T::BUSSTS: PECERR Mask                */
+
+#define I2C_BUSSTS_ALERT_Pos             (3)                                               /*!< I2C_T::BUSSTS: ALERT Position             */
+#define I2C_BUSSTS_ALERT_Msk             (0x1ul << I2C_BUSSTS_ALERT_Pos)                   /*!< I2C_T::BUSSTS: ALERT Mask                 */
+
+#define I2C_BUSSTS_SCTLDIN_Pos           (4)                                               /*!< I2C_T::BUSSTS: SCTLDIN Position           */
+#define I2C_BUSSTS_SCTLDIN_Msk           (0x1ul << I2C_BUSSTS_SCTLDIN_Pos)                 /*!< I2C_T::BUSSTS: SCTLDIN Mask               */
+
+#define I2C_BUSSTS_BUSTO_Pos             (5)                                               /*!< I2C_T::BUSSTS: BUSTO Position             */
+#define I2C_BUSSTS_BUSTO_Msk             (0x1ul << I2C_BUSSTS_BUSTO_Pos)                   /*!< I2C_T::BUSSTS: BUSTO Mask                 */
+
+#define I2C_BUSSTS_CLKTO_Pos             (6)                                               /*!< I2C_T::BUSSTS: CLKTO Position             */
+#define I2C_BUSSTS_CLKTO_Msk             (0x1ul << I2C_BUSSTS_CLKTO_Pos)                   /*!< I2C_T::BUSSTS: CLKTO Mask                 */
+
+#define I2C_PKTSIZE_PLDSIZE_Pos          (0)                                               /*!< I2C_T::PKTSIZE: PLDSIZE Position          */
+#define I2C_PKTSIZE_PLDSIZE_Msk          (0xfful << I2C_PKTSIZE_PLDSIZE_Pos)               /*!< I2C_T::PKTSIZE: PLDSIZE Mask              */
+
+#define I2C_PKTCRC_PECCRC_Pos            (0)                                               /*!< I2C_T::PKTCRC: PECCRC Position            */
+#define I2C_PKTCRC_PECCRC_Msk            (0xfful << I2C_PKTCRC_PECCRC_Pos)                 /*!< I2C_T::PKTCRC: PECCRC Mask                */
+
+#define I2C_BUSTOUT_BUSTO_Pos            (0)                                               /*!< I2C_T::BUSTOUT: BUSTO Position            */
+#define I2C_BUSTOUT_BUSTO_Msk            (0xfful << I2C_BUSTOUT_BUSTO_Pos)                 /*!< I2C_T::BUSTOUT: BUSTO Mask                */
+
+#define I2C_CLKTOUT_CLKTO_Pos            (0)                                               /*!< I2C_T::CLKTOUT: CLKTO Position            */
+#define I2C_CLKTOUT_CLKTO_Msk            (0xfful << I2C_CLKTOUT_CLKTO_Pos)                 /*!< I2C_T::CLKTOUT: CLKTO Mask                */
+
+
+/**@}*/ /* I2C_CONST */
+/**@}*/ /* end of I2C register group */
+
+/*---------------------- USB On-The-Go Controller -------------------------*/
+/**
+    @addtogroup OTG USB On-The-Go Controller(OTG)
+    Memory Mapped Structure for OTG Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var OTG_T::CTL
+ * Offset: 0x00  OTG Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |VBUSDROP  |Drop VBUS Control
+ * |        |          |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS.
+ * |        |          |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
+ * |        |          |0 = Not drop the VBUS.
+ * |        |          |1 = Drop the VBUS.
+ * |[1]     |BUSREQ    |OTG Bus Request
+ * |        |          |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection.
+ * |        |          |If user won't use the bus any more, clearing this bit will drop VBUS to save power.
+ * |        |          |This bit will be cleared when A-device goes to A_wait_vfall state. A_wait_vfall state is defined in OTG specification.
+ * |        |          |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
+ * |        |          |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol.
+ * |        |          |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification).
+ * |        |          |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
+ * |        |          |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
+ * |        |          |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
+ * |[2]     |HNPREQEN  |OTG HNP Request Enable Bit
+ * |        |          |When USB frame as A-device, set this bit when A-device allows to process Host Negotiation Protocol.
+ * |        |          |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state.
+ * |        |          |When USB frame is as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change.
+ * |        |          |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
+ * |        |          |0 = HNP request Disabled.
+ * |        |          |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
+ * |        |          |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
+ * |[4]     |OTGEN     |OTG Function Enable Bit
+ * |        |          |User needs to set this bit to enable OTG function while USB frame configured as OTG device.
+ * |        |          |When USB frame not configured as OTG device, this bit is must be low.
+ * |        |          |0 = OTG function Disabled.
+ * |        |          |1 = OTG function Enabled.
+ * |[5]     |WKEN      |OTG ID Pin Wake-Up Enable Bit
+ * |        |          |0 = OTG ID pin status change wake-up function Disabled.
+ * |        |          |1 = OTG ID pin status change wake-up function Enabled.
+ * @var OTG_T::PHYCTL
+ * Offset: 0x04  OTG PHY Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |OTGPHYEN  |OTG PHY Enable
+ * |        |          |When USB frame is configured as OTG-device, user needs to set this bit before using OTG function.
+ * |        |          |If device is not configured as OTG-device, this bit is "don't care".
+ * |        |          |0 = OTG PHY Disabled.
+ * |        |          |1 = OTG PHY Enabled.
+ * |[1]     |IDDETEN   |ID Detection Enable Bit
+ * |        |          |0 = Detect ID pin status Disabled.
+ * |        |          |1 = Detect ID pin status Enabled.
+ * |[4]     |VBENPOL   |Off-Chip USB VBUS Power Switch Enable Polarity
+ * |        |          |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need.
+ * |        |          |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
+ * |        |          |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component.
+ * |        |          |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+ * |        |          |0 = The off-chip USB VBUS power switch enable is active high.
+ * |        |          |1 = The off-chip USB VBUS power switch enable is active low.
+ * |[5]     |VBSTSPOL  |Off-Chip USB VBUS Power Switch Status Polarity
+ * |        |          |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component.
+ * |        |          |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch.
+ * |        |          |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+ * |        |          |0 = The polarity of off-chip USB VBUS power switch valid status is high.
+ * |        |          |1 = The polarity of off-chip USB VBUS power switch valid status is low.
+ * @var OTG_T::INTEN
+ * Offset: 0x08  OTG Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ROLECHGIEN|Role (Host Or Peripheral) Changed Interrupt Enable Bit
+ * |        |          |0 = Interrupt Disabled.
+ * |        |          |1 = Interrupt Enabled.
+ * |[1]     |VBEIEN    |VBUS Error Interrupt Enable Bit
+ * |        |          |0 = Interrupt Disabled.
+ * |        |          |1 = Interrupt Enabled.
+ * |        |          |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
+ * |[2]     |SRPFIEN   |SRP Fail Interrupt Enable Bit
+ * |        |          |0 = Interrupt Disabled.
+ * |        |          |1 = Interrupt Enabled.
+ * |[3]     |HNPFIEN   |HNP Fail Interrupt Enable Bit
+ * |        |          |0 = Interrupt Disabled.
+ * |        |          |1 = Interrupt Enabled.
+ * |[4]     |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
+ * |        |          |0 = Interrupt Disabled.
+ * |        |          |1 = Interrupt Enabled.
+ * |        |          |Note: Going to idle state means going to a_idle or b_idle state.
+ * |        |          |Please refer to A-device state diagram and B-device state diagram in OTG spec.
+ * |[5]     |IDCHGIEN  |IDSTS Changed Interrupt Enable Bit
+ * |        |          |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * |        |          |0 = Interrupt Disabled.
+ * |        |          |1 = Interrupt Enabled.
+ * |[6]     |PDEVIEN   |Act As Peripheral Interrupt Enable Bit
+ * |        |          |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
+ * |        |          |0 = This device as a peripheral interrupt Disabled.
+ * |        |          |1 = This device as a peripheral interrupt Enabled.
+ * |[7]     |HOSTIEN   |Act As Host Interrupt Enable Bit
+ * |        |          |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
+ * |        |          |0 = This device as a host interrupt Disabled.
+ * |        |          |1 = This device as a host interrupt Enabled.
+ * |[8]     |BVLDCHGIEN|B-Device Session Valid Status Changed Interrupt Enable Bit
+ * |        |          |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * |        |          |0 = Interrupt Disabled.
+ * |        |          |1 = Interrupt Enabled.
+ * |[9]     |AVLDCHGIEN|A-Device Session Valid Status Changed Interrupt Enable Bit
+ * |        |          |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * |        |          |0 = Interrupt Disabled.
+ * |        |          |1 = Interrupt Enabled.
+ * |[10]    |VBCHGIEN  |VBUSVLD Status Changed
+ * |        |          |Interrupt Enable Bit
+ * |        |          |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * |        |          |0 = Interrupt Disabled.
+ * |        |          |1 = Interrupt Enabled.
+ * |[11]    |SECHGIEN  |SESSEND Status Changed Interrupt Enable Bit
+ * |        |          |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * |        |          |0 = Interrupt Disabled.
+ * |        |          |1 = Interrupt Enabled.
+ * |[13]    |SRPDETIEN |SRP Detected Interrupt Enable Bit
+ * |        |          |0 = Interrupt Disabled.
+ * |        |          |1 = Interrupt Enabled.
+ * @var OTG_T::INTSTS
+ * Offset: 0x0C  OTG Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ROLECHGIF |OTG Role Change Interrupt Status
+ * |        |          |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
+ * |        |          |0 = OTG device role not changed.
+ * |        |          |1 = OTG device role changed.
+ * |        |          |Note: Write 1 to clear this flag.
+ * |[1]     |VBEIF     |VBUS Error Interrupt Status
+ * |        |          |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
+ * |        |          |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
+ * |        |          |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
+ * |        |          |Note: Write 1 to clear this flag and recover from the VBUS error state.
+ * |[2]     |SRPFIF    |SRP Fail Interrupt Status
+ * |        |          |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification.
+ * |        |          |This flag is set when the OTG B-device does not get VBUS high after this interval.
+ * |        |          |0 = OTG B-device gets VBUS high before this interval.
+ * |        |          |1 = OTG B-device does not get VBUS high before this interval.
+ * |        |          |Note: Write 1 to clear this flag.
+ * |[3]     |HNPFIF    |HNP Fail Interrupt Status
+ * |        |          |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
+ * |        |          |0 = A-device connects to B-device before specified interval expires.
+ * |        |          |1 = A-device does not connect to B-device before specified interval expires.
+ * |        |          |Note: Write 1 to clear this flag.
+ * |[4]     |GOIDLEIF  |OTG Device Goes to IDLE Interrupt Status
+ * |        |          |Flag is set if the OTG device transfers from non-idle state to idle state.
+ * |        |          |The OTG device will be neither a host nor a peripheral.
+ * |        |          |0 = OTG device does not go back to idle state (a_idle or b_idle).
+ * |        |          |1 = OTG device goes back to idle state (a_idle or b_idle).
+ * |        |          |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification for the details of a_idle state and b_idle state.
+ * |        |          |Note 2: Write 1 to clear this flag.
+ * |[5]     |IDCHGIF   |ID State Change Interrupt Status
+ * |        |          |0 = IDSTS (OTG_STATUS[1]) not toggled.
+ * |        |          |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
+ * |        |          |Note: Write 1 to clear this flag.
+ * |[6]     |PDEVIF    |Act As Peripheral Interrupt Status
+ * |        |          |0 = This device does not act as a peripheral.
+ * |        |          |1 = This device acts as a peripheral.
+ * |        |          |Note: Write 1 to clear this flag.
+ * |[7]     |HOSTIF    |Act As Host Interrupt Status
+ * |        |          |0 = This device does not act as a host.
+ * |        |          |1 = This device acts as a host.
+ * |        |          |Note: Write 1 to clear this flag.
+ * |[8]     |BVLDCHGIF |B-Device Session Valid State Change Interrupt Status
+ * |        |          |0 = BVLD (OTG_STATUS[3]) is not toggled.
+ * |        |          |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
+ * |        |          |Note: Write 1 to clear this status.
+ * |[9]     |AVLDCHGIF |A-Device Session Valid State Change Interrupt Status
+ * |        |          |0 = AVLD (OTG_STATUS[4]) not toggled.
+ * |        |          |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
+ * |        |          |Note: Write 1 to clear this status.
+ * |[10]    |VBCHGIF   |VBUSVLD State Change Interrupt Status
+ * |        |          |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
+ * |        |          |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
+ * |        |          |Note: Write 1 to clear this status.
+ * |[11]    |SECHGIF   |SESSEND State Change Interrupt Status
+ * |        |          |0 = SESSEND (OTG_STATUS[2]) not toggled.
+ * |        |          |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
+ * |        |          |Note: Write 1 to clear this flag.
+ * |[13]    |SRPDETIF  |SRP Detected Interrupt Status
+ * |        |          |0 = SRP not detected.
+ * |        |          |1 = SRP detected.
+ * |        |          |Note: Write 1 to clear this status.
+ * @var OTG_T::STATUS
+ * Offset: 0x10  OTG Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |OVERCUR   |Over Current Condition
+ * |        |          |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
+ * |        |          |0 = OTG A-device drives VBUS successfully.
+ * |        |          |1 = OTG A-device cannot drives VBUS high in this interval.
+ * |[1]     |IDSTS     |USB_ID Pin State Of Mini-B/Micro-Plug
+ * |        |          |0 = Mini-A/Micro-A plug is attached.
+ * |        |          |1 = Mini-B/Micro-B plug is attached.
+ * |[2]     |SESSEND   |Session End Status
+ * |        |          |When VBUS voltage is lower than 0.4V, this bit will be set to 1.
+ * |        |          |Session end means no meaningful power on VBUS.
+ * |        |          |0 = Session is not end.
+ * |        |          |1 = Session is end.
+ * |[3]     |BVLD      |B-Device Session Valid Status
+ * |        |          |0 = B-device session is not valid.
+ * |        |          |1 = B-device session is valid.
+ * |[4]     |AVLD      |A-Device Session Valid Status
+ * |        |          |0 = A-device session is not valid.
+ * |        |          |1 = A-device session is valid.
+ * |[5]     |VBUSVLD   |VBUS Valid Status
+ * |        |          |When VBUS is larger than 4.7V, this bit will be set to 1.
+ * |        |          |0 = VBUS is not valid.
+ * |        |          |1 = VBUS is valid.
+ */
+
+    __IO uint32_t CTL;           /* Offset: 0x00  OTG Control Register                                               */
+    __IO uint32_t PHYCTL;        /* Offset: 0x04  OTG PHY Control Register                                           */
+    __IO uint32_t INTEN;         /* Offset: 0x08  OTG Interrupt Enable Register                                      */
+    __IO uint32_t INTSTS;        /* Offset: 0x0C  OTG Interrupt Status Register                                      */
+    __I  uint32_t STATUS;        /* Offset: 0x10  OTG Status Register                                                */
+
+} OTG_T;
+
+
+
+/**
+    @addtogroup OTG_CONST OTG Bit Field Definition
+    Constant Definitions for OTG Controller
+@{ */
+
+#define OTG_CTL_VBUSDROP_Pos             (0)                                               /*!< OTG_T::CTL: VBUSDROP Position             */
+#define OTG_CTL_VBUSDROP_Msk             (0x1ul << OTG_CTL_VBUSDROP_Pos)                   /*!< OTG_T::CTL: VBUSDROP Mask                 */
+
+#define OTG_CTL_BUSREQ_Pos               (1)                                               /*!< OTG_T::CTL: BUSREQ Position               */
+#define OTG_CTL_BUSREQ_Msk               (0x1ul << OTG_CTL_BUSREQ_Pos)                     /*!< OTG_T::CTL: BUSREQ Mask                   */
+
+#define OTG_CTL_HNPREQEN_Pos             (2)                                               /*!< OTG_T::CTL: HNPREQEN Position             */
+#define OTG_CTL_HNPREQEN_Msk             (0x1ul << OTG_CTL_HNPREQEN_Pos)                   /*!< OTG_T::CTL: HNPREQEN Mask                 */
+
+#define OTG_CTL_OTGEN_Pos                (4)                                               /*!< OTG_T::CTL: OTGEN Position                */
+#define OTG_CTL_OTGEN_Msk                (0x1ul << OTG_CTL_OTGEN_Pos)                      /*!< OTG_T::CTL: OTGEN Mask                    */
+
+#define OTG_CTL_WKEN_Pos                 (5)                                               /*!< OTG_T::CTL: WKEN Position                 */
+#define OTG_CTL_WKEN_Msk                 (0x1ul << OTG_CTL_WKEN_Pos)                       /*!< OTG_T::CTL: WKEN Mask                     */
+
+#define OTG_PHYCTL_OTGPHYEN_Pos          (0)                                               /*!< OTG_T::PHYCTL: OTGPHYEN Position          */
+#define OTG_PHYCTL_OTGPHYEN_Msk          (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos)                /*!< OTG_T::PHYCTL: OTGPHYEN Mask              */
+
+#define OTG_PHYCTL_IDDETEN_Pos           (1)                                               /*!< OTG_T::PHYCTL: IDDETEN Position           */
+#define OTG_PHYCTL_IDDETEN_Msk           (0x1ul << OTG_PHYCTL_IDDETEN_Pos)                 /*!< OTG_T::PHYCTL: IDDETEN Mask               */
+
+#define OTG_PHYCTL_VBENPOL_Pos           (4)                                               /*!< OTG_T::PHYCTL: VBENPOL Position           */
+#define OTG_PHYCTL_VBENPOL_Msk           (0x1ul << OTG_PHYCTL_VBENPOL_Pos)                 /*!< OTG_T::PHYCTL: VBENPOL Mask               */
+
+#define OTG_PHYCTL_VBSTSPOL_Pos          (5)                                               /*!< OTG_T::PHYCTL: VBSTSPOL Position          */
+#define OTG_PHYCTL_VBSTSPOL_Msk          (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos)                /*!< OTG_T::PHYCTL: VBSTSPOL Mask              */
+
+#define OTG_INTEN_ROLECHGIEN_Pos         (0)                                               /*!< OTG_T::INTEN: ROLECHGIEN Position         */
+#define OTG_INTEN_ROLECHGIEN_Msk         (0x1ul << OTG_INTEN_ROLECHGIEN_Pos)               /*!< OTG_T::INTEN: ROLECHGIEN Mask             */
+
+#define OTG_INTEN_VBEIEN_Pos             (1)                                               /*!< OTG_T::INTEN: VBEIEN Position             */
+#define OTG_INTEN_VBEIEN_Msk             (0x1ul << OTG_INTEN_VBEIEN_Pos)                   /*!< OTG_T::INTEN: VBEIEN Mask                 */
+
+#define OTG_INTEN_SRPFIEN_Pos            (2)                                               /*!< OTG_T::INTEN: SRPFIEN Position            */
+#define OTG_INTEN_SRPFIEN_Msk            (0x1ul << OTG_INTEN_SRPFIEN_Pos)                  /*!< OTG_T::INTEN: SRPFIEN Mask                */
+
+#define OTG_INTEN_HNPFIEN_Pos            (3)                                               /*!< OTG_T::INTEN: HNPFIEN Position            */
+#define OTG_INTEN_HNPFIEN_Msk            (0x1ul << OTG_INTEN_HNPFIEN_Pos)                  /*!< OTG_T::INTEN: HNPFIEN Mask                */
+
+#define OTG_INTEN_GOIDLEIEN_Pos          (4)                                               /*!< OTG_T::INTEN: GOIDLEIEN Position          */
+#define OTG_INTEN_GOIDLEIEN_Msk          (0x1ul << OTG_INTEN_GOIDLEIEN_Pos)                /*!< OTG_T::INTEN: GOIDLEIEN Mask              */
+
+#define OTG_INTEN_IDCHGIEN_Pos           (5)                                               /*!< OTG_T::INTEN: IDCHGIEN Position           */
+#define OTG_INTEN_IDCHGIEN_Msk           (0x1ul << OTG_INTEN_IDCHGIEN_Pos)                 /*!< OTG_T::INTEN: IDCHGIEN Mask               */
+
+#define OTG_INTEN_PDEVIEN_Pos            (6)                                               /*!< OTG_T::INTEN: PDEVIEN Position            */
+#define OTG_INTEN_PDEVIEN_Msk            (0x1ul << OTG_INTEN_PDEVIEN_Pos)                  /*!< OTG_T::INTEN: PDEVIEN Mask                */
+
+#define OTG_INTEN_HOSTIEN_Pos            (7)                                               /*!< OTG_T::INTEN: HOSTIEN Position            */
+#define OTG_INTEN_HOSTIEN_Msk            (0x1ul << OTG_INTEN_HOSTIEN_Pos)                  /*!< OTG_T::INTEN: HOSTIEN Mask                */
+
+#define OTG_INTEN_BVLDCHGIEN_Pos         (8)                                               /*!< OTG_T::INTEN: BVLDCHGIEN Position         */
+#define OTG_INTEN_BVLDCHGIEN_Msk         (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos)               /*!< OTG_T::INTEN: BVLDCHGIEN Mask             */
+
+#define OTG_INTEN_AVLDCHGIEN_Pos         (9)                                               /*!< OTG_T::INTEN: AVLDCHGIEN Position         */
+#define OTG_INTEN_AVLDCHGIEN_Msk         (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos)               /*!< OTG_T::INTEN: AVLDCHGIEN Mask             */
+
+#define OTG_INTEN_VBCHGIEN_Pos           (10)                                              /*!< OTG_T::INTEN: VBCHGIEN Position           */
+#define OTG_INTEN_VBCHGIEN_Msk           (0x1ul << OTG_INTEN_VBCHGIEN_Pos)                 /*!< OTG_T::INTEN: VBCHGIEN Mask               */
+
+#define OTG_INTEN_SECHGIEN_Pos           (11)                                              /*!< OTG_T::INTEN: SECHGIEN Position           */
+#define OTG_INTEN_SECHGIEN_Msk           (0x1ul << OTG_INTEN_SECHGIEN_Pos)                 /*!< OTG_T::INTEN: SECHGIEN Mask               */
+
+#define OTG_INTEN_SRPDETIEN_Pos          (13)                                              /*!< OTG_T::INTEN: SRPDETIEN Position          */
+#define OTG_INTEN_SRPDETIEN_Msk          (0x1ul << OTG_INTEN_SRPDETIEN_Pos)                /*!< OTG_T::INTEN: SRPDETIEN Mask              */
+
+#define OTG_INTSTS_ROLECHGIF_Pos         (0)                                               /*!< OTG_T::INTSTS: ROLECHGIF Position         */
+#define OTG_INTSTS_ROLECHGIF_Msk         (0x1ul << OTG_INTSTS_ROLECHGIF_Pos)               /*!< OTG_T::INTSTS: ROLECHGIF Mask             */
+
+#define OTG_INTSTS_VBEIF_Pos             (1)                                               /*!< OTG_T::INTSTS: VBEIF Position             */
+#define OTG_INTSTS_VBEIF_Msk             (0x1ul << OTG_INTSTS_VBEIF_Pos)                   /*!< OTG_T::INTSTS: VBEIF Mask                 */
+
+#define OTG_INTSTS_SRPFIF_Pos            (2)                                               /*!< OTG_T::INTSTS: SRPFIF Position            */
+#define OTG_INTSTS_SRPFIF_Msk            (0x1ul << OTG_INTSTS_SRPFIF_Pos)                  /*!< OTG_T::INTSTS: SRPFIF Mask                */
+
+#define OTG_INTSTS_HNPFIF_Pos            (3)                                               /*!< OTG_T::INTSTS: HNPFIF Position            */
+#define OTG_INTSTS_HNPFIF_Msk            (0x1ul << OTG_INTSTS_HNPFIF_Pos)                  /*!< OTG_T::INTSTS: HNPFIF Mask                */
+
+#define OTG_INTSTS_GOIDLEIF_Pos          (4)                                               /*!< OTG_T::INTSTS: GOIDLEIF Position          */
+#define OTG_INTSTS_GOIDLEIF_Msk          (0x1ul << OTG_INTSTS_GOIDLEIF_Pos)                /*!< OTG_T::INTSTS: GOIDLEIF Mask              */
+
+#define OTG_INTSTS_IDCHGIF_Pos           (5)                                               /*!< OTG_T::INTSTS: IDCHGIF Position           */
+#define OTG_INTSTS_IDCHGIF_Msk           (0x1ul << OTG_INTSTS_IDCHGIF_Pos)                 /*!< OTG_T::INTSTS: IDCHGIF Mask               */
+
+#define OTG_INTSTS_PDEVIF_Pos            (6)                                               /*!< OTG_T::INTSTS: PDEVIF Position            */
+#define OTG_INTSTS_PDEVIF_Msk            (0x1ul << OTG_INTSTS_PDEVIF_Pos)                  /*!< OTG_T::INTSTS: PDEVIF Mask                */
+
+#define OTG_INTSTS_HOSTIF_Pos            (7)                                               /*!< OTG_T::INTSTS: HOSTIF Position            */
+#define OTG_INTSTS_HOSTIF_Msk            (0x1ul << OTG_INTSTS_HOSTIF_Pos)                  /*!< OTG_T::INTSTS: HOSTIF Mask                */
+
+#define OTG_INTSTS_BVLDCHGIF_Pos         (8)                                               /*!< OTG_T::INTSTS: BVLDCHGIF Position         */
+#define OTG_INTSTS_BVLDCHGIF_Msk         (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos)               /*!< OTG_T::INTSTS: BVLDCHGIF Mask             */
+
+#define OTG_INTSTS_AVLDCHGIF_Pos         (9)                                               /*!< OTG_T::INTSTS: AVLDCHGIF Position         */
+#define OTG_INTSTS_AVLDCHGIF_Msk         (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos)               /*!< OTG_T::INTSTS: AVLDCHGIF Mask             */
+
+#define OTG_INTSTS_VBCHGIF_Pos           (10)                                              /*!< OTG_T::INTSTS: VBCHGIF Position           */
+#define OTG_INTSTS_VBCHGIF_Msk           (0x1ul << OTG_INTSTS_VBCHGIF_Pos)                 /*!< OTG_T::INTSTS: VBCHGIF Mask               */
+
+#define OTG_INTSTS_SECHGIF_Pos           (11)                                              /*!< OTG_T::INTSTS: SECHGIF Position           */
+#define OTG_INTSTS_SECHGIF_Msk           (0x1ul << OTG_INTSTS_SECHGIF_Pos)                 /*!< OTG_T::INTSTS: SECHGIF Mask               */
+
+#define OTG_INTSTS_SRPDETIF_Pos          (13)                                              /*!< OTG_T::INTSTS: SRPDETIF Position          */
+#define OTG_INTSTS_SRPDETIF_Msk          (0x1ul << OTG_INTSTS_SRPDETIF_Pos)                /*!< OTG_T::INTSTS: SRPDETIF Mask              */
+
+#define OTG_STATUS_OVERCUR_Pos           (0)                                               /*!< OTG_T::STATUS: OVERCUR Position           */
+#define OTG_STATUS_OVERCUR_Msk           (0x1ul << OTG_STATUS_OVERCUR_Pos)                 /*!< OTG_T::STATUS: OVERCUR Mask               */
+
+#define OTG_STATUS_IDSTS_Pos             (1)                                               /*!< OTG_T::STATUS: IDSTS Position             */
+#define OTG_STATUS_IDSTS_Msk             (0x1ul << OTG_STATUS_IDSTS_Pos)                   /*!< OTG_T::STATUS: IDSTS Mask                 */
+
+#define OTG_STATUS_SESSEND_Pos           (2)                                               /*!< OTG_T::STATUS: SESSEND Position           */
+#define OTG_STATUS_SESSEND_Msk           (0x1ul << OTG_STATUS_SESSEND_Pos)                 /*!< OTG_T::STATUS: SESSEND Mask               */
+
+#define OTG_STATUS_BVLD_Pos              (3)                                               /*!< OTG_T::STATUS: BVLD Position              */
+#define OTG_STATUS_BVLD_Msk              (0x1ul << OTG_STATUS_BVLD_Pos)                    /*!< OTG_T::STATUS: BVLD Mask                  */
+
+#define OTG_STATUS_AVLD_Pos              (4)                                               /*!< OTG_T::STATUS: AVLD Position              */
+#define OTG_STATUS_AVLD_Msk              (0x1ul << OTG_STATUS_AVLD_Pos)                    /*!< OTG_T::STATUS: AVLD Mask                  */
+
+#define OTG_STATUS_VBUSVLD_Pos           (5)                                               /*!< OTG_T::STATUS: VBUSVLD Position           */
+#define OTG_STATUS_VBUSVLD_Msk           (0x1ul << OTG_STATUS_VBUSVLD_Pos)                 /*!< OTG_T::STATUS: VBUSVLD Mask               */
+
+/**@}*/ /* OTG_CONST */
+/**@}*/ /* end of OTG register group */
+
+
+/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
+/**
+    @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
+    Memory Mapped Structure for PDMA Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var DSCT_T::CTL
+ * Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0  Descriptor Table Control Register of PDMA Channel 0~11
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |OPMODE    |PDMA Operation Mode Selection
+ * |        |          |0 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
+ * |        |          |1 = Basic mode: The descriptor table only has one task.
+ * |        |          |When this task is finished, the PDMA_INTSTS[x] will be asserted.
+ * |        |          |2 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute.
+ * |        |          |3 = Reserved.
+ * |        |          |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
+ * |[2]     |TXTYPE    |Transfer Type
+ * |        |          |0 = Burst transfer type.
+ * |        |          |1 = Single transfer type.
+ * |[6:4]   |BURSIZE   |Burst Size
+ * |        |          |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
+ * |        |          |000 = 128 Transfers.
+ * |        |          |001 = 64 Transfers.
+ * |        |          |010 = 32 Transfers.
+ * |        |          |011 = 16 Transfers.
+ * |        |          |100 = 8 Transfers.
+ * |        |          |101 = 4 Transfers.
+ * |        |          |110 = 2 Transfers.
+ * |        |          |111 = 1 Transfers.
+ * |        |          |Note: This field is only useful in burst transfer type.
+ * |[7]     |TBINTDIS  |Table Interrupt Disable
+ * |        |          |This field can be used to decide whether to enable table interrupt or not.
+ * |        |          |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates interrupt.
+ * |        |          |0 = Table interrupt Enabled.
+ * |        |          |1 = Table interrupt Disabled.
+ * |        |          |Note: If this bit set to '1', the TEMPTYF will not be set.
+ * |[9:8]   |SAINC     |Source Address Increment
+ * |        |          |This field is used to set the source address increment size.
+ * |        |          |11 = No increment (fixed address).
+ * |        |          |Others = Increment and size is depended on TXWIDTH selection.
+ * |[11:10] |DAINC     |Destination Address Increment
+ * |        |          |This field is used to set the destination address increment size.
+ * |        |          |11 = No increment (fixed address).
+ * |        |          |Others = Increment and size is depended on TXWIDTH selection.
+ * |[13:12] |TXWIDTH   |Transfer Width Selection
+ * |        |          |This field is used for transfer width.
+ * |        |          |00 = One byte (8 bit) is transferred for every operation.
+ * |        |          |01= One half-word (16 bit) is transferred for every operation.
+ * |        |          |10 = One word (32-bit) is transferred for every operation.
+ * |        |          |11 = Reserved.
+ * |        |          |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
+ * |[29:16] |TXCNT     |Transfer Count
+ * |        |          |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
+ * |        |          |Note: When PDMA finish each transfer data, this field will be decrease immediately.
+ * @var DSCT_T::SA
+ * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4  Source Address Register of PDMA Channel 0~11
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |SA        |PDMA Transfer Source Address Register
+ * |        |          |This field indicates a 32-bit source address of PDMA controller.
+ * @var DSCT_T::DA
+ * Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8  Destination Address Register of PDMA Channel 0~11
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |DA        |PDMA Transfer Destination Address Register
+ * |        |          |This field indicates a 32-bit destination address of PDMA controller.
+ * @var DSCT_T::NEXT
+ * Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC  First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:2]  |NEXT      |PDMA Next Descriptor Table Offset Address Register
+ * |        |          |This field indicates the offset of next descriptor table address in system memory.
+ * |        |          |The system memory based address is 0x2000_0000 (PDMA_SCATBA), if the next descriptor table is 0x2000_0100, then this field must fill in 0x0100.
+ * |        |          |Note1: The next descriptor table address must be word boundary.
+ * |        |          |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
+ */
+
+    __IO uint32_t CTL;           /* Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0  Descriptor Table Control Register of PDMA Channel 0~11 */
+    __IO uint32_t SA;            /* Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4  Source Address Register of PDMA Channel 0~11 */
+    __IO uint32_t DA;            /* Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8  Destination Address Register of PDMA Channel 0~11 */
+    __IO uint32_t NEXT;          /* Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC  First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11 */
+
+} DSCT_T;
+
+
+
+
+typedef struct
+{
+
+
+/**
+ * @var PDMA_T::DSCT
+ * Offset: 0x0000 ~ 0x00BC  DMA Embedded Description Table 0~11
+ * ---------------------------------------------------------------------------------------------------
+ * @var PDMA_T::CURSCAT
+ * Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |CURADDR   |PDMA Current Description Address Register (Read Only)
+ * |        |          |This field indicates a 32-bit current external description address of PDMA controller.
+ * |        |          |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
+ * @var PDMA_T::CHCTL
+ * Offset: 0x400  PDMA Channel Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |CHENn     |PDMA Channel Enable Bit
+ * |        |          |Set this bit to 1 to enable PDMAn operation.
+ * |        |          |If each channel is not set as enabled, each channel cannot be active.
+ * |        |          |0 = PDMA channel [n] Disabled.
+ * |        |          |1 = PDMA channel [n] Enabled.
+ * |        |          |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
+ * |        |          |Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
+ * @var PDMA_T::STOP
+ * Offset: 0x404  PDMA Transfer Stop Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |STOPn     |PDMA Transfer Stop Control Register (Write Only)
+ * |        |          |User can stop the PDMA transfer by STOPn bit field or by software reset (writing '0xFFFF_FFFF' to PDMA_STOP register).
+ * |        |          |By bit field:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Stop PDMA transfer[n].
+ * |        |          |When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag.
+ * |        |          |By write 0xFFFF_FFFF to PDMA_STOP:
+ * |        |          |Setting all PDMA_STOP bit to "1" will generate software reset to reset internal state machine (the DSCT will not be reset).
+ * |        |          |When software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag will be cleared to '0'.
+ * |        |          |Note: User can poll channel enable bit to know if the on-going transfer is finished.
+ * @var PDMA_T::SWREQ
+ * Offset: 0x408  PDMA Software Request Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |SWREQn    |PDMA Software Request Register (Write Only)
+ * |        |          |Set this bit to 1 to generate a software request to PDMA [n].
+ * |        |          |0 = No effect.
+ * |        |          |1 = Generate a software request.
+ * |        |          |Note1: User can read PDMA_TRGSTS register to know which channel is on active.
+ * |        |          |Active flag may be triggered by software request or peripheral request.
+ * |        |          |Note2: If user does not enable each PDMA channel, the software request will be ignored.
+ * @var PDMA_T::TRGSTS
+ * Offset: 0x40C  PDMA Channel Request Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |REQSTSn   |PDMA Channel Request Status (Read Only)
+ * |        |          |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral.
+ * |        |          |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
+ * |        |          |0 = PDMA Channel n has no request.
+ * |        |          |1 = PDMA Channel n has a request.
+ * |        |          |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
+ * |        |          |Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
+ * @var PDMA_T::PRISET
+ * Offset: 0x410  PDMA Fixed Priority Setting Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |FPRISETn  |PDMA Fixed Priority Setting Register
+ * |        |          |Set this bit to 1 to enable fixed priority level.
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Set PDMA channel [n] to fixed priority channel.
+ * |        |          |Read Operation:
+ * |        |          |0 = Corresponding PDMA channel is round-robin priority.
+ * |        |          |1 = Corresponding PDMA channel is fixed priority.
+ * |        |          |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
+ * @var PDMA_T::PRICLR
+ * Offset: 0x414  PDMA Fixed Priority Clear Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |FPRICLRn  |PDMA Fixed Priority Clear Register (Write Only)
+ * |        |          |Set this bit to 1 to clear fixed priority level.
+ * |        |          |0 = No effect.
+ * |        |          |1 = Clear PDMA channel [n] fixed priority setting.
+ * |        |          |Note: User can read PDMA_PRISET register to know the channel priority.
+ * @var PDMA_T::INTEN
+ * Offset: 0x418  PDMA Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |INTENn    |PDMA Interrupt Enable Register
+ * |        |          |This field is used for enabling PDMA channel[n] interrupt.
+ * |        |          |0 = PDMA channel n interrupt Disabled.
+ * |        |          |1 = PDMA channel n interrupt Enabled.
+ * |[31:12] |Reserved  |should be keep 0.
+ * @var PDMA_T::INTSTS
+ * Offset: 0x41C  PDMA Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ABTIF     |PDMA Read/Write Target Abort Interrupt Flag (Read-Only)
+ * |        |          |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
+ * |        |          |0 = No AHB bus ERROR response received.
+ * |        |          |1 = AHB bus ERROR response received.
+ * |[1]     |TDIF      |Transfer Done Interrupt Flag (Read Only)
+ * |        |          |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
+ * |        |          |0 = Not finished yet.
+ * |        |          |1 = PDMA channel has finished transmission.
+ * |[2]     |TEIF      |Table Empty Interrupt Flag (Read Only)
+ * |        |          |This bit indicates that PDMA controller has finished each table transmission and the operation is Stop mode.
+ * |        |          |User can read TEIF register to indicate which channel finished transfer.
+ * |        |          |0 = PDMA channel transfer is not finished.
+ * |        |          |1 = PDMA channel transfer is finished and the operation is in idle state.
+ * |[8:15]  |REQTOFn   |Request Time-out Flag For Each Channel [N](M45xD/M45xC Only)
+ * |        |          |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
+ * |        |          |0 = No request time-out.
+ * |        |          |1 = Peripheral request time-out.
+ * @var PDMA_T::ABTSTS
+ * Offset: 0x420  PDMA Channel Read/Write Target Abort Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |ABTIFn    |PDMA Read/Write Target Abort Interrupt Status Flag
+ * |        |          |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
+ * |        |          |0 = No AHB bus ERROR response received when channel n transfer.
+ * |        |          |1 = AHB bus ERROR response received when channel n transfer.
+ * @var PDMA_T::TDSTS
+ * Offset: 0x424  PDMA Channel Transfer Done Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |TDIFn     |Transfer Done Flag Register
+ * |        |          |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
+ * |        |          |0 = PDMA channel transfer has not finished.
+ * |        |          |1 = PDMA channel has finished transmission.
+ * @var PDMA_T::SCATSTS
+ * Offset: 0x428  PDMA Scatter-Gather Table Empty Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |TEMPTYFn  |Scatter-Gather Table Empty Flag Register
+ * |        |          |This bit indicates which PDMA channel n Scatter Gather table is empty when SWREQn set to high or channel has finished transmission and the operation mode is Stop mode.
+ * |        |          |User can write 1 to clear these bits.
+ * |        |          |0 = PDMA channel scatter-gather table is not empty.
+ * |        |          |1 = PDMA channel scatter-gather table is empty and PDMA SWREQ has be set.
+ * @var PDMA_T::TACTSTS
+ * Offset: 0x42C  PDMA Transfer Active Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |TXACTFn   |Transfer On Active Flag Register (Read Only)
+ * |        |          |This bit indicates which PDMA channel is in active.
+ * |        |          |0 = PDMA channel is not finished.
+ * |        |          |1 = PDMA channel is active.
+ * @var PDMA_T::TOUTEN
+ * Offset: 0x434  PDMA Time-out Enable register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |TOUTENn   |PDMA Time-Out Enable Bits
+ * |        |          |0 = PDMA Channel n time-out function Disable.
+ * |        |          |1 = PDMA Channel n time-out function Enable.
+ * @var PDMA_T::TOUTIEN
+ * Offset: 0x438  PDMA Time-out Interrupt Enable register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |TOUTIENn  |PDMA Time-Out Interrupt Enable Bits
+ * |        |          |0 = PDMA Channel n time-out interrupt Disable.
+ * |        |          |1 = PDMA Channel n time-out interrupt Enable.
+ * @var PDMA_T::SCATBA
+ * Offset: 0x43C  PDMA Scatter-Gather Descriptor Table Base Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:16] |SCATBA    |PDMA Scatter-Gather Descriptor Table Address Register
+ * |        |          |In Scatter-Gather mode, this is the base address for calculating the next link - list address.
+ * |        |          |The next link address equation is.
+ * |        |          |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
+ * |        |          |Note: Only useful in Scatter-Gather mode.
+ * @var PDMA_T::TOC0_1
+ * Offset: 0x440  PDMA Time-out Counter Ch1 and Ch0 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:16] |TOC1      |Time-Out Counter For Channel 1
+ * |        |          |This controls the period of time-out function for channel 1. The calculation unit is based on 10 kHz clock.
+ * |[15:0]  |TOC0      |Time-Out Counter For Channel 0
+ * |        |          |This controls the period of time-out function for channel 0. The calculation unit is based on 10 kHz clock.
+ * @var PDMA_T::TOC2_3
+ * Offset: 0x444  PDMA Time-out Counter Ch3 and Ch2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:16] |TOC3      |Time-Out Counter For Channel 3
+ * |        |          |This controls the period of time-out function for channel 3. The calculation unit is based on 10 kHz clock.
+ * |[15:0]  |TOC2      |Time-Out Counter For Channel 2
+ * |        |          |This controls the period of time-out function for channel 2. The calculation unit is based on 10 kHz clock.
+ * @var PDMA_T::TOC4_5
+ * Offset: 0x448  PDMA Time-out Counter Ch5 and Ch4 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:16] |TOC5      |Time-Out Counter For Channel 5
+ * |        |          |This controls the period of time-out function for channel 5. The calculation unit is based on 10 kHz clock.
+ * |[15:0]  |TOC4      |Time-Out Counter For Channel 4
+ * |        |          |This controls the period of time-out function for channel 4. The calculation unit is based on 10 kHz clock.
+ * @var PDMA_T::TOC6_7
+ * Offset: 0x44C  PDMA Time-out Counter Ch7 and Ch6 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:16] |TOC7      |Time-Out Counter For Channel 7
+ * |        |          |This controls the period of time-out function for channel 7. The calculation unit is based on 10 kHz clock.
+ * |[15:0]  |TOC6      |Time-Out Counter For Channel 6
+ * |        |          |This controls the period of time-out function for channel 6. The calculation unit is based on 10 kHz clock.
+ * @var PDMA_T::REQSEL0_3
+ * Offset: 0x480  PDMA Request Source Select Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[4:0]   |REQSRC0   |Channel 0 Request Source Selection
+ * |        |          |This filed defines which peripheral is connected to PDMA channel 0.
+ * |        |          |User can configure the peripheral by setting REQSRC0.
+ * |        |          |1 = Channel connects to SPI0_TX.
+ * |        |          |2 = Channel connects to SPI1_TX.
+ * |        |          |3 = Channel connects to SPI2_TX.
+ * |        |          |4 = Channel connects to UART0_TX.
+ * |        |          |5 = Channel connects to UART1_TX.
+ * |        |          |6 = Channel connects to UART2_TX.
+ * |        |          |7 = Channel connects to UART3_TX.
+ * |        |          |8 = Channel connects to DAC_TX.
+ * |        |          |9 = Channel connects to ADC_RX.
+ * |        |          |11 = Channel connects to PWM0_P1_RX.
+ * |        |          |12 = Channel connects to PWM0_P2_RX.
+ * |        |          |13 = Channel connects to PWM0_P3_RX.
+ * |        |          |14 = Channel connects to PWM1_P1_RX.
+ * |        |          |15 = Channel connects to PWM1_P2_RX.
+ * |        |          |16 = Channel connects to PWM1_P3_RX.
+ * |        |          |17 = Channel connects to SPI0_RX.
+ * |        |          |18 = Channel connects to SPI1_RX.
+ * |        |          |19 = Channel connects to SPI2_RX.
+ * |        |          |20 = Channel connects to UART0_RX.
+ * |        |          |21 = Channel connects to UART1_RX.
+ * |        |          |22 = Channel connects to UART2_RX.
+ * |        |          |23 = Channel connects to UART3_RX.
+ * |        |          |31 = Disable PDMA.
+ * |        |          |Others = Reserved.
+ * |        |          |Note 1: A peripheral can't assign to two channels at the same time.
+ * |        |          |Note 2: This field is useless when transfer between memory and memory.
+ * |[12:8]  |REQSRC1   |Channel 1 Request Source Selection
+ * |        |          |This filed defines which peripheral is connected to PDMA channel 1.
+ * |        |          |User can configure the peripheral setting by REQSRC1.
+ * |        |          |Note: The channel configuration is the same as REQSRC0 field.
+ * |        |          |Please refer to the explanation of REQSRC0.
+ * |[20:16] |REQSRC2   |Channel 2 Request Source Selection
+ * |        |          |This filed defines which peripheral is connected to PDMA channel 2.
+ * |        |          |User can configure the peripheral setting by REQSRC2.
+ * |        |          |Note: The channel configuration is the same as REQSRC0 field.
+ * |        |          |Please refer to the explanation of REQSRC0.
+ * |[28:24] |REQSRC3   |Channel 3 Request Source Selection
+ * |        |          |This filed defines which peripheral is connected to PDMA channel 3.
+ * |        |          |User can configure the peripheral setting by REQSRC3.
+ * |        |          |Note: The channel configuration is the same as REQSRC0 field.
+ * |        |          |Please refer to the explanation of REQSRC0.
+ * @var PDMA_T::REQSEL4_7
+ * Offset: 0x484  PDMA Request Source Select Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[4:0]   |REQSRC4   |Channel 4 Request Source Selection
+ * |        |          |This filed defines which peripheral is connected to PDMA channel 4.
+ * |        |          |User can configure the peripheral setting by REQSRC4.
+ * |        |          |Note: The channel configuration is the same as REQSRC0 field.
+ * |        |          |Please refer to the explanation of REQSRC0.
+ * |[12:8]  |REQSRC5   |Channel 5 Request Source Selection
+ * |        |          |This filed defines which peripheral is connected to PDMA channel 5.
+ * |        |          |User can configure the peripheral setting by REQSRC5.
+ * |        |          |Note: The channel configuration is the same as REQSRC0 field.
+ * |        |          |Please refer to the explanation of REQSRC0.
+ * |[20:16] |REQSRC6   |Channel 6 Request Source Selection
+ * |        |          |This filed defines which peripheral is connected to PDMA channel 6.
+ * |        |          |User can configure the peripheral setting by REQSRC6.
+ * |        |          |Note: The channel configuration is the same as REQSRC0 field.
+ * |        |          |Please refer to the explanation of REQSRC0.
+ * |[28:24] |REQSRC7   |Channel 7 Request Source Selection
+ * |        |          |This filed defines which peripheral is connected to PDMA channel 7.
+ * |        |          |User can configure the peripheral setting by REQSRC7.
+ * |        |          |Note: The channel configuration is the same as REQSRC0 field.
+ * |        |          |Please refer to the explanation of REQSRC0.
+ * @var PDMA_T::REQSEL8_11
+ * Offset: 0x488  PDMA Request Source Select Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[4:0]   |REQSRC8   |Channel 8 Request Source Selection
+ * |        |          |This filed defines which peripheral is connected to PDMA channel 8.
+ * |        |          |User can configure the peripheral setting by REQSRC8.
+ * |        |          |Note: The channel configuration is the same as REQSRC0 field.
+ * |        |          |Please refer to the explanation of REQSRC0.
+ * |[12:8]  |REQSRC9   |Channel 9 Request Source Selection
+ * |        |          |This filed defines which peripheral is connected to PDMA channel 9.
+ * |        |          |User can configure the peripheral setting by REQSRC9.
+ * |        |          |Note: The channel configuration is the same as REQSRC0 field.
+ * |        |          |Please refer to the explanation of REQSRC0.
+ * |[20:16] |REQSRC10  |Channel 10 Request Source Selection
+ * |        |          |This filed defines which peripheral is connected to PDMA channel 10.
+ * |        |          |User can configure the peripheral setting by REQSRC10.
+ * |        |          |Note: The channel configuration is the same as REQSRC0 field.
+ * |        |          |Please refer to the explanation of REQSRC0.
+ * |[28:24] |REQSRC11  |Channel 11 Request Source Selection
+ * |        |          |This filed defines which peripheral is connected to PDMA channel 11.
+ * |        |          |User can configure the peripheral setting by REQSRC11.
+ * |        |          |Note: The channel configuration is the same as REQSRC0 field.
+ * |        |          |Please refer to the explanation of REQSRC0.
+ */
+    
+    DSCT_T        DSCT[12];      /* Offset: 0x0000 ~ 0x00BC  DMA Embedded Description Table 0~11                     */             
+    __I  uint32_t CURSCAT[12];                                                                                                      
+    __I  uint32_t RESERVE0[196]; /* Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11 */     
+    __IO uint32_t CHCTL;         /* Offset: 0x400  PDMA Channel Control Register                                     */             
+    __O  uint32_t STOP;          /* Offset: 0x404  PDMA Transfer Stop Control Register                               */             
+    __O  uint32_t SWREQ;         /* Offset: 0x408  PDMA Software Request Register                                    */             
+    __I  uint32_t TRGSTS;        /* Offset: 0x40C  PDMA Channel Request Status Register                              */             
+    __IO uint32_t PRISET;        /* Offset: 0x410  PDMA Fixed Priority Setting Register                              */             
+    __O  uint32_t PRICLR;        /* Offset: 0x414  PDMA Fixed Priority Clear Register                                */             
+    __IO uint32_t INTEN;         /* Offset: 0x418  PDMA Interrupt Enable Register                                    */             
+    __IO uint32_t INTSTS;        /* Offset: 0x41C  PDMA Interrupt Status Register                                    */             
+    __IO uint32_t ABTSTS;        /* Offset: 0x420  PDMA Channel Read/Write Target Abort Flag Register                */             
+    __IO uint32_t TDSTS;         /* Offset: 0x424  PDMA Channel Transfer Done Flag Register                          */             
+    __IO uint32_t SCATSTS;       /* Offset: 0x428  PDMA Scatter-Gather Table Empty Status Register                   */             
+    __I  uint32_t TACTSTS;                                                                                                          
+    __I  uint32_t RESERVE1[1];   /* Offset: 0x42C  PDMA Transfer Active Flag Register                                */             
+    __IO uint32_t TOUTEN;        /* Offset: 0x434  PDMA Time-out Enable register                                     */             
+    __IO uint32_t TOUTIEN;       /* Offset: 0x438  PDMA Time-out Interrupt Enable register                           */             
+    __IO uint32_t SCATBA;        /* Offset: 0x43C  PDMA Scatter-Gather Descriptor Table Base Address Register        */             
+    __IO uint32_t TOC0_1;        /* Offset: 0x440  PDMA Time-out Counter Ch1 and Ch0 Register                        */             
+    __IO uint32_t TOC2_3;        /* Offset: 0x444  PDMA Time-out Counter Ch3 and Ch2 Register                        */             
+    __IO uint32_t TOC4_5;        /* Offset: 0x448  PDMA Time-out Counter Ch5 and Ch4 Register                        */             
+    __IO uint32_t TOC6_7;                                                                                                           
+    __I  uint32_t RESERVE2[12];  /* Offset: 0x44C  PDMA Time-out Counter Ch7 and Ch6 Register                        */             
+    __IO uint32_t REQSEL0_3;     /* Offset: 0x480  PDMA Request Source Select Register 0                             */             
+    __IO uint32_t REQSEL4_7;     /* Offset: 0x484  PDMA Request Source Select Register 1                             */             
+    __IO uint32_t REQSEL8_11;    /* Offset: 0x484  PDMA Request Source Select Register 2                             */
+
+} PDMA_T;
+
+
+
+/**
+    @addtogroup PDMA_CONST PDMA Bit Field Definition
+    Constant Definitions for PDMA Controller
+@{ */
+
+#define PDMA_DSCT_CTL_OPMODE_Pos         (0)                                               /*!< DSCT_T::CTL: OPMODE Position              */
+#define PDMA_DSCT_CTL_OPMODE_Msk         (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos)               /*!< DSCT_T::CTL: OPMODE Mask                  */
+
+#define PDMA_DSCT_CTL_TXTYPE_Pos         (2)                                               /*!< DSCT_T::CTL: TXTYPE Position              */
+#define PDMA_DSCT_CTL_TXTYPE_Msk         (1ul << PDMA_DSCT_CTL_TXTYPE_Pos)                 /*!< DSCT_T::CTL: TXTYPE Mask                  */
+
+#define PDMA_DSCT_CTL_BURSIZE_Pos        (4)                                               /*!< DSCT_T::CTL: BURSIZE Position             */
+#define PDMA_DSCT_CTL_BURSIZE_Msk        (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos)              /*!< DSCT_T::CTL: BURSIZE Mask                 */
+
+#define PDMA_DSCT_CTL_TBINTDIS_Pos       (7)                                               /*!< DSCT_T::CTL: TBINTDIS Position            */
+#define PDMA_DSCT_CTL_TBINTDIS_Msk       (1ul << PDMA_DSCT_CTL_TBINTDIS_Pos)               /*!< DSCT_T::CTL: TBINTDIS Mask                */
+
+#define PDMA_DSCT_CTL_SAINC_Pos          (8)                                               /*!< DSCT_T::CTL: SAINC Position               */
+#define PDMA_DSCT_CTL_SAINC_Msk          (0x3ul << PDMA_DSCT_CTL_SAINC_Pos)                /*!< DSCT_T::CTL: SAINC Mask                   */
+
+#define PDMA_DSCT_CTL_DAINC_Pos          (10)                                              /*!< DSCT_T::CTL: DAINC Position               */
+#define PDMA_DSCT_CTL_DAINC_Msk          (0x3ul << PDMA_DSCT_CTL_DAINC_Pos)                /*!< DSCT_T::CTL: DAINC Mask                   */
+
+#define PDMA_DSCT_CTL_TXWIDTH_Pos        (12)                                              /*!< DSCT_T::CTL: TXWIDTH Position             */
+#define PDMA_DSCT_CTL_TXWIDTH_Msk        (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos)              /*!< DSCT_T::CTL: TXWIDTH Mask                 */
+
+#define PDMA_DSCT_CTL_TXCNT_Pos          (16)                                              /*!< DSCT_T::CTL: TXCNT Position               */
+#define PDMA_DSCT_CTL_TXCNT_Msk          (0x3FFFul << PDMA_DSCT_CTL_TXCNT_Pos)             /*!< DSCT_T::CTL: TXCNT Mask                   */
+
+#define PDMA_DSCT_SA_SA_Pos              (0)                                               /*!< DSCT_T::SA: SA Position                   */
+#define PDMA_DSCT_SA_SA_Msk              (0xFFFFFFFFul << PDMA_DSCT_SA_SA_Pos)             /*!< DSCT_T::SA: SA Mask                       */
+
+#define PDMA_DSCT_DA_DA_Pos              (0)                                               /*!< DSCT_T::DA: DA Position                   */
+#define PDMA_DSCT_DA_DA_Msk              (0xFFFFFFFFul << PDMA_DSCT_DA_DA_Pos)             /*!< DSCT_T::DA: DA Mask                       */
+
+#define PDMA_DSCT_NEXT_NEXT_Pos          (0)                                               /*!< DSCT_T::NEXT: NEXT Position               */
+#define PDMA_DSCT_NEXT_NEXT_Msk          (0xFFFFul << PDMA_DSCT_NEXT_NEXT_Pos)             /*!< DSCT_T::NEXT: NEXT Mask                   */
+
+#define PDMA_CURSCAT_CURADDR_Pos         (0)                                               /*!< PDMA_T::CURSCAT: CURADDR Position         */
+#define PDMA_CURSCAT_CURADDR_Msk         (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos)        /*!< PDMA_T::CURSCAT: CURADDR Mask             */
+
+#define PDMA_CHCTL_CHENn_Pos             (0)                                               /*!< PDMA_T::CHCTL: CHENn Position             */
+#define PDMA_CHCTL_CHENn_Msk             (0xffful << PDMA_CHCTL_CHENn_Pos)                 /*!< PDMA_T::CHCTL: CHENn Mask                 */
+
+#define PDMA_STOP_STOPn_Pos              (0)                                               /*!< PDMA_T::STOP: STOPn Position              */
+#define PDMA_STOP_STOPn_Msk              (0xffful << PDMA_STOP_STOPn_Pos)                  /*!< PDMA_T::STOP: STOPn Mask                  */
+
+#define PDMA_SWREQ_SWREQn_Pos            (0)                                               /*!< PDMA_T::SWREQ: SWREQn Position            */
+#define PDMA_SWREQ_SWREQn_Msk            (0xffful << PDMA_SWREQ_SWREQn_Pos)                /*!< PDMA_T::SWREQ: SWREQn Mask                */
+
+#define PDMA_TRGSTS_REQSTSn_Pos          (0)                                               /*!< PDMA_T::TRGSTS: REQSTSn Position          */
+#define PDMA_TRGSTS_REQSTSn_Msk          (0xffful << PDMA_TRGSTS_REQSTSn_Pos)              /*!< PDMA_T::TRGSTS: REQSTSn Mask              */
+
+#define PDMA_PRISET_FPRISETn_Pos         (0)                                               /*!< PDMA_T::PRISET: FPRISETn Position         */
+#define PDMA_PRISET_FPRISETn_Msk         (0xffful << PDMA_PRISET_FPRISETn_Pos)             /*!< PDMA_T::PRISET: FPRISETn Mask             */
+
+#define PDMA_PRICLR_FPRICLRn_Pos         (0)                                               /*!< PDMA_T::PRICLR: FPRICLRn Position         */
+#define PDMA_PRICLR_FPRICLRn_Msk         (0xffful << PDMA_PRICLR_FPRICLRn_Pos)             /*!< PDMA_T::PRICLR: FPRICLRn Mask             */
+
+#define PDMA_INTEN_INTENn_Pos            (0)                                               /*!< PDMA_T::INTEN: INTENn Position            */
+#define PDMA_INTEN_INTENn_Msk            (0xffful << PDMA_INTEN_INTENn_Pos)                /*!< PDMA_T::INTEN: INTENn Mask                */
+
+#define PDMA_INTSTS_ABTIF_Pos            (0)                                               /*!< PDMA_T::INTSTS: ABTIF Position            */
+#define PDMA_INTSTS_ABTIF_Msk            (0x1ul << PDMA_INTSTS_ABTIF_Pos)                  /*!< PDMA_T::INTSTS: ABTIF Mask                */
+
+#define PDMA_INTSTS_TDIF_Pos             (1)                                               /*!< PDMA_T::INTSTS: TDIF Position             */
+#define PDMA_INTSTS_TDIF_Msk             (0x1ul << PDMA_INTSTS_TDIF_Pos)                   /*!< PDMA_T::INTSTS: TDIF Mask                 */
+
+#define PDMA_INTSTS_TEIF_Pos             (2)                                               /*!< PDMA_T::INTSTS: TEIF Position             */
+#define PDMA_INTSTS_TEIF_Msk             (0x1ul << PDMA_INTSTS_TEIF_Pos)                   /*!< PDMA_T::INTSTS: TEIF Mask                 */
+
+#define PDMA_INTSTS_REQTOFn_Pos          (8)                                               /*!< PDMA_T::INTSTS: REQTOFn Position          */
+#define PDMA_INTSTS_REQTOFn_Msk          (0xfful << PDMA_INTSTS_REQTOFn_Pos)               /*!< PDMA_T::INTSTS: REQTOFn Mask              */
+
+#define PDMA_ABTSTS_ABTIFn_Pos           (0)                                               /*!< PDMA_T::ABTSTS: ABTIFn Position           */
+#define PDMA_ABTSTS_ABTIFn_Msk           (0xffful << PDMA_ABTSTS_ABTIFn_Pos)               /*!< PDMA_T::ABTSTS: ABTIFn Mask               */
+
+#define PDMA_TDSTS_TDIFn_Pos             (0)                                               /*!< PDMA_T::TDSTS: TDIFn Position             */
+#define PDMA_TDSTS_TDIFn_Msk             (0xffful << PDMA_TDSTS_TDIFn_Pos)                 /*!< PDMA_T::TDSTS: TDIFn Mask                 */
+
+#define PDMA_SCATSTS_TEMPTYFn_Pos        (0)                                               /*!< PDMA_T::SCATSTS: TEMPTYFn Position        */
+#define PDMA_SCATSTS_TEMPTYFn_Msk        (0xffful << PDMA_SCATSTS_TEMPTYFn_Pos)            /*!< PDMA_T::SCATSTS: TEMPTYFn Mask            */
+
+#define PDMA_TACTSTS_TXACTFn_Pos         (0)                                               /*!< PDMA_T::TACTSTS: TXACTFn Position         */
+#define PDMA_TACTSTS_TXACTFn_Msk         (0xffful << PDMA_TACTSTS_TXACTFn_Pos)             /*!< PDMA_T::TACTSTS: TXACTFn Mask             */
+
+#define PDMA_TOUTEN_TOUTENn_Pos          (0)                                               /*!< PDMA_T::TOUTEN: TOUTENn Position          */
+#define PDMA_TOUTEN_TOUTENn_Msk          (0xfful << PDMA_TOUTEN_TOUTENn_Pos)               /*!< PDMA_T::TOUTEN: TOUTENn Mask              */
+
+#define PDMA_TOUTIEN_TOUTIENn_Pos        (0)                                               /*!< PDMA_T::TOUTIEN: TOUTIENn Position        */
+#define PDMA_TOUTIEN_TOUTIENn_Msk        (0xfful << PDMA_TOUTIEN_TOUTIENn_Pos)             /*!< PDMA_T::TOUTIEN: TOUTIENn Mask            */
+
+#define PDMA_SCATBA_SCATBA_Pos           (16)                                              /*!< PDMA_T::SCATBA: SCATBA Position           */
+#define PDMA_SCATBA_SCATBA_Msk           (0xfffful << PDMA_SCATBA_SCATBA_Pos)              /*!< PDMA_T::SCATBA: SCATBA Mask               */
+
+#define PDMA_TOC0_1_TOC0_Pos             (0)                                               /*!< PDMA_T::TOC0_1: TOC0 Position             */
+#define PDMA_TOC0_1_TOC0_Msk             (0xfffful << PDMA_TOC0_1_TOC0_Pos)                /*!< PDMA_T::TOC0_1: TOC0 Mask                 */
+
+#define PDMA_TOC0_1_TOC1_Pos             (16)                                              /*!< PDMA_T::TOC0_1: TOC1 Position             */
+#define PDMA_TOC0_1_TOC1_Msk             (0xfffful << PDMA_TOC0_1_TOC1_Pos)                /*!< PDMA_T::TOC0_1: TOC1 Mask                 */
+
+#define PDMA_TOC2_3_TOC2_Pos             (0)                                               /*!< PDMA_T::TOC2_3: TOC2 Position             */
+#define PDMA_TOC2_3_TOC2_Msk             (0xfffful << PDMA_TOC2_3_TOC2_Pos)                /*!< PDMA_T::TOC2_3: TOC2 Mask                 */
+
+#define PDMA_TOC2_3_TOC3_Pos             (16)                                              /*!< PDMA_T::TOC2_3: TOC3 Position             */
+#define PDMA_TOC2_3_TOC3_Msk             (0xfffful << PDMA_TOC2_3_TOC3_Pos)                /*!< PDMA_T::TOC2_3: TOC3 Mask                 */
+
+#define PDMA_TOC4_5_TOC4_Pos             (0)                                               /*!< PDMA_T::TOC4_5: TOC4 Position             */
+#define PDMA_TOC4_5_TOC4_Msk             (0xfffful << PDMA_TOC4_5_TOC4_Pos)                /*!< PDMA_T::TOC4_5: TOC4 Mask                 */
+
+#define PDMA_TOC4_5_TOC5_Pos             (16)                                              /*!< PDMA_T::TOC4_5: TOC5 Position             */
+#define PDMA_TOC4_5_TOC5_Msk             (0xfffful << PDMA_TOC4_5_TOC5_Pos)                /*!< PDMA_T::TOC4_5: TOC5 Mask                 */
+
+#define PDMA_TOC6_7_TOC6_Pos             (0)                                               /*!< PDMA_T::TOC6_7: TOC6 Position             */
+#define PDMA_TOC6_7_TOC6_Msk             (0xfffful << PDMA_TOC6_7_TOC6_Pos)                /*!< PDMA_T::TOC6_7: TOC6 Mask                 */
+
+#define PDMA_TOC6_7_TOC7_Pos             (16)                                              /*!< PDMA_T::TOC6_7: TOC7 Position             */
+#define PDMA_TOC6_7_TOC7_Msk             (0xfffful << PDMA_TOC6_7_TOC7_Pos)                /*!< PDMA_T::TOC6_7: TOC7 Mask                 */
+
+#define PDMA_REQSEL0_3_REQSRC0_Pos       (0)                                               /*!< PDMA_T::REQSEL0_3: REQSRC0 Position       */
+#define PDMA_REQSEL0_3_REQSRC0_Msk       (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos)            /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask           */
+
+#define PDMA_REQSEL0_3_REQSRC1_Pos       (8)                                               /*!< PDMA_T::REQSEL0_3: REQSRC1 Position       */
+#define PDMA_REQSEL0_3_REQSRC1_Msk       (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos)            /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask           */
+
+#define PDMA_REQSEL0_3_REQSRC2_Pos       (16)                                              /*!< PDMA_T::REQSEL0_3: REQSRC2 Position       */
+#define PDMA_REQSEL0_3_REQSRC2_Msk       (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos)            /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask           */
+
+#define PDMA_REQSEL0_3_REQSRC3_Pos       (24)                                              /*!< PDMA_T::REQSEL0_3: REQSRC3 Position       */
+#define PDMA_REQSEL0_3_REQSRC3_Msk       (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos)            /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask           */
+
+#define PDMA_REQSEL4_7_REQSRC4_Pos       (0)                                               /*!< PDMA_T::REQSEL4_7: REQSRC4 Position       */
+#define PDMA_REQSEL4_7_REQSRC4_Msk       (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos)            /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask           */
+
+#define PDMA_REQSEL4_7_REQSRC5_Pos       (8)                                               /*!< PDMA_T::REQSEL4_7: REQSRC5 Position       */
+#define PDMA_REQSEL4_7_REQSRC5_Msk       (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos)            /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask           */
+
+#define PDMA_REQSEL4_7_REQSRC6_Pos       (16)                                              /*!< PDMA_T::REQSEL4_7: REQSRC6 Position       */
+#define PDMA_REQSEL4_7_REQSRC6_Msk       (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos)            /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask           */
+
+#define PDMA_REQSEL4_7_REQSRC7_Pos       (24)                                              /*!< PDMA_T::REQSEL4_7: REQSRC7 Position       */
+#define PDMA_REQSEL4_7_REQSRC7_Msk       (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos)            /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask           */
+
+#define PDMA_REQSEL8_11_REQSRC8_Pos      (0)                                               /*!< PDMA_T::REQSEL8_11: REQSRC8 Position      */
+#define PDMA_REQSEL8_11_REQSRC8_Msk      (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos)           /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask          */
+
+#define PDMA_REQSEL8_11_REQSRC9_Pos      (8)                                               /*!< PDMA_T::REQSEL8_11: REQSRC9 Position      */
+#define PDMA_REQSEL8_11_REQSRC9_Msk      (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos)           /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask          */
+
+#define PDMA_REQSEL8_11_REQSRC10_Pos     (16)                                              /*!< PDMA_T::REQSEL8_11: REQSRC10 Position     */
+#define PDMA_REQSEL8_11_REQSRC10_Msk     (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos)          /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask         */
+
+#define PDMA_REQSEL8_11_REQSRC11_Pos     (24)                                              /*!< PDMA_T::REQSEL8_11: REQSRC11 Position     */
+#define PDMA_REQSEL8_11_REQSRC11_Msk     (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos)          /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask         */
+
+/**@}*/ /* PDMA_CONST */
+/**@}*/ /* end of PDMA register group */
+
+
+/*---------------------- Pulse Width Modulation Controller -------------------------*/
+/**
+    @addtogroup PWM Pulse Width Modulation Controller(PWM)
+    Memory Mapped Structure for PWM Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var PWM_T::CTL0
+ * Offset: 0x00  PWM Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |CTRLDn    |Center Re-Load
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period.
+ * |        |          |CMPDAT will load to CMPBUF at the center point of a period.
+ * |[13:8]  |WINLDENn  |Window Load Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = PERIOD will load to PBUF at the end point of each period.
+ * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * |        |          |1 = PERIOD will load to PBUF at the end point of each period.
+ * |        |          |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set.
+ * |        |          |The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success.
+ * |[21:16] |IMMLDENn  |Immediately Load Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = PERIOD will load to PBUF at the end point of each period.
+ * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * |        |          |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+ * |[24]    |GROUPEN   |Group Function Enable
+ * |        |          |0 = The output waveform of each PWM channel are independent.
+ * |        |          |1 = Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1.
+ * |[30]    |DBGHALT   |ICE Debug Mode Counter Halt (Write Protect)
+ * |        |          |If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode.
+ * |        |          |0 = ICE debug mode counter halt disable.
+ * |        |          |1 = ICE debug mode counter halt enable.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[31]    |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
+ * |        |          |0 = ICE debug mode acknowledgement effects PWM output.
+ * |        |          |PWM pin will be forced as tri-state while ICE debug mode acknowledged.
+ * |        |          |1 = ICE debug mode acknowledgement disabled.
+ * |        |          |PWM pin will keep output no matter ICE debug mode acknowledged or not.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::CTL1
+ * Offset: 0x04  PWM Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |CNTTYPEn  |PWM Counter Behavior Type
+ * |        |          |Each bit n controls corresponding PWM channel n.
+ * |        |          |00 = Up counter type (supports in capture mode).
+ * |        |          |01 = Down count type (supports in capture mode).
+ * |        |          |10 = Up-down counter type.
+ * |        |          |11 = Reserved.
+ * |[21:16] |CNTMODEn  |PWM Counter Mode
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Auto-reload mode.
+ * |        |          |1 = One-shot mode.
+ * |[26:24] |OUTMODEn  |PWM Output Mode
+ * |        |          |Each bit n controls the
+ * |        |          |output mode of
+ * |        |          |corresponding PWM channel n.
+ * |        |          |0 = PWM independent mode.
+ * |        |          |1 = PWM complementary mode.
+ * |        |          |Note: When operating in group function, these bits must all set to the same mode.
+ * @var PWM_T::SYNC
+ * Offset: 0x08  PWM Synchronization Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[2:0]   |PHSENn    |SYNC Phase Enable
+ * |        |          |Each bit n controls corresponding PWM channel n.
+ * |        |          |0 = PWM counter disable to load PHS value.
+ * |        |          |1 = PWM counter enable to load PHS value.
+ * |[13:8]  |SINSRCn   |PWM_SYNC_IN Source Selection
+ * |        |          |Each bit n controls corresponding PWM channel n.
+ * |        |          |00 = Synchronize source from SYNC_IN or SWSYNC.
+ * |        |          |01 = Counter equal to 0.
+ * |        |          |10 = Counter equal to PWM_CMPDATm, m denotes 1, 3, 5.
+ * |        |          |11 = SYNC_OUT will not be generated.
+ * |[16]    |SNFLTEN   |PWM_SYNC_IN Noise Filter Enable
+ * |        |          |0 = Noise filter of input pin PWM_SYNC_IN is Disabled.
+ * |        |          |1 = Noise filter of input pin PWM_SYNC_IN is Enabled.
+ * |[19:17] |SFLTCSEL  |SYNC Edge Detector Filter Clock Selection
+ * |        |          |000 = Filter clock = HCLK.
+ * |        |          |001 = Filter clock = HCLK/2.
+ * |        |          |010 = Filter clock = HCLK/4.
+ * |        |          |011 = Filter clock = HCLK/8.
+ * |        |          |100 = Filter clock = HCLK/16.
+ * |        |          |101 = Filter clock = HCLK/32.
+ * |        |          |110 = Filter clock = HCLK/64.
+ * |        |          |111 = Filter clock = HCLK/128.
+ * |[22:20] |SFLTCNT   |SYNC Edge Detector Filter Count
+ * |        |          |The register bits control the counter number of edge detector.
+ * |[23]    |SINPINV   |SYNC Input Pin Inverse
+ * |        |          |0 = The state of pin SYNC is passed to the negative edge detector.
+ * |        |          |1 = The inverted state of pin SYNC is passed to the negative edge detector.
+ * |[26:24] |PHSDIRn   |PWM Phase Direction Control
+ * |        |          |Each bit n controls corresponding PWM channel n.
+ * |        |          |0 = Control PWM counter count decrement after synchronizing.
+ * |        |          |1 = Control PWM counter count increment after synchronizing.
+ * @var PWM_T::SWSYNC
+ * Offset: 0x0C  PWM Software Control Synchronization Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[2:0]   |SWSYNCn   |Software SYNC Function
+ * |        |          |Each bit n controls corresponding PWM channel n.
+ * |        |          |When SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
+ * @var PWM_T::CLKSRC
+ * Offset: 0x10  PWM Clock Source Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[2:0]   |ECLKSRC0  |PWM_CH01 External Clock Source Select
+ * |        |          |000 = PWMx_CLK, x denotes 0 or 1.
+ * |        |          |001 = TIMER0 overflow.
+ * |        |          |010 = TIMER1 overflow.
+ * |        |          |011 = TIMER2 overflow.
+ * |        |          |100 = TIMER3 overflow.
+ * |        |          |Others = Reserved.
+ * |[10:8]  |ECLKSRC2  |PWM_CH23 External Clock Source Select
+ * |        |          |000 = PWMx_CLK, x denotes 0 or 1.
+ * |        |          |001 = TIMER0 overflow.
+ * |        |          |010 = TIMER1 overflow.
+ * |        |          |011 = TIMER2 overflow.
+ * |        |          |100 = TIMER3 overflow.
+ * |        |          |Others = Reserved.
+ * |[18:16] |ECLKSRC4  |PWM_CH45 External Clock Source Select
+ * |        |          |000 = PWMx_CLK, x denotes 0 or 1.
+ * |        |          |001 = TIMER0 overflow.
+ * |        |          |010 = TIMER1 overflow.
+ * |        |          |011 = TIMER2 overflow.
+ * |        |          |100 = TIMER3 overflow.
+ * |        |          |Others = Reserved.
+ * @var PWM_T::CLKPSC0_1
+ * Offset: 0x14  PWM Clock Pre-scale Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |CLKPSC    |PWM Counter Clock Pre-Scale
+ * |        |          |The clock of PWM counter is decided by clock prescaler.
+ * |        |          |Each PWM pair share one PWM counter clock prescaler.
+ * |        |          |The clock of PWM counter is divided by (CLKPSC+ 1).
+ * @var PWM_T::CLKPSC2_3
+ * Offset: 0x18  PWM Clock Pre-scale Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |CLKPSC    |PWM Counter Clock Pre-Scale
+ * |        |          |The clock of PWM counter is decided by clock prescaler.
+ * |        |          |Each PWM pair share one PWM counter clock prescaler.
+ * |        |          |The clock of PWM counter is divided by (CLKPSC+ 1).
+ * @var PWM_T::CLKPSC4_5
+ * Offset: 0x1C  PWM Clock Pre-scale Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |CLKPSC    |PWM Counter Clock Pre-Scale
+ * |        |          |The clock of PWM counter is decided by clock prescaler.
+ * |        |          |Each PWM pair share one PWM counter clock prescaler.
+ * |        |          |The clock of PWM counter is divided by (CLKPSC+ 1).
+ * @var PWM_T::CNTEN
+ * Offset: 0x20  PWM Counter Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |CNTENn    |PWM Counter Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = PWM Counter and clock prescaler Stop Running.
+ * |        |          |1 = PWM Counter and clock prescaler Start Running.
+ * @var PWM_T::CNTCLR
+ * Offset: 0x24  PWM Clear Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |CNTCLRn   |Clear PWM Counter Control Bit
+ * |        |          |It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = No effect.
+ * |        |          |1 = Clear 16-bit PWM counter to 0000H.
+ * @var PWM_T::LOAD
+ * Offset: 0x28  PWM Load Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |LOADn     |Re-Load PWM Comparator Register (CMPDAT) Control Bit
+ * |        |          |This bit is software write, hardware clear when current PWM period end.
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Set load window of window loading mode.
+ * |        |          |Read Operation:
+ * |        |          |0 = No load window is set.
+ * |        |          |1 = Load window is set.
+ * |        |          |Note: This bit only use in window loading mode, WINLDENn(PWM_CTL0[13:8]) = 1.
+ * @var PWM_T::PERIOD
+ * Offset: 0x30~0x44  PWM Period Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |PERIOD    |PWM Period Register
+ * |        |          |Up-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.
+ * |        |          |Down-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
+ * |        |          |PWM period time = (PERIOD+1) * PWM_CLK period.
+ * |        |          |Up-Down-Count mode: In this mode, PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
+ * |        |          |PWM period time = 2 * PERIOD * PWM_CLK period.
+ * @var PWM_T::CMPDAT
+ * Offset: 0x50~0x64  PWM Comparator Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |CMP       |PWM Comparator Register
+ * |        |          |CMP use to compare with CNTR to generate PWM waveform, interrupt and trigger EADC/DAC.
+ * |        |          |In independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.
+ * |        |          |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
+ * @var PWM_T::DTCTL0_1
+ * Offset: 0x70  PWM Dead-Time Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |DTCNT     |Dead-Time Counter (Write Protect)
+ * |        |          |The dead-time can be calculated from the following formula:
+ * |        |          |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[16]    |DTEN      |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
+ * |        |          |Dead-time insertion is only active when this pair of complementary PWM is enabled.
+ * |        |          |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
+ * |        |          |0 = Dead-time insertion Disabled on the pin pair.
+ * |        |          |1 = Dead-time insertion Enabled on the pin pair.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[24]    |DTCKSEL   |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
+ * |        |          |0 = Dead-time clock source from PWM_CLK.
+ * |        |          |1 = Dead-time clock source from prescaler output.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::DTCTL2_3
+ * Offset: 0x74  PWM Dead-Time Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |DTCNT     |Dead-Time Counter (Write Protect)
+ * |        |          |The dead-time can be calculated from the following formula:
+ * |        |          |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[16]    |DTEN      |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
+ * |        |          |Dead-time insertion is only active when this pair of complementary PWM is enabled.
+ * |        |          |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
+ * |        |          |0 = Dead-time insertion Disabled on the pin pair.
+ * |        |          |1 = Dead-time insertion Enabled on the pin pair.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[24]    |DTCKSEL   |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
+ * |        |          |0 = Dead-time clock source from PWM_CLK.
+ * |        |          |1 = Dead-time clock source from prescaler output.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::DTCTL4_5
+ * Offset: 0x78  PWM Dead-Time Control Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |DTCNT     |Dead-Time Counter (Write Protect)
+ * |        |          |The dead-time can be calculated from the following formula:
+ * |        |          |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[16]    |DTEN      |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
+ * |        |          |Dead-time insertion is only active when this pair of complementary PWM is enabled.
+ * |        |          |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
+ * |        |          |0 = Dead-time insertion Disabled on the pin pair.
+ * |        |          |1 = Dead-time insertion Enabled on the pin pair.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[24]    |DTCKSEL   |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
+ * |        |          |0 = Dead-time clock source from PWM_CLK.
+ * |        |          |1 = Dead-time clock source from prescaler output.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::PHS0_1
+ * Offset: 0x80  PWM Counter Phase Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |PHS       |PWM Synchronous Start Phase Bits
+ * |        |          |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
+ * @var PWM_T::PHS2_3
+ * Offset: 0x84  PWM Counter Phase Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |PHS       |PWM Synchronous Start Phase Bits
+ * |        |          |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
+ * @var PWM_T::PHS4_5
+ * Offset: 0x88  PWM Counter Phase Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |PHS       |PWM Synchronous Start Phase Bits
+ * |        |          |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
+ * @var PWM_T::CNT
+ * Offset: 0x90~0xA4  PWM Counter Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |CNT       |PWM Data Register (Read Only)
+ * |        |          |User can monitor CNTR to know the current value in 16-bit period counter.
+ * |[16]    |DIRF      |PWM Direction Indicator Flag (Read Only)
+ * |        |          |0 = Counter is Down count.
+ * |        |          |1 = Counter is UP count.
+ * @var PWM_T::WGCTL0
+ * Offset: 0xB0  PWM Generation Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |ZPCTLn    |PWM Zero Point Control
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |00 = Do nothing.
+ * |        |          |01 = PWM zero point output Low.
+ * |        |          |10 = PWM zero point output High.
+ * |        |          |11 = PWM zero point output Toggle.
+ * |        |          |PWM can control output level when PWM counter count to zero.
+ * |[27:16] |PRDPCTLn  |PWM Period (Center) Point Control
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |00 = Do nothing.
+ * |        |          |01 = PWM period (center) point output Low.
+ * |        |          |10 = PWM period (center) point output High.
+ * |        |          |11 = PWM period (center) point output Toggle.
+ * |        |          |PWM can control output level when PWM counter count to (PERIODn+1).
+ * |        |          |Note: This bit is center point control when PWM counter operating in up-down counter type.
+ * @var PWM_T::WGCTL1
+ * Offset: 0xB4  PWM Generation Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |CMPUCTLn  |PWM Compare Up Point Control
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |00 = Do nothing.
+ * |        |          |01 = PWM compare up point output Low.
+ * |        |          |10 = PWM compare up point output High.
+ * |        |          |11 = PWM compare up point output Toggle.
+ * |        |          |PWM can control output level when PWM counter up count to CMPDAT.
+ * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+ * |[27:16] |CMPDCTLn  |PWM Compare Down Point Control
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |00 = Do nothing.
+ * |        |          |01 = PWM compare down point output Low.
+ * |        |          |10 = PWM compare down point output High.
+ * |        |          |11 = PWM compare down point output Toggle.
+ * |        |          |PWM can control output level when PWM counter down count to CMPDAT.
+ * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+ * @var PWM_T::MSKEN
+ * Offset: 0xB8  PWM Mask Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |MSKENn    |PWM Mask Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |The PWM output signal will be masked when this bit is enabled.
+ * |        |          |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
+ * |        |          |0 = PWM output signal is non-masked.
+ * |        |          |1 = PWM output signal is masked and output MSKDATn data.
+ * @var PWM_T::MSK
+ * Offset: 0xBC  PWM Mask Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |MSKDATn   |PWM Mask Data Bit
+ * |        |          |This data bit control the state of PWMn output pin, if corresponding mask function is enabled.
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Output logic low to PWMn.
+ * |        |          |1 = Output logic high to PWMn.
+ * @var PWM_T::BNF
+ * Offset: 0xC0  PWM Brake Noise Filter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |BRK0NFEN  |PWM Brake 0 Noise Filter Enable
+ * |        |          |0 = Noise filter of PWM Brake 0 Disabled.
+ * |        |          |1 = Noise filter of PWM Brake 0 Enabled.
+ * |[3:1]   |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection
+ * |        |          |000 = Filter clock = HCLK.
+ * |        |          |001 = Filter clock = HCLK/2.
+ * |        |          |010 = Filter clock = HCLK/4.
+ * |        |          |011 = Filter clock = HCLK/8.
+ * |        |          |100 = Filter clock = HCLK/16.
+ * |        |          |101 = Filter clock = HCLK/32.
+ * |        |          |110 = Filter clock = HCLK/64.
+ * |        |          |111 = Filter clock = HCLK/128.
+ * |[6:4]   |BRK0FCNT  |Brake 0 Edge Detector Filter Count
+ * |        |          |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
+ * |[7]     |BRK0PINV  |Brake 0 Pin Inverse
+ * |        |          |0 = The state of pin PWMx_BRAKE0 is passed to the negative edge detector.
+ * |        |          |1 = The inverted state of pin PWMx_BRAKE10 is passed to the negative edge detector.
+ * |[8]     |BRK1NFEN  |PWM Brake 1 Noise Filter Enable
+ * |        |          |0 = Noise filter of PWM Brake 1 Disabled.
+ * |        |          |1 = Noise filter of PWM Brake 1 Enabled.
+ * |[11:9]  |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection
+ * |        |          |000 = Filter clock = HCLK.
+ * |        |          |001 = Filter clock = HCLK/2.
+ * |        |          |010 = Filter clock = HCLK/4.
+ * |        |          |011 = Filter clock = HCLK/8.
+ * |        |          |100 = Filter clock = HCLK/16.
+ * |        |          |101 = Filter clock = HCLK/32.
+ * |        |          |110 = Filter clock = HCLK/64.
+ * |        |          |111 = Filter clock = HCLK/128.
+ * |[14:12] |BRK1FCNT  |Brake 1 Edge Detector Filter Count
+ * |        |          |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
+ * |[15]    |BRK1PINV  |Brake 1 Pin Inverse
+ * |        |          |0 = The state of pin PWMx_BRAKE1 is passed to the negative edge detector.
+ * |        |          |1 = The inverted state of pin PWMx_BRAKE1 is passed to the negative edge detector.
+ * |[16]    |BK0SRC    |Brake 0 Pin Source Select (M45xD/M45xC Only)
+ * |        |          |For PWM0 setting:
+ * |        |          |0 = Brake 0 pin source come from PWM0_BRAKE0.
+ * |        |          |1 = Brake 0 pin source come from PWM1_BRAKE0.
+ * |        |          |For PWM1 setting:
+ * |        |          |0 = Brake 0 pin source come from PWM1_BRAKE0.
+ * |        |          |1 = Brake 0 pin source come from PWM0_BRAKE0.
+ * |[24]    |BK1SRC    |Brake 1 Pin Source Select (M45xD/M45xC Only)
+ * |        |          |For PWM0 setting:
+ * |        |          |0 = Brake 1 pin source come from PWM0_BRAKE1.
+ * |        |          |1 = Brake 1 pin source come from PWM1_BRAKE1.
+ * |        |          |For PWM1 setting:
+ * |        |          |0 = Brake 1 pin source come from PWM1_BRAKE1.
+ * |        |          |1 = Brake 1 pin source come from PWM0_BRAKE1.
+ * @var PWM_T::FAILBRK
+ * Offset: 0xC4  PWM System Fail Brake Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |CSSBRKEN  |Clock Security System Detection Trigger PWM Brake Function 0 Enable
+ * |        |          |0 = Brake Function triggered by CSS detection Disabled.
+ * |        |          |1 = Brake Function triggered by CSS detection Enabled.
+ * |[1]     |BODBRKEN  |Brown-Out Detection Trigger PWM Brake Function 0 Enable
+ * |        |          |0 = Brake Function triggered by BOD Disabled.
+ * |        |          |1 = Brake Function triggered by BOD Enabled.
+ * |[2]     |RAMBRKEN  |SRAM Parity Error Detection Trigger PWM Brake Function 0 Enable
+ * |        |          |0 = Brake Function triggered by SRAM parity error detection Disabled.
+ * |        |          |1 = Brake Function triggered by SRAM parity error detection Enabled.
+ * |[3]     |CORBRKEN  |Core Lockup Detection Trigger PWM Brake Function 0 Enable
+ * |        |          |0 = Brake Function triggered by Core lockup detection Disabled.
+ * |        |          |1 = Brake Function triggered by Core lockup detection Enabled.
+ * @var PWM_T::BRKCTL0_1
+ * Offset: 0xC8  PWM Brake Edge Detect Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |CPO0EBEN  |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = ACMP0_O as edge-detect brake source Disabled.
+ * |        |          |1 = ACMP0_O as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[1]     |CPO1EBEN  |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = ACMP1_O as edge-detect brake source Disabled.
+ * |        |          |1 = ACMP1_O as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[4]     |BRKP0EEN  |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = BKP0 pin as edge-detect brake source Disabled.
+ * |        |          |1 = BKP0 pin as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[5]     |BRKP1EEN  |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = BKP1 pin as edge-detect brake source Disabled.
+ * |        |          |1 = BKP1 pin as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[7]     |SYSEBEN   |Enable System Fail As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = System Fail condition as edge-detect brake source Disabled.
+ * |        |          |1 = System Fail condition as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[8]     |CPO0LBEN  |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = ACMP0_O as level-detect brake source Disabled.
+ * |        |          |1 = ACMP0_O as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[9]     |CPO1LBEN  |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = ACMP1_O as level-detect brake source Disabled.
+ * |        |          |1 = ACMP1_O as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[12]    |BRKP0LEN  |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
+ * |        |          |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[13]    |BRKP1LEN  |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
+ * |        |          |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[15]    |SYSLBEN   |Enable System Fail As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = System Fail condition as level-detect brake source Disabled.
+ * |        |          |1 = System Fail condition as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[17:16] |BRKAEVEN  |PWM Brake Action Select For Even Channel (Write Protect)
+ * |        |          |00 = PWM even channel level-detect brake function not affect channel output.
+ * |        |          |01 = PWM even channel output tri-state when level-detect brake happened.
+ * |        |          |10 = PWM even channel output low level when level-detect brake happened.
+ * |        |          |11 = PWM even channel output high level when level-detect brake happened.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[19:18] |BRKAODD   |PWM Brake Action Select For Odd Channel (Write Protect)
+ * |        |          |00 = PWM odd channel level-detect brake function not affect channel output.
+ * |        |          |01 = PWM odd channel output tri-state when level-detect brake happened.
+ * |        |          |10 = PWM odd channel output low level when level-detect brake happened.
+ * |        |          |11 = PWM odd channel output high level when level-detect brake happened.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::BRKCTL2_3
+ * Offset: 0xCC  PWM Brake Edge Detect Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |CPO0EBEN  |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = ACMP0_O as edge-detect brake source Disabled.
+ * |        |          |1 = ACMP0_O as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[1]     |CPO1EBEN  |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = ACMP1_O as edge-detect brake source Disabled.
+ * |        |          |1 = ACMP1_O as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[4]     |BRKP0EEN  |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = BKP0 pin as edge-detect brake source Disabled.
+ * |        |          |1 = BKP0 pin as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[5]     |BRKP1EEN  |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = BKP1 pin as edge-detect brake source Disabled.
+ * |        |          |1 = BKP1 pin as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[7]     |SYSEBEN   |Enable System Fail As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = System Fail condition as edge-detect brake source Disabled.
+ * |        |          |1 = System Fail condition as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[8]     |CPO0LBEN  |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = ACMP0_O as level-detect brake source Disabled.
+ * |        |          |1 = ACMP0_O as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[9]     |CPO1LBEN  |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = ACMP1_O as level-detect brake source Disabled.
+ * |        |          |1 = ACMP1_O as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[12]    |BRKP0LEN  |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
+ * |        |          |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[13]    |BRKP1LEN  |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
+ * |        |          |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[15]    |SYSLBEN   |Enable System Fail As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = System Fail condition as level-detect brake source Disabled.
+ * |        |          |1 = System Fail condition as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[17:16] |BRKAEVEN  |PWM Brake Action Select For Even Channel (Write Protect)
+ * |        |          |00 = PWM even channel level-detect brake function not affect channel output.
+ * |        |          |01 = PWM even channel output tri-state when level-detect brake happened.
+ * |        |          |10 = PWM even channel output low level when level-detect brake happened.
+ * |        |          |11 = PWM even channel output high level when level-detect brake happened.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[19:18] |BRKAODD   |PWM Brake Action Select For Odd Channel (Write Protect)
+ * |        |          |00 = PWM odd channel level-detect brake function not affect channel output.
+ * |        |          |01 = PWM odd channel output tri-state when level-detect brake happened.
+ * |        |          |10 = PWM odd channel output low level when level-detect brake happened.
+ * |        |          |11 = PWM odd channel output high level when level-detect brake happened.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::BRKCTL4_5
+ * Offset: 0xD0  PWM Brake Edge Detect Control Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |CPO0EBEN  |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = ACMP0_O as edge-detect brake source Disabled.
+ * |        |          |1 = ACMP0_O as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[1]     |CPO1EBEN  |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = ACMP1_O as edge-detect brake source Disabled.
+ * |        |          |1 = ACMP1_O as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[4]     |BRKP0EEN  |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = BKP0 pin as edge-detect brake source Disabled.
+ * |        |          |1 = BKP0 pin as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[5]     |BRKP1EEN  |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = BKP1 pin as edge-detect brake source Disabled.
+ * |        |          |1 = BKP1 pin as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[7]     |SYSEBEN   |Enable System Fail As Edge-Detect Brake Source (Write Protect)
+ * |        |          |0 = System Fail condition as edge-detect brake source Disabled.
+ * |        |          |1 = System Fail condition as edge-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[8]     |CPO0LBEN  |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = ACMP0_O as level-detect brake source Disabled.
+ * |        |          |1 = ACMP0_O as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[9]     |CPO1LBEN  |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = ACMP1_O as level-detect brake source Disabled.
+ * |        |          |1 = ACMP1_O as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[12]    |BRKP0LEN  |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
+ * |        |          |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[13]    |BRKP1LEN  |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
+ * |        |          |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[15]    |SYSLBEN   |Enable System Fail As Level-Detect Brake Source (Write Protect)
+ * |        |          |0 = System Fail condition as level-detect brake source Disabled.
+ * |        |          |1 = System Fail condition as level-detect brake source Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[17:16] |BRKAEVEN  |PWM Brake Action Select For Even Channel (Write Protect)
+ * |        |          |00 = PWM even channel level-detect brake function not affect channel output.
+ * |        |          |01 = PWM even channel output tri-state when level-detect brake happened.
+ * |        |          |10 = PWM even channel output low level when level-detect brake happened.
+ * |        |          |11 = PWM even channel output high level when level-detect brake happened.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[19:18] |BRKAODD   |PWM Brake Action Select For Odd Channel (Write Protect)
+ * |        |          |00 = PWM odd channel level-detect brake function not affect channel output.
+ * |        |          |01 = PWM odd channel output tri-state when level-detect brake happened.
+ * |        |          |10 = PWM odd channel output low level when level-detect brake happened.
+ * |        |          |11 = PWM odd channel output high level when level-detect brake happened.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::POLCTL
+ * Offset: 0xD4  PWM Pin Polar Inverse Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |PINVn     |PWM PIN Polar Inverse Control
+ * |        |          |The register controls polarity state of PWM output.
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = PWM output polar inverse Disabled.
+ * |        |          |1 = PWM output polar inverse Enabled.
+ * @var PWM_T::POEN
+ * Offset: 0xD8  PWM Output Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |POENn     |PWM Pin Output Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = PWM pin at tri-state.
+ * |        |          |1 = PWM pin in output mode.
+ * @var PWM_T::SWBRK
+ * Offset: 0xDC  PWM Software Brake Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[2:0]   |BRKETRGn  |PWM Edge Brake Software Trigger (Write Only) (Write Protect) (M45xD/M45xC Only)
+ * |        |          |Each bit n controls the corresponding PWM pair n.
+ * |        |          |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[10:8]  |BRKLTRGn  |PWM Level Brake Software Trigger (Write Only) (Write Protect)
+ * |        |          |Each bit n controls the corresponding PWM pair n.
+ * |        |          |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::INTEN0
+ * Offset: 0xE0  PWM Interrupt Enable Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |ZIENn     |PWM Zero Point Interrupt Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Zero point interrupt Disabled.
+ * |        |          |1 = Zero point interrupt Enabled.
+ * |        |          |Note: Odd channels will read always 0 at complementary mode.
+ * |[7]     |IFAIEN0_1 |PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable
+ * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+ * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+ * |[13:8]  |PIENn     |PWM Period Point Interrupt Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Period point interrupt Disabled.
+ * |        |          |1 = Period point interrupt Enabled.
+ * |        |          |Note1: When up-down counter type period point means center point.
+ * |        |          |Note2: Odd channels will read always 0 at complementary mode.
+ * |[15]    |IFAIEN2_3 |PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable
+ * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+ * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+ * |[21:16] |CMPUIENn  |PWM Compare Up Count Interrupt Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Compare up count interrupt Disabled.
+ * |        |          |1 = Compare up count interrupt Enabled.
+ * |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+ * |[23]    |IFAIEN4_5 |PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable
+ * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+ * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+ * |[29:24] |CMPDIENn  |PWM Compare Down Count Interrupt Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Compare down count interrupt Disabled.
+ * |        |          |1 = Compare down count interrupt Enabled.
+ * |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+ * @var PWM_T::INTEN1
+ * Offset: 0xE4  PWM Interrupt Enable Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |BRKEIEN0_1|PWM Edge-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
+ * |        |          |0 = Edge-detect Brake interrupt for channel0/1 Disabled.
+ * |        |          |1 = Edge-detect Brake interrupt for channel0/1 Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[1]     |BRKEIEN2_3|PWM Edge-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
+ * |        |          |0 = Edge-detect Brake interrupt for channel2/3 Disabled.
+ * |        |          |1 = Edge-detect Brake interrupt for channel2/3 Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[2]     |BRKEIEN4_5|PWM Edge-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
+ * |        |          |0 = Edge-detect Brake interrupt for channel4/5 Disabled.
+ * |        |          |1 = Edge-detect Brake interrupt for channel4/5 Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[8]     |BRKLIEN0_1|PWM Level-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
+ * |        |          |0 = Level-detect Brake interrupt for channel0/1 Disabled.
+ * |        |          |1 = Level-detect Brake interrupt for channel0/1 Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[9]     |BRKLIEN2_3|PWM Level-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
+ * |        |          |0 = Level-detect Brake interrupt for channel2/3 Disabled.
+ * |        |          |1 = Level-detect Brake interrupt for channel2/3 Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[10]    |BRKLIEN4_5|PWM Level-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
+ * |        |          |0 = Level-detect Brake interrupt for channel4/5 Disabled.
+ * |        |          |1 = Level-detect Brake interrupt for channel4/5 Enabled.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::INTSTS0
+ * Offset: 0xE8  PWM Interrupt Flag Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |ZIFn      |PWM Zero Point Interrupt Flag
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
+ * |[7]     |IFAIF0_1  |PWM_CH0/1 Interrupt Flag Accumulator Interrupt Flag
+ * |        |          |Flag is set by hardware when condition match IFSEL0_1 in PWM_IFA register, software can clear this bit by writing 1 to it.
+ * |[13:8]  |PIFn      |PWM Period Point Interrupt Flag
+ * |        |          |This bit is set by hardware when PWM counter reaches PWM_PERIODn, software can write 1 to clear this bit to zero.
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |[15]    |IFAIF2_3  |PWM_CH2/3 Interrupt Flag Accumulator Interrupt Flag
+ * |        |          |Flag is set by hardware when condition match IFSEL2_3 in PWM_IFA register, software can clear this bit by writing 1 to it.
+ * |[21:16] |CMPUIFn   |PWM Compare Up Count Interrupt Flag
+ * |        |          |Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * |        |          |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+ * |[23]    |IFAIF4_5  |PWM_CH4/5 Interrupt Flag Accumulator Interrupt Flag
+ * |        |          |Flag is set by hardware when condition match IFSEL4_5 in PWM_IFA register, software can clear this bit by writing 1 to it.
+ * |[29:24] |CMPDIFn   |PWM Compare Down Count Interrupt Flag
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * |        |          |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+ * @var PWM_T::INTSTS1
+ * Offset: 0xEC  PWM Interrupt Flag Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |BRKEIF0   |PWM Channel0 Edge-Detect Brake Interrupt Flag (Write Protect)
+ * |        |          |0 = PWM channel0 edge-detect brake event do not happened.
+ * |        |          |1 = When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[1]     |BRKEIF1   |PWM Channel1 Edge-Detect Brake Interrupt Flag (Write Protect)
+ * |        |          |0 = PWM channel1 edge-detect brake event do not happened.
+ * |        |          |1 = When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[2]     |BRKEIF2   |PWM Channel2 Edge-Detect Brake Interrupt Flag (Write Protect)
+ * |        |          |0 = PWM channel2 edge-detect brake event do not happened.
+ * |        |          |1 = When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[3]     |BRKEIF3   |PWM Channel3 Edge-Detect Brake Interrupt Flag (Write Protect)
+ * |        |          |0 = PWM channel3 edge-detect brake event do not happened.
+ * |        |          |1 = When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[4]     |BRKEIF4   |PWM Channel4 Edge-Detect Brake Interrupt Flag (Write Protect)
+ * |        |          |0 = PWM channel4 edge-detect brake event do not happened.
+ * |        |          |1 = When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[5]     |BRKEIF5   |PWM Channel5 Edge-Detect Brake Interrupt Flag (Write Protect)
+ * |        |          |0 = PWM channel5 edge-detect brake event do not happened.
+ * |        |          |1 = When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[8]     |BRKLIF0   |PWM Channel0 Level-Detect Brake Interrupt Flag (Write Protect)
+ * |        |          |0 = PWM channel0 level-detect brake event do not happened.
+ * |        |          |1 = When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[9]     |BRKLIF1   |PWM Channel1 Level-Detect Brake Interrupt Flag (Write Protect)
+ * |        |          |0 = PWM channel1 level-detect brake event do not happened.
+ * |        |          |1 = When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[10]    |BRKLIF2   |PWM Channel2 Level-Detect Brake Interrupt Flag (Write Protect)
+ * |        |          |0 = PWM channel2 level-detect brake event do not happened.
+ * |        |          |1 = When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[11]    |BRKLIF3   |PWM Channel3 Level-Detect Brake Interrupt Flag (Write Protect)
+ * |        |          |0 = PWM channel3 level-detect brake event do not happened.
+ * |        |          |1 = When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[12]    |BRKLIF4   |PWM Channel4 Level-Detect Brake Interrupt Flag (Write Protect)
+ * |        |          |0 = PWM channel4 level-detect brake event do not happened.
+ * |        |          |1 = When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[13]    |BRKLIF5   |PWM Channel5 Level-Detect Brake Interrupt Flag (Write Protect)
+ * |        |          |0 = PWM channel5 level-detect brake event do not happened.
+ * |        |          |1 = When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[16]    |BRKESTS0  |PWM Channel0 Edge-Detect Brake Status
+ * |        |          |0 = PWM channel0 edge-detect brake state is released.
+ * |        |          |1 = When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state, writing 1 to clear.
+ * |[17]    |BRKESTS1  |PWM Channel1 Edge-Detect Brake Status
+ * |        |          |0 = PWM channel1 edge-detect brake state is released.
+ * |        |          |1 = When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state, writing 1 to clear.
+ * |[18]    |BRKESTS2  |PWM Channel2 Edge-Detect Brake Status
+ * |        |          |0 = PWM channel2 edge-detect brake state is released.
+ * |        |          |1 = When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state, writing 1 to clear.
+ * |[19]    |BRKESTS3  |PWM Channel3 Edge-Detect Brake Status
+ * |        |          |0 = PWM channel3 edge-detect brake state is released.
+ * |        |          |1 = When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state, writing 1 to clear.
+ * |[20]    |BRKESTS4  |PWM Channel4 Edge-Detect Brake Status
+ * |        |          |0 = PWM channel4 edge-detect brake state is released.
+ * |        |          |1 = When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state, writing 1 to clear.
+ * |[21]    |BRKESTS5  |PWM Channel5 Edge-Detect Brake Status
+ * |        |          |0 = PWM channel5 edge-detect brake state is released.
+ * |        |          |1 = When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state, writing 1 to clear.
+ * |[24]    |BRKLSTS0  |PWM Channel0 Level-Detect Brake Status (Read Only)
+ * |        |          |0 = PWM channel0 level-detect brake state is released.
+ * |        |          |1 = When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state.
+ * |        |          |Note: This bit is read only and auto cleared by hardware.
+ * |        |          |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
+ * |        |          |The PWM waveform will start output from next full PWM period.
+ * |[25]    |BRKLSTS1  |PWM Channel1 Level-Detect Brake Status (Read Only)
+ * |        |          |0 = PWM channel1 level-detect brake state is released.
+ * |        |          |1 = When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state.
+ * |        |          |Note: This bit is read only and auto cleared by hardware.
+ * |        |          |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
+ * |        |          |The PWM waveform will start output from next full PWM period.
+ * |[26]    |BRKLSTS2  |PWM Channel2 Level-Detect Brake Status (Read Only)
+ * |        |          |0 = PWM channel2 level-detect brake state is released.
+ * |        |          |1 = When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state.
+ * |        |          |Note: This bit is read only and auto cleared by hardware.
+ * |        |          |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
+ * |        |          |The PWM waveform will start output from next full PWM period.
+ * |[27]    |BRKLSTS3  |PWM Channel3 Level-Detect Brake Status (Read Only)
+ * |        |          |0 = PWM channel3 level-detect brake state is released.
+ * |        |          |1 = When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state.
+ * |        |          |Note: This bit is read only and auto cleared by hardware.
+ * |        |          |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
+ * |        |          |The PWM waveform will start output from next full PWM period.
+ * |[28]    |BRKLSTS4  |PWM Channel4 Level-Detect Brake Status (Read Only)
+ * |        |          |0 = PWM channel4 level-detect brake state is released.
+ * |        |          |1 = When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state.
+ * |        |          |Note: This bit is read only and auto cleared by hardware.
+ * |        |          |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
+ * |        |          |The PWM waveform will start output from next full PWM period.
+ * |[29]    |BRKLSTS5  |PWM Channel5 Level-Detect Brake Status (Read Only)
+ * |        |          |0 = PWM channel5 level-detect brake state is released.
+ * |        |          |1 = When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state.
+ * |        |          |Note: This bit is read only and auto cleared by hardware.
+ * |        |          |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
+ * |        |          |The PWM waveform will start output from next full PWM period.
+ * @var PWM_T::IFA
+ * Offset: 0xF0  PWM Interrupt Flag Accumulator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |IFCNT0_1  |PWM_CH0 And PWM_CH1 Interrupt Flag Counter
+ * |        |          |The register sets the count number which defines how many times of PWM_CH0 and PWM_CH1 period occurs to set bit IFAIF0_1 to request the PWM period interrupt.
+ * |        |          |PWM flag will be set in every IFCNT0_1 [3:0] times of PWM period.
+ * |[6:4]   |IFSEL0_1  |PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Source Select
+ * |        |          |000 = CNT equal to Zero in channel 0.
+ * |        |          |001 = CNT equal to PERIOD in channel 0.
+ * |        |          |010 = CNT equal to CMPU in channel 0.
+ * |        |          |011 = CNT equal to CMPD in channel 0.
+ * |        |          |100 = CNT equal to Zero in channel 1.
+ * |        |          |101 = CNT equal to PERIOD in channel 1.
+ * |        |          |110 = CNT equal to CMPU in channel 1.
+ * |        |          |111 = CNT equal to CMPD in channel 1.
+ * |[7]     |IFAEN0_1  |PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Enable
+ * |        |          |0 = PWM_CH0 and PWM_CH1 interrupt flag accumulator disable.
+ * |        |          |1 = PWM_CH0 and PWM_CH1 interrupt flag accumulator enable.
+ * |[11:8]  |IFCNT2_3  |PWM_CH2 And PWM_CH3 Interrupt Flag Counter
+ * |        |          |The register sets the count number which defines how many times of PWM_CH2 and PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt.
+ * |        |          |PWM flag will be set in every IFCNT2_3[3:0] times of PWM period.
+ * |[14:12] |IFSEL2_3  |PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Source Select
+ * |        |          |000 = CNT equal to Zero in channel 2.
+ * |        |          |001 = CNT equal to PERIOD in channel 2.
+ * |        |          |010 = CNT equal to CMPU in channel 2.
+ * |        |          |011 = CNT equal to CMPD in channel 2.
+ * |        |          |100 = CNT equal to Zero in channel 3.
+ * |        |          |101 = CNT equal to PERIOD in channel 3.
+ * |        |          |110 = CNT equal to CMPU in channel 3.
+ * |        |          |111 = CNT equal to CMPD in channel 3.
+ * |[15]    |IFAEN2_3  |PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Enable
+ * |        |          |0 = PWM_CH2 and PWM_CH3 interrupt flag accumulator disable.
+ * |        |          |1 = PWM_CH2 and PWM_CH3 interrupt flag accumulator enable.
+ * |[19:16] |IFCNT4_5  |PWM_CH4 And PWM_CH5 Interrupt Flag Counter
+ * |        |          |The register sets the count number which defines how many times of PWM_CH4 and PWM_CH5 period occurs to set bit IFAIF4_5 to request the PWM period interrupt.
+ * |        |          |PWM flag will be set in every IFCNT4_5[3:0] times of PWM period.
+ * |[22:20] |IFSEL4_5  |PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Source Select
+ * |        |          |000 = CNT equal to Zero in channel 4.
+ * |        |          |001 = CNT equal to PERIOD in channel 4.
+ * |        |          |010 = CNT equal to CMPU in channel 4.
+ * |        |          |011 = CNT equal to CMPD in channel 4.
+ * |        |          |100 = CNT equal to Zero in channel 5.
+ * |        |          |101 = CNT equal to PERIOD in channel 5.
+ * |        |          |110 = CNT equal to CMPU in channel 5.
+ * |        |          |111 = CNT equal to CMPD in channel 5.
+ * |[23]    |IFAEN4_5  |PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Enable
+ * |        |          |0 = PWM_CH4 and PWM_CH5 interrupt flag accumulator disable.
+ * |        |          |1 = PWM_CH4 and PWM_CH5 interrupt flag accumulator enable.
+ * @var PWM_T::DACTRGEN
+ * Offset: 0xF4  PWM Trigger DAC Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |ZTEn      |PWM Zero Point Trigger DAC Enable
+ * |        |          |0 = PWM period point trigger DAC function Disabled.
+ * |        |          |1 = PWM period point trigger DAC function Enabled.
+ * |        |          |PWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to 1.
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |[13:8]  |PTEn      |PWM Period Point Trigger DAC Enable
+ * |        |          |0 = PWM period point trigger DAC function Disabled.
+ * |        |          |1 = PWM period point trigger DAC function Enabled.
+ * |        |          |PWM can trigger DAC to start action when PWM counter up count to (PERIODn+1) if this bit is set to 1.
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |[21:16] |CUTRGEn   |PWM Compare Up Count Point Trigger DAC Enable
+ * |        |          |0 = PWM Compare Up point trigger DAC function Disabled.
+ * |        |          |1 = PWM Compare Up point trigger DAC function Enabled.
+ * |        |          |PWM can trigger DAC to start action when PWM counter up count to CMPDAT if this bit is set to 1.
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |Note1: This bit should keep at 0 when PWM counter operating in down counter type.
+ * |        |          |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+ * |[29:24] |CDTRGEn   |PWM Compare Down Count Point Trigger DAC Enable
+ * |        |          |0 = PWM Compare Down count point trigger DAC function Disabled.
+ * |        |          |1 = PWM Compare Down count point trigger DAC function Enabled.
+ * |        |          |PWM can trigger DAC to start action when PWM counter down count to CMPDAT if this bit is set to 1.
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |Note1: This bit should keep at 0 when PWM counter operating in up counter type.
+ * |        |          |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+ * @var PWM_T::EADCTS0
+ * Offset: 0xF8  PWM Trigger EADC Source Select Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |TRGSEL0   |PWM_CH0 Trigger EADC Source Select
+ * |        |          |0000 = PWM_CH0 zero point.
+ * |        |          |0001 = PWM_CH0 period point.
+ * |        |          |0010 = PWM_CH0 zero or period point.
+ * |        |          |0011 = PWM_CH0 up-count CMPDAT point.
+ * |        |          |0100 = PWM_CH0 down-count CMPDAT point.
+ * |        |          |0101 = PWM_CH1 zero point.
+ * |        |          |0110 = PWM_CH1 period point.
+ * |        |          |0111 = PWM_CH1 zero or period point.
+ * |        |          |1000 = PWM_CH1 up-count CMPDAT point.
+ * |        |          |1001 = PWM_CH1 down-count CMPDAT point.
+ * |        |          |1010 = PWM_CH0 up-count free CMPDAT point.
+ * |        |          |1011 = PWM_CH0 down-count free CMPDAT point.
+ * |        |          |1100 = PWM_CH2 up-count free CMPDAT point.
+ * |        |          |1101 = PWM_CH2 down-count free CMPDAT point.
+ * |        |          |1110 = PWM_CH4 up-count free CMPDAT point.
+ * |        |          |1111 = PWM_CH4 down-count free CMPDAT point.
+ * |[7]     |TRGEN0    |PWM_CH0 Trigger EADC enable bit
+ * |[11:8]  |TRGSEL1   |PWM_CH1 Trigger EADC Source Select
+ * |        |          |0000 = PWM_CH0 zero point.
+ * |        |          |0001 = PWM_CH0 period point.
+ * |        |          |0010 = PWM_CH0 zero or period point.
+ * |        |          |0011 = PWM_CH0 up-count CMPDAT point.
+ * |        |          |0100 = PWM_CH0 down-count CMPDAT point.
+ * |        |          |0101 = PWM_CH1 zero point.
+ * |        |          |0110 = PWM_CH1 period point.
+ * |        |          |0111 = PWM_CH1 zero or period point.
+ * |        |          |1000 = PWM_CH1 up-count CMPDAT point.
+ * |        |          |1001 = PWM_CH1 down-count CMPDAT point.
+ * |        |          |1010 = PWM_CH0 up-count free CMPDAT point.
+ * |        |          |1011 = PWM_CH0 down-count free CMPDAT point.
+ * |        |          |1100 = PWM_CH2 up-count free CMPDAT point.
+ * |        |          |1101 = PWM_CH2 down-count free CMPDAT point.
+ * |        |          |1110 = PWM_CH4 up-count free CMPDAT point.
+ * |        |          |1111 = PWM_CH4 down-count free CMPDAT point.
+ * |[15]    |TRGEN1    |PWM_CH1 Trigger EADC enable bit
+ * |[19:16] |TRGSEL2   |PWM_CH2 Trigger EADC Source Select
+ * |        |          |0000 = PWM_CH2 zero point.
+ * |        |          |0001 = PWM_CH2 period point.
+ * |        |          |0010 = PWM_CH2 zero or period point.
+ * |        |          |0011 = PWM_CH2 up-count CMPDAT point.
+ * |        |          |0100 = PWM_CH2 down-count CMPDAT point.
+ * |        |          |0101 = PWM_CH3 zero point.
+ * |        |          |0110 = PWM_CH3 period point.
+ * |        |          |0111 = PWM_CH3 zero or period point.
+ * |        |          |1000 = PWM_CH3 up-count CMPDAT point.
+ * |        |          |1001 = PWM_CH3 down-count CMPDAT point.
+ * |        |          |1010 = PWM_CH0 up-count free CMPDAT point.
+ * |        |          |1011 = PWM_CH0 down-count free CMPDAT point.
+ * |        |          |1100 = PWM_CH2 up-count free CMPDAT point.
+ * |        |          |1101 = PWM_CH2 down-count free CMPDAT point.
+ * |        |          |1110 = PWM_CH4 up-count free CMPDAT point.
+ * |        |          |1111 = PWM_CH4 down-count free CMPDAT point.
+ * |[23]    |TRGEN2    |PWM_CH2 Trigger EADC enable bit
+ * |[27:24] |TRGSEL3   |PWM_CH3 Trigger EADC Source Select
+ * |        |          |0000 = PWM_CH2 zero point.
+ * |        |          |0001 = PWM_CH2 period point.
+ * |        |          |0010 = PWM_CH2 zero or period point.
+ * |        |          |0011 = PWM_CH2 up-count CMPDAT point.
+ * |        |          |0100 = PWM_CH2 down-count CMPDAT point.
+ * |        |          |0101 = PWM_CH3 zero point.
+ * |        |          |0110 = PWM_CH3 period point.
+ * |        |          |0111 = PWM_CH3 zero or period point.
+ * |        |          |1000 = PWM_CH3 up-count CMPDAT point.
+ * |        |          |1001 = PWM_CH3 down-count CMPDAT point.
+ * |        |          |1010 = PWM_CH0 up-count free CMPDAT point.
+ * |        |          |1011 = PWM_CH0 down-count free CMPDAT point.
+ * |        |          |1100 = PWM_CH2 up-count free CMPDAT point.
+ * |        |          |1101 = PWM_CH2 down-count free CMPDAT point.
+ * |        |          |1110 = PWM_CH4 up-count free CMPDAT point.
+ * |        |          |1111 = PWM_CH4 down-count free CMPDAT point.
+ * |[31]    |TRGEN3    |PWM_CH3 Trigger EADC enable bit
+ * @var PWM_T::EADCTS1
+ * Offset: 0xFC  PWM Trigger EADC Source Select Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |TRGSEL4   |PWM_CH4 Trigger EADC Source Select
+ * |        |          |0000 = PWM_CH4 zero point.
+ * |        |          |0001 = PWM_CH4 period point.
+ * |        |          |0010 = PWM_CH4 zero or period point.
+ * |        |          |0011 = PWM_CH4 up-count CMPDAT point.
+ * |        |          |0100 = PWM_CH4 down-count CMPDAT point.
+ * |        |          |0101 = PWM_CH5 zero point.
+ * |        |          |0110 = PWM_CH5 period point.
+ * |        |          |0111 = PWM_CH5 zero or period point.
+ * |        |          |1000 = PWM_CH5 up-count CMPDAT point.
+ * |        |          |1001 = PWM_CH5 down-count CMPDAT point.
+ * |        |          |1010 = PWM_CH0 up-count free CMPDAT point.
+ * |        |          |1011 = PWM_CH0 down-count free CMPDAT point.
+ * |        |          |1100 = PWM_CH2 up-count free CMPDAT point.
+ * |        |          |1101 = PWM_CH2 down-count free CMPDAT point.
+ * |        |          |1110 = PWM_CH4 up-count free CMPDAT point.
+ * |        |          |1111 = PWM_CH4 down-count free CMPDAT point.
+ * |[7]     |TRGEN4    |PWM_CH4 Trigger EADC enable bit
+ * |[11:8]  |TRGSEL5   |PWM_CH5 Trigger EADC Source Select
+ * |        |          |0000 = PWM_CH4 zero point.
+ * |        |          |0001 = PWM_CH4 period point.
+ * |        |          |0010 = PWM_CH4 zero or period point.
+ * |        |          |0011 = PWM_CH4 up-count CMPDAT point.
+ * |        |          |0100 = PWM_CH4 down-count CMPDAT point.
+ * |        |          |0101 = PWM_CH5 zero point.
+ * |        |          |0110 = PWM_CH5 period point.
+ * |        |          |0111 = PWM_CH5 zero or period point.
+ * |        |          |1000 = PWM_CH5 up-count CMPDAT point.
+ * |        |          |1001 = PWM_CH5 down-count CMPDAT point.
+ * |        |          |1010 = PWM_CH0 up-count free CMPDAT point.
+ * |        |          |1011 = PWM_CH0 down-count free CMPDAT point.
+ * |        |          |1100 = PWM_CH2 up-count free CMPDAT point.
+ * |        |          |1101 = PWM_CH2 down-count free CMPDAT point.
+ * |        |          |1110 = PWM_CH4 up-count free CMPDAT point.
+ * |        |          |1111 = PWM_CH4 down-count free CMPDAT point.
+ * |[15]    |TRGEN5    |PWM_CH5 Trigger EADC enable bit
+ * @var PWM_T::FTCMPDAT0_1
+ * Offset: 0x100  PWM Free Trigger Compare Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |FTCMP     |PWM Free Trigger Compare Register
+ * |        |          |FTCMP use to compare with even CNTR to trigger EADC.
+ * |        |          |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
+ * @var PWM_T::FTCMPDAT2_3
+ * Offset: 0x104  PWM Free Trigger Compare Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |FTCMP     |PWM Free Trigger Compare Register
+ * |        |          |FTCMP use to compare with even CNTR to trigger EADC.
+ * |        |          |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
+ * @var PWM_T::FTCMPDAT4_5
+ * Offset: 0x108  PWM Free Trigger Compare Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |FTCMP     |PWM Free Trigger Compare Register
+ * |        |          |FTCMP use to compare with even CNTR to trigger EADC.
+ * |        |          |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
+ * @var PWM_T::SSCTL
+ * Offset: 0x110  PWM Synchronous Start Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |SSENn     |PWM Synchronous Start Function Enable
+ * |        |          |When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = PWM synchronous start function Disabled.
+ * |        |          |1 = PWM synchronous start function Enabled.
+ * @var PWM_T::SSTRG
+ * Offset: 0x114  PWM Synchronous Start Trigger Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |CNTSEN    |PWM Counter Synchronous Start Enable (Write Only)
+ * |        |          |PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.
+ * |        |          |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
+ * |        |          |Note: This bit only present in PWM0_BA.
+ * @var PWM_T::STATUS
+ * Offset: 0x120  PWM Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |CNTMAXFn  |Time-Base Counter Equal To 0xFFFF Latched Flag
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+ * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+ * |[10:8]  |SYNCINFn  |Input Synchronization Latched Flag
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Indicates no SYNC_IN event has occurred.
+ * |        |          |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
+ * |[21:16] |ADCTRGFn  |EADC Start Of Conversion Flag
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * |[24]    |DACTRGF   |DAC Start Of Conversion Flag
+ * |        |          |0 = Indicates no DAC start of conversion trigger event has occurred.
+ * |        |          |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit
+ * @var PWM_T::CAPINEN
+ * Offset: 0x200  PWM Capture Input Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |CAPINENn  |Capture Input Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = PWM Channel capture input path Disabled.
+ * |        |          |The input of PWM channel capture function is always regarded as 0.
+ * |        |          |1 = PWM Channel capture input path Enabled.
+ * |        |          |The input of PWM channel capture function comes from correlative multifunction pin.
+ * @var PWM_T::CAPCTL
+ * Offset: 0x204  PWM Capture Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |CAPENn    |Capture Function Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * |        |          |1 = Capture function Enabled.
+ * |        |          |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[13:8]  |CAPINVn   |Capture Inverter Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Capture source inverter Disabled.
+ * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[21:16] |RCRLDENn  |Rising Capture Reload Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Rising capture reload counter Disabled.
+ * |        |          |1 = Rising capture reload counter Enabled.
+ * |[29:24] |FCRLDENn  |Falling Capture Reload Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Falling capture reload counter Disabled.
+ * |        |          |1 = Falling capture reload counter Enabled.
+ * @var PWM_T::CAPSTS
+ * Offset: 0x208  PWM Capture Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |CRLIFOVn  |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+ * |        |          |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+ * |[13:8]  |CFLIFOVn  |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+ * |        |          |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+ * @var PWM_T::RCAPDAT0
+ * Offset: 0x20C  PWM Rising Capture Data Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |RCAPDAT   |PWM Rising Capture Data Register (Read Only)
+ * |        |          |When rising capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::FCAPDAT0
+ * Offset: 0x210  PWM Falling Capture Data Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |FCAPDAT   |PWM Falling Capture Data Register (Read Only)
+ * |        |          |When falling capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::RCAPDAT1
+ * Offset: 0x214  PWM Rising Capture Data Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |RCAPDAT   |PWM Rising Capture Data Register (Read Only)
+ * |        |          |When rising capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::FCAPDAT1
+ * Offset: 0x218  PWM Falling Capture Data Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |FCAPDAT   |PWM Falling Capture Data Register (Read Only)
+ * |        |          |When falling capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::RCAPDAT2
+ * Offset: 0x21C  PWM Rising Capture Data Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |RCAPDAT   |PWM Rising Capture Data Register (Read Only)
+ * |        |          |When rising capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::FCAPDAT2
+ * Offset: 0x220  PWM Falling Capture Data Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |FCAPDAT   |PWM Falling Capture Data Register (Read Only)
+ * |        |          |When falling capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::RCAPDAT3
+ * Offset: 0x224  PWM Rising Capture Data Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |RCAPDAT   |PWM Rising Capture Data Register (Read Only)
+ * |        |          |When rising capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::FCAPDAT3
+ * Offset: 0x228  PWM Falling Capture Data Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |FCAPDAT   |PWM Falling Capture Data Register (Read Only)
+ * |        |          |When falling capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::RCAPDAT4
+ * Offset: 0x22C  PWM Rising Capture Data Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |RCAPDAT   |PWM Rising Capture Data Register (Read Only)
+ * |        |          |When rising capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::FCAPDAT4
+ * Offset: 0x230  PWM Falling Capture Data Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |FCAPDAT   |PWM Falling Capture Data Register (Read Only)
+ * |        |          |When falling capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::RCAPDAT5
+ * Offset: 0x234  PWM Rising Capture Data Register 5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |RCAPDAT   |PWM Rising Capture Data Register (Read Only)
+ * |        |          |When rising capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::FCAPDAT5
+ * Offset: 0x238  PWM Falling Capture Data Register 5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |FCAPDAT   |PWM Falling Capture Data Register (Read Only)
+ * |        |          |When falling capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::PDMACTL
+ * Offset: 0x23C  PWM PDMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |CHEN0_1   |Channel 0/1 PDMA Enable
+ * |        |          |0 = Channel 0/1 PDMA function Disabled.
+ * |        |          |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.
+ * |[2:1]   |CAPMOD0_1 |Select PWM_RCAPDAT0/1 Or PWM_FCAPDAT0/1 To Do PDMA Transfer
+ * |        |          |00 = Reserved.
+ * |        |          |01 = PWM_RCAPDAT0/1.
+ * |        |          |10 = PWM_FCAPDAT0/1.
+ * |        |          |11 = Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1.
+ * |[3]     |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order
+ * |        |          |Set this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 = 11.
+ * |        |          |0 = PWM_FCAPDAT0/1 is the first captured data to memory.
+ * |        |          |1 = PWM_RCAPDAT0/1 is the first captured data to memory.
+ * |[4]     |CHSEL0_1  |Select Channel 0/1 To Do PDMA Transfer
+ * |        |          |0 = Channel0.
+ * |        |          |1 = Channel1.
+ * |[8]     |CHEN2_3   |Channel 2/3 PDMA Enable
+ * |        |          |0 = Channel 2/3 PDMA function Disabled.
+ * |        |          |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.
+ * |[10:9]  |CAPMOD2_3 |Select PWM_RCAPDAT2/3 Or PWM_FCAODAT2/3 To Do PDMA Transfer
+ * |        |          |00 = Reserved.
+ * |        |          |01 = PWM_RCAPDAT2/3.
+ * |        |          |10 = PWM_FCAPDAT2/3.
+ * |        |          |11 = Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3.
+ * |[11]    |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order
+ * |        |          |Set this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 = 11.
+ * |        |          |0 = PWM_FCAPDAT2/3 is the first captured data to memory.
+ * |        |          |1 = PWM_RCAPDAT2/3 is the first captured data to memory.
+ * |[12]    |CHSEL2_3  |Select Channel 2/3 To Do PDMA Transfer
+ * |        |          |0 = Channel2.
+ * |        |          |1 = Channel3.
+ * |[16]    |CHEN4_5   |Channel 4/5 PDMA Enable
+ * |        |          |0 = Channel 4/5 PDMA function Disabled.
+ * |        |          |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.
+ * |[18:17] |CAPMOD4_5 |Select PWM_RCAPDAT4/5 Or PWM_FCAPDAT4/5 To Do PDMA Transfer
+ * |        |          |00 = Reserved.
+ * |        |          |01 = PWM_RCAPDAT4/5.
+ * |        |          |10 = PWM_FCAPDAT4/5.
+ * |        |          |11 = Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5.
+ * |[19]    |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order
+ * |        |          |Set this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 = 11.
+ * |        |          |0 = PWM_FCAPDAT4/5 is the first captured data to memory.
+ * |        |          |1 = PWM_RCAPDAT4/5 is the first captured data to memory.
+ * |[20]    |CHSEL4_5  |Select Channel 4/5 To Do PDMA Transfer
+ * |        |          |0 = Channel4.
+ * |        |          |1 = Channel5.
+ * @var PWM_T::PDMACAP0_1
+ * Offset: 0x240  PWM Capture Channel 01 PDMA Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |CAPBUF    |PWM Capture PDMA Register
+ * |        |          |(Read Only)
+ * |        |          |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
+ * @var PWM_T::PDMACAP2_3
+ * Offset: 0x244  PWM Capture Channel 23 PDMA Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |CAPBUF    |PWM Capture PDMA Register
+ * |        |          |(Read Only)
+ * |        |          |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
+ * @var PWM_T::PDMACAP4_5
+ * Offset: 0x248  PWM Capture Channel 45 PDMA Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |CAPBUF    |PWM Capture PDMA Register
+ * |        |          |(Read Only)
+ * |        |          |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
+ * @var PWM_T::CAPIEN
+ * Offset: 0x250  PWM Capture Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |CAPRIENn  |PWM Capture Rising Latch Interrupt Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Capture rising edge latch interrupt Disabled.
+ * |        |          |1 = Capture rising edge latch interrupt Enabled.
+ * |        |          |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
+ * |[13:8]  |CAPFIENn  |PWM Capture Falling Latch Interrupt Enable
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = Capture falling edge latch interrupt Disabled.
+ * |        |          |1 = Capture falling edge latch interrupt Enabled.
+ * |        |          |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
+ * @var PWM_T::CAPIF
+ * Offset: 0x254  PWM Capture Interrupt Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |CRLIFn    |PWM Capture Rising Latch Interrupt Flag
+ * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = No capture rising latch condition happened.
+ * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+ * |        |          |Note: When Capture with PDMA operating, CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+ * |[13:8]  |CFLIFn    |PWM Capture Falling Latch Interrupt Flag
+ * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
+ * |        |          |0 = No capture falling latch condition happened.
+ * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+ * |        |          |Note: When Capture with PDMA operating, CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+ * @var PWM_T::PBUF
+ * Offset: 0x304~0x318  PWM PERIOD0~5 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |PBUF      |PWM Period Register Buffer
+ * |        |          |(Read Only)
+ * |        |          |Used as PERIOD active register.
+ * @var PWM_T::CMPBUF
+ * Offset: 0x31C~0x330  PWM CMPDAT0~5 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |CMPBUF    |PWM Comparator Register Buffer
+ * |        |          |(Read Only)
+ * |        |          |Used as CMP active register.
+ * @var PWM_T::FTCBUF0_1
+ * Offset: 0x340  PWM FTCMPDAT0_1 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |FTCMPBUF  |PWM FTCMPDAT Buffer (Read Only)
+ * |        |          |Used as FTCMPDAT active register.
+ * @var PWM_T::FTCBUF2_3
+ * Offset: 0x344  PWM FTCMPDAT2_3 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |FTCMPBUF  |PWM FTCMPDAT Buffer (Read Only)
+ * |        |          |Used as FTCMPDAT active register.
+ * @var PWM_T::FTCBUF4_5
+ * Offset: 0x348  PWM FTCMPDAT4_5 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |FTCMPBUF  |PWM FTCMPDAT Buffer (Read Only)
+ * |        |          |Used as FTCMPDAT active register.
+ * @var PWM_T::FTCI
+ * Offset: 0x34C  PWM FTCMPDAT Indicator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[2:0]   |FTCMUn    |PWM FTCMPDAT Up Indicator
+ * |        |          |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=1, software can write 1 to clear this bit.
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ * |[10:8]  |FTCMDn    |PWM FTCMPDAT Down Indicator
+ * |        |          |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=0, software can write 1 to clear this bit.
+ * |        |          |Each bit n controls the corresponding PWM channel n.
+ */
+
+    __IO uint32_t CTL0;          /* Offset: 0x00  PWM Control Register 0                                             */
+    __IO uint32_t CTL1;          /* Offset: 0x04  PWM Control Register 1                                             */
+    __IO uint32_t SYNC;          /* Offset: 0x08  PWM Synchronization Register                                       */
+    __IO uint32_t SWSYNC;        /* Offset: 0x0C  PWM Software Control Synchronization Register                      */
+    __IO uint32_t CLKSRC;        /* Offset: 0x10  PWM Clock Source Register                                          */
+    __IO uint32_t CLKPSC0_1;     /* Offset: 0x14  PWM Clock Pre-scale Register 0                                     */
+    __IO uint32_t CLKPSC2_3;     /* Offset: 0x18  PWM Clock Pre-scale Register 2                                     */
+    __IO uint32_t CLKPSC4_5;     /* Offset: 0x1C  PWM Clock Pre-scale Register 4                                     */
+    __IO uint32_t CNTEN;         /* Offset: 0x20  PWM Counter Enable Register                                        */
+    __IO uint32_t CNTCLR;        /* Offset: 0x24  PWM Clear Counter Register                                         */
+    __IO uint32_t LOAD;          /* Offset: 0x28  PWM Load Register                                                  */
+    __I  uint32_t RESERVE0[1];  
+    __IO uint32_t PERIOD[6];     /* Offset: 0x30~0x44  PWM Period Register 0~5                                       */
+    __I  uint32_t RESERVE1[2];  
+    __IO uint32_t CMPDAT[6];     /* Offset: 0x50~0x64  PWM Comparator Register 0~5                                   */
+    __I  uint32_t RESERVE2[2];  
+    __IO uint32_t DTCTL0_1;      /* Offset: 0x70  PWM Dead-Time Control Register 0                                   */
+    __IO uint32_t DTCTL2_3;      /* Offset: 0x74  PWM Dead-Time Control Register 2                                   */
+    __IO uint32_t DTCTL4_5;      /* Offset: 0x78  PWM Dead-Time Control Register 4                                   */
+    __I  uint32_t RESERVE3[1];  
+    __IO uint32_t PHS0_1;        /* Offset: 0x80  PWM Counter Phase Register 0                                       */
+    __IO uint32_t PHS2_3;        /* Offset: 0x84  PWM Counter Phase Register 2                                       */
+    __IO uint32_t PHS4_5;        /* Offset: 0x88  PWM Counter Phase Register 4                                       */
+    __I  uint32_t RESERVE4[1];  
+    __I  uint32_t CNT[6];        /* Offset: 0x90~0xA4  PWM Counter Register 0~5                                      */
+    __I  uint32_t RESERVE5[2];  
+    __IO uint32_t WGCTL0;        /* Offset: 0xB0  PWM Generation Register 0                                          */
+    __IO uint32_t WGCTL1;        /* Offset: 0xB4  PWM Generation Register 1                                          */
+    __IO uint32_t MSKEN;         /* Offset: 0xB8  PWM Mask Enable Register                                           */
+    __IO uint32_t MSK;           /* Offset: 0xBC  PWM Mask Data Register                                             */
+    __IO uint32_t BNF;           /* Offset: 0xC0  PWM Brake Noise Filter Register                                    */
+    __IO uint32_t FAILBRK;       /* Offset: 0xC4  PWM System Fail Brake Control Register                             */
+    __IO uint32_t BRKCTL0_1;     /* Offset: 0xC8  PWM Brake Edge Detect Control Register 0                           */
+    __IO uint32_t BRKCTL2_3;     /* Offset: 0xCC  PWM Brake Edge Detect Control Register 2                           */
+    __IO uint32_t BRKCTL4_5;     /* Offset: 0xD0  PWM Brake Edge Detect Control Register 4                           */
+    __IO uint32_t POLCTL;        /* Offset: 0xD4  PWM Pin Polar Inverse Register                                     */
+    __IO uint32_t POEN;          /* Offset: 0xD8  PWM Output Enable Register                                         */
+    __O  uint32_t SWBRK;         /* Offset: 0xDC  PWM Software Brake Control Register                                */
+    __IO uint32_t INTEN0;        /* Offset: 0xE0  PWM Interrupt Enable Register 0                                    */
+    __IO uint32_t INTEN1;        /* Offset: 0xE4  PWM Interrupt Enable Register 1                                    */
+    __IO uint32_t INTSTS0;       /* Offset: 0xE8  PWM Interrupt Flag Register 0                                      */
+    __IO uint32_t INTSTS1;       /* Offset: 0xEC  PWM Interrupt Flag Register 1                                      */
+    __IO uint32_t IFA;           /* Offset: 0xF0  PWM Interrupt Flag Accumulator Register                            */
+    __IO uint32_t DACTRGEN;      /* Offset: 0xF4  PWM Trigger DAC Enable Register                                    */
+    __IO uint32_t EADCTS0;       /* Offset: 0xF8  PWM Trigger EADC Source Select Register 0                          */
+    __IO uint32_t EADCTS1;       /* Offset: 0xFC  PWM Trigger EADC Source Select Register 1                          */
+    __IO uint32_t FTCMPDAT0_1;   /* Offset: 0x100  PWM Free Trigger Compare Register 0                               */
+    __IO uint32_t FTCMPDAT2_3;   /* Offset: 0x104  PWM Free Trigger Compare Register 2                               */
+    __IO uint32_t FTCMPDAT4_5;   /* Offset: 0x108  PWM Free Trigger Compare Register 4                               */
+    __I  uint32_t RESERVE6[1];  
+    __IO uint32_t SSCTL;         /* Offset: 0x110  PWM Synchronous Start Control Register                            */
+    __O  uint32_t SSTRG;         /* Offset: 0x114  PWM Synchronous Start Trigger Register                            */
+    __I  uint32_t RESERVE7[2];  
+    __IO uint32_t STATUS;        /* Offset: 0x120  PWM Status Register                                               */
+    __I  uint32_t RESERVE8[55]; 
+    __IO uint32_t CAPINEN;       /* Offset: 0x200  PWM Capture Input Enable Register                                 */
+    __IO uint32_t CAPCTL;        /* Offset: 0x204  PWM Capture Control Register                                      */
+    __I  uint32_t CAPSTS;        /* Offset: 0x208  PWM Capture Status Register                                       */
+    __I  uint32_t RCAPDAT0;      /* Offset: 0x20C  PWM Rising Capture Data Register 0                                */
+    __I  uint32_t FCAPDAT0;      /* Offset: 0x210  PWM Falling Capture Data Register 0                               */
+    __I  uint32_t RCAPDAT1;      /* Offset: 0x214  PWM Rising Capture Data Register 1                                */
+    __I  uint32_t FCAPDAT1;      /* Offset: 0x218  PWM Falling Capture Data Register 1                               */
+    __I  uint32_t RCAPDAT2;      /* Offset: 0x21C  PWM Rising Capture Data Register 2                                */
+    __I  uint32_t FCAPDAT2;      /* Offset: 0x220  PWM Falling Capture Data Register 2                               */
+    __I  uint32_t RCAPDAT3;      /* Offset: 0x224  PWM Rising Capture Data Register 3                                */
+    __I  uint32_t FCAPDAT3;      /* Offset: 0x228  PWM Falling Capture Data Register 3                               */
+    __I  uint32_t RCAPDAT4;      /* Offset: 0x22C  PWM Rising Capture Data Register 4                                */
+    __I  uint32_t FCAPDAT4;      /* Offset: 0x230  PWM Falling Capture Data Register 4                               */
+    __I  uint32_t RCAPDAT5;      /* Offset: 0x234  PWM Rising Capture Data Register 5                                */
+    __I  uint32_t FCAPDAT5;      /* Offset: 0x238  PWM Falling Capture Data Register 5                               */
+    __IO uint32_t PDMACTL;       /* Offset: 0x23C  PWM PDMA Control Register                                         */
+    __I  uint32_t PDMACAP0_1;    /* Offset: 0x240  PWM Capture Channel 01 PDMA Register                              */
+    __I  uint32_t PDMACAP2_3;    /* Offset: 0x244  PWM Capture Channel 23 PDMA Register                              */
+    __I  uint32_t PDMACAP4_5;    /* Offset: 0x248  PWM Capture Channel 45 PDMA Register                              */
+    __I  uint32_t RESERVE9[1];  
+    __IO uint32_t CAPIEN;        /* Offset: 0x250  PWM Capture Interrupt Enable Register                             */
+    __IO uint32_t CAPIF;         /* Offset: 0x254  PWM Capture Interrupt Flag Register                               */
+    __I  uint32_t RESERVE10[43];
+    __I  uint32_t PBUF[6];       /* Offset: 0x304~0x318  PWM PERIOD0~5 Buffer                                        */
+    __I  uint32_t CMPBUF[6];     /* Offset: 0x31C~0x330  PWM CMPDAT0~5 Buffer                                        */
+    __I  uint32_t RESERVE11[3]; 
+    __I  uint32_t FTCBUF0_1;     /* Offset: 0x340  PWM FTCMPDAT0_1 Buffer                                            */
+    __I  uint32_t FTCBUF2_3;     /* Offset: 0x344  PWM FTCMPDAT2_3 Buffer                                            */
+    __I  uint32_t FTCBUF4_5;     /* Offset: 0x348  PWM FTCMPDAT4_5 Buffer                                            */
+    __IO uint32_t FTCI;          /* Offset: 0x34C  PWM FTCMPDAT Indicator Register                                   */
+
+} PWM_T;
+
+
+
+/**
+    @addtogroup PWM_CONST PWM Bit Field Definition
+    Constant Definitions for PWM Controller
+@{ */
+
+#define PWM_CTL0_CTRLDn_Pos              (0)                                               /*!< PWM_T::CTL0: CTRLDn Position              */
+#define PWM_CTL0_CTRLDn_Msk              (0x3ful << PWM_CTL0_CTRLDn_Pos)                   /*!< PWM_T::CTL0: CTRLDn Mask                  */
+
+#define PWM_CTL0_CTRLD0_Pos              (0)                                               /*!< PWM_T::CTL0: CTRLD0 Position              */
+#define PWM_CTL0_CTRLD0_Msk              (0x1ul << PWM_CTL0_CTRLD0_Pos)                    /*!< PWM_T::CTL0: CTRLD0 Mask                  */
+
+#define PWM_CTL0_CTRLD1_Pos              (1)                                               /*!< PWM_T::CTL0: CTRLD1 Position              */
+#define PWM_CTL0_CTRLD1_Msk              (0x1ul << PWM_CTL0_CTRLD1_Pos)                    /*!< PWM_T::CTL0: CTRLD1 Mask                  */
+
+#define PWM_CTL0_CTRLD2_Pos              (2)                                               /*!< PWM_T::CTL0: CTRLD2 Position              */
+#define PWM_CTL0_CTRLD2_Msk              (0x1ul << PWM_CTL0_CTRLD2_Pos)                    /*!< PWM_T::CTL0: CTRLD2 Mask                  */
+
+#define PWM_CTL0_CTRLD3_Pos              (3)                                               /*!< PWM_T::CTL0: CTRLD3 Position              */
+#define PWM_CTL0_CTRLD3_Msk              (0x1ul << PWM_CTL0_CTRLD3_Pos)                    /*!< PWM_T::CTL0: CTRLD3 Mask                  */
+
+#define PWM_CTL0_CTRLD4_Pos              (4)                                               /*!< PWM_T::CTL0: CTRLD4 Position              */
+#define PWM_CTL0_CTRLD4_Msk              (0x1ul << PWM_CTL0_CTRLD4_Pos)                    /*!< PWM_T::CTL0: CTRLD4 Mask                  */
+
+#define PWM_CTL0_CTRLD5_Pos              (5)                                               /*!< PWM_T::CTL0: CTRLD5 Position              */
+#define PWM_CTL0_CTRLD5_Msk              (0x1ul << PWM_CTL0_CTRLD5_Pos)                    /*!< PWM_T::CTL0: CTRLD5 Mask                  */
+
+#define PWM_CTL0_WINLDENn_Pos            (8)                                               /*!< PWM_T::CTL0: WINLDENn Position            */
+#define PWM_CTL0_WINLDENn_Msk            (0x3ful << PWM_CTL0_WINLDENn_Pos)                 /*!< PWM_T::CTL0: WINLDENn Mask                */
+
+#define PWM_CTL0_WINLDEN0_Pos            (8)                                               /*!< PWM_T::CTL0: WINLDEN0 Position            */
+#define PWM_CTL0_WINLDEN0_Msk            (0x1ul << PWM_CTL0_WINLDEN0_Pos)                  /*!< PWM_T::CTL0: WINLDEN0 Mask                */
+
+#define PWM_CTL0_WINLDEN1_Pos            (9)                                               /*!< PWM_T::CTL0: WINLDEN1 Position            */
+#define PWM_CTL0_WINLDEN1_Msk            (0x1ul << PWM_CTL0_WINLDEN1_Pos)                  /*!< PWM_T::CTL0: WINLDEN1 Mask                */
+
+#define PWM_CTL0_WINLDEN2_Pos            (10)                                              /*!< PWM_T::CTL0: WINLDEN2 Position            */
+#define PWM_CTL0_WINLDEN2_Msk            (0x1ul << PWM_CTL0_WINLDEN2_Pos)                  /*!< PWM_T::CTL0: WINLDEN2 Mask                */
+
+#define PWM_CTL0_WINLDEN3_Pos            (11)                                              /*!< PWM_T::CTL0: WINLDEN3 Position            */
+#define PWM_CTL0_WINLDEN3_Msk            (0x1ul << PWM_CTL0_WINLDEN3_Pos)                  /*!< PWM_T::CTL0: WINLDEN3 Mask                */
+
+#define PWM_CTL0_WINLDEN4_Pos            (12)                                              /*!< PWM_T::CTL0: WINLDEN4 Position            */
+#define PWM_CTL0_WINLDEN4_Msk            (0x1ul << PWM_CTL0_WINLDEN4_Pos)                  /*!< PWM_T::CTL0: WINLDEN4 Mask                */
+
+#define PWM_CTL0_WINLDEN5_Pos            (13)                                              /*!< PWM_T::CTL0: WINLDEN5 Position            */
+#define PWM_CTL0_WINLDEN5_Msk            (0x1ul << PWM_CTL0_WINLDEN5_Pos)                  /*!< PWM_T::CTL0: WINLDEN5 Mask                */
+
+#define PWM_CTL0_IMMLDENn_Pos            (16)                                              /*!< PWM_T::CTL0: IMMLDENn Position            */
+#define PWM_CTL0_IMMLDENn_Msk            (0x3ful << PWM_CTL0_IMMLDENn_Pos)                 /*!< PWM_T::CTL0: IMMLDENn Mask                */
+
+#define PWM_CTL0_IMMLDEN0_Pos            (16)                                              /*!< PWM_T::CTL0: IMMLDEN0 Position            */
+#define PWM_CTL0_IMMLDEN0_Msk            (0x1ul << PWM_CTL0_IMMLDEN0_Pos)                  /*!< PWM_T::CTL0: IMMLDEN0 Mask                */
+
+#define PWM_CTL0_IMMLDEN1_Pos            (17)                                              /*!< PWM_T::CTL0: IMMLDEN1 Position            */
+#define PWM_CTL0_IMMLDEN1_Msk            (0x1ul << PWM_CTL0_IMMLDEN1_Pos)                  /*!< PWM_T::CTL0: IMMLDEN1 Mask                */
+
+#define PWM_CTL0_IMMLDEN2_Pos            (18)                                              /*!< PWM_T::CTL0: IMMLDEN2 Position            */
+#define PWM_CTL0_IMMLDEN2_Msk            (0x1ul << PWM_CTL0_IMMLDEN2_Pos)                  /*!< PWM_T::CTL0: IMMLDEN2 Mask                */
+
+#define PWM_CTL0_IMMLDEN3_Pos            (19)                                              /*!< PWM_T::CTL0: IMMLDEN3 Position            */
+#define PWM_CTL0_IMMLDEN3_Msk            (0x1ul << PWM_CTL0_IMMLDEN3_Pos)                  /*!< PWM_T::CTL0: IMMLDEN3 Mask                */
+
+#define PWM_CTL0_IMMLDEN4_Pos            (20)                                              /*!< PWM_T::CTL0: IMMLDEN4 Position            */
+#define PWM_CTL0_IMMLDEN4_Msk            (0x1ul << PWM_CTL0_IMMLDEN4_Pos)                  /*!< PWM_T::CTL0: IMMLDEN4 Mask                */
+
+#define PWM_CTL0_IMMLDEN5_Pos            (21)                                              /*!< PWM_T::CTL0: IMMLDEN5 Position            */
+#define PWM_CTL0_IMMLDEN5_Msk            (0x1ul << PWM_CTL0_IMMLDEN5_Pos)                  /*!< PWM_T::CTL0: IMMLDEN5 Mask                */
+
+#define PWM_CTL0_GROUPEN_Pos             (24)                                              /*!< PWM_T::CTL0: GROUPEN Position             */
+#define PWM_CTL0_GROUPEN_Msk             (0x1ul << PWM_CTL0_GROUPEN_Pos)                   /*!< PWM_T::CTL0: GROUPEN Mask                 */
+
+#define PWM_CTL0_DBGHALT_Pos             (30)                                              /*!< PWM_T::CTL0: DBGHALT Position             */
+#define PWM_CTL0_DBGHALT_Msk             (0x1ul << PWM_CTL0_DBGHALT_Pos)                   /*!< PWM_T::CTL0: DBGHALT Mask                 */
+
+#define PWM_CTL0_DBGTRIOFF_Pos           (31)                                              /*!< PWM_T::CTL0: DBGTRIOFF Position           */
+#define PWM_CTL0_DBGTRIOFF_Msk           (0x1ul << PWM_CTL0_DBGTRIOFF_Pos)                 /*!< PWM_T::CTL0: DBGTRIOFF Mask               */
+
+#define PWM_CTL1_CNTTYPEn_Pos            (0)                                               /*!< PWM_T::CTL1: CNTTYPEn Position            */
+#define PWM_CTL1_CNTTYPEn_Msk            (0xffful << PWM_CTL1_CNTTYPEn_Pos)                /*!< PWM_T::CTL1: CNTTYPEn Mask                */
+
+#define PWM_CTL1_CNTTYPE0_Pos            (0)                                               /*!< PWM_T::CTL1: CNTTYPE0 Position            */
+#define PWM_CTL1_CNTTYPE0_Msk            (0x3ul << PWM_CTL1_CNTTYPE0_Pos)                  /*!< PWM_T::CTL1: CNTTYPE0 Mask                */
+
+#define PWM_CTL1_CNTTYPE1_Pos            (2)                                               /*!< PWM_T::CTL1: CNTTYPE1 Position            */
+#define PWM_CTL1_CNTTYPE1_Msk            (0x3ul << PWM_CTL1_CNTTYPE1_Pos)                  /*!< PWM_T::CTL1: CNTTYPE1 Mask                */
+
+#define PWM_CTL1_CNTTYPE2_Pos            (4)                                               /*!< PWM_T::CTL1: CNTTYPE2 Position            */
+#define PWM_CTL1_CNTTYPE2_Msk            (0x3ul << PWM_CTL1_CNTTYPE2_Pos)                  /*!< PWM_T::CTL1: CNTTYPE2 Mask                */
+
+#define PWM_CTL1_CNTTYPE3_Pos            (6)                                               /*!< PWM_T::CTL1: CNTTYPE3 Position            */
+#define PWM_CTL1_CNTTYPE3_Msk            (0x3ul << PWM_CTL1_CNTTYPE3_Pos)                  /*!< PWM_T::CTL1: CNTTYPE3 Mask                */
+
+#define PWM_CTL1_CNTTYPE4_Pos            (8)                                               /*!< PWM_T::CTL1: CNTTYPE4 Position            */
+#define PWM_CTL1_CNTTYPE4_Msk            (0x3ul << PWM_CTL1_CNTTYPE4_Pos)                  /*!< PWM_T::CTL1: CNTTYPE4 Mask                */
+
+#define PWM_CTL1_CNTTYPE5_Pos            (10)                                              /*!< PWM_T::CTL1: CNTTYPE5 Position            */
+#define PWM_CTL1_CNTTYPE5_Msk            (0x3ul << PWM_CTL1_CNTTYPE5_Pos)                  /*!< PWM_T::CTL1: CNTTYPE5 Mask                */
+
+#define PWM_CTL1_CNTMODEn_Pos            (16)                                              /*!< PWM_T::CTL1: CNTMODEn Position            */
+#define PWM_CTL1_CNTMODEn_Msk            (0x3ful << PWM_CTL1_CNTMODEn_Pos)                 /*!< PWM_T::CTL1: CNTMODEn Mask                */
+
+#define PWM_CTL1_CNTMODE0_Pos            (16)                                              /*!< PWM_T::CTL1: CNTMODE0 Position            */
+#define PWM_CTL1_CNTMODE0_Msk            (0x1ul << PWM_CTL1_CNTMODE0_Pos)                  /*!< PWM_T::CTL1: CNTMODE0 Mask                */
+
+#define PWM_CTL1_CNTMODE1_Pos            (17)                                              /*!< PWM_T::CTL1: CNTMODE1 Position            */
+#define PWM_CTL1_CNTMODE1_Msk            (0x1ul << PWM_CTL1_CNTMODE1_Pos)                  /*!< PWM_T::CTL1: CNTMODE1 Mask                */
+
+#define PWM_CTL1_CNTMODE2_Pos            (18)                                              /*!< PWM_T::CTL1: CNTMODE2 Position            */
+#define PWM_CTL1_CNTMODE2_Msk            (0x1ul << PWM_CTL1_CNTMODE2_Pos)                  /*!< PWM_T::CTL1: CNTMODE2 Mask                */
+
+#define PWM_CTL1_CNTMODE3_Pos            (19)                                              /*!< PWM_T::CTL1: CNTMODE3 Position            */
+#define PWM_CTL1_CNTMODE3_Msk            (0x1ul << PWM_CTL1_CNTMODE3_Pos)                  /*!< PWM_T::CTL1: CNTMODE3 Mask                */
+
+#define PWM_CTL1_CNTMODE4_Pos            (20)                                              /*!< PWM_T::CTL1: CNTMODE4 Position            */
+#define PWM_CTL1_CNTMODE4_Msk            (0x1ul << PWM_CTL1_CNTMODE4_Pos)                  /*!< PWM_T::CTL1: CNTMODE4 Mask                */
+
+#define PWM_CTL1_CNTMODE5_Pos            (21)                                              /*!< PWM_T::CTL1: CNTMODE5 Position            */
+#define PWM_CTL1_CNTMODE5_Msk            (0x1ul << PWM_CTL1_CNTMODE5_Pos)                  /*!< PWM_T::CTL1: CNTMODE5 Mask                */
+
+#define PWM_CTL1_OUTMODEn_Pos            (24)                                              /*!< PWM_T::CTL1: OUTMODEn Position            */
+#define PWM_CTL1_OUTMODEn_Msk            (0x7ul << PWM_CTL1_OUTMODEn_Pos)                  /*!< PWM_T::CTL1: OUTMODEn Mask                */
+
+#define PWM_CTL1_OUTMODE0_Pos            (24)                                              /*!< PWM_T::CTL1: OUTMODE0 Position            */
+#define PWM_CTL1_OUTMODE0_Msk            (0x1ul << PWM_CTL1_OUTMODE0_Pos)                  /*!< PWM_T::CTL1: OUTMODE0 Mask                */
+
+#define PWM_CTL1_OUTMODE2_Pos            (25)                                              /*!< PWM_T::CTL1: OUTMODE2 Position            */
+#define PWM_CTL1_OUTMODE2_Msk            (0x1ul << PWM_CTL1_OUTMODE2_Pos)                  /*!< PWM_T::CTL1: OUTMODE2 Mask                */
+
+#define PWM_CTL1_OUTMODE4_Pos            (26)                                              /*!< PWM_T::CTL1: OUTMODE4 Position            */
+#define PWM_CTL1_OUTMODE4_Msk            (0x1ul << PWM_CTL1_OUTMODE4_Pos)                  /*!< PWM_T::CTL1: OUTMODE4 Mask                */
+
+#define PWM_SYNC_PHSENn_Pos              (0)                                               /*!< PWM_T::SYNC: PHSENn Position              */
+#define PWM_SYNC_PHSENn_Msk              (0x7ul << PWM_SYNC_PHSENn_Pos)                    /*!< PWM_T::SYNC: PHSENn Mask                  */
+
+#define PWM_SYNC_PHSEN0_Pos              (0)                                               /*!< PWM_T::SYNC: PHSEN0 Position              */
+#define PWM_SYNC_PHSEN0_Msk              (0x1ul << PWM_SYNC_PHSEN0_Pos)                    /*!< PWM_T::SYNC: PHSEN0 Mask                  */
+
+#define PWM_SYNC_PHSEN2_Pos              (1)                                               /*!< PWM_T::SYNC: PHSEN2 Position              */
+#define PWM_SYNC_PHSEN2_Msk              (0x1ul << PWM_SYNC_PHSEN2_Pos)                    /*!< PWM_T::SYNC: PHSEN2 Mask                  */
+
+#define PWM_SYNC_PHSEN4_Pos              (2)                                               /*!< PWM_T::SYNC: PHSEN4 Position              */
+#define PWM_SYNC_PHSEN4_Msk              (0x1ul << PWM_SYNC_PHSEN4_Pos)                    /*!< PWM_T::SYNC: PHSEN4 Mask                  */
+
+#define PWM_SYNC_SINSRCn_Pos             (8)                                               /*!< PWM_T::SYNC: SINSRCn Position             */
+#define PWM_SYNC_SINSRCn_Msk             (0x3ful << PWM_SYNC_SINSRCn_Pos)                  /*!< PWM_T::SYNC: SINSRCn Mask                 */
+
+#define PWM_SYNC_SINSRC0_Pos             (8)                                               /*!< PWM_T::SYNC: SINSRC0 Position             */
+#define PWM_SYNC_SINSRC0_Msk             (0x3ul << PWM_SYNC_SINSRC0_Pos)                   /*!< PWM_T::SYNC: SINSRC0 Mask                 */
+
+#define PWM_SYNC_SINSRC2_Pos             (10)                                              /*!< PWM_T::SYNC: SINSRC2 Position             */
+#define PWM_SYNC_SINSRC2_Msk             (0x3ul << PWM_SYNC_SINSRC2_Pos)                   /*!< PWM_T::SYNC: SINSRC2 Mask                 */
+
+#define PWM_SYNC_SINSRC4_Pos             (12)                                              /*!< PWM_T::SYNC: SINSRC4 Position             */
+#define PWM_SYNC_SINSRC4_Msk             (0x3ul << PWM_SYNC_SINSRC4_Pos)                   /*!< PWM_T::SYNC: SINSRC4 Mask                 */
+
+#define PWM_SYNC_SNFLTEN_Pos             (16)                                              /*!< PWM_T::SYNC: SNFLTEN Position             */
+#define PWM_SYNC_SNFLTEN_Msk             (0x1ul << PWM_SYNC_SNFLTEN_Pos)                   /*!< PWM_T::SYNC: SNFLTEN Mask                 */
+
+#define PWM_SYNC_SFLTCSEL_Pos            (17)                                              /*!< PWM_T::SYNC: SFLTCSEL Position            */
+#define PWM_SYNC_SFLTCSEL_Msk            (0x7ul << PWM_SYNC_SFLTCSEL_Pos)                  /*!< PWM_T::SYNC: SFLTCSEL Mask                */
+
+#define PWM_SYNC_SFLTCNT_Pos             (20)                                              /*!< PWM_T::SYNC: SFLTCNT Position             */
+#define PWM_SYNC_SFLTCNT_Msk             (0x7ul << PWM_SYNC_SFLTCNT_Pos)                   /*!< PWM_T::SYNC: SFLTCNT Mask                 */
+
+#define PWM_SYNC_SINPINV_Pos             (23)                                              /*!< PWM_T::SYNC: SINPINV Position             */
+#define PWM_SYNC_SINPINV_Msk             (0x1ul << PWM_SYNC_SINPINV_Pos)                   /*!< PWM_T::SYNC: SINPINV Mask                 */
+
+#define PWM_SYNC_PHSDIRn_Pos             (24)                                              /*!< PWM_T::SYNC: PHSDIRn Position             */
+#define PWM_SYNC_PHSDIRn_Msk             (0x7ul << PWM_SYNC_PHSDIRn_Pos)                   /*!< PWM_T::SYNC: PHSDIRn Mask                 */
+
+#define PWM_SYNC_PHSDIR0_Pos             (24)                                              /*!< PWM_T::SYNC: PHSDIR0 Position             */
+#define PWM_SYNC_PHSDIR0_Msk             (0x1ul << PWM_SYNC_PHSDIR0_Pos)                   /*!< PWM_T::SYNC: PHSDIR0 Mask                 */
+
+#define PWM_SYNC_PHSDIR2_Pos             (25)                                              /*!< PWM_T::SYNC: PHSDIR2 Position             */
+#define PWM_SYNC_PHSDIR2_Msk             (0x1ul << PWM_SYNC_PHSDIR2_Pos)                   /*!< PWM_T::SYNC: PHSDIR2 Mask                 */
+
+#define PWM_SYNC_PHSDIR4_Pos             (26)                                              /*!< PWM_T::SYNC: PHSDIR4 Position             */
+#define PWM_SYNC_PHSDIR4_Msk             (0x1ul << PWM_SYNC_PHSDIR4_Pos)                   /*!< PWM_T::SYNC: PHSDIR4 Mask                 */
+
+#define PWM_SWSYNC_SWSYNCn_Pos           (0)                                               /*!< PWM_T::SWSYNC: SWSYNCn Position           */
+#define PWM_SWSYNC_SWSYNCn_Msk           (0x7ul << PWM_SWSYNC_SWSYNCn_Pos)                 /*!< PWM_T::SWSYNC: SWSYNCn Mask               */
+
+#define PWM_SWSYNC_SWSYNC0_Pos           (0)                                               /*!< PWM_T::SWSYNC: SWSYNC0 Position           */
+#define PWM_SWSYNC_SWSYNC0_Msk           (0x1ul << PWM_SWSYNC_SWSYNC0_Pos)                 /*!< PWM_T::SWSYNC: SWSYNC0 Mask               */
+
+#define PWM_SWSYNC_SWSYNC2_Pos           (1)                                               /*!< PWM_T::SWSYNC: SWSYNC2 Position           */
+#define PWM_SWSYNC_SWSYNC2_Msk           (0x1ul << PWM_SWSYNC_SWSYNC2_Pos)                 /*!< PWM_T::SWSYNC: SWSYNC2 Mask               */
+
+#define PWM_SWSYNC_SWSYNC4_Pos           (2)                                               /*!< PWM_T::SWSYNC: SWSYNC4 Position           */
+#define PWM_SWSYNC_SWSYNC4_Msk           (0x1ul << PWM_SWSYNC_SWSYNC4_Pos)                 /*!< PWM_T::SWSYNC: SWSYNC4 Mask               */
+
+#define PWM_CLKSRC_ECLKSRC0_Pos          (0)                                               /*!< PWM_T::CLKSRC: ECLKSRC0 Position          */
+#define PWM_CLKSRC_ECLKSRC0_Msk          (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos)                /*!< PWM_T::CLKSRC: ECLKSRC0 Mask              */
+
+#define PWM_CLKSRC_ECLKSRC2_Pos          (8)                                               /*!< PWM_T::CLKSRC: ECLKSRC2 Position          */
+#define PWM_CLKSRC_ECLKSRC2_Msk          (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos)                /*!< PWM_T::CLKSRC: ECLKSRC2 Mask              */
+
+#define PWM_CLKSRC_ECLKSRC4_Pos          (16)                                              /*!< PWM_T::CLKSRC: ECLKSRC4 Position          */
+#define PWM_CLKSRC_ECLKSRC4_Msk          (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos)                /*!< PWM_T::CLKSRC: ECLKSRC4 Mask              */
+
+#define PWM_CLKPSC0_1_CLKPSC_Pos         (0)                                               /*!< PWM_T::CLKPSC0_1: CLKPSC Position         */
+#define PWM_CLKPSC0_1_CLKPSC_Msk         (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos)             /*!< PWM_T::CLKPSC0_1: CLKPSC Mask             */
+
+#define PWM_CLKPSC2_3_CLKPSC_Pos         (0)                                               /*!< PWM_T::CLKPSC2_3: CLKPSC Position         */
+#define PWM_CLKPSC2_3_CLKPSC_Msk         (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos)             /*!< PWM_T::CLKPSC2_3: CLKPSC Mask             */
+
+#define PWM_CLKPSC4_5_CLKPSC_Pos         (0)                                               /*!< PWM_T::CLKPSC4_5: CLKPSC Position         */
+#define PWM_CLKPSC4_5_CLKPSC_Msk         (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos)             /*!< PWM_T::CLKPSC4_5: CLKPSC Mask             */
+
+#define PWM_CNTEN_CNTENn_Pos             (0)                                               /*!< PWM_T::CNTEN: CNTENn Position             */
+#define PWM_CNTEN_CNTENn_Msk             (0x3ful << PWM_CNTEN_CNTENn_Pos)                  /*!< PWM_T::CNTEN: CNTENn Mask                 */
+
+#define PWM_CNTEN_CNTEN0_Pos             (0)                                               /*!< PWM_T::CNTEN: CNTEN0 Position             */
+#define PWM_CNTEN_CNTEN0_Msk             (0x1ul << PWM_CNTEN_CNTEN0_Pos)                   /*!< PWM_T::CNTEN: CNTEN0 Mask                 */
+
+#define PWM_CNTEN_CNTEN1_Pos             (1)                                               /*!< PWM_T::CNTEN: CNTEN1 Position             */
+#define PWM_CNTEN_CNTEN1_Msk             (0x1ul << PWM_CNTEN_CNTEN1_Pos)                   /*!< PWM_T::CNTEN: CNTEN1 Mask                 */
+
+#define PWM_CNTEN_CNTEN2_Pos             (2)                                               /*!< PWM_T::CNTEN: CNTEN2 Position             */
+#define PWM_CNTEN_CNTEN2_Msk             (0x1ul << PWM_CNTEN_CNTEN2_Pos)                   /*!< PWM_T::CNTEN: CNTEN2 Mask                 */
+
+#define PWM_CNTEN_CNTEN3_Pos             (3)                                               /*!< PWM_T::CNTEN: CNTEN3 Position             */
+#define PWM_CNTEN_CNTEN3_Msk             (0x1ul << PWM_CNTEN_CNTEN3_Pos)                   /*!< PWM_T::CNTEN: CNTEN3 Mask                 */
+
+#define PWM_CNTEN_CNTEN4_Pos             (4)                                               /*!< PWM_T::CNTEN: CNTEN4 Position             */
+#define PWM_CNTEN_CNTEN4_Msk             (0x1ul << PWM_CNTEN_CNTEN4_Pos)                   /*!< PWM_T::CNTEN: CNTEN4 Mask                 */
+
+#define PWM_CNTEN_CNTEN5_Pos             (5)                                               /*!< PWM_T::CNTEN: CNTEN5 Position             */
+#define PWM_CNTEN_CNTEN5_Msk             (0x1ul << PWM_CNTEN_CNTEN5_Pos)                   /*!< PWM_T::CNTEN: CNTEN5 Mask                 */
+
+#define PWM_CNTCLR_CNTCLRn_Pos           (0)                                               /*!< PWM_T::CNTCLR: CNTCLRn Position           */
+#define PWM_CNTCLR_CNTCLRn_Msk           (0x3ful << PWM_CNTCLR_CNTCLRn_Pos)                /*!< PWM_T::CNTCLR: CNTCLRn Mask               */
+
+#define PWM_CNTCLR_CNTCLR0_Pos           (0)                                               /*!< PWM_T::CNTCLR: CNTCLR0 Position           */
+#define PWM_CNTCLR_CNTCLR0_Msk           (0x1ul << PWM_CNTCLR_CNTCLR0_Pos)                 /*!< PWM_T::CNTCLR: CNTCLR0 Mask               */
+
+#define PWM_CNTCLR_CNTCLR1_Pos           (1)                                               /*!< PWM_T::CNTCLR: CNTCLR1 Position           */
+#define PWM_CNTCLR_CNTCLR1_Msk           (0x1ul << PWM_CNTCLR_CNTCLR1_Pos)                 /*!< PWM_T::CNTCLR: CNTCLR1 Mask               */
+
+#define PWM_CNTCLR_CNTCLR2_Pos           (2)                                               /*!< PWM_T::CNTCLR: CNTCLR2 Position           */
+#define PWM_CNTCLR_CNTCLR2_Msk           (0x1ul << PWM_CNTCLR_CNTCLR2_Pos)                 /*!< PWM_T::CNTCLR: CNTCLR2 Mask               */
+
+#define PWM_CNTCLR_CNTCLR3_Pos           (3)                                               /*!< PWM_T::CNTCLR: CNTCLR3 Position           */
+#define PWM_CNTCLR_CNTCLR3_Msk           (0x1ul << PWM_CNTCLR_CNTCLR3_Pos)                 /*!< PWM_T::CNTCLR: CNTCLR3 Mask               */
+
+#define PWM_CNTCLR_CNTCLR4_Pos           (4)                                               /*!< PWM_T::CNTCLR: CNTCLR4 Position           */
+#define PWM_CNTCLR_CNTCLR4_Msk           (0x1ul << PWM_CNTCLR_CNTCLR4_Pos)                 /*!< PWM_T::CNTCLR: CNTCLR4 Mask               */
+
+#define PWM_CNTCLR_CNTCLR5_Pos           (5)                                               /*!< PWM_T::CNTCLR: CNTCLR5 Position           */
+#define PWM_CNTCLR_CNTCLR5_Msk           (0x1ul << PWM_CNTCLR_CNTCLR5_Pos)                 /*!< PWM_T::CNTCLR: CNTCLR5 Mask               */
+
+#define PWM_LOAD_LOADn_Pos               (0)                                               /*!< PWM_T::LOAD: LOADn Position               */
+#define PWM_LOAD_LOADn_Msk               (0x3ful << PWM_LOAD_LOADn_Pos)                    /*!< PWM_T::LOAD: LOADn Mask                   */
+
+#define PWM_LOAD_LOAD0_Pos               (0)                                               /*!< PWM_T::LOAD: LOAD0 Position               */
+#define PWM_LOAD_LOAD0_Msk               (0x1ul << PWM_LOAD_LOAD0_Pos)                     /*!< PWM_T::LOAD: LOAD0 Mask                   */
+
+#define PWM_LOAD_LOAD1_Pos               (1)                                               /*!< PWM_T::LOAD: LOAD1 Position               */
+#define PWM_LOAD_LOAD1_Msk               (0x1ul << PWM_LOAD_LOAD1_Pos)                     /*!< PWM_T::LOAD: LOAD1 Mask                   */
+
+#define PWM_LOAD_LOAD2_Pos               (2)                                               /*!< PWM_T::LOAD: LOAD2 Position               */
+#define PWM_LOAD_LOAD2_Msk               (0x1ul << PWM_LOAD_LOAD2_Pos)                     /*!< PWM_T::LOAD: LOAD2 Mask                   */
+
+#define PWM_LOAD_LOAD3_Pos               (3)                                               /*!< PWM_T::LOAD: LOAD3 Position               */
+#define PWM_LOAD_LOAD3_Msk               (0x1ul << PWM_LOAD_LOAD3_Pos)                     /*!< PWM_T::LOAD: LOAD3 Mask                   */
+
+#define PWM_LOAD_LOAD4_Pos               (4)                                               /*!< PWM_T::LOAD: LOAD4 Position               */
+#define PWM_LOAD_LOAD4_Msk               (0x1ul << PWM_LOAD_LOAD4_Pos)                     /*!< PWM_T::LOAD: LOAD4 Mask                   */
+
+#define PWM_LOAD_LOAD5_Pos               (5)                                               /*!< PWM_T::LOAD: LOAD5 Position               */
+#define PWM_LOAD_LOAD5_Msk               (0x1ul << PWM_LOAD_LOAD5_Pos)                     /*!< PWM_T::LOAD: LOAD5 Mask                   */
+
+#define PWM_PERIOD_PERIOD_Pos            (0)                                               /*!< PWM_T::PERIOD: PERIOD Position            */
+#define PWM_PERIOD_PERIOD_Msk            (0xfffful << PWM_PERIOD_PERIOD_Pos)               /*!< PWM_T::PERIOD: PERIOD Mask                */
+
+#define PWM_CMPDAT_CMP_Pos               (0)                                               /*!< PWM_T::CMPDAT: CMP Position               */
+#define PWM_CMPDAT_CMP_Msk               (0xfffful << PWM_CMPDAT_CMP_Pos)                  /*!< PWM_T::CMPDAT: CMP Mask                   */
+
+#define PWM_DTCTL0_1_DTCNT_Pos           (0)                                               /*!< PWM_T::DTCTL0_1: DTCNT Position           */
+#define PWM_DTCTL0_1_DTCNT_Msk           (0xffful << PWM_DTCTL0_1_DTCNT_Pos)               /*!< PWM_T::DTCTL0_1: DTCNT Mask               */
+
+#define PWM_DTCTL0_1_DTEN_Pos            (16)                                              /*!< PWM_T::DTCTL0_1: DTEN Position            */
+#define PWM_DTCTL0_1_DTEN_Msk            (0x1ul << PWM_DTCTL0_1_DTEN_Pos)                  /*!< PWM_T::DTCTL0_1: DTEN Mask                */
+
+#define PWM_DTCTL0_1_DTCKSEL_Pos         (24)                                              /*!< PWM_T::DTCTL0_1: DTCKSEL Position         */
+#define PWM_DTCTL0_1_DTCKSEL_Msk         (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos)               /*!< PWM_T::DTCTL0_1: DTCKSEL Mask             */
+
+#define PWM_DTCTL2_3_DTCNT_Pos           (0)                                               /*!< PWM_T::DTCTL2_3: DTCNT Position           */
+#define PWM_DTCTL2_3_DTCNT_Msk           (0xffful << PWM_DTCTL2_3_DTCNT_Pos)               /*!< PWM_T::DTCTL2_3: DTCNT Mask               */
+
+#define PWM_DTCTL2_3_DTEN_Pos            (16)                                              /*!< PWM_T::DTCTL2_3: DTEN Position            */
+#define PWM_DTCTL2_3_DTEN_Msk            (0x1ul << PWM_DTCTL2_3_DTEN_Pos)                  /*!< PWM_T::DTCTL2_3: DTEN Mask                */
+
+#define PWM_DTCTL2_3_DTCKSEL_Pos         (24)                                              /*!< PWM_T::DTCTL2_3: DTCKSEL Position         */
+#define PWM_DTCTL2_3_DTCKSEL_Msk         (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos)               /*!< PWM_T::DTCTL2_3: DTCKSEL Mask             */
+
+#define PWM_DTCTL4_5_DTCNT_Pos           (0)                                               /*!< PWM_T::DTCTL4_5: DTCNT Position           */
+#define PWM_DTCTL4_5_DTCNT_Msk           (0xffful << PWM_DTCTL4_5_DTCNT_Pos)               /*!< PWM_T::DTCTL4_5: DTCNT Mask               */
+
+#define PWM_DTCTL4_5_DTEN_Pos            (16)                                              /*!< PWM_T::DTCTL4_5: DTEN Position            */
+#define PWM_DTCTL4_5_DTEN_Msk            (0x1ul << PWM_DTCTL4_5_DTEN_Pos)                  /*!< PWM_T::DTCTL4_5: DTEN Mask                */
+
+#define PWM_DTCTL4_5_DTCKSEL_Pos         (24)                                              /*!< PWM_T::DTCTL4_5: DTCKSEL Position         */
+#define PWM_DTCTL4_5_DTCKSEL_Msk         (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos)               /*!< PWM_T::DTCTL4_5: DTCKSEL Mask             */
+
+#define PWM_PHS0_1_PHS_Pos               (0)                                               /*!< PWM_T::PHS0_1: PHS Position               */
+#define PWM_PHS0_1_PHS_Msk               (0xfffful << PWM_PHS0_1_PHS_Pos)                  /*!< PWM_T::PHS0_1: PHS Mask                   */
+
+#define PWM_PHS2_3_PHS_Pos               (0)                                               /*!< PWM_T::PHS2_3: PHS Position               */
+#define PWM_PHS2_3_PHS_Msk               (0xfffful << PWM_PHS2_3_PHS_Pos)                  /*!< PWM_T::PHS2_3: PHS Mask                   */
+
+#define PWM_PHS4_5_PHS_Pos               (0)                                               /*!< PWM_T::PHS4_5: PHS Position               */
+#define PWM_PHS4_5_PHS_Msk               (0xfffful << PWM_PHS4_5_PHS_Pos)                  /*!< PWM_T::PHS4_5: PHS Mask                   */
+
+#define PWM_CNT_CNT_Pos                  (0)                                               /*!< PWM_T::CNT: CNT Position                  */
+#define PWM_CNT_CNT_Msk                  (0xfffful << PWM_CNT_CNT_Pos)                     /*!< PWM_T::CNT: CNT Mask                      */
+
+#define PWM_CNT_DIRF_Pos                 (16)                                              /*!< PWM_T::CNT: DIRF Position                 */
+#define PWM_CNT_DIRF_Msk                 (0x1ul << PWM_CNT_DIRF_Pos)                       /*!< PWM_T::CNT: DIRF Mask                     */
+
+#define PWM_WGCTL0_ZPCTLn_Pos            (0)                                               /*!< PWM_T::WGCTL0: ZPCTLn Position            */
+#define PWM_WGCTL0_ZPCTLn_Msk            (0xffful << PWM_WGCTL0_ZPCTLn_Pos)                /*!< PWM_T::WGCTL0: ZPCTLn Mask                */
+
+#define PWM_WGCTL0_ZPCTL0_Pos            (0)                                               /*!< PWM_T::WGCTL0: ZPCTL0 Position            */
+#define PWM_WGCTL0_ZPCTL0_Msk            (0x3ul << PWM_WGCTL0_ZPCTL0_Pos)                  /*!< PWM_T::WGCTL0: ZPCTL0 Mask                */
+
+#define PWM_WGCTL0_ZPCTL1_Pos            (2)                                               /*!< PWM_T::WGCTL0: ZPCTL1 Position            */
+#define PWM_WGCTL0_ZPCTL1_Msk            (0x3ul << PWM_WGCTL0_ZPCTL1_Pos)                  /*!< PWM_T::WGCTL0: ZPCTL1 Mask                */
+
+#define PWM_WGCTL0_ZPCTL2_Pos            (4)                                               /*!< PWM_T::WGCTL0: ZPCTL2 Position            */
+#define PWM_WGCTL0_ZPCTL2_Msk            (0x3ul << PWM_WGCTL0_ZPCTL2_Pos)                  /*!< PWM_T::WGCTL0: ZPCTL2 Mask                */
+
+#define PWM_WGCTL0_ZPCTL3_Pos            (6)                                               /*!< PWM_T::WGCTL0: ZPCTL3 Position            */
+#define PWM_WGCTL0_ZPCTL3_Msk            (0x3ul << PWM_WGCTL0_ZPCTL3_Pos)                  /*!< PWM_T::WGCTL0: ZPCTL3 Mask                */
+
+#define PWM_WGCTL0_ZPCTL4_Pos            (8)                                               /*!< PWM_T::WGCTL0: ZPCTL4 Position            */
+#define PWM_WGCTL0_ZPCTL4_Msk            (0x3ul << PWM_WGCTL0_ZPCTL4_Pos)                  /*!< PWM_T::WGCTL0: ZPCTL4 Mask                */
+
+#define PWM_WGCTL0_ZPCTL5_Pos            (10)                                              /*!< PWM_T::WGCTL0: ZPCTL5 Position            */
+#define PWM_WGCTL0_ZPCTL5_Msk            (0x3ul << PWM_WGCTL0_ZPCTL5_Pos)                  /*!< PWM_T::WGCTL0: ZPCTL5 Mask                */
+
+#define PWM_WGCTL0_PRDPCTLn_Pos          (16)                                              /*!< PWM_T::WGCTL0: PRDPCTLn Position          */
+#define PWM_WGCTL0_PRDPCTLn_Msk          (0xffful << PWM_WGCTL0_PRDPCTLn_Pos)              /*!< PWM_T::WGCTL0: PRDPCTLn Mask              */
+
+#define PWM_WGCTL0_PRDPCTL0_Pos          (16)                                              /*!< PWM_T::WGCTL0: PRDPCTL0 Position          */
+#define PWM_WGCTL0_PRDPCTL0_Msk          (0x3ul << PWM_WGCTL0_PRDPCTL0_Pos)                /*!< PWM_T::WGCTL0: PRDPCTL0 Mask              */
+
+#define PWM_WGCTL0_PRDPCTL1_Pos          (18)                                              /*!< PWM_T::WGCTL0: PRDPCTL1 Position          */
+#define PWM_WGCTL0_PRDPCTL1_Msk          (0x3ul << PWM_WGCTL0_PRDPCTL1_Pos)                /*!< PWM_T::WGCTL0: PRDPCTL1 Mask              */
+
+#define PWM_WGCTL0_PRDPCTL2_Pos          (20)                                              /*!< PWM_T::WGCTL0: PRDPCTL2 Position          */
+#define PWM_WGCTL0_PRDPCTL2_Msk          (0x3ul << PWM_WGCTL0_PRDPCTL2_Pos)                /*!< PWM_T::WGCTL0: PRDPCTL2 Mask              */
+
+#define PWM_WGCTL0_PRDPCTL3_Pos          (22)                                              /*!< PWM_T::WGCTL0: PRDPCTL3 Position          */
+#define PWM_WGCTL0_PRDPCTL3_Msk          (0x3ul << PWM_WGCTL0_PRDPCTL3_Pos)                /*!< PWM_T::WGCTL0: PRDPCTL3 Mask              */
+
+#define PWM_WGCTL0_PRDPCTL4_Pos          (24)                                              /*!< PWM_T::WGCTL0: PRDPCTL4 Position          */
+#define PWM_WGCTL0_PRDPCTL4_Msk          (0x3ul << PWM_WGCTL0_PRDPCTL4_Pos)                /*!< PWM_T::WGCTL0: PRDPCTL4 Mask              */
+
+#define PWM_WGCTL0_PRDPCTL5_Pos          (26)                                              /*!< PWM_T::WGCTL0: PRDPCTL5 Position          */
+#define PWM_WGCTL0_PRDPCTL5_Msk          (0x3ul << PWM_WGCTL0_PRDPCTL5_Pos)                /*!< PWM_T::WGCTL0: PRDPCTL5 Mask              */
+
+#define PWM_WGCTL1_CMPUCTLn_Pos          (0)                                               /*!< PWM_T::WGCTL1: CMPUCTLn Position          */
+#define PWM_WGCTL1_CMPUCTLn_Msk          (0xffful << PWM_WGCTL1_CMPUCTLn_Pos)              /*!< PWM_T::WGCTL1: CMPUCTLn Mask              */
+
+#define PWM_WGCTL1_CMPUCTL0_Pos          (0)                                               /*!< PWM_T::WGCTL1: CMPUCTL0 Position          */
+#define PWM_WGCTL1_CMPUCTL0_Msk          (0x3ul << PWM_WGCTL1_CMPUCTL0_Pos)                /*!< PWM_T::WGCTL1: CMPUCTL0 Mask              */
+
+#define PWM_WGCTL1_CMPUCTL1_Pos          (2)                                               /*!< PWM_T::WGCTL1: CMPUCTL1 Position          */
+#define PWM_WGCTL1_CMPUCTL1_Msk          (0x3ul << PWM_WGCTL1_CMPUCTL1_Pos)                /*!< PWM_T::WGCTL1: CMPUCTL1 Mask              */
+
+#define PWM_WGCTL1_CMPUCTL2_Pos          (4)                                               /*!< PWM_T::WGCTL1: CMPUCTL2 Position          */
+#define PWM_WGCTL1_CMPUCTL2_Msk          (0x3ul << PWM_WGCTL1_CMPUCTL2_Pos)                /*!< PWM_T::WGCTL1: CMPUCTL2 Mask              */
+
+#define PWM_WGCTL1_CMPUCTL3_Pos          (6)                                               /*!< PWM_T::WGCTL1: CMPUCTL3 Position          */
+#define PWM_WGCTL1_CMPUCTL3_Msk          (0x3ul << PWM_WGCTL1_CMPUCTL3_Pos)                /*!< PWM_T::WGCTL1: CMPUCTL3 Mask              */
+
+#define PWM_WGCTL1_CMPUCTL4_Pos          (8)                                               /*!< PWM_T::WGCTL1: CMPUCTL4 Position          */
+#define PWM_WGCTL1_CMPUCTL4_Msk          (0x3ul << PWM_WGCTL1_CMPUCTL4_Pos)                /*!< PWM_T::WGCTL1: CMPUCTL4 Mask              */
+
+#define PWM_WGCTL1_CMPUCTL5_Pos          (10)                                              /*!< PWM_T::WGCTL1: CMPUCTL5 Position          */
+#define PWM_WGCTL1_CMPUCTL5_Msk          (0x3ul << PWM_WGCTL1_CMPUCTL5_Pos)                /*!< PWM_T::WGCTL1: CMPUCTL5 Mask              */
+
+#define PWM_WGCTL1_CMPDCTLn_Pos          (16)                                              /*!< PWM_T::WGCTL1: CMPDCTLn Position          */
+#define PWM_WGCTL1_CMPDCTLn_Msk          (0xffful << PWM_WGCTL1_CMPDCTLn_Pos)              /*!< PWM_T::WGCTL1: CMPDCTLn Mask              */
+
+#define PWM_WGCTL1_CMPDCTL0_Pos          (16)                                              /*!< PWM_T::WGCTL1: CMPDCTL0 Position          */
+#define PWM_WGCTL1_CMPDCTL0_Msk          (0x3ul << PWM_WGCTL1_CMPDCTL0_Pos)                /*!< PWM_T::WGCTL1: CMPDCTL0 Mask              */
+
+#define PWM_WGCTL1_CMPDCTL1_Pos          (18)                                              /*!< PWM_T::WGCTL1: CMPDCTL1 Position          */
+#define PWM_WGCTL1_CMPDCTL1_Msk          (0x3ul << PWM_WGCTL1_CMPDCTL1_Pos)                /*!< PWM_T::WGCTL1: CMPDCTL1 Mask              */
+
+#define PWM_WGCTL1_CMPDCTL2_Pos          (20)                                              /*!< PWM_T::WGCTL1: CMPDCTL2 Position          */
+#define PWM_WGCTL1_CMPDCTL2_Msk          (0x3ul << PWM_WGCTL1_CMPDCTL2_Pos)                /*!< PWM_T::WGCTL1: CMPDCTL2 Mask              */
+
+#define PWM_WGCTL1_CMPDCTL3_Pos          (22)                                              /*!< PWM_T::WGCTL1: CMPDCTL3 Position          */
+#define PWM_WGCTL1_CMPDCTL3_Msk          (0x3ul << PWM_WGCTL1_CMPDCTL3_Pos)                /*!< PWM_T::WGCTL1: CMPDCTL3 Mask              */
+
+#define PWM_WGCTL1_CMPDCTL4_Pos          (24)                                              /*!< PWM_T::WGCTL1: CMPDCTL4 Position          */
+#define PWM_WGCTL1_CMPDCTL4_Msk          (0x3ul << PWM_WGCTL1_CMPDCTL4_Pos)                /*!< PWM_T::WGCTL1: CMPDCTL4 Mask              */
+
+#define PWM_WGCTL1_CMPDCTL5_Pos          (26)                                              /*!< PWM_T::WGCTL1: CMPDCTL5 Position          */
+#define PWM_WGCTL1_CMPDCTL5_Msk          (0x3ul << PWM_WGCTL1_CMPDCTL5_Pos)                /*!< PWM_T::WGCTL1: CMPDCTL5 Mask              */
+
+#define PWM_MSKEN_MSKENn_Pos             (0)                                               /*!< PWM_T::MSKEN: MSKENn Position             */
+#define PWM_MSKEN_MSKENn_Msk             (0x3ful << PWM_MSKEN_MSKENn_Pos)                  /*!< PWM_T::MSKEN: MSKENn Mask                 */
+
+#define PWM_MSKEN_MSKEN0_Pos             (0)                                               /*!< PWM_T::MSKEN: MSKEN0 Position             */
+#define PWM_MSKEN_MSKEN0_Msk             (0x1ul << PWM_MSKEN_MSKEN0_Pos)                   /*!< PWM_T::MSKEN: MSKEN0 Mask                 */
+
+#define PWM_MSKEN_MSKEN1_Pos             (1)                                               /*!< PWM_T::MSKEN: MSKEN1 Position             */
+#define PWM_MSKEN_MSKEN1_Msk             (0x1ul << PWM_MSKEN_MSKEN1_Pos)                   /*!< PWM_T::MSKEN: MSKEN1 Mask                 */
+
+#define PWM_MSKEN_MSKEN2_Pos             (2)                                               /*!< PWM_T::MSKEN: MSKEN2 Position             */
+#define PWM_MSKEN_MSKEN2_Msk             (0x1ul << PWM_MSKEN_MSKEN2_Pos)                   /*!< PWM_T::MSKEN: MSKEN2 Mask                 */
+
+#define PWM_MSKEN_MSKEN3_Pos             (3)                                               /*!< PWM_T::MSKEN: MSKEN3 Position             */
+#define PWM_MSKEN_MSKEN3_Msk             (0x1ul << PWM_MSKEN_MSKEN3_Pos)                   /*!< PWM_T::MSKEN: MSKEN3 Mask                 */
+
+#define PWM_MSKEN_MSKEN4_Pos             (4)                                               /*!< PWM_T::MSKEN: MSKEN4 Position             */
+#define PWM_MSKEN_MSKEN4_Msk             (0x1ul << PWM_MSKEN_MSKEN4_Pos)                   /*!< PWM_T::MSKEN: MSKEN4 Mask                 */
+
+#define PWM_MSKEN_MSKEN5_Pos             (5)                                               /*!< PWM_T::MSKEN: MSKEN5 Position             */
+#define PWM_MSKEN_MSKEN5_Msk             (0x1ul << PWM_MSKEN_MSKEN5_Pos)                   /*!< PWM_T::MSKEN: MSKEN5 Mask                 */
+
+#define PWM_MSK_MSKDATn_Pos              (0)                                               /*!< PWM_T::MSK: MSKDATn Position              */
+#define PWM_MSK_MSKDATn_Msk              (0x3ful << PWM_MSK_MSKDATn_Pos)                   /*!< PWM_T::MSK: MSKDATn Mask                  */
+
+#define PWM_MSK_MSKDAT0_Pos              (0)                                               /*!< PWM_T::MSK: MSKDAT0 Position              */
+#define PWM_MSK_MSKDAT0_Msk              (0x1ul << PWM_MSK_MSKDAT0_Pos)                    /*!< PWM_T::MSK: MSKDAT0 Mask                  */
+
+#define PWM_MSK_MSKDAT1_Pos              (1)                                               /*!< PWM_T::MSK: MSKDAT1 Position              */
+#define PWM_MSK_MSKDAT1_Msk              (0x1ul << PWM_MSK_MSKDAT1_Pos)                    /*!< PWM_T::MSK: MSKDAT1 Mask                  */
+
+#define PWM_MSK_MSKDAT2_Pos              (2)                                               /*!< PWM_T::MSK: MSKDAT2 Position              */
+#define PWM_MSK_MSKDAT2_Msk              (0x1ul << PWM_MSK_MSKDAT2_Pos)                    /*!< PWM_T::MSK: MSKDAT2 Mask                  */
+
+#define PWM_MSK_MSKDAT3_Pos              (3)                                               /*!< PWM_T::MSK: MSKDAT3 Position              */
+#define PWM_MSK_MSKDAT3_Msk              (0x1ul << PWM_MSK_MSKDAT3_Pos)                    /*!< PWM_T::MSK: MSKDAT3 Mask                  */
+
+#define PWM_MSK_MSKDAT4_Pos              (4)                                               /*!< PWM_T::MSK: MSKDAT4 Position              */
+#define PWM_MSK_MSKDAT4_Msk              (0x1ul << PWM_MSK_MSKDAT4_Pos)                    /*!< PWM_T::MSK: MSKDAT4 Mask                  */
+
+#define PWM_MSK_MSKDAT5_Pos              (5)                                               /*!< PWM_T::MSK: MSKDAT5 Position              */
+#define PWM_MSK_MSKDAT5_Msk              (0x1ul << PWM_MSK_MSKDAT5_Pos)                    /*!< PWM_T::MSK: MSKDAT5 Mask                  */
+
+#define PWM_BNF_BRK0NFEN_Pos             (0)                                               /*!< PWM_T::BNF: BRK0NFEN Position             */
+#define PWM_BNF_BRK0NFEN_Msk             (0x1ul << PWM_BNF_BRK0NFEN_Pos)                   /*!< PWM_T::BNF: BRK0NFEN Mask                 */
+
+#define PWM_BNF_BRK0NFSEL_Pos            (1)                                               /*!< PWM_T::BNF: BRK0NFSEL Position            */
+#define PWM_BNF_BRK0NFSEL_Msk            (0x7ul << PWM_BNF_BRK0NFSEL_Pos)                  /*!< PWM_T::BNF: BRK0NFSEL Mask                */
+
+#define PWM_BNF_BRK0FCNT_Pos             (4)                                               /*!< PWM_T::BNF: BRK0FCNT Position             */
+#define PWM_BNF_BRK0FCNT_Msk             (0x7ul << PWM_BNF_BRK0FCNT_Pos)                   /*!< PWM_T::BNF: BRK0FCNT Mask                 */
+
+#define PWM_BNF_BRK0PINV_Pos             (7)                                               /*!< PWM_T::BNF: BRK0PINV Position             */
+#define PWM_BNF_BRK0PINV_Msk             (0x1ul << PWM_BNF_BRK0PINV_Pos)                   /*!< PWM_T::BNF: BRK0PINV Mask                 */
+
+#define PWM_BNF_BRK1NFEN_Pos             (8)                                               /*!< PWM_T::BNF: BRK1NFEN Position             */
+#define PWM_BNF_BRK1NFEN_Msk             (0x1ul << PWM_BNF_BRK1NFEN_Pos)                   /*!< PWM_T::BNF: BRK1NFEN Mask                 */
+
+#define PWM_BNF_BRK1NFSEL_Pos            (9)                                               /*!< PWM_T::BNF: BRK1NFSEL Position            */
+#define PWM_BNF_BRK1NFSEL_Msk            (0x7ul << PWM_BNF_BRK1NFSEL_Pos)                  /*!< PWM_T::BNF: BRK1NFSEL Mask                */
+
+#define PWM_BNF_BRK1FCNT_Pos             (12)                                              /*!< PWM_T::BNF: BRK1FCNT Position             */
+#define PWM_BNF_BRK1FCNT_Msk             (0x7ul << PWM_BNF_BRK1FCNT_Pos)                   /*!< PWM_T::BNF: BRK1FCNT Mask                 */
+
+#define PWM_BNF_BRK1PINV_Pos             (15)                                              /*!< PWM_T::BNF: BRK1PINV Position             */
+#define PWM_BNF_BRK1PINV_Msk             (0x1ul << PWM_BNF_BRK1PINV_Pos)                   /*!< PWM_T::BNF: BRK1PINV Mask                 */
+
+#define PWM_BNF_BK0SRC_Pos               (16)                                              /*!< PWM_T::BNF: BK0SRC Position               */
+#define PWM_BNF_BK0SRC_Msk               (0x1ul << PWM_BNF_BK0SRC_Pos)                     /*!< PWM_T::BNF: BK0SRC Mask                   */
+
+#define PWM_BNF_BK1SRC_Pos               (24)                                              /*!< PWM_T::BNF: BK1SRC Position               */
+#define PWM_BNF_BK1SRC_Msk               (0x1ul << PWM_BNF_BK1SRC_Pos)                     /*!< PWM_T::BNF: BK1SRC Mask                   */
+
+#define PWM_FAILBRK_CSSBRKEN_Pos         (0)                                               /*!< PWM_T::FAILBRK: CSSBRKEN Position         */
+#define PWM_FAILBRK_CSSBRKEN_Msk         (0x1ul << PWM_FAILBRK_CSSBRKEN_Pos)               /*!< PWM_T::FAILBRK: CSSBRKEN Mask             */
+
+#define PWM_FAILBRK_BODBRKEN_Pos         (1)                                               /*!< PWM_T::FAILBRK: BODBRKEN Position         */
+#define PWM_FAILBRK_BODBRKEN_Msk         (0x1ul << PWM_FAILBRK_BODBRKEN_Pos)               /*!< PWM_T::FAILBRK: BODBRKEN Mask             */
+
+#define PWM_FAILBRK_RAMBRKEN_Pos         (2)                                               /*!< PWM_T::FAILBRK: RAMBRKEN Position         */
+#define PWM_FAILBRK_RAMBRKEN_Msk         (0x1ul << PWM_FAILBRK_RAMBRKEN_Pos)               /*!< PWM_T::FAILBRK: RAMBRKEN Mask             */
+
+#define PWM_FAILBRK_CORBRKEN_Pos         (3)                                               /*!< PWM_T::FAILBRK: CORBRKEN Position         */
+#define PWM_FAILBRK_CORBRKEN_Msk         (0x1ul << PWM_FAILBRK_CORBRKEN_Pos)               /*!< PWM_T::FAILBRK: CORBRKEN Mask             */
+
+#define PWM_BRKCTL0_1_CPO0EBEN_Pos       (0)                                               /*!< PWM_T::BRKCTL0_1: CPO0EBEN Position       */
+#define PWM_BRKCTL0_1_CPO0EBEN_Msk       (0x1ul << PWM_BRKCTL0_1_CPO0EBEN_Pos)             /*!< PWM_T::BRKCTL0_1: CPO0EBEN Mask           */
+
+#define PWM_BRKCTL0_1_CPO1EBEN_Pos       (1)                                               /*!< PWM_T::BRKCTL0_1: CPO1EBEN Position       */
+#define PWM_BRKCTL0_1_CPO1EBEN_Msk       (0x1ul << PWM_BRKCTL0_1_CPO1EBEN_Pos)             /*!< PWM_T::BRKCTL0_1: CPO1EBEN Mask           */
+
+#define PWM_BRKCTL0_1_BRKP0EEN_Pos       (4)                                               /*!< PWM_T::BRKCTL0_1: BRKP0EEN Position       */
+#define PWM_BRKCTL0_1_BRKP0EEN_Msk       (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos)             /*!< PWM_T::BRKCTL0_1: BRKP0EEN Mask           */
+
+#define PWM_BRKCTL0_1_BRKP1EEN_Pos       (5)                                               /*!< PWM_T::BRKCTL0_1: BRKP1EEN Position       */
+#define PWM_BRKCTL0_1_BRKP1EEN_Msk       (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos)             /*!< PWM_T::BRKCTL0_1: BRKP1EEN Mask           */
+
+#define PWM_BRKCTL0_1_SYSEBEN_Pos        (7)                                               /*!< PWM_T::BRKCTL0_1: SYSEBEN Position        */
+#define PWM_BRKCTL0_1_SYSEBEN_Msk        (0x1ul << PWM_BRKCTL0_1_SYSEBEN_Pos)              /*!< PWM_T::BRKCTL0_1: SYSEBEN Mask            */
+
+#define PWM_BRKCTL0_1_CPO0LBEN_Pos       (8)                                               /*!< PWM_T::BRKCTL0_1: CPO0LBEN Position       */
+#define PWM_BRKCTL0_1_CPO0LBEN_Msk       (0x1ul << PWM_BRKCTL0_1_CPO0LBEN_Pos)             /*!< PWM_T::BRKCTL0_1: CPO0LBEN Mask           */
+
+#define PWM_BRKCTL0_1_CPO1LBEN_Pos       (9)                                               /*!< PWM_T::BRKCTL0_1: CPO1LBEN Position       */
+#define PWM_BRKCTL0_1_CPO1LBEN_Msk       (0x1ul << PWM_BRKCTL0_1_CPO1LBEN_Pos)             /*!< PWM_T::BRKCTL0_1: CPO1LBEN Mask           */
+
+#define PWM_BRKCTL0_1_BRKP0LEN_Pos       (12)                                              /*!< PWM_T::BRKCTL0_1: BRKP0LEN Position       */
+#define PWM_BRKCTL0_1_BRKP0LEN_Msk       (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos)             /*!< PWM_T::BRKCTL0_1: BRKP0LEN Mask           */
+
+#define PWM_BRKCTL0_1_BRKP1LEN_Pos       (13)                                              /*!< PWM_T::BRKCTL0_1: BRKP1LEN Position       */
+#define PWM_BRKCTL0_1_BRKP1LEN_Msk       (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos)             /*!< PWM_T::BRKCTL0_1: BRKP1LEN Mask           */
+
+#define PWM_BRKCTL0_1_SYSLBEN_Pos        (15)                                              /*!< PWM_T::BRKCTL0_1: SYSLBEN Position        */
+#define PWM_BRKCTL0_1_SYSLBEN_Msk        (0x1ul << PWM_BRKCTL0_1_SYSLBEN_Pos)              /*!< PWM_T::BRKCTL0_1: SYSLBEN Mask            */
+
+#define PWM_BRKCTL0_1_BRKAEVEN_Pos       (16)                                              /*!< PWM_T::BRKCTL0_1: BRKAEVEN Position       */
+#define PWM_BRKCTL0_1_BRKAEVEN_Msk       (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos)             /*!< PWM_T::BRKCTL0_1: BRKAEVEN Mask           */
+
+#define PWM_BRKCTL0_1_BRKAODD_Pos        (18)                                              /*!< PWM_T::BRKCTL0_1: BRKAODD Position        */
+#define PWM_BRKCTL0_1_BRKAODD_Msk        (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos)              /*!< PWM_T::BRKCTL0_1: BRKAODD Mask            */
+
+#define PWM_BRKCTL2_3_CPO0EBEN_Pos       (0)                                               /*!< PWM_T::BRKCTL2_3: CPO0EBEN Position       */
+#define PWM_BRKCTL2_3_CPO0EBEN_Msk       (0x1ul << PWM_BRKCTL2_3_CPO0EBEN_Pos)             /*!< PWM_T::BRKCTL2_3: CPO0EBEN Mask           */
+
+#define PWM_BRKCTL2_3_CPO1EBEN_Pos       (1)                                               /*!< PWM_T::BRKCTL2_3: CPO1EBEN Position       */
+#define PWM_BRKCTL2_3_CPO1EBEN_Msk       (0x1ul << PWM_BRKCTL2_3_CPO1EBEN_Pos)             /*!< PWM_T::BRKCTL2_3: CPO1EBEN Mask           */
+
+#define PWM_BRKCTL2_3_BRKP0EEN_Pos       (4)                                               /*!< PWM_T::BRKCTL2_3: BRKP0EEN Position       */
+#define PWM_BRKCTL2_3_BRKP0EEN_Msk       (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos)             /*!< PWM_T::BRKCTL2_3: BRKP0EEN Mask           */
+
+#define PWM_BRKCTL2_3_BRKP1EEN_Pos       (5)                                               /*!< PWM_T::BRKCTL2_3: BRKP1EEN Position       */
+#define PWM_BRKCTL2_3_BRKP1EEN_Msk       (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos)             /*!< PWM_T::BRKCTL2_3: BRKP1EEN Mask           */
+
+#define PWM_BRKCTL2_3_SYSEBEN_Pos        (7)                                               /*!< PWM_T::BRKCTL2_3: SYSEBEN Position        */
+#define PWM_BRKCTL2_3_SYSEBEN_Msk        (0x1ul << PWM_BRKCTL2_3_SYSEBEN_Pos)              /*!< PWM_T::BRKCTL2_3: SYSEBEN Mask            */
+
+#define PWM_BRKCTL2_3_CPO0LBEN_Pos       (8)                                               /*!< PWM_T::BRKCTL2_3: CPO0LBEN Position       */
+#define PWM_BRKCTL2_3_CPO0LBEN_Msk       (0x1ul << PWM_BRKCTL2_3_CPO0LBEN_Pos)             /*!< PWM_T::BRKCTL2_3: CPO0LBEN Mask           */
+
+#define PWM_BRKCTL2_3_CPO1LBEN_Pos       (9)                                               /*!< PWM_T::BRKCTL2_3: CPO1LBEN Position       */
+#define PWM_BRKCTL2_3_CPO1LBEN_Msk       (0x1ul << PWM_BRKCTL2_3_CPO1LBEN_Pos)             /*!< PWM_T::BRKCTL2_3: CPO1LBEN Mask           */
+
+#define PWM_BRKCTL2_3_BRKP0LEN_Pos       (12)                                              /*!< PWM_T::BRKCTL2_3: BRKP0LEN Position       */
+#define PWM_BRKCTL2_3_BRKP0LEN_Msk       (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos)             /*!< PWM_T::BRKCTL2_3: BRKP0LEN Mask           */
+
+#define PWM_BRKCTL2_3_BRKP1LEN_Pos       (13)                                              /*!< PWM_T::BRKCTL2_3: BRKP1LEN Position       */
+#define PWM_BRKCTL2_3_BRKP1LEN_Msk       (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos)             /*!< PWM_T::BRKCTL2_3: BRKP1LEN Mask           */
+
+#define PWM_BRKCTL2_3_SYSLBEN_Pos        (15)                                              /*!< PWM_T::BRKCTL2_3: SYSLBEN Position        */
+#define PWM_BRKCTL2_3_SYSLBEN_Msk        (0x1ul << PWM_BRKCTL2_3_SYSLBEN_Pos)              /*!< PWM_T::BRKCTL2_3: SYSLBEN Mask            */
+
+#define PWM_BRKCTL2_3_BRKAEVEN_Pos       (16)                                              /*!< PWM_T::BRKCTL2_3: BRKAEVEN Position       */
+#define PWM_BRKCTL2_3_BRKAEVEN_Msk       (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos)             /*!< PWM_T::BRKCTL2_3: BRKAEVEN Mask           */
+
+#define PWM_BRKCTL2_3_BRKAODD_Pos        (18)                                              /*!< PWM_T::BRKCTL2_3: BRKAODD Position        */
+#define PWM_BRKCTL2_3_BRKAODD_Msk        (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos)              /*!< PWM_T::BRKCTL2_3: BRKAODD Mask            */
+
+#define PWM_BRKCTL4_5_CPO0EBEN_Pos       (0)                                               /*!< PWM_T::BRKCTL4_5: CPO0EBEN Position       */
+#define PWM_BRKCTL4_5_CPO0EBEN_Msk       (0x1ul << PWM_BRKCTL4_5_CPO0EBEN_Pos)             /*!< PWM_T::BRKCTL4_5: CPO0EBEN Mask           */
+
+#define PWM_BRKCTL4_5_CPO1EBEN_Pos       (1)                                               /*!< PWM_T::BRKCTL4_5: CPO1EBEN Position       */
+#define PWM_BRKCTL4_5_CPO1EBEN_Msk       (0x1ul << PWM_BRKCTL4_5_CPO1EBEN_Pos)             /*!< PWM_T::BRKCTL4_5: CPO1EBEN Mask           */
+
+#define PWM_BRKCTL4_5_BRKP0EEN_Pos       (4)                                               /*!< PWM_T::BRKCTL4_5: BRKP0EEN Position       */
+#define PWM_BRKCTL4_5_BRKP0EEN_Msk       (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos)             /*!< PWM_T::BRKCTL4_5: BRKP0EEN Mask           */
+
+#define PWM_BRKCTL4_5_BRKP1EEN_Pos       (5)                                               /*!< PWM_T::BRKCTL4_5: BRKP1EEN Position       */
+#define PWM_BRKCTL4_5_BRKP1EEN_Msk       (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos)             /*!< PWM_T::BRKCTL4_5: BRKP1EEN Mask           */
+
+#define PWM_BRKCTL4_5_SYSEBEN_Pos        (7)                                               /*!< PWM_T::BRKCTL4_5: SYSEBEN Position        */
+#define PWM_BRKCTL4_5_SYSEBEN_Msk        (0x1ul << PWM_BRKCTL4_5_SYSEBEN_Pos)              /*!< PWM_T::BRKCTL4_5: SYSEBEN Mask            */
+
+#define PWM_BRKCTL4_5_CPO0LBEN_Pos       (8)                                               /*!< PWM_T::BRKCTL4_5: CPO0LBEN Position       */
+#define PWM_BRKCTL4_5_CPO0LBEN_Msk       (0x1ul << PWM_BRKCTL4_5_CPO0LBEN_Pos)             /*!< PWM_T::BRKCTL4_5: CPO0LBEN Mask           */
+
+#define PWM_BRKCTL4_5_CPO1LBEN_Pos       (9)                                               /*!< PWM_T::BRKCTL4_5: CPO1LBEN Position       */
+#define PWM_BRKCTL4_5_CPO1LBEN_Msk       (0x1ul << PWM_BRKCTL4_5_CPO1LBEN_Pos)             /*!< PWM_T::BRKCTL4_5: CPO1LBEN Mask           */
+
+#define PWM_BRKCTL4_5_BRKP0LEN_Pos       (12)                                              /*!< PWM_T::BRKCTL4_5: BRKP0LEN Position       */
+#define PWM_BRKCTL4_5_BRKP0LEN_Msk       (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos)             /*!< PWM_T::BRKCTL4_5: BRKP0LEN Mask           */
+
+#define PWM_BRKCTL4_5_BRKP1LEN_Pos       (13)                                              /*!< PWM_T::BRKCTL4_5: BRKP1LEN Position       */
+#define PWM_BRKCTL4_5_BRKP1LEN_Msk       (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos)             /*!< PWM_T::BRKCTL4_5: BRKP1LEN Mask           */
+
+#define PWM_BRKCTL4_5_SYSLBEN_Pos        (15)                                              /*!< PWM_T::BRKCTL4_5: SYSLBEN Position        */
+#define PWM_BRKCTL4_5_SYSLBEN_Msk        (0x1ul << PWM_BRKCTL4_5_SYSLBEN_Pos)              /*!< PWM_T::BRKCTL4_5: SYSLBEN Mask            */
+
+#define PWM_BRKCTL4_5_BRKAEVEN_Pos       (16)                                              /*!< PWM_T::BRKCTL4_5: BRKAEVEN Position       */
+#define PWM_BRKCTL4_5_BRKAEVEN_Msk       (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos)             /*!< PWM_T::BRKCTL4_5: BRKAEVEN Mask           */
+
+#define PWM_BRKCTL4_5_BRKAODD_Pos        (18)                                              /*!< PWM_T::BRKCTL4_5: BRKAODD Position        */
+#define PWM_BRKCTL4_5_BRKAODD_Msk        (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos)              /*!< PWM_T::BRKCTL4_5: BRKAODD Mask            */
+
+#define PWM_POLCTL_PINVn_Pos             (0)                                               /*!< PWM_T::POLCTL: PINVn Position             */
+#define PWM_POLCTL_PINVn_Msk             (0x3ful << PWM_POLCTL_PINVn_Pos)                  /*!< PWM_T::POLCTL: PINVn Mask                 */
+
+#define PWM_POLCTL_PINV0_Pos             (0)                                               /*!< PWM_T::POLCTL: PINV0 Position             */
+#define PWM_POLCTL_PINV0_Msk             (0x1ul << PWM_POLCTL_PINV0_Pos)                   /*!< PWM_T::POLCTL: PINV0 Mask                 */
+
+#define PWM_POLCTL_PINV1_Pos             (1)                                               /*!< PWM_T::POLCTL: PINV1 Position             */
+#define PWM_POLCTL_PINV1_Msk             (0x1ul << PWM_POLCTL_PINV1_Pos)                   /*!< PWM_T::POLCTL: PINV1 Mask                 */
+
+#define PWM_POLCTL_PINV2_Pos             (2)                                               /*!< PWM_T::POLCTL: PINV2 Position             */
+#define PWM_POLCTL_PINV2_Msk             (0x1ul << PWM_POLCTL_PINV2_Pos)                   /*!< PWM_T::POLCTL: PINV2 Mask                 */
+
+#define PWM_POLCTL_PINV3_Pos             (3)                                               /*!< PWM_T::POLCTL: PINV3 Position             */
+#define PWM_POLCTL_PINV3_Msk             (0x1ul << PWM_POLCTL_PINV3_Pos)                   /*!< PWM_T::POLCTL: PINV3 Mask                 */
+
+#define PWM_POLCTL_PINV4_Pos             (4)                                               /*!< PWM_T::POLCTL: PINV4 Position             */
+#define PWM_POLCTL_PINV4_Msk             (0x1ul << PWM_POLCTL_PINV4_Pos)                   /*!< PWM_T::POLCTL: PINV4 Mask                 */
+
+#define PWM_POLCTL_PINV5_Pos             (5)                                               /*!< PWM_T::POLCTL: PINV5 Position             */
+#define PWM_POLCTL_PINV5_Msk             (0x1ul << PWM_POLCTL_PINV5_Pos)                   /*!< PWM_T::POLCTL: PINV5 Mask                 */
+
+#define PWM_POEN_POENn_Pos               (0)                                               /*!< PWM_T::POEN: POENn Position               */
+#define PWM_POEN_POENn_Msk               (0x3ful << PWM_POEN_POENn_Pos)                    /*!< PWM_T::POEN: POENn Mask                   */
+
+#define PWM_POEN_POEN0_Pos               (0)                                               /*!< PWM_T::POEN: POEN0 Position               */
+#define PWM_POEN_POEN0_Msk               (0x1ul << PWM_POEN_POEN0_Pos)                     /*!< PWM_T::POEN: POEN0 Mask                   */
+
+#define PWM_POEN_POEN1_Pos               (1)                                               /*!< PWM_T::POEN: POEN1 Position               */
+#define PWM_POEN_POEN1_Msk               (0x1ul << PWM_POEN_POEN1_Pos)                     /*!< PWM_T::POEN: POEN1 Mask                   */
+
+#define PWM_POEN_POEN2_Pos               (2)                                               /*!< PWM_T::POEN: POEN2 Position               */
+#define PWM_POEN_POEN2_Msk               (0x1ul << PWM_POEN_POEN2_Pos)                     /*!< PWM_T::POEN: POEN2 Mask                   */
+
+#define PWM_POEN_POEN3_Pos               (3)                                               /*!< PWM_T::POEN: POEN3 Position               */
+#define PWM_POEN_POEN3_Msk               (0x1ul << PWM_POEN_POEN3_Pos)                     /*!< PWM_T::POEN: POEN3 Mask                   */
+
+#define PWM_POEN_POEN4_Pos               (4)                                               /*!< PWM_T::POEN: POEN4 Position               */
+#define PWM_POEN_POEN4_Msk               (0x1ul << PWM_POEN_POEN4_Pos)                     /*!< PWM_T::POEN: POEN4 Mask                   */
+
+#define PWM_POEN_POEN5_Pos               (5)                                               /*!< PWM_T::POEN: POEN5 Position               */
+#define PWM_POEN_POEN5_Msk               (0x1ul << PWM_POEN_POEN5_Pos)                     /*!< PWM_T::POEN: POEN5 Mask                   */
+
+#define PWM_SWBRK_BRKETRGn_Pos           (0)                                               /*!< PWM_T::SWBRK: BRKETRGn Position           */
+#define PWM_SWBRK_BRKETRGn_Msk           (0x7ul << PWM_SWBRK_BRKETRGn_Pos)                 /*!< PWM_T::SWBRK: BRKETRGn Mask               */
+
+#define PWM_SWBRK_BRKETRG0_Pos           (0)                                               /*!< PWM_T::SWBRK: BRKETRG0 Position           */
+#define PWM_SWBRK_BRKETRG0_Msk           (0x1ul << PWM_SWBRK_BRKETRG0_Pos)                 /*!< PWM_T::SWBRK: BRKETRG0 Mask               */
+
+#define PWM_SWBRK_BRKETRG2_Pos           (1)                                               /*!< PWM_T::SWBRK: BRKETRG2 Position           */
+#define PWM_SWBRK_BRKETRG2_Msk           (0x1ul << PWM_SWBRK_BRKETRG2_Pos)                 /*!< PWM_T::SWBRK: BRKETRG2 Mask               */
+
+#define PWM_SWBRK_BRKETRG4_Pos           (2)                                               /*!< PWM_T::SWBRK: BRKETRG4 Position           */
+#define PWM_SWBRK_BRKETRG4_Msk           (0x1ul << PWM_SWBRK_BRKETRG4_Pos)                 /*!< PWM_T::SWBRK: BRKETRG4 Mask               */
+
+#define PWM_SWBRK_BRKLTRGn_Pos           (8)                                               /*!< PWM_T::SWBRK: BRKLTRGn Position           */
+#define PWM_SWBRK_BRKLTRGn_Msk           (0x7ul << PWM_SWBRK_BRKLTRGn_Pos)                 /*!< PWM_T::SWBRK: BRKLTRGn Mask               */
+
+#define PWM_SWBRK_BRKLTRG0_Pos           (8)                                               /*!< PWM_T::SWBRK: BRKLTRG0 Position           */
+#define PWM_SWBRK_BRKLTRG0_Msk           (0x1ul << PWM_SWBRK_BRKLTRG0_Pos)                 /*!< PWM_T::SWBRK: BRKLTRG0 Mask               */
+
+#define PWM_SWBRK_BRKLTRG2_Pos           (9)                                               /*!< PWM_T::SWBRK: BRKLTRG2 Position           */
+#define PWM_SWBRK_BRKLTRG2_Msk           (0x1ul << PWM_SWBRK_BRKLTRG2_Pos)                 /*!< PWM_T::SWBRK: BRKLTRG2 Mask               */
+
+#define PWM_SWBRK_BRKLTRG4_Pos           (10)                                              /*!< PWM_T::SWBRK: BRKLTRG4 Position           */
+#define PWM_SWBRK_BRKLTRG4_Msk           (0x1ul << PWM_SWBRK_BRKLTRG4_Pos)                 /*!< PWM_T::SWBRK: BRKLTRG4 Mask               */
+
+#define PWM_INTEN0_ZIENn_Pos             (0)                                               /*!< PWM_T::INTEN0: ZIENn Position             */
+#define PWM_INTEN0_ZIENn_Msk             (0x3ful << PWM_INTEN0_ZIENn_Pos)                  /*!< PWM_T::INTEN0: ZIENn Mask                 */
+
+#define PWM_INTEN0_ZIEN0_Pos             (0)                                               /*!< PWM_T::INTEN0: ZIEN0 Position             */
+#define PWM_INTEN0_ZIEN0_Msk             (0x1ul << PWM_INTEN0_ZIEN0_Pos)                   /*!< PWM_T::INTEN0: ZIEN0 Mask                 */
+
+#define PWM_INTEN0_ZIEN1_Pos             (1)                                               /*!< PWM_T::INTEN0: ZIEN1 Position             */
+#define PWM_INTEN0_ZIEN1_Msk             (0x1ul << PWM_INTEN0_ZIEN1_Pos)                   /*!< PWM_T::INTEN0: ZIEN1 Mask                 */
+
+#define PWM_INTEN0_ZIEN2_Pos             (2)                                               /*!< PWM_T::INTEN0: ZIEN2 Position             */
+#define PWM_INTEN0_ZIEN2_Msk             (0x1ul << PWM_INTEN0_ZIEN2_Pos)                   /*!< PWM_T::INTEN0: ZIEN2 Mask                 */
+
+#define PWM_INTEN0_ZIEN3_Pos             (3)                                               /*!< PWM_T::INTEN0: ZIEN3 Position             */
+#define PWM_INTEN0_ZIEN3_Msk             (0x1ul << PWM_INTEN0_ZIEN3_Pos)                   /*!< PWM_T::INTEN0: ZIEN3 Mask                 */
+
+#define PWM_INTEN0_ZIEN4_Pos             (4)                                               /*!< PWM_T::INTEN0: ZIEN4 Position             */
+#define PWM_INTEN0_ZIEN4_Msk             (0x1ul << PWM_INTEN0_ZIEN4_Pos)                   /*!< PWM_T::INTEN0: ZIEN4 Mask                 */
+
+#define PWM_INTEN0_ZIEN5_Pos             (5)                                               /*!< PWM_T::INTEN0: ZIEN5 Position             */
+#define PWM_INTEN0_ZIEN5_Msk             (0x1ul << PWM_INTEN0_ZIEN5_Pos)                   /*!< PWM_T::INTEN0: ZIEN5 Mask                 */
+
+#define PWM_INTEN0_IFAIEN0_1_Pos         (7)                                               /*!< PWM_T::INTEN0: IFAIEN0_1 Position         */
+#define PWM_INTEN0_IFAIEN0_1_Msk         (0x1ul << PWM_INTEN0_IFAIEN0_1_Pos)               /*!< PWM_T::INTEN0: IFAIEN0_1 Mask             */
+
+#define PWM_INTEN0_PIENn_Pos             (8)                                               /*!< PWM_T::INTEN0: PIENn Position             */
+#define PWM_INTEN0_PIENn_Msk             (0x3ful << PWM_INTEN0_PIENn_Pos)                  /*!< PWM_T::INTEN0: PIENn Mask                 */
+
+#define PWM_INTEN0_PIEN0_Pos             (8)                                               /*!< PWM_T::INTEN0: PIEN0 Position             */
+#define PWM_INTEN0_PIEN0_Msk             (0x1ul << PWM_INTEN0_PIEN0_Pos)                   /*!< PWM_T::INTEN0: PIEN0 Mask                 */
+
+#define PWM_INTEN0_PIEN1_Pos             (9)                                               /*!< PWM_T::INTEN0: PIEN1 Position             */
+#define PWM_INTEN0_PIEN1_Msk             (0x1ul << PWM_INTEN0_PIEN1_Pos)                   /*!< PWM_T::INTEN0: PIEN1 Mask                 */
+
+#define PWM_INTEN0_PIEN2_Pos             (10)                                              /*!< PWM_T::INTEN0: PIEN2 Position             */
+#define PWM_INTEN0_PIEN2_Msk             (0x1ul << PWM_INTEN0_PIEN2_Pos)                   /*!< PWM_T::INTEN0: PIEN2 Mask                 */
+
+#define PWM_INTEN0_PIEN3_Pos             (11)                                              /*!< PWM_T::INTEN0: PIEN3 Position             */
+#define PWM_INTEN0_PIEN3_Msk             (0x1ul << PWM_INTEN0_PIEN3_Pos)                   /*!< PWM_T::INTEN0: PIEN3 Mask                 */
+
+#define PWM_INTEN0_PIEN4_Pos             (12)                                              /*!< PWM_T::INTEN0: PIEN4 Position             */
+#define PWM_INTEN0_PIEN4_Msk             (0x1ul << PWM_INTEN0_PIEN4_Pos)                   /*!< PWM_T::INTEN0: PIEN4 Mask                 */
+
+#define PWM_INTEN0_PIEN5_Pos             (13)                                              /*!< PWM_T::INTEN0: PIEN5 Position             */
+#define PWM_INTEN0_PIEN5_Msk             (0x1ul << PWM_INTEN0_PIEN5_Pos)                   /*!< PWM_T::INTEN0: PIEN5 Mask                 */
+
+#define PWM_INTEN0_IFAIEN2_3_Pos         (15)                                              /*!< PWM_T::INTEN0: IFAIEN2_3 Position         */
+#define PWM_INTEN0_IFAIEN2_3_Msk         (0x1ul << PWM_INTEN0_IFAIEN2_3_Pos)               /*!< PWM_T::INTEN0: IFAIEN2_3 Mask             */
+
+#define PWM_INTEN0_CMPUIENn_Pos          (16)                                              /*!< PWM_T::INTEN0: CMPUIENn Position          */
+#define PWM_INTEN0_CMPUIENn_Msk          (0x3ful << PWM_INTEN0_CMPUIENn_Pos)               /*!< PWM_T::INTEN0: CMPUIENn Mask              */
+
+#define PWM_INTEN0_CMPUIEN0_Pos          (16)                                              /*!< PWM_T::INTEN0: CMPUIEN0 Position          */
+#define PWM_INTEN0_CMPUIEN0_Msk          (0x1ul << PWM_INTEN0_CMPUIEN0_Pos)                /*!< PWM_T::INTEN0: CMPUIEN0 Mask              */
+
+#define PWM_INTEN0_CMPUIEN1_Pos          (17)                                              /*!< PWM_T::INTEN0: CMPUIEN1 Position          */
+#define PWM_INTEN0_CMPUIEN1_Msk          (0x1ul << PWM_INTEN0_CMPUIEN1_Pos)                /*!< PWM_T::INTEN0: CMPUIEN1 Mask              */
+
+#define PWM_INTEN0_CMPUIEN2_Pos          (18)                                              /*!< PWM_T::INTEN0: CMPUIEN2 Position          */
+#define PWM_INTEN0_CMPUIEN2_Msk          (0x1ul << PWM_INTEN0_CMPUIEN2_Pos)                /*!< PWM_T::INTEN0: CMPUIEN2 Mask              */
+
+#define PWM_INTEN0_CMPUIEN3_Pos          (19)                                              /*!< PWM_T::INTEN0: CMPUIEN3 Position          */
+#define PWM_INTEN0_CMPUIEN3_Msk          (0x1ul << PWM_INTEN0_CMPUIEN3_Pos)                /*!< PWM_T::INTEN0: CMPUIEN3 Mask              */
+
+#define PWM_INTEN0_CMPUIEN4_Pos          (20)                                              /*!< PWM_T::INTEN0: CMPUIEN4 Position          */
+#define PWM_INTEN0_CMPUIEN4_Msk          (0x1ul << PWM_INTEN0_CMPUIEN4_Pos)                /*!< PWM_T::INTEN0: CMPUIEN4 Mask              */
+
+#define PWM_INTEN0_CMPUIEN5_Pos          (21)                                              /*!< PWM_T::INTEN0: CMPUIEN5 Position          */
+#define PWM_INTEN0_CMPUIEN5_Msk          (0x1ul << PWM_INTEN0_CMPUIEN5_Pos)                /*!< PWM_T::INTEN0: CMPUIEN5 Mask              */
+
+#define PWM_INTEN0_IFAIEN4_5_Pos         (23)                                              /*!< PWM_T::INTEN0: IFAIEN4_5 Position         */
+#define PWM_INTEN0_IFAIEN4_5_Msk         (0x1ul << PWM_INTEN0_IFAIEN4_5_Pos)               /*!< PWM_T::INTEN0: IFAIEN4_5 Mask             */
+
+#define PWM_INTEN0_CMPDIENn_Pos          (24)                                              /*!< PWM_T::INTEN0: CMPDIENn Position          */
+#define PWM_INTEN0_CMPDIENn_Msk          (0x3ful << PWM_INTEN0_CMPDIENn_Pos)               /*!< PWM_T::INTEN0: CMPDIENn Mask              */
+
+#define PWM_INTEN0_CMPDIEN0_Pos          (24)                                              /*!< PWM_T::INTEN0: CMPDIEN0 Position          */
+#define PWM_INTEN0_CMPDIEN0_Msk          (0x1ul << PWM_INTEN0_CMPDIEN0_Pos)                /*!< PWM_T::INTEN0: CMPDIEN0 Mask              */
+
+#define PWM_INTEN0_CMPDIEN1_Pos          (25)                                              /*!< PWM_T::INTEN0: CMPDIEN1 Position          */
+#define PWM_INTEN0_CMPDIEN1_Msk          (0x1ul << PWM_INTEN0_CMPDIEN1_Pos)                /*!< PWM_T::INTEN0: CMPDIEN1 Mask              */
+
+#define PWM_INTEN0_CMPDIEN2_Pos          (26)                                              /*!< PWM_T::INTEN0: CMPDIEN2 Position          */
+#define PWM_INTEN0_CMPDIEN2_Msk          (0x1ul << PWM_INTEN0_CMPDIEN2_Pos)                /*!< PWM_T::INTEN0: CMPDIEN2 Mask              */
+
+#define PWM_INTEN0_CMPDIEN3_Pos          (27)                                              /*!< PWM_T::INTEN0: CMPDIEN3 Position          */
+#define PWM_INTEN0_CMPDIEN3_Msk          (0x1ul << PWM_INTEN0_CMPDIEN3_Pos)                /*!< PWM_T::INTEN0: CMPDIEN3 Mask              */
+
+#define PWM_INTEN0_CMPDIEN4_Pos          (28)                                              /*!< PWM_T::INTEN0: CMPDIEN4 Position          */
+#define PWM_INTEN0_CMPDIEN4_Msk          (0x1ul << PWM_INTEN0_CMPDIEN4_Pos)                /*!< PWM_T::INTEN0: CMPDIEN4 Mask              */
+
+#define PWM_INTEN0_CMPDIEN5_Pos          (29)                                              /*!< PWM_T::INTEN0: CMPDIEN5 Position          */
+#define PWM_INTEN0_CMPDIEN5_Msk          (0x1ul << PWM_INTEN0_CMPDIEN5_Pos)                /*!< PWM_T::INTEN0: CMPDIEN5 Mask              */
+
+#define PWM_INTEN1_BRKEIEN0_1_Pos        (0)                                               /*!< PWM_T::INTEN1: BRKEIEN0_1 Position        */
+#define PWM_INTEN1_BRKEIEN0_1_Msk        (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos)              /*!< PWM_T::INTEN1: BRKEIEN0_1 Mask            */
+
+#define PWM_INTEN1_BRKEIEN2_3_Pos        (1)                                               /*!< PWM_T::INTEN1: BRKEIEN2_3 Position        */
+#define PWM_INTEN1_BRKEIEN2_3_Msk        (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos)              /*!< PWM_T::INTEN1: BRKEIEN2_3 Mask            */
+
+#define PWM_INTEN1_BRKEIEN4_5_Pos        (2)                                               /*!< PWM_T::INTEN1: BRKEIEN4_5 Position        */
+#define PWM_INTEN1_BRKEIEN4_5_Msk        (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos)              /*!< PWM_T::INTEN1: BRKEIEN4_5 Mask            */
+
+#define PWM_INTEN1_BRKLIEN0_1_Pos        (8)                                               /*!< PWM_T::INTEN1: BRKLIEN0_1 Position        */
+#define PWM_INTEN1_BRKLIEN0_1_Msk        (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos)              /*!< PWM_T::INTEN1: BRKLIEN0_1 Mask            */
+
+#define PWM_INTEN1_BRKLIEN2_3_Pos        (9)                                               /*!< PWM_T::INTEN1: BRKLIEN2_3 Position        */
+#define PWM_INTEN1_BRKLIEN2_3_Msk        (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos)              /*!< PWM_T::INTEN1: BRKLIEN2_3 Mask            */
+
+#define PWM_INTEN1_BRKLIEN4_5_Pos        (10)                                              /*!< PWM_T::INTEN1: BRKLIEN4_5 Position        */
+#define PWM_INTEN1_BRKLIEN4_5_Msk        (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos)              /*!< PWM_T::INTEN1: BRKLIEN4_5 Mask            */
+
+#define PWM_INTSTS0_ZIFn_Pos             (0)                                               /*!< PWM_T::INTSTS0: ZIFn Position             */
+#define PWM_INTSTS0_ZIFn_Msk             (0x3ful << PWM_INTSTS0_ZIFn_Pos)                  /*!< PWM_T::INTSTS0: ZIFn Mask                 */
+
+#define PWM_INTSTS0_ZIF0_Pos             (0)                                               /*!< PWM_T::INTSTS0: ZIF0 Position             */
+#define PWM_INTSTS0_ZIF0_Msk             (0x1ul << PWM_INTSTS0_ZIF0_Pos)                   /*!< PWM_T::INTSTS0: ZIF0 Mask                 */
+
+#define PWM_INTSTS0_ZIF1_Pos             (1)                                               /*!< PWM_T::INTSTS0: ZIF1 Position             */
+#define PWM_INTSTS0_ZIF1_Msk             (0x1ul << PWM_INTSTS0_ZIF1_Pos)                   /*!< PWM_T::INTSTS0: ZIF1 Mask                 */
+
+#define PWM_INTSTS0_ZIF2_Pos             (2)                                               /*!< PWM_T::INTSTS0: ZIF2 Position             */
+#define PWM_INTSTS0_ZIF2_Msk             (0x1ul << PWM_INTSTS0_ZIF2_Pos)                   /*!< PWM_T::INTSTS0: ZIF2 Mask                 */
+
+#define PWM_INTSTS0_ZIF3_Pos             (3)                                               /*!< PWM_T::INTSTS0: ZIF3 Position             */
+#define PWM_INTSTS0_ZIF3_Msk             (0x1ul << PWM_INTSTS0_ZIF3_Pos)                   /*!< PWM_T::INTSTS0: ZIF3 Mask                 */
+
+#define PWM_INTSTS0_ZIF4_Pos             (4)                                               /*!< PWM_T::INTSTS0: ZIF4 Position             */
+#define PWM_INTSTS0_ZIF4_Msk             (0x1ul << PWM_INTSTS0_ZIF4_Pos)                   /*!< PWM_T::INTSTS0: ZIF4 Mask                 */
+
+#define PWM_INTSTS0_ZIF5_Pos             (5)                                               /*!< PWM_T::INTSTS0: ZIF5 Position             */
+#define PWM_INTSTS0_ZIF5_Msk             (0x1ul << PWM_INTSTS0_ZIF5_Pos)                   /*!< PWM_T::INTSTS0: ZIF5 Mask                 */
+
+#define PWM_INTSTS0_IFAIF0_1_Pos         (7)                                               /*!< PWM_T::INTSTS0: IFAIF0_1 Position         */
+#define PWM_INTSTS0_IFAIF0_1_Msk         (0x1ul << PWM_INTSTS0_IFAIF0_1_Pos)               /*!< PWM_T::INTSTS0: IFAIF0_1 Mask             */
+
+#define PWM_INTSTS0_PIFn_Pos             (8)                                               /*!< PWM_T::INTSTS0: PIFn Position             */
+#define PWM_INTSTS0_PIFn_Msk             (0x3ful << PWM_INTSTS0_PIFn_Pos)                  /*!< PWM_T::INTSTS0: PIFn Mask                 */
+
+#define PWM_INTSTS0_PIF0_Pos             (8)                                               /*!< PWM_T::INTSTS0: PIF0 Position             */
+#define PWM_INTSTS0_PIF0_Msk             (0x1ul << PWM_INTSTS0_PIF0_Pos)                   /*!< PWM_T::INTSTS0: PIF0 Mask                 */
+
+#define PWM_INTSTS0_PIF1_Pos             (9)                                               /*!< PWM_T::INTSTS0: PIF1 Position             */
+#define PWM_INTSTS0_PIF1_Msk             (0x1ul << PWM_INTSTS0_PIF1_Pos)                   /*!< PWM_T::INTSTS0: PIF1 Mask                 */
+
+#define PWM_INTSTS0_PIF2_Pos             (10)                                              /*!< PWM_T::INTSTS0: PIF2 Position             */
+#define PWM_INTSTS0_PIF2_Msk             (0x1ul << PWM_INTSTS0_PIF2_Pos)                   /*!< PWM_T::INTSTS0: PIF2 Mask                 */
+
+#define PWM_INTSTS0_PIF3_Pos             (11)                                              /*!< PWM_T::INTSTS0: PIF3 Position             */
+#define PWM_INTSTS0_PIF3_Msk             (0x1ul << PWM_INTSTS0_PIF3_Pos)                   /*!< PWM_T::INTSTS0: PIF3 Mask                 */
+
+#define PWM_INTSTS0_PIF4_Pos             (12)                                              /*!< PWM_T::INTSTS0: PIF4 Position             */
+#define PWM_INTSTS0_PIF4_Msk             (0x1ul << PWM_INTSTS0_PIF4_Pos)                   /*!< PWM_T::INTSTS0: PIF4 Mask                 */
+
+#define PWM_INTSTS0_PIF5_Pos             (13)                                              /*!< PWM_T::INTSTS0: PIF5 Position             */
+#define PWM_INTSTS0_PIF5_Msk             (0x1ul << PWM_INTSTS0_PIF5_Pos)                   /*!< PWM_T::INTSTS0: PIF5 Mask                 */
+
+#define PWM_INTSTS0_IFAIF2_3_Pos         (15)                                              /*!< PWM_T::INTSTS0: IFAIF2_3 Position         */
+#define PWM_INTSTS0_IFAIF2_3_Msk         (0x1ul << PWM_INTSTS0_IFAIF2_3_Pos)               /*!< PWM_T::INTSTS0: IFAIF2_3 Mask             */
+
+#define PWM_INTSTS0_CMPUIFn_Pos          (16)                                              /*!< PWM_T::INTSTS0: CMPUIFn Position          */
+#define PWM_INTSTS0_CMPUIFn_Msk          (0x3ful << PWM_INTSTS0_CMPUIFn_Pos)               /*!< PWM_T::INTSTS0: CMPUIFn Mask              */
+
+#define PWM_INTSTS0_CMPUIF0_Pos          (16)                                              /*!< PWM_T::INTSTS0: CMPUIF0 Position          */
+#define PWM_INTSTS0_CMPUIF0_Msk          (0x1ul << PWM_INTSTS0_CMPUIF0_Pos)                /*!< PWM_T::INTSTS0: CMPUIF0 Mask              */
+
+#define PWM_INTSTS0_CMPUIF1_Pos          (17)                                              /*!< PWM_T::INTSTS0: CMPUIF1 Position          */
+#define PWM_INTSTS0_CMPUIF1_Msk          (0x1ul << PWM_INTSTS0_CMPUIF1_Pos)                /*!< PWM_T::INTSTS0: CMPUIF1 Mask              */
+
+#define PWM_INTSTS0_CMPUIF2_Pos          (18)                                              /*!< PWM_T::INTSTS0: CMPUIF2 Position          */
+#define PWM_INTSTS0_CMPUIF2_Msk          (0x1ul << PWM_INTSTS0_CMPUIF2_Pos)                /*!< PWM_T::INTSTS0: CMPUIF2 Mask              */
+
+#define PWM_INTSTS0_CMPUIF3_Pos          (19)                                              /*!< PWM_T::INTSTS0: CMPUIF3 Position          */
+#define PWM_INTSTS0_CMPUIF3_Msk          (0x1ul << PWM_INTSTS0_CMPUIF3_Pos)                /*!< PWM_T::INTSTS0: CMPUIF3 Mask              */
+
+#define PWM_INTSTS0_CMPUIF4_Pos          (20)                                              /*!< PWM_T::INTSTS0: CMPUIF4 Position          */
+#define PWM_INTSTS0_CMPUIF4_Msk          (0x1ul << PWM_INTSTS0_CMPUIF4_Pos)                /*!< PWM_T::INTSTS0: CMPUIF4 Mask              */
+
+#define PWM_INTSTS0_CMPUIF5_Pos          (21)                                              /*!< PWM_T::INTSTS0: CMPUIF5 Position          */
+#define PWM_INTSTS0_CMPUIF5_Msk          (0x1ul << PWM_INTSTS0_CMPUIF5_Pos)                /*!< PWM_T::INTSTS0: CMPUIF5 Mask              */
+
+#define PWM_INTSTS0_IFAIF4_5_Pos         (23)                                              /*!< PWM_T::INTSTS0: IFAIF4_5 Position         */
+#define PWM_INTSTS0_IFAIF4_5_Msk         (0x1ul << PWM_INTSTS0_IFAIF4_5_Pos)               /*!< PWM_T::INTSTS0: IFAIF4_5 Mask             */
+
+#define PWM_INTSTS0_CMPDIFn_Pos          (24)                                              /*!< PWM_T::INTSTS0: CMPDIFn Position          */
+#define PWM_INTSTS0_CMPDIFn_Msk          (0x3ful << PWM_INTSTS0_CMPDIFn_Pos)               /*!< PWM_T::INTSTS0: CMPDIFn Mask              */
+
+#define PWM_INTSTS0_CMPDIF0_Pos          (24)                                              /*!< PWM_T::INTSTS0: CMPDIF0 Position          */
+#define PWM_INTSTS0_CMPDIF0_Msk          (0x1ul << PWM_INTSTS0_CMPDIF0_Pos)                /*!< PWM_T::INTSTS0: CMPDIF0 Mask              */
+
+#define PWM_INTSTS0_CMPDIF1_Pos          (25)                                              /*!< PWM_T::INTSTS0: CMPDIF1 Position          */
+#define PWM_INTSTS0_CMPDIF1_Msk          (0x1ul << PWM_INTSTS0_CMPDIF1_Pos)                /*!< PWM_T::INTSTS0: CMPDIF1 Mask              */
+
+#define PWM_INTSTS0_CMPDIF2_Pos          (26)                                              /*!< PWM_T::INTSTS0: CMPDIF2 Position          */
+#define PWM_INTSTS0_CMPDIF2_Msk          (0x1ul << PWM_INTSTS0_CMPDIF2_Pos)                /*!< PWM_T::INTSTS0: CMPDIF2 Mask              */
+
+#define PWM_INTSTS0_CMPDIF3_Pos          (27)                                              /*!< PWM_T::INTSTS0: CMPDIF3 Position          */
+#define PWM_INTSTS0_CMPDIF3_Msk          (0x1ul << PWM_INTSTS0_CMPDIF3_Pos)                /*!< PWM_T::INTSTS0: CMPDIF3 Mask              */
+
+#define PWM_INTSTS0_CMPDIF4_Pos          (28)                                              /*!< PWM_T::INTSTS0: CMPDIF4 Position          */
+#define PWM_INTSTS0_CMPDIF4_Msk          (0x1ul << PWM_INTSTS0_CMPDIF4_Pos)                /*!< PWM_T::INTSTS0: CMPDIF4 Mask              */
+
+#define PWM_INTSTS0_CMPDIF5_Pos          (29)                                              /*!< PWM_T::INTSTS0: CMPDIF5 Position          */
+#define PWM_INTSTS0_CMPDIF5_Msk          (0x1ul << PWM_INTSTS0_CMPDIF5_Pos)                /*!< PWM_T::INTSTS0: CMPDIF5 Mask              */
+
+#define PWM_INTSTS1_BRKEIFn_Pos          (0)                                               /*!< PWM_T::INTSTS1: BRKEIFn Position          */
+#define PWM_INTSTS1_BRKEIFn_Msk          (0x3ful << PWM_INTSTS1_BRKEIFn_Pos)               /*!< PWM_T::INTSTS1: BRKEIFn Mask              */
+
+#define PWM_INTSTS1_BRKEIF0_Pos          (0)                                               /*!< PWM_T::INTSTS1: BRKEIF0 Position          */
+#define PWM_INTSTS1_BRKEIF0_Msk          (0x1ul << PWM_INTSTS1_BRKEIF0_Pos)                /*!< PWM_T::INTSTS1: BRKEIF0 Mask              */
+
+#define PWM_INTSTS1_BRKEIF1_Pos          (1)                                               /*!< PWM_T::INTSTS1: BRKEIF1 Position          */
+#define PWM_INTSTS1_BRKEIF1_Msk          (0x1ul << PWM_INTSTS1_BRKEIF1_Pos)                /*!< PWM_T::INTSTS1: BRKEIF1 Mask              */
+
+#define PWM_INTSTS1_BRKEIF2_Pos          (2)                                               /*!< PWM_T::INTSTS1: BRKEIF2 Position          */
+#define PWM_INTSTS1_BRKEIF2_Msk          (0x1ul << PWM_INTSTS1_BRKEIF2_Pos)                /*!< PWM_T::INTSTS1: BRKEIF2 Mask              */
+
+#define PWM_INTSTS1_BRKEIF3_Pos          (3)                                               /*!< PWM_T::INTSTS1: BRKEIF3 Position          */
+#define PWM_INTSTS1_BRKEIF3_Msk          (0x1ul << PWM_INTSTS1_BRKEIF3_Pos)                /*!< PWM_T::INTSTS1: BRKEIF3 Mask              */
+
+#define PWM_INTSTS1_BRKEIF4_Pos          (4)                                               /*!< PWM_T::INTSTS1: BRKEIF4 Position          */
+#define PWM_INTSTS1_BRKEIF4_Msk          (0x1ul << PWM_INTSTS1_BRKEIF4_Pos)                /*!< PWM_T::INTSTS1: BRKEIF4 Mask              */
+
+#define PWM_INTSTS1_BRKEIF5_Pos          (5)                                               /*!< PWM_T::INTSTS1: BRKEIF5 Position          */
+#define PWM_INTSTS1_BRKEIF5_Msk          (0x1ul << PWM_INTSTS1_BRKEIF5_Pos)                /*!< PWM_T::INTSTS1: BRKEIF5 Mask              */
+
+#define PWM_INTSTS1_BRKLIFn_Pos          (8)                                               /*!< PWM_T::INTSTS1: BRKLIFn Position          */
+#define PWM_INTSTS1_BRKLIFn_Msk          (0x3ful << PWM_INTSTS1_BRKLIFn_Pos)               /*!< PWM_T::INTSTS1: BRKLIFn Mask              */
+
+#define PWM_INTSTS1_BRKLIF0_Pos          (8)                                               /*!< PWM_T::INTSTS1: BRKLIF0 Position          */
+#define PWM_INTSTS1_BRKLIF0_Msk          (0x1ul << PWM_INTSTS1_BRKLIF0_Pos)                /*!< PWM_T::INTSTS1: BRKLIF0 Mask              */
+
+#define PWM_INTSTS1_BRKLIF1_Pos          (9)                                               /*!< PWM_T::INTSTS1: BRKLIF1 Position          */
+#define PWM_INTSTS1_BRKLIF1_Msk          (0x1ul << PWM_INTSTS1_BRKLIF1_Pos)                /*!< PWM_T::INTSTS1: BRKLIF1 Mask              */
+
+#define PWM_INTSTS1_BRKLIF2_Pos          (10)                                              /*!< PWM_T::INTSTS1: BRKLIF2 Position          */
+#define PWM_INTSTS1_BRKLIF2_Msk          (0x1ul << PWM_INTSTS1_BRKLIF2_Pos)                /*!< PWM_T::INTSTS1: BRKLIF2 Mask              */
+
+#define PWM_INTSTS1_BRKLIF3_Pos          (11)                                              /*!< PWM_T::INTSTS1: BRKLIF3 Position          */
+#define PWM_INTSTS1_BRKLIF3_Msk          (0x1ul << PWM_INTSTS1_BRKLIF3_Pos)                /*!< PWM_T::INTSTS1: BRKLIF3 Mask              */
+
+#define PWM_INTSTS1_BRKLIF4_Pos          (12)                                              /*!< PWM_T::INTSTS1: BRKLIF4 Position          */
+#define PWM_INTSTS1_BRKLIF4_Msk          (0x1ul << PWM_INTSTS1_BRKLIF4_Pos)                /*!< PWM_T::INTSTS1: BRKLIF4 Mask              */
+
+#define PWM_INTSTS1_BRKLIF5_Pos          (13)                                              /*!< PWM_T::INTSTS1: BRKLIF5 Position          */
+#define PWM_INTSTS1_BRKLIF5_Msk          (0x1ul << PWM_INTSTS1_BRKLIF5_Pos)                /*!< PWM_T::INTSTS1: BRKLIF5 Mask              */
+
+#define PWM_INTSTS1_BRKESTS0_Pos         (16)                                              /*!< PWM_T::INTSTS1: BRKESTS0 Position         */
+#define PWM_INTSTS1_BRKESTS0_Msk         (0x1ul << PWM_INTSTS1_BRKESTS0_Pos)               /*!< PWM_T::INTSTS1: BRKESTS0 Mask             */
+
+#define PWM_INTSTS1_BRKESTS1_Pos         (17)                                              /*!< PWM_T::INTSTS1: BRKESTS1 Position         */
+#define PWM_INTSTS1_BRKESTS1_Msk         (0x1ul << PWM_INTSTS1_BRKESTS1_Pos)               /*!< PWM_T::INTSTS1: BRKESTS1 Mask             */
+
+#define PWM_INTSTS1_BRKESTS2_Pos         (18)                                              /*!< PWM_T::INTSTS1: BRKESTS2 Position         */
+#define PWM_INTSTS1_BRKESTS2_Msk         (0x1ul << PWM_INTSTS1_BRKESTS2_Pos)               /*!< PWM_T::INTSTS1: BRKESTS2 Mask             */
+
+#define PWM_INTSTS1_BRKESTS3_Pos         (19)                                              /*!< PWM_T::INTSTS1: BRKESTS3 Position         */
+#define PWM_INTSTS1_BRKESTS3_Msk         (0x1ul << PWM_INTSTS1_BRKESTS3_Pos)               /*!< PWM_T::INTSTS1: BRKESTS3 Mask             */
+
+#define PWM_INTSTS1_BRKESTS4_Pos         (20)                                              /*!< PWM_T::INTSTS1: BRKESTS4 Position         */
+#define PWM_INTSTS1_BRKESTS4_Msk         (0x1ul << PWM_INTSTS1_BRKESTS4_Pos)               /*!< PWM_T::INTSTS1: BRKESTS4 Mask             */
+
+#define PWM_INTSTS1_BRKESTS5_Pos         (21)                                              /*!< PWM_T::INTSTS1: BRKESTS5 Position         */
+#define PWM_INTSTS1_BRKESTS5_Msk         (0x1ul << PWM_INTSTS1_BRKESTS5_Pos)               /*!< PWM_T::INTSTS1: BRKESTS5 Mask             */
+
+#define PWM_INTSTS1_BRKLSTS0_Pos         (24)                                              /*!< PWM_T::INTSTS1: BRKLSTS0 Position         */
+#define PWM_INTSTS1_BRKLSTS0_Msk         (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos)               /*!< PWM_T::INTSTS1: BRKLSTS0 Mask             */
+
+#define PWM_INTSTS1_BRKLSTS1_Pos         (25)                                              /*!< PWM_T::INTSTS1: BRKLSTS1 Position         */
+#define PWM_INTSTS1_BRKLSTS1_Msk         (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos)               /*!< PWM_T::INTSTS1: BRKLSTS1 Mask             */
+
+#define PWM_INTSTS1_BRKLSTS2_Pos         (26)                                              /*!< PWM_T::INTSTS1: BRKLSTS2 Position         */
+#define PWM_INTSTS1_BRKLSTS2_Msk         (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos)               /*!< PWM_T::INTSTS1: BRKLSTS2 Mask             */
+
+#define PWM_INTSTS1_BRKLSTS3_Pos         (27)                                              /*!< PWM_T::INTSTS1: BRKLSTS3 Position         */
+#define PWM_INTSTS1_BRKLSTS3_Msk         (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos)               /*!< PWM_T::INTSTS1: BRKLSTS3 Mask             */
+
+#define PWM_INTSTS1_BRKLSTS4_Pos         (28)                                              /*!< PWM_T::INTSTS1: BRKLSTS4 Position         */
+#define PWM_INTSTS1_BRKLSTS4_Msk         (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos)               /*!< PWM_T::INTSTS1: BRKLSTS4 Mask             */
+
+#define PWM_INTSTS1_BRKLSTS5_Pos         (29)                                              /*!< PWM_T::INTSTS1: BRKLSTS5 Position         */
+#define PWM_INTSTS1_BRKLSTS5_Msk         (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos)               /*!< PWM_T::INTSTS1: BRKLSTS5 Mask             */
+
+#define PWM_IFA_IFCNT0_1_Pos             (0)                                               /*!< PWM_T::IFA: IFCNT0_1 Position             */
+#define PWM_IFA_IFCNT0_1_Msk             (0xful << PWM_IFA_IFCNT0_1_Pos)                   /*!< PWM_T::IFA: IFCNT0_1 Mask                 */
+
+#define PWM_IFA_IFSEL0_1_Pos             (4)                                               /*!< PWM_T::IFA: IFSEL0_1 Position             */
+#define PWM_IFA_IFSEL0_1_Msk             (0x7ul << PWM_IFA_IFSEL0_1_Pos)                   /*!< PWM_T::IFA: IFSEL0_1 Mask                 */
+
+#define PWM_IFA_IFAEN0_1_Pos             (7)                                               /*!< PWM_T::IFA: IFAEN0_1 Position             */
+#define PWM_IFA_IFAEN0_1_Msk             (0x1ul << PWM_IFA_IFAEN0_1_Pos)                   /*!< PWM_T::IFA: IFAEN0_1 Mask                 */
+
+#define PWM_IFA_IFCNT2_3_Pos             (8)                                               /*!< PWM_T::IFA: IFCNT2_3 Position             */
+#define PWM_IFA_IFCNT2_3_Msk             (0xful << PWM_IFA_IFCNT2_3_Pos)                   /*!< PWM_T::IFA: IFCNT2_3 Mask                 */
+
+#define PWM_IFA_IFSEL2_3_Pos             (12)                                              /*!< PWM_T::IFA: IFSEL2_3 Position             */
+#define PWM_IFA_IFSEL2_3_Msk             (0x7ul << PWM_IFA_IFSEL2_3_Pos)                   /*!< PWM_T::IFA: IFSEL2_3 Mask                 */
+
+#define PWM_IFA_IFAEN2_3_Pos             (15)                                              /*!< PWM_T::IFA: IFAEN2_3 Position             */
+#define PWM_IFA_IFAEN2_3_Msk             (0x1ul << PWM_IFA_IFAEN2_3_Pos)                   /*!< PWM_T::IFA: IFAEN2_3 Mask                 */
+
+#define PWM_IFA_IFCNT4_5_Pos             (16)                                              /*!< PWM_T::IFA: IFCNT4_5 Position             */
+#define PWM_IFA_IFCNT4_5_Msk             (0xful << PWM_IFA_IFCNT4_5_Pos)                   /*!< PWM_T::IFA: IFCNT4_5 Mask                 */
+
+#define PWM_IFA_IFSEL4_5_Pos             (20)                                              /*!< PWM_T::IFA: IFSEL4_5 Position             */
+#define PWM_IFA_IFSEL4_5_Msk             (0x7ul << PWM_IFA_IFSEL4_5_Pos)                   /*!< PWM_T::IFA: IFSEL4_5 Mask                 */
+
+#define PWM_IFA_IFAEN4_5_Pos             (23)                                              /*!< PWM_T::IFA: IFAEN4_5 Position             */
+#define PWM_IFA_IFAEN4_5_Msk             (0x1ul << PWM_IFA_IFAEN4_5_Pos)                   /*!< PWM_T::IFA: IFAEN4_5 Mask                 */
+
+#define PWM_DACTRGEN_ZTEn_Pos            (0)                                               /*!< PWM_T::DACTRGEN: ZTEn Position            */
+#define PWM_DACTRGEN_ZTEn_Msk            (0x3ful << PWM_DACTRGEN_ZTEn_Pos)                 /*!< PWM_T::DACTRGEN: ZTEn Mask                */
+
+#define PWM_DACTRGEN_ZTE0_Pos            (0)                                               /*!< PWM_T::DACTRGEN: ZTE0 Position            */
+#define PWM_DACTRGEN_ZTE0_Msk            (0x1ul << PWM_DACTRGEN_ZTE0_Pos)                  /*!< PWM_T::DACTRGEN: ZTE0 Mask                */
+
+#define PWM_DACTRGEN_ZTE1_Pos            (1)                                               /*!< PWM_T::DACTRGEN: ZTE1 Position            */
+#define PWM_DACTRGEN_ZTE1_Msk            (0x1ul << PWM_DACTRGEN_ZTE1_Pos)                  /*!< PWM_T::DACTRGEN: ZTE1 Mask                */
+
+#define PWM_DACTRGEN_ZTE2_Pos            (2)                                               /*!< PWM_T::DACTRGEN: ZTE2 Position            */
+#define PWM_DACTRGEN_ZTE2_Msk            (0x1ul << PWM_DACTRGEN_ZTE2_Pos)                  /*!< PWM_T::DACTRGEN: ZTE2 Mask                */
+
+#define PWM_DACTRGEN_ZTE3_Pos            (3)                                               /*!< PWM_T::DACTRGEN: ZTE3 Position            */
+#define PWM_DACTRGEN_ZTE3_Msk            (0x1ul << PWM_DACTRGEN_ZTE3_Pos)                  /*!< PWM_T::DACTRGEN: ZTE3 Mask                */
+
+#define PWM_DACTRGEN_ZTE4_Pos            (4)                                               /*!< PWM_T::DACTRGEN: ZTE4 Position            */
+#define PWM_DACTRGEN_ZTE4_Msk            (0x1ul << PWM_DACTRGEN_ZTE4_Pos)                  /*!< PWM_T::DACTRGEN: ZTE4 Mask                */
+
+#define PWM_DACTRGEN_ZTE5_Pos            (5)                                               /*!< PWM_T::DACTRGEN: ZTE5 Position            */
+#define PWM_DACTRGEN_ZTE5_Msk            (0x1ul << PWM_DACTRGEN_ZTE5_Pos)                  /*!< PWM_T::DACTRGEN: ZTE5 Mask                */
+
+#define PWM_DACTRGEN_PTEn_Pos            (8)                                               /*!< PWM_T::DACTRGEN: PTEn Position            */
+#define PWM_DACTRGEN_PTEn_Msk            (0x3ful << PWM_DACTRGEN_PTEn_Pos)                 /*!< PWM_T::DACTRGEN: PTEn Mask                */
+
+#define PWM_DACTRGEN_PTE0_Pos            (8)                                               /*!< PWM_T::DACTRGEN: PTE0 Position            */
+#define PWM_DACTRGEN_PTE0_Msk            (0x1ul << PWM_DACTRGEN_PTE0_Pos)                  /*!< PWM_T::DACTRGEN: PTE0 Mask                */
+
+#define PWM_DACTRGEN_PTE1_Pos            (9)                                               /*!< PWM_T::DACTRGEN: PTE1 Position            */
+#define PWM_DACTRGEN_PTE1_Msk            (0x1ul << PWM_DACTRGEN_PTE1_Pos)                  /*!< PWM_T::DACTRGEN: PTE1 Mask                */
+
+#define PWM_DACTRGEN_PTE2_Pos            (10)                                              /*!< PWM_T::DACTRGEN: PTE2 Position            */
+#define PWM_DACTRGEN_PTE2_Msk            (0x1ul << PWM_DACTRGEN_PTE2_Pos)                  /*!< PWM_T::DACTRGEN: PTE2 Mask                */
+
+#define PWM_DACTRGEN_PTE3_Pos            (11)                                              /*!< PWM_T::DACTRGEN: PTE3 Position            */
+#define PWM_DACTRGEN_PTE3_Msk            (0x1ul << PWM_DACTRGEN_PTE3_Pos)                  /*!< PWM_T::DACTRGEN: PTE3 Mask                */
+
+#define PWM_DACTRGEN_PTE4_Pos            (12)                                              /*!< PWM_T::DACTRGEN: PTE4 Position            */
+#define PWM_DACTRGEN_PTE4_Msk            (0x1ul << PWM_DACTRGEN_PTE4_Pos)                  /*!< PWM_T::DACTRGEN: PTE4 Mask                */
+
+#define PWM_DACTRGEN_PTE5_Pos            (13)                                              /*!< PWM_T::DACTRGEN: PTE5 Position            */
+#define PWM_DACTRGEN_PTE5_Msk            (0x1ul << PWM_DACTRGEN_PTE5_Pos)                  /*!< PWM_T::DACTRGEN: PTE5 Mask                */
+
+#define PWM_DACTRGEN_CUTRGEn_Pos         (16)                                              /*!< PWM_T::DACTRGEN: CUTRGEn Position         */
+#define PWM_DACTRGEN_CUTRGEn_Msk         (0x3ful << PWM_DACTRGEN_CUTRGEn_Pos)              /*!< PWM_T::DACTRGEN: CUTRGEn Mask             */
+
+#define PWM_DACTRGEN_CUTRGE0_Pos         (16)                                              /*!< PWM_T::DACTRGEN: CUTRGE0 Position         */
+#define PWM_DACTRGEN_CUTRGE0_Msk         (0x1ul << PWM_DACTRGEN_CUTRGE0_Pos)               /*!< PWM_T::DACTRGEN: CUTRGE0 Mask             */
+
+#define PWM_DACTRGEN_CUTRGE1_Pos         (17)                                              /*!< PWM_T::DACTRGEN: CUTRGE1 Position         */
+#define PWM_DACTRGEN_CUTRGE1_Msk         (0x1ul << PWM_DACTRGEN_CUTRGE1_Pos)               /*!< PWM_T::DACTRGEN: CUTRGE1 Mask             */
+
+#define PWM_DACTRGEN_CUTRGE2_Pos         (18)                                              /*!< PWM_T::DACTRGEN: CUTRGE2 Position         */
+#define PWM_DACTRGEN_CUTRGE2_Msk         (0x1ul << PWM_DACTRGEN_CUTRGE2_Pos)               /*!< PWM_T::DACTRGEN: CUTRGE2 Mask             */
+
+#define PWM_DACTRGEN_CUTRGE3_Pos         (19)                                              /*!< PWM_T::DACTRGEN: CUTRGE3 Position         */
+#define PWM_DACTRGEN_CUTRGE3_Msk         (0x1ul << PWM_DACTRGEN_CUTRGE3_Pos)               /*!< PWM_T::DACTRGEN: CUTRGE3 Mask             */
+
+#define PWM_DACTRGEN_CUTRGE4_Pos         (20)                                              /*!< PWM_T::DACTRGEN: CUTRGE4 Position         */
+#define PWM_DACTRGEN_CUTRGE4_Msk         (0x1ul << PWM_DACTRGEN_CUTRGE4_Pos)               /*!< PWM_T::DACTRGEN: CUTRGE4 Mask             */
+
+#define PWM_DACTRGEN_CUTRGE5_Pos         (21)                                              /*!< PWM_T::DACTRGEN: CUTRGE5 Position         */
+#define PWM_DACTRGEN_CUTRGE5_Msk         (0x1ul << PWM_DACTRGEN_CUTRGE5_Pos)               /*!< PWM_T::DACTRGEN: CUTRGE5 Mask             */
+
+#define PWM_DACTRGEN_CDTRGEn_Pos         (24)                                              /*!< PWM_T::DACTRGEN: CDTRGEn Position         */
+#define PWM_DACTRGEN_CDTRGEn_Msk         (0x3ful << PWM_DACTRGEN_CDTRGEn_Pos)              /*!< PWM_T::DACTRGEN: CDTRGEn Mask             */
+
+#define PWM_DACTRGEN_CDTRGE0_Pos         (24)                                              /*!< PWM_T::DACTRGEN: CDTRGE0 Position         */
+#define PWM_DACTRGEN_CDTRGE0_Msk         (0x1ul << PWM_DACTRGEN_CDTRGE0_Pos)               /*!< PWM_T::DACTRGEN: CDTRGE0 Mask             */
+
+#define PWM_DACTRGEN_CDTRGE1_Pos         (25)                                              /*!< PWM_T::DACTRGEN: CDTRGE1 Position         */
+#define PWM_DACTRGEN_CDTRGE1_Msk         (0x1ul << PWM_DACTRGEN_CDTRGE1_Pos)               /*!< PWM_T::DACTRGEN: CDTRGE1 Mask             */
+
+#define PWM_DACTRGEN_CDTRGE2_Pos         (26)                                              /*!< PWM_T::DACTRGEN: CDTRGE2 Position         */
+#define PWM_DACTRGEN_CDTRGE2_Msk         (0x1ul << PWM_DACTRGEN_CDTRGE2_Pos)               /*!< PWM_T::DACTRGEN: CDTRGE2 Mask             */
+
+#define PWM_DACTRGEN_CDTRGE3_Pos         (27)                                              /*!< PWM_T::DACTRGEN: CDTRGE3 Position         */
+#define PWM_DACTRGEN_CDTRGE3_Msk         (0x1ul << PWM_DACTRGEN_CDTRGE3_Pos)               /*!< PWM_T::DACTRGEN: CDTRGE3 Mask             */
+
+#define PWM_DACTRGEN_CDTRGE4_Pos         (28)                                              /*!< PWM_T::DACTRGEN: CDTRGE4 Position         */
+#define PWM_DACTRGEN_CDTRGE4_Msk         (0x1ul << PWM_DACTRGEN_CDTRGE4_Pos)               /*!< PWM_T::DACTRGEN: CDTRGE4 Mask             */
+
+#define PWM_DACTRGEN_CDTRGE5_Pos         (29)                                              /*!< PWM_T::DACTRGEN: CDTRGE5 Position         */
+#define PWM_DACTRGEN_CDTRGE5_Msk         (0x1ul << PWM_DACTRGEN_CDTRGE5_Pos)               /*!< PWM_T::DACTRGEN: CDTRGE5 Mask             */
+
+#define PWM_EADCTS0_TRGSEL0_Pos          (0)                                               /*!< PWM_T::EADCTS0: TRGSEL0 Position          */
+#define PWM_EADCTS0_TRGSEL0_Msk          (0xful << PWM_EADCTS0_TRGSEL0_Pos)                /*!< PWM_T::EADCTS0: TRGSEL0 Mask              */
+
+#define PWM_EADCTS0_TRGEN0_Pos           (7)                                               /*!< PWM_T::EADCTS0: TRGEN0 Position           */
+#define PWM_EADCTS0_TRGEN0_Msk           (0x1ul << PWM_EADCTS0_TRGEN0_Pos)                 /*!< PWM_T::EADCTS0: TRGEN0 Mask               */
+
+#define PWM_EADCTS0_TRGSEL1_Pos          (8)                                               /*!< PWM_T::EADCTS0: TRGSEL1 Position          */
+#define PWM_EADCTS0_TRGSEL1_Msk          (0xful << PWM_EADCTS0_TRGSEL1_Pos)                /*!< PWM_T::EADCTS0: TRGSEL1 Mask              */
+
+#define PWM_EADCTS0_TRGEN1_Pos           (15)                                              /*!< PWM_T::EADCTS0: TRGEN1 Position           */
+#define PWM_EADCTS0_TRGEN1_Msk           (0x1ul << PWM_EADCTS0_TRGEN1_Pos)                 /*!< PWM_T::EADCTS0: TRGEN1 Mask               */
+
+#define PWM_EADCTS0_TRGSEL2_Pos          (16)                                              /*!< PWM_T::EADCTS0: TRGSEL2 Position          */
+#define PWM_EADCTS0_TRGSEL2_Msk          (0xful << PWM_EADCTS0_TRGSEL2_Pos)                /*!< PWM_T::EADCTS0: TRGSEL2 Mask              */
+
+#define PWM_EADCTS0_TRGEN2_Pos           (23)                                              /*!< PWM_T::EADCTS0: TRGEN2 Position           */
+#define PWM_EADCTS0_TRGEN2_Msk           (0x1ul << PWM_EADCTS0_TRGEN2_Pos)                 /*!< PWM_T::EADCTS0: TRGEN2 Mask               */
+
+#define PWM_EADCTS0_TRGSEL3_Pos          (24)                                              /*!< PWM_T::EADCTS0: TRGSEL3 Position          */
+#define PWM_EADCTS0_TRGSEL3_Msk          (0xful << PWM_EADCTS0_TRGSEL3_Pos)                /*!< PWM_T::EADCTS0: TRGSEL3 Mask              */
+
+#define PWM_EADCTS0_TRGEN3_Pos           (31)                                              /*!< PWM_T::EADCTS0: TRGEN3 Position           */
+#define PWM_EADCTS0_TRGEN3_Msk           (0x1ul << PWM_EADCTS0_TRGEN3_Pos)                 /*!< PWM_T::EADCTS0: TRGEN3 Mask               */
+
+#define PWM_EADCTS1_TRGSEL4_Pos          (0)                                               /*!< PWM_T::EADCTS1: TRGSEL4 Position          */
+#define PWM_EADCTS1_TRGSEL4_Msk          (0xful << PWM_EADCTS1_TRGSEL4_Pos)                /*!< PWM_T::EADCTS1: TRGSEL4 Mask              */
+
+#define PWM_EADCTS1_TRGEN4_Pos           (7)                                               /*!< PWM_T::EADCTS1: TRGEN4 Position           */
+#define PWM_EADCTS1_TRGEN4_Msk           (0x1ul << PWM_EADCTS1_TRGEN4_Pos)                 /*!< PWM_T::EADCTS1: TRGEN4 Mask               */
+
+#define PWM_EADCTS1_TRGSEL5_Pos          (8)                                               /*!< PWM_T::EADCTS1: TRGSEL5 Position          */
+#define PWM_EADCTS1_TRGSEL5_Msk          (0xful << PWM_EADCTS1_TRGSEL5_Pos)                /*!< PWM_T::EADCTS1: TRGSEL5 Mask              */
+
+#define PWM_EADCTS1_TRGEN5_Pos           (15)                                              /*!< PWM_T::EADCTS1: TRGEN5 Position           */
+#define PWM_EADCTS1_TRGEN5_Msk           (0x1ul << PWM_EADCTS1_TRGEN5_Pos)                 /*!< PWM_T::EADCTS1: TRGEN5 Mask               */
+
+#define PWM_FTCMPDAT0_1_FTCMP_Pos        (0)                                               /*!< PWM_T::FTCMPDAT0_1: FTCMP Position        */
+#define PWM_FTCMPDAT0_1_FTCMP_Msk        (0xfffful << PWM_FTCMPDAT0_1_FTCMP_Pos)           /*!< PWM_T::FTCMPDAT0_1: FTCMP Mask            */
+
+#define PWM_FTCMPDAT2_3_FTCMP_Pos        (0)                                               /*!< PWM_T::FTCMPDAT2_3: FTCMP Position        */
+#define PWM_FTCMPDAT2_3_FTCMP_Msk        (0xfffful << PWM_FTCMPDAT2_3_FTCMP_Pos)           /*!< PWM_T::FTCMPDAT2_3: FTCMP Mask            */
+
+#define PWM_FTCMPDAT4_5_FTCMP_Pos        (0)                                               /*!< PWM_T::FTCMPDAT4_5: FTCMP Position        */
+#define PWM_FTCMPDAT4_5_FTCMP_Msk        (0xfffful << PWM_FTCMPDAT4_5_FTCMP_Pos)           /*!< PWM_T::FTCMPDAT4_5: FTCMP Mask            */
+
+#define PWM_SSCTL_SSENn_Pos              (0)                                               /*!< PWM_T::SSCTL: SSENn Position              */
+#define PWM_SSCTL_SSENn_Msk              (0x3ful << PWM_SSCTL_SSENn_Pos)                   /*!< PWM_T::SSCTL: SSENn Mask                  */
+
+#define PWM_SSCTL_SSEN0_Pos              (0)                                               /*!< PWM_T::SSCTL: SSEN0 Position              */
+#define PWM_SSCTL_SSEN0_Msk              (0x1ul << PWM_SSCTL_SSEN0_Pos)                    /*!< PWM_T::SSCTL: SSEN0 Mask                  */
+
+#define PWM_SSCTL_SSEN1_Pos              (1)                                               /*!< PWM_T::SSCTL: SSEN1 Position              */
+#define PWM_SSCTL_SSEN1_Msk              (0x1ul << PWM_SSCTL_SSEN1_Pos)                    /*!< PWM_T::SSCTL: SSEN1 Mask                  */
+
+#define PWM_SSCTL_SSEN2_Pos              (2)                                               /*!< PWM_T::SSCTL: SSEN2 Position              */
+#define PWM_SSCTL_SSEN2_Msk              (0x1ul << PWM_SSCTL_SSEN2_Pos)                    /*!< PWM_T::SSCTL: SSEN2 Mask                  */
+
+#define PWM_SSCTL_SSEN3_Pos              (3)                                               /*!< PWM_T::SSCTL: SSEN3 Position              */
+#define PWM_SSCTL_SSEN3_Msk              (0x1ul << PWM_SSCTL_SSEN3_Pos)                    /*!< PWM_T::SSCTL: SSEN3 Mask                  */
+
+#define PWM_SSCTL_SSEN4_Pos              (4)                                               /*!< PWM_T::SSCTL: SSEN4 Position              */
+#define PWM_SSCTL_SSEN4_Msk              (0x1ul << PWM_SSCTL_SSEN4_Pos)                    /*!< PWM_T::SSCTL: SSEN4 Mask                  */
+
+#define PWM_SSCTL_SSEN5_Pos              (5)                                               /*!< PWM_T::SSCTL: SSEN5 Position              */
+#define PWM_SSCTL_SSEN5_Msk              (0x1ul << PWM_SSCTL_SSEN5_Pos)                    /*!< PWM_T::SSCTL: SSEN5 Mask                  */
+
+#define PWM_SSTRG_CNTSEN_Pos             (0)                                               /*!< PWM_T::SSTRG: CNTSEN Position             */
+#define PWM_SSTRG_CNTSEN_Msk             (0x1ul << PWM_SSTRG_CNTSEN_Pos)                   /*!< PWM_T::SSTRG: CNTSEN Mask                 */
+
+#define PWM_STATUS_CNTMAXFn_Pos          (0)                                               /*!< PWM_T::STATUS: CNTMAXFn Position          */
+#define PWM_STATUS_CNTMAXFn_Msk          (0x3ful << PWM_STATUS_CNTMAXFn_Pos)               /*!< PWM_T::STATUS: CNTMAXFn Mask              */
+
+#define PWM_STATUS_CNTMAXF0_Pos          (0)                                               /*!< PWM_T::STATUS: CNTMAXF0 Position          */
+#define PWM_STATUS_CNTMAXF0_Msk          (0x1ul << PWM_STATUS_CNTMAXF0_Pos)                /*!< PWM_T::STATUS: CNTMAXF0 Mask              */
+
+#define PWM_STATUS_CNTMAXF1_Pos          (1)                                               /*!< PWM_T::STATUS: CNTMAXF1 Position          */
+#define PWM_STATUS_CNTMAXF1_Msk          (0x1ul << PWM_STATUS_CNTMAXF1_Pos)                /*!< PWM_T::STATUS: CNTMAXF1 Mask              */
+
+#define PWM_STATUS_CNTMAXF2_Pos          (2)                                               /*!< PWM_T::STATUS: CNTMAXF2 Position          */
+#define PWM_STATUS_CNTMAXF2_Msk          (0x1ul << PWM_STATUS_CNTMAXF2_Pos)                /*!< PWM_T::STATUS: CNTMAXF2 Mask              */
+
+#define PWM_STATUS_CNTMAXF3_Pos          (3)                                               /*!< PWM_T::STATUS: CNTMAXF3 Position          */
+#define PWM_STATUS_CNTMAXF3_Msk          (0x1ul << PWM_STATUS_CNTMAXF3_Pos)                /*!< PWM_T::STATUS: CNTMAXF3 Mask              */
+
+#define PWM_STATUS_CNTMAXF4_Pos          (4)                                               /*!< PWM_T::STATUS: CNTMAXF4 Position          */
+#define PWM_STATUS_CNTMAXF4_Msk          (0x1ul << PWM_STATUS_CNTMAXF4_Pos)                /*!< PWM_T::STATUS: CNTMAXF4 Mask              */
+
+#define PWM_STATUS_CNTMAXF5_Pos          (5)                                               /*!< PWM_T::STATUS: CNTMAXF5 Position          */
+#define PWM_STATUS_CNTMAXF5_Msk          (0x1ul << PWM_STATUS_CNTMAXF5_Pos)                /*!< PWM_T::STATUS: CNTMAXF5 Mask              */
+
+#define PWM_STATUS_SYNCINFn_Pos          (8)                                               /*!< PWM_T::STATUS: SYNCINFn Position          */
+#define PWM_STATUS_SYNCINFn_Msk          (0x7ul << PWM_STATUS_SYNCINFn_Pos)                /*!< PWM_T::STATUS: SYNCINFn Mask              */
+
+#define PWM_STATUS_SYNCINF0_Pos          (8)                                               /*!< PWM_T::STATUS: SYNCINF0 Position          */
+#define PWM_STATUS_SYNCINF0_Msk          (0x1ul << PWM_STATUS_SYNCINF0_Pos)                /*!< PWM_T::STATUS: SYNCINF0 Mask              */
+
+#define PWM_STATUS_SYNCINF2_Pos          (9)                                               /*!< PWM_T::STATUS: SYNCINF2 Position          */
+#define PWM_STATUS_SYNCINF2_Msk          (0x1ul << PWM_STATUS_SYNCINF2_Pos)                /*!< PWM_T::STATUS: SYNCINF2 Mask              */
+
+#define PWM_STATUS_SYNCINF4_Pos          (10)                                              /*!< PWM_T::STATUS: SYNCINF4 Position          */
+#define PWM_STATUS_SYNCINF4_Msk          (0x1ul << PWM_STATUS_SYNCINF4_Pos)                /*!< PWM_T::STATUS: SYNCINF4 Mask              */
+
+#define PWM_STATUS_ADCTRGFn_Pos          (16)                                              /*!< PWM_T::STATUS: ADCTRGFn Position          */
+#define PWM_STATUS_ADCTRGFn_Msk          (0x3ful << PWM_STATUS_ADCTRGFn_Pos)               /*!< PWM_T::STATUS: ADCTRGFn Mask              */
+
+#define PWM_STATUS_ADCTRGF0_Pos          (16)                                              /*!< PWM_T::STATUS: ADCTRGF0 Position          */
+#define PWM_STATUS_ADCTRGF0_Msk          (0x1ul << PWM_STATUS_ADCTRGF0_Pos)                /*!< PWM_T::STATUS: ADCTRGF0 Mask              */
+
+#define PWM_STATUS_ADCTRGF1_Pos          (17)                                              /*!< PWM_T::STATUS: ADCTRGF1 Position          */
+#define PWM_STATUS_ADCTRGF1_Msk          (0x1ul << PWM_STATUS_ADCTRGF1_Pos)                /*!< PWM_T::STATUS: ADCTRGF1 Mask              */
+
+#define PWM_STATUS_ADCTRGF2_Pos          (18)                                              /*!< PWM_T::STATUS: ADCTRGF2 Position          */
+#define PWM_STATUS_ADCTRGF2_Msk          (0x1ul << PWM_STATUS_ADCTRGF2_Pos)                /*!< PWM_T::STATUS: ADCTRGF2 Mask              */
+
+#define PWM_STATUS_ADCTRGF3_Pos          (19)                                              /*!< PWM_T::STATUS: ADCTRGF3 Position          */
+#define PWM_STATUS_ADCTRGF3_Msk          (0x1ul << PWM_STATUS_ADCTRGF3_Pos)                /*!< PWM_T::STATUS: ADCTRGF3 Mask              */
+
+#define PWM_STATUS_ADCTRGF4_Pos          (20)                                              /*!< PWM_T::STATUS: ADCTRGF4 Position          */
+#define PWM_STATUS_ADCTRGF4_Msk          (0x1ul << PWM_STATUS_ADCTRGF4_Pos)                /*!< PWM_T::STATUS: ADCTRGF4 Mask              */
+
+#define PWM_STATUS_ADCTRGF5_Pos          (21)                                              /*!< PWM_T::STATUS: ADCTRGF5 Position          */
+#define PWM_STATUS_ADCTRGF5_Msk          (0x1ul << PWM_STATUS_ADCTRGF5_Pos)                /*!< PWM_T::STATUS: ADCTRGF5 Mask              */
+
+#define PWM_STATUS_DACTRGF_Pos           (24)                                              /*!< PWM_T::STATUS: DACTRGF Position           */
+#define PWM_STATUS_DACTRGF_Msk           (0x1ul << PWM_STATUS_DACTRGF_Pos)                 /*!< PWM_T::STATUS: DACTRGF Mask               */
+
+#define PWM_CAPINEN_CAPINENn_Pos         (0)                                               /*!< PWM_T::CAPINEN: CAPINENn Position         */
+#define PWM_CAPINEN_CAPINENn_Msk         (0x3ful << PWM_CAPINEN_CAPINENn_Pos)              /*!< PWM_T::CAPINEN: CAPINENn Mask             */
+
+#define PWM_CAPINEN_CAPINEN0_Pos         (0)                                               /*!< PWM_T::CAPINEN: CAPINEN0 Position         */
+#define PWM_CAPINEN_CAPINEN0_Msk         (0x1ul << PWM_CAPINEN_CAPINEN0_Pos)               /*!< PWM_T::CAPINEN: CAPINEN0 Mask             */
+
+#define PWM_CAPINEN_CAPINEN1_Pos         (1)                                               /*!< PWM_T::CAPINEN: CAPINEN1 Position         */
+#define PWM_CAPINEN_CAPINEN1_Msk         (0x1ul << PWM_CAPINEN_CAPINEN1_Pos)               /*!< PWM_T::CAPINEN: CAPINEN1 Mask             */
+
+#define PWM_CAPINEN_CAPINEN2_Pos         (2)                                               /*!< PWM_T::CAPINEN: CAPINEN2 Position         */
+#define PWM_CAPINEN_CAPINEN2_Msk         (0x1ul << PWM_CAPINEN_CAPINEN2_Pos)               /*!< PWM_T::CAPINEN: CAPINEN2 Mask             */
+
+#define PWM_CAPINEN_CAPINEN3_Pos         (3)                                               /*!< PWM_T::CAPINEN: CAPINEN3 Position         */
+#define PWM_CAPINEN_CAPINEN3_Msk         (0x1ul << PWM_CAPINEN_CAPINEN3_Pos)               /*!< PWM_T::CAPINEN: CAPINEN3 Mask             */
+
+#define PWM_CAPINEN_CAPINEN4_Pos         (4)                                               /*!< PWM_T::CAPINEN: CAPINEN4 Position         */
+#define PWM_CAPINEN_CAPINEN4_Msk         (0x1ul << PWM_CAPINEN_CAPINEN4_Pos)               /*!< PWM_T::CAPINEN: CAPINEN4 Mask             */
+
+#define PWM_CAPINEN_CAPINEN5_Pos         (5)                                               /*!< PWM_T::CAPINEN: CAPINEN5 Position         */
+#define PWM_CAPINEN_CAPINEN5_Msk         (0x1ul << PWM_CAPINEN_CAPINEN5_Pos)               /*!< PWM_T::CAPINEN: CAPINEN5 Mask             */
+
+#define PWM_CAPCTL_CAPENn_Pos            (0)                                               /*!< PWM_T::CAPCTL: CAPENn Position            */
+#define PWM_CAPCTL_CAPENn_Msk            (0x3ful << PWM_CAPCTL_CAPENn_Pos)                 /*!< PWM_T::CAPCTL: CAPENn Mask                */
+
+#define PWM_CAPCTL_CAPEN0_Pos            (0)                                               /*!< PWM_T::CAPCTL: CAPEN0 Position            */
+#define PWM_CAPCTL_CAPEN0_Msk            (0x1ul << PWM_CAPCTL_CAPEN0_Pos)                  /*!< PWM_T::CAPCTL: CAPEN0 Mask                */
+
+#define PWM_CAPCTL_CAPEN1_Pos            (1)                                               /*!< PWM_T::CAPCTL: CAPEN1 Position            */
+#define PWM_CAPCTL_CAPEN1_Msk            (0x1ul << PWM_CAPCTL_CAPEN1_Pos)                  /*!< PWM_T::CAPCTL: CAPEN1 Mask                */
+
+#define PWM_CAPCTL_CAPEN2_Pos            (2)                                               /*!< PWM_T::CAPCTL: CAPEN2 Position            */
+#define PWM_CAPCTL_CAPEN2_Msk            (0x1ul << PWM_CAPCTL_CAPEN2_Pos)                  /*!< PWM_T::CAPCTL: CAPEN2 Mask                */
+
+#define PWM_CAPCTL_CAPEN3_Pos            (3)                                               /*!< PWM_T::CAPCTL: CAPEN3 Position            */
+#define PWM_CAPCTL_CAPEN3_Msk            (0x1ul << PWM_CAPCTL_CAPEN3_Pos)                  /*!< PWM_T::CAPCTL: CAPEN3 Mask                */
+
+#define PWM_CAPCTL_CAPEN4_Pos            (4)                                               /*!< PWM_T::CAPCTL: CAPEN4 Position            */
+#define PWM_CAPCTL_CAPEN4_Msk            (0x1ul << PWM_CAPCTL_CAPEN4_Pos)                  /*!< PWM_T::CAPCTL: CAPEN4 Mask                */
+
+#define PWM_CAPCTL_CAPEN5_Pos            (5)                                               /*!< PWM_T::CAPCTL: CAPEN5 Position            */
+#define PWM_CAPCTL_CAPEN5_Msk            (0x1ul << PWM_CAPCTL_CAPEN5_Pos)                  /*!< PWM_T::CAPCTL: CAPEN5 Mask                */
+
+#define PWM_CAPCTL_CAPINVn_Pos           (8)                                               /*!< PWM_T::CAPCTL: CAPINVn Position           */
+#define PWM_CAPCTL_CAPINVn_Msk           (0x3ful << PWM_CAPCTL_CAPINVn_Pos)                /*!< PWM_T::CAPCTL: CAPINVn Mask               */
+
+#define PWM_CAPCTL_CAPINV0_Pos           (8)                                               /*!< PWM_T::CAPCTL: CAPINV0 Position           */
+#define PWM_CAPCTL_CAPINV0_Msk           (0x1ul << PWM_CAPCTL_CAPINV0_Pos)                 /*!< PWM_T::CAPCTL: CAPINV0 Mask               */
+
+#define PWM_CAPCTL_CAPINV1_Pos           (9)                                               /*!< PWM_T::CAPCTL: CAPINV1 Position           */
+#define PWM_CAPCTL_CAPINV1_Msk           (0x1ul << PWM_CAPCTL_CAPINV1_Pos)                 /*!< PWM_T::CAPCTL: CAPINV1 Mask               */
+
+#define PWM_CAPCTL_CAPINV2_Pos           (10)                                              /*!< PWM_T::CAPCTL: CAPINV2 Position           */
+#define PWM_CAPCTL_CAPINV2_Msk           (0x1ul << PWM_CAPCTL_CAPINV2_Pos)                 /*!< PWM_T::CAPCTL: CAPINV2 Mask               */
+
+#define PWM_CAPCTL_CAPINV3_Pos           (11)                                              /*!< PWM_T::CAPCTL: CAPINV3 Position           */
+#define PWM_CAPCTL_CAPINV3_Msk           (0x1ul << PWM_CAPCTL_CAPINV3_Pos)                 /*!< PWM_T::CAPCTL: CAPINV3 Mask               */
+
+#define PWM_CAPCTL_CAPINV4_Pos           (12)                                              /*!< PWM_T::CAPCTL: CAPINV4 Position           */
+#define PWM_CAPCTL_CAPINV4_Msk           (0x1ul << PWM_CAPCTL_CAPINV4_Pos)                 /*!< PWM_T::CAPCTL: CAPINV4 Mask               */
+
+#define PWM_CAPCTL_CAPINV5_Pos           (13)                                              /*!< PWM_T::CAPCTL: CAPINV5 Position           */
+#define PWM_CAPCTL_CAPINV5_Msk           (0x1ul << PWM_CAPCTL_CAPINV5_Pos)                 /*!< PWM_T::CAPCTL: CAPINV5 Mask               */
+
+#define PWM_CAPCTL_RCRLDENn_Pos          (16)                                              /*!< PWM_T::CAPCTL: RCRLDENn Position          */
+#define PWM_CAPCTL_RCRLDENn_Msk          (0x3ful << PWM_CAPCTL_RCRLDENn_Pos)               /*!< PWM_T::CAPCTL: RCRLDENn Mask              */
+
+#define PWM_CAPCTL_RCRLDEN0_Pos          (16)                                              /*!< PWM_T::CAPCTL: RCRLDEN0 Position          */
+#define PWM_CAPCTL_RCRLDEN0_Msk          (0x1ul << PWM_CAPCTL_RCRLDEN0_Pos)                /*!< PWM_T::CAPCTL: RCRLDEN0 Mask              */
+
+#define PWM_CAPCTL_RCRLDEN1_Pos          (17)                                              /*!< PWM_T::CAPCTL: RCRLDEN1 Position          */
+#define PWM_CAPCTL_RCRLDEN1_Msk          (0x1ul << PWM_CAPCTL_RCRLDEN1_Pos)                /*!< PWM_T::CAPCTL: RCRLDEN1 Mask              */
+
+#define PWM_CAPCTL_RCRLDEN2_Pos          (18)                                              /*!< PWM_T::CAPCTL: RCRLDEN2 Position          */
+#define PWM_CAPCTL_RCRLDEN2_Msk          (0x1ul << PWM_CAPCTL_RCRLDEN2_Pos)                /*!< PWM_T::CAPCTL: RCRLDEN2 Mask              */
+
+#define PWM_CAPCTL_RCRLDEN3_Pos          (19)                                              /*!< PWM_T::CAPCTL: RCRLDEN3 Position          */
+#define PWM_CAPCTL_RCRLDEN3_Msk          (0x1ul << PWM_CAPCTL_RCRLDEN3_Pos)                /*!< PWM_T::CAPCTL: RCRLDEN3 Mask              */
+
+#define PWM_CAPCTL_RCRLDEN4_Pos          (20)                                              /*!< PWM_T::CAPCTL: RCRLDEN4 Position          */
+#define PWM_CAPCTL_RCRLDEN4_Msk          (0x1ul << PWM_CAPCTL_RCRLDEN4_Pos)                /*!< PWM_T::CAPCTL: RCRLDEN4 Mask              */
+
+#define PWM_CAPCTL_RCRLDEN5_Pos          (21)                                              /*!< PWM_T::CAPCTL: RCRLDEN5 Position          */
+#define PWM_CAPCTL_RCRLDEN5_Msk          (0x1ul << PWM_CAPCTL_RCRLDEN5_Pos)                /*!< PWM_T::CAPCTL: RCRLDEN5 Mask              */
+
+#define PWM_CAPCTL_FCRLDENn_Pos          (24)                                              /*!< PWM_T::CAPCTL: FCRLDENn Position          */
+#define PWM_CAPCTL_FCRLDENn_Msk          (0x3ful << PWM_CAPCTL_FCRLDENn_Pos)               /*!< PWM_T::CAPCTL: FCRLDENn Mask              */
+
+#define PWM_CAPCTL_FCRLDEN0_Pos          (24)                                              /*!< PWM_T::CAPCTL: FCRLDEN0 Position          */
+#define PWM_CAPCTL_FCRLDEN0_Msk          (0x1ul << PWM_CAPCTL_FCRLDEN0_Pos)                /*!< PWM_T::CAPCTL: FCRLDEN0 Mask              */
+
+#define PWM_CAPCTL_FCRLDEN1_Pos          (25)                                              /*!< PWM_T::CAPCTL: FCRLDEN1 Position          */
+#define PWM_CAPCTL_FCRLDEN1_Msk          (0x1ul << PWM_CAPCTL_FCRLDEN1_Pos)                /*!< PWM_T::CAPCTL: FCRLDEN1 Mask              */
+
+#define PWM_CAPCTL_FCRLDEN2_Pos          (26)                                              /*!< PWM_T::CAPCTL: FCRLDEN2 Position          */
+#define PWM_CAPCTL_FCRLDEN2_Msk          (0x1ul << PWM_CAPCTL_FCRLDEN2_Pos)                /*!< PWM_T::CAPCTL: FCRLDEN2 Mask              */
+
+#define PWM_CAPCTL_FCRLDEN3_Pos          (27)                                              /*!< PWM_T::CAPCTL: FCRLDEN3 Position          */
+#define PWM_CAPCTL_FCRLDEN3_Msk          (0x1ul << PWM_CAPCTL_FCRLDEN3_Pos)                /*!< PWM_T::CAPCTL: FCRLDEN3 Mask              */
+
+#define PWM_CAPCTL_FCRLDEN4_Pos          (28)                                              /*!< PWM_T::CAPCTL: FCRLDEN4 Position          */
+#define PWM_CAPCTL_FCRLDEN4_Msk          (0x1ul << PWM_CAPCTL_FCRLDEN4_Pos)                /*!< PWM_T::CAPCTL: FCRLDEN4 Mask              */
+
+#define PWM_CAPCTL_FCRLDEN5_Pos          (29)                                              /*!< PWM_T::CAPCTL: FCRLDEN5 Position          */
+#define PWM_CAPCTL_FCRLDEN5_Msk          (0x1ul << PWM_CAPCTL_FCRLDEN5_Pos)                /*!< PWM_T::CAPCTL: FCRLDEN5 Mask              */
+
+#define PWM_CAPSTS_CRLIFOVn_Pos          (0)                                               /*!< PWM_T::CAPSTS: CRLIFOVn Position          */
+#define PWM_CAPSTS_CRLIFOVn_Msk          (0x3ful << PWM_CAPSTS_CRLIFOVn_Pos)               /*!< PWM_T::CAPSTS: CRLIFOVn Mask              */
+
+#define PWM_CAPSTS_CRLIFOV0_Pos          (0)                                               /*!< PWM_T::CAPSTS: CRLIFOV0 Position          */
+#define PWM_CAPSTS_CRLIFOV0_Msk          (0x1ul << PWM_CAPSTS_CRLIFOV0_Pos)                /*!< PWM_T::CAPSTS: CRLIFOV0 Mask              */
+
+#define PWM_CAPSTS_CRLIFOV1_Pos          (1)                                               /*!< PWM_T::CAPSTS: CRLIFOV1 Position          */
+#define PWM_CAPSTS_CRLIFOV1_Msk          (0x1ul << PWM_CAPSTS_CRLIFOV1_Pos)                /*!< PWM_T::CAPSTS: CRLIFOV1 Mask              */
+
+#define PWM_CAPSTS_CRLIFOV2_Pos          (2)                                               /*!< PWM_T::CAPSTS: CRLIFOV2 Position          */
+#define PWM_CAPSTS_CRLIFOV2_Msk          (0x1ul << PWM_CAPSTS_CRLIFOV2_Pos)                /*!< PWM_T::CAPSTS: CRLIFOV2 Mask              */
+
+#define PWM_CAPSTS_CRLIFOV3_Pos          (3)                                               /*!< PWM_T::CAPSTS: CRLIFOV3 Position          */
+#define PWM_CAPSTS_CRLIFOV3_Msk          (0x1ul << PWM_CAPSTS_CRLIFOV3_Pos)                /*!< PWM_T::CAPSTS: CRLIFOV3 Mask              */
+
+#define PWM_CAPSTS_CRLIFOV4_Pos          (4)                                               /*!< PWM_T::CAPSTS: CRLIFOV4 Position          */
+#define PWM_CAPSTS_CRLIFOV4_Msk          (0x1ul << PWM_CAPSTS_CRLIFOV4_Pos)                /*!< PWM_T::CAPSTS: CRLIFOV4 Mask              */
+
+#define PWM_CAPSTS_CRLIFOV5_Pos          (5)                                               /*!< PWM_T::CAPSTS: CRLIFOV5 Position          */
+#define PWM_CAPSTS_CRLIFOV5_Msk          (0x1ul << PWM_CAPSTS_CRLIFOV5_Pos)                /*!< PWM_T::CAPSTS: CRLIFOV5 Mask              */
+
+#define PWM_CAPSTS_CFLIFOVn_Pos          (8)                                               /*!< PWM_T::CAPSTS: CFLIFOVn Position          */
+#define PWM_CAPSTS_CFLIFOVn_Msk          (0x3ful << PWM_CAPSTS_CFLIFOVn_Pos)               /*!< PWM_T::CAPSTS: CFLIFOVn Mask              */
+
+#define PWM_CAPSTS_CFLIFOV0_Pos          (8)                                               /*!< PWM_T::CAPSTS: CFLIFOV0 Position          */
+#define PWM_CAPSTS_CFLIFOV0_Msk          (0x1ul << PWM_CAPSTS_CFLIFOV0_Pos)                /*!< PWM_T::CAPSTS: CFLIFOV0 Mask              */
+
+#define PWM_CAPSTS_CFLIFOV1_Pos          (9)                                               /*!< PWM_T::CAPSTS: CFLIFOV1 Position          */
+#define PWM_CAPSTS_CFLIFOV1_Msk          (0x1ul << PWM_CAPSTS_CFLIFOV1_Pos)                /*!< PWM_T::CAPSTS: CFLIFOV1 Mask              */
+
+#define PWM_CAPSTS_CFLIFOV2_Pos          (10)                                              /*!< PWM_T::CAPSTS: CFLIFOV2 Position          */
+#define PWM_CAPSTS_CFLIFOV2_Msk          (0x1ul << PWM_CAPSTS_CFLIFOV2_Pos)                /*!< PWM_T::CAPSTS: CFLIFOV2 Mask              */
+
+#define PWM_CAPSTS_CFLIFOV3_Pos          (11)                                              /*!< PWM_T::CAPSTS: CFLIFOV3 Position          */
+#define PWM_CAPSTS_CFLIFOV3_Msk          (0x1ul << PWM_CAPSTS_CFLIFOV3_Pos)                /*!< PWM_T::CAPSTS: CFLIFOV3 Mask              */
+
+#define PWM_CAPSTS_CFLIFOV4_Pos          (12)                                              /*!< PWM_T::CAPSTS: CFLIFOV4 Position          */
+#define PWM_CAPSTS_CFLIFOV4_Msk          (0x1ul << PWM_CAPSTS_CFLIFOV4_Pos)                /*!< PWM_T::CAPSTS: CFLIFOV4 Mask              */
+
+#define PWM_CAPSTS_CFLIFOV5_Pos          (13)                                              /*!< PWM_T::CAPSTS: CFLIFOV5 Position          */
+#define PWM_CAPSTS_CFLIFOV5_Msk          (0x1ul << PWM_CAPSTS_CFLIFOV5_Pos)                /*!< PWM_T::CAPSTS: CFLIFOV5 Mask              */
+
+#define PWM_RCAPDAT0_RCAPDAT_Pos         (0)                                               /*!< PWM_T::RCAPDAT0: RCAPDAT Position         */
+#define PWM_RCAPDAT0_RCAPDAT_Msk         (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos)            /*!< PWM_T::RCAPDAT0: RCAPDAT Mask             */
+
+#define PWM_FCAPDAT0_FCAPDAT_Pos         (0)                                               /*!< PWM_T::FCAPDAT0: FCAPDAT Position         */
+#define PWM_FCAPDAT0_FCAPDAT_Msk         (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos)            /*!< PWM_T::FCAPDAT0: FCAPDAT Mask             */
+
+#define PWM_RCAPDAT1_RCAPDAT_Pos         (0)                                               /*!< PWM_T::RCAPDAT1: RCAPDAT Position         */
+#define PWM_RCAPDAT1_RCAPDAT_Msk         (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos)            /*!< PWM_T::RCAPDAT1: RCAPDAT Mask             */
+
+#define PWM_FCAPDAT1_FCAPDAT_Pos         (0)                                               /*!< PWM_T::FCAPDAT1: FCAPDAT Position         */
+#define PWM_FCAPDAT1_FCAPDAT_Msk         (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos)            /*!< PWM_T::FCAPDAT1: FCAPDAT Mask             */
+
+#define PWM_RCAPDAT2_RCAPDAT_Pos         (0)                                               /*!< PWM_T::RCAPDAT2: RCAPDAT Position         */
+#define PWM_RCAPDAT2_RCAPDAT_Msk         (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos)            /*!< PWM_T::RCAPDAT2: RCAPDAT Mask             */
+
+#define PWM_FCAPDAT2_FCAPDAT_Pos         (0)                                               /*!< PWM_T::FCAPDAT2: FCAPDAT Position         */
+#define PWM_FCAPDAT2_FCAPDAT_Msk         (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos)            /*!< PWM_T::FCAPDAT2: FCAPDAT Mask             */
+
+#define PWM_RCAPDAT3_RCAPDAT_Pos         (0)                                               /*!< PWM_T::RCAPDAT3: RCAPDAT Position         */
+#define PWM_RCAPDAT3_RCAPDAT_Msk         (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos)            /*!< PWM_T::RCAPDAT3: RCAPDAT Mask             */
+
+#define PWM_FCAPDAT3_FCAPDAT_Pos         (0)                                               /*!< PWM_T::FCAPDAT3: FCAPDAT Position         */
+#define PWM_FCAPDAT3_FCAPDAT_Msk         (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos)            /*!< PWM_T::FCAPDAT3: FCAPDAT Mask             */
+
+#define PWM_RCAPDAT4_RCAPDAT_Pos         (0)                                               /*!< PWM_T::RCAPDAT4: RCAPDAT Position         */
+#define PWM_RCAPDAT4_RCAPDAT_Msk         (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos)            /*!< PWM_T::RCAPDAT4: RCAPDAT Mask             */
+
+#define PWM_FCAPDAT4_FCAPDAT_Pos         (0)                                               /*!< PWM_T::FCAPDAT4: FCAPDAT Position         */
+#define PWM_FCAPDAT4_FCAPDAT_Msk         (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos)            /*!< PWM_T::FCAPDAT4: FCAPDAT Mask             */
+
+#define PWM_RCAPDAT5_RCAPDAT_Pos         (0)                                               /*!< PWM_T::RCAPDAT5: RCAPDAT Position         */
+#define PWM_RCAPDAT5_RCAPDAT_Msk         (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos)            /*!< PWM_T::RCAPDAT5: RCAPDAT Mask             */
+
+#define PWM_FCAPDAT5_FCAPDAT_Pos         (0)                                               /*!< PWM_T::FCAPDAT5: FCAPDAT Position         */
+#define PWM_FCAPDAT5_FCAPDAT_Msk         (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos)            /*!< PWM_T::FCAPDAT5: FCAPDAT Mask             */
+
+#define PWM_PDMACTL_CHEN0_1_Pos          (0)                                               /*!< PWM_T::PDMACTL: CHEN0_1 Position          */
+#define PWM_PDMACTL_CHEN0_1_Msk          (0x1ul << PWM_PDMACTL_CHEN0_1_Pos)                /*!< PWM_T::PDMACTL: CHEN0_1 Mask              */
+
+#define PWM_PDMACTL_CAPMOD0_1_Pos        (1)                                               /*!< PWM_T::PDMACTL: CAPMOD0_1 Position        */
+#define PWM_PDMACTL_CAPMOD0_1_Msk        (0x3ul << PWM_PDMACTL_CAPMOD0_1_Pos)              /*!< PWM_T::PDMACTL: CAPMOD0_1 Mask            */
+
+#define PWM_PDMACTL_CAPORD0_1_Pos        (3)                                               /*!< PWM_T::PDMACTL: CAPORD0_1 Position        */
+#define PWM_PDMACTL_CAPORD0_1_Msk        (0x1ul << PWM_PDMACTL_CAPORD0_1_Pos)              /*!< PWM_T::PDMACTL: CAPORD0_1 Mask            */
+
+#define PWM_PDMACTL_CHSEL0_1_Pos         (4)                                               /*!< PWM_T::PDMACTL: CHSEL0_1 Position         */
+#define PWM_PDMACTL_CHSEL0_1_Msk         (0x1ul << PWM_PDMACTL_CHSEL0_1_Pos)               /*!< PWM_T::PDMACTL: CHSEL0_1 Mask             */
+
+#define PWM_PDMACTL_CHEN2_3_Pos          (8)                                               /*!< PWM_T::PDMACTL: CHEN2_3 Position          */
+#define PWM_PDMACTL_CHEN2_3_Msk          (0x1ul << PWM_PDMACTL_CHEN2_3_Pos)                /*!< PWM_T::PDMACTL: CHEN2_3 Mask              */
+
+#define PWM_PDMACTL_CAPMOD2_3_Pos        (9)                                               /*!< PWM_T::PDMACTL: CAPMOD2_3 Position        */
+#define PWM_PDMACTL_CAPMOD2_3_Msk        (0x3ul << PWM_PDMACTL_CAPMOD2_3_Pos)              /*!< PWM_T::PDMACTL: CAPMOD2_3 Mask            */
+
+#define PWM_PDMACTL_CAPORD2_3_Pos        (11)                                              /*!< PWM_T::PDMACTL: CAPORD2_3 Position        */
+#define PWM_PDMACTL_CAPORD2_3_Msk        (0x1ul << PWM_PDMACTL_CAPORD2_3_Pos)              /*!< PWM_T::PDMACTL: CAPORD2_3 Mask            */
+
+#define PWM_PDMACTL_CHSEL2_3_Pos         (12)                                              /*!< PWM_T::PDMACTL: CHSEL2_3 Position         */
+#define PWM_PDMACTL_CHSEL2_3_Msk         (0x1ul << PWM_PDMACTL_CHSEL2_3_Pos)               /*!< PWM_T::PDMACTL: CHSEL2_3 Mask             */
+
+#define PWM_PDMACTL_CHEN4_5_Pos          (16)                                              /*!< PWM_T::PDMACTL: CHEN4_5 Position          */
+#define PWM_PDMACTL_CHEN4_5_Msk          (0x1ul << PWM_PDMACTL_CHEN4_5_Pos)                /*!< PWM_T::PDMACTL: CHEN4_5 Mask              */
+
+#define PWM_PDMACTL_CAPMOD4_5_Pos        (17)                                              /*!< PWM_T::PDMACTL: CAPMOD4_5 Position        */
+#define PWM_PDMACTL_CAPMOD4_5_Msk        (0x3ul << PWM_PDMACTL_CAPMOD4_5_Pos)              /*!< PWM_T::PDMACTL: CAPMOD4_5 Mask            */
+
+#define PWM_PDMACTL_CAPORD4_5_Pos        (19)                                              /*!< PWM_T::PDMACTL: CAPORD4_5 Position        */
+#define PWM_PDMACTL_CAPORD4_5_Msk        (0x1ul << PWM_PDMACTL_CAPORD4_5_Pos)              /*!< PWM_T::PDMACTL: CAPORD4_5 Mask            */
+
+#define PWM_PDMACTL_CHSEL4_5_Pos         (20)                                              /*!< PWM_T::PDMACTL: CHSEL4_5 Position         */
+#define PWM_PDMACTL_CHSEL4_5_Msk         (0x1ul << PWM_PDMACTL_CHSEL4_5_Pos)               /*!< PWM_T::PDMACTL: CHSEL4_5 Mask             */
+
+#define PWM_PDMACAP0_1_CAPBUF_Pos        (0)                                               /*!< PWM_T::PDMACAP0_1: CAPBUF Position        */
+#define PWM_PDMACAP0_1_CAPBUF_Msk        (0xfffful << PWM_PDMACAP0_1_CAPBUF_Pos)           /*!< PWM_T::PDMACAP0_1: CAPBUF Mask            */
+
+#define PWM_PDMACAP2_3_CAPBUF_Pos        (0)                                               /*!< PWM_T::PDMACAP2_3: CAPBUF Position        */
+#define PWM_PDMACAP2_3_CAPBUF_Msk        (0xfffful << PWM_PDMACAP2_3_CAPBUF_Pos)           /*!< PWM_T::PDMACAP2_3: CAPBUF Mask            */
+
+#define PWM_PDMACAP4_5_CAPBUF_Pos        (0)                                               /*!< PWM_T::PDMACAP4_5: CAPBUF Position        */
+#define PWM_PDMACAP4_5_CAPBUF_Msk        (0xfffful << PWM_PDMACAP4_5_CAPBUF_Pos)           /*!< PWM_T::PDMACAP4_5: CAPBUF Mask            */
+
+#define PWM_CAPIEN_CAPRIENn_Pos          (0)                                               /*!< PWM_T::CAPIEN: CAPRIENn Position          */
+#define PWM_CAPIEN_CAPRIENn_Msk          (0x3ful << PWM_CAPIEN_CAPRIENn_Pos)               /*!< PWM_T::CAPIEN: CAPRIENn Mask              */
+
+#define PWM_CAPIEN_CAPRIEN0_Pos          (0)                                               /*!< PWM_T::CAPIEN: CAPRIEN0 Position          */
+#define PWM_CAPIEN_CAPRIEN0_Msk          (0x1ul << PWM_CAPIEN_CAPRIEN0_Pos)                /*!< PWM_T::CAPIEN: CAPRIEN0 Mask              */
+
+#define PWM_CAPIEN_CAPRIEN1_Pos          (1)                                               /*!< PWM_T::CAPIEN: CAPRIEN1 Position          */
+#define PWM_CAPIEN_CAPRIEN1_Msk          (0x1ul << PWM_CAPIEN_CAPRIEN1_Pos)                /*!< PWM_T::CAPIEN: CAPRIEN1 Mask              */
+
+#define PWM_CAPIEN_CAPRIEN2_Pos          (2)                                               /*!< PWM_T::CAPIEN: CAPRIEN2 Position          */
+#define PWM_CAPIEN_CAPRIEN2_Msk          (0x1ul << PWM_CAPIEN_CAPRIEN2_Pos)                /*!< PWM_T::CAPIEN: CAPRIEN2 Mask              */
+
+#define PWM_CAPIEN_CAPRIEN3_Pos          (3)                                               /*!< PWM_T::CAPIEN: CAPRIEN3 Position          */
+#define PWM_CAPIEN_CAPRIEN3_Msk          (0x1ul << PWM_CAPIEN_CAPRIEN3_Pos)                /*!< PWM_T::CAPIEN: CAPRIEN3 Mask              */
+
+#define PWM_CAPIEN_CAPRIEN4_Pos          (4)                                               /*!< PWM_T::CAPIEN: CAPRIEN4 Position          */
+#define PWM_CAPIEN_CAPRIEN4_Msk          (0x1ul << PWM_CAPIEN_CAPRIEN4_Pos)                /*!< PWM_T::CAPIEN: CAPRIEN4 Mask              */
+
+#define PWM_CAPIEN_CAPRIEN5_Pos          (5)                                               /*!< PWM_T::CAPIEN: CAPRIEN5 Position          */
+#define PWM_CAPIEN_CAPRIEN5_Msk          (0x1ul << PWM_CAPIEN_CAPRIEN5_Pos)                /*!< PWM_T::CAPIEN: CAPRIEN5 Mask              */
+
+#define PWM_CAPIEN_CAPFIENn_Pos          (8)                                               /*!< PWM_T::CAPIEN: CAPFIENn Position          */
+#define PWM_CAPIEN_CAPFIENn_Msk          (0x3ful << PWM_CAPIEN_CAPFIENn_Pos)               /*!< PWM_T::CAPIEN: CAPFIENn Mask              */
+
+#define PWM_CAPIEN_CAPFIEN0_Pos          (8)                                               /*!< PWM_T::CAPIEN: CAPFIEN0 Position          */
+#define PWM_CAPIEN_CAPFIEN0_Msk          (0x1ul << PWM_CAPIEN_CAPFIEN0_Pos)                /*!< PWM_T::CAPIEN: CAPFIEN0 Mask              */
+
+#define PWM_CAPIEN_CAPFIEN1_Pos          (9)                                               /*!< PWM_T::CAPIEN: CAPFIEN1 Position          */
+#define PWM_CAPIEN_CAPFIEN1_Msk          (0x1ul << PWM_CAPIEN_CAPFIEN1_Pos)                /*!< PWM_T::CAPIEN: CAPFIEN1 Mask              */
+
+#define PWM_CAPIEN_CAPFIEN2_Pos          (10)                                              /*!< PWM_T::CAPIEN: CAPFIEN2 Position          */
+#define PWM_CAPIEN_CAPFIEN2_Msk          (0x1ul << PWM_CAPIEN_CAPFIEN2_Pos)                /*!< PWM_T::CAPIEN: CAPFIEN2 Mask              */
+
+#define PWM_CAPIEN_CAPFIEN3_Pos          (11)                                              /*!< PWM_T::CAPIEN: CAPFIEN3 Position          */
+#define PWM_CAPIEN_CAPFIEN3_Msk          (0x1ul << PWM_CAPIEN_CAPFIEN3_Pos)                /*!< PWM_T::CAPIEN: CAPFIEN3 Mask              */
+
+#define PWM_CAPIEN_CAPFIEN4_Pos          (12)                                              /*!< PWM_T::CAPIEN: CAPFIEN4 Position          */
+#define PWM_CAPIEN_CAPFIEN4_Msk          (0x1ul << PWM_CAPIEN_CAPFIEN4_Pos)                /*!< PWM_T::CAPIEN: CAPFIEN4 Mask              */
+
+#define PWM_CAPIEN_CAPFIEN5_Pos          (13)                                              /*!< PWM_T::CAPIEN: CAPFIEN5 Position          */
+#define PWM_CAPIEN_CAPFIEN5_Msk          (0x1ul << PWM_CAPIEN_CAPFIEN5_Pos)                /*!< PWM_T::CAPIEN: CAPFIEN5 Mask              */
+
+#define PWM_CAPIF_CRLIFn_Pos             (0)                                               /*!< PWM_T::CAPIF: CRLIFn Position             */
+#define PWM_CAPIF_CRLIFn_Msk             (0x3ful << PWM_CAPIF_CRLIFn_Pos)                  /*!< PWM_T::CAPIF: CRLIFn Mask                 */
+
+#define PWM_CAPIF_CRLIF0_Pos             (0)                                               /*!< PWM_T::CAPIF: CRLIF0 Position             */
+#define PWM_CAPIF_CRLIF0_Msk             (0x1ul << PWM_CAPIF_CRLIF0_Pos)                   /*!< PWM_T::CAPIF: CRLIF0 Mask                 */
+
+#define PWM_CAPIF_CRLIF1_Pos             (1)                                               /*!< PWM_T::CAPIF: CRLIF1 Position             */
+#define PWM_CAPIF_CRLIF1_Msk             (0x1ul << PWM_CAPIF_CRLIF1_Pos)                   /*!< PWM_T::CAPIF: CRLIF1 Mask                 */
+
+#define PWM_CAPIF_CRLIF2_Pos             (2)                                               /*!< PWM_T::CAPIF: CRLIF2 Position             */
+#define PWM_CAPIF_CRLIF2_Msk             (0x1ul << PWM_CAPIF_CRLIF2_Pos)                   /*!< PWM_T::CAPIF: CRLIF2 Mask                 */
+
+#define PWM_CAPIF_CRLIF3_Pos             (3)                                               /*!< PWM_T::CAPIF: CRLIF3 Position             */
+#define PWM_CAPIF_CRLIF3_Msk             (0x1ul << PWM_CAPIF_CRLIF3_Pos)                   /*!< PWM_T::CAPIF: CRLIF3 Mask                 */
+
+#define PWM_CAPIF_CRLIF4_Pos             (4)                                               /*!< PWM_T::CAPIF: CRLIF4 Position             */
+#define PWM_CAPIF_CRLIF4_Msk             (0x1ul << PWM_CAPIF_CRLIF4_Pos)                   /*!< PWM_T::CAPIF: CRLIF4 Mask                 */
+
+#define PWM_CAPIF_CRLIF5_Pos             (5)                                               /*!< PWM_T::CAPIF: CRLIF5 Position             */
+#define PWM_CAPIF_CRLIF5_Msk             (0x1ul << PWM_CAPIF_CRLIF5_Pos)                   /*!< PWM_T::CAPIF: CRLIF5 Mask                 */
+
+#define PWM_CAPIF_CFLIFn_Pos             (8)                                               /*!< PWM_T::CAPIF: CFLIFn Position             */
+#define PWM_CAPIF_CFLIFn_Msk             (0x3ful << PWM_CAPIF_CFLIFn_Pos)                  /*!< PWM_T::CAPIF: CFLIFn Mask                 */
+
+#define PWM_CAPIF_CFLIF0_Pos             (8)                                               /*!< PWM_T::CAPIF: CFLIF0 Position             */
+#define PWM_CAPIF_CFLIF0_Msk             (0x1ul << PWM_CAPIF_CFLIF0_Pos)                   /*!< PWM_T::CAPIF: CFLIF0 Mask                 */
+
+#define PWM_CAPIF_CFLIF1_Pos             (9)                                               /*!< PWM_T::CAPIF: CFLIF1 Position             */
+#define PWM_CAPIF_CFLIF1_Msk             (0x1ul << PWM_CAPIF_CFLIF1_Pos)                   /*!< PWM_T::CAPIF: CFLIF1 Mask                 */
+
+#define PWM_CAPIF_CFLIF2_Pos             (10)                                              /*!< PWM_T::CAPIF: CFLIF2 Position             */
+#define PWM_CAPIF_CFLIF2_Msk             (0x1ul << PWM_CAPIF_CFLIF2_Pos)                   /*!< PWM_T::CAPIF: CFLIF2 Mask                 */
+
+#define PWM_CAPIF_CFLIF3_Pos             (11)                                              /*!< PWM_T::CAPIF: CFLIF3 Position             */
+#define PWM_CAPIF_CFLIF3_Msk             (0x1ul << PWM_CAPIF_CFLIF3_Pos)                   /*!< PWM_T::CAPIF: CFLIF3 Mask                 */
+
+#define PWM_CAPIF_CFLIF4_Pos             (12)                                              /*!< PWM_T::CAPIF: CFLIF4 Position             */
+#define PWM_CAPIF_CFLIF4_Msk             (0x1ul << PWM_CAPIF_CFLIF4_Pos)                   /*!< PWM_T::CAPIF: CFLIF4 Mask                 */
+
+#define PWM_CAPIF_CFLIF5_Pos             (13)                                              /*!< PWM_T::CAPIF: CFLIF5 Position             */
+#define PWM_CAPIF_CFLIF5_Msk             (0x1ul << PWM_CAPIF_CFLIF5_Pos)                   /*!< PWM_T::CAPIF: CFLIF5 Mask                 */
+
+#define PWM_PBUF_PBUF_Pos                (0)                                               /*!< PWM_T::PBUF: PBUF Position                */
+#define PWM_PBUF_PBUF_Msk                (0xfffful << PWM_PBUF_PBUF_Pos)                   /*!< PWM_T::PBUF: PBUF Mask                    */
+
+#define PWM_CMPBUF_CMPBUF_Pos            (0)                                               /*!< PWM_T::CMPBUF: CMPBUF Position            */
+#define PWM_CMPBUF_CMPBUF_Msk            (0xfffful << PWM_CMPBUF_CMPBUF_Pos)               /*!< PWM_T::CMPBUF: CMPBUF Mask                */
+
+#define PWM_FTCBUF0_1_FTCMPBUF_Pos       (0)                                               /*!< PWM_T::FTCBUF0_1: FTCMPBUF Position       */
+#define PWM_FTCBUF0_1_FTCMPBUF_Msk       (0xfffful << PWM_FTCBUF0_1_FTCMPBUF_Pos)          /*!< PWM_T::FTCBUF0_1: FTCMPBUF Mask           */
+
+#define PWM_FTCBUF2_3_FTCMPBUF_Pos       (0)                                               /*!< PWM_T::FTCBUF2_3: FTCMPBUF Position       */
+#define PWM_FTCBUF2_3_FTCMPBUF_Msk       (0xfffful << PWM_FTCBUF2_3_FTCMPBUF_Pos)          /*!< PWM_T::FTCBUF2_3: FTCMPBUF Mask           */
+
+#define PWM_FTCBUF4_5_FTCMPBUF_Pos       (0)                                               /*!< PWM_T::FTCBUF4_5: FTCMPBUF Position       */
+#define PWM_FTCBUF4_5_FTCMPBUF_Msk       (0xfffful << PWM_FTCBUF4_5_FTCMPBUF_Pos)          /*!< PWM_T::FTCBUF4_5: FTCMPBUF Mask           */
+
+#define PWM_FTCI_FTCMUn_Pos              (0)                                               /*!< PWM_T::FTCI: FTCMUn Position              */
+#define PWM_FTCI_FTCMUn_Msk              (0x7ul << PWM_FTCI_FTCMUn_Pos)                    /*!< PWM_T::FTCI: FTCMUn Mask                  */
+
+#define PWM_FTCI_FTCMU0_Pos              (0)                                               /*!< PWM_T::FTCI: FTCMU0 Position              */
+#define PWM_FTCI_FTCMU0_Msk              (0x1ul << PWM_FTCI_FTCMU0_Pos)                    /*!< PWM_T::FTCI: FTCMU0 Mask                  */
+
+#define PWM_FTCI_FTCMU2_Pos              (1)                                               /*!< PWM_T::FTCI: FTCMU2 Position              */
+#define PWM_FTCI_FTCMU2_Msk              (0x1ul << PWM_FTCI_FTCMU2_Pos)                    /*!< PWM_T::FTCI: FTCMU2 Mask                  */
+
+#define PWM_FTCI_FTCMU4_Pos              (2)                                               /*!< PWM_T::FTCI: FTCMU4 Position              */
+#define PWM_FTCI_FTCMU4_Msk              (0x1ul << PWM_FTCI_FTCMU4_Pos)                    /*!< PWM_T::FTCI: FTCMU4 Mask                  */
+
+#define PWM_FTCI_FTCMDn_Pos              (8)                                               /*!< PWM_T::FTCI: FTCMDn Position              */
+#define PWM_FTCI_FTCMDn_Msk              (0x7ul << PWM_FTCI_FTCMDn_Pos)                    /*!< PWM_T::FTCI: FTCMDn Mask                  */
+
+#define PWM_FTCI_FTCMD0_Pos              (8)                                               /*!< PWM_T::FTCI: FTCMD0 Position              */
+#define PWM_FTCI_FTCMD0_Msk              (0x1ul << PWM_FTCI_FTCMD0_Pos)                    /*!< PWM_T::FTCI: FTCMD0 Mask                  */
+
+#define PWM_FTCI_FTCMD2_Pos              (9)                                               /*!< PWM_T::FTCI: FTCMD2 Position              */
+#define PWM_FTCI_FTCMD2_Msk              (0x1ul << PWM_FTCI_FTCMD2_Pos)                    /*!< PWM_T::FTCI: FTCMD2 Mask                  */
+
+#define PWM_FTCI_FTCMD4_Pos              (10)                                              /*!< PWM_T::FTCI: FTCMD4 Position              */
+#define PWM_FTCI_FTCMD4_Msk              (0x1ul << PWM_FTCI_FTCMD4_Pos)                    /*!< PWM_T::FTCI: FTCMD4 Mask                  */
+
+/**@}*/ /* PWM_CONST */
+/**@}*/ /* end of PWM register group */
+
+
+/*---------------------- Real Time Clock Controller -------------------------*/
+/**
+    @addtogroup RTC Real Time Clock Controller(RTC)
+    Memory Mapped Structure for RTC Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var RTC_T::INIT
+ * Offset: 0x00  RTC Initiation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |INIT[0]/ACTIVE|RTC Active Status (Read Only)
+ * |        |          |0 = RTC is at reset state.
+ * |        |          |1 = RTC is at normal active state.
+ * |[31:1]  |INIT[31:1]|RTC Initiation
+ * |        |          |When RTC block is powered on, RTC is at reset state.
+ * |        |          |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state.
+ * |        |          |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
+ * |        |          |The INIT is a write-only field and read value will be always 0.
+ * @var RTC_T::RWEN
+ * Offset: 0x04  RTC Access Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |RWEN      |RTC Register Access Enable Password (Write Only)
+ * |        |          |Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock.
+ * |[16]    |RWENF     |RTC Register Access Enable Flag (Read Only)
+ * |        |          |0 = RTC register read/write Disabled.
+ * |        |          |1 = RTC register read/write Enabled.
+ * |        |          |This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock.
+ * @var RTC_T::FREQADJ
+ * Offset: 0x08  RTC Frequency Compensation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |FRACTION  |Fraction Part
+ * |        |          |Formula = (fraction part of detected value) x 60.
+ * |        |          |Note: Digit in RTC_FREQADJ must be expressed as hexadecimal number.
+ * |[11:8]  |INTEGER   |Integer Part
+ * @var RTC_T::TIME
+ * Offset: 0x0C  Time Loading Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |SEC       |1-Sec Time Digit (0~9)
+ * |[6:4]   |TENSEC    |10-Sec Time Digit (0~5)
+ * |[11:8]  |MIN       |1-Min Time Digit (0~9)
+ * |[14:12] |TENMIN    |10-Min Time Digit (0~5)
+ * |[19:16] |HR        |1-Hour Time Digit (0~9)
+ * |[21:20] |TENHR     |10-Hour Time Digit (0~2)
+ * @var RTC_T::CAL
+ * Offset: 0x10  RTC Calendar Loading Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |DAY       |1-Day Calendar Digit (0~9)
+ * |[5:4]   |TENDAY    |10-Day Calendar Digit (0~3)
+ * |[11:8]  |MON       |1-Month Calendar Digit (0~9)
+ * |[12]    |TENMON    |10-Month Calendar Digit (0~1)
+ * |[19:16] |YEAR      |1-Year Calendar Digit (0~9)
+ * |[23:20] |TENYEAR   |10-Year Calendar Digit (0~9)
+ * @var RTC_T::CLKFMT
+ * Offset: 0x14  Time Scale Selection Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |24HEN     |24-Hour / 12-Hour Time Scale Selection
+ * |        |          |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
+ * |        |          |0 = 12-hour time scale with AM and PM indication selected.
+ * |        |          |1 = 24-hour time scale selected.
+ * @var RTC_T::WEEKDAY
+ * Offset: 0x18  Day of the Week Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[2:0]   |WEEKDAY   |Day Of The Week Register
+ * |        |          |000 = Sunday.
+ * |        |          |001 = Monday.
+ * |        |          |010 = Tuesday.
+ * |        |          |011 = Wednesday.
+ * |        |          |100 = Thursday.
+ * |        |          |101 = Friday.
+ * |        |          |110 = Saturday.
+ * |        |          |111 = Reserved.
+ * @var RTC_T::TALM
+ * Offset: 0x1C  Time Alarm Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |SEC       |1-Sec Time Digit of Alarm Setting (0~9)
+ * |[6:4]   |TENSEC    |10-Sec Time Digit of Alarm Setting (0~5)
+ * |[11:8]  |MIN       |1-Min Time Digit of Alarm Setting (0~9)
+ * |[14:12] |TENMIN    |10-Min Time Digit of Alarm Setting (0~5)
+ * |[19:16] |HR        |1-Hour Time Digit of Alarm Setting (0~9)
+ * |[21:20] |TENHR     |10-Hour Time Digit of Alarm Setting (0~2)
+ * @var RTC_T::CALM
+ * Offset: 0x20  Calendar Alarm Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |DAY       |1-Day Calendar Digit of Alarm Setting (0~9)
+ * |[5:4]   |TENDAY    |10-Day Calendar Digit of Alarm Setting (0~3)
+ * |[11:8]  |MON       |1-Month Calendar Digit of Alarm Setting (0~9)
+ * |[12]    |TENMON    |10-Month Calendar Digit of Alarm Setting (0~1)
+ * |[19:16] |YEAR      |1-Year Calendar Digit of Alarm Setting (0~9)
+ * |[23:20] |TENYEAR   |10-Year Calendar Digit of Alarm Setting (0~9)
+ * @var RTC_T::LEAPYEAR
+ * Offset: 0x24  RTC Leap Year Indicator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |LEAPYEAR  |Leap Year Indication Register (Read Only)
+ * |        |          |0 = This year is not a leap year.
+ * |        |          |1 = This year is leap year.
+ * @var RTC_T::INTEN
+ * Offset: 0x28  RTC Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ALMIEN    |Alarm Interrupt Enable Bit
+ * |        |          |0 = RTC Alarm interrupt Disabled.
+ * |        |          |1 = RTC Alarm interrupt Enabled.
+ * |[1]     |TICKIEN   |Time Tick Interrupt Enable Bit
+ * |        |          |0 = RTC Time Tick interrupt Disabled.
+ * |        |          |1 = RTC Time Tick interrupt Enabled.
+ * |[2]     |SNPDIEN   |Snoop Detection Interrupt Enable Bit
+ * |        |          |0 = Snoop detected interrupt Disabled.
+ * |        |          |1 = Snoop detected interrupt Enabled.
+ * @var RTC_T::INTSTS
+ * Offset: 0x2C  RTC Interrupt Indicator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |ALMIF     |RTC Alarm Interrupt Flag
+ * |        |          |When RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1.
+ * |        |          |Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.
+ * |        |          |0 = Alarm condition is not matched.
+ * |        |          |1 = Alarm condition is matched.
+ * |        |          |Note: Write 1 to clear this bit.
+ * |[1]     |TICKIF    |RTC Time Tick Interrupt Flag
+ * |        |          |When RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1.
+ * |        |          |Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.
+ * |        |          |0 = Tick condition does not occur.
+ * |        |          |1 = Tick condition occur.
+ * |        |          |Note: Write 1 to clear to clear this bit.
+ * |[2]     |SNPDIF    |Snoop Detect Interrupt Flag
+ * |        |          |When tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1.
+ * |        |          |Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled.
+ * |        |          |0 = No snoop event is detected.
+ * |        |          |1 = Snoop event is detected.
+ * |        |          |Note: Write 1 to clear this bit.
+ * @var RTC_T::TICK
+ * Offset: 0x30  RTC Time Tick Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[2:0]   |TICK      |Time Tick Register
+ * |        |          |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
+ * |        |          |000 = Time tick is 1 second.
+ * |        |          |001 = Time tick is 1/2 second.
+ * |        |          |010 = Time tick is 1/4 second.
+ * |        |          |011 = Time tick is 1/8 second.
+ * |        |          |100 = Time tick is 1/16 second.
+ * |        |          |101 = Time tick is 1/32 second.
+ * |        |          |110 = Time tick is 1/64 second.
+ * |        |          |111 = Time tick is 1/28 second.
+ * |        |          |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
+ * @var RTC_T::TAMSK
+ * Offset: 0x34  Time Alarm Mask Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |MSEC      |Mask 1-Sec Time Digit of Alarm Setting (0~9)
+ * |[1]     |MTENSEC   |Mask 10-Sec Time Digit of Alarm Setting (0~5)
+ * |[2]     |MMIN      |Mask 1-Min Time Digit of Alarm Setting (0~9)
+ * |[3]     |MTENMIN   |Mask 10-Min Time Digit of Alarm Setting (0~5)
+ * |[4]     |MHR       |Mask 1-Hour Time Digit of Alarm Setting (0~9)
+ * |[5]     |MTENHR    |Mask 10-Hour Time Digit of Alarm Setting (0~2)
+ * @var RTC_T::CAMSK
+ * Offset: 0x38  Calendar Alarm Mask Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |MDAY      |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
+ * |[1]     |MTENDAY   |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
+ * |[2]     |MMON      |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
+ * |[3]     |MTENMON   |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
+ * |[4]     |MYEAR     |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
+ * |[5]     |MTENYEAR  |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
+ * @var RTC_T::SPRCTL
+ * Offset: 0x3C  RTC Spare Functional Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SNPDEN    |Snoop Detection Enable Bit
+ * |        |          |0 = TAMPER pin detection is Disabled.
+ * |        |          |1 = TAMPER pin detection is Enabled.
+ * |[1]     |SNPTYPE0  |Snoop Detection Level
+ * |        |          |This bit controls TAMPER detect event is high level/rising edge or low level/falling edge.
+ * |        |          |0 = Low level/Falling edge detection.
+ * |        |          |1 = High level/Rising edge detection.
+ * |[2]     |SPRRWEN   |Spare Register Enable Bit
+ * |        |          |0 = Spare register is Disabled.
+ * |        |          |1 = Spare register is Enabled.
+ * |        |          |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
+ * |[3]     |SNPTYPE1  |Snoop Detection Mode
+ * |        |          |This bit controls TAMPER pin is edge or level detection
+ * |        |          |0 = Level detection.
+ * |        |          |1 = Edge detection.
+ * |[5]     |SPRCSTS   |SPR Clear Flag
+ * |        |          |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected.
+ * |        |          |0 = Spare register content is not cleared.
+ * |        |          |1 = Spare register content is cleared.
+ * |        |          |Writes 1 to clear this bit.
+ * |[7]     |SPRRWRDY  |SPR Register Ready
+ * |        |          |This bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are ready to be accessed.
+ * |        |          |After user writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19, read this bit to check if these registers are updated done is necessary.
+ * |        |          |0 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 updating is in progress.
+ * |        |          |1 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are updated done and ready to be accessed.
+ * |        |          |Note: This bit is read only and any write to it won't take any effect.
+ * @var RTC_T::SPR
+ * Offset: 0x40 ~ 0x8C  RTC Spare Register 0 ~ 19
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |SPARE     |Spare Register
+ * |        |          |This field is used to store back-up information defined by user.
+ * |        |          |This field will be cleared by hardware automatically once a snooper pin event is detected.
+ * |        |          |Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled.
+ * @var RTC_T::LXTCTL
+ * Offset: 0x100  RTC 32.768 kHz Oscillator Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |LXTEN     |Backup Domain 32K Oscillator Enable Bit
+ * |        |          |0 = Oscillator is Disabled.
+ * |        |          |1 = Oscillator is Enabled.
+ * |        |          |This bit controls 32 kHz oscillator on/off.
+ * |        |          |User can set either LXTEN in RTC domain or system manager control register CLK_PWRCTL[1] (LXTEN) to enable 32 kHz oscillator.
+ * |        |          |If this bit is set 1, X32 kHz oscillator keep running after system power is turned off, if this bit is clear to 0, oscillator is turned off when system power is turned off.
+ * |[3:1]   |GAIN      |Oscillator Gain Option
+ * |        |          |User can select oscillator gain according to crystal external loading and operating temperature range.
+ * |        |          |The larger gain value corresponding to stronger driving capability and higher power consumption.
+ * |        |          |000 = L0 mode.
+ * |        |          |001 = L1 mode.
+ * |        |          |010 = L2 mode.
+ * |        |          |011 = L3 mode.
+ * |        |          |100 = L4 mode.
+ * |        |          |101 = L5 mode.
+ * |        |          |110 = L6 mode.
+ * |        |          |111 = L7 mode (Default).
+ * @var RTC_T::LXTOCTL
+ * Offset: 0x104  X32KO Pin Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |OPMODE    |GPF0 Operation Mode
+ * |        |          |00 = X32KO (PF.0) is input only mode, without pull-up resistor.
+ * |        |          |01 = X32KO (PF.0) is output push pull mode.
+ * |        |          |10 = X32KO (PF.0) is open drain mode.
+ * |        |          |11 = X32KO (PF.0) is input only mode with internal pull up.
+ * |[2]     |DOUT      |IO Output Data
+ * |        |          |0 = X32KO (PF.0) output low.
+ * |        |          |1 = X32KO (PF.0) output high.
+ * |[3]     |CTLSEL    |IO Pin State Backup Selection
+ * |        |          |When low speed 32 kHz oscillator is disabled, X32KO (PF.0) pin can be used as GPIO function.
+ * |        |          |User can program CTLSEL bit to decide X32KO (PF.0) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register.
+ * |        |          |0 = X32KO (PF.0) pin I/O function is controlled by GPIO module.
+ * |        |          |It becomes floating when system power is turned off.
+ * |        |          |1 = X32KO (PF.0) pin I/O function is controlled by VBAT power domain, X32KO (PF.0) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
+ * |        |          |I/O pin keeps the previous state after system power is turned off.
+ * @var RTC_T::LXTICTL
+ * Offset: 0x108  X32KI Pin Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |OPMODE    |IO Operation Mode
+ * |        |          |00 = X32KI (PF.1) is input only mode, without pull-up resistor.
+ * |        |          |01 = X32KI (PF.1) is output push pull mode.
+ * |        |          |10 = X32KI (PF.1) is open drain mode.
+ * |        |          |11 = X32KI (PF.1) is input only mode with internal pull up.
+ * |[2]     |DOUT      |IO Output Data
+ * |        |          |0 = X32KI (PF.1) output low.
+ * |        |          |1 = X32KI (PF.1) output high.
+ * |[3]     |CTLSEL    |IO Pin State Backup Selection
+ * |        |          |When low speed 32 kHz oscillator is disabled, X32KI (PF.1) pin can be used as GPIO function.
+ * |        |          |User can program CTLSEL bit to decide X32KI (PF.1) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register.
+ * |        |          |0 = X32KI (PF.1) pin I/O function is controlled by GPIO module.
+ * |        |          |It becomes floating state when system power is turned off.
+ * |        |          |1 = X32KI (PF.1) pin I/O function is controlled by VBAT power domain, X32KI (PF.1) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
+ * |        |          |I/O pin keeps the previous state after system power is turned off.
+ * @var RTC_T::TAMPCTL
+ * Offset: 0x10C  TAMPER Pin Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |OPMODE    |IO Operation Mode
+ * |        |          |00 = TAMPER (PF.2) is input only mode, without pull-up resistor.
+ * |        |          |01 = TAMPER (PF.2) is output push pull mode.
+ * |        |          |10 = TAMPER (PF.2) is open drain mode.
+ * |        |          |11 = TAMPER (PF.2) is input only mode with internal pull up.
+ * |[2]     |DOUT      |IO Output Data
+ * |        |          |0 = TAMPER (PF.2) output low.
+ * |        |          |1 = TAMPER (PF.2) output high.
+ * |[3]     |CTLSEL    |IO Pin State Backup Selection
+ * |        |          |When tamper function is disabled, TAMPER pin can be used as GPIO function.
+ * |        |          |User can program CTLSEL bit to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register.
+ * |        |          |0 =TAMPER (PF.2) I/O function is controlled by GPIO module.
+ * |        |          |It becomes floating state when system power is turned off.
+ * |        |          |1 =TAMPER (PF.2) I/O function is controlled by VBAT power domain.
+ * |        |          |PF.2 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
+ * |        |          |I/O pin state keeps previous state after system power is turned off.
+ */
+
+    __IO uint32_t INIT;          /* Offset: 0x00  RTC Initiation Register                                            */
+    __O  uint32_t RWEN;          /* Offset: 0x04  RTC Access Enable Register                                         */
+    __IO uint32_t FREQADJ;       /* Offset: 0x08  RTC Frequency Compensation Register                                */
+    __IO uint32_t TIME;          /* Offset: 0x0C  Time Loading Register                                              */
+    __IO uint32_t CAL;           /* Offset: 0x10  RTC Calendar Loading Register                                      */
+    __IO uint32_t CLKFMT;        /* Offset: 0x14  Time Scale Selection Register                                      */
+    __IO uint32_t WEEKDAY;       /* Offset: 0x18  Day of the Week Register                                           */
+    __IO uint32_t TALM;          /* Offset: 0x1C  Time Alarm Register                                                */
+    __IO uint32_t CALM;          /* Offset: 0x20  Calendar Alarm Register                                            */
+    __I  uint32_t LEAPYEAR;      /* Offset: 0x24  RTC Leap Year Indicator Register                                   */
+    __IO uint32_t INTEN;         /* Offset: 0x28  RTC Interrupt Enable Register                                      */
+    __IO uint32_t INTSTS;        /* Offset: 0x2C  RTC Interrupt Indicator Register                                   */
+    __IO uint32_t TICK;          /* Offset: 0x30  RTC Time Tick Register                                             */
+    __IO uint32_t TAMSK;         /* Offset: 0x34  Time Alarm Mask Register                                           */
+    __IO uint32_t CAMSK;         /* Offset: 0x38  Calendar Alarm Mask Register                                       */
+    __IO uint32_t SPRCTL;        /* Offset: 0x3C  RTC Spare Functional Control Register                              */
+    __IO uint32_t SPR[20];       /* Offset: 0x40 ~ 0x8C  RTC Spare Register 0 ~ 19                                   */
+    __I  uint32_t RESERVE0[28]; 
+    __IO uint32_t LXTCTL;        /* Offset: 0x100  RTC 32.768 kHz Oscillator Control Register                        */
+    __IO uint32_t LXTOCTL;       /* Offset: 0x104  X32KO Pin Control Register                                        */
+    __IO uint32_t LXTICTL;       /* Offset: 0x108  X32KI Pin Control Register                                        */
+    __IO uint32_t TAMPCTL;       /* Offset: 0x10C  TAMPER Pin Control Register                                       */
+
+} RTC_T;
+
+
+
+/**
+    @addtogroup RTC_CONST RTC Bit Field Definition
+    Constant Definitions for RTC Controller
+@{ */
+
+#define RTC_INIT_ACTIVE_Pos              (0)                                               /*!< RTC_T::INIT: ACTIVE Position              */
+#define RTC_INIT_ACTIVE_Msk              (0x1ul << RTC_INIT_ACTIVE_Pos)                    /*!< RTC_T::INIT: ACTIVE Mask                  */
+
+#define RTC_INIT_INIT_Pos                (0)                                               /*!< RTC_T::INIT: INIT Position                */
+#define RTC_INIT_INIT_Msk                (0xfffffffful << RTC_INIT_INIT_Pos)               /*!< RTC_T::INIT: INIT Mask                    */
+
+#define RTC_RWEN_RWEN_Pos                (0)                                               /*!< RTC_T::RWEN: RWEN Position                */
+#define RTC_RWEN_RWEN_Msk                (0xfffful << RTC_RWEN_RWEN_Pos)                   /*!< RTC_T::RWEN: RWEN Mask                    */
+
+#define RTC_RWEN_RWENF_Pos               (16)                                              /*!< RTC_T::RWEN: RWENF Position               */
+#define RTC_RWEN_RWENF_Msk               (0x1ul << RTC_RWEN_RWENF_Pos)                     /*!< RTC_T::RWEN: RWENF Mask                   */
+
+#define RTC_FREQADJ_FRACTION_Pos         (0)                                               /*!< RTC_T::FREQADJ: FRACTION Position         */
+#define RTC_FREQADJ_FRACTION_Msk         (0x3ful << RTC_FREQADJ_FRACTION_Pos)              /*!< RTC_T::FREQADJ: FRACTION Mask             */
+
+#define RTC_FREQADJ_INTEGER_Pos          (8)                                               /*!< RTC_T::FREQADJ: INTEGER Position          */
+#define RTC_FREQADJ_INTEGER_Msk          (0xful << RTC_FREQADJ_INTEGER_Pos)                /*!< RTC_T::FREQADJ: INTEGER Mask              */
+
+#define RTC_TIME_SEC_Pos                 (0)                                               /*!< RTC_T::TIME: SEC Position                 */
+#define RTC_TIME_SEC_Msk                 (0xful << RTC_TIME_SEC_Pos)                       /*!< RTC_T::TIME: SEC Mask                     */
+
+#define RTC_TIME_TENSEC_Pos              (4)                                               /*!< RTC_T::TIME: TENSEC Position              */
+#define RTC_TIME_TENSEC_Msk              (0x7ul << RTC_TIME_TENSEC_Pos)                    /*!< RTC_T::TIME: TENSEC Mask                  */
+
+#define RTC_TIME_MIN_Pos                 (8)                                               /*!< RTC_T::TIME: MIN Position                 */
+#define RTC_TIME_MIN_Msk                 (0xful << RTC_TIME_MIN_Pos)                       /*!< RTC_T::TIME: MIN Mask                     */
+
+#define RTC_TIME_TENMIN_Pos              (12)                                              /*!< RTC_T::TIME: TENMIN Position              */
+#define RTC_TIME_TENMIN_Msk              (0x7ul << RTC_TIME_TENMIN_Pos)                    /*!< RTC_T::TIME: TENMIN Mask                  */
+
+#define RTC_TIME_HR_Pos                  (16)                                              /*!< RTC_T::TIME: HR Position                  */
+#define RTC_TIME_HR_Msk                  (0xful << RTC_TIME_HR_Pos)                        /*!< RTC_T::TIME: HR Mask                      */
+
+#define RTC_TIME_TENHR_Pos               (20)                                              /*!< RTC_T::TIME: TENHR Position               */
+#define RTC_TIME_TENHR_Msk               (0x3ul << RTC_TIME_TENHR_Pos)                     /*!< RTC_T::TIME: TENHR Mask                   */
+
+#define RTC_CAL_DAY_Pos                  (0)                                               /*!< RTC_T::CAL: DAY Position                  */
+#define RTC_CAL_DAY_Msk                  (0xful << RTC_CAL_DAY_Pos)                        /*!< RTC_T::CAL: DAY Mask                      */
+
+#define RTC_CAL_TENDAY_Pos               (4)                                               /*!< RTC_T::CAL: TENDAY Position               */
+#define RTC_CAL_TENDAY_Msk               (0x3ul << RTC_CAL_TENDAY_Pos)                     /*!< RTC_T::CAL: TENDAY Mask                   */
+
+#define RTC_CAL_MON_Pos                  (8)                                               /*!< RTC_T::CAL: MON Position                  */
+#define RTC_CAL_MON_Msk                  (0xful << RTC_CAL_MON_Pos)                        /*!< RTC_T::CAL: MON Mask                      */
+
+#define RTC_CAL_TENMON_Pos               (12)                                              /*!< RTC_T::CAL: TENMON Position               */
+#define RTC_CAL_TENMON_Msk               (0x1ul << RTC_CAL_TENMON_Pos)                     /*!< RTC_T::CAL: TENMON Mask                   */
+
+#define RTC_CAL_YEAR_Pos                 (16)                                              /*!< RTC_T::CAL: YEAR Position                 */
+#define RTC_CAL_YEAR_Msk                 (0xful << RTC_CAL_YEAR_Pos)                       /*!< RTC_T::CAL: YEAR Mask                     */
+
+#define RTC_CAL_TENYEAR_Pos              (20)                                              /*!< RTC_T::CAL: TENYEAR Position              */
+#define RTC_CAL_TENYEAR_Msk              (0xful << RTC_CAL_TENYEAR_Pos)                    /*!< RTC_T::CAL: TENYEAR Mask                  */
+
+#define RTC_CLKFMT_24HEN_Pos             (0)                                               /*!< RTC_T::CLKFMT: 24HEN Position             */
+#define RTC_CLKFMT_24HEN_Msk             (0x1ul << RTC_CLKFMT_24HEN_Pos)                   /*!< RTC_T::CLKFMT: 24HEN Mask                 */
+
+#define RTC_WEEKDAY_WEEKDAY_Pos          (0)                                               /*!< RTC_T::WEEKDAY: WEEKDAY Position          */
+#define RTC_WEEKDAY_WEEKDAY_Msk          (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos)                /*!< RTC_T::WEEKDAY: WEEKDAY Mask              */
+
+#define RTC_TALM_SEC_Pos                 (0)                                               /*!< RTC_T::TALM: SEC Position                 */
+#define RTC_TALM_SEC_Msk                 (0xful << RTC_TALM_SEC_Pos)                       /*!< RTC_T::TALM: SEC Mask                     */
+
+#define RTC_TALM_TENSEC_Pos              (4)                                               /*!< RTC_T::TALM: TENSEC Position              */
+#define RTC_TALM_TENSEC_Msk              (0x7ul << RTC_TALM_TENSEC_Pos)                    /*!< RTC_T::TALM: TENSEC Mask                  */
+
+#define RTC_TALM_MIN_Pos                 (8)                                               /*!< RTC_T::TALM: MIN Position                 */
+#define RTC_TALM_MIN_Msk                 (0xful << RTC_TALM_MIN_Pos)                       /*!< RTC_T::TALM: MIN Mask                     */
+
+#define RTC_TALM_TENMIN_Pos              (12)                                              /*!< RTC_T::TALM: TENMIN Position              */
+#define RTC_TALM_TENMIN_Msk              (0x7ul << RTC_TALM_TENMIN_Pos)                    /*!< RTC_T::TALM: TENMIN Mask                  */
+
+#define RTC_TALM_HR_Pos                  (16)                                              /*!< RTC_T::TALM: HR Position                  */
+#define RTC_TALM_HR_Msk                  (0xful << RTC_TALM_HR_Pos)                        /*!< RTC_T::TALM: HR Mask                      */
+
+#define RTC_TALM_TENHR_Pos               (20)                                              /*!< RTC_T::TALM: TENHR Position               */
+#define RTC_TALM_TENHR_Msk               (0x3ul << RTC_TALM_TENHR_Pos)                     /*!< RTC_T::TALM: TENHR Mask                   */
+
+#define RTC_CALM_DAY_Pos                 (0)                                               /*!< RTC_T::CALM: DAY Position                 */
+#define RTC_CALM_DAY_Msk                 (0xful << RTC_CALM_DAY_Pos)                       /*!< RTC_T::CALM: DAY Mask                     */
+
+#define RTC_CALM_TENDAY_Pos              (4)                                               /*!< RTC_T::CALM: TENDAY Position              */
+#define RTC_CALM_TENDAY_Msk              (0x3ul << RTC_CALM_TENDAY_Pos)                    /*!< RTC_T::CALM: TENDAY Mask                  */
+
+#define RTC_CALM_MON_Pos                 (8)                                               /*!< RTC_T::CALM: MON Position                 */
+#define RTC_CALM_MON_Msk                 (0xful << RTC_CALM_MON_Pos)                       /*!< RTC_T::CALM: MON Mask                     */
+
+#define RTC_CALM_TENMON_Pos              (12)                                              /*!< RTC_T::CALM: TENMON Position              */
+#define RTC_CALM_TENMON_Msk              (0x1ul << RTC_CALM_TENMON_Pos)                    /*!< RTC_T::CALM: TENMON Mask                  */
+
+#define RTC_CALM_YEAR_Pos                (16)                                              /*!< RTC_T::CALM: YEAR Position                */
+#define RTC_CALM_YEAR_Msk                (0xful << RTC_CALM_YEAR_Pos)                      /*!< RTC_T::CALM: YEAR Mask                    */
+
+#define RTC_CALM_TENYEAR_Pos             (20)                                              /*!< RTC_T::CALM: TENYEAR Position             */
+#define RTC_CALM_TENYEAR_Msk             (0xful << RTC_CALM_TENYEAR_Pos)                   /*!< RTC_T::CALM: TENYEAR Mask                 */
+
+#define RTC_LEAPYEAR_LEAPYEAR_Pos        (0)                                               /*!< RTC_T::LEAPYEAR: LEAPYEAR Position        */
+#define RTC_LEAPYEAR_LEAPYEAR_Msk        (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos)              /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask            */
+
+#define RTC_INTEN_ALMIEN_Pos             (0)                                               /*!< RTC_T::INTEN: ALMIEN Position             */
+#define RTC_INTEN_ALMIEN_Msk             (0x1ul << RTC_INTEN_ALMIEN_Pos)                   /*!< RTC_T::INTEN: ALMIEN Mask                 */
+
+#define RTC_INTEN_TICKIEN_Pos            (1)                                               /*!< RTC_T::INTEN: TICKIEN Position            */
+#define RTC_INTEN_TICKIEN_Msk            (0x1ul << RTC_INTEN_TICKIEN_Pos)                  /*!< RTC_T::INTEN: TICKIEN Mask                */
+
+#define RTC_INTEN_SNPDIEN_Pos            (2)                                               /*!< RTC_T::INTEN: SNPDIEN Position            */
+#define RTC_INTEN_SNPDIEN_Msk            (0x1ul << RTC_INTEN_SNPDIEN_Pos)                  /*!< RTC_T::INTEN: SNPDIEN Mask                */
+
+#define RTC_INTSTS_ALMIF_Pos             (0)                                               /*!< RTC_T::INTSTS: ALMIF Position             */
+#define RTC_INTSTS_ALMIF_Msk             (0x1ul << RTC_INTSTS_ALMIF_Pos)                   /*!< RTC_T::INTSTS: ALMIF Mask                 */
+
+#define RTC_INTSTS_TICKIF_Pos            (1)                                               /*!< RTC_T::INTSTS: TICKIF Position            */
+#define RTC_INTSTS_TICKIF_Msk            (0x1ul << RTC_INTSTS_TICKIF_Pos)                  /*!< RTC_T::INTSTS: TICKIF Mask                */
+
+#define RTC_INTSTS_SNPDIF_Pos            (2)                                               /*!< RTC_T::INTSTS: SNPDIF Position            */
+#define RTC_INTSTS_SNPDIF_Msk            (0x1ul << RTC_INTSTS_SNPDIF_Pos)                  /*!< RTC_T::INTSTS: SNPDIF Mask                */
+
+#define RTC_TICK_TICK_Pos                (0)                                               /*!< RTC_T::TICK: TICK Position                */
+#define RTC_TICK_TICK_Msk                (0x7ul << RTC_TICK_TICK_Pos)                      /*!< RTC_T::TICK: TICK Mask                    */
+
+#define RTC_TAMSK_MSEC_Pos               (0)                                               /*!< RTC_T::TAMSK: MSEC Position               */
+#define RTC_TAMSK_MSEC_Msk               (0x1ul << RTC_TAMSK_MSEC_Pos)                     /*!< RTC_T::TAMSK: MSEC Mask                   */
+
+#define RTC_TAMSK_MTENSEC_Pos            (1)                                               /*!< RTC_T::TAMSK: MTENSEC Position            */
+#define RTC_TAMSK_MTENSEC_Msk            (0x1ul << RTC_TAMSK_MTENSEC_Pos)                  /*!< RTC_T::TAMSK: MTENSEC Mask                */
+
+#define RTC_TAMSK_MMIN_Pos               (2)                                               /*!< RTC_T::TAMSK: MMIN Position               */
+#define RTC_TAMSK_MMIN_Msk               (0x1ul << RTC_TAMSK_MMIN_Pos)                     /*!< RTC_T::TAMSK: MMIN Mask                   */
+
+#define RTC_TAMSK_MTENMIN_Pos            (3)                                               /*!< RTC_T::TAMSK: MTENMIN Position            */
+#define RTC_TAMSK_MTENMIN_Msk            (0x1ul << RTC_TAMSK_MTENMIN_Pos)                  /*!< RTC_T::TAMSK: MTENMIN Mask                */
+
+#define RTC_TAMSK_MHR_Pos                (4)                                               /*!< RTC_T::TAMSK: MHR Position                */
+#define RTC_TAMSK_MHR_Msk                (0x1ul << RTC_TAMSK_MHR_Pos)                      /*!< RTC_T::TAMSK: MHR Mask                    */
+
+#define RTC_TAMSK_MTENHR_Pos             (5)                                               /*!< RTC_T::TAMSK: MTENHR Position             */
+#define RTC_TAMSK_MTENHR_Msk             (0x1ul << RTC_TAMSK_MTENHR_Pos)                   /*!< RTC_T::TAMSK: MTENHR Mask                 */
+
+#define RTC_CAMSK_MDAY_Pos               (0)                                               /*!< RTC_T::CAMSK: MDAY Position               */
+#define RTC_CAMSK_MDAY_Msk               (0x1ul << RTC_CAMSK_MDAY_Pos)                     /*!< RTC_T::CAMSK: MDAY Mask                   */
+
+#define RTC_CAMSK_MTENDAY_Pos            (1)                                               /*!< RTC_T::CAMSK: MTENDAY Position            */
+#define RTC_CAMSK_MTENDAY_Msk            (0x1ul << RTC_CAMSK_MTENDAY_Pos)                  /*!< RTC_T::CAMSK: MTENDAY Mask                */
+
+#define RTC_CAMSK_MMON_Pos               (2)                                               /*!< RTC_T::CAMSK: MMON Position               */
+#define RTC_CAMSK_MMON_Msk               (0x1ul << RTC_CAMSK_MMON_Pos)                     /*!< RTC_T::CAMSK: MMON Mask                   */
+
+#define RTC_CAMSK_MTENMON_Pos            (3)                                               /*!< RTC_T::CAMSK: MTENMON Position            */
+#define RTC_CAMSK_MTENMON_Msk            (0x1ul << RTC_CAMSK_MTENMON_Pos)                  /*!< RTC_T::CAMSK: MTENMON Mask                */
+
+#define RTC_CAMSK_MYEAR_Pos              (4)                                               /*!< RTC_T::CAMSK: MYEAR Position              */
+#define RTC_CAMSK_MYEAR_Msk              (0x1ul << RTC_CAMSK_MYEAR_Pos)                    /*!< RTC_T::CAMSK: MYEAR Mask                  */
+
+#define RTC_CAMSK_MTENYEAR_Pos           (5)                                               /*!< RTC_T::CAMSK: MTENYEAR Position           */
+#define RTC_CAMSK_MTENYEAR_Msk           (0x1ul << RTC_CAMSK_MTENYEAR_Pos)                 /*!< RTC_T::CAMSK: MTENYEAR Mask               */
+
+#define RTC_SPRCTL_SNPDEN_Pos            (0)                                               /*!< RTC_T::SPRCTL: SNPDEN Position            */
+#define RTC_SPRCTL_SNPDEN_Msk            (0x1ul << RTC_SPRCTL_SNPDEN_Pos)                  /*!< RTC_T::SPRCTL: SNPDEN Mask                */
+
+#define RTC_SPRCTL_SNPTYPE0_Pos          (1)                                               /*!< RTC_T::SPRCTL: SNPTYPE0 Position          */
+#define RTC_SPRCTL_SNPTYPE0_Msk          (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos)                /*!< RTC_T::SPRCTL: SNPTYPE0 Mask              */
+
+#define RTC_SPRCTL_SPRRWEN_Pos           (2)                                               /*!< RTC_T::SPRCTL: SPRRWEN Position           */
+#define RTC_SPRCTL_SPRRWEN_Msk           (0x1ul << RTC_SPRCTL_SPRRWEN_Pos)                 /*!< RTC_T::SPRCTL: SPRRWEN Mask               */
+
+#define RTC_SPRCTL_SNPTYPE1_Pos          (3)                                               /*!< RTC_T::SPRCTL: SNPTYPE1 Position          */
+#define RTC_SPRCTL_SNPTYPE1_Msk          (0x1ul << RTC_SPRCTL_SNPTYPE1_Pos)                /*!< RTC_T::SPRCTL: SNPTYPE1 Mask              */
+
+#define RTC_SPRCTL_SPRCSTS_Pos           (5)                                               /*!< RTC_T::SPRCTL: SPRCSTS Position           */
+#define RTC_SPRCTL_SPRCSTS_Msk           (0x1ul << RTC_SPRCTL_SPRCSTS_Pos)                 /*!< RTC_T::SPRCTL: SPRCSTS Mask               */
+
+#define RTC_SPRCTL_SPRRWRDY_Pos          (7)                                               /*!< RTC_T::SPRCTL: SPRRWRDY Position          */
+#define RTC_SPRCTL_SPRRWRDY_Msk          (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos)                /*!< RTC_T::SPRCTL: SPRRWRDY Mask              */
+
+#define RTC_SPR_SPARE_Pos                (0)                                               /*!< RTC_T::SPR: SPARE Position                */
+#define RTC_SPR_SPARE_Msk                (0xfffffffful << RTC_SPR_SPARE_Pos)               /*!< RTC_T::SPR: SPARE Mask                    */
+
+#define RTC_LXTCTL_LXTEN_Pos             (0)                                               /*!< RTC_T::LXTCTL: LXTEN Position             */
+#define RTC_LXTCTL_LXTEN_Msk             (0x1ul << RTC_LXTCTL_LXTEN_Pos)                   /*!< RTC_T::LXTCTL: LXTEN Mask                 */
+
+#define RTC_LXTCTL_GAIN_Pos              (1)                                               /*!< RTC_T::LXTCTL: GAIN Position              */
+#define RTC_LXTCTL_GAIN_Msk              (0x7ul << RTC_LXTCTL_GAIN_Pos)                    /*!< RTC_T::LXTCTL: GAIN Mask                  */
+
+#define RTC_LXTOCTL_OPMODE_Pos           (0)                                               /*!< RTC_T::LXTOCTL: OPMODE Position           */
+#define RTC_LXTOCTL_OPMODE_Msk           (0x3ul << RTC_LXTOCTL_OPMODE_Pos)                 /*!< RTC_T::LXTOCTL: OPMODE Mask               */
+
+#define RTC_LXTOCTL_DOUT_Pos             (2)                                               /*!< RTC_T::LXTOCTL: DOUT Position             */
+#define RTC_LXTOCTL_DOUT_Msk             (0x1ul << RTC_LXTOCTL_DOUT_Pos)                   /*!< RTC_T::LXTOCTL: DOUT Mask                 */
+
+#define RTC_LXTOCTL_CTLSEL_Pos           (3)                                               /*!< RTC_T::LXTOCTL: CTLSEL Position           */
+#define RTC_LXTOCTL_CTLSEL_Msk           (0x1ul << RTC_LXTOCTL_CTLSEL_Pos)                 /*!< RTC_T::LXTOCTL: CTLSEL Mask               */
+
+#define RTC_LXTICTL_OPMODE_Pos           (0)                                               /*!< RTC_T::LXTICTL: OPMODE Position           */
+#define RTC_LXTICTL_OPMODE_Msk           (0x3ul << RTC_LXTICTL_OPMODE_Pos)                 /*!< RTC_T::LXTICTL: OPMODE Mask               */
+
+#define RTC_LXTICTL_DOUT_Pos             (2)                                               /*!< RTC_T::LXTICTL: DOUT Position             */
+#define RTC_LXTICTL_DOUT_Msk             (0x1ul << RTC_LXTICTL_DOUT_Pos)                   /*!< RTC_T::LXTICTL: DOUT Mask                 */
+
+#define RTC_LXTICTL_CTLSEL_Pos           (3)                                               /*!< RTC_T::LXTICTL: CTLSEL Position           */
+#define RTC_LXTICTL_CTLSEL_Msk           (0x1ul << RTC_LXTICTL_CTLSEL_Pos)                 /*!< RTC_T::LXTICTL: CTLSEL Mask               */
+
+#define RTC_TAMPCTL_OPMODE_Pos           (0)                                               /*!< RTC_T::TAMPCTL: OPMODE Position           */
+#define RTC_TAMPCTL_OPMODE_Msk           (0x3ul << RTC_TAMPCTL_OPMODE_Pos)                 /*!< RTC_T::TAMPCTL: OPMODE Mask               */
+
+#define RTC_TAMPCTL_DOUT_Pos             (2)                                               /*!< RTC_T::TAMPCTL: DOUT Position             */
+#define RTC_TAMPCTL_DOUT_Msk             (0x1ul << RTC_TAMPCTL_DOUT_Pos)                   /*!< RTC_T::TAMPCTL: DOUT Mask                 */
+
+#define RTC_TAMPCTL_CTLSEL_Pos           (3)                                               /*!< RTC_T::TAMPCTL: CTLSEL Position           */
+#define RTC_TAMPCTL_CTLSEL_Msk           (0x1ul << RTC_TAMPCTL_CTLSEL_Pos)                 /*!< RTC_T::TAMPCTL: CTLSEL Mask               */
+
+/**@}*/ /* RTC_CONST */
+/**@}*/ /* end of RTC register group */
+
+
+/*---------------------- Smart Card Host Interface Controller -------------------------*/
+/**
+    @addtogroup SC Smart Card Host Interface Controller(SC)
+    Memory Mapped Structure for SC Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var SC_T::DAT
+ * Offset: 0x00  SC Receiving/Transmit Holding Buffer Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |DAT       |Receiving/ Transmit Holding Buffer
+ * |        |          |Write Operation:
+ * |        |          |By writing data to DAT, the SC will send out an 8-bit data.
+ * |        |          |Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.
+ * |        |          |Read Operation:
+ * |        |          |By reading DAT, the SC will return an 8-bit received data.
+ * @var SC_T::CTL
+ * Offset: 0x04  SC Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SCEN      |SC Engine Enable Bit
+ * |        |          |Set this bit to 1 to enable SC operation.
+ * |        |          |If this bit is cleared, SC will force all transition to IDLE state.
+ * |[1]     |RXOFF     |RX Transition Disable Control
+ * |        |          |0 = The receiver Enabled.
+ * |        |          |1 = The receiver Disabled.
+ * |        |          |Note:
+ * |        |          |If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored.
+ * |[2]     |TXOFF     |TX Transition Disable Control
+ * |        |          |0 = The transceiver Enabled.
+ * |        |          |1 = The transceiver Disabled.
+ * |[3]     |AUTOCEN   |Auto Convention Enable Bit
+ * |        |          |0 = Auto-convention Disabled.
+ * |        |          |1 = Auto-convention Enabled.
+ * |        |          |When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.
+ * |        |          |If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F.
+ * |        |          |After hardware received first data and stored it at buffer, 
+ * |        |          |hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically.
+ * |        |          |If the first data is not 0x3B or 0x3F, hardware will generate an interrupt if ACERRIEN (SC_INTEN[10]) = 1 to CPU.
+ * |[5:4]   |CONSEL    |Convention Selection
+ * |        |          |00 = Direct convention.
+ * |        |          |01 = Reserved.
+ * |        |          |10 = Reserved.
+ * |        |          |11 = Inverse convention.
+ * |        |          |Note:
+ * |        |          |If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
+ * |[7:6]   |RXTRGLV   |Rx Buffer Trigger Level
+ * |        |          |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled, an interrupt will be generated).
+ * |        |          |00 = INTR_RDA Trigger Level with 01 Bytes.
+ * |        |          |01 = INTR_RDA Trigger Level with 02 Bytes.
+ * |        |          |10 = INTR_RDA Trigger Level with 03 Bytes.
+ * |        |          |11 = Reserved.
+ * |[12:8]  |BGT       |Block Guard Time (BGT)
+ * |        |          |Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions.
+ * |        |          |This field indicates the counter for the bit length of block guard time.
+ * |        |          |According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it.
+ * |        |          |Note:
+ * |        |          |The real block guard time is BGT + 1.
+ * |[14:13] |TMRSEL    |Timer Selection
+ * |        |          |00 = All internal timer function Disabled.
+ * |        |          |01 = Internal 24 bit timer Enabled.
+ * |        |          |Software can configure it by setting SC_TMRCTL0 [23:0].
+ * |        |          |SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode.
+ * |        |          |10 = internal 24 bit timer and 8 bit internal timer Enabled.
+ * |        |          |Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0].
+ * |        |          |SC_TMRCTL2 will be ignored in this mode.
+ * |        |          |11 = Internal 24 bit timer and two 8 bit timers Enabled.
+ * |        |          |Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0].
+ * |[15]    |NSB       |Stop Bit Length
+ * |        |          |This field indicates the length of stop bit.
+ * |        |          |0 = The stop bit length is 2 ETU.
+ * |        |          |1= The stop bit length is 1 ETU.
+ * |        |          |Note:
+ * |        |          |The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
+ * |[18:16] |RXRTY     |RX Error Retry Count Number
+ * |        |          |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
+ * |        |          |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
+ * |        |          |Note2: This field cannot be changed when RXRTYEN enabled.
+ * |        |          |The change flow is to disable RXRTYEN first and then fill in new retry value.
+ * |[19]    |RXRTYEN   |RX Error Retry Enable Bit
+ * |        |          |This bit enables receiver retry function when parity error has occurred.
+ * |        |          |0 = RX error retry function Disabled.
+ * |        |          |1 = RX error retry function Enabled.
+ * |        |          |Note:
+ * |        |          |Software must fill in the RXRTY value before enabling this bit.
+ * |[22:20] |TXRTY     |TX Error Retry Count Number
+ * |        |          |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
+ * |        |          |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
+ * |        |          |Note2: This field cannot be changed when TXRTYEN enabled.
+ * |        |          |The change flow is to disable TXRTYEN first and then fill in new retry value.
+ * |[23]    |TXRTYEN   |TX Error Retry Enable Bit
+ * |        |          |This bit enables transmitter retry function when parity error has occurred.
+ * |        |          |0 = TX error retry function Disabled.
+ * |        |          |1 = TX error retry function Enabled.
+ * |[25:24] |CDDBSEL   |Card Detect De-Bounce Selection
+ * |        |          |This field indicates the card detect de-bounce selection.
+ * |        |          |00 = De-bounce sample card insert once per 384 (128 * 3) peripheral clocks and de-bounce sample card removal once per 128 peripheral clocks.
+ * |        |          |01 = De-bounce sample card insert once per 192 (64 * 3) peripheral clocks and de-bounce sample card removal once per 64 peripheral clocks.
+ * |        |          |10 = De-bounce sample card insert once per 96 (32 * 3) peripheral clocks and de-bounce sample card removal once per 32 peripheral clocks.
+ * |        |          |11 = De-bounce sample card insert once per 48 (16 * 3) peripheral clocks and de-bounce sample card removal once per 16 peripheral clocks.
+ * |[26]    |CDLV      |Card Detect Level
+ * |        |          |0 = When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected.
+ * |        |          |1 = When hardware detects the card detect pin from low to high, it indicates a card is detected.
+ * |        |          |Note: Software must select card detect level before Smart Card engine enabled.
+ * |[30]    |SYNC      |SYNC Flag Indicator
+ * |        |          |Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.
+ * |        |          |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
+ * |        |          |1 = Last value is synchronizing.
+ * |        |          |Note: This bit is read only.
+ * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable Control
+ * |        |          |0 = ICE debug mode acknowledgement affects SC counting.
+ * |        |          |SC internal counter will be held while CPU is held by ICE.
+ * |        |          |1 = ICE debug mode acknowledgement Disabled.
+ * |        |          |SC internal counter will keep going no matter CPU is held by ICE or not.
+ * @var SC_T::ALTCTL
+ * Offset: 0x08  SC Alternate Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |TXRST     |TX Software Reset
+ * |        |          |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
+ * |        |          |0 = No effect.
+ * |        |          |1 = Reset the TX internal state machine and pointers.
+ * |        |          |Note:
+ * |        |          |This bit will be auto cleared after reset is complete.
+ * |[1]     |RXRST     |Rx Software Reset
+ * |        |          |When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.
+ * |        |          |0 = No effect.
+ * |        |          |1 = Reset the Rx internal state machine and pointers.
+ * |        |          |Note:
+ * |        |          |This bit will be auto cleared after reset is complete.
+ * |[2]     |DACTEN    |Deactivation Sequence Generator Enable Bit
+ * |        |          |This bit enables SC controller to initiate the card by deactivation sequence
+ * |        |          |0 = No effect.
+ * |        |          |1 = Deactivation sequence generator Enabled.
+ * |        |          |Note1:
+ * |        |          |When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
+ * |        |          |Note2:
+ * |        |          |This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
+ * |        |          |So don't fill this bit, TXRST, and RXRST at the same time.
+ * |        |          |Note3:
+ * |        |          |If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[3]     |ACTEN     |Activation Sequence Generator Enable Bit
+ * |        |          |This bit enables SC controller to initiate the card by activation sequence
+ * |        |          |0 = No effect.
+ * |        |          |1 = Activation sequence generator Enabled.
+ * |        |          |Note1:
+ * |        |          |When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
+ * |        |          |Note2:
+ * |        |          |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
+ * |        |          |Note3:
+ * |        |          |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[4]     |WARSTEN   |Warm Reset Sequence Generator Enable Bit
+ * |        |          |This bit enables SC controller to initiate the card by warm reset sequence
+ * |        |          |0 = No effect.
+ * |        |          |1 = Warm reset sequence generator Enabled.
+ * |        |          |Note1:
+ * |        |          |When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
+ * |        |          |Note2:
+ * |        |          |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.
+ * |        |          |Note3:
+ * |        |          |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[5]     |CNTEN0    |Internal Timer0 Start Enable Bit
+ * |        |          |This bit enables Timer 0 to start counting.
+ * |        |          |Software can fill 0 to stop it and set 1 to reload and count.
+ * |        |          |0 = Stops counting.
+ * |        |          |1 = Start counting.
+ * |        |          |Note1:
+ * |        |          |This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 01.
+ * |        |          |Note2:
+ * |        |          |If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
+ * |        |          |Note3:
+ * |        |          |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
+ * |        |          |So don't fill this bit, TXRST and RXRST at the same time.
+ * |        |          |Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[6]     |CNTEN1    |Internal Timer1 Start Enable Bit
+ * |        |          |This bit enables Timer 1 to start counting.
+ * |        |          |Software can fill 0 to stop it and set 1 to reload and count.
+ * |        |          |0 = Stops counting.
+ * |        |          |1 = Start counting.
+ * |        |          |Note1:
+ * |        |          |This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 10 or TMRSEL(SC_CTL[14:13]) = 11.
+ * |        |          |Don't filled CNTEN1 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01.
+ * |        |          |Note2:
+ * |        |          |If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
+ * |        |          |Note3:
+ * |        |          |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
+ * |        |          |Note4:
+ * |        |          |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[7]     |CNTEN2    |Internal Timer2 Start Enable Bit
+ * |        |          |This bit enables Timer 2 to start counting.
+ * |        |          |Software can fill 0 to stop it and set 1 to reload and count.
+ * |        |          |0 = Stops counting.
+ * |        |          |1 = Start counting.
+ * |        |          |Note1:
+ * |        |          |This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11.
+ * |        |          |Don't filled CNTEN2 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10.
+ * |        |          |Note2:
+ * |        |          |If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
+ * |        |          |Note3:
+ * |        |          |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
+ * |        |          |So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
+ * |        |          |Note4:
+ * |        |          |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[9:8]   |INITSEL   |Initial Timing Selection
+ * |        |          |This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).
+ * |        |          |Unit: SC clock
+ * |        |          |Activation: refer to SC Activation Sequence in Figure 6.17-4
+ * |        |          |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5
+ * |        |          |Deactivation: refer to Deactivation Sequence in Figure 6.17-6
+ * |[12]    |RXBGTEN   |Receiver Block Guard Time Function Enable Bit
+ * |        |          |0 = Receiver block guard time function Disabled.
+ * |        |          |1 = Receiver block guard time function Enabled.
+ * |[13]    |ACTSTS0   |Internal Timer0 Active State (Read Only)
+ * |        |          |This bit indicates the timer counter status of timer0.
+ * |        |          |0 = Timer0 is not active.
+ * |        |          |1 = Timer0 is active.
+ * |[14]    |ACTSTS1   |Internal Timer1 Active State (Read Only)
+ * |        |          |This bit indicates the timer counter status of timer1.
+ * |        |          |0 = Timer1 is not active.
+ * |        |          |1 = Timer1 is active.
+ * |[15]    |ACTSTS2   |Internal Timer2 Active State (Read Only)
+ * |        |          |This bit indicates the timer counter status of timer2.
+ * |        |          |0 = Timer2 is not active.
+ * |        |          |1 = Timer2 is active.
+ * @var SC_T::EGT
+ * Offset: 0x0C  SC Extend Guard Time Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |EGT       |Extended Guard Time
+ * |        |          |This field indicates the extended guard timer value.
+ * |        |          |Note:
+ * |        |          |The counter is ETU base and the real extended guard time is EGT.
+ * @var SC_T::RXTOUT
+ * Offset: 0x10  SC Receive buffer Time-out Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[8:0]   |RFTM      |SC Receiver FIFO Time-out (ETU Base)
+ * |        |          |The time-out counter resets and starts counting whenever the RX buffer received a new data word.
+ * |        |          |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ).
+ * |        |          |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
+ * |        |          |Note2:
+ * |        |          |Filling all 0 to this field indicates to disable this function.
+ * @var SC_T::ETUCTL
+ * Offset: 0x14  SC ETU Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |ETURDIV   |ETU Rate Divider
+ * |        |          |The field indicates the clock rate divider.
+ * |        |          |The real ETU is ETURDIV + 1.
+ * |        |          |Note:
+ * |        |          |Software can configure this field, but this field must be greater than 0x004.
+ * |[15]    |CMPEN     |Compensation Mode Enable Bit
+ * |        |          |This bit enables clock compensation function.
+ * |        |          |When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV .
+ * |        |          |0 = Compensation function Disabled.
+ * |        |          |1 = Compensation function Enabled.
+ * @var SC_T::INTEN
+ * Offset: 0x18  SC Interrupt Enable Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |RDAIEN    |Receive Data Reach Interrupt Enable Bit
+ * |        |          |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.
+ * |        |          |0 = Receive data reach trigger level interrupt Disabled.
+ * |        |          |1 = Receive data reach trigger level interrupt Enabled.
+ * |[1]     |TBEIEN    |Transmit Buffer Empty Interrupt Enable Bit
+ * |        |          |This field is used for transmit buffer empty interrupt enable.
+ * |        |          |0 = Transmit buffer empty interrupt Disabled.
+ * |        |          |1 = Transmit buffer empty interrupt Enabled.
+ * |[2]     |TERRIEN   |Transfer Error Interrupt Enable Bit
+ * |        |          |This field is used for transfer error interrupt enable.
+ * |        |          |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]).
+ * |        |          |0 = Transfer error interrupt Disabled.
+ * |        |          |1 = Transfer error interrupt Enabled.
+ * |[3]     |TMR0IEN   |Timer0 Interrupt Enable Bit
+ * |        |          |This field is used to enable TMR0 interrupt enable.
+ * |        |          |0 = Timer0 interrupt Disabled.
+ * |        |          |1 = Timer0 interrupt Enabled.
+ * |[4]     |TMR1IEN   |Timer1 Interrupt Enable Bit
+ * |        |          |This field is used to enable the TMR1 interrupt.
+ * |        |          |0 = Timer1 interrupt Disabled.
+ * |        |          |1 = Timer1 interrupt Enabled.
+ * |[5]     |TMR2IEN   |Timer2 Interrupt Enable Bit
+ * |        |          |This field is used for TMR2 interrupt enable.
+ * |        |          |0 = Timer2 interrupt Disabled.
+ * |        |          |1 = Timer2 interrupt Enabled.
+ * |[6]     |BGTIEN    |Block Guard Time Interrupt Enable Bit
+ * |        |          |This field is used for block guard time interrupt enable.
+ * |        |          |0 = Block guard time Disabled.
+ * |        |          |1 = Block guard time Enabled.
+ * |[7]     |CDIEN     |Card Detect Interrupt Enable Bit
+ * |        |          |This field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12])
+ * |        |          |0 = Card detect interrupt Disabled.
+ * |        |          |1 = Card detect interrupt Enabled.
+ * |[8]     |INITIEN   |Initial End Interrupt Enable Bit
+ * |        |          |This field is used for activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation ((DACTEN SC_ALTCTL[2]) = 1) and warm reset (WARSTEN (SC_ALTCTL [4])) sequence interrupt enable.
+ * |        |          |0 = Initial end interrupt Disabled.
+ * |        |          |1 = Initial end interrupt Enabled.
+ * |[9]     |RXTOIF    |Receiver Buffer Time-Out Interrupt Enable Bit
+ * |        |          |This field is used for receiver buffer time-out interrupt enable.
+ * |        |          |0 = Receiver buffer time-out interrupt Disabled.
+ * |        |          |1 = Receiver buffer time-out interrupt Enabled.
+ * |[10]    |ACERRIEN  |Auto Convention Error Interrupt Enable Bit
+ * |        |          |This field is used for auto-convention error interrupt enable.
+ * |        |          |0 = Auto-convention error interrupt Disabled.
+ * |        |          |1 = Auto-convention error interrupt Enabled.
+ * @var SC_T::INTSTS
+ * Offset: 0x1C  SC Interrupt Status Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |RDAIF     |Receive Data Reach Interrupt Status Flag (Read Only)
+ * |        |          |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
+ * |        |          |Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]).
+ * |        |          |If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
+ * |[1]     |TBEIF     |Transmit Buffer Empty Interrupt Status Flag (Read Only)
+ * |        |          |This field is used for transmit buffer empty interrupt status flag.
+ * |        |          |Note: This field is the status flag of transmit buffer empty state.
+ * |        |          |If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically.
+ * |[2]     |TERRIF    |Transfer Error Interrupt Status Flag (Read Only)
+ * |        |          |This field is used for transfer error interrupt status flag.
+ * |        |          |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]) and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR(SC_STATUS[30]).
+ * |        |          |Note: This field is the status flag of
+ * |        |          |BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]).
+ * |        |          |So, if software wants to clear this bit, software must write 1 to each field.
+ * |[3]     |TMR0IF    |Timer0 Interrupt Status Flag (Read Only)
+ * |        |          |This field is used for TMR0 interrupt status flag.
+ * |        |          |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[4]     |TMR1IF    |Timer1 Interrupt Status Flag (Read Only)
+ * |        |          |This field is used for TMR1 interrupt status flag.
+ * |        |          |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[5]     |TMR2IF    |Timer2 Interrupt Status Flag (Read Only)
+ * |        |          |This field is used for TMR2 interrupt status flag.
+ * |        |          |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[6]     |BGTIF     |Block   Guard Time Interrupt Status Flag (Read Only)
+ * |        |          |This field   is used for block guard time interrupt status flag.
+ * |        |          |Note1: This bit is valid when RXBGTEN   (SC_ALTCTL[12]) is enabled.
+ * |        |          |Note2: This bit is read only, but it can be cleared by   writing "1" to it.
+ * |[7]     |CDIF      |Card Detect Interrupt Status Flag (Read Only)
+ * |        |          |This field is used for card detect interrupt status flag.
+ * |        |          |The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
+ * |        |          |Note:
+ * |        |          |This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])].
+ * |        |          |So if software wants to clear this bit, software must write 1 to this field.
+ * |[8]     |INITIF    |Initial End Interrupt Status Flag (Read Only)
+ * |        |          |This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.
+ * |        |          |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[9]     |RBTOIF    |Receiver Buffer Time-Out Interrupt Status Flag (Read Only)
+ * |        |          |This field is used for receiver buffer time-out interrupt status flag.
+ * |        |          |Note: This field is the status flag of receiver buffer time-out state.
+ * |        |          |If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,.
+ * |[10]    |ACERRIF   |Auto Convention Error Interrupt Status Flag (Read Only)
+ * |        |          |This field indicates auto convention sequence error.
+ * |        |          |If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.
+ * |        |          |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * @var SC_T::STATUS
+ * Offset: 0x20  SC Status Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |RXOV      |RX Overflow Error Status Flag (Read Only)
+ * |        |          |This bit is set when RX buffer overflow.
+ * |        |          |If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.
+ * |        |          |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[1]     |RXEMPTY   |Receiver Buffer Empty Status Flag(Read Only)
+ * |        |          |This bit indicates RX buffer empty or not.
+ * |        |          |When the last byte of Rx buffer has been read by CPU, hardware sets this bit high.
+ * |        |          |It will be cleared when SC receives any new data.
+ * |[2]     |RXFULL    |Receiver Buffer Full Status Flag (Read Only)
+ * |        |          |This bit indicates RX buffer full or not.
+ * |        |          |This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
+ * |[4]     |PEF       |Receiver Parity Error Status Flag (Read Only)
+ * |        |          |This bit is set to logic 1 whenever the received character does not have a valid
+ * |        |          |"parity bit".
+ * |        |          |Note1:
+ * |        |          |This bit is read only, but it can be cleared by writing 1 to it.
+ * |        |          |Note2:
+ * |        |          |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
+ * |[5]     |FEF       |Receiver Frame Error Status Flag (Read Only)
+ * |        |          |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
+ * |        |          |Note1:
+ * |        |          |This bit is read only, but it can be cleared by writing 1 to it.
+ * |        |          |Note2:
+ * |        |          |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
+ * |[6]     |BEF       |Receiver Break Error Status Flag (Read Only)
+ * |        |          |This bit is set to logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
+ * |        |          |.
+ * |        |          |Note1:
+ * |        |          |This bit is read only, but it can be cleared by writing 1 to it.
+ * |        |          |Note2:
+ * |        |          |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
+ * |[8]     |TXOV      |TX Overflow Error Interrupt Status Flag (Read Only)
+ * |        |          |If TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to "1" by hardware.
+ * |        |          |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[9]     |TXEMPTY   |Transmit Buffer Empty Status Flag (Read Only)
+ * |        |          |This bit indicates TX buffer empty or not.
+ * |        |          |When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high.
+ * |        |          |It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty).
+ * |[10]    |TXFULL    |Transmit Buffer Full Status Flag (Read Only)
+ * |        |          |This bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
+ * |[11]    |CREMOVE   |Card Detect Removal Status Of SC_CD Pin (Read Only)
+ * |        |          |This bit is set whenever card has been removal.
+ * |        |          |0 = No effect.
+ * |        |          |1 = Card removed.
+ * |        |          |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * |        |          |Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
+ * |[12]    |CINSERT   |Card Detect Insert Status Of SC_CD Pin (Read Only)
+ * |        |          |This bit is set whenever card has been inserted.
+ * |        |          |0 = No effect.
+ * |        |          |1 = Card insert.
+ * |        |          |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * |        |          |Note2: The
+ * |        |          |card detect engine will start after SCEN (SC_CTL[0]) set.
+ * |[13]    |CDPINSTS  |Card Detect Status Of SC_CD Pin Status (Read Only)
+ * |        |          |This bit is the pin status flag of SC_CD
+ * |        |          |0 = The SC_CD pin state at low.
+ * |        |          |1 = The SC_CD pin state at high.
+ * |[17:16] |RXPOINT   |Receiver Buffer Pointer Status Flag (Read Only)
+ * |        |          |This field indicates the RX buffer pointer status flag.
+ * |        |          |When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one.
+ * |        |          |When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
+ * |[21]    |RXRERR    |Receiver Retry Error (Read Only)
+ * |        |          |This bit is set by hardware when RX has any error and retries transfer.
+ * |        |          |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * |        |          |Note2 This bit is a flag and cannot generate any interrupt to CPU.
+ * |        |          |Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
+ * |[22]    |RXOVERR   |Receiver Over Retry Error (Read Only)
+ * |        |          |This bit is set by hardware when RX transfer error retry over retry number limit.
+ * |        |          |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * |        |          |Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
+ * |[23]    |RXACT     |Receiver In Active Status Flag (Read Only)
+ * |        |          |This bit is set by hardware when RX transfer is in active.
+ * |        |          |This bit is cleared automatically when RX transfer is finished.
+ * |[25:24] |TXPOINT   |Transmit Buffer Pointer Status Flag (Read Only)
+ * |        |          |This field indicates the TX buffer pointer status flag.
+ * |        |          |When CPU writes data into SC_DAT, TXPOINT increases one.
+ * |        |          |When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
+ * |[29]    |TXRERR    |Transmitter Retry Error (Read Only)
+ * |        |          |This bit is set by hardware when transmitter re-transmits.
+ * |        |          |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * |        |          |Note2 This bit is a flag and cannot generate any interrupt to CPU.
+ * |[30]    |TXOVERR   |Transmitter Over Retry Error (Read Only)
+ * |        |          |This bit is set by hardware when transmitter re-transmits over retry number limitation.
+ * |        |          |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[31]    |TXACT     |Transmit In Active Status Flag (Read Only)
+ * |        |          |0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
+ * |        |          |1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.
+ * @var SC_T::PINCTL
+ * Offset: 0x24  SC Pin Control State Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |PWREN     |SC_PWREN Pin Signal
+ * |        |          |Software can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.
+ * |        |          |Write this field to drive SC_PWR pin
+ * |        |          |Refer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level.
+ * |        |          |Read this field to get SC_PWR pin status.
+ * |        |          |0 = SC_PWR pin status is low.
+ * |        |          |1 = SC_PWR pin status is high.
+ * |        |          |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * |        |          |So don't fill this field when operating in these modes.
+ * |[1]     |SCRST     |SC_RST Pin Signal
+ * |        |          |This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.
+ * |        |          |Write this field to drive SC_RST pin.
+ * |        |          |0 = Drive SC_RST pin to low.
+ * |        |          |1 = Drive SC_RST pin to high.
+ * |        |          |Read this field to get SC_RST pin status.
+ * |        |          |0 = SC_RST pin status is low.
+ * |        |          |1 = SC_RST pin status is high.
+ * |        |          |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * |        |          |So don't fill this field when operating in these modes.
+ * |[5]     |CSTOPLV   |SC Clock Stop Level
+ * |        |          |This field indicates the clock polarity control in clock stop mode.
+ * |        |          |0 = SC_CLK stopped in low level.
+ * |        |          |1 = SC_CLK stopped in high level.
+ * |[6]     |CLKKEEP   |SC Clock Enable Bit
+ * |        |          |0 = SC clock generation Disabled.
+ * |        |          |1 = SC clock always keeps free running.
+ * |        |          |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * |        |          |So don't fill this field when operating in these modes.
+ * |[9]     |SCDOUT    |SC Data Output Pin
+ * |        |          |This bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.
+ * |        |          |0 = Drive SCDATOUT pin to low.
+ * |        |          |1 = Drive SCDATOUT pin to high.
+ * |        |          |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * |        |          |So don't fill this field when SC is in these modes.
+ * |[11]    |PWRINV    |SC_POW Pin Inverse
+ * |        |          |This bit is used for inverse the SC_POW pin.
+ * |        |          |There are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]).
+ * |        |          |PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.
+ * |        |          |00 = SC_POW_ Pin is 0.
+ * |        |          |01 = SC_POW _Pin is 1.
+ * |        |          |10 = SC_POW _Pin is 1.
+ * |        |          |11 = SC_POW_ Pin is 0.
+ * |        |          |Note: Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]).
+ * |[12]    |SCDOSTS   |SC Data Pin Output Status
+ * |        |          |This bit is the pin status of SCDATOUT
+ * |        |          |0 = SCDATOUT pin to low.
+ * |        |          |1 = SCDATOUT pin to high.
+ * |        |          |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * |        |          |This bit is not allowed to program when SC is operated at these modes.
+ * |[16]    |DATSTS    |This bit   is the pin status of SC_DAT
+ * |        |          |0 = The   SC_DAT pin is low.
+ * |        |          |1 = The   SC_DAT pin is high.
+ * |[17]    |PWRSTS    |SC_PWR   Pin Signal
+ * |        |          |This bit   is the pin status of SC_PWR
+ * |        |          |0 = SC_PWR   pin to low.
+ * |        |          |1 = SC_PWR   pin to high.
+ * |        |          |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * |        |          |This bit is not allowed to program when SC is operated at these modes.
+ * |[18]    |RSTSTS    |SCRST Pin Signals
+ * |        |          |This bit is the pin status of SC_RST
+ * |        |          |0 = SC_RST pin is low.
+ * |        |          |1 = SC_RST pin is high.
+ * |        |          |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * |        |          |This bit is not allowed to program when SC is operated at these modes.
+ * |[30]    |SYNC      |SYNC Flag Indicator
+ * |        |          |Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register.
+ * |        |          |0 = Synchronizing is completion, user can write new data to SC_PINCTL register.
+ * |        |          |1 = Last value is synchronizing.
+ * |        |          |Note: This bit is read only.
+ * |[31]    |LOOPBK    |Loop Back Test
+ * |        |          |0 = loop back test Disabled.
+ * |        |          |1 = Enabling loop back test and the internal SCDATOUT will connect to internal SC_DATA_I.
+ * @var SC_T::TMRCTL0
+ * Offset: 0x28  SC Internal Timer Control Register 0.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[23:0]  |CNT       |Timer 0 Counter Value (ETU Base)
+ * |        |          |This field indicates the internal timer operation values.
+ * |[27:24] |OPMODE    |Timer 0 Operation Mode Selection
+ * |        |          |This field indicates the internal 24-bit timer operation selection.
+ * |        |          |Refer to 6.17.5.4 for programming Timer0
+ * @var SC_T::TMRCTL1
+ * Offset: 0x2C  SC Internal Timer Control Register 1.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |CNT       |Timer 1 Counter Value (ETU Base)
+ * |        |          |This field indicates the internal timer operation values.
+ * |[27:24] |OPMODE    |Timer 1 Operation Mode Selection
+ * |        |          |This field indicates the internal 8-bit timer operation selection.
+ * |        |          |Refer to 6.17.5.4 for programming Timer1
+ * @var SC_T::TMRCTL2
+ * Offset: 0x30  SC Internal Timer Control Register 2.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |CNT       |Timer 2 Counter Value (ETU Base)
+ * |        |          |This field indicates the internal timer operation values.
+ * |[27:24] |OPMODE    |Timer 2 Operation Mode Selection
+ * |        |          |This field indicates the internal 8-bit timer operation selection
+ * |        |          |Refer to 6.17.5.4 for programming Timer2
+ * @var SC_T::UARTCTL
+ * Offset: 0x34  SC UART Mode Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |UARTEN    |UART Mode Enable Bit
+ * |        |          |0 = Smart Card mode.
+ * |        |          |1 = UART mode.
+ * |        |          |Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0.
+ * |        |          |Note2: When operating in Smart Card mode, user must set UARTEN(SC_UARTCTL [0]) = 00.
+ * |        |          |Note3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
+ * |[5:4]   |WLS10     |Word Length Selection
+ * |        |          |00 = Word length is 8 bits.
+ * |        |          |01 = Word length is 7 bits.
+ * |        |          |10 = Word length is 6 bits.
+ * |        |          |11 = Word length is 5 bits.
+ * |        |          |Note: In smart card mode, this WLS must be '00'
+ * |[6]     |PBOFF     |Parity Bit Disable Control
+ * |        |          |0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
+ * |        |          |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
+ * |        |          |Note: In smart card mode, this field must be '0' (default setting is with parity bit)
+ * |[7]     |OPE       |Odd Parity Enable Bit
+ * |        |          |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+ * |        |          |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+ * |        |          |Note: This bit has effect only when PBOFF bit is '0'.
+ * @var SC_T::TMRDAT0
+ * Offset: 0x38  SC Timer Current Data Register A.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[23:0]  |CNT0      |Timer0 Current Data Value (Read Only)
+ * |        |          |This field indicates the current count values of timer0.
+ * @var SC_T::TMRDAT1_2
+ * Offset: 0x3C  SC Timer Current Data Register B.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |CNT1      |Timer1 Current Data Value (Read Only)
+ * |        |          |This field indicates the current count values of timer1.
+ * |[15:8]  |CNT2      |Timer2 Current Data Value (Read Only)
+ * |        |          |This field indicates the current count values of timer2.
+ */
+
+    __IO uint32_t DAT;           /* Offset: 0x00  SC Receiving/Transmit Holding Buffer Register.                     */
+    __IO uint32_t CTL;           /* Offset: 0x04  SC Control Register.                                               */
+    __IO uint32_t ALTCTL;        /* Offset: 0x08  SC Alternate Control Register.                                     */
+    __IO uint32_t EGT;           /* Offset: 0x0C  SC Extend Guard Time Register.                                     */
+    __IO uint32_t RXTOUT;        /* Offset: 0x10  SC Receive buffer Time-out Register.                               */
+    __IO uint32_t ETUCTL;        /* Offset: 0x14  SC ETU Control Register.                                           */
+    __IO uint32_t INTEN;         /* Offset: 0x18  SC Interrupt Enable Control Register.                              */
+    __IO uint32_t INTSTS;        /* Offset: 0x1C  SC Interrupt Status Register.                                      */
+    __IO uint32_t STATUS;        /* Offset: 0x20  SC Status Register.                                                */
+    __IO uint32_t PINCTL;        /* Offset: 0x24  SC Pin Control State Register.                                     */
+    __IO uint32_t TMRCTL0;       /* Offset: 0x28  SC Internal Timer Control Register 0.                              */
+    __IO uint32_t TMRCTL1;       /* Offset: 0x2C  SC Internal Timer Control Register 1.                              */
+    __IO uint32_t TMRCTL2;       /* Offset: 0x30  SC Internal Timer Control Register 2.                              */
+    __IO uint32_t UARTCTL;       /* Offset: 0x34  SC UART Mode Control Register.                                     */
+    __I  uint32_t TMRDAT0;       /* Offset: 0x38  SC Timer Current Data Register A.                                  */
+    __I  uint32_t TMRDAT1_2;     /* Offset: 0x3C  SC Timer Current Data Register B.                                  */
+
+} SC_T;
+
+
+
+/**
+    @addtogroup SC_CONST SC Bit Field Definition
+    Constant Definitions for SC Controller
+@{ */
+
+#define SC_DAT_DAT_Pos                   (0)                                        /*!< SC_T::DAT: DAT Position   */
+#define SC_DAT_DAT_Msk                   (0xfful << SC_DAT_DAT_Pos)                 /*!< SC_T::DAT: DAT Mask       */
+
+#define SC_CTL_SCEN_Pos                  (0)                                        /*!< SC_T::CTL: SCEN Position  */
+#define SC_CTL_SCEN_Msk                  (0x1ul << SC_CTL_SCEN_Pos)                 /*!< SC_T::CTL: SCEN Mask      */
+
+#define SC_CTL_RXOFF_Pos                 (1)                                        /*!< SC_T::CTL: RXOFF Position */
+#define SC_CTL_RXOFF_Msk                 (0x1ul << SC_CTL_RXOFF_Pos)                /*!< SC_T::CTL: RXOFF Mask     */
+
+#define SC_CTL_TXOFF_Pos                 (2)                                        /*!< SC_T::CTL: TXOFF Position */
+#define SC_CTL_TXOFF_Msk                 (0x1ul << SC_CTL_TXOFF_Pos)                /*!< SC_T::CTL: TXOFF Mask     */
+
+#define SC_CTL_AUTOCEN_Pos               (3)                                        /*!< SC_T::CTL: AUTOCEN Position   */
+#define SC_CTL_AUTOCEN_Msk               (0x1ul << SC_CTL_AUTOCEN_Pos)              /*!< SC_T::CTL: AUTOCEN Mask       */
+
+#define SC_CTL_CONSEL_Pos                (4)                                        /*!< SC_T::CTL: CONSEL Position    */
+#define SC_CTL_CONSEL_Msk                (0x3ul << SC_CTL_CONSEL_Pos)               /*!< SC_T::CTL: CONSEL Mask        */
+
+#define SC_CTL_RXTRGLV_Pos               (6)                                        /*!< SC_T::CTL: RXTRGLV Position   */
+#define SC_CTL_RXTRGLV_Msk               (0x3ul << SC_CTL_RXTRGLV_Pos)              /*!< SC_T::CTL: RXTRGLV Mask       */
+
+#define SC_CTL_BGT_Pos                   (8)                                        /*!< SC_T::CTL: BGT Position   */
+#define SC_CTL_BGT_Msk                   (0x1ful << SC_CTL_BGT_Pos)                 /*!< SC_T::CTL: BGT Mask       */
+
+#define SC_CTL_TMRSEL_Pos                (13)                                       /*!< SC_T::CTL: TMRSEL Position    */
+#define SC_CTL_TMRSEL_Msk                (0x3ul << SC_CTL_TMRSEL_Pos)               /*!< SC_T::CTL: TMRSEL Mask        */
+
+#define SC_CTL_NSB_Pos                   (15)                                       /*!< SC_T::CTL: NSB Position   */
+#define SC_CTL_NSB_Msk                   (0x1ul << SC_CTL_NSB_Pos)                  /*!< SC_T::CTL: NSB Mask       */
+
+#define SC_CTL_RXRTY_Pos                 (16)                                       /*!< SC_T::CTL: RXRTY Position */
+#define SC_CTL_RXRTY_Msk                 (0x7ul << SC_CTL_RXRTY_Pos)                /*!< SC_T::CTL: RXRTY Mask     */
+
+#define SC_CTL_RXRTYEN_Pos               (19)                                       /*!< SC_T::CTL: RXRTYEN Position   */
+#define SC_CTL_RXRTYEN_Msk               (0x1ul << SC_CTL_RXRTYEN_Pos)              /*!< SC_T::CTL: RXRTYEN Mask       */
+
+#define SC_CTL_TXRTY_Pos                 (20)                                       /*!< SC_T::CTL: TXRTY Position */
+#define SC_CTL_TXRTY_Msk                 (0x7ul << SC_CTL_TXRTY_Pos)                /*!< SC_T::CTL: TXRTY Mask     */
+
+#define SC_CTL_TXRTYEN_Pos               (23)                                       /*!< SC_T::CTL: TXRTYEN Position   */
+#define SC_CTL_TXRTYEN_Msk               (0x1ul << SC_CTL_TXRTYEN_Pos)              /*!< SC_T::CTL: TXRTYEN Mask       */
+
+#define SC_CTL_CDDBSEL_Pos               (24)                                       /*!< SC_T::CTL: CDDBSEL Position   */
+#define SC_CTL_CDDBSEL_Msk               (0x3ul << SC_CTL_CDDBSEL_Pos)              /*!< SC_T::CTL: CDDBSEL Mask       */
+
+#define SC_CTL_CDLV_Pos                  (26)                                       /*!< SC_T::CTL: CDLV Position  */
+#define SC_CTL_CDLV_Msk                  (0x1ul << SC_CTL_CDLV_Pos)                 /*!< SC_T::CTL: CDLV Mask      */
+
+#define SC_CTL_SYNC_Pos                  (30)                                       /*!< SC_T::CTL: SYNC Position  */
+#define SC_CTL_SYNC_Msk                  (0x1ul << SC_CTL_SYNC_Pos)                 /*!< SC_T::CTL: SYNC Mask      */
+
+#define SC_CTL_ICEDEBUG_Pos              (31)                                       /*!< SC_T::CTL: ICEDEBUG Position  */
+#define SC_CTL_ICEDEBUG_Msk              (0x1ul << SC_CTL_ICEDEBUG_Pos)             /*!< SC_T::CTL: ICEDEBUG Mask      */
+
+#define SC_ALTCTL_TXRST_Pos              (0)                                        /*!< SC_T::ALTCTL: TXRST Position  */
+#define SC_ALTCTL_TXRST_Msk              (0x1ul << SC_ALTCTL_TXRST_Pos)             /*!< SC_T::ALTCTL: TXRST Mask      */
+
+#define SC_ALTCTL_RXRST_Pos              (1)                                        /*!< SC_T::ALTCTL: RXRST Position  */
+#define SC_ALTCTL_RXRST_Msk              (0x1ul << SC_ALTCTL_RXRST_Pos)             /*!< SC_T::ALTCTL: RXRST Mask      */
+
+#define SC_ALTCTL_DACTEN_Pos             (2)                                        /*!< SC_T::ALTCTL: DACTEN Position */
+#define SC_ALTCTL_DACTEN_Msk             (0x1ul << SC_ALTCTL_DACTEN_Pos)            /*!< SC_T::ALTCTL: DACTEN Mask     */
+
+#define SC_ALTCTL_ACTEN_Pos              (3)                                        /*!< SC_T::ALTCTL: ACTEN Position  */
+#define SC_ALTCTL_ACTEN_Msk              (0x1ul << SC_ALTCTL_ACTEN_Pos)             /*!< SC_T::ALTCTL: ACTEN Mask      */
+
+#define SC_ALTCTL_WARSTEN_Pos            (4)                                        /*!< SC_T::ALTCTL: WARSTEN Position    */
+#define SC_ALTCTL_WARSTEN_Msk            (0x1ul << SC_ALTCTL_WARSTEN_Pos)           /*!< SC_T::ALTCTL: WARSTEN Mask        */
+
+#define SC_ALTCTL_CNTEN0_Pos             (5)                                        /*!< SC_T::ALTCTL: CNTEN0 Position */
+#define SC_ALTCTL_CNTEN0_Msk             (0x1ul << SC_ALTCTL_CNTEN0_Pos)            /*!< SC_T::ALTCTL: CNTEN0 Mask     */
+
+#define SC_ALTCTL_CNTEN1_Pos             (6)                                        /*!< SC_T::ALTCTL: CNTEN1 Position */
+#define SC_ALTCTL_CNTEN1_Msk             (0x1ul << SC_ALTCTL_CNTEN1_Pos)            /*!< SC_T::ALTCTL: CNTEN1 Mask     */
+
+#define SC_ALTCTL_CNTEN2_Pos             (7)                                        /*!< SC_T::ALTCTL: CNTEN2 Position */
+#define SC_ALTCTL_CNTEN2_Msk             (0x1ul << SC_ALTCTL_CNTEN2_Pos)            /*!< SC_T::ALTCTL: CNTEN2 Mask     */
+
+#define SC_ALTCTL_INITSEL_Pos            (8)                                        /*!< SC_T::ALTCTL: INITSEL Position    */
+#define SC_ALTCTL_INITSEL_Msk            (0x3ul << SC_ALTCTL_INITSEL_Pos)           /*!< SC_T::ALTCTL: INITSEL Mask        */
+
+#define SC_ALTCTL_ADACEN_Pos             (11)                                       /*!< SC_T::ALTCTL: ADACEN Position    */
+#define SC_ALTCTL_ADACEN_Msk             (0x1ul << SC_ALTCTL_ADACEN_Pos)            /*!< SC_T::ALTCTL: ADACEN Mask        */
+
+#define SC_ALTCTL_RXBGTEN_Pos            (12)                                       /*!< SC_T::ALTCTL: RXBGTEN Position    */
+#define SC_ALTCTL_RXBGTEN_Msk            (0x1ul << SC_ALTCTL_RXBGTEN_Pos)           /*!< SC_T::ALTCTL: RXBGTEN Mask        */
+
+#define SC_ALTCTL_ACTSTS0_Pos            (13)                                       /*!< SC_T::ALTCTL: ACTSTS0 Position    */
+#define SC_ALTCTL_ACTSTS0_Msk            (0x1ul << SC_ALTCTL_ACTSTS0_Pos)           /*!< SC_T::ALTCTL: ACTSTS0 Mask        */
+
+#define SC_ALTCTL_ACTSTS1_Pos            (14)                                       /*!< SC_T::ALTCTL: ACTSTS1 Position    */
+#define SC_ALTCTL_ACTSTS1_Msk            (0x1ul << SC_ALTCTL_ACTSTS1_Pos)           /*!< SC_T::ALTCTL: ACTSTS1 Mask        */
+
+#define SC_ALTCTL_ACTSTS2_Pos            (15)                                       /*!< SC_T::ALTCTL: ACTSTS2 Position    */
+#define SC_ALTCTL_ACTSTS2_Msk            (0x1ul << SC_ALTCTL_ACTSTS2_Pos)           /*!< SC_T::ALTCTL: ACTSTS2 Mask        */
+
+#define SC_ALTCTL_OUTSEL_Pos             (16)                                       /*!< SC_T::ALTCTL: OUTSEL Position */
+#define SC_ALTCTL_OUTSEL_Msk             (0x1ul << SC_ALTCTL_OUTSEL_Pos)            /*!< SC_T::ALTCTL: OUTSEL Mask     */
+
+#define SC_EGT_EGT_Pos                   (0)                                        /*!< SC_T::EGT: EGT Position   */
+#define SC_EGT_EGT_Msk                   (0xfful << SC_EGT_EGT_Pos)                 /*!< SC_T::EGT: EGT Mask       */
+
+#define SC_RXTOUT_RFTM_Pos               (0)                                        /*!< SC_T::RXTOUT: RFTM Position   */
+#define SC_RXTOUT_RFTM_Msk               (0x1fful << SC_RXTOUT_RFTM_Pos)            /*!< SC_T::RXTOUT: RFTM Mask       */
+
+#define SC_ETUCTL_ETURDIV_Pos            (0)                                        /*!< SC_T::ETUCTL: ETURDIV_ Position   */
+#define SC_ETUCTL_ETURDIV_Msk            (0xffful << SC_ETUCTL_ETURDIV_Pos)         /*!< SC_T::ETUCTL: ETURDIV_ Mask       */
+
+#define SC_ETUCTL_CMPEN_Pos              (15)                                       /*!< SC_T::ETUCTL: CMPEN_ Position */
+#define SC_ETUCTL_CMPEN_Msk              (0x1ul << SC_ETUCTL_CMPEN_Pos)             /*!< SC_T::ETUCTL: CMPEN_ Mask     */
+
+#define SC_INTEN_RDAIEN_Pos              (0)                                        /*!< SC_T::INTEN: RDAIEN Position  */
+#define SC_INTEN_RDAIEN_Msk              (0x1ul << SC_INTEN_RDAIEN_Pos)             /*!< SC_T::INTEN: RDAIEN Mask      */
+
+#define SC_INTEN_TBEIEN_Pos              (1)                                        /*!< SC_T::INTEN: TBEIEN Position  */
+#define SC_INTEN_TBEIEN_Msk              (0x1ul << SC_INTEN_TBEIEN_Pos)             /*!< SC_T::INTEN: TBEIEN Mask      */
+
+#define SC_INTEN_TERRIEN_Pos             (2)                                        /*!< SC_T::INTEN: TERRIEN Position */
+#define SC_INTEN_TERRIEN_Msk             (0x1ul << SC_INTEN_TERRIEN_Pos)            /*!< SC_T::INTEN: TERRIEN Mask     */
+
+#define SC_INTEN_TMR0IEN_Pos             (3)                                        /*!< SC_T::INTEN: TMR0IEN_Position */
+#define SC_INTEN_TMR0IEN_Msk             (0x1ul << SC_INTEN_TMR0IEN_Pos)            /*!< SC_T::INTEN: TMR0IEN Mask     */
+
+#define SC_INTEN_TMR1IEN_Pos             (4)                                        /*!< SC_T::INTEN: TMR1IEN Position */
+#define SC_INTEN_TMR1IEN_Msk             (0x1ul << SC_INTEN_TMR1IEN_Pos)            /*!< SC_T::INTEN: TMR1IEN Mask     */
+
+#define SC_INTEN_TMR2IEN_Pos             (5)                                        /*!< SC_T::INTEN: TMR2IEN Position */
+#define SC_INTEN_TMR2IEN_Msk             (0x1ul << SC_INTEN_TMR2IEN_Pos)            /*!< SC_T::INTEN: TMR2IEN Mask     */
+
+#define SC_INTEN_BGTIEN_Pos              (6)                                        /*!< SC_T::INTEN: BGTIEN Position  */
+#define SC_INTEN_BGTIEN_Msk              (0x1ul << SC_INTEN_BGTIEN_Pos)             /*!< SC_T::INTEN: BGTIEN Mask      */
+
+#define SC_INTEN_CDIEN_Pos               (7)                                        /*!< SC_T::INTEN: CDIEN Position   */
+#define SC_INTEN_CDIEN_Msk               (0x1ul << SC_INTEN_CDIEN_Pos)              /*!< SC_T::INTEN: CDIEN Mask       */
+
+#define SC_INTEN_INITIEN_Pos             (8)                                        /*!< SC_T::INTEN: INITIEN Position */
+#define SC_INTEN_INITIEN_Msk             (0x1ul << SC_INTEN_INITIEN_Pos)            /*!< SC_T::INTEN: INITIEN Mask     */
+
+#define SC_INTEN_RXTOIF_Pos              (9)                                        /*!< SC_T::INTEN: RXTOIF Position  */
+#define SC_INTEN_RXTOIF_Msk              (0x1ul << SC_INTEN_RXTOIF_Pos)             /*!< SC_T::INTEN: RXTOIF Mask      */
+
+#define SC_INTEN_ACERRIEN_Pos            (10)                                       /*!< SC_T::INTEN: ACERRIEN Position    */
+#define SC_INTEN_ACERRIEN_Msk            (0x1ul << SC_INTEN_ACERRIEN_Pos)           /*!< SC_T::INTEN: ACERRIEN Mask        */
+
+#define SC_INTSTS_RDAIF_Pos              (0)                                        /*!< SC_T::INTSTS: RDAIF Position  */
+#define SC_INTSTS_RDAIF_Msk              (0x1ul << SC_INTSTS_RDAIF_Pos)             /*!< SC_T::INTSTS: RDAIF Mask      */
+
+#define SC_INTSTS_TBEIF_Pos              (1)                                        /*!< SC_T::INTSTS: TBEIF Position  */
+#define SC_INTSTS_TBEIF_Msk              (0x1ul << SC_INTSTS_TBEIF_Pos)             /*!< SC_T::INTSTS: TBEIF Mask      */
+
+#define SC_INTSTS_TERRIF_Pos             (2)                                        /*!< SC_T::INTSTS: TERRIF Position */
+#define SC_INTSTS_TERRIF_Msk             (0x1ul << SC_INTSTS_TERRIF_Pos)            /*!< SC_T::INTSTS: TERRIF Mask     */
+
+#define SC_INTSTS_TMR0IF_Pos             (3)                                        /*!< SC_T::INTSTS: TMR0IF Position */
+#define SC_INTSTS_TMR0IF_Msk             (0x1ul << SC_INTSTS_TMR0IF_Pos)            /*!< SC_T::INTSTS: TMR0IF Mask     */
+
+#define SC_INTSTS_TMR1IF_Pos             (4)                                        /*!< SC_T::INTSTS: TMR1IF Position */
+#define SC_INTSTS_TMR1IF_Msk             (0x1ul << SC_INTSTS_TMR1IF_Pos)            /*!< SC_T::INTSTS: TMR1IF Mask     */
+
+#define SC_INTSTS_TMR2IF_Pos             (5)                                        /*!< SC_T::INTSTS: TMR2IF Position */
+#define SC_INTSTS_TMR2IF_Msk             (0x1ul << SC_INTSTS_TMR2IF_Pos)            /*!< SC_T::INTSTS: TMR2IF Mask     */
+
+#define SC_INTSTS_BGTIF_Pos              (6)                                        /*!< SC_T::INTSTS: BGTIF Position  */
+#define SC_INTSTS_BGTIF_Msk              (0x1ul << SC_INTSTS_BGTIF_Pos)             /*!< SC_T::INTSTS: BGTIF Mask      */
+
+#define SC_INTSTS_CDIF_Pos               (7)                                        /*!< SC_T::INTSTS: CDIF Position   */
+#define SC_INTSTS_CDIF_Msk               (0x1ul << SC_INTSTS_CDIF_Pos)              /*!< SC_T::INTSTS: CDIF Mask       */
+
+#define SC_INTSTS_INITIF_Pos             (8)                                        /*!< SC_T::INTSTS: INITIF Position */
+#define SC_INTSTS_INITIF_Msk             (0x1ul << SC_INTSTS_INITIF_Pos)            /*!< SC_T::INTSTS: INITIF Mask     */
+
+#define SC_INTSTS_RBTOIF_Pos             (9)                                        /*!< SC_T::INTSTS: RBTOIF Position */
+#define SC_INTSTS_RBTOIF_Msk             (0x1ul << SC_INTSTS_RBTOIF_Pos)            /*!< SC_T::INTSTS: RBTOIF Mask     */
+
+#define SC_INTSTS_ACERRIF_Pos            (10)                                       /*!< SC_T::INTSTS: ACERRIF Position    */
+#define SC_INTSTS_ACERRIF_Msk            (0x1ul << SC_INTSTS_ACERRIF_Pos)           /*!< SC_T::INTSTS: ACERRIF Mask        */
+
+#define SC_STATUS_RXOV_Pos               (0)                                        /*!< SC_T::STATUS: RXO Position    */
+#define SC_STATUS_RXOV_Msk               (0x1ul << SC_STATUS_RXOV_Pos)              /*!< SC_T::STATUS: RXO Mask        */
+
+#define SC_STATUS_RXEMPTY_Pos            (1)                                        /*!< SC_T::STATUS: RXEMPTY Position    */
+#define SC_STATUS_RXEMPTY_Msk            (0x1ul << SC_STATUS_RXEMPTY_Pos)           /*!< SC_T::STATUS: RXEMPTY Mask        */
+
+#define SC_STATUS_RXFULL_Pos             (2)                                        /*!< SC_T::STATUS: RXFULL Position */
+#define SC_STATUS_RXFULL_Msk             (0x1ul << SC_STATUS_RXFULL_Pos)            /*!< SC_T::STATUS: RXFULL Mask     */
+
+#define SC_STATUS_PEF_Pos                (4)                                        /*!< SC_T::STATUS: PEF Position    */
+#define SC_STATUS_PEF_Msk                (0x1ul << SC_STATUS_PEF_Pos)               /*!< SC_T::STATUS: PEF Mask        */
+
+#define SC_STATUS_FEF_Pos                (5)                                        /*!< SC_T::STATUS: FEF Position    */
+#define SC_STATUS_FEF_Msk                (0x1ul << SC_STATUS_FEF_Pos)               /*!< SC_T::STATUS: FEF Mask        */
+
+#define SC_STATUS_BEF_Pos                (6)                                        /*!< SC_T::STATUS: BEF Position    */
+#define SC_STATUS_BEF_Msk                (0x1ul << SC_STATUS_BEF_Pos)               /*!< SC_T::STATUS: BEF Mask        */
+
+#define SC_STATUS_TXOV_Pos               (8)                                        /*!< SC_T::STATUS: TXOV Position   */
+#define SC_STATUS_TXOV_Msk               (0x1ul << SC_STATUS_TXOV_Pos)              /*!< SC_T::STATUS: TXOV Mask       */
+
+#define SC_STATUS_TXEMPTY_Pos            (9)                                        /*!< SC_T::STATUS: TXEMPTY Position    */
+#define SC_STATUS_TXEMPTY_Msk            (0x1ul << SC_STATUS_TXEMPTY_Pos)           /*!< SC_T::STATUS: TXEMPTY Mask        */
+
+#define SC_STATUS_TXFULL_Pos             (10)                                       /*!< SC_T::STATUS: TXFULL Position */
+#define SC_STATUS_TXFULL_Msk             (0x1ul << SC_STATUS_TXFULL_Pos)            /*!< SC_T::STATUS: TXFULL Mask     */
+
+#define SC_STATUS_CREMOVE_Pos            (11)                                       /*!< SC_T::STATUS: CREMOVE Position    */
+#define SC_STATUS_CREMOVE_Msk            (0x1ul << SC_STATUS_CREMOVE_Pos)           /*!< SC_T::STATUS: CREMOVE Mask        */
+
+#define SC_STATUS_CINSERT_Pos            (12)                                       /*!< SC_T::STATUS: CINSERT Position    */
+#define SC_STATUS_CINSERT_Msk            (0x1ul << SC_STATUS_CINSERT_Pos)           /*!< SC_T::STATUS: CINSERT Mask        */
+
+#define SC_STATUS_CDPINSTS_Pos           (13)                                       /*!< SC_T::STATUS: CDPINSTS Position   */
+#define SC_STATUS_CDPINSTS_Msk           (0x1ul << SC_STATUS_CDPINSTS_Pos)          /*!< SC_T::STATUS: CDPINSTS Mask       */
+
+#define SC_STATUS_RXPOINT_Pos            (16)                                       /*!< SC_T::STATUS: RXPOINT Position    */
+#define SC_STATUS_RXPOINT_Msk            (0x3ul << SC_STATUS_RXPOINT_Pos)           /*!< SC_T::STATUS: RXPOINT Mask        */
+
+#define SC_STATUS_RXRERR_Pos             (21)                                       /*!< SC_T::STATUS: RXRERR Position     */
+#define SC_STATUS_RXRERR_Msk             (0x1ul << SC_STATUS_RXRERR_Pos)            /*!< SC_T::STATUS: RXRERR Mask         */
+
+#define SC_STATUS_RXOVERR_Pos            (22)                                       /*!< SC_T::STATUS: RXOVERR Position    */
+#define SC_STATUS_RXOVERR_Msk            (0x1ul << SC_STATUS_RXOVERR_Pos)           /*!< SC_T::STATUS: RXOVERR Mask        */
+
+#define SC_STATUS_RXACT_Pos              (23)                                       /*!< SC_T::STATUS: RXACT Position      */
+#define SC_STATUS_RXACT_Msk              (0x1ul << SC_STATUS_RXACT_Pos)             /*!< SC_T::STATUS: RXACT Msk           */
+
+#define SC_STATUS_TXPOINT_Pos            (24)                                       /*!< SC_T::STATUS: TXPOINT Position    */
+#define SC_STATUS_TXPOINT_Msk            (0x3ul << SC_STATUS_TXPOINT_Pos)           /*!< SC_T::STATUS: TXPOINT Msk         */
+
+#define SC_STATUS_TXRERR_Pos             (29)                                       /*!< SC_T::STATUS: TXRERR Position     */
+#define SC_STATUS_TXRERR_Msk             (0x1ul << SC_STATUS_TXRERR_Pos)            /*!< SC_T::STATUS: TXRERR Msk          */
+
+#define SC_STATUS_TXOVERR_Pos            (30)                                       /*!< SC_T::STATUS: TXOVERR_ Position   */
+#define SC_STATUS_TXOVERR_Msk            (0x1ul << SC_STATUS_TXOVERR_Pos)           /*!< SC_T::STATUS: TXOVERR_ Msk        */
+
+#define SC_STATUS_TXACT_Pos              (31)                                       /*!< SC_T::STATUS: TXACT Position      */
+#define SC_STATUS_TXACT_Msk              (0x1ul << SC_STATUS_TXACT_Pos)             /*!< SC_T::STATUS: TXACT Msk           */
+
+#define SC_PINCTL_PWREN_Pos              (0)                                        /*!< SC_T::PINCTL: PWREN Position  */
+#define SC_PINCTL_PWREN_Msk              (0x1ul << SC_PINCTL_PWREN_Pos)             /*!< SC_T::PINCTL: PWREN Msk       */
+
+#define SC_PINCTL_SCRST_Pos              (1)                                        /*!< SC_T::PINCTL: SCRST Position  */
+#define SC_PINCTL_SCRST_Msk              (0x1ul << SC_PINCTL_SCRST_Pos)             /*!< SC_T::PINCTL: SCRST Msk       */
+
+#define SC_PINCTL_CSTOPLV_Pos            (5)                                        /*!< SC_T::PINCTL: CSTOPLV Position    */
+#define SC_PINCTL_CSTOPLV_Msk            (0x1ul << SC_PINCTL_CSTOPLV_Pos)           /*!< SC_T::PINCTL: CSTOPLV Msk         */
+
+#define SC_PINCTL_CLKKEEP_Pos            (6)                                        /*!< SC_T::PINCTL: CLKKEEP Position    */
+#define SC_PINCTL_CLKKEEP_Msk            (0x1ul << SC_PINCTL_CLKKEEP_Pos)           /*!< SC_T::PINCTL: CLKKEEP Msk         */
+
+#define SC_PINCTL_SCDOUT_Pos             (9)                                        /*!< SC_T::PINCTL: SCDOUT Position */
+#define SC_PINCTL_SCDOUT_Msk             (0x1ul << SC_PINCTL_SCDOUT_Pos)            /*!< SC_T::PINCTL: SCDOUT Msk      */
+
+#define SC_PINCTL_PWRINV_Pos             (11)                                       /*!< SC_T::PINCTL: PWRINV Position */
+#define SC_PINCTL_PWRINV_Msk             (0x1ul << SC_PINCTL_PWRINV_Pos)            /*!< SC_T::PINCTL: PWRINV Msk      */
+
+#define SC_PINCTL_SCDOSTS_Pos            (12)                                       /*!< SC_T::PINCTL: SCDOSTS Position    */
+#define SC_PINCTL_SCDOSTS_Msk            (0x1ul << SC_PINCTL_SCDOSTS_Pos)           /*!< SC_T::PINCTL: SCDOSTS Msk         */
+
+#define SC_PINCTL_DATSTS_Pos             (16)                                       /*!< SC_T::PINCTL: DATSTS Position */
+#define SC_PINCTL_DATSTS_Msk             (0x1ul << SC_PINCTL_DATSTS_Pos)            /*!< SC_T::PINCTL: DATSTS Msk      */
+
+#define SC_PINCTL_PWRSTS_Pos             (17)                                       /*!< SC_T::PINCTL: PWRSTS Position */
+#define SC_PINCTL_PWRSTS_Msk             (0x1ul << SC_PINCTL_PWRSTS_Pos)            /*!< SC_T::PINCTL: PWRSTS Msk      */
+
+#define SC_PINCTL_RSTSTS_Pos             (18)                                       /*!< SC_T::PINCTL: RSTSTS Position */
+#define SC_PINCTL_RSTSTS_Msk             (0x1ul << SC_PINCTL_RSTSTS_Pos)            /*!< SC_T::PINCTL: RSTSTS Msk      */
+
+#define SC_PINCTL_SYNC_Pos               (30)                                       /*!< SC_T::PINCTL: SYNC Position   */
+#define SC_PINCTL_SYNC_Msk               (0x1ul << SC_PINCTL_SYNC_Pos)              /*!< SC_T::PINCTL: SYNC Msk        */
+
+#define SC_PINCTL_LOOPBK_Pos             (31)                                       /*!< SC_T::PINCTL: LOOPBK Position */
+#define SC_PINCTL_LOOPBK_Msk             (0x1ul << SC_PINCTL_LOOPBK_Pos)            /*!< SC_T::PINCTL: LOOPBK Msk      */
+
+#define SC_TMRCTL0_CNT_Pos               (0)                                        /*!< SC_T::TMRCTL0: CNT Position   */
+#define SC_TMRCTL0_CNT_Msk               (0xfffffful << SC_TMRCTL0_CNT_Pos)         /*!< SC_T::TMRCTL0: CNT Msk        */
+
+#define SC_TMRCTL0_OPMODE_Pos            (24)                                       /*!< SC_T::TMRCTL0: OPMODE Position    */
+#define SC_TMRCTL0_OPMODE_Msk            (0xful << SC_TMRCTL0_OPMODE_Pos)           /*!< SC_T::TMRCTL0: OPMODE Msk         */
+
+#define SC_TMRCTL1_CNT_Pos               (0)                                        /*!< SC_T::TMRCTL1: CNT Position   */
+#define SC_TMRCTL1_CNT_Msk               (0xfful << SC_TMRCTL1_CNT_Pos)             /*!< SC_T::TMRCTL1: CNT Msk        */
+
+#define SC_TMRCTL1_OPMODE_Pos            (24)                                       /*!< SC_T::TMRCTL1: OPMODE Position    */
+#define SC_TMRCTL1_OPMODE_Msk            (0xful << SC_TMRCTL1_OPMODE_Pos)           /*!< SC_T::TMRCTL1: OPMODE Msk         */
+
+#define SC_TMRCTL2_CNT_Pos               (0)                                        /*!< SC_T::TMRCTL2: CNT Position   */
+#define SC_TMRCTL2_CNT_Msk               (0xfful << SC_TMRCTL2_CNT_Pos)             /*!< SC_T::TMRCTL2: CNT Msk        */
+
+#define SC_TMRCTL2_OPMODE_Pos            (24)                                       /*!< SC_T::TMRCTL2: OPMODE Position    */
+#define SC_TMRCTL2_OPMODE_Msk            (0xful << SC_TMRCTL2_OPMODE_Pos)           /*!< SC_T::TMRCTL2: OPMODE Msk         */
+
+#define SC_UARTCTL_UARTEN_Pos            (0)                                        /*!< SC_T::UARTCTL: UARTEN Position    */
+#define SC_UARTCTL_UARTEN_Msk            (0x1ul << SC_UARTCTL_UARTEN_Pos)           /*!< SC_T::UARTCTL: UARTEN Msk         */
+
+#define SC_UARTCTL_WLS_Pos               (4)                                        /*!< SC_T::UARTCTL: WLS Position   */
+#define SC_UARTCTL_WLS_Msk               (0x3ul << SC_UARTCTL_WLS10_Pos)            /*!< SC_T::UARTCTL: WLS Msk        */
+
+#define SC_UARTCTL_PBOFF_Pos             (6)                                        /*!< SC_T::UARTCTL: PBOFF Position */
+#define SC_UARTCTL_PBOFF_Msk             (0x1ul << SC_UARTCTL_PBOFF_Pos)            /*!< SC_T::UARTCTL: PBOFF Msk      */
+
+#define SC_UARTCTL_OPE_Pos               (7)                                        /*!< SC_T::UARTCTL: OPE Position   */
+#define SC_UARTCTL_OPE_Msk               (0x1ul << SC_UARTCTL_OPE_Pos)              /*!< SC_T::UARTCTL: OPE Msk        */
+
+#define SC_TMRDAT0_CNT0_Pos              (0)                                        /*!< SC_T::TMRDAT0: CNT0 Position  */
+#define SC_TMRDAT0_CNT0_Msk              (0xfffffful << SC_TMRDAT0_CNT0_Pos)        /*!< SC_T::TMRDAT0: CNT0 Msk       */
+
+#define SC_TMRDAT1_2_CNT1_Pos            (0)                                        /*!< SC_T::TMRDAT1_2: CNT1 Position    */
+#define SC_TMRDAT1_2_CNT1_Msk            (0xfful << SC_TMRDAT1_2_CNT1_Pos)          /*!< SC_T::TMRDAT1_2: CNT1 Msk         */
+
+#define SC_TMRDAT1_2_CNT2_Pos            (8)                                        /*!< SC_T::TMRDAT1_2: CNT2 Position    */
+#define SC_TMRDAT1_2_CNT2_Msk            (0xfful << SC_TMRDAT1_2_CNT2_Pos)          /*!< SC_T::TMRDAT1_2: CNT2 Msk         */
+
+/**@}*/ /* SC_CONST */
+/**@}*/ /* end of SC register group */
+
+
+/*---------------------- Serial Peripheral Interface Controller -------------------------*/
+/**
+    @addtogroup SPI Serial Peripheral Interface Controller(SPI)
+    Memory Mapped Structure for SPI Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var SPI_T::CTL
+ * Offset: 0x00  Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SPIEN     |SPI Transfer Control Enable Bit
+ * |        |          |In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1.
+ * |        |          |In Slave mode, this device is ready to receive data when this bit is set to 1.
+ * |        |          |0 = Transfer control Disabled.
+ * |        |          |1 = Transfer control Enabled.
+ * |        |          |Note: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0.
+ * |[1]     |RXNEG     |Receive On Negative Edge
+ * |        |          |0 = Received data input signal is latched on the rising edge of SPI bus clock.
+ * |        |          |1 = Received data input signal is latched on the falling edge of SPI bus clock.
+ * |[2]     |TXNEG     |Transmit On Negative Edge
+ * |        |          |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
+ * |        |          |1 = Transmitted data output signal is changed on the falling edge of SP bus clock.
+ * |[3]     |CLKPOL    |Clock Polarity
+ * |        |          |0 = SPI bus clock is idle low.
+ * |        |          |1 = SPI bus clock is idle high.
+ * |[7:4]   |SUSPITV   |Suspend Interval (Master Only)
+ * |        |          |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
+ * |        |          |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
+ * |        |          |The default value is 0x3.
+ * |        |          |The period of the suspend interval is obtained according to the following equation.
+ * |        |          |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
+ * |        |          |Example:
+ * |        |          |SUSPITV = 0x0 ... 0.5 SPICLK clock cycle.
+ * |        |          |SUSPITV = 0x1 ... 1.5 SPICLK clock cycle.
+ * |        |          |...
+ * |        |          |SUSPITV = 0xE ... 14.5 SPICLK clock cycle.
+ * |        |          |SUSPITV = 0xF ... 15.5 SPICLK clock cycle.
+ * |[12:8]  |DWIDTH    |Data Width
+ * |        |          |This field specifies how many bits can be transmitted / received in one transaction.
+ * |        |          |The minimum bit length is 8 bits and can up to 32 bits.
+ * |        |          |DWIDTH = 0x08 ... 8 bits.
+ * |        |          |DWIDTH = 0x09 ... 9 bits.
+ * |        |          |...
+ * |        |          |DWIDTH = 0x1F ... 31 bits.
+ * |        |          |DWIDTH = 0x00 ... 32 bits.
+ * |[13]    |LSB       |Send LSB First
+ * |        |          |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
+ * |        |          |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
+ * |[16]    |TWOBIT    |2-Bit Transfer Mode Enable Bit (Only Supported in SPI0)
+ * |        |          |0 = 2-Bit Transfer mode Disabled.
+ * |        |          |1 = 2-Bit Transfer mode Enabled.
+ * |        |          |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd
+ * |        |          |serial transmitted bit data is from the second FIFO buffer data.
+ * |        |          |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
+ * |[17]    |UNITIEN   |Unit Transfer Interrupt Enable Bit
+ * |        |          |0 = SPI unit transfer interrupt Disabled.
+ * |        |          |1 = SPI unit transfer interrupt Enabled.
+ * |[18]    |SLAVE     |Slave Mode Control
+ * |        |          |0 = Master mode.
+ * |        |          |1 = Slave mode.
+ * |[19]    |REORDER   |Byte Reorder Function Enable Bit
+ * |        |          |0 = Byte Reorder function Disabled.
+ * |        |          |1 = Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte.
+ * |        |          |The period of the byte suspend interval depends on the setting of SUSPITV.
+ * |        |          |Note:
+ * |        |          |1. Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
+ * |        |          |2. Byte Reorder function is not supported when the Quad or Dual I/O mode is enabled.
+ * |[20]    |QDIODIR   |Quad Or Dual I/O Mode Direction Control (Only Supported in SPI0)
+ * |        |          |0 = Quad or Dual Input mode.
+ * |        |          |1 = Quad or Dual Output mode.
+ * |[21]    |DUALIOEN  |Dual I/O Mode Enable Bit (Only Supported in SPI0)
+ * |        |          |0 = Dual I/O mode Disabled.
+ * |        |          |1 = Dual I/O mode Enabled.
+ * |[22]    |QUADIOEN  |Quad I/O Mode Enable Bit (Only Supported in SPI0)
+ * |        |          |0 = Quad I/O mode Disabled.
+ * |        |          |1 = Quad I/O mode Enabled.
+ * @var SPI_T::CLKDIV
+ * Offset: 0x04  Clock Divider Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |DIVIDER   |Clock Divider
+ * |        |          |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master.
+ * |        |          |The frequency is obtained according to the following equation.
+ * |        |          | fspi_eclk = fspi_clock_src / (DIVIDER + 1)
+ * |        |          |where fspi_clock_src is the peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
+ * @var SPI_T::SSCTL
+ * Offset: 0x08  Slave Select Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SS        |Slave Selection Control (Master Only)
+ * |        |          |If AUTOSS bit is cleared to 0,
+ * |        |          |0 = set the SPIn_SS line to inactive state.
+ * |        |          |1 = set the SPIn_SS line to active state
+ * |        |          |If the AUTOSS bit is set to 1,
+ * |        |          |0 = Keep the SPIn_SS line at inactive state.
+ * |        |          |1 = SPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time.
+ * |        |          |The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2]).
+ * |[2]     |SSACTPOL  |Slave Selection Active Polarity
+ * |        |          |This bit defines the active polarity of slave selection signal (SPIn_SS).
+ * |        |          |0 = The slave selection signal SPIn_SS is active low.
+ * |        |          |1 = The slave selection signal SPIn_SS is active high.
+ * |[3]     |AUTOSS    |Automatic Slave Selection Function Enable Bit (Master Only)
+ * |        |          |0 = Automatic slave selection function Disabled.
+ * |        |          |Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0]).
+ * |        |          |1 = Automatic slave selection function Enabled.
+ * |[4]     |SLV3WIRE  |Slave 3-Wire Mode Enable Bit
+ * |        |          |Slave 3-wire mode is only available in SPI0.
+ * |        |          |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO, and SPI0_MOSI.
+ * |        |          |0 = 4-wire bi-direction interface.
+ * |        |          |1 = 3-wire bi-direction interface.
+ * |[5]     |SLVTOIEN  |Slave Mode Time-Out Interrupt Enable Bit (Only Supported in SPI0)
+ * |        |          |0 = Slave mode time-out interrupt Disabled.
+ * |        |          |1 = Slave mode time-out interrupt Enabled.
+ * |[6]     |SLVTORST  |Slave Mode Time-Out Reset Control (Only Supported in SPI0)
+ * |        |          |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
+ * |        |          |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
+ * |[8]     |SLVBEIEN  |Slave Mode Bit Count Error Interrupt Enable Bit
+ * |        |          |0 = Slave mode bit count error interrupt Disabled.
+ * |        |          |1 = Slave mode bit count error interrupt Enabled.
+ * |[9]     |SLVURIEN  |Slave Mode TX Under Run Interrupt Enable Bit
+ * |        |          |0 = Slave mode TX under run interrupt Disabled.
+ * |        |          |1 = Slave mode TX under run interrupt Enabled.
+ * |[12]    |SSACTIEN  |Slave Select Active Interrupt Enable Bit
+ * |        |          |0 = Slave select active interrupt Disabled.
+ * |        |          |1 = Slave select active interrupt Enabled.
+ * |[13]    |SSINAIEN  |Slave Select Inactive Interrupt Enable Bit
+ * |        |          |0 = Slave select inactive interrupt Disabled.
+ * |        |          |1 = Slave select inactive interrupt Enabled.
+ * |[31:16] |SLVTOCNT  |Slave Mode Time-Out Period (Only Supported in SPI0)
+ * |        |          |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active.
+ * |        |          |The clock source of the time-out counter is Slave peripheral clock.
+ * |        |          |If the value is 0, it indicates the slave mode time-out function is disabled.
+ * @var SPI_T::PDMACTL
+ * Offset: 0x0C  SPI PDMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |TXPDMAEN  |Transmit PDMA Enable Bit
+ * |        |          |0 = Transmit PDMA function Disabled.
+ * |        |          |1 = Transmit PDMA function Enabled.
+ * |        |          |Note: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function.
+ * |        |          |User can enable TX PDMA function firstly or enable both functions simultaneously.
+ * |[1]     |RXPDMAEN  |Receive PDMA Enable Bit
+ * |        |          |0 = Receiver PDMA function Disabled.
+ * |        |          |1 = Receiver PDMA function Enabled.
+ * |[2]     |PDMARST   |PDMA Reset
+ * |        |          |0 = No effect.
+ * |        |          |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
+ * @var SPI_T::FIFOCTL
+ * Offset: 0x10  SPI FIFO Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |RXRST     |Receive Reset
+ * |        |          |0 = No effect.
+ * |        |          |1 = Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
+ * |        |          |This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
+ * |        |          |User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
+ * |        |          |Note: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
+ * |[1]     |TXRST     |Transmit Reset
+ * |        |          |0 = No effect.
+ * |        |          |1 = Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
+ * |        |          |This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
+ * |        |          |User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
+ * |        |          |Note: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
+ * |[2]     |RXTHIEN   |Receive FIFO Threshold Interrupt Enable Bit
+ * |        |          |0 = RX FIFO threshold interrupt Disabled.
+ * |        |          |1 = RX FIFO threshold interrupt Enabled.
+ * |[3]     |TXTHIEN   |Transmit FIFO Threshold Interrupt Enable Bit
+ * |        |          |0 = TX FIFO threshold interrupt Disabled.
+ * |        |          |1 = TX FIFO threshold interrupt Enabled.
+ * |[4]     |RXTOIEN   |Slave Receive Time-Out Interrupt Enable Bit
+ * |        |          |0 = Receive time-out interrupt Disabled.
+ * |        |          |1 = Receive time-out interrupt Enabled.
+ * |[5]     |RXOVIEN   |Receive FIFO Overrun Interrupt Enable Bit
+ * |        |          |0 = Receive FIFO overrun interrupt Disabled.
+ * |        |          |1 = Receive FIFO overrun interrupt Enabled.
+ * |[6]     |TXUFPOL   |TX Underflow Data Polarity
+ * |        |          |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
+ * |        |          |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
+ * |        |          |Note: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
+ * |[7]     |TXUFIEN   |TX Underflow Interrupt Enable Bit
+ * |        |          |In Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1.
+ * |        |          |0 = Slave TX underflow interrupt Disabled.
+ * |        |          |1 = Slave TX underflow interrupt Enabled.
+ * |[8]     |RXFBCLR   |Receive FIFO Buffer Clear
+ * |        |          |0 = No effect.
+ * |        |          |1 = Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
+ * |        |          |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+ * |        |          |Note: The RX shift register will not be cleared.
+ * |[9]     |TXFBCLR   |Transmit FIFO Buffer Clear
+ * |        |          |0 = No effect.
+ * |        |          |1 = Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
+ * |        |          |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+ * |        |          |Note: The TX shift register will not be cleared.
+ * |[26:24] |RXTH      |Receive FIFO Threshold
+ * |        |          |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
+ * |        |          |In SPI0, RXTH is a 3-bit wide configuration; in SPI1 and SPI2, 2-bit wide only (SPI_FIFOCTL[25:24]).
+ * |[30:28] |TXTH      |Transmit FIFO Threshold
+ * |        |          |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
+ * |        |          |In SPI0, TXTH is a 3-bit wide configuration; in SPI1 and SPI2, 2-bit wide only (SPI_FIFOCTL[29:28]).
+ * @var SPI_T::STATUS
+ * Offset: 0x14  SPI Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |BUSY      |Busy Status (Read Only)
+ * |        |          |0 = SPI controller is in idle state.
+ * |        |          |1 = SPI controller is in busy state.
+ * |        |          |The following listing are the bus busy conditions:
+ * |        |          |a. SPI_CTL[0] = 1 and the TXEMPTY = 0.
+ * |        |          |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
+ * |        |          |c. For SPI Slave mode, the SPI_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
+ * |        |          |d. For SPI Slave mode, the SPI_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
+ * |[1]     |UNITIF    |Unit Transfer Interrupt Flag
+ * |        |          |0 = No transaction has been finished since this bit was cleared to 0.
+ * |        |          |1 = SPI controller has finished one unit transfer.
+ * |        |          |Note: This bit will be cleared by writing 1 to it.
+ * |[2]     |SSACTIF   |Slave Select Active Interrupt Flag
+ * |        |          |0 = Slave select active interrupt was cleared or not occurred.
+ * |        |          |1 = Slave select active interrupt event occurred.
+ * |        |          |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+ * |[3]     |SSINAIF   |Slave Select Inactive Interrupt Flag
+ * |        |          |0 = Slave select inactive interrupt was cleared or not occurred.
+ * |        |          |1 = Slave select inactive interrupt event occurred.
+ * |        |          |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+ * |[4]     |SSLINE    |Slave Select Line Bus Status (Read Only)
+ * |        |          |0 = The slave select line status is 0.
+ * |        |          |1 = The slave select line status is 1.
+ * |        |          |Note: This bit is only available in Slave mode.
+ * |        |          |If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
+ * |[5]     |SLVTOIF   |Slave Time-Out Interrupt Flag (Only Supported in SPI0)
+ * |        |          |When the Slave Select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started.
+ * |        |          |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
+ * |        |          |0 = Slave time-out is not active.
+ * |        |          |1 = Slave time-out is active.
+ * |        |          |Note: This bit will be cleared by writing 1 to it.
+ * |[6]     |SLVBEIF   |Slave Mode Bit Count Error Interrupt Flag
+ * |        |          |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
+ * |        |          |0 = No Slave mode bit count error event.
+ * |        |          |1 = Slave mode bit count error event occurs.
+ * |        |          |Note: If the slave select active but there is no any bus clock input, the SLVBCEIF also active when the slave select goes to inactive state.
+ * |        |          |This bit will be cleared by writing 1 to it.
+ * |[7]     |SLVURIF   |Slave Mode TX Under Run Interrupt Flag
+ * |        |          |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
+ * |        |          |0 = No Slave TX under run event.
+ * |        |          |1 = Slave TX under run occurs.
+ * |        |          |Note: This bit will be cleared by writing 1 to it.
+ * |[8]     |RXEMPTY   |Receive FIFO Buffer Empty Indicator (Read Only)
+ * |        |          |0 = Receive FIFO buffer is not empty.
+ * |        |          |1 = Receive FIFO buffer is empty.
+ * |[9]     |RXFULL    |Receive FIFO Buffer Full Indicator (Read Only)
+ * |        |          |0 = Receive FIFO buffer is not full.
+ * |        |          |1 = Receive FIFO buffer is full.
+ * |[10]    |RXTHIF    |Receive FIFO Threshold Interrupt Flag (Read Only)
+ * |        |          |0 = The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH.
+ * |        |          |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
+ * |[11]    |RXOVIF    |Receive FIFO Overrun Interrupt Flag
+ * |        |          |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
+ * |        |          |0 = No FIFO is over run.
+ * |        |          |1 = Receive FIFO over run.
+ * |        |          |Note: This bit will be cleared by writing 1 to it.
+ * |[12]    |RXTOIF    |Receive Time-Out Interrupt Flag
+ * |        |          |0 = No receive FIFO time-out event.
+ * |        |          |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
+ * |        |          |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
+ * |        |          |Note: This bit will be cleared by writing 1 to it.
+ * |[15]    |SPIENSTS  |SPI Enable Status (Read Only)
+ * |        |          |0 = The SPI controller is disabled.
+ * |        |          |1 = The SPI controller is enabled.
+ * |        |          |Note: The SPI peripheral clock is asynchronous with the system clock.
+ * |        |          |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
+ * |[16]    |TXEMPTY   |Transmit FIFO Buffer Empty Indicator (Read Only)
+ * |        |          |0 = Transmit FIFO buffer is not empty.
+ * |        |          |1 = Transmit FIFO buffer is empty.
+ * |[17]    |TXFULL    |Transmit FIFO Buffer Full Indicator (Read Only)
+ * |        |          |0 = Transmit FIFO buffer is not full.
+ * |        |          |1 = Transmit FIFO buffer is full.
+ * |[18]    |TXTHIF    |Transmit FIFO Threshold Interrupt Flag (Read Only)
+ * |        |          |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
+ * |        |          |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
+ * |[19]    |TXUFIF    |TX Underflow Interrupt Flag
+ * |        |          |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
+ * |        |          |0 = No effect.
+ * |        |          |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
+ * |        |          |Note 1: This bit will be cleared by writing 1 to it.
+ * |        |          |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
+ * |[23]    |TXRXRST   |TX or RX Reset Status (Read Only)
+ * |        |          |0 = The reset function of TXRST or RXRST is done.
+ * |        |          |1 = Doing the reset function of TXRST or RXRST.
+ * |        |          |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles.
+ * |        |          |User can check the status of this bit to monitor the reset function is doing or done.
+ * |[27:24] |RXCNT     |Receive FIFO Data Count (Read Only)
+ * |        |          |This bit field indicates the valid data count of receive FIFO buffer.
+ * |[31:28] |TXCNT     |Transmit FIFO Data Count (Read Only)
+ * |        |          |This bit field indicates the valid data count of transmit FIFO buffer.
+ * @var SPI_T::TX
+ * Offset: 0x20  Data Transmit Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |TX        |Data Transmit Register
+ * |        |          |The data transmit registers pass through the transmitted data into the 8-/4-level transmit FIFO buffer.
+ * |        |          |The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]).
+ * |        |          |For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
+ * |        |          |If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
+ * |        |          |Note: In Master mode, SPI controller will start to transfer after 5 peripheral clock cycles after user writes to this register.
+ * @var SPI_T::RX
+ * Offset: 0x30  Data Receive Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |RX        |Data Receive Register
+ * |        |          |There are 8-/4-level FIFO buffers in this controller.
+ * |        |          |The data receive register holds the data received from SPI data input pin.
+ * |        |          |If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
+ * |        |          |This is a read only register.
+ * @var SPI_T::I2SCTL
+ * Offset: 0x60  I2S Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |I2SEN     |I2S Controller Enable Bit
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |        |          |Note: If enable this bit, I2Sn_BCLK will start to output in master mode.
+ * |[1]     |TXEN      |Transmit Enable Bit
+ * |        |          |0 = Data transmit Disabled.
+ * |        |          |1 = Data transmit Enabled.
+ * |[2]     |RXEN      |Receive Enable Bit
+ * |        |          |0 = Data receiving Disabled.
+ * |        |          |1 = Data receiving Enabled.
+ * |[3]     |MUTE      |Transmit Mute Enable Bit
+ * |        |          |0 = Transmit data is shifted from buffer.
+ * |        |          |1= Transmit channel zero.
+ * |[5:4]   |WDWIDTH   |Word Width
+ * |        |          |00 = data is 8-bit.
+ * |        |          |01 = data is 16-bit.
+ * |        |          |10 = data is 24-bit.
+ * |        |          |11 = data is 32-bit.
+ * |[6]     |MONO      |Monaural Data
+ * |        |          |0 = Data is stereo format.
+ * |        |          |1 = Data is monaural format.
+ * |[7]     |ORDER     |Stereo Data Order In FIFO
+ * |        |          |0 = Left channel data at high byte.
+ * |        |          |1 = Left channel data at low byte.
+ * |[8]     |SLAVE     |Slave Mode
+ * |        |          |I2S can operate as master or slave.
+ * |        |          |For Master mode, I2Sn_BCLK and I2Sn_LRCLK pins are output mode and send bit clock from NuMicro M451 series to Audio CODEC chip.
+ * |        |          |In Slave mode, I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and I2Sn_LRCLK signals are received from outer Audio CODEC chip.
+ * |        |          |0 = Master mode.
+ * |        |          |1 = Slave mode.
+ * |[15]    |MCLKEN    |Master Clock Enable Bit
+ * |        |          |If MCLKEN is set to 1, I2S controller will generate master clock on I2Sn_MCLK pin for external audio devices.
+ * |        |          |0 = Master clock Disabled.
+ * |        |          |1 = Master clock Enabled.
+ * |[16]    |RZCEN     |Right Channel Zero Cross Detection Enable Bit
+ * |        |          |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register is set to 1.
+ * |        |          |This function is only available in transmit operation.
+ * |        |          |0 = Right channel zero cross detection Disabled.
+ * |        |          |1 = Right channel zero cross detection Enabled.
+ * |[17]    |LZCEN     |Left Channel Zero Cross Detection Enable Bit
+ * |        |          |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI_I2SSTS register is set to 1.
+ * |        |          |This function is only available in transmit operation.
+ * |        |          |0 = Left channel zero cross detection Disabled.
+ * |        |          |1 = Left channel zero cross detection Enabled.
+ * |[23]    |RXLCH     |Receive Left Channel Enable Bit
+ * |        |          |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
+ * |        |          |0 = Receive right channel data in Mono mode.
+ * |        |          |1 = Receive left channel data in Mono mode.
+ * |[24]    |RZCIEN    |Right Channel Zero-Cross Interrupt Enable Bit
+ * |        |          |Interrupt occurs if this bit is set to 1 and right channel zero-cross event occurs.
+ * |        |          |0 = Interrupt Disabled.
+ * |        |          |1 = Interrupt Enabled.
+ * |[25]    |LZCIEN    |Left Channel Zero-Cross Interrupt Enable Bit
+ * |        |          |Interrupt occurs if this bit is set to 1 and left channel zero-cross event occurs.
+ * |        |          |0 = Interrupt Disabled.
+ * |        |          |1 = Interrupt Enabled.
+ * |[29:28] |FORMAT    |Data Format Selection
+ * |        |          |00 = I2S data format.
+ * |        |          |01 = MSB justified data format.
+ * |        |          |10 = PCM mode A.
+ * |        |          |11 = PCM mode B.
+ * @var SPI_T::I2SCLK
+ * Offset: 0x64  I2S Clock Divider Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |MCLKDIV   |Master Clock Divider
+ * |        |          |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices.
+ * |        |          |The master clock rate, F_MCLK, is determined by the following expressions.
+ * |        |          |If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)).
+ * |        |          |If MCLKDIV = 0, F_MCLK = F_I2SCLK.
+ * |        |          |F_I2SCLK is the frequency of I2S peripheral clock.
+ * |        |          |In general, the master clock rate is 256 times sampling clock rate.
+ * |[16:8]  |BCLKDIV   |Bit Clock Divider
+ * |        |          |The I2S controller will generate bit clock in Master mode.
+ * |        |          |The bit clock rate, F_BCLK, is determined by the following expression.
+ * |        |          |F_BCLK = F_I2SCLK /(2x(BCLKDIV + 1)) , where F_I2SCLK is the frequency of I2S peripheral clock.
+ * @var SPI_T::I2SSTS
+ * Offset: 0x68  I2S Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[4]     |RIGHT     |Right Channel (Read Only)
+ * |        |          |This bit indicates the current transmit data is belong to which channel.
+ * |        |          |0 = Left channel.
+ * |        |          |1 = Right channel.
+ * |[8]     |RXEMPTY   |Receive FIFO Buffer Empty Indicator (Read Only)
+ * |        |          |0 = Receive FIFO buffer is not empty.
+ * |        |          |1 = Receive FIFO buffer is empty.
+ * |[9]     |RXFULL    |Receive FIFO Buffer Full Indicator (Read Only)
+ * |        |          |0 = Receive FIFO buffer is not full.
+ * |        |          |1 = Receive FIFO buffer is full.
+ * |[10]    |RXTHIF    |Receive FIFO Threshold Interrupt Flag (Read Only)
+ * |        |          |0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH.
+ * |        |          |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
+ * |        |          |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
+ * |[11]    |RXOVIF    |Receive FIFO Overrun Interrupt Flag
+ * |        |          |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
+ * |        |          |Note: This bit will be cleared by writing 1 to it.
+ * |[12]    |RXTOIF    |Receive Time-Out Interrupt Flag
+ * |        |          |0 = No receive FIFO time-out event.
+ * |        |          |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
+ * |        |          |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
+ * |        |          |Note: This bit will be cleared by writing 1 to it.
+ * |[15]    |I2SENSTS  |I2S Enable Status (Read Only)
+ * |        |          |0 = The SPI/I2S control logic is disabled.
+ * |        |          |1 = The SPI/I2S control logic is enabled.
+ * |        |          |Note: The SPI peripheral clock is asynchronous with the system clock.
+ * |        |          |In order to make sure the SPI/I2S controller logic is disabled, this bit indicates the real status of SPI/I2S controller logic for user.
+ * |[16]    |TXEMPTY   |Transmit FIFO Buffer Empty Indicator (Read Only)
+ * |        |          |0 = Transmit FIFO buffer is not empty.
+ * |        |          |1 = Transmit FIFO buffer is empty.
+ * |[17]    |TXFULL    |Transmit FIFO Buffer Full Indicator (Read Only)
+ * |        |          |0 = Transmit FIFO buffer is not full.
+ * |        |          |1 = Transmit FIFO buffer is full.
+ * |[18]    |TXTHIF    |Transmit FIFO Threshold Interrupt Flag (Read Only)
+ * |        |          |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
+ * |        |          |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
+ * |        |          |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request.
+ * |[19]    |TXUFIF    |Transmit FIFO Underflow Interrupt Flag
+ * |        |          |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input,
+ * |        |          | the output data depends on the setting of TXUFPOL and this bit will be set to 1.
+ * |        |          |Note: This bit will be cleared by writing 1 to it.
+ * |[20]    |RZCIF     |Right Channel Zero Cross Interrupt Flag
+ * |        |          |0 = No zero cross event occurred on right channel.
+ * |        |          |1 = Zero cross event occurred on right channel.
+ * |[21]    |LZCIF     |Left Channel Zero Cross Interrupt Flag
+ * |        |          |0 = No zero cross event occurred on left channel.
+ * |        |          |1 = Zero cross event occurred on left channel.
+ * |[23]    |TXRXRST   |TX or RX Reset Status (Read Only)
+ * |        |          |0 = The reset function of TXRST or RXRST is done.
+ * |        |          |1 = Doing the reset function of TXRST or RXRST.
+ * |        |          |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 3 peripheral clock cycles.
+ * |        |          |User can check the status of this bit to monitor the reset function is doing or done.
+ * |[26:24] |RXCNT     |Receive FIFO Data Count (Read Only)
+ * |        |          |This bit field indicates the valid data count of receive FIFO buffer.
+ * |[30:28] |TXCNT     |Transmit FIFO Data Count (Read Only)
+ * |        |          |This bit field indicates the valid data count of transmit FIFO buffer.
+ */
+
+    __IO uint32_t CTL;           /* Offset: 0x00  Control Register                                                   */
+    __IO uint32_t CLKDIV;        /* Offset: 0x04  Clock Divider Register                                             */
+    __IO uint32_t SSCTL;         /* Offset: 0x08  Slave Select Control Register                                      */
+    __IO uint32_t PDMACTL;       /* Offset: 0x0C  SPI PDMA Control Register                                          */
+    __IO uint32_t FIFOCTL;       /* Offset: 0x10  SPI FIFO Control Register                                          */
+    __IO uint32_t STATUS;        /* Offset: 0x14  SPI Status Register                                                */
+    __I  uint32_t RESERVE0[2];  
+    __O  uint32_t TX;            /* Offset: 0x20  Data Transmit Register                                             */
+    __I  uint32_t RESERVE1[3];  
+    __I  uint32_t RX;            /* Offset: 0x30  Data Receive Register                                              */
+    __I  uint32_t RESERVE2[11]; 
+    __IO uint32_t I2SCTL;        /* Offset: 0x60  I2S Control Register                                               */
+    __IO uint32_t I2SCLK;        /* Offset: 0x64  I2S Clock Divider Control Register                                 */
+    __IO uint32_t I2SSTS;        /* Offset: 0x68  I2S Status Register                                                */
+
+} SPI_T;
+
+
+
+/**
+    @addtogroup SPI_CONST SPI Bit Field Definition
+    Constant Definitions for SPI Controller
+@{ */
+
+#define SPI_CTL_SPIEN_Pos                (0)                                               /*!< SPI_T::CTL: SPIEN Position                */
+#define SPI_CTL_SPIEN_Msk                (0x1ul << SPI_CTL_SPIEN_Pos)                      /*!< SPI_T::CTL: SPIEN Mask                    */
+
+#define SPI_CTL_RXNEG_Pos                (1)                                               /*!< SPI_T::CTL: RXNEG Position                */
+#define SPI_CTL_RXNEG_Msk                (0x1ul << SPI_CTL_RXNEG_Pos)                      /*!< SPI_T::CTL: RXNEG Mask                    */
+
+#define SPI_CTL_TXNEG_Pos                (2)                                               /*!< SPI_T::CTL: TXNEG Position                */
+#define SPI_CTL_TXNEG_Msk                (0x1ul << SPI_CTL_TXNEG_Pos)                      /*!< SPI_T::CTL: TXNEG Mask                    */
+
+#define SPI_CTL_CLKPOL_Pos               (3)                                               /*!< SPI_T::CTL: CLKPOL Position               */
+#define SPI_CTL_CLKPOL_Msk               (0x1ul << SPI_CTL_CLKPOL_Pos)                     /*!< SPI_T::CTL: CLKPOL Mask                   */
+
+#define SPI_CTL_SUSPITV_Pos              (4)                                               /*!< SPI_T::CTL: SUSPITV Position              */
+#define SPI_CTL_SUSPITV_Msk              (0xful << SPI_CTL_SUSPITV_Pos)                    /*!< SPI_T::CTL: SUSPITV Mask                  */
+
+#define SPI_CTL_DWIDTH_Pos               (8)                                               /*!< SPI_T::CTL: DWIDTH Position               */
+#define SPI_CTL_DWIDTH_Msk               (0x1ful << SPI_CTL_DWIDTH_Pos)                    /*!< SPI_T::CTL: DWIDTH Mask                   */
+
+#define SPI_CTL_LSB_Pos                  (13)                                              /*!< SPI_T::CTL: LSB Position                  */
+#define SPI_CTL_LSB_Msk                  (0x1ul << SPI_CTL_LSB_Pos)                        /*!< SPI_T::CTL: LSB Mask                      */
+
+#define SPI_CTL_TWOBIT_Pos               (16)                                              /*!< SPI_T::CTL: TWOBIT Position               */
+#define SPI_CTL_TWOBIT_Msk               (0x1ul << SPI_CTL_TWOBIT_Pos)                     /*!< SPI_T::CTL: TWOBIT Mask                   */
+
+#define SPI_CTL_UNITIEN_Pos              (17)                                              /*!< SPI_T::CTL: UNITIEN Position              */
+#define SPI_CTL_UNITIEN_Msk              (0x1ul << SPI_CTL_UNITIEN_Pos)                    /*!< SPI_T::CTL: UNITIEN Mask                  */
+
+#define SPI_CTL_SLAVE_Pos                (18)                                              /*!< SPI_T::CTL: SLAVE Position                */
+#define SPI_CTL_SLAVE_Msk                (0x1ul << SPI_CTL_SLAVE_Pos)                      /*!< SPI_T::CTL: SLAVE Mask                    */
+
+#define SPI_CTL_REORDER_Pos              (19)                                              /*!< SPI_T::CTL: REORDER Position              */
+#define SPI_CTL_REORDER_Msk              (0x1ul << SPI_CTL_REORDER_Pos)                    /*!< SPI_T::CTL: REORDER Mask                  */
+
+#define SPI_CTL_QDIODIR_Pos              (20)                                              /*!< SPI_T::CTL: QDIODIR Position              */
+#define SPI_CTL_QDIODIR_Msk              (0x1ul << SPI_CTL_QDIODIR_Pos)                    /*!< SPI_T::CTL: QDIODIR Mask                  */
+
+#define SPI_CTL_DUALIOEN_Pos             (21)                                              /*!< SPI_T::CTL: DUALIOEN Position             */
+#define SPI_CTL_DUALIOEN_Msk             (0x1ul << SPI_CTL_DUALIOEN_Pos)                   /*!< SPI_T::CTL: DUALIOEN Mask                 */
+
+#define SPI_CTL_QUADIOEN_Pos             (22)                                              /*!< SPI_T::CTL: QUADIOEN Position             */
+#define SPI_CTL_QUADIOEN_Msk             (0x1ul << SPI_CTL_QUADIOEN_Pos)                   /*!< SPI_T::CTL: QUADIOEN Mask                 */
+
+#define SPI_CLKDIV_DIVIDER_Pos           (0)                                               /*!< SPI_T::CLKDIV: DIVIDER Position           */
+#define SPI_CLKDIV_DIVIDER_Msk           (0xfful << SPI_CLKDIV_DIVIDER_Pos)                /*!< SPI_T::CLKDIV: DIVIDER Mask               */
+
+#define SPI_SSCTL_SS_Pos                 (0)                                               /*!< SPI_T::SSCTL: SS Position                 */
+#define SPI_SSCTL_SS_Msk                 (0x1ul << SPI_SSCTL_SS_Pos)                       /*!< SPI_T::SSCTL: SS Mask                     */
+
+#define SPI_SSCTL_SSACTPOL_Pos           (2)                                               /*!< SPI_T::SSCTL: SSACTPOL Position           */
+#define SPI_SSCTL_SSACTPOL_Msk           (0x1ul << SPI_SSCTL_SSACTPOL_Pos)                 /*!< SPI_T::SSCTL: SSACTPOL Mask               */
+
+#define SPI_SSCTL_AUTOSS_Pos             (3)                                               /*!< SPI_T::SSCTL: AUTOSS Position             */
+#define SPI_SSCTL_AUTOSS_Msk             (0x1ul << SPI_SSCTL_AUTOSS_Pos)                   /*!< SPI_T::SSCTL: AUTOSS Mask                 */
+
+#define SPI_SSCTL_SLV3WIRE_Pos           (4)                                               /*!< SPI_T::SSCTL: SLV3WIRE Position           */
+#define SPI_SSCTL_SLV3WIRE_Msk           (0x1ul << SPI_SSCTL_SLV3WIRE_Pos)                 /*!< SPI_T::SSCTL: SLV3WIRE Mask               */
+
+#define SPI_SSCTL_SLVTOIEN_Pos           (5)                                               /*!< SPI_T::SSCTL: SLVTOIEN Position           */
+#define SPI_SSCTL_SLVTOIEN_Msk           (0x1ul << SPI_SSCTL_SLVTOIEN_Pos)                 /*!< SPI_T::SSCTL: SLVTOIEN Mask               */
+
+#define SPI_SSCTL_SLVTORST_Pos           (6)                                               /*!< SPI_T::SSCTL: SLVTORST Position           */
+#define SPI_SSCTL_SLVTORST_Msk           (0x1ul << SPI_SSCTL_SLVTORST_Pos)                 /*!< SPI_T::SSCTL: SLVTORST Mask               */
+
+#define SPI_SSCTL_SLVBEIEN_Pos           (8)                                               /*!< SPI_T::SSCTL: SLVBEIEN Position           */
+#define SPI_SSCTL_SLVBEIEN_Msk           (0x1ul << SPI_SSCTL_SLVBEIEN_Pos)                 /*!< SPI_T::SSCTL: SLVBEIEN Mask               */
+
+#define SPI_SSCTL_SLVURIEN_Pos           (9)                                               /*!< SPI_T::SSCTL: SLVURIEN Position           */
+#define SPI_SSCTL_SLVURIEN_Msk           (0x1ul << SPI_SSCTL_SLVURIEN_Pos)                 /*!< SPI_T::SSCTL: SLVURIEN Mask               */
+
+#define SPI_SSCTL_SSACTIEN_Pos           (12)                                              /*!< SPI_T::SSCTL: SSACTIEN Position           */
+#define SPI_SSCTL_SSACTIEN_Msk           (0x1ul << SPI_SSCTL_SSACTIEN_Pos)                 /*!< SPI_T::SSCTL: SSACTIEN Mask               */
+
+#define SPI_SSCTL_SSINAIEN_Pos           (13)                                              /*!< SPI_T::SSCTL: SSINAIEN Position           */
+#define SPI_SSCTL_SSINAIEN_Msk           (0x1ul << SPI_SSCTL_SSINAIEN_Pos)                 /*!< SPI_T::SSCTL: SSINAIEN Mask               */
+
+#define SPI_SSCTL_SLVTOCNT_Pos           (16)                                              /*!< SPI_T::SSCTL: SLVTOCNT Position           */
+#define SPI_SSCTL_SLVTOCNT_Msk           (0xfffful << SPI_SSCTL_SLVTOCNT_Pos)              /*!< SPI_T::SSCTL: SLVTOCNT Mask               */
+
+#define SPI_PDMACTL_TXPDMAEN_Pos         (0)                                               /*!< SPI_T::PDMACTL: TXPDMAEN Position         */
+#define SPI_PDMACTL_TXPDMAEN_Msk         (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos)               /*!< SPI_T::PDMACTL: TXPDMAEN Mask             */
+
+#define SPI_PDMACTL_RXPDMAEN_Pos         (1)                                               /*!< SPI_T::PDMACTL: RXPDMAEN Position         */
+#define SPI_PDMACTL_RXPDMAEN_Msk         (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos)               /*!< SPI_T::PDMACTL: RXPDMAEN Mask             */
+
+#define SPI_PDMACTL_PDMARST_Pos          (2)                                               /*!< SPI_T::PDMACTL: PDMARST Position          */
+#define SPI_PDMACTL_PDMARST_Msk          (0x1ul << SPI_PDMACTL_PDMARST_Pos)                /*!< SPI_T::PDMACTL: PDMARST Mask              */
+
+#define SPI_FIFOCTL_RXRST_Pos            (0)                                               /*!< SPI_T::FIFOCTL: RXRST Position            */
+#define SPI_FIFOCTL_RXRST_Msk            (0x1ul << SPI_FIFOCTL_RXRST_Pos)                  /*!< SPI_T::FIFOCTL: RXRST Mask                */
+
+#define SPI_FIFOCTL_TXRST_Pos            (1)                                               /*!< SPI_T::FIFOCTL: TXRST Position            */
+#define SPI_FIFOCTL_TXRST_Msk            (0x1ul << SPI_FIFOCTL_TXRST_Pos)                  /*!< SPI_T::FIFOCTL: TXRST Mask                */
+
+#define SPI_FIFOCTL_RXTHIEN_Pos          (2)                                               /*!< SPI_T::FIFOCTL: RXTHIEN Position          */
+#define SPI_FIFOCTL_RXTHIEN_Msk          (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos)                /*!< SPI_T::FIFOCTL: RXTHIEN Mask              */
+
+#define SPI_FIFOCTL_TXTHIEN_Pos          (3)                                               /*!< SPI_T::FIFOCTL: TXTHIEN Position          */
+#define SPI_FIFOCTL_TXTHIEN_Msk          (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos)                /*!< SPI_T::FIFOCTL: TXTHIEN Mask              */
+
+#define SPI_FIFOCTL_RXTOIEN_Pos          (4)                                               /*!< SPI_T::FIFOCTL: RXTOIEN Position          */
+#define SPI_FIFOCTL_RXTOIEN_Msk          (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos)                /*!< SPI_T::FIFOCTL: RXTOIEN Mask              */
+
+#define SPI_FIFOCTL_RXOVIEN_Pos          (5)                                               /*!< SPI_T::FIFOCTL: RXOVIEN Position          */
+#define SPI_FIFOCTL_RXOVIEN_Msk          (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos)                /*!< SPI_T::FIFOCTL: RXOVIEN Mask              */
+
+#define SPI_FIFOCTL_TXUFPOL_Pos          (6)                                               /*!< SPI_T::FIFOCTL: TXUFPOL Position          */
+#define SPI_FIFOCTL_TXUFPOL_Msk          (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos)                /*!< SPI_T::FIFOCTL: TXUFPOL Mask              */
+
+#define SPI_FIFOCTL_TXUFIEN_Pos          (7)                                               /*!< SPI_T::FIFOCTL: TXUFIEN Position          */
+#define SPI_FIFOCTL_TXUFIEN_Msk          (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos)                /*!< SPI_T::FIFOCTL: TXUFIEN Mask              */
+
+#define SPI_FIFOCTL_RXFBCLR_Pos          (8)                                               /*!< SPI_T::FIFOCTL: RXFBCLR Position          */
+#define SPI_FIFOCTL_RXFBCLR_Msk          (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos)                /*!< SPI_T::FIFOCTL: RXFBCLR Mask              */
+
+#define SPI_FIFOCTL_TXFBCLR_Pos          (9)                                               /*!< SPI_T::FIFOCTL: TXFBCLR Position          */
+#define SPI_FIFOCTL_TXFBCLR_Msk          (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos)                /*!< SPI_T::FIFOCTL: TXFBCLR Mask              */
+
+#define SPI_FIFOCTL_RXTH_Pos             (24)                                              /*!< SPI_T::FIFOCTL: RXTH Position             */
+#define SPI_FIFOCTL_RXTH_Msk             (0x7ul << SPI_FIFOCTL_RXTH_Pos)                   /*!< SPI_T::FIFOCTL: RXTH Mask                 */
+
+#define SPI_FIFOCTL_TXTH_Pos             (28)                                              /*!< SPI_T::FIFOCTL: TXTH Position             */
+#define SPI_FIFOCTL_TXTH_Msk             (0x7ul << SPI_FIFOCTL_TXTH_Pos)                   /*!< SPI_T::FIFOCTL: TXTH Mask                 */
+
+#define SPI_STATUS_BUSY_Pos              (0)                                               /*!< SPI_T::STATUS: BUSY Position              */
+#define SPI_STATUS_BUSY_Msk              (0x1ul << SPI_STATUS_BUSY_Pos)                    /*!< SPI_T::STATUS: BUSY Mask                  */
+
+#define SPI_STATUS_UNITIF_Pos            (1)                                               /*!< SPI_T::STATUS: UNITIF Position            */
+#define SPI_STATUS_UNITIF_Msk            (0x1ul << SPI_STATUS_UNITIF_Pos)                  /*!< SPI_T::STATUS: UNITIF Mask                */
+
+#define SPI_STATUS_SSACTIF_Pos           (2)                                               /*!< SPI_T::STATUS: SSACTIF Position           */
+#define SPI_STATUS_SSACTIF_Msk           (0x1ul << SPI_STATUS_SSACTIF_Pos)                 /*!< SPI_T::STATUS: SSACTIF Mask               */
+
+#define SPI_STATUS_SSINAIF_Pos           (3)                                               /*!< SPI_T::STATUS: SSINAIF Position           */
+#define SPI_STATUS_SSINAIF_Msk           (0x1ul << SPI_STATUS_SSINAIF_Pos)                 /*!< SPI_T::STATUS: SSINAIF Mask               */
+
+#define SPI_STATUS_SSLINE_Pos            (4)                                               /*!< SPI_T::STATUS: SSLINE Position            */
+#define SPI_STATUS_SSLINE_Msk            (0x1ul << SPI_STATUS_SSLINE_Pos)                  /*!< SPI_T::STATUS: SSLINE Mask                */
+
+#define SPI_STATUS_SLVTOIF_Pos           (5)                                               /*!< SPI_T::STATUS: SLVTOIF Position           */
+#define SPI_STATUS_SLVTOIF_Msk           (0x1ul << SPI_STATUS_SLVTOIF_Pos)                 /*!< SPI_T::STATUS: SLVTOIF Mask               */
+
+#define SPI_STATUS_SLVBEIF_Pos           (6)                                               /*!< SPI_T::STATUS: SLVBEIF Position           */
+#define SPI_STATUS_SLVBEIF_Msk           (0x1ul << SPI_STATUS_SLVBEIF_Pos)                 /*!< SPI_T::STATUS: SLVBEIF Mask               */
+
+#define SPI_STATUS_SLVURIF_Pos           (7)                                               /*!< SPI_T::STATUS: SLVURIF Position           */
+#define SPI_STATUS_SLVURIF_Msk           (0x1ul << SPI_STATUS_SLVURIF_Pos)                 /*!< SPI_T::STATUS: SLVURIF Mask               */
+
+#define SPI_STATUS_RXEMPTY_Pos           (8)                                               /*!< SPI_T::STATUS: RXEMPTY Position           */
+#define SPI_STATUS_RXEMPTY_Msk           (0x1ul << SPI_STATUS_RXEMPTY_Pos)                 /*!< SPI_T::STATUS: RXEMPTY Mask               */
+
+#define SPI_STATUS_RXFULL_Pos            (9)                                               /*!< SPI_T::STATUS: RXFULL Position            */
+#define SPI_STATUS_RXFULL_Msk            (0x1ul << SPI_STATUS_RXFULL_Pos)                  /*!< SPI_T::STATUS: RXFULL Mask                */
+
+#define SPI_STATUS_RXTHIF_Pos            (10)                                              /*!< SPI_T::STATUS: RXTHIF Position            */
+#define SPI_STATUS_RXTHIF_Msk            (0x1ul << SPI_STATUS_RXTHIF_Pos)                  /*!< SPI_T::STATUS: RXTHIF Mask                */
+
+#define SPI_STATUS_RXOVIF_Pos            (11)                                              /*!< SPI_T::STATUS: RXOVIF Position            */
+#define SPI_STATUS_RXOVIF_Msk            (0x1ul << SPI_STATUS_RXOVIF_Pos)                  /*!< SPI_T::STATUS: RXOVIF Mask                */
+
+#define SPI_STATUS_RXTOIF_Pos            (12)                                              /*!< SPI_T::STATUS: RXTOIF Position            */
+#define SPI_STATUS_RXTOIF_Msk            (0x1ul << SPI_STATUS_RXTOIF_Pos)                  /*!< SPI_T::STATUS: RXTOIF Mask                */
+
+#define SPI_STATUS_SPIENSTS_Pos          (15)                                              /*!< SPI_T::STATUS: SPIENSTS Position          */
+#define SPI_STATUS_SPIENSTS_Msk          (0x1ul << SPI_STATUS_SPIENSTS_Pos)                /*!< SPI_T::STATUS: SPIENSTS Mask              */
+
+#define SPI_STATUS_TXEMPTY_Pos           (16)                                              /*!< SPI_T::STATUS: TXEMPTY Position           */
+#define SPI_STATUS_TXEMPTY_Msk           (0x1ul << SPI_STATUS_TXEMPTY_Pos)                 /*!< SPI_T::STATUS: TXEMPTY Mask               */
+
+#define SPI_STATUS_TXFULL_Pos            (17)                                              /*!< SPI_T::STATUS: TXFULL Position            */
+#define SPI_STATUS_TXFULL_Msk            (0x1ul << SPI_STATUS_TXFULL_Pos)                  /*!< SPI_T::STATUS: TXFULL Mask                */
+
+#define SPI_STATUS_TXTHIF_Pos            (18)                                              /*!< SPI_T::STATUS: TXTHIF Position            */
+#define SPI_STATUS_TXTHIF_Msk            (0x1ul << SPI_STATUS_TXTHIF_Pos)                  /*!< SPI_T::STATUS: TXTHIF Mask                */
+
+#define SPI_STATUS_TXUFIF_Pos            (19)                                              /*!< SPI_T::STATUS: TXUFIF Position            */
+#define SPI_STATUS_TXUFIF_Msk            (0x1ul << SPI_STATUS_TXUFIF_Pos)                  /*!< SPI_T::STATUS: TXUFIF Mask                */
+
+#define SPI_STATUS_TXRXRST_Pos           (23)                                              /*!< SPI_T::STATUS: TXRXRST Position           */
+#define SPI_STATUS_TXRXRST_Msk           (0x1ul << SPI_STATUS_TXRXRST_Pos)                 /*!< SPI_T::STATUS: TXRXRST Mask               */
+
+#define SPI_STATUS_RXCNT_Pos             (24)                                              /*!< SPI_T::STATUS: RXCNT Position             */
+#define SPI_STATUS_RXCNT_Msk             (0xful << SPI_STATUS_RXCNT_Pos)                   /*!< SPI_T::STATUS: RXCNT Mask                 */
+
+#define SPI_STATUS_TXCNT_Pos             (28)                                              /*!< SPI_T::STATUS: TXCNT Position             */
+#define SPI_STATUS_TXCNT_Msk             (0xful << SPI_STATUS_TXCNT_Pos)                   /*!< SPI_T::STATUS: TXCNT Mask                 */
+
+#define SPI_TX_TX_Pos                    (0)                                               /*!< SPI_T::TX: TX Position                    */
+#define SPI_TX_TX_Msk                    (0xfffffffful << SPI_TX_TX_Pos)                   /*!< SPI_T::TX: TX Mask                        */
+
+#define SPI_RX_RX_Pos                    (0)                                               /*!< SPI_T::RX: RX Position                    */
+#define SPI_RX_RX_Msk                    (0xfffffffful << SPI_RX_RX_Pos)                   /*!< SPI_T::RX: RX Mask                        */
+
+#define SPI_I2SCTL_I2SEN_Pos             (0)                                               /*!< SPI_T::I2SCTL: I2SEN Position             */
+#define SPI_I2SCTL_I2SEN_Msk             (0x1ul << SPI_I2SCTL_I2SEN_Pos)                   /*!< SPI_T::I2SCTL: I2SEN Mask                 */
+
+#define SPI_I2SCTL_TXEN_Pos              (1)                                               /*!< SPI_T::I2SCTL: TXEN Position              */
+#define SPI_I2SCTL_TXEN_Msk              (0x1ul << SPI_I2SCTL_TXEN_Pos)                    /*!< SPI_T::I2SCTL: TXEN Mask                  */
+
+#define SPI_I2SCTL_RXEN_Pos              (2)                                               /*!< SPI_T::I2SCTL: RXEN Position              */
+#define SPI_I2SCTL_RXEN_Msk              (0x1ul << SPI_I2SCTL_RXEN_Pos)                    /*!< SPI_T::I2SCTL: RXEN Mask                  */
+
+#define SPI_I2SCTL_MUTE_Pos              (3)                                               /*!< SPI_T::I2SCTL: MUTE Position              */
+#define SPI_I2SCTL_MUTE_Msk              (0x1ul << SPI_I2SCTL_MUTE_Pos)                    /*!< SPI_T::I2SCTL: MUTE Mask                  */
+
+#define SPI_I2SCTL_WDWIDTH_Pos           (4)                                               /*!< SPI_T::I2SCTL: WDWIDTH Position           */
+#define SPI_I2SCTL_WDWIDTH_Msk           (0x3ul << SPI_I2SCTL_WDWIDTH_Pos)                 /*!< SPI_T::I2SCTL: WDWIDTH Mask               */
+
+#define SPI_I2SCTL_MONO_Pos              (6)                                               /*!< SPI_T::I2SCTL: MONO Position              */
+#define SPI_I2SCTL_MONO_Msk              (0x1ul << SPI_I2SCTL_MONO_Pos)                    /*!< SPI_T::I2SCTL: MONO Mask                  */
+
+#define SPI_I2SCTL_ORDER_Pos             (7)                                               /*!< SPI_T::I2SCTL: ORDER Position             */
+#define SPI_I2SCTL_ORDER_Msk             (0x1ul << SPI_I2SCTL_ORDER_Pos)                   /*!< SPI_T::I2SCTL: ORDER Mask                 */
+
+#define SPI_I2SCTL_SLAVE_Pos             (8)                                               /*!< SPI_T::I2SCTL: SLAVE Position             */
+#define SPI_I2SCTL_SLAVE_Msk             (0x1ul << SPI_I2SCTL_SLAVE_Pos)                   /*!< SPI_T::I2SCTL: SLAVE Mask                 */
+
+#define SPI_I2SCTL_MCLKEN_Pos            (15)                                              /*!< SPI_T::I2SCTL: MCLKEN Position            */
+#define SPI_I2SCTL_MCLKEN_Msk            (0x1ul << SPI_I2SCTL_MCLKEN_Pos)                  /*!< SPI_T::I2SCTL: MCLKEN Mask                */
+
+#define SPI_I2SCTL_RZCEN_Pos             (16)                                              /*!< SPI_T::I2SCTL: RZCEN Position             */
+#define SPI_I2SCTL_RZCEN_Msk             (0x1ul << SPI_I2SCTL_RZCEN_Pos)                   /*!< SPI_T::I2SCTL: RZCEN Mask                 */
+
+#define SPI_I2SCTL_LZCEN_Pos             (17)                                              /*!< SPI_T::I2SCTL: LZCEN Position             */
+#define SPI_I2SCTL_LZCEN_Msk             (0x1ul << SPI_I2SCTL_LZCEN_Pos)                   /*!< SPI_T::I2SCTL: LZCEN Mask                 */
+
+#define SPI_I2SCTL_RXLCH_Pos             (23)                                              /*!< SPI_T::I2SCTL: RXLCH Position             */
+#define SPI_I2SCTL_RXLCH_Msk             (0x1ul << SPI_I2SCTL_RXLCH_Pos)                   /*!< SPI_T::I2SCTL: RXLCH Mask                 */
+
+#define SPI_I2SCTL_RZCIEN_Pos            (24)                                              /*!< SPI_T::I2SCTL: RZCIEN Position            */
+#define SPI_I2SCTL_RZCIEN_Msk            (0x1ul << SPI_I2SCTL_RZCIEN_Pos)                  /*!< SPI_T::I2SCTL: RZCIEN Mask                */
+
+#define SPI_I2SCTL_LZCIEN_Pos            (25)                                              /*!< SPI_T::I2SCTL: LZCIEN Position            */
+#define SPI_I2SCTL_LZCIEN_Msk            (0x1ul << SPI_I2SCTL_LZCIEN_Pos)                  /*!< SPI_T::I2SCTL: LZCIEN Mask                */
+
+#define SPI_I2SCTL_FORMAT_Pos            (28)                                              /*!< SPI_T::I2SCTL: FORMAT Position            */
+#define SPI_I2SCTL_FORMAT_Msk            (0x3ul << SPI_I2SCTL_FORMAT_Pos)                  /*!< SPI_T::I2SCTL: FORMAT Mask                */
+
+#define SPI_I2SCLK_MCLKDIV_Pos           (0)                                               /*!< SPI_T::I2SCLK: MCLKDIV Position           */
+#define SPI_I2SCLK_MCLKDIV_Msk           (0x3ful << SPI_I2SCLK_MCLKDIV_Pos)                /*!< SPI_T::I2SCLK: MCLKDIV Mask               */
+
+#define SPI_I2SCLK_BCLKDIV_Pos           (8)                                               /*!< SPI_T::I2SCLK: BCLKDIV Position           */
+#define SPI_I2SCLK_BCLKDIV_Msk           (0x1fful << SPI_I2SCLK_BCLKDIV_Pos)               /*!< SPI_T::I2SCLK: BCLKDIV Mask               */
+
+#define SPI_I2SSTS_RIGHT_Pos             (4)                                               /*!< SPI_T::I2SSTS: RIGHT Position             */
+#define SPI_I2SSTS_RIGHT_Msk             (0x1ul << SPI_I2SSTS_RIGHT_Pos)                   /*!< SPI_T::I2SSTS: RIGHT Mask                 */
+
+#define SPI_I2SSTS_RXEMPTY_Pos           (8)                                               /*!< SPI_T::I2SSTS: RXEMPTY Position           */
+#define SPI_I2SSTS_RXEMPTY_Msk           (0x1ul << SPI_I2SSTS_RXEMPTY_Pos)                 /*!< SPI_T::I2SSTS: RXEMPTY Mask               */
+
+#define SPI_I2SSTS_RXFULL_Pos            (9)                                               /*!< SPI_T::I2SSTS: RXFULL Position            */
+#define SPI_I2SSTS_RXFULL_Msk            (0x1ul << SPI_I2SSTS_RXFULL_Pos)                  /*!< SPI_T::I2SSTS: RXFULL Mask                */
+
+#define SPI_I2SSTS_RXTHIF_Pos            (10)                                              /*!< SPI_T::I2SSTS: RXTHIF Position            */
+#define SPI_I2SSTS_RXTHIF_Msk            (0x1ul << SPI_I2SSTS_RXTHIF_Pos)                  /*!< SPI_T::I2SSTS: RXTHIF Mask                */
+
+#define SPI_I2SSTS_RXOVIF_Pos            (11)                                              /*!< SPI_T::I2SSTS: RXOVIF Position            */
+#define SPI_I2SSTS_RXOVIF_Msk            (0x1ul << SPI_I2SSTS_RXOVIF_Pos)                  /*!< SPI_T::I2SSTS: RXOVIF Mask                */
+
+#define SPI_I2SSTS_RXTOIF_Pos            (12)                                              /*!< SPI_T::I2SSTS: RXTOIF Position            */
+#define SPI_I2SSTS_RXTOIF_Msk            (0x1ul << SPI_I2SSTS_RXTOIF_Pos)                  /*!< SPI_T::I2SSTS: RXTOIF Mask                */
+
+#define SPI_I2SSTS_I2SENSTS_Pos          (15)                                              /*!< SPI_T::I2SSTS: I2SENSTS Position          */
+#define SPI_I2SSTS_I2SENSTS_Msk          (0x1ul << SPI_I2SSTS_I2SENSTS_Pos)                /*!< SPI_T::I2SSTS: I2SENSTS Mask              */
+
+#define SPI_I2SSTS_TXEMPTY_Pos           (16)                                              /*!< SPI_T::I2SSTS: TXEMPTY Position           */
+#define SPI_I2SSTS_TXEMPTY_Msk           (0x1ul << SPI_I2SSTS_TXEMPTY_Pos)                 /*!< SPI_T::I2SSTS: TXEMPTY Mask               */
+
+#define SPI_I2SSTS_TXFULL_Pos            (17)                                              /*!< SPI_T::I2SSTS: TXFULL Position            */
+#define SPI_I2SSTS_TXFULL_Msk            (0x1ul << SPI_I2SSTS_TXFULL_Pos)                  /*!< SPI_T::I2SSTS: TXFULL Mask                */
+
+#define SPI_I2SSTS_TXTHIF_Pos            (18)                                              /*!< SPI_T::I2SSTS: TXTHIF Position            */
+#define SPI_I2SSTS_TXTHIF_Msk            (0x1ul << SPI_I2SSTS_TXTHIF_Pos)                  /*!< SPI_T::I2SSTS: TXTHIF Mask                */
+
+#define SPI_I2SSTS_TXUFIF_Pos            (19)                                              /*!< SPI_T::I2SSTS: TXUFIF Position            */
+#define SPI_I2SSTS_TXUFIF_Msk            (0x1ul << SPI_I2SSTS_TXUFIF_Pos)                  /*!< SPI_T::I2SSTS: TXUFIF Mask                */
+
+#define SPI_I2SSTS_RZCIF_Pos             (20)                                              /*!< SPI_T::I2SSTS: RZCIF Position             */
+#define SPI_I2SSTS_RZCIF_Msk             (0x1ul << SPI_I2SSTS_RZCIF_Pos)                   /*!< SPI_T::I2SSTS: RZCIF Mask                 */
+
+#define SPI_I2SSTS_LZCIF_Pos             (21)                                              /*!< SPI_T::I2SSTS: LZCIF Position             */
+#define SPI_I2SSTS_LZCIF_Msk             (0x1ul << SPI_I2SSTS_LZCIF_Pos)                   /*!< SPI_T::I2SSTS: LZCIF Mask                 */
+
+#define SPI_I2SSTS_TXRXRST_Pos           (23)                                              /*!< SPI_T::I2SSTS: TXRXRST Position           */
+#define SPI_I2SSTS_TXRXRST_Msk           (0x1ul << SPI_I2SSTS_TXRXRST_Pos)                 /*!< SPI_T::I2SSTS: TXRXRST Mask               */
+
+#define SPI_I2SSTS_RXCNT_Pos             (24)                                              /*!< SPI_T::I2SSTS: RXCNT Position             */
+#define SPI_I2SSTS_RXCNT_Msk             (0x7ul << SPI_I2SSTS_RXCNT_Pos)                   /*!< SPI_T::I2SSTS: RXCNT Mask                 */
+
+#define SPI_I2SSTS_TXCNT_Pos             (28)                                              /*!< SPI_T::I2SSTS: TXCNT Position             */
+#define SPI_I2SSTS_TXCNT_Msk             (0x7ul << SPI_I2SSTS_TXCNT_Pos)                   /*!< SPI_T::I2SSTS: TXCNT Mask                 */
+
+/**@}*/ /* SPI_CONST */
+/**@}*/ /* end of SPI register group */
+
+
+/*---------------------- System Manger Controller -------------------------*/
+/**
+    @addtogroup SYS System Manger Controller(SYS)
+    Memory Mapped Structure for SYS Controller
+@{ */
+
+
+typedef struct
+{
+
+/**
+ * @var SYS_T::PDID
+ * Offset: 0x00  Part Device Identification Number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |PDID      |Part Device Identification Number (Read Only)
+ * |        |          |This register reflects device part number code.
+ * |        |          |Software can read this register to identify which device is used.
+ * @var SYS_T::RSTSTS
+ * Offset: 0x04  System Reset Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |PORF      |POR Reset Flag
+ * |        |          |The POR reset flag is set by the "Reset Signal" from the Power-On Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
+ * |        |          |0 = No reset from POR or CHIPRST.
+ * |        |          |1 = Power-On Reset (POR) or CHIPRST had issued the reset signal to reset the system.
+ * |        |          |Note: Write 1 to clear this bit to 0.
+ * |[1]     |PINRF     |nRESET Pin Reset Flag
+ * |        |          |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.
+ * |        |          |0 = No reset from nRESET pin.
+ * |        |          |1 = Pin nRESET had issued the reset signal to reset the system.
+ * |        |          |Note: Write 1 to clear this bit to 0.
+ * |[2]     |WDTRF     |WDT Reset Flag
+ * |        |          |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
+ * |        |          |0 = No reset from watchdog timer or window watchdog timer.
+ * |        |          |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.
+ * |        |          |Note1:
+ * |        |          |Write 1 to clear this bit to 0.
+ * |        |          |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset.
+ * |        |          |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
+ * |[3]     |LVRF      |LVR Reset Flag
+ * |        |          |The LVR reset flag is set by the "Reset Signal" from the Low-Voltage-Reset Controller to indicate the previous reset source.
+ * |        |          |0 = No reset from LVR.
+ * |        |          |1 = LVR controller had issued the reset signal to reset the system.
+ * |        |          |Note: Write 1 to clear this bit to 0.
+ * |[4]     |BODRF     |BOD Reset Flag
+ * |        |          |The BOD reset flag is set by the "Reset Signal" from the Brown-Out-Detector to indicate the previous reset source.
+ * |        |          |0 = No reset from BOD.
+ * |        |          |1 = The BOD had issued the reset signal to reset the system.
+ * |        |          |Note: Write 1 to clear this bit to 0.
+ * |[5]     |SYSRF     |System Reset Flag
+ * |        |          |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source.
+ * |        |          |0 = No reset from Cortex-M4.
+ * |        |          |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core.
+ * |        |          |Note: Write 1 to clear this bit to 0.
+ * |[7]     |CPURF     |CPU Reset Flag
+ * |        |          |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).
+ * |        |          |0 = No reset from CPU.
+ * |        |          |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1.
+ * |        |          |Note: Write 1 to clear this bit to 0.
+ * |[8]     |CPULKRF   |CPU Lockup Reset Flag
+ * |        |          |The CPU reset flag is set by hardware if Cortex-M4 lockup happened.
+ * |        |          |0 = No reset from CPU lockup happened.
+ * |        |          |1 = The Cortex-M4 lockup happened and chip is reset.
+ * |        |          |Note: Write 1 to clear this bit to 0.
+ * @var SYS_T::IPRST0
+ * Offset: 0x08  Peripheral  Reset Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |CHIPRST   |Chip One-Shot Reset (Write Protect)
+ * |        |          |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
+ * |        |          |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
+ * |        |          |About the difference between CHIPRST and SYSRESETREQ, please refer to section 5.2.2
+ * |        |          |0 = Chip normal operation.
+ * |        |          |1 = Chip one shot reset.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1]     |CPURST    |Processor Core One-Shot Reset (Write Protect)
+ * |        |          |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
+ * |        |          |0 = Processor core normal operation.
+ * |        |          |1 = Processor core one-shot reset.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2]     |PDMARST   |PDMA Controller Reset (Write Protect)
+ * |        |          |Setting this bit to 1 will generate a reset signal to the PDMA.
+ * |        |          |User needs to set this bit to 0 to release from reset state.
+ * |        |          |0 = PDMA controller normal operation.
+ * |        |          |1 = PDMA controller reset.
+ * |[3]     |EBIRST    |EBI Controller Reset (Write Protect)
+ * |        |          |Set this bit to 1 will generate a reset signal to the EBI.
+ * |        |          |User needs to set this bit to 0 to release from the reset state.
+ * |        |          |0 = EBI controller normal operation.
+ * |        |          |1 = EBI controller reset.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4]     |USBHRST   |USBH Controller Reset (Write Protect)
+ * |        |          |Set this bit to 1 will generate a reset signal to the USB host controller.
+ * |        |          |User needs to set this bit to 0 to release from the reset state.
+ * |        |          |0 = USBH controller normal operation.
+ * |        |          |1 = USBH controller reset.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7]     |CRCRST    |CRC Calculation Unit Reset (Write Protect)
+ * |        |          |Set this bit to 1 will generate a reset signal to the CRC calculation module.
+ * |        |          |User needs to set this bit to 0 to release from the reset state.
+ * |        |          |0 = CRC Calculation unit normal operation.
+ * |        |          |1 = CRC Calculation unit reset.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::IPRST1
+ * Offset: 0x0C  Peripheral Reset Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1]     |GPIORST   |GPIO Controller Reset
+ * |        |          |0 = GPIO controller normal operation.
+ * |        |          |1 = GPIO controller reset.
+ * |[2]     |TMR0RST   |Timer0 Controller Reset
+ * |        |          |0 = Timer0 controller normal operation.
+ * |        |          |1 = Timer0 controller reset.
+ * |[3]     |TMR1RST   |Timer1 Controller Reset
+ * |        |          |0 = Timer1 controller normal operation.
+ * |        |          |1 = Timer1 controller reset.
+ * |[4]     |TMR2RST   |Timer2 Controller Reset
+ * |        |          |0 = Timer2 controller normal operation.
+ * |        |          |1 = Timer2 controller reset.
+ * |[5]     |TMR3RST   |Timer3 Controller Reset
+ * |        |          |0 = Timer3 controller normal operation.
+ * |        |          |1 = Timer3 controller reset.
+ * |[7]     |ACMP01RST |Analog Comparator 0/1 Controller Reset
+ * |        |          |0 = Analog Comparator 0/1 controller normal operation.
+ * |        |          |1 = Analog Comparator 0/1 controller reset.
+ * |[8]     |I2C0RST   |I2C0 Controller Reset
+ * |        |          |0 = I2C0 controller normal operation.
+ * |        |          |1 = I2C0 controller reset.
+ * |[9]     |I2C1RST   |I2C1 Controller Reset
+ * |        |          |0 = I2C1 controller normal operation.
+ * |        |          |1 = I2C1 controller reset.
+ * |[12]    |SPI0RST   |SPI0 Controller Reset
+ * |        |          |0 = SPI0 controller normal operation.
+ * |        |          |1 = SPI0 controller reset.
+ * |[13]    |SPI1RST   |SPI1 Controller Reset
+ * |        |          |0 = SPI1 controller normal operation.
+ * |        |          |1 = SPI1 controller reset.
+ * |[14]    |SPI2RST   |SPI2 Controller Reset
+ * |        |          |0 = SPI2 controller normal operation.
+ * |        |          |1 = SPI2 controller reset.
+ * |[16]    |UART0RST  |UART0 Controller Reset
+ * |        |          |0 = UART0 controller normal operation.
+ * |        |          |1 = UART0 controller reset.
+ * |[17]    |UART1RST  |UART1 Controller Reset
+ * |        |          |0 = UART1 controller normal operation.
+ * |        |          |1 = UART1 controller reset.
+ * |[18]    |UART2RST  |UART2 Controller Reset
+ * |        |          |0 = UART2 controller normal operation.
+ * |        |          |1 = UART2 controller reset.
+ * |[19]    |UART3RST  |UART3 Controller Reset
+ * |        |          |0 = UART3 controller normal operation.
+ * |        |          |1 = UART3 controller reset.
+ * |[24]    |CAN0RST   |CAN0 Controller Reset
+ * |        |          |0 = CAN0 controller normal operation.
+ * |        |          |1 = CAN0 controller reset.
+ * |[26]    |OTGRST    |OTG Controller Reset
+ * |        |          |0 = OTG controller normal operation.
+ * |        |          |1 = OTG controller reset.
+ * |[27]    |USBDRST   |USB Device Controller Reset
+ * |        |          |0 = USB device controller normal operation.
+ * |        |          |1 = USB device controller reset.
+ * |[28]    |EADCRST   |EADC Controller Reset
+ * |        |          |0 = EADC controller normal operation.
+ * |        |          |1 = EADC controller reset.
+ * @var SYS_T::IPRST2
+ * Offset: 0x10  Peripheral Reset Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SC0RST    |SC0 Controller Reset
+ * |        |          |0 = SC0 controller normal operation.
+ * |        |          |1 = SC0 controller reset.
+ * |[12]    |DACRST    |DAC Controller Reset
+ * |        |          |0 = DAC controller normal operation.
+ * |        |          |1 = DAC controller reset.
+ * |[16]    |PWM0RST   |PWM0 Controller Reset
+ * |        |          |0 = PWM0 controller normal operation.
+ * |        |          |1 = PWM0 controller reset.
+ * |[17]    |PWM1RST   |PWM1 Controller Reset
+ * |        |          |0 = PWM1 controller normal operation.
+ * |        |          |1 = PWM1 controller reset.
+ * |[25]    |TKRST     |Touch Key Controller Reset
+ * |        |          |0 = Touch Key controller normal operation.
+ * |        |          |1 = Touch Key controller reset.
+ * @var SYS_T::BODCTL
+ * Offset: 0x18  Brown-Out Detector Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |BODEN     |Brown-Out Detector Enable Bit (Write Protect)
+ * |        |          |The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).
+ * |        |          |0 = Brown-out Detector function Disabled.
+ * |        |          |1 = Brown-out Detector function Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2:1]   |BODVL     |Brown-Out Detector Threshold Voltage Selection (Write Protect)
+ * |        |          |The default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).
+ * |        |          |00 = Brown-Out Detector Threshold Voltage is 2.2V
+ * |        |          |01 = Brown-Out Detector Threshold Voltage is 2.7V
+ * |        |          |10 = Brown-Out Detector Threshold Voltage is 3.7V
+ * |        |          |11 = Brown-Out Detector Threshold Voltage is 4.5V
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3]     |BODRSTEN  |Brown-Out Reset Enable Bit (Write Protect)
+ * |        |          |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .
+ * |        |          |0 = Brown-out "INTERRUPT" function Enabled.
+ * |        |          |1 = Brown-out "RESET" function Enabled.
+ * |        |          |Note1:
+ * |        |          |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
+ * |        |          |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high.
+ * |        |          |BOD interrupt will keep till to the BODEN set to 0.
+ * |        |          |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
+ * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4]     |BODIF     |Brown-Out Detector Interrupt Flag
+ * |        |          |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
+ * |        |          |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
+ * |        |          |Note: Write 1 to clear this bit to 0.
+ * |[5]     |BODLPM    |Brown-Out Detector Low Power Mode (Write Protect)
+ * |        |          |0 = BOD operate in normal mode (default).
+ * |        |          |1 = BOD Low Power mode Enabled.
+ * |        |          |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
+ * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6]     |BODOUT    |Brown-Out Detector Output Status
+ * |        |          |0 = Brown-out Detector output status is 0.
+ * |        |          |It means the detected voltage is higher than BODVL setting or BODEN is 0.
+ * |        |          |1 = Brown-out Detector output status is 1.
+ * |        |          |It means the detected voltage is lower than BODVL setting.
+ * |        |          |If the BODEN is 0, BOD function disabled , this bit always responds 0000.
+ * |[7]     |LVREN     |Low Voltage Reset Enable Bit (Write Protect)
+ * |        |          |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting.
+ * |        |          |LVR function is enabled by default.
+ * |        |          |0 = Low Voltage Reset function Disabled.
+ * |        |          |1 = Low Voltage Reset function Enabled
+ * |        |          |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).
+ * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[10:8]  |BODDGSEL  |Brown-Out Detector Output De-Glitch Time Select (Write Protect)
+ * |        |          |000 = BOD output is sampled by RC10K clock.
+ * |        |          |001 = 4 system clock (HCLK).
+ * |        |          |010 = 8 system clock (HCLK).
+ * |        |          |011 = 16 system clock (HCLK).
+ * |        |          |100 = 32 system clock (HCLK).
+ * |        |          |101 = 64 system clock (HCLK).
+ * |        |          |110 = 128 system clock (HCLK).
+ * |        |          |111 = 256 system clock (HCLK).
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[14:12] |LVRDGSEL  |LVR Output De-Glitch Time Select (Write Protect)
+ * |        |          |000 = Without de-glitch function.
+ * |        |          |001 = 4 system clock (HCLK).
+ * |        |          |010 = 8 system clock (HCLK).
+ * |        |          |011 = 16 system clock (HCLK).
+ * |        |          |100 = 32 system clock (HCLK).
+ * |        |          |101 = 64 system clock (HCLK).
+ * |        |          |110 = 128 system clock (HCLK).
+ * |        |          |111 = 256 system clock (HCLK).
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::IVSCTL
+ * Offset: 0x1C  Internal Voltage Source Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |VTEMPEN   |Temperature Sensor Enable Bit
+ * |        |          |This bit is used to enable/disable temperature sensor function.
+ * |        |          |0 = Temperature sensor function Disabled (default).
+ * |        |          |1 = Temperature sensor function Enabled.
+ * |        |          |Note: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result.
+ * |        |          |Please refer to ADC function chapter for details.
+ * |[1]     |VBATUGEN  |VBAT Unity Gain Buffer Enable Bit
+ * |        |          |This bit is used to enable/disable VBAT unity gain buffer function.
+ * |        |          |0 = VBAT unity gain buffer function Disabled (default).
+ * |        |          |1 = VBAT unity gain buffer function Enabled.
+ * |        |          |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result
+ * @var SYS_T::PORCTL
+ * Offset: 0x24  Power-On-Reset Controller Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |POROFF    |Power-On-Reset Enable Bit (Write Protect)
+ * |        |          |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
+ * |        |          |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
+ * |        |          |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
+ * |        |          |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::VREFCTL
+ * Offset: 0x28  VREF Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[4:0]   |VREFCTL   |VREF Control Bits (Write Protect)
+ * |        |          |00011 = VREF is internal 2.65V.
+ * |        |          |00111 = VREF is internal 2.048V.
+ * |        |          |01011 = VREF is internal 3.072V.
+ * |        |          |01111 = VREF is internal 4.096V.
+ * |        |          |Others = Reserved.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::USBPHY
+ * Offset: 0x2C  USB PHY Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |USBROLE   |USB Role Option (Write Protect)
+ * |        |          |These two bits are used to select the role of USB.
+ * |        |          |00 = Standard USB Device mode.
+ * |        |          |01 = Standard USB Host mode.
+ * |        |          |10 = ID dependent mode.
+ * |        |          |11 = On-The-Go device mode.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[8]     |LDO33EN   |USB LDO33 Enable Bit (Write Protect)
+ * |        |          |0 = USB LDO33 Disabled.
+ * |        |          |1 = USB LDO33 Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::GPA_MFPL
+ * Offset: 0x30  GPIOA Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |PA0MFP    |PA.0 Multi-function Pin Selection
+ * |[7:4]   |PA1MFP    |PA.1 Multi-function Pin Selection
+ * |[11:8]  |PA2MFP    |PA.2 Multi-function Pin Selection
+ * |[15:12] |PA3MFP    |PA.3 Multi-function Pin Selection
+ * |[19:16] |PA4MFP    |PA.4 Multi-function Pin Selection
+ * |[23:20] |PA5MFP    |PA.5 Multi-function Pin Selection
+ * |[27:24] |PA6MFP    |PA.6 Multi-function Pin Selection
+ * |[31:28] |PA7MFP    |PA.7 Multi-function Pin Selection
+ * @var SYS_T::GPA_MFPH
+ * Offset: 0x34  GPIOA High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |PA8MFP    |PA.8 Multi-function Pin Selection
+ * |[7:4]   |PA9MFP    |PA.9 Multi-function Pin Selection
+ * |[11:8]  |PA10MFP   |PA.10 Multi-function Pin Selection
+ * |[15:12] |PA11MFP   |PA.11 Multi-function Pin Selection
+ * |[19:16] |PA12MFP   |PA.12 Multi-function Pin Selection
+ * |[23:20] |PA13MFP   |PA.13 Multi-function Pin Selection
+ * |[27:24] |PA14MFP   |PA.14 Multi-function Pin Selection
+ * |[31:28] |PA15MFP   |PA.15 Multi-function Pin Selection
+ * @var SYS_T::GPB_MFPL
+ * Offset: 0x38  GPIOB Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |PB0MFP    |PB.0 Multi-function Pin Selection
+ * |[7:4]   |PB1MFP    |PB.1 Multi-function Pin Selection
+ * |[11:8]  |PB2MFP    |PB.2 Multi-function Pin Selection
+ * |[15:12] |PB3MFP    |PB.3 Multi-function Pin Selection
+ * |[19:16] |PB4MFP    |PB.4 Multi-function Pin Selection
+ * |[23:20] |PB5MFP    |PB.5 Multi-function Pin Selection
+ * |[27:24] |PB6MFP    |PB.6 Multi-function Pin Selection
+ * |[31:28] |PB7MFP    |PB.7 Multi-function Pin Selection
+ * @var SYS_T::GPB_MFPH
+ * Offset: 0x3C  GPIOB High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |PB8MFP    |PB.8 Multi-function Pin Selection
+ * |[7:4]   |PB9MFP    |PB.9 Multi-function Pin Selection
+ * |[11:8]  |PB10MFP   |PB.10 Multi-function Pin Selection
+ * |[15:12] |PB11MFP   |PB.11 Multi-function Pin Selection
+ * |[19:16] |PB12MFP   |PB.12 Multi-function Pin Selection
+ * |[23:20] |PB13MFP   |PB.13 Multi-function Pin Selection
+ * |[27:24] |PB14MFP   |PB.14 Multi-function Pin Selection
+ * |[31:28] |PB15MFP   |PB.15 Multi-function Pin Selection
+ * @var SYS_T::GPC_MFPL
+ * Offset: 0x40  GPIOC Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |PC0MFP    |PC.0 Multi-function Pin Selection
+ * |[7:4]   |PC1MFP    |PC.1 Multi-function Pin Selection
+ * |[11:8]  |PC2MFP    |PC.2 Multi-function Pin Selection
+ * |[15:12] |PC3MFP    |PC.3 Multi-function Pin Selection
+ * |[19:16] |PC4MFP    |PC.4 Multi-function Pin Selection
+ * |[23:20] |PC5MFP    |PC.5 Multi-function Pin Selection
+ * |[27:24] |PC6MFP    |PC.6 Multi-function Pin Selection
+ * |[31:28] |PC7MFP    |PC.7 Multi-function Pin Selection
+ * @var SYS_T::GPC_MFPH
+ * Offset: 0x44  GPIOC High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |PC8MFP    |PC.8 Multi-function Pin Selection
+ * |[7:4]   |PC9MFP    |PC.9 Multi-function Pin Selection
+ * |[11:8]  |PC10MFP   |PC.10 Multi-function Pin Selection
+ * |[15:12] |PC11MFP   |PC.11 Multi-function Pin Selection
+ * |[19:16] |PC12MFP   |PC.12 Multi-function Pin Selection
+ * |[23:20] |PC13MFP   |PC.13 Multi-function Pin Selection
+ * |[27:24] |PC14MFP   |PC.14 Multi-function Pin Selection
+ * |[31:28] |PC15MFP   |PC.15 Multi-function Pin Selection
+ * @var SYS_T::GPD_MFPL
+ * Offset: 0x48  GPIOD Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |PD0MFP    |PD.0 Multi-function Pin Selection
+ * |[7:4]   |PD1MFP    |PD.1 Multi-function Pin Selection
+ * |[11:8]  |PD2MFP    |PD.2 Multi-function Pin Selection
+ * |[15:12] |PD3MFP    |PD.3 Multi-function Pin Selection
+ * |[19:16] |PD4MFP    |PD.4 Multi-function Pin Selection
+ * |[23:20] |PD5MFP    |PD.5 Multi-function Pin Selection
+ * |[27:24] |PD6MFP    |PD.6 Multi-function Pin Selection
+ * |[31:28] |PD7MFP    |PD.7 Multi-function Pin Selection
+ * @var SYS_T::GPD_MFPH
+ * Offset: 0x4C  GPIOD High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |PD8MFP    |PD.8 Multi-function Pin Selection
+ * |[7:4]   |PD9MFP    |PD.9 Multi-function Pin Selection
+ * |[11:8]  |PD10MFP   |PD.10 Multi-function Pin Selection
+ * |[15:12] |PD11MFP   |PD.11 Multi-function Pin Selection
+ * |[19:16] |PD12MFP   |PD.12 Multi-function Pin Selection
+ * |[23:20] |PD13MFP   |PD.13 Multi-function Pin Selection
+ * |[27:24] |PD14MFP   |PD.14 Multi-function Pin Selection
+ * |[31:28] |PD15MFP   |PD.15 Multi-function Pin Selection
+ * @var SYS_T::GPE_MFPL
+ * Offset: 0x50  GPIOE Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |PE0MFP    |PE.0 Multi-function Pin Selection
+ * |[7:4]   |PE1MFP    |PE.1 Multi-function Pin Selection
+ * |[11:8]  |PE2MFP    |PE.2 Multi-function Pin Selection
+ * |[15:12] |PE3MFP    |PE.3 Multi-function Pin Selection
+ * |[19:16] |PE4MFP    |PE.4 Multi-function Pin Selection
+ * |[23:20] |PE5MFP    |PE.5 Multi-function Pin Selection
+ * |[27:24] |PE6MFP    |PE.6 Multi-function Pin Selection
+ * |[31:28] |PE7MFP    |PE.7 Multi-function Pin Selection
+ * @var SYS_T::GPE_MFPH
+ * Offset: 0x54  GPIOE High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |PE8MFP    |PE.8 Multi-function Pin Selection
+ * |[7:4]   |PE9MFP    |PE.9 Multi-function Pin Selection
+ * |[11:8]  |PE10MFP   |PE.10 Multi-function Pin Selection
+ * |[15:12] |PE11MFP   |PE.11 Multi-function Pin Selection
+ * |[19:16] |PE12MFP   |PE.12 Multi-function Pin Selection
+ * |[23:20] |PE13MFP   |PE.13 Multi-function Pin Selection
+ * |[27:24] |PE14_MFP  |PE.14 Multi-function Pin Selection
+ * @var SYS_T::GPF_MFPL
+ * Offset: 0x58  GPIOF Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |PF0MFP    |PF.0 Multi-function Pin Selection
+ * |[7:4]   |PF1MFP    |PF.1 Multi-function Pin Selection
+ * |[11:8]  |PF2MFP    |PF.2 Multi-function Pin Selection
+ * |[15:12] |PF3MFP    |PF.3 Multi-function Pin Selection
+ * |[19:16] |PF4MFP    |PF.4 Multi-function Pin Selection
+ * |[23:20] |PF5MFP    |PF.5 Multi-function Pin Selection
+ * |[27:24] |PF6MFP    |PF.6 Multi-function Pin Selection
+ * |[31:28] |PF7MFP    |PF.7 Multi-function Pin Selection
+ * @var SYS_T::SRAM_INTCTL
+ * Offset: 0xC0  System SRAM Interrupt Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |PERRIEN   |SRAM Parity Check Error Interrupt Enable Bit
+ * |        |          |0 = SRAM parity check error interrupt Disabled.
+ * |        |          |1 = SRAM parity check error interrupt Enabled.
+ * @var SYS_T::SRAM_STATUS
+ * Offset: 0xC4  System SRAM Parity Error Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |PERRIF    |SRAM Parity Check Error Flag
+ * |        |          |0 = No System SRAM parity error.
+ * |        |          |1 = System SRAM parity error occur.
+ * @var SYS_T::SRAM_ERRADDR
+ * Offset: 0xC8  System SRAM Parity Check Error Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |ERRADDR   |System SRAM Parity Error Address
+ * |        |          |This register shows system SRAM parity error byte address.
+ * @var SYS_T::SRAM_BISTCTL
+ * Offset: 0xD0  System SRAM BIST Test Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SRBIST0   |1st
+ * |        |          |SRAM BIST Enable Bit
+ * |        |          |This bit enables BIST test for SRAM located in address 0x2000_0000 ~0x2000_3FFF
+ * |        |          |0 = system SRAM BIST Disabled.
+ * |        |          |1 = system SRAM BIST Enabled.
+ * |[1]     |SRBIST1   |2nd
+ * |        |          |SRAM BIST Enable Bit
+ * |        |          |This bit enables BIST test for SRAM located in address 0x2000_4000 ~0x2000_7FFF
+ * |        |          |0 = system SRAM BIST Disabled.
+ * |        |          |1 = system SRAM BIST Enabled.
+ * |[2]     |CRBIST    |CACHE BIST Enable Bit
+ * |        |          |This bit enables BIST test for CACHE RAM
+ * |        |          |0 = system CACHE BIST Disabled.
+ * |        |          |1 = system CACHE BIST Enabled.
+ * |[3]     |CANBIST   |CAN BIST Enable Bit
+ * |        |          |This bit enables BIST test for CAN RAM
+ * |        |          |0 = system CAN BIST Disabled.
+ * |        |          |1 = system CAN BIST Enabled.
+ * |[4]     |USBBIST   |USB BIST Enable Bit
+ * |        |          |This bit enables BIST test for USB RAM
+ * |        |          |0 = system USB BIST Disabled.
+ * |        |          |1 = system USB BIST Enabled.
+ * @var SYS_T::SRAM_BISTSTS
+ * Offset: 0xD4  System SRAM BIST Test Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SRBISTEF0 |1st System SRAM BIST Fail Flag
+ * |        |          |0 = 1st system SRAM BIST test pass.
+ * |        |          |1 = 1st system SRAM BIST test fail.
+ * |[1]     |SRBISTEF1 |2nd System SRAM BIST Fail Flag
+ * |        |          |0 = 2nd system SRAM BIST test pass.
+ * |        |          |1 = 2nd system SRAM BIST test fail.
+ * |[2]     |CRBISTEF  |CACHE SRAM BIST Fail Flag
+ * |        |          |0 = System CACHE RAM BIST test pass.
+ * |        |          |1 = System CACHE RAM BIST test fail.
+ * |[3]     |CANBEF    |CAN SRAM BIST Fail Flag
+ * |        |          |0 = CAN SRAM BIST test pass.
+ * |        |          |1 = CAN SRAM BIST test fail.
+ * |[4]     |USBBEF    |USB SRAM BIST Fail Flag
+ * |        |          |0 = USB SRAM BIST test pass.
+ * |        |          |1 = USB SRAM BIST test fail.
+ * |[16]    |SRBEND0   |1st SRAM BIST Test Finish
+ * |        |          |0 = 1st system SRAM BIST active.
+ * |        |          |1 = 1st system SRAM BIST finish.
+ * |[17]    |SRBEND1   |2nd SRAM BIST Test Finish
+ * |        |          |0 = 2nd system SRAM BIST is active.
+ * |        |          |1 = 2nd system SRAM BIST finish.
+ * |[18]    |CRBEND    |CACHE SRAM BIST Test Finish
+ * |        |          |0 = System CACHE RAM BIST is active.
+ * |        |          |1 = System CACHE RAM BIST test finish.
+ * |[19]    |CANBEND   |CAN SRAM BIST Test Finish
+ * |        |          |0 = CAN SRAM BIST is active.
+ * |        |          |1 = CAN SRAM BIST test finish.
+ * |[20]    |USBBEND   |USB SRAM BIST Test Finish
+ * |        |          |0 = USB SRAM BIST is active.
+ * |        |          |1 = USB SRAM BIST test finish.
+ * @var SYS_T::IRCTCTL
+ * Offset: 0xF0  IRC Trim Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |FREQSEL   |Trim Frequency Selection
+ * |        |          |This field indicates the target frequency of internal 22.1184 MHz high-speed oscillator auto trim.
+ * |        |          |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
+ * |        |          |00 = Disable HIRC auto trim function.
+ * |        |          |01 = Enable HIRC auto trim function and trim HIRC to 22.1184 MHz.
+ * |        |          |10 = Enable HIRC auto trim function and trim HIRC to 24 MHz.
+ * |        |          |11 = Reserved.
+ * |[5:4]   |LOOPSEL   |Trim Calculation Loop Selection
+ * |        |          |This field defines that trim value calculation is based on how many 32.768 kHz clock.
+ * |        |          |00 = Trim value calculation is based on average difference in 4 32.768 kHz clock.
+ * |        |          |01 = Trim value calculation is based on average difference in 8 32.768 kHz clock.
+ * |        |          |10 = Trim value calculation is based on average difference in 16 32.768 kHz clock.
+ * |        |          |11 = Trim value calculation is based on average difference in 32 32.768 kHz clock.
+ * |        |          |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
+ * |[7:6]   |RETRYCNT  |Trim Value Update Limitation Count
+ * |        |          |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
+ * |        |          |Once the HIRC locked, the internal trim value update counter will be reset.
+ * |        |          |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
+ * |        |          |00 = Trim retry count limitation is 64 loops.
+ * |        |          |01 = Trim retry count limitation is 128 loops.
+ * |        |          |10 = Trim retry count limitation is 256 loops.
+ * |        |          |11 = Trim retry count limitation is 512 loops.
+ * |[8]     |CESTOPEN  |Clock Error Stop Enable Bit
+ * |        |          |0 = The trim operation is keep going if clock is inaccuracy.
+ * |        |          |1 = The trim operation is stopped if clock is inaccuracy.
+ * @var SYS_T::IRCTIEN
+ * Offset: 0xF4  IRC Trim Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1]     |TFAILIEN  |Trim Failure Interrupt Enable Bit
+ * |        |          |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
+ * |        |          |If this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+ * |        |          |0 = Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
+ * |        |          |1 = Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
+ * |[2]     |CLKEIEN   |Clock Error Interrupt Enable Bit
+ * |        |          |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
+ * |        |          |If this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+ * |        |          |0 = Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.
+ * |        |          |1 = Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.
+ * @var SYS_T::IRCTISTS
+ * Offset: 0xF8  IRC Trim Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |FREQLOCK  |HIRC Frequency Lock Status
+ * |        |          |This bit indicates the internal 22.1184 MHz high-speed oscillator frequency is locked.
+ * |        |          |This is a status bit and doesn't trigger any interrupt.
+ * |[1]     |TFAILIF   |Trim Failure Interrupt Status
+ * |        |          |This bit indicates that internal 22.1184 MHz high-speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high-speed oscillator clock frequency still doesn't be locked.
+ * |        |          |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
+ * |        |          |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+ * |        |          |Write 1 to clear this to 0.
+ * |        |          |0 = Trim value update limitation count does not reach.
+ * |        |          |1 = Trim value update limitation count reached and internal 22.1184 MHz high-speed oscillator frequency still not locked.
+ * |[2]     |CLKERRIF  |Clock Error Interrupt Status
+ * |        |          |When the frequency of external 32.768 kHz low-speed crystal or internal 22.1184 MHz high-speed oscillator is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
+ * |        |          |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.
+ * |        |          |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+ * |        |          |Write 1 to clear this to 0.
+ * |        |          |0 = Clock frequency is accuracy.
+ * |        |          |1 = Clock frequency is inaccuracy.
+ * @var SYS_T::REGLCTL
+ * Offset: 0x100  Register Lock Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |REGLCTL   |Register Lock Control Code
+ * |        |          |Write operation:
+ * |        |          |Some registers have write-protection function.
+ * |        |          |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
+ * |        |          |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
+ * |        |          |Read operation:
+ * |        |          |0 = Write-protection Enabled for writing protected registers.
+ * |        |          |Any write to the protected register is ignored.
+ * |        |          |1 = Write-protection Disabled for writing protected registers.
+ * |        |          |The Protected registers are:
+ * |        |          |SYS_IPRST0: address 0x4000_0008
+ * |        |          |SYS_BODCTL: address 0x4000_0018
+ * |        |          |SYS_PORCTL: address 0x4000_0024
+ * |        |          |SYS_VREFCTL: address 0x4000_0028
+ * |        |          |SYS_USBPHY: address 0x4000_002C
+ * |        |          |CLK_PWRCTL: address 0x4000_0200 (bit[6] is not protected for power wake-up interrupt clear)
+ * |        |          |SYS_SRAM_BISTCTL: address 0x4000_00D0
+ * |        |          |CLK_APBCLK0 [0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
+ * |        |          |CLK_CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select)
+ * |        |          |CLK_CLKSEL1 [1:0]: address 0x4000_0214 (for watchdog clock source select)
+ * |        |          |CLK_CLKSEL1 [31:30]: address 0x4000_0214 (for window watchdog clock source select)
+ * |        |          |CLK_CLKDSTS: address 0x4000_0274
+ * |        |          |NMIEN: address 0x4000_0300
+ * |        |          |FMC_ISPCTL: address 0x4000_C000 (Flash ISP Control register)
+ * |        |          |FMC_ISPTRG: address 0x4000_C010 (ISP Trigger Control register)
+ * |        |          |FMC_ISPSTS: address 0x4000_C040
+ * |        |          |WDT_CTL: address 0x4004_0000
+ * |        |          |FMC_FTCTL: address 0x4000_5018
+ * |        |          |FMC_ICPCMD: address 0x4000_501C
+ * |        |          |CLK_PLLCTL: address 0x40000240
+ * |        |          |PWM_CTL0: address 0x4005_8000
+ * |        |          |PWM_CTL0: address 0x4005_9000
+ * |        |          |PWM_DTCTL0_1: address 0x4005_8070
+ * |        |          |PWM_DTCTL0_1: address 0x4005_9070
+ * |        |          |PWM_DTCTL2_3: address 0x4005_8074
+ * |        |          |PWM_DTCTL2_3: address 0x4005_9074
+ * |        |          |PWM_DTCTL4_5: address 0x4005_8078
+ * |        |          |PWM_DTCTL4_5: address 0x4005_9078
+ * |        |          |PWM_BRKCTL0_1: address 0x4005_80C8
+ * |        |          |PWM_BRKCTL0_1: address 0x4005_90C8
+ * |        |          |PWM_BRKCTL2_3: address0x4005_80CC
+ * |        |          |PWM_BRKCTL2_3: address0x4005_90CC
+ * |        |          |PWM_BRKCTL4_5: address0x4005_80D0
+ * |        |          |PWM_BRKCTL4_5: address0x4005_90D0
+ * |        |          |PWM_INTEN1: address0x4005_80E4
+ * |        |          |PWM_INTEN1: address0x4005_90E4
+ * |        |          |PWM_INTSTS1: address0x4005_80EC
+ * |        |          |PWM_INTSTS1: address0x4005_90EC
+ */
+
+    __I  uint32_t PDID;          /* Offset: 0x00  Part Device Identification Number Register                         */
+    __IO uint32_t RSTSTS;        /* Offset: 0x04  System Reset Status Register                                       */
+    __IO uint32_t IPRST0;        /* Offset: 0x08  Peripheral  Reset Control Register 0                               */
+    __IO uint32_t IPRST1;        /* Offset: 0x0C  Peripheral Reset Control Register 1                                */
+    __IO uint32_t IPRST2;        /* Offset: 0x10  Peripheral Reset Control Register 2                                */
+    __I  uint32_t RESERVE0[1];  
+    __IO uint32_t BODCTL;        /* Offset: 0x18  Brown-Out Detector Control Register                                */
+    __IO uint32_t IVSCTL;        /* Offset: 0x1C  Internal Voltage Source Control Register                           */
+    __I  uint32_t RESERVE1[1];  
+    __IO uint32_t PORCTL;        /* Offset: 0x24  Power-On-Reset Controller Register                                 */
+    __IO uint32_t VREFCTL;       /* Offset: 0x28  VREF Control Register                                              */
+    __IO uint32_t USBPHY;        /* Offset: 0x2C  USB PHY Control Register                                           */
+    __IO uint32_t GPA_MFPL;      /* Offset: 0x30  GPIOA Low Byte Multiple Function Control Register                  */
+    __IO uint32_t GPA_MFPH;      /* Offset: 0x34  GPIOA High Byte Multiple Function Control Register                 */
+    __IO uint32_t GPB_MFPL;      /* Offset: 0x38  GPIOB Low Byte Multiple Function Control Register                  */
+    __IO uint32_t GPB_MFPH;      /* Offset: 0x3C  GPIOB High Byte Multiple Function Control Register                 */
+    __IO uint32_t GPC_MFPL;      /* Offset: 0x40  GPIOC Low Byte Multiple Function Control Register                  */
+    __IO uint32_t GPC_MFPH;      /* Offset: 0x44  GPIOC High Byte Multiple Function Control Register                 */
+    __IO uint32_t GPD_MFPL;      /* Offset: 0x48  GPIOD Low Byte Multiple Function Control Register                  */
+    __IO uint32_t GPD_MFPH;      /* Offset: 0x4C  GPIOD High Byte Multiple Function Control Register                 */
+    __IO uint32_t GPE_MFPL;      /* Offset: 0x50  GPIOE Low Byte Multiple Function Control Register                  */
+    __IO uint32_t GPE_MFPH;      /* Offset: 0x54  GPIOE High Byte Multiple Function Control Register                 */
+    __IO uint32_t GPF_MFPL;      /* Offset: 0x58  GPIOF Low Byte Multiple Function Control Register                  */
+    __I  uint32_t RESERVE2[25]; 
+    __IO uint32_t SRAM_INTCTL;   /* Offset: 0xC0  System SRAM Interrupt Enable Control Register                      */
+    __I  uint32_t SRAM_STATUS;   /* Offset: 0xC4  System SRAM Parity Error Status Register                           */
+    __I  uint32_t SRAM_ERRADDR;  /* Offset: 0xC8  System SRAM Parity Check Error Address Register                    */
+    __I  uint32_t RESERVE3[1];  
+    __IO uint32_t SRAM_BISTCTL;  /* Offset: 0xD0  System SRAM BIST Test Control Register                             */
+    __I  uint32_t SRAM_BISTSTS;  /* Offset: 0xD4  System SRAM BIST Test Status Register                              */
+    __I  uint32_t RESERVE4[6];  
+    __IO uint32_t IRCTCTL;       /* Offset: 0xF0  IRC Trim Control Register                                          */
+    __IO uint32_t IRCTIEN;       /* Offset: 0xF4  IRC Trim Interrupt Enable Register                                 */
+    __IO uint32_t IRCTISTS;      /* Offset: 0xF8  IRC Trim Interrupt Status Register                                 */
+    __I  uint32_t RESERVE5[1];  
+    __IO uint32_t REGLCTL;       /* Offset: 0x100  Register Lock Control Register                                    */
+
+} SYS_T;
+
+
+
+/**
+    @addtogroup SYS_CONST SYS Bit Field Definition
+    Constant Definitions for SYS Controller
+@{ */
+
+#define SYS_PDID_PDID_Pos                (0)                                               /*!< SYS_T::PDID: PDID Position                */
+#define SYS_PDID_PDID_Msk                (0xfffffffful << SYS_PDID_PDID_Pos)               /*!< SYS_T::PDID: PDID Mask                    */
+
+#define SYS_RSTSTS_PORF_Pos              (0)                                               /*!< SYS_T::RSTSTS: PORF Position              */
+#define SYS_RSTSTS_PORF_Msk              (0x1ul << SYS_RSTSTS_PORF_Pos)                    /*!< SYS_T::RSTSTS: PORF Mask                  */
+
+#define SYS_RSTSTS_PINRF_Pos             (1)                                               /*!< SYS_T::RSTSTS: PINRF Position             */
+#define SYS_RSTSTS_PINRF_Msk             (0x1ul << SYS_RSTSTS_PINRF_Pos)                   /*!< SYS_T::RSTSTS: PINRF Mask                 */
+
+#define SYS_RSTSTS_WDTRF_Pos             (2)                                               /*!< SYS_T::RSTSTS: WDTRF Position             */
+#define SYS_RSTSTS_WDTRF_Msk             (0x1ul << SYS_RSTSTS_WDTRF_Pos)                   /*!< SYS_T::RSTSTS: WDTRF Mask                 */
+
+#define SYS_RSTSTS_LVRF_Pos              (3)                                               /*!< SYS_T::RSTSTS: LVRF Position              */
+#define SYS_RSTSTS_LVRF_Msk              (0x1ul << SYS_RSTSTS_LVRF_Pos)                    /*!< SYS_T::RSTSTS: LVRF Mask                  */
+
+#define SYS_RSTSTS_BODRF_Pos             (4)                                               /*!< SYS_T::RSTSTS: BODRF Position             */
+#define SYS_RSTSTS_BODRF_Msk             (0x1ul << SYS_RSTSTS_BODRF_Pos)                   /*!< SYS_T::RSTSTS: BODRF Mask                 */
+
+#define SYS_RSTSTS_SYSRF_Pos             (5)                                               /*!< SYS_T::RSTSTS: SYSRF Position             */
+#define SYS_RSTSTS_SYSRF_Msk             (0x1ul << SYS_RSTSTS_SYSRF_Pos)                   /*!< SYS_T::RSTSTS: SYSRF Mask                 */
+
+#define SYS_RSTSTS_CPURF_Pos             (7)                                               /*!< SYS_T::RSTSTS: CPURF Position             */
+#define SYS_RSTSTS_CPURF_Msk             (0x1ul << SYS_RSTSTS_CPURF_Pos)                   /*!< SYS_T::RSTSTS: CPURF Mask                 */
+
+#define SYS_RSTSTS_CPULKRF_Pos           (8)                                               /*!< SYS_T::RSTSTS: CPULKRF Position           */
+#define SYS_RSTSTS_CPULKRF_Msk           (0x1ul << SYS_RSTSTS_CPULKRF_Pos)                 /*!< SYS_T::RSTSTS: CPULKRF Mask               */
+
+#define SYS_IPRST0_CHIPRST_Pos           (0)                                               /*!< SYS_T::IPRST0: CHIPRST Position           */
+#define SYS_IPRST0_CHIPRST_Msk           (0x1ul << SYS_IPRST0_CHIPRST_Pos)                 /*!< SYS_T::IPRST0: CHIPRST Mask               */
+
+#define SYS_IPRST0_CPURST_Pos            (1)                                               /*!< SYS_T::IPRST0: CPURST Position            */
+#define SYS_IPRST0_CPURST_Msk            (0x1ul << SYS_IPRST0_CPURST_Pos)                  /*!< SYS_T::IPRST0: CPURST Mask                */
+
+#define SYS_IPRST0_PDMARST_Pos           (2)                                               /*!< SYS_T::IPRST0: PDMARST Position           */
+#define SYS_IPRST0_PDMARST_Msk           (0x1ul << SYS_IPRST0_PDMARST_Pos)                 /*!< SYS_T::IPRST0: PDMARST Mask               */
+
+#define SYS_IPRST0_EBIRST_Pos            (3)                                               /*!< SYS_T::IPRST0: EBIRST Position            */
+#define SYS_IPRST0_EBIRST_Msk            (0x1ul << SYS_IPRST0_EBIRST_Pos)                  /*!< SYS_T::IPRST0: EBIRST Mask                */
+
+#define SYS_IPRST0_USBHRST_Pos           (4)                                               /*!< SYS_T::IPRST0: USBHRST Position           */
+#define SYS_IPRST0_USBHRST_Msk           (0x1ul << SYS_IPRST0_USBHRST_Pos)                 /*!< SYS_T::IPRST0: USBHRST Mask               */
+
+#define SYS_IPRST0_CRCRST_Pos            (7)                                               /*!< SYS_T::IPRST0: CRCRST Position            */
+#define SYS_IPRST0_CRCRST_Msk            (0x1ul << SYS_IPRST0_CRCRST_Pos)                  /*!< SYS_T::IPRST0: CRCRST Mask                */
+
+#define SYS_IPRST1_GPIORST_Pos           (1)                                               /*!< SYS_T::IPRST1: GPIORST Position           */
+#define SYS_IPRST1_GPIORST_Msk           (0x1ul << SYS_IPRST1_GPIORST_Pos)                 /*!< SYS_T::IPRST1: GPIORST Mask               */
+
+#define SYS_IPRST1_TMR0RST_Pos           (2)                                               /*!< SYS_T::IPRST1: TMR0RST Position           */
+#define SYS_IPRST1_TMR0RST_Msk           (0x1ul << SYS_IPRST1_TMR0RST_Pos)                 /*!< SYS_T::IPRST1: TMR0RST Mask               */
+
+#define SYS_IPRST1_TMR1RST_Pos           (3)                                               /*!< SYS_T::IPRST1: TMR1RST Position           */
+#define SYS_IPRST1_TMR1RST_Msk           (0x1ul << SYS_IPRST1_TMR1RST_Pos)                 /*!< SYS_T::IPRST1: TMR1RST Mask               */
+
+#define SYS_IPRST1_TMR2RST_Pos           (4)                                               /*!< SYS_T::IPRST1: TMR2RST Position           */
+#define SYS_IPRST1_TMR2RST_Msk           (0x1ul << SYS_IPRST1_TMR2RST_Pos)                 /*!< SYS_T::IPRST1: TMR2RST Mask               */
+
+#define SYS_IPRST1_TMR3RST_Pos           (5)                                               /*!< SYS_T::IPRST1: TMR3RST Position           */
+#define SYS_IPRST1_TMR3RST_Msk           (0x1ul << SYS_IPRST1_TMR3RST_Pos)                 /*!< SYS_T::IPRST1: TMR3RST Mask               */
+
+#define SYS_IPRST1_ACMP01RST_Pos         (7)                                               /*!< SYS_T::IPRST1: ACMP01RST Position         */
+#define SYS_IPRST1_ACMP01RST_Msk         (0x1ul << SYS_IPRST1_ACMP01RST_Pos)               /*!< SYS_T::IPRST1: ACMP01RST Mask             */
+
+#define SYS_IPRST1_I2C0RST_Pos           (8)                                               /*!< SYS_T::IPRST1: I2C0RST Position           */
+#define SYS_IPRST1_I2C0RST_Msk           (0x1ul << SYS_IPRST1_I2C0RST_Pos)                 /*!< SYS_T::IPRST1: I2C0RST Mask               */
+
+#define SYS_IPRST1_I2C1RST_Pos           (9)                                               /*!< SYS_T::IPRST1: I2C1RST Position           */
+#define SYS_IPRST1_I2C1RST_Msk           (0x1ul << SYS_IPRST1_I2C1RST_Pos)                 /*!< SYS_T::IPRST1: I2C1RST Mask               */
+
+#define SYS_IPRST1_SPI0RST_Pos           (12)                                              /*!< SYS_T::IPRST1: SPI0RST Position           */
+#define SYS_IPRST1_SPI0RST_Msk           (0x1ul << SYS_IPRST1_SPI0RST_Pos)                 /*!< SYS_T::IPRST1: SPI0RST Mask               */
+
+#define SYS_IPRST1_SPI1RST_Pos           (13)                                              /*!< SYS_T::IPRST1: SPI1RST Position           */
+#define SYS_IPRST1_SPI1RST_Msk           (0x1ul << SYS_IPRST1_SPI1RST_Pos)                 /*!< SYS_T::IPRST1: SPI1RST Mask               */
+
+#define SYS_IPRST1_SPI2RST_Pos           (14)                                              /*!< SYS_T::IPRST1: SPI2RST Position           */
+#define SYS_IPRST1_SPI2RST_Msk           (0x1ul << SYS_IPRST1_SPI2RST_Pos)                 /*!< SYS_T::IPRST1: SPI2RST Mask               */
+
+#define SYS_IPRST1_UART0RST_Pos          (16)                                              /*!< SYS_T::IPRST1: UART0RST Position          */
+#define SYS_IPRST1_UART0RST_Msk          (0x1ul << SYS_IPRST1_UART0RST_Pos)                /*!< SYS_T::IPRST1: UART0RST Mask              */
+
+#define SYS_IPRST1_UART1RST_Pos          (17)                                              /*!< SYS_T::IPRST1: UART1RST Position          */
+#define SYS_IPRST1_UART1RST_Msk          (0x1ul << SYS_IPRST1_UART1RST_Pos)                /*!< SYS_T::IPRST1: UART1RST Mask              */
+
+#define SYS_IPRST1_UART2RST_Pos          (18)                                              /*!< SYS_T::IPRST1: UART2RST Position          */
+#define SYS_IPRST1_UART2RST_Msk          (0x1ul << SYS_IPRST1_UART2RST_Pos)                /*!< SYS_T::IPRST1: UART2RST Mask              */
+
+#define SYS_IPRST1_UART3RST_Pos          (19)                                              /*!< SYS_T::IPRST1: UART3RST Position          */
+#define SYS_IPRST1_UART3RST_Msk          (0x1ul << SYS_IPRST1_UART3RST_Pos)                /*!< SYS_T::IPRST1: UART3RST Mask              */
+
+#define SYS_IPRST1_CAN0RST_Pos           (24)                                              /*!< SYS_T::IPRST1: CAN0RST Position           */
+#define SYS_IPRST1_CAN0RST_Msk           (0x1ul << SYS_IPRST1_CAN0RST_Pos)                 /*!< SYS_T::IPRST1: CAN0RST Mask               */
+
+#define SYS_IPRST1_OTGRST_Pos            (26)                                              /*!< SYS_T::IPRST1: OTGRST Position            */
+#define SYS_IPRST1_OTGRST_Msk            (0x1ul << SYS_IPRST1_OTGRST_Pos)                  /*!< SYS_T::IPRST1: OTGRST Mask                */
+
+#define SYS_IPRST1_USBDRST_Pos           (27)                                              /*!< SYS_T::IPRST1: USBDRST Position           */
+#define SYS_IPRST1_USBDRST_Msk           (0x1ul << SYS_IPRST1_USBDRST_Pos)                 /*!< SYS_T::IPRST1: USBDRST Mask               */
+
+#define SYS_IPRST1_EADCRST_Pos           (28)                                              /*!< SYS_T::IPRST1: EADCRST Position           */
+#define SYS_IPRST1_EADCRST_Msk           (0x1ul << SYS_IPRST1_EADCRST_Pos)                 /*!< SYS_T::IPRST1: EADCRST Mask               */
+
+#define SYS_IPRST2_SC0RST_Pos            (0)                                               /*!< SYS_T::IPRST2: SC0RST Position            */
+#define SYS_IPRST2_SC0RST_Msk            (0x1ul << SYS_IPRST2_SC0RST_Pos)                  /*!< SYS_T::IPRST2: SC0RST Mask                */
+
+#define SYS_IPRST2_DACRST_Pos            (12)                                              /*!< SYS_T::IPRST2: DACRST Position            */
+#define SYS_IPRST2_DACRST_Msk            (0x1ul << SYS_IPRST2_DACRST_Pos)                  /*!< SYS_T::IPRST2: DACRST Mask                */
+
+#define SYS_IPRST2_PWM0RST_Pos           (16)                                              /*!< SYS_T::IPRST2: PWM0RST Position           */
+#define SYS_IPRST2_PWM0RST_Msk           (0x1ul << SYS_IPRST2_PWM0RST_Pos)                 /*!< SYS_T::IPRST2: PWM0RST Mask               */
+
+#define SYS_IPRST2_PWM1RST_Pos           (17)                                              /*!< SYS_T::IPRST2: PWM1RST Position           */
+#define SYS_IPRST2_PWM1RST_Msk           (0x1ul << SYS_IPRST2_PWM1RST_Pos)                 /*!< SYS_T::IPRST2: PWM1RST Mask               */
+
+#define SYS_IPRST2_TKRST_Pos             (25)                                              /*!< SYS_T::IPRST2: TKRST Position             */
+#define SYS_IPRST2_TKRST_Msk             (0x1ul << SYS_IPRST2_TKRST_Pos)                   /*!< SYS_T::IPRST2: TKRST Mask                 */
+
+#define SYS_BODCTL_BODEN_Pos             (0)                                               /*!< SYS_T::BODCTL: BODEN Position             */
+#define SYS_BODCTL_BODEN_Msk             (0x1ul << SYS_BODCTL_BODEN_Pos)                   /*!< SYS_T::BODCTL: BODEN Mask                 */
+
+#define SYS_BODCTL_BODVL_Pos             (1)                                               /*!< SYS_T::BODCTL: BODVL Position             */
+#define SYS_BODCTL_BODVL_Msk             (0x3ul << SYS_BODCTL_BODVL_Pos)                   /*!< SYS_T::BODCTL: BODVL Mask                 */
+
+#define SYS_BODCTL_BODRSTEN_Pos          (3)                                               /*!< SYS_T::BODCTL: BODRSTEN Position          */
+#define SYS_BODCTL_BODRSTEN_Msk          (0x1ul << SYS_BODCTL_BODRSTEN_Pos)                /*!< SYS_T::BODCTL: BODRSTEN Mask              */
+
+#define SYS_BODCTL_BODIF_Pos             (4)                                               /*!< SYS_T::BODCTL: BODIF Position             */
+#define SYS_BODCTL_BODIF_Msk             (0x1ul << SYS_BODCTL_BODIF_Pos)                   /*!< SYS_T::BODCTL: BODIF Mask                 */
+
+#define SYS_BODCTL_BODLPM_Pos            (5)                                               /*!< SYS_T::BODCTL: BODLPM Position            */
+#define SYS_BODCTL_BODLPM_Msk            (0x1ul << SYS_BODCTL_BODLPM_Pos)                  /*!< SYS_T::BODCTL: BODLPM Mask                */
+
+#define SYS_BODCTL_BODOUT_Pos            (6)                                               /*!< SYS_T::BODCTL: BODOUT Position            */
+#define SYS_BODCTL_BODOUT_Msk            (0x1ul << SYS_BODCTL_BODOUT_Pos)                  /*!< SYS_T::BODCTL: BODOUT Mask                */
+
+#define SYS_BODCTL_LVREN_Pos             (7)                                               /*!< SYS_T::BODCTL: LVREN Position             */
+#define SYS_BODCTL_LVREN_Msk             (0x1ul << SYS_BODCTL_LVREN_Pos)                   /*!< SYS_T::BODCTL: LVREN Mask                 */
+
+#define SYS_BODCTL_BODDGSEL_Pos          (8)                                               /*!< SYS_T::BODCTL: BODDGSEL Position          */
+#define SYS_BODCTL_BODDGSEL_Msk          (0x7ul << SYS_BODCTL_BODDGSEL_Pos)                /*!< SYS_T::BODCTL: BODDGSEL Mask              */
+
+#define SYS_BODCTL_LVRDGSEL_Pos          (12)                                              /*!< SYS_T::BODCTL: LVRDGSEL Position          */
+#define SYS_BODCTL_LVRDGSEL_Msk          (0x7ul << SYS_BODCTL_LVRDGSEL_Pos)                /*!< SYS_T::BODCTL: LVRDGSEL Mask              */
+
+#define SYS_IVSCTL_VTEMPEN_Pos           (0)                                               /*!< SYS_T::IVSCTL: VTEMPEN Position           */
+#define SYS_IVSCTL_VTEMPEN_Msk           (0x1ul << SYS_IVSCTL_VTEMPEN_Pos)                 /*!< SYS_T::IVSCTL: VTEMPEN Mask               */
+
+#define SYS_IVSCTL_VBATUGEN_Pos          (1)                                               /*!< SYS_T::IVSCTL: VBATUGEN Position          */
+#define SYS_IVSCTL_VBATUGEN_Msk          (0x1ul << SYS_IVSCTL_VBATUGEN_Pos)                /*!< SYS_T::IVSCTL: VBATUGEN Mask              */
+
+#define SYS_PORCTL_POROFF_Pos            (0)                                               /*!< SYS_T::PORCTL: POROFF Position            */
+#define SYS_PORCTL_POROFF_Msk            (0xfffful << SYS_PORCTL_POROFF_Pos)               /*!< SYS_T::PORCTL: POROFF Mask                */
+
+#define SYS_VREFCTL_VREFCTL_Pos          (0)                                               /*!< SYS_T::VREFCTL: VREFCTL Position          */
+#define SYS_VREFCTL_VREFCTL_Msk          (0x1ful << SYS_VREFCTL_VREFCTL_Pos)               /*!< SYS_T::VREFCTL: VREFCTL Mask              */
+
+#define SYS_USBPHY_USBROLE_Pos           (0)                                               /*!< SYS_T::USBPHY: USBROLE Position           */
+#define SYS_USBPHY_USBROLE_Msk           (0x3ul << SYS_USBPHY_USBROLE_Pos)                 /*!< SYS_T::USBPHY: USBROLE Mask               */
+
+#define SYS_USBPHY_LDO33EN_Pos           (8)                                               /*!< SYS_T::USBPHY: LDO33EN Position           */
+#define SYS_USBPHY_LDO33EN_Msk           (0x1ul << SYS_USBPHY_LDO33EN_Pos)                 /*!< SYS_T::USBPHY: LDO33EN Mask               */
+
+#define SYS_GPA_MFPL_PA0MFP_Pos          (0)                                               /*!< SYS_T::GPA_MFPL: PA0MFP Position          */
+#define SYS_GPA_MFPL_PA0MFP_Msk          (0xful << SYS_GPA_MFPL_PA0MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA0MFP Mask              */
+
+#define SYS_GPA_MFPL_PA1MFP_Pos          (4)                                               /*!< SYS_T::GPA_MFPL: PA1MFP Position          */
+#define SYS_GPA_MFPL_PA1MFP_Msk          (0xful << SYS_GPA_MFPL_PA1MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA1MFP Mask              */
+
+#define SYS_GPA_MFPL_PA2MFP_Pos          (8)                                               /*!< SYS_T::GPA_MFPL: PA2MFP Position          */
+#define SYS_GPA_MFPL_PA2MFP_Msk          (0xful << SYS_GPA_MFPL_PA2MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA2MFP Mask              */
+
+#define SYS_GPA_MFPL_PA3MFP_Pos          (12)                                              /*!< SYS_T::GPA_MFPL: PA3MFP Position          */
+#define SYS_GPA_MFPL_PA3MFP_Msk          (0xful << SYS_GPA_MFPL_PA3MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA3MFP Mask              */
+
+#define SYS_GPA_MFPL_PA4MFP_Pos          (16)                                              /*!< SYS_T::GPA_MFPL: PA4MFP Position          */
+#define SYS_GPA_MFPL_PA4MFP_Msk          (0xful << SYS_GPA_MFPL_PA4MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA4MFP Mask              */
+
+#define SYS_GPA_MFPL_PA5MFP_Pos          (20)                                              /*!< SYS_T::GPA_MFPL: PA5MFP Position          */
+#define SYS_GPA_MFPL_PA5MFP_Msk          (0xful << SYS_GPA_MFPL_PA5MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA5MFP Mask              */
+
+#define SYS_GPA_MFPL_PA6MFP_Pos          (24)                                              /*!< SYS_T::GPA_MFPL: PA6MFP Position          */
+#define SYS_GPA_MFPL_PA6MFP_Msk          (0xful << SYS_GPA_MFPL_PA6MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA6MFP Mask              */
+
+#define SYS_GPA_MFPL_PA7MFP_Pos          (28)                                              /*!< SYS_T::GPA_MFPL: PA7MFP Position          */
+#define SYS_GPA_MFPL_PA7MFP_Msk          (0xful << SYS_GPA_MFPL_PA7MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA7MFP Mask              */
+
+#define SYS_GPA_MFPH_PA8MFP_Pos          (0)                                               /*!< SYS_T::GPA_MFPH: PA8MFP Position          */
+#define SYS_GPA_MFPH_PA8MFP_Msk          (0xful << SYS_GPA_MFPH_PA8MFP_Pos)                /*!< SYS_T::GPA_MFPH: PA8MFP Mask              */
+
+#define SYS_GPA_MFPH_PA9MFP_Pos          (4)                                               /*!< SYS_T::GPA_MFPH: PA9MFP Position          */
+#define SYS_GPA_MFPH_PA9MFP_Msk          (0xful << SYS_GPA_MFPH_PA9MFP_Pos)                /*!< SYS_T::GPA_MFPH: PA9MFP Mask              */
+
+#define SYS_GPA_MFPH_PA10MFP_Pos         (8)                                               /*!< SYS_T::GPA_MFPH: PA10MFP Position         */
+#define SYS_GPA_MFPH_PA10MFP_Msk         (0xful << SYS_GPA_MFPH_PA10MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA10MFP Mask             */
+
+#define SYS_GPA_MFPH_PA11MFP_Pos         (12)                                              /*!< SYS_T::GPA_MFPH: PA11MFP Position         */
+#define SYS_GPA_MFPH_PA11MFP_Msk         (0xful << SYS_GPA_MFPH_PA11MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA11MFP Mask             */
+
+#define SYS_GPA_MFPH_PA12MFP_Pos         (16)                                              /*!< SYS_T::GPA_MFPH: PA12MFP Position         */
+#define SYS_GPA_MFPH_PA12MFP_Msk         (0xful << SYS_GPA_MFPH_PA12MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA12MFP Mask             */
+
+#define SYS_GPA_MFPH_PA13MFP_Pos         (20)                                              /*!< SYS_T::GPA_MFPH: PA13MFP Position         */
+#define SYS_GPA_MFPH_PA13MFP_Msk         (0xful << SYS_GPA_MFPH_PA13MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA13MFP Mask             */
+
+#define SYS_GPA_MFPH_PA14MFP_Pos         (24)                                              /*!< SYS_T::GPA_MFPH: PA14MFP Position         */
+#define SYS_GPA_MFPH_PA14MFP_Msk         (0xful << SYS_GPA_MFPH_PA14MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA14MFP Mask             */
+
+#define SYS_GPA_MFPH_PA15MFP_Pos         (28)                                              /*!< SYS_T::GPA_MFPH: PA15MFP Position         */
+#define SYS_GPA_MFPH_PA15MFP_Msk         (0xful << SYS_GPA_MFPH_PA15MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA15MFP Mask             */
+
+#define SYS_GPB_MFPL_PB0MFP_Pos          (0)                                               /*!< SYS_T::GPB_MFPL: PB0MFP Position          */
+#define SYS_GPB_MFPL_PB0MFP_Msk          (0xful << SYS_GPB_MFPL_PB0MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB0MFP Mask              */
+
+#define SYS_GPB_MFPL_PB1MFP_Pos          (4)                                               /*!< SYS_T::GPB_MFPL: PB1MFP Position          */
+#define SYS_GPB_MFPL_PB1MFP_Msk          (0xful << SYS_GPB_MFPL_PB1MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB1MFP Mask              */
+
+#define SYS_GPB_MFPL_PB2MFP_Pos          (8)                                               /*!< SYS_T::GPB_MFPL: PB2MFP Position          */
+#define SYS_GPB_MFPL_PB2MFP_Msk          (0xful << SYS_GPB_MFPL_PB2MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB2MFP Mask              */
+
+#define SYS_GPB_MFPL_PB3MFP_Pos          (12)                                              /*!< SYS_T::GPB_MFPL: PB3MFP Position          */
+#define SYS_GPB_MFPL_PB3MFP_Msk          (0xful << SYS_GPB_MFPL_PB3MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB3MFP Mask              */
+
+#define SYS_GPB_MFPL_PB4MFP_Pos          (16)                                              /*!< SYS_T::GPB_MFPL: PB4MFP Position          */
+#define SYS_GPB_MFPL_PB4MFP_Msk          (0xful << SYS_GPB_MFPL_PB4MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB4MFP Mask              */
+
+#define SYS_GPB_MFPL_PB5MFP_Pos          (20)                                              /*!< SYS_T::GPB_MFPL: PB5MFP Position          */
+#define SYS_GPB_MFPL_PB5MFP_Msk          (0xful << SYS_GPB_MFPL_PB5MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB5MFP Mask              */
+
+#define SYS_GPB_MFPL_PB6MFP_Pos          (24)                                              /*!< SYS_T::GPB_MFPL: PB6MFP Position          */
+#define SYS_GPB_MFPL_PB6MFP_Msk          (0xful << SYS_GPB_MFPL_PB6MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB6MFP Mask              */
+
+#define SYS_GPB_MFPL_PB7MFP_Pos          (28)                                              /*!< SYS_T::GPB_MFPL: PB7MFP Position          */
+#define SYS_GPB_MFPL_PB7MFP_Msk          (0xful << SYS_GPB_MFPL_PB7MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB7MFP Mask              */
+
+#define SYS_GPB_MFPH_PB8MFP_Pos          (0)                                               /*!< SYS_T::GPB_MFPH: PB8MFP Position          */
+#define SYS_GPB_MFPH_PB8MFP_Msk          (0xful << SYS_GPB_MFPH_PB8MFP_Pos)                /*!< SYS_T::GPB_MFPH: PB8MFP Mask              */
+
+#define SYS_GPB_MFPH_PB9MFP_Pos          (4)                                               /*!< SYS_T::GPB_MFPH: PB9MFP Position          */
+#define SYS_GPB_MFPH_PB9MFP_Msk          (0xful << SYS_GPB_MFPH_PB9MFP_Pos)                /*!< SYS_T::GPB_MFPH: PB9MFP Mask              */
+
+#define SYS_GPB_MFPH_PB10MFP_Pos         (8)                                               /*!< SYS_T::GPB_MFPH: PB10MFP Position         */
+#define SYS_GPB_MFPH_PB10MFP_Msk         (0xful << SYS_GPB_MFPH_PB10MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB10MFP Mask             */
+
+#define SYS_GPB_MFPH_PB11MFP_Pos         (12)                                              /*!< SYS_T::GPB_MFPH: PB11MFP Position         */
+#define SYS_GPB_MFPH_PB11MFP_Msk         (0xful << SYS_GPB_MFPH_PB11MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB11MFP Mask             */
+
+#define SYS_GPB_MFPH_PB12MFP_Pos         (16)                                              /*!< SYS_T::GPB_MFPH: PB12MFP Position         */
+#define SYS_GPB_MFPH_PB12MFP_Msk         (0xful << SYS_GPB_MFPH_PB12MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB12MFP Mask             */
+
+#define SYS_GPB_MFPH_PB13MFP_Pos         (20)                                              /*!< SYS_T::GPB_MFPH: PB13MFP Position         */
+#define SYS_GPB_MFPH_PB13MFP_Msk         (0xful << SYS_GPB_MFPH_PB13MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB13MFP Mask             */
+
+#define SYS_GPB_MFPH_PB14MFP_Pos         (24)                                              /*!< SYS_T::GPB_MFPH: PB14MFP Position         */
+#define SYS_GPB_MFPH_PB14MFP_Msk         (0xful << SYS_GPB_MFPH_PB14MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB14MFP Mask             */
+
+#define SYS_GPB_MFPH_PB15MFP_Pos         (28)                                              /*!< SYS_T::GPB_MFPH: PB15MFP Position         */
+#define SYS_GPB_MFPH_PB15MFP_Msk         (0xful << SYS_GPB_MFPH_PB15MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB15MFP Mask             */
+
+#define SYS_GPC_MFPL_PC0MFP_Pos          (0)                                               /*!< SYS_T::GPC_MFPL: PC0MFP Position          */
+#define SYS_GPC_MFPL_PC0MFP_Msk          (0xful << SYS_GPC_MFPL_PC0MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC0MFP Mask              */
+
+#define SYS_GPC_MFPL_PC1MFP_Pos          (4)                                               /*!< SYS_T::GPC_MFPL: PC1MFP Position          */
+#define SYS_GPC_MFPL_PC1MFP_Msk          (0xful << SYS_GPC_MFPL_PC1MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC1MFP Mask              */
+
+#define SYS_GPC_MFPL_PC2MFP_Pos          (8)                                               /*!< SYS_T::GPC_MFPL: PC2MFP Position          */
+#define SYS_GPC_MFPL_PC2MFP_Msk          (0xful << SYS_GPC_MFPL_PC2MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC2MFP Mask              */
+
+#define SYS_GPC_MFPL_PC3MFP_Pos          (12)                                              /*!< SYS_T::GPC_MFPL: PC3MFP Position          */
+#define SYS_GPC_MFPL_PC3MFP_Msk          (0xful << SYS_GPC_MFPL_PC3MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC3MFP Mask              */
+
+#define SYS_GPC_MFPL_PC4MFP_Pos          (16)                                              /*!< SYS_T::GPC_MFPL: PC4MFP Position          */
+#define SYS_GPC_MFPL_PC4MFP_Msk          (0xful << SYS_GPC_MFPL_PC4MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC4MFP Mask              */
+
+#define SYS_GPC_MFPL_PC5MFP_Pos          (20)                                              /*!< SYS_T::GPC_MFPL: PC5MFP Position          */
+#define SYS_GPC_MFPL_PC5MFP_Msk          (0xful << SYS_GPC_MFPL_PC5MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC5MFP Mask              */
+
+#define SYS_GPC_MFPL_PC6MFP_Pos          (24)                                              /*!< SYS_T::GPC_MFPL: PC6MFP Position          */
+#define SYS_GPC_MFPL_PC6MFP_Msk          (0xful << SYS_GPC_MFPL_PC6MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC6MFP Mask              */
+
+#define SYS_GPC_MFPL_PC7MFP_Pos          (28)                                              /*!< SYS_T::GPC_MFPL: PC7MFP Position          */
+#define SYS_GPC_MFPL_PC7MFP_Msk          (0xful << SYS_GPC_MFPL_PC7MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC7MFP Mask              */
+
+#define SYS_GPC_MFPH_PC8MFP_Pos          (0)                                               /*!< SYS_T::GPC_MFPH: PC8MFP Position          */
+#define SYS_GPC_MFPH_PC8MFP_Msk          (0xful << SYS_GPC_MFPH_PC8MFP_Pos)                /*!< SYS_T::GPC_MFPH: PC8MFP Mask              */
+
+#define SYS_GPC_MFPH_PC9MFP_Pos          (4)                                               /*!< SYS_T::GPC_MFPH: PC9MFP Position          */
+#define SYS_GPC_MFPH_PC9MFP_Msk          (0xful << SYS_GPC_MFPH_PC9MFP_Pos)                /*!< SYS_T::GPC_MFPH: PC9MFP Mask              */
+
+#define SYS_GPC_MFPH_PC10MFP_Pos         (8)                                               /*!< SYS_T::GPC_MFPH: PC10MFP Position         */
+#define SYS_GPC_MFPH_PC10MFP_Msk         (0xful << SYS_GPC_MFPH_PC10MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC10MFP Mask             */
+
+#define SYS_GPC_MFPH_PC11MFP_Pos         (12)                                              /*!< SYS_T::GPC_MFPH: PC11MFP Position         */
+#define SYS_GPC_MFPH_PC11MFP_Msk         (0xful << SYS_GPC_MFPH_PC11MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC11MFP Mask             */
+
+#define SYS_GPC_MFPH_PC12MFP_Pos         (16)                                              /*!< SYS_T::GPC_MFPH: PC12MFP Position         */
+#define SYS_GPC_MFPH_PC12MFP_Msk         (0xful << SYS_GPC_MFPH_PC12MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC12MFP Mask             */
+
+#define SYS_GPC_MFPH_PC13MFP_Pos         (20)                                              /*!< SYS_T::GPC_MFPH: PC13MFP Position         */
+#define SYS_GPC_MFPH_PC13MFP_Msk         (0xful << SYS_GPC_MFPH_PC13MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC13MFP Mask             */
+
+#define SYS_GPC_MFPH_PC14MFP_Pos         (24)                                              /*!< SYS_T::GPC_MFPH: PC14MFP Position         */
+#define SYS_GPC_MFPH_PC14MFP_Msk         (0xful << SYS_GPC_MFPH_PC14MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC14MFP Mask             */
+
+#define SYS_GPC_MFPH_PC15MFP_Pos         (28)                                              /*!< SYS_T::GPC_MFPH: PC15MFP Position         */
+#define SYS_GPC_MFPH_PC15MFP_Msk         (0xful << SYS_GPC_MFPH_PC15MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC15MFP Mask             */
+
+#define SYS_GPD_MFPL_PD0MFP_Pos          (0)                                               /*!< SYS_T::GPD_MFPL: PD0MFP Position          */
+#define SYS_GPD_MFPL_PD0MFP_Msk          (0xful << SYS_GPD_MFPL_PD0MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD0MFP Mask              */
+
+#define SYS_GPD_MFPL_PD1MFP_Pos          (4)                                               /*!< SYS_T::GPD_MFPL: PD1MFP Position          */
+#define SYS_GPD_MFPL_PD1MFP_Msk          (0xful << SYS_GPD_MFPL_PD1MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD1MFP Mask              */
+
+#define SYS_GPD_MFPL_PD2MFP_Pos          (8)                                               /*!< SYS_T::GPD_MFPL: PD2MFP Position          */
+#define SYS_GPD_MFPL_PD2MFP_Msk          (0xful << SYS_GPD_MFPL_PD2MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD2MFP Mask              */
+
+#define SYS_GPD_MFPL_PD3MFP_Pos          (12)                                              /*!< SYS_T::GPD_MFPL: PD3MFP Position          */
+#define SYS_GPD_MFPL_PD3MFP_Msk          (0xful << SYS_GPD_MFPL_PD3MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD3MFP Mask              */
+
+#define SYS_GPD_MFPL_PD4MFP_Pos          (16)                                              /*!< SYS_T::GPD_MFPL: PD4MFP Position          */
+#define SYS_GPD_MFPL_PD4MFP_Msk          (0xful << SYS_GPD_MFPL_PD4MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD4MFP Mask              */
+
+#define SYS_GPD_MFPL_PD5MFP_Pos          (20)                                              /*!< SYS_T::GPD_MFPL: PD5MFP Position          */
+#define SYS_GPD_MFPL_PD5MFP_Msk          (0xful << SYS_GPD_MFPL_PD5MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD5MFP Mask              */
+
+#define SYS_GPD_MFPL_PD6MFP_Pos          (24)                                              /*!< SYS_T::GPD_MFPL: PD6MFP Position          */
+#define SYS_GPD_MFPL_PD6MFP_Msk          (0xful << SYS_GPD_MFPL_PD6MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD6MFP Mask              */
+
+#define SYS_GPD_MFPL_PD7MFP_Pos          (28)                                              /*!< SYS_T::GPD_MFPL: PD7MFP Position          */
+#define SYS_GPD_MFPL_PD7MFP_Msk          (0xful << SYS_GPD_MFPL_PD7MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD7MFP Mask              */
+
+#define SYS_GPD_MFPH_PD8MFP_Pos          (0)                                               /*!< SYS_T::GPD_MFPH: PD8MFP Position          */
+#define SYS_GPD_MFPH_PD8MFP_Msk          (0xful << SYS_GPD_MFPH_PD8MFP_Pos)                /*!< SYS_T::GPD_MFPH: PD8MFP Mask              */
+
+#define SYS_GPD_MFPH_PD9MFP_Pos          (4)                                               /*!< SYS_T::GPD_MFPH: PD9MFP Position          */
+#define SYS_GPD_MFPH_PD9MFP_Msk          (0xful << SYS_GPD_MFPH_PD9MFP_Pos)                /*!< SYS_T::GPD_MFPH: PD9MFP Mask              */
+
+#define SYS_GPD_MFPH_PD10MFP_Pos         (8)                                               /*!< SYS_T::GPD_MFPH: PD10MFP Position         */
+#define SYS_GPD_MFPH_PD10MFP_Msk         (0xful << SYS_GPD_MFPH_PD10MFP_Pos)              /*!< SYS_T::GPD_MFPH: PD10MFP Mask              */
+
+#define SYS_GPD_MFPH_PD11MFP_Pos         (12)                                              /*!< SYS_T::GPD_MFPH: PD11MFP Position         */
+#define SYS_GPD_MFPH_PD11MFP_Msk         (0xful << SYS_GPD_MFPH_PD11MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD11MFP Mask             */
+
+#define SYS_GPD_MFPH_PD12MFP_Pos         (16)                                              /*!< SYS_T::GPD_MFPH: PD12MFP Position         */
+#define SYS_GPD_MFPH_PD12MFP_Msk         (0xful << SYS_GPD_MFPH_PD12MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD12MFP Mask             */
+
+#define SYS_GPD_MFPH_PD13MFP_Pos         (20)                                              /*!< SYS_T::GPD_MFPH: PD13MFP Position         */
+#define SYS_GPD_MFPH_PD13MFP_Msk         (0xful << SYS_GPD_MFPH_PD13MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD13MFP Mask             */
+
+#define SYS_GPD_MFPH_PD14MFP_Pos         (24)                                              /*!< SYS_T::GPD_MFPH: PD14MFP Position         */
+#define SYS_GPD_MFPH_PD14MFP_Msk         (0xful << SYS_GPD_MFPH_PD14MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD14MFP Mask             */
+
+#define SYS_GPD_MFPH_PD15MFP_Pos         (28)                                              /*!< SYS_T::GPD_MFPH: PD15MFP Position         */
+#define SYS_GPD_MFPH_PD15MFP_Msk         (0xful << SYS_GPD_MFPH_PD15MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD15MFP Mask             */
+
+#define SYS_GPE_MFPL_PE0MFP_Pos          (0)                                               /*!< SYS_T::GPE_MFPL: PE0MFP Position          */
+#define SYS_GPE_MFPL_PE0MFP_Msk          (0xful << SYS_GPE_MFPL_PE0MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE0MFP Mask              */
+
+#define SYS_GPE_MFPL_PE1MFP_Pos          (4)                                               /*!< SYS_T::GPE_MFPL: PE1MFP Position          */
+#define SYS_GPE_MFPL_PE1MFP_Msk          (0xful << SYS_GPE_MFPL_PE1MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE1MFP Mask              */
+
+#define SYS_GPE_MFPL_PE2MFP_Pos          (8)                                               /*!< SYS_T::GPE_MFPL: PE2MFP Position          */
+#define SYS_GPE_MFPL_PE2MFP_Msk          (0xful << SYS_GPE_MFPL_PE2MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE2MFP Mask              */
+
+#define SYS_GPE_MFPL_PE3MFP_Pos          (12)                                              /*!< SYS_T::GPE_MFPL: PE3MFP Position          */
+#define SYS_GPE_MFPL_PE3MFP_Msk          (0xful << SYS_GPE_MFPL_PE3MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE3MFP Mask              */
+
+#define SYS_GPE_MFPL_PE4MFP_Pos          (16)                                              /*!< SYS_T::GPE_MFPL: PE4MFP Position          */
+#define SYS_GPE_MFPL_PE4MFP_Msk          (0xful << SYS_GPE_MFPL_PE4MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE4MFP Mask              */
+
+#define SYS_GPE_MFPL_PE5MFP_Pos          (20)                                              /*!< SYS_T::GPE_MFPL: PE5MFP Position          */
+#define SYS_GPE_MFPL_PE5MFP_Msk          (0xful << SYS_GPE_MFPL_PE5MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE5MFP Mask              */
+
+#define SYS_GPE_MFPL_PE6MFP_Pos          (24)                                              /*!< SYS_T::GPE_MFPL: PE6MFP Position          */
+#define SYS_GPE_MFPL_PE6MFP_Msk          (0xful << SYS_GPE_MFPL_PE6MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE6MFP Mask              */
+
+#define SYS_GPE_MFPL_PE7MFP_Pos          (28)                                              /*!< SYS_T::GPE_MFPL: PE7MFP Position          */
+#define SYS_GPE_MFPL_PE7MFP_Msk          (0xful << SYS_GPE_MFPL_PE7MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE7MFP Mask              */
+
+#define SYS_GPE_MFPH_PE8MFP_Pos          (0)                                               /*!< SYS_T::GPE_MFPH: PE8MFP Position          */
+#define SYS_GPE_MFPH_PE8MFP_Msk          (0xful << SYS_GPE_MFPH_PE8MFP_Pos)                /*!< SYS_T::GPE_MFPH: PE8MFP Mask              */
+
+#define SYS_GPE_MFPH_PE9MFP_Pos          (4)                                               /*!< SYS_T::GPE_MFPH: PE9MFP Position          */
+#define SYS_GPE_MFPH_PE9MFP_Msk          (0xful << SYS_GPE_MFPH_PE9MFP_Pos)                /*!< SYS_T::GPE_MFPH: PE9MFP Mask              */
+
+#define SYS_GPE_MFPH_PE10MFP_Pos         (8)                                               /*!< SYS_T::GPE_MFPH: PE10MFP Position         */
+#define SYS_GPE_MFPH_PE10MFP_Msk         (0xful << SYS_GPE_MFPH_PE10MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE10MFP Mask             */
+
+#define SYS_GPE_MFPH_PE11MFP_Pos         (12)                                              /*!< SYS_T::GPE_MFPH: PE11MFP Position         */
+#define SYS_GPE_MFPH_PE11MFP_Msk         (0xful << SYS_GPE_MFPH_PE11MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE11MFP Mask             */
+
+#define SYS_GPE_MFPH_PE12MFP_Pos         (16)                                              /*!< SYS_T::GPE_MFPH: PE12MFP Position         */
+#define SYS_GPE_MFPH_PE12MFP_Msk         (0xful << SYS_GPE_MFPH_PE12MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE12MFP Mask             */
+
+#define SYS_GPE_MFPH_PE13MFP_Pos         (20)                                              /*!< SYS_T::GPE_MFPH: PE13MFP Position         */
+#define SYS_GPE_MFPH_PE13MFP_Msk         (0xful << SYS_GPE_MFPH_PE13MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE13MFP Mask             */
+
+#define SYS_GPE_MFPH_PE14MFP_Pos         (24)                                              /*!< SYS_T::GPE_MFPH: PE14MFP Position         */
+#define SYS_GPE_MFPH_PE14MFP_Msk         (0xful << SYS_GPE_MFPH_PE14MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE14MFP Mask             */
+
+#define SYS_GPF_MFPL_PF0MFP_Pos          (0)                                               /*!< SYS_T::GPF_MFPL: PF0MFP Position          */
+#define SYS_GPF_MFPL_PF0MFP_Msk          (0xful << SYS_GPF_MFPL_PF0MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF0MFP Mask              */
+
+#define SYS_GPF_MFPL_PF1MFP_Pos          (4)                                               /*!< SYS_T::GPF_MFPL: PF1MFP Position          */
+#define SYS_GPF_MFPL_PF1MFP_Msk          (0xful << SYS_GPF_MFPL_PF1MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF1MFP Mask              */
+
+#define SYS_GPF_MFPL_PF2MFP_Pos          (8)                                               /*!< SYS_T::GPF_MFPL: PF2MFP Position          */
+#define SYS_GPF_MFPL_PF2MFP_Msk          (0xful << SYS_GPF_MFPL_PF2MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF2MFP Mask              */
+
+#define SYS_GPF_MFPL_PF3MFP_Pos          (12)                                              /*!< SYS_T::GPF_MFPL: PF3MFP Position          */
+#define SYS_GPF_MFPL_PF3MFP_Msk          (0xful << SYS_GPF_MFPL_PF3MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF3MFP Mask              */
+
+#define SYS_GPF_MFPL_PF4MFP_Pos          (16)                                              /*!< SYS_T::GPF_MFPL: PF4MFP Position          */
+#define SYS_GPF_MFPL_PF4MFP_Msk          (0xful << SYS_GPF_MFPL_PF4MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF4MFP Mask              */
+
+#define SYS_GPF_MFPL_PF5MFP_Pos          (20)                                              /*!< SYS_T::GPF_MFPL: PF5MFP Position          */
+#define SYS_GPF_MFPL_PF5MFP_Msk          (0xful << SYS_GPF_MFPL_PF5MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF5MFP Mask              */
+
+#define SYS_GPF_MFPL_PF6MFP_Pos          (24)                                              /*!< SYS_T::GPF_MFPL: PF6MFP Position          */
+#define SYS_GPF_MFPL_PF6MFP_Msk          (0xful << SYS_GPF_MFPL_PF6MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF6MFP Mask              */
+
+#define SYS_GPF_MFPL_PF7MFP_Pos          (28)                                              /*!< SYS_T::GPF_MFPL: PF7MFP Position          */
+#define SYS_GPF_MFPL_PF7MFP_Msk          (0xful << SYS_GPF_MFPL_PF7MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF7MFP Mask              */
+
+#define SYS_SRAM_INTCTL_PERRIEN_Pos      (0)                                               /*!< SYS_T::SRAM_INTCTL: PERRIEN Position      */
+#define SYS_SRAM_INTCTL_PERRIEN_Msk      (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos)            /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask          */
+
+#define SYS_SRAM_STATUS_PERRIF_Pos       (0)                                               /*!< SYS_T::SRAM_STATUS: PERRIF Position       */
+#define SYS_SRAM_STATUS_PERRIF_Msk       (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos)             /*!< SYS_T::SRAM_STATUS: PERRIF Mask           */
+
+#define SYS_SRAM_ERRADDR_ERRADDR_Pos     (0)                                               /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position     */
+#define SYS_SRAM_ERRADDR_ERRADDR_Msk     (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos)    /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask         */
+
+#define SYS_SRAM_BISTCTL_SRBIST0_Pos     (0)                                               /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position     */
+#define SYS_SRAM_BISTCTL_SRBIST0_Msk     (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos)           /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask         */
+
+#define SYS_SRAM_BISTCTL_SRBIST1_Pos     (1)                                               /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position     */
+#define SYS_SRAM_BISTCTL_SRBIST1_Msk     (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos)           /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask         */
+
+#define SYS_SRAM_BISTCTL_CRBIST_Pos      (2)                                               /*!< SYS_T::SRAM_BISTCTL: CRBIST Position      */
+#define SYS_SRAM_BISTCTL_CRBIST_Msk      (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos)            /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask          */
+
+#define SYS_SRAM_BISTCTL_CANBIST_Pos     (3)                                               /*!< SYS_T::SRAM_BISTCTL: CANBIST Position     */
+#define SYS_SRAM_BISTCTL_CANBIST_Msk     (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos)           /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask         */
+
+#define SYS_SRAM_BISTCTL_USBBIST_Pos     (4)                                               /*!< SYS_T::SRAM_BISTCTL: USBBIST Position     */
+#define SYS_SRAM_BISTCTL_USBBIST_Msk     (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos)           /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask         */
+
+#define SYS_SRAM_BISTSTS_SRBISTEF0_Pos   (0)                                               /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position   */
+#define SYS_SRAM_BISTSTS_SRBISTEF0_Msk   (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos)         /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask       */
+
+#define SYS_SRAM_BISTSTS_SRBISTEF1_Pos   (1)                                               /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position   */
+#define SYS_SRAM_BISTSTS_SRBISTEF1_Msk   (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos)         /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask       */
+
+#define SYS_SRAM_BISTSTS_CRBISTEF_Pos    (2)                                               /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position    */
+#define SYS_SRAM_BISTSTS_CRBISTEF_Msk    (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos)          /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask        */
+
+#define SYS_SRAM_BISTSTS_CANBEF_Pos      (3)                                               /*!< SYS_T::SRAM_BISTSTS: CANBEF Position      */
+#define SYS_SRAM_BISTSTS_CANBEF_Msk      (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos)            /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask          */
+
+#define SYS_SRAM_BISTSTS_USBBEF_Pos      (4)                                               /*!< SYS_T::SRAM_BISTSTS: USBBEF Position      */
+#define SYS_SRAM_BISTSTS_USBBEF_Msk      (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos)            /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask          */
+
+#define SYS_SRAM_BISTSTS_SRBEND0_Pos     (16)                                              /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position     */
+#define SYS_SRAM_BISTSTS_SRBEND0_Msk     (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos)           /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask         */
+
+#define SYS_SRAM_BISTSTS_SRBEND1_Pos     (17)                                              /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position     */
+#define SYS_SRAM_BISTSTS_SRBEND1_Msk     (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos)           /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask         */
+
+#define SYS_SRAM_BISTSTS_CRBEND_Pos      (18)                                              /*!< SYS_T::SRAM_BISTSTS: CRBEND Position      */
+#define SYS_SRAM_BISTSTS_CRBEND_Msk      (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos)            /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask          */
+
+#define SYS_SRAM_BISTSTS_CANBEND_Pos     (19)                                              /*!< SYS_T::SRAM_BISTSTS: CANBEND Position     */
+#define SYS_SRAM_BISTSTS_CANBEND_Msk     (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos)           /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask         */
+
+#define SYS_SRAM_BISTSTS_USBBEND_Pos     (20)                                              /*!< SYS_T::SRAM_BISTSTS: USBBEND Position     */
+#define SYS_SRAM_BISTSTS_USBBEND_Msk     (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos)           /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask         */
+
+#define SYS_IRCTCTL_FREQSEL_Pos          (0)                                               /*!< SYS_T::IRCTCTL: FREQSEL Position          */
+#define SYS_IRCTCTL_FREQSEL_Msk          (0x3ul << SYS_IRCTCTL_FREQSEL_Pos)                /*!< SYS_T::IRCTCTL: FREQSEL Mask              */
+
+#define SYS_IRCTCTL_LOOPSEL_Pos          (4)                                               /*!< SYS_T::IRCTCTL: LOOPSEL Position          */
+#define SYS_IRCTCTL_LOOPSEL_Msk          (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos)                /*!< SYS_T::IRCTCTL: LOOPSEL Mask              */
+
+#define SYS_IRCTCTL_RETRYCNT_Pos         (6)                                               /*!< SYS_T::IRCTCTL: RETRYCNT Position         */
+#define SYS_IRCTCTL_RETRYCNT_Msk         (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos)               /*!< SYS_T::IRCTCTL: RETRYCNT Mask             */
+
+#define SYS_IRCTCTL_CESTOPEN_Pos         (8)                                               /*!< SYS_T::IRCTCTL: CESTOPEN Position         */
+#define SYS_IRCTCTL_CESTOPEN_Msk         (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos)               /*!< SYS_T::IRCTCTL: CESTOPEN Mask             */
+
+#define SYS_IRCTIEN_TFAILIEN_Pos         (1)                                               /*!< SYS_T::IRCTIEN: TFAILIEN Position         */
+#define SYS_IRCTIEN_TFAILIEN_Msk         (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos)               /*!< SYS_T::IRCTIEN: TFAILIEN Mask             */
+
+#define SYS_IRCTIEN_CLKEIEN_Pos          (2)                                               /*!< SYS_T::IRCTIEN: CLKEIEN Position          */
+#define SYS_IRCTIEN_CLKEIEN_Msk          (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos)                /*!< SYS_T::IRCTIEN: CLKEIEN Mask              */
+
+#define SYS_IRCTISTS_FREQLOCK_Pos        (0)                                               /*!< SYS_T::IRCTISTS: FREQLOCK Position        */
+#define SYS_IRCTISTS_FREQLOCK_Msk        (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos)              /*!< SYS_T::IRCTISTS: FREQLOCK Mask            */
+
+#define SYS_IRCTISTS_TFAILIF_Pos         (1)                                               /*!< SYS_T::IRCTISTS: TFAILIF Position         */
+#define SYS_IRCTISTS_TFAILIF_Msk         (0x1ul << SYS_IRCTISTS_TFAILIF_Pos)               /*!< SYS_T::IRCTISTS: TFAILIF Mask             */
+
+#define SYS_IRCTISTS_CLKERRIF_Pos        (2)                                               /*!< SYS_T::IRCTISTS: CLKERRIF Position        */
+#define SYS_IRCTISTS_CLKERRIF_Msk        (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos)              /*!< SYS_T::IRCTISTS: CLKERRIF Mask            */
+
+#define SYS_REGLCTL_REGLCTL_Pos          (0)                                               /*!< SYS_T::REGLCTL: REGLCTL Position          */
+#define SYS_REGLCTL_REGLCTL_Msk          (0xfful << SYS_REGLCTL_REGLCTL_Pos)               /*!< SYS_T::REGLCTL: REGLCTL Mask              */
+
+/**@}*/ /* SYS_CONST */
+
+
+typedef struct
+{
+
+/**
+ * @var SYS_INT_T::NMIEN
+ * Offset: 0x00  NMI Source Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |BODOUT    |BOD NMI Source Enable (Write Protect)
+ * |        |          |0 = BOD NMI source Disabled.
+ * |        |          |1 = BOD NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.    
+ * |[1]     |IRC_INT   |IRC TRIM NMI Source Enable (Write Protect)
+ * |        |          |0 = IRC TRIM NMI source Disabled.
+ * |        |          |1 = IRC TRIM NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.   
+ * |[2]     |PWRWU_INT |Power-Down Mode Wake-Up NMI Source Enable (Write Protect)
+ * |        |          |0 = Power-down mode wake-up NMI source Disabled.
+ * |        |          |1 = Power-down mode wake-up NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.    
+ * |[3]     |SRAM_PERR   |SRAM ParityCheck Error NMI Source Enable (Write Protect)
+ * |        |          |0 = SRAM parity check error NMI source Disabled.
+ * |        |          |1 = SRAM parity check error NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.    
+ * |[4]     |CLKFAIL   |Clock Fail Detected NMI Source Enable (Write Protect)
+ * |        |          |0 = Clock fail detected interrupt NMI source Disabled.
+ * |        |          |1 = Clock fail detected interrupt NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.    
+ * |[6]     |RTC_INT   |RTC NMI Source Enable (Write Protect)
+ * |        |          |0 = RTC NMI source Disabled.
+ * |        |          |1 = RTC NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.    
+ * |[7]     |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect)
+ * |        |          |0 = Backup register tamper detected interrupt.NMI source Disabled.
+ * |        |          |1 = Backup register tamper detected interrupt.NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.     
+ * |[8]     |EINT0     |External Interrupt From PA.0, PD.2 Or PE.4 Pin NMI Source Enable (Write Protect)
+ * |        |          |0 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Disabled.
+ * |        |          |1 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.        
+ * |[9]     |EINT1     |External Interrupt From PB.0, PD.3 Or PE.5 Pin NMI Source Enable (Write Protect)
+ * |        |          |0 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Disabled.
+ * |        |          |1 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[10]    |EINT2     |External Interrupt From PC.0 Pin NMI Source Enable (Write Protect)
+ * |        |          |0 = External interrupt from PC.0 pin NMI source Disabled.
+ * |        |          |1 = External interrupt from PC.0 pin NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.       
+ * |[11]    |EINT3     |External Interrupt From PD.0 Pin NMI Source Enable (Write Protect)
+ * |        |          |0 = External interrupt from PD.0 pin NMI source Disabled.
+ * |        |          |1 = External interrupt from PD.0 pin NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.     
+ * |[12]    |EINT4     |External Interrupt From PE.0 Pin NMI Source Enable (Write Protect)
+ * |        |          |0 = External interrupt from PE.0 pin NMI source Disabled.
+ * |        |          |1 = External interrupt from PE.0 pin NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.      
+ * |[13]    |EINT5     |External Interrupt From PF.0 Pin NMI Source Enable (Write Protect)
+ * |        |          |0 = External interrupt from PF.0 pin NMI source Disabled.
+ * |        |          |1 = External interrupt from PF.0 pin NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.     
+ * |[14]    |UART0_INT |UART0 NMI Source Enable (Write Protect)
+ * |        |          |0 = UART0 NMI source Disabled.
+ * |        |          |1 = UART0 NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.    
+ * |[15]    |UART1_INT |UART1 NMI Source Enable (Write Protect)
+ * |        |          |0 = UART1 NMI source Disabled.
+ * |        |          |1 = UART1 NMI source Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_INT_T::NMISTS
+ * Offset: 0x04  NMI source interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |BODOUT    |BOD Interrupt Flag (Read Only)
+ * |        |          |0 = BOD interrupt is deasserted.
+ * |        |          |1 = BOD interrupt is asserted. 
+ * |[1]     |IRC_INT   |IRC TRIM Interrupt Flag (Read Only)
+ * |        |          |0 = HIRC TRIM interrupt is deasserted.
+ * |        |          |1 = HIRC TRIM interrupt is asserted. 
+ * |[2]     |PWRWU_INT |Power-Down Mode Wake-Up Interrupt Flag (Read Only)
+ * |        |          |0 = Power-down mode wake-up interrupt is deasserted.
+ * |        |          |1 = Power-down mode wake-up interrupt is asserted. 
+ * |[3]     |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only)
+ * |        |          |0 = SRAM parity check error interrupt is deasserted.
+ * |        |          |1 = SRAM parity check error interrupt is asserted. 
+ * |[4]     |CLKFAIL   |Clock Fail Detected Interrupt Flag (Read Only)
+ * |        |          |0 = Clock fail detected interrupt is deasserted.
+ * |        |          |1 = Clock fail detected interrupt is asserted.
+ * |[6]     |RTC_INT   |RTC Interrupt Flag (Read Only)
+ * |        |          |0 = RTC interrupt is deasserted.
+ * |        |          |1 = RTC interrupt is asserted.
+ * |[7]     |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only)
+ * |        |          |0 = Backup register tamper detected interrupt is deasserted.
+ * |        |          |1 = Backup register tamper detected interrupt is asserted.
+ * |[8]     |EINT0     |External Interrupt From PA.0, PD.2 Or PE.4 Pin Interrupt Flag (Read Only)
+ * |        |          |0 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is deasserted.
+ * |        |          |1 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is asserted. 
+ * |[9]     |EINT1     |External Interrupt From PB.0, PD.3 Or PE.5 Pin Interrupt Flag (Read Only)
+ * |        |          |0 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is deasserted.
+ * |        |          |1 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is asserted. 
+ * |[10]    |EINT2     |External Interrupt From PC.0 Pin Interrupt Flag (Read Only)
+ * |        |          |0 = External Interrupt from PC.0 interrupt is deasserted.
+ * |        |          |1 = External Interrupt from PC.0 interrupt is asserted. 
+ * |[11]    |EINT3     |External Interrupt From PD.0 Pin Interrupt Flag (Read Only)
+ * |        |          |0 = External Interrupt from PD.0 interrupt is deasserted.
+ * |        |          |1 = External Interrupt from PD.0 interrupt is asserted. 
+ * |[12]    |EINT4     |External Interrupt From PE.0 Pin Interrupt Flag (Read Only)
+ * |        |          |0 = External Interrupt from PE.0 interrupt is deasserted.
+ * |        |          |1 = External Interrupt from PE.0 interrupt is asserted. 
+ * |[13]    |EINT5     |External Interrupt From PF.0 Pin Interrupt Flag (Read Only)
+ * |        |          |0 = External Interrupt from PF.0 interrupt is deasserted.
+ * |        |          |1 = External Interrupt from PF.0 interrupt is asserted. 
+ * |[14]    |UART0_INT |UART0 Interrupt Flag (Read Only)
+ * |        |          |0 = UART1 interrupt is deasserted.
+ * |        |          |1 = UART1 interrupt is asserted.
+ * |[15]    |UART1_INT |UART1 Interrupt Flag (Read Only)
+ * |        |          |0 = UART1 interrupt is deasserted.
+ * |        |          |1 = UART1 interrupt is asserted.
+ */
+
+    __IO  uint32_t NMIEN;          /* Offset: 0x00  NMI Source Interrupt Enable Register                               */
+    __I   uint32_t NMISTS;         /* Offset: 0x04  NMI source interrupt Status Register                               */
+
+} SYS_INT_T;
+
+
+
+/**
+    @addtogroup INT_CONST INT Bit Field Definition
+    Constant Definitions for SYS Controller
+@{ */
+
+#define SYS_NMIEN_BODOUT_Pos             (0)                                               /*!< SYS_INT_T::NMIEN: BODOUT Position         */
+#define SYS_NMIEN_BODOUT_Msk             (0x1ul << SYS_NMIEN_BODOUT_Pos )                  /*!< SYS_INT_T::NMIEN: BODOUT Mask             */
+
+#define SYS_NMIEN_IRC_INT_Pos            (1)                                               /*!< SYS_INT_T::NMIEN: IRC_INT Position        */
+#define SYS_NMIEN_IRC_INT_Msk            (0x1ul << SYS_NMIEN_IRC_INT_Pos )                 /*!< SYS_INT_T::NMIEN: IRC_INT Mask            */
+
+#define SYS_NMIEN_PWRWU_INT_Pos          (2)                                               /*!< SYS_INT_T::NMIEN: PWRWU_INT Position      */
+#define SYS_NMIEN_PWRWU_INT_Msk          (0x1ul << SYS_NMIEN_PWRWU_INT_Pos )               /*!< SYS_INT_T::NMIEN: PWRWU_INT Mask          */
+
+#define SYS_NMIEN_SRAM_PERR_Pos          (3)                                               /*!< SYS_INT_T::NMIEN: SRAM_PERR Position      */
+#define SYS_NMIEN_SRAM_PERR_Msk          (0x1ul << SYS_NMIEN_SRAM_PERR_Pos )               /*!< SYS_INT_T::NMIEN: SRAM_PERR Mask          */
+
+#define SYS_NMIEN_CLKFAIL_Pos            (4)                                               /*!< SYS_INT_T::NMIEN: CLKFAIL Position        */
+#define SYS_NMIEN_CLKFAIL_Msk            (0x1ul << SYS_NMIEN_CLKFAIL_Pos )                 /*!< SYS_INT_T::NMIEN: CLKFAIL Mask            */
+
+#define SYS_NMIEN_RTC_INT_Pos            (6)                                               /*!< SYS_INT_T::NMIEN: RTC_INT Position        */
+#define SYS_NMIEN_RTC_INT_Msk            (0x1ul << SYS_NMIEN_RTC_INT_Pos )                 /*!< SYS_INT_T::NMIEN: RTC_INT Mask            */
+
+#define SYS_NMIEN_TAMPER_INT_Pos         (7)                                               /*!< SYS_INT_T::NMIEN: TAMPER_INT Position     */
+#define SYS_NMIEN_TAMPER_INT_Msk         (0x1ul << SYS_NMIEN_TAMPER_INT_Pos )              /*!< SYS_INT_T::NMIEN: TAMPER_INT Mask         */
+
+#define SYS_NMIEN_EINT0_Pos              (8)                                               /*!< SYS_INT_T::NMIEN: EINT0 Position          */
+#define SYS_NMIEN_EINT0_Msk              (0x1ul << SYS_NMIEN_EINT0_Pos )                   /*!< SYS_INT_T::NMIEN: EINT0 Mask              */
+
+#define SYS_NMIEN_EINT1_Pos              (9)                                               /*!< SYS_INT_T::NMIEN: EINT1 Position          */
+#define SYS_NMIEN_EINT1_Msk              (0x1ul << SYS_NMIEN_EINT1_Pos )                   /*!< SYS_INT_T::NMIEN: EINT1 Mask              */
+
+#define SYS_NMIEN_EINT2_Pos              (10)                                              /*!< SYS_INT_T::NMIEN: EINT2 Position          */
+#define SYS_NMIEN_EINT2_Msk              (0x1ul << SYS_NMIEN_EINT2_Pos )                   /*!< SYS_INT_T::NMIEN: EINT2 Mask              */
+
+#define SYS_NMIEN_EINT3_Pos              (11)                                              /*!< SYS_INT_T::NMIEN: EINT3 Position          */
+#define SYS_NMIEN_EINT3_Msk              (0x1ul << SYS_NMIEN_EINT3_Pos )                   /*!< SYS_INT_T::NMIEN: EINT3 Mask              */
+
+#define SYS_NMIEN_EINT4_Pos              (12)                                              /*!< SYS_INT_T::NMIEN: EINT4 Position          */
+#define SYS_NMIEN_EINT4_Msk              (0x1ul << SYS_NMIEN_EINT4_Pos )                   /*!< SYS_INT_T::NMIEN: EINT4 Mask              */
+
+#define SYS_NMIEN_EINT5_Pos              (13)                                              /*!< SYS_INT_T::NMIEN: EINT5 Position          */
+#define SYS_NMIEN_EINT5_Msk              (0x1ul << SYS_NMIEN_EINT5_Pos )                   /*!< SYS_INT_T::NMIEN: EINT5 Mask              */
+
+#define SYS_NMIEN_UART0_INT_Pos          (14)                                              /*!< SYS_INT_T::NMIEN: UART0_INT Position      */
+#define SYS_NMIEN_UART0_INT_Msk          (0x1ul << SYS_NMIEN_UART0_INT_Pos )               /*!< SYS_INT_T::NMIEN: UART0_INT Mask          */
+
+#define SYS_NMIEN_UART1_INT_Pos          (15)                                              /*!< SYS_INT_T::NMIEN: UART1_INT Position      */
+#define SYS_NMIEN_UART1_INT_Msk          (0x1ul << SYS_NMIEN_UART1_INT_Pos )               /*!< SYS_INT_T::NMIEN: UART1_INT Mask          */
+
+#define SYS_NMISTS_BODOUT_Pos            (0)                                               /*!< SYS_INT_T::NMISTS: BODOUT Position        */
+#define SYS_NMISTS_BODOUT_Msk            (0x1ul << SYS_NMISTS_BODOUT_Pos )                 /*!< SYS_INT_T::NMISTS: BODOUT Mask            */
+
+#define SYS_NMISTS_IRC_INT_Pos           (1)                                               /*!< SYS_INT_T::NMISTS: IRC_INT Position       */
+#define SYS_NMISTS_IRC_INT_Msk           (0x1ul << SYS_NMISTS_IRC_INT_Pos )                /*!< SYS_INT_T::NMISTS: IRC_INT Mask           */
+
+#define SYS_NMISTS_PWRWU_INT_Pos         (2)                                               /*!< SYS_INT_T::NMISTS: PWRWU_INT Position     */
+#define SYS_NMISTS_PWRWU_INT_Msk         (0x1ul << SYS_NMISTS_PWRWU_INT_Pos )              /*!< SYS_INT_T::NMISTS: PWRWU_INT Mask         */
+
+#define SYS_NMISTS_SRAM_PERR_Pos         (3)                                               /*!< SYS_INT_T::NMISTS: SRAM_PERR Position     */
+#define SYS_NMISTS_SRAM_PERR_Msk         (0x1ul << SYS_NMISTS_SRAM_PERR_Pos )              /*!< SYS_INT_T::NMISTS: SRAM_PERR Mask         */
+
+#define SYS_NMISTS_CLKFAIL_Pos           (4)                                               /*!< SYS_INT_T::NMISTS: CLKFAIL Position       */
+#define SYS_NMISTS_CLKFAIL_Msk           (0x1ul << SYS_NMISTS_CLKFAIL_Pos )                /*!< SYS_INT_T::NMISTS: CLKFAIL Mask           */
+
+#define SYS_NMISTS_RTC_INT_Pos           (6)                                               /*!< SYS_INT_T::NMISTS: RTC_INT Position       */
+#define SYS_NMISTS_RTC_INT_Msk           (0x1ul << SYS_NMISTS_RTC_INT_Pos )                /*!< SYS_INT_T::NMISTS: RTC_INT Mask           */
+
+#define SYS_NMISTS_TAMPER_INT_Pos        (7)                                               /*!< SYS_INT_T::NMISTS: TAMPER_INT Position    */
+#define SYS_NMISTS_TAMPER_INT_Msk        (0x1ul << SYS_NMISTS_TAMPER_INT_Pos )             /*!< SYS_INT_T::NMISTS: TAMPER_INT Mask        */
+
+#define SYS_NMISTS_EINT0_Pos             (8)                                               /*!< SYS_INT_T::NMISTS: EINT0 Position         */
+#define SYS_NMISTS_EINT0_Msk             (0x1ul << SYS_NMISTS_EINT0_Pos )                  /*!< SYS_INT_T::NMISTS: EINT0 Mask             */
+
+#define SYS_NMISTS_EINT1_Pos             (9)                                               /*!< SYS_INT_T::NMISTS: EINT1 Position         */
+#define SYS_NMISTS_EINT1_Msk             (0x1ul << SYS_NMISTS_EINT1_Pos )                  /*!< SYS_INT_T::NMISTS: EINT1 Mask             */
+
+#define SYS_NMISTS_EINT2_Pos             (10)                                              /*!< SYS_INT_T::NMISTS: EINT2 Position         */
+#define SYS_NMISTS_EINT2_Msk             (0x1ul << SYS_NMISTS_EINT2_Pos )                  /*!< SYS_INT_T::NMISTS: EINT2 Mask             */
+
+#define SYS_NMISTS_EINT3_Pos             (11)                                              /*!< SYS_INT_T::NMISTS: EINT3 Position         */
+#define SYS_NMISTS_EINT3_Msk             (0x1ul << SYS_NMISTS_EINT3_Pos )                  /*!< SYS_INT_T::NMISTS: EINT3 Mask             */
+
+#define SYS_NMISTS_EINT4_Pos             (12)                                              /*!< SYS_INT_T::NMISTS: EINT4 Position         */
+#define SYS_NMISTS_EINT4_Msk             (0x1ul << SYS_NMISTS_EINT4_Pos )                  /*!< SYS_INT_T::NMISTS: EINT4 Mask             */
+
+#define SYS_NMISTS_EINT5_Pos             (13)                                              /*!< SYS_INT_T::NMISTS: EINT5 Position         */
+#define SYS_NMISTS_EINT5_Msk             (0x1ul << SYS_NMISTS_EINT5_Pos )                  /*!< SYS_INT_T::NMISTS: EINT5 Mask             */
+
+#define SYS_NMISTS_UART0_INT_Pos         (14)                                              /*!< SYS_INT_T::NMISTS: UART0_INT Position     */
+#define SYS_NMISTS_UART0_INT_Msk         (0x1ul << SYS_NMISTS_UART0_INT_Pos )              /*!< SYS_INT_T::NMISTS: UART0_INT Mask         */
+
+#define SYS_NMISTS_UART1_INT_Pos         (15)                                              /*!< SYS_INT_T::NMISTS: UART1_INT Position     */
+#define SYS_NMISTS_UART1_INT_Msk         (0x1ul << SYS_NMISTS_UART1_INT_Pos )              /*!< SYS_INT_T::NMISTS: UART1_INT Mask         */
+
+/**@}*/ /* INT_CONST */
+/**@}*/ /* end of SYS register group */
+
+
+/*---------------------- Touch Key Controller -------------------------*/
+/**
+    @addtogroup TK Touch Key Controller(TK)
+    Memory Mapped Structure for TK Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var TK_T::CTL
+ * Offset: 0x00  Touch Key Scan Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |TKSEN0    |TK0 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN0 (TK_REFCTL[0]) is "1" except SCANALL (TK_REFCTL[23]) is "1".
+ * |        |          |0 = TKDAT0 (TK_DAT0[7:0]) is invalid.
+ * |        |          |1 = TK0 is always enable for Touch Key scan. TKDAT0 (TK_DAT0[7:0]) is valid.
+ * |[1]     |TKSEN1    |TK1 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN1 (TK_REFCTL[1]) is "1".
+ * |        |          |0 = TKDAT1 (TK_DAT0[15:8]) is invalid.
+ * |        |          |1 = TK1 is always enable for Touch Key scan. TKDAT1 (TK_DAT0[15:8]) is valid.
+ * |[2]     |TKSEN2    |TK2 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN2 (TK_REFCTL[2]) is "1".
+ * |        |          |0 = TKDAT2 (TK_DAT0[23:16]) is invalid.
+ * |        |          |1 = TK2 is always enable for Touch Key scan. TKDAT2 (TK_DAT0[23:16]) is valid.
+ * |[3]     |TKSEN3    |TK3 Scan Enable Bit
+ * |        |          |0 = TKDAT3 (TK_DAT0[31:24]) is invalid.
+ * |        |          |1 = TK3 is always enable for Touch Key scan. TKDAT3 (TK_DAT0[31:24]) is valid.
+ * |        |          |This bit is ignored if TKREN3 (TK_REFCTL[3]) is "1".
+ * |[4]     |TKSEN4    |TK4 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN4 (TK_REFCTL[4]) is "1".
+ * |        |          |0 = TKDAT4 (TK_DAT1[7:0]) is invalid.
+ * |        |          |1 = TK4 is always enable for Touch Key scan. TKDAT4 (TK_DAT1[7:0]) is valid.
+ * |[5]     |TKSEN5    |TK5 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN5 (TK_REFCTL[5]) is "1".
+ * |        |          |0 = TKDAT5 (TK_DAT1[15:8]) is invalid.
+ * |        |          |1 = TK5 is always enable for Touch Key scan. TKDAT5 (TK_DAT1[15:8]) is valid.
+ * |[6]     |TKSEN6    |TK6 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN6 (TK_REFCTL[6]) is "1".
+ * |        |          |0 = TKDAT6 (TK_DAT1[23:16]) is invalid.
+ * |        |          |1 = TK6 is always enable for Touch Key scan. TKDAT6 (TK_DAT1[23:16]) is valid.
+ * |[7]     |TKSEN7    |TK7 Scan Enable
+ * |        |          |This bit is ignored if TKREN7 (TK_REFCTL[7]) is "1".
+ * |        |          |0 = TKDAT7 (TK_DAT1[31:24]) is invalid.
+ * |        |          |1 = TK7 is always enable for Touch Key scan. TKDAT7 (TK_DAT1[31:24]) is valid.
+ * |[8]     |TKSEN8    |TK8 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN8 (TK_REFCTL[8]) is "1".
+ * |        |          |0 = TKDAT8 (TK_DAT2[7:0]) is invalid.
+ * |        |          |1 = TK8 is always enable for Touch Key scan. TKDAT8 (TK_DAT2[7:0]) is valid.
+ * |[9]     |TKSEN9    |TK9 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN9 (TK_REFCTL[9]) is "1".
+ * |        |          |0 = TKDAT9 (TK_DAT2[15:8]) is invalid.
+ * |        |          |1 = TK9 is always enable for Touch Key scan. TKDAT9 (TK_DAT2[15:8]) is valid.
+ * |[10]    |TKSEN10   |TK10 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN10 (TK_REFCTL[10]) is "1".
+ * |        |          |0 = TKDAT10 (TK_DAT2[23:16]) is invalid.
+ * |        |          |1 = TK10 is always enable for Touch Key scan. TKDAT10 (TK_DAT2[23:16]) is valid.
+ * |[11]    |TKSEN11   |TK11 Scan Enable
+ * |        |          |This bit is ignored if TKREN11 (TK_REFCTL[11]) is "1".
+ * |        |          |0 = TKDAT11 (TK_DAT2[31:24]) is invalid.
+ * |        |          |1 = TK11 is always enable for Touch Key scan. TKDAT11 (TK_DAT2[31:24]) is valid.
+ * |[12]    |TKSEN12   |TK12 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN12 (TK_REFCTL[12]) is "1".
+ * |        |          |0 = TKDAT12 (TK_DAT3[7:0]) is invalid.
+ * |        |          |1 = TK12 is always enable for Touch Key scan. TKDAT12 (TK_DAT3[7:0]) is valid.
+ * |[13]    |TKSEN13   |TK13 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN13 (TK_REFCTL[13]) is "1".
+ * |        |          |0 = TKDAT13 (TK_DAT3[15:8]) is invalid.
+ * |        |          |1 = TK13 is always enable for key scan. TKDAT13 (TK_DAT3[15:8]) is valid.
+ * |[14]    |TKSEN14   |TK14 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN14 (TK_REFCTL[14]) is "1".
+ * |        |          |0 = TKDAT14 (TK_DAT3[23:16]) is invalid.
+ * |        |          |1 = TK14 is always enabled for key scan. TKDAT14 (TK_DAT3[23:16]) is valid.
+ * |[15]    |TKSEN15   |TK15 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN15 (TK_REFCTL[15]) is "1".
+ * |        |          |0 = TKDAT15 (TK_DAT3[31:24]) is invalid.
+ * |        |          |1 = TK15 is always enabled for key scan. TKDAT15 (TK_DAT3[31:24]) is valid.
+ * |[16]    |TKSEN16   |TK16 Scan Enable Bit
+ * |        |          |This bit is ignored if TKREN16 (TK_REFCTL[16]) is "1".
+ * |        |          |0 = TKDAT16 (TK_DAT4[7:0]) is invalid.
+ * |        |          |1 = TK16 is always enabled for key scan. TKDAT16 (TK_DAT4[7:0]) is valid.
+ * |[22:20] |AVCCHSEL  |AVCCH Voltage Select
+ * |        |          |000 = 1/16 VDD.
+ * |        |          |001 = 1/8 VDD.
+ * |        |          |010 = 3/16 VDD.
+ * |        |          |011 = 1/4 VDD.
+ * |        |          |100 = 5/16 VDD.
+ * |        |          |101 = 3/8 VDD.
+ * |        |          |110 = 7/16 VDD.
+ * |        |          |111 = 1/2 VDD.
+ * |[24]    |SCAN      |Scan
+ * |        |          |Write an '1' to this bit will immediately initiate key scan on all channels which are enabled.
+ * |        |          |This bit will be self-cleared after key scan started.
+ * |[25]    |TMRTRGEN  |Timer Trigger Enable Bit
+ * |        |          |0 = Disable timer to trigger key scan.
+ * |        |          |1 = Enable timer triggers key scan periodically. Key scan will be initiated by Timer0 periodically.
+ * |[31]    |TKEN      |Touch Key Scan Enable Bit
+ * |        |          |0 = Disable Touch Key Function.
+ * |        |          |1 = Enable Touch Key Function.
+ * @var TK_T::REFCTL
+ * Offset: 0x04  Touch Key Reference Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |TKREN0    |TK0 Reference Enable Bit
+ * |        |          |0 = TK0 is not reference.
+ * |        |          |1 = TK0 is set as reference, and TKDAT0 (TK_DAT0[7:0]) is invalid except SCANALL (TK_REFCTL[23]) is "1".
+ * |[1]     |TKREN1    |TK1 Reference Enable Bit
+ * |        |          |0 = TK1 is not reference.
+ * |        |          |1 = TK1 is set as reference, and TKDAT1 (TK_DAT0[15:8]) is invalid.
+ * |[2]     |TKREN2    |TK2 Reference Enable Bit
+ * |        |          |0 = TK2 is not reference.
+ * |        |          |1 = TK2 is set as reference, and TKDAT2 (TK_DAT0[23:16]) is invalid.
+ * |[3]     |TKREN3    |TK3 Reference Enable Bit
+ * |        |          |0 = TK3 is not reference.
+ * |        |          |1 = TK3 is set as reference, and TKDAT3 (TK_DAT0[31:24]) is invalid.
+ * |[4]     |TKREN4    |TK4 Reference Enable Bit
+ * |        |          |0 = TK4 is not reference.
+ * |        |          |1 = TK4 is set as reference, and TKDAT4 (TK_DAT1[7:0]) is invalid.
+ * |[5]     |TKREN5    |TK5 Reference Enable Bit
+ * |        |          |0 = TK5 is not reference.
+ * |        |          |1 = TK5 is set as reference, and TKDAT5 (TK_DAT1[15:8]) is invalid.
+ * |[6]     |TKREN6    |TK6 Reference Enable Bit
+ * |        |          |0 = TK6 is not reference.
+ * |        |          |1 = TK6 is set as reference, and TKDAT6 (TK_DAT1[23:16]) is invalid.
+ * |[7]     |TKREN7    |TK7 Reference Enable Bit
+ * |        |          |0 = TK7 is not reference.
+ * |        |          |1 = TK7 is set as reference, and TKDAT7 (TK_DAT1[31:24]) is invalid.
+ * |[8]     |TKREN8    |TK8 Reference Enable Bit
+ * |        |          |0 = TK8 is not reference.
+ * |        |          |1 = TK8 is set as reference, and TKDAT8 (TK_DAT2[7:0]) is invalid.
+ * |[9]     |TKREN9    |TK9 Reference Enable Bit
+ * |        |          |0 = TK9 is not reference.
+ * |        |          |1 = TK9 is set as reference, and TKDAT9 (TK_DAT2[15:8]) is invalid.
+ * |[10]    |TKREN10   |TK10 Reference Enable Bit
+ * |        |          |0 = TK10 is not reference.
+ * |        |          |1 = TK10 is set as reference, and TKDAT10 (TK_DAT2[23:16]) is invalid.
+ * |[11]    |TKREN11   |TK11 Reference Enable Bit
+ * |        |          |0 = TK11 is not reference.
+ * |        |          |1 = TK11 is set as reference, and TKDAT11 (TK_DAT2[31:24]) is invalid.
+ * |[12]    |TKREN12   |TK12 Reference Enable Bit
+ * |        |          |0 = TK12 is not reference.
+ * |        |          |1 = TK12 is set as reference, and TKDAT12 (TK_DAT3[7:0]) is invalid.
+ * |[13]    |TKREN13   |TK13 Reference Enable Bit
+ * |        |          |0 = TK13 is not reference.
+ * |        |          |1 = TK13 is set as reference, and TKDAT13 (TK_DAT3[15:8]) is invalid.
+ * |[14]    |TKREN14   |TK14 Reference Enable Bit
+ * |        |          |0 = TK14 is not reference.
+ * |        |          |1 = TK14 is set as reference, and TKDAT14 (TK_DAT3[23:16]) is invalid.
+ * |[15]    |TKREN15   |TK15 Reference Enable Bit
+ * |        |          |0 = TK15 is not reference.
+ * |        |          |1 = TK15 is set as reference, and TKDAT15 (TK_DAT3[31:24]) is invalid.
+ * |[16]    |TKREN16   |TK16 Reference Enable Bit
+ * |        |          |0 = TK16 is not reference.
+ * |        |          |1 = TK16 is set as reference, and TKDAT16 (TK_DAT4[7:0]) is invalid.
+ * |        |          |Note: This bit is forced to "1" automatically if none is set as reference.
+ * |[23]    |SCANALL   |All Key Scan Enable Bit
+ * |        |          |This function is used for low power key scanning operation.
+ * |        |          |TKDAT0 (TK_DAT0[7:0]) is the only one valid data when key scan is complete.
+ * |        |          |0 = Disable All Keys Scan function.
+ * |        |          |1 = Enable All Keys Scan function.
+ * |[25:24] |SENTCTL   |Touch Key Sensing Time Control
+ * |        |          |00 = 128 x SENPTCTL.
+ * |        |          |01 = 255 x SENPTCTL.
+ * |        |          |10 = 511 x SENPTCTL.
+ * |        |          |11 = 1023 x SENPTCTL.
+ * |[29:28] |SENPTCTL  |Touch Key Sensing Pulse Width Time Control
+ * |        |          |00 = 1us.
+ * |        |          |01 = 2us.
+ * |        |          |10 = 4us.
+ * |        |          |11 = 8us.
+ * @var TK_T::CCBDAT0
+ * Offset: 0x08  Touch Key Complement Capacitor Bank Data Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |CCBDAT0   |TK0 Complement CB Data
+ * |        |          |This is register is used for TK0 sensitivity adjustment.
+ * |[15:8]  |CCBDAT1   |TK1 Complement CB Data
+ * |        |          |This is register is used for TK1 sensitivity adjustment.
+ * |[23:16] |CCBDAT2   |TK2 Complement CB Data
+ * |        |          |This is register is used for TK2 sensitivity adjustment.
+ * |[31:24] |CCBDAT3   |TK3 Complement CB Data
+ * |        |          |This is register is used for TK3 sensitivity adjustment.
+ * @var TK_T::CCBDAT1
+ * Offset: 0x0C  Touch Key Complement Capacitor Bank Data Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |CCBDAT4   |TK4 Complement CB Data
+ * |        |          |This is register is used for TK4 sensitivity adjustment.
+ * |[15:8]  |CCBDAT5   |TK5 Complement CB Data
+ * |        |          |This is register is used for TK5 sensitivity adjustment.
+ * |[23:16] |CCBDAT6   |TK6 Complement CB Data
+ * |        |          |This is register is used for TK6 sensitivity adjustment.
+ * |[31:24] |CCBDAT7   |TK7 Complement CB Data
+ * |        |          |This is register is used for TK7 sensitivity adjustment.
+ * @var TK_T::CCBDAT2
+ * Offset: 0x10  Touch Key Complement Capacitor Bank Data Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |CCBDAT8   |TK8 Complement CB Data
+ * |        |          |This is register is used for TK8 sensitivity adjustment.
+ * |[15:8]  |CCBDAT9   |TK9 Complement CB Data
+ * |        |          |This is register is used for TK9 sensitivity adjustment.
+ * |[23:16] |CCBDAT10  |TK10 Complement CB Data
+ * |        |          |This is register is used for TK10 sensitivity adjustment.
+ * |[31:24] |CCBDAT11  |TK11 Complement CB Data
+ * |        |          |This is register is used for TK11 sensitivity adjustment.
+ * @var TK_T::CCBDAT3
+ * Offset: 0x14  Touch Key Complement Capacitor Bank Data Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |CCBDAT12  |TK12 Complement CB Data
+ * |        |          |This is register is used for TK12 sensitivity adjustment.
+ * |[15:8]  |CCBDAT13  |TK13 Complement CB Data
+ * |        |          |This is register is used for TK13 sensitivity adjustment.
+ * |[23:16] |CCBDAT14  |TK14 Complement CB Data
+ * |        |          |This is register is used for TK14 sensitivity adjustment.
+ * |[31:24] |CCBDAT15  |TK15 Complement CB Data
+ * |        |          |This is register is used for TK15 sensitivity adjustment.
+ * @var TK_T::CCBDAT4
+ * Offset: 0x18  Touch Key Complement Capacitor Bank Data Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |CCBDAT16  |TK16 Complement CB Data
+ * |        |          |This is register is used for TK16 sensitivity adjustment.
+ * |[31:24] |REFCBDAT  |Reference CB Data
+ * @var TK_T::IDLESEL
+ * Offset: 0x1C  Touch Key Idle State Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |IDLSn     |TKn Idle State Control
+ * |        |          |This register is ignored if both TKSENn (TK_CTL[n]) and POLENn (TK_POLCTL[n+8]) are "0" or TKRENn (TK_REFCTL[n]) is "1".
+ * |        |          |00 = TKn connected to GND.
+ * |        |          |01 = TKn connected to AVCCH.
+ * |        |          |10 = TKn connected to VDD.
+ * |        |          |11 = TKn connected to VDD.
+ * |        |          |n = 0 to 15.
+ * @var TK_T::POLSEL
+ * Offset: 0x20  Touch Key Polarity Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |POLSELn   |TKn Polarity Select
+ * |        |          |This register is ignored if POLENn (TK_POLCTL[n+8]) is "0", or either TKSENn (TK_CTL[n]) or TKRENn (TK_REFCTL[n]) is "1".
+ * |        |          |00 = TKn connected to Gnd.
+ * |        |          |01 = TKn connected to AVCCH.
+ * |        |          |10 = TKn connected to VDD.
+ * |        |          |11 = TKn connected to VDD.
+ * @var TK_T::POLCTL
+ * Offset: 0x24  Touch Key Polarity Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |IDLS16    |TK16 Idle State Control
+ * |        |          |This register is ignored if both TKSEN16 (TK_CTL[16]) and POLEN16 (TK_POLCTL[24]) are "0" or TKREN16 (TK_REFCTL[16]) is "1".
+ * |        |          |00 = TK16 connected to Gnd.
+ * |        |          |01 = TK16 connected to AVCCH.
+ * |        |          |10 = TK16 connected to VDD.
+ * |        |          |11 = TK16 connected to VDD.
+ * |[3:2]   |POLSEL16  |TK16 Polarity Control
+ * |        |          |This register is ignored if POLEN16 (TK_POLCTL[24]) is "0", or either TKSEN16 (TK_CTL[16]) or TKREN16 (TK_REFCTL[16]) is "1".
+ * |        |          |00 = TK16 connected to Gnd.
+ * |        |          |01 = TK16 connected to AVCCH.
+ * |        |          |10 = TK16 connected to VDD.
+ * |        |          |11 = TK16 connected to VDD.
+ * |[5:4]   |CBPOLSEL  |Capacitor Bank Polarity Select
+ * |        |          |00 = Gnd.
+ * |        |          |01 = AVCCH.
+ * |        |          |10 = VDD.
+ * |        |          |11 = VDD.
+ * |[8]     |POLEN0    |TK0 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[9]     |POLEN1    |TK1 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[10]    |POLEN2    |TK2 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[11]    |POLEN3    |TK3 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[12]    |POLEN4    |TK4 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[13]    |POLEN5    |TK5 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[14]    |POLEN6    |TK6 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[15]    |POLEN7    |TK7 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[16]    |POLEN8    |TK8 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[17]    |POLEN9    |TK9 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[18]    |POLEN10   |TK10 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[19]    |POLEN11   |TK11 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[20]    |POLEN12   |TK12 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[21]    |POLEN13   |TK13 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[22]    |POLEN14   |TK14 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[23]    |POLEN15   |TK15 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[24]    |POLEN16   |TK16 Polarity Function Enable Control
+ * |        |          |0 = Disabled.
+ * |        |          |1 = Enabled.
+ * |[31]    |SPOTINIT  |Touch Key Sensing Initial Potential Control
+ * |        |          |0 = Key pad is connected to Gnd before sensing.
+ * |        |          |1 = Key pad is connected to AVCCH before sensing.
+ * @var TK_T::STATUS
+ * Offset: 0x28  Touch Key Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |BUSY      |Touch Key Busy (Read Only)
+ * |        |          |0 = Key scan is complete or stopped.
+ * |        |          |1 = Key scan is proceeding.
+ * |[1]     |SCIF      |Touch Key Scan Complete Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = Key scan is proceeding and data is not ready for read.
+ * |        |          |1 = Key scan is complete and data is ready for read in TKDATx registers.
+ * |        |          |Note1: The Touch Key interrupt asserts if SCINTEN bit of TK_INTEN register is set.
+ * |        |          |Note2: The Touch Key interrupt also asserts if SCTHIEN bit of TK_INTEN register is set and any channel data value is greater/less than its threshold setting
+ * |[8]     |TKIF0     |TK0 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK0.
+ * |        |          |1 = Threshold control event occurs with TK0.
+ * |[9]     |TKIF1     |TK1 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK1.
+ * |        |          |1 = Threshold control event occurs with TK1.
+ * |[10]    |TKIF2     |TK2 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK2.
+ * |        |          |1 = Threshold control event occurs with TK2.
+ * |[11]    |TKIF3     |TK3 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK3.
+ * |        |          |1 = Threshold control event occurs with TK3.
+ * |[12]    |TKIF4     |TK4 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK4.
+ * |        |          |1 = Threshold control event occurs with TK4.
+ * |[13]    |TKIF5     |TK5 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK5.
+ * |        |          |1 = Threshold control event occurs with TK5.
+ * |[14]    |TKIF6     |TK6 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK6.
+ * |        |          |1 = Threshold control event occurs with TK6.
+ * |[15]    |TKIF7     |TK7 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK7.
+ * |        |          |1 = Threshold control event occurs with TK7.
+ * |[16]    |TKIF8     |TK8 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK8.
+ * |        |          |1 = Threshold control event occurs with TK8.
+ * |[17]    |TKIF9     |TK9 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK9.
+ * |        |          |1 = Threshold control event occurs with TK9.
+ * |[18]    |TKIF10    |TK10 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK10.
+ * |        |          |1 = Threshold control event occurs with TK10.
+ * |[19]    |TKIF11    |TK11 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK11.
+ * |        |          |1 = Threshold control event occurs with TK11.
+ * |[20]    |TKIF12    |TK12 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK12.
+ * |        |          |1 = Threshold control event occurs with TK12.
+ * |[21]    |TKIF13    |TK13 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK13.
+ * |        |          |1 = Threshold control event occurs with TK13.
+ * |[22]    |TKIF14    |TK14 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK14.
+ * |        |          |1 = Threshold control event occurs with TK14.
+ * |[23]    |TKIF15    |TK15 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK15.
+ * |        |          |1 = Threshold control event occurs with TK15.
+ * |[24]    |TKIF16    |TK16 Interrupt Flag
+ * |        |          |This bit will be cleared by writing a "1" to this bit.
+ * |        |          |0 = No threshold control event with TK16.
+ * |        |          |1 = Threshold control event occurs with TK16.
+ * @var TK_T::DAT0
+ * Offset: 0x2C  Touch Key Data Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |TKDAT0    |TK0 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN0 (TK_CTL[0]) is "0" or TKREN0 (TK_REFCTL[0]) is "1" except SCANALL (TK_REFCTL[23]) is "1".
+ * |[15:8]  |TKDAT1    |TK1 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN1 (TK_CTL[1]) is "0" or TKREN1 (TK_REFCTL[1]) is "1".
+ * |[23:16] |TKDAT2    |TK2 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN2 (TK_CTL[2]) is "0" or TKREN2 (TK_REFCTL[2]) is "1".
+ * |[31:24] |TKDAT3    |TK3 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN3 (TK_CTL[3]) is "0" or TKREN3 (TK_REFCTL[3]) is "1".
+ * @var TK_T::DAT1
+ * Offset: 0x30  Touch Key Data Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |TKDAT4    |TK0 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN4 (TK_CTL[4]) is "0" or TKREN4 (TK_REFCTL[4]) is "1".
+ * |[15:8]  |TKDAT5    |TK5 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN5 (TK_CTL[5]) is "0" or TKREN5 (TK_REFCTL[5]) is "1".
+ * |[23:16] |TKDAT6    |TK6 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN6 (TK_CTL[6]) is "0" or TKREN6 (TK_REFCTL[6]) is "1".
+ * |[31:24] |TKDAT7    |TK7 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN7 (TK_CTL[7]) is "0" or TKREN7 (TK_REFCTL[7]) is "1".
+ * @var TK_T::DAT2
+ * Offset: 0x34  Touch Key Data Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |TKDAT8    |TK8 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN8 (TK_CTL[8]) is "0" or TKREN8 (TK_REFCTL[8]) is "1".
+ * |[15:8]  |TKDAT9    |TK9 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN9 (TK_CTL[9]) is "0" or TKREN9 (TK_REFCTL[9]) is "1".
+ * |[23:16] |TKDAT10   |TK10 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN10 (TK_CTL[10]) is "0" or TKREN10 (TK_REFCTL[10]) is "1".
+ * |[31:24] |TKDAT11   |TK11 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN11 (TK_CTL[11]) is "0" or TKREN11 (TK_REFCTL[11]) is "1".
+ * @var TK_T::DAT3
+ * Offset: 0x38  Touch Key Data Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |TKDAT12   |TK12 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN12 (TK_CTL[12]) is "0" or TKREN12 (TK_REFCTL[12]) is "1".
+ * |[15:8]  |TKDAT13   |TK13 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN13 (TK_CTL[13]) is "0" or TKREN13 (TK_REFCTL[13]) is "1".
+ * |[23:16] |TKDAT14   |TK14 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN14 (TK_CTL[14]) is "0" or TKREN14 (TK_REFCTL[14]) is "1".
+ * |[31:24] |TKDAT15   |TK15 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN15 (TK_CTL[15]) is "0" or TKREN15 (TK_REFCTL[15]) is "1".
+ * @var TK_T::DAT4
+ * Offset: 0x3C  Touch Key Data Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |TKDAT16   |TK16 Sensing Result Data (Read Only)
+ * |        |          |This data is invalid if TKSEN16 (TK_CTL[16]) is "0" or TKREN16 (TK_REFCTL[16]) is "1".
+ * @var TK_T::INTEN
+ * Offset: 0x40  Touch Key Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SCTHIEN   |Touch Key Scan Complete With High/Low Threshold Control Interrupt Enable Bit
+ * |        |          |0 = Key scan complete with threshold control interrupt is disable.
+ * |        |          |1 = Key scan complete with threshold control interrupt is enable.
+ * |[1]     |SCINTEN   |Touch Key Scan Complete Interrupt Enable
+ * |        |          |Bit
+ * |        |          |0 = Key scan complete without threshold control interrupt is disable.
+ * |        |          |1 = Key scan complete without threshold control interrupt is enable.
+ * |[31]    |THIMOD    |Touch Key Threshold Interrupt Mode Select
+ * |        |          |0 = Edge trigger mode.
+ * |        |          |1 = Level trigger mode.
+ * @var TK_T::TH0_1
+ * Offset: 0x44  Touch Key TK0/TK1 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |LTH0      |Low Threshold Of TK0
+ * |        |          |Low level for TK0 threshold control.
+ * |[15:8]  |HTH0      |High Threshold Of TK0
+ * |        |          |High level for TK0 threshold control.
+ * |[23:16] |LTH1      |Low Threshold Of TK1
+ * |        |          |Low level for TK1 threshold control.
+ * |[31:24] |HTH1      |High Threshold Of TK1
+ * |        |          |High level for TK1 threshold control.
+ * @var TK_T::TH2_3
+ * Offset: 0x48  Touch Key TK2/TK3 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |LTH2      |Low Threshold Of TK2
+ * |        |          |Low level for TK2 threshold control.
+ * |[15:8]  |HTH2      |High Threshold Of TK2
+ * |        |          |High level for TK2 threshold control.
+ * |[23:16] |LTH3      |Low Threshold Of TK3
+ * |        |          |Low level for TK3 threshold control.
+ * |[31:24] |HTH3      |High Threshold Of TK3
+ * |        |          |High level for TK3 threshold control.
+ * @var TK_T::TH4_5
+ * Offset: 0x4C  Touch Key TK4/TK5 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |LTH4      |Low Threshold Of TK4
+ * |        |          |Low level for TK4 threshold control.
+ * |[15:8]  |HTH4      |High Threshold Of TK4
+ * |        |          |High level for TK4 threshold control.
+ * |[23:16] |LTH5      |Low Threshold Of TK5
+ * |        |          |Low level for TK5 threshold control.
+ * |[31:24] |HTH5      |High Threshold Of TK5
+ * |        |          |High level for TK5 threshold control.
+ * @var TK_T::TH6_7
+ * Offset: 0x50  Touch Key TK6/TK7 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |LTH6      |Low Threshold Of TK6
+ * |        |          |Low level for TK6 threshold control.
+ * |[15:8]  |HTH6      |High Threshold Of TK6
+ * |        |          |High level for TK6 threshold control.
+ * |[23:16] |LTH7      |Low Threshold Of TK7
+ * |        |          |Low level for TK7 threshold control.
+ * |[31:24] |HTH7      |High Threshold Of TK7
+ * |        |          |High level for TK7 threshold control.
+ * @var TK_T::TH8_9
+ * Offset: 0x54  Touch Key TK8/TK9 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |LTH8      |Low Threshold Of TK8
+ * |        |          |Low level for TK8 threshold control.
+ * |[15:8]  |HTH8      |High Threshold Of TK8
+ * |        |          |High level for TK8 threshold control.
+ * |[23:16] |LTH9      |Low Threshold Of TK9
+ * |        |          |Low level for TK9 threshold control.
+ * |[31:24] |HTH9      |High Threshold Of TK9
+ * |        |          |High level for TK9 threshold control.
+ * @var TK_T::TH10_11
+ * Offset: 0x58  Touch Key TK10/TK11 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |LTH10     |Low Threshold Of TK10
+ * |        |          |Low level for TK10 threshold control.
+ * |[15:8]  |HTH10     |High Threshold Of TK10
+ * |        |          |High level for TK10 threshold control.
+ * |[23:16] |LTH11     |Low Threshold Of TK11
+ * |        |          |Low level for TK11 threshold control.
+ * |[31:24] |HTH11     |High Threshold Of TK11
+ * |        |          |High level for TK11 threshold control.
+ * @var TK_T::TH12_13
+ * Offset: 0x5C  Touch Key TK12/TK13 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |LTH12     |Low Threshold Of TK12
+ * |        |          |Low level for TK12 threshold control.
+ * |[15:8]  |HTH12     |High Threshold Of TK12
+ * |        |          |High level for TK12 threshold control.
+ * |[23:16] |LTH13     |Low Threshold Of TK13
+ * |        |          |Low level for TK13 threshold control.
+ * |[31:24] |HTH13     |High Threshold Of TK13
+ * |        |          |High level for TK13 threshold control.
+ * @var TK_T::TH14_15
+ * Offset: 0x60  Touch Key TK14/TK15 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |LTH14     |Low Threshold Of TK14
+ * |        |          |Low level for TK14 threshold control.
+ * |[15:8]  |HTH14     |High Threshold Of TK14
+ * |        |          |High level for TK14 threshold control.
+ * |[23:16] |LTH15     |Low Threshold Of TK15
+ * |        |          |Low level for TK15 threshold control.
+ * |[31:24] |HTH15     |High Threshold Of TK15
+ * |        |          |High level for TK15 threshold control.
+ * @var TK_T::TH16
+ * Offset: 0x64  Touch Key TK16 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |LTH16     |Low Threshold Of TK16
+ * |        |          |Low level for TK16 threshold control.
+ * |[15:8]  |HTH16     |High Threshold Of TK16
+ * |        |          |High level for TK16 threshold control.
+ */
+
+    __IO uint32_t CTL;           /* Offset: 0x00  Touch Key Scan Control Register                                    */
+    __IO uint32_t REFCTL;        /* Offset: 0x04  Touch Key Reference Control Register                               */
+    __IO uint32_t CCBDAT0;       /* Offset: 0x08  Touch Key Complement Capacitor Bank Data Register 0                */
+    __IO uint32_t CCBDAT1;       /* Offset: 0x0C  Touch Key Complement Capacitor Bank Data Register 1                */
+    __IO uint32_t CCBDAT2;       /* Offset: 0x10  Touch Key Complement Capacitor Bank Data Register 2                */
+    __IO uint32_t CCBDAT3;       /* Offset: 0x14  Touch Key Complement Capacitor Bank Data Register 3                */
+    __IO uint32_t CCBDAT4;       /* Offset: 0x18  Touch Key Complement Capacitor Bank Data Register 4                */
+    __IO uint32_t IDLESEL;       /* Offset: 0x1C  Touch Key Idle State Control Register                              */
+    __IO uint32_t POLSEL;        /* Offset: 0x20  Touch Key Polarity Select Register                                 */
+    __IO uint32_t POLCTL;        /* Offset: 0x24  Touch Key Polarity Control Register                                */
+    __IO uint32_t STATUS;        /* Offset: 0x28  Touch Key Status Register                                          */
+    __I  uint32_t DAT0;          /* Offset: 0x2C  Touch Key Data Register 0                                          */
+    __I  uint32_t DAT1;          /* Offset: 0x30  Touch Key Data Register 1                                          */
+    __I  uint32_t DAT2;          /* Offset: 0x34  Touch Key Data Register 2                                          */
+    __I  uint32_t DAT3;          /* Offset: 0x38  Touch Key Data Register 3                                          */
+    __I  uint32_t DAT4;          /* Offset: 0x3C  Touch Key Data Register 4                                          */
+    __IO uint32_t INTEN;         /* Offset: 0x40  Touch Key Interrupt Enable Register                                */
+    __IO uint32_t TH0_1;         /* Offset: 0x44  Touch Key TK0/TK1 Threshold Control Register                       */
+    __IO uint32_t TH2_3;         /* Offset: 0x48  Touch Key TK2/TK3 Threshold Control Register                       */
+    __IO uint32_t TH4_5;         /* Offset: 0x4C  Touch Key TK4/TK5 Threshold Control Register                       */
+    __IO uint32_t TH6_7;         /* Offset: 0x50  Touch Key TK6/TK7 Threshold Control Register                       */
+    __IO uint32_t TH8_9;         /* Offset: 0x54  Touch Key TK8/TK9 Threshold Control Register                       */
+    __IO uint32_t TH10_11;       /* Offset: 0x58  Touch Key TK10/TK11 Threshold Control Register                     */
+    __IO uint32_t TH12_13;       /* Offset: 0x5C  Touch Key TK12/TK13 Threshold Control Register                     */
+    __IO uint32_t TH14_15;       /* Offset: 0x60  Touch Key TK14/TK15 Threshold Control Register                     */
+    __IO uint32_t TH16;          /* Offset: 0x64  Touch Key TK16 Threshold Control Register                          */
+
+} TK_T;
+
+
+
+/**
+    @addtogroup TK_CONST TK Bit Field Definition
+    Constant Definitions for TK Controller
+@{ */
+
+
+#define TK_CTL_TKSEN0_Pos                (0)                                               /*!< TK_T::CTL: TKSEN0 Position                */
+#define TK_CTL_TKSEN0_Msk                (0x1ul << TK_CTL_TKSEN0_Pos)                      /*!< TK_T::CTL: TKSEN0 Mask                    */
+
+#define TK_CTL_TKSEN1_Pos                (1)                                               /*!< TK_T::CTL: TKSEN1 Position                */
+#define TK_CTL_TKSEN1_Msk                (0x1ul << TK_CTL_TKSEN1_Pos)                      /*!< TK_T::CTL: TKSEN1 Mask                    */
+
+#define TK_CTL_TKSEN2_Pos                (2)                                               /*!< TK_T::CTL: TKSEN2 Position                */
+#define TK_CTL_TKSEN2_Msk                (0x1ul << TK_CTL_TKSEN2_Pos)                      /*!< TK_T::CTL: TKSEN2 Mask                    */
+
+#define TK_CTL_TKSEN3_Pos                (3)                                               /*!< TK_T::CTL: TKSEN3 Position                */
+#define TK_CTL_TKSEN3_Msk                (0x1ul << TK_CTL_TKSEN3_Pos)                      /*!< TK_T::CTL: TKSEN3 Mask                    */
+
+#define TK_CTL_TKSEN4_Pos                (4)                                               /*!< TK_T::CTL: TKSEN4 Position                */
+#define TK_CTL_TKSEN4_Msk                (0x1ul << TK_CTL_TKSEN4_Pos)                      /*!< TK_T::CTL: TKSEN4 Mask                    */
+
+#define TK_CTL_TKSEN5_Pos                (5)                                               /*!< TK_T::CTL: TKSEN5 Position                */
+#define TK_CTL_TKSEN5_Msk                (0x1ul << TK_CTL_TKSEN5_Pos)                      /*!< TK_T::CTL: TKSEN5 Mask                    */
+
+#define TK_CTL_TKSEN6_Pos                (6)                                               /*!< TK_T::CTL: TKSEN6 Position                */
+#define TK_CTL_TKSEN6_Msk                (0x1ul << TK_CTL_TKSEN6_Pos)                      /*!< TK_T::CTL: TKSEN6 Mask                    */
+
+#define TK_CTL_TKSEN7_Pos                (7)                                               /*!< TK_T::CTL: TKSEN7 Position                */
+#define TK_CTL_TKSEN7_Msk                (0x1ul << TK_CTL_TKSEN7_Pos)                      /*!< TK_T::CTL: TKSEN7 Mask                    */
+
+#define TK_CTL_TKSEN8_Pos                (8)                                               /*!< TK_T::CTL: TKSEN8 Position                */
+#define TK_CTL_TKSEN8_Msk                (0x1ul << TK_CTL_TKSEN8_Pos)                      /*!< TK_T::CTL: TKSEN8 Mask                    */
+
+#define TK_CTL_TKSEN9_Pos                (9)                                               /*!< TK_T::CTL: TKSEN9 Position                */
+#define TK_CTL_TKSEN9_Msk                (0x1ul << TK_CTL_TKSEN9_Pos)                      /*!< TK_T::CTL: TKSEN9 Mask                    */
+
+#define TK_CTL_TKSEN10_Pos               (10)                                              /*!< TK_T::CTL: TKSEN10 Position               */
+#define TK_CTL_TKSEN10_Msk               (0x1ul << TK_CTL_TKSEN10_Pos)                     /*!< TK_T::CTL: TKSEN10 Mask                   */
+
+#define TK_CTL_TKSEN11_Pos               (11)                                              /*!< TK_T::CTL: TKSEN11 Position               */
+#define TK_CTL_TKSEN11_Msk               (0x1ul << TK_CTL_TKSEN11_Pos)                     /*!< TK_T::CTL: TKSEN11 Mask                   */
+
+#define TK_CTL_TKSEN12_Pos               (12)                                              /*!< TK_T::CTL: TKSEN12 Position               */
+#define TK_CTL_TKSEN12_Msk               (0x1ul << TK_CTL_TKSEN12_Pos)                     /*!< TK_T::CTL: TKSEN12 Mask                   */
+
+#define TK_CTL_TKSEN13_Pos               (13)                                              /*!< TK_T::CTL: TKSEN13 Position               */
+#define TK_CTL_TKSEN13_Msk               (0x1ul << TK_CTL_TKSEN13_Pos)                     /*!< TK_T::CTL: TKSEN13 Mask                   */
+
+#define TK_CTL_TKSEN14_Pos               (14)                                              /*!< TK_T::CTL: TKSEN14 Position               */
+#define TK_CTL_TKSEN14_Msk               (0x1ul << TK_CTL_TKSEN14_Pos)                     /*!< TK_T::CTL: TKSEN14 Mask                   */
+
+#define TK_CTL_TKSEN15_Pos               (15)                                              /*!< TK_T::CTL: TKSEN15 Position               */
+#define TK_CTL_TKSEN15_Msk               (0x1ul << TK_CTL_TKSEN15_Pos)                     /*!< TK_T::CTL: TKSEN15 Mask                   */
+
+#define TK_CTL_TKSEN16_Pos               (16)                                              /*!< TK_T::CTL: TKSEN16 Position               */
+#define TK_CTL_TKSEN16_Msk               (0x1ul << TK_CTL_TKSEN16_Pos)                     /*!< TK_T::CTL: TKSEN16 Mask                   */
+
+#define TK_CTL_AVCCHSEL_Pos              (20)                                              /*!< TK_T::CTL: AVCCHSEL Position              */
+#define TK_CTL_AVCCHSEL_Msk              (0x7ul << TK_CTL_AVCCHSEL_Pos)                    /*!< TK_T::CTL: AVCCHSEL Mask                  */
+
+#define TK_CTL_SCAN_Pos                  (24)                                              /*!< TK_T::CTL: SCAN Position                  */
+#define TK_CTL_SCAN_Msk                  (0x1ul << TK_CTL_SCAN_Pos)                        /*!< TK_T::CTL: SCAN Mask                      */
+
+#define TK_CTL_TMRTRGEN_Pos              (25)                                              /*!< TK_T::CTL: TMRTRGEN Position              */
+#define TK_CTL_TMRTRGEN_Msk              (0x1ul << TK_CTL_TMRTRGEN_Pos)                    /*!< TK_T::CTL: TMRTRGEN Mask                  */
+
+#define TK_CTL_TKEN_Pos                  (31)                                              /*!< TK_T::CTL: TKEN Position                  */
+#define TK_CTL_TKEN_Msk                  (0x1ul << TK_CTL_TKEN_Pos)                        /*!< TK_T::CTL: TKEN Mask                      */
+
+#define TK_REFCTL_TKREN0_Pos             (0)                                               /*!< TK_T::REFCTL: TKREN0 Position             */
+#define TK_REFCTL_TKREN0_Msk             (0x1ul << TK_REFCTL_TKREN0_Pos)                   /*!< TK_T::REFCTL: TKREN0 Mask                 */
+
+#define TK_REFCTL_TKREN1_Pos             (1)                                               /*!< TK_T::REFCTL: TKREN1 Position             */
+#define TK_REFCTL_TKREN1_Msk             (0x1ul << TK_REFCTL_TKREN1_Pos)                   /*!< TK_T::REFCTL: TKREN1 Mask                 */
+
+#define TK_REFCTL_TKREN2_Pos             (2)                                               /*!< TK_T::REFCTL: TKREN2 Position             */
+#define TK_REFCTL_TKREN2_Msk             (0x1ul << TK_REFCTL_TKREN2_Pos)                   /*!< TK_T::REFCTL: TKREN2 Mask                 */
+
+#define TK_REFCTL_TKREN3_Pos             (3)                                               /*!< TK_T::REFCTL: TKREN3 Position             */
+#define TK_REFCTL_TKREN3_Msk             (0x1ul << TK_REFCTL_TKREN3_Pos)                   /*!< TK_T::REFCTL: TKREN3 Mask                 */
+
+#define TK_REFCTL_TKREN4_Pos             (4)                                               /*!< TK_T::REFCTL: TKREN4 Position             */
+#define TK_REFCTL_TKREN4_Msk             (0x1ul << TK_REFCTL_TKREN4_Pos)                   /*!< TK_T::REFCTL: TKREN4 Mask                 */
+
+#define TK_REFCTL_TKREN5_Pos             (5)                                               /*!< TK_T::REFCTL: TKREN5 Position             */
+#define TK_REFCTL_TKREN5_Msk             (0x1ul << TK_REFCTL_TKREN5_Pos)                   /*!< TK_T::REFCTL: TKREN5 Mask                 */
+
+#define TK_REFCTL_TKREN6_Pos             (6)                                               /*!< TK_T::REFCTL: TKREN6 Position             */
+#define TK_REFCTL_TKREN6_Msk             (0x1ul << TK_REFCTL_TKREN6_Pos)                   /*!< TK_T::REFCTL: TKREN6 Mask                 */
+
+#define TK_REFCTL_TKREN7_Pos             (7)                                               /*!< TK_T::REFCTL: TKREN7 Position             */
+#define TK_REFCTL_TKREN7_Msk             (0x1ul << TK_REFCTL_TKREN7_Pos)                   /*!< TK_T::REFCTL: TKREN7 Mask                 */
+
+#define TK_REFCTL_TKREN8_Pos             (8)                                               /*!< TK_T::REFCTL: TKREN8 Position             */
+#define TK_REFCTL_TKREN8_Msk             (0x1ul << TK_REFCTL_TKREN8_Pos)                   /*!< TK_T::REFCTL: TKREN8 Mask                 */
+
+#define TK_REFCTL_TKREN9_Pos             (9)                                               /*!< TK_T::REFCTL: TKREN9 Position             */
+#define TK_REFCTL_TKREN9_Msk             (0x1ul << TK_REFCTL_TKREN9_Pos)                   /*!< TK_T::REFCTL: TKREN9 Mask                 */
+
+#define TK_REFCTL_TKREN10_Pos            (10)                                              /*!< TK_T::REFCTL: TKREN10 Position            */
+#define TK_REFCTL_TKREN10_Msk            (0x1ul << TK_REFCTL_TKREN10_Pos)                  /*!< TK_T::REFCTL: TKREN10 Mask                */
+
+#define TK_REFCTL_TKREN11_Pos            (11)                                              /*!< TK_T::REFCTL: TKREN11 Position            */
+#define TK_REFCTL_TKREN11_Msk            (0x1ul << TK_REFCTL_TKREN11_Pos)                  /*!< TK_T::REFCTL: TKREN11 Mask                */
+
+#define TK_REFCTL_TKREN12_Pos            (12)                                              /*!< TK_T::REFCTL: TKREN12 Position            */
+#define TK_REFCTL_TKREN12_Msk            (0x1ul << TK_REFCTL_TKREN12_Pos)                  /*!< TK_T::REFCTL: TKREN12 Mask                */
+
+#define TK_REFCTL_TKREN13_Pos            (13)                                              /*!< TK_T::REFCTL: TKREN13 Position            */
+#define TK_REFCTL_TKREN13_Msk            (0x1ul << TK_REFCTL_TKREN13_Pos)                  /*!< TK_T::REFCTL: TKREN13 Mask                */
+
+#define TK_REFCTL_TKREN14_Pos            (14)                                              /*!< TK_T::REFCTL: TKREN14 Position            */
+#define TK_REFCTL_TKREN14_Msk            (0x1ul << TK_REFCTL_TKREN14_Pos)                  /*!< TK_T::REFCTL: TKREN14 Mask                */
+
+#define TK_REFCTL_TKREN15_Pos            (15)                                              /*!< TK_T::REFCTL: TKREN15 Position            */
+#define TK_REFCTL_TKREN15_Msk            (0x1ul << TK_REFCTL_TKREN15_Pos)                  /*!< TK_T::REFCTL: TKREN15 Mask                */
+
+#define TK_REFCTL_TKREN16_Pos            (16)                                              /*!< TK_T::REFCTL: TKREN16 Position            */
+#define TK_REFCTL_TKREN16_Msk            (0x1ul << TK_REFCTL_TKREN16_Pos)                  /*!< TK_T::REFCTL: TKREN16 Mask                */
+
+#define TK_REFCTL_SCANALL_Pos            (23)                                              /*!< TK_T::REFCTL: SCANALL Position            */
+#define TK_REFCTL_SCANALL_Msk            (0x1ul << TK_REFCTL_SCANALL_Pos)                  /*!< TK_T::REFCTL: SCANALL Mask                */
+
+#define TK_REFCTL_SENTCTL_Pos            (24)                                              /*!< TK_T::REFCTL: SENTCTL Position            */
+#define TK_REFCTL_SENTCTL_Msk            (0x3ul << TK_REFCTL_SENTCTL_Pos)                  /*!< TK_T::REFCTL: SENTCTL Mask                */
+
+#define TK_REFCTL_SENPTCTL_Pos           (28)                                              /*!< TK_T::REFCTL: SENPTCTL Position           */
+#define TK_REFCTL_SENPTCTL_Msk           (0x3ul << TK_REFCTL_SENPTCTL_Pos)                 /*!< TK_T::REFCTL: SENPTCTL Mask               */
+
+#define TK_CCBDAT0_CCBDAT0_Pos           (0)                                               /*!< TK_T::CCBDAT0: CCBDAT0 Position           */
+#define TK_CCBDAT0_CCBDAT0_Msk           (0xfful << TK_CCBDAT0_CCBDAT0_Pos)                /*!< TK_T::CCBDAT0: CCBDAT0 Mask               */
+
+#define TK_CCBDAT0_CCBDAT1_Pos           (8)                                               /*!< TK_T::CCBDAT0: CCBDAT1 Position           */
+#define TK_CCBDAT0_CCBDAT1_Msk           (0xfful << TK_CCBDAT0_CCBDAT1_Pos)                /*!< TK_T::CCBDAT0: CCBDAT1 Mask               */
+
+#define TK_CCBDAT0_CCBDAT2_Pos           (16)                                              /*!< TK_T::CCBDAT0: CCBDAT2 Position           */
+#define TK_CCBDAT0_CCBDAT2_Msk           (0xfful << TK_CCBDAT0_CCBDAT2_Pos)                /*!< TK_T::CCBDAT0: CCBDAT2 Mask               */
+
+#define TK_CCBDAT0_CCBDAT3_Pos           (24)                                              /*!< TK_T::CCBDAT0: CCBDAT3 Position           */
+#define TK_CCBDAT0_CCBDAT3_Msk           (0xfful << TK_CCBDAT0_CCBDAT3_Pos)                /*!< TK_T::CCBDAT0: CCBDAT3 Mask               */
+
+#define TK_CCBDAT1_CCBDAT4_Pos           (0)                                               /*!< TK_T::CCBDAT1: CCBDAT4 Position           */
+#define TK_CCBDAT1_CCBDAT4_Msk           (0xfful << TK_CCBDAT1_CCBDAT4_Pos)                /*!< TK_T::CCBDAT1: CCBDAT4 Mask               */
+
+#define TK_CCBDAT1_CCBDAT5_Pos           (8)                                               /*!< TK_T::CCBDAT1: CCBDAT5 Position           */
+#define TK_CCBDAT1_CCBDAT5_Msk           (0xfful << TK_CCBDAT1_CCBDAT5_Pos)                /*!< TK_T::CCBDAT1: CCBDAT5 Mask               */
+
+#define TK_CCBDAT1_CCBDAT6_Pos           (16)                                              /*!< TK_T::CCBDAT1: CCBDAT6 Position           */
+#define TK_CCBDAT1_CCBDAT6_Msk           (0xfful << TK_CCBDAT1_CCBDAT6_Pos)                /*!< TK_T::CCBDAT1: CCBDAT6 Mask               */
+
+#define TK_CCBDAT1_CCBDAT7_Pos           (24)                                              /*!< TK_T::CCBDAT1: CCBDAT7 Position           */
+#define TK_CCBDAT1_CCBDAT7_Msk           (0xfful << TK_CCBDAT1_CCBDAT7_Pos)                /*!< TK_T::CCBDAT1: CCBDAT7 Mask               */
+
+#define TK_CCBDAT2_CCBDAT8_Pos           (0)                                               /*!< TK_T::CCBDAT2: CCBDAT8 Position           */
+#define TK_CCBDAT2_CCBDAT8_Msk           (0xfful << TK_CCBDAT2_CCBDAT8_Pos)                /*!< TK_T::CCBDAT2: CCBDAT8 Mask               */
+
+#define TK_CCBDAT2_CCBDAT9_Pos           (8)                                               /*!< TK_T::CCBDAT2: CCBDAT9 Position           */
+#define TK_CCBDAT2_CCBDAT9_Msk           (0xfful << TK_CCBDAT2_CCBDAT9_Pos)                /*!< TK_T::CCBDAT2: CCBDAT9 Mask               */
+
+#define TK_CCBDAT2_CCBDAT10_Pos          (16)                                              /*!< TK_T::CCBDAT2: CCBDAT10 Position          */
+#define TK_CCBDAT2_CCBDAT10_Msk          (0xfful << TK_CCBDAT2_CCBDAT10_Pos)               /*!< TK_T::CCBDAT2: CCBDAT10 Mask              */
+
+#define TK_CCBDAT2_CCBDAT11_Pos          (24)                                              /*!< TK_T::CCBDAT2: CCBDAT11 Position          */
+#define TK_CCBDAT2_CCBDAT11_Msk          (0xfful << TK_CCBDAT2_CCBDAT11_Pos)               /*!< TK_T::CCBDAT2: CCBDAT11 Mask              */
+
+#define TK_CCBDAT3_CCBDAT12_Pos          (0)                                               /*!< TK_T::CCBDAT3: CCBDAT12 Position          */
+#define TK_CCBDAT3_CCBDAT12_Msk          (0xfful << TK_CCBDAT3_CCBDAT12_Pos)               /*!< TK_T::CCBDAT3: CCBDAT12 Mask              */
+
+#define TK_CCBDAT3_CCBDAT13_Pos          (8)                                               /*!< TK_T::CCBDAT3: CCBDAT13 Position          */
+#define TK_CCBDAT3_CCBDAT13_Msk          (0xfful << TK_CCBDAT3_CCBDAT13_Pos)               /*!< TK_T::CCBDAT3: CCBDAT13 Mask              */
+
+#define TK_CCBDAT3_CCBDAT14_Pos          (16)                                              /*!< TK_T::CCBDAT3: CCBDAT14 Position          */
+#define TK_CCBDAT3_CCBDAT14_Msk          (0xfful << TK_CCBDAT3_CCBDAT14_Pos)               /*!< TK_T::CCBDAT3: CCBDAT14 Mask              */
+
+#define TK_CCBDAT3_CCBDAT15_Pos          (24)                                              /*!< TK_T::CCBDAT3: CCBDAT15 Position          */
+#define TK_CCBDAT3_CCBDAT15_Msk          (0xfful << TK_CCBDAT3_CCBDAT15_Pos)               /*!< TK_T::CCBDAT3: CCBDAT15 Mask              */
+
+#define TK_CCBDAT4_CCBDAT16_Pos          (0)                                               /*!< TK_T::CCBDAT4: CCBDAT16 Position          */
+#define TK_CCBDAT4_CCBDAT16_Msk          (0xfful << TK_CCBDAT4_CCBDAT16_Pos)               /*!< TK_T::CCBDAT4: CCBDAT16 Mask              */
+
+#define TK_CCBDAT4_REFCBDAT_Pos          (24)                                              /*!< TK_T::CCBDAT4: REFCBDAT Position          */
+#define TK_CCBDAT4_REFCBDAT_Msk          (0xfful << TK_CCBDAT4_REFCBDAT_Pos)               /*!< TK_T::CCBDAT4: REFCBDAT Mask              */
+
+#define TK_IDLESEL_IDLS_Pos              (0)                                               /*!< TK_T::IDLESEL: IDLS Position              */
+#define TK_IDLESEL_IDLS_Msk              (0xfffffffful << TK_IDLESEL_IDLS_Pos)             /*!< TK_T::IDLESEL: IDLS Mask                  */
+
+#define TK_IDLESEL_IDLSn_Pos             (0)                                               /*!< TK_T::IDLESEL: IDLSn Position             */
+#define TK_IDLESEL_IDLSn_Msk             (0x3ul << TK_IDLESEL_IDLSn_Pos)                   /*!< TK_T::IDLESEL: IDLSn Mask                 */
+
+#define TK_POLSEL_POLSEL_Pos             (0)                                               /*!< TK_T::POLSEL: POLSEL Position             */
+#define TK_POLSEL_POLSEL_Msk             (0xfffffffful << TK_POLSEL_POLSEL_Pos)            /*!< TK_T::POLSEL: POLSEL Mask                 */
+
+#define TK_POLSEL_POLSELn_Pos            (0)                                               /*!< TK_T::POLSEL: POLSELn Position            */
+#define TK_POLSEL_POLSELn_Msk            (0x3ul << TK_POLSEL_POLSELn_Pos)                  /*!< TK_T::POLSEL: POLSELn Mask                */
+
+#define TK_POLCTL_IDLS16_Pos             (0)                                               /*!< TK_T::POLCTL: IDLS16 Position             */
+#define TK_POLCTL_IDLS16_Msk             (0x3ul << TK_POLCTL_IDLS16_Pos)                   /*!< TK_T::POLCTL: IDLS16 Mask                 */
+
+#define TK_POLCTL_POLSEL16_Pos           (2)                                               /*!< TK_T::POLCTL: POLSEL16 Position           */
+#define TK_POLCTL_POLSEL16_Msk           (0x3ul << TK_POLCTL_POLSEL16_Pos)                 /*!< TK_T::POLCTL: POLSEL16 Mask               */
+
+#define TK_POLCTL_CBPOLSEL_Pos           (4)                                               /*!< TK_T::POLCTL: CBPOLSEL Position           */
+#define TK_POLCTL_CBPOLSEL_Msk           (0x3ul << TK_POLCTL_CBPOLSEL_Pos)                 /*!< TK_T::POLCTL: CBPOLSEL Mask               */
+
+#define TK_POLCTL_POLEN0_Pos             (8)                                               /*!< TK_T::POLCTL: POLEN0 Position             */
+#define TK_POLCTL_POLEN0_Msk             (0x1ul << TK_POLCTL_POLEN0_Pos)                   /*!< TK_T::POLCTL: POLEN0 Mask                 */
+
+#define TK_POLCTL_POLEN1_Pos             (9)                                               /*!< TK_T::POLCTL: POLEN1 Position             */
+#define TK_POLCTL_POLEN1_Msk             (0x1ul << TK_POLCTL_POLEN1_Pos)                   /*!< TK_T::POLCTL: POLEN1 Mask                 */
+
+#define TK_POLCTL_POLEN2_Pos             (10)                                              /*!< TK_T::POLCTL: POLEN2 Position             */
+#define TK_POLCTL_POLEN2_Msk             (0x1ul << TK_POLCTL_POLEN2_Pos)                   /*!< TK_T::POLCTL: POLEN2 Mask                 */
+
+#define TK_POLCTL_POLEN3_Pos             (11)                                              /*!< TK_T::POLCTL: POLEN3 Position             */
+#define TK_POLCTL_POLEN3_Msk             (0x1ul << TK_POLCTL_POLEN3_Pos)                   /*!< TK_T::POLCTL: POLEN3 Mask                 */
+
+#define TK_POLCTL_POLEN4_Pos             (12)                                              /*!< TK_T::POLCTL: POLEN4 Position             */
+#define TK_POLCTL_POLEN4_Msk             (0x1ul << TK_POLCTL_POLEN4_Pos)                   /*!< TK_T::POLCTL: POLEN4 Mask                 */
+
+#define TK_POLCTL_POLEN5_Pos             (13)                                              /*!< TK_T::POLCTL: POLEN5 Position             */
+#define TK_POLCTL_POLEN5_Msk             (0x1ul << TK_POLCTL_POLEN5_Pos)                   /*!< TK_T::POLCTL: POLEN5 Mask                 */
+
+#define TK_POLCTL_POLEN6_Pos             (14)                                              /*!< TK_T::POLCTL: POLEN6 Position             */
+#define TK_POLCTL_POLEN6_Msk             (0x1ul << TK_POLCTL_POLEN6_Pos)                   /*!< TK_T::POLCTL: POLEN6 Mask                 */
+
+#define TK_POLCTL_POLEN7_Pos             (15)                                              /*!< TK_T::POLCTL: POLEN7 Position             */
+#define TK_POLCTL_POLEN7_Msk             (0x1ul << TK_POLCTL_POLEN7_Pos)                   /*!< TK_T::POLCTL: POLEN7 Mask                 */
+
+#define TK_POLCTL_POLEN8_Pos             (16)                                              /*!< TK_T::POLCTL: POLEN8 Position             */
+#define TK_POLCTL_POLEN8_Msk             (0x1ul << TK_POLCTL_POLEN8_Pos)                   /*!< TK_T::POLCTL: POLEN8 Mask                 */
+
+#define TK_POLCTL_POLEN9_Pos             (17)                                              /*!< TK_T::POLCTL: POLEN9 Position             */
+#define TK_POLCTL_POLEN9_Msk             (0x1ul << TK_POLCTL_POLEN9_Pos)                   /*!< TK_T::POLCTL: POLEN9 Mask                 */
+
+#define TK_POLCTL_POLEN10_Pos            (18)                                              /*!< TK_T::POLCTL: POLEN10 Position            */
+#define TK_POLCTL_POLEN10_Msk            (0x1ul << TK_POLCTL_POLEN10_Pos)                  /*!< TK_T::POLCTL: POLEN10 Mask                */
+
+#define TK_POLCTL_POLEN11_Pos            (19)                                              /*!< TK_T::POLCTL: POLEN11 Position            */
+#define TK_POLCTL_POLEN11_Msk            (0x1ul << TK_POLCTL_POLEN11_Pos)                  /*!< TK_T::POLCTL: POLEN11 Mask                */
+
+#define TK_POLCTL_POLEN12_Pos            (20)                                              /*!< TK_T::POLCTL: POLEN12 Position            */
+#define TK_POLCTL_POLEN12_Msk            (0x1ul << TK_POLCTL_POLEN12_Pos)                  /*!< TK_T::POLCTL: POLEN12 Mask                */
+
+#define TK_POLCTL_POLEN13_Pos            (21)                                              /*!< TK_T::POLCTL: POLEN13 Position            */
+#define TK_POLCTL_POLEN13_Msk            (0x1ul << TK_POLCTL_POLEN13_Pos)                  /*!< TK_T::POLCTL: POLEN13 Mask                */
+
+#define TK_POLCTL_POLEN14_Pos            (22)                                              /*!< TK_T::POLCTL: POLEN14 Position            */
+#define TK_POLCTL_POLEN14_Msk            (0x1ul << TK_POLCTL_POLEN14_Pos)                  /*!< TK_T::POLCTL: POLEN14 Mask                */
+
+#define TK_POLCTL_POLEN15_Pos            (23)                                              /*!< TK_T::POLCTL: POLEN15 Position            */
+#define TK_POLCTL_POLEN15_Msk            (0x1ul << TK_POLCTL_POLEN15_Pos)                  /*!< TK_T::POLCTL: POLEN15 Mask                */
+
+#define TK_POLCTL_POLEN16_Pos            (24)                                              /*!< TK_T::POLCTL: POLEN16 Position            */
+#define TK_POLCTL_POLEN16_Msk            (0x1ul << TK_POLCTL_POLEN16_Pos)                  /*!< TK_T::POLCTL: POLEN16 Mask                */
+
+#define TK_POLCTL_SPOTINIT_Pos           (31)                                              /*!< TK_T::POLCTL: SPOTINIT Position           */
+#define TK_POLCTL_SPOTINIT_Msk           (0x1ul << TK_POLCTL_SPOTINIT_Pos)                 /*!< TK_T::POLCTL: SPOTINIT Mask               */
+
+#define TK_STATUS_BUSY_Pos               (0)                                               /*!< TK_T::STATUS: BUSY Position               */
+#define TK_STATUS_BUSY_Msk               (0x1ul << TK_STATUS_BUSY_Pos)                     /*!< TK_T::STATUS: BUSY Mask                   */
+
+#define TK_STATUS_SCIF_Pos               (1)                                               /*!< TK_T::STATUS: SCIF Position               */
+#define TK_STATUS_SCIF_Msk               (0x1ul << TK_STATUS_SCIF_Pos)                     /*!< TK_T::STATUS: SCIF Mask                   */
+
+#define TK_STATUS_TKIF0_Pos              (8)                                               /*!< TK_T::STATUS: TKIF0 Position              */
+#define TK_STATUS_TKIF0_Msk              (0x1ul << TK_STATUS_TKIF0_Pos)                    /*!< TK_T::STATUS: TKIF0 Mask                  */
+
+#define TK_STATUS_TKIF1_Pos              (9)                                               /*!< TK_T::STATUS: TKIF1 Position              */
+#define TK_STATUS_TKIF1_Msk              (0x1ul << TK_STATUS_TKIF1_Pos)                    /*!< TK_T::STATUS: TKIF1 Mask                  */
+
+#define TK_STATUS_TKIF2_Pos              (10)                                              /*!< TK_T::STATUS: TKIF2 Position              */
+#define TK_STATUS_TKIF2_Msk              (0x1ul << TK_STATUS_TKIF2_Pos)                    /*!< TK_T::STATUS: TKIF2 Mask                  */
+
+#define TK_STATUS_TKIF3_Pos              (11)                                              /*!< TK_T::STATUS: TKIF3 Position              */
+#define TK_STATUS_TKIF3_Msk              (0x1ul << TK_STATUS_TKIF3_Pos)                    /*!< TK_T::STATUS: TKIF3 Mask                  */
+
+#define TK_STATUS_TKIF4_Pos              (12)                                              /*!< TK_T::STATUS: TKIF4 Position              */
+#define TK_STATUS_TKIF4_Msk              (0x1ul << TK_STATUS_TKIF4_Pos)                    /*!< TK_T::STATUS: TKIF4 Mask                  */
+
+#define TK_STATUS_TKIF5_Pos              (13)                                              /*!< TK_T::STATUS: TKIF5 Position              */
+#define TK_STATUS_TKIF5_Msk              (0x1ul << TK_STATUS_TKIF5_Pos)                    /*!< TK_T::STATUS: TKIF5 Mask                  */
+
+#define TK_STATUS_TKIF6_Pos              (14)                                              /*!< TK_T::STATUS: TKIF6 Position              */
+#define TK_STATUS_TKIF6_Msk              (0x1ul << TK_STATUS_TKIF6_Pos)                    /*!< TK_T::STATUS: TKIF6 Mask                  */
+
+#define TK_STATUS_TKIF7_Pos              (15)                                              /*!< TK_T::STATUS: TKIF7 Position              */
+#define TK_STATUS_TKIF7_Msk              (0x1ul << TK_STATUS_TKIF7_Pos)                    /*!< TK_T::STATUS: TKIF7 Mask                  */
+
+#define TK_STATUS_TKIF8_Pos              (16)                                              /*!< TK_T::STATUS: TKIF8 Position              */
+#define TK_STATUS_TKIF8_Msk              (0x1ul << TK_STATUS_TKIF8_Pos)                    /*!< TK_T::STATUS: TKIF8 Mask                  */
+
+#define TK_STATUS_TKIF9_Pos              (17)                                              /*!< TK_T::STATUS: TKIF9 Position              */
+#define TK_STATUS_TKIF9_Msk              (0x1ul << TK_STATUS_TKIF9_Pos)                    /*!< TK_T::STATUS: TKIF9 Mask                  */
+
+#define TK_STATUS_TKIF10_Pos             (18)                                              /*!< TK_T::STATUS: TKIF10 Position             */
+#define TK_STATUS_TKIF10_Msk             (0x1ul << TK_STATUS_TKIF10_Pos)                   /*!< TK_T::STATUS: TKIF10 Mask                 */
+
+#define TK_STATUS_TKIF11_Pos             (19)                                              /*!< TK_T::STATUS: TKIF11 Position             */
+#define TK_STATUS_TKIF11_Msk             (0x1ul << TK_STATUS_TKIF11_Pos)                   /*!< TK_T::STATUS: TKIF11 Mask                 */
+
+#define TK_STATUS_TKIF12_Pos             (20)                                              /*!< TK_T::STATUS: TKIF12 Position             */
+#define TK_STATUS_TKIF12_Msk             (0x1ul << TK_STATUS_TKIF12_Pos)                   /*!< TK_T::STATUS: TKIF12 Mask                 */
+
+#define TK_STATUS_TKIF13_Pos             (21)                                              /*!< TK_T::STATUS: TKIF13 Position             */
+#define TK_STATUS_TKIF13_Msk             (0x1ul << TK_STATUS_TKIF13_Pos)                   /*!< TK_T::STATUS: TKIF13 Mask                 */
+
+#define TK_STATUS_TKIF14_Pos             (22)                                              /*!< TK_T::STATUS: TKIF14 Position             */
+#define TK_STATUS_TKIF14_Msk             (0x1ul << TK_STATUS_TKIF14_Pos)                   /*!< TK_T::STATUS: TKIF14 Mask                 */
+
+#define TK_STATUS_TKIF15_Pos             (23)                                              /*!< TK_T::STATUS: TKIF15 Position             */
+#define TK_STATUS_TKIF15_Msk             (0x1ul << TK_STATUS_TKIF15_Pos)                   /*!< TK_T::STATUS: TKIF15 Mask                 */
+
+#define TK_STATUS_TKIF16_Pos             (24)                                              /*!< TK_T::STATUS: TKIF16 Position             */
+#define TK_STATUS_TKIF16_Msk             (0x1ul << TK_STATUS_TKIF16_Pos)                   /*!< TK_T::STATUS: TKIF16 Mask                 */
+
+#define TK_DAT0_TKDAT0_Pos               (0)                                               /*!< TK_T::DAT0: TKDAT0 Position               */
+#define TK_DAT0_TKDAT0_Msk               (0xfful << TK_DAT0_TKDAT0_Pos)                    /*!< TK_T::DAT0: TKDAT0 Mask                   */
+
+#define TK_DAT0_TKDAT1_Pos               (8)                                               /*!< TK_T::DAT0: TKDAT1 Position               */
+#define TK_DAT0_TKDAT1_Msk               (0xfful << TK_DAT0_TKDAT1_Pos)                    /*!< TK_T::DAT0: TKDAT1 Mask                   */
+
+#define TK_DAT0_TKDAT2_Pos               (16)                                              /*!< TK_T::DAT0: TKDAT2 Position               */
+#define TK_DAT0_TKDAT2_Msk               (0xfful << TK_DAT0_TKDAT2_Pos)                    /*!< TK_T::DAT0: TKDAT2 Mask                   */
+
+#define TK_DAT0_TKDAT3_Pos               (24)                                              /*!< TK_T::DAT0: TKDAT3 Position               */
+#define TK_DAT0_TKDAT3_Msk               (0xfful << TK_DAT0_TKDAT3_Pos)                    /*!< TK_T::DAT0: TKDAT3 Mask                   */
+
+#define TK_DAT1_TKDAT4_Pos               (0)                                               /*!< TK_T::DAT1: TKDAT4 Position               */
+#define TK_DAT1_TKDAT4_Msk               (0xfful << TK_DAT1_TKDAT4_Pos)                    /*!< TK_T::DAT1: TKDAT4 Mask                   */
+
+#define TK_DAT1_TKDAT5_Pos               (8)                                               /*!< TK_T::DAT1: TKDAT5 Position               */
+#define TK_DAT1_TKDAT5_Msk               (0xfful << TK_DAT1_TKDAT5_Pos)                    /*!< TK_T::DAT1: TKDAT5 Mask                   */
+
+#define TK_DAT1_TKDAT6_Pos               (16)                                              /*!< TK_T::DAT1: TKDAT6 Position               */
+#define TK_DAT1_TKDAT6_Msk               (0xfful << TK_DAT1_TKDAT6_Pos)                    /*!< TK_T::DAT1: TKDAT6 Mask                   */
+
+#define TK_DAT1_TKDAT7_Pos               (24)                                              /*!< TK_T::DAT1: TKDAT7 Position               */
+#define TK_DAT1_TKDAT7_Msk               (0xfful << TK_DAT1_TKDAT7_Pos)                    /*!< TK_T::DAT1: TKDAT7 Mask                   */
+
+#define TK_DAT2_TKDAT8_Pos               (0)                                               /*!< TK_T::DAT2: TKDAT8 Position               */
+#define TK_DAT2_TKDAT8_Msk               (0xfful << TK_DAT2_TKDAT8_Pos)                    /*!< TK_T::DAT2: TKDAT8 Mask                   */
+
+#define TK_DAT2_TKDAT9_Pos               (8)                                               /*!< TK_T::DAT2: TKDAT9 Position               */
+#define TK_DAT2_TKDAT9_Msk               (0xfful << TK_DAT2_TKDAT9_Pos)                    /*!< TK_T::DAT2: TKDAT9 Mask                   */
+
+#define TK_DAT2_TKDAT10_Pos              (16)                                              /*!< TK_T::DAT2: TKDAT10 Position              */
+#define TK_DAT2_TKDAT10_Msk              (0xfful << TK_DAT2_TKDAT10_Pos)                   /*!< TK_T::DAT2: TKDAT10 Mask                  */
+
+#define TK_DAT2_TKDAT11_Pos              (24)                                              /*!< TK_T::DAT2: TKDAT11 Position              */
+#define TK_DAT2_TKDAT11_Msk              (0xfful << TK_DAT2_TKDAT11_Pos)                   /*!< TK_T::DAT2: TKDAT11 Mask                  */
+
+#define TK_DAT3_TKDAT12_Pos              (0)                                               /*!< TK_T::DAT3: TKDAT12 Position              */
+#define TK_DAT3_TKDAT12_Msk              (0xfful << TK_DAT3_TKDAT12_Pos)                   /*!< TK_T::DAT3: TKDAT12 Mask                  */
+
+#define TK_DAT3_TKDAT13_Pos              (8)                                               /*!< TK_T::DAT3: TKDAT13 Position              */
+#define TK_DAT3_TKDAT13_Msk              (0xfful << TK_DAT3_TKDAT13_Pos)                   /*!< TK_T::DAT3: TKDAT13 Mask                  */
+
+#define TK_DAT3_TKDAT14_Pos              (16)                                              /*!< TK_T::DAT3: TKDAT14 Position              */
+#define TK_DAT3_TKDAT14_Msk              (0xfful << TK_DAT3_TKDAT14_Pos)                   /*!< TK_T::DAT3: TKDAT14 Mask                  */
+
+#define TK_DAT3_TKDAT15_Pos              (24)                                              /*!< TK_T::DAT3: TKDAT15 Position              */
+#define TK_DAT3_TKDAT15_Msk              (0xfful << TK_DAT3_TKDAT15_Pos)                   /*!< TK_T::DAT3: TKDAT15 Mask                  */
+
+#define TK_DAT4_TKDAT16_Pos              (0)                                               /*!< TK_T::DAT4: TKDAT16 Position              */
+#define TK_DAT4_TKDAT16_Msk              (0xfful << TK_DAT4_TKDAT16_Pos)                   /*!< TK_T::DAT4: TKDAT16 Mask                  */
+
+#define TK_INTEN_SCTHIEN_Pos             (0)                                               /*!< TK_T::INTEN: SCTHIEN Position             */
+#define TK_INTEN_SCTHIEN_Msk             (0x1ul << TK_INTEN_SCTHIEN_Pos)                   /*!< TK_T::INTEN: SCTHIEN Mask                 */
+
+#define TK_INTEN_SCINTEN_Pos             (1)                                               /*!< TK_T::INTEN: SCINTEN Position             */
+#define TK_INTEN_SCINTEN_Msk             (0x1ul << TK_INTEN_SCINTEN_Pos)                   /*!< TK_T::INTEN: SCINTEN Mask                 */
+
+#define TK_INTEN_THIMOD_Pos              (31)                                              /*!< TK_T::INTEN: THIMOD Position              */
+#define TK_INTEN_THIMOD_Msk              (0x1ul << TK_INTEN_THIMOD_Pos)                    /*!< TK_T::INTEN: THIMOD Mask                  */
+
+#define TK_TH0_1_LTH0_Pos                (0)                                               /*!< TK_T::TH0_1: LTH0 Position                */
+#define TK_TH0_1_LTH0_Msk                (0xfful << TK_TH0_1_LTH0_Pos)                     /*!< TK_T::TH0_1: LTH0 Mask                    */
+
+#define TK_TH0_1_HTH0_Pos                (8)                                               /*!< TK_T::TH0_1: HTH0 Position                */
+#define TK_TH0_1_HTH0_Msk                (0xfful << TK_TH0_1_HTH0_Pos)                     /*!< TK_T::TH0_1: HTH0 Mask                    */
+
+#define TK_TH0_1_LTH1_Pos                (16)                                              /*!< TK_T::TH0_1: LTH1 Position                */
+#define TK_TH0_1_LTH1_Msk                (0xfful << TK_TH0_1_LTH1_Pos)                     /*!< TK_T::TH0_1: LTH1 Mask                    */
+
+#define TK_TH0_1_HTH1_Pos                (24)                                              /*!< TK_T::TH0_1: HTH1 Position                */
+#define TK_TH0_1_HTH1_Msk                (0xfful << TK_TH0_1_HTH1_Pos)                     /*!< TK_T::TH0_1: HTH1 Mask                    */
+
+#define TK_TH2_3_LTH2_Pos                (0)                                               /*!< TK_T::TH2_3: LTH2 Position                */
+#define TK_TH2_3_LTH2_Msk                (0xfful << TK_TH2_3_LTH2_Pos)                     /*!< TK_T::TH2_3: LTH2 Mask                    */
+
+#define TK_TH2_3_HTH2_Pos                (8)                                               /*!< TK_T::TH2_3: HTH2 Position                */
+#define TK_TH2_3_HTH2_Msk                (0xfful << TK_TH2_3_HTH2_Pos)                     /*!< TK_T::TH2_3: HTH2 Mask                    */
+
+#define TK_TH2_3_LTH3_Pos                (16)                                              /*!< TK_T::TH2_3: LTH3 Position                */
+#define TK_TH2_3_LTH3_Msk                (0xfful << TK_TH2_3_LTH3_Pos)                     /*!< TK_T::TH2_3: LTH3 Mask                    */
+
+#define TK_TH2_3_HTH3_Pos                (24)                                              /*!< TK_T::TH2_3: HTH3 Position                */
+#define TK_TH2_3_HTH3_Msk                (0xfful << TK_TH2_3_HTH3_Pos)                     /*!< TK_T::TH2_3: HTH3 Mask                    */
+
+#define TK_TH4_5_LTH4_Pos                (0)                                               /*!< TK_T::TH4_5: LTH4 Position                */
+#define TK_TH4_5_LTH4_Msk                (0xfful << TK_TH4_5_LTH4_Pos)                     /*!< TK_T::TH4_5: LTH4 Mask                    */
+
+#define TK_TH4_5_HTH4_Pos                (8)                                               /*!< TK_T::TH4_5: HTH4 Position                */
+#define TK_TH4_5_HTH4_Msk                (0xfful << TK_TH4_5_HTH4_Pos)                     /*!< TK_T::TH4_5: HTH4 Mask                    */
+
+#define TK_TH4_5_LTH5_Pos                (16)                                              /*!< TK_T::TH4_5: LTH5 Position                */
+#define TK_TH4_5_LTH5_Msk                (0xfful << TK_TH4_5_LTH5_Pos)                     /*!< TK_T::TH4_5: LTH5 Mask                    */
+
+#define TK_TH4_5_HTH5_Pos                (24)                                              /*!< TK_T::TH4_5: HTH5 Position                */
+#define TK_TH4_5_HTH5_Msk                (0xfful << TK_TH4_5_HTH5_Pos)                     /*!< TK_T::TH4_5: HTH5 Mask                    */
+
+#define TK_TH6_7_LTH6_Pos                (0)                                               /*!< TK_T::TH6_7: LTH6 Position                */
+#define TK_TH6_7_LTH6_Msk                (0xfful << TK_TH6_7_LTH6_Pos)                     /*!< TK_T::TH6_7: LTH6 Mask                    */
+
+#define TK_TH6_7_HTH6_Pos                (8)                                               /*!< TK_T::TH6_7: HTH6 Position                */
+#define TK_TH6_7_HTH6_Msk                (0xfful << TK_TH6_7_HTH6_Pos)                     /*!< TK_T::TH6_7: HTH6 Mask                    */
+
+#define TK_TH6_7_LTH7_Pos                (16)                                              /*!< TK_T::TH6_7: LTH7 Position                */
+#define TK_TH6_7_LTH7_Msk                (0xfful << TK_TH6_7_LTH7_Pos)                     /*!< TK_T::TH6_7: LTH7 Mask                    */
+
+#define TK_TH6_7_HTH7_Pos                (24)                                              /*!< TK_T::TH6_7: HTH7 Position                */
+#define TK_TH6_7_HTH7_Msk                (0xfful << TK_TH6_7_HTH7_Pos)                     /*!< TK_T::TH6_7: HTH7 Mask                    */
+
+#define TK_TH8_9_LTH8_Pos                (0)                                               /*!< TK_T::TH8_9: LTH8 Position                */
+#define TK_TH8_9_LTH8_Msk                (0xfful << TK_TH8_9_LTH8_Pos)                     /*!< TK_T::TH8_9: LTH8 Mask                    */
+
+#define TK_TH8_9_HTH8_Pos                (8)                                               /*!< TK_T::TH8_9: HTH8 Position                */
+#define TK_TH8_9_HTH8_Msk                (0xfful << TK_TH8_9_HTH8_Pos)                     /*!< TK_T::TH8_9: HTH8 Mask                    */
+
+#define TK_TH8_9_LTH9_Pos                (16)                                              /*!< TK_T::TH8_9: LTH9 Position                */
+#define TK_TH8_9_LTH9_Msk                (0xfful << TK_TH8_9_LTH9_Pos)                     /*!< TK_T::TH8_9: LTH9 Mask                    */
+
+#define TK_TH8_9_HTH9_Pos                (24)                                              /*!< TK_T::TH8_9: HTH9 Position                */
+#define TK_TH8_9_HTH9_Msk                (0xfful << TK_TH8_9_HTH9_Pos)                     /*!< TK_T::TH8_9: HTH9 Mask                    */
+
+#define TK_TH10_11_LTH10_Pos             (0)                                               /*!< TK_T::TH10_11: LTH10 Position             */
+#define TK_TH10_11_LTH10_Msk             (0xfful << TK_TH10_11_LTH10_Pos)                  /*!< TK_T::TH10_11: LTH10 Mask                 */
+
+#define TK_TH10_11_HTH10_Pos             (8)                                               /*!< TK_T::TH10_11: HTH10 Position             */
+#define TK_TH10_11_HTH10_Msk             (0xfful << TK_TH10_11_HTH10_Pos)                  /*!< TK_T::TH10_11: HTH10 Mask                 */
+
+#define TK_TH10_11_LTH11_Pos             (16)                                              /*!< TK_T::TH10_11: LTH11 Position             */
+#define TK_TH10_11_LTH11_Msk             (0xfful << TK_TH10_11_LTH11_Pos)                  /*!< TK_T::TH10_11: LTH11 Mask                 */
+
+#define TK_TH10_11_HTH11_Pos             (24)                                              /*!< TK_T::TH10_11: HTH11 Position             */
+#define TK_TH10_11_HTH11_Msk             (0xfful << TK_TH10_11_HTH11_Pos)                  /*!< TK_T::TH10_11: HTH11 Mask                 */
+
+#define TK_TH12_13_LTH12_Pos             (0)                                               /*!< TK_T::TH12_13: LTH12 Position             */
+#define TK_TH12_13_LTH12_Msk             (0xfful << TK_TH12_13_LTH12_Pos)                  /*!< TK_T::TH12_13: LTH12 Mask                 */
+
+#define TK_TH12_13_HTH12_Pos             (8)                                               /*!< TK_T::TH12_13: HTH12 Position             */
+#define TK_TH12_13_HTH12_Msk             (0xfful << TK_TH12_13_HTH12_Pos)                  /*!< TK_T::TH12_13: HTH12 Mask                 */
+
+#define TK_TH12_13_LTH13_Pos             (16)                                              /*!< TK_T::TH12_13: LTH13 Position             */
+#define TK_TH12_13_LTH13_Msk             (0xfful << TK_TH12_13_LTH13_Pos)                  /*!< TK_T::TH12_13: LTH13 Mask                 */
+
+#define TK_TH12_13_HTH13_Pos             (24)                                              /*!< TK_T::TH12_13: HTH13 Position             */
+#define TK_TH12_13_HTH13_Msk             (0xfful << TK_TH12_13_HTH13_Pos)                  /*!< TK_T::TH12_13: HTH13 Mask                 */
+
+#define TK_TH14_15_LTH14_Pos             (0)                                               /*!< TK_T::TH14_15: LTH14 Position             */
+#define TK_TH14_15_LTH14_Msk             (0xfful << TK_TH14_15_LTH14_Pos)                  /*!< TK_T::TH14_15: LTH14 Mask                 */
+
+#define TK_TH14_15_HTH14_Pos             (8)                                               /*!< TK_T::TH14_15: HTH14 Position             */
+#define TK_TH14_15_HTH14_Msk             (0xfful << TK_TH14_15_HTH14_Pos)                  /*!< TK_T::TH14_15: HTH14 Mask                 */
+
+#define TK_TH14_15_LTH15_Pos             (16)                                              /*!< TK_T::TH14_15: LTH15 Position             */
+#define TK_TH14_15_LTH15_Msk             (0xfful << TK_TH14_15_LTH15_Pos)                  /*!< TK_T::TH14_15: LTH15 Mask                 */
+
+#define TK_TH14_15_HTH15_Pos             (24)                                              /*!< TK_T::TH14_15: HTH15 Position             */
+#define TK_TH14_15_HTH15_Msk             (0xfful << TK_TH14_15_HTH15_Pos)                  /*!< TK_T::TH14_15: HTH15 Mask                 */
+
+#define TK_TH16_LTH16_Pos                (0)                                               /*!< TK_T::TH16: LTH16 Position                */
+#define TK_TH16_LTH16_Msk                (0xfful << TK_TH16_LTH16_Pos)                     /*!< TK_T::TH16: LTH16 Mask                    */
+
+#define TK_TH16_HTH16_Pos                (8)                                               /*!< TK_T::TH16: HTH16 Position                */
+#define TK_TH16_HTH16_Msk                (0xfful << TK_TH16_HTH16_Pos)                     /*!< TK_T::TH16: HTH16 Mask                    */
+
+/**@}*/ /* TK_CONST */
+/**@}*/ /* end of TK register group */
+
+
+/*---------------------- Timer Controller -------------------------*/
+/**
+    @addtogroup TMR Timer Controller(TMR)
+    Memory Mapped Structure for TMR Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var TIMER_T::CTL
+ * Offset: 0x00  Timer Control and Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |PSC       |Prescale Counter
+ * |        |          |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter.
+ * |        |          |If this field is 0 (PSC = 0), then there is no scaling.
+ * |[17]    |WKTKEN    |Wake-Up Touch-Key Scan Enable Bit
+ * |        |          |If this bit is set to 1, timer time-out interrupt in Power-down mode can be triggered Touch-Key start scan.
+ * |        |          |0 = Timer time-out interrupt signal trigger Touch-Key start scan Disabled.
+ * |        |          |1 = Timer time-out interrupt signal trigger Touch-Key start scan Enabled.
+ * |        |          |Note: This bit is only available in TIMER0_CTL.
+ * |[18]    |TRGSSEL   |Trigger Source Select Bit
+ * |        |          |This bit is used to select trigger source is form Timer time-out interrupt signal or capture interrupt signal.
+ * |        |          |0 = Timer time-out interrupt signal is used to trigger PWM, EADC and DAC.
+ * |        |          |1 = Capture interrupt signal is used to trigger PWM, EADC and DAC.
+ * |[19]    |TRGPWM    |Trigger PWM Enable Bit
+ * |        |          |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered PWM.
+ * |        |          |0 = Timer interrupt trigger PWM Disabled.
+ * |        |          |1 = Timer interrupt trigger PWM Enabled.
+ * |        |          |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger PWM.
+ * |        |          |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger PWM.
+ * |[20]    |TRGDAC    |Trigger DAC Enable Bit
+ * |        |          |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
+ * |        |          |0 = Timer interrupt trigger DAC Disabled.
+ * |        |          |1 = Timer interrupt trigger DAC Enabled.
+ * |        |          |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger DAC.
+ * |        |          |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger DAC.
+ * |[21]    |TRGEADC   |Trigger EADC Enable Bit
+ * |        |          |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered EADC.
+ * |        |          |0 = Timer interrupt trigger EADC Disabled.
+ * |        |          |1 = Timer interrupt trigger EADC Enabled.
+ * |        |          |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger EADC.
+ * |        |          |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger EADC.
+ * |[22]    |TGLPINSEL |Toggle-Output Pin Select
+ * |        |          |0 = Toggle mode output to Tx_OUT (Timer Event Counter Pin).
+ * |        |          |1 = Toggle mode output to Tx_EXT(Timer External Capture Pin).
+ * |[23]    |WKEN      |Wake-Up Function Enable Bit
+ * |        |          |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
+ * |        |          |0 = Wake-up function Disabled if timer interrupt signal generated.
+ * |        |          |1 = Wake-up function Enabled if timer interrupt signal generated.
+ * |[24]    |EXTCNTEN  |Event Counter Mode Enable Bit
+ * |        |          |This bit is for external counting pin function enabled.
+ * |        |          |0 = Event counter mode Disabled.
+ * |        |          |1 = Event counter mode Enabled.
+ * |        |          |Note: When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source.
+ * |[25]    |ACTSTS    |Timer Active Status Bit (Read Only)
+ * |        |          |This bit indicates the 24-bit up counter status.
+ * |        |          |0 = 24-bit up counter is not active.
+ * |        |          |1 = 24-bit up counter is active.
+ * |[26]    |RSTCNT    |Timer Counter Reset Bit
+ * |        |          |Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
+ * |        |          |0 = No effect.
+ * |        |          |1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit.
+ * |[28:27] |OPMODE    |Timer Counting Mode Select
+ * |        |          |00 = The Timer controller is operated in One-shot mode.
+ * |        |          |01 = The Timer controller is operated in Periodic mode.
+ * |        |          |10 = The Timer controller is operated in Toggle-output mode.
+ * |        |          |11 = The Timer controller is operated in Continuous Counting mode.
+ * |[29]    |INTEN     |Timer Interrupt Enable Bit
+ * |        |          |0 = Timer Interrupt Disabled.
+ * |        |          |1 = Timer Interrupt Enabled.
+ * |        |          |Note: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
+ * |[30]    |CNTEN     |Timer Counting Enable Bit
+ * |        |          |0 = Stops/Suspends counting.
+ * |        |          |1 = Starts counting.
+ * |        |          |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
+ * |        |          |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
+ * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable
+ * |        |          |0 = ICE debug mode acknowledgement effects TIMER counting.
+ * |        |          |TIMER counter will be held while CPU is held by ICE.
+ * |        |          |1 = ICE debug mode acknowledgement Disabled.
+ * |        |          |TIMER counter will keep going no matter CPU is held by ICE or not.
+ * @var TIMER_T::CMP
+ * Offset: 0x04  Timer Compare Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[23:0]  |CMPDAT    |Timer Compared Value
+ * |        |          |CMPDAT is a 24-bit compared value register.
+ * |        |          |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
+ * |        |          |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
+ * |        |          |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
+ * |        |          |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field.
+ * |        |          |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
+ * @var TIMER_T::INTSTS
+ * Offset: 0x08  Timer Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |TIF       |Timer Interrupt Flag
+ * |        |          |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
+ * |        |          |0 = No effect.
+ * |        |          |1 = CNT value matches the CMPDAT value.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * |[1]     |TWKF      |Timer Wake-Up Flag
+ * |        |          |This bit indicates the interrupt wake-up flag status of timer.
+ * |        |          |0 = Timer does not cause CPU wake-up.
+ * |        |          |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * @var TIMER_T::CNT
+ * Offset: 0x0C  Timer Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[23:0]  |CNT       |Timer Data Register
+ * |        |          |This field can be reflected the internal 24-bit timer counter value or external event input counter value from Tx_CNT (x=0~3) pin.
+ * |        |          |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24- bit counter value .
+ * |        |          |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24- bit event input counter value.
+ * @var TIMER_T::CAP
+ * Offset: 0x10  Timer Capture Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[23:0]  |CAPDAT    |Timer Capture Data Register
+ * |        |          |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
+ * @var TIMER_T::EXTCTL
+ * Offset: 0x14  Timer External Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |CNTPHASE  |Timer External Count Phase
+ * |        |          |This bit indicates the detection phase of external counting pin Tx_CNT (x= 0~3).
+ * |        |          |0 = A Falling edge of external counting pin will be counted.
+ * |        |          |1 = A Rising edge of external counting pin will be counted.
+ * |[2:1]   |CAPEDGE   |Timer External Capture Pin Edge Detect
+ * |        |          |00 = A Falling edge on Tx_EXT (x= 0~3) pin will be detected.
+ * |        |          |01 = A Rising edge on Tx_EXT (x= 0~3) pin will be detected.
+ * |        |          |10 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected.
+ * |        |          |11 = Reserved.
+ * |[3]     |CAPEN     |Timer External Capture Pin Enable
+ * |        |          |This bit enables the Tx_EXT pin.
+ * |        |          |0 =Tx_EXT (x= 0~3) pin Disabled.
+ * |        |          |1 =Tx_EXT (x= 0~3) pin Enabled.
+ * |[4]     |CAPFUNCS  |Capture Function Selection
+ * |        |          |0 = External Capture Mode Enabled.
+ * |        |          |1 = External Reset Mode Enabled.
+ * |        |          |Note1: When CAPFUNCS is 0, transition on Tx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value.
+ * |        |          |Note2: When CAPFUNCS is 1, transition on Tx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value.
+ * |[5]     |CAPIEN    |Timer External Capture Interrupt Enable
+ * |        |          |0 = Tx_EXT (x= 0~3) pin detection Interrupt Disabled.
+ * |        |          |1 = Tx_EXT (x= 0~3) pin detection Interrupt Enabled.
+ * |        |          |Note: CAPIEN is used to enable timer external interrupt.
+ * |        |          |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
+ * |        |          |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the Tx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
+ * |[6]     |CAPDBEN   |Timer External Capture Pin De-Bounce Enable
+ * |        |          |0 = Tx_EXT (x= 0~3) pin de-bounce Disabled.
+ * |        |          |1 = Tx_EXT (x= 0~3) pin de-bounce Enabled.
+ * |        |          |Note: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit.
+ * |[7]     |CNTDBEN   |Timer Counter Pin De-Bounce Enable
+ * |        |          |0 = Tx_CNT (x= 0~3) pin de-bounce Disabled.
+ * |        |          |1 = Tx_CNT (x= 0~3) pin de-bounce Enabled.
+ * |        |          |Note: If this bit is enabled, the edge detection of Tx_CNT pin is detected with de-bounce circuit.
+ * @var TIMER_T::EINTSTS
+ * Offset: 0x18  Timer External Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |CAPIF     |Timer External Capture Interrupt Flag
+ * |        |          |This bit indicates the timer external capture interrupt flag status.
+ * |        |          |0 = Tx_EXT (x= 0~3) pin interrupt did not occur.
+ * |        |          |1 = Tx_EXT (x= 0~3) pin interrupt occurred.
+ * |        |          |Note1: This bit is cleared by writing 1 to it.
+ * |        |          |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
+ * |        |          |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status.
+ * |        |          |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
+ */
+
+    __IO uint32_t CTL;           /* Offset: 0x00  Timer Control and Status Register                                  */
+    __IO uint32_t CMP;           /* Offset: 0x04  Timer Compare Register                                             */
+    __IO uint32_t INTSTS;        /* Offset: 0x08  Timer Interrupt Status Register                                    */
+    __I  uint32_t CNT;           /* Offset: 0x0C  Timer Data Register                                                */
+    __I  uint32_t CAP;           /* Offset: 0x10  Timer Capture Data Register                                        */
+    __IO uint32_t EXTCTL;        /* Offset: 0x14  Timer External Control Register                                    */
+    __IO uint32_t EINTSTS;       /* Offset: 0x18  Timer External Interrupt Status Register                           */
+
+} TIMER_T;
+
+
+
+/**
+    @addtogroup TMR_CONST TMR Bit Field Definition
+    Constant Definitions for TMR Controller
+@{ */
+
+#define TIMER_CTL_PSC_Pos                  (0)                                             /*!< TIMER_T::CTL: PSC Position                  */
+#define TIMER_CTL_PSC_Msk                  (0xfful << TIMER_CTL_PSC_Pos)                   /*!< TIMER_T::CTL: PSC Mask                      */
+
+#define TIMER_CTL_WKTKEN_Pos               (17)                                            /*!< TIMER_T::CTL: WKTKEN Position               */
+#define TIMER_CTL_WKTKEN_Msk               (0x1ul << TIMER_CTL_WKTKEN_Pos)                 /*!< TIMER_T::CTL: WKTKEN Mask                   */
+
+#define TIMER_CTL_TRGSSEL_Pos              (18)                                            /*!< TIMER_T::CTL: TRGSSEL Position              */
+#define TIMER_CTL_TRGSSEL_Msk              (0x1ul << TIMER_CTL_TRGSSEL_Pos)                /*!< TIMER_T::CTL: TRGSSEL Mask                  */
+
+#define TIMER_CTL_TRGPWM_Pos               (19)                                            /*!< TIMER_T::CTL: TRGPWM Position               */
+#define TIMER_CTL_TRGPWM_Msk               (0x1ul << TIMER_CTL_TRGPWM_Pos)                 /*!< TIMER_T::CTL: TRGPWM Mask                   */
+
+#define TIMER_CTL_TRGDAC_Pos               (20)                                            /*!< TIMER_T::CTL: TRGDAC Position               */
+#define TIMER_CTL_TRGDAC_Msk               (0x1ul << TIMER_CTL_TRGDAC_Pos)                 /*!< TIMER_T::CTL: TRGDAC Mask                   */
+
+#define TIMER_CTL_TRGEADC_Pos              (21)                                            /*!< TIMER_T::CTL: TRGEADC Position              */
+#define TIMER_CTL_TRGEADC_Msk              (0x1ul << TIMER_CTL_TRGEADC_Pos)                /*!< TIMER_T::CTL: TRGEADC Mask                  */
+
+#define TIMER_CTL_TGLPINSEL_Pos            (22)                                            /*!< TIMER_T::CTL: TGLPINSEL Position            */
+#define TIMER_CTL_TGLPINSEL_Msk            (0x1ul << TIMER_CTL_TGLPINSEL_Pos)              /*!< TIMER_T::CTL: TGLPINSEL Mask                */
+
+#define TIMER_CTL_WKEN_Pos                 (23)                                            /*!< TIMER_T::CTL: WKEN Position                 */
+#define TIMER_CTL_WKEN_Msk                 (0x1ul << TIMER_CTL_WKEN_Pos)                   /*!< TIMER_T::CTL: WKEN Mask                     */
+
+#define TIMER_CTL_EXTCNTEN_Pos             (24)                                            /*!< TIMER_T::CTL: EXTCNTEN Position             */
+#define TIMER_CTL_EXTCNTEN_Msk             (0x1ul << TIMER_CTL_EXTCNTEN_Pos)               /*!< TIMER_T::CTL: EXTCNTEN Mask                 */
+
+#define TIMER_CTL_ACTSTS_Pos               (25)                                            /*!< TIMER_T::CTL: ACTSTS Position               */
+#define TIMER_CTL_ACTSTS_Msk               (0x1ul << TIMER_CTL_ACTSTS_Pos)                 /*!< TIMER_T::CTL: ACTSTS Mask                   */
+
+#define TIMER_CTL_RSTCNT_Pos               (26)                                            /*!< TIMER_T::CTL: RSTCNT Position               */
+#define TIMER_CTL_RSTCNT_Msk               (0x1ul << TIMER_CTL_RSTCNT_Pos)                 /*!< TIMER_T::CTL: RSTCNT Mask                   */
+
+#define TIMER_CTL_OPMODE_Pos               (27)                                            /*!< TIMER_T::CTL: OPMODE Position               */
+#define TIMER_CTL_OPMODE_Msk               (0x3ul << TIMER_CTL_OPMODE_Pos)                 /*!< TIMER_T::CTL: OPMODE Mask                   */
+
+#define TIMER_CTL_INTEN_Pos                (29)                                            /*!< TIMER_T::CTL: INTEN Position                */
+#define TIMER_CTL_INTEN_Msk                (0x1ul << TIMER_CTL_INTEN_Pos)                  /*!< TIMER_T::CTL: INTEN Mask                    */
+
+#define TIMER_CTL_CNTEN_Pos                (30)                                            /*!< TIMER_T::CTL: CNTEN Position                */
+#define TIMER_CTL_CNTEN_Msk                (0x1ul << TIMER_CTL_CNTEN_Pos)                  /*!< TIMER_T::CTL: CNTEN Mask                    */
+
+#define TIMER_CTL_ICEDEBUG_Pos             (31)                                            /*!< TIMER_T::CTL: ICEDEBUG Position             */
+#define TIMER_CTL_ICEDEBUG_Msk             (0x1ul << TIMER_CTL_ICEDEBUG_Pos)               /*!< TIMER_T::CTL: ICEDEBUG Mask                 */
+
+#define TIMER_CMP_CMPDAT_Pos               (0)                                             /*!< TIMER_T::CMP: CMPDAT Position               */
+#define TIMER_CMP_CMPDAT_Msk               (0xfffffful << TIMER_CMP_CMPDAT_Pos)            /*!< TIMER_T::CMP: CMPDAT Mask                   */
+
+#define TIMER_INTSTS_TIF_Pos               (0)                                             /*!< TIMER_T::INTSTS: TIF Position               */
+#define TIMER_INTSTS_TIF_Msk               (0x1ul << TIMER_INTSTS_TIF_Pos)                 /*!< TIMER_T::INTSTS: TIF Mask                   */
+
+#define TIMER_INTSTS_TWKF_Pos              (1)                                             /*!< TIMER_T::INTSTS: TWKF Position              */
+#define TIMER_INTSTS_TWKF_Msk              (0x1ul << TIMER_INTSTS_TWKF_Pos)                /*!< TIMER_T::INTSTS: TWKF Mask                  */
+
+#define TIMER_CNT_CNT_Pos                  (0)                                             /*!< TIMER_T::CNT: CNT Position                  */
+#define TIMER_CNT_CNT_Msk                  (0xfffffful << TIMER_CNT_CNT_Pos)               /*!< TIMER_T::CNT: CNT Mask                      */
+
+#define TIMER_CAP_CAPDAT_Pos               (0)                                             /*!< TIMER_T::CAP: CAPDAT Position               */
+#define TIMER_CAP_CAPDAT_Msk               (0xfffffful << TIMER_CAP_CAPDAT_Pos)            /*!< TIMER_T::CAP: CAPDAT Mask                   */
+
+#define TIMER_EXTCTL_CNTPHASE_Pos          (0)                                             /*!< TIMER_T::EXTCTL: CNTPHASE Position          */
+#define TIMER_EXTCTL_CNTPHASE_Msk          (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos)            /*!< TIMER_T::EXTCTL: CNTPHASE Mask              */
+
+#define TIMER_EXTCTL_CAPEDGE_Pos           (1)                                             /*!< TIMER_T::EXTCTL: CAPEDGE Position           */
+#define TIMER_EXTCTL_CAPEDGE_Msk           (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos)             /*!< TIMER_T::EXTCTL: CAPEDGE Mask               */
+
+#define TIMER_EXTCTL_CAPEN_Pos             (3)                                             /*!< TIMER_T::EXTCTL: CAPEN Position             */
+#define TIMER_EXTCTL_CAPEN_Msk             (0x1ul << TIMER_EXTCTL_CAPEN_Pos)               /*!< TIMER_T::EXTCTL: CAPEN Mask                 */
+
+#define TIMER_EXTCTL_CAPFUNCS_Pos          (4)                                             /*!< TIMER_T::EXTCTL: CAPFUNCS Position          */
+#define TIMER_EXTCTL_CAPFUNCS_Msk          (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos)            /*!< TIMER_T::EXTCTL: CAPFUNCS Mask              */
+
+#define TIMER_EXTCTL_CAPIEN_Pos            (5)                                             /*!< TIMER_T::EXTCTL: CAPIEN Position            */
+#define TIMER_EXTCTL_CAPIEN_Msk            (0x1ul << TIMER_EXTCTL_CAPIEN_Pos)              /*!< TIMER_T::EXTCTL: CAPIEN Mask                */
+
+#define TIMER_EXTCTL_CAPDBEN_Pos           (6)                                             /*!< TIMER_T::EXTCTL: CAPDBEN Position           */
+#define TIMER_EXTCTL_CAPDBEN_Msk           (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos)             /*!< TIMER_T::EXTCTL: CAPDBEN Mask               */
+
+#define TIMER_EXTCTL_CNTDBEN_Pos           (7)                                             /*!< TIMER_T::EXTCTL: CNTDBEN Position           */
+#define TIMER_EXTCTL_CNTDBEN_Msk           (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos)             /*!< TIMER_T::EXTCTL: CNTDBEN Mask               */
+
+#define TIMER_EINTSTS_CAPIF_Pos            (0)                                             /*!< TIMER_T::EINTSTS: CAPIF Position            */
+#define TIMER_EINTSTS_CAPIF_Msk            (0x1ul << TIMER_EINTSTS_CAPIF_Pos)              /*!< TIMER_T::EINTSTS: CAPIF Mask                */
+
+/**@}*/ /* TIMER_CONST */
+/**@}*/ /* end of TIMER register group */
+
+
+/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
+/**
+    @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
+    Memory Mapped Structure for UART Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var UART_T::DAT
+ * Offset: 0x00  UART Receive/Transmit Buffer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |DAT       |Receiving/Transmit Buffer
+ * |        |          |Write Operation:
+ * |        |          |By writing one byte to this register, the data byte will be stored in transmitter FIFO.
+ * |        |          |The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
+ * |        |          |Read Operation:
+ * |        |          |By reading this register, the UART will return an 8-bit data received from receiving FIFO.
+ * @var UART_T::INTEN
+ * Offset: 0x04  UART Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |RDAIEN    |Receive Data Available Interrupt Enable Bit
+ * |        |          |0 = Receive data available interrupt Disabled.
+ * |        |          |1 = Receive data available interrupt Enabled.
+ * |[1]     |THREIEN   |Transmit Holding Register Empty Interrupt Enable Bit
+ * |        |          |0 = Transmit holding register empty interrupt Disabled.
+ * |        |          |1 = Transmit holding register empty interrupt Enabled.
+ * |[2]     |RLSIEN    |Receive Line Status Interrupt Enable Bit
+ * |        |          |0 = Receive Line Status interrupt Disabled.
+ * |        |          |1 = Receive Line Status interrupt Enabled.
+ * |[3]     |MODEMIEN  |Modem Status Interrupt Enable Bit
+ * |        |          |0 = Modem status interrupt Disabled.
+ * |        |          |1 = Modem status interrupt Enabled.
+ * |[4]     |RXTOIEN   |RX Time-Out Interrupt Enable Bit
+ * |        |          |0 = RX time-out interrupt Disabled.
+ * |        |          |1 = RX time-out interrupt Enabled.
+ * |[5]     |BUFERRIEN |Buffer Error Interrupt Enable Bit
+ * |        |          |0 = Buffer error interrupt Disabled.
+ * |        |          |1 = Buffer error interrupt Enabled.
+ * |[8]     |LINIEN    |LIN Bus Interrupt Enable Bit (Not Available In UART2/UART3)
+ * |        |          |0 = LIN bus interrupt Disabled.
+ * |        |          |1 = LIN bus interrupt Enabled.
+ * |        |          |Note: This bit is used for LIN function mode.
+ * |[9]     |WKCTSIEN  |nCTS Wake-Up Interrupt Enable Bit
+ * |        |          |0 = nCTS wake-up system function Disabled.
+ * |        |          |1 = Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode.
+ * |[10]    |WKDATIEN  |Incoming Data Wake-Up Interrupt Enable Bit
+ * |        |          |0 = Incoming data wake-up system function Disabled.
+ * |        |          |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
+ * |        |          |Note: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable
+ * |[11]    |TOCNTEN   |Time-Out Counter Enable Bit
+ * |        |          |0 = Time-out counter Disabled.
+ * |        |          |1 = Time-out counter Enabled.
+ * |[12]    |ATORTSEN  |nRTS Auto-Flow Control Enable Bit
+ * |        |          |0 = nRTS auto-flow control Disabled.
+ * |        |          |1 = nRTS auto-flow control Enabled.
+ * |        |          |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
+ * |[13]    |ATOCTSEN  |nCTS Auto-Flow Control Enable Bit
+ * |        |          |0 = nCTS auto-flow control Disabled.
+ * |        |          |1 = nCTS auto-flow control Enabled.
+ * |        |          |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
+ * |[14]    |TXPDMAEN  |TX DMA Enable Bit
+ * |        |          |This bit can enable or disable TX DMA service.
+ * |        |          |0 = TX DMA Disabled.
+ * |        |          |1 = TX DMA Enabled.
+ * |[15]    |RXPDMAEN  |RX DMA Enable Bit
+ * |        |          |This bit can enable or disable RX DMA service.
+ * |        |          |0 = RX DMA Disabled.
+ * |        |          |1 = RX DMA Enabled.
+ * |[18]    |ABRIEN    |Auto-Baud Rate Interrupt Enable Bit
+ * |        |          |0 = Auto-baud rate interrupt Disabled.
+ * |        |          |1 = Auto-baud rate interrupt Enabled.
+ * @var UART_T::FIFO
+ * Offset: 0x08  UART FIFO Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1]     |RXRST     |RX Field Software Reset
+ * |        |          |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
+ * |        |          |0 = No effect.
+ * |        |          |1 = Reset the RX internal state machine and pointers.
+ * |        |          |Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
+ * |[2]     |TXRST     |TX Field Software Reset
+ * |        |          |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
+ * |        |          |0 = No effect.
+ * |        |          |1 = Reset the TX internal state machine and pointers.
+ * |        |          |Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
+ * |[7:4]   |RFITL     |RX FIFO Interrupt Trigger Level
+ * |        |          |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
+ * |        |          |0000 = RX FIFO Interrupt Trigger Level is 1 byte.
+ * |        |          |0001 = RX FIFO Interrupt Trigger Level is 4 bytes.
+ * |        |          |0010 = RX FIFO Interrupt Trigger Level is 8 bytes.
+ * |        |          |0011 = RX FIFO Interrupt Trigger Level is 14 bytes.
+ * |        |          |Others = Reserved.
+ * |[8]     |RXOFF     |Receiver Disable
+ * |        |          |The receiver is disabled or not (set 1 to disable receiver)
+ * |        |          |0 = Receiver Enabled.
+ * |        |          |1 = Receiver Disabled.
+ * |        |          |Note: This bit is used for RS-485 Normal Multi-drop mode.
+ * |        |          |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
+ * |[19:16] |RTSTRGLV  |nRTS Trigger Level For Auto-Flow Control Use
+ * |        |          |0000 = nRTS Trigger Level is 1 bytes.
+ * |        |          |0001 = nRTS Trigger Level is 4bytes.
+ * |        |          |0010 = nRTS Trigger Level is 8 bytes.
+ * |        |          |0011 = nRTS Trigger Level is 14 bytes.
+ * |        |          |Others = Reserved.
+ * |        |          |Note: This field is used for auto nRTS flow control.
+ * @var UART_T::LINE
+ * Offset: 0x0C  UART Line Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |WLS       |Word Length Selection
+ * |        |          |This field sets UART word length.
+ * |        |          |00 = 5 bits.
+ * |        |          |01 = 6 bits.
+ * |        |          |10 = 7 bits.
+ * |        |          |11 = 8 bits.
+ * |[2]     |NSB       |Number Of "STOP Bit"
+ * |        |          |0 = One "STOP bit" is generated in the transmitted data.
+ * |        |          |1 = When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data.
+ * |        |          |When select 6-, 7- and 8-bit word length, 2 "STOP bit" is generated in the transmitted data.
+ * |[3]     |PBE       |Parity Bit Enable Bit
+ * |        |          |0 = No parity bit generated Disabled.
+ * |        |          |1 = Parity bit generated Enabled.
+ * |        |          |Note : Parity bit is generated on each outgoing character and is checked on each incoming data.
+ * |[4]     |EPE       |Even Parity Enable Bit
+ * |        |          |0 = Odd number of logic 1's is transmitted and checked in each word.
+ * |        |          |1 = Even number of logic 1's is transmitted and checked in each word.
+ * |        |          |Note:This bit has effect only when PBE (UART_LINE[3]) is set.
+ * |[5]     |SPE       |Stick Parity Enable Bit
+ * |        |          |0 = Stick parity Disabled.
+ * |        |          |1 = Stick parity Enabled.
+ * |        |          |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0.
+ * |        |          |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
+ * |[6]     |BCB       |Break Control Bit
+ * |        |          |0 = Break Control Disabled.
+ * |        |          |1 = Break Control Enabled.
+ * |        |          |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
+ * |        |          |This bit acts only on TX line and has no effect on the transmitter logic.
+ * @var UART_T::MODEM
+ * Offset: 0x10  UART Modem Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1]     |RTS       |nRTS (Request-To-Send) Signal Control
+ * |        |          |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
+ * |        |          |0 = nRTS signal is active.
+ * |        |          |1 = nRTS signal is inactive.
+ * |        |          |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
+ * |        |          |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
+ * |[9]     |RTSACTLV  |nRTS Pin Active Level
+ * |        |          |This bit defines the active level state of nRTS pin output.
+ * |        |          |0 =n RTS pin output is high level active.
+ * |        |          |1 = nRTS pin output is low level active. (Default)
+ * |        |          |Note1: Refer to Figure 6.21-10 and Figure 6.21-11 for UART function mode.
+ * |        |          |Note2: Refer to Figure 6.21-21 and Figure 6.21-22 for RS-485 function mode.
+ * |[13]    |RTSSTS    |nRTS Pin Status (Read Only)
+ * |        |          |This bit mirror from nRTS pin output of voltage logic status.
+ * |        |          |0 = nRTS pin output is low level voltage logic state.
+ * |        |          |1 = nRTS pin output is high level voltage logic state.
+ * @var UART_T::MODEMSTS
+ * Offset: 0x14  UART Modem Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |CTSDETF   |Detect nCTS State Change Flag (Read Only)
+ * |        |          |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
+ * |        |          |0 = nCTS input has not change state.
+ * |        |          |1 = nCTS input has change state.
+ * |        |          |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[4]     |CTSSTS    |nCTS Pin Status (Read Only)
+ * |        |          |This bit mirror from nCTS pin input of voltage logic status.
+ * |        |          |0 = nCTS pin input is low level voltage logic state.
+ * |        |          |1 = nCTS pin input is high level voltage logic state.
+ * |        |          |Note: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
+ * |[8]     |CTSACTLV  |nCTS Pin Active Level
+ * |        |          |This bit defines the active level state of nCTS pin input.
+ * |        |          |0 = nCTS pin input is high level active.
+ * |        |          |1 = nCTS pin input is low level active. (Default)
+ * @var UART_T::FIFOSTS
+ * Offset: 0x18  UART FIFO Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |RXOVIF    |RX Overflow Error Interrupt Flag (Read Only)
+ * |        |          |This bit is set when RX FIFO overflow.
+ * |        |          |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.
+ * |        |          |0 = RX FIFO is not overflow.
+ * |        |          |1 = RX FIFO is overflow.
+ * |        |          |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[1]     |ABRDIF    |Auto-Baud Rate Detect Interrupt (Read Only)
+ * |        |          |0 = Auto-baud rate detect function is not finished.
+ * |        |          |1 = Auto-baud rate detect function is finished.
+ * |        |          |This bit is set to logic "1" when auto-baud rate detect function is finished.
+ * |        |          |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[2]     |ABRDTOIF  |Auto-Baud Rate Time-Out Interrupt (Read Only)
+ * |        |          |0 = Auto-baud rate counter is underflow.
+ * |        |          |1 = Auto-baud rate counter is overflow.
+ * |        |          |Note1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.
+ * |        |          |Note2: This bit is read only, but can be cleared by writing "1" to it.
+ * |[3]     |ADDRDETF  |RS-485 Address Byte Detect Flag (Read Only)
+ * |        |          |0 = Receiver detects a data that is not an address bit (bit 9 ='0').
+ * |        |          |1 = Receiver detects a data that is an address bit (bit 9 ='1').
+ * |        |          |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .
+ * |        |          |Note2: This bit is read only, but can be cleared by writing '1' to it.
+ * |[4]     |PEF       |Parity Error Flag (Read Only)
+ * |        |          |This bit is set to logic 1 whenever the received character does not have a valid "parity bit".
+ * |        |          |0 = No parity error is generated.
+ * |        |          |1 = Parity error is generated.
+ * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+ * |[5]     |FEF       |Framing Error Flag (Read Only)
+ * |        |          |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
+ * |        |          |0 = No framing error is generated.
+ * |        |          |1 = Framing error is generated.
+ * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+ * |[6]     |BIF       |Break Interrupt Flag (Read Only)
+ * |        |          |This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
+ * |        |          |0 = No Break interrupt is generated.
+ * |        |          |1 = Break interrupt is generated.
+ * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+ * |[13:8]  |RXPTR     |RX FIFO Pointer (Read Only)
+ * |        |          |This field indicates the RX FIFO Buffer Pointer.
+ * |        |          |When UART receives one byte from external device, RXPTR increases one.
+ * |        |          |When one byte of RX FIFO is read by CPU, RXPTR decreases one.
+ * |        |          |The Maximum value shown in RXPTR is 15.
+ * |        |          |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0.
+ * |        |          |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
+ * |[14]    |RXEMPTY   |Receiver FIFO Empty (Read Only)
+ * |        |          |This bit initiate RX FIFO empty or not.
+ * |        |          |0 = RX FIFO is not empty.
+ * |        |          |1 = RX FIFO is empty.
+ * |        |          |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high.
+ * |        |          |It will be cleared when UART receives any new data.
+ * |[15]    |RXFULL    |Receiver FIFO Full (Read Only)
+ * |        |          |This bit initiates RX FIFO full or not.
+ * |        |          |0 = RX FIFO is not full.
+ * |        |          |1 = RX FIFO is full.
+ * |        |          |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
+ * |[21:16] |TXPTR     |TX FIFO Pointer (Read Only)
+ * |        |          |This field indicates the TX FIFO Buffer Pointer.
+ * |        |          |When CPU writes one byte into UART_DAT, TXPTR increases one.
+ * |        |          |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
+ * |        |          |The Maximum value shown in TXPTR is 15.
+ * |        |          |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0.
+ * |        |          |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
+ * |[22]    |TXEMPTY   |Transmitter FIFO Empty (Read Only)
+ * |        |          |This bit indicates TX FIFO empty or not.
+ * |        |          |0 = TX FIFO is not empty.
+ * |        |          |1 = TX FIFO is empty.
+ * |        |          |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
+ * |        |          |It will be cleared when writing data into DAT (TX FIFO not empty).
+ * |[23]    |TXFULL    |Transmitter FIFO Full (Read Only)
+ * |        |          |This bit indicates TX FIFO full or not.
+ * |        |          |0 = TX FIFO is not full.
+ * |        |          |1 = TX FIFO is full.
+ * |        |          |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
+ * |[24]    |TXOVIF    |TX Overflow Error Interrupt Flag (Read Only)
+ * |        |          |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
+ * |        |          |0 = TX FIFO is not overflow.
+ * |        |          |1 = TX FIFO is overflow.
+ * |        |          |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[28]    |TXEMPTYF  |Transmitter Empty Flag (Read Only)
+ * |        |          |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
+ * |        |          |0 = TX FIFO is not empty.
+ * |        |          |1 = TX FIFO is empty.
+ * |        |          |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
+ * @var UART_T::INTSTS
+ * Offset: 0x1C  UART Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |RDAIF     |Receive Data Available Interrupt Flag (Read Only)
+ * |        |          |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set.
+ * |        |          |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
+ * |        |          |0 = No RDA interrupt flag is generated.
+ * |        |          |1 = RDA interrupt flag is generated.
+ * |        |          |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4])).
+ * |[1]     |THREIF    |Transmit Holding Register Empty Interrupt Flag (Read Only)
+ * |        |          |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register.
+ * |        |          |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
+ * |        |          |0 = No THRE interrupt flag is generated.
+ * |        |          |1 = THRE interrupt flag is generated.
+ * |        |          |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
+ * |[2]     |RLSIF     |Receive Line Interrupt Flag (Read Only)
+ * |        |          |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set).
+ * |        |          |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
+ * |        |          |0 = No RLS interrupt flag is generated.
+ * |        |          |1 = RLS interrupt flag is generated.
+ * |        |          |Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = '1') bit.
+ * |        |          |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.
+ * |        |          |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
+ * |        |          |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
+ * |[3]     |MODEMIF   |MODEM Interrupt Flag (Read Only) Channel This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
+ * |        |          |0 = No Modem interrupt flag is generated.
+ * |        |          |1 = Modem interrupt flag is generated.
+ * |        |          |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
+ * |[4]     |RXTOIF    |Time-Out Interrupt Flag (Read Only)
+ * |        |          |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC.
+ * |        |          |If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
+ * |        |          |0 = No Time-out interrupt flag is generated.
+ * |        |          |1 = Time-out interrupt flag is generated.
+ * |        |          |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
+ * |[5]     |BUFERRIF  |Buffer Error Interrupt Flag (Read Only)
+ * |        |          |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set).
+ * |        |          |When BERRIF (UART_INTSTS[5])is set, the transfer is not correct.
+ * |        |          |If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.
+ * |        |          |0 = No buffer error interrupt flag is generated.
+ * |        |          |1 = Buffer error interrupt flag is generated.
+ * |        |          |Note: This bit is read only.
+ * |        |          |This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
+ * |[6]     |WKIF      |UART Wake-up Interrupt Flag (Read Only)
+ * |        |          |This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.
+ * |        |          |0 = No DATWKIF and CTSWKIF are generated.
+ * |        |          |1 = DATWKIF or CTSWKIF.
+ * |        |          |Note: This bit is read only.
+ * |        |          |This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]).
+ * |[7]     |LINIF     |LIN Bus Interrupt Flag (Read Only) (Not Available in UART2/UART3 Channel)
+ * |        |          |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] =1)), LIN break detect (BRKDETF(UART_LINSTS[9])=1), bit error detect (BITEF(UART_LINSTS[9])=1), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2]) = 1) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])).
+ * |        |          |If LIN_ IEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.
+ * |        |          |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
+ * |        |          |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
+ * |        |          |Note: This bit is read only.
+ * |        |          |This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]), SLVHEF(UART_LINSTS[1]) and SLVSYNCF(UART_LINSTS[3]) all are cleared.
+ * |[8]     |RDAINT    |Receive Data Available Interrupt Indicator (Read Only)
+ * |        |          |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
+ * |        |          |0 = No RDA interrupt is generated.
+ * |        |          |1 = RDA interrupt is generated.
+ * |[9]     |THREINT   |Transmit Holding Register Empty Interrupt Indicator (Read Only)
+ * |        |          |This bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1.
+ * |        |          |0 = No DATE interrupt is generated.
+ * |        |          |1 = DATE interrupt is generated.
+ * |[10]    |RLSINT    |Receive Line Status Interrupt Indicator (Read Only)
+ * |        |          |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
+ * |        |          |0 = No RLS interrupt is generated.
+ * |        |          |1 = RLS interrupt is generated.
+ * |[11]    |MODEMINT  |MODEM Status Interrupt Indicator (Read Only)
+ * |        |          |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[4]) are both set to 1
+ * |        |          |0 = No Modem interrupt is generated.
+ * |        |          |1 = Modem interrupt is generated.
+ * |[12]    |RXTOINT   |Time-Out Interrupt Indicator (Read Only)
+ * |        |          |This bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
+ * |        |          |0 = No Tout interrupt is generated.
+ * |        |          |1 = Tout interrupt is generated.
+ * |[13]    |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)
+ * |        |          |This bit is set if BFERRIEN(UART_INTEN[5]) and BERRIF(UART_INTSTS[5]) are both set to 1.
+ * |        |          |0 = No buffer error interrupt is generated.
+ * |        |          |1 = Buffer error interrupt is generated.
+ * |[15]    |LININT    |LIN Bus Interrupt Indicator (Read Only)(Not Available in UART2/UART3 Channel)
+ * |        |          |This bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1.
+ * |        |          |0 = No LIN Bus interrupt is generated.
+ * |        |          |1 = The LIN Bus interrupt is generated.
+ * |[16]    |CTSWKIF   |nCTS Wake-Up Interrupt Flag (Read Only)
+ * |        |          |0 = Chip stays in power-down state.
+ * |        |          |1 = Chip wake-up from power-down state by nCTS wake-up.
+ * |        |          |Note1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.
+ * |        |          |Note2: This bit is read only, but can be cleared by writing '1' to it.
+ * |[17]    |DATWKIF   |Data Wake-Up Interrupt Flag (Read Only)
+ * |        |          |This bit is set if chip wake-up from power-down state by data wake-up.
+ * |        |          |0 = Chip stays in power-down state.
+ * |        |          |1 = Chip wake-up from power-down state by data wake-up.
+ * |        |          |Note1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.
+ * |        |          |Note2: This bit is read only, but can be cleared by writing '1' to it.
+ * |[18]    |HWRLSIF   |In DMA Mode, Receive Line Status Flag (Read Only)
+ * |        |          |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set).
+ * |        |          |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
+ * |        |          |0 = No RLS interrupt flag is generated.
+ * |        |          |1 = RLS interrupt flag is generated.
+ * |        |          |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = '1') bit.
+ * |        |          |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
+ * |        |          |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared
+ * |[19]    |HWMODIF   |In DMA Mode, MODEM Interrupt Flag (Read Only)
+ * |        |          |This bit is set when the nCTS pin has state change (CTSDETF (UART_CTSDETF[0] =1)).
+ * |        |          |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
+ * |        |          |0 = No Modem interrupt flag is generated.
+ * |        |          |1 = Modem interrupt flag is generated.
+ * |        |          |Note: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0]).
+ * |[20]    |HWTOIF    |In DMA Mode, Time-Out Interrupt Flag (Read Only)
+ * |        |          |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]).
+ * |        |          |If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
+ * |        |          |0 = No Time-out interrupt flag is generated.
+ * |        |          |1 = Time-out interrupt flag is generated.
+ * |        |          |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
+ * |[21]    |HWBUFEIF  |In DMA Mode, Buffer Error Interrupt Flag (Read Only)
+ * |        |          |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set).
+ * |        |          |When BERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct.
+ * |        |          |If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
+ * |        |          |0 = No buffer error interrupt flag is generated.
+ * |        |          |1 = Buffer error interrupt flag is generated.
+ * |        |          |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
+ * |[26]    |HWRLSINT  |In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)
+ * |        |          |This bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1.
+ * |        |          |0 = No RLS interrupt is generated in DMA mode.
+ * |        |          |1 = RLS interrupt is generated in DMA mode.
+ * |[27]    |HWMODINT  |In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
+ * |        |          |This bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1.
+ * |        |          |0 = No Modem interrupt is generated in DMA mode.
+ * |        |          |1 = Modem interrupt is generated in DMA mode.
+ * |[28]    |HWTOINT   |In DMA Mode, Time-Out Interrupt Indicator (Read Only)
+ * |        |          |This bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1.
+ * |        |          |0 = No Tout interrupt is generated in DMA mode.
+ * |        |          |1 = Tout interrupt is generated in DMA mode.
+ * |[29]    |HWBUFEINT |In DMA Mode, Buffer Error Interrupt Indicator (Read Only)
+ * |        |          |This bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1.
+ * |        |          |0 = No buffer error interrupt is generated in DMA mode.
+ * |        |          |1 = Buffer error interrupt is generated in DMA mode.
+ * @var UART_T::TOUT
+ * Offset: 0x20  UART Time-out Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |TOIC      |Time-Out Interrupt Comparator
+ * |        |          |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word.
+ * |        |          |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled.
+ * |        |          |A new incoming data word or RX FIFO empty will clear RXTOINT(UART_INTSTS[12]).
+ * |        |          |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255.
+ * |        |          |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
+ * |[15:8]  |DLY       |TX Delay Time Value
+ * |        |          |This field is used to programming the transfer delay time between the last stop bit and next start bit.
+ * |        |          |The unit is bit time.
+ * @var UART_T::BAUD
+ * Offset: 0x24  UART Baud Rate Divisor Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |BRD       |Baud Rate Divider
+ * |        |          |The field indicates the baud rate divider.
+ * |        |          |This filed is used in baud rate calculation.
+ * |        |          |The detail description is shown in Table 6.21-2.
+ * |[27:24] |EDIVM1    |Extra Divider For BAUD Rate Mode 1
+ * |        |          |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2.
+ * |        |          |The detail description is shown in Table 6.21-2.
+ * |[28]    |BAUDM0    |BAUD Rate Mode Selection Bit 0
+ * |        |          |This bit is baud rate mode selection bit 0.
+ * |        |          |UART provides three baud rate calculation modes.
+ * |        |          |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode.
+ * |        |          |The detail description is shown in Table 6.21-2.
+ * |[29]    |BAUDM1    |BAUD Rate Mode Selection Bit 1
+ * |        |          |This bit is baud rate mode selection bit 1.
+ * |        |          |UART provides three baud rate calculation modes.
+ * |        |          |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode.
+ * |        |          |The detail description is shown in Table 6.21-2.
+ * |        |          |Note: In IrDA mode must be operated in mode 0.
+ * @var UART_T::IRDA
+ * Offset: 0x28  UART IrDA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1]     |TXEN      |IrDA Receiver/Transmitter Selection Enable Bit
+ * |        |          |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)
+ * |        |          |1 = IrDA Transmitter Enabled and Receiver Disabled.
+ * |        |          |Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.
+ * |[5]     |TXINV     |IrDA Inverse Transmitting Output Signal
+ * |        |          |0 = None inverse transmitting signal. (Default)
+ * |        |          |1 = Inverse transmitting output signal.
+ * |[6]     |RXINV     |IrDA Inverse Receive Input Signal
+ * |        |          |0 = None inverse receiving input signal.
+ * |        |          |1 = Inverse receiving input signal. (Default)
+ * @var UART_T::ALTCTL
+ * Offset: 0x2C  UART Alternate Control/Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |BRKFL     |UART LIN Break Field Length (Only Available In UART0/UART1 Channel)
+ * |        |          |This field indicates a 4-bit LIN TX break field count.
+ * |        |          |Note1: This break field length is BRKFL + 1
+ * |        |          |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
+ * |[6]     |LINRXEN   |LIN RX Enable Bit (Only Available In UART0/UART1 Channel)
+ * |        |          |0 = LIN RX mode Disabled.
+ * |        |          |1 = LIN RX mode Enabled.
+ * |[7]     |LINTXEN   |LIN TX Break Mode Enable Bit (Only Available In UART0/UART1 Channel)
+ * |        |          |0 = LIN TX Break mode Disabled.
+ * |        |          |1 = LIN TX Break mode Enabled.
+ * |        |          |Note: When TX break field transfer operation finished, this bit will be cleared automatically.
+ * |[8]     |RS485NMM  |RS-485 Normal Multi-Drop Operation Mode (NMM)
+ * |        |          |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
+ * |        |          |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
+ * |        |          |Note: It cannot be active with RS-485_AAD operation mode.
+ * |[9]     |RS485AAD  |RS-485 Auto Address Detection Operation Mode (AAD)
+ * |        |          |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
+ * |        |          |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
+ * |        |          |Note: It cannot be active with RS-485_NMM operation mode.
+ * |[10]    |RS485AUD  |RS-485 Auto Direction Function (AUD)
+ * |        |          |0 = RS-485 Auto Direction Operation function (AUD) Disabled.
+ * |        |          |1 = RS-485 Auto Direction Operation function (AUD) Enabled.
+ * |        |          |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
+ * |[15]    |ADDRDEN   |RS-485 Address Detection Enable Bit
+ * |        |          |This bit is used to enable RS-485 Address Detection mode.
+ * |        |          |0 = Address detection mode Disabled.
+ * |        |          |1 = Address detection mode Enabled.
+ * |        |          |Note: This bit is used for RS-485 any operation mode.
+ * |[17]    |ABRIF     |Auto-Baud Rate Interrupt Flag (Read Only)
+ * |        |          |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
+ * |        |          |Note: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1])
+ * |[18]    |ABRDEN    |Auto-Baud Rate Detect Enable Bit
+ * |        |          |0 = Auto-baud rate detect function Disabled.
+ * |        |          |1 = Auto-baud rate detect function Enabled.
+ * |        |          |This bit is cleared automatically after auto-baud detection is finished.
+ * |[20:19] |ABRDBITS  |Auto-Baud Rate Detect Bit Length
+ * |        |          |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01.
+ * |        |          |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02.
+ * |        |          |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08.
+ * |        |          |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80.
+ * |        |          |Note : The calculation of bit number includes the START bit.
+ * |[31:24] |ADDRMV    |Address Match Value
+ * |        |          |This field contains the RS-485 address match values.
+ * |        |          |Note: This field is used for RS-485 auto address detection mode.
+ * @var UART_T::FUNCSEL
+ * Offset: 0x30  UART Function Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |FUNCSEL   |Function Select
+ * |        |          |00 = UART function.
+ * |        |          |01 = LIN function (Only Available in UART0/UART1 Channel).
+ * |        |          |10 = IrDA function.
+ * |        |          |11 = RS-485 function.
+ * |        |          |Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.
+ * @var UART_T::LINCTL
+ * Offset: 0x34  UART LIN Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SLVEN     |LIN Slave Mode Enable Bit
+ * |        |          |0 = LIN slave mode Disabled.
+ * |        |          |1 = LIN slave mode Enabled.
+ * |[1]     |SLVHDEN   |LIN Slave Header Detection Enable Bit
+ * |        |          |0 = LIN slave header detection Disabled.
+ * |        |          |1 = LIN slave header detection Enabled.
+ * |        |          |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+ * |        |          |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted.
+ * |        |          |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+ * |[2]     |SLVAREN   |LIN Slave Automatic Resynchronization Mode Enable Bit
+ * |        |          |0 = LIN automatic resynchronization Disabled.
+ * |        |          |1 = LIN automatic resynchronization Enabled.
+ * |        |          |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+ * |        |          |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).
+ * |        |          |Note3: The control and interactions of this field are explained in 6.21.5.9(Slave mode with automatic resynchronization).
+ * |[3]     |SLVDUEN   |LIN Slave Divider Update Method Enable Bit
+ * |        |          |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time).
+ * |        |          |1 = UART_BAUD is updated at the next received character.
+ * |        |          |User must set the bit before checksum reception.
+ * |        |          |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+ * |        |          |Note2: This bit used for LIN Slave Automatic Resynchronization mode.
+ * |        |          |(for Non-Automatic Resynchronization mode, this bit should be kept cleared).
+ * |        |          |Note3: The control and interactions of this field are explained in 6.21.5.9 (Slave mode with automatic resynchronization).
+ * |[4]     |MUTE      |LIN Mute Mode Enable Bit
+ * |        |          |0 = LIN mute mode Disabled.
+ * |        |          |1 = LIN mute mode Enabled.
+ * |        |          |Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.21.5.9 (LIN slave mode).
+ * |[8]     |SENDH     |LIN TX Send Header Enable Bit
+ * |        |          |The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting HSEL (UART_LINCTL[23:22]).
+ * |        |          |0 = Send LIN TX header Disabled.
+ * |        |          |1 = Send LIN TX header Enabled.
+ * |        |          |Note1: These registers are shadow registers of SENDH (UART_ALTCTL [7]); user can read/write it by setting SENDH (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
+ * |        |          |Note2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
+ * |[9]     |IDPEN     |LIN ID Parity Enable Bit
+ * |        |          |0 = LIN frame ID parity Disabled.
+ * |        |          |1 = LIN frame ID parity Enabled.
+ * |        |          |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8]) = 1 and HSEL (UART_LINCTL[23:22]) = 10) or be used for enable LIN slave received frame ID parity checked.
+ * |        |          |Note2: This bit is only use when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10
+ * |[10]    |BRKDETEN  |LIN Break Detection Enable Bit
+ * |        |          |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set in UART_LINSTS register at the end of break field.
+ * |        |          |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated.
+ * |        |          |0 = LIN break detection Disabled .
+ * |        |          |1 = LIN break detection Enabled.
+ * |[11]    |RXOFF     |LIN Receiver Disable Bit
+ * |        |          |If the receiver is enabled (RXOFF (UART_LINCTL[11] ) = 0), 
+ * |        |          |all received byte data will be accepted and stored in the RX-FIFO, 
+ * |        |          |and if the receiver is disabled (RXOFF (UART_LINCTL[11]) = 1), all received byte data will be ignore.
+ * |        |          |0 = LIN receiver Enabled.
+ * |        |          |1 = LIN receiver Disabled.
+ * |        |          |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01).
+ * |[12]    |BITERREN  |Bit Error Detect Enable Bit
+ * |        |          |0 = Bit error detection function Disabled.
+ * |        |          |1 = Bit error detection Enabled.
+ * |        |          |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted.
+ * |        |          |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+ * |[19:16] |BRKFL     |LIN Break Field Length
+ * |        |          |This field indicates a 4-bit LIN TX break field count.
+ * |        |          |Note1: These registers are shadow registers of BRKFL, User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).
+ * |        |          |Note2: This break field length is BRKFL + 1.
+ * |        |          |Note3: According to LIN spec, the reset value is 12 (break field length = 13).
+ * |[21:20] |BSL       |LIN Break/Sync Delimiter Length
+ * |        |          |00 = The LIN break/sync delimiter length is 1-bit time.
+ * |        |          |01 = The LIN break/sync delimiter length is 2-bit time.
+ * |        |          |10 = The LIN break/sync delimiter length is 3-bit time.
+ * |        |          |11 = The LIN break/sync delimiter length is 4-bit time.
+ * |        |          |Note: This bit used for LIN master to sending header field.
+ * |[23:22] |HSEL      |LIN Header Select
+ * |        |          |00 = The LIN header includes "break field".
+ * |        |          |01 = The LIN header includes "break field" and "sync field".
+ * |        |          |10 = The LIN header includes "break field", "sync field" and "frame ID field".
+ * |        |          |11 = Reserved.
+ * |        |          |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4]) = 1).
+ * |[31:24] |PID       |LIN PID Bits
+ * |        |          |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.
+ * |        |          |If the parity generated by hardware, user fill ID0~ID5, (PID [29:24] )hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.
+ * |        |          |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).
+ * |        |          |Note2: This field can be used for LIN master mode or slave mode.
+ * @var UART_T::LINSTS
+ * Offset: 0x38  UART LIN Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SLVHDETF  |LIN Slave Header Detection Flag (Read Only)
+ * |        |          |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
+ * |        |          |0 = LIN header not detected.
+ * |        |          |1 = LIN header detected (break + sync + frame ID).
+ * |        |          |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * |        |          |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
+ * |        |          |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ("break + sync + frame ID"), the SLVHDETF will be set whether the frame ID correct or not.
+ * |[1]     |SLVHEF    |LIN Slave Header Error Flag (Read Only)
+ * |        |          |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it.
+ * |        |          |The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out".
+ * |        |          |0 = LIN header error not detected.
+ * |        |          |1 = LIN header error detected.
+ * |        |          |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * |        |          |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
+ * |[2]     |SLVIDPEF  |LIN Slave ID Parity Error Flag
+ * |        |          |This bit is set by hardware when receipted frame ID parity is not correct.
+ * |        |          |0 = No active.
+ * |        |          |1 = Receipted frame ID parity is not correct.
+ * |        |          |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * |        |          |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).
+ * |[3]     |SLVSYNCF  |LIN Slave Sync Field (Read Only)
+ * |        |          |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode.
+ * |        |          |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.
+ * |        |          |0 = The current character is not at LIN sync state.
+ * |        |          |1 = The current character is at LIN sync state.
+ * |        |          |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1).
+ * |        |          |Note2: This bit is read only, but it can be cleared by writing 1 to it.
+ * |        |          |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
+ * |[8]     |BRKDETF   |LIN Break Detection Flag (Read Only)
+ * |        |          |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.
+ * |        |          |0 = LIN break not detected.
+ * |        |          |1 = LIN break detected.
+ * |        |          |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * |        |          |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1).
+ * |[9]     |BITEF     |Bit Error Detect Status Flag (Read Only)
+ * |        |          |At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF (UART_LINSTS[9]) will be set.
+ * |        |          |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+ * |        |          |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * |        |          |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1).
+ */
+
+    __IO uint32_t DAT;           /* Offset: 0x00  UART Receive/Transmit Buffer Register                              */
+    __IO uint32_t INTEN;         /* Offset: 0x04  UART Interrupt Enable Register                                     */
+    __IO uint32_t FIFO;          /* Offset: 0x08  UART FIFO Control Register                                         */
+    __IO uint32_t LINE;          /* Offset: 0x0C  UART Line Control Register                                         */
+    __IO uint32_t MODEM;         /* Offset: 0x10  UART Modem Control Register                                        */
+    __IO uint32_t MODEMSTS;      /* Offset: 0x14  UART Modem Status Register                                         */
+    __IO uint32_t FIFOSTS;       /* Offset: 0x18  UART FIFO Status Register                                          */
+    __IO uint32_t INTSTS;        /* Offset: 0x1C  UART Interrupt Status Register                                     */
+    __IO uint32_t TOUT;          /* Offset: 0x20  UART Time-out Register                                             */
+    __IO uint32_t BAUD;          /* Offset: 0x24  UART Baud Rate Divisor Register                                    */
+    __IO uint32_t IRDA;          /* Offset: 0x28  UART IrDA Control Register                                         */
+    __IO uint32_t ALTCTL;        /* Offset: 0x2C  UART Alternate Control/Status Register                             */
+    __IO uint32_t FUNCSEL;       /* Offset: 0x30  UART Function Select Register                                      */
+    __IO uint32_t LINCTL;        /* Offset: 0x34  UART LIN Control Register                                          */
+    __IO uint32_t LINSTS;        /* Offset: 0x38  UART LIN Status Register                                           */
+
+} UART_T;
+
+
+
+/**
+    @addtogroup UART_CONST UART Bit Field Definition
+    Constant Definitions for UART Controller
+@{ */
+
+#define UART_DAT_DAT_Pos                 (0)                                               /*!< UART_T::DAT: DAT Position                 */
+#define UART_DAT_DAT_Msk                 (0xfful << UART_DAT_DAT_Pos)                      /*!< UART_T::DAT: DAT Mask                     */
+
+#define UART_INTEN_RDAIEN_Pos            (0)                                               /*!< UART_T::INTEN: RDAIEN Position            */
+#define UART_INTEN_RDAIEN_Msk            (0x1ul << UART_INTEN_RDAIEN_Pos)                  /*!< UART_T::INTEN: RDAIEN Mask                */
+
+#define UART_INTEN_THREIEN_Pos           (1)                                               /*!< UART_T::INTEN: THREIEN Position           */
+#define UART_INTEN_THREIEN_Msk           (0x1ul << UART_INTEN_THREIEN_Pos)                 /*!< UART_T::INTEN: THREIEN Mask               */
+
+#define UART_INTEN_RLSIEN_Pos            (2)                                               /*!< UART_T::INTEN: RLSIEN Position            */
+#define UART_INTEN_RLSIEN_Msk            (0x1ul << UART_INTEN_RLSIEN_Pos)                  /*!< UART_T::INTEN: RLSIEN Mask                */
+
+#define UART_INTEN_MODEMIEN_Pos          (3)                                               /*!< UART_T::INTEN: MODEMIEN Position          */
+#define UART_INTEN_MODEMIEN_Msk          (0x1ul << UART_INTEN_MODEMIEN_Pos)                /*!< UART_T::INTEN: MODEMIEN Mask              */
+
+#define UART_INTEN_RXTOIEN_Pos           (4)                                               /*!< UART_T::INTEN: RXTOIEN Position           */
+#define UART_INTEN_RXTOIEN_Msk           (0x1ul << UART_INTEN_RXTOIEN_Pos)                 /*!< UART_T::INTEN: RXTOIEN Mask               */
+
+#define UART_INTEN_BUFERRIEN_Pos         (5)                                               /*!< UART_T::INTEN: BUFERRIEN Position         */
+#define UART_INTEN_BUFERRIEN_Msk         (0x1ul << UART_INTEN_BUFERRIEN_Pos)               /*!< UART_T::INTEN: BUFERRIEN Mask             */
+
+#define UART_INTEN_LINIEN_Pos            (8)                                               /*!< UART_T::INTEN: LINIEN Position            */
+#define UART_INTEN_LINIEN_Msk            (0x1ul << UART_INTEN_LINIEN_Pos)                  /*!< UART_T::INTEN: LINIEN Mask                */
+
+#define UART_INTEN_WKCTSIEN_Pos          (9)                                               /*!< UART_T::INTEN: WKCTSIEN Position          */
+#define UART_INTEN_WKCTSIEN_Msk          (0x1ul << UART_INTEN_WKCTSIEN_Pos)                /*!< UART_T::INTEN: WKCTSIEN Mask              */
+
+#define UART_INTEN_WKDATIEN_Pos          (10)                                              /*!< UART_T::INTEN: WKDATIEN Position          */
+#define UART_INTEN_WKDATIEN_Msk          (0x1ul << UART_INTEN_WKDATIEN_Pos)                /*!< UART_T::INTEN: WKDATIEN Mask              */
+
+#define UART_INTEN_TOCNTEN_Pos           (11)                                              /*!< UART_T::INTEN: TOCNTEN Position           */
+#define UART_INTEN_TOCNTEN_Msk           (0x1ul << UART_INTEN_TOCNTEN_Pos)                 /*!< UART_T::INTEN: TOCNTEN Mask               */
+
+#define UART_INTEN_ATORTSEN_Pos          (12)                                              /*!< UART_T::INTEN: ATORTSEN Position          */
+#define UART_INTEN_ATORTSEN_Msk          (0x1ul << UART_INTEN_ATORTSEN_Pos)                /*!< UART_T::INTEN: ATORTSEN Mask              */
+
+#define UART_INTEN_ATOCTSEN_Pos          (13)                                              /*!< UART_T::INTEN: ATOCTSEN Position          */
+#define UART_INTEN_ATOCTSEN_Msk          (0x1ul << UART_INTEN_ATOCTSEN_Pos)                /*!< UART_T::INTEN: ATOCTSEN Mask              */
+
+#define UART_INTEN_TXPDMAEN_Pos          (14)                                              /*!< UART_T::INTEN: TXPDMAEN Position          */
+#define UART_INTEN_TXPDMAEN_Msk          (0x1ul << UART_INTEN_TXPDMAEN_Pos)                /*!< UART_T::INTEN: TXPDMAEN Mask              */
+
+#define UART_INTEN_RXPDMAEN_Pos          (15)                                              /*!< UART_T::INTEN: RXPDMAEN Position          */
+#define UART_INTEN_RXPDMAEN_Msk          (0x1ul << UART_INTEN_RXPDMAEN_Pos)                /*!< UART_T::INTEN: RXPDMAEN Mask              */
+
+#define UART_INTEN_ABRIEN_Pos            (18)                                              /*!< UART_T::INTEN: ABRIEN Position            */
+#define UART_INTEN_ABRIEN_Msk            (0x1ul << UART_INTEN_ABRIEN_Pos)                  /*!< UART_T::INTEN: ABRIEN Mask                */
+
+#define UART_FIFO_RXRST_Pos              (1)                                               /*!< UART_T::FIFO: RXRST Position              */
+#define UART_FIFO_RXRST_Msk              (0x1ul << UART_FIFO_RXRST_Pos)                    /*!< UART_T::FIFO: RXRST Mask                  */
+
+#define UART_FIFO_TXRST_Pos              (2)                                               /*!< UART_T::FIFO: TXRST Position              */
+#define UART_FIFO_TXRST_Msk              (0x1ul << UART_FIFO_TXRST_Pos)                    /*!< UART_T::FIFO: TXRST Mask                  */
+
+#define UART_FIFO_RFITL_Pos              (4)                                               /*!< UART_T::FIFO: RFITL Position              */
+#define UART_FIFO_RFITL_Msk              (0xful << UART_FIFO_RFITL_Pos)                    /*!< UART_T::FIFO: RFITL Mask                  */
+
+#define UART_FIFO_RXOFF_Pos              (8)                                               /*!< UART_T::FIFO: RXOFF Position              */
+#define UART_FIFO_RXOFF_Msk              (0x1ul << UART_FIFO_RXOFF_Pos)                    /*!< UART_T::FIFO: RXOFF Mask                  */
+
+#define UART_FIFO_RTSTRGLV_Pos           (16)                                              /*!< UART_T::FIFO: RTSTRGLV Position           */
+#define UART_FIFO_RTSTRGLV_Msk           (0xful << UART_FIFO_RTSTRGLV_Pos)                 /*!< UART_T::FIFO: RTSTRGLV Mask               */
+
+#define UART_LINE_WLS_Pos                (0)                                               /*!< UART_T::LINE: WLS Position                */
+#define UART_LINE_WLS_Msk                (0x3ul << UART_LINE_WLS_Pos)                      /*!< UART_T::LINE: WLS Mask                    */
+
+#define UART_LINE_NSB_Pos                (2)                                               /*!< UART_T::LINE: NSB Position                */
+#define UART_LINE_NSB_Msk                (0x1ul << UART_LINE_NSB_Pos)                      /*!< UART_T::LINE: NSB Mask                    */
+
+#define UART_LINE_PBE_Pos                (3)                                               /*!< UART_T::LINE: PBE Position                */
+#define UART_LINE_PBE_Msk                (0x1ul << UART_LINE_PBE_Pos)                      /*!< UART_T::LINE: PBE Mask                    */
+
+#define UART_LINE_EPE_Pos                (4)                                               /*!< UART_T::LINE: EPE Position                */
+#define UART_LINE_EPE_Msk                (0x1ul << UART_LINE_EPE_Pos)                      /*!< UART_T::LINE: EPE Mask                    */
+
+#define UART_LINE_SPE_Pos                (5)                                               /*!< UART_T::LINE: SPE Position                */
+#define UART_LINE_SPE_Msk                (0x1ul << UART_LINE_SPE_Pos)                      /*!< UART_T::LINE: SPE Mask                    */
+
+#define UART_LINE_BCB_Pos                (6)                                               /*!< UART_T::LINE: BCB Position                */
+#define UART_LINE_BCB_Msk                (0x1ul << UART_LINE_BCB_Pos)                      /*!< UART_T::LINE: BCB Mask                    */
+
+#define UART_MODEM_RTS_Pos               (1)                                               /*!< UART_T::MODEM: RTS Position               */
+#define UART_MODEM_RTS_Msk               (0x1ul << UART_MODEM_RTS_Pos)                     /*!< UART_T::MODEM: RTS Mask                   */
+
+#define UART_MODEM_RTSACTLV_Pos          (9)                                               /*!< UART_T::MODEM: RTSACTLV Position          */
+#define UART_MODEM_RTSACTLV_Msk          (0x1ul << UART_MODEM_RTSACTLV_Pos)                /*!< UART_T::MODEM: RTSACTLV Mask              */
+
+#define UART_MODEM_RTSSTS_Pos            (13)                                              /*!< UART_T::MODEM: RTSSTS Position            */
+#define UART_MODEM_RTSSTS_Msk            (0x1ul << UART_MODEM_RTSSTS_Pos)                  /*!< UART_T::MODEM: RTSSTS Mask                */
+
+#define UART_MODEMSTS_CTSDETF_Pos        (0)                                               /*!< UART_T::MODEMSTS: CTSDETF Position        */
+#define UART_MODEMSTS_CTSDETF_Msk        (0x1ul << UART_MODEMSTS_CTSDETF_Pos)              /*!< UART_T::MODEMSTS: CTSDETF Mask            */
+
+#define UART_MODEMSTS_CTSSTS_Pos         (4)                                               /*!< UART_T::MODEMSTS: CTSSTS Position         */
+#define UART_MODEMSTS_CTSSTS_Msk         (0x1ul << UART_MODEMSTS_CTSSTS_Pos)               /*!< UART_T::MODEMSTS: CTSSTS Mask             */
+
+#define UART_MODEMSTS_CTSACTLV_Pos       (8)                                               /*!< UART_T::MODEMSTS: CTSACTLV Position       */
+#define UART_MODEMSTS_CTSACTLV_Msk       (0x1ul << UART_MODEMSTS_CTSACTLV_Pos)             /*!< UART_T::MODEMSTS: CTSACTLV Mask           */
+
+#define UART_FIFOSTS_RXOVIF_Pos          (0)                                               /*!< UART_T::FIFOSTS: RXOVIF Position          */
+#define UART_FIFOSTS_RXOVIF_Msk          (0x1ul << UART_FIFOSTS_RXOVIF_Pos)                /*!< UART_T::FIFOSTS: RXOVIF Mask              */
+
+#define UART_FIFOSTS_ABRDIF_Pos          (1)                                               /*!< UART_T::FIFOSTS: ABRDIF Position          */
+#define UART_FIFOSTS_ABRDIF_Msk          (0x1ul << UART_FIFOSTS_ABRDIF_Pos)                /*!< UART_T::FIFOSTS: ABRDIF Mask              */
+
+#define UART_FIFOSTS_ABRDTOIF_Pos        (2)                                               /*!< UART_T::FIFOSTS: ABRDTOIF Position        */
+#define UART_FIFOSTS_ABRDTOIF_Msk        (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos)              /*!< UART_T::FIFOSTS: ABRDTOIF Mask            */
+
+#define UART_FIFOSTS_ADDRDETF_Pos        (3)                                               /*!< UART_T::FIFOSTS: ADDRDETF Position        */
+#define UART_FIFOSTS_ADDRDETF_Msk        (0x1ul << UART_FIFOSTS_ADDRDETF_Pos)              /*!< UART_T::FIFOSTS: ADDRDETF Mask            */
+
+#define UART_FIFOSTS_PEF_Pos             (4)                                               /*!< UART_T::FIFOSTS: PEF Position             */
+#define UART_FIFOSTS_PEF_Msk             (0x1ul << UART_FIFOSTS_PEF_Pos)                   /*!< UART_T::FIFOSTS: PEF Mask                 */
+
+#define UART_FIFOSTS_FEF_Pos             (5)                                               /*!< UART_T::FIFOSTS: FEF Position             */
+#define UART_FIFOSTS_FEF_Msk             (0x1ul << UART_FIFOSTS_FEF_Pos)                   /*!< UART_T::FIFOSTS: FEF Mask                 */
+
+#define UART_FIFOSTS_BIF_Pos             (6)                                               /*!< UART_T::FIFOSTS: BIF Position             */
+#define UART_FIFOSTS_BIF_Msk             (0x1ul << UART_FIFOSTS_BIF_Pos)                   /*!< UART_T::FIFOSTS: BIF Mask                 */
+
+#define UART_FIFOSTS_RXPTR_Pos           (8)                                               /*!< UART_T::FIFOSTS: RXPTR Position           */
+#define UART_FIFOSTS_RXPTR_Msk           (0x3ful << UART_FIFOSTS_RXPTR_Pos)                /*!< UART_T::FIFOSTS: RXPTR Mask               */
+
+#define UART_FIFOSTS_RXEMPTY_Pos         (14)                                              /*!< UART_T::FIFOSTS: RXEMPTY Position         */
+#define UART_FIFOSTS_RXEMPTY_Msk         (0x1ul << UART_FIFOSTS_RXEMPTY_Pos)               /*!< UART_T::FIFOSTS: RXEMPTY Mask             */
+
+#define UART_FIFOSTS_RXFULL_Pos          (15)                                              /*!< UART_T::FIFOSTS: RXFULL Position          */
+#define UART_FIFOSTS_RXFULL_Msk          (0x1ul << UART_FIFOSTS_RXFULL_Pos)                /*!< UART_T::FIFOSTS: RXFULL Mask              */
+
+#define UART_FIFOSTS_TXPTR_Pos           (16)                                              /*!< UART_T::FIFOSTS: TXPTR Position           */
+#define UART_FIFOSTS_TXPTR_Msk           (0x3ful << UART_FIFOSTS_TXPTR_Pos)                /*!< UART_T::FIFOSTS: TXPTR Mask               */
+
+#define UART_FIFOSTS_TXEMPTY_Pos         (22)                                              /*!< UART_T::FIFOSTS: TXEMPTY Position         */
+#define UART_FIFOSTS_TXEMPTY_Msk         (0x1ul << UART_FIFOSTS_TXEMPTY_Pos)               /*!< UART_T::FIFOSTS: TXEMPTY Mask             */
+
+#define UART_FIFOSTS_TXFULL_Pos          (23)                                              /*!< UART_T::FIFOSTS: TXFULL Position          */
+#define UART_FIFOSTS_TXFULL_Msk          (0x1ul << UART_FIFOSTS_TXFULL_Pos)                /*!< UART_T::FIFOSTS: TXFULL Mask              */
+
+#define UART_FIFOSTS_TXOVIF_Pos          (24)                                              /*!< UART_T::FIFOSTS: TXOVIF Position          */
+#define UART_FIFOSTS_TXOVIF_Msk          (0x1ul << UART_FIFOSTS_TXOVIF_Pos)                /*!< UART_T::FIFOSTS: TXOVIF Mask              */
+
+#define UART_FIFOSTS_TXEMPTYF_Pos        (28)                                              /*!< UART_T::FIFOSTS: TXEMPTYF Position        */
+#define UART_FIFOSTS_TXEMPTYF_Msk        (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos)              /*!< UART_T::FIFOSTS: TXEMPTYF Mask            */
+
+#define UART_INTSTS_RDAIF_Pos            (0)                                               /*!< UART_T::INTSTS: RDAIF Position            */
+#define UART_INTSTS_RDAIF_Msk            (0x1ul << UART_INTSTS_RDAIF_Pos)                  /*!< UART_T::INTSTS: RDAIF Mask                */
+
+#define UART_INTSTS_THREIF_Pos           (1)                                               /*!< UART_T::INTSTS: THREIF Position           */
+#define UART_INTSTS_THREIF_Msk           (0x1ul << UART_INTSTS_THREIF_Pos)                 /*!< UART_T::INTSTS: THREIF Mask               */
+
+#define UART_INTSTS_RLSIF_Pos            (2)                                               /*!< UART_T::INTSTS: RLSIF Position            */
+#define UART_INTSTS_RLSIF_Msk            (0x1ul << UART_INTSTS_RLSIF_Pos)                  /*!< UART_T::INTSTS: RLSIF Mask                */
+
+#define UART_INTSTS_MODEMIF_Pos          (3)                                               /*!< UART_T::INTSTS: MODEMIF Position          */
+#define UART_INTSTS_MODEMIF_Msk          (0x1ul << UART_INTSTS_MODEMIF_Pos)                /*!< UART_T::INTSTS: MODEMIF Mask              */
+
+#define UART_INTSTS_RXTOIF_Pos           (4)                                               /*!< UART_T::INTSTS: RXTOIF Position           */
+#define UART_INTSTS_RXTOIF_Msk           (0x1ul << UART_INTSTS_RXTOIF_Pos)                 /*!< UART_T::INTSTS: RXTOIF Mask               */
+
+#define UART_INTSTS_BUFERRIF_Pos         (5)                                               /*!< UART_T::INTSTS: BUFERRIF Position         */
+#define UART_INTSTS_BUFERRIF_Msk         (0x1ul << UART_INTSTS_BUFERRIF_Pos)               /*!< UART_T::INTSTS: BUFERRIF Mask             */
+
+#define UART_INTSTS_WKIF_Pos             (6)                                               /*!< UART_T::INTSTS: WKIF Position             */
+#define UART_INTSTS_WKIF_Msk             (0x1ul << UART_INTSTS_WKIF_Pos)                   /*!< UART_T::INTSTS: WKIF Mask                 */
+
+#define UART_INTSTS_LINIF_Pos            (7)                                               /*!< UART_T::INTSTS: LINIF Position            */
+#define UART_INTSTS_LINIF_Msk            (0x1ul << UART_INTSTS_LINIF_Pos)                  /*!< UART_T::INTSTS: LINIF Mask                */
+
+#define UART_INTSTS_RDAINT_Pos           (8)                                               /*!< UART_T::INTSTS: RDAINT Position           */
+#define UART_INTSTS_RDAINT_Msk           (0x1ul << UART_INTSTS_RDAINT_Pos)                 /*!< UART_T::INTSTS: RDAINT Mask               */
+
+#define UART_INTSTS_THREINT_Pos          (9)                                               /*!< UART_T::INTSTS: THREINT Position          */
+#define UART_INTSTS_THREINT_Msk          (0x1ul << UART_INTSTS_THREINT_Pos)                /*!< UART_T::INTSTS: THREINT Mask              */
+
+#define UART_INTSTS_RLSINT_Pos           (10)                                              /*!< UART_T::INTSTS: RLSINT Position           */
+#define UART_INTSTS_RLSINT_Msk           (0x1ul << UART_INTSTS_RLSINT_Pos)                 /*!< UART_T::INTSTS: RLSINT Mask               */
+
+#define UART_INTSTS_MODEMINT_Pos         (11)                                              /*!< UART_T::INTSTS: MODEMINT Position         */
+#define UART_INTSTS_MODEMINT_Msk         (0x1ul << UART_INTSTS_MODEMINT_Pos)               /*!< UART_T::INTSTS: MODEMINT Mask             */
+
+#define UART_INTSTS_RXTOINT_Pos          (12)                                              /*!< UART_T::INTSTS: RXTOINT Position          */
+#define UART_INTSTS_RXTOINT_Msk          (0x1ul << UART_INTSTS_RXTOINT_Pos)                /*!< UART_T::INTSTS: RXTOINT Mask              */
+
+#define UART_INTSTS_BUFERRINT_Pos        (13)                                              /*!< UART_T::INTSTS: BUFERRINT Position        */
+#define UART_INTSTS_BUFERRINT_Msk        (0x1ul << UART_INTSTS_BUFERRINT_Pos)              /*!< UART_T::INTSTS: BUFERRINT Mask            */
+
+#define UART_INTSTS_LININT_Pos           (15)                                              /*!< UART_T::INTSTS: LININT Position           */
+#define UART_INTSTS_LININT_Msk           (0x1ul << UART_INTSTS_LININT_Pos)                 /*!< UART_T::INTSTS: LININT Mask               */
+
+#define UART_INTSTS_CTSWKIF_Pos          (16)                                              /*!< UART_T::INTSTS: CTSWKIF Position          */
+#define UART_INTSTS_CTSWKIF_Msk          (0x1ul << UART_INTSTS_CTSWKIF_Pos)                /*!< UART_T::INTSTS: CTSWKIF Mask              */
+
+#define UART_INTSTS_DATWKIF_Pos          (17)                                              /*!< UART_T::INTSTS: DATWKIF Position          */
+#define UART_INTSTS_DATWKIF_Msk          (0x1ul << UART_INTSTS_DATWKIF_Pos)                /*!< UART_T::INTSTS: DATWKIF Mask              */
+
+#define UART_INTSTS_HWRLSIF_Pos          (18)                                              /*!< UART_T::INTSTS: HWRLSIF Position          */
+#define UART_INTSTS_HWRLSIF_Msk          (0x1ul << UART_INTSTS_HWRLSIF_Pos)                /*!< UART_T::INTSTS: HWRLSIF Mask              */
+
+#define UART_INTSTS_HWMODIF_Pos          (19)                                              /*!< UART_T::INTSTS: HWMODIF Position          */
+#define UART_INTSTS_HWMODIF_Msk          (0x1ul << UART_INTSTS_HWMODIF_Pos)                /*!< UART_T::INTSTS: HWMODIF Mask              */
+
+#define UART_INTSTS_HWTOIF_Pos           (20)                                              /*!< UART_T::INTSTS: HWTOIF Position           */
+#define UART_INTSTS_HWTOIF_Msk           (0x1ul << UART_INTSTS_HWTOIF_Pos)                 /*!< UART_T::INTSTS: HWTOIF Mask               */
+
+#define UART_INTSTS_HWBUFEIF_Pos         (21)                                              /*!< UART_T::INTSTS: HWBUFEIF Position         */
+#define UART_INTSTS_HWBUFEIF_Msk         (0x1ul << UART_INTSTS_HWBUFEIF_Pos)               /*!< UART_T::INTSTS: HWBUFEIF Mask             */
+
+#define UART_INTSTS_HWRLSINT_Pos         (26)                                              /*!< UART_T::INTSTS: HWRLSINT Position         */
+#define UART_INTSTS_HWRLSINT_Msk         (0x1ul << UART_INTSTS_HWRLSINT_Pos)               /*!< UART_T::INTSTS: HWRLSINT Mask             */
+
+#define UART_INTSTS_HWMODINT_Pos         (27)                                              /*!< UART_T::INTSTS: HWMODINT Position         */
+#define UART_INTSTS_HWMODINT_Msk         (0x1ul << UART_INTSTS_HWMODINT_Pos)               /*!< UART_T::INTSTS: HWMODINT Mask             */
+
+#define UART_INTSTS_HWTOINT_Pos          (28)                                              /*!< UART_T::INTSTS: HWTOINT Position          */
+#define UART_INTSTS_HWTOINT_Msk          (0x1ul << UART_INTSTS_HWTOINT_Pos)                /*!< UART_T::INTSTS: HWTOINT Mask              */
+
+#define UART_INTSTS_HWBUFEINT_Pos        (29)                                              /*!< UART_T::INTSTS: HWBUFEINT Position        */
+#define UART_INTSTS_HWBUFEINT_Msk        (0x1ul << UART_INTSTS_HWBUFEINT_Pos)              /*!< UART_T::INTSTS: HWBUFEINT Mask            */
+
+#define UART_TOUT_TOIC_Pos               (0)                                               /*!< UART_T::TOUT: TOIC Position               */
+#define UART_TOUT_TOIC_Msk               (0xfful << UART_TOUT_TOIC_Pos)                    /*!< UART_T::TOUT: TOIC Mask                   */
+
+#define UART_TOUT_DLY_Pos                (8)                                               /*!< UART_T::TOUT: DLY Position                */
+#define UART_TOUT_DLY_Msk                (0xfful << UART_TOUT_DLY_Pos)                     /*!< UART_T::TOUT: DLY Mask                    */
+
+#define UART_BAUD_BRD_Pos                (0)                                               /*!< UART_T::BAUD: BRD Position                */
+#define UART_BAUD_BRD_Msk                (0xfffful << UART_BAUD_BRD_Pos)                   /*!< UART_T::BAUD: BRD Mask                    */
+
+#define UART_BAUD_EDIVM1_Pos             (24)                                              /*!< UART_T::BAUD: EDIVM1 Position             */
+#define UART_BAUD_EDIVM1_Msk             (0xful << UART_BAUD_EDIVM1_Pos)                   /*!< UART_T::BAUD: EDIVM1 Mask                 */
+
+#define UART_BAUD_BAUDM0_Pos             (28)                                              /*!< UART_T::BAUD: BAUDM0 Position             */
+#define UART_BAUD_BAUDM0_Msk             (0x1ul << UART_BAUD_BAUDM0_Pos)                   /*!< UART_T::BAUD: BAUDM0 Mask                 */
+
+#define UART_BAUD_BAUDM1_Pos             (29)                                              /*!< UART_T::BAUD: BAUDM1 Position             */
+#define UART_BAUD_BAUDM1_Msk             (0x1ul << UART_BAUD_BAUDM1_Pos)                   /*!< UART_T::BAUD: BAUDM1 Mask                 */
+
+#define UART_IRDA_TXEN_Pos               (1)                                               /*!< UART_T::IRDA: TXEN Position               */
+#define UART_IRDA_TXEN_Msk               (0x1ul << UART_IRDA_TXEN_Pos)                     /*!< UART_T::IRDA: TXEN Mask                   */
+
+#define UART_IRDA_TXINV_Pos              (5)                                               /*!< UART_T::IRDA: TXINV Position              */
+#define UART_IRDA_TXINV_Msk              (0x1ul << UART_IRDA_TXINV_Pos)                    /*!< UART_T::IRDA: TXINV Mask                  */
+
+#define UART_IRDA_RXINV_Pos              (6)                                               /*!< UART_T::IRDA: RXINV Position              */
+#define UART_IRDA_RXINV_Msk              (0x1ul << UART_IRDA_RXINV_Pos)                    /*!< UART_T::IRDA: RXINV Mask                  */
+
+#define UART_ALTCTL_BRKFL_Pos            (0)                                               /*!< UART_T::ALTCTL: BRKFL Position            */
+#define UART_ALTCTL_BRKFL_Msk            (0xful << UART_ALTCTL_BRKFL_Pos)                  /*!< UART_T::ALTCTL: BRKFL Mask                */
+
+#define UART_ALTCTL_LINRXEN_Pos          (6)                                               /*!< UART_T::ALTCTL: LINRXEN Position          */
+#define UART_ALTCTL_LINRXEN_Msk          (0x1ul << UART_ALTCTL_LINRXEN_Pos)                /*!< UART_T::ALTCTL: LINRXEN Mask              */
+
+#define UART_ALTCTL_LINTXEN_Pos          (7)                                               /*!< UART_T::ALTCTL: LINTXEN Position          */
+#define UART_ALTCTL_LINTXEN_Msk          (0x1ul << UART_ALTCTL_LINTXEN_Pos)                /*!< UART_T::ALTCTL: LINTXEN Mask              */
+
+#define UART_ALTCTL_RS485NMM_Pos         (8)                                               /*!< UART_T::ALTCTL: RS485NMM Position         */
+#define UART_ALTCTL_RS485NMM_Msk         (0x1ul << UART_ALTCTL_RS485NMM_Pos)               /*!< UART_T::ALTCTL: RS485NMM Mask             */
+
+#define UART_ALTCTL_RS485AAD_Pos         (9)                                               /*!< UART_T::ALTCTL: RS485AAD Position         */
+#define UART_ALTCTL_RS485AAD_Msk         (0x1ul << UART_ALTCTL_RS485AAD_Pos)               /*!< UART_T::ALTCTL: RS485AAD Mask             */
+
+#define UART_ALTCTL_RS485AUD_Pos         (10)                                              /*!< UART_T::ALTCTL: RS485AUD Position         */
+#define UART_ALTCTL_RS485AUD_Msk         (0x1ul << UART_ALTCTL_RS485AUD_Pos)               /*!< UART_T::ALTCTL: RS485AUD Mask             */
+
+#define UART_ALTCTL_ADDRDEN_Pos          (15)                                              /*!< UART_T::ALTCTL: ADDRDEN Position          */
+#define UART_ALTCTL_ADDRDEN_Msk          (0x1ul << UART_ALTCTL_ADDRDEN_Pos)                /*!< UART_T::ALTCTL: ADDRDEN Mask              */
+
+#define UART_ALTCTL_ABRIF_Pos            (17)                                              /*!< UART_T::ALTCTL: ABRIF Position            */
+#define UART_ALTCTL_ABRIF_Msk            (0x1ul << UART_ALTCTL_ABRIF_Pos)                  /*!< UART_T::ALTCTL: ABRIF Mask                */
+
+#define UART_ALTCTL_ABRDEN_Pos           (18)                                              /*!< UART_T::ALTCTL: ABRDEN Position           */
+#define UART_ALTCTL_ABRDEN_Msk           (0x1ul << UART_ALTCTL_ABRDEN_Pos)                 /*!< UART_T::ALTCTL: ABRDEN Mask               */
+
+#define UART_ALTCTL_ABRDBITS_Pos         (19)                                              /*!< UART_T::ALTCTL: ABRDBITS Position         */
+#define UART_ALTCTL_ABRDBITS_Msk         (0x3ul << UART_ALTCTL_ABRDBITS_Pos)               /*!< UART_T::ALTCTL: ABRDBITS Mask             */
+
+#define UART_ALTCTL_ADDRMV_Pos           (24)                                              /*!< UART_T::ALTCTL: ADDRMV Position           */
+#define UART_ALTCTL_ADDRMV_Msk           (0xfful << UART_ALTCTL_ADDRMV_Pos)                /*!< UART_T::ALTCTL: ADDRMV Mask               */
+
+#define UART_FUNCSEL_FUNCSEL_Pos         (0)                                               /*!< UART_T::FUNCSEL: FUNCSEL Position         */
+#define UART_FUNCSEL_FUNCSEL_Msk         (0x3ul << UART_FUNCSEL_FUNCSEL_Pos)               /*!< UART_T::FUNCSEL: FUNCSEL Mask             */
+
+#define UART_LINCTL_SLVEN_Pos            (0)                                               /*!< UART_T::LINCTL: SLVEN Position            */
+#define UART_LINCTL_SLVEN_Msk            (0x1ul << UART_LINCTL_SLVEN_Pos)                  /*!< UART_T::LINCTL: SLVEN Mask                */
+
+#define UART_LINCTL_SLVHDEN_Pos          (1)                                               /*!< UART_T::LINCTL: SLVHDEN Position          */
+#define UART_LINCTL_SLVHDEN_Msk          (0x1ul << UART_LINCTL_SLVHDEN_Pos)                /*!< UART_T::LINCTL: SLVHDEN Mask              */
+
+#define UART_LINCTL_SLVAREN_Pos          (2)                                               /*!< UART_T::LINCTL: SLVAREN Position          */
+#define UART_LINCTL_SLVAREN_Msk          (0x1ul << UART_LINCTL_SLVAREN_Pos)                /*!< UART_T::LINCTL: SLVAREN Mask              */
+
+#define UART_LINCTL_SLVDUEN_Pos          (3)                                               /*!< UART_T::LINCTL: SLVDUEN Position          */
+#define UART_LINCTL_SLVDUEN_Msk          (0x1ul << UART_LINCTL_SLVDUEN_Pos)                /*!< UART_T::LINCTL: SLVDUEN Mask              */
+
+#define UART_LINCTL_MUTE_Pos             (4)                                               /*!< UART_T::LINCTL: MUTE Position             */
+#define UART_LINCTL_MUTE_Msk             (0x1ul << UART_LINCTL_MUTE_Pos)                   /*!< UART_T::LINCTL: MUTE Mask                 */
+
+#define UART_LINCTL_SENDH_Pos            (8)                                               /*!< UART_T::LINCTL: SENDH Position            */
+#define UART_LINCTL_SENDH_Msk            (0x1ul << UART_LINCTL_SENDH_Pos)                  /*!< UART_T::LINCTL: SENDH Mask                */
+
+#define UART_LINCTL_IDPEN_Pos            (9)                                               /*!< UART_T::LINCTL: IDPEN Position            */
+#define UART_LINCTL_IDPEN_Msk            (0x1ul << UART_LINCTL_IDPEN_Pos)                  /*!< UART_T::LINCTL: IDPEN Mask                */
+
+#define UART_LINCTL_BRKDETEN_Pos         (10)                                              /*!< UART_T::LINCTL: BRKDETEN Position         */
+#define UART_LINCTL_BRKDETEN_Msk         (0x1ul << UART_LINCTL_BRKDETEN_Pos)               /*!< UART_T::LINCTL: BRKDETEN Mask             */
+
+#define UART_LINCTL_RXOFF_Pos            (11)                                              /*!< UART_T::LINCTL: RXOFF Position            */
+#define UART_LINCTL_RXOFF_Msk            (0x1ul << UART_LINCTL_RXOFF_Pos)                  /*!< UART_T::LINCTL: RXOFF Mask                */
+
+#define UART_LINCTL_BITERREN_Pos         (12)                                              /*!< UART_T::LINCTL: BITERREN Position         */
+#define UART_LINCTL_BITERREN_Msk         (0x1ul << UART_LINCTL_BITERREN_Pos)               /*!< UART_T::LINCTL: BITERREN Mask             */
+
+#define UART_LINCTL_BRKFL_Pos            (16)                                              /*!< UART_T::LINCTL: BRKFL Position            */
+#define UART_LINCTL_BRKFL_Msk            (0xful << UART_LINCTL_BRKFL_Pos)                  /*!< UART_T::LINCTL: BRKFL Mask                */
+
+#define UART_LINCTL_BSL_Pos              (20)                                              /*!< UART_T::LINCTL: BSL Position              */
+#define UART_LINCTL_BSL_Msk              (0x3ul << UART_LINCTL_BSL_Pos)                    /*!< UART_T::LINCTL: BSL Mask                  */
+
+#define UART_LINCTL_HSEL_Pos             (22)                                              /*!< UART_T::LINCTL: HSEL Position             */
+#define UART_LINCTL_HSEL_Msk             (0x3ul << UART_LINCTL_HSEL_Pos)                   /*!< UART_T::LINCTL: HSEL Mask                 */
+
+#define UART_LINCTL_PID_Pos              (24)                                              /*!< UART_T::LINCTL: PID Position              */
+#define UART_LINCTL_PID_Msk              (0xfful << UART_LINCTL_PID_Pos)                   /*!< UART_T::LINCTL: PID Mask                  */
+
+#define UART_LINSTS_SLVHDETF_Pos         (0)                                               /*!< UART_T::LINSTS: SLVHDETF Position         */
+#define UART_LINSTS_SLVHDETF_Msk         (0x1ul << UART_LINSTS_SLVHDETF_Pos)               /*!< UART_T::LINSTS: SLVHDETF Mask             */
+
+#define UART_LINSTS_SLVHEF_Pos           (1)                                               /*!< UART_T::LINSTS: SLVHEF Position           */
+#define UART_LINSTS_SLVHEF_Msk           (0x1ul << UART_LINSTS_SLVHEF_Pos)                 /*!< UART_T::LINSTS: SLVHEF Mask               */
+
+#define UART_LINSTS_SLVIDPEF_Pos         (2)                                               /*!< UART_T::LINSTS: SLVIDPEF Position         */
+#define UART_LINSTS_SLVIDPEF_Msk         (0x1ul << UART_LINSTS_SLVIDPEF_Pos)               /*!< UART_T::LINSTS: SLVIDPEF Mask             */
+
+#define UART_LINSTS_SLVSYNCF_Pos         (3)                                               /*!< UART_T::LINSTS: SLVSYNCF Position         */
+#define UART_LINSTS_SLVSYNCF_Msk         (0x1ul << UART_LINSTS_SLVSYNCF_Pos)               /*!< UART_T::LINSTS: SLVSYNCF Mask             */
+
+#define UART_LINSTS_BRKDETF_Pos          (8)                                               /*!< UART_T::LINSTS: BRKDETF Position          */
+#define UART_LINSTS_BRKDETF_Msk          (0x1ul << UART_LINSTS_BRKDETF_Pos)                /*!< UART_T::LINSTS: BRKDETF Mask              */
+
+#define UART_LINSTS_BITEF_Pos            (9)                                               /*!< UART_T::LINSTS: BITEF Position            */
+#define UART_LINSTS_BITEF_Msk            (0x1ul << UART_LINSTS_BITEF_Pos)                  /*!< UART_T::LINSTS: BITEF Mask                */
+
+
+/**@}*/ /* UART_CONST */
+/**@}*/ /* end of UART register group */
+
+
+/*---------------------- Universal Serial Bus Controller -------------------------*/
+/**
+    @addtogroup USB Universal Serial Bus Controller(USB)
+    Memory Mapped Structure for USB Controller
+@{ */
+
+/**
+  * @brief USBD endpoints register
+  */
+
+typedef struct
+{
+
+
+/**
+ * @var USBD_EP_T::BUFSEG
+ * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570  Endpoint 0~7 Buffer Segmentation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[8:3]   |BUFSEG    |Endpoint Buffer Segmentation
+ * |        |          |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
+ * |        |          |USB_SRAM address + { BUFSEG[8:3], 3'b000}
+ * |        |          |Where the USB_SRAM address = USBD_BA+0x100h.
+ * |        |          |Refer to the section 5.4.4.7 for the endpoint SRAM structure and its description.
+ * @var USBD_EP_T::MXPLD
+ * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574  Endpoint 0~7 Maximal Payload Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[8:0]   |MXPLD     |Maximal Payload
+ * |        |          |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token).
+ * |        |          |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
+ * |        |          |(1) When the register is written by CPU,
+ * |        |          |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
+ * |        |          |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
+ * |        |          |(2) When the register is read by CPU,
+ * |        |          |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
+ * |        |          |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
+ * |        |          |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
+ * @var USBD_EP_T::CFG
+ * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578  Endpoint 0~7 Configuration Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[3:0]   |EPNUM     |Endpoint Number
+ * |        |          |These bits are used to define the endpoint number of the current endpoint.
+ * |[4]     |ISOCH     |Isochronous Endpoint
+ * |        |          |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
+ * |        |          |0 = No Isochronous endpoint.
+ * |        |          |1 = Isochronous endpoint.
+ * |[6:5]   |STATE     |Endpoint STATE
+ * |        |          |00 = Endpoint is Disabled.
+ * |        |          |01 = Out endpoint.
+ * |        |          |10 = IN endpoint.
+ * |        |          |11 = Undefined.
+ * |[7]     |DSQSYNC   |Data Sequence Synchronization
+ * |        |          |0 = DATA0 PID.
+ * |        |          |1 = DATA1 PID.
+ * |        |          |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction.
+ * |        |          |Hardware will toggle automatically in IN token base on the bit.
+ * |[9]     |CSTALL    |Clear STALL Response
+ * |        |          |0 = Disable the device to clear the STALL handshake in setup stage.
+ * |        |          |1 = Clear the device to response STALL handshake in setup stage.
+ * @var USBD_EP_T::CFGP
+ * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C  Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register
+    * ---------------------------------------------------------------------------------------------------
+    * |Bits    |Field     |Descriptions
+    * | :----: | :----:   | :---- |
+    * |[0]     |CLRRDY    |Clear Ready
+    * |        |          |When the USB_MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data.
+    * |        |          |If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it will be cleared to 0 automatically.
+    * |        |          |For IN token, write 1 to clear the IN token had ready to transmit the data to USB.
+    * |        |          |For OUT token, write 1 to clear the OUT token had ready to receive the data from USB.
+    * |        |          |This bit is write 1 only and is always 0 when it is read back.
+    * |[1]     |SSTALL    |Set STALL
+    * |        |          |0 = Disable the device to response STALL.
+    * |        |          |1 = Set the device to respond STALL automatically.
+    */
+
+    __IO uint32_t BUFSEG;        /* Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570  Endpoint 0~7 Buffer Segmentation Register */
+    __IO uint32_t MXPLD;         /* Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574  Endpoint 0~7 Maximal Payload Register */
+    __IO uint32_t CFG;           /* Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578  Endpoint 0~7 Configuration Register */
+    __IO uint32_t CFGP;          /* Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C  Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register */
+
+} USBD_EP_T;
+
+
+
+
+
+typedef struct
+{
+
+
+/**
+ * @var USBD_T::INTEN
+ * Offset: 0x00  USB Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |BUSIEN    |Bus Event Interrupt Enable
+ * |        |          |0 = BUS event interrupt Disabled.
+ * |        |          |1 = BUS event interrupt Enabled.
+ * |[1]     |USBIEN    |USB Event Interrupt Enable
+ * |        |          |0 = USB event interrupt Disabled.
+ * |        |          |1 = USB event interrupt Enabled.
+ * |[2]     |VBDETIEN  |VBUS Detection Interrupt Enable
+ * |        |          |0 = Floating detection Interrupt Disabled.
+ * |        |          |1 = Floating detection Interrupt Enabled.
+ * |[3]     |NEVWKIEN  |USB No-Event-Wake-Up Interrupt Enable
+ * |        |          |0 = No-Event-Wake-up Interrupt Disabled.
+ * |        |          |1 = No-Event-Wake-up Interrupt Enabled.
+ * |[8]     |WKEN      |Wake-Up Function Enable
+ * |        |          |0 = USB wake-up function Disabled.
+ * |        |          |1 = USB wake-up function Enabled.
+ * |[15]    |INNAKEN   |Active NAK Function And Its Status In IN Token
+ * |        |          |0 = When device responds NAK after receiving IN token, IN NAK status will not be
+ * |        |          |    updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted.
+ * |        |          |1 = IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event
+ * |        |          |    will be asserted, when the device responds NAK after receiving IN token.
+ * @var USBD_T::INTSTS
+ * Offset: 0x04  USB Interrupt Event Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |BUSIF     |BUS Interrupt Status
+ * |        |          |The BUS event means that there is one of the suspense or the resume function in the bus.
+ * |        |          |0 = No BUS event occurred.
+ * |        |          |1 = Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0].
+ * |[1]     |USBIF     |USB Event Interrupt Status
+ * |        |          |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
+ * |        |          |0 = No USB event occurred.
+ * |        |          |1 = USB event occurred, check EPSTS0~7 to know which kind of USB event occurred.
+ * |        |          |Cleared by write 1 to USB_INTSTS[1] or EPEVT0~7 and SETUP (USB_INTSTS[31]).
+ * |[2]     |VBDETIF   |VBUS Detection Interrupt Status
+ * |        |          |0 = There is not attached/detached event in the USB.
+ * |        |          |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2].
+ * |[3]     |NEVWKIF   |USB No-Event-Wake-Up Interrupt Status
+ * |        |          |0 = No Wake-up event occurred.
+ * |        |          |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS[3].
+ * |[16]    |EPEVT0    |Endpoint 0's USB Event Status
+ * |        |          |0 = No event occurred on endpoint 0.
+ * |        |          |1 = USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1].
+ * |[17]    |EPEVT1    |Endpoint 1's USB Event Status
+ * |        |          |0 = No event occurred on endpoint 1.
+ * |        |          |1 = USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1].
+ * |[18]    |EPEVT2    |Endpoint 2's USB Event Status
+ * |        |          |0 = No event occurred on endpoint 2.
+ * |        |          |1 = USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1].
+ * |[19]    |EPEVT3    |Endpoint 3's USB Event Status
+ * |        |          |0 = No event occurred on endpoint 3.
+ * |        |          |1 = USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1].
+ * |[20]    |EPEVT4    |Endpoint 4's USB Event Status
+ * |        |          |0 = No event occurred on endpoint 4.
+ * |        |          |1 = USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1].
+ * |[21]    |EPEVT5    |Endpoint 5's USB Event Status
+ * |        |          |0 = No event occurred on endpoint 5.
+ * |        |          |1 = USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1].
+ * |[22]    |EPEVT6    |Endpoint 6's USB Event Status
+ * |        |          |0 = No event occurred on endpoint 6.
+ * |        |          |1 = USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[22] or USB_INTSTS[1].
+ * |[23]    |EPEVT7    |Endpoint 7's USB Event Status
+ * |        |          |0 = No event occurred on endpoint 7.
+ * |        |          |1 = USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[23] or USB_INTSTS[1].
+ * |[31]    |SETUP     |Setup Event Status
+ * |        |          |0 = No Setup event.
+ * |        |          |1 = SETUP event occurred, cleared by write 1 to USB_INTSTS[31].
+ * @var USBD_T::FADDR
+ * Offset: 0x08  USB Device Function Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[6:0]   |FADDR     |USB Device Function Address
+ * @var USBD_T::EPSTS
+ * Offset: 0x0C  USB Endpoint Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7]     |OV        |Overrun
+ * |        |          |It indicates that the received data is over the maximum payload number or not.
+ * |        |          |0 = No overrun.
+ * |        |          |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
+ * |[10:8]  |EPSTS0    |Endpoint 0 Bus Status
+ * |        |          |These bits are used to indicate the current status of this endpoint
+ * |        |          |000 = In ACK.
+ * |        |          |001 = In NAK.
+ * |        |          |010 = Out Packet Data0 ACK.
+ * |        |          |110 = Out Packet Data1 ACK.
+ * |        |          |011 = Setup ACK.
+ * |        |          |111 = Isochronous transfer end.
+ * |[13:11] |EPSTS1    |Endpoint 1 Bus Status
+ * |        |          |These bits are used to indicate the current status of this endpoint
+ * |        |          |000 = In ACK.
+ * |        |          |001 = In NAK.
+ * |        |          |010 = Out Packet Data0 ACK.
+ * |        |          |110 = Out Packet Data1 ACK.
+ * |        |          |011 = Setup ACK.
+ * |        |          |111 = Isochronous transfer end.
+ * |[16:14] |EPSTS2    |Endpoint 2 Bus Status
+ * |        |          |These bits are used to indicate the current status of this endpoint
+ * |        |          |000 = In ACK.
+ * |        |          |001 = In NAK.
+ * |        |          |010 = Out Packet Data0 ACK.
+ * |        |          |110 = Out Packet Data1 ACK.
+ * |        |          |011 = Setup ACK.
+ * |        |          |111 = Isochronous transfer end.
+ * |[19:17] |EPSTS3    |Endpoint 3 Bus Status
+ * |        |          |These bits are used to indicate the current status of this endpoint
+ * |        |          |000 = In ACK.
+ * |        |          |001 = In NAK.
+ * |        |          |010 = Out Packet Data0 ACK.
+ * |        |          |110 = Out Packet Data1 ACK.
+ * |        |          |011 = Setup ACK.
+ * |        |          |111 = Isochronous transfer end.
+ * |[22:20] |EPSTS4    |Endpoint 4 Bus Status
+ * |        |          |These bits are used to indicate the current status of this endpoint
+ * |        |          |000 = In ACK.
+ * |        |          |001 = In NAK.
+ * |        |          |010 = Out Packet Data0 ACK.
+ * |        |          |110 = Out Packet Data1 ACK.
+ * |        |          |011 = Setup ACK.
+ * |        |          |111 = Isochronous transfer end.
+ * |[25:23] |EPSTS5    |Endpoint 5 Bus Status
+ * |        |          |These bits are used to indicate the current status of this endpoint
+ * |        |          |000 = In ACK.
+ * |        |          |001 = In NAK.
+ * |        |          |010 = Out Packet Data0 ACK.
+ * |        |          |110 = Out Packet Data1 ACK.
+ * |        |          |011 = Setup ACK.
+ * |        |          |111 = Isochronous transfer end.
+ * |[28:26] |EPSTS6    |Endpoint 6 Bus Status
+ * |        |          |These bits are used to indicate the current status of this endpoint
+ * |        |          |000 = In ACK.
+ * |        |          |001 = In NAK.
+ * |        |          |010 = Out Packet Data0 ACK.
+ * |        |          |110 = Out Packet Data1 ACK.
+ * |        |          |011 = Setup ACK.
+ * |        |          |111 = Isochronous transfer end.
+ * |[31:29] |EPSTS7    |Endpoint 7 Bus Status
+ * |        |          |These bits are used to indicate the current status of this endpoint
+ * |        |          |000 = In ACK.
+ * |        |          |001 = In NAK.
+ * |        |          |010 = Out Packet Data0 ACK.
+ * |        |          |110 = Out Packet Data1 ACK.
+ * |        |          |011 = Setup ACK.
+ * |        |          |111 = Isochronous transfer end.
+ * @var USBD_T::ATTR
+ * Offset: 0x10  USB Bus Status and Attribution Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |USBRST    |USB Reset Status
+ * |        |          |0 = Bus no reset.
+ * |        |          |1 = Bus reset when SE0 (single-ended 0) is presented more than 2.5us.
+ * |        |          |Note: This bit is read only.
+ * |[1]     |SUSPEND   |Suspend Status
+ * |        |          |0 = Bus no suspend.
+ * |        |          |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
+ * |        |          |Note: This bit is read only.
+ * |[2]     |RESUME    |Resume Status
+ * |        |          |0 = No bus resume.
+ * |        |          |1 = Resume from suspend.
+ * |        |          |Note: This bit is read only.
+ * |[3]     |TOUT      |Time-Out Status
+ * |        |          |0 = No time-out.
+ * |        |          |1 = No Bus response more than 18 bits time.
+ * |        |          |Note: This bit is read only.
+ * |[4]     |PHYEN     |PHY Transceiver Function Enable
+ * |        |          |0 = PHY transceiver function Disabled.
+ * |        |          |1 = PHY transceiver function Enabled.
+ * |[5]     |RWAKEUP   |Remote Wake-Up
+ * |        |          |0 = Release the USB bus from K state.
+ * |        |          |1 = Force USB bus to K (USB_D+ low, USB_D- high) state, used for remote wake-up.
+ * |[7]     |USBEN     |USB Controller Enable
+ * |        |          |0 = USB Controller Disabled.
+ * |        |          |1 = USB Controller Enabled.
+ * |[8]     |DPPUEN    |Pull-Up Resistor On USB_D+ Enable
+ * |        |          |0 = Pull-up resistor in USB_D+ pin Disabled.
+ * |        |          |1 = Pull-up resistor in USB_D+ pin Enabled.
+ * |[9]     |PWRDN     |Power Down PHY Transceiver, Low Active (M45xD/M45xC Only)
+ * |        |          |0 = Power down related circuits of PHY transceiver.
+ * |        |          |1 = Turn on related circuits of  PHY transceiver.
+ * |[10]    |BYTEM     |CPU Access USB SRAM Size Mode Selection
+ * |        |          |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
+ * |        |          |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
+ * @var USBD_T::VBUSDET
+ * Offset: 0x14  USB Device VBUS Detection Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |FLDET     |Device VBUS Detected
+ * |        |          |0 = Controller is not attached into the USB host.
+ * |        |          |1 =Controller is attached into the BUS.
+ * @var USBD_T::STBUFSEG
+ * Offset: 0x18  Setup Token Buffer Segmentation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[8:3]   |STBUFSEG  |Setup Token Buffer Segmentation
+ * |        |          |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
+ * |        |          |USB_SRAM address + {STBUFSEG[8:3], 3'b000}
+ * |        |          |Where the USB_SRAM address = USBD_BA+0x100h.
+ * |        |          |Note: It is used for SETUP token only.
+ * @var USBD_T::SE0
+ * Offset: 0x90  USB Drive SE0 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |DRVSE0    |Drive Single Ended Zero In USB Bus
+ * |        |          |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
+ * |        |          |0 = None.
+ * |        |          |1 = Force USB PHY transceiver to drive SE0.
+ * @var USBD_T::EP
+ * Offset: 0x500 ~ 0x57C  USB End Point 0 ~ 7 Configuration Register
+ * ---------------------------------------------------------------------------------------------------
+ */
+
+    __IO uint32_t INTEN;         /* Offset: 0x00  USB Interrupt Enable Register                                      */
+    __IO uint32_t INTSTS;        /* Offset: 0x04  USB Interrupt Event Status Register                                */
+    __IO uint32_t FADDR;         /* Offset: 0x08  USB Device Function Address Register                               */
+    __I  uint32_t EPSTS;         /* Offset: 0x0C  USB Endpoint Status Register                                       */
+    __IO uint32_t ATTR;          /* Offset: 0x10  USB Bus Status and Attribution Register                            */
+    __I  uint32_t VBUSDET;       /* Offset: 0x14  USB Device VBUS Detection Register                                 */
+    __IO uint32_t STBUFSEG;      /* Offset: 0x18  Setup Token Buffer Segmentation Register                           */
+    __I  uint32_t RESERVE0[29]; 
+    __IO uint32_t SE0;           /* Offset: 0x90  USB Drive SE0 Control Register                                     */
+    __I  uint32_t RESERVE1[283];
+    USBD_EP_T     EP[8];         /* Offset: 0x500 ~ 0x57C  USB End Point 0 ~ 7 Configuration Register                */
+
+} USBD_T;
+
+
+
+/**
+    @addtogroup USB_CONST USB Bit Field Definition
+    Constant Definitions for USB Controller
+@{ */
+
+#define USBD_INTEN_BUSIEN_Pos            (0)                                               /*!< USBD_T::INTEN: BUSIEN Position            */
+#define USBD_INTEN_BUSIEN_Msk            (0x1ul << USBD_INTEN_BUSIEN_Pos)                  /*!< USBD_T::INTEN: BUSIEN Mask                */
+
+#define USBD_INTEN_USBIEN_Pos            (1)                                               /*!< USBD_T::INTEN: USBIEN Position            */
+#define USBD_INTEN_USBIEN_Msk            (0x1ul << USBD_INTEN_USBIEN_Pos)                  /*!< USBD_T::INTEN: USBIEN Mask                */
+
+#define USBD_INTEN_VBDETIEN_Pos          (2)                                               /*!< USBD_T::INTEN: VBDETIEN Position          */
+#define USBD_INTEN_VBDETIEN_Msk          (0x1ul << USBD_INTEN_VBDETIEN_Pos)                /*!< USBD_T::INTEN: VBDETIEN Mask              */
+
+#define USBD_INTEN_NEVWKIEN_Pos          (3)                                               /*!< USBD_T::INTEN: NEVWKIEN Position          */
+#define USBD_INTEN_NEVWKIEN_Msk          (0x1ul << USBD_INTEN_NEVWKIEN_Pos)                /*!< USBD_T::INTEN: NEVWKIEN Mask              */
+
+#define USBD_INTEN_WKEN_Pos              (8)                                               /*!< USBD_T::INTEN: WKEN Position              */
+#define USBD_INTEN_WKEN_Msk              (0x1ul << USBD_INTEN_WKEN_Pos)                    /*!< USBD_T::INTEN: WKEN Mask                  */
+
+#define USBD_INTEN_INNAKEN_Pos           (15)                                              /*!< USBD_T::INTEN: INNAKEN Position           */
+#define USBD_INTEN_INNAKEN_Msk           (0x1ul << USBD_INTEN_INNAKEN_Pos)                 /*!< USBD_T::INTEN: INNAKEN Mask               */
+
+#define USBD_INTSTS_BUSIF_Pos            (0)                                               /*!< USBD_T::INTSTS: BUSIF Position            */
+#define USBD_INTSTS_BUSIF_Msk            (0x1ul << USBD_INTSTS_BUSIF_Pos)                  /*!< USBD_T::INTSTS: BUSIF Mask                */
+
+#define USBD_INTSTS_USBIF_Pos            (1)                                               /*!< USBD_T::INTSTS: USBIF Position            */
+#define USBD_INTSTS_USBIF_Msk            (0x1ul << USBD_INTSTS_USBIF_Pos)                  /*!< USBD_T::INTSTS: USBIF Mask                */
+
+#define USBD_INTSTS_VBDETIF_Pos          (2)                                               /*!< USBD_T::INTSTS: VBDETIF Position          */
+#define USBD_INTSTS_VBDETIF_Msk          (0x1ul << USBD_INTSTS_VBDETIF_Pos)                /*!< USBD_T::INTSTS: VBDETIF Mask              */
+
+#define USBD_INTSTS_NEVWKIF_Pos          (3)                                               /*!< USBD_T::INTSTS: NEVWKIF Position          */
+#define USBD_INTSTS_NEVWKIF_Msk          (0x1ul << USBD_INTSTS_NEVWKIF_Pos)                /*!< USBD_T::INTSTS: NEVWKIF Mask              */
+
+#define USBD_INTSTS_EPEVT0_Pos           (16)                                              /*!< USBD_T::INTSTS: EPEVT0 Position           */
+#define USBD_INTSTS_EPEVT0_Msk           (0x1ul << USBD_INTSTS_EPEVT0_Pos)                 /*!< USBD_T::INTSTS: EPEVT0 Mask               */
+
+#define USBD_INTSTS_EPEVT1_Pos           (17)                                              /*!< USBD_T::INTSTS: EPEVT1 Position           */
+#define USBD_INTSTS_EPEVT1_Msk           (0x1ul << USBD_INTSTS_EPEVT1_Pos)                 /*!< USBD_T::INTSTS: EPEVT1 Mask               */
+
+#define USBD_INTSTS_EPEVT2_Pos           (18)                                              /*!< USBD_T::INTSTS: EPEVT2 Position           */
+#define USBD_INTSTS_EPEVT2_Msk           (0x1ul << USBD_INTSTS_EPEVT2_Pos)                 /*!< USBD_T::INTSTS: EPEVT2 Mask               */
+
+#define USBD_INTSTS_EPEVT3_Pos           (19)                                              /*!< USBD_T::INTSTS: EPEVT3 Position           */
+#define USBD_INTSTS_EPEVT3_Msk           (0x1ul << USBD_INTSTS_EPEVT3_Pos)                 /*!< USBD_T::INTSTS: EPEVT3 Mask               */
+
+#define USBD_INTSTS_EPEVT4_Pos           (20)                                              /*!< USBD_T::INTSTS: EPEVT4 Position           */
+#define USBD_INTSTS_EPEVT4_Msk           (0x1ul << USBD_INTSTS_EPEVT4_Pos)                 /*!< USBD_T::INTSTS: EPEVT4 Mask               */
+
+#define USBD_INTSTS_EPEVT5_Pos           (21)                                              /*!< USBD_T::INTSTS: EPEVT5 Position           */
+#define USBD_INTSTS_EPEVT5_Msk           (0x1ul << USBD_INTSTS_EPEVT5_Pos)                 /*!< USBD_T::INTSTS: EPEVT5 Mask               */
+
+#define USBD_INTSTS_EPEVT6_Pos           (22)                                              /*!< USBD_T::INTSTS: EPEVT6 Position           */
+#define USBD_INTSTS_EPEVT6_Msk           (0x1ul << USBD_INTSTS_EPEVT6_Pos)                 /*!< USBD_T::INTSTS: EPEVT6 Mask               */
+
+#define USBD_INTSTS_EPEVT7_Pos           (23)                                              /*!< USBD_T::INTSTS: EPEVT7 Position           */
+#define USBD_INTSTS_EPEVT7_Msk           (0x1ul << USBD_INTSTS_EPEVT7_Pos)                 /*!< USBD_T::INTSTS: EPEVT7 Mask               */
+
+#define USBD_INTSTS_SETUP_Pos            (31)                                              /*!< USBD_T::INTSTS: SETUP Position            */
+#define USBD_INTSTS_SETUP_Msk            (0x1ul << USBD_INTSTS_SETUP_Pos)                  /*!< USBD_T::INTSTS: SETUP Mask                */
+
+#define USBD_FADDR_FADDR_Pos             (0)                                               /*!< USBD_T::FADDR: FADDR Position             */
+#define USBD_FADDR_FADDR_Msk             (0x7ful << USBD_FADDR_FADDR_Pos)                  /*!< USBD_T::FADDR: FADDR Mask                 */
+
+#define USBD_EPSTS_OV_Pos                (7)                                               /*!< USBD_T::EPSTS: OV Position                */
+#define USBD_EPSTS_OV_Msk                (0x1ul << USBD_EPSTS_OV_Pos)                      /*!< USBD_T::EPSTS: OV Mask                    */
+
+#define USBD_EPSTS_EPSTS0_Pos            (8)                                               /*!< USBD_T::EPSTS: EPSTS0 Position            */
+#define USBD_EPSTS_EPSTS0_Msk            (0x7ul << USBD_EPSTS_EPSTS0_Pos)                  /*!< USBD_T::EPSTS: EPSTS0 Mask                */
+
+#define USBD_EPSTS_EPSTS1_Pos            (11)                                              /*!< USBD_T::EPSTS: EPSTS1 Position            */
+#define USBD_EPSTS_EPSTS1_Msk            (0x7ul << USBD_EPSTS_EPSTS1_Pos)                  /*!< USBD_T::EPSTS: EPSTS1 Mask                */
+
+#define USBD_EPSTS_EPSTS2_Pos            (14)                                              /*!< USBD_T::EPSTS: EPSTS2 Position            */
+#define USBD_EPSTS_EPSTS2_Msk            (0x7ul << USBD_EPSTS_EPSTS2_Pos)                  /*!< USBD_T::EPSTS: EPSTS2 Mask                */
+
+#define USBD_EPSTS_EPSTS3_Pos            (17)                                              /*!< USBD_T::EPSTS: EPSTS3 Position            */
+#define USBD_EPSTS_EPSTS3_Msk            (0x7ul << USBD_EPSTS_EPSTS3_Pos)                  /*!< USBD_T::EPSTS: EPSTS3 Mask                */
+
+#define USBD_EPSTS_EPSTS4_Pos            (20)                                              /*!< USBD_T::EPSTS: EPSTS4 Position            */
+#define USBD_EPSTS_EPSTS4_Msk            (0x7ul << USBD_EPSTS_EPSTS4_Pos)                  /*!< USBD_T::EPSTS: EPSTS4 Mask                */
+
+#define USBD_EPSTS_EPSTS5_Pos            (23)                                              /*!< USBD_T::EPSTS: EPSTS5 Position            */
+#define USBD_EPSTS_EPSTS5_Msk            (0x7ul << USBD_EPSTS_EPSTS5_Pos)                  /*!< USBD_T::EPSTS: EPSTS5 Mask                */
+
+#define USBD_EPSTS_EPSTS6_Pos            (26)                                              /*!< USBD_T::EPSTS: EPSTS6 Position            */
+#define USBD_EPSTS_EPSTS6_Msk            (0x7ul << USBD_EPSTS_EPSTS6_Pos)                  /*!< USBD_T::EPSTS: EPSTS6 Mask                */
+
+#define USBD_EPSTS_EPSTS7_Pos            (29)                                              /*!< USBD_T::EPSTS: EPSTS7 Position            */
+#define USBD_EPSTS_EPSTS7_Msk            (0x7ul << USBD_EPSTS_EPSTS7_Pos)                  /*!< USBD_T::EPSTS: EPSTS7 Mask                */
+
+#define USBD_ATTR_USBRST_Pos             (0)                                               /*!< USBD_T::ATTR: USBRST Position             */
+#define USBD_ATTR_USBRST_Msk             (0x1ul << USBD_ATTR_USBRST_Pos)                   /*!< USBD_T::ATTR: USBRST Mask                 */
+
+#define USBD_ATTR_SUSPEND_Pos            (1)                                               /*!< USBD_T::ATTR: SUSPEND Position            */
+#define USBD_ATTR_SUSPEND_Msk            (0x1ul << USBD_ATTR_SUSPEND_Pos)                  /*!< USBD_T::ATTR: SUSPEND Mask                */
+
+#define USBD_ATTR_RESUME_Pos             (2)                                               /*!< USBD_T::ATTR: RESUME Position             */
+#define USBD_ATTR_RESUME_Msk             (0x1ul << USBD_ATTR_RESUME_Pos)                   /*!< USBD_T::ATTR: RESUME Mask                 */
+
+#define USBD_ATTR_TOUT_Pos               (3)                                               /*!< USBD_T::ATTR: TOUT Position               */
+#define USBD_ATTR_TOUT_Msk               (0x1ul << USBD_ATTR_TOUT_Pos)                     /*!< USBD_T::ATTR: TOUT Mask                   */
+
+#define USBD_ATTR_PHYEN_Pos              (4)                                               /*!< USBD_T::ATTR: PHYEN Position              */
+#define USBD_ATTR_PHYEN_Msk              (0x1ul << USBD_ATTR_PHYEN_Pos)                    /*!< USBD_T::ATTR: PHYEN Mask                  */
+
+#define USBD_ATTR_RWAKEUP_Pos            (5)                                               /*!< USBD_T::ATTR: RWAKEUP Position            */
+#define USBD_ATTR_RWAKEUP_Msk            (0x1ul << USBD_ATTR_RWAKEUP_Pos)                  /*!< USBD_T::ATTR: RWAKEUP Mask                */
+
+#define USBD_ATTR_USBEN_Pos              (7)                                               /*!< USBD_T::ATTR: USBEN Position              */
+#define USBD_ATTR_USBEN_Msk              (0x1ul << USBD_ATTR_USBEN_Pos)                    /*!< USBD_T::ATTR: USBEN Mask                  */
+
+#define USBD_ATTR_DPPUEN_Pos             (8)                                               /*!< USBD_T::ATTR: DPPUEN Position             */
+#define USBD_ATTR_DPPUEN_Msk             (0x1ul << USBD_ATTR_DPPUEN_Pos)                   /*!< USBD_T::ATTR: DPPUEN Mask                 */
+
+#define USBD_ATTR_PWRDN_Pos              (9)                                               /*!< USBD_T::ATTR: PWRDN Position              */
+#define USBD_ATTR_PWRDN_Msk              (0x1ul << USBD_ATTR_PWRDN_Pos)                    /*!< USBD_T::ATTR: PWRDN Mask                  */
+
+#define USBD_ATTR_BYTEM_Pos              (10)                                              /*!< USBD_T::ATTR: BYTEM Position              */
+#define USBD_ATTR_BYTEM_Msk              (0x1ul << USBD_ATTR_BYTEM_Pos)                    /*!< USBD_T::ATTR: BYTEM Mask                  */
+
+#define USBD_VBUSDET_VBUSDET_Pos         (0)                                               /*!< USBD_T::VBUSDET: VBUSDET Position         */
+#define USBD_VBUSDET_VBUSDET_Msk         (0x1ul << USBD_VBUSDET_VBUSDET_Pos)               /*!< USBD_T::VBUSDET: VBUSDET Mask             */
+
+#define USBD_STBUFSEG_STBUFSEG_Pos       (3)                                               /*!< USBD_T::STBUFSEG: STBUFSEG Position       */
+#define USBD_STBUFSEG_STBUFSEG_Msk       (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos)            /*!< USBD_T::STBUFSEG: STBUFSEG Mask           */
+
+#define USBD_SE0_SE0_Pos                 (0)                                               /*!< USBD_T::SE0: SE0 Position                 */
+#define USBD_SE0_SE0_Msk                 (0x1ul << USBD_SE0_SE0_Pos)                       /*!< USBD_T::SE0: SE0 Mask                     */
+
+#define USBD_BUFSEG_BUFSEG_Pos           (3)                                               /*!< USBD_EP_T::BUFSEG: BUFSEG Position          */
+#define USBD_BUFSEG_BUFSEG_Msk           (0x3ful << USBD_BUFSEG_BUFSEG_Pos)                /*!< USBD_EP_T::BUFSEG: BUFSEG Mask              */
+
+#define USBD_MXPLD_MXPLD_Pos             (0)                                               /*!< USBD_EP_T::MXPLD: MXPLD Position            */
+#define USBD_MXPLD_MXPLD_Msk             (0x1fful << USBD_MXPLD_MXPLD_Pos)                 /*!< USBD_EP_T::MXPLD: MXPLD Mask                */
+
+#define USBD_CFG_EPNUM_Pos               (0)                                               /*!< USBD_EP_T::CFG: EPNUM Position              */
+#define USBD_CFG_EPNUM_Msk               (0xful << USBD_CFG_EPNUM_Pos)                     /*!< USBD_EP_T::CFG: EPNUM Mask                  */
+
+#define USBD_CFG_ISOCH_Pos               (4)                                               /*!< USBD_EP_T::CFG: ISOCH Position              */
+#define USBD_CFG_ISOCH_Msk               (0x1ul << USBD_CFG_ISOCH_Pos)                     /*!< USBD_EP_T::CFG: ISOCH Mask                  */
+
+#define USBD_CFG_STATE_Pos               (5)                                               /*!< USBD_EP_T::CFG: STATE Position              */
+#define USBD_CFG_STATE_Msk               (0x3ul << USBD_CFG_STATE_Pos)                     /*!< USBD_EP_T::CFG: STATE Mask                  */
+
+#define USBD_CFG_DSQSYNC_Pos             (7)                                               /*!< USBD_EP_T::CFG: DSQSYNC Position            */
+#define USBD_CFG_DSQSYNC_Msk             (0x1ul << USBD_CFG_DSQSYNC_Pos)                   /*!< USBD_EP_T::CFG: DSQSYNC Mask                */
+
+#define USBD_CFG_CSTALL_Pos              (9)                                               /*!< USBD_EP_T::CFG: CSTALL Position             */
+#define USBD_CFG_CSTALL_Msk              (0x1ul << USBD_CFG_CSTALL_Pos)                    /*!< USBD_EP_T::CFG: CSTALL Mask                 */
+
+#define USBD_CFGP_CLRRDY_Pos             (0)                                               /*!< USBD_EP_T::CFGP: CLRRDY Position            */
+#define USBD_CFGP_CLRRDY_Msk             (0x1ul << USBD_CFGP_CLRRDY_Pos)                   /*!< USBD_EP_T::CFGP: CLRRDY Mask                */
+
+#define USBD_CFGP_SSTALL_Pos             (1)                                               /*!< USBD_EP_T::CFGP: SSTALL Position            */
+#define USBD_CFGP_SSTALL_Msk             (0x1ul << USBD_CFGP_SSTALL_Pos)                   /*!< USBD_EP_T::CFGP: SSTALL Mask                */
+
+/**@}*/ /* USB_CONST */
+/**@}*/ /* end of USB register group */
+
+
+/*---------------------- USB Host Controller -------------------------*/
+/**
+    @addtogroup USBH USB Host Controller(USBH)
+    Memory Mapped Structure for USBH Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var USBH_T::HcRevision
+ * Offset: 0x00  Host Controller Revision Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |REV       |Revision Number
+ * |        |          |Indicates the Open HCI Specification revision number implemented by the Hardware.
+ * |        |          |Host Controller supports 1.1 specification.
+ * |        |          |(X.Y = XYh).
+ * @var USBH_T::HcControl
+ * Offset: 0x04  Host Controller Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |CBSR      |Control Bulk Service Ratio
+ * |        |          |This specifies the service ratio between Control and Bulk EDs.
+ * |        |          |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs.
+ * |        |          |The internal count will be retained when crossing the frame boundary.
+ * |        |          |In case of reset, HCD is responsible for restoring this.
+ * |        |          |Value.
+ * |        |          |00 = Number of Control EDs over Bulk EDs served is 1:1.
+ * |        |          |01 = Number of Control EDs over Bulk EDs served is 2:1.
+ * |        |          |10 = Number of Control EDs over Bulk EDs served is 3:1.
+ * |        |          |11 = Number of Control EDs over Bulk EDs served is 4:1.
+ * |[2]     |PLE       |Periodic List Enable Bit
+ * |        |          |When set, this bit enables processing of the Periodic (interrupt and Isochronous) list.
+ * |        |          |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
+ * |        |          |0 = Disable the processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame).
+ * |        |          |1 = Enable the processing of the Periodic (Interrupt and Isochronous) list in the next frame.
+ * |        |          |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
+ * |[3]     |IE        |Isochronous List Enable Bit
+ * |        |          |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list.
+ * |        |          |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
+ * |        |          |0 = Disable the processing of the Isochronous list after next SOF (Start-Of-Frame).
+ * |        |          |1 = Enable the processing of the Isochronous list in the next frame if the PLE (HcControl[2]) is high, too.
+ * |[4]     |CLE       |Control List Enable Bit
+ * |        |          |0 = Disable processing of the Control list after next SOF (Start-Of-Frame).
+ * |        |          |1 = Enable processing of the Control list in the next frame.
+ * |[5]     |BLE       |Bulk List Enable Bit
+ * |        |          |0 = Disable processing of the Bulk list after next SOF (Start-Of-Frame).
+ * |        |          |1 = Enable processing of the Bulk list in the next frame.
+ * |[7:6]   |HCFS      |Host Controller Functional State
+ * |        |          |This field sets the Host Controller state.
+ * |        |          |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port.
+ * |        |          |States are:
+ * |        |          |00 = USBSUSPEND.
+ * |        |          |01 = USBRESUME.
+ * |        |          |10 = USBOPERATIONAL.
+ * |        |          |11 = USBRESET.
+ * @var USBH_T::HcCommandStatus
+ * Offset: 0x08  Host Controller CMD Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |HCR       |Host Controller Reset
+ * |        |          |This bit is set to initiate the software reset of Host Controller.
+ * |        |          |This bit is cleared by the Host Controller, upon completed of the reset operation.
+ * |        |          |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
+ * |        |          |0 = Host Controller is not in software reset state.
+ * |        |          |1 = Host Controller is in software reset state.
+ * |[1]     |CLF       |Control List Filled
+ * |        |          |Set high to indicate there is an active TD on the Control List.
+ * |        |          |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
+ * |        |          |0 = No active TD found or Host Controller begins to process the head of the Control list.
+ * |        |          |1 = An active TD added or found on the Control list.
+ * |[2]     |BLF       |Bulk List Filled
+ * |        |          |Set high to indicate there is an active TD on the Bulk list.
+ * |        |          |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
+ * |        |          |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
+ * |        |          |1 = An active TD added or found on the Bulk list.
+ * |[17:16] |SOC       |Schedule Overrun Count
+ * |        |          |These bits are incremented on each scheduling overrun error.
+ * |        |          |It is initialized to 00b and wraps around at 11b.
+ * |        |          |This will be incremented when a scheduling overrun is detected even if SO (HcIntSts[0]) has already been set.
+ * @var USBH_T::HcInterruptStatus
+ * Offset: 0x0C  Host Controller Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SO        |Scheduling Overrun
+ * |        |          |Set when the List Processor determines a Schedule Overrun has occurred.
+ * |        |          |0 = Schedule Overrun didn't occur.
+ * |        |          |1 = Schedule Overrun has occurred.
+ * |[1]     |WDH       |Write Back Done Head
+ * |        |          |Set after the Host Controller has written HcDoneHead to HccaDoneHead.
+ * |        |          |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
+ * |        |          |0 =.Host Controller didn't update HccaDoneHead.
+ * |        |          |1 =.Host Controller has written HcDoneHead to HccaDoneHead.
+ * |[2]     |SF        |Start Of Frame
+ * |        |          |Set when the Frame Management functional block signals a 'Start of Frame' event.
+ * |        |          |Host Control generates a SOF token at the same time.
+ * |        |          |0 =.Not the start of a frame.
+ * |        |          |1 =.Indicate the start of a frame and Host Controller generates a SOF token.
+ * |[3]     |RD        |Resume Detected
+ * |        |          |Set when Host Controller detects resume signaling on a downstream port.
+ * |        |          |0 = No resume signaling detected on a downstream port.
+ * |        |          |1 = Resume signaling detected on a downstream port.
+ * |[5]     |FNO       |Frame Number Overflow
+ * |        |          |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
+ * |        |          |0 = The bit 15 of Frame Number didn't change.
+ * |        |          |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
+ * |[6]     |RHSC      |Root Hub Status Change
+ * |        |          |This bit is set when the content of HcRhSts or the content of HcRhPrt1 register has changed.
+ * |        |          |0 = The content of HcRhSts and the content of HcRhPrt1 register didn't change.
+ * |        |          |1 = The content of HcRhSts or the content of HcRhPrt1 register has changed.
+ * @var USBH_T::HcInterruptEnable
+ * Offset: 0x10  Host Controller Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SO        |Scheduling Overrun Enable Bit
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Enable interrupt generation due to SO (HcIntSts[0]).
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
+ * |        |          |1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
+ * |[1]     |WDH       |Write Back Done Head Enable Bit
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Enable interrupt generation due to WDH (HcIntSts[1]).
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
+ * |        |          |1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
+ * |[2]     |SF        |Start Of Frame Enable Bit
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Enable interrupt generation due to SF (HcIntSts[2]).
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
+ * |        |          |1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
+ * |[3]     |RD        |Resume Detected Enable Bit
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Enable interrupt generation due to RD (HcIntSts[3]).
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
+ * |        |          |1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
+ * |[5]     |FNO       |Frame Number Overflow Enable Bit
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Enable interrupt generation due to FNO (HcIntSts[5]).
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
+ * |        |          |1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
+ * |[6]     |RHSC      |Root Hub Status Change Enable Bit
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Enable interrupt generation due to RHSC (HcIntSts[6]).
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
+ * |        |          |1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
+ * |[31]    |MIE       |Master Interrupt Enable Bit
+ * |        |          |This bit is a global interrupt enable.
+ * |        |          |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Enable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
+ * |        |          |1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.
+ * @var USBH_T::HcInterruptDisable
+ * Offset: 0x14  Host Controller Interrupt Disable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |SO        |Scheduling Overrun Disable Bit
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Disable interrupt generation due to SO (HcIntSts[0]).
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
+ * |        |          |1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
+ * |[1]     |WDH       |Write Back Done Head Disable Bit
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Disable interrupt generation due to WDH (HcIntSts[1]).
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
+ * |        |          |1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
+ * |[2]     |SF        |Start Of Frame Disable Bit
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Disable interrupt generation due to SF (HcIntSts[2]).
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
+ * |        |          |1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
+ * |[3]     |RD        |Resume Detected Disable Bit
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Disable interrupt generation due to RD (HcIntSts[3]).
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
+ * |        |          |1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
+ * |[5]     |FNO       |Frame Number Overflow Disable Bit
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Disable interrupt generation due to FNO (HcIntSts[5]).
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
+ * |        |          |1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
+ * |[6]     |RHSC      |Root Hub Status Change Disable Bit
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Disable interrupt generation due to RHSC (HcIntSts[6]).
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
+ * |        |          |1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
+ * |[31]    |MIE       |Master Interrupt Disable Bit
+ * |        |          |Global interrupt disable. Writing '1' to disable all interrupts.
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Disable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
+ * |        |          |Read Operation:
+ * |        |          |0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
+ * |        |          |1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.
+ * @var USBH_T::HcHCCA
+ * Offset: 0x18  Host Controller Communication Area Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:8]  |HCCA      |Host Controller Communication Area
+ * |        |          |Pointer to indicate base address of the Host Controller Communication Area (HCCA).
+ * @var USBH_T::HcPeriodCurrentED
+ * Offset: 0x1C  Host Controller Period Current ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:4]  |PCED      |Periodic Current ED
+ * |        |          |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
+ * @var USBH_T::HcControlHeadED
+ * Offset: 0x20  Host Controller Control Head ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:4]  |CHED      |Control Head ED
+ * |        |          |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
+ * @var USBH_T::HcControlCurrentED
+ * Offset: 0x24  Host Controller Control Current ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:4]  |CCED      |Control Current Head ED
+ * |        |          |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
+ * @var USBH_T::HcBulkHeadED
+ * Offset: 0x28  Host Controller Bulk Head ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:4]  |BHED      |Bulk Head ED
+ * |        |          |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
+ * @var USBH_T::HcBulkCurrentED
+ * Offset: 0x2C  Host Controller Bulk Current ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:4]  |BCED      |Bulk Current Head ED
+ * |        |          |Pointer to indicate the physical address of the current endpoint of the Bulk list.
+ * @var USBH_T::HcDoneHead
+ * Offset: 0x30  Host Controller Done Head Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:4]  |DH        |Done Head
+ * |        |          |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
+ * @var USBH_T::HcFmInterval
+ * Offset: 0x34  Host Controller Frame Interval Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[13:0]  |FI        |Frame Interval
+ * |        |          |This field specifies the length of a frame as (bit times - 1).
+ * |        |          |For 12,000 bit times in a frame, a value of 11,999 is stored here.
+ * |[30:16] |FSMPS     |FS Largest Data Packet
+ * |        |          |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
+ * |[31]    |FIT       |Frame Interval Toggle
+ * |        |          |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmIntv[13:0]).
+ * |        |          |0 = Host Controller Driver didn't load new value into FI (HcFmIntv[13:0]).
+ * |        |          |1 = Host Controller Driver loads a new value into FI (HcFmIntv[13:0]).
+ * @var USBH_T::HcFmRemaining
+ * Offset: 0x38  Host Controller Frame Remaining Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[13:0]  |FR        |Frame Remaining
+ * |        |          |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period.
+ * |        |          |When the count reaches 0, (end of frame) the counter reloads with Frame Interval.
+ * |        |          |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
+ * |[31]    |FRT       |Frame Remaining Toggle
+ * |        |          |This bit is loaded from the FIT (HcFmIntv[31]) whenever FR (HcFmRem[13:0]) reaches 0.
+ * @var USBH_T::HcFmNumber
+ * Offset: 0x3C  Host Controller Frame Number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[15:0]  |FN        |Frame Number
+ * |        |          |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRem[13:0]).
+ * |        |          |The count rolls over from 'FFFFh' to '0h.'.
+ * @var USBH_T::HcPeriodicStart
+ * Offset: 0x40  Host Controller Periodic Start Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[13:0]  |PS        |Periodic Start
+ * |        |          |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
+ * @var USBH_T::HcLSThreshold
+ * Offset: 0x44  Host Controller Low-speed Threshold Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[11:0]  |LST       |Low-Speed Threshold
+ * |        |          |This field contains a value which is compared to the FR (HcFmRem[13:0]) field prior to initiating a Low-speed transaction.
+ * |        |          |The transaction is started only if FR (HcFmRem[13:0]) >= this field.
+ * |        |          |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
+ * @var USBH_T::HcRhDescriptorA
+ * Offset: 0x48  Host Controller Root Hub Descriptor A Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[7:0]   |NDP       |Number Downstream Ports
+ * |        |          |USB host control supports two downstream ports and only one port is available in this series of chip.
+ * |[8]     |PSM       |Power Switching Mode
+ * |        |          |This bit is used to specify how the power switching of the Root Hub ports is controlled.
+ * |        |          |0 = Global Switching.
+ * |        |          |1 = Individual Switching.
+ * |[11]    |OCPM      |Over Current Protection Mode
+ * |        |          |This bit describes how the over current status for the Root Hub ports reported.
+ * |        |          |This bit is only valid when NOCP (HcRhDeA[12]) is cleared.
+ * |        |          |0 = Global Over current.
+ * |        |          |1 = Individual Over current.
+ * |[12]    |NOCP      |No Over Current Protection
+ * |        |          |This bit describes how the over current status for the Root Hub ports reported.
+ * |        |          |0 = Over current status is reported.
+ * |        |          |1 = Over current status is not reported.
+ * @var USBH_T::HcRhDescriptorB
+ * Offset: 0x4C  Host Controller Root Hub Descriptor B Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:16] |PPCM      |Port Power Control Mask
+ * |        |          |Global power switching.
+ * |        |          |This field is only valid if PowerSwitchingMode is set (individual port switching).
+ * |        |          |When set, the port only responds to individual port power switching commands (Set/ClearPortPower).
+ * |        |          |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
+ * |        |          |0 = Port power controlled by global power switching.
+ * |        |          |1 = Port power controlled by port power switching.
+ * |        |          |Note: PPCM[15:2] and PPCM[0] are reserved.
+ * @var USBH_T::HcRhStatus
+ * Offset: 0x50  Host Controller Root Hub Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |LPS       |Clear Global Power
+ * |        |          |In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to clear all ports' power.
+ * |        |          |This bit always read as zero.
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Clear global power.
+ * |[1]     |OCI       |Over Current Indicator
+ * |        |          |This bit reflects the state of the over current status pin.
+ * |        |          |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
+ * |        |          |0 = No over current condition.
+ * |        |          |1 = Over current condition.
+ * |[15]    |DRWE      |Device Remote Wakeup Enable Bit
+ * |        |          |This bit controls if port's Connect Status Change as a remote wake-up event.
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Enable Connect Status Change as a remote wake-up event.
+ * |        |          |Read Operation:
+ * |        |          |0 = Connect Status Change as a remote wake-up event disabled.
+ * |        |          |1 = Connect Status Change as a remote wake-up event enabled.
+ * |[16]    |LPSC      |Set Global Power
+ * |        |          |In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to enable power to all ports.
+ * |        |          |This bit always read as zero.
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Set global power.
+ * |[17]    |OCIC      |Over Current Indicator Change
+ * |        |          |This bit is set by hardware when a change has occurred in OCI (HcRhSts[1]).
+ * |        |          |Write 1 to clear this bit to zero.
+ * |        |          |0 = OCI (HcRhSts[1]) didn't change.
+ * |        |          |1 = OCI (HcRhSts[1]) change.
+ * |[31]    |CRWE      |Clear Remote Wake-up Enable Bit
+ * |        |          |This bit is use to clear DRWE (HcRhSts[15]).
+ * |        |          |This bit always read as zero.
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Clear DRWE (HcRhSts[15]).
+ * @var USBH_T::HcRhPortStatus
+ * Offset: 0x54  Host Controller Root Hub Port Status [1]
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |CCS       |CurrentConnectStatus (Read) Or ClearPortEnable Bit (Write)
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Clear port enable.
+ * |        |          |Read Operation:
+ * |        |          |0 = No device connected.
+ * |        |          |1 = Device connected.
+ * |[1]     |PES       |Port Enable Status
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Set port enable.
+ * |        |          |Read Operation:
+ * |        |          |0 = Port Disabled.
+ * |        |          |1 = Port Enabled.
+ * |[2]     |PSS       |Port Suspend Status
+ * |        |          |This bit indicates the port is suspended
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Set port suspend.
+ * |        |          |Read Operation:
+ * |        |          |0 = Port is not suspended.
+ * |        |          |1 = Port is selectively suspended.
+ * |[3]     |POCI      |Port Over Current Indicator (Read) Or Clear Port Suspend (Write)
+ * |        |          |This bit reflects the state of the over current status pin dedicated to this port.
+ * |        |          |This field is only valid if NOCP (HcRhDeA[12]) is cleared and OCPM (HcRhDeA[11]) is set.
+ * |        |          |This bit is also used to initiate the selective result sequence for the port.
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Clear port suspend.
+ * |        |          |Read Operation:
+ * |        |          |0 = No over current condition.
+ * |        |          |1 = Over current condition.
+ * |[4]     |PRS       |Port Reset Status
+ * |        |          |This bit reflects the reset state of the port.
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Set port reset.
+ * |        |          |Read Operation
+ * |        |          |0 = Port reset signal is not active.
+ * |        |          |1 = Port reset signal is active.
+ * |[8]     |PPS       |Port Power Status
+ * |        |          |This bit reflects the power state of the port regardless of the power switching mode.
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Port Power Enabled.
+ * |        |          |Read Operation:
+ * |        |          |0 = Port power is Disabled.
+ * |        |          |1 = Port power is Enabled.
+ * |[9]     |LSDA      |Low Speed Device Attached (Read) Or Clear Port Power (Write)
+ * |        |          |This bit defines the speed (and bud idle) of the attached device.
+ * |        |          |It is only valid when CCS (HcRhPrt1[0]) is set.
+ * |        |          |This bit is also used to clear port power.
+ * |        |          |Write Operation:
+ * |        |          |0 = No effect.
+ * |        |          |1 = Clear PPS (HcRhPrt1[8]).
+ * |        |          |Read Operation:
+ * |        |          |0 = Full Speed device.
+ * |        |          |1 = Low-speed device.
+ * |[16]    |CSC       |Connect Status Change
+ * |        |          |This bit indicates connect or disconnect event has been detected (CCS
+ * |        |          |(HcRhPrt1[0]) changed).
+ * |        |          |Write 1 to clear this bit to zero.
+ * |        |          |0 = No connect/disconnect event (CCS (HcRhPrt1[0]) didn't change).
+ * |        |          |1 = Hardware detection of connect/disconnect event (CCS
+ * |        |          |(HcRhPrt1[0]) changed).
+ * |[17]    |PESC      |Port Enable Status Change
+ * |        |          |This bit indicates that the port has been disabled (PES (HcRhPrt1[1]) cleared) due to a hardware event.
+ * |        |          |Write 1 to clear this bit to zero.
+ * |        |          |0 = PES (HcRhPrt1[1]) didn't change.
+ * |        |          |1 = PES (HcRhPrt1[1]) changed.
+ * |[18]    |PSSC      |Port Suspend Status Change
+ * |        |          |This bit indicates the completion of the selective resume sequence for the port.
+ * |        |          |Write 1 to clear this bit to zero.
+ * |        |          |0 = Port resume is not completed.
+ * |        |          |1 = Port resume completed.
+ * |[19]    |OCIC      |Port Over Current Indicator Change
+ * |        |          |This bit is set when POCI (HcRhPrt1[3]) changes.
+ * |        |          |Write 1 to clear this bit to zero.
+ * |        |          |0 = POCI (HcRhPrt1[3]) didn't change.
+ * |        |          |1 = POCI (HcRhPrt1[3]) changes.
+ * |[20]    |PRSC      |Port Reset Status Change
+ * |        |          |This bit indicates that the port reset signal has completed.
+ * |        |          |Write 1 to clear this bit to zero.
+ * |        |          |0 = Port reset is not complete.
+ * |        |          |1 = Port reset is complete.
+ * @var USBH_T::HcPhyControl
+ * Offset: 0x200  USB Host Controller PHY Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[27]    |STBYEN    |USB Transceiver Standby Enable Bit
+ * |        |          |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
+ * |        |          |0 = The USB transceiver would never enter the standby mode.
+ * |        |          |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
+ * @var USBH_T::HcMiscControl
+ * Offset: 0x204  USB Host Controller Miscellaneous Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1]     |ABORT     |AHB Bus ERROR Response
+ * |        |          |This bit indicates there is an ERROR response received in AHB bus.
+ * |        |          |0 = No ERROR response received.
+ * |        |          |1 = ERROR response received.
+ * |[3]     |OCAL      |Over Current Active Low
+ * |        |          |This bit controls the polarity of over current flag from external power IC.
+ * |        |          |0 = Over current flag is high active.
+ * |        |          |1 = Over current flag is low active.
+ * |[16]    |DPRT1     |Disable Port 1
+ * |        |          |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled.
+ * |        |          |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
+ * |        |          |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
+ * |        |          |0 = The connection between USB host controller and transceiver of port 1 is enabled.
+ * |        |          |1 = The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode.
+    */
+
+    __I  uint32_t HcRevision;    /* Offset: 0x00  Host Controller Revision Register                                  */
+    __IO uint32_t HcControl;     /* Offset: 0x04  Host Controller Control Register                                   */
+    __IO uint32_t HcCommandStatus; /* Offset: 0x08  Host Controller CMD Status Register                                */
+    __IO uint32_t HcInterruptStatus; /* Offset: 0x0C  Host Controller Interrupt Status Register                          */
+    __IO uint32_t HcInterruptEnable; /* Offset: 0x10  Host Controller Interrupt Enable Register                          */
+    __IO uint32_t HcInterruptDisable; /* Offset: 0x14  Host Controller Interrupt Disable Register                         */
+    __IO uint32_t HcHCCA;        /* Offset: 0x18  Host Controller Communication Area Register                        */
+    __IO uint32_t HcPeriodCurrentED; /* Offset: 0x1C  Host Controller Period Current ED Register                         */
+    __IO uint32_t HcControlHeadED; /* Offset: 0x20  Host Controller Control Head ED Register                           */
+    __IO uint32_t HcControlCurrentED; /* Offset: 0x24  Host Controller Control Current ED Register                        */
+    __IO uint32_t HcBulkHeadED;  /* Offset: 0x28  Host Controller Bulk Head ED Register                              */
+    __IO uint32_t HcBulkCurrentED; /* Offset: 0x2C  Host Controller Bulk Current ED Register                           */
+    __IO uint32_t HcDoneHead;    /* Offset: 0x30  Host Controller Done Head Register                                 */
+    __IO uint32_t HcFmInterval;  /* Offset: 0x34  Host Controller Frame Interval Register                            */
+    __I  uint32_t HcFmRemaining; /* Offset: 0x38  Host Controller Frame Remaining Register                           */
+    __I  uint32_t HcFmNumber;    /* Offset: 0x3C  Host Controller Frame Number Register                              */
+    __IO uint32_t HcPeriodicStart; /* Offset: 0x40  Host Controller Periodic Start Register                            */
+    __IO uint32_t HcLSThreshold; /* Offset: 0x44  Host Controller Low-speed Threshold Register                       */
+    __IO uint32_t HcRhDescriptorA; /* Offset: 0x48  Host Controller Root Hub Descriptor A Register                     */
+    __IO uint32_t HcRhDescriptorB; /* Offset: 0x4C  Host Controller Root Hub Descriptor B Register                     */
+    __IO uint32_t HcRhStatus;    /* Offset: 0x50  Host Controller Root Hub Status Register                           */
+    __IO uint32_t HcRhPortStatus[2]; /* Offset: 0x54  Host Controller Root Hub Port Status [1]                           */
+    __I  uint32_t RESERVE0[105];
+    __IO uint32_t HcPhyControl;  /* Offset: 0x200  USB Host Controller PHY Control Register                          */
+    __IO uint32_t HcMiscControl; /* Offset: 0x204  USB Host Controller Miscellaneous Control Register                */
+
+} USBH_T;
+
+
+
+
+/**
+    @addtogroup USBH_CONST USBH Bit Field Definition
+    Constant Definitions for USBH Controller
+@{ */
+
+#define USBH_HcRevision_REV_Pos          (0)                                               /*!< USBH_T::HcRevision: REV Position          */
+#define USBH_HcRevision_REV_Msk          (0xfful << USBH_HcRevision_REV_Pos)               /*!< USBH_T::HcRevision: REV Mask              */
+
+#define USBH_HcControl_CBSR_Pos          (0)                                               /*!< USBH_T::HcControl: CBSR Position          */
+#define USBH_HcControl_CBSR_Msk          (0x3ul << USBH_HcControl_CBSR_Pos)                /*!< USBH_T::HcControl: CBSR Mask              */
+
+#define USBH_HcControl_PLE_Pos           (2)                                               /*!< USBH_T::HcControl: CBSR Position          */
+#define USBH_HcControl_PLE_Msk           (0x1ul << USBH_HcControl_PLE_Pos)                 /*!< USBH_T::HcControl: CBSR Mask              */
+
+#define USBH_HcControl_IE_Pos            (3)                                               /*!< USBH_T::HcControl: IE Position            */
+#define USBH_HcControl_IE_Msk            (0x1ul << USBH_HcControl_IE_Pos)                  /*!< USBH_T::HcControl: IE Mask                */
+
+#define USBH_HcControl_CLE_Pos           (4)                                               /*!< USBH_T::HcControl: CLE Position           */
+#define USBH_HcControl_CLE_Msk           (0x1ul << USBH_HcControl_CLE_Pos)                 /*!< USBH_T::HcControl: CLE Mask               */
+
+#define USBH_HcControl_BLE_Pos           (5)                                               /*!< USBH_T::HcControl: BLE Position           */
+#define USBH_HcControl_BLE_Msk           (0x1ul << USBH_HcControl_BLE_Pos)                 /*!< USBH_T::HcControl: BLE Mask               */
+
+#define USBH_HcControl_HCFS_Pos          (6)                                               /*!< USBH_T::HcControl: HCFS Position          */
+#define USBH_HcControl_HCFS_Msk          (0x3ul << USBH_HcControl_HCFS_Pos)                /*!< USBH_T::HcControl: HCFS Mask              */
+
+#define USBH_HcCommandStatus_HCR_Pos     (0)                                               /*!< USBH_T::HcCommandStatus: HCR Position     */
+#define USBH_HcCommandStatus_HCR_Msk     (0x1ul << USBH_HcCommandStatus_HCR_Pos)           /*!< USBH_T::HcCommandStatus: HCR Mask         */
+
+#define USBH_HcCommandStatus_CLF_Pos     (1)                                               /*!< USBH_T::HcCommandStatus: CLF Position     */
+#define USBH_HcCommandStatus_CLF_Msk     (0x1ul << USBH_HcCommandStatus_CLF_Pos)           /*!< USBH_T::HcCommandStatus: CLF Mask         */
+
+#define USBH_HcCommandStatus_BLF_Pos     (2)                                               /*!< USBH_T::HcCommandStatus: BLF Position     */
+#define USBH_HcCommandStatus_BLF_Msk     (0x1ul << USBH_HcCommandStatus_BLF_Pos)           /*!< USBH_T::HcCommandStatus: BLF Mask         */
+
+#define USBH_HcCommandStatus_SOC_Pos     (16)                                              /*!< USBH_T::HcCommandStatus: SOC Position     */
+#define USBH_HcCommandStatus_SOC_Msk     (0x3ul << USBH_HcCommandStatus_SOC_Pos)           /*!< USBH_T::HcCommandStatus: SOC Mask         */
+
+#define USBH_HcInterruptStatus_SO_Pos    (0)                                               /*!< USBH_T::HcInterruptStatus: SO Position    */
+#define USBH_HcInterruptStatus_SO_Msk    (0x1ul << USBH_HcInterruptStatus_SO_Pos)          /*!< USBH_T::HcInterruptStatus: SO Mask        */
+
+#define USBH_HcInterruptStatus_WDH_Pos   (1)                                               /*!< USBH_T::HcInterruptStatus: WDH Position   */
+#define USBH_HcInterruptStatus_WDH_Msk   (0x1ul << USBH_HcInterruptStatus_WDH_Pos)         /*!< USBH_T::HcInterruptStatus: WDH Mask       */
+
+#define USBH_HcInterruptStatus_SF_Pos    (2)                                               /*!< USBH_T::HcInterruptStatus: SF Position    */
+#define USBH_HcInterruptStatus_SF_Msk    (0x1ul << USBH_HcInterruptStatus_SF_Pos)          /*!< USBH_T::HcInterruptStatus: SF Mask        */
+
+#define USBH_HcInterruptStatus_RD_Pos    (3)                                               /*!< USBH_T::HcInterruptStatus: RD Position    */
+#define USBH_HcInterruptStatus_RD_Msk    (0x1ul << USBH_HcInterruptStatus_RD_Pos)          /*!< USBH_T::HcInterruptStatus: RD Mask        */
+
+#define USBH_HcInterruptStatus_FNO_Pos   (5)                                               /*!< USBH_T::HcInterruptStatus: FNO Position   */
+#define USBH_HcInterruptStatus_FNO_Msk   (0x1ul << USBH_HcInterruptStatus_FNO_Pos)         /*!< USBH_T::HcInterruptStatus: FNO Mask       */
+
+#define USBH_HcInterruptStatus_RHSC_Pos  (6)                                               /*!< USBH_T::HcInterruptStatus: RHSC Position  */
+#define USBH_HcInterruptStatus_RHSC_Msk  (0x1ul << USBH_HcInterruptStatus_RHSC_Pos)        /*!< USBH_T::HcInterruptStatus: RHSC Mask      */
+
+#define USBH_HcInterruptEnable_SO_Pos    (0)                                               /*!< USBH_T::HcInterruptEnable: SO Position    */
+#define USBH_HcInterruptEnable_SO_Msk    (0x1ul << USBH_HcInterruptEnable_SO_Pos)          /*!< USBH_T::HcInterruptEnable: SO Mask        */
+
+#define USBH_HcInterruptEnable_WDH_Pos   (1)                                               /*!< USBH_T::HcInterruptEnable: WDH Position   */
+#define USBH_HcInterruptEnable_WDH_Msk   (0x1ul << USBH_HcInterruptEnable_WDH_Pos)         /*!< USBH_T::HcInterruptEnable: WDH Mask       */
+
+#define USBH_HcInterruptEnable_SF_Pos    (2)                                               /*!< USBH_T::HcInterruptEnable: SF Position    */
+#define USBH_HcInterruptEnable_SF_Msk    (0x1ul << USBH_HcInterruptEnable_SF_Pos)          /*!< USBH_T::HcInterruptEnable: SF Mask        */
+
+#define USBH_HcInterruptEnable_RD_Pos    (3)                                               /*!< USBH_T::HcInterruptEnable: RD Position    */
+#define USBH_HcInterruptEnable_RD_Msk    (0x1ul << USBH_HcInterruptEnable_RD_Pos)          /*!< USBH_T::HcInterruptEnable: RD Mask        */
+
+#define USBH_HcInterruptEnable_FNO_Pos   (5)                                               /*!< USBH_T::HcInterruptEnable: FNO Position   */
+#define USBH_HcInterruptEnable_FNO_Msk   (0x1ul << USBH_HcInterruptEnable_FNO_Pos)         /*!< USBH_T::HcInterruptEnable: FNO Mask       */
+
+#define USBH_HcInterruptEnable_RHSC_Pos  (6)                                               /*!< USBH_T::HcInterruptEnable: RHSC Position  */
+#define USBH_HcInterruptEnable_RHSC_Msk  (0x1ul << USBH_HcInterruptEnable_RHSC_Pos)        /*!< USBH_T::HcInterruptEnable: RHSC Mask      */
+
+#define USBH_HcInterruptEnable_MIE_Pos   (31)                                              /*!< USBH_T::HcInterruptEnable: MIE Position   */
+#define USBH_HcInterruptEnable_MIE_Msk   (0x1ul << USBH_HcInterruptEnable_MIE_Pos)         /*!< USBH_T::HcInterruptEnable: MIE Mask       */
+
+#define USBH_HcInterruptDisable_SO_Pos   (0)                                               /*!< USBH_T::HcInterruptDisable: SO Position   */
+#define USBH_HcInterruptDisable_SO_Msk   (0x1ul << USBH_HcInterruptDisable_SO_Pos)         /*!< USBH_T::HcInterruptDisable: SO Mask       */
+
+#define USBH_HcInterruptDisable_WDH_Pos  (1)                                               /*!< USBH_T::HcInterruptDisable: WDH Position  */
+#define USBH_HcInterruptDisable_WDH_Msk  (0x1ul << USBH_HcInterruptDisable_WDH_Pos)        /*!< USBH_T::HcInterruptDisable: WDH Mask      */
+
+#define USBH_HcInterruptDisable_SF_Pos   (2)                                               /*!< USBH_T::HcInterruptDisable: SF Position   */
+#define USBH_HcInterruptDisable_SF_Msk   (0x1ul << USBH_HcInterruptDisable_SF_Pos)         /*!< USBH_T::HcInterruptDisable: SF Mask       */
+
+#define USBH_HcInterruptDisable_RD_Pos   (3)                                               /*!< USBH_T::HcInterruptDisable: RD Position   */
+#define USBH_HcInterruptDisable_RD_Msk   (0x1ul << USBH_HcInterruptDisable_RD_Pos)         /*!< USBH_T::HcInterruptDisable: RD Mask       */
+
+#define USBH_HcInterruptDisable_FNO_Pos  (5)                                               /*!< USBH_T::HcInterruptDisable: FNO Position  */
+#define USBH_HcInterruptDisable_FNO_Msk  (0x1ul << USBH_HcInterruptDisable_FNO_Pos)        /*!< USBH_T::HcInterruptDisable: FNO Mask      */
+
+#define USBH_HcInterruptDisable_RHSC_Pos (6)                                               /*!< USBH_T::HcInterruptDisable: RHSC Position */
+#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos)       /*!< USBH_T::HcInterruptDisable: RHSC Mask     */
+
+#define USBH_HcInterruptDisable_MIE_Pos  (31)                                              /*!< USBH_T::HcInterruptDisable: MIE Position  */
+#define USBH_HcInterruptDisable_MIE_Msk  (0x1ul << USBH_HcInterruptDisable_MIE_Pos)        /*!< USBH_T::HcInterruptDisable: MIE Mask      */
+
+#define USBH_HcHCCA_HCCA_Pos             (8)                                               /*!< USBH_T::HcHCCA: HCCA Position             */
+#define USBH_HcHCCA_HCCA_Msk             (0xfffffful << USBH_HcHCCA_HCCA_Pos)              /*!< USBH_T::HcHCCA: HCCA Mask                 */
+
+#define USBH_HcPeriodCurrentED_PCED_Pos  (4)                                               /*!< USBH_T::HcPeriodCurrentED: PCED Position  */
+#define USBH_HcPeriodCurrentED_PCED_Msk  (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos)  /*!< USBH_T::HcPeriodCurrentED: PCED Mask      */
+
+#define USBH_HcControlHeadED_CHED_Pos    (4)                                               /*!< USBH_T::HcControlHeadED: CHED Position    */
+#define USBH_HcControlHeadED_CHED_Msk    (0xffffffful << USBH_HcControlHeadED_CHED_Pos)    /*!< USBH_T::HcControlHeadED: CHED Mask        */
+
+#define USBH_HcControlCurrentED_CCED_Pos (4)                                               /*!< USBH_T::HcControlCurrentED: CCED Position */
+#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask     */
+
+#define USBH_HcBulkHeadED_BHED_Pos       (4)                                               /*!< USBH_T::HcBulkHeadED: BHED Position       */
+#define USBH_HcBulkHeadED_BHED_Msk       (0xffffffful << USBH_HcBulkHeadED_BHED_Pos)       /*!< USBH_T::HcBulkHeadED: BHED Mask           */
+
+#define USBH_HcBulkCurrentED_BCED_Pos    (4)                                               /*!< USBH_T::HcBulkCurrentED: BCED Position    */
+#define USBH_HcBulkCurrentED_BCED_Msk    (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos)    /*!< USBH_T::HcBulkCurrentED: BCED Mask        */
+
+#define USBH_HcDoneHead_DH_Pos           (4)                                               /*!< USBH_T::HcDoneHead: DH Position           */
+#define USBH_HcDoneHead_DH_Msk           (0xffffffful << USBH_HcDoneHead_DH_Pos)           /*!< USBH_T::HcDoneHead: DH Mask               */
+
+#define USBH_HcFmInterval_FI_Pos         (0)                                               /*!< USBH_T::HcFmInterval: FI Position         */
+#define USBH_HcFmInterval_FI_Msk         (0x3ffful << USBH_HcFmInterval_FI_Pos)            /*!< USBH_T::HcFmInterval: FI Mask             */
+
+#define USBH_HcFmInterval_FSMPS_Pos      (16)                                              /*!< USBH_T::HcFmInterval: FSMPS Position      */
+#define USBH_HcFmInterval_FSMPS_Msk      (0x7ffful << USBH_HcFmInterval_FSMPS_Pos)         /*!< USBH_T::HcFmInterval: FSMPS Mask          */
+
+#define USBH_HcFmInterval_FIT_Pos        (31)                                              /*!< USBH_T::HcFmInterval: FIT Position        */
+#define USBH_HcFmInterval_FIT_Msk        (0x1ul << USBH_HcFmInterval_FIT_Pos)              /*!< USBH_T::HcFmInterval: FIT Mask            */
+
+#define USBH_HcFmRemaining_FR_Pos        (0)                                               /*!< USBH_T::HcFmRemaining: FR Position        */
+#define USBH_HcFmRemaining_FR_Msk        (0x3ffful << USBH_HcFmRemaining_FR_Pos)           /*!< USBH_T::HcFmRemaining: FR Mask            */
+
+#define USBH_HcFmRemaining_FRT_Pos       (31)                                              /*!< USBH_T::HcFmRemaining: FRT Position       */
+#define USBH_HcFmRemaining_FRT_Msk       (0x1ul << USBH_HcFmRemaining_FRT_Pos)             /*!< USBH_T::HcFmRemaining: FRT Mask           */
+
+#define USBH_HcFmNumber_FN_Pos           (0)                                               /*!< USBH_T::HcFmNumber: FN Position           */
+#define USBH_HcFmNumber_FN_Msk           (0xfffful << USBH_HcFmNumber_FN_Pos)              /*!< USBH_T::HcFmNumber: FN Mask               */
+
+#define USBH_HcPeriodicStart_PS_Pos      (0)                                               /*!< USBH_T::HcPeriodicStart: PS Position      */
+#define USBH_HcPeriodicStart_PS_Msk      (0x3ffful << USBH_HcPeriodicStart_PS_Pos)         /*!< USBH_T::HcPeriodicStart: PS Mask          */
+
+#define USBH_HcLSThreshold_LST_Pos       (0)                                               /*!< USBH_T::HcLSThreshold: LST Position       */
+#define USBH_HcLSThreshold_LST_Msk       (0xffful << USBH_HcLSThreshold_LST_Pos)           /*!< USBH_T::HcLSThreshold: LST Mask           */
+
+#define USBH_HcRhDescriptorA_NDP_Pos     (0)                                               /*!< USBH_T::HcRhDescriptorA: NDP Position     */
+#define USBH_HcRhDescriptorA_NDP_Msk     (0xfful << USBH_HcRhDescriptorA_NDP_Pos)          /*!< USBH_T::HcRhDescriptorA: NDP Mask         */
+
+#define USBH_HcRhDescriptorA_PSM_Pos     (8)                                               /*!< USBH_T::HcRhDescriptorA: PSM Position     */
+#define USBH_HcRhDescriptorA_PSM_Msk     (0x1ul << USBH_HcRhDescriptorA_PSM_Pos)           /*!< USBH_T::HcRhDescriptorA: PSM Mask         */
+
+#define USBH_HcRhDescriptorA_OCPM_Pos    (11)                                              /*!< USBH_T::HcRhDescriptorA: OCPM Position    */
+#define USBH_HcRhDescriptorA_OCPM_Msk    (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos)          /*!< USBH_T::HcRhDescriptorA: OCPM Mask        */
+
+#define USBH_HcRhDescriptorA_NOCP_Pos    (12)                                              /*!< USBH_T::HcRhDescriptorA: NOCP Position    */
+#define USBH_HcRhDescriptorA_NOCP_Msk    (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos)          /*!< USBH_T::HcRhDescriptorA: NOCP Mask        */
+
+#define USBH_HcRhDescriptorB_PPCM_Pos    (16)                                              /*!< USBH_T::HcRhDescriptorB: PPCM Position    */
+#define USBH_HcRhDescriptorB_PPCM_Msk    (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos)       /*!< USBH_T::HcRhDescriptorB: PPCM Mask        */
+
+#define USBH_HcRhStatus_LPS_Pos          (0)                                               /*!< USBH_T::HcRhStatus: LPS Position          */
+#define USBH_HcRhStatus_LPS_Msk          (0x1ul << USBH_HcRhStatus_LPS_Pos)                /*!< USBH_T::HcRhStatus: LPS Mask              */
+
+#define USBH_HcRhStatus_OCI_Pos          (1)                                               /*!< USBH_T::HcRhStatus: OCI Position          */
+#define USBH_HcRhStatus_OCI_Msk          (0x1ul << USBH_HcRhStatus_OCI_Pos)                /*!< USBH_T::HcRhStatus: OCI Mask              */
+
+#define USBH_HcRhStatus_DRWE_Pos         (15)                                              /*!< USBH_T::HcRhStatus: DRWE Position         */
+#define USBH_HcRhStatus_DRWE_Msk         (0x1ul << USBH_HcRhStatus_DRWE_Pos)               /*!< USBH_T::HcRhStatus: DRWE Mask             */
+
+#define USBH_HcRhStatus_LPSC_Pos         (16)                                              /*!< USBH_T::HcRhStatus: LPSC Position         */
+#define USBH_HcRhStatus_LPSC_Msk         (0x1ul << USBH_HcRhStatus_LPSC_Pos)               /*!< USBH_T::HcRhStatus: LPSC Mask             */
+
+#define USBH_HcRhStatus_OCIC_Pos         (17)                                              /*!< USBH_T::HcRhStatus: OCIC Position         */
+#define USBH_HcRhStatus_OCIC_Msk         (0x1ul << USBH_HcRhStatus_OCIC_Pos)               /*!< USBH_T::HcRhStatus: OCIC Mask             */
+
+#define USBH_HcRhStatus_CRWE_Pos         (31)                                              /*!< USBH_T::HcRhStatus: CRWE Position         */
+#define USBH_HcRhStatus_CRWE_Msk         (0x1ul << USBH_HcRhStatus_CRWE_Pos)               /*!< USBH_T::HcRhStatus: CRWE Mask             */
+
+#define USBH_HcRhPortStatus_CCS_Pos      (0)                                               /*!< USBH_T::HcRhPortStatus: CCS Position      */
+#define USBH_HcRhPortStatus_CCS_Msk      (0x1ul << USBH_HcRhPortStatus_CCS_Pos)             /*!< USBH_T::HcRhPortStatus: CCS Mask         */
+
+#define USBH_HcRhPortStatus_PES_Pos      (1)                                               /*!< USBH_T::HcRhPortStatus: PES Position      */
+#define USBH_HcRhPortStatus_PES_Msk      (0x1ul << USBH_HcRhPortStatus_PES_Pos)            /*!< USBH_T::HcRhPortStatus: PES Mask          */
+
+#define USBH_HcRhPortStatus_PSS_Pos      (2)                                               /*!< USBH_T::HcRhPortStatus: PSS Position      */
+#define USBH_HcRhPortStatus_PSS_Msk      (0x1ul << USBH_HcRhPortStatus_PSS_Pos)            /*!< USBH_T::HcRhPortStatus: PSS Mask          */
+
+#define USBH_HcRhPortStatus_POCI_Pos     (3)                                               /*!< USBH_T::HcRhPortStatus: POCI Position     */
+#define USBH_HcRhPortStatus_POCI_Msk     (0x1ul << USBH_HcRhPortStatus_POCI_Pos)           /*!< USBH_T::HcRhPortStatus: POCI Mask         */
+
+#define USBH_HcRhPortStatus_PRS_Pos      (4)                                               /*!< USBH_T::HcRhPortStatus: PRS Position      */
+#define USBH_HcRhPortStatus_PRS_Msk      (0x1ul << USBH_HcRhPortStatus_PRS_Pos)            /*!< USBH_T::HcRhPortStatus: PRS Mask          */
+
+#define USBH_HcRhPortStatus_PPS_Pos      (8)                                               /*!< USBH_T::HcRhPortStatus: PPS Position      */
+#define USBH_HcRhPortStatus_PPS_Msk      (0x1ul << USBH_HcRhPortStatus_PPS_Pos)            /*!< USBH_T::HcRhPortStatus: PPS Mask          */
+
+#define USBH_HcRhPortStatus_LSDA_Pos     (9)                                               /*!< USBH_T::HcRhPortStatus: LSDA Position     */
+#define USBH_HcRhPortStatus_LSDA_Msk     (0x1ul << USBH_HcRhPortStatus_LSDA_Pos)           /*!< USBH_T::HcRhPortStatus: LSDA Mask         */
+
+#define USBH_HcRhPortStatus_CSC_Pos      (16)                                              /*!< USBH_T::HcRhPortStatus: CSC Position      */
+#define USBH_HcRhPortStatus_CSC_Msk      (0x1ul << USBH_HcRhPortStatus_CSC_Pos)            /*!< USBH_T::HcRhPortStatus: CSC Mask          */
+
+#define USBH_HcRhPortStatus_PESC_Pos     (17)                                              /*!< USBH_T::HcRhPortStatus: PESC Position     */
+#define USBH_HcRhPortStatus_PESC_Msk     (0x1ul << USBH_HcRhPortStatus_PESC_Pos)           /*!< USBH_T::HcRhPortStatus: PESC Mask         */
+
+#define USBH_HcRhPortStatus_PSSC_Pos     (18)                                              /*!< USBH_T::HcRhPortStatus: PSSC Position     */
+#define USBH_HcRhPortStatus_PSSC_Msk     (0x1ul << USBH_HcRhPortStatus_PSSC_Pos)           /*!< USBH_T::HcRhPortStatus: PSSC Mask         */
+
+#define USBH_HcRhPortStatus_OCIC_Pos     (19)                                              /*!< USBH_T::HcRhPortStatus: OCIC Position     */
+#define USBH_HcRhPortStatus_OCIC_Msk     (0x1ul << USBH_HcRhPortStatus_OCIC_Pos)           /*!< USBH_T::HcRhPortStatus: OCIC Mask         */
+
+#define USBH_HcRhPortStatus_PRSC_Pos     (20)                                              /*!< USBH_T::HcRhPortStatus: PRSC Position     */
+#define USBH_HcRhPortStatus_PRSC_Msk     (0x1ul << USBH_HcRhPortStatus_PRSC_Pos)           /*!< USBH_T::HcRhPortStatus: PRSC Mask         */
+
+#define USBH_HcPhyControl_STBYEN_Pos     (27)                                              /*!< USBH_T::HcPhyControl: STBYEN Position     */
+#define USBH_HcPhyControl_STBYEN_Msk     (0x1ul << USBH_HcPhyControl_STBYEN_Pos)           /*!< USBH_T::HcPhyControl: STBYEN Mask         */
+
+#define USBH_HcMiscControl_ABORT_Pos     (1)                                               /*!< USBH_T::HcMiscControl: ABORT Position     */
+#define USBH_HcMiscControl_ABORT_Msk     (0x1ul << USBH_HcMiscControl_ABORT_Pos)           /*!< USBH_T::HcMiscControl: ABORT Mask         */
+
+#define USBH_HcMiscControl_OCAL_Pos      (3)                                               /*!< USBH_T::HcMiscControl: OCAL Position      */
+#define USBH_HcMiscControl_OCAL_Msk      (0x1ul << USBH_HcMiscControl_OCAL_Pos)            /*!< USBH_T::HcMiscControl: OCAL Mask          */
+
+#define USBH_HcMiscControl_DPRT1_Pos     (16)                                              /*!< USBH_T::HcMiscControl: DPRT1 Position     */
+#define USBH_HcMiscControl_DPRT1_Msk     (0x1ul << USBH_HcMiscControl_DPRT1_Pos)           /*!< USBH_T::HcMiscControl: DPRT1 Mask         */
+
+/**@}*/ /* USBH_CONST */
+/**@}*/ /* end of USBH register group */
+
+
+/*---------------------- Watch Dog Timer Controller -------------------------*/
+/**
+    @addtogroup WDT Watch Dog Timer Controller(WDT)
+    Memory Mapped Structure for WDT Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var WDT_T::CTL
+ * Offset: 0x00  WDT Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |RSTCNT    |Reset WDT Up Counter (Write Protect)
+ * |        |          |0 = No effect.
+ * |        |          |1 = Reset the internal 18-bit WDT up counter value.
+ * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |        |          |Note2: This bit will be automatically cleared by hardware.
+ * |[1]     |RSTEN     |WDT Time-Out Reset Enable Control (Write Protect)
+ * |        |          |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
+ * |        |          |0 = WDT time-out reset function Disabled.
+ * |        |          |1 = WDT time-out reset function Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2]     |RSTF      |WDT Time-Out Reset Flag
+ * |        |          |This bit indicates the system has been reset by WDT time-out reset or not.
+ * |        |          |0 = WDT time-out reset did not occur.
+ * |        |          |1 = WDT time-out reset occurred.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * |[3]     |IF        |WDT Time-Out Interrupt Flag
+ * |        |          |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
+ * |        |          |0 = WDT time-out interrupt did not occur.
+ * |        |          |1 = WDT time-out interrupt occurred.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * |[4]     |WKEN      |WDT Time-Out Wake-Up Function Control (Write Protect)
+ * |        |          |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
+ * |        |          |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
+ * |        |          |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
+ * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |        |          |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
+ * |[5]     |WKF       |WDT Time-Out Wake-Up Flag
+ * |        |          |This bit indicates the interrupt wake-up flag status of WDT
+ * |        |          |0 = WDT does not cause chip wake-up.
+ * |        |          |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
+ * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |        |          |Note2: This bit is cleared by writing 1 to it.
+ * |[6]     |INTEN     |WDT Time-Out Interrupt Enable Control (Write Protect)
+ * |        |          |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
+ * |        |          |0 = WDT time-out interrupt Disabled.
+ * |        |          |1 = WDT time-out interrupt Enabled.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7]     |WDTEN     |WDT Enable Control (Write Protect)
+ * |        |          |0 = WDT Disabled (This action will reset the internal up counter value).
+ * |        |          |1 = WDT Enabled.
+ * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |        |          |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
+ * |[10:8]  |TOUTSEL   |WDT Time-Out Interval Selection (Write Protect)
+ * |        |          |These three bits select the time-out interval period for the WDT.
+ * |        |          |000 = (2^4)*TWDT.
+ * |        |          |001 = (2^6)*TWDT.
+ * |        |          |010 = (2^8)*TWDT.
+ * |        |          |011 = (2^10)*TWDT.
+ * |        |          |100 = (2^12)*TWDT.
+ * |        |          |101 = (2^14)*TWDT.
+ * |        |          |110 = (2^16)*TWDT.
+ * |        |          |111 = (2^18)*TWDT.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable Control (Write Protect)
+ * |        |          |0 = ICE debug mode acknowledgement affects WDT counting.
+ * |        |          |WDT up counter will be held while CPU is held by ICE.
+ * |        |          |1 = ICE debug mode acknowledgement Disabled.
+ * |        |          |WDT up counter will keep going no matter CPU is held by ICE or not.
+ * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var WDT_T::ALTCTL
+ * Offset: 0x04  WDT Alternative Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[1:0]   |RSTDSEL   |WDT Reset Delay Selection (Write Protect)
+ * |        |          |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened.
+ * |        |          |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
+ * |        |          |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
+ * |        |          |01 = WDT Reset Delay Period is 130 * WDT_CLK.
+ * |        |          |10 = WDT Reset Delay Period is 18 * WDT_CLK.
+ * |        |          |11 = WDT Reset Delay Period is 3 * WDT_CLK.
+ * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |        |          |Note2: This register will be reset to 0 if WDT time-out reset happened.
+ */
+
+    __IO uint32_t CTL;           /* Offset: 0x00  WDT Control Register                                               */
+    __IO uint32_t ALTCTL;        /* Offset: 0x04  WDT Alternative Control Register                                   */
+
+} WDT_T;
+
+
+
+/**
+    @addtogroup WDT_CONST WDT Bit Field Definition
+    Constant Definitions for WDT Controller
+@{ */
+
+#define WDT_CTL_RSTCNT_Pos               (0)                                               /*!< WDT_T::CTL: RSTCNT Position               */
+#define WDT_CTL_RSTCNT_Msk               (0x1ul << WDT_CTL_RSTCNT_Pos)                     /*!< WDT_T::CTL: RSTCNT Mask                   */
+
+#define WDT_CTL_RSTEN_Pos                (1)                                               /*!< WDT_T::CTL: RSTEN Position                */
+#define WDT_CTL_RSTEN_Msk                (0x1ul << WDT_CTL_RSTEN_Pos)                      /*!< WDT_T::CTL: RSTEN Mask                    */
+
+#define WDT_CTL_RSTF_Pos                 (2)                                               /*!< WDT_T::CTL: RSTF Position                 */
+#define WDT_CTL_RSTF_Msk                 (0x1ul << WDT_CTL_RSTF_Pos)                       /*!< WDT_T::CTL: RSTF Mask                     */
+
+#define WDT_CTL_IF_Pos                   (3)                                               /*!< WDT_T::CTL: IF Position                   */
+#define WDT_CTL_IF_Msk                   (0x1ul << WDT_CTL_IF_Pos)                         /*!< WDT_T::CTL: IF Mask                       */
+
+#define WDT_CTL_WKEN_Pos                 (4)                                               /*!< WDT_T::CTL: WKEN Position                 */
+#define WDT_CTL_WKEN_Msk                 (0x1ul << WDT_CTL_WKEN_Pos)                       /*!< WDT_T::CTL: WKEN Mask                     */
+
+#define WDT_CTL_WKF_Pos                  (5)                                               /*!< WDT_T::CTL: WKF Position                  */
+#define WDT_CTL_WKF_Msk                  (0x1ul << WDT_CTL_WKF_Pos)                        /*!< WDT_T::CTL: WKF Mask                      */
+
+#define WDT_CTL_INTEN_Pos                (6)                                               /*!< WDT_T::CTL: INTEN Position                */
+#define WDT_CTL_INTEN_Msk                (0x1ul << WDT_CTL_INTEN_Pos)                      /*!< WDT_T::CTL: INTEN Mask                    */
+
+#define WDT_CTL_WDTEN_Pos                (7)                                               /*!< WDT_T::CTL: WDTEN Position                */
+#define WDT_CTL_WDTEN_Msk                (0x1ul << WDT_CTL_WDTEN_Pos)                      /*!< WDT_T::CTL: WDTEN Mask                    */
+
+#define WDT_CTL_TOUTSEL_Pos              (8)                                               /*!< WDT_T::CTL: TOUTSEL Position              */
+#define WDT_CTL_TOUTSEL_Msk              (0x7ul << WDT_CTL_TOUTSEL_Pos)                    /*!< WDT_T::CTL: TOUTSEL Mask                  */
+
+#define WDT_CTL_ICEDEBUG_Pos             (31)                                              /*!< WDT_T::CTL: ICEDEBUG Position             */
+#define WDT_CTL_ICEDEBUG_Msk             (0x1ul << WDT_CTL_ICEDEBUG_Pos)                   /*!< WDT_T::CTL: ICEDEBUG Mask                 */
+
+#define WDT_ALTCTL_RSTDSEL_Pos           (0)                                               /*!< WDT_T::ALTCTL: RSTDSEL Position           */
+#define WDT_ALTCTL_RSTDSEL_Msk           (0x3ul << WDT_ALTCTL_RSTDSEL_Pos)                 /*!< WDT_T::ALTCTL: RSTDSEL Mask               */
+
+/**@}*/ /* WDT_CONST */
+/**@}*/ /* end of WDT register group */
+
+
+/*---------------------- Window Watchdog Timer -------------------------*/
+/**
+    @addtogroup WWDT Window Watchdog Timer(WWDT)
+    Memory Mapped Structure for WWDT Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var WWDT_T::RLDCNT
+ * Offset: 0x00  WWDT Reload Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[31:0]  |WWDT_RLDCNT|WWDT Reload Counter Register
+ * |        |          |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
+ * |        |          |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]).
+ * |        |          |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately.
+ * @var WWDT_T::CTL
+ * Offset: 0x04  WWDT Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |WWDTEN    |WWDT Enable Control Bit
+ * |        |          |Set this bit to enable WWDT counter counting.
+ * |        |          |0 = WWDT counter is stopped.
+ * |        |          |1 = WWDT counter is starting counting.
+ * |[1]     |INTEN     |WWDT Interrupt Enable Control Bit
+ * |        |          |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
+ * |        |          |0 = WWDT counter compare match interrupt Disabled.
+ * |        |          |1 = WWDT counter compare match interrupt Enabled.
+ * |[11:8]  |PSCSEL    |WWDT Counter Prescale Period Selection
+ * |        |          |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT.
+ * |        |          |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT.
+ * |        |          |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT.
+ * |        |          |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT.
+ * |        |          |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT.
+ * |        |          |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT.
+ * |        |          |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT.
+ * |        |          |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT.
+ * |        |          |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT.
+ * |        |          |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT.
+ * |        |          |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT.
+ * |        |          |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT.
+ * |        |          |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT.
+ * |        |          |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT.
+ * |        |          |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT.
+ * |        |          |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT.
+ * |[21:16] |CMPDAT    |WWDT Window Compare Register
+ * |        |          |Set this register to adjust the valid reload window.
+ * |        |          |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
+ * |        |          |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
+ * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable Control
+ * |        |          |0 = ICE debug mode acknowledgement effects WWDT counting.
+ * |        |          |WWDT down counter will be held while CPU is held by ICE.
+ * |        |          |1 = ICE debug mode acknowledgement Disabled.
+ * |        |          |WWDT down counter will keep going no matter CPU is held by ICE or not.
+ * @var WWDT_T::STATUS
+ * Offset: 0x08  WWDT Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[0]     |WWDTIF    |WWDT Compare Match Interrupt Flag
+ * |        |          |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
+ * |        |          |0 = No effect.
+ * |        |          |1 = WWDT counter value matches CMPDAT.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * |[1]     |WWDTRF    |WWDT Timer-Out Reset Flag
+ * |        |          |This bit indicates the system has been reset by WWDT time-out reset or not.
+ * |        |          |0 = WWDT time-out reset did not occur.
+ * |        |          |1 = WWDT time-out reset occurred.
+ * |        |          |Note: This bit is cleared by writing 1 to it.
+ * @var WWDT_T::CNT
+ * Offset: 0x0C  WWDT Counter Value Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits    |Field     |Descriptions
+ * | :----: | :----:   | :---- |
+ * |[5:0]   |CNTDAT    |WWDT Counter Value
+ * |        |          |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
+ */
+
+    __O  uint32_t RLDCNT;        /* Offset: 0x00  WWDT Reload Counter Register                                       */
+    __IO uint32_t CTL;           /* Offset: 0x04  WWDT Control Register                                              */
+    __IO uint32_t STATUS;        /* Offset: 0x08  WWDT Status Register                                               */
+    __I  uint32_t CNT;           /* Offset: 0x0C  WWDT Counter Value Register                                        */
+
+} WWDT_T;
+
+
+
+/**
+    @addtogroup WWDT_CONST WWDT Bit Field Definition
+    Constant Definitions for WWDT Controller
+@{ */
+
+#define WWDT_RLDCNT_WWDT_RLDCNT_Pos      (0)                                               /*!< WWDT_T::RLDCNT: WWDT_RLDCNT Position      */
+#define WWDT_RLDCNT_WWDT_RLDCNT_Msk      (0xfffffffful << WWDT_RLDCNT_WWDT_RLDCNT_Pos)     /*!< WWDT_T::RLDCNT: WWDT_RLDCNT Mask          */
+
+#define WWDT_CTL_WWDTEN_Pos              (0)                                               /*!< WWDT_T::CTL: WWDTEN Position              */
+#define WWDT_CTL_WWDTEN_Msk              (0x1ul << WWDT_CTL_WWDTEN_Pos)                    /*!< WWDT_T::CTL: WWDTEN Mask                  */
+
+#define WWDT_CTL_INTEN_Pos               (1)                                               /*!< WWDT_T::CTL: INTEN Position               */
+#define WWDT_CTL_INTEN_Msk               (0x1ul << WWDT_CTL_INTEN_Pos)                     /*!< WWDT_T::CTL: INTEN Mask                   */
+
+#define WWDT_CTL_PSCSEL_Pos              (8)                                               /*!< WWDT_T::CTL: PSCSEL Position              */
+#define WWDT_CTL_PSCSEL_Msk              (0xful << WWDT_CTL_PSCSEL_Pos)                    /*!< WWDT_T::CTL: PSCSEL Mask                  */
+
+#define WWDT_CTL_CMPDAT_Pos              (16)                                              /*!< WWDT_T::CTL: CMPDAT Position              */
+#define WWDT_CTL_CMPDAT_Msk              (0x3ful << WWDT_CTL_CMPDAT_Pos)                   /*!< WWDT_T::CTL: CMPDAT Mask                  */
+
+#define WWDT_CTL_ICEDEBUG_Pos            (31)                                              /*!< WWDT_T::CTL: ICEDEBUG Position            */
+#define WWDT_CTL_ICEDEBUG_Msk            (0x1ul << WWDT_CTL_ICEDEBUG_Pos)                  /*!< WWDT_T::CTL: ICEDEBUG Mask                */
+
+#define WWDT_STATUS_WWDTIF_Pos           (0)                                               /*!< WWDT_T::STATUS: WWDTIF Position           */
+#define WWDT_STATUS_WWDTIF_Msk           (0x1ul << WWDT_STATUS_WWDTIF_Pos)                 /*!< WWDT_T::STATUS: WWDTIF Mask               */
+
+#define WWDT_STATUS_WWDTRF_Pos           (1)                                               /*!< WWDT_T::STATUS: WWDTRF Position           */
+#define WWDT_STATUS_WWDTRF_Msk           (0x1ul << WWDT_STATUS_WWDTRF_Pos)                 /*!< WWDT_T::STATUS: WWDTRF Mask               */
+
+#define WWDT_CNT_CNTDAT_Pos              (0)                                               /*!< WWDT_T::CNT: CNTDAT Position              */
+#define WWDT_CNT_CNTDAT_Msk              (0x3ful << WWDT_CNT_CNTDAT_Pos)                   /*!< WWDT_T::CNT: CNTDAT Mask                  */
+
+/**@}*/ /* WWDT_CONST */
+/**@}*/ /* end of WWDT register group */
+
+
+/**@}*/ /* end of REGISTER group */
+
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/** @addtogroup MemoryMap Memory Mapping
+  @{
+*/
+
+/* Peripheral and SRAM base address */
+#define SRAM_BASE            (0x20000000UL)                              /*!< (SRAM      ) Base Address */
+#define PERIPH_BASE          (0x40000000UL)                              /*!< (Peripheral) Base Address */
+
+
+/* Peripheral memory map */
+#define AHBPERIPH_BASE       PERIPH_BASE
+#define APBPERIPH_BASE       (PERIPH_BASE + 0x00040000)
+
+/*!< AHB peripherals */
+#define GCR_BASE             (AHBPERIPH_BASE + 0x00000)               
+#define CLK_BASE             (AHBPERIPH_BASE + 0x00200)
+#define INT_BASE             (AHBPERIPH_BASE + 0x00300)
+#define GPIO_BASE            (AHBPERIPH_BASE + 0x04000)
+#define GPIOA_BASE           (AHBPERIPH_BASE + 0x04000)
+#define GPIOB_BASE           (AHBPERIPH_BASE + 0x04040)
+#define GPIOC_BASE           (AHBPERIPH_BASE + 0x04080)
+#define GPIOD_BASE           (AHBPERIPH_BASE + 0x040C0)
+#define GPIOE_BASE           (AHBPERIPH_BASE + 0x04100)
+#define GPIOF_BASE           (AHBPERIPH_BASE + 0x04140)
+#define GPIO_DBCTL_BASE      (AHBPERIPH_BASE + 0x04440)
+#define GPIO_PIN_DATA_BASE   (AHBPERIPH_BASE + 0x04800)
+#define PDMA_BASE            (AHBPERIPH_BASE + 0x08000)
+#define USBH_BASE            (AHBPERIPH_BASE + 0x09000)
+#define FMC_BASE             (AHBPERIPH_BASE + 0x0C000)
+#define EBI_BASE             (AHBPERIPH_BASE + 0x10000)
+#define CRC_BASE             (AHBPERIPH_BASE + 0x31000)
+
+/*!< APB0 peripherals */
+#define WDT_BASE             (APBPERIPH_BASE + 0x00000)
+#define WWDT_BASE            (APBPERIPH_BASE + 0x00100)
+#define TMR01_BASE           (APBPERIPH_BASE + 0x10000)
+#define PWM0_BASE            (APBPERIPH_BASE + 0x18000)
+#define SPI0_BASE            (APBPERIPH_BASE + 0x20000)
+#define SPI2_BASE            (APBPERIPH_BASE + 0x22000)
+#define UART0_BASE           (APBPERIPH_BASE + 0x30000)
+#define UART2_BASE           (APBPERIPH_BASE + 0x32000)
+#define I2C0_BASE            (APBPERIPH_BASE + 0x40000)
+#define SC0_BASE             (APBPERIPH_BASE + 0x50000)
+#define CAN0_BASE            (APBPERIPH_BASE + 0x60000)
+#define USBD_BASE            (APBPERIPH_BASE + 0x80000)
+#define TK_BASE              (APBPERIPH_BASE + 0xA2000)
+
+/*!< APB1 peripherals */
+#define RTC_BASE             (APBPERIPH_BASE + 0x01000)
+#define EADC0_BASE           (APBPERIPH_BASE + 0x03000)
+#define ACMP01_BASE          (APBPERIPH_BASE + 0x05000)
+#define DAC_BASE             (APBPERIPH_BASE + 0x07000)
+#define OTG_BASE             (APBPERIPH_BASE + 0x0D000)
+#define TMR23_BASE           (APBPERIPH_BASE + 0x11000)
+#define PWM1_BASE            (APBPERIPH_BASE + 0x19000)
+#define SPI1_BASE            (APBPERIPH_BASE + 0x21000)
+#define UART1_BASE           (APBPERIPH_BASE + 0x31000)
+#define UART3_BASE           (APBPERIPH_BASE + 0x33000)
+#define I2C1_BASE            (APBPERIPH_BASE + 0x41000)
+/*@}*/ /* end of group MemoryMap */
+
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+/** @addtogroup PeripheralDecl Peripheral Declaration
+  @{
+*/
+
+
+#define SYS                  ((SYS_T *)   GCR_BASE)
+#define SYSINT               ((SYS_INT_T *) INT_BASE)                   
+#define CLK                  ((CLK_T *)   CLK_BASE)
+#define PA                   ((GPIO_T *)  GPIOA_BASE)
+#define PB                   ((GPIO_T *)  GPIOB_BASE)
+#define PC                   ((GPIO_T *)  GPIOC_BASE)
+#define PD                   ((GPIO_T *)  GPIOD_BASE)
+#define PE                   ((GPIO_T *)  GPIOE_BASE)
+#define PF                   ((GPIO_T *)  GPIOF_BASE)
+#define GPIO                 ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
+#define PDMA                 ((PDMA_T *)  PDMA_BASE)
+#define USBH                 ((USBH_T *)  USBH_BASE)
+#define FMC                  ((FMC_T *)   FMC_BASE)
+#define EBI                  ((EBI_T *)   EBI_BASE)
+#define CRC                  ((CRC_T *)   CRC_BASE)
+
+#define WDT                  ((WDT_T *)   WDT_BASE)
+#define WWDT                 ((WWDT_T *)  WWDT_BASE)
+#define RTC                  ((RTC_T *)   RTC_BASE)
+#define EADC                  ((EADC_T *)   EADC0_BASE)
+#define ACMP01               ((ACMP_T *)  ACMP01_BASE)
+
+#define USBD                 ((USBD_T *)  USBD_BASE)
+#define OTG                  ((OTG_T *)   OTG_BASE)
+#define TIMER0               ((TIMER_T *) TMR01_BASE)
+#define TIMER1               ((TIMER_T *) (TMR01_BASE + 0x20))
+#define TIMER2               ((TIMER_T *) TMR23_BASE)
+#define TIMER3               ((TIMER_T *) (TMR23_BASE+ 0x20))
+#define PWM0                 ((PWM_T *)   PWM0_BASE)
+#define PWM1                 ((PWM_T *)   PWM1_BASE)
+#define DAC                  ((DAC_T *)   DAC_BASE)
+#define SPI0                 ((SPI_T *)   SPI0_BASE)
+#define SPI1                 ((SPI_T *)   SPI1_BASE)
+#define SPI2                 ((SPI_T *)   SPI2_BASE)
+#define UART0                ((UART_T *)  UART0_BASE)
+#define UART1                ((UART_T *)  UART1_BASE)
+#define UART2                ((UART_T *)  UART2_BASE)
+#define UART3                ((UART_T *)  UART3_BASE)
+#define I2C0                 ((I2C_T *)   I2C0_BASE)
+#define I2C1                 ((I2C_T *)   I2C1_BASE)
+#define SC0                  ((SC_T *)    SC0_BASE)
+#define CAN0                 ((CAN_T *)   CAN0_BASE)
+#define TK                   ((TK_T *)   TK_BASE)
+
+/* One Bit Mask Definitions */
+#define BIT0    0x00000001
+#define BIT1    0x00000002
+#define BIT2    0x00000004
+#define BIT3    0x00000008
+#define BIT4    0x00000010
+#define BIT5    0x00000020
+#define BIT6    0x00000040
+#define BIT7    0x00000080
+#define BIT8    0x00000100
+#define BIT9    0x00000200
+#define BIT10   0x00000400
+#define BIT11   0x00000800
+#define BIT12   0x00001000
+#define BIT13   0x00002000
+#define BIT14   0x00004000
+#define BIT15   0x00008000
+#define BIT16   0x00010000
+#define BIT17   0x00020000
+#define BIT18   0x00040000
+#define BIT19   0x00080000
+#define BIT20   0x00100000
+#define BIT21   0x00200000
+#define BIT22   0x00400000
+#define BIT23   0x00800000
+#define BIT24   0x01000000
+#define BIT25   0x02000000
+#define BIT26   0x04000000
+#define BIT27   0x08000000
+#define BIT28   0x10000000
+#define BIT29   0x20000000
+#define BIT30   0x40000000
+#define BIT31   0x80000000
+
+/* Byte Mask Definitions */
+#define BYTE0_Msk               (0x000000FF)
+#define BYTE1_Msk               (0x0000FF00)
+#define BYTE2_Msk               (0x00FF0000)
+#define BYTE3_Msk               (0xFF000000)
+
+#define _GET_BYTE0(u32Param)    (((u32Param) & BYTE0_Msk)      )  /*!< Extract Byte 0 (Bit  0~ 7) from parameter u32Param */
+#define _GET_BYTE1(u32Param)    (((u32Param) & BYTE1_Msk) >>  8)  /*!< Extract Byte 1 (Bit  8~15) from parameter u32Param */
+#define _GET_BYTE2(u32Param)    (((u32Param) & BYTE2_Msk) >> 16)  /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
+#define _GET_BYTE3(u32Param)    (((u32Param) & BYTE3_Msk) >> 24)  /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
+
+#ifndef TRUE
+# define TRUE 1
+#endif
+#ifndef FALSE
+# define FALSE 0
+#endif
+
+#ifndef NULL
+#define NULL        0
+#endif
+
+#include "m451_sys.h"
+#include "m451_clk.h"
+#include "m451_gpio.h"
+#include "m451_i2c.h"
+#include "m451_crc.h"
+#include "m451_ebi.h"
+#include "m451_rtc.h"
+#include "m451_timer.h"
+#include "m451_wdt.h"
+#include "m451_wwdt.h"
+#include "m451_spi.h"
+#include "m451_sc.h"
+#include "m451_scuart.h"
+#include "m451_acmp.h"
+#include "m451_eadc.h"
+#include "m451_dac.h"
+#include "m451_can.h"
+#include "m451_usbd.h"
+#include "m451_fmc.h"
+#include "m451_uart.h"
+#include "m451_pwm.h"
+#include "m451_pdma.h"
+#include "m451_tk.h"
+#include "m451_otg.h"
+
+typedef volatile unsigned char  vu8;
+typedef volatile unsigned long  vu32;
+typedef volatile unsigned short vu16;
+#define M8(adr)  (*((vu8  *) (adr)))
+#define M16(adr) (*((vu16 *) (adr)))
+#define M32(adr) (*((vu32 *) (adr)))
+
+#define outpw(port,value)   (*((volatile unsigned int *)(port))=(value))
+#define inpw(port)          (*((volatile unsigned int *)(port)))
+#define outpb(port,value)   (*((volatile unsigned char *)(port))=(value))
+#define inpb(port)          (*((volatile unsigned char *)(port)))
+#define outps(port,value)   (*((volatile unsigned short *)(port))=(value))
+#define inps(port)          (*((volatile unsigned short *)(port)))
+
+#define outp32(port,value)  (*((volatile unsigned int *)(port))=(value))
+#define inp32(port)         (*((volatile unsigned int *)(port)))
+#define outp8(port,value)   (*((volatile unsigned char *)(port))=(value))
+#define inp8(port)          (*((volatile unsigned char *)(port)))
+#define outp16(port,value)  (*((volatile unsigned short *)(port))=(value))
+#define inp16(port)         (*((volatile unsigned short *)(port)))
+
+/*@}*/ /* end of group PeripheralDecl */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __M451SERIES_H__ */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
+
+
+
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_acmp.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_acmp.c
new file mode 100644
index 00000000000..6b5edd12906
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_acmp.c
@@ -0,0 +1,84 @@
+/**************************************************************************//**
+ * @file     acmp.c
+ * @version  V3.00
+ * $Revision: 4 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series Analog Comparator(ACMP) driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup ACMP_Driver ACMP Driver
+  @{
+*/
+
+
+/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief  Configure the specified ACMP module
+  *
+  * @param[in]  Acmp The pointer of the specified ACMP module
+  * @param[in]  u32ChNum Comparator number.
+  * @param[in]  u32NegSrc Comparator negative input selection.  Including:
+  *                  - \ref ACMP_CTL_NEGSEL_PIN
+  *                  - \ref ACMP_CTL_NEGSEL_CRV
+  *                  - \ref ACMP_CTL_NEGSEL_VBG
+  *                  - \ref ACMP_CTL_NEGSEL_DAC
+  * @param[in]  u32HysteresisEn The hysteresis function option. Including:
+  *                  - \ref ACMP_CTL_HYSTERESIS_ENABLE
+  *                  - \ref ACMP_CTL_HYSTERESIS_DISABLE
+  *
+  * @return     None
+  *
+  * @details    Configure hysteresis function, select the source of negative input and enable analog comparator.
+  */
+void ACMP_Open(ACMP_T *Acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn)
+{
+    Acmp->CTL[u32ChNum] = (Acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSEN_Msk))) | (u32NegSrc | u32HysteresisEn | ACMP_CTL_ACMPEN_Msk);
+}
+
+/**
+  * @brief  Close analog comparator
+  *
+  * @param[in]  Acmp The pointer of the specified ACMP module
+  * @param[in]  u32ChNum Comparator number.
+  *
+  * @return     None
+  *
+  * @details  This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
+  */
+void ACMP_Close(ACMP_T *Acmp, uint32_t u32ChNum)
+{
+    Acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);
+}
+
+
+
+/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group ACMP_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
+
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_acmp.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_acmp.h
new file mode 100644
index 00000000000..67857f42d1a
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_acmp.h
@@ -0,0 +1,333 @@
+/**************************************************************************//**
+ * @file     ACMP.h
+ * @version  V0.10
+ * $Revision: 10 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 Series ACMP Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __ACMP_H__
+#define __ACMP_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup ACMP_Driver ACMP Driver
+  @{
+*/
+
+
+/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
+  @{
+*/
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ACMP_CTL constant definitions                                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ACMP_CTL_FILTSEL_OFF         (0UL << 13) /*!< ACMP_CTL setting for filter function disabled. */
+#define ACMP_CTL_FILTSEL_1PCLK       (1UL << 13) /*!< ACMP_CTL setting for 1 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_2PCLK       (2UL << 13) /*!< ACMP_CTL setting for 2 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_4PCLK       (3UL << 13) /*!< ACMP_CTL setting for 4 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_8PCLK       (4UL << 13) /*!< ACMP_CTL setting for 8 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_16PCLK      (5UL << 13) /*!< ACMP_CTL setting for 16 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_32PCLK      (6UL << 13) /*!< ACMP_CTL setting for 32 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_64PCLK      (7UL << 13) /*!< ACMP_CTL setting for 64 PCLK filter count. */
+#define ACMP_CTL_INTPOL_RF           (0UL << 8)  /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. */
+#define ACMP_CTL_INTPOL_R            (1UL << 8)  /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. */
+#define ACMP_CTL_INTPOL_F            (2UL << 8)  /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. */
+#define ACMP_CTL_POSSEL_P0           (0UL << 6)  /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. */
+#define ACMP_CTL_POSSEL_P1           (1UL << 6)  /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. */
+#define ACMP_CTL_POSSEL_P2           (2UL << 6)  /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. */
+#define ACMP_CTL_POSSEL_P3           (3UL << 6)  /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. */
+#define ACMP_CTL_NEGSEL_PIN          (0UL << 4)  /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. */
+#define ACMP_CTL_NEGSEL_CRV          (1UL << 4)  /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. */
+#define ACMP_CTL_NEGSEL_VBG          (2UL << 4)  /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. */
+#define ACMP_CTL_NEGSEL_DAC          (3UL << 4)  /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. */
+#define ACMP_CTL_HYSTERESIS_ENABLE   (1UL << 2)  /*!< ACMP_CTL setting for enabling the hysteresis function. */
+#define ACMP_CTL_HYSTERESIS_DISABLE  (0UL << 2)  /*!< ACMP_CTL setting for disabling the hysteresis function. */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ACMP_VREF constant definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ACMP_VREF_CRVSSEL_VDDA       (0UL << 6)  /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage */
+#define ACMP_VREF_CRVSSEL_INTVREF    (1UL << 6)  /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage */
+
+
+/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Define Macros and functions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+  * @brief This macro is used to enable output inverse function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function.
+  */
+#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_ACMPOINV_Msk)
+
+/**
+  * @brief This macro is used to disable output inverse function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function.
+  */
+#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_ACMPOINV_Msk)
+
+/**
+  * @brief This macro is used to select ACMP negative input source
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32Src is comparator negative input selection. Including:
+  *                  - \ref ACMP_CTL_NEGSEL_PIN
+  *                  - \ref ACMP_CTL_NEGSEL_CRV
+  *                  - \ref ACMP_CTL_NEGSEL_VBG
+  *                  - \ref ACMP_CTL_NEGSEL_DAC
+  * @return None
+  * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input.
+  */
+#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)%2] = ((acmp)->CTL[(u32ChNum)%2] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src))
+
+/**
+  * @brief This macro is used to enable hysteresis function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set HYSEN bit of ACMP_CTL register to enable hysteresis function.
+  */
+#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_HYSEN_Msk)
+
+/**
+  * @brief This macro is used to disable hysteresis function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear HYSEN bit of ACMP_CTL register to disable hysteresis function.
+  */
+#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_HYSEN_Msk)
+
+/**
+  * @brief This macro is used to enable interrupt
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function.
+  *          If wake-up function is enabled, the wake-up interrupt will be enabled as well.
+  */
+#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_ACMPIE_Msk)
+
+/**
+  * @brief This macro is used to disable interrupt
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function.
+  */
+#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_ACMPIE_Msk)
+
+/**
+  * @brief This macro is used to enable ACMP
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator.
+  */
+#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_ACMPEN_Msk)
+
+/**
+  * @brief This macro is used to disable ACMP
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
+  */
+#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_ACMPEN_Msk)
+
+/**
+  * @brief This macro is used to get ACMP output value
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return  ACMP output value
+  * @details This macro will return the ACMP output value.
+  */
+#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum)%2)))?1:0)
+
+/**
+  * @brief This macro is used to get ACMP interrupt flag
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return   ACMP interrupt occurred (1) or not (0)
+  * @details This macro will return the ACMP interrupt flag.
+  */
+#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)%2)))?1:0)
+
+/**
+  * @brief This macro is used to clear ACMP interrupt flag
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return   None
+  * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag.
+  */
+#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)%2)))
+
+/**
+  * @brief This macro is used to clear ACMP wake-up interrupt flag
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return   None
+  * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag.
+  */
+#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum)%2)))
+
+/**
+  * @brief This macro is used to enable ACMP wake-up function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function.
+  */
+#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_WKEN_Msk)
+
+/**
+  * @brief This macro is used to disable ACMP wake-up function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function.
+  */
+#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_WKEN_Msk)
+
+/**
+  * @brief This macro is used to select ACMP positive input pin
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32Pin Comparator positive pin selection. Including:
+  *                  - \ref ACMP_CTL_POSSEL_P0
+  *                  - \ref ACMP_CTL_POSSEL_P1
+  *                  - \ref ACMP_CTL_POSSEL_P2
+  *                  - \ref ACMP_CTL_POSSEL_P3
+  * @return None
+  * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin.
+  */
+#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)%2] = ((acmp)->CTL[(u32ChNum)%2] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
+
+/**
+  * @brief This macro is used to enable ACMP filter function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function.
+  */
+#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_OUTSEL_Msk)
+
+/**
+  * @brief This macro is used to disable ACMP filter function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function.
+  */
+#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_OUTSEL_Msk)
+
+/**
+  * @brief This macro is used to set ACMP filter function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32Cnt is comparator filter count setting.
+  *                  - \ref ACMP_CTL_FILTSEL_OFF
+  *                  - \ref ACMP_CTL_FILTSEL_1PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_2PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_4PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_8PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_16PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_32PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_64PCLK
+  * @return None
+  * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]).
+  */
+#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)%2] = ((acmp)->CTL[(u32ChNum)%2] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))
+
+/**
+  * @brief This macro is used to select comparator reference voltage
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32Level  The comparator reference voltage setting.
+  *             The formula is:
+  *                       comparator reference voltage = CRV source voltage x (1/6 + u32Level/24)
+  *             The range of u32Level is 0 ~ 15.
+  * @return   None
+  * @details  When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]).
+  */
+#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<<ACMP_VREF_CRVCTL_Pos))
+
+/**
+  * @brief This macro is used to select the source of CRV
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32Src is the source of CRV. Including:
+  *                  - \ref ACMP_VREF_CRVSSEL_VDDA
+  *                  - \ref ACMP_VREF_CRVSSEL_INTVREF
+  * @return None
+  * @details The source of CRV can be VDDA or internal reference voltage. The internal reference voltage level is determined by SYS_VREFCTL register.
+  */
+#define ACMP_SELECT_CRV_SRC(acmp, u32Src) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src))
+
+/**
+  * @brief This macro is used to select ACMP interrupt condition
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32Cond Comparator interrupt condition selection. Including:
+  *                  - \ref ACMP_CTL_INTPOL_RF
+  *                  - \ref ACMP_CTL_INTPOL_R
+  *                  - \ref ACMP_CTL_INTPOL_F
+  * @return None
+  * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge.
+  */
+#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)%2] = ((acmp)->CTL[(u32ChNum)%2] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond))
+
+
+
+/* Function prototype declaration */
+void ACMP_Open(ACMP_T *, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn);
+void ACMP_Close(ACMP_T *, uint32_t u32ChNum);
+
+
+
+/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group ACMP_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif //__ACMP_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_can.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_can.c
new file mode 100644
index 00000000000..a1ab3a90623
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_can.c
@@ -0,0 +1,1004 @@
+/**************************************************************************//**
+ * @file     can.c
+ * @version  V2.00
+ * $Revision: 8 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series CAN driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CAN_Driver CAN Driver
+  @{
+*/
+
+/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
+  @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+
+#if defined(CAN1)
+static uint8_t gu8LockCanIf[2][2] = {0};    // The chip has two CANs.
+#elif defined(CAN0) || defined(CAN)
+static uint8_t gu8LockCanIf[1][2] = {0};    // The chip only has one CAN.
+#endif
+
+#define RETRY_COUNTS    (0x10000000)
+
+//#define DEBUG_PRINTF printf
+#define DEBUG_PRINTF(...)
+
+/**
+  * @brief Check if any interface is available then lock it for usage.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @retval 0 IF0 is free
+  * @retval 1 IF1 is free
+  * @retval 2 No IF is free
+  * @details Search the first free message interface, starting from 0. If a interface is
+  *          available, set a flag to lock the interface.
+  */
+static uint32_t LockIF(CAN_T *tCAN)
+{
+    uint32_t u32CanNo;
+    uint32_t u32FreeIfNo;
+    uint32_t u32IntMask;
+
+#if defined(CAN1)
+    u32CanNo = (tCAN == CAN1) ? 1 : 0;
+#else // defined(CAN0) || defined(CAN)
+    u32CanNo = 0;
+#endif
+
+    u32FreeIfNo = 2;
+
+    /* Disable CAN interrupt */
+    u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+    tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+
+    /* Check interface 1 is available or not */
+    if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0)
+    {
+        if(gu8LockCanIf[u32CanNo][0] == FALSE)
+        {
+            gu8LockCanIf[u32CanNo][0] = TRUE;
+            u32FreeIfNo = 0;
+        }
+    }
+
+    /* Or check interface 2 is available or not */
+    if(u32FreeIfNo == 2 && (tCAN->IF[1].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0)
+    {
+        if(gu8LockCanIf[u32CanNo][1] == FALSE)
+        {
+            gu8LockCanIf[u32CanNo][1] = TRUE;
+            u32FreeIfNo = 1;
+        }
+    }
+
+    /* Enable CAN interrupt */
+    tCAN->CON |= u32IntMask;
+
+    return u32FreeIfNo;
+}
+
+/**
+  * @brief Check if any interface is available in a time limitation then lock it for usage.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @retval 0 IF0 is free
+  * @retval 1 IF1 is free
+  * @retval 2 No IF is free
+  * @details Search the first free message interface, starting from 0. If no interface is
+  *          it will try again until time out. If a interface is available,  set a flag to
+  *          lock the interface.
+  */
+static uint32_t LockIF_TL(CAN_T *tCAN)
+{
+    uint32_t u32Count;
+    uint32_t u32FreeIfNo;
+
+    for(u32Count = 0; u32Count < RETRY_COUNTS; u32Count++)
+    {
+        if((u32FreeIfNo = LockIF(tCAN)) != 2)
+            return u32FreeIfNo;
+    }
+
+    return u32FreeIfNo;
+}
+
+/**
+  * @brief Release locked interface.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32Info The interface number, 0 or 1.
+  * @return none
+  * @details Release the locked interface.
+  */
+static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo)
+{
+    uint32_t u32IntMask;
+    uint32_t u32CanNo;
+
+    if(u32IfNo >= 2)
+        return;
+
+#if defined(CAN1)
+    u32CanNo = (tCAN == CAN1) ? 1 : 0;
+#else // defined(CAN0) || defined(CAN)
+    u32CanNo = 0;
+#endif
+
+    /* Disable CAN interrupt */
+    u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+    tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+
+    gu8LockCanIf[u32CanNo][u32IfNo] = FALSE;
+
+    /* Enable CAN interrupt */
+    tCAN->CON |= u32IntMask;
+}
+
+/**
+  * @brief Enter initialization mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] Following values can be used.
+  *            \ref CAN_CON_DAR_Msk Disable automatic retransmission.
+  *            \ref CAN_CON_EIE_Msk Enable error interrupt.
+  *            \ref CAN_CON_SIE_Msk Enable status interrupt.
+  *            \ref CAN_CON_IE_Msk CAN interrupt.
+  * @return None
+  * @details This function is used to set CAN to enter initialization mode and enable access bit timing
+  *          register. After bit timing configuration ready, user must call CAN_LeaveInitMode()
+  *          to leave initialization mode and lock bit timing register to let new configuration
+  *          take effect.
+  */
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask)
+{
+    tCAN->CON = u8Mask | (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
+}
+
+
+/**
+  * @brief Leave initialization mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return None
+  * @details This function is used to set CAN to leave initialization mode to let
+  *          bit timing configuration take effect after configuration ready.
+  */
+void CAN_LeaveInitMode(CAN_T *tCAN)
+{
+    tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
+    while(tCAN->CON & CAN_CON_INIT_Msk); /* Check INIT bit is released */
+}
+
+/**
+  * @brief Wait message into message buffer in basic mode.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return None
+  * @details This function is used to wait message into message buffer in basic mode. Please notice the
+  *          function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode.
+  */
+void CAN_WaitMsg(CAN_T *tCAN)
+{
+    tCAN->STATUS = 0x0; /* clr status */
+
+    while(1)
+    {
+        if(tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk)   /* check new data */
+        {
+            DEBUG_PRINTF("New Data IN\n");
+            break;
+        }
+
+        if(tCAN->STATUS & CAN_STATUS_RXOK_Msk)
+            DEBUG_PRINTF("Rx OK\n");
+
+        if(tCAN->STATUS & CAN_STATUS_LEC_Msk)
+        {
+            DEBUG_PRINTF("Error\n");
+        }
+    }
+}
+
+/**
+  * @brief Get current bit rate
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return Current Bit-Rate (kilo bit per second)
+  * @details Return current CAN bit rate according to the user bit-timing parameter settings
+  */
+uint32_t CAN_GetCANBitRate(CAN_T *tCAN)
+{
+    uint8_t u8Tseg1, u8Tseg2;
+    uint32_t u32Bpr;
+
+    u8Tseg1 = (tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos;
+    u8Tseg2 = (tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos;
+    u32Bpr  = (tCAN->BTIME & CAN_BTIME_BRP_Msk) | (tCAN->BRPE << 6);
+
+    return (SystemCoreClock / (u32Bpr + 1) / (u8Tseg1 + u8Tseg2 + 3));
+}
+
+/**
+  * @brief Switch the CAN into test mode.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u8TestMask Specifies the configuration in test modes
+  *                       \ref CAN_TEST_BASIC_Msk Enable basic mode of test mode
+  *                       \ref CAN_TEST_SILENT_Msk Enable silent mode of test mode
+  *                       \ref CAN_TEST_LBACK_Msk Enable Loop Back Mode of test mode
+  *                       \ref CAN_TEST_TX0_Msk / \ref CAN_TEST_TX1_Msk Control CAN_TX pin bit field
+  * @return None
+  * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/
+  *          LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user
+  *          must call CAN_LeaveInitMode() to let the setting take effect.
+  */
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask)
+{
+    tCAN->CON |= CAN_CON_TEST_Msk;
+    tCAN->TEST = u8TestMask;
+}
+
+
+/**
+  * @brief Leave the test mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return   None
+  * @details  This function is used to Leave the test mode (switch into normal mode).
+  */
+void CAN_LeaveTestMode(CAN_T *tCAN)
+{
+    tCAN->CON |= CAN_CON_TEST_Msk;
+    tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk);
+    tCAN->CON &= (~CAN_CON_TEST_Msk);
+}
+
+/**
+  * @brief Get the waiting status of a received message.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @retval non-zero The corresponding message object has a new data bit is set.
+  * @retval 0 No message object has new data.
+  * @details This function is used to get the waiting status of a received message.
+  */
+uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj)
+{
+    return (u8MsgObj < 16 ? tCAN->NDAT1 & (1 << u8MsgObj) : tCAN->NDAT2 & (1 << (u8MsgObj - 16)));
+}
+
+
+/**
+  * @brief Send CAN message in BASIC mode of test mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] pCanMsg Pointer to the message structure containing data to transmit.
+  * @return TRUE:  Transmission OK
+  *         FALSE: Check busy flag of interface 0 is timeout
+  * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API,
+  *          the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter
+  *          basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode.
+  */
+int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
+{
+    uint32_t i = 0;
+    while(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk);
+
+    tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
+
+    if(pCanMsg->IdType == CAN_STD_ID)
+    {
+        /* standard ID*/
+        tCAN->IF[0].ARB1 = 0;
+        tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x7FF) << 2) ;
+    }
+    else
+    {
+        /* extended ID*/
+        tCAN->IF[0].ARB1 = (pCanMsg->Id) & 0xFFFF;
+        tCAN->IF[0].ARB2 = ((pCanMsg->Id) & 0x1FFF0000) >> 16  | CAN_IF_ARB2_XTD_Msk;
+
+    }
+
+    if(pCanMsg->FrameType)
+        tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk;
+    else
+        tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
+
+    tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC;
+    tCAN->IF[0].DAT_A1 = ((uint16_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0];
+    tCAN->IF[0].DAT_A2 = ((uint16_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2];
+    tCAN->IF[0].DAT_B1 = ((uint16_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4];
+    tCAN->IF[0].DAT_B2 = ((uint16_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6];
+
+    /* request transmission*/
+    tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk);
+    if(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk)
+    {
+        DEBUG_PRINTF("Cannot clear busy for sending ...\n");
+        return FALSE;
+    }
+
+    tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk;                          // sending
+
+    for(i = 0; i < 0xFFFFF; i++)
+    {
+        if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0)
+            break;
+    }
+
+    if(i >= 0xFFFFF)
+    {
+        DEBUG_PRINTF("Cannot send out...\n");
+        return FALSE;
+    }
+
+    return TRUE;
+}
+
+/**
+  * @brief Get a message information in BASIC mode.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @return FALSE No any message received.
+  *         TRUE Receive a message success.
+  *
+  */
+int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
+{
+
+    if((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0)   /* In basic mode, receive data always save in IF2 */
+    {
+        return FALSE;
+    }
+
+    tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
+
+    tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk
+                        | CAN_IF_CMASK_CONTROL_Msk
+                        | CAN_IF_CMASK_DATAA_Msk
+                        | CAN_IF_CMASK_DATAB_Msk;
+
+    if((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0)
+    {
+        /* standard ID*/
+        pCanMsg->IdType = CAN_STD_ID;
+        pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FF;
+
+    }
+    else
+    {
+        /* extended ID*/
+        pCanMsg->IdType = CAN_EXT_ID;
+        pCanMsg->Id  = (tCAN->IF[1].ARB2 & 0x1FFF) << 16;
+        pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1;
+    }
+
+    pCanMsg->FrameType = !((tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) >> CAN_IF_ARB2_DIR_Pos);
+
+    pCanMsg->DLC     = tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk;
+    pCanMsg->Data[0] = tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk;
+    pCanMsg->Data[1] = (tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos;
+    pCanMsg->Data[2] = tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk;
+    pCanMsg->Data[3] = (tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos;
+    pCanMsg->Data[4] = tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk;
+    pCanMsg->Data[5] = (tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos;
+    pCanMsg->Data[6] = tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk;
+    pCanMsg->Data[7] = (tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos;
+
+    return TRUE;
+}
+
+/**
+  * @brief Set Rx message object, include ID mask.
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
+  *                     This parameter can be one of the following values:
+  *                     \ref CAN_STD_ID (standard ID, 11-bit)
+  *                     \ref CAN_EXT_ID (extended ID, 29-bit)
+  * @param[in] u32id Specifies the identifier used for acceptance filtering.
+  * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
+  *                               This parameter can be one of the following values:
+  *                               TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
+  *                               FALSE: for a FIFO receive object that is not the last one.
+  * @retval TRUE SUCCESS
+  * @retval FALSE No useful interface
+  * @details The function is used to configure a receive message object.
+  */
+int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast)
+{
+    uint8_t u8MsgIfNum;
+
+    /* Get and lock a free interface */
+    if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
+        return FALSE;
+
+    /* Command Setting */
+    tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+                                 CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+    if(u8idType == CAN_STD_ID)    /* According STD/EXT ID format,Configure Mask and Arbitration register */
+    {
+        tCAN->IF[u8MsgIfNum].ARB1 = 0;
+        tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FF) << 2;
+    }
+    else
+    {
+        tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFF;
+        tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000) >> 16;
+    }
+
+    tCAN->IF[u8MsgIfNum].MASK1 = (u32idmask & 0xFFFF);
+    tCAN->IF[u8MsgIfNum].MASK2 = (u32idmask >> 16) & 0xFFFF;
+
+    //tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+    tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+    if(u8singleOrFifoLast)
+        tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
+    else
+        tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
+
+    tCAN->IF[u8MsgIfNum].DAT_A1  = 0;
+    tCAN->IF[u8MsgIfNum].DAT_A2  = 0;
+    tCAN->IF[u8MsgIfNum].DAT_B1  = 0;
+    tCAN->IF[u8MsgIfNum].DAT_B2  = 0;
+
+    tCAN->IF[u8MsgIfNum].CREQ = 1 + u8MsgObj;
+    ReleaseIF(tCAN, u8MsgIfNum);
+
+    return TRUE;
+}
+
+/**
+  * @brief Set Rx message object
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
+  *                     This parameter can be one of the following values:
+  *                     \ref CAN_STD_ID (standard ID, 11-bit)
+  *                     \ref CAN_EXT_ID (extended ID, 29-bit)
+  * @param[in] u32id Specifies the identifier used for acceptance filtering.
+  * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
+  *                               This parameter can be one of the following values:
+  *                               TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
+  *                               FALSE: for a FIFO receive object that is not the last one.
+  * @retval TRUE SUCCESS
+  * @retval FALSE No useful interface
+  * @details The function is used to configure a receive message object.
+  */
+int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast)
+{
+    uint8_t u8MsgIfNum;
+
+    /* Get and lock a free interface */
+    if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
+        return FALSE;
+
+    /* Command Setting */
+    tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+                                 CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+    if(u8idType == CAN_STD_ID)    /* According STD/EXT ID format,Configure Mask and Arbitration register */
+    {
+        tCAN->IF[u8MsgIfNum].ARB1 = 0;
+        tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FF) << 2;
+    }
+    else
+    {
+        tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFF;
+        tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000) >> 16;
+    }
+
+    //tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+    tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+    if(u8singleOrFifoLast)
+        tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
+    else
+        tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
+
+    tCAN->IF[u8MsgIfNum].DAT_A1  = 0;
+    tCAN->IF[u8MsgIfNum].DAT_A2  = 0;
+    tCAN->IF[u8MsgIfNum].DAT_B1  = 0;
+    tCAN->IF[u8MsgIfNum].DAT_B2  = 0;
+
+    tCAN->IF[u8MsgIfNum].CREQ = 1 + u8MsgObj;
+    ReleaseIF(tCAN, u8MsgIfNum);
+
+    return TRUE;
+}
+
+/**
+  * @brief Gets the message
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @param[in] u8Release Specifies the message release indicator.
+  *                      This parameter can be one of the following values:
+  *                      TRUE: the message object is released when getting the data.
+  *                      FALSE:the message object is not released.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  * @retval TRUE Success
+  * @retval FALSE No any message received
+  * @details Gets the message, if received.
+  */
+int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg)
+{
+    uint8_t u8MsgIfNum;
+
+    if(!CAN_IsNewDataReceived(tCAN, u8MsgObj))
+        return FALSE;
+
+    /* Get and lock a free interface */
+    if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
+        return FALSE;
+
+    tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
+
+    /* read the message contents*/
+    tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_MASK_Msk
+                                 | CAN_IF_CMASK_ARB_Msk
+                                 | CAN_IF_CMASK_CONTROL_Msk
+                                 | CAN_IF_CMASK_CLRINTPND_Msk
+                                 | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0)
+                                 | CAN_IF_CMASK_DATAA_Msk
+                                 | CAN_IF_CMASK_DATAB_Msk;
+
+    tCAN->IF[u8MsgIfNum].CREQ = 1 + u8MsgObj;
+
+    while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)
+    {
+        /*Wait*/
+    }
+
+    if((tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0)
+    {
+        /* standard ID*/
+        pCanMsg->IdType = CAN_STD_ID;
+        pCanMsg->Id     = (tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2;
+    }
+    else
+    {
+        /* extended ID*/
+        pCanMsg->IdType = CAN_EXT_ID;
+        pCanMsg->Id  = (((tCAN->IF[u8MsgIfNum].ARB2) & 0x1FFF) << 16) | tCAN->IF[u8MsgIfNum].ARB1;
+    }
+
+    pCanMsg->DLC     = tCAN->IF[u8MsgIfNum].MCON & CAN_IF_MCON_DLC_Msk;
+    pCanMsg->Data[0] = tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk;
+    pCanMsg->Data[1] = (tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos;
+    pCanMsg->Data[2] = tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk;
+    pCanMsg->Data[3] = (tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos;
+    pCanMsg->Data[4] = tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk;
+    pCanMsg->Data[5] = (tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos;
+    pCanMsg->Data[6] = tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk;
+    pCanMsg->Data[7] = (tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos;
+
+    ReleaseIF(tCAN, u8MsgIfNum);
+    return TRUE;
+}
+
+/// @endcond HIDDEN_SYMBOLS
+
+
+/**
+  * @brief Set bus baud-rate.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
+  *
+  * @return u32CurrentBitRate  Real baud-rate value.
+  *
+  * @details The function is used to set bus timing parameter according current clock and target baud-rate.
+  */
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)
+{
+    uint8_t u8Tseg1, u8Tseg2;
+    uint32_t u32Brp;
+    uint32_t u32Value;
+
+    CAN_EnterInitMode(tCAN, 0);
+    SystemCoreClockUpdate();
+    u32Value = SystemCoreClock / u32BaudRate;
+
+#if 0
+    u8Tseg1 = 2;
+    u8Tseg2 = 1;
+    while(1)
+    {
+        if(((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0))
+            break;
+        if(u8Tseg1 < 7)
+            u8Tseg2++;
+
+        if((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0)
+            break;
+        if(u8Tseg1 < 15)
+            u8Tseg1++;
+        else
+        {
+            u8Tseg1 = 2;
+            u8Tseg2 = 1;
+            break;
+        }
+    }
+#else
+
+    /* Fix for most standard baud rates, include 125K */
+
+    u8Tseg1 = 3;
+    u8Tseg2 = 2;
+    while(1)
+    {
+        if(((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0) | (u8Tseg1 >= 15))
+            break;
+
+        u8Tseg1++;
+
+        if((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0)
+            break;
+
+        if(u8Tseg2 < 7)
+            u8Tseg2++;
+    }
+#endif
+    u32Brp  = SystemCoreClock / (u32BaudRate) / (u8Tseg1 + u8Tseg2 + 3) - 1;
+
+    u32Value = ((uint32_t)u8Tseg2 << CAN_BTIME_TSEG2_Pos) | ((uint32_t)u8Tseg1 << CAN_BTIME_TSEG1_Pos) |
+               (u32Brp & CAN_BTIME_BRP_Msk) | (tCAN->BTIME & CAN_BTIME_SJW_Msk);
+    tCAN->BTIME = u32Value;
+    tCAN->BRPE     = (u32Brp >> 6) & 0x0F;
+
+    CAN_LeaveInitMode(tCAN);
+
+    return (CAN_GetCANBitRate(tCAN));
+}
+
+/**
+  * @brief The function is used to disable all CAN interrupt.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  *
+  * @return None
+  *
+  * @details No Status Change Interrupt and Error Status Interrupt will be generated.
+  */
+void CAN_Close(CAN_T *tCAN)
+{
+    CAN_DisableInt(tCAN, (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
+}
+
+/**
+  * @brief Set CAN operation mode and target baud-rate.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
+  * @param[in] u32Mode The CAN operation mode. Valid values are:
+  *                    - \ref CAN_NORMAL_MODE Normal operation.
+  *                    - \ref CAN_BASIC_MODE Basic mode.
+  * @return u32CurrentBitRate  Real baud-rate value.
+  *
+  * @details Set bus timing parameter according current clock and target baud-rate.
+  *          In Basic mode, IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
+  */
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode)
+{
+    uint32_t u32CurrentBitRate;
+
+    u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate);
+
+    if(u32Mode == CAN_BASIC_MODE)
+        CAN_EnterTestMode(tCAN, CAN_TEST_BASIC_Msk);
+
+    return u32CurrentBitRate;
+}
+
+/**
+  * @brief The function is used to configure a transmit object.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Config message object success.
+  *
+  * @details The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM.
+  *          They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission.
+  */
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
+{
+    uint8_t u8MsgIfNum;
+
+    if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
+        return FALSE;
+
+    /* update the contents needed for transmission*/
+    tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+                                 CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk  | CAN_IF_CMASK_DATAB_Msk;
+
+    if(pCanMsg->IdType == CAN_STD_ID)
+    {
+        /* standard ID*/
+        tCAN->IF[u8MsgIfNum].ARB1 = 0;
+        tCAN->IF[u8MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x7FF) << 2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk;
+    }
+    else
+    {
+        /* extended ID*/
+        tCAN->IF[u8MsgIfNum].ARB1 = (pCanMsg->Id) & 0xFFFF;
+        tCAN->IF[u8MsgIfNum].ARB2 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 |
+                                    CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk;
+    }
+
+    if(pCanMsg->FrameType)
+        tCAN->IF[u8MsgIfNum].ARB2 |=   CAN_IF_ARB2_DIR_Msk;
+    else
+        tCAN->IF[u8MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
+
+    tCAN->IF[u8MsgIfNum].DAT_A1 = ((uint16_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0];
+    tCAN->IF[u8MsgIfNum].DAT_A2 = ((uint16_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2];
+    tCAN->IF[u8MsgIfNum].DAT_B1 = ((uint16_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4];
+    tCAN->IF[u8MsgIfNum].DAT_B2 = ((uint16_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6];
+
+    tCAN->IF[u8MsgIfNum].MCON   =  CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk;
+    tCAN->IF[u8MsgIfNum].CREQ   = 1 + u32MsgNum;
+
+    ReleaseIF(tCAN, u8MsgIfNum);
+    return TRUE;
+}
+
+/**
+  * @brief Set transmit request bit.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  *
+  * @return TRUE: Start transmit message.
+  *
+  * @details If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst (IFn_MCON[8]) will be ignored.
+  */
+int32_t CAN_TriggerTxMsg(CAN_T  *tCAN, uint32_t u32MsgNum)
+{
+    uint8_t u8MsgIfNum;
+
+    if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
+        return FALSE;
+
+    tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
+
+    /* read the message contents*/
+    tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk
+                                 | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+
+    tCAN->IF[u8MsgIfNum].CREQ = 1 + u32MsgNum;
+
+    while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)
+    {
+        /*Wait*/
+    }
+    tCAN->IF[u8MsgIfNum].CMASK  = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+    tCAN->IF[u8MsgIfNum].CREQ  = 1 + u32MsgNum;
+
+    ReleaseIF(tCAN, u8MsgIfNum);
+    return TRUE;
+}
+
+/**
+  * @brief Enable CAN interrupt.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32Mask Interrupt Mask. Valid values are:
+  *                    - \ref CAN_CON_IE_Msk Module interrupt enable.
+  *                    - \ref CAN_CON_SIE_Msk Status change interrupt enable.
+  *                    - \ref CAN_CON_EIE_Msk Error interrupt enable.
+  *
+  * @return None
+  *
+  * @details The application software has two possibilities to follow the source of a message interrupt.
+  *          First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register.
+  */
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask)
+{
+    tCAN->CON = (tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)) |
+                (u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
+}
+
+/**
+  * @brief Disable CAN interrupt.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32Mask Interrupt Mask. (CAN_CON_IE_Msk / CAN_CON_SIE_Msk / CAN_CON_EIE_Msk).
+  *
+  * @return None
+  *
+  * @details The interrupt remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.
+  */
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask)
+{
+    tCAN->CON = tCAN->CON & ~((u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)));
+}
+
+
+/**
+  * @brief The function is used to configure a receive message object.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+  *                      - \ref CAN_STD_ID The 11-bit identifier.
+  *                      - \ref CAN_EXT_ID The 29-bit identifier.
+  * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Configure a receive message object success.
+  *
+  * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
+  *          will be set when a received Data Frame is accepted and stored in the Message Object.
+  */
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID)
+{
+    uint32_t u32TimeOutCount = 0;
+
+    while(CAN_SetRxMsgObj(tCAN, u32MsgNum, u32IDType, u32ID, TRUE) == FALSE)
+    {
+        if(++u32TimeOutCount >= RETRY_COUNTS) return FALSE;
+    }
+
+    return TRUE;
+}
+
+/**
+  * @brief The function is used to configure a receive message object.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+  *                      - \ref CAN_STD_ID The 11-bit identifier.
+  *                      - \ref CAN_EXT_ID The 29-bit identifier.
+  * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+  * @param[in] u32IDMask Specifies the identifier mask used for acceptance filtering.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Configure a receive message object success.
+  *
+  * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
+  *          will be set when a received Data Frame is accepted and stored in the Message Object.
+  */
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask)
+{
+    uint32_t u32TimeOutCount = 0;
+
+    while(CAN_SetRxMsgObjAndMsk(tCAN, u32MsgNum, u32IDType, u32ID, u32IDMask, TRUE) == FALSE)
+    {
+        if(++u32TimeOutCount >= RETRY_COUNTS) return FALSE;
+    }
+
+    return TRUE;
+}
+
+/**
+  * @brief The function is used to configure several receive message objects.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum The starting MSG RAM number(0 ~ 31).
+  * @param[in] u32MsgCount the number of MSG RAM of the FIFO.
+  * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+  *                      - \ref CAN_STD_ID The 11-bit identifier.
+  *                      - \ref CAN_EXT_ID The 29-bit identifier.
+  * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Configure receive message objects success.
+  *
+  * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
+  *          and transmission by buffering the data to be transferred.
+  */
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID)
+{
+    uint32_t i = 0;
+    uint32_t u32TimeOutCount;
+    uint32_t u32EOB_Flag = 0;
+
+    for(i = 1; i < u32MsgCount; i++)
+    {
+        u32TimeOutCount = 0;
+
+        u32MsgNum += (i - 1);
+
+        if(i == u32MsgCount) u32EOB_Flag = 1;
+
+        while(CAN_SetRxMsgObj(tCAN, u32MsgNum, u32IDType, u32ID, u32EOB_Flag) == FALSE)
+        {
+            if(++u32TimeOutCount >= RETRY_COUNTS) return FALSE;
+        }
+    }
+
+    return TRUE;
+}
+
+
+/**
+  * @brief Send CAN message.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @retval FALSE 1. When operation in basic mode: Transmit message time out. \n
+  *               2. When operation in normal mode: No useful interface. \n
+  * @retval TRUE Transmit Message success.
+  *
+  * @details The receive/transmit priority for the Message Objects is attached to the message number.
+  *          Message Object 1 has the highest priority, while Message Object 32 has the lowest priority.
+  */
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
+{
+    if((tCAN->CON & CAN_CON_TEST_Msk) && (tCAN->TEST & CAN_TEST_BASIC_Msk))
+    {
+        return (CAN_BasicSendMsg(tCAN, pCanMsg));
+    }
+    else
+    {
+        if(CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == FALSE)
+            return FALSE;
+        CAN_TriggerTxMsg(tCAN, u32MsgNum);
+    }
+
+    return TRUE;
+}
+
+
+/**
+  * @brief Gets the message, if received.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @retval FALSE No any message received.
+  * @retval TRUE Receive Message success.
+  *
+  * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
+  *          and transmission by buffering the data to be transferred.
+  */
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
+{
+    if((tCAN->CON & CAN_CON_TEST_Msk) && (tCAN->TEST & CAN_TEST_BASIC_Msk))
+    {
+        return (CAN_BasicReceiveMsg(tCAN, pCanMsg));
+    }
+    else
+    {
+        return CAN_ReadMsgObj(tCAN, u32MsgNum, TRUE, pCanMsg);
+    }
+}
+
+/**
+  * @brief Clear interrupt pending bit.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  *
+  * @return None
+  *
+  * @details An interrupt remains pending until the application software has cleared it.
+  */
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum)
+{
+    uint32_t u32MsgIfNum;
+
+    if((u32MsgIfNum = LockIF_TL(tCAN)) == 2)
+        u32MsgIfNum = 0;
+
+    tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+    tCAN->IF[u32MsgIfNum].CREQ = 1 + u32MsgNum;
+
+    ReleaseIF(tCAN, u32MsgIfNum);
+}
+
+
+/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CAN_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
+
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_can.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_can.h
new file mode 100644
index 00000000000..7f661c3bb04
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_can.h
@@ -0,0 +1,175 @@
+/**************************************************************************//**
+ * @file     can.h
+ * @version  V2.00
+ * $Revision: 9 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 Series CAN Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __CAN_H__
+#define __CAN_H__
+
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CAN_Driver CAN Driver
+  @{
+*/
+
+/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAN Test Mode Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_NORMAL_MODE   0
+#define    CAN_BASIC_MODE    1
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message ID Type Constant Definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_STD_ID    0
+#define    CAN_EXT_ID    1
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message Frame Type Constant Definitions                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_REMOTE_FRAME    0
+#define    CAN_DATA_FRAME    1
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CAN message structure                                                                                  */
+/*---------------------------------------------------------------------------------------------------------*/
+typedef struct
+{
+    uint32_t  IdType;
+    uint32_t  FrameType;
+    uint32_t  Id;
+    uint8_t   DLC;
+    uint8_t   Data[8];
+} STR_CANMSG_T;
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CAN mask message structure                                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+typedef struct
+{
+    uint8_t   u8Xtd;
+    uint8_t   u8Dir;
+    uint32_t  u32Id;
+    uint8_t   u8IdType;
+} STR_CANMASK_T;
+
+#define MSG(id)  (id)
+
+
+/*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
+  @{
+*/
+
+/**
+ * @brief Get interrupt status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return CAN module status register value.
+ *
+ * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]),
+ *          EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]).
+ */
+#define CAN_GET_INT_STATUS(can) ((can)->STATUS)
+
+/**
+ * @brief Get specified interrupt pending status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return The source of the interrupt.
+ *
+ * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
+ *          with the highest priority, disregarding their chronological order.
+ */
+#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR)
+
+/**
+ * @brief Disable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details  The macro is used to disable wake-up function.
+ */
+#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0)
+
+/**
+ * @brief Enable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details User can wake-up system when there is a falling edge in the CAN_Rx pin.
+ */
+#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WUEN_WAKUP_EN_Msk)
+
+/**
+ * @brief Get specified Message Object new data into bit value.
+ *
+ * @param[in] can The base address of can module.
+ * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31.
+ *
+ * @return Specified Message Object new data into bit value.
+ *
+ * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers
+ *          or by the Message Handler after reception of a Data Frame or after a successful transmission.
+ */
+#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16)))
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define CAN functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate);
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode);
+void CAN_Close(CAN_T *tCAN);
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum);
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask);
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask);
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask);
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
+int32_t CAN_TriggerTxMsg(CAN_T  *tCAN, uint32_t u32MsgNum);
+
+
+/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CAN_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__CAN_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_clk.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_clk.c
new file mode 100644
index 00000000000..eae295ea443
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_clk.c
@@ -0,0 +1,751 @@
+/**************************************************************************//**
+ * @file     clk.c
+ * @version  V3.00
+ * $Revision: 35 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series CLK driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CLK_Driver CLK Driver
+  @{
+*/
+
+/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Disable clock divider output function
+  * @param      None
+  * @return     None
+  * @details    This function disable clock divider output function.
+  */
+void CLK_DisableCKO(void)
+{
+    /* Disable CKO clock source */
+    CLK_DisableModuleClock(CLKO_MODULE);
+}
+
+/**
+  * @brief      This function enable clock divider output module clock,
+  *             enable clock divider output function and set frequency selection.
+  * @param[in]  u32ClkSrc is frequency divider function clock source. Including :
+  *             - \ref CLK_CLKSEL1_CLKOSEL_HXT
+  *             - \ref CLK_CLKSEL1_CLKOSEL_LXT
+  *             - \ref CLK_CLKSEL1_CLKOSEL_HCLK
+  *             - \ref CLK_CLKSEL1_CLKOSEL_HIRC
+  * @param[in]  u32ClkDiv is divider output frequency selection. It could be 0~15.
+  * @param[in]  u32ClkDivBy1En is clock divided by one enabled.
+  * @return     None
+  * @details    Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n
+  *             The formula is: \n
+  *                 CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n
+  *             This function is just used to set CKO clock.
+  *             User must enable I/O for CKO clock output pin by themselves. \n
+  */
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
+{
+    /* CKO = clock source / 2^(u32ClkDiv + 1) */
+    CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
+
+    /* Enable CKO clock source */
+    CLK_EnableModuleClock(CLKO_MODULE);
+
+    /* Select CKO clock source */
+    CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0);
+}
+
+/**
+  * @brief      Enter to Power-down mode
+  * @param      None
+  * @return     None
+  * @details    This function is used to let system enter to Power-down mode. \n
+  *             The register write-protection function should be disabled before using this function. 
+  */
+void CLK_PowerDown(void)
+{
+    /* Set the processor uses deep sleep as its low power mode */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    /* Set system Power-down enabled and Power-down entry condition */
+    CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk | CLK_PWRCTL_PDWTCPU_Msk);
+
+    /* Chip enter Power-down mode after CPU run WFI instruction */
+    __WFI();
+}
+
+/**
+  * @brief      Enter to Idle mode
+  * @param      None
+  * @return     None
+  * @details    This function let system enter to Idle mode. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_Idle(void)
+{
+    /* Set the processor uses sleep as its low power mode */
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+
+    /* Set chip in idle mode because of WFI command */
+    CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
+
+    /* Chip enter idle mode after CPU run WFI instruction */
+    __WFI();
+}
+
+/**
+  * @brief      Get external high speed crystal clock frequency
+  * @param      None
+  * @return     External high frequency crystal frequency
+  * @details    This function get external high frequency crystal frequency. The frequency unit is Hz.
+  */
+uint32_t CLK_GetHXTFreq(void)
+{
+    if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk)
+        return __HXT;
+    else
+        return 0;
+}
+
+
+/**
+  * @brief      Get external low speed crystal clock frequency
+  * @param      None
+  * @return     External low speed crystal clock frequency
+  * @details    This function get external low frequency crystal frequency. The frequency unit is Hz.
+  */
+uint32_t CLK_GetLXTFreq(void)
+{
+    if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk)
+        return __LXT;
+    else
+        return 0;
+}
+
+/**
+  * @brief      Get PCLK0 frequency
+  * @param      None
+  * @return     PCLK0 frequency
+  * @details    This function get PCLK0 frequency. The frequency unit is Hz.
+  */
+uint32_t CLK_GetPCLK0Freq(void)
+{
+    SystemCoreClockUpdate();
+    if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk)
+        return SystemCoreClock / 2;
+    else
+        return SystemCoreClock;
+}
+
+
+/**
+  * @brief      Get PCLK1 frequency
+  * @param      None
+  * @return     PCLK1 frequency
+  * @details    This function get PCLK1 frequency. The frequency unit is Hz.
+  */
+uint32_t CLK_GetPCLK1Freq(void)
+{
+    SystemCoreClockUpdate();
+    if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk)
+        return SystemCoreClock / 2;
+    else
+        return SystemCoreClock;
+}
+
+
+/**
+  * @brief      Get HCLK frequency
+  * @param      None
+  * @return     HCLK frequency
+  * @details    This function get HCLK frequency. The frequency unit is Hz.
+  */
+uint32_t CLK_GetHCLKFreq(void)
+{
+    SystemCoreClockUpdate();
+    return SystemCoreClock;
+}
+
+
+/**
+  * @brief      Get CPU frequency
+  * @param      None
+  * @return     CPU frequency
+  * @details    This function get CPU frequency. The frequency unit is Hz.
+  */
+uint32_t CLK_GetCPUFreq(void)
+{
+    SystemCoreClockUpdate();
+    return SystemCoreClock;
+}
+
+
+/**
+  * @brief      Set HCLK frequency
+  * @param[in]  u32Hclk is HCLK frequency. The range of u32Hclk is 25 MHz ~ 72 MHz.
+  * @return     HCLK frequency
+  * @details    This function is used to set HCLK frequency. The frequency unit is Hz. \n
+  *             It would configure PLL frequency to 50MHz ~ 144MHz,
+  *             set HCLK clock divider as 2 and switch HCLK clock source to PLL. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
+{
+    uint32_t u32HIRCSTB;
+
+    /* Read HIRC clock source stable flag */
+    u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+
+    /* The range of u32Hclk is 25 MHz ~ 72 MHz */
+    if(u32Hclk > FREQ_72MHZ)
+        u32Hclk = FREQ_72MHZ;
+    if(u32Hclk < FREQ_25MHZ)
+        u32Hclk = FREQ_25MHZ;
+
+    /* Switch HCLK clock source to HIRC clock for safe */
+    CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+    CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
+    CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
+
+    /* Configure PLL setting if HXT clock is enabled */
+    if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk)
+        u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, (u32Hclk << 1));
+
+    /* Configure PLL setting if HXT clock is not enabled */
+    else
+    {
+        u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, (u32Hclk << 1));
+
+        /* Read HIRC clock source stable flag */
+        u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+    }
+
+    /* Select HCLK clock source to PLL,
+       Select HCLK clock source divider as 2
+       and update system core clock
+    */
+    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(2));
+
+    /* Disable HIRC if HIRC is disabled before setting core clock */
+    if(u32HIRCSTB == 0)
+        CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
+
+    /* Return actually HCLK frequency is PLL frequency divide 2 */
+    return u32Hclk >> 1;
+}
+
+/**
+  * @brief      This function set HCLK clock source and HCLK clock divider
+  * @param[in]  u32ClkSrc is HCLK clock source. Including :
+  *             - \ref CLK_CLKSEL0_HCLKSEL_HXT
+  *             - \ref CLK_CLKSEL0_HCLKSEL_LXT
+  *             - \ref CLK_CLKSEL0_HCLKSEL_PLL
+  *             - \ref CLK_CLKSEL0_HCLKSEL_LIRC
+  *             - \ref CLK_CLKSEL0_HCLKSEL_HIRC
+  * @param[in]  u32ClkDiv is HCLK clock divider. Including :
+  *             - \ref CLK_CLKDIV0_HCLK(x)
+  * @return     None
+  * @details    This function set HCLK clock source and HCLK clock divider. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+    uint32_t u32HIRCSTB;
+
+    /* Read HIRC clock source stable flag */
+    u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+
+    /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
+    CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+    CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
+
+    /* Apply new Divider */
+    CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
+
+    /* Switch HCLK to new HCLK source */
+    CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
+
+    /* Update System Core Clock */
+    SystemCoreClockUpdate();
+
+    /* Disable HIRC if HIRC is disabled before switching HCLK source */
+    if(u32HIRCSTB == 0)
+        CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
+}
+
+/**
+  * @brief      This function set selected module clock source and module clock divider
+  * @param[in]  u32ModuleIdx is module index.
+  * @param[in]  u32ClkSrc is module clock source.
+  * @param[in]  u32ClkDiv is module clock divider.
+  * @return     None
+  * @details    Valid parameter combinations listed in following table:
+  *
+  * |Module index        |Clock source                           |Divider                  |
+  * | :----------------  | :-----------------------------------  | :---------------------- |
+  * |\ref WDT_MODULE     |\ref CLK_CLKSEL1_WDTSEL_LXT            | x                       |
+  * |\ref WDT_MODULE     |\ref CLK_CLKSEL1_WDTSEL_PCLK0_DIV2048  | x                       |
+  * |\ref WDT_MODULE     |\ref CLK_CLKSEL1_WDTSEL_LIRC           | x                       |
+  * |\ref RTC_MODULE     |\ref CLK_CLKSEL3_RTCSEL_LXT            | x                       |
+  * |\ref RTC_MODULE     |\ref CLK_CLKSEL3_RTCSEL_LIRC           | x                       |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_HXT           | x                       |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_LXT           | x                       |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_PCLK0         | x                       |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_EXT_TRG       | x                       |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_LIRC          | x                       |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_HIRC          | x                       |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_HXT           | x                       |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_LXT           | x                       |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_PCLK0         | x                       |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_EXT_TRG       | x                       |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_LIRC          | x                       |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_HIRC          | x                       |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_HXT           | x                       |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_LXT           | x                       |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_PCLK1         | x                       |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_EXT_TRG       | x                       |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_LIRC          | x                       |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_HIRC          | x                       |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_HXT           | x                       |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_LXT           | x                       |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_PCLK1         | x                       |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_EXT_TRG       | x                       |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_LIRC          | x                       |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_HIRC          | x                       |
+  * |\ref CLKO_MODULE    |\ref CLK_CLKSEL1_CLKOSEL_HXT           | x                       |
+  * |\ref CLKO_MODULE    |\ref CLK_CLKSEL1_CLKOSEL_LXT           | x                       |
+  * |\ref CLKO_MODULE    |\ref CLK_CLKSEL1_CLKOSEL_HCLK          | x                       |
+  * |\ref CLKO_MODULE    |\ref CLK_CLKSEL1_CLKOSEL_HIRC          | x                       |
+  * |\ref SPI0_MODULE    |\ref CLK_CLKSEL2_SPI0SEL_HXT           | x                       |
+  * |\ref SPI0_MODULE    |\ref CLK_CLKSEL2_SPI0SEL_PLL           | x                       |
+  * |\ref SPI0_MODULE    |\ref CLK_CLKSEL2_SPI0SEL_PCLK0         | x                       |
+  * |\ref SPI0_MODULE    |\ref CLK_CLKSEL2_SPI0SEL_HIRC          | x                       |
+  * |\ref SPI1_MODULE    |\ref CLK_CLKSEL2_SPI1SEL_HXT           | x                       |
+  * |\ref SPI1_MODULE    |\ref CLK_CLKSEL2_SPI1SEL_PLL           | x                       |
+  * |\ref SPI1_MODULE    |\ref CLK_CLKSEL2_SPI1SEL_PCLK1         | x                       |
+  * |\ref SPI1_MODULE    |\ref CLK_CLKSEL2_SPI1SEL_HIRC          | x                       |
+  * |\ref SPI2_MODULE    |\ref CLK_CLKSEL2_SPI2SEL_HXT           | x                       |
+  * |\ref SPI2_MODULE    |\ref CLK_CLKSEL2_SPI2SEL_PLL           | x                       |
+  * |\ref SPI2_MODULE    |\ref CLK_CLKSEL2_SPI2SEL_PCLK0         | x                       |
+  * |\ref SPI2_MODULE    |\ref CLK_CLKSEL2_SPI2SEL_HIRC          | x                       |
+  * |\ref UART0_MODULE   |\ref CLK_CLKSEL1_UARTSEL_HXT           |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART0_MODULE   |\ref CLK_CLKSEL1_UARTSEL_PLL           |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART0_MODULE   |\ref CLK_CLKSEL1_UARTSEL_LXT           |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART0_MODULE   |\ref CLK_CLKSEL1_UARTSEL_HIRC          |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART1_MODULE   |\ref CLK_CLKSEL1_UARTSEL_HXT           |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART1_MODULE   |\ref CLK_CLKSEL1_UARTSEL_PLL           |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART1_MODULE   |\ref CLK_CLKSEL1_UARTSEL_LXT           |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART1_MODULE   |\ref CLK_CLKSEL1_UARTSEL_HIRC          |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART2_MODULE   |\ref CLK_CLKSEL1_UARTSEL_HXT           |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART2_MODULE   |\ref CLK_CLKSEL1_UARTSEL_PLL           |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART2_MODULE   |\ref CLK_CLKSEL1_UARTSEL_LXT           |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART2_MODULE   |\ref CLK_CLKSEL1_UARTSEL_HIRC          |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART3_MODULE   |\ref CLK_CLKSEL1_UARTSEL_HXT           |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART3_MODULE   |\ref CLK_CLKSEL1_UARTSEL_LXT           |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART3_MODULE   |\ref CLK_CLKSEL1_UARTSEL_PLL           |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref UART3_MODULE   |\ref CLK_CLKSEL1_UARTSEL_HIRC          |\ref CLK_CLKDIV0_UART(x) |
+  * |\ref USBH_MODULE    | x                                     |\ref CLK_CLKDIV0_USB(x)  |
+  * |\ref USBD_MODULE    | x                                     |\ref CLK_CLKDIV0_USB(x)  |
+  * |\ref OTG_MODULE     | x                                     |\ref CLK_CLKDIV0_USB(x)  |
+  * |\ref EADC_MODULE    | x                                     |\ref CLK_CLKDIV0_EADC(x) |
+  * |\ref SC0_MODULE     |\ref CLK_CLKSEL3_SC0SEL_HXT            |\ref CLK_CLKDIV1_SC0(x)  |
+  * |\ref SC0_MODULE     |\ref CLK_CLKSEL3_SC0SEL_PLL            |\ref CLK_CLKDIV1_SC0(x)  |
+  * |\ref SC0_MODULE     |\ref CLK_CLKSEL3_SC0SEL_PCLK0          |\ref CLK_CLKDIV1_SC0(x)  |
+  * |\ref SC0_MODULE     |\ref CLK_CLKSEL3_SC0SEL_HIRC           |\ref CLK_CLKDIV1_SC0(x)  |
+  * |\ref PWM0_MODULE    |\ref CLK_CLKSEL2_PWM0SEL_PLL           | x                       |
+  * |\ref PWM0_MODULE    |\ref CLK_CLKSEL2_PWM0SEL_PCLK0         | x                       |
+  * |\ref PWM1_MODULE    |\ref CLK_CLKSEL2_PWM1SEL_PLL           | x                       |
+  * |\ref PWM1_MODULE    |\ref CLK_CLKSEL2_PWM1SEL_PCLK1         | x                       |
+  * |\ref WWDT_MODULE    |\ref CLK_CLKSEL1_WWDTSEL_PCLK0_DIV2048 | x                       |
+  * |\ref WWDT_MODULE    |\ref CLK_CLKSEL1_WWDTSEL_LIRC          | x                       |
+  */
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+    uint32_t u32sel = 0, u32div = 0;
+
+    if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
+    {
+        /* Get clock divider control register address */
+        u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4);
+        /* Apply new divider */
+        M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
+    }
+
+    if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
+    {
+        /* Get clock select control register address */
+        u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4);
+        /* Set new clock selection setting */
+        M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
+    }
+}
+
+
+/**
+  * @brief      Set SysTick clock source
+  * @param[in]  u32ClkSrc is module clock source. Including:
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HXT
+  *             - \ref CLK_CLKSEL0_STCLKSEL_LXT
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
+  * @return     None
+  * @details    This function set SysTick clock source. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
+{
+    CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
+
+}
+
+/**
+  * @brief      Enable clock source
+  * @param[in]  u32ClkMask is clock source mask. Including :
+  *             - \ref CLK_PWRCTL_HXTEN_Msk
+  *             - \ref CLK_PWRCTL_LXTEN_Msk
+  *             - \ref CLK_PWRCTL_HIRCEN_Msk
+  *             - \ref CLK_PWRCTL_LIRCEN_Msk
+  * @return     None
+  * @details    This function enable clock source. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_EnableXtalRC(uint32_t u32ClkMask)
+{
+    CLK->PWRCTL |= u32ClkMask;
+}
+
+/**
+  * @brief      Disable clock source
+  * @param[in]  u32ClkMask is clock source mask. Including :
+  *             - \ref CLK_PWRCTL_HXTEN_Msk
+  *             - \ref CLK_PWRCTL_LXTEN_Msk
+  *             - \ref CLK_PWRCTL_HIRCEN_Msk
+  *             - \ref CLK_PWRCTL_LIRCEN_Msk
+  * @return     None
+  * @details    This function disable clock source. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_DisableXtalRC(uint32_t u32ClkMask)
+{
+    CLK->PWRCTL &= ~u32ClkMask;
+}
+
+/**
+  * @brief      Enable module clock
+  * @param[in]  u32ModuleIdx is module index. Including :
+  *             - \ref PDMA_MODULE
+  *             - \ref ISP_MODULE
+  *             - \ref EBI_MODULE
+  *             - \ref USBH_MODULE
+  *             - \ref CRC_MODULE
+  *             - \ref WDT_MODULE
+  *             - \ref WWDT_MODULE
+  *             - \ref RTC_MODULE
+  *             - \ref TMR0_MODULE
+  *             - \ref TMR1_MODULE
+  *             - \ref TMR2_MODULE
+  *             - \ref TMR3_MODULE
+  *             - \ref CLKO_MODULE
+  *             - \ref ACMP01_MODULE
+  *             - \ref I2C0_MODULE
+  *             - \ref I2C1_MODULE
+  *             - \ref SPI0_MODULE
+  *             - \ref SPI1_MODULE
+  *             - \ref SPI2_MODULE
+  *             - \ref UART0_MODULE
+  *             - \ref UART1_MODULE
+  *             - \ref UART2_MODULE
+  *             - \ref UART3_MODULE
+  *             - \ref CAN0_MODULE
+  *             - \ref OTG_MODULE
+  *             - \ref USBD_MODULE
+  *             - \ref EADC_MODULE
+  *             - \ref SC0_MODULE
+  *             - \ref DAC_MODULE
+  *             - \ref PWM0_MODULE
+  *             - \ref PWM1_MODULE
+  *             - \ref TK_MODULE
+  * @return     None
+  * @details    This function is used to enable module clock.
+  */
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
+{
+    *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4))  |= 1 << MODULE_IP_EN_Pos(u32ModuleIdx);
+}
+
+/**
+  * @brief      Disable module clock
+  * @param[in]  u32ModuleIdx is module index. Including :
+  *             - \ref PDMA_MODULE
+  *             - \ref ISP_MODULE
+  *             - \ref EBI_MODULE
+  *             - \ref USBH_MODULE
+  *             - \ref CRC_MODULE
+  *             - \ref WDT_MODULE
+  *             - \ref WWDT_MODULE
+  *             - \ref RTC_MODULE
+  *             - \ref TMR0_MODULE
+  *             - \ref TMR1_MODULE
+  *             - \ref TMR2_MODULE
+  *             - \ref TMR3_MODULE
+  *             - \ref CLKO_MODULE
+  *             - \ref ACMP01_MODULE
+  *             - \ref I2C0_MODULE
+  *             - \ref I2C1_MODULE
+  *             - \ref SPI0_MODULE
+  *             - \ref SPI1_MODULE
+  *             - \ref SPI2_MODULE
+  *             - \ref UART0_MODULE
+  *             - \ref UART1_MODULE
+  *             - \ref UART2_MODULE
+  *             - \ref UART3_MODULE
+  *             - \ref CAN0_MODULE
+  *             - \ref OTG_MODULE
+  *             - \ref USBD_MODULE
+  *             - \ref EADC_MODULE
+  *             - \ref SC0_MODULE
+  *             - \ref DAC_MODULE
+  *             - \ref PWM0_MODULE
+  *             - \ref PWM1_MODULE
+  *             - \ref TK_MODULE
+  * @return     None
+  * @details    This function is used to disable module clock.
+  */
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
+{
+    *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4))  &= ~(1 << MODULE_IP_EN_Pos(u32ModuleIdx));
+}
+
+
+/**
+  * @brief      Set PLL frequency
+  * @param[in]  u32PllClkSrc is PLL clock source. Including :
+  *             - \ref CLK_PLLCTL_PLLSRC_HXT
+  *             - \ref CLK_PLLCTL_PLLSRC_HIRC
+  * @param[in]  u32PllFreq is PLL frequency.
+  * @return     PLL frequency
+  * @details    This function is used to configure PLLCTL register to set specified PLL frequency. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
+{
+    uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC;
+    uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR;
+
+    /* Disable PLL first to avoid unstable when setting PLL */
+    CLK_DisablePLL();
+
+    /* PLL source clock is from HXT */
+    if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
+    {
+        /* Enable HXT clock */
+        CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
+
+        /* Wait for HXT clock ready */
+        CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+
+        /* Select PLL source clock from HXT */
+        u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
+        u32PllSrcClk = __HXT;
+
+        /* u32NR start from 2 */
+        u32NR = 2;
+    }
+
+    /* PLL source clock is from HIRC */
+    else
+    {
+        /* Enable HIRC clock */
+        CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+
+        /* Wait for HIRC clock ready */
+        CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+
+        /* Select PLL source clock from HIRC */
+        u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC;
+        u32PllSrcClk = __HIRC;
+
+        /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
+        u32NR = 4;
+    }
+
+    /* Select "NO" according to request frequency */
+    if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq > FREQ_250MHZ))
+    {
+        u32NO = 0;
+    }
+    else if((u32PllFreq <= FREQ_250MHZ) && (u32PllFreq > FREQ_125MHZ))
+    {
+        u32NO = 1;
+        u32PllFreq = u32PllFreq << 1;
+    }
+    else if((u32PllFreq <= FREQ_125MHZ) && (u32PllFreq >= FREQ_50MHZ))
+    {
+        u32NO = 3;
+        u32PllFreq = u32PllFreq << 2;
+    }
+    else
+    {
+        /* Wrong frequency request. Just return default setting. */
+        goto lexit;
+    }
+
+    /* Find best solution */
+    u32Min = (uint32_t) - 1;
+    u32MinNR = 0;
+    u32MinNF = 0;
+    for(; u32NR <= 33; u32NR++)
+    {
+        u32Tmp = u32PllSrcClk / u32NR;
+        if((u32Tmp > 1600000) && (u32Tmp < 16000000))
+        {
+            for(u32NF = 2; u32NF <= 513; u32NF++)
+            {
+                u32Tmp2 = u32Tmp * u32NF;
+                if((u32Tmp2 >= 200000000) && (u32Tmp2 <= 500000000))
+                {
+                    u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
+                    if(u32Tmp3 < u32Min)
+                    {
+                        u32Min = u32Tmp3;
+                        u32MinNR = u32NR;
+                        u32MinNF = u32NF;
+
+                        /* Break when get good results */
+                        if(u32Min == 0)
+                            break;
+                    }
+                }
+            }
+        }
+    }
+
+    /* Enable and apply new PLL setting. */
+    CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2);
+
+    /* Wait for PLL clock stable */
+    CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
+
+    /* Return actual PLL output clock frequency */
+    return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF;
+
+lexit:
+
+    /* Apply default PLL setting and return */
+    if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
+        CLK->PLLCTL = CLK_PLLCTL_72MHz_HXT; /* 72MHz */
+    else
+        CLK->PLLCTL = CLK_PLLCTL_72MHz_HIRC; /* 71.8848MHz */
+
+    /* Wait for PLL clock stable */
+    CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
+
+    return CLK_GetPLLClockFreq();
+
+}
+
+/**
+  * @brief      Disable PLL
+  * @param      None
+  * @return     None
+  * @details    This function set PLL in Power-down mode. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_DisablePLL(void)
+{
+    CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
+}
+
+
+/**
+  * @brief      This function check selected clock source status
+  * @param[in]  u32ClkMask is selected clock source. Including :
+  *             - \ref CLK_STATUS_HXTSTB_Msk
+  *             - \ref CLK_STATUS_LXTSTB_Msk
+  *             - \ref CLK_STATUS_HIRCSTB_Msk
+  *             - \ref CLK_STATUS_LIRCSTB_Msk
+  *             - \ref CLK_STATUS_PLLSTB_Msk
+  * @retval     0  clock is not stable
+  * @retval     1  clock is stable
+  * @details    To wait for clock ready by specified clock source stable flag or timeout (~300ms)
+  */
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
+{    
+    int32_t i32TimeOutCnt = 2160000;
+
+    while((CLK->STATUS & u32ClkMask) != u32ClkMask)
+    {
+        if(i32TimeOutCnt-- <= 0)
+            return 0;
+    }
+
+    return 1;
+}
+
+/**
+  * @brief      Enable System Tick counter
+  * @param[in]  u32ClkSrc is System Tick clock source. Including:
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HXT
+  *             - \ref CLK_CLKSEL0_STCLKSEL_LXT
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HCLK
+  * @param[in]  u32Count is System Tick reload value. It could be 0~0xFFFFFF.
+  * @return     None
+  * @details    This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
+  *             The register write-protection function should be disabled before using this function. 
+  */
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) 
+{
+    /* Set System Tick counter disabled */
+    SysTick->CTRL = 0;    
+
+    /* Set System Tick clock source */
+    if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK )         
+        SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
+    else
+        CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; 
+
+    /* Set System Tick reload value */
+    SysTick->LOAD = u32Count;   
+    
+    /* Clear System Tick current value and counter flag */
+    SysTick->VAL = 0;           
+    
+    /* Set System Tick interrupt enabled and counter enabled */    
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;       
+}
+
+/**
+  * @brief      Disable System Tick counter
+  * @param      None 
+  * @return     None
+  * @details    This function disable System Tick counter.
+  */
+void CLK_DisableSysTick(void) 
+{    
+    /* Set System Tick counter disabled */
+	SysTick->CTRL = 0;    
+}
+
+
+/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CLK_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_clk.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_clk.h
new file mode 100644
index 00000000000..7b4da2ba5e7
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_clk.h
@@ -0,0 +1,447 @@
+/******************************************************************************
+ * @file     CLK.h
+ * @version  V3.0
+ * $Revision  1 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 Series CLK Header File
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __CLK_H__
+#define __CLK_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CLK_Driver CLK Driver
+  @{
+*/
+
+/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
+  @{
+*/
+
+
+#define FREQ_25MHZ         25000000
+#define FREQ_50MHZ         50000000
+#define FREQ_72MHZ         72000000
+#define FREQ_125MHZ        125000000
+#define FREQ_200MHZ        200000000
+#define FREQ_250MHZ        250000000
+#define FREQ_500MHZ        500000000
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKSEL0 constant definitions.  (Write-protection)                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL0_HCLKSEL_HXT        (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as HXT */
+#define CLK_CLKSEL0_HCLKSEL_LXT        (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as LXT */
+#define CLK_CLKSEL0_HCLKSEL_PLL        (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as PLL */
+#define CLK_CLKSEL0_HCLKSEL_LIRC       (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as LIRC */
+#define CLK_CLKSEL0_HCLKSEL_HIRC       (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as HIRC */
+
+#define CLK_CLKSEL0_STCLKSEL_HXT       (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HXT */
+#define CLK_CLKSEL0_STCLKSEL_LXT       (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as LXT */
+#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2  (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HXT */
+#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HCLK/2 */
+#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HIRC/2 */
+#define CLK_CLKSEL0_STCLKSEL_HCLK      (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos) /*!< Setting SysTick clock source as HCLK */
+
+#define CLK_CLKSEL0_PCLK0SEL_HCLK      (0x00UL<<CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Setting PCLK0 clock source as HCLK */
+#define CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Setting PCLK0 clock source as HCLK/2 */
+
+#define CLK_CLKSEL0_PCLK1SEL_HCLK      (0x00UL<<CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Setting PCLK1 clock source as HCLK */
+#define CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Setting PCLK1 clock source as HCLK/2 */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKSEL1 constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL1_WDTSEL_LXT           (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos)  /*!< Setting WDT clock source as LXT */
+#define CLK_CLKSEL1_WDTSEL_PCLK0_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos)  /*!< Setting WDT clock source as PCLK0/2048 */
+#define CLK_CLKSEL1_WDTSEL_LIRC          (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos)  /*!< Setting WDT clock source as LIRC */
+
+#define CLK_CLKSEL1_TMR0SEL_HXT          (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as HXT */
+#define CLK_CLKSEL1_TMR0SEL_LXT          (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as LXT */
+#define CLK_CLKSEL1_TMR0SEL_PCLK0        (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as PCLK0 */
+#define CLK_CLKSEL1_TMR0SEL_EXT_TRG      (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external trigger */
+#define CLK_CLKSEL1_TMR0SEL_LIRC         (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as LIRC */
+#define CLK_CLKSEL1_TMR0SEL_HIRC         (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as HIRC */
+
+#define CLK_CLKSEL1_TMR1SEL_HXT          (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as HXT */
+#define CLK_CLKSEL1_TMR1SEL_LXT          (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as LXT */
+#define CLK_CLKSEL1_TMR1SEL_PCLK0        (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as PCLK0 */
+#define CLK_CLKSEL1_TMR1SEL_EXT_TRG      (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external trigger */
+#define CLK_CLKSEL1_TMR1SEL_LIRC         (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as LIRC */
+#define CLK_CLKSEL1_TMR1SEL_HIRC         (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as HIRC */
+
+#define CLK_CLKSEL1_TMR2SEL_HXT          (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as HXT */
+#define CLK_CLKSEL1_TMR2SEL_LXT          (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as LXT */
+#define CLK_CLKSEL1_TMR2SEL_PCLK1        (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as PCLK1 */
+#define CLK_CLKSEL1_TMR2SEL_EXT_TRG      (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external trigger */
+#define CLK_CLKSEL1_TMR2SEL_LIRC         (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as LIRC */
+#define CLK_CLKSEL1_TMR2SEL_HIRC         (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as HIRC */
+
+#define CLK_CLKSEL1_TMR3SEL_HXT          (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as HXT */
+#define CLK_CLKSEL1_TMR3SEL_LXT          (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as LXT */
+#define CLK_CLKSEL1_TMR3SEL_PCLK1        (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as PCLK1 */
+#define CLK_CLKSEL1_TMR3SEL_EXT_TRG      (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external trigger */
+#define CLK_CLKSEL1_TMR3SEL_LIRC         (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as LIRC */
+#define CLK_CLKSEL1_TMR3SEL_HIRC         (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as HIRC */
+
+#define CLK_CLKSEL1_UARTSEL_HXT          (0x0UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UART clock source as HXT */
+#define CLK_CLKSEL1_UARTSEL_PLL          (0x1UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UART clock source as PLL */
+#define CLK_CLKSEL1_UARTSEL_LXT          (0x2UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UART clock source as LXT */
+#define CLK_CLKSEL1_UARTSEL_HIRC         (0x3UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UART clock source as HIRC */
+
+#define CLK_CLKSEL1_CLKOSEL_HXT          (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HXT */
+#define CLK_CLKSEL1_CLKOSEL_LXT          (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as LXT */
+#define CLK_CLKSEL1_CLKOSEL_HCLK         (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HCLK */
+#define CLK_CLKSEL1_CLKOSEL_HIRC         (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HIRC */
+
+#define CLK_CLKSEL1_WWDTSEL_PCLK0_DIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WWDT clock source as PCLK0/2048 */
+#define CLK_CLKSEL1_WWDTSEL_LIRC          (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WWDT clock source as LIRC */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKSEL2 constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL2_PWM0SEL_PLL            (0x0UL<<CLK_CLKSEL2_PWM0SEL_Pos) /*!< Setting PWM0 clock source as PLL */
+#define CLK_CLKSEL2_PWM0SEL_PCLK0          (0x1UL<<CLK_CLKSEL2_PWM0SEL_Pos) /*!< Setting PWM0 clock source as PCLK0 */
+
+#define CLK_CLKSEL2_PWM1SEL_PLL            (0x0UL<<CLK_CLKSEL2_PWM1SEL_Pos) /*!< Setting PWM1 clock source as PLL */
+#define CLK_CLKSEL2_PWM1SEL_PCLK1          (0x1UL<<CLK_CLKSEL2_PWM1SEL_Pos) /*!< Setting PWM1 clock source as PCLK1 */
+
+#define CLK_CLKSEL2_SPI0SEL_HXT            (0x0UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as HXT */
+#define CLK_CLKSEL2_SPI0SEL_PLL            (0x1UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PLL */
+#define CLK_CLKSEL2_SPI0SEL_PCLK0          (0x2UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PCLK0 */
+#define CLK_CLKSEL2_SPI0SEL_HIRC           (0x3UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as HIRC */
+
+#define CLK_CLKSEL2_SPI1SEL_HXT            (0x0UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as HXT */
+#define CLK_CLKSEL2_SPI1SEL_PLL            (0x1UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PLL */
+#define CLK_CLKSEL2_SPI1SEL_PCLK1          (0x2UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PCLK1 */
+#define CLK_CLKSEL2_SPI1SEL_HIRC           (0x3UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as HIRC */
+
+#define CLK_CLKSEL2_SPI2SEL_HXT            (0x0UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as HXT */
+#define CLK_CLKSEL2_SPI2SEL_PLL            (0x1UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PLL */
+#define CLK_CLKSEL2_SPI2SEL_PCLK0          (0x2UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PCLK0 */
+#define CLK_CLKSEL2_SPI2SEL_HIRC           (0x3UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as HIRC */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKSEL3 constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL3_SC0SEL_HXT             (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as HXT */
+#define CLK_CLKSEL3_SC0SEL_PLL             (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PLL */
+#define CLK_CLKSEL3_SC0SEL_PCLK0           (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PCLK0 */
+#define CLK_CLKSEL3_SC0SEL_HIRC            (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as HIRC */
+
+#define CLK_CLKSEL3_RTCSEL_LXT             (0x0UL<<CLK_CLKSEL3_RTCSEL_Pos) /*!< Setting RTC clock source as LXT */
+#define CLK_CLKSEL3_RTCSEL_LIRC            (0x1UL<<CLK_CLKSEL3_RTCSEL_Pos) /*!< Setting RTC clock source as LIRC */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKDIV0 constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV0_HCLK(x)     (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 */
+#define CLK_CLKDIV0_USB(x)      (((x)-1) << CLK_CLKDIV0_USBDIV_Pos)  /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 */
+#define CLK_CLKDIV0_UART(x)     (((x)-1) << CLK_CLKDIV0_UARTDIV_Pos) /*!< CLKDIV0 Setting for UART clock divider. It could be 1~16 */
+#define CLK_CLKDIV0_EADC(x)     (((x)-1) << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKDIV1 constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKDIV1_SC0(x)      (((x)-1) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  PLLCTL constant definitions. PLL = FIN * NF / NR / NO                                                  */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PLLCTL_PLLSRC_HXT   0x00000000UL    /*!< For PLL clock source is HXT.  3.2MHz < FIN < 150MHz */
+#define CLK_PLLCTL_PLLSRC_HIRC  0x00080000UL    /*!< For PLL clock source is HIRC. 3.2MHz < FIN < 150MHz */
+
+#define CLK_PLLCTL_NF(x)        ((x)-2)         /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*NF/NR < 500MHz. (FIN*NF/NR > 250MHz is preferred.) */
+#define CLK_PLLCTL_NR(x)        (((x)-2)<<9)    /*!< x must be constant and 2 <= x <= 33.  1.6MHz < FIN/NR < 16MHz */
+
+#define CLK_PLLCTL_NO_1         0x0000UL        /*!< For output divider is 1 */
+#define CLK_PLLCTL_NO_2         0x4000UL        /*!< For output divider is 2 */
+#define CLK_PLLCTL_NO_4         0xC000UL        /*!< For output divider is 4 */
+
+#define CLK_PLLCTL_72MHz_HXT    (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 48) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) */
+#define CLK_PLLCTL_144MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 48) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) */
+#define CLK_PLLCTL_72MHz_HIRC   (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 52) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 71.8848MHz PLL output with HIRC(22.1184MHz IRC) */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  MODULE constant definitions.                                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
+
+#define MODULE_APBCLK(x)        (((x) >>30) & 0x3)    /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
+#define MODULE_CLKSEL(x)        (((x) >>28) & 0x3)    /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
+#define MODULE_CLKSEL_Msk(x)    (((x) >>25) & 0x7)    /*!< Calculate CLKSEL mask offset on MODULE index */
+#define MODULE_CLKSEL_Pos(x)    (((x) >>20) & 0x1f)   /*!< Calculate CLKSEL position offset on MODULE index */
+#define MODULE_CLKDIV(x)        (((x) >>18) & 0x3)    /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1 */
+#define MODULE_CLKDIV_Msk(x)    (((x) >>10) & 0xff)   /*!< Calculate CLKDIV mask offset on MODULE index */
+#define MODULE_CLKDIV_Pos(x)    (((x) >>5 ) & 0x1f)   /*!< Calculate CLKDIV position offset on MODULE index */
+#define MODULE_IP_EN_Pos(x)     (((x) >>0 ) & 0x1f)   /*!< Calculate APBCLK offset on MODULE index */
+#define MODULE_NoMsk            0x0                 /*!< Not mask on MODULE index */
+#define NA                      MODULE_NoMsk        /*!< Not Available */
+
+#define MODULE_APBCLK_ENC(x)        (((x) & 0x03) << 30)   /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
+#define MODULE_CLKSEL_ENC(x)        (((x) & 0x03) << 28)   /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
+#define MODULE_CLKSEL_Msk_ENC(x)    (((x) & 0x07) << 25)   /*!< CLKSEL mask offset on MODULE index */
+#define MODULE_CLKSEL_Pos_ENC(x)    (((x) & 0x1f) << 20)   /*!< CLKSEL position offset on MODULE index */
+#define MODULE_CLKDIV_ENC(x)        (((x) & 0x03) << 18)   /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1 */
+#define MODULE_CLKDIV_Msk_ENC(x)    (((x) & 0xff) << 10)   /*!< CLKDIV mask offset on MODULE index */
+#define MODULE_CLKDIV_Pos_ENC(x)    (((x) & 0x1f) <<  5)   /*!< CLKDIV position offset on MODULE index */
+#define MODULE_IP_EN_Pos_ENC(x)     (((x) & 0x1f) <<  0)   /*!< AHBCLK/APBCLK offset on MODULE index */
+
+
+//AHBCLK
+#define PDMA_MODULE    (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_PDMACKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< PDMA Module */
+
+#define ISP_MODULE     (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_ISPCKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< ISP Module */
+
+#define EBI_MODULE     (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_EBICKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< EBI Module */
+
+#define USBH_MODULE    (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_USBHCKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(4))     /*!< USBH Module */
+
+#define CRC_MODULE     (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_CRCCKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< CRC Module */
+
+
+//APBCLK0
+#define WDT_MODULE     (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< WDT Module */
+
+#define WWDT_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(30)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< WWDT Module */
+
+#define RTC_MODULE     (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_RTCCKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 8)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< RTC Module */
+
+#define TMR0_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR0CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC( 8)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< TMR0 Module */
+
+#define TMR1_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR1CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(12)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< TMR1 Module */
+
+#define TMR2_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR2CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(16)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< TMR2 Module */
+
+#define TMR3_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR3CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(20)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< TMR3 Module */
+
+#define CLKO_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_CLKOCKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(28)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< CLKO Module */
+
+#define ACMP01_MODULE  (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_ACMP01CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< ACMP01 Module */
+
+#define I2C0_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C0CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< I2C0 Module */
+
+#define I2C1_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C1CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< I2C1 Module */
+
+#define SPI0_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI0CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 2)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< SPI0 Module */
+
+#define SPI1_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI1CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 4)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< SPI1 Module */
+
+#define SPI2_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI2CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 6)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< SPI2 Module */
+
+#define UART0_MODULE   (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
+                        MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8))    /*!< UART0 Module */
+
+#define UART1_MODULE   (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART1CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
+                        MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8))    /*!< UART1 Module */
+
+#define UART2_MODULE   (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART2CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
+                        MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8))    /*!< UART2 Module */
+
+#define UART3_MODULE   (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART3CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
+                        MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8))    /*!< UART3 Module */
+
+#define CAN0_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_CAN0CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< CAN0 Module */
+
+#define OTG_MODULE     (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_OTGCKEN_Pos) |\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(4))     /*!< OTG Module */
+
+#define USBD_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_USBDCKEN_Pos) |\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(4))     /*!< USBD Module */
+
+#define EADC_MODULE    (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_EADCCKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC(16))    /*!< EADC Module */
+
+
+//APBCLK1
+#define SC0_MODULE     (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_SC0CKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\
+                        MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC( 0))    /*!< SC0 Module */
+
+#define DAC_MODULE     (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_DACCKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< DAC Module */
+
+#define PWM0_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 0)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< PWM0 Module */
+
+#define PWM1_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM1CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 1)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< PWM1 Module */
+
+#define TK_MODULE      (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_TKCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< TK Module */
+
+
+/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief      Get PLL clock frequency
+  * @param      None
+  * @return     PLL frequency
+  * @details    This function get PLL frequency. The frequency unit is Hz.
+  */
+__STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
+{
+    uint32_t u32PllFreq = 0, u32PllReg;
+    uint32_t u32FIN, u32NF, u32NR, u32NO;
+    uint8_t au8NoTbl[4] = {1, 2, 2, 4};
+
+    u32PllReg = CLK->PLLCTL;
+
+    if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))
+        return 0;           /* PLL is in power down mode or fix low */
+
+    if(u32PllReg & CLK_PLLCTL_PLLSRC_HIRC)
+        u32FIN = __HIRC;    /* PLL source clock from HIRC */
+    else
+        u32FIN = __HXT;     /* PLL source clock from HXT */
+
+    if(u32PllReg & CLK_PLLCTL_BP_Msk)
+        return u32FIN;      /* PLL is in bypass mode */
+
+    /* PLL is output enabled in normal work mode */
+    u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
+    u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2;
+    u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 2;
+
+    /* u32FIN is shifted 2 bits to avoid overflow */
+    u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2);
+
+    return u32PllFreq;
+}
+
+/**
+  * @brief      This function execute delay function.
+  * @param      us  Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
+  *                             72MHz => 233016us, 50MHz => 335544us,
+                                48MHz => 349525us, 28MHz => 699050us ...
+  * @return     None
+  * @details    Use the SysTick to generate the delay time and the unit is in us.
+  *             The SysTick clock source is from HCLK, i.e the same as system core clock.
+  */
+__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
+{
+    SysTick->LOAD = us * CyclesPerUs;
+    SysTick->VAL  = (0x00);
+    SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+
+    /* Waiting for down-count to zero */
+    while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
+    
+    /* Disable SysTick counter */
+    SysTick->CTRL = 0;
+}
+
+
+void CLK_DisableCKO(void);
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
+void CLK_PowerDown(void);
+void CLK_Idle(void);
+uint32_t CLK_GetHXTFreq(void);
+uint32_t CLK_GetLXTFreq(void);
+uint32_t CLK_GetHCLKFreq(void);
+uint32_t CLK_GetPCLK0Freq(void);
+uint32_t CLK_GetPCLK1Freq(void);
+uint32_t CLK_GetCPUFreq(void);
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
+void CLK_EnableXtalRC(uint32_t u32ClkMask);
+void CLK_DisableXtalRC(uint32_t u32ClkMask);
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
+void CLK_DisablePLL(void);
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
+void CLK_DisableSysTick(void);
+
+
+
+/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CLK_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  //__CLK_H__
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_crc.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_crc.c
new file mode 100644
index 00000000000..346a6a5991f
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_crc.c
@@ -0,0 +1,93 @@
+/**************************************************************************//**
+ * @file     crc.c
+ * @version  V3.00
+ * $Revision: 7 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series CRC driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CRC_Driver CRC Driver
+  @{
+*/
+
+/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
+  @{
+*/
+
+/**
+  * @brief      CRC Open
+  *
+  * @param[in]  u32Mode         CRC operation polynomial mode. Valid values are:
+  *                             - \ref CRC_CCITT
+  *                             - \ref CRC_8
+  *                             - \ref CRC_16
+  *                             - \ref CRC_32
+  * @param[in]  u32Attribute    CRC operation data attribute. Valid values are combined with:
+  *                             - \ref CRC_CHECKSUM_COM
+  *                             - \ref CRC_CHECKSUM_RVS
+  *                             - \ref CRC_WDATA_COM
+  *                             - \ref CRC_WDATA_RVS
+  * @param[in]  u32Seed         Seed value.
+  * @param[in]  u32DataLen      CPU Write Data Length. Valid values are:
+  *                             - \ref CRC_CPU_WDATA_8
+  *                             - \ref CRC_CPU_WDATA_16
+  *                             - \ref CRC_CPU_WDATA_32
+  *
+  * @return     None
+  *
+  * @details    This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n
+  *             After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.
+  */
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
+{
+    CRC->SEED = u32Seed;
+    CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;
+
+    /* Setting CRCRST bit will reload the initial seed value(CRC_SEED register) to CRC controller */
+    CRC->CTL |= CRC_CTL_CRCRST_Msk;
+}
+
+/**
+  * @brief      Get CRC Checksum
+  *
+  * @param[in]  None
+  *
+  * @return     Checksum Result
+  *
+  * @details    This macro gets the CRC checksum result by current CRC polynomial mode.
+  */
+uint32_t CRC_GetChecksum(void)
+{
+    switch(CRC->CTL & CRC_CTL_CRCMODE_Msk)
+    {
+        case CRC_CCITT:
+        case CRC_16:
+            return (CRC->CHECKSUM & 0xFFFF);
+
+        case CRC_32:
+            return (CRC->CHECKSUM);
+
+        case CRC_8:
+            return (CRC->CHECKSUM & 0xFF);
+
+        default:
+            return 0;
+    }
+}
+
+/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CRC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_crc.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_crc.h
new file mode 100644
index 00000000000..4c8c3332625
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_crc.h
@@ -0,0 +1,112 @@
+/**************************************************************************//**
+ * @file     crc.h
+ * @version  V3.00
+ * $Revision: 6 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series CRC driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CRC_H__
+#define __CRC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CRC_Driver CRC Driver
+  @{
+*/
+
+/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CRC Polynomial Mode Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CCITT           0x00000000UL            /*!<CRC Polynomial Mode - CCITT */
+#define CRC_8               0x40000000UL            /*!<CRC Polynomial Mode - CRC8 */
+#define CRC_16              0x80000000UL            /*!<CRC Polynomial Mode - CRC16 */
+#define CRC_32              0xC0000000UL            /*!<CRC Polynomial Mode - CRC32 */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Checksum, Write data Constant Definitions                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CHECKSUM_COM    0x08000000UL            /*!<CRC Checksum Complement */
+#define CRC_CHECKSUM_RVS    0x02000000UL            /*!<CRC Checksum Reverse */
+#define CRC_WDATA_COM       0x04000000UL            /*!<CRC Write Data Complement */
+#define CRC_WDATA_RVS       0x01000000UL            /*!<CRC Write Data Reverse */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CPU Write Data Length Constant Definitions                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CPU_WDATA_8     0x00000000UL            /*!<CRC CPU Write Data length is 8-bit */
+#define CRC_CPU_WDATA_16    0x10000000UL            /*!<CRC CPU Write Data length is 16-bit */
+#define CRC_CPU_WDATA_32    0x20000000UL            /*!<CRC CPU Write Data length is 32-bit */
+
+/*@}*/ /* end of group CRC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Set CRC Seed Value
+  *
+  * @param[in]  u32Seed     Seed value
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set CRC seed value.
+  *
+  * @note       User must to perform CRC_RST(CRC_CTL[1] CRC Engine Reset) to reload the new seed value
+  *             to CRC controller.
+  */
+#define CRC_SET_SEED(u32Seed)   { CRC->SEED = (u32Seed); CRC->CTL |= CRC_CTL_CRCRST_Msk; }
+
+/**
+ * @brief       Get CRC Seed Value
+ *
+  * @param      None
+ *
+ * @return      CRC seed value
+ *
+ * @details     This macro gets the current CRC seed value.
+ */
+#define CRC_GET_SEED()          (CRC->SEED)
+
+/**
+ * @brief       CRC Write Data
+ *
+ * @param[in]   u32Data     Write data
+ *
+ * @return      None
+ *
+  * @details    User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.
+ */
+#define CRC_WRITE_DATA(u32Data)   (CRC->DAT = (u32Data))
+
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
+uint32_t CRC_GetChecksum(void);
+
+/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CRC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__CRC_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_dac.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_dac.c
new file mode 100644
index 00000000000..4baffbd8012
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_dac.c
@@ -0,0 +1,94 @@
+/**************************************************************************//**
+ * @file     dac.c
+ * @version  V2.00
+ * $Revision: 8 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series DAC driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup DAC_Driver DAC Driver
+  @{
+*/
+
+/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
+  @{
+*/
+
+/**
+  * @brief This function make DAC module be ready to convert.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M451 Series DAC.
+  * @param[in] u32TrgSrc Decides the trigger source. Valid values are:
+  *                      - \ref DAC_WRITE_DAT_TRIGGER             :Write DAC_DAT trigger
+  *                      - \ref DAC_SOFTWARE_TRIGGER              :Software trigger
+  *                      - \ref DAC_LOW_LEVEL_TRIGGER             :STDAC pin low level trigger
+  *                      - \ref DAC_HIGH_LEVEL_TRIGGER            :STDAC pin high level trigger
+  *                      - \ref DAC_FALLING_EDGE_TRIGGER          :STDAC pin falling edge trigger
+  *                      - \ref DAC_RISING_EDGE_TRIGGER           :STDAC pin rising edge trigger
+  *                      - \ref DAC_TIMER0_TRIGGER                :Timer 0 trigger
+  *                      - \ref DAC_TIMER1_TRIGGER                :Timer 1 trigger
+  *                      - \ref DAC_TIMER2_TRIGGER                :Timer 2 trigger
+  *                      - \ref DAC_TIMER3_TRIGGER                :Timer 3 trigger
+  *                      - \ref DAC_PWM0_TRIGGER                  :PWM0 trigger
+  *                      - \ref DAC_PWM1_TRIGGER                  :PWM1 trigger
+  * @return None
+  * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger.
+  *         When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register.
+  *         When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1,
+  *         external STDAC pin, timer event, or PWM timer event.
+  */
+void DAC_Open(DAC_T *dac,
+              uint32_t u32Ch,
+              uint32_t u32TrgSrc)
+{
+    dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk);
+
+    dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk);
+}
+
+/**
+  * @brief Disable DAC analog power.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M451 Series DAC.
+  * @return None
+  * @details Disable DAC analog power for saving power consumption.
+  */
+void DAC_Close(DAC_T *dac, uint32_t u32Ch)
+{
+    dac->CTL &= (~DAC_CTL_DACEN_Msk);
+}
+
+/**
+  * @brief Set delay time for DAC to become stable.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK*1000000) micro seconds.
+  * @return Real DAC conversion settling time (micro second).
+  * @details For example, DAC controller clock speed is 72MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0x48.
+  * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed.
+  */
+float DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)
+{
+    SystemCoreClockUpdate();
+
+    dac->TCTL = ((SystemCoreClock * u32Delay / 1000000) & 0x3FF);
+
+    return ((dac->TCTL) * 1000000 / SystemCoreClock);
+}
+
+
+
+/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group DAC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_dac.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_dac.h
new file mode 100644
index 00000000000..c0914a3a744
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_dac.h
@@ -0,0 +1,245 @@
+/******************************************************************************
+ * @file     dac.h
+ * @version  V0.10
+ * $Revision: 12 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series DAC driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __DAC_H__
+#define __DAC_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#include "M451Series.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup DAC_Driver DAC Driver
+  @{
+*/
+
+
+/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  DAC_CTL Constant Definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define DAC_CTL_LALIGN_RIGHT_ALIGN   (0UL<<DAC_CTL_LALIGN_Pos)   /*!< Right alignment. */
+#define DAC_CTL_LALIGN_LEFT_ALIGN    (1UL<<DAC_CTL_LALIGN_Pos)   /*!< Left alignment */
+
+#define DAC_WRITE_DAT_TRIGGER      (0UL)    /*!< Write DAC_DAT trigger */
+#define DAC_SOFTWARE_TRIGGER       (0UL|DAC_CTL_TRGEN_Msk)    /*!< Software trigger */
+#define DAC_LOW_LEVEL_TRIGGER      ((0UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< STDAC pin low level trigger */
+#define DAC_HIGH_LEVEL_TRIGGER     ((1UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< STDAC pin high level trigger */
+#define DAC_FALLING_EDGE_TRIGGER   ((2UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< STDAC pin falling edge trigger */
+#define DAC_RISING_EDGE_TRIGGER    ((3UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< STDAC pin rising edge trigger */
+#define DAC_TIMER0_TRIGGER         ((2UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< Timer 0 trigger */
+#define DAC_TIMER1_TRIGGER         ((3UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< Timer 1 trigger */
+#define DAC_TIMER2_TRIGGER         ((4UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< Timer 2 trigger */
+#define DAC_TIMER3_TRIGGER         ((5UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< Timer 3 trigger */
+#define DAC_PWM0_TRIGGER           ((6UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< PWM0 trigger */
+#define DAC_PWM1_TRIGGER           ((7UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk)   /*!< PWM1 trigger */
+
+#define DAC_TRIGGER_MODE_DISABLE   (0UL<<DAC_CTL_TRGEN_Pos)   /*!< Trigger mode disable */
+#define DAC_TRIGGER_MODE_ENABLE    (1UL<<DAC_CTL_TRGEN_Pos)   /*!< Trigger mode enable */
+
+
+/*@}*/ /* end of group DAC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  DAC Macro Definitions                                                                                  */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/**
+  * @brief Start the D/A conversion.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details User writes SWTRG bit (DAC_SWTRG[0]) to generate one shot pulse and it is cleared to 0 by hardware automatically.
+  */
+#define DAC_START_CONV(dac) ((dac)->SWTRG = DAC_SWTRG_SWTRG_Msk)
+
+/**
+  * @brief Enable DAC data left-aligned.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion.
+  */
+#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
+
+/**
+  * @brief Enable DAC data right-aligned.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion.
+  */
+#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
+
+/**
+  * @brief Enable output voltage buffer.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and
+  *         drive external loads directly without having to add an external operational amplifier.
+  */
+#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
+
+/**
+  * @brief Disable output voltage buffer.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details This macro is used to disable output voltage buffer.
+  */
+#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
+
+/**
+  * @brief Enable the interrupt.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M451 Series DAC.
+  * @return None
+  * @details This macro is used to enable DAC interrupt.
+  */
+#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
+
+/**
+  * @brief Disable the interrupt.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M451 Series DAC.
+  * @return None
+  * @details This macro is used to disable DAC interrupt.
+  */
+#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
+
+/**
+  * @brief Enable DMA under-run interrupt.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details This macro is used to enable DMA under-run interrupt.
+  */
+#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
+
+/**
+  * @brief Disable DMA under-run interrupt.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details This macro is used to disable DMA under-run interrupt.
+  */
+#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
+
+/**
+  * @brief Enable PDMA mode.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set.
+  */
+#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
+
+/**
+  * @brief Disable PDMA mode.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details This macro is used to disable DMA mode.
+  */
+#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
+
+/**
+  * @brief Write data for conversion.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M451 Series DAC.
+  * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.
+  * @return None
+  * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
+  *         12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
+  */
+#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data))
+
+/**
+  * @brief Read DAC 12-bit holding data.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M451 Series DAC.
+  * @return Return DAC 12-bit holding data.
+  * @details This macro is used to read DAC_DAT register.
+  */
+#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT)
+
+/**
+  * @brief Get the busy state of DAC.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M451 Series DAC.
+  * @retval 0 Idle state.
+  * @retval 1 Busy state.
+  * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state.
+  */
+#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos)
+
+/**
+  * @brief Get the interrupt flag.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M451 Series DAC.
+  * @retval 0 DAC is in conversion state.
+  * @retval 1 DAC conversion finish.
+  * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag.
+  */
+#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk)
+
+/**
+  * @brief Get the DMA under-run flag.
+  * @param[in] dac Base address of DAC module.
+  * @retval 0 No DMA under-run error condition occurred.
+  * @retval 1 DMA under-run error condition occurred.
+  * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state.
+  */
+#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos)
+
+/**
+  * @brief This macro clear the interrupt status bit.
+  * @param[in] dac Base address of DAC module.
+  * @param[in] u32Ch Not used in M451 Series DAC.
+  * @return None
+  * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag.
+  */
+#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk)
+
+/**
+  * @brief This macro clear the  DMA under-run flag.
+  * @param[in] dac Base address of DAC module.
+  * @return None
+  * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag.
+  */
+#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk)
+
+void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
+void DAC_Close(DAC_T *dac, uint32_t u32Ch);
+float DAC_SetDelayTime(DAC_T *dac, uint32_t u16Delay);
+
+/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group DAC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__DAC_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_eadc.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_eadc.c
new file mode 100644
index 00000000000..741e51dcc0f
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_eadc.c
@@ -0,0 +1,159 @@
+/**************************************************************************//**
+ * @file     eadc.c
+ * @version  V2.00
+ * $Revision: 8 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series EADC driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EADC_Driver EADC Driver
+  @{
+*/
+
+/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
+  @{
+*/
+
+/**
+  * @brief This function make EADC_module be ready to convert.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32InputMode Decides the input mode.
+  *                       - \ref EADC_CTL_DIFFEN_SINGLE_END      :Single end input mode.
+  *                       - \ref EADC_CTL_DIFFEN_DIFFERENTIAL    :Differential input type.
+  * @return None
+  * @details This function is used to set analog input mode and enable A/D Converter.
+  *         Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.
+  * @note
+  */
+void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
+{
+    eadc->CTL &= (~EADC_CTL_DIFFEN_Msk);
+
+    eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk);
+}
+
+/**
+  * @brief Disable EADC_module.
+  * @param[in] eadc The pointer of the specified EADC module..
+  * @return None
+  * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption.
+  */
+void EADC_Close(EADC_T *eadc)
+{
+    eadc->CTL &= ~EADC_CTL_ADCEN_Msk;
+}
+
+/**
+  * @brief Configure the sample control logic module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+  * @param[in] u32TriggerSrc Decides the trigger source. Valid values are:
+  *                            - \ref EADC_SOFTWARE_TRIGGER              : Disable trigger
+  *                            - \ref EADC_FALLING_EDGE_TRIGGER          : STADC pin falling edge trigger
+  *                            - \ref EADC_RISING_EDGE_TRIGGER           : STADC pin rising edge trigger
+  *                            - \ref EADC_FALLING_RISING_EDGE_TRIGGER   : STADC pin both falling and rising edge trigger
+  *                            - \ref EADC_ADINT0_TRIGGER                : ADC ADINT0 interrupt EOC pulse trigger
+  *                            - \ref EADC_ADINT1_TRIGGER                : ADC ADINT1 interrupt EOC pulse trigger
+  *                            - \ref EADC_TIMER0_TRIGGER                : Timer0 overflow pulse trigger
+  *                            - \ref EADC_TIMER1_TRIGGER                : Timer1 overflow pulse trigger
+  *                            - \ref EADC_TIMER2_TRIGGER                : Timer2 overflow pulse trigger
+  *                            - \ref EADC_TIMER3_TRIGGER                : Timer3 overflow pulse trigger
+  *                            - \ref EADC_PWM0TG0_TRIGGER               : PWM0TG0 trigger
+  *                            - \ref EADC_PWM0TG1_TRIGGER               : PWM0TG1 trigger
+  *                            - \ref EADC_PWM0TG2_TRIGGER               : PWM0TG2 trigger
+  *                            - \ref EADC_PWM0TG3_TRIGGER               : PWM0TG3 trigger
+  *                            - \ref EADC_PWM0TG4_TRIGGER               : PWM0TG4 trigger
+  *                            - \ref EADC_PWM0TG5_TRIGGER               : PWM0TG5 trigger
+  *                            - \ref EADC_PWM1TG0_TRIGGER               : PWM1TG0 trigger
+  *                            - \ref EADC_PWM1TG1_TRIGGER               : PWM1TG1 trigger
+  *                            - \ref EADC_PWM1TG2_TRIGGER               : PWM1TG2 trigger
+  *                            - \ref EADC_PWM1TG3_TRIGGER               : PWM1TG3 trigger
+  *                            - \ref EADC_PWM1TG4_TRIGGER               : PWM1TG4 trigger
+  *                            - \ref EADC_PWM1TG5_TRIGGER               : PWM1TG5 trigger
+  * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15.
+  * @return None
+  * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source.
+  *         sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).
+  */
+void EADC_ConfigSampleModule(EADC_T *eadc, \
+                             uint32_t u32ModuleNum, \
+                             uint32_t u32TriggerSrc, \
+                             uint32_t u32Channel)
+{
+    eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk);
+    eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel);
+}
+
+
+/**
+  * @brief Set trigger delay time.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+  * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF.
+  * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are:
+    *                                - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1    : Trigger delay clock frequency is ADC_CLK/1
+    *                                - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2    : Trigger delay clock frequency is ADC_CLK/2
+    *                                - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4    : Trigger delay clock frequency is ADC_CLK/4
+    *                                - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16   : Trigger delay clock frequency is ADC_CLK/16
+  * @return None
+  * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15).
+  *         Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.
+  */
+void EADC_SetTriggerDelayTime(EADC_T *eadc, \
+                              uint32_t u32ModuleNum, \
+                              uint32_t u32TriggerDelayTime, \
+                              uint32_t u32DelayClockDivider)
+{
+    eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk);
+    eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider);
+}
+
+/**
+  * @brief Set ADC internal sample time.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32SampleTime Decides the internal sampling time, the range is from 1~8 ADC clock. Valid value are from 1 to 8.
+  * @return None
+  * @details When A/D operation at high ADC clock rate, the sampling time of analog input voltage may not enough
+  *         if the analog channel has heavy loading to cause fully charge time is longer.
+  *         User can set SMPTSEL (EADC_CTL[18:16]) to select the sampling cycle in ADC.
+  */
+void EADC_SetInternalSampleTime(EADC_T *eadc, uint32_t u32SampleTime)
+{
+    eadc->CTL &= ~EADC_CTL_SMPTSEL_Msk;
+
+    eadc->CTL |= (u32SampleTime - 1) << EADC_CTL_SMPTSEL_Pos;
+
+}
+
+/**
+  * @brief Set ADC extend sample time.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+  * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF.
+  * @return None
+  * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy,
+  *         user can extend A/D sampling time after trigger source is coming to get enough sampling time.
+  */
+void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
+{
+    eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk;
+
+    eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos);
+
+}
+
+/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EADC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_eadc.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_eadc.h
new file mode 100644
index 00000000000..9751d5781d4
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_eadc.h
@@ -0,0 +1,569 @@
+/******************************************************************************
+ * @file     eadc.h
+ * @version  V0.10
+ * $Revision: 18 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series EADC driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __EADC_H__
+#define __EADC_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#include "M451Series.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EADC_Driver EADC Driver
+  @{
+*/
+
+/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  EADC_CTL Constant Definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EADC_CTL_DIFFEN_SINGLE_END          (0UL<<EADC_CTL_DIFFEN_Pos)   /*!< Single-end input mode      */
+#define EADC_CTL_DIFFEN_DIFFERENTIAL        (1UL<<EADC_CTL_DIFFEN_Pos)   /*!< Differential input mode    */
+
+#define EADC_CTL_DMOF_STRAIGHT_BINARY       (0UL<<EADC_CTL_DMOF_Pos)     /*!< Select the straight binary format as the output format of the conversion result   */
+#define EADC_CTL_DMOF_TWOS_COMPLEMENT       (1UL<<EADC_CTL_DMOF_Pos)     /*!< Select the 2's complement format as the output format of the conversion result    */
+
+#define EADC_CTL_SMPTSEL1                   (0UL<<EADC_CTL_SMPTSEL_Pos)   /*!< 1 ADC clock sampling time */
+#define EADC_CTL_SMPTSEL2                   (1UL<<EADC_CTL_SMPTSEL_Pos)   /*!< 2 ADC clock sampling time */
+#define EADC_CTL_SMPTSEL3                   (2UL<<EADC_CTL_SMPTSEL_Pos)   /*!< 3 ADC clock sampling time */
+#define EADC_CTL_SMPTSEL4                   (3UL<<EADC_CTL_SMPTSEL_Pos)   /*!< 4 ADC clock sampling time */
+#define EADC_CTL_SMPTSEL5                   (4UL<<EADC_CTL_SMPTSEL_Pos)   /*!< 5 ADC clock sampling time */
+#define EADC_CTL_SMPTSEL6                   (5UL<<EADC_CTL_SMPTSEL_Pos)   /*!< 6 ADC clock sampling time */
+#define EADC_CTL_SMPTSEL7                   (6UL<<EADC_CTL_SMPTSEL_Pos)   /*!< 7 ADC clock sampling time */
+#define EADC_CTL_SMPTSEL8                   (7UL<<EADC_CTL_SMPTSEL_Pos)   /*!< 8 ADC clock sampling time */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* EADC_SCTL Constant Definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EADC_SCTL_CHSEL(x)                  ((x) << EADC_SCTL_CHSEL_Pos)       /*!< A/D sample module channel selection */
+#define EADC_SCTL_TRGDLYDIV(x)              ((x) << EADC_SCTL_TRGDLYDIV_Pos)   /*!< A/D sample module start of conversion trigger delay clock divider selection */
+#define EADC_SCTL_TRGDLYCNT(x)              ((x) << EADC_SCTL_TRGDLYCNT_Pos)   /*!< A/D sample module start of conversion trigger delay time */
+
+#define EADC_SOFTWARE_TRIGGER               (0UL<<EADC_SCTL_TRGSEL_Pos)      /*!< Software trigger */
+#define EADC_FALLING_EDGE_TRIGGER           (EADC_SCTL_EXTFEN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos))       /*!< STADC pin falling edge trigger */
+#define EADC_RISING_EDGE_TRIGGER            (EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos))       /*!< STADC pin rising edge trigger */
+#define EADC_FALLING_RISING_EDGE_TRIGGER    (EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin both falling and rising edge trigger */
+#define EADC_ADINT0_TRIGGER                 (2UL<<EADC_SCTL_TRGSEL_Pos)      /*!< ADC ADINT0 interrupt EOC pulse trigger */
+#define EADC_ADINT1_TRIGGER                 (3UL<<EADC_SCTL_TRGSEL_Pos)      /*!< ADC ADINT1 interrupt EOC pulse trigger */
+#define EADC_TIMER0_TRIGGER                 (4UL<<EADC_SCTL_TRGSEL_Pos)      /*!< Timer0 overflow pulse trigger */
+#define EADC_TIMER1_TRIGGER                 (5UL<<EADC_SCTL_TRGSEL_Pos)      /*!< Timer1 overflow pulse trigger */
+#define EADC_TIMER2_TRIGGER                 (6UL<<EADC_SCTL_TRGSEL_Pos)      /*!< Timer2 overflow pulse trigger */
+#define EADC_TIMER3_TRIGGER                 (7UL<<EADC_SCTL_TRGSEL_Pos)      /*!< Timer3 overflow pulse trigger */
+#define EADC_PWM0TG0_TRIGGER                (8UL<<EADC_SCTL_TRGSEL_Pos)      /*!< PWM0TG0 trigger */
+#define EADC_PWM0TG1_TRIGGER                (9UL<<EADC_SCTL_TRGSEL_Pos)      /*!< PWM0TG1 trigger */
+#define EADC_PWM0TG2_TRIGGER                (0xAUL<<EADC_SCTL_TRGSEL_Pos)    /*!< PWM0TG2 trigger */
+#define EADC_PWM0TG3_TRIGGER                (0xBUL<<EADC_SCTL_TRGSEL_Pos)    /*!< PWM0TG3 trigger */
+#define EADC_PWM0TG4_TRIGGER                (0xCUL<<EADC_SCTL_TRGSEL_Pos)    /*!< PWM0TG4 trigger */
+#define EADC_PWM0TG5_TRIGGER                (0xDUL<<EADC_SCTL_TRGSEL_Pos)    /*!< PWM0TG5 trigger */
+#define EADC_PWM1TG0_TRIGGER                (0xEUL<<EADC_SCTL_TRGSEL_Pos)    /*!< PWM1TG0 trigger */
+#define EADC_PWM1TG1_TRIGGER                (0xFUL<<EADC_SCTL_TRGSEL_Pos)    /*!< PWM1TG1 trigger */
+#define EADC_PWM1TG2_TRIGGER                (0x10UL<<EADC_SCTL_TRGSEL_Pos)   /*!< PWM1TG2 trigger */
+#define EADC_PWM1TG3_TRIGGER                (0x11UL<<EADC_SCTL_TRGSEL_Pos)   /*!< PWM1TG3 trigger */
+#define EADC_PWM1TG4_TRIGGER                (0x12UL<<EADC_SCTL_TRGSEL_Pos)   /*!< PWM1TG4 trigger */
+#define EADC_PWM1TG5_TRIGGER                (0x13UL<<EADC_SCTL_TRGSEL_Pos)   /*!< PWM1TG5 trigger */
+
+#define EADC_SCTL_TRGDLYDIV_DIVIDER_1       (0<<EADC_SCTL_TRGDLYDIV_Pos)           /*!< Trigger delay clock frequency is ADC_CLK/1 */
+#define EADC_SCTL_TRGDLYDIV_DIVIDER_2       (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos)       /*!< Trigger delay clock frequency is ADC_CLK/2 */
+#define EADC_SCTL_TRGDLYDIV_DIVIDER_4       (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos)       /*!< Trigger delay clock frequency is ADC_CLK/4 */
+#define EADC_SCTL_TRGDLYDIV_DIVIDER_16      (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos)       /*!< Trigger delay clock frequency is ADC_CLK/16 */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* EADC_CMP Constant Definitions                                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EADC_CMP_CMPCOND_LESS_THAN          (0UL<<EADC_CMP_CMPCOND_Pos)   /*!< The compare condition is "less than" */
+#define EADC_CMP_CMPCOND_GREATER_OR_EQUAL   (1UL<<EADC_CMP_CMPCOND_Pos)   /*!< The compare condition is "greater than or equal to" */
+#define EADC_CMP_CMPWEN_ENABLE              (EADC_CMP_CMPWEN_Msk)    /*!< Compare window mode enable */
+#define EADC_CMP_CMPWEN_DISABLE             (~EADC_CMP_CMPWEN_Msk)   /*!< Compare window mode disable */
+#define EADC_CMP_ADCMPIE_ENABLE             (EADC_CMP_ADCMPIE_Msk)   /*!< A/D result compare interrupt enable */
+#define EADC_CMP_ADCMPIE_DISABLE            (~EADC_CMP_ADCMPIE_Msk)  /*!< A/D result compare interrupt disable */
+
+/*@}*/ /* end of group EADC_EXPORTED_CONSTANTS */
+
+/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  EADC Macro Definitions                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/**
+  * @brief A/D Converter Control Circuits Reset.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details ADCRST bit (EADC_CT[1]) remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
+  */
+#define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADRST_Msk)
+
+/**
+  * @brief Enable PDMA transfer.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register,
+  *         user can enable this bit to generate a PDMA data transfer request.
+  * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
+  */
+#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)
+
+/**
+  * @brief Disable PDMA transfer.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable PDMA transfer.
+  */
+#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))
+
+/**
+  * @brief Enable double buffer mode.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
+  * @return None
+  * @details The ADC controller supports a double buffer mode in sample module 0~3.
+  *         If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable.
+  */
+#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)
+
+/**
+  * @brief Disable double buffer mode.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
+  * @return None
+  * @details Sample has one sample result register.
+  */
+#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)
+
+/**
+  * @brief Set ADIFn at A/D end of conversion.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+  * @return None
+  * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion.
+  */
+#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)
+
+/**
+  * @brief Set ADIFn at A/D start of conversion.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+  * @return None
+  * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion.
+  */
+#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)
+
+/**
+  * @brief Enable the interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
+  *                    This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
+  * @return None
+  * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion.
+  *         If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
+  */
+#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
+
+/**
+  * @brief Disable the interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
+  *                    This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
+  * @return None
+  * @details Specific sample module A/D ADINT0 interrupt function Disabled.
+  */
+#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
+
+/**
+  * @brief Enable the sample module interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
+  * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+  *                          This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF.
+  * @return None
+  * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
+  */
+#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
+
+/**
+  * @brief Disable the sample module interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
+  * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+  *                          This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
+  * @return None
+  * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
+  */
+#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))
+
+/**
+  * @brief Set the input mode output format.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Format Decides the output format. Valid values are:
+  *                       - \ref EADC_CTL_DMOF_STRAIGHT_BINARY      :Select the straight binary format as the output format of the conversion result.
+  *                       - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT      :Select the 2's complement format as the output format of the conversion result.
+  * @return None
+  * @details The macro is used to set A/D input mode output format.
+  */
+#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))
+
+/**
+  * @brief Start the A/D conversion.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
+  *                         This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF.
+  *                         Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.
+  * @return None
+  * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.
+  */
+#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
+
+/**
+  * @brief Cancel the conversion for sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
+  *                         This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF.
+  *                         Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18.
+  * @return None
+  * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
+  */
+#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask))
+
+/**
+  * @brief Get the conversion pending flag.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return Return the conversion pending sample module.
+  * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end,
+  *         the STPFn (n=0~18) bit is automatically cleared to 0.
+  */
+#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
+
+/**
+  * @brief Get the conversion data of the user-specified sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+  * @return Return the conversion data of the user-specified sample module.
+  * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.
+  */
+#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)
+
+/**
+  * @brief Get the data overrun flag of the user-specified sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.
+  * @return Return the data overrun flag of the user-specified sample module.
+  * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.
+  */
+#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))
+
+/**
+  * @brief Get the data valid flag of the user-specified sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.
+  * @return Return the data valid flag of the user-specified sample module.
+  * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[1:0]) field to get data overrun status.
+  */
+#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))
+
+/**
+  * @brief Get the double data of the user-specified sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+  * @return Return the double data of the user-specified sample module.
+  * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.
+  */
+#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT_RESULT_Msk)
+
+/**
+  * @brief Get the user-specified interrupt flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status.
+  *                    Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
+  *                    Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
+  * @return Return the user-specified interrupt flags.
+  * @details This macro is used to get the user-specified interrupt flags.
+  */
+#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask))
+
+/**
+  * @brief Get the user-specified sample module overrun flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF.
+  * @return Return the user-specified sample module overrun flags.
+  * @details This macro is used to get the user-specified sample module overrun flags.
+  */
+#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask))
+
+/**
+  * @brief Clear the selected interrupt status bits.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status.
+  *                    Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
+  *                    Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
+  * @return None
+  * @details This macro is used to clear clear the selected interrupt status bits.
+  */
+#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask))
+
+/**
+  * @brief Clear the selected sample module overrun status bits.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status.
+  *                      Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18.
+  * @return None
+  * @details This macro is used to clear the selected sample module overrun status bits.
+  */
+#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask))
+
+/**
+  * @brief Check all sample module A/D result data register overrun flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 None of sample module data register overrun flag is set to 1.
+  * @retval 1 Any one of sample module data register overrun flag is set to 1.
+  * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+  */
+#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)
+
+/**
+  * @brief Check all sample module A/D result data register valid flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 None of sample module data register valid flag is set to 1.
+  * @retval 1 Any one of sample module data register valid flag is set to 1.
+  * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+  */
+#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)
+
+/**
+  * @brief Check all A/D sample module start of conversion overrun flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 None of sample module event overrun flag is set to 1.
+  * @retval 1 Any one of sample module event overrun flag is set to 1.
+  * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+  */
+#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)
+
+/**
+  * @brief Check all A/D interrupt flag overrun bits.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 None of ADINT interrupt flag is overwritten to 1.
+  * @retval 1 Any one of ADINT interrupt flag is overwritten to 1.
+  * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+  */
+#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)
+
+/**
+  * @brief Get the busy state of EADC.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 Idle state.
+  * @retval 1 Busy state.
+  * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state.
+  */
+#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)
+
+/**
+  * @brief Configure the comparator 0 and enable it.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+  * @param[in] u32Condition specifies the compare condition. Valid values are:
+  *                        - \ref EADC_CMP_CMPCOND_LESS_THAN            :The compare condition is "less than the compare value"
+  *                        - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL     :The compare condition is "greater than or equal to the compare value
+  * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+  * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+  * @return None
+  * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
+  *         Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or
+  *         equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+  */
+#define EADC_ENABLE_CMP0(eadc,\
+                         u32ModuleNum,\
+                         u32Condition,\
+                         u16CMPData,\
+                         u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                                                            (u32Condition) |\
+                                                            ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+                                                            (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+                                                            EADC_CMP_ADCMPEN_Msk))
+
+/**
+  * @brief Configure the comparator 1 and enable it.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+  * @param[in] u32Condition specifies the compare condition. Valid values are:
+  *                        - \ref EADC_CMP_CMPCOND_LESS_THAN            :The compare condition is "less than the compare value"
+  *                        - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL     :The compare condition is "greater than or equal to the compare value
+  * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+  * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+  * @return None
+  * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
+  *         Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or
+  *         equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+  */
+#define EADC_ENABLE_CMP1(eadc,\
+                         u32ModuleNum,\
+                         u32Condition,\
+                         u16CMPData,\
+                         u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                                                            (u32Condition) |\
+                                                            ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+                                                            (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+                                                            EADC_CMP_ADCMPEN_Msk))
+
+/**
+  * @brief Configure the comparator 2 and enable it.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+  * @param[in] u32Condition specifies the compare condition. Valid values are:
+  *                        - \ref EADC_CMP_CMPCOND_LESS_THAN            :The compare condition is "less than the compare value"
+  *                        - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL     :The compare condition is "greater than or equal to the compare value
+  * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+  * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+  * @return None
+  * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
+  *         Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or
+  *         equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+  */
+#define EADC_ENABLE_CMP2(eadc,\
+                         u32ModuleNum,\
+                         u32Condition,\
+                         u16CMPData,\
+                         u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                                                            (u32Condition) |\
+                                                            ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+                                                            (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+                                                            EADC_CMP_ADCMPEN_Msk))
+
+/**
+  * @brief Configure the comparator 3 and enable it.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+  * @param[in] u32Condition specifies the compare condition. Valid values are:
+  *                        - \ref EADC_CMP_CMPCOND_LESS_THAN            :The compare condition is "less than the compare value"
+  *                        - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL     :The compare condition is "greater than or equal to the compare value
+  * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+  * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.
+  * @return None
+  * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
+  *         Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or
+  *         equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+  */
+#define EADC_ENABLE_CMP3(eadc,\
+                         u32ModuleNum,\
+                         u32Condition,\
+                         u16CMPData,\
+                         u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                                                            (u32Condition) |\
+                                                            ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+                                                            (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+                                                            EADC_CMP_ADCMPEN_Msk))
+
+/**
+  * @brief Enable the compare window mode.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
+  * @return None
+  * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
+  */
+#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)
+
+/**
+  * @brief Disable the compare window mode.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
+  * @return None
+  * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
+  */
+#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)
+
+/**
+  * @brief Enable the compare interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
+  * @return None
+  * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3)
+  *         and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile,
+  *         if ADCMPIE is set to 1, a compare interrupt request is generated.
+  */
+#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)
+
+/**
+  * @brief Disable the compare interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
+  * @return None
+  * @details This macro is used to disable the compare interrupt.
+  */
+#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)
+
+/**
+  * @brief Disable comparator 0.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable comparator 0.
+  */
+#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0)
+
+/**
+  * @brief Disable comparator 1.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable comparator 1.
+  */
+#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0)
+
+/**
+  * @brief Disable comparator 2.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable comparator 2.
+  */
+#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0)
+
+/**
+  * @brief Disable comparator 3.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable comparator 3.
+  */
+#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0)
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define EADC functions prototype                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
+void EADC_Close(EADC_T *eadc);
+void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSource, uint32_t u32Channel);
+void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider);
+void EADC_SetInternalSampleTime(EADC_T *eadc, uint32_t u32SampleTime);
+void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
+
+/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EADC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__EADC_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_ebi.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_ebi.c
new file mode 100644
index 00000000000..e4d7b7ca2f0
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_ebi.c
@@ -0,0 +1,178 @@
+/**************************************************************************//**
+ * @file     ebi.c
+ * @version  V3.00
+ * $Revision: 9 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series EBI driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EBI_Driver EBI Driver
+  @{
+*/
+
+/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Initialize EBI for specify Bank
+  *
+  * @param[in]  u32Bank             Bank number for EBI. Valid values are:
+  *                                     - \ref EBI_BANK0
+  *                                     - \ref EBI_BANK1
+  * @param[in]  u32DataWidth        Data bus width. Valid values are:
+  *                                     - \ref EBI_BUSWIDTH_8BIT
+  *                                     - \ref EBI_BUSWIDTH_16BIT
+  * @param[in]  u32TimingClass      Default timing configuration. Valid values are:
+  *                                     - \ref EBI_TIMING_FASTEST
+  *                                     - \ref EBI_TIMING_VERYFAST
+  *                                     - \ref EBI_TIMING_FAST
+  *                                     - \ref EBI_TIMING_NORMAL
+  *                                     - \ref EBI_TIMING_SLOW
+  *                                     - \ref EBI_TIMING_VERYSLOW
+  *                                     - \ref EBI_TIMING_SLOWEST
+  * @param[in]  u32BusMode          Enable EBI separate mode. This parameter is current not used.
+  * @param[in]  u32CSActiveLevel    CS is active High/Low. Valid values are:
+  *                                     - \ref EBI_CS_ACTIVE_HIGH
+  *                                     - \ref EBI_CS_ACTIVE_LOW
+  *
+  * @return none
+  *
+  * @details    This function is used to open specify EBI bank with different bus width, timing setting and \n
+  *             active level of CS pin to access EBI device.
+  * @note       Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register.
+  */
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
+{
+    volatile uint32_t *pu32EBICTL  = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10));
+    volatile uint32_t *pu32EBITCTL = (uint32_t *)((uint32_t)&EBI->TCTL0 + (u32Bank * 0x10));
+
+    if(u32DataWidth == EBI_BUSWIDTH_8BIT)
+        *pu32EBICTL &= ~EBI_CTL0_DW16_Msk;
+    else
+        *pu32EBICTL |= EBI_CTL0_DW16_Msk;
+
+    switch(u32TimingClass)
+    {
+        case EBI_TIMING_FASTEST:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+                          (EBI_MCLKDIV_1 << EBI_CTL0_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk;
+            *pu32EBITCTL = 0x0;
+            break;
+
+        case EBI_TIMING_VERYFAST:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+                          (EBI_MCLKDIV_1 << EBI_CTL0_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
+                          (0x3 << EBI_CTL0_TALE_Pos) ;
+            *pu32EBITCTL = 0x03003318;
+            break;
+
+        case EBI_TIMING_FAST:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+                          (EBI_MCLKDIV_2 << EBI_CTL0_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk;
+            *pu32EBITCTL = 0x0;
+            break;
+
+        case EBI_TIMING_NORMAL:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+                          (EBI_MCLKDIV_2 << EBI_CTL0_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
+                          (0x3 << EBI_CTL0_TALE_Pos) ;
+            *pu32EBITCTL = 0x03003318;
+            break;
+
+        case EBI_TIMING_SLOW:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+                          (EBI_MCLKDIV_2 << EBI_CTL0_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
+                          (0x7 << EBI_CTL0_TALE_Pos) ;
+            *pu32EBITCTL = 0x07007738;
+            break;
+
+        case EBI_TIMING_VERYSLOW:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+                          (EBI_MCLKDIV_4 << EBI_CTL0_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
+                          (0x7 << EBI_CTL0_TALE_Pos) ;
+            *pu32EBITCTL = 0x07007738;
+            break;
+
+        case EBI_TIMING_SLOWEST:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+                          (EBI_MCLKDIV_8 << EBI_CTL0_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
+                          (0x7 << EBI_CTL0_TALE_Pos) ;
+            *pu32EBITCTL = 0x07007738;
+            break;
+
+        default:
+            *pu32EBICTL &= ~EBI_CTL0_EN_Msk;
+            break;
+    }
+}
+
+/**
+  * @brief      Disable EBI on specify Bank
+  *
+  * @param[in]  u32Bank     Bank number for EBI. Valid values are:
+  *                             - \ref EBI_BANK0
+  *                             - \ref EBI_BANK1
+  *
+  * @return     none
+  *
+  * @details    This function is used to close specify EBI function.
+  */
+void EBI_Close(uint32_t u32Bank)
+{
+    volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10));
+
+    *pu32EBICTL &= ~EBI_CTL0_EN_Msk;
+}
+
+/**
+  * @brief      Set EBI Bus Timing for specify Bank
+  *
+  * @param[in]  u32Bank             Bank number for EBI. Valid values are:
+  *                                     - \ref EBI_BANK0
+  *                                     - \ref EBI_BANK1
+  * @param[in]  u32TimingConfig     Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting.
+  * @param[in]  u32MclkDiv          Divider for MCLK. Valid values are:
+  *                                     - \ref EBI_MCLKDIV_1
+  *                                     - \ref EBI_MCLKDIV_2
+  *                                     - \ref EBI_MCLKDIV_4
+  *                                     - \ref EBI_MCLKDIV_8
+  *                                     - \ref EBI_MCLKDIV_16
+  *                                     - \ref EBI_MCLKDIV_32
+  *
+  * @return none
+  *
+  * @details    This function is used to configure specify EBI bus timing for access EBI device.
+  */
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
+{
+    volatile uint32_t *pu32EBICTL  = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10));
+    volatile uint32_t *pu32EBITCTL = (uint32_t *)((uint32_t)&EBI->TCTL0 + (u32Bank * 0x10));
+
+    *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL0_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL0_MCLKDIV_Pos);
+    *pu32EBITCTL = u32TimingConfig;
+}
+
+/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EBI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_ebi.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_ebi.h
new file mode 100644
index 00000000000..36af7ff5169
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_ebi.h
@@ -0,0 +1,235 @@
+/**************************************************************************//**
+ * @file     ebi.h
+ * @version  V3.00
+ * $Revision: 8 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series EBI driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EBI_H__
+#define __EBI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EBI_Driver EBI Driver
+  @{
+*/
+
+/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Miscellaneous Constant Definitions                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BANK0_BASE_ADDR     0x60000000UL /*!< EBI bank0 base address */
+#define EBI_BANK1_BASE_ADDR     0x60100000UL /*!< EBI bank1 base address */
+#define EBI_MAX_SIZE            0x00100000UL /*!< Maximum EBI size for each bank is 1 MB */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Constants for EBI bank number                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BANK0               0   /*!< EBI bank 0 */
+#define EBI_BANK1               1   /*!< EBI bank 1 */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Constants for EBI data bus width                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BUSWIDTH_8BIT       8   /*!< EBI bus width is 8-bit */
+#define EBI_BUSWIDTH_16BIT      16  /*!< EBI bus width is 16-bit */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Constants for EBI CS Active Level                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_CS_ACTIVE_LOW       0   /*!< EBI CS active level is low */
+#define EBI_CS_ACTIVE_HIGH      1   /*!< EBI CS active level is high */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Constants for EBI MCLK divider and Timing                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_MCLKDIV_1           0x0UL /*!< EBI output clock(MCLK) is HCLK/1 */
+#define EBI_MCLKDIV_2           0x1UL /*!< EBI output clock(MCLK) is HCLK/2 */
+#define EBI_MCLKDIV_4           0x2UL /*!< EBI output clock(MCLK) is HCLK/4 */
+#define EBI_MCLKDIV_8           0x3UL /*!< EBI output clock(MCLK) is HCLK/8 */
+#define EBI_MCLKDIV_16          0x4UL /*!< EBI output clock(MCLK) is HCLK/16 */
+#define EBI_MCLKDIV_32          0x5UL /*!< EBI output clock(MCLK) is HCLK/32 */
+
+#define EBI_TIMING_FASTEST      0x0UL /*!< EBI timing is the fastest */
+#define EBI_TIMING_VERYFAST     0x1UL /*!< EBI timing is very fast */
+#define EBI_TIMING_FAST         0x2UL /*!< EBI timing is fast */
+#define EBI_TIMING_NORMAL       0x3UL /*!< EBI timing is normal  */
+#define EBI_TIMING_SLOW         0x4UL /*!< EBI timing is slow */
+#define EBI_TIMING_VERYSLOW     0x5UL /*!< EBI timing is very slow */
+#define EBI_TIMING_SLOWEST      0x6UL /*!< EBI timing is the slowest */
+
+/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Read 8-bit data on EBI bank0
+  *
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  *
+  * @return     8-bit Data
+  *
+  * @details    This macro is used to read 8-bit data from specify address on EBI bank0.
+  */
+#define EBI0_READ_DATA8(u32Addr)            (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 8-bit data to EBI bank0
+  *
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 8-bit data to specify address on EBI bank0.
+  */
+#define EBI0_WRITE_DATA8(u32Addr, u32Data)  (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 16-bit data on EBI bank0
+  *
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  *
+  * @return     16-bit Data
+  *
+  * @details    This macro is used to read 16-bit data from specify address on EBI bank0.
+  */
+#define EBI0_READ_DATA16(u32Addr)           (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 16-bit data to EBI bank0
+  *
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 16-bit data to specify address on EBI bank0.
+  */
+#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 32-bit data on EBI bank0
+  *
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  *
+  * @return     32-bit Data
+  *
+  * @details    This macro is used to read 32-bit data from specify address on EBI bank0.
+  */
+#define EBI0_READ_DATA32(u32Addr)           (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 32-bit data to EBI bank0
+  *
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 32-bit data to specify address on EBI bank0.
+  */
+#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 8-bit data on EBI bank1
+  *
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  *
+  * @return     8-bit Data
+  *
+  * @details    This macro is used to read 8-bit data from specify address on EBI bank1.
+  */
+#define EBI1_READ_DATA8(u32Addr)            (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 8-bit data to EBI bank1
+  *
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 8-bit data to specify address on EBI bank1.
+  */
+#define EBI1_WRITE_DATA8(u32Addr, u32Data)  (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 16-bit data on EBI bank1
+  *
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  *
+  * @return     16-bit Data
+  *
+  * @details    This macro is used to read 16-bit data from specify address on EBI bank1.
+  */
+#define EBI1_READ_DATA16(u32Addr)           (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 16-bit data to EBI bank1
+  *
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 16-bit data to specify address on EBI bank1.
+  */
+#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 32-bit data on EBI bank1
+  *
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  *
+  * @return     32-bit Data
+  *
+  * @details    This macro is used to read 32-bit data from specify address on EBI bank1.
+  */
+#define EBI1_READ_DATA32(u32Addr)           (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
+
+/**
+  * @brief      Write 32-bit data to EBI bank1
+  *
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 32-bit data to specify address on EBI bank1.
+  */
+#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
+
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
+void EBI_Close(uint32_t u32Bank);
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
+
+/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EBI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__EBI_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_fmc.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_fmc.c
new file mode 100644
index 00000000000..01fcb84e95b
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_fmc.c
@@ -0,0 +1,320 @@
+/**************************************************************************//**
+ * @file     fmc.c
+ * @version  V3.00
+ * $Revision: 7 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series FMC driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+//* Includes ------------------------------------------------------------------*/
+#include <stdio.h>
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup FMC_Driver FMC Driver
+  @{
+*/
+
+
+/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief      Set boot source from LDROM or APROM after next software reset
+  *
+  * @param[in]  i32BootSrc
+  *                         1: Boot from LDROM,
+  *                         0: Boot from APROM
+  *
+  * @return   None
+  *
+  * @details  This function is used to switch APROM boot or LDROM boot. User need to call
+  *           FMC_SetBootSource to select boot source first, then use CPU reset or
+  *           System Reset Request to reset system.
+  *
+  */
+void FMC_SetBootSource(int32_t i32BootSrc)
+{
+    if(i32BootSrc)
+        FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */
+    else
+        FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */
+}
+
+
+/**
+  * @brief    Disable ISP Functions
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  This function will clear ISPEN bit of ISPCTL to disable ISP function
+  *
+  */
+void FMC_Close(void)
+{
+    FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk;
+}
+
+
+/**
+  * @brief    Disable APROM update function
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Disable APROM update function will forbid APROM programming when boot form APROM.
+  *           APROM update is default to be disable.
+  *
+  */
+void FMC_DisableAPUpdate(void)
+{
+    FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk;
+}
+
+
+/**
+  * @brief    Disable User Configuration update function
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Disable User Configuration update function will forbid User Configuration programming.
+  *           User Configuration update is default to be disable.
+  */
+void FMC_DisableConfigUpdate(void)
+{
+    FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk;
+}
+
+
+/**
+  * @brief    Disable LDROM update function
+  *
+  * @param    None
+  *
+  * @return   None
+
+  * @details  Disable LDROM update function will forbid LDROM programming.
+  *           LDROM update is default to be disable.
+  */
+void FMC_DisableLDUpdate(void)
+{
+    FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk;
+}
+
+
+/**
+  * @brief    Enable APROM update function
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Enable APROM to be able to program when boot from APROM.
+  *
+  */
+void FMC_EnableAPUpdate(void)
+{
+    FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk;
+}
+
+
+/**
+  * @brief    Enable User Configuration update function
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Enable User Configuration to be able to program.
+  *
+  */
+void FMC_EnableConfigUpdate(void)
+{
+    FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk;
+}
+
+
+/**
+  * @brief    Enable LDROM update function
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Enable LDROM to be able to program.
+  *
+  */
+void FMC_EnableLDUpdate(void)
+{
+    FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk;
+}
+
+
+/**
+  * @brief    Get the current boot source
+  *
+  * @param    None
+  *
+  * @retval   0 This chip is currently booting from APROM
+  * @retval   1 This chip is currently booting from LDROM
+  *
+  * @note     This function only show the boot source.
+  *           User need to read ISPSTA register to know if IAP mode supported or not in relative boot.
+  */
+int32_t FMC_GetBootSource(void)
+{
+    if(FMC->ISPCTL & FMC_ISPCTL_BS_Msk)
+        return 1;
+    else
+        return 0;
+}
+
+
+/**
+  * @brief    Enable FMC ISP function
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  ISPEN bit of ISPCTL must be set before we can use ISP commands.
+  *           Therefore, To use all FMC function APIs, user needs to call FMC_Open() first to enable ISP functions.
+  *
+  * @note     ISP functions are write-protected. user also needs to unlock it by calling SYS_UnlockReg() before using all ISP functions.
+  *
+  */
+void FMC_Open(void)
+{
+    FMC->ISPCTL |=  FMC_ISPCTL_ISPEN_Msk;
+}
+
+/**
+  * @brief    Get the base address of Data Flash if enabled.
+  *
+  * @param    None
+  *
+  * @return   The base address of Data Flash
+  *
+  * @details  This function is used to return the base address of Data Flash.
+  *
+  */
+uint32_t FMC_ReadDataFlashBaseAddr(void)
+{
+    return FMC->DFBA;
+}
+
+
+/**
+  * @brief       Read the User Configuration words.
+  *
+  * @param[out]  u32Config  The word buffer to store the User Configuration data.
+  * @param[in]   u32Count   The word count to be read.
+  *
+  * @retval       0 Success
+  * @retval      -1 Failed
+  *
+  * @details     This function is used to read the settings of user configuration.
+  *              if u32Count = 1, Only CONFIG0 will be returned to the buffer specified by u32Config.
+  *              if u32Count = 2, Both CONFIG0 and CONFIG1 will be returned.
+  */
+int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count)
+{
+    int32_t i;
+
+    for(i = 0; i < u32Count; i++)
+        u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4);
+
+    return 0;
+}
+
+
+/**
+  * @brief      Write User Configuration
+  *
+  * @param[in]  u32Config The word buffer to store the User Configuration data.
+  * @param[in]  u32Count The word count to program to User Configuration.
+  *
+  * @retval     0 Success
+  * @retval    -1 Failed
+  *
+  * @details    User must enable User Configuration update before writing it.
+  *             User must erase User Configuration before writing it.
+  *             User Configuration is also be page erase. User needs to backup necessary data
+  *             before erase User Configuration.
+  */
+int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count)
+{
+    int32_t i;
+
+    for(i = 0; i < u32Count; i++)
+    {
+        FMC_Write(FMC_CONFIG_BASE + i * 4, u32Config[i]);
+        if(FMC_Read(FMC_CONFIG_BASE + i * 4) != u32Config[i])
+            return -1;
+    }
+
+    return 0;
+}
+
+/**
+ * @brief      Enable Flash Access Frequency  Optimization Mode
+ *
+ * @param[in]  u32Mode   Optimize flash access cycle mode
+ *             - \ref FMC_FTCTL_OPTIMIZE_DISABLE
+ *             - \ref FMC_FTCTL_OPTIMIZE_12MHZ
+ *             - \ref FMC_FTCTL_OPTIMIZE_36MHZ
+ *             - \ref FMC_FTCTL_OPTIMIZE_60MHZ
+ *             - \ref FMC_FTCTL_OPTIMIZE_72MHZ
+ *
+ * @return     None
+ *
+ * @details    This function will set FOM bit fields of FTCTL register to set flash access frequency optimization mode.
+ *
+ * @note       The flash optimization mode (FOM) bits are write protect.
+ *
+ */
+void FMC_EnableFreqOptimizeMode(uint32_t u32Mode)
+{
+    FMC->FTCTL &= ~FMC_FTCTL_FOM_Msk;
+    FMC->FTCTL |= (u32Mode << FMC_FTCTL_FOM_Pos);
+}
+
+/**
+ * @brief      Disable Flash Access Frequency  Optimization Mode
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will clear FOM bit fields of FTCTL register to disable flash access frequency optimization mode.
+ *
+ * @note       The flash optimization mode (FOM) bits are write protect.
+ *
+ */
+void FMC_DisableFreqOptimizeMode(void)
+{
+    FMC->FTCTL &= ~FMC_FTCTL_FOM_Msk;
+}
+
+/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group FMC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
+
+
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_fmc.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_fmc.h
new file mode 100644
index 00000000000..994c0b311ed
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_fmc.h
@@ -0,0 +1,605 @@
+/**************************************************************************//**
+ * @file     FMC.h
+ * @version  V2.1
+ * $Revision: 19 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 Series Flash Memory Controller Driver Header File
+ *
+ * @note
+ * Copyright (C) 2011~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __FMC_H__
+#define __FMC_H__
+
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup FMC_Driver FMC Driver
+  @{
+*/
+
+/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global constant definitions                                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ISBEN   0
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Base Address                                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_APROM_BASE          0x00000000UL    /*!< APROM  Base Address         */
+#define FMC_LDROM_BASE          0x00100000UL    /*!< LDROM  Base Address         */
+#define FMC_SPROM_BASE          0x00200000UL    /*!< SPROM  Base Address         */
+#define FMC_CONFIG_BASE         0x00300000UL    /*!< CONFIG Base Address         */
+
+#define FMC_CONFIG0_ADDR        (FMC_CONFIG_BASE)       /*!< CONFIG 0 Address */
+#define FMC_CONFIG1_ADDR        (FMC_CONFIG_BASE + 4)   /*!< CONFIG 1 Address */
+
+
+#define FMC_FLASH_PAGE_SIZE     0x800           /*!< Flash Page Size (2048 Bytes) */
+#define FMC_LDROM_SIZE          0x1000          /*!< LDROM Size (4 kBytes)       */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  ISPCTL constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_ISPCTL_BS_LDROM     0x2     /*!< ISPCTL setting to select to boot from LDROM */
+#define FMC_ISPCTL_BS_APROM     0x0     /*!< ISPCTL setting to select to boot from APROM */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  ISPCMD constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_ISPCMD_READ         0x00     /*!< ISP Command: Read Flash               */
+#define FMC_ISPCMD_PROGRAM      0x21     /*!< ISP Command: 32-bit Program Flash     */
+#define FMC_ISPCMD_WRITE_8      0x61     /*!< ISP Command: 64-bit program Flash     */
+#define FMC_ISPCMD_PAGE_ERASE   0x22     /*!< ISP Command: Page Erase Flash         */
+#define FMC_ISPCMD_READ_CID     0x0B     /*!< ISP Command: Read Company ID          */
+#define FMC_ISPCMD_READ_UID     0x04     /*!< ISP Command: Read Unique ID           */
+#define FMC_ISPCMD_READ_DID     0x0C     /*!< ISP Command: Read Device ID           */
+#define FMC_ISPCMD_VECMAP       0x2E     /*!< ISP Command: Set vector mapping       */
+#define FMC_ISPCMD_CHECKSUM     0x0D     /*!< ISP Command: Read Checksum            */
+#define FMC_ISPCMD_CAL_CHECKSUM 0x2D     /*!< ISP Command: Run Check Calculation    */
+#define FMC_ISPCMD_MULTI_PROG   0x27     /*!< ISP Command: Flash Multi-Word Program */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  FTCTL constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_FTCTL_OPTIMIZE_DISABLE      0x00       /*!< Frequency Optimize Mode disable */
+#define FMC_FTCTL_OPTIMIZE_12MHZ        0x01       /*!< Frequency Optimize Mode <= 12Mhz */
+#define FMC_FTCTL_OPTIMIZE_36MHZ        0x02       /*!< Frequency Optimize Mode <= 36Mhz */
+#define FMC_FTCTL_OPTIMIZE_60MHZ        0x04       /*!< Frequency Optimize Mode <= 60Mhz */
+#define FMC_FTCTL_OPTIMIZE_72MHZ        0x05       /*!< Frequency Optimize Mode <= 72Mhz */
+
+/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */
+
+/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  FMC Macro Definitions                                                                                  */
+/*---------------------------------------------------------------------------------------------------------*/
+/**
+ * @brief      Enable ISP Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will set ISPEN bit of ISPCTL control register to enable ISP function.
+ *
+ */
+#define FMC_ENABLE_ISP()          (FMC->ISPCTL |=  FMC_ISPCTL_ISPEN_Msk)  /*!< Enable ISP Function  */
+
+/**
+ * @brief      Disable ISP Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will clear ISPEN bit of ISPCTL control register to disable ISP function.
+ *
+ */
+#define FMC_DISABLE_ISP()         (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk)  /*!< Disable ISP Function */
+
+/**
+ * @brief      Enable LDROM Update Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will set LDUEN bit of ISPCTL control register to enable LDROM update function.
+ *             User needs to set LDUEN bit before they can update LDROM.
+ *
+ */
+#define FMC_ENABLE_LD_UPDATE()    (FMC->ISPCTL |=  FMC_ISPCTL_LDUEN_Msk)  /*!< Enable LDROM Update Function   */
+
+/**
+ * @brief      Disable LDROM Update Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will set ISPEN bit of ISPCTL control register to disable LDROM update function.
+ *
+ */
+#define FMC_DISABLE_LD_UPDATE()   (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk)  /*!< Disable LDROM Update Function  */
+
+/**
+ * @brief      Enable User Configuration Update Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will set CFGUEN bit of ISPCTL control register to enable User Configuration update function.
+ *             User needs to set CFGUEN bit before they can update User Configuration area.
+ *
+ */
+#define FMC_ENABLE_CFG_UPDATE()   (FMC->ISPCTL |=  FMC_ISPCTL_CFGUEN_Msk) /*!< Enable CONFIG Update Function  */
+
+/**
+ * @brief      Disable User Configuration Update Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will clear CFGUEN bit of ISPCTL control register to disable User Configuration update function.
+ *
+ */
+#define FMC_DISABLE_CFG_UPDATE()  (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable CONFIG Update Function */
+
+
+/**
+ * @brief      Enable APROM Update Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will set APUEN bit of ISPCTL control register to enable APROM update function.
+ *             User needs to set APUEN bit before they can update APROM in APROM boot mode.
+ *
+ */
+#define FMC_ENABLE_AP_UPDATE()    (FMC->ISPCTL |=  FMC_ISPCTL_APUEN_Msk)  /*!< Enable APROM Update Function   */
+
+/**
+ * @brief      Disable APROM Update Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will clear APUEN bit of ISPCTL control register to disable APROM update function.
+ *
+ */
+#define FMC_DISABLE_AP_UPDATE()   (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk)  /*!< Disable APROM Update Function  */
+
+/**
+ * @brief      Next Booting Selection function
+ *
+ * @param[in]  x   Booting from APROM(0)/LDROM(1)
+ *
+ * @return     None
+ *
+ * @details    This function will set MCU next booting from LDROM/APROM.
+ *
+ * @note       When use this macro, the Boot Loader booting selection MBS(CONFIG0[5]) must be set.
+ *
+ */
+#define FMC_SELECT_NEXT_BOOT(x)   (FMC->ISPCTL = (FMC->ISPCTL & ~FMC_ISPCTL_BS_Msk) | ((x) << FMC_ISPCTL_BS_Pos)) /*!< Select Next Booting, x = 0 or 1 */
+
+/**
+ * @brief      Get MCU Booting Status
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will get status of chip next booting from LDROM/APROM.
+ *
+ */
+#define FMC_GET_BOOT_STATUS()     ((FMC->ISPCTL & FMC_ISPCTL_BS_Msk)?1:0) /*!< Get MCU Booting Status */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* inline functions                                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+/**
+ * @brief      Program 32-bit data into specified address of flash
+ *
+ * @param[in]  u32Addr  Flash address include APROM, LDROM, Data Flash, and CONFIG
+ * @param[in]  u32Data  32-bit Data to program
+ *
+ * @return     None
+ *
+ * @details    To program word data into Flash include APROM, LDROM, Data Flash, and CONFIG.
+ *             The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
+ *
+ */
+static __INLINE void FMC_Write(uint32_t u32Addr, uint32_t u32Data)
+{
+    FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+    FMC->ISPADDR = u32Addr;
+    FMC->ISPDAT = u32Data;
+    FMC->ISPTRG = 0x1;
+#if ISBEN
+    __ISB();
+#endif
+    while(FMC->ISPTRG);
+}
+
+/**
+ * @brief      Program 64-bit data into specified address of flash
+ *
+ * @param[in]  u32Addr  Flash address include APROM, LDROM, Data Flash, and CONFIG
+ * @param[in]  u32Data0 32-bit Data to program
+ * @param[in]  u32Data1 32-bit Data to program
+ *
+ * @return     None
+ *
+ * @details    To program two words data into Flash include APROM, LDROM, Data Flash, and CONFIG.
+ *             The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
+ *
+ */
+static __INLINE void FMC_Write8(uint32_t u32Addr, uint32_t u32Data0, uint32_t u32Data1)
+{
+    FMC->ISPCMD = FMC_ISPCMD_WRITE_8;
+    FMC->ISPADDR = u32Addr;
+    FMC->MPDAT0 = u32Data0;
+    FMC->MPDAT1 = u32Data1;
+    FMC->ISPTRG = 0x1;
+#if ISBEN
+    __ISB();
+#endif
+    while(FMC->ISPTRG);
+}
+
+
+/**
+ * @brief       Read 32-bit Data from specified address of flash
+ *
+ * @param[in]   u32Addr  Flash address include APROM, LDROM, Data Flash, and CONFIG
+ *
+ * @return      The data of specified address
+ *
+ * @details     To read word data from Flash include APROM, LDROM, Data Flash, and CONFIG.
+ *
+ */
+static __INLINE uint32_t FMC_Read(uint32_t u32Addr)
+{
+    FMC->ISPCMD = FMC_ISPCMD_READ;
+    FMC->ISPADDR = u32Addr;
+    FMC->ISPDAT = 0;
+    FMC->ISPTRG = 0x1;
+#if ISBEN
+    __ISB();
+#endif
+    while(FMC->ISPTRG);
+
+    return FMC->ISPDAT;
+}
+
+/**
+ * @brief      Flash page erase
+ *
+ * @param[in]  u32Addr  Flash address including APROM, LDROM, Data Flash, and CONFIG
+ *
+ * @details    To do flash page erase. The target address could be APROM, LDROM, Data Flash, or CONFIG.
+ *             The page size is 2048 bytes.
+ *
+ * @retval      0 Success
+ * @retval     -1 Erase failed
+ *
+ */
+static __INLINE int32_t FMC_Erase(uint32_t u32Addr)
+{
+    FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+    FMC->ISPADDR = u32Addr;
+    FMC->ISPTRG = 0x1;
+#if ISBEN
+    __ISB();
+#endif
+    while(FMC->ISPTRG);
+
+    /* Check ISPFF flag to know whether erase OK or fail. */
+    if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
+    {
+        FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+        return -1;
+    }
+    return 0;
+}
+
+/**
+ * @brief       Read Unique ID
+ *
+ * @param[in]   u8Index  UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
+ *
+ * @return      The 32-bit unique ID data of specified UID index.
+ *
+ * @details     To read out 96-bit Unique ID.
+ *
+ */
+static __INLINE uint32_t FMC_ReadUID(uint8_t u8Index)
+{
+    FMC->ISPCMD = FMC_ISPCMD_READ_UID;
+    FMC->ISPADDR = (u8Index << 2);
+    FMC->ISPDAT = 0;
+    FMC->ISPTRG = 0x1;
+#if ISBEN
+    __ISB();
+#endif
+    while(FMC->ISPTRG);
+
+    return FMC->ISPDAT;
+}
+
+/**
+  * @brief    Read company ID
+  *
+  * @param    None
+  *
+  * @return   The company ID (32-bit)
+  *
+  * @details  The company ID of Nuvoton is fixed to be 0xDA
+  *
+  */
+static __INLINE uint32_t FMC_ReadCID(void)
+{
+    FMC->ISPCMD = FMC_ISPCMD_READ_CID;           /* Set ISP Command Code */
+    FMC->ISPADDR = 0x0;                          /* Must keep 0x0 when read CID */
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;          /* Trigger to start ISP procedure */
+#if ISBEN
+    __ISB();
+#endif                                    /* To make sure ISP/CPU be Synchronized */
+    while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;  /* Waiting for ISP Done */
+
+    return FMC->ISPDAT;
+}
+
+/**
+  * @brief    Read product ID
+  *
+  * @param    None
+  *
+  * @return   The product ID (32-bit)
+  *
+  * @details  This function is used to read product ID.
+  *
+  */
+static __INLINE uint32_t FMC_ReadPID(void)
+{
+    FMC->ISPCMD = FMC_ISPCMD_READ_DID;          /* Set ISP Command Code */
+    FMC->ISPADDR = 0x04;                         /* Must keep 0x4 when read PID */
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;         /* Trigger to start ISP procedure */
+#if ISBEN
+    __ISB();
+#endif                                     /* To make sure ISP/CPU be Synchronized */
+    while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk);  /* Waiting for ISP Done */
+
+    return FMC->ISPDAT;
+}
+
+/**
+  * @brief      To read UCID
+  *
+  * @param[in]  u32Index    Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
+  *
+  * @return     The UCID of specified index
+  *
+  * @details    This function is used to read unique chip ID (UCID).
+  *
+  */
+static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index)
+{
+    FMC->ISPCMD = FMC_ISPCMD_READ_UID;          /* Set ISP Command Code */
+    FMC->ISPADDR = (0x04 * u32Index) + 0x10;     /* The UCID is at offset 0x10 with word alignment. */
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;         /* Trigger to start ISP procedure */
+#if ISBEN
+    __ISB();
+#endif                                     /* To make sure ISP/CPU be Synchronized */
+    while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk);  /* Waiting for ISP Done */
+
+    return FMC->ISPDAT;
+}
+
+/**
+ * @brief       Set vector mapping address
+ *
+ * @param[in]   u32PageAddr  The page address to remap to address 0x0. The address must be page alignment.
+ *
+ * @return      To set VECMAP to remap specified page address to 0x0.
+ *
+ * @details     This function is used to set VECMAP to map specified page to vector page (0x0).
+ *
+ * @note
+ *              VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
+ *
+ */
+static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
+{
+    FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */
+    FMC->ISPADDR = u32PageAddr;       /* The address of specified page which will be map to address 0x0. It must be page alignment. */
+    FMC->ISPTRG = 0x1;               /* Trigger to start ISP procedure */
+#if ISBEN
+    __ISB();
+#endif                         /* To make sure ISP/CPU be Synchronized */
+    while(FMC->ISPTRG);              /* Waiting for ISP Done */
+}
+
+/**
+ * @brief       Get current vector mapping address.
+ *
+ * @param       None
+ *
+ * @return      The current vector mapping address.
+ *
+ * @details     To get VECMAP value which is the page address for remapping to vector page (0x0).
+ *
+ * @note
+ *              VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
+ *
+ */
+static __INLINE uint32_t FMC_GetVECMAP(void)
+{
+    return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk);
+}
+
+/**
+ * @brief       Get Flash Checksum
+ *
+ * @param[in]   u32Addr    Specific flash start address
+ * @param[in]   i32Size    Specific a size of Flash area
+ *
+ * @return      A checksum value of a flash block.
+ *
+ * @details     To get VECMAP value which is the page address for remapping to vector page (0x0).
+ *
+ */
+static __INLINE uint32_t FMC_GetCheckSum(uint32_t u32Addr, int32_t i32Size)
+{
+    FMC->ISPCMD = FMC_ISPCMD_CAL_CHECKSUM;
+    FMC->ISPADDR = u32Addr;
+    FMC->ISPDAT = i32Size;
+    FMC->ISPTRG = 0x1;
+#if ISBEN
+    __ISB();
+#endif
+    while(FMC->ISPTRG);
+
+    FMC->ISPCMD = FMC_ISPCMD_CHECKSUM;
+    FMC->ISPTRG = 0x1;
+    while(FMC->ISPTRG);
+
+    return FMC->ISPDAT;
+}
+
+/**
+ * @brief      Program Multi-Word data into specified address of flash
+ *
+ * @param[in]  u32Addr  Flash address include APROM, LDROM, Data Flash, and CONFIG
+ * @param[in]  pu32Buf  A data pointer is point to a data buffer start address;
+ *
+ * @return     None
+ *
+ * @details    To program multi-words data into Flash include APROM, LDROM, Data Flash, and CONFIG.
+ *             The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
+ *
+ */
+static __INLINE void FMC_Write256(uint32_t u32Addr, uint32_t *pu32Buf)
+{
+    int32_t i, idx;
+    volatile uint32_t *pu32IspData;
+    //int32_t i32Err;
+
+    //i32Err = 0;
+    idx = 0;
+    FMC->ISPCMD = FMC_ISPCMD_MULTI_PROG;
+    FMC->ISPADDR = u32Addr;
+
+retrigger:
+
+    //if(i32Err)
+    //    printf("idx=%d  ISPADDR = 0x%08x\n",idx, FMC->ISPADDR);
+
+    FMC->MPDAT0 = pu32Buf[idx + 0];
+    FMC->MPDAT1 = pu32Buf[idx + 1];
+    FMC->MPDAT2 = pu32Buf[idx + 2];
+    FMC->MPDAT3 = pu32Buf[idx + 3];
+
+
+
+    FMC->ISPTRG = 0x1;
+
+    pu32IspData = &FMC->MPDAT0;
+    idx += 4;
+
+    for(i = idx; i < 256 / 4; i += 4) // Max data length is 256 bytes (256/4 words)
+    {
+
+        __set_PRIMASK(1); // Mask interrupt to avoid status check coherence error
+        do
+        {
+            if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0)
+            {
+                __set_PRIMASK(0);
+                //printf("%d %x\n", i, FMC->MPADDR);
+                FMC->ISPADDR = FMC->MPADDR & (~0xful);
+                idx = (FMC->ISPADDR - u32Addr) / 4;
+                //i32Err = -1;
+                goto retrigger;
+            }
+        }
+        while(FMC->MPSTS & (3 << FMC_MPSTS_D0_Pos));
+
+        // Update new data for D0
+        pu32IspData[0] = pu32Buf[i  ];
+        pu32IspData[1] = pu32Buf[i + 1];
+
+        do
+        {
+            if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0)
+            {
+                __set_PRIMASK(0);
+                //printf("%d %x\n", i, FMC->MPADDR);
+                FMC->ISPADDR = FMC->MPADDR & (~0xful);
+                idx = (FMC->ISPADDR - u32Addr) / 4;
+                //i32Err = -1;
+                goto retrigger;
+            }
+        }
+        while(FMC->MPSTS & (3 << FMC_MPSTS_D2_Pos));
+
+        // Update new data for D2
+        pu32IspData[2] = pu32Buf[i + 2];
+        pu32IspData[3] = pu32Buf[i + 3];
+        __set_PRIMASK(0);
+    }
+
+    while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk);
+}
+
+void FMC_Open(void);
+void FMC_Close(void);
+void FMC_EnableAPUpdate(void);
+void FMC_DisableAPUpdate(void);
+void FMC_EnableConfigUpdate(void);
+void FMC_DisableConfigUpdate(void);
+void FMC_EnableLDUpdate(void);
+void FMC_DisableLDUpdate(void);
+int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count);
+int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count);
+void FMC_SetBootSource(int32_t i32BootSrc);
+int32_t FMC_GetBootSource(void);
+uint32_t FMC_ReadDataFlashBaseAddr(void);
+void FMC_EnableFreqOptimizeMode(uint32_t u32Mode);
+void FMC_DisableFreqOptimizeMode(void);
+/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group FMC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_gpio.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_gpio.c
new file mode 100644
index 00000000000..7300e4eb9fc
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_gpio.c
@@ -0,0 +1,102 @@
+/**************************************************************************//**
+ * @file     gpio.c
+ * @version  V3.00
+ * $Revision: 6 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series GPIO driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+  @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+  @{
+*/
+
+/**
+ * @brief       Set GPIO operation mode
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC and PD GPIO port.
+ *                          It could be BIT0 ~ BIT14 for PE GPIO port.
+ *                          It could be BIT0 ~ BIT7 for PF GPIO port.
+ * @param[in]   u32Mode     Operation mode.  It could be \n
+ *                          GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_OPEN_DRAIN, GPIO_MODE_QUASI.
+ *
+ * @return      None
+ *
+ * @details     This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+    uint32_t i;
+
+    for(i = 0; i < GPIO_PIN_MAX; i++)
+    {
+        if(u32PinMask & (1 << i))
+        {
+            port->MODE = (port->MODE & ~(0x3 << (i << 1))) | (u32Mode << (i << 1));
+        }
+    }
+}
+
+/**
+ * @brief       Enable GPIO interrupt
+ *
+ * @param[in]   port            GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in]   u32Pin          The pin of specified GPIO port.
+ *                              It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
+ *                              It could be 0 ~ 14 for PE GPIO port.
+ *                              It could be 0 ~ 7 for PF GPIO port.
+ * @param[in]   u32IntAttribs   The interrupt attribute of specified GPIO pin. It could be \n
+ *                              GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
+ *
+ * @return      None
+ *
+ * @details     This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
+{
+    port->INTTYPE |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
+    port->INTEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
+}
+
+
+/**
+ * @brief       Disable GPIO interrupt
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in]   u32Pin      The pin of specified GPIO port.
+ *                          It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
+ *                          It could be 0 ~ 14 for PE GPIO port.
+ *                          It could be 0 ~ 7 for PF GPIO port.
+ *
+ * @return      None
+ *
+ * @details     This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
+{
+    port->INTTYPE &= ~(1UL << u32Pin);
+    port->INTEN &= ~((0x00010001UL) << u32Pin);
+}
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group GPIO_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_gpio.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_gpio.h
new file mode 100644
index 00000000000..37ca98f2754
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_gpio.h
@@ -0,0 +1,439 @@
+/**************************************************************************//**
+ * @file     GPIO.h
+ * @version  V3.00
+ * $Revision: 21 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series GPIO driver header file
+ *
+ * @note
+ * Copyright (C) 2011~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+  @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
+  @{
+*/
+
+
+#define GPIO_PIN_MAX            16 /*!< Specify Maximum Pins of Each GPIO Port */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO_MODE Constant Definitions                                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_MODE_INPUT          0x0UL /*!< Input Mode */
+#define GPIO_MODE_OUTPUT         0x1UL /*!< Output Mode */
+#define GPIO_MODE_OPEN_DRAIN     0x2UL /*!< Open-Drain Mode */
+#define GPIO_MODE_QUASI          0x3UL /*!< Quasi-bidirectional Mode */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO Interrupt Type Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INT_RISING         0x00010000UL /*!< Interrupt enable by Input Rising Edge */
+#define GPIO_INT_FALLING        0x00000001UL /*!< Interrupt enable by Input Falling Edge */
+#define GPIO_INT_BOTH_EDGE      0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
+#define GPIO_INT_HIGH           0x01010000UL /*!< Interrupt enable by Level-High */
+#define GPIO_INT_LOW            0x01000001UL /*!< Interrupt enable by Level-Level */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO_INTTYPE Constant Definitions                                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INTTYPE_EDGE           0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode */
+#define GPIO_INTTYPE_LEVEL          1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO_DBCTL Constant Definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_DBCTL_ICLK_ON            0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset */
+#define GPIO_DBCTL_ICLK_OFF           0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
+
+#define GPIO_DBCTL_DBCLKSRC_LIRC      0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz */
+#define GPIO_DBCTL_DBCLKSRC_HCLK      0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK */
+
+#define GPIO_DBCTL_DBCLKSEL_1         0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks */
+#define GPIO_DBCTL_DBCLKSEL_2         0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks */
+#define GPIO_DBCTL_DBCLKSEL_4         0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks */
+#define GPIO_DBCTL_DBCLKSEL_8         0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks */
+#define GPIO_DBCTL_DBCLKSEL_16        0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks */
+#define GPIO_DBCTL_DBCLKSEL_32        0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks */
+#define GPIO_DBCTL_DBCLKSEL_64        0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks */
+#define GPIO_DBCTL_DBCLKSEL_128       0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks */
+#define GPIO_DBCTL_DBCLKSEL_256       0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks */
+#define GPIO_DBCTL_DBCLKSEL_512       0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks */
+#define GPIO_DBCTL_DBCLKSEL_1024      0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks */
+#define GPIO_DBCTL_DBCLKSEL_2048      0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks */
+#define GPIO_DBCTL_DBCLKSEL_4096      0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks */
+#define GPIO_DBCTL_DBCLKSEL_8192      0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks */
+#define GPIO_DBCTL_DBCLKSEL_16384     0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks */
+#define GPIO_DBCTL_DBCLKSEL_32768     0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks */
+
+
+/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
+   Example 1:
+
+       PA0 = 1;
+
+   It is used to set GPIO PA.0 to high;
+
+   Example 2:
+
+       if (PA0)
+           PA0 = 0;
+
+   If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low.
+ */
+#define GPIO_PIN_DATA(port, pin)    (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
+#define PA0             GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */
+#define PA1             GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */
+#define PA2             GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */
+#define PA3             GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */
+#define PA4             GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */
+#define PA5             GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */
+#define PA6             GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */
+#define PA7             GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */
+#define PA8             GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */
+#define PA9             GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */
+#define PA10            GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output */
+#define PA11            GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output */
+#define PA12            GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output */
+#define PA13            GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output */
+#define PA14            GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output */
+#define PA15            GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output */
+#define PB0             GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */
+#define PB1             GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */
+#define PB2             GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */
+#define PB3             GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */
+#define PB4             GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */
+#define PB5             GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */
+#define PB6             GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */
+#define PB7             GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */
+#define PB8             GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */
+#define PB9             GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */
+#define PB10            GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output */
+#define PB11            GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output */
+#define PB12            GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output */
+#define PB13            GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output */
+#define PB14            GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output */
+#define PB15            GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output */
+#define PC0             GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */
+#define PC1             GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */
+#define PC2             GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */
+#define PC3             GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */
+#define PC4             GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */
+#define PC5             GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */
+#define PC6             GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */
+#define PC7             GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */
+#define PC8             GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */
+#define PC9             GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */
+#define PC10            GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output */
+#define PC11            GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output */
+#define PC12            GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output */
+#define PC13            GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output */
+#define PC14            GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output */
+#define PC15            GPIO_PIN_DATA(2, 15) /*!< Specify PC.15 Pin Data Input/Output */
+#define PD0             GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */
+#define PD1             GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */
+#define PD2             GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */
+#define PD3             GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */
+#define PD4             GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */
+#define PD5             GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */
+#define PD6             GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */
+#define PD7             GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */
+#define PD8             GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */
+#define PD9             GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */
+#define PD10            GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output */
+#define PD11            GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output */
+#define PD12            GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output */
+#define PD13            GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output */
+#define PD14            GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output */
+#define PD15            GPIO_PIN_DATA(3, 15) /*!< Specify PD.15 Pin Data Input/Output */
+#define PE0             GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */
+#define PE1             GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */
+#define PE2             GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */
+#define PE3             GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */
+#define PE4             GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */
+#define PE5             GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */
+#define PE6             GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */
+#define PE7             GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */
+#define PE8             GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */
+#define PE9             GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */
+#define PE10            GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output */
+#define PE11            GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output */
+#define PE12            GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output */
+#define PE13            GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output */
+#define PE14            GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output */
+#define PF0             GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */
+#define PF1             GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */
+#define PF2             GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */
+#define PF3             GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */
+#define PF4             GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */
+#define PF5             GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */
+#define PF6             GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */
+#define PF7             GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+  @{
+*/
+
+/**
+ * @brief       Clear GPIO Pin Interrupt Flag
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ *                          It could be BIT0 ~ BIT14 for PE.
+ *                          It could be BIT0 ~ BIT7 for PF.
+ *
+ * @return      None
+ *
+ * @details     Clear the interrupt status of specified GPIO pin.
+ */
+#define GPIO_CLR_INT_FLAG(port, u32PinMask)         ((port)->INTSRC = (u32PinMask))
+
+/**
+ * @brief       Disable Pin De-bounce Function
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ *                          It could be BIT0 ~ BIT14 for PE.
+ *                          It could be BIT0 ~ BIT7 for PF.
+ *
+ * @return      None
+ *
+ * @details     Disable the interrupt de-bounce function of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask)     ((port)->DBEN &= ~(u32PinMask))
+
+/**
+ * @brief       Enable Pin De-bounce Function
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ *                          It could be BIT0 ~ BIT14 for PE.
+ *                          It could be BIT0 ~ BIT7 for PF.
+ * @return      None
+ *
+ * @details     Enable the interrupt de-bounce function of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask)      ((port)->DBEN |= (u32PinMask))
+
+/**
+ * @brief       Disable I/O Digital Input Path
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ *                          It could be BIT0 ~ BIT14 for PE.
+ *                          It could be BIT0 ~ BIT7 for PF.
+ *
+ * @return      None
+ *
+ * @details     Disable I/O digital input path of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))
+
+/**
+ * @brief       Enable I/O Digital Input Path
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ *                          It could be BIT0 ~ BIT14 for PE.
+ *                          It could be BIT0 ~ BIT7 for PF.
+ *
+ * @return      None
+ *
+ * @details     Enable I/O digital input path of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask)  ((port)->DINOFF &= ~((u32PinMask)<<16))
+
+/**
+ * @brief       Disable I/O DOUT mask
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ *                          It could be BIT0 ~ BIT14 for PE.
+ *                          It could be BIT0 ~ BIT7 for PF.
+ *
+ * @return      None
+ *
+ * @details     Disable I/O DOUT mask of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask)    ((port)->DATMSK &= ~(u32PinMask))    
+
+/**
+ * @brief       Enable I/O DOUT mask
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ *                          It could be BIT0 ~ BIT14 for PE.
+ *                          It could be BIT0 ~ BIT7 for PF.
+ *
+ * @return      None
+ *
+ * @details     Enable I/O DOUT mask of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))
+
+/**
+ * @brief       Get GPIO Pin Interrupt Flag
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port.
+ *                          It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ *                          It could be BIT0 ~ BIT14 for PE.
+ *                          It could be BIT0 ~ BIT7 for PF.
+ *
+ * @retval      0           No interrupt at specified GPIO pin
+ * @retval      1           The specified GPIO pin generate an interrupt
+ *
+ * @details     Get the interrupt status of specified GPIO pin.
+ */
+#define GPIO_GET_INT_FLAG(port, u32PinMask)     ((port)->INTSRC & (u32PinMask))
+
+/**
+ * @brief       Set De-bounce Sampling Cycle Time
+ *
+ * @param[in]   u32ClkSrc   The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC.
+ * @param[in]   u32ClkSel   The de-bounce sampling cycle selection. It could be
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_1
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_2 
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_4 
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_8
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_16 
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_32 
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_64 
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_128
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_256 
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_512 
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_1024 
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_2048
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_4096 
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_8192 
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_16384 
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_32768
+ *
+ * @return      None
+ *
+ * @details     Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
+ *              Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n
+ *              It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
+ *              Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us,
+ *              and system will sampling interrupt input once per 00 us.
+ */
+#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel)    (GPIO->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel)))
+
+/**
+ * @brief       Get GPIO Port IN Data
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ *
+ * @return      The specified port data
+ *
+ * @details     Get the PIN register of specified GPIO port.
+ */
+#define GPIO_GET_IN_DATA(port)  ((port)->PIN)
+
+/**
+ * @brief       Set GPIO Port OUT Data
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in]   u32Data     GPIO port data.
+ *
+ * @return      None
+ *
+ * @details     Set the Data into specified GPIO port.
+ */
+#define GPIO_SET_OUT_DATA(port, u32Data)    ((port)->DOUT = (u32Data))
+
+/**
+ * @brief       Toggle Specified GPIO pin
+ *
+ * @param[in]   u32Pin      Pxy
+ *
+ * @return      None
+ *
+ * @details     Toggle the specified GPIO pint.
+ */
+#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
+
+
+/**
+* @brief       Enable External GPIO interrupt
+*
+* @param[in]   port            GPIO port. It could be PA, PB, PC, PD, PE or PF.
+* @param[in]   u32Pin          The pin of specified GPIO port.
+*                              It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
+*                              It could be 0 ~ 14 for PE GPIO port.
+*                              It could be 0 ~ 7 for PF GPIO port.
+* @param[in]   u32IntAttribs   The interrupt attribute of specified GPIO pin. It could be \n
+*                              GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
+*
+* @return      None
+*
+* @details     This function is used to enable specified GPIO pin interrupt.
+*/
+#define GPIO_EnableEINT     GPIO_EnableInt
+
+/**
+* @brief       Disable External GPIO interrupt
+*
+* @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE or PF.
+* @param[in]   u32Pin      The pin of specified GPIO port.
+*                          It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
+*                          It could be 0 ~ 14 for PE GPIO port.
+*                          It could be 0 ~ 7 for PF GPIO port.
+*
+* @return      None
+*
+* @details     This function is used to enable specified GPIO pin interrupt.
+*/
+#define GPIO_DisableEINT    GPIO_DisableInt
+
+
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group GPIO_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __GPIO_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_i2c.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_i2c.c
new file mode 100644
index 00000000000..ad77a32c20f
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_i2c.c
@@ -0,0 +1,612 @@
+/**************************************************************************//**
+ * @file     i2c.c
+ * @version  V3.00
+ * $Revision: 23 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series I2C driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup I2C_Driver I2C Driver
+  @{
+*/
+
+
+/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Enable specify I2C Controller and set Clock Divider
+  *
+  * @param[in]  i2c         Specify I2C port
+  * @param[in]  u32BusClock The target I2C bus clock in Hz
+  *
+  * @return     Actual I2C bus clock frequency
+  *
+  * @details    The function enable the specify I2C Controller and set proper Clock Divider
+  *             in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock.
+  *             I2C Bus clock = PCLK / (4*(divider+1).
+  *
+  */
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
+{
+    uint32_t u32Div;
+
+    u32Div = (uint32_t)(((SystemCoreClock * 10) / (u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
+    i2c->CLKDIV = u32Div;
+
+    /* Enable I2C */
+    i2c->CTL |= I2C_CTL_I2CEN_Msk;
+
+    return (SystemCoreClock / ((u32Div + 1) << 2));
+}
+
+/**
+  * @brief      Disable specify I2C Controller
+  *
+  * @param[in]  i2c         Specify I2C port
+    *
+  * @return     None
+  *
+  * @details    Reset I2C Controller and disable specify I2C port.
+    *
+  */
+
+void I2C_Close(I2C_T *i2c)
+{
+    /* Reset I2C Controller */
+    if((uint32_t)i2c == I2C0_BASE)
+    {
+        SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk;
+    }
+    else if((uint32_t)i2c == I2C1_BASE)
+    {
+        SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk;
+    }
+
+    /* Disable I2C */
+    i2c->CTL &= ~I2C_CTL_I2CEN_Msk;
+}
+
+/**
+  * @brief      Clear Time-out Counter flag
+  *
+  * @param[in]  i2c         Specify I2C port
+    *
+  * @return     None
+  *
+  * @details    When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag .
+    *
+  */
+void I2C_ClearTimeoutFlag(I2C_T *i2c)
+{
+    i2c->TOCTL |= I2C_TOCTL_TOIF_Msk;
+}
+
+/**
+  * @brief      Set Control bit of I2C Controller
+  *
+  * @param[in]  i2c         Specify I2C port
+  * @param[in]  u8Start     Set I2C START condition
+  * @param[in]  u8Stop      Set I2C STOP condition
+  * @param[in]  u8Si        Clear SI flag
+  * @param[in]  u8Ack       Set I2C ACK bit
+  *
+  * @return     None
+  *
+  * @details    The function set I2C Control bit of I2C Bus protocol.
+  *
+  */
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
+{
+    uint32_t u32Reg = 0;
+
+    if(u8Start)
+        u32Reg |= I2C_CTL_STA;
+    if(u8Stop)
+        u32Reg |= I2C_CTL_STO;
+    if(u8Si)
+        u32Reg |= I2C_CTL_SI;
+    if(u8Ack)
+        u32Reg |= I2C_CTL_AA;
+
+    i2c->CTL = (i2c->CTL & ~0x3C) | u32Reg;
+}
+
+/**
+  * @brief      Disable Interrupt of I2C Controller
+  *
+  * @param[in]  i2c         Specify I2C port
+  *
+  * @return     None
+  *
+  * @details    The function is used for disable I2C interrupt
+  *
+  */
+void I2C_DisableInt(I2C_T *i2c)
+{
+    i2c->CTL &= ~I2C_CTL_INTEN_Msk;
+}
+
+/**
+  * @brief      Enable Interrupt of I2C Controller
+  *
+  * @param[in]  i2c         Specify I2C port
+  *
+  * @return     None
+  *
+  * @details    The function is used for enable I2C interrupt
+  *
+  */
+void I2C_EnableInt(I2C_T *i2c)
+{
+    i2c->CTL |= I2C_CTL_INTEN_Msk;
+}
+
+/**
+ * @brief      Get I2C Bus Clock
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     The actual I2C Bus clock in Hz
+ *
+ * @details    To get the actual I2C Bus Clock frequency.
+ */
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
+{
+    uint32_t u32Divider = i2c->CLKDIV;
+
+    return (SystemCoreClock / ((u32Divider + 1) << 2));
+}
+
+/**
+ * @brief      Set I2C Bus Clock
+ *
+ * @param[in]  i2c          Specify I2C port
+ * @param[in]  u32BusClock  The target I2C Bus Clock in Hz
+ *
+ * @return     The actual I2C Bus Clock in Hz
+ *
+ * @details    To set the actual I2C Bus Clock frequency.
+ */
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
+{
+    uint32_t u32Div;
+
+    u32Div = (uint32_t)(((SystemCoreClock * 10) / (u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
+    i2c->CLKDIV = u32Div;
+
+    return (SystemCoreClock / ((u32Div + 1) << 2));
+}
+
+/**
+ * @brief      Get Interrupt Flag
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     I2C interrupt flag status
+ *
+ * @details    To get I2C Bus interrupt flag.
+ */
+uint32_t I2C_GetIntFlag(I2C_T *i2c)
+{
+    return ((i2c->CTL & I2C_CTL_SI_Msk) == I2C_CTL_SI_Msk ? 1 : 0);
+}
+
+/**
+ * @brief      Get I2C Bus Status Code
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     I2C Status Code
+ *
+ * @details    To get I2C Bus Status Code.
+ */
+uint32_t I2C_GetStatus(I2C_T *i2c)
+{
+    return (i2c->STATUS);
+}
+
+/**
+ * @brief      Read a Byte from I2C Bus
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     I2C Data
+ *
+ * @details    To read a bytes data from specify I2C port.
+ */
+uint8_t I2C_GetData(I2C_T *i2c)
+{
+    return (i2c->DAT);
+}
+
+/**
+ * @brief      Send a byte to I2C Bus
+ *
+ * @param[in]  i2c          Specify I2C port
+ * @param[in]  u8Data       The data to send to I2C bus
+ *
+ * @return     None
+ *
+ * @details    This function is used to write a byte to specified I2C port
+ */
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
+{
+    i2c->DAT = u8Data;
+}
+
+/**
+ * @brief      Set 7-bit Slave Address and GC Mode
+ *
+ * @param[in]  i2c          Specify I2C port
+ * @param[in]  u8SlaveNo    Set the number of I2C address register (0~3)
+ * @param[in]  u8SlaveAddr  7-bit slave address
+ * @param[in]  u8GCMode     Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE)
+ *
+ * @return     None
+ *
+ * @details    This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3)
+ *             and enable GC Mode.
+ *
+ */
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
+{
+    switch(u8SlaveNo)
+    {
+        case 1:
+            i2c->ADDR1  = (u8SlaveAddr << 1) | u8GCMode;
+            break;
+        case 2:
+            i2c->ADDR2  = (u8SlaveAddr << 1) | u8GCMode;
+            break;
+        case 3:
+            i2c->ADDR3  = (u8SlaveAddr << 1) | u8GCMode;
+            break;
+        case 0:
+        default:
+            i2c->ADDR0  = (u8SlaveAddr << 1) | u8GCMode;
+            break;
+    }
+}
+
+/**
+ * @brief      Configure the mask bits of 7-bit Slave Address
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8SlaveNo        Set the number of I2C address mask register (0~3)
+ * @param[in]  u8SlaveAddrMask  A byte for slave address mask
+ *
+ * @return     None
+ *
+ * @details    This function is used to set 7-bit slave addresses.
+ *
+ */
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
+{
+    switch(u8SlaveNo)
+    {
+        case 1:
+            i2c->ADDRMSK1  = u8SlaveAddrMask << 1;
+            break;
+        case 2:
+            i2c->ADDRMSK2  = u8SlaveAddrMask << 1;
+            break;
+        case 3:
+            i2c->ADDRMSK3  = u8SlaveAddrMask << 1;
+            break;
+        case 0:
+        default:
+            i2c->ADDRMSK0  = u8SlaveAddrMask << 1;
+            break;
+    }
+}
+
+/**
+ * @brief      Enable Time-out Counter Function and support Long Time-out
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8LongTimeout    Configure DIV4 to enable Long Time-out (0/1)
+ *
+ * @return     None
+ *
+ * @details    This function enable Time-out Counter function and configure DIV4 to support Long
+ *             Time-out.
+ *
+ */
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
+{
+    if(u8LongTimeout)
+        i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk;
+    else
+        i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk;
+
+    i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+}
+
+/**
+ * @brief      Disable Time-out Counter Function
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    To disable Time-out Counter function in I2CTOC register.
+ *
+ */
+void I2C_DisableTimeout(I2C_T *i2c)
+{
+    i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+}
+
+/**
+ * @brief      Enable I2C Wake-up Function
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    To enable Wake-up function of I2C Wake-up control register.
+ *
+ */
+void I2C_EnableWakeup(I2C_T *i2c)
+{
+    i2c->WKCTL |= I2C_WKCTL_WKEN_Msk;
+}
+
+/**
+ * @brief      Disable I2C Wake-up Function
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    To disable Wake-up function of I2C Wake-up control register.
+ *
+ */
+void I2C_DisableWakeup(I2C_T *i2c)
+{
+    i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk;
+}
+
+/**
+ * @brief      To get SMBus Status
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     SMBus status
+ *
+ * @details    To get the Bus Management status of I2C_BUSSTS register
+ *
+ */
+uint32_t I2C_SMBusGetStatus(I2C_T *i2c)
+{
+    return (i2c->BUSSTS);
+}
+
+/**
+ * @brief      Clear SMBus Interrupt Flag
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8SMBusIntFlag   Specify SMBus interrupt flag
+ *
+ * @return     None
+ *
+ * @details    To clear flags of I2C_BUSSTS status register if interrupt set.
+ *
+ */
+void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag)
+{
+    i2c->BUSSTS |= u8SMBusIntFlag;
+}
+
+/**
+ * @brief      Set SMBus Bytes Counts of Transmission or Reception
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u32PktSize       Transmit / Receive bytes
+ *
+ * @return     None
+ *
+ * @details    The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
+ *
+ */
+void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize)
+{
+    i2c->PKTSIZE = u32PktSize;
+}
+
+/**
+ * @brief      Init SMBus Host/Device Mode
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8HostDevice     Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0))
+ *
+ * @return     None
+ *
+ * @details    Using SMBus communication must specify the port is a Host or a Device.
+ *
+ */
+void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice)
+{
+    /* Clear  BMHEN, BMDEN of BUSCTL Register */
+    i2c->BUSCTL &=  ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk);
+
+    /* Set SMBus Host/Device Mode, and enable Bus Management*/
+    if(u8HostDevice == I2C_SMBH_ENABLE)
+        i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk);
+    else
+        i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk);
+}
+
+/**
+ * @brief      Disable SMBus function
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode.
+ *
+ */
+void I2C_SMBusClose(I2C_T *i2c)
+{
+
+    i2c->BUSCTL = 0x00;
+}
+
+/**
+ * @brief      Enable SMBus PEC Transmit Function
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8PECTxEn        CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE)
+ *
+ * @return     None
+ *
+ * @details    When enable CRC check function, the Host or Device needs to transmit CRC byte.
+ *
+ */
+void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn)
+{
+    i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk;
+
+    if(u8PECTxEn)
+        i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk);
+    else
+        i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk;
+}
+
+/**
+ * @brief      Get SMBus CRC value
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     A byte is packet error check value
+ *
+ * @details    The CRC check value after a transmission or a reception by count by using CRC8
+ *
+ */
+uint8_t I2C_SMBusGetPECValue(I2C_T *i2c)
+{
+    return i2c->PKTCRC;
+}
+
+/**
+ * @brief      Calculate Time-out of SMBus idle period
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  us               Time-out length(us)
+ * @param[in]  u32Hclk          I2C peripheral clock frequency
+ *
+ * @return     None
+ *
+ * @details    This function is used to set SMBus Time-out length when bus is in Idle state.
+ *
+ */
+
+void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk)
+{
+    uint32_t  u32Div, u32Hclk_kHz;
+
+    i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk;
+    u32Hclk_kHz = u32Hclk / 1000;
+    u32Div = (((us * u32Hclk_kHz) / 1000) >> 2) - 1;
+    if(u32Div > 255)
+    {
+        i2c->BUSTOUT = 0xFF;
+    }
+    else
+    {
+        i2c->BUSTOUT = u32Div;
+    }
+
+}
+
+/**
+ * @brief      Calculate Time-out of SMBus active period
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  ms               Time-out length(ms)
+ * @param[in]  u32Pclk          peripheral clock frequency
+ *
+ * @return     None
+ *
+ * @details    This function is used to set SMBus Time-out length when bus is in active state.
+ *             Time-out length is calculate the SCL line "one clock" pull low timing.
+ *
+ */
+
+void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
+{
+    uint32_t u32Div, u32Pclk_kHz;
+
+    i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
+
+    /* DIV4 disabled */
+    i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+    u32Pclk_kHz = u32Pclk / 1000;
+    u32Div = ((ms * u32Pclk_kHz) / (16 * 1024)) - 1;
+    if(u32Div <= 0xFF)
+    {
+        i2c->BUSTOUT = u32Div;
+        return;
+    }
+
+    /* DIV4 enabled */
+    i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+
+    i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16 * 1024 * 4)) - 1) & 0xFF; //The max value is 255
+}
+
+/**
+ * @brief      Calculate Cumulative Clock low Time-out of SMBus active period
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  ms               Time-out length(ms)
+ * @param[in]  u32Pclk          peripheral clock frequency
+ *
+ * @return     None
+ *
+ * @details    This function is used to set SMBus Time-out length when bus is in Active state.
+ *             Time-out length is calculate the SCL line "clocks" low cumulative timing.
+ *
+ */
+
+void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
+{
+    uint32_t u32Div, u32Pclk_kHz;
+
+    i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
+
+    /* DIV4 disabled */
+    i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+    u32Pclk_kHz = u32Pclk / 1000;
+    u32Div = ((ms * u32Pclk_kHz) / (16 * 1024)) - 1;
+    if(u32Div <= 0xFF)
+    {
+        i2c->CLKTOUT = u32Div;
+        return;
+    }
+
+    /* DIV4 enabled */
+    i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+    i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16 * 1024 * 4)) - 1) & 0xFF; //The max value is 255
+}
+
+/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group I2C_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_i2c.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_i2c.h
new file mode 100644
index 00000000000..3d30c66b74d
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_i2c.h
@@ -0,0 +1,415 @@
+/**************************************************************************//**
+ * @file     I2C.h
+ * @version  V3.0
+ * $Revision: 19 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 Series I2C Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __I2C_H__
+#define __I2C_H__
+
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup I2C_Driver I2C Driver
+  @{
+*/
+
+/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  I2C_CTL constant definitions.                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define I2C_CTL_STA_STO_SI        0x38UL /*!< I2C_CTL setting for I2C control bits. It would set STA, STO and SI bits     */
+#define I2C_CTL_STA_STO_SI_AA     0x3CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, STO, SI and AA bits */
+#define I2C_CTL_STA_SI            0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits          */
+#define I2C_CTL_STA_SI_AA         0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits      */
+#define I2C_CTL_STO_SI            0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits          */
+#define I2C_CTL_STO_SI_AA         0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits      */
+#define I2C_CTL_SI                0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit                   */
+#define I2C_CTL_SI_AA             0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits           */
+#define I2C_CTL_STA               0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit                  */
+#define I2C_CTL_STO               0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit                  */
+#define I2C_CTL_AA                0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit                   */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  I2C GCMode constant definitions.                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define I2C_GCMODE_ENABLE           1    /*!< Enable  I2C GC Mode                                                         */
+#define I2C_GCMODE_DISABLE          0    /*!< Disable I2C GC Mode                                                         */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  I2C SMBUS constant definitions.                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define I2C_SMBH_ENABLE             1    /*!< Enable  SMBus Host Mode enable                                              */
+#define I2C_SMBD_ENABLE             0    /*!< Enable  SMBus Device Mode enable                                            */
+#define I2C_PECTX_ENABLE            1    /*!< Enable  SMBus Packet Error Check Transmit function                          */
+#define I2C_PECTX_DISABLE           0    /*!< Disable SMBus Packet Error Check Transmit function                          */
+
+/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */
+
+/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
+  @{
+*/
+/**
+ *    @brief        The macro is used to set I2C bus condition at One Time
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *    @param[in]    u8Ctrl     A byte writes to I2C control register
+ *
+ *    @return       None
+ *
+ *    @details      Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
+ */
+#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL = ((i2c)->CTL & ~0x3c) | (u8Ctrl))
+
+/**
+ *    @brief        The macro is used to set START condition of I2C Bus
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       None
+ *
+ *    @details      Set the I2C bus START condition in I2C_CTL register.
+ */
+#define I2C_START(i2c)  ((i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk)
+
+/**
+ *    @brief        The macro is used to wait I2C bus status get ready
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       None
+ *
+ *    @details      When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
+ */
+#define I2C_WAIT_READY(i2c)     while(!((i2c)->CTL & I2C_CTL_SI_Msk))
+
+/**
+ *    @brief        The macro is used to Read I2C Bus Data Register
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       A byte of I2C data register
+ *
+ *    @details      I2C controller read data from bus and save it in I2CDAT register.
+ */
+#define I2C_GET_DATA(i2c)   ((i2c)->DAT)
+
+/**
+ *    @brief        Write a Data to I2C Data Register
+ *
+ *    @param[in]    i2c         Specify I2C port
+ *    @param[in]    u8Data      A byte that writes to data register
+ *
+ *    @return       None
+ *
+ *    @details      When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
+ */
+#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
+
+/**
+ *    @brief        Get I2C Bus status code
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       I2C status code
+ *
+ *    @details      To get this status code to monitor I2C bus event.
+ */
+#define I2C_GET_STATUS(i2c) ((i2c)->STATUS)
+
+/**
+ *    @brief        Get Time-out flag from I2C Bus
+ *
+ *    @param[in]    i2c     Specify I2C port
+ *
+ *    @retval       0       I2C Bus time-out is not happened
+ *    @retval       1       I2C Bus time-out is happened
+ *
+ *    @details      When I2C bus occurs time-out event, the time-out flag will be set.
+ */
+#define I2C_GET_TIMEOUT_FLAG(i2c)   ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
+
+/**
+ *    @brief        To get wake-up flag from I2C Bus
+ *
+ *    @param[in]    i2c     Specify I2C port
+ *
+ *    @retval       0       Chip is not woken-up from power-down mode
+ *    @retval       1       Chip is woken-up from power-down mode
+ *
+ *    @details      I2C bus occurs wake-up event, wake-up flag will be set.
+ */
+#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0  )
+
+/**
+ *    @brief        To clear wake-up flag
+ *
+ *    @param[in]    i2c     Specify I2C port
+ *
+ *    @return       None
+ *
+ *    @details      If wake-up flag is set, use this macro to clear it.
+ */
+#define I2C_CLEAR_WAKEUP_FLAG(i2c)  ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
+
+/**
+ * @brief      To get SMBus Status
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     SMBus status
+ *
+ * @details    To get the Bus Management status of I2C_BUSSTS register
+ *
+ */
+#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)
+
+/**
+ * @brief      Get SMBus CRC value
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     Packet error check byte value
+ *
+ * @details    The CRC check value after a transmission or a reception by count by using CRC8
+ *
+ */
+#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)
+
+/**
+ * @brief      Set SMBus Bytes number of Transmission or reception
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u32PktSize       Transmit / Receive bytes
+ *
+ * @return     None
+ *
+ * @details    The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
+ *
+ */
+#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))
+
+/**
+ * @brief      Enable SMBus Alert function
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host
+ *             Host   Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)
+ *
+ */
+#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)
+
+/**
+ * @brief      Disable SMBus Alert pin function
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host
+ *             Host   Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)
+ *
+ */
+#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)
+
+/**
+ * @brief      Set SMBus SUSCON pin is output mode
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.
+ *
+ *
+ */
+#define I2C_SMBUS_SET_SUSCON_OUT(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)
+
+/**
+ * @brief      Set SMBus SUSCON pin is input mode
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.
+ *
+ *
+ */
+#define I2C_SMBUS_SET_SUSCON_IN(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)
+
+/**
+ * @brief      Set SMBus SUSCON pin output high state
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.
+ *
+ */
+#define I2C_SMBUS_SET_SUSCON_HIGH(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)
+
+
+/**
+ * @brief      Set SMBus SUSCON pin output low state
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.
+ *
+ */
+#define I2C_SMBUS_SET_SUSCON_LOW(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)
+
+/**
+ * @brief      Enable SMBus Acknowledge control by manual
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.
+ *
+ */
+#define I2C_SMBUS_ACK_MANUAL(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)
+
+/**
+ * @brief      Disable SMBus Acknowledge control by manual
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    Disable acknowledge response control by user.
+ *
+ */
+#define I2C_SMBUS_ACK_AUTO(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)
+
+/**
+ * @brief      Enable SMBus Acknowledge manual interrupt
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
+ *
+ */
+#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)
+
+/**
+ * @brief      Disable SMBus Acknowledge manual interrupt
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
+ *
+ */
+#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)
+
+/**
+ * @brief      Enable SMBus PEC clear at REPEAT START
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function is used to enable the condition of REAEAT START can clear the PEC calculation.
+ *
+ */
+#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)
+
+/**
+ * @brief      Disable SMBus PEC clear at Repeat START
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function is used to disable the condition of Repeat START can clear the PEC calculation.
+ *
+ */
+#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* inline functions                                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+/**
+ *    @brief        The macro is used to set STOP condition of I2C Bus
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       None
+ *
+ *    @details      Set the I2C bus STOP condition in I2C_CTL register.
+ */
+static __INLINE void I2C_STOP(I2C_T *i2c)
+{
+
+    (i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk);
+    while(i2c->CTL & I2C_CTL_STO_Msk);
+}
+
+void I2C_ClearTimeoutFlag(I2C_T *i2c);
+void I2C_Close(I2C_T *i2c);
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
+void I2C_DisableInt(I2C_T *i2c);
+void I2C_EnableInt(I2C_T *i2c);
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
+uint32_t I2C_GetIntFlag(I2C_T *i2c);
+uint32_t I2C_GetStatus(I2C_T *i2c);
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
+uint8_t I2C_GetData(I2C_T *i2c);
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
+void I2C_DisableTimeout(I2C_T *i2c);
+void I2C_EnableWakeup(I2C_T *i2c);
+void I2C_DisableWakeup(I2C_T *i2c);
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
+
+uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
+void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8ClrSMBusIntFlag);
+void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
+void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
+void I2C_SMBusClose(I2C_T *i2c);
+void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
+uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
+void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk);
+void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
+void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
+/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group I2C_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+#endif //__I2C_H__
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_otg.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_otg.h
new file mode 100644
index 00000000000..4137650aa5c
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_otg.h
@@ -0,0 +1,260 @@
+/**************************************************************************//**
+ * @file     otg.h
+ * @version  V0.10
+ * $Revision: 3 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 Series OTG Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __OTG_H__
+#define __OTG_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup OTG_Driver OTG Driver
+  @{
+*/
+
+
+/** @addtogroup OTG_EXPORTED_CONSTANTS OTG Exported Constants
+  @{
+*/
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* OTG constant definitions                                                                                */
+/*---------------------------------------------------------------------------------------------------------*/
+#define OTG_VBUS_EN_ACTIVE_HIGH      (0UL) /*!< USB VBUS power switch enable signal is active high. */
+#define OTG_VBUS_EN_ACTIVE_LOW       (1UL) /*!< USB VBUS power switch enable signal is active low. */
+#define OTG_VBUS_ST_VALID_HIGH       (0UL) /*!< USB VBUS power switch valid status is high. */
+#define OTG_VBUS_ST_VALID_LOW        (1UL) /*!< USB VBUS power switch valid status is low. */
+
+
+/*@}*/ /* end of group OTG_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup OTG_EXPORTED_FUNCTIONS OTG Exported Functions
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Define Macros and functions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+  * @brief This macro is used to enable OTG function
+  * @param None
+  * @return None
+  * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function.
+  */
+#define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk)
+
+/**
+  * @brief This macro is used to disable OTG function
+  * @param None
+  * @return None
+  * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function.
+  */
+#define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk)
+
+/**
+  * @brief This macro is used to enable USB PHY
+  * @param None
+  * @return None
+  * @details When the USB role is selected as OTG device, use this macro to enable USB PHY.
+  *          This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY.
+  */
+#define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)
+
+/**
+  * @brief This macro is used to disable USB PHY
+  * @param None
+  * @return None
+  * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY.
+  */
+#define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)
+
+/**
+  * @brief This macro is used to enable ID detection function
+  * @param None
+  * @return None
+  * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function.
+  */
+#define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)
+
+/**
+  * @brief This macro is used to disable ID detection function
+  * @param None
+  * @return None
+  * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function.
+  */
+#define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)
+
+/**
+  * @brief This macro is used to enable OTG wake-up function
+  * @param None
+  * @return None
+  * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function.
+  */
+#define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk)
+
+/**
+  * @brief This macro is used to disable OTG wake-up function
+  * @param None
+  * @return None
+  * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function.
+  */
+#define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk)
+
+/**
+  * @brief This macro is used to set the polarity of USB_VBUS_EN pin
+  * @param[in] u32Pol The polarity selection. Valid values are listed below.
+  *                    - \ref OTG_VBUS_EN_ACTIVE_HIGH
+  *                    - \ref OTG_VBUS_EN_ACTIVE_LOW
+  * @return None
+  * @details This macro is used to set the polarity of external USB VBUS power switch enable signal.
+  */
+#define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBENPOL_Pos))
+
+/**
+  * @brief This macro is used to set the polarity of USB_VBUS_ST pin
+  * @param[in] u32Pol The polarity selection. Valid values are listed below.
+  *                    - \ref OTG_VBUS_ST_VALID_HIGH
+  *                    - \ref OTG_VBUS_ST_VALID_LOW
+  * @return None
+  * @details This macro is used to set the polarity of external USB VBUS power switch status signal.
+  */
+#define OTG_SET_VBUS_STS_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBSTSPOL_Pos))
+
+/**
+  * @brief This macro is used to enable OTG related interrupts
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref OTG_INTEN_ROLECHGIEN_Msk
+  *                    - \ref OTG_INTEN_VBEIEN_Msk
+  *                    - \ref OTG_INTEN_SRPFIEN_Msk
+  *                    - \ref OTG_INTEN_HNPFIEN_Msk
+  *                    - \ref OTG_INTEN_GOIDLEIEN_Msk
+  *                    - \ref OTG_INTEN_IDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_PDEVIEN_Msk
+  *                    - \ref OTG_INTEN_HOSTIEN_Msk
+  *                    - \ref OTG_INTEN_BVLDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_AVLDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_VBCHGIEN_Msk
+  *                    - \ref OTG_INTEN_SECHGIEN_Msk
+  *                    - \ref OTG_INTEN_SRPDETIEN_Msk
+  * @return None
+  * @details This macro will enable OTG related interrupts specified by u32Mask parameter.
+  */
+#define OTG_ENABLE_INT(u32Mask) (OTG->INTEN |= (u32Mask))
+
+/**
+  * @brief This macro is used to disable OTG related interrupts
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref OTG_INTEN_ROLECHGIEN_Msk
+  *                    - \ref OTG_INTEN_VBEIEN_Msk
+  *                    - \ref OTG_INTEN_SRPFIEN_Msk
+  *                    - \ref OTG_INTEN_HNPFIEN_Msk
+  *                    - \ref OTG_INTEN_GOIDLEIEN_Msk
+  *                    - \ref OTG_INTEN_IDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_PDEVIEN_Msk
+  *                    - \ref OTG_INTEN_HOSTIEN_Msk
+  *                    - \ref OTG_INTEN_BVLDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_AVLDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_VBCHGIEN_Msk
+  *                    - \ref OTG_INTEN_SECHGIEN_Msk
+  *                    - \ref OTG_INTEN_SRPDETIEN_Msk
+  * @return None
+  * @details This macro will disable OTG related interrupts specified by u32Mask parameter.
+  */
+#define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask))
+
+/**
+  * @brief This macro is used to get OTG related interrupt flags
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref OTG_INTSTS_ROLECHGIF_Msk
+  *                    - \ref OTG_INTSTS_VBEIF_Msk
+  *                    - \ref OTG_INTSTS_SRPFIF_Msk
+  *                    - \ref OTG_INTSTS_HNPFIF_Msk
+  *                    - \ref OTG_INTSTS_GOIDLEIF_Msk
+  *                    - \ref OTG_INTSTS_IDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_PDEVIF_Msk
+  *                    - \ref OTG_INTSTS_HOSTIF_Msk
+  *                    - \ref OTG_INTSTS_BVLDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_AVLDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_VBCHGIF_Msk
+  *                    - \ref OTG_INTSTS_SECHGIF_Msk
+  *                    - \ref OTG_INTSTS_SRPDETIF_Msk
+  * @return Interrupt flags of selected sources.
+  * @details This macro will return OTG related interrupt flags specified by u32Mask parameter.
+  */
+#define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask))
+
+/**
+  * @brief This macro is used to clear OTG related interrupt flags
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref OTG_INTSTS_ROLECHGIF_Msk
+  *                    - \ref OTG_INTSTS_VBEIF_Msk
+  *                    - \ref OTG_INTSTS_SRPFIF_Msk
+  *                    - \ref OTG_INTSTS_HNPFIF_Msk
+  *                    - \ref OTG_INTSTS_GOIDLEIF_Msk
+  *                    - \ref OTG_INTSTS_IDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_PDEVIF_Msk
+  *                    - \ref OTG_INTSTS_HOSTIF_Msk
+  *                    - \ref OTG_INTSTS_BVLDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_AVLDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_VBCHGIF_Msk
+  *                    - \ref OTG_INTSTS_SECHGIF_Msk
+  *                    - \ref OTG_INTSTS_SRPDETIF_Msk
+  * @return None
+  * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter.
+  */
+#define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask))
+
+/**
+  * @brief This macro is used to get OTG related status
+  * @param[in] u32Mask The combination of user specified source. Valid values are listed below.
+  *                    - \ref OTG_STATUS_OVERCUR_Msk
+  *                    - \ref OTG_STATUS_IDSTS_Msk
+  *                    - \ref OTG_STATUS_SESSEND_Msk
+  *                    - \ref OTG_STATUS_BVLD_Msk
+  *                    - \ref OTG_STATUS_AVLD_Msk
+  *                    - \ref OTG_STATUS_VBUSVLD_Msk
+  * @return The user specified status.
+  * @details This macro will return OTG related status specified by u32Mask parameter.
+  */
+#define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask))
+
+
+
+/*@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group OTG_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif //__OTG_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pdma.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pdma.c
new file mode 100644
index 00000000000..53f4420c1c6
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pdma.c
@@ -0,0 +1,389 @@
+/**************************************************************************//**
+ * @file     pdma.c
+ * @version  V1.00
+ * $Revision: 12 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series PDMA driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+static uint8_t u32ChSelect[PDMA_CH_MAX];
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup PDMA_Driver PDMA Driver
+  @{
+*/
+
+
+/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
+  @{
+*/
+
+/**
+ * @brief       PDMA Open
+ *
+ * @param[in]   u32Mask     Channel enable bits.
+ *
+ * @return      None
+ *
+ * @details     This function enable the PDMA channels.
+ */
+void PDMA_Open(uint32_t u32Mask)
+{
+    int volatile i;
+
+    for(i = 0; i < PDMA_CH_MAX; i++)
+    {
+        PDMA->DSCT[i].CTL = 0;
+        u32ChSelect[i] = 0x1f;
+    }
+
+    PDMA->CHCTL |= u32Mask;
+}
+
+/**
+ * @brief       PDMA Close
+ *
+ * @param       None
+ *
+ * @return      None
+ *
+ * @details     This function disable all PDMA channels.
+ */
+void PDMA_Close(void)
+{
+    PDMA->CHCTL = 0;
+}
+
+/**
+ * @brief       Set PDMA Transfer Count
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32Width        Data width. Valid values are
+ *                - \ref PDMA_WIDTH_8
+ *                - \ref PDMA_WIDTH_16
+ *                - \ref PDMA_WIDTH_32
+ * @param[in]   u32TransCount   Transfer count
+ *
+ * @return      None
+ *
+ * @details     This function set the selected channel data width and transfer count.
+ */
+void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
+{
+    PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
+    PDMA->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1) << PDMA_DSCT_CTL_TXCNT_Pos));
+}
+
+/**
+ * @brief       Set PDMA Transfer Address
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32SrcAddr      Source address
+ * @param[in]   u32SrcCtrl      Source control attribute. Valid values are
+ *                - \ref PDMA_SAR_INC
+ *                - \ref PDMA_SAR_FIX
+ * @param[in]   u32DstAddr      destination address
+ * @param[in]   u32DstCtrl      destination control attribute. Valid values are
+ *                - \ref PDMA_DAR_INC
+ *                - \ref PDMA_DAR_FIX
+ *
+ * @return      None
+ *
+ * @details     This function set the selected channel source/destination address and attribute.
+ */
+void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
+{
+    PDMA->DSCT[u32Ch].SA = u32SrcAddr;
+    PDMA->DSCT[u32Ch].DA = u32DstAddr;
+    PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
+    PDMA->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
+}
+
+/**
+ * @brief       Set PDMA Transfer Mode
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32Peripheral   The selected peripheral. Valid values are
+ *                - \ref PDMA_SPI0_TX
+ *                - \ref PDMA_SPI1_TX
+ *                - \ref PDMA_SPI2_TX
+ *                - \ref PDMA_UART0_TX
+ *                - \ref PDMA_UART1_TX
+ *                - \ref PDMA_UART2_TX
+ *                - \ref PDMA_UART3_TX
+ *                - \ref PDMA_DAC_TX
+ *                - \ref PDMA_ADC_RX
+ *                - \ref PDMA_PWM0_P1_RX
+ *                - \ref PDMA_PWM0_P2_RX
+ *                - \ref PDMA_PWM0_P3_RX
+ *                - \ref PDMA_PWM1_P1_RX
+ *                - \ref PDMA_PWM1_P2_RX
+ *                - \ref PDMA_PWM1_P3_RX
+ *                - \ref PDMA_SPI0_RX
+ *                - \ref PDMA_SPI1_RX
+ *                - \ref PDMA_SPI2_RX
+ *                - \ref PDMA_UART0_RX
+ *                - \ref PDMA_UART1_RX
+ *                - \ref PDMA_UART2_RX
+ *                - \ref PDMA_UART3_RX
+ *                - \ref PDMA_MEM
+ * @param[in]   u32ScatterEn    Scatter-gather mode enable
+ * @param[in]   u32DescAddr     Scatter-gather descriptor address
+ *
+ * @return      None
+ *
+ * @details     This function set the selected channel transfer mode. Include peripheral setting.
+ */
+void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
+{
+    u32ChSelect[u32Ch] = u32Peripheral;
+    switch(u32Ch)
+    {
+        case 0:
+            PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
+            break;
+        case 1:
+            PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
+            break;
+        case 2:
+            PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
+            break;
+        case 3:
+            PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
+            break;
+        case 4:
+            PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
+            break;
+        case 5:
+            PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
+            break;
+        case 6:
+            PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
+            break;
+        case 7:
+            PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
+            break;
+        case 8:
+            PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral;
+            break;
+        case 9:
+            PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos);
+            break;
+        case 10:
+            PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos);
+            break;
+        case 11:
+            PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos);
+            break;
+        default:
+            ;
+    }
+
+    if(u32ScatterEn)
+    {
+        PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
+        PDMA->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA);
+    }
+    else
+        PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
+}
+
+/**
+ * @brief       Set PDMA Burst Type and Size
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32BurstType    Burst mode or single mode. Valid values are
+ *                - \ref PDMA_REQ_SINGLE
+ *                - \ref PDMA_REQ_BURST
+ * @param[in]   u32BurstSize    Set the size of burst mode. Valid values are
+ *                - \ref PDMA_BURST_128
+ *                - \ref PDMA_BURST_64
+ *                - \ref PDMA_BURST_32
+ *                - \ref PDMA_BURST_16
+ *                - \ref PDMA_BURST_8
+ *                - \ref PDMA_BURST_4
+ *                - \ref PDMA_BURST_2
+ *                - \ref PDMA_BURST_1
+ *
+ * @return      None
+ *
+ * @details     This function set the selected channel burst type and size.
+ */
+void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
+{
+    PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
+    PDMA->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
+}
+
+/**
+ * @brief       Enable timeout function
+ *
+ * @param[in]   u32Mask         Channel enable bits.
+ *
+ * @return      None
+ *
+ * @details     This function enable timeout function of the selected channel(s).
+ * @note        This function is only supported in M45xD/M45xC.
+ */
+void PDMA_EnableTimeout(uint32_t u32Mask)
+{
+    PDMA->TOUTEN |= u32Mask;
+}
+
+/**
+ * @brief       Disable timeout function
+ *
+ * @param[in]   u32Mask         Channel enable bits.
+ *
+ * @return      None
+ *
+ * @details     This function disable timeout function of the selected channel(s).
+ * @note        This function is only supported in M45xD/M45xC.
+ */
+void PDMA_DisableTimeout(uint32_t u32Mask)
+{
+    PDMA->TOUTEN &= ~u32Mask;
+}
+
+/**
+ * @brief       Set PDMA Timeout Count
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32OnOff        Enable/disable time out function
+ * @param[in]   u32TimeOutCnt   Timeout count
+ *
+ * @return      None
+ *
+ * @details     This function set the timeout count.
+ * @note        This function is only supported in M45xD/M45xC.
+ */
+void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
+{
+    switch(u32Ch)
+    {
+        case 0:
+            PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
+            break;
+        case 1:
+            PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
+            break;
+        case 2:
+            PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC2_Msk) | u32TimeOutCnt;
+            break;
+        case 3:
+            PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC3_Msk) | (u32TimeOutCnt << PDMA_TOC2_3_TOC3_Pos);
+            break;
+        case 4:
+            PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC4_Msk) | u32TimeOutCnt;
+            break;
+        case 5:
+            PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC5_Msk) | (u32TimeOutCnt << PDMA_TOC4_5_TOC5_Pos);
+            break;
+        case 6:
+            PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC6_Msk) | u32TimeOutCnt;
+            break;
+        case 7:
+            PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC7_Msk) | (u32TimeOutCnt << PDMA_TOC6_7_TOC7_Pos);
+            break;
+
+        default:
+            ;
+    }
+}
+
+/**
+ * @brief       Trigger PDMA
+ *
+ * @param[in]   u32Ch           The selected channel
+ *
+ * @return      None
+ *
+ * @details     This function trigger the selected channel.
+ */
+void PDMA_Trigger(uint32_t u32Ch)
+{
+    if(u32ChSelect[u32Ch] == PDMA_MEM)
+        PDMA->SWREQ = (1 << u32Ch);
+}
+
+/**
+ * @brief       Enable Interrupt
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32Mask         The Interrupt Type. Valid values are
+ *                - \ref PDMA_INT_TRANS_DONE
+ *                - \ref PDMA_INT_TEMPTY
+ *                - \ref PDMA_INT_TIMEOUT
+ *
+ * @return      None
+ *
+ * @details     This function enable the selected channel interrupt.
+ * @note        PDMA_INT_TIMEOUT is only supported in M45xD/M45xC.
+ */
+void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
+{
+    switch(u32Mask)
+    {
+        case PDMA_INT_TRANS_DONE:
+            PDMA->INTEN |= (1 << u32Ch);
+            break;
+        case PDMA_INT_TEMPTY:
+            PDMA->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;
+            break;
+        case PDMA_INT_TIMEOUT:
+            PDMA->TOUTIEN |= (1 << u32Ch);
+            break;
+
+        default:
+            ;
+    }
+}
+
+/**
+ * @brief       Disable Interrupt
+ *
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32Mask         The Interrupt Type. Valid values are
+ *                - \ref PDMA_INT_TRANS_DONE
+ *                - \ref PDMA_INT_TEMPTY
+ *                - \ref PDMA_INT_TIMEOUT
+ *
+ * @return      None
+ *
+ * @details     This function disable the selected channel interrupt.
+ * @note        PDMA_INT_TIMEOUT is only supported in M45xD/M45xC.
+ */
+void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
+{
+    switch(u32Mask)
+    {
+        case PDMA_INT_TRANS_DONE:
+            PDMA->INTEN &= ~(1 << u32Ch);
+            break;
+        case PDMA_INT_TEMPTY:
+            PDMA->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;
+            break;
+        case PDMA_INT_TIMEOUT:
+            PDMA->TOUTIEN &= ~(1 << u32Ch);
+            break;
+
+        default:
+            ;
+    }
+}
+
+/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group PDMA_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pdma.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pdma.h
new file mode 100644
index 00000000000..7ca4b45a9e4
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pdma.h
@@ -0,0 +1,300 @@
+/**************************************************************************//**
+ * @file     pdma.h
+ * @version  V1.00
+ * $Revision: 15 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series PDMA driver header file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __PDMA_H__
+#define __PDMA_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup PDMA_Driver PDMA Driver
+  @{
+*/
+
+/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
+  @{
+*/
+#define PDMA_CH_MAX    12   /*!< Specify Maximum Channels of PDMA  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Operation Mode Constant Definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_OP_STOP        0x00000000UL            /*!<DMA Stop Mode  \hideinitializer */
+#define PDMA_OP_BASIC       0x00000001UL            /*!<DMA Basic Mode  \hideinitializer */
+#define PDMA_OP_SCATTER     0x00000002UL            /*!<DMA Scatter-gather Mode  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Data Width Constant Definitions                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_WIDTH_8        0x00000000UL            /*!<DMA Transfer Width 8-bit  \hideinitializer */
+#define PDMA_WIDTH_16       0x00001000UL            /*!<DMA Transfer Width 16-bit  \hideinitializer */
+#define PDMA_WIDTH_32       0x00002000UL            /*!<DMA Transfer Width 32-bit  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Address Attribute Constant Definitions                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_SAR_INC        0x00000000UL            /*!<DMA SAR increment  \hideinitializer */
+#define PDMA_SAR_FIX        0x00000300UL            /*!<DMA SAR fix address  \hideinitializer */
+#define PDMA_DAR_INC        0x00000000UL            /*!<DMA DAR increment  \hideinitializer */
+#define PDMA_DAR_FIX        0x00000C00UL            /*!<DMA DAR fix address  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Burst Mode Constant Definitions                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_REQ_SINGLE     0x00000004UL            /*!<DMA Single Request  \hideinitializer */
+#define PDMA_REQ_BURST      0x00000000UL            /*!<DMA Burst Request  \hideinitializer */
+
+#define PDMA_BURST_128      0x00000000UL            /*!<DMA Burst 128 Transfers  \hideinitializer */
+#define PDMA_BURST_64       0x00000010UL            /*!<DMA Burst 64 Transfers  \hideinitializer */
+#define PDMA_BURST_32       0x00000020UL            /*!<DMA Burst 32 Transfers  \hideinitializer */
+#define PDMA_BURST_16       0x00000030UL            /*!<DMA Burst 16 Transfers  \hideinitializer */
+#define PDMA_BURST_8        0x00000040UL            /*!<DMA Burst 8 Transfers  \hideinitializer */
+#define PDMA_BURST_4        0x00000050UL            /*!<DMA Burst 4 Transfers  \hideinitializer */
+#define PDMA_BURST_2        0x00000060UL            /*!<DMA Burst 2 Transfers  \hideinitializer */
+#define PDMA_BURST_1        0x00000070UL            /*!<DMA Burst 1 Transfers  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Peripheral Transfer Mode Constant Definitions                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_SPI0_TX        0x00000001UL            /*!<DMA Connect to SPI1 TX  \hideinitializer */
+#define PDMA_SPI1_TX        0x00000002UL            /*!<DMA Connect to SPI2 TX  \hideinitializer */
+#define PDMA_SPI2_TX        0x00000003UL            /*!<DMA Connect to SPI3 TX  \hideinitializer */
+#define PDMA_UART0_TX       0x00000004UL            /*!<DMA Connect to UART0 TX  \hideinitializer */
+#define PDMA_UART1_TX       0x00000005UL            /*!<DMA Connect to UART1 TX  \hideinitializer */
+#define PDMA_UART2_TX       0x00000006UL            /*!<DMA Connect to UART2 TX  \hideinitializer */
+#define PDMA_UART3_TX       0x00000007UL            /*!<DMA Connect to UART3 TX  \hideinitializer */
+#define PDMA_DAC_TX         0x00000008UL            /*!<DMA Connect to DAC TX  \hideinitializer */
+#define PDMA_ADC_RX         0x00000009UL            /*!<DMA Connect to ADC RX  \hideinitializer */
+#define PDMA_PWM0_P1_RX     0x0000000BUL            /*!<DMA Connect to PWM0 P1 RX  \hideinitializer */
+#define PDMA_PWM0_P2_RX     0x0000000CUL            /*!<DMA Connect to PWM0 P2 RX  \hideinitializer */
+#define PDMA_PWM0_P3_RX     0x0000000DUL            /*!<DMA Connect to PWM0 P3 RX  \hideinitializer */
+#define PDMA_PWM1_P1_RX     0x0000000EUL            /*!<DMA Connect to PWM1 P1 RX  \hideinitializer */
+#define PDMA_PWM1_P2_RX     0x0000000FUL            /*!<DMA Connect to PWM1 P2 RX  \hideinitializer */
+#define PDMA_PWM1_P3_RX     0x00000010UL            /*!<DMA Connect to PWM1 P3 RX  \hideinitializer */
+#define PDMA_SPI0_RX        0x00000011UL            /*!<DMA Connect to SPI0 RX  \hideinitializer */
+#define PDMA_SPI1_RX        0x00000012UL            /*!<DMA Connect to SPI1 RX  \hideinitializer */
+#define PDMA_SPI2_RX        0x00000013UL            /*!<DMA Connect to SPI2 RX  \hideinitializer */
+#define PDMA_UART0_RX       0x00000014UL            /*!<DMA Connect to UART0 RX  \hideinitializer */
+#define PDMA_UART1_RX       0x00000015UL            /*!<DMA Connect to UART1 RX  \hideinitializer */
+#define PDMA_UART2_RX       0x00000016UL            /*!<DMA Connect to UART2 RX  \hideinitializer */
+#define PDMA_UART3_RX       0x00000017UL            /*!<DMA Connect to UART3 RX  \hideinitializer */
+#define PDMA_MEM            0x0000001FUL            /*!<DMA Connect to Memory  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Interrupt Type Constant Definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_INT_TRANS_DONE 0x00000000UL            /*!<Transfer Done Interrupt  \hideinitializer */
+#define PDMA_INT_TEMPTY     0x00000001UL            /*!<Table Empty Interrupt  \hideinitializer */
+#define PDMA_INT_TIMEOUT    0x00000002UL            /*!<Timeout Interrupt(M45xD/M45xC Only)  \hideinitializer */
+
+
+/*@}*/ /* end of group PDMA_EXPORTED_CONSTANTS */
+
+/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
+  @{
+*/
+
+/**
+ * @brief       Get PDMA Interrupt Status
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     This macro gets the interrupt status.
+ */
+#define PDMA_GET_INT_STATUS() ((uint32_t)(PDMA->INTSTS))
+
+/**
+ * @brief       Get Transfer Done Interrupt Status
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     Get the transfer done Interrupt status.
+ */
+#define PDMA_GET_TD_STS() ((uint32_t)(PDMA->TDSTS))
+
+/**
+ * @brief       Clear Transfer Done Interrupt Status
+ *
+ * @param[in]   u32Mask     The channel mask
+ *
+ * @return      None
+ *
+ * @details     Clear the transfer done Interrupt status.
+ */
+#define PDMA_CLR_TD_FLAG(u32Mask) ((uint32_t)(PDMA->TDSTS = (u32Mask)))
+
+/**
+ * @brief       Get Target Abort Interrupt Status
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     Get the target abort Interrupt status.
+ */
+#define PDMA_GET_ABORT_STS() ((uint32_t)(PDMA->ABTSTS))
+
+/**
+ * @brief       Clear Target Abort Interrupt Status
+ *
+ * @param[in]   u32Mask     The channel mask
+ *
+ * @return      None
+ *
+ * @details     Clear the target abort Interrupt status.
+ */
+#define PDMA_CLR_ABORT_FLAG(u32Mask) ((uint32_t)(PDMA->ABTSTS = (u32Mask)))
+
+/**
+ * @brief       Get Scatter-Gather Table Empty Interrupt Status
+ *
+ * @param[in]   None
+ *
+ * @return      None
+ *
+ * @details     Get the scatter-gather table empty Interrupt status.
+ */
+#define PDMA_GET_EMPTY_STS() ((uint32_t)(PDMA->SCATSTS))
+
+/**
+ * @brief       Clear Scatter-Gather Table Empty Interrupt Status
+ *
+ * @param[in]   u32Mask     The channel mask
+ *
+ * @return      None
+ *
+ * @details     Clear the scatter-gather table empty Interrupt status.
+ */
+#define PDMA_CLR_EMPTY_FLAG(u32Mask) ((uint32_t)(PDMA->SCATSTS = (u32Mask)))
+
+/**
+ * @brief       Clear Timeout Interrupt Status
+ *
+ * @param[in]   u32Ch     The selected channel
+ *
+ * @return      None
+ *
+ * @details     Clear the selected channel timeout interrupt status.
+ * @note        This function is only supported in M45xD/M45xC.
+ */
+#define PDMA_CLR_TMOUT_FLAG(u32Ch) ((uint32_t)(PDMA->INTSTS = (1 << ((u32Ch) + 8))))
+
+/**
+ * @brief       Check Channel Status
+ *
+ * @param[in]   u32Ch     The selected channel
+ *
+ * @retval      0 Idle state
+ * @retval      1 Busy state
+ *
+ * @details     Check the selected channel is busy or not.
+ */
+#define PDMA_IS_CH_BUSY(u32Ch) ((uint32_t)(PDMA->TRGSTS & (1 << (u32Ch)))? 1 : 0)
+
+/**
+ * @brief       Set Source Address
+ *
+ * @param[in]   u32Ch     The selected channel
+ * @param[in]   u32Addr   The selected address
+ *
+ * @return      None
+ *
+ * @details     This macro set the selected channel source address.
+ */
+#define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[(u32Ch)].SA = (u32Addr)))
+
+/**
+ * @brief       Set Destination Address
+ *
+ * @param[in]   u32Ch     The selected channel
+ * @param[in]   u32Addr   The selected address
+ *
+ * @return      None
+ *
+ * @details     This macro set the selected channel destination address.
+ */
+#define PDMA_SET_DST_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[(u32Ch)].DA = (u32Addr)))
+
+/**
+ * @brief       Set Transfer Count
+ *
+ * @param[in]   u32Ch          The selected channel
+ * @param[in]   u32TransCount  Transfer Count
+ *
+ * @return      None
+ *
+ * @details     This macro set the selected channel transfer count.
+ */
+#define PDMA_SET_TRANS_CNT(u32Ch, u32TransCount) ((uint32_t)(PDMA->DSCT[(u32Ch)].CTL=(PDMA->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|((u32TransCount-1) << PDMA_DSCT_CTL_TXCNT_Pos)))
+
+/**
+ * @brief       Set Scatter-gather descriptor Address
+ *
+ * @param[in]   u32Ch     The selected channel
+ * @param[in]   u32Addr   The descriptor address
+ *
+ * @return      None
+ *
+ * @details     This macro set the selected channel scatter-gather descriptor address.
+ */
+#define PDMA_SET_SCATTER_DESC(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[(u32Ch)].NEXT = (u32Addr) - (PDMA->SCATBA)))
+
+/**
+ * @brief       Stop the channel
+ *
+ * @param[in]   u32Ch     The selected channel
+ *
+ * @return      None
+ *
+ * @details     This macro stop the selected channel.
+ */
+#define PDMA_STOP(u32Ch) ((uint32_t)(PDMA->STOP = (1 << (u32Ch))))
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define PWM functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+void PDMA_Open(uint32_t u32Mask);
+void PDMA_Close(void);
+void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
+void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
+void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
+void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);
+void PDMA_EnableTimeout(uint32_t u32Mask);
+void PDMA_DisableTimeout(uint32_t u32Mask);
+void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
+void PDMA_Trigger(uint32_t u32Ch);
+void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask);
+void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask);
+
+
+/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group PDMA_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__PDMA_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pwm.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pwm.c
new file mode 100644
index 00000000000..f579cccabfe
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pwm.c
@@ -0,0 +1,1375 @@
+/**************************************************************************//**
+ * @file     pwm.c
+ * @version  V3.00
+ * $Revision: 21 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series PWM driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup PWM_Driver PWM Driver
+  @{
+*/
+
+
+/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
+  @{
+*/
+
+/**
+ * @brief Configure PWM capture and get the nearest unit time.
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32UnitTimeNsec The unit time of counter
+ * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
+ * @return The nearest unit time in nano second.
+ * @details This function is used to Configure PWM capture and get the nearest unit time.
+ */
+uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
+{
+    uint32_t u32Src;
+    uint32_t u32PWMClockSrc;
+    uint32_t u32NearestUnitTimeNsec;
+    uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
+
+    if(pwm == PWM0)
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk;
+    else//(pwm == PWM1)
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk;
+
+    if(u32Src == 0)
+    {
+        //clock source is from PLL clock
+        u32PWMClockSrc = CLK_GetPLLClockFreq();
+    }
+    else
+    {
+        //clock source is from PCLK
+        SystemCoreClockUpdate();
+        u32PWMClockSrc = SystemCoreClock;
+    }
+
+    u32PWMClockSrc /= 1000;
+    for(u16Prescale = 1; u16Prescale <= 0x1000; u16Prescale++)
+    {
+        u32NearestUnitTimeNsec = (1000000 * u16Prescale) / u32PWMClockSrc;
+        if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
+        {
+            if(u16Prescale == 0x1000)  //limit to the maximum unit time(nano second)
+                break;
+            if(!((1000000 * (u16Prescale + 1) > (u32NearestUnitTimeNsec * u32PWMClockSrc))))
+                break;
+            continue;
+        }
+        break;
+    }
+
+    // convert to real register value
+    // every two channels share a prescaler
+    PWM_SET_PRESCALER(pwm, u32ChannelNum, --u16Prescale);
+
+    // set PWM to down count type(edge aligned)
+    (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << (2 * u32ChannelNum))) | (1UL << (2 * u32ChannelNum));
+    // set PWM to auto-reload mode
+    (pwm)->CTL1 &= ~(PWM_CTL1_CNTMODE0_Msk << u32ChannelNum);
+    PWM_SET_CNR(pwm, u32ChannelNum, u16CNR);
+
+    return (u32NearestUnitTimeNsec);
+}
+
+/**
+ * @brief This function Configure PWM generator and get the nearest frequency in edge aligned auto-reload mode
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Frequency Target generator frequency
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @return Nearest frequency clock in nano second
+ * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure PWM frequency may affect
+ *       existing frequency of other channel.
+ */
+uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
+                                  uint32_t u32ChannelNum,
+                                  uint32_t u32Frequency,
+                                  uint32_t u32DutyCycle)
+{
+    return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1);
+}
+
+/**
+ * @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
+ * @param[in] pwm The base address of PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Frequency Target generator frequency = u32Frequency / u32Frequency2
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
+ * @return Nearest frequency clock in nano second
+ * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
+ *       existing frequency of other channel.
+ */
+uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
+                                 uint32_t u32ChannelNum,
+                                 uint32_t u32Frequency,
+                                 uint32_t u32DutyCycle,
+                                 uint32_t u32Frequency2)
+{
+    uint32_t u32Src;
+    uint32_t u32PWMClockSrc;
+    uint32_t i;
+    uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
+
+    if(pwm == PWM0)
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk;
+    else//(pwm == PWM1)
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk;
+
+    if(u32Src == 0)
+    {
+        //clock source is from PLL clock
+        u32PWMClockSrc = CLK_GetPLLClockFreq();
+    }
+    else
+    {
+        //clock source is from PCLK
+        SystemCoreClockUpdate();
+        u32PWMClockSrc = SystemCoreClock;
+    }
+
+    for(u16Prescale = 1; u16Prescale < 0xFFF; u16Prescale++)//prescale could be 0~0xFFF
+    {
+        // Note: Support frequency < 1
+        i = (uint64_t) u32PWMClockSrc * u32Frequency2 / u32Frequency / u16Prescale;
+        // If target value is larger than CNR, need to use a larger prescaler
+        if(i > (0x10000))
+            continue;
+
+        u16CNR = i;
+        break;
+    }
+    // Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register
+    i = u32PWMClockSrc / (u16Prescale * u16CNR);
+
+    // convert to real register value
+    // every two channels share a prescaler
+    PWM_SET_PRESCALER(pwm, u32ChannelNum, --u16Prescale);
+    // set PWM to down count type(edge aligned)
+    (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << (2 * u32ChannelNum))) | (1UL << (2 * u32ChannelNum));
+    // set PWM to auto-reload mode
+    (pwm)->CTL1 &= ~(PWM_CTL1_CNTMODE0_Msk << u32ChannelNum);
+
+    PWM_SET_CNR(pwm, u32ChannelNum, --u16CNR);
+    if(u32DutyCycle)
+    {
+        PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1) / 100 - 1);
+        (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2));
+        (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_PRDPCTL0_Pos));
+        (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2));
+        (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << (u32ChannelNum * 2 + PWM_WGCTL1_CMPDCTL0_Pos));
+    }
+    else
+    {
+        PWM_SET_CMR(pwm, u32ChannelNum, 0);
+        (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2));
+        (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_ZPCTL0_Pos));
+        (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2));
+        (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << (u32ChannelNum * 2 + PWM_WGCTL1_CMPDCTL0_Pos));
+    }
+
+    return(i);
+}
+
+/**
+ * @brief Start PWM module
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to start PWM module.
+ */
+void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+    (pwm)->CNTEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Stop PWM module
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop PWM module.
+ */
+void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+    uint32_t i;
+    for(i = 0; i < PWM_CHANNEL_NUM; i ++)
+    {
+        if(u32ChannelMask & (1 << i))
+        {
+            (pwm)->PERIOD[i] = 0;
+        }
+    }
+}
+
+/**
+ * @brief Stop PWM generation immediately by clear channel enable bit
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop PWM generation immediately by clear channel enable bit.
+ */
+void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+    (pwm)->CNTEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enable selected channel to trigger EADC
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger EADC. Combination of following conditions:
+ *                  - \ref PWM_TRIGGER_ADC_EVEN_ZERO_POINT
+ *                  - \ref PWM_TRIGGER_ADC_EVEN_PERIOD_POINT
+ *                  - \ref PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT
+ *                  - \ref PWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT
+ *                  - \ref PWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT
+ *                  - \ref PWM_TRIGGER_ADC_ODD_ZERO_POINT
+ *                  - \ref PWM_TRIGGER_ADC_ODD_PERIOD_POINT
+ *                  - \ref PWM_TRIGGER_ADC_ODD_ZERO_OR_PERIOD_POINT
+ *                  - \ref PWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT
+ *                  - \ref PWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT
+ *                  - \ref PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_UP_COUNT_POINT
+ *                  - \ref PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_DOWN_COUNT_POINT
+ *                  - \ref PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_UP_COUNT_POINT
+ *                  - \ref PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_DOWN_COUNT_POINT
+ *                  - \ref PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_UP_COUNT_POINT
+ *                  - \ref PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_DOWN_COUNT_POINT
+ * @return None
+ * @details This function is used to enable selected channel to trigger EADC.
+ */
+void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    if(u32ChannelNum < 4)
+    {
+        (pwm)->EADCTS0 &= ~((PWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum * 8));
+        (pwm)->EADCTS0 |= ((PWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum * 8));
+    }
+    else
+    {
+        (pwm)->EADCTS1 &= ~((PWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4) * 8));
+        (pwm)->EADCTS1 |= ((PWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4) * 8));
+    }
+}
+
+/**
+ * @brief Disable selected channel to trigger EADC
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable selected channel to trigger EADC.
+ */
+void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    if(u32ChannelNum < 4)
+    {
+        (pwm)->EADCTS0 &= ~(PWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum * 8));
+    }
+    else
+    {
+        (pwm)->EADCTS1 &= ~(PWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4) * 8));
+    }
+}
+
+/**
+ * @brief Clear selected channel trigger EADC flag
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger EADC flag.
+ */
+void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    (pwm)->STATUS = (PWM_STATUS_ADCTRGF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get selected channel trigger EADC flag
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @retval 0 The specified channel trigger EADC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger EADC to start of conversion flag is set
+ * @details This function is used to get PWM trigger EADC to start of conversion flag for specified channel.
+ */
+uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    return (((pwm)->STATUS & (PWM_STATUS_ADCTRGF0_Msk << u32ChannelNum)) ? 1 : 0);
+}
+
+/**
+ * @brief Enable selected channel to trigger DAC
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions:
+ *                  - \ref PWM_TRIGGER_DAC_ZERO_POINT
+ *                  - \ref PWM_TRIGGER_DAC_PERIOD_POINT
+ *                  - \ref PWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT
+ *                  - \ref PWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT
+ * @return None
+ * @details This function is used to enable selected channel to trigger DAC.
+ */
+void PWM_EnableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    (pwm)->DACTRGEN |= (u32Condition << u32ChannelNum);
+}
+
+/**
+ * @brief Disable selected channel to trigger DAC
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable selected channel to trigger DAC.
+ */
+void PWM_DisableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->DACTRGEN &= ~((PWM_TRIGGER_DAC_ZERO_POINT | PWM_TRIGGER_DAC_PERIOD_POINT | PWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT | \
+                          PWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear selected channel trigger DAC flag
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. This parameter is not used
+ * @param[in] u32Condition The condition to trigger DAC. This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger DAC flag.
+ */
+void PWM_ClearDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    (pwm)->STATUS = PWM_STATUS_DACTRGF_Msk;
+}
+
+/**
+ * @brief Get selected channel trigger DAC flag
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. This parameter is not used
+ * @retval 0 The specified channel trigger DAC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger DAC to start of conversion flag is set
+ * @details This function is used to get selected channel trigger DAC flag.
+ */
+uint32_t PWM_GetDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    return (((pwm)->STATUS & PWM_STATUS_DACTRGF_Msk) ? 1 : 0);
+}
+
+/**
+ * @brief This function enable fault brake of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel
+ *                         while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32BrakeSource Fault brake source, could be one of following source
+ *                  - \ref PWM_FB_EDGE_ACMP0
+ *                  - \ref PWM_FB_EDGE_ACMP1
+ *                  - \ref PWM_FB_EDGE_BKP0
+ *                  - \ref PWM_FB_EDGE_BKP1
+ *                  - \ref PWM_FB_EDGE_SYS_CSS
+ *                  - \ref PWM_FB_EDGE_SYS_BOD
+ *                  - \ref PWM_FB_EDGE_SYS_RAM
+ *                  - \ref PWM_FB_EDGE_SYS_COR
+ *                  - \ref PWM_FB_LEVEL_ACMP0
+ *                  - \ref PWM_FB_LEVEL_ACMP1
+ *                  - \ref PWM_FB_LEVEL_BKP0
+ *                  - \ref PWM_FB_LEVEL_BKP1
+ *                  - \ref PWM_FB_LEVEL_SYS_CSS
+ *                  - \ref PWM_FB_LEVEL_SYS_BOD
+ *                  - \ref PWM_FB_LEVEL_SYS_RAM
+ *                  - \ref PWM_FB_LEVEL_SYS_COR
+ * @return None
+ * @details This function is used to enable fault brake of selected channel(s).
+ *          The write-protection function should be disabled before using this function.
+ */
+void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
+{
+    uint32_t i;
+    for(i = 0; i < PWM_CHANNEL_NUM; i ++)
+    {
+        if(u32ChannelMask & (1 << i))
+        {
+            if((u32BrakeSource == PWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == PWM_FB_EDGE_SYS_BOD) || \
+                    (u32BrakeSource == PWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == PWM_FB_EDGE_SYS_COR) || \
+                    (u32BrakeSource == PWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == PWM_FB_LEVEL_SYS_BOD) || \
+                    (u32BrakeSource == PWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == PWM_FB_LEVEL_SYS_COR))
+            {
+                *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= (u32BrakeSource & (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_BRKCTL0_1_SYSLBEN_Msk));
+                (pwm)->FAILBRK |= (u32BrakeSource & 0xF);
+            }
+            else
+            {
+                *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= u32BrakeSource;
+            }
+        }
+
+        if(u32LevelMask & (1 << i))
+        {
+            if(i % 2 == 0)
+            {
+                //set brake action as high level for even channel
+                *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk;
+                *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((3UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos);
+            }
+            else
+            {
+                //set brake action as high level for odd channel
+                *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAODD_Msk;
+                *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((3UL) << PWM_BRKCTL0_1_BRKAODD_Pos);
+            }
+        }
+        else
+        {
+            if(i % 2 == 0)
+            {
+                //set brake action as low level for even channel
+                *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk;
+                *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((2UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos);
+            }
+            else
+            {
+                //set brake action as low level for odd channel
+                *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAODD_Msk;
+                *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((2UL) << PWM_BRKCTL0_1_BRKAODD_Pos);
+            }
+        }
+    }
+
+}
+
+/**
+ * @brief Enable capture of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable capture of selected channel(s).
+ */
+void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+    (pwm)->CAPINEN |= u32ChannelMask;
+    (pwm)->CAPCTL |= u32ChannelMask;
+}
+
+/**
+ * @brief Disable capture of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable capture of selected channel(s).
+ */
+void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+    (pwm)->CAPINEN &= ~u32ChannelMask;
+    (pwm)->CAPCTL &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables PWM output generation of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
+ * @return None
+ * @details This function is used to enable PWM output generation of selected channel(s).
+ */
+void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+    (pwm)->POEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Disables PWM output generation of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
+ * @return None
+ * @details This function is used to disable PWM output generation of selected channel(s).
+ */
+void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+    (pwm)->POEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables PDMA transfer of selected channel for PWM capture
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number.
+ * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE.
+ * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either
+ *              - \ref PWM_CAPTURE_PDMA_RISING_LATCH
+ *              - \ref PWM_CAPTURE_PDMA_FALLING_LATCH
+ *              - \ref PWM_CAPTURE_PDMA_RISING_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable PDMA transfer of selected channel(s) for PWM capture.
+ * @note This function can only selects even or odd channel of pairs to do PDMA transfer.
+ */
+void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
+{
+    uint32_t u32IsOddCh;
+    u32IsOddCh = u32ChannelNum % 2;
+    (pwm)->PDMACTL = ((pwm)->PDMACTL & ~((PWM_PDMACTL_CHSEL0_1_Msk | PWM_PDMACTL_CAPORD0_1_Msk | PWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1) * 8))) | \
+                     (((u32IsOddCh << PWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << PWM_PDMACTL_CAPORD0_1_Pos) | \
+                       u32Mode | PWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Disables PDMA transfer of selected channel for PWM capture
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number.
+ * @return None
+ * @details This function is used to enable PDMA transfer of selected channel(s) for PWM capture.
+ */
+void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->PDMACTL &= ~(PWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Enable Dead zone of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Duration Dead zone length in PWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone.
+ * @return None
+ * @details This function is used to enable Dead zone of selected channel.
+ *          The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
+{
+    // every two channels share the same setting
+    *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) &= ~PWM_DTCTL0_1_DTCNT_Msk;
+    *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) |= PWM_DTCTL0_1_DTEN_Msk | u32Duration;
+}
+
+/**
+ * @brief Disable Dead zone of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable Dead zone of selected channel.
+ *          The write-protection function should be disabled before using this function.
+ */
+void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    // every two channels shares the same setting
+    *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) &= ~PWM_DTCTL0_1_DTEN_Msk;
+}
+
+/**
+ * @brief Enable capture interrupt of selected channel.
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref PWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref PWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable capture interrupt of selected channel.
+ */
+void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (pwm)->CAPIEN |= (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Disable capture interrupt of selected channel.
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref PWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref PWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to disable capture interrupt of selected channel.
+ */
+void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (pwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Clear capture interrupt of selected channel.
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref PWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref PWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to clear capture interrupt of selected channel.
+ */
+void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (pwm)->CAPIF = (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Get capture interrupt of selected channel.
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @retval 0 No capture interrupt
+ * @retval 1 Rising edge latch interrupt
+ * @retval 2 Falling edge latch interrupt
+ * @retval 3 Rising and falling latch interrupt
+ * @details This function is used to get capture interrupt of selected channel.
+ */
+uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    return (((((pwm)->CAPIF & (PWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1 : 0) << 1) | \
+            (((pwm)->CAPIF & (PWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1 : 0));
+}
+/**
+ * @brief Enable duty interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32IntDutyType Duty interrupt type, could be either
+ *              - \ref PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
+ *              - \ref PWM_DUTY_INT_UP_COUNT_MATCH_CMP
+ * @return None
+ * @details This function is used to enable duty interrupt of selected channel.
+ */
+void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
+{
+    (pwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum);
+}
+
+/**
+ * @brief Disable duty interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable duty interrupt of selected channel.
+ */
+void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->INTEN0 &= ~((PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | PWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear duty interrupt flag of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear duty interrupt flag of selected channel.
+ */
+void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->INTSTS0 = (PWM_INTSTS0_CMPUIF0_Msk | PWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum;
+}
+
+/**
+ * @brief Get duty interrupt flag of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Duty interrupt did not occur
+ * @retval 1 Duty interrupt occurred
+ * @details This function is used to get duty interrupt flag of selected channel.
+ */
+uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    return ((((pwm)->INTSTS0 & ((PWM_INTSTS0_CMPDIF0_Msk | PWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1 : 0);
+}
+
+/**
+ * @brief This function enable fault brake interrupt
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ *              - \ref PWM_FB_EDGE
+ *              - \ref PWM_FB_LEVEL
+ * @return None
+ * @details This function is used to enable fault brake interrupt.
+ *          The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
+{
+    (pwm)->INTEN1 |= (0x7 << u32BrakeSource);
+}
+
+/**
+ * @brief This function disable fault brake interrupt
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ *              - \ref PWM_FB_EDGE
+ *              - \ref PWM_FB_LEVEL
+ * @return None
+ * @details This function is used to disable fault brake interrupt.
+ *          The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
+{
+    (pwm)->INTEN1 &= ~(0x7 << u32BrakeSource);
+}
+
+/**
+ * @brief This function clear fault brake interrupt of selected source
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ *              - \ref PWM_FB_EDGE
+ *              - \ref PWM_FB_LEVEL
+ * @return None
+ * @details This function is used to clear fault brake interrupt of selected source.
+ *          The write-protection function should be disabled before using this function.
+ */
+void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
+{
+    (pwm)->INTSTS1 = (0x3f << u32BrakeSource);
+}
+
+/**
+ * @brief This function get fault brake interrupt flag of selected source
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32BrakeSource Fault brake source, could be either
+ *              - \ref PWM_FB_EDGE
+ *              - \ref PWM_FB_LEVEL
+ * @return Fault brake interrupt flag of specified source
+ * @retval 0 Fault brake interrupt did not occurred
+ * @retval 1 Fault brake interrupt occurred
+ * @details This function is used to get fault brake interrupt flag of selected source.
+ */
+uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
+{
+    return (((pwm)->INTSTS1 & (0x3f << u32BrakeSource)) ? 1 : 0);
+}
+
+/**
+ * @brief Enable period interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
+ * @return None
+ * @details This function is used to enable period interrupt of selected channel.
+ */
+void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType)
+{
+    (pwm)->INTEN0 |= (PWM_INTEN0_PIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Disable period interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable period interrupt of selected channel.
+ */
+void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->INTEN0 &= ~(PWM_INTEN0_PIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Clear period interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear period interrupt of selected channel.
+ */
+void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->INTSTS0 = (PWM_INTSTS0_PIF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get period interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return Period interrupt flag of specified channel
+ * @retval 0 Period interrupt did not occur
+ * @retval 1 Period interrupt occurred
+ * @details This function is used to get period interrupt of selected channel.
+ */
+uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    return ((((pwm)->INTSTS0 & (PWM_INTSTS0_PIF0_Msk << u32ChannelNum))) ? 1 : 0);
+}
+
+/**
+ * @brief Enable zero interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable zero interrupt of selected channel.
+ */
+void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->INTEN0 |= (PWM_INTEN0_ZIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Disable zero interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable zero interrupt of selected channel.
+ */
+void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->INTEN0 &= ~(PWM_INTEN0_ZIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Clear zero interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear zero interrupt of selected channel.
+ */
+void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->INTSTS0 = (PWM_INTSTS0_ZIF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get zero interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return Zero interrupt flag of specified channel
+ * @retval 0 Zero interrupt did not occur
+ * @retval 1 Zero interrupt occurred
+ * @details This function is used to get zero interrupt of selected channel.
+ */
+uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    return ((((pwm)->INTSTS0 & (PWM_INTSTS0_ZIF0_Msk << u32ChannelNum))) ? 1 : 0);
+}
+
+/**
+ * @brief Enable interrupt flag accumulator of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~15.
+ * @param[in] u32IntAccSrc Interrupt flag accumulator source selection.
+ *              - \ref PWM_IFA_EVEN_ZERO_POINT
+ *              - \ref PWM_IFA_EVEN_PERIOD_POINT
+ *              - \ref PWM_IFA_EVEN_COMPARE_UP_COUNT_POINT
+ *              - \ref PWM_IFA_EVEN_COMPARE_DOWN_COUNT_POINT
+ *              - \ref PWM_IFA_ODD_ZERO_POINT
+ *              - \ref PWM_IFA_ODD_PERIOD_POINT
+ *              - \ref PWM_IFA_ODD_COMPARE_UP_COUNT_POINT
+ *              - \ref PWM_IFA_ODD_COMPARE_DOWN_COUNT_POINT
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void PWM_EnableAcc(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc)
+{
+    (pwm)->IFA = ((pwm)->IFA & ~((PWM_IFA_IFCNT0_1_Msk | PWM_IFA_IFSEL0_1_Msk) << ((u32ChannelNum >> 1) * 8))) | \
+                 ((PWM_IFA_IFAEN0_1_Msk | (u32IntAccSrc << PWM_IFA_IFSEL0_1_Pos) | u32IntFlagCnt) << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Disable interrupt flag accumulator of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to Disable interrupt flag accumulator of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void PWM_DisableAcc(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->IFA = (pwm)->IFA & ~(PWM_IFA_IFAEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Enable interrupt flag accumulator interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator interrupt of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void PWM_EnableAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->INTEN0 |= (PWM_INTEN0_IFAIEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Disable interrupt flag accumulator interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable interrupt flag accumulator interrupt of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void PWM_DisableAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->INTEN0 &= ~(PWM_INTEN0_IFAIEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Clear interrupt flag accumulator interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear interrupt flag accumulator interrupt of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void PWM_ClearAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->INTSTS0 = (PWM_INTSTS0_IFAIF0_1_Msk << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Get interrupt flag accumulator interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @retval 0 Accumulator interrupt did not occur
+ * @retval 1 Accumulator interrupt occurred
+ * @details This function is used to Get interrupt flag accumulator interrupt of selected channel.
+ * @note Every two channels share the same setting.
+ */
+uint32_t PWM_GetAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    return (((pwm)->INTSTS0 & (PWM_INTSTS0_IFAIF0_1_Msk << ((u32ChannelNum >> 1) * 8))) ? 1 : 0);
+}
+
+/**
+ * @brief Clear free trigger duty interrupt flag of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear free trigger duty interrupt flag of selected channel.
+ */
+void PWM_ClearFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->FTCI = ((PWM_FTCI_FTCMU0_Msk | PWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1));
+}
+
+/**
+ * @brief Get free trigger duty interrupt flag of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Free trigger duty interrupt did not occur
+ * @retval 1 Free trigger duty interrupt occurred
+ * @details This function is used to get free trigger duty interrupt flag of selected channel.
+ */
+uint32_t PWM_GetFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    return (((pwm)->FTCI & ((PWM_FTCI_FTCMU0_Msk | PWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1))) ? 1 : 0);
+}
+
+/**
+ * @brief Enable load mode of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode PWM counter loading mode.
+ *              - \ref PWM_LOAD_MODE_IMMEDIATE
+ *              - \ref PWM_LOAD_MODE_WINDOW
+ *              - \ref PWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to enable load mode of selected channel.
+ */
+void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+    (pwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Disable load mode of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode PWM counter loading mode.
+ *              - \ref PWM_LOAD_MODE_IMMEDIATE
+ *              - \ref PWM_LOAD_MODE_WINDOW
+ *              - \ref PWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to disable load mode of selected channel.
+ */
+void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+    (pwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Configure synchronization phase of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32SyncSrc PWM synchronize source selection.
+ *              - \ref PWM_SYNC_OUT_FROM_SYNCIN_SWSYNC
+ *              - \ref PWM_SYNC_OUT_FROM_COUNT_TO_ZERO
+ *              - \ref PWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR
+ *              - \ref PWM_SYNC_OUT_DISABLE
+ * @param[in] u32Direction Phase direction. Control PWM counter count decrement or increment  after synchronizing.
+ *              - \ref PWM_PHS_DIR_DECREMENT
+ *              - \ref PWM_PHS_DIR_INCREMENT
+ * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535.
+ * @return None
+ * @details This function is used to configure synchronization phase of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void PWM_ConfigSyncPhase(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase)
+{
+    // every two channels shares the same setting
+    u32ChannelNum >>= 1;
+    (pwm)->SYNC = (((pwm)->SYNC & ~((PWM_SYNC_SINSRC0_Msk << (u32ChannelNum << 1)) | (PWM_SYNC_PHSDIR0_Msk << u32ChannelNum))) | \
+                   (u32Direction << PWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | (u32SyncSrc << PWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1));
+    *(__IO uint32_t *)(&((pwm)->PHS0_1) + u32ChannelNum) = u32StartPhase;
+}
+
+
+/**
+ * @brief Enable SYNC phase of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable SYNC phase of selected channel(s).
+ * @note Every two channels share the same setting.
+ */
+void PWM_EnableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+    uint32_t i;
+    for(i = 0; i < PWM_CHANNEL_NUM; i ++)
+    {
+        if(u32ChannelMask & (1 << i))
+        {
+            (pwm)->SYNC |= (PWM_SYNC_PHSEN0_Msk << (i >> 1));
+        }
+    }
+}
+
+/**
+ * @brief Disable SYNC phase of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable SYNC phase of selected channel(s).
+ * @note Every two channels share the same setting.
+ */
+void PWM_DisableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+    uint32_t i;
+    for(i = 0; i < PWM_CHANNEL_NUM; i ++)
+    {
+        if(u32ChannelMask & (1 << i))
+        {
+            (pwm)->SYNC &= ~(PWM_SYNC_PHSEN0_Msk << (i >> 1));
+        }
+    }
+}
+
+/**
+ * @brief Enable PWM SYNC_IN noise filter function
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector.
+ *            The valid value is 0~7.
+ * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
+ *              - \ref PWM_NF_CLK_DIV_1
+ *              - \ref PWM_NF_CLK_DIV_2
+ *              - \ref PWM_NF_CLK_DIV_4
+ *              - \ref PWM_NF_CLK_DIV_8
+ *              - \ref PWM_NF_CLK_DIV_16
+ *              - \ref PWM_NF_CLK_DIV_32
+ *              - \ref PWM_NF_CLK_DIV_64
+ *              - \ref PWM_NF_CLK_DIV_128
+ * @return None
+ * @details This function is used to enable PWM SYNC_IN noise filter function.
+ */
+void PWM_EnableSyncNoiseFilter(PWM_T *pwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
+{
+    (pwm)->SYNC = ((pwm)->SYNC & ~(PWM_SYNC_SFLTCNT_Msk | PWM_SYNC_SFLTCSEL_Msk)) | \
+                  ((u32ClkCnt << PWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << PWM_SYNC_SFLTCSEL_Pos) | PWM_SYNC_SNFLTEN_Msk);
+}
+
+/**
+ * @brief Disable PWM SYNC_IN noise filter function
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @return None
+ * @details This function is used to Disable PWM SYNC_IN noise filter function.
+ */
+void PWM_DisableSyncNoiseFilter(PWM_T *pwm)
+{
+    (pwm)->SYNC &= ~PWM_SYNC_SNFLTEN_Msk;
+}
+
+/**
+ * @brief Enable PWM SYNC input pin inverse function
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @return None
+ * @details This function is used to enable PWM SYNC input pin inverse function.
+ */
+void PWM_EnableSyncPinInverse(PWM_T *pwm)
+{
+    (pwm)->SYNC |= PWM_SYNC_SINPINV_Msk;
+}
+
+/**
+ * @brief Disable PWM SYNC input pin inverse function
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @return None
+ * @details This function is used to Disable PWM SYNC input pin inverse function.
+ */
+void PWM_DisableSyncPinInverse(PWM_T *pwm)
+{
+    (pwm)->SYNC &= ~PWM_SYNC_SINPINV_Msk;
+}
+
+/**
+ * @brief Set PWM clock source
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32ClkSrcSel PWM external clock source.
+ *              - \ref PWM_CLKSRC_PWM_CLK
+ *              - \ref PWM_CLKSRC_TIMER0
+ *              - \ref PWM_CLKSRC_TIMER1
+ *              - \ref PWM_CLKSRC_TIMER2
+ *              - \ref PWM_CLKSRC_TIMER3
+ * @return None
+ * @details This function is used to set PWM clock source.
+ * @note Every two channels share the same setting.
+ */
+void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
+{
+    (pwm)->CLKSRC = (pwm)->CLKSRC & ~(PWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1) * PWM_CLKSRC_ECLKSRC2_Pos)) | \
+                    (u32ClkSrcSel << ((u32ChannelNum >> 1) * PWM_CLKSRC_ECLKSRC2_Pos));
+}
+
+/**
+ * @brief Enable PWM brake noise filter function
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector
+ * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
+ *              - \ref PWM_NF_CLK_DIV_1
+ *              - \ref PWM_NF_CLK_DIV_2
+ *              - \ref PWM_NF_CLK_DIV_4
+ *              - \ref PWM_NF_CLK_DIV_8
+ *              - \ref PWM_NF_CLK_DIV_16
+ *              - \ref PWM_NF_CLK_DIV_32
+ *              - \ref PWM_NF_CLK_DIV_64
+ *              - \ref PWM_NF_CLK_DIV_128
+ * @return None
+ * @details This function is used to enable PWM brake noise filter function.
+ */
+void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
+{
+    (pwm)->BNF = ((pwm)->BNF & ~((PWM_BNF_BRK0FCNT_Msk | PWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos))) | \
+                 (((u32ClkCnt << PWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << PWM_BNF_BRK0NFSEL_Pos) | PWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
+}
+
+/**
+ * @brief Disable PWM brake noise filter function
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to disable PWM brake noise filter function.
+ */
+void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum)
+{
+    (pwm)->BNF &= ~(PWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
+}
+
+/**
+ * @brief Enable PWM brake pin inverse function
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to enable PWM brake pin inverse function.
+ */
+void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
+{
+    (pwm)->BNF |= (PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
+}
+
+/**
+ * @brief Disable PWM brake pin inverse function
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to disable PWM brake pin inverse function.
+ */
+void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
+{
+    (pwm)->BNF &= ~(PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
+}
+
+/**
+ * @brief Set PWM brake pin source
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE.
+ * @return None
+ * @details This function is used to set PWM brake pin source.
+ * @note This function is only supported in M45xD/M45xC.
+ */
+void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
+{
+    (pwm)->BNF = ((pwm)->BNF & ~(PWM_BNF_BK0SRC_Msk << (u32BrakePinNum * 8))) | (u32SelAnotherModule << (PWM_BNF_BK0SRC_Pos + u32BrakePinNum * 8));
+}
+
+/**
+ * @brief Get the time-base counter reached its maximum value flag of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return Count to max interrupt flag of specified channel
+ * @retval 0 Count to max interrupt did not occur
+ * @retval 1 Count to max interrupt occurred
+ * @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
+ */
+uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    return (((pwm)->STATUS & (PWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1 : 0);
+}
+
+/**
+ * @brief Clear the time-base counter reached its maximum value flag of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ *                - PWM0 : PWM Group 0
+ *                - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
+ */
+void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+    (pwm)->STATUS = (PWM_STATUS_CNTMAXF0_Msk << u32ChannelNum);
+}
+
+
+/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group PWM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pwm.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pwm.h
new file mode 100644
index 00000000000..916131622c0
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pwm.h
@@ -0,0 +1,560 @@
+/**************************************************************************//**
+ * @file     pwm.h
+ * @version  V1.00
+ * $Revision: 26 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series PWM driver header file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __PWM_H__
+#define __PWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup PWM_Driver PWM Driver
+  @{
+*/
+
+/** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants
+  @{
+*/
+#define PWM_CHANNEL_NUM                          (6)        /*!< PWM channel number */
+#define PWM_CH_0_MASK                            (0x1UL)    /*!< PWM channel 0 mask \hideinitializer */
+#define PWM_CH_1_MASK                            (0x2UL)    /*!< PWM channel 1 mask \hideinitializer */
+#define PWM_CH_2_MASK                            (0x4UL)    /*!< PWM channel 2 mask \hideinitializer */
+#define PWM_CH_3_MASK                            (0x8UL)    /*!< PWM channel 3 mask \hideinitializer */
+#define PWM_CH_4_MASK                            (0x10UL)   /*!< PWM channel 4 mask \hideinitializer */
+#define PWM_CH_5_MASK                            (0x20UL)   /*!< PWM channel 5 mask \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Counter Type Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_UP_COUNTER                           (0UL)      /*!< Up counter type */
+#define PWM_DOWN_COUNTER                         (1UL)      /*!< Down counter type */
+#define PWM_UP_DOWN_COUNTER                      (2UL)      /*!< Up-Down counter type */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Aligned Type Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_EDGE_ALIGNED                         (1UL)      /*!< PWM working in edge aligned type(down count) */
+#define PWM_CENTER_ALIGNED                       (2UL)      /*!< PWM working in center aligned type */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Output Level Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_OUTPUT_NOTHING                       (0UL)      /*!< PWM output nothing */
+#define PWM_OUTPUT_LOW                           (1UL)      /*!< PWM output low */
+#define PWM_OUTPUT_HIGH                          (2UL)      /*!< PWM output high */
+#define PWM_OUTPUT_TOGGLE                        (3UL)      /*!< PWM output toggle */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Trigger Source Select Constant Definitions                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_TRIGGER_ADC_EVEN_ZERO_POINT                     (0UL)     /*!< PWM trigger ADC while counter of even channel matches zero point */
+#define PWM_TRIGGER_ADC_EVEN_PERIOD_POINT                   (1UL)     /*!< PWM trigger ADC while counter of even channel matches period point */
+#define PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT           (2UL)     /*!< PWM trigger ADC while counter of even channel matches zero or period point */
+#define PWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT         (3UL)     /*!< PWM trigger ADC while counter of even channel matches up count to comparator point */
+#define PWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT       (4UL)     /*!< PWM trigger ADC while counter of even channel matches down count to comparator point */
+#define PWM_TRIGGER_ADC_ODD_ZERO_POINT                      (5UL)     /*!< PWM trigger ADC while counter of odd channel matches zero point */
+#define PWM_TRIGGER_ADC_ODD_PERIOD_POINT                    (6UL)     /*!< PWM trigger ADC while counter of odd channel matches period point */
+#define PWM_TRIGGER_ADC_ODD_ZERO_OR_PERIOD_POINT            (7UL)     /*!< PWM trigger ADC while counter of odd channel matches zero or period point */
+#define PWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT          (8UL)     /*!< PWM trigger ADC while counter of odd channel matches up count to comparator point */
+#define PWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT        (9UL)     /*!< PWM trigger ADC while counter of odd channel matches down count to comparator point */
+#define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_UP_COUNT_POINT    (10UL)    /*!< PWM trigger ADC while counter of channel 0 matches up count to free comparator point */
+#define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_DOWN_COUNT_POINT  (11UL)    /*!< PWM trigger ADC while counter of channel 0 matches down count to free comparator point */
+#define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_UP_COUNT_POINT    (12UL)    /*!< PWM trigger ADC while counter of channel 2 matches up count to free comparator point */
+#define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_DOWN_COUNT_POINT  (13UL)    /*!< PWM trigger ADC while counter of channel 2 matches down count to free comparator point */
+#define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_UP_COUNT_POINT    (14UL)    /*!< PWM trigger ADC while counter of channel 4 matches up count to free comparator point */
+#define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_DOWN_COUNT_POINT  (15UL)    /*!< PWM trigger ADC while counter of channel 4 matches down count to free comparator point */
+
+#define PWM_TRIGGER_DAC_ZERO_POINT                          (0x1UL)           /*!< PWM trigger ADC while counter down count to 0  \hideinitializer */
+#define PWM_TRIGGER_DAC_PERIOD_POINT                        (0x100UL)         /*!< PWM trigger ADC while counter matches (PERIOD + 1) \hideinitializer */
+#define PWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT              (0x10000UL)       /*!< PWM trigger ADC while counter up count to CMPDAT \hideinitializer */
+#define PWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT            (0x1000000UL)     /*!< PWM trigger ADC while counter down count to CMPDAT \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Fail brake Control Constant Definitions                                                                */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_FB_EDGE_ACMP0                        (PWM_BRKCTL0_1_CPO0EBEN_Msk)    /*!< Comparator 0 as edge-detect fault brake source */
+#define PWM_FB_EDGE_ACMP1                        (PWM_BRKCTL0_1_CPO1EBEN_Msk)    /*!< Comparator 1 as edge-detect fault brake source */
+#define PWM_FB_EDGE_BKP0                         (PWM_BRKCTL0_1_BRKP0EEN_Msk)    /*!< BKP0 pin as edge-detect fault brake source */
+#define PWM_FB_EDGE_BKP1                         (PWM_BRKCTL0_1_BRKP1EEN_Msk)    /*!< BKP1 pin as edge-detect fault brake source */
+#define PWM_FB_EDGE_SYS_CSS                      (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk)    /*!< System fail condition: clock security system detection as edge-detect fault brake source */
+#define PWM_FB_EDGE_SYS_BOD                      (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk)    /*!< System fail condition: brown-out detection as edge-detect fault brake source */
+#define PWM_FB_EDGE_SYS_RAM                      (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_RAMBRKEN_Msk)    /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source */
+#define PWM_FB_EDGE_SYS_COR                      (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk)    /*!< System fail condition: core lockup detection as edge-detect fault brake source */
+
+#define PWM_FB_LEVEL_ACMP0                       (PWM_BRKCTL0_1_CPO0LBEN_Msk)    /*!< Comparator 0 as level-detect fault brake source */
+#define PWM_FB_LEVEL_ACMP1                       (PWM_BRKCTL0_1_CPO1LBEN_Msk)    /*!< Comparator 1 as level-detect fault brake source */
+#define PWM_FB_LEVEL_BKP0                        (PWM_BRKCTL0_1_BRKP0LEN_Msk)    /*!< BKP0 pin as level-detect fault brake source */
+#define PWM_FB_LEVEL_BKP1                        (PWM_BRKCTL0_1_BRKP1LEN_Msk)    /*!< BKP1 pin as level-detect fault brake source */
+#define PWM_FB_LEVEL_SYS_CSS                     (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk)    /*!< System fail condition: clock security system detection as level-detect fault brake source */
+#define PWM_FB_LEVEL_SYS_BOD                     (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk)    /*!< System fail condition: brown-out detection as level-detect fault brake source */
+#define PWM_FB_LEVEL_SYS_RAM                     (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_RAMBRKEN_Msk)    /*!< System fail condition: SRAM parity error detection as level-detect fault brake source */
+#define PWM_FB_LEVEL_SYS_COR                     (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk)    /*!< System fail condition: core lockup detection as level-detect fault brake source */
+
+#define PWM_FB_EDGE                              (0UL)    /*!< edge-detect fault brake */
+#define PWM_FB_LEVEL                             (8UL)    /*!< level-detect fault brake */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Capture Control Constant Definitions                                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_CAPTURE_INT_RISING_LATCH             (1UL)        /*!< PWM capture interrupt if channel has rising transition */
+#define PWM_CAPTURE_INT_FALLING_LATCH            (0x100UL)    /*!< PWM capture interrupt if channel has falling transition */
+
+#define PWM_CAPTURE_PDMA_RISING_LATCH            (0x2UL)      /*!< PWM capture rising latched data transfer by PDMA */
+#define PWM_CAPTURE_PDMA_FALLING_LATCH           (0x4UL)      /*!< PWM capture falling latched data transfer by PDMA */
+#define PWM_CAPTURE_PDMA_RISING_FALLING_LATCH    (0x6UL)      /*!< PWM capture rising and falling latched data transfer by PDMA */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Duty Interrupt Type Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP        (PWM_INTEN0_CMPDIEN0_Msk)   /*!< PWM duty interrupt triggered if down count match comparator */
+#define PWM_DUTY_INT_UP_COUNT_MATCH_CMP          (PWM_INTEN0_CMPUIEN0_Msk)   /*!< PWM duty interrupt triggered if up down match comparator */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Interrupt Flag Accumulator Constant Definitions                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_IFA_EVEN_ZERO_POINT                  (0UL)         /*!< PWM counter equal to zero in even channel  \hideinitializer */
+#define PWM_IFA_EVEN_PERIOD_POINT                (1UL)         /*!< PWM counter equal to period in even channel \hideinitializer */
+#define PWM_IFA_EVEN_COMPARE_UP_COUNT_POINT      (2UL)         /*!< PWM counter up count to comparator value in even channel \hideinitializer */
+#define PWM_IFA_EVEN_COMPARE_DOWN_COUNT_POINT    (3UL)         /*!< PWM counter down count to comparator value in even channel \hideinitializer */
+#define PWM_IFA_ODD_ZERO_POINT                   (4UL)         /*!< PWM counter equal to zero in odd channel  \hideinitializer */
+#define PWM_IFA_ODD_PERIOD_POINT                 (5UL)         /*!< PWM counter equal to period in odd channel \hideinitializer */
+#define PWM_IFA_ODD_COMPARE_UP_COUNT_POINT       (6UL)         /*!< PWM counter up count to comparator value in odd channel \hideinitializer */
+#define PWM_IFA_ODD_COMPARE_DOWN_COUNT_POINT     (7UL)         /*!< PWM counter down count to comparator value in odd channel \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Load Mode Constant Definitions                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_LOAD_MODE_IMMEDIATE                  (PWM_CTL0_IMMLDEN0_Msk)    /*!< PWM immediately load mode \hideinitializer */
+#define PWM_LOAD_MODE_WINDOW                     (PWM_CTL0_WINLDEN0_Msk)    /*!< PWM window load mode \hideinitializer */
+#define PWM_LOAD_MODE_CENTER                     (PWM_CTL0_CTRLD0_Msk)      /*!< PWM center load mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Synchronize Control Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_SYNC_OUT_FROM_SYNCIN_SWSYNC          (0UL)    /*!< Synchronize source from SYNC_IN or SWSYNC  \hideinitializer */
+#define PWM_SYNC_OUT_FROM_COUNT_TO_ZERO          (1UL)    /*!< Synchronize source from counter equal to 0  \hideinitializer */
+#define PWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR    (2UL)    /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */
+#define PWM_SYNC_OUT_DISABLE                     (3UL)    /*!< SYNC_OUT will not be generated \hideinitializer */
+#define PWM_PHS_DIR_DECREMENT                    (0UL)    /*!< PWM counter count decrement  \hideinitializer */
+#define PWM_PHS_DIR_INCREMENT                    (1UL)    /*!< PWM counter count increment  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Noise Filter Clock Divide Select Constant Definitions                                                  */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_NF_CLK_DIV_1                         (0UL)    /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */
+#define PWM_NF_CLK_DIV_2                         (1UL)    /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */
+#define PWM_NF_CLK_DIV_4                         (2UL)    /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */
+#define PWM_NF_CLK_DIV_8                         (3UL)    /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */
+#define PWM_NF_CLK_DIV_16                        (4UL)    /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */
+#define PWM_NF_CLK_DIV_32                        (5UL)    /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */
+#define PWM_NF_CLK_DIV_64                        (6UL)    /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */
+#define PWM_NF_CLK_DIV_128                       (7UL)    /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Clock Source Select Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_CLKSRC_PWM_CLK                       (0UL)    /*!< PWM Clock source selects to PWM0_CLK or PWM1_CLK \hideinitializer */
+#define PWM_CLKSRC_TIMER0                        (1UL)    /*!< PWM Clock source selects to TIMER0 overflow \hideinitializer */
+#define PWM_CLKSRC_TIMER1                        (2UL)    /*!< PWM Clock source selects to TIMER1 overflow \hideinitializer */
+#define PWM_CLKSRC_TIMER2                        (3UL)    /*!< PWM Clock source selects to TIMER2 overflow \hideinitializer */
+#define PWM_CLKSRC_TIMER3                        (4UL)    /*!< PWM Clock source selects to TIMER3 overflow \hideinitializer */
+
+
+/*@}*/ /* end of group PWM_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
+  @{
+*/
+
+/**
+ * @brief This macro enable complementary mode
+ * @param[in] pwm The pointer of the specified PWM module
+ * @return None
+ * @details This macro is used to enable complementary mode of PWM module.
+ * \hideinitializer
+ */
+#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 | PWM_CTL1_OUTMODEn_Msk)
+
+/**
+ * @brief This macro disable complementary mode, and enable independent mode.
+ * @param[in] pwm The pointer of the specified PWM module
+ * @return None
+ * @details This macro is used to disable complementary mode of PWM module.
+ * \hideinitializer
+ */
+#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 & ~PWM_CTL1_OUTMODEn_Msk)
+
+/**
+ * @brief This macro enable group mode
+ * @param[in] pwm The pointer of the specified PWM module
+ * @return None
+ * @details This macro is used to enable group mode of PWM module.
+ * \hideinitializer
+ */
+#define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 | PWM_CTL0_GROUPEN_Msk)
+
+/**
+ * @brief This macro disable group mode
+ * @param[in] pwm The pointer of the specified PWM module
+ * @return None
+ * @details This macro is used to disable group mode of PWM module.
+ * \hideinitializer
+ */
+#define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 & ~PWM_CTL0_GROUPEN_Msk)
+
+/**
+ * @brief Enable timer synchronous mode of specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to enable timer synchronous mode of specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_ENABLE_TIMER_SYNC(pwm, u32ChannelMask) ((pwm)->SSCTL |= (u32ChannelMask))
+
+/**
+ * @brief Disable timer synchronous mode of specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to disable timer synchronous mode of specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_DISABLE_TIMER_SYNC(pwm, u32ChannelMask) \
+    do{ \
+        int i;\
+        for(i = 0; i < 6; i++) { \
+            if((u32ChannelMask) & (1 << i)) \
+                (pwm)->SSCTL &= ~(1UL << i); \
+        } \
+    }while(0)
+
+/**
+ * @brief This macro enable output inverter of specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to enable output inverter of specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->POLCTL = (u32ChannelMask))
+
+/**
+ * @brief This macro get captured rising data
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This macro is used to get captured rising data of specified channel.
+ * \hideinitializer
+ */
+#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->RCAPDAT0) + 2 * (u32ChannelNum)))
+
+/**
+ * @brief This macro get captured falling data
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This macro is used to get captured falling data of specified channel.
+ * \hideinitializer
+ */
+#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->FCAPDAT0) + 2 * (u32ChannelNum)))
+
+/**
+ * @brief This macro mask output logic to high or low
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32LevelMask Output logic to high or low
+ * @return None
+ * @details This macro is used to mask output logic to high or low of specified channel(s).
+ * @note If u32ChannelMask parameter is 0, then mask function will be disabled.
+ * \hideinitializer
+ */
+#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) \
+    { \
+        (pwm)->MSKEN = (u32ChannelMask); \
+        (pwm)->MSK = (u32LevelMask); \
+    }
+
+/**
+ * @brief This macro set the prescaler of the selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
+ * @return None
+ * @details This macro is used to set the prescaler of specified channel.
+ * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
+ *       channel 1 will also be affected.
+ * \hideinitializer
+ */
+#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) (*(__IO uint32_t *) (&((pwm)->CLKPSC0_1) + ((u32ChannelNum) >> 1)) = (u32Prescaler))
+
+/**
+ * @brief This macro set the comparator of the selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the comparator of specified channel.
+ * @note This new setting will take effect on next PWM period.
+ * \hideinitializer
+ */
+#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)]= (u32CMR))
+
+/**
+ * @brief This macro set the free trigger comparator of the selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the free trigger comparator of specified channel.
+ * @note This new setting will take effect on next PWM period.
+ * \hideinitializer
+ */
+#define PWM_SET_FTCMR(pwm, u32ChannelNum, u32FTCMR) (*(__IO uint32_t *) (&((pwm)->FTCMPDAT0_1) + ((u32ChannelNum) >> 1)) = (u32FTCMR))
+
+/**
+ * @brief This macro set the period of the selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the period of specified channel.
+ * @note This new setting will take effect on next PWM period.
+ * @note PWM counter will stop if period length set to 0.
+ * \hideinitializer
+ */
+#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR)  ((pwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
+
+/**
+ * @brief This macro set the PWM aligned type
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32AlignedType PWM aligned type, valid values are:
+ *              - \ref PWM_EDGE_ALIGNED
+ *              - \ref PWM_CENTER_ALIGNED
+ * @return None
+ * @details This macro is used to set the PWM aligned type of specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
+   do{ \
+        int i; \
+        for(i = 0; i < 6; i++) { \
+            if((u32ChannelMask) & (1 << i)) \
+                (pwm)->CTL1 = (((pwm)->CTL1 & ~(3UL << (2 * i))) | ((u32AlignedType) << ( 2 * i))); \
+        } \
+    }while(0)
+
+/**
+ * @brief Set load window of window loading mode for specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to set load window of window loading mode for specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_SET_LOAD_WINDOW(pwm, u32ChannelMask) ((pwm)->LOAD |= (u32ChannelMask))
+
+/**
+ * @brief Trigger synchronous event from specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are 0, 2, 4
+ *                           Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
+ * @return None
+ * @details This macro is used to trigger synchronous event from specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_TRIGGER_SYNC(pwm, u32ChannelNum) ((pwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1)))
+
+/**
+ * @brief Clear counter of specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to clear counter of specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_CLR_COUNTER(pwm, u32ChannelMask) ((pwm)->CNTCLR |= (u32ChannelMask))
+
+/**
+ * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32ZeroLevel output level at zero point, valid values are:
+ *              - \ref PWM_OUTPUT_NOTHING
+ *              - \ref PWM_OUTPUT_LOW
+ *              - \ref PWM_OUTPUT_HIGH
+ *              - \ref PWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpUpLevel output level at compare up point, valid values are:
+ *              - \ref PWM_OUTPUT_NOTHING
+ *              - \ref PWM_OUTPUT_LOW
+ *              - \ref PWM_OUTPUT_HIGH
+ *              - \ref PWM_OUTPUT_TOGGLE
+ * @param[in] u32PeriodLevel output level at period(center) point, valid values are:
+ *              - \ref PWM_OUTPUT_NOTHING
+ *              - \ref PWM_OUTPUT_LOW
+ *              - \ref PWM_OUTPUT_HIGH
+ *              - \ref PWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpDownLevel output level at compare down point, valid values are:
+ *              - \ref PWM_OUTPUT_NOTHING
+ *              - \ref PWM_OUTPUT_LOW
+ *              - \ref PWM_OUTPUT_HIGH
+ *              - \ref PWM_OUTPUT_TOGGLE
+ * @return None
+ * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_SET_OUTPUT_LEVEL(pwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
+   do{ \
+        int i; \
+        for(i = 0; i < 6; i++) { \
+            if((u32ChannelMask) & (1 << i)) { \
+                (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (2 * i))) | ((u32ZeroLevel) << (2 * i))); \
+                (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (PWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))) | ((u32PeriodLevel) << (PWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))); \
+                (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (2 * i))) | ((u32CmpUpLevel) << (2 * i))); \
+                (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (PWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))) | ((u32CmpDownLevel) << (PWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))); \
+            } \
+        } \
+    }while(0)
+
+/**
+ * @brief Trigger brake event from specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
+ * @param[in] u32BrakeType Type of brake trigger. PWM_FB_EDGE of this macro is only supported in M45xD/M45xC.
+ *              - \ref PWM_FB_EDGE
+ *              - \ref PWM_FB_LEVEL
+ * @return None
+ * @details This macro is used to trigger brake event from specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_TRIGGER_BRAKE(pwm, u32ChannelMask, u32BrakeType) ((pwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType)))
+
+/**
+ * @brief Set Dead zone clock source
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
+ * @return None
+ * @details This macro is used to set Dead zone clock source. Every two channels share the same setting.
+ * @note The write-protection function should be disabled before using this function.
+ * @note This function is only supported in M45xD/M45xC.
+ * \hideinitializer
+ */
+#define PWM_SET_DEADZONE_CLK_SRC(pwm, u32ChannelNum, u32AfterPrescaler) \
+    (*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1)) = (*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1)) & ~PWM_DTCTL0_1_DTCKSEL_Msk) | \
+    ((u32AfterPrescaler) << PWM_DTCTL0_1_DTCKSEL_Pos))
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define PWM functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
+uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
+uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
+                                 uint32_t u32ChannelNum,
+                                 uint32_t u32Frequency,
+                                 uint32_t u32DutyCycle,
+                                 uint32_t u32Frequency2);
+void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void PWM_DisableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t PWM_GetDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource);
+void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
+void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
+void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
+void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
+void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
+void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
+uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
+void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType);
+void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableAcc(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc);
+void PWM_DisableAcc(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_DisableAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
+uint32_t PWM_GetAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+uint32_t PWM_GetFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void PWM_ConfigSyncPhase(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase);
+void PWM_EnableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_DisableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnableSyncNoiseFilter(PWM_T *pwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
+void PWM_DisableSyncNoiseFilter(PWM_T *pwm);
+void PWM_EnableSyncPinInverse(PWM_T *pwm);
+void PWM_DisableSyncPinInverse(PWM_T *pwm);
+void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
+void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
+void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum);
+void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
+void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
+void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule);
+uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+
+
+/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group PWM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__PWM_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_rtc.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_rtc.c
new file mode 100644
index 00000000000..3489e4e6167
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_rtc.c
@@ -0,0 +1,789 @@
+/**************************************************************************//**
+ * @file     rtc.c
+ * @version  V3.00
+ * $Revision: 7 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series RTC driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+/// @cond HIDDEN_SYMBOLS
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macro, type and constant definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_GLOBALS
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global file scope (static) variables                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay;
+static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec;
+
+/// @endcond HIDDEN_SYMBOLS
+
+
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup RTC_Driver RTC Driver
+  @{
+*/
+
+/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Initialize RTC module and start counting
+  *
+  * @param[in]  sPt     Specify the time property and current date and time. It includes:           \n
+  *                     u32Year: Year value, range between 2000 ~ 2099.                             \n
+  *                     u32Month: Month value, range between 1 ~ 12.                                \n
+  *                     u32Day: Day value, range between 1 ~ 31.                                    \n
+  *                     u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+  *                                                     RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+  *                                                     RTC_SATURDAY]                               \n
+  *                     u32Hour: Hour value, range between 0 ~ 23.                                  \n
+  *                     u32Minute: Minute value, range between 0 ~ 59.                              \n
+  *                     u32Second: Second value, range between 0 ~ 59.                              \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                                 \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                                   \n
+  *
+  * @return     None
+  *
+  * @details    This function is used to: \n
+  *                 1. Write initial key to let RTC start count.  \n
+  *                 2. Input parameter indicates start date/time. \n
+  *                 3. User has to make sure that parameters of RTC date/time are reasonable. \n
+  * @note       Null pointer for using default starting date/time.
+  */
+void RTC_Open(S_RTC_TIME_DATA_T *sPt)
+{
+    RTC->INIT = RTC_INIT_KEY;
+
+    if(RTC->INIT != RTC_INIT_ACTIVE_Msk)
+    {
+        RTC->INIT = RTC_INIT_KEY;
+        while(RTC->INIT != RTC_INIT_ACTIVE_Msk);
+    }
+
+    if(sPt == 0)
+        return ;
+
+    /* Set RTC date and time */
+    RTC_SetDateAndTime(sPt);
+
+    /* Waiting for RTC settings stable */
+    while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == RTC_RWEN_RWENF_Msk);
+}
+
+/**
+  * @brief      Disable RTC Clock
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This API will disable RTC peripheral clock and stops RTC counting.
+  */
+void RTC_Close(void)
+{
+    CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
+}
+
+/**
+  * @brief      Set 32k Frequency Compensation Data
+  *
+  * @param[in]  i32FrequencyX100    Specify the RTC clock X100, ex: 3277365 means 32773.65.
+  *
+  * @return     None
+  *
+  * @details    This API is used to compensate the 32 kHz frequency by current LXT frequency for RTC application.
+  */
+void RTC_32KCalibration(int32_t i32FrequencyX100)
+{
+    int32_t i32RegInt, i32RegFra;
+
+    /* Compute integer and fraction for RTC FCR register */
+    i32RegInt = (i32FrequencyX100 / 100) - RTC_FCR_REFERENCE;
+    i32RegFra = (((i32FrequencyX100 % 100)) * 60) / 100;
+
+    /* Judge Integer part is reasonable */
+    if((i32RegInt < 0) | (i32RegInt > 15))
+    {
+        return ;
+    }
+
+    RTC_WaitAccessEnable();
+    RTC->FREQADJ = (uint32_t)((i32RegInt << 8) | i32RegFra);
+}
+
+/**
+  * @brief      Get Current RTC Date and Time
+  *
+  * @param[out] sPt     The returned pointer is specified the current RTC value. It includes: \n
+  *                     u32Year: Year value                                                   \n
+  *                     u32Month: Month value                                                 \n
+  *                     u32Day: Day value                                                     \n
+  *                     u32DayOfWeek: Day of week                                             \n
+  *                     u32Hour: Hour value                                                   \n
+  *                     u32Minute: Minute value                                               \n
+  *                     u32Second: Second value                                               \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                           \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                             \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to get the current RTC date and time value.
+  */
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+    uint32_t u32Tmp;
+
+    sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk;     /* 12/24-hour */
+    sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
+
+    /* Get [Date digit] data */
+    g_u32hiYear  = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos;
+    g_u32loYear  = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos;
+    g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos;
+    g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos;
+    g_u32hiDay   = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos;
+    g_u32loDay   = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos;
+
+    /* Get [Time digit] data */
+    g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos;
+    g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos;
+    g_u32hiMin  = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos;
+    g_u32loMin  = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos;
+    g_u32hiSec  = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos;
+    g_u32loSec  = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos;
+
+    /* Compute to 20XX year */
+    u32Tmp  = (g_u32hiYear * 10);
+    u32Tmp += g_u32loYear;
+    sPt->u32Year = u32Tmp + RTC_YEAR2000;
+
+    /* Compute 0~12 month */
+    u32Tmp = (g_u32hiMonth * 10);
+    sPt->u32Month = u32Tmp + g_u32loMonth;
+
+    /* Compute 0~31 day */
+    u32Tmp = (g_u32hiDay * 10);
+    sPt->u32Day =  u32Tmp  + g_u32loDay;
+
+    /* Compute 12/24 hour */
+    if(sPt->u32TimeScale == RTC_CLOCK_12)
+    {
+        u32Tmp = (g_u32hiHour * 10);
+        u32Tmp += g_u32loHour;
+        sPt->u32Hour = u32Tmp;          /* AM: 1~12. PM: 21~32. */
+
+        if(sPt->u32Hour >= 21)
+        {
+            sPt->u32AmPm  = RTC_PM;
+            sPt->u32Hour -= 20;
+        }
+        else
+        {
+            sPt->u32AmPm = RTC_AM;
+        }
+
+        u32Tmp  = (g_u32hiMin  * 10);
+        u32Tmp += g_u32loMin;
+        sPt->u32Minute = u32Tmp;
+
+        u32Tmp  = (g_u32hiSec  * 10);
+        u32Tmp += g_u32loSec;
+        sPt->u32Second = u32Tmp;
+    }
+    else
+    {
+        u32Tmp  = (g_u32hiHour * 10);
+        u32Tmp += g_u32loHour;
+        sPt->u32Hour = u32Tmp;
+
+        u32Tmp  = (g_u32hiMin * 10);
+        u32Tmp +=  g_u32loMin;
+        sPt->u32Minute = u32Tmp;
+
+        u32Tmp  = (g_u32hiSec * 10);
+        u32Tmp += g_u32loSec;
+        sPt->u32Second = u32Tmp;
+    }
+}
+
+/**
+  * @brief      Get RTC Alarm Date and Time
+  *
+  * @param[out] sPt     The returned pointer is specified the RTC alarm value. It includes: \n
+  *                     u32Year: Year value                                                 \n
+  *                     u32Month: Month value                                               \n
+  *                     u32Day: Day value                                                   \n
+  *                     u32DayOfWeek: Day of week                                           \n
+  *                     u32Hour: Hour value                                                 \n
+  *                     u32Minute: Minute value                                             \n
+  *                     u32Second: Second value                                             \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                         \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                           \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to get the RTC alarm date and time setting.
+  */
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+    uint32_t u32Tmp;
+
+    sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk;     /* 12/24-hour */
+    sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
+
+    /* Get alarm [Date digit] data */
+    RTC_WaitAccessEnable();
+    g_u32hiYear  = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos;
+    g_u32loYear  = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos;
+    g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos;
+    g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos;
+    g_u32hiDay   = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos;
+    g_u32loDay   = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos;
+
+    /* Get alarm [Time digit] data */
+    RTC_WaitAccessEnable();
+    g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos;
+    g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos;
+    g_u32hiMin  = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos;
+    g_u32loMin  = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos;
+    g_u32hiSec  = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos;
+    g_u32loSec  = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos;
+
+    /* Compute to 20XX year */
+    u32Tmp  = (g_u32hiYear * 10);
+    u32Tmp += g_u32loYear;
+    sPt->u32Year = u32Tmp + RTC_YEAR2000;
+
+    /* Compute 0~12 month */
+    u32Tmp = (g_u32hiMonth * 10);
+    sPt->u32Month = u32Tmp + g_u32loMonth;
+
+    /* Compute 0~31 day */
+    u32Tmp = (g_u32hiDay * 10);
+    sPt->u32Day = u32Tmp + g_u32loDay;
+
+    /* Compute 12/24 hour */
+    if(sPt->u32TimeScale == RTC_CLOCK_12)
+    {
+        u32Tmp  = (g_u32hiHour * 10);
+        u32Tmp += g_u32loHour;
+        sPt->u32Hour = u32Tmp;          /* AM: 1~12. PM: 21~32. */
+
+        if(sPt->u32Hour >= 21)
+        {
+            sPt->u32AmPm  = RTC_PM;
+            sPt->u32Hour -= 20;
+        }
+        else
+        {
+            sPt->u32AmPm = RTC_AM;
+        }
+
+        u32Tmp  = (g_u32hiMin * 10);
+        u32Tmp += g_u32loMin;
+        sPt->u32Minute = u32Tmp;
+
+        u32Tmp  = (g_u32hiSec * 10);
+        u32Tmp += g_u32loSec;
+        sPt->u32Second = u32Tmp;
+
+    }
+    else
+    {
+        u32Tmp  = (g_u32hiHour * 10);
+        u32Tmp +=  g_u32loHour;
+        sPt->u32Hour = u32Tmp;
+
+        u32Tmp  = (g_u32hiMin * 10);
+        u32Tmp += g_u32loMin;
+        sPt->u32Minute = u32Tmp;
+
+        u32Tmp  = (g_u32hiSec * 10);
+        u32Tmp += g_u32loSec;
+        sPt->u32Second = u32Tmp;
+    }
+}
+
+/**
+  * @brief      Update Current RTC Date and Time
+  *
+  * @param[in]  sPt     Specify the time property and current date and time. It includes:           \n
+  *                     u32Year: Year value, range between 2000 ~ 2099.                             \n
+  *                     u32Month: Month value, range between 1 ~ 12.                                \n
+  *                     u32Day: Day value, range between 1 ~ 31.                                    \n
+  *                     u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+  *                                                     RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+  *                                                     RTC_SATURDAY]                               \n
+  *                     u32Hour: Hour value, range between 0 ~ 23.                                  \n
+  *                     u32Minute: Minute value, range between 0 ~ 59.                              \n
+  *                     u32Second: Second value, range between 0 ~ 59.                              \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                                 \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                                   \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to update current date and time to RTC.
+  */
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+    uint32_t u32RegCAL, u32RegTIME;
+
+    if(sPt == 0)
+        return ;
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Set RTC 24/12 hour setting and Day of the Week                                                      */
+    /*-----------------------------------------------------------------------------------------------------*/
+    RTC_WaitAccessEnable();
+    if(sPt->u32TimeScale == RTC_CLOCK_12)
+    {
+        RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+
+        /*-------------------------------------------------------------------------------------------------*/
+        /* Important, range of 12-hour PM mode is 21 up to 32                                               */
+        /*-------------------------------------------------------------------------------------------------*/
+        if(sPt->u32AmPm == RTC_PM)
+            sPt->u32Hour += 20;
+    }
+    else
+    {
+        RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+    }
+
+    /* Set Day of the Week */
+    RTC->WEEKDAY = sPt->u32DayOfWeek;
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Set RTC Current Date and Time                                                                       */
+    /*-----------------------------------------------------------------------------------------------------*/
+    u32RegCAL  = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20;
+    u32RegCAL |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16);
+    u32RegCAL |= ((sPt->u32Month  / 10) << 12);
+    u32RegCAL |= ((sPt->u32Month  % 10) << 8);
+    u32RegCAL |= ((sPt->u32Day    / 10) << 4);
+    u32RegCAL |= (sPt->u32Day     % 10);
+
+    u32RegTIME  = ((sPt->u32Hour   / 10) << 20);
+    u32RegTIME |= ((sPt->u32Hour   % 10) << 16);
+    u32RegTIME |= ((sPt->u32Minute / 10) << 12);
+    u32RegTIME |= ((sPt->u32Minute % 10) << 8);
+    u32RegTIME |= ((sPt->u32Second / 10) << 4);
+    u32RegTIME |= (sPt->u32Second % 10);
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Set RTC Calender and Time Loading                                                                   */
+    /*-----------------------------------------------------------------------------------------------------*/
+    RTC_WaitAccessEnable();
+    RTC->CAL  = (uint32_t)u32RegCAL;
+    RTC->TIME = (uint32_t)u32RegTIME;
+}
+
+/**
+  * @brief      Update RTC Alarm Date and Time
+  *
+  * @param[in]  sPt     Specify the time property and alarm date and time. It includes:             \n
+  *                     u32Year: Year value, range between 2000 ~ 2099.                             \n
+  *                     u32Month: Month value, range between 1 ~ 12.                                \n
+  *                     u32Day: Day value, range between 1 ~ 31.                                    \n
+  *                     u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+  *                                                     RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+  *                                                     RTC_SATURDAY]                               \n
+  *                     u32Hour: Hour value, range between 0 ~ 23.                                  \n
+  *                     u32Minute: Minute value, range between 0 ~ 59.                              \n
+  *                     u32Second: Second value, range between 0 ~ 59.                              \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                                 \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                                   \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to update alarm date and time setting to RTC.
+  */
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+    uint32_t u32RegCALM, u32RegTALM;
+
+    if(sPt == 0)
+        return ;
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Set RTC 24/12 hour setting and Day of the Week                                                      */
+    /*-----------------------------------------------------------------------------------------------------*/
+    RTC_WaitAccessEnable();
+    if(sPt->u32TimeScale == RTC_CLOCK_12)
+    {
+        RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+
+        /*-------------------------------------------------------------------------------------------------*/
+        /* Important, range of 12-hour PM mode is 21 up to 32                                               */
+        /*-------------------------------------------------------------------------------------------------*/
+        if(sPt->u32AmPm == RTC_PM)
+            sPt->u32Hour += 20;
+    }
+    else
+    {
+        RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+    }
+
+    /* Set Day of the Week */
+    RTC->WEEKDAY = sPt->u32DayOfWeek;
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Set RTC Alarm Date and Time                                                                         */
+    /*-----------------------------------------------------------------------------------------------------*/
+    u32RegCALM  = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20;
+    u32RegCALM |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16);
+    u32RegCALM |= ((sPt->u32Month  / 10) << 12);
+    u32RegCALM |= ((sPt->u32Month  % 10) << 8);
+    u32RegCALM |= ((sPt->u32Day    / 10) << 4);
+    u32RegCALM |= (sPt->u32Day    % 10);
+
+    u32RegTALM  = ((sPt->u32Hour   / 10) << 20);
+    u32RegTALM |= ((sPt->u32Hour   % 10) << 16);
+    u32RegTALM |= ((sPt->u32Minute / 10) << 12);
+    u32RegTALM |= ((sPt->u32Minute % 10) << 8);
+    u32RegTALM |= ((sPt->u32Second / 10) << 4);
+    u32RegTALM |= (sPt->u32Second % 10);
+
+    RTC_WaitAccessEnable();
+    RTC->CALM = (uint32_t)u32RegCALM;
+    RTC->TALM = (uint32_t)u32RegTALM;
+}
+
+/**
+  * @brief      Update RTC Current Date
+  *
+  * @param[in]  u32Year         The year calendar digit of current RTC setting.
+  * @param[in]  u32Month        The month calendar digit of current RTC setting.
+  * @param[in]  u32Day          The day calendar digit of current RTC setting.
+  * @param[in]  u32DayOfWeek    The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+  *                                                   RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+  *                                                   RTC_SATURDAY]
+  *
+  * @return     None
+  *
+  * @details    This API is used to update current date to RTC.
+  */
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek)
+{
+    uint32_t u32RegCAL;
+
+    u32RegCAL  = ((u32Year - RTC_YEAR2000) / 10) << 20;
+    u32RegCAL |= (((u32Year - RTC_YEAR2000) % 10) << 16);
+    u32RegCAL |= ((u32Month / 10) << 12);
+    u32RegCAL |= ((u32Month % 10) << 8);
+    u32RegCAL |= ((u32Day   / 10) << 4);
+    u32RegCAL |= (u32Day   % 10);
+
+    RTC_WaitAccessEnable();
+
+    /* Set Day of the Week */
+    RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;
+
+    /* Set RTC Calender Loading */
+    RTC->CAL = (uint32_t)u32RegCAL;
+}
+
+/**
+  * @brief      Update RTC Current Time
+  *
+  * @param[in]  u32Hour         The hour time digit of current RTC setting.
+  * @param[in]  u32Minute       The minute time digit of current RTC setting.
+  * @param[in]  u32Second       The second time digit of current RTC setting.
+  * @param[in]  u32TimeMode     The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
+  * @param[in]  u32AmPm         12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
+  *
+  * @return     None
+  *
+  * @details    This API is used to update current time to RTC.
+  */
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+    uint32_t u32RegTIME;
+
+    /* Important, range of 12-hour PM mode is 21 up to 32 */
+    if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
+        u32Hour += 20;
+
+    u32RegTIME  = ((u32Hour   / 10) << 20);
+    u32RegTIME |= ((u32Hour   % 10) << 16);
+    u32RegTIME |= ((u32Minute / 10) << 12);
+    u32RegTIME |= ((u32Minute % 10) << 8);
+    u32RegTIME |= ((u32Second / 10) << 4);
+    u32RegTIME |= (u32Second % 10);
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Set RTC 24/12 hour setting and Day of the Week                                                      */
+    /*-----------------------------------------------------------------------------------------------------*/
+    RTC_WaitAccessEnable();
+    if(u32TimeMode == RTC_CLOCK_12)
+    {
+        RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+    }
+    else
+    {
+        RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+    }
+
+    RTC->TIME = (uint32_t)u32RegTIME;
+}
+
+/**
+  * @brief      Update RTC Alarm Date
+  *
+  * @param[in]  u32Year         The year calendar digit of RTC alarm setting.
+  * @param[in]  u32Month        The month calendar digit of RTC alarm setting.
+  * @param[in]  u32Day          The day calendar digit of RTC alarm setting.
+  *
+  * @return     None
+  *
+  * @details    This API is used to update alarm date setting to RTC.
+  */
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day)
+{
+    uint32_t u32RegCALM;
+
+    u32RegCALM  = ((u32Year - RTC_YEAR2000) / 10) << 20;
+    u32RegCALM |= (((u32Year - RTC_YEAR2000) % 10) << 16);
+    u32RegCALM |= ((u32Month / 10) << 12);
+    u32RegCALM |= ((u32Month % 10) << 8);
+    u32RegCALM |= ((u32Day   / 10) << 4);
+    u32RegCALM |= (u32Day   % 10);
+
+    RTC_WaitAccessEnable();
+
+    /* Set RTC Alarm Date */
+    RTC->CALM = (uint32_t)u32RegCALM;
+}
+
+/**
+  * @brief      Update RTC Alarm Time
+  *
+  * @param[in]  u32Hour         The hour time digit of RTC alarm setting.
+  * @param[in]  u32Minute       The minute time digit of RTC alarm setting.
+  * @param[in]  u32Second       The second time digit of RTC alarm setting.
+  * @param[in]  u32TimeMode     The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
+  * @param[in]  u32AmPm         12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
+  *
+  * @return     None
+  *
+  * @details    This API is used to update alarm time setting to RTC.
+  */
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+    uint32_t u32RegTALM;
+
+    /* Important, range of 12-hour PM mode is 21 up to 32 */
+    if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
+        u32Hour += 20;
+
+    u32RegTALM  = ((u32Hour   / 10) << 20);
+    u32RegTALM |= ((u32Hour   % 10) << 16);
+    u32RegTALM |= ((u32Minute / 10) << 12);
+    u32RegTALM |= ((u32Minute % 10) << 8);
+    u32RegTALM |= ((u32Second / 10) << 4);
+    u32RegTALM |= (u32Second % 10);
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Set RTC 24/12 hour setting and Day of the Week                                                      */
+    /*-----------------------------------------------------------------------------------------------------*/
+    RTC_WaitAccessEnable();
+    if(u32TimeMode == RTC_CLOCK_12)
+    {
+        RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+    }
+    else
+    {
+        RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+    }
+
+    /* Set RTC Alarm Time */
+    RTC->TALM = (uint32_t)u32RegTALM;
+}
+
+/**
+  * @brief      Get Day of the Week
+  *
+  * @param      None
+  *
+  * @retval     0   Sunday
+  * @retval     1   Monday
+  * @retval     2   Tuesday
+  * @retval     3   Wednesday
+  * @retval     4   Thursday
+  * @retval     5   Friday
+  * @retval     6   Saturday
+  *
+  * @details    This API is used to get day of the week of current RTC date.
+  */
+uint32_t RTC_GetDayOfWeek(void)
+{
+    return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk);
+}
+
+/**
+  * @brief      Set RTC Tick Period Time
+  *
+  * @param[in]  u32TickSelection    It is used to set the RTC tick period time for Periodic Time Tick request. \n
+  *                                 It consists of:                                     \n
+  *                                     RTC_TICK_1_SEC: Time tick is 1 second           \n
+  *                                     RTC_TICK_1_2_SEC: Time tick is 1/2 second       \n
+  *                                     RTC_TICK_1_4_SEC: Time tick is 1/4 second       \n
+  *                                     RTC_TICK_1_8_SEC: Time tick is 1/8 second       \n
+  *                                     RTC_TICK_1_16_SEC: Time tick is 1/16 second     \n
+  *                                     RTC_TICK_1_32_SEC: Time tick is 1/32 second     \n
+  *                                     RTC_TICK_1_64_SEC: Time tick is 1/64 second     \n
+  *                                     RTC_TICK_1_128_SEC: Time tick is 1/128 second
+  *
+  * @return     None
+  *
+  * @details    This API is used to set RTC tick period time for each tick interrupt.
+  */
+void RTC_SetTickPeriod(uint32_t u32TickSelection)
+{
+    RTC_WaitAccessEnable();
+
+    RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection;
+}
+
+/**
+  * @brief      Enable RTC Interrupt
+  *
+  * @param[in]  u32IntFlagMask      Specify the interrupt source. It consists of:                    \n
+  *                                     RTC_INTEN_ALMIEN_Msk: Alarm interrupt                        \n
+  *                                     RTC_INTEN_TICKIEN_Msk: Tick interrupt                        \n
+  *                                     RTC_INTEN_SNPDIEN_Msk: Snooper Pin Event Detection interrupt \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the specify RTC interrupt function.
+  */
+void RTC_EnableInt(uint32_t u32IntFlagMask)
+{
+    RTC->INTEN |= u32IntFlagMask;
+}
+
+/**
+  * @brief      Disable RTC Interrupt
+  *
+  * @param[in]  u32IntFlagMask      Specify the interrupt source. It consists of:                    \n
+  *                                     RTC_INTEN_ALMIEN_Msk: Alarm interrupt                        \n
+  *                                     RTC_INTEN_TICKIEN_Msk: Tick interrupt                        \n
+  *                                     RTC_INTEN_SNPDIEN_Msk: Snooper Pin Event Detection interrupt \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the specify RTC interrupt function.
+  */
+void RTC_DisableInt(uint32_t u32IntFlagMask)
+{
+    if(u32IntFlagMask & RTC_INTEN_ALMIEN_Msk)
+    {
+        RTC->INTEN  &= ~RTC_INTEN_ALMIEN_Msk;
+        RTC->INTSTS = RTC_INTSTS_ALMIF_Msk;
+    }
+
+    if(u32IntFlagMask & RTC_INTEN_TICKIEN_Msk)
+    {
+        RTC->INTEN  &= ~RTC_INTEN_TICKIEN_Msk;
+        RTC->INTSTS = RTC_INTSTS_TICKIF_Msk;
+    }
+
+    if(u32IntFlagMask & RTC_INTEN_SNPDIEN_Msk)
+    {
+        RTC->INTEN  &= ~RTC_INTEN_SNPDIEN_Msk;
+        RTC->INTSTS = RTC_INTSTS_SNPDIF_Msk;
+    }
+}
+
+/**
+  * @brief      Enable Spare Registers Access
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the spare registers 0~19 can be accessed.
+  */
+void RTC_EnableSpareAccess(void)
+{
+    RTC_WaitAccessEnable();
+
+    RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;
+
+    while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
+}
+
+/**
+  * @brief      Disable Spare Register
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the spare register 0~19 cannot be accessed.
+  */
+void RTC_DisableSpareRegister(void)
+{
+    RTC_WaitAccessEnable();
+
+    RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk;
+}
+
+/**
+  * @brief      Enable Snooper Pin Detect
+  *
+  * @param[in]  u32PinCondition     Snooper pin trigger condition. Possible options are
+  *                                 - \ref RTC_SNOOPER_LOW_LEVEL
+  *                                 - \ref RTC_SNOOPER_HIGH_LEVEL
+  *                                 - \ref RTC_SNOOPER_FALLING_EDGE
+  *                                 - \ref RTC_SNOOPER_RISING_EDGE
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the snooper pin detect function with specify trigger condition.
+  */
+void RTC_EnableSnooperDetection(uint32_t u32PinCondition)
+{
+    RTC_WaitAccessEnable();
+
+    RTC->SPRCTL = ((RTC->SPRCTL & ~RTC_SNOOPER_DETECT_Msk) | u32PinCondition) | RTC_SPRCTL_SNPDEN_Msk;
+}
+
+/**
+  * @brief      Disable Snooper Pin Detect
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the snooper pin detect function.
+  */
+void RTC_DisableSnooperDetection(void)
+{
+    RTC_WaitAccessEnable();
+
+    RTC->SPRCTL &= ~RTC_SPRCTL_SNPDEN_Msk;
+}
+
+/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group RTC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_rtc.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_rtc.h
new file mode 100644
index 00000000000..fd0c44222d6
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_rtc.h
@@ -0,0 +1,272 @@
+/**************************************************************************//**
+ * @file     rtc.h
+ * @version  V3.00
+ * $Revision: 10 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series RTC driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __RTC_H__
+#define __RTC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup RTC_Driver RTC Driver
+  @{
+*/
+
+/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Initial Keyword Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_INIT_KEY            0xA5EB1357UL    /*!< RTC Initiation Key to make RTC leaving reset state */
+#define RTC_WRITE_KEY           0x0000A965UL    /*!< RTC Register Access Enable Key to enable RTC read/write accessible and kept 1024 RTC clock */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Time Attribute Constant Definitions                                                                */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_CLOCK_12            0               /*!< RTC as 12-hour time scale with AM and PM indication */
+#define RTC_CLOCK_24            1               /*!< RTC as 24-hour time scale */
+#define RTC_AM                  1               /*!< RTC as AM indication */
+#define RTC_PM                  2               /*!< RTC as PM indication */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Tick Period Constant Definitions                                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_TICK_1_SEC          0x0UL           /*!< RTC time tick period is 1 second */
+#define RTC_TICK_1_2_SEC        0x1UL           /*!< RTC time tick period is 1/2 second */
+#define RTC_TICK_1_4_SEC        0x2UL           /*!< RTC time tick period is 1/4 second */
+#define RTC_TICK_1_8_SEC        0x3UL           /*!< RTC time tick period is 1/8 second */
+#define RTC_TICK_1_16_SEC       0x4UL           /*!< RTC time tick period is 1/16 second */
+#define RTC_TICK_1_32_SEC       0x5UL           /*!< RTC time tick period is 1/32 second */
+#define RTC_TICK_1_64_SEC       0x6UL           /*!< RTC time tick period is 1/64 second */
+#define RTC_TICK_1_128_SEC      0x7UL           /*!< RTC time tick period is 1/128 second */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Day of Week Constant Definitions                                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_SUNDAY              0x0UL           /*!< Day of the Week is Sunday */
+#define RTC_MONDAY              0x1UL           /*!< Day of the Week is Monday */
+#define RTC_TUESDAY             0x2UL           /*!< Day of the Week is Tuesday */
+#define RTC_WEDNESDAY           0x3UL           /*!< Day of the Week is Wednesday */
+#define RTC_THURSDAY            0x4UL           /*!< Day of the Week is Thursday */
+#define RTC_FRIDAY              0x5UL           /*!< Day of the Week is Friday */
+#define RTC_SATURDAY            0x6UL           /*!< Day of the Week is Saturday */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Snooper Detection Mode Constant Definitions                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_SNOOPER_LOW_LEVEL       0x0UL       /*!< Snooper pin detected is low-level trigger */
+#define RTC_SNOOPER_HIGH_LEVEL      0x2UL       /*!< Snooper pin detected is high-level trigger */
+#define RTC_SNOOPER_FALLING_EDGE    0x8UL       /*!< Snooper pin detected is falling-edge trigger */
+#define RTC_SNOOPER_RISING_EDGE     0xAUL       /*!< Snooper pin detected is rising-edge trigger */
+#define RTC_SNOOPER_DETECT_Msk      0xAUL       /*!< Snooper pin detected mask bits */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Miscellaneous Constant Definitions                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_WAIT_COUNT          0xFFFFFFFF      /*!< Initial Time-out Value */
+#define RTC_YEAR2000            2000            /*!< RTC Reference for compute year data */
+#define RTC_FCR_REFERENCE       32761           /*!< RTC Reference for frequency compensation */
+
+/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs
+  @{
+*/
+/**
+  * @details    RTC define Time Data Struct
+  */
+typedef struct
+{
+    uint32_t u32Year;           /*!< Year value */
+    uint32_t u32Month;          /*!< Month value */
+    uint32_t u32Day;            /*!< Day value */
+    uint32_t u32DayOfWeek;      /*!< Day of week value */
+    uint32_t u32Hour;           /*!< Hour value */
+    uint32_t u32Minute;         /*!< Minute value */
+    uint32_t u32Second;         /*!< Second value */
+    uint32_t u32TimeScale;      /*!< 12-Hour, 24-Hour */
+    uint32_t u32AmPm;           /*!< Only Time Scale select 12-hr used */
+} S_RTC_TIME_DATA_T;
+
+/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */
+
+
+/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Indicate is Leap Year or not
+  *
+  * @param      None
+  *
+  * @retval     0   This year is not a leap year
+  * @retval     1   This year is a leap year
+  *
+  * @details    According to current date, return this year is leap year or not.
+  */
+#define RTC_IS_LEAP_YEAR()              (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0)
+
+/**
+  * @brief      Clear RTC Alarm Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear RTC alarm interrupt flag.
+  */
+#define RTC_CLEAR_ALARM_INT_FLAG()      (RTC->INTSTS = (RTC->INTSTS & ~(RTC_INTSTS_TICKIF_Msk | RTC_INTSTS_SNPDIF_Msk)) | RTC_INTSTS_ALMIF_Msk)
+
+/**
+  * @brief      Clear RTC Tick Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear RTC tick interrupt flag.
+  */
+#define RTC_CLEAR_TICK_INT_FLAG()       (RTC->INTSTS = (RTC->INTSTS & ~(RTC_INTSTS_ALMIF_Msk | RTC_INTSTS_SNPDIF_Msk)) | RTC_INTSTS_TICKIF_Msk)
+
+/**
+  * @brief      Clear RTC Snooper Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear RTC snooper pin interrupt flag.
+  */
+#define RTC_CLEAR_SNOOPER_INT_FLAG()    (RTC->INTSTS = (RTC->INTSTS & ~(RTC_INTSTS_ALMIF_Msk | RTC_INTSTS_TICKIF_Msk)) | RTC_INTSTS_SNPDIF_Msk)
+
+/**
+  * @brief      Get RTC Alarm Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   RTC alarm interrupt did not occur
+  * @retval     1   RTC alarm interrupt occurred
+  *
+  * @details    This macro indicates RTC alarm interrupt occurred or not.
+  */
+#define RTC_GET_ALARM_INT_FLAG()        ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0)
+
+/**
+  * @brief      Get RTC Time Tick Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   RTC time tick interrupt did not occur
+  * @retval     1   RTC time tick interrupt occurred
+  *
+  * @details    This macro indicates RTC time tick interrupt occurred or not.
+  */
+#define RTC_GET_TICK_INT_FLAG()         ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0)
+
+/**
+  * @brief      Get RTC Snooper Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   RTC snooper pin interrupt did not occur
+  * @retval     1   RTC snooper pin interrupt occurred
+  *
+  * @details    This macro indicates RTC snooper pin interrupt occurred or not.
+  */
+#define RTC_GET_SNPPOER_INT_FLAG()      ((RTC->INTSTS & RTC_INTSTS_SNPDIF_Msk)? 1:0)
+
+/**
+  * @brief      Read Spare Register
+  *
+  * @param[in]  u32RegNum   The spare register number, 0~19.
+  *
+  * @return     Spare register content
+  *
+  * @details    Read the specify spare register content.
+  * @note       The returned value is valid only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n
+  *             And its controlled by RTC Access Enable Register.
+  */
+#define RTC_READ_SPARE_REGISTER(u32RegNum)                  (RTC->SPR[(u32RegNum)])
+
+/**
+  * @brief      Write Spare Register
+  *
+  * @param[in]  u32RegNum    The spare register number, 0~19.
+  * @param[in]  u32RegValue  The spare register value.
+  *
+  * @return     None
+  *
+  * @details    Write specify data to spare register.
+  * @note       This macro is effect only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n
+  *             And its controlled by RTC Access Enable Register(RTC_RWEN).
+  */
+#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue)    (RTC->SPR[(u32RegNum)] = (u32RegValue))
+
+/**
+  * @brief      Wait RTC Access Enable
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the maximum RTC read/write accessible time.
+  */
+static __INLINE void RTC_WaitAccessEnable(void)
+{
+    /* To wait RWENF bit is cleared and enable RWENF bit (Access Enable bit) again */
+    while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == RTC_RWEN_RWENF_Msk);
+    RTC->RWEN = RTC_WRITE_KEY;
+
+    /* To wait RWENF bit is set and user can access the protected-register of RTC from now on */
+    while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == 0x0);
+}
+
+void RTC_Open(S_RTC_TIME_DATA_T *sPt);
+void RTC_Close(void);
+void RTC_32KCalibration(int32_t i32FrequencyX100);
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+uint32_t RTC_GetDayOfWeek(void);
+void RTC_SetTickPeriod(uint32_t u32TickSelection);
+void RTC_EnableInt(uint32_t u32IntFlagMask);
+void RTC_DisableInt(uint32_t u32IntFlagMask);
+void RTC_EnableSpareAccess(void);
+void RTC_DisableSpareRegister(void);
+void RTC_EnableSnooperDetection(uint32_t u32PinCondition);
+void RTC_DisableSnooperDetection(void);
+
+/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group RTC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__RTC_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sc.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sc.c
new file mode 100644
index 00000000000..85aa2bb7b8c
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sc.c
@@ -0,0 +1,299 @@
+/**************************************************************************//**
+ * @file     sc.c
+ * @version  V3.00
+ * $Revision: 9 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series Smartcard(SC) driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+// Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined
+/// @cond HIDDEN_SYMBOLS
+static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0};
+
+/// @endcond HIDDEN_SYMBOLS
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SC_Driver SC Driver
+  @{
+*/
+
+
+/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions
+  @{
+*/
+
+/**
+  * @brief This function indicates specified smartcard slot status.
+  * @param[in] sc The pointer of smartcard module.
+  * @retval TRUE Card insert.
+  * @retval FALSE Card remove.
+  * @details This function is used to check if specified smart card slot is presented.
+  */
+uint32_t SC_IsCardInserted(SC_T *sc)
+{
+    // put conditions into two variable to remove IAR compilation warning
+    uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos);
+    uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos);
+
+    if(sc == SC0 && u32CardStateIgnore[0] == 1)
+        return TRUE;
+#if 0 /* M451 series has only one SC interface */    
+    else if(sc == SC1 && u32CardStateIgnore[1] == 1)
+        return TRUE;
+    else if(sc == SC2 && u32CardStateIgnore[2] == 1)
+        return TRUE;
+    else if(sc == SC3 && u32CardStateIgnore[3] == 1)
+        return TRUE;
+    else if(sc == SC4 && u32CardStateIgnore[4] == 1)
+        return TRUE;
+    else if(sc == SC5 && u32CardStateIgnore[5] == 1)
+        return TRUE;    
+#endif    
+    else if(cond1 != cond2)
+        return FALSE;
+    else
+        return TRUE;
+}
+
+/**
+  * @brief Reset the Tx/Rx FIFO.
+  * @param[in] sc The pointer of smartcard module.
+  * @return None
+  * @details This function reset both transmit and receive FIFO of specified smartcard module.
+  */
+void SC_ClearFIFO(SC_T *sc)
+{
+    sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk);
+}
+
+/**
+  * @brief This function disable specified smartcard module.
+  * @param[in] sc The pointer of smartcard module.
+  * @return None
+  * @details SC will force all transition to IDLE state.
+  */
+void SC_Close(SC_T *sc)
+{
+    sc->INTEN = 0;
+    sc->PINCTL = 0;
+    sc->ALTCTL = 0;
+    sc->CTL = 0;
+}
+
+/**
+  * @brief This function initialized smartcard module.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32CD Card detect polarity, select the CD pin state which indicates card insert. Could be:
+  *                 -\ref SC_PIN_STATE_HIGH.
+  *                 -\ref SC_PIN_STATE_LOW.
+  *                 -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present.
+  * @param[in] u32PWR Power on polarity, select the PWR pin state which could set smartcard VCC to high level. Could be:
+  *                 -\ref SC_PIN_STATE_HIGH.
+  *                 -\ref SC_PIN_STATE_LOW.
+  * @return None
+  * @details Initialization process configures smartcard and enables engine clock.
+  */
+void SC_Open(SC_T *sc, uint32_t u32CD, uint32_t u32PWR)
+{
+    uint32_t u32Reg = 0, u32Intf;
+
+    if(sc == SC0)
+        u32Intf = 0;
+#if 0 /* M451 series has only one SC interface */    
+    else if(sc == SC1)
+        u32Intf = 1;
+    else if(sc == SC2)
+        u32Intf = 2;
+    else if(sc == SC3)
+        u32Intf = 3;
+    else if(sc == SC4)
+        u32Intf = 4;
+    else if(sc == SC5)
+        u32Intf = 5;
+#endif    
+    else
+        return ;
+
+    if(u32CD != SC_PIN_STATE_IGNORE) {
+        u32Reg = u32CD ? 0: SC_CTL_CDLV_Msk;
+        u32CardStateIgnore[u32Intf] = 0;
+    } else {
+        u32CardStateIgnore[u32Intf] = 1;
+    }
+    while(sc->PINCTL & SC_PINCTL_SYNC_Msk);
+    sc->PINCTL = u32PWR ? 0 : SC_PINCTL_PWRINV_Msk;
+    while(sc->CTL & SC_CTL_SYNC_Msk);
+    sc->CTL = SC_CTL_SCEN_Msk | u32Reg;
+}
+
+/**
+  * @brief This function reset specified smartcard module to its default state for activate smartcard.
+  * @param[in] sc The pointer of smartcard module.
+  * @return None
+  * @details Reset the Tx/Rx FIFO & clock & initial default parameter.
+  */
+void SC_ResetReader(SC_T *sc)
+{
+    uint32_t u32Intf;
+
+    if(sc == SC0)
+        u32Intf = 0;
+#if 0 /* M451 series has only one SC interface */    
+    else if(sc == SC1)
+        u32Intf = 1;
+    else if(sc == SC2)
+        u32Intf = 2;
+    else if(sc == SC3)
+        u32Intf = 3;
+    else if(sc == SC4)
+        u32Intf = 4;
+    else if(sc == SC5)
+        u32Intf = 5;
+#endif    
+    else
+        return ;
+
+	// Reset FIFO, enable auto de-activation while card removal
+    sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk);
+    // Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry)
+    while(sc->CTL & SC_CTL_SYNC_Msk);
+    sc->CTL &= ~(SC_CTL_RXTRGLV_Msk | SC_CTL_CDDBSEL_Msk | SC_CTL_TXRTY_Msk | SC_CTL_RXRTY_Msk);
+    // Enable auto convention, and all three smartcard internal timers
+    sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk;
+    // Disable Rx timeout
+    sc->RXTOUT = 0;
+    // 372 clocks per ETU by default
+    sc->ETUCTL = 371;
+
+    /* Enable necessary interrupt for smartcard operation */
+    if(u32CardStateIgnore[u32Intf]) // Do not enable card detect interrupt if card present state ignore
+        sc->INTEN = (SC_INTEN_RDAIEN_Msk |
+                     SC_INTEN_TERRIEN_Msk |
+                     SC_INTEN_TMR0IEN_Msk |
+                     SC_INTEN_TMR1IEN_Msk |
+                     SC_INTEN_TMR2IEN_Msk |
+                     SC_INTEN_BGTIEN_Msk |
+                     SC_INTEN_ACERRIEN_Msk);
+    else
+        sc->INTEN = (SC_INTEN_RDAIEN_Msk |
+                     SC_INTEN_TERRIEN_Msk |
+                     SC_INTEN_TMR0IEN_Msk |
+                     SC_INTEN_TMR1IEN_Msk |
+                     SC_INTEN_TMR2IEN_Msk |
+                     SC_INTEN_BGTIEN_Msk |
+                     SC_INTEN_ACERRIEN_Msk |
+                     SC_INTEN_CDIEN_Msk);
+
+    return;
+}
+
+/**
+  * @brief Set Block Guard Time.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32.
+  * @return None
+  * @details This function block guard time (BGT) of specified smartcard module.
+  */
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT)
+{
+    sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1) << SC_CTL_BGT_Pos);
+}
+
+/**
+  * @brief Set character guard time.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267.
+  * @return None
+  * @details This function character guard time (CGT) of specified smartcard module.
+  * @note Before using this API, user should set the correct stop bit length first.
+  */
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT)
+{
+    u32CGT -= sc->CTL & SC_CTL_NSB_Msk ? 11 : 12;
+    sc->EGT = u32CGT;
+}
+
+/**
+  * @brief Stop all Timer counting.
+  * @param[in] sc The pointer of smartcard module.
+  * @return None
+  * @details This function stop all smartcard timer of specified smartcard module.
+  * @note This function stop the timers within smartcard module, \b not timer module.
+  */
+void SC_StopAllTimer(SC_T *sc)
+{
+    sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk);
+}
+
+/**
+  * @brief This function configure and start a smartcard timer of specified smartcard module.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32TimerNum Timer(s) to start. Valid values are 0, 1, 2.
+  * @param[in] u32Mode Timer operating mode, valid values are:
+  *             - \ref SC_TMR_MODE_0
+  *             - \ref SC_TMR_MODE_1
+  *             - \ref SC_TMR_MODE_2
+  *             - \ref SC_TMR_MODE_3
+  *             - \ref SC_TMR_MODE_4
+  *             - \ref SC_TMR_MODE_5
+  *             - \ref SC_TMR_MODE_6
+  *             - \ref SC_TMR_MODE_7
+  *             - \ref SC_TMR_MODE_8
+  *             - \ref SC_TMR_MODE_F
+  * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid  range are between 1~0x1000000ETUs.
+  *                        For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs.
+  * @return None
+  * @details Enable Timer starting, counter will count when condition match.
+  * @note This function start the timer within smartcard module, \b not timer module.
+  * @note Depend on the timer operating mode, timer may not start counting immediately.
+  */
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount)
+{
+    uint32_t reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1));
+
+    if(u32TimerNum == 0) {
+        sc->TMRCTL0 = reg;
+        sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk;
+    } else if(u32TimerNum == 1) {
+        sc->TMRCTL1 = reg;
+        sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk;
+    } else {   // timer 2
+        sc->TMRCTL2 = reg;
+        sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk;
+    }
+}
+
+/**
+  * @brief Stop Timer counting.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32TimerNum Timer(s) to stop. Valid values are 0, 1, 2.
+  * @return None
+  * @details This function stop a smartcard timer of specified smartcard module.
+  * @note This function stop the timer within smartcard module, \b not timer module.
+  */
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum)
+{
+    if(u32TimerNum == 0)
+        sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk;
+    else if(u32TimerNum == 1)
+        sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk;
+    else    // timer 2
+        sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk;
+}
+
+
+
+/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sc.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sc.h
new file mode 100644
index 00000000000..295e872110b
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sc.h
@@ -0,0 +1,269 @@
+/**************************************************************************//**
+ * @file     sc.h
+ * @version  V3.00
+ * $Revision: 13 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series Smartcard (SC) driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SC_H__
+#define __SC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SC_Driver SC Driver
+  @{
+*/
+
+/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants
+  @{
+*/
+#define SC_INTERFACE_NUM        1                /*!< Smartcard interface numbers */ /* M451 series has only one SC interface */
+#define SC_PIN_STATE_HIGH       1                /*!< Smartcard pin status high   */
+#define SC_PIN_STATE_LOW        0                /*!< Smartcard pin status low    */
+#define SC_PIN_STATE_IGNORE     0xFFFFFFFF       /*!< Ignore pin status           */
+#define SC_CLK_ON               1                /*!< Smartcard clock on          */
+#define SC_CLK_OFF              0                /*!< Smartcard clock off         */
+
+#define SC_TMR_MODE_0                   (0ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 0, down count                                                      */
+#define SC_TMR_MODE_1                   (1ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 1, down count, start after detect start bit                        */
+#define SC_TMR_MODE_2                   (2ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 2, down count, start after receive start bit                       */
+#define SC_TMR_MODE_3                   (3ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 3, down count, use for activation, only timer 0 support this mode  */
+#define SC_TMR_MODE_4                   (4ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 4, down count with reload after timeout                            */
+#define SC_TMR_MODE_5                   (5ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 5, down count, start after detect start bit, reload after timeout  */
+#define SC_TMR_MODE_6                   (6ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 6, down count, start after receive start bit, reload after timeout */
+#define SC_TMR_MODE_7                   (7ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 7, down count, start and reload after detect start bit             */
+#define SC_TMR_MODE_8                   (8ul << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 8, up count                                                        */
+#define SC_TMR_MODE_F                   (0xF << SC_TMRCTL0_OPMODE_Pos)     /*!<Timer Operation Mode 15, down count, reload after detect start bit                      */
+
+
+/*@}*/ /* end of group SC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions
+  @{
+*/
+
+/**
+  * @brief Enable smartcard interrupt.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32Mask Interrupt mask to be enabled. A combination of
+  *             - \ref SC_INTEN_ACERRIEN_Msk
+  *             - \ref SC_INTEN_RXTOIF_Msk
+  *             - \ref SC_INTEN_INITIEN_Msk
+  *             - \ref SC_INTEN_CDIEN_Msk
+  *             - \ref SC_INTEN_BGTIEN_Msk
+  *             - \ref SC_INTEN_TMR2IEN_Msk
+  *             - \ref SC_INTEN_TMR1IEN_Msk
+  *             - \ref SC_INTEN_TMR0IEN_Msk
+  *             - \ref SC_INTEN_TERRIEN_Msk
+  *             - \ref SC_INTEN_TBEIEN_Msk
+  *             - \ref SC_INTEN_RDAIEN_Msk
+  * @return None
+  * @details The macro is used to enable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,
+  *          Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,
+  *          Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.
+  * \hideinitializer
+  */
+#define SC_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
+
+/**
+  * @brief Disable smartcard interrupt.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32Mask Interrupt mask to be disabled. A combination of
+  *             - \ref SC_INTEN_ACERRIEN_Msk
+  *             - \ref SC_INTEN_RXTOIF_Msk
+  *             - \ref SC_INTEN_INITIEN_Msk
+  *             - \ref SC_INTEN_CDIEN_Msk
+  *             - \ref SC_INTEN_BGTIEN_Msk
+  *             - \ref SC_INTEN_TMR2IEN_Msk
+  *             - \ref SC_INTEN_TMR1IEN_Msk
+  *             - \ref SC_INTEN_TMR0IEN_Msk
+  *             - \ref SC_INTEN_TERRIEN_Msk
+  *             - \ref SC_INTEN_TBEIEN_Msk
+  *             - \ref SC_INTEN_RDAIEN_Msk
+  * @return None
+  * @details The macro is used to disable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,
+  *          Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,
+  *          Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.
+  * \hideinitializer
+  */
+#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
+
+/**
+  * @brief This macro set VCC pin state of smartcard interface.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32State Pin state of VCC pin, valid parameters are:
+  *                 \ref SC_PIN_STATE_HIGH    :Smartcard pin status high.
+  *                 \ref SC_PIN_STATE_LOW     :Smartcard pin status low.
+  * @return None
+  * @details User can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.
+  * \hideinitializer
+  */
+#define SC_SET_VCC_PIN(sc, u32State) \
+    do {\
+            while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+            if(u32State)\
+                (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\
+            else\
+                (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\
+    }while(0)
+
+
+/**
+  * @brief Set CLK output status.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are:
+  *                 \ref SC_CLK_ON    :Smartcard clock on.
+  *                 \ref SC_CLK_OFF   :Smartcard clock off.
+  * @return None
+  * @details User can set CLKKEEP (SC_PINCTL[6]) to decide SC_CLK pin always keeps free running or not.
+  * \hideinitializer
+  */
+#define SC_SET_CLK_PIN(sc, u32OnOff)\
+    do {\
+            while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+            if(u32OnOff)\
+                (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\
+            else\
+                (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\
+    }while(0)
+
+/**
+  * @brief Set I/O pin state.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32State Pin state of I/O pin, valid parameters are:
+  *                 \ref SC_PIN_STATE_HIGH    :Smartcard pin status high.
+  *                 \ref SC_PIN_STATE_LOW     :Smartcard pin status low.
+  * @return None
+  * @details User can set SCDOUT(SC_PINCTL[9]) to decide SCDOUT pin to high or low.
+  * \hideinitializer
+  */
+#define SC_SET_IO_PIN(sc, u32State)\
+    do {\
+            while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+            if(u32State)\
+                (sc)->PINCTL |= SC_PINCTL_SCDOUT_Msk;\
+            else\
+                (sc)->PINCTL &= ~SC_PINCTL_SCDOUT_Msk;\
+    }while(0)
+
+/**
+  * @brief Set RST pin state.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32State Pin state of RST pin, valid parameters are:
+  *                 \ref SC_PIN_STATE_HIGH    :Smartcard pin status high.
+  *                 \ref SC_PIN_STATE_LOW     :Smartcard pin status low.
+  * @return None
+  * @details User can set SCRST(SC_PINCTL[1]) to decide SCRST pin to high or low.
+  * \hideinitializer
+  */
+#define SC_SET_RST_PIN(sc, u32State)\
+    do {\
+            while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+            if(u32State)\
+                (sc)->PINCTL |= SC_PINCTL_SCRST_Msk;\
+            else\
+                (sc)->PINCTL &= ~SC_PINCTL_SCRST_Msk;\
+    }while(0)
+
+/**
+  * @brief Read one byte from smartcard module receive FIFO.
+  * @param[in] sc The pointer of smartcard module.
+  * @return One byte read from receive FIFO.
+  * @details By reading DAT register, the SC will return an 8-bit received data.
+  * \hideinitializer
+  */
+#define SC_READ(sc) ((char)((sc)->DAT))
+
+/**
+  * @brief Write one byte to smartcard module transmit FIFO.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u8Data Data to write to transmit FIFO.
+  * @return None
+  * @details By writing data to DAT register, the SC will send out an 8-bit data.
+  * \hideinitializer
+  */
+#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
+
+/**
+  * @brief This macro set smartcard stop bit length.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32Len Stop bit length, ether 1 or 2.
+  * @return None
+  * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol.
+  * \hideinitializer
+  */
+#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | ((u32Len) == 1 ? SC_CTL_NSB_Msk : 0))
+
+/**
+  * @brief Enable/Disable Tx error retry, and set Tx error retry count.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry.
+  * @return None
+  * @details This macro enable/disable transmitter retry function when parity error has occurred, and set error retry count.
+  */
+__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count)
+{
+    while((sc)->CTL & SC_CTL_SYNC_Msk);
+    if(u32Count == 0) {       // disable Tx error retry
+        (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk);
+    } else {
+        (sc)->CTL = ((sc)->CTL & ~SC_CTL_TXRTY_Msk) | ((u32Count - 1) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk;
+    }
+}
+
+/**
+  * @brief Enable/Disable Rx error retry, and set Rx error retry count.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry.
+  * @return None
+  * @details This macro enable/disable receiver retry function when parity error has occurred, and set error retry count.
+  */
+__STATIC_INLINE void  SC_SetRxRetry(SC_T *sc, uint32_t u32Count)
+{
+    while((sc)->CTL & SC_CTL_SYNC_Msk);
+    if(u32Count == 0) {       // disable Rx error retry
+        (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk);
+    } else {
+        (sc)->CTL = ((sc)->CTL & ~SC_CTL_RXRTY_Msk) | ((u32Count - 1) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk;
+    }
+}
+
+
+uint32_t SC_IsCardInserted(SC_T *sc);
+void SC_ClearFIFO(SC_T *sc);
+void SC_Close(SC_T *sc);
+void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR);
+void SC_ResetReader(SC_T *sc);
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT);
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT);
+void SC_StopAllTimer(SC_T *sc);
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount);
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum);
+
+
+/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SC_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
+
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_scuart.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_scuart.c
new file mode 100644
index 00000000000..aca419e2228
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_scuart.c
@@ -0,0 +1,223 @@
+/**************************************************************************//**
+ * @file     scuart.c
+ * @version  V3.00
+ * $Revision: 8 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series Smartcard UART mode (SCUART) driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SCUART_Driver SCUART Driver
+  @{
+*/
+
+
+/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+  @{
+*/
+
+/**
+  * @brief Disable smartcard uart interface.
+  * @param sc The pointer of smartcard module.
+  * @return None
+  * @details The function is used to disable smartcard interface UART mode.
+  */
+void SCUART_Close(SC_T* sc)
+{
+    sc->INTEN = 0;
+    sc->UARTCTL = 0;
+    sc->CTL = 0;
+
+}
+
+/// @cond HIDDEN_SYMBOLS
+/**
+  * @brief This function returns module clock of specified SC interface
+  * @param[in] sc The pointer of smartcard module.
+  * @return Module clock of specified SC interface
+  */
+static uint32_t SCUART_GetClock(SC_T *sc)
+{
+    uint32_t u32ClkSrc, u32Num, u32Clk;
+
+    if(sc == SC0)
+        u32Num = 0;
+#if 0 /* M451 series has only one SC interface */    
+    else if(sc == SC1)
+        u32Num = 1;
+    else if(sc == SC2)
+        u32Num = 2;
+    else if(sc == SC3)
+        u32Num = 3;
+    else if(sc == SC4)
+        u32Num = 4;
+    else if(sc == SC5)
+        u32Intf = 5;
+#endif    
+    else
+        return FALSE;
+
+    u32ClkSrc = (CLK->CLKSEL3 >> (2 * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk;
+
+    // Get smartcard module clock
+    if(u32ClkSrc == 0)
+        u32Clk = __HXT;
+    else if(u32ClkSrc == 1)
+        u32Clk = CLK_GetPLLClockFreq();
+    else if(u32ClkSrc == 2) {
+        SystemCoreClockUpdate();
+        if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk)
+            u32Clk = SystemCoreClock / 2;
+        else
+            u32Clk = SystemCoreClock;
+    } else
+        u32Clk = __HIRC;
+
+#if 0 /* M451 series has only one SC interface */  
+    if(u32Num < 4) {
+        u32Clk /= (((CLK->CLKDIV1 >> (8 * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1);
+    } else {
+        u32Clk /= (((CLK->CLKDIV2 >> (8 * (u32Num - 4))) & CLK_CLKDIV2_SC4DIV_Msk) + 1);
+    }
+#else    
+    u32Clk /= (((CLK->CLKDIV1 >> (8 * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1);
+#endif    
+
+    return u32Clk;
+}
+/// @endcond HIDDEN_SYMBOLS
+
+/**
+  * @brief Enable smartcard uart interface.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32baudrate Target baudrate of smartcard module.
+  * @return Actual baudrate of smartcard mode.
+  * @details This function use to enable smartcard module UART mode and set baudrate.
+  * @note This function configures character width to 8 bits, 1 stop bit, and no parity.
+  *       And can use \ref SCUART_SetLineConfig function to update these settings.
+  */
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate)
+{
+    uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
+
+    // Calculate divider for target baudrate
+    u32Div = (u32Clk + (u32baudrate >> 1) - 1) / u32baudrate - 1;
+
+    sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk;  // Enable smartcard interface and stop bit = 1
+    sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; // Enable UART mode, disable parity and 8 bit per character
+    sc->ETUCTL = u32Div;
+
+    return(u32Clk / (u32Div+1));
+}
+
+/**
+  * @brief Read data from smartcard UART interface.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] pu8RxBuf The buffer to store receive the data.
+  * @param[in] u32ReadBytes Target number of characters to receive.
+  * @return Actual character number reads to buffer.
+  * @details The function is used to read Rx data from RX FIFO.
+  * @note This function does not block and return immediately if there's no data available.
+  */
+uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
+{
+    uint32_t u32Count;
+
+    for(u32Count = 0; u32Count < u32ReadBytes; u32Count++) {
+        if(SCUART_GET_RX_EMPTY(sc)) { // no data available
+            break;
+        }
+        pu8RxBuf[u32Count] = SCUART_READ(sc);    // get data from FIFO
+    }
+
+    return u32Count;
+}
+
+/**
+  * @brief This function use to config smartcard UART mode line setting.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change.
+  * @param[in] u32DataWidth The data length, could be:
+  *                 - \ref SCUART_CHAR_LEN_5
+  *                 - \ref SCUART_CHAR_LEN_6
+  *                 - \ref SCUART_CHAR_LEN_7
+  *                 - \ref SCUART_CHAR_LEN_8
+  * @param[in] u32Parity The parity setting, could be:
+  *                 - \ref SCUART_PARITY_NONE
+  *                 - \ref SCUART_PARITY_ODD
+  *                 - \ref SCUART_PARITY_EVEN
+  * @param[in] u32StopBits The stop bit length, could be:
+  *                 - \ref SCUART_STOP_BIT_1
+  *                 - \ref SCUART_STOP_BIT_2
+  * @return Actual baudrate of smartcard.
+  * @details Smartcard UART mode is operated in LIN data frame.
+  */
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t  u32StopBits)
+{
+
+    uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
+
+    if(u32Baudrate == 0) {  // keep original baudrate setting
+        u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk;
+    } else {
+        // Calculate divider for target baudrate
+        u32Div = (u32Clk + (u32Baudrate >> 1) - 1) / u32Baudrate - 1;
+        sc->ETUCTL = u32Div;
+    }
+
+    sc->CTL = u32StopBits | SC_CTL_SCEN_Msk;  // Set stop bit
+    sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk;  // Set character width and parity
+
+    return(u32Clk / (u32Div+1));
+}
+
+/**
+  * @brief This function use to set receive timeout count.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF,
+  *                   set this value to 0 will disable timeout counter.
+  * @return None
+  * @details The time-out counter resets and starts counting whenever the RX buffer received a
+  *          new data word. Once the counter decrease to 1 and no new data is received or CPU
+  *          does not read any data from FIFO, a receiver time-out interrupt will be generated.
+  */
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC)
+{
+    sc->RXTOUT = u32TOC;
+}
+
+
+/**
+  * @brief Write data to smartcard UART interface.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO.
+  * @param[in] u32WriteBytes Number of data to send.
+  * @return None
+  * @details This function is to write data into transmit FIFO to send data out.
+  * @note This function blocks until all data write into FIFO.
+  */
+void SCUART_Write(SC_T* sc, uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
+{
+    uint32_t u32Count;
+
+    for(u32Count = 0; u32Count != u32WriteBytes; u32Count++) {
+        while(SCUART_GET_TX_FULL(sc));  // Wait 'til FIFO not full
+        sc->DAT = pu8TxBuf[u32Count];    // Write 1 byte to FIFO
+    }
+}
+
+
+/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SCUART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_scuart.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_scuart.h
new file mode 100644
index 00000000000..0ab13abe696
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_scuart.h
@@ -0,0 +1,279 @@
+/**************************************************************************//**
+ * @file     sc.h
+ * @version  V3.00
+ * $Revision: 7 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series Smartcard UART mode (SCUART) driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SCUART_H__
+#define __SCUART_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SCUART_Driver SCUART Driver
+  @{
+*/
+
+/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
+  @{
+*/
+#define SCUART_CHAR_LEN_5     (0x3ul << SC_UARTCTL_WLS_Pos)  /*!< Set SCUART word length to 5 bits */
+#define SCUART_CHAR_LEN_6     (0x2ul << SC_UARTCTL_WLS_Pos)  /*!< Set SCUART word length to 6 bits */
+#define SCUART_CHAR_LEN_7     (0x1ul << SC_UARTCTL_WLS_Pos)  /*!< Set SCUART word length to 7 bits */
+#define SCUART_CHAR_LEN_8     (0)                            /*!< Set SCUART word length to 8 bits */
+
+#define SCUART_PARITY_NONE    (SC_UARTCTL_PBOFF_Msk)         /*!< Set SCUART transfer with no parity   */
+#define SCUART_PARITY_ODD     (SC_UARTCTL_OPE_Msk)           /*!< Set SCUART transfer with odd parity  */
+#define SCUART_PARITY_EVEN    (0)                            /*!< Set SCUART transfer with even parity */
+
+#define SCUART_STOP_BIT_1     (SC_CTL_NSB_Msk)                 /*!< Set SCUART transfer with one stop bit  */
+#define SCUART_STOP_BIT_2     (0)                               /*!< Set SCUART transfer with two stop bits */
+
+
+/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+  @{
+*/
+
+/* TX Macros */
+/**
+  * @brief Write Data to Tx data register.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u8Data Data byte to transmit.
+  * @return None
+  * @details By writing data to DAT register, the SC will send out an 8-bit data.
+  * \hideinitializer
+  */
+#define SCUART_WRITE(sc, u8Data) ((sc)-> DAT = (u8Data))
+
+/**
+  * @brief Get TX FIFO empty flag status from register.
+  * @param[in] sc The pointer of smartcard module.
+  * @return Transmit FIFO empty status.
+  * @retval 0 Transmit FIFO is not empty.
+  * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty.
+  * @details When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets TXEMPTY bit (SC_STATUS[9]) high.
+  *          It will be cleared when writing data into DAT (SC_DAT[7:0]).
+  * \hideinitializer
+  */
+#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)
+
+/**
+  * @brief Get TX FIFO full flag status from register.
+  * @param[in] sc The pointer of smartcard module.
+  * @retval 0 Transmit FIFO is not full.
+  * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full.
+  * @details TXFULL(SC_STATUS[10]) is set when TX pointer is equal to 4, otherwise is cleared by hardware.
+  * \hideinitializer
+  */
+#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk)
+
+/**
+  * @brief Wait specified smartcard port transmission complete.
+  * @param[in] sc The pointer of smartcard module.
+  * @return None
+  * @details TXACT (SC_STATUS[31]) is cleared automatically when TX transfer is finished or the last byte transmission has completed.
+  * @note This macro blocks until transmit complete.
+  * \hideinitializer
+  */
+#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk)
+
+/**
+  * @brief Check specified smartcard port transmit FIFO is full or not.
+  * @param[in] sc The pointer of smartcard module.
+  * @retval 0 Transmit FIFO is not full.
+  * @retval 1 Transmit FIFO is full.
+  * @details TXFULL(SC_STATUS[10]) indicates TX buffer full or not.
+  *          This is set when TX pointer is equal to 4, otherwise is cleared by hardware.
+  * \hideinitializer
+  */
+#define SCUART_IS_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0)
+
+/**
+  * @brief Check specified smartcard port transmission is over.
+  * @param[in] sc The pointer of smartcard module.
+  * @retval 0 Transmit is not complete.
+  * @retval 1 Transmit complete.
+  * @details TXACT (SC_STATUS[31]) is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.
+  * \hideinitializer
+  */
+#define SCUART_IS_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1)
+
+
+/* RX Macros */
+
+/**
+  * @brief Read Rx data register.
+  * @param[in] sc The pointer of smartcard module.
+  * @return The oldest data byte in RX FIFO.
+  * @details By reading DAT register, the SC will return an 8-bit received data.
+  * \hideinitializer
+  */
+#define SCUART_READ(sc) ((sc)->DAT)
+
+/**
+  * @brief Get RX FIFO empty flag status from register.
+  * @param[in] sc The pointer of smartcard module.
+  * @retval 0 Receive FIFO is not empty.
+  * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty.
+  * @details When the last byte of Rx buffer has been read by CPU, hardware sets RXEMPTY(SC_STATUS[1]) high.
+  *          It will be cleared when SC receives any new data.
+  * \hideinitializer
+  */
+#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk)
+
+
+/**
+  * @brief Get RX FIFO full flag status from register.
+  * @param[in] sc The pointer of smartcard module.
+  * @retval 0 Receive FIFO is not full.
+  * @retval SC_STATUS_TXFULL_Msk Receive FIFO is full.
+  * @details RXFULLF(SC_STATUS[2]) is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
+  * \hideinitializer
+  */
+#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk)
+
+/**
+  * @brief Check if receive data number in FIFO reach FIFO trigger level or not.
+  * @param[in] sc The pointer of smartcard module.
+  * @retval 0 The number of bytes in receive FIFO is less than trigger level.
+  * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level.
+  * @details RDAIF(SC_INTSTS[0]) is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
+  * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO.
+  * \hideinitializer
+  */
+#define SCUART_IS_RX_READY(sc) ((sc)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0)
+
+/**
+  * @brief Check specified smartcard port receive FIFO is full or not.
+  * @param[in] sc The pointer of smartcard module.
+  * @retval 0 Receive FIFO is not full.
+  * @retval 1 Receive FIFO is full.
+  * @details RXFULLF(SC_STATUS[2]) is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
+  * \hideinitializer
+  */
+#define SCUART_IS_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk ? 1 : 0)
+
+/* Interrupt Macros */
+
+/**
+  * @brief Enable specified interrupts.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32Mask Interrupt masks to enable, a combination of following bits.
+  *             - \ref SC_INTEN_RXTOIF_Msk
+  *             - \ref SC_INTEN_TERRIEN_Msk
+  *             - \ref SC_INTEN_TBEIEN_Msk
+  *             - \ref SC_INTEN_RDAIEN_Msk
+  * @return None
+  * @details The macro is used to enable receiver buffer time-out interrupt, transfer error interrupt,
+  *          transmit buffer empty interrupt or receive data reach trigger level interrupt.
+  * \hideinitializer
+  */
+#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
+
+/**
+  * @brief Disable specified interrupts.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32Mask Interrupt masks to disable, a combination of following bits.
+  *             - \ref SC_INTEN_RXTOIF_Msk
+  *             - \ref SC_INTEN_TERRIEN_Msk
+  *             - \ref SC_INTEN_TBEIEN_Msk
+  *             - \ref SC_INTEN_RDAIEN_Msk
+  * @return None
+  * @details The macro is used to disable receiver buffer time-out interrupt, transfer error interrupt,
+  *          transmit buffer empty interrupt or receive data reach trigger level interrupt.
+  * \hideinitializer
+  */
+#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
+
+/**
+  * @brief Get specified interrupt flag/status.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32Type Interrupt flag/status to check, could be one of following value:
+  *             - \ref SC_INTSTS_RBTOIF_Msk
+  *             - \ref SC_INTSTS_TERRIF_Msk
+  *             - \ref SC_INTSTS_TBEIF_Msk
+  *             - \ref SC_INTSTS_RDAIF_Msk
+  * @return The status of specified interrupt.
+  * @retval 0 Specified interrupt does not happened.
+  * @retval 1 Specified interrupt happened.
+  * @details The macro is used to get receiver buffer time-out interrupt status, transfer error interrupt status,
+  *          transmit buffer empty interrupt status or receive data reach interrupt status.
+  * \hideinitializer
+  */
+#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->INTSTS & (u32Type) ? 1 : 0)
+
+/**
+  * @brief Clear specified interrupt flag/status.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values:
+  *             - \ref SC_INTSTS_RBTOIF_Msk
+  *             - \ref SC_INTSTS_TERRIF_Msk
+  *             - \ref SC_INTSTS_TBEIF_Msk
+  * @return None
+  * @details The macro is used to clear receiver buffer time-out interrupt flag, transfer error interrupt flag or
+  *          transmit buffer empty interrupt flag.
+  * \hideinitializer
+  */
+#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type))
+
+/**
+  * @brief Get receive error flag/status.
+  * @param[in] sc The pointer of smartcard module.
+  * @return Current receive error status, could one of following errors:
+  * @retval SC_STATUS_PEF_Msk Parity error.
+  * @retval SC_STATUS_FEF_Msk Frame error.
+  * @retval SC_STATUS_BEF_Msk Break error.
+  * @details The macro is used to get receiver parity error status, receiver frame error status or
+  *          receiver break error status.
+  * \hideinitializer
+  */
+#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk))
+
+/**
+  * @brief Clear specified receive error flag/status.
+  * @param[in] sc The pointer of smartcard module.
+  * @param[in] u32Mask Receive error flag/status to clear, combination following values:
+  *             - \ref SC_STATUS_PEF_Msk
+  *             - \ref SC_STATUS_FEF_Msk
+  *             - \ref SC_STATUS_BEF_Msk
+  * @return None
+  * @details The macro is used to clear receiver parity error flag, receiver frame error flag or
+  *          receiver break error flag.
+  * \hideinitializer
+  */
+#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask))
+
+void SCUART_Close(SC_T* sc);
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate);
+uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t  u32StopBits);
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC);
+void SCUART_Write(SC_T* sc, uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
+
+/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SCUART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SCUART_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_spi.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_spi.c
new file mode 100644
index 00000000000..ad30b8e39a9
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_spi.c
@@ -0,0 +1,1154 @@
+/**************************************************************************//**
+ * @file     spi.c
+ * @version  V3.00
+ * $Revision: 11 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series SPI driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SPI_Driver SPI Driver
+  @{
+*/
+
+
+/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+  @{
+*/
+
+/**
+  * @brief  This function make SPI module be ready to transfer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER)
+  * @param[in]  u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3)
+  * @param[in]  u32DataWidth Decides the data width of a SPI transaction.
+  * @param[in]  u32BusClock The expected frequency of SPI bus clock in Hz.
+  * @return Actual frequency of SPI peripheral clock.
+  * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic
+  *          slave selection function is disabled.
+  *          In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0.
+  *          The actual clock rate may be different from the target SPI clock rate.
+  *          For example, if the SPI source clock rate is 12MHz and the target SPI bus clock rate is 7MHz, the
+  *          actual SPI clock rate will be 6MHz.
+  * @note   If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+  * @note   If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+  * @note   If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
+  * @note   In slave mode, the SPI peripheral clock rate will be equal to APB clock rate.
+  */
+uint32_t SPI_Open(SPI_T *spi,
+                  uint32_t u32MasterSlave,
+                  uint32_t u32SPIMode,
+                  uint32_t u32DataWidth,
+                  uint32_t u32BusClock)
+{
+    uint32_t u32ClkSrc = 0, u32Div, u32HCLKFreq;
+
+    if((spi == SPI1) || (spi == SPI2))
+        /* Disable I2S mode */
+        spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
+
+    if(u32DataWidth == 32)
+        u32DataWidth = 0;
+
+    /* Get system clock frequency */
+    u32HCLKFreq = CLK_GetHCLKFreq();
+
+    if(u32MasterSlave == SPI_MASTER)
+    {
+        /* Default setting: slave selection signal is active low; disable automatic slave selection function. */
+        spi->SSCTL = SPI_SS_ACTIVE_LOW;
+
+        /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+        spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
+
+        if(u32BusClock >= u32HCLKFreq)
+        {
+            /* Select PCLK as the clock source of SPI */
+            if(spi == SPI0)
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
+            else if(spi == SPI1)
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
+            else
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
+        }
+
+        /* Check clock source of SPI */
+        if(spi == SPI0)
+        {
+            if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
+                u32ClkSrc = __HXT; /* Clock source is HXT */
+            else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
+                u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+            else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0)
+            {
+                /* Clock source is PCLK0 */
+                if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+                    u32ClkSrc = (u32HCLKFreq / 2);
+                else
+                    u32ClkSrc = u32HCLKFreq;
+            }
+            else
+                u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+        else if(spi == SPI1)
+        {
+            if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
+                u32ClkSrc = __HXT; /* Clock source is HXT */
+            else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
+                u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+            else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1)
+            {
+                /* Clock source is PCLK1 */
+                if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
+                    u32ClkSrc = (u32HCLKFreq / 2);
+                else
+                    u32ClkSrc = u32HCLKFreq;
+            }
+            else
+                u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+        else
+        {
+            if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
+                u32ClkSrc = __HXT; /* Clock source is HXT */
+            else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
+                u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+            else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0)
+            {
+                /* Clock source is PCLK0 */
+                if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+                    u32ClkSrc = (u32HCLKFreq / 2);
+                else
+                    u32ClkSrc = u32HCLKFreq;
+            }
+            else
+                u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+
+        if(u32BusClock >= u32HCLKFreq)
+        {
+            /* Set DIVIDER = 0 */
+            spi->CLKDIV = 0;
+            /* Return master peripheral clock rate */
+            return u32ClkSrc;
+        }
+        else if(u32BusClock >= u32ClkSrc)
+        {
+            /* Set DIVIDER = 0 */
+            spi->CLKDIV = 0;
+            /* Return master peripheral clock rate */
+            return u32ClkSrc;
+        }
+        else if(u32BusClock == 0)
+        {
+            /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+            spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+            /* Return master peripheral clock rate */
+            return (u32ClkSrc / (0xFF + 1));
+        }
+        else
+        {
+            u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
+            if(u32Div > 0xFF)
+            {
+                u32Div = 0xFF;
+                spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+                /* Return master peripheral clock rate */
+                return (u32ClkSrc / (0xFF + 1));
+            }
+            else
+            {
+                spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
+                /* Return master peripheral clock rate */
+                return (u32ClkSrc / (u32Div + 1));
+            }
+        }
+    }
+    else     /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */
+    {
+        /* Default setting: slave selection signal is low level active. */
+        spi->SSCTL = SPI_SS_ACTIVE_LOW;
+
+        /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+        spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
+
+        /* Set DIVIDER = 0 */
+        spi->CLKDIV = 0;
+
+        /* Select PCLK as the clock source of SPI */
+        if(spi == SPI0)
+        {
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
+            /* Return slave peripheral clock rate */
+            if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+                return (u32HCLKFreq / 2);
+            else
+                return u32HCLKFreq;
+        }
+        else if(spi == SPI1)
+        {
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
+            /* Return slave peripheral clock rate */
+            if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
+                return (u32HCLKFreq / 2);
+            else
+                return u32HCLKFreq;
+        }
+        else
+        {
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
+            /* Return slave peripheral clock rate */
+            if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+                return (u32HCLKFreq / 2);
+            else
+                return u32HCLKFreq;
+        }
+    }
+}
+
+/**
+  * @brief  Disable SPI controller.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return None
+  * @details This function will reset SPI controller.
+  */
+void SPI_Close(SPI_T *spi)
+{
+    if(spi == SPI0)
+    {
+        /* Reset SPI */
+        SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
+    }
+    else if(spi == SPI1)
+    {
+        /* Reset SPI */
+        SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
+    }
+    else
+    {
+        /* Reset SPI */
+        SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
+    }
+}
+
+/**
+  * @brief  Clear RX FIFO buffer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return None
+  * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1.
+  */
+void SPI_ClearRxFIFO(SPI_T *spi)
+{
+    spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk;
+}
+
+/**
+  * @brief  Clear TX FIFO buffer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return None
+  * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1.
+  * @note The TX shift register will not be cleared.
+  */
+void SPI_ClearTxFIFO(SPI_T *spi)
+{
+    spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk;
+}
+
+/**
+  * @brief  Disable the automatic slave selection function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return None
+  * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.
+  */
+void SPI_DisableAutoSS(SPI_T *spi)
+{
+    spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk);
+}
+
+/**
+  * @brief  Enable the automatic slave selection function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32SSPinMask Specifies slave selection pins. (SPI_SS)
+  * @param[in]  u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW)
+  * @return None
+  * @details This function will enable the automatic slave selection function. Only available in Master mode.
+  *          The slave selection pin and the active level will be set in this function.
+  */
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
+{
+    spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk);
+}
+
+/**
+  * @brief  Set the SPI bus clock.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32BusClock The expected frequency of SPI bus clock in Hz.
+  * @return Actual frequency of SPI bus clock.
+  * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate.
+  *          For example, if the SPI source clock rate is 12MHz and the target SPI bus clock rate is 7MHz, the actual SPI bus clock
+  *          rate will be 6MHz.
+  * @note   If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+  * @note   If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+  * @note   If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
+  */
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
+{
+    uint32_t u32ClkSrc, u32HCLKFreq;
+    uint32_t u32Div;
+
+    /* Get system clock frequency */
+    u32HCLKFreq = CLK_GetHCLKFreq();
+
+    if(u32BusClock >= u32HCLKFreq)
+    {
+        /* Select PCLK as the clock source of SPI */
+        if(spi == SPI0)
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
+        else if(spi == SPI1)
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
+        else
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
+    }
+
+    /* Check clock source of SPI */
+    if(spi == SPI0)
+    {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0)
+        {
+            /* Clock source is PCLK0 */
+            if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+                u32ClkSrc = (u32HCLKFreq / 2);
+            else
+                u32ClkSrc = u32HCLKFreq;
+        }
+        else
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+    }
+    else if(spi == SPI1)
+    {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1)
+        {
+            /* Clock source is PCLK1 */
+            if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
+                u32ClkSrc = (u32HCLKFreq / 2);
+            else
+                u32ClkSrc = u32HCLKFreq;
+        }
+        else
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+    }
+    else
+    {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0)
+        {
+            /* Clock source is PCLK0 */
+            if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+                u32ClkSrc = (u32HCLKFreq / 2);
+            else
+                u32ClkSrc = u32HCLKFreq;
+        }
+        else
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+    }
+
+    if(u32BusClock >= u32HCLKFreq)
+    {
+        /* Set DIVIDER = 0 */
+        spi->CLKDIV = 0;
+        /* Return master peripheral clock rate */
+        return u32ClkSrc;
+    }
+    else if(u32BusClock >= u32ClkSrc)
+    {
+        /* Set DIVIDER = 0 */
+        spi->CLKDIV = 0;
+        /* Return master peripheral clock rate */
+        return u32ClkSrc;
+    }
+    else if(u32BusClock == 0)
+    {
+        /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+        spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+        /* Return master peripheral clock rate */
+        return (u32ClkSrc / (0xFF + 1));
+    }
+    else
+    {
+        u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
+        if(u32Div > 0xFF)
+        {
+            u32Div = 0xFF;
+            spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+            /* Return master peripheral clock rate */
+            return (u32ClkSrc / (0xFF + 1));
+        }
+        else
+        {
+            spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
+            /* Return master peripheral clock rate */
+            return (u32ClkSrc / (u32Div + 1));
+        }
+    }
+}
+
+/**
+  * @brief  Configure FIFO threshold setting.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32TxThreshold Decides the TX FIFO threshold. For SPI0, it could be 0 ~ 7. For SPI1 and SPI2, it could be 0 ~ 3.
+  * @param[in]  u32RxThreshold Decides the RX FIFO threshold. For SPI0, it could be 0 ~ 7. For SPI1 and SPI2, it could be 0 ~ 3.
+  * @return None
+  * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+  */
+void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+    spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk) |
+                    (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
+                    (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos));
+}
+
+/**
+  * @brief  Get the actual frequency of SPI bus clock. Only available in Master mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return Actual SPI bus clock frequency in Hz.
+  * @details This function will calculate the actual SPI bus clock rate according to the SPInSEL and DIVIDER settings. Only available in Master mode.
+  */
+uint32_t SPI_GetBusClock(SPI_T *spi)
+{
+    uint32_t u32Div;
+    uint32_t u32ClkSrc, u32HCLKFreq;
+
+    /* Get DIVIDER setting */
+    u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos;
+
+    /* Get system clock frequency */
+    u32HCLKFreq = CLK_GetHCLKFreq();
+
+    /* Check clock source of SPI */
+    if(spi == SPI0)
+    {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0)
+        {
+            /* Clock source is PCLK0 */
+            if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+                u32ClkSrc = (u32HCLKFreq / 2);
+            else
+                u32ClkSrc = u32HCLKFreq;
+        }
+        else
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+    }
+    else if(spi == SPI1)
+    {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1)
+        {
+            /* Clock source is PCLK1 */
+            if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
+                u32ClkSrc = (u32HCLKFreq / 2);
+            else
+                u32ClkSrc = u32HCLKFreq;
+        }
+        else
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+    }
+    else
+    {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0)
+        {
+            /* Clock source is PCLK0 */
+            if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+                u32ClkSrc = (u32HCLKFreq / 2);
+            else
+                u32ClkSrc = u32HCLKFreq;
+        }
+        else
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+    }
+
+    /* Return SPI bus clock rate */
+    return (u32ClkSrc / (u32Div + 1));
+}
+
+/**
+  * @brief  Enable interrupt function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt enable bits.
+  *                     Each bit corresponds to a interrupt enable bit.
+  *                     This parameter decides which interrupts will be enabled. It is combination of:
+  *                       - \ref SPI_UNIT_INT_MASK
+  *                       - \ref SPI_SSACT_INT_MASK
+  *                       - \ref SPI_SSINACT_INT_MASK
+  *                       - \ref SPI_SLVUR_INT_MASK
+  *                       - \ref SPI_SLVBE_INT_MASK
+  *                       - \ref SPI_SLVTO_INT_MASK
+  *                       - \ref SPI_TXUF_INT_MASK
+  *                       - \ref SPI_FIFO_TXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXOV_INT_MASK
+  *                       - \ref SPI_FIFO_RXTO_INT_MASK
+  *
+  * @return None
+  * @details Enable SPI related interrupts specified by u32Mask parameter.
+  */
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
+{
+    /* Enable unit transfer interrupt flag */
+    if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
+        spi->CTL |= SPI_CTL_UNITIEN_Msk;
+
+    /* Enable slave selection signal active interrupt flag */
+    if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
+        spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk;
+
+    /* Enable slave selection signal inactive interrupt flag */
+    if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)
+        spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk;
+
+    /* Enable slave TX under run interrupt flag */
+    if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
+        spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk;
+
+    /* Enable slave bit count error interrupt flag */
+    if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
+        spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk;
+
+    /* Enable slave time-out interrupt flag */
+    if((u32Mask & SPI_SLVTO_INT_MASK) == SPI_SLVTO_INT_MASK)
+        spi->SSCTL |= SPI_SSCTL_SLVTOIEN_Msk;
+
+    /* Enable slave TX underflow interrupt flag */
+    if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
+        spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
+
+    /* Enable TX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)
+        spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
+
+    /* Enable RX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)
+        spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
+
+    /* Enable RX overrun interrupt flag */
+    if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
+        spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
+
+    /* Enable RX time-out interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)
+        spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
+}
+
+/**
+  * @brief  Disable interrupt function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt enable bits.
+  *                     Each bit corresponds to a interrupt bit.
+  *                     This parameter decides which interrupts will be disabled. It is combination of:
+  *                       - \ref SPI_UNIT_INT_MASK
+  *                       - \ref SPI_SSACT_INT_MASK
+  *                       - \ref SPI_SSINACT_INT_MASK
+  *                       - \ref SPI_SLVUR_INT_MASK
+  *                       - \ref SPI_SLVBE_INT_MASK
+  *                       - \ref SPI_SLVTO_INT_MASK
+  *                       - \ref SPI_TXUF_INT_MASK
+  *                       - \ref SPI_FIFO_TXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXOV_INT_MASK
+  *                       - \ref SPI_FIFO_RXTO_INT_MASK
+  *
+  * @return None
+  * @details Disable SPI related interrupts specified by u32Mask parameter.
+  */
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
+{
+    /* Disable unit transfer interrupt flag */
+    if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
+        spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
+
+    /* Disable slave selection signal active interrupt flag */
+    if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
+        spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;
+
+    /* Disable slave selection signal inactive interrupt flag */
+    if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)
+        spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;
+
+    /* Disable slave TX under run interrupt flag */
+    if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
+        spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;
+
+    /* Disable slave bit count error interrupt flag */
+    if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
+        spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;
+
+    /* Disable slave time-out interrupt flag */
+    if((u32Mask & SPI_SLVTO_INT_MASK) == SPI_SLVTO_INT_MASK)
+        spi->SSCTL &= ~SPI_SSCTL_SLVTOIEN_Msk;
+
+    /* Disable slave TX underflow interrupt flag */
+    if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
+        spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
+
+    /* Disable TX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)
+        spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
+
+    /* Disable RX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)
+        spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
+
+    /* Disable RX overrun interrupt flag */
+    if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
+        spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
+
+    /* Disable RX time-out interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)
+        spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
+}
+
+/**
+  * @brief  Get interrupt flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt sources.
+  *                     Each bit corresponds to a interrupt source.
+  *                     This parameter decides which interrupt flags will be read. It is combination of:
+  *                       - \ref SPI_UNIT_INT_MASK
+  *                       - \ref SPI_SSACT_INT_MASK
+  *                       - \ref SPI_SSINACT_INT_MASK
+  *                       - \ref SPI_SLVUR_INT_MASK
+  *                       - \ref SPI_SLVBE_INT_MASK
+  *                       - \ref SPI_SLVTO_INT_MASK
+  *                       - \ref SPI_TXUF_INT_MASK
+  *                       - \ref SPI_FIFO_TXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXOV_INT_MASK
+  *                       - \ref SPI_FIFO_RXTO_INT_MASK
+  *
+  * @return Interrupt flags of selected sources.
+  * @details Get SPI related interrupt flags specified by u32Mask parameter.
+  */
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)
+{
+    uint32_t u32IntFlag = 0;
+
+    /* Check unit transfer interrupt flag */
+    if((u32Mask & SPI_UNIT_INT_MASK) && (spi->STATUS & SPI_STATUS_UNITIF_Msk))
+        u32IntFlag |= SPI_UNIT_INT_MASK;
+
+    /* Check slave selection signal active interrupt flag */
+    if((u32Mask & SPI_SSACT_INT_MASK) && (spi->STATUS & SPI_STATUS_SSACTIF_Msk))
+        u32IntFlag |= SPI_SSACT_INT_MASK;
+
+    /* Check slave selection signal inactive interrupt flag */
+    if((u32Mask & SPI_SSINACT_INT_MASK) && (spi->STATUS & SPI_STATUS_SSINAIF_Msk))
+        u32IntFlag |= SPI_SSINACT_INT_MASK;
+
+    /* Check slave TX under run interrupt flag */
+    if((u32Mask & SPI_SLVUR_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVURIF_Msk))
+        u32IntFlag |= SPI_SLVUR_INT_MASK;
+
+    /* Check slave bit count error interrupt flag */
+    if((u32Mask & SPI_SLVBE_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVBEIF_Msk))
+        u32IntFlag |= SPI_SLVBE_INT_MASK;
+
+    /* Check slave time-out interrupt flag */
+    if((u32Mask & SPI_SLVTO_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVTOIF_Msk))
+        u32IntFlag |= SPI_SLVTO_INT_MASK;
+
+    /* Check slave TX underflow interrupt flag */
+    if((u32Mask & SPI_TXUF_INT_MASK) && (spi->STATUS & SPI_STATUS_TXUFIF_Msk))
+        u32IntFlag |= SPI_TXUF_INT_MASK;
+
+    /* Check TX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (spi->STATUS & SPI_STATUS_TXTHIF_Msk))
+        u32IntFlag |= SPI_FIFO_TXTH_INT_MASK;
+
+    /* Check RX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (spi->STATUS & SPI_STATUS_RXTHIF_Msk))
+        u32IntFlag |= SPI_FIFO_RXTH_INT_MASK;
+
+    /* Check RX overrun interrupt flag */
+    if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (spi->STATUS & SPI_STATUS_RXOVIF_Msk))
+        u32IntFlag |= SPI_FIFO_RXOV_INT_MASK;
+
+    /* Check RX time-out interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (spi->STATUS & SPI_STATUS_RXTOIF_Msk))
+        u32IntFlag |= SPI_FIFO_RXTO_INT_MASK;
+
+    return u32IntFlag;
+}
+
+/**
+  * @brief  Clear interrupt flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt sources.
+  *                     Each bit corresponds to a interrupt source.
+  *                     This parameter decides which interrupt flags will be cleared. It could be the combination of:
+  *                       - \ref SPI_UNIT_INT_MASK
+  *                       - \ref SPI_SSACT_INT_MASK
+  *                       - \ref SPI_SSINACT_INT_MASK
+  *                       - \ref SPI_SLVUR_INT_MASK
+  *                       - \ref SPI_SLVBE_INT_MASK
+  *                       - \ref SPI_SLVTO_INT_MASK 
+  *                       - \ref SPI_TXUF_INT_MASK 
+  *                       - \ref SPI_FIFO_RXOV_INT_MASK 
+  *                       - \ref SPI_FIFO_RXTO_INT_MASK
+  *
+  * @return None
+  * @details Clear SPI related interrupt flags specified by u32Mask parameter.
+  */
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)
+{
+    if(u32Mask & SPI_UNIT_INT_MASK)
+        spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
+
+    if(u32Mask & SPI_SSACT_INT_MASK)
+        spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
+
+    if(u32Mask & SPI_SSINACT_INT_MASK)
+        spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
+
+    if(u32Mask & SPI_SLVUR_INT_MASK)
+        spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
+
+    if(u32Mask & SPI_SLVBE_INT_MASK)
+        spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
+
+    if(u32Mask & SPI_SLVTO_INT_MASK)
+        spi->STATUS = SPI_STATUS_SLVTOIF_Msk; /* Clear slave time-out interrupt flag */
+
+    if(u32Mask & SPI_TXUF_INT_MASK)
+        spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
+
+    if(u32Mask & SPI_FIFO_RXOV_INT_MASK)
+        spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
+
+    if(u32Mask & SPI_FIFO_RXTO_INT_MASK)
+        spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
+}
+
+/**
+  * @brief  Get SPI status.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related sources.
+  *                     Each bit corresponds to a source.
+  *                     This parameter decides which flags will be read. It is combination of:
+  *                       - \ref SPI_BUSY_MASK
+  *                       - \ref SPI_RX_EMPTY_MASK
+  *                       - \ref SPI_RX_FULL_MASK
+  *                       - \ref SPI_TX_EMPTY_MASK
+  *                       - \ref SPI_TX_FULL_MASK
+  *                       - \ref SPI_TXRX_RESET_MASK
+  *                       - \ref SPI_SPIEN_STS_MASK
+  *                       - \ref SPI_SSLINE_STS_MASK
+  *
+  * @return Flags of selected sources.
+  * @details Get SPI related status specified by u32Mask parameter.
+  */
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)
+{
+    uint32_t u32Flag = 0;
+
+    /* Check busy status */
+    if((u32Mask & SPI_BUSY_MASK) && (spi->STATUS & SPI_STATUS_BUSY_Msk))
+        u32Flag |= SPI_BUSY_MASK;
+
+    /* Check RX empty flag */
+    if((u32Mask & SPI_RX_EMPTY_MASK) && (spi->STATUS & SPI_STATUS_RXEMPTY_Msk))
+        u32Flag |= SPI_RX_EMPTY_MASK;
+
+    /* Check RX full flag */
+    if((u32Mask & SPI_RX_FULL_MASK) && (spi->STATUS & SPI_STATUS_RXFULL_Msk))
+        u32Flag |= SPI_RX_FULL_MASK;
+
+    /* Check TX empty flag */
+    if((u32Mask & SPI_TX_EMPTY_MASK) && (spi->STATUS & SPI_STATUS_TXEMPTY_Msk))
+        u32Flag |= SPI_TX_EMPTY_MASK;
+
+    /* Check TX full flag */
+    if((u32Mask & SPI_TX_FULL_MASK) && (spi->STATUS & SPI_STATUS_TXFULL_Msk))
+        u32Flag |= SPI_TX_FULL_MASK;
+
+    /* Check TX/RX reset flag */
+    if((u32Mask & SPI_TXRX_RESET_MASK) && (spi->STATUS & SPI_STATUS_TXRXRST_Msk))
+        u32Flag |= SPI_TXRX_RESET_MASK;
+
+    /* Check SPIEN flag */
+    if((u32Mask & SPI_SPIEN_STS_MASK) && (spi->STATUS & SPI_STATUS_SPIENSTS_Msk))
+        u32Flag |= SPI_SPIEN_STS_MASK;
+
+    /* Check SPIn_SS line status */
+    if((u32Mask & SPI_SSLINE_STS_MASK) && (spi->STATUS & SPI_STATUS_SSLINE_Msk))
+        u32Flag |= SPI_SSLINE_STS_MASK;
+
+    return u32Flag;
+}
+
+
+/**
+  * @brief  This function is used to get I2S source clock frequency.
+  * @param[in]  i2s The pointer of the specified I2S module.
+  * @return I2S source clock frequency (Hz).
+  * @details Return the source clock frequency according to the setting of SPI1SEL (CLKSEL2[5:4]) or SPI2SEL (CLKSEL2[7:6]).
+  * @note   Only SPI1 and SPI2 support I2S mode.
+  */
+static uint32_t I2S_GetSourceClockFreq(SPI_T *i2s)
+{
+    uint32_t u32Freq, u32HCLKFreq;
+
+    if(i2s == SPI1)
+    {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
+            u32Freq = __HXT; /* Clock source is HXT */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
+            u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1)
+        {
+            /* Get system clock frequency */
+            u32HCLKFreq = CLK_GetHCLKFreq();
+            /* Clock source is PCLK1 */
+            if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
+                u32Freq = (u32HCLKFreq / 2);
+            else
+                u32Freq = u32HCLKFreq;
+        }
+        else
+            u32Freq = __HIRC; /* Clock source is HIRC */
+    }
+    else
+    {
+        if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
+            u32Freq = __HXT; /* Clock source is HXT */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
+            u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0)
+        {
+            /* Get system clock frequency */
+            u32HCLKFreq = CLK_GetHCLKFreq();
+            /* Clock source is PCLK0 */
+            if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+                u32Freq = (u32HCLKFreq / 2);
+            else
+                u32Freq = u32HCLKFreq;
+        }
+        else
+            u32Freq = __HIRC; /* Clock source is HIRC */
+    }
+
+    return u32Freq;
+}
+
+/**
+  * @brief  This function configures some parameters of I2S interface for general purpose use.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below.
+  *                                     - \ref I2S_MODE_MASTER
+  *                                     - \ref I2S_MODE_SLAVE
+  * @param[in] u32SampleRate Sample rate
+  * @param[in] u32WordWidth Data length. Valid values are listed below.
+  *                                     - \ref I2S_DATABIT_8
+  *                                     - \ref I2S_DATABIT_16
+  *                                     - \ref I2S_DATABIT_24
+  *                                     - \ref I2S_DATABIT_32
+  * @param[in] u32Channels Audio format. Valid values are listed below.
+  *                                     - \ref I2S_MONO
+  *                                     - \ref I2S_STEREO
+  * @param[in] u32DataFormat Data format. Valid values are listed below.
+  *                                     - \ref I2S_FORMAT_I2S
+  *                                     - \ref I2S_FORMAT_MSB
+  *                                     - \ref I2S_FORMAT_PCMA
+  *                                     - \ref I2S_FORMAT_PCMB
+  * @return Real sample rate of master mode or peripheral clock rate of slave mode.
+  * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters.
+  *          Set TX and RX FIFO threshold to middle value. Both the TX and RX functions will be enabled.
+  *          The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference.
+  * @note   Only SPI1 and SPI2 support I2S mode.
+  * @note   In slave mode, the SPI peripheral clock rate will be equal to APB clock rate.
+  */
+uint32_t I2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat)
+{
+    uint32_t u32Divider;
+    uint32_t u32BitRate, u32SrcClk;
+    uint32_t u32HCLKFreq;
+
+    /* Reset SPI/I2S */
+    if(i2s == SPI1)
+    {
+        SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
+    }
+    else
+    {
+        SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
+    }
+
+    /* Configure I2S controller */
+    i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat;
+    /* Set TX and RX FIFO threshold to middle value */
+    i2s->FIFOCTL = I2S_FIFO_TX_LEVEL_WORD_2 | I2S_FIFO_RX_LEVEL_WORD_2;
+
+    if(u32MasterSlave == SPI_MASTER)
+    {
+        /* Get the source clock rate */
+        u32SrcClk = I2S_GetSourceClockFreq(i2s);
+
+        /* Calculate the bit clock rate */
+        u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1) * 16;
+        u32Divider = ((u32SrcClk / u32BitRate) >> 1) - 1;
+        /* Set BCLKDIV setting */
+        i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos);
+
+        /* Calculate bit clock rate */
+        u32BitRate = u32SrcClk / ((u32Divider + 1) * 2);
+        /* Calculate real sample rate */
+        u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1) * 16);
+
+        /* Enable TX function, RX function and I2S mode. */
+        i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+
+        /* Return the real sample rate */
+        return u32SampleRate;
+    }
+    else
+    {
+        /* Set BCLKDIV = 0 */
+        i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk;
+        /* Get system clock frequency */
+        u32HCLKFreq = CLK_GetHCLKFreq();
+
+        if(i2s == SPI1)
+        {
+            /* Set the peripheral clock rate to equal APB clock rate */
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
+            /* Enable TX function, RX function and I2S mode. */
+            i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+            /* Return slave peripheral clock rate */
+            if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
+                return (u32HCLKFreq / 2);
+            else
+                return u32HCLKFreq;
+        }
+        else
+        {
+            /* Set the peripheral clock rate to equal APB clock rate */
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
+            /* Enable TX function, RX function and I2S mode. */
+            i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+            /* Return slave peripheral clock rate */
+            if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+                return (u32HCLKFreq / 2);
+            else
+                return u32HCLKFreq;
+        }
+    }
+}
+
+/**
+  * @brief  Disable I2S function.
+  * @param[in]  i2s The pointer of the specified I2S module.
+  * @return None
+  * @details Disable I2S function.
+  * @note   Only SPI1 and SPI2 support I2S mode.
+  */
+void I2S_Close(SPI_T *i2s)
+{
+    i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
+}
+
+/**
+  * @brief Enable interrupt function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Mask The combination of all related interrupt enable bits.
+  *            Each bit corresponds to a interrupt source. Valid values are listed below.
+  *            - \ref I2S_FIFO_TXTH_INT_MASK
+  *            - \ref I2S_FIFO_RXTH_INT_MASK
+  *            - \ref I2S_FIFO_RXOV_INT_MASK
+  *            - \ref I2S_FIFO_RXTO_INT_MASK
+  *            - \ref I2S_TXUF_INT_MASK
+  *            - \ref I2S_RIGHT_ZC_INT_MASK
+  *            - \ref I2S_LEFT_ZC_INT_MASK
+  * @return None
+  * @details This function enables the interrupt according to the u32Mask parameter.
+  * @note   Only SPI1 and SPI2 support I2S mode.
+  */
+void I2S_EnableInt(SPI_T *i2s, uint32_t u32Mask)
+{
+    /* Enable TX threshold interrupt flag */
+    if((u32Mask & I2S_FIFO_TXTH_INT_MASK) == I2S_FIFO_TXTH_INT_MASK)
+        i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
+
+    /* Enable RX threshold interrupt flag */
+    if((u32Mask & I2S_FIFO_RXTH_INT_MASK) == I2S_FIFO_RXTH_INT_MASK)
+        i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
+
+    /* Enable RX overrun interrupt flag */
+    if((u32Mask & I2S_FIFO_RXOV_INT_MASK) == I2S_FIFO_RXOV_INT_MASK)
+        i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
+
+    /* Enable RX time-out interrupt flag */
+    if((u32Mask & I2S_FIFO_RXTO_INT_MASK) == I2S_FIFO_RXTO_INT_MASK)
+        i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
+
+    /* Enable TX underflow interrupt flag */
+    if((u32Mask & I2S_TXUF_INT_MASK) == I2S_TXUF_INT_MASK)
+        i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
+
+    /* Enable right channel zero cross interrupt flag */
+    if((u32Mask & I2S_RIGHT_ZC_INT_MASK) == I2S_RIGHT_ZC_INT_MASK)
+        i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk;
+
+    /* Enable left channel zero cross interrupt flag */
+    if((u32Mask & I2S_LEFT_ZC_INT_MASK) == I2S_LEFT_ZC_INT_MASK)
+        i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk;
+}
+
+/**
+  * @brief Disable interrupt function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Mask The combination of all related interrupt enable bits.
+  *            Each bit corresponds to a interrupt source. Valid values are listed below.
+  *            - \ref I2S_FIFO_TXTH_INT_MASK
+  *            - \ref I2S_FIFO_RXTH_INT_MASK
+  *            - \ref I2S_FIFO_RXOV_INT_MASK
+  *            - \ref I2S_FIFO_RXTO_INT_MASK
+  *            - \ref I2S_TXUF_INT_MASK
+  *            - \ref I2S_RIGHT_ZC_INT_MASK
+  *            - \ref I2S_LEFT_ZC_INT_MASK
+  * @return None
+  * @details This function disables the interrupt according to the u32Mask parameter.
+  * @note   Only SPI1 and SPI2 support I2S mode.
+  */
+void I2S_DisableInt(SPI_T *i2s, uint32_t u32Mask)
+{
+    /* Disable TX threshold interrupt flag */
+    if((u32Mask & I2S_FIFO_TXTH_INT_MASK) == I2S_FIFO_TXTH_INT_MASK)
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
+
+    /* Disable RX threshold interrupt flag */
+    if((u32Mask & I2S_FIFO_RXTH_INT_MASK) == I2S_FIFO_RXTH_INT_MASK)
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
+
+    /* Disable RX overrun interrupt flag */
+    if((u32Mask & I2S_FIFO_RXOV_INT_MASK) == I2S_FIFO_RXOV_INT_MASK)
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
+
+    /* Disable RX time-out interrupt flag */
+    if((u32Mask & I2S_FIFO_RXTO_INT_MASK) == I2S_FIFO_RXTO_INT_MASK)
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
+
+    /* Disable TX underflow interrupt flag */
+    if((u32Mask & I2S_TXUF_INT_MASK) == I2S_TXUF_INT_MASK)
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
+
+    /* Disable right channel zero cross interrupt flag */
+    if((u32Mask & I2S_RIGHT_ZC_INT_MASK) == I2S_RIGHT_ZC_INT_MASK)
+        i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk;
+
+    /* Disable left channel zero cross interrupt flag */
+    if((u32Mask & I2S_LEFT_ZC_INT_MASK) == I2S_LEFT_ZC_INT_MASK)
+        i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk;
+}
+
+/**
+  * @brief  Enable master clock (MCLK).
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32BusClock The target MCLK clock rate.
+  * @return Actual MCLK clock rate
+  * @details Set the master clock rate according to u32BusClock parameter and enable master clock output.
+  *          The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference.
+  * @note   Only SPI1 and SPI2 support I2S mode.
+  */
+uint32_t I2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock)
+{
+    uint32_t u32Divider;
+    uint32_t u32SrcClk;
+
+    u32SrcClk = I2S_GetSourceClockFreq(i2s);
+    if(u32BusClock == u32SrcClk)
+        u32Divider = 0;
+    else
+    {
+        u32Divider = (u32SrcClk / u32BusClock) >> 1;
+        /* MCLKDIV is a 6-bit width configuration. The maximum value is 0x3F. */
+        if(u32Divider > 0x3F)
+            u32Divider = 0x3F;
+    }
+
+    /* Write u32Divider to MCLKDIV (SPI_I2SCLK[5:0]) */
+    i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos);
+
+    /* Enable MCLK output */
+    i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk;
+
+    if(u32Divider == 0)
+        return u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */
+    else
+        return ((u32SrcClk >> 1) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */
+}
+
+/**
+  * @brief  Disable master clock (MCLK).
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output.
+  * @note   Only SPI1 and SPI2 support I2S mode.
+  */
+void I2S_DisableMCLK(SPI_T *i2s)
+{
+    i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk;
+}
+
+/**
+  * @brief  Configure FIFO threshold setting.
+  * @param[in]  i2s The pointer of the specified I2S module.
+  * @param[in]  u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3.
+  * @param[in]  u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3.
+  * @return None
+  * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+  */
+void I2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+    i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk) |
+                    (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
+                    (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos));
+}
+
+/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SPI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_spi.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_spi.h
new file mode 100644
index 00000000000..02d2469190a
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_spi.h
@@ -0,0 +1,630 @@
+/******************************************************************************
+ * @file     spi.h
+ * @version  V0.10
+ * $Revision: 17 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series SPI driver header file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __SPI_H__
+#define __SPI_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SPI_Driver SPI Driver
+  @{
+*/
+
+/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
+  @{
+*/
+
+#define SPI_MODE_0        (SPI_CTL_TXNEG_Msk)                             /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */
+#define SPI_MODE_1        (SPI_CTL_RXNEG_Msk)                             /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */
+#define SPI_MODE_2        (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)        /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */
+#define SPI_MODE_3        (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)        /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */
+
+#define SPI_SLAVE         (SPI_CTL_SLAVE_Msk)                             /*!< Set as slave */
+#define SPI_MASTER        (0x0)                                           /*!< Set as master */
+
+#define SPI_SS                (SPI_SSCTL_SS_Msk)                          /*!< Set SS */
+#define SPI_SS_ACTIVE_HIGH    (SPI_SSCTL_SSACTPOL_Msk)                    /*!< SS active high */
+#define SPI_SS_ACTIVE_LOW     (0x0)                                       /*!< SS active low */
+
+/* SPI Interrupt Mask */
+#define SPI_UNIT_INT_MASK                (0x001)                          /*!< Unit transfer interrupt mask */
+#define SPI_SSACT_INT_MASK               (0x002)                          /*!< Slave selection signal active interrupt mask */
+#define SPI_SSINACT_INT_MASK             (0x004)                          /*!< Slave selection signal inactive interrupt mask */
+#define SPI_SLVUR_INT_MASK               (0x008)                          /*!< Slave under run interrupt mask */
+#define SPI_SLVBE_INT_MASK               (0x010)                          /*!< Slave bit count error interrupt mask */
+#define SPI_SLVTO_INT_MASK               (0x020)                          /*!< Slave time-out interrupt mask */
+#define SPI_TXUF_INT_MASK                (0x040)                          /*!< Slave TX underflow interrupt mask */
+#define SPI_FIFO_TXTH_INT_MASK           (0x080)                          /*!< FIFO TX threshold interrupt mask */
+#define SPI_FIFO_RXTH_INT_MASK           (0x100)                          /*!< FIFO RX threshold interrupt mask */
+#define SPI_FIFO_RXOV_INT_MASK           (0x200)                          /*!< FIFO RX overrun interrupt mask */
+#define SPI_FIFO_RXTO_INT_MASK           (0x400)                          /*!< FIFO RX time-out interrupt mask */
+
+/* SPI Status Mask */
+#define SPI_BUSY_MASK                    (0x01)                           /*!< Busy status mask */
+#define SPI_RX_EMPTY_MASK                (0x02)                           /*!< RX empty status mask */
+#define SPI_RX_FULL_MASK                 (0x04)                           /*!< RX full status mask */
+#define SPI_TX_EMPTY_MASK                (0x08)                           /*!< TX empty status mask */
+#define SPI_TX_FULL_MASK                 (0x10)                           /*!< TX full status mask */
+#define SPI_TXRX_RESET_MASK              (0x20)                           /*!< TX or RX reset status mask */
+#define SPI_SPIEN_STS_MASK               (0x40)                           /*!< SPIEN status mask */
+#define SPI_SSLINE_STS_MASK              (0x80)                           /*!< SPIn_SS line status mask */
+
+
+/* I2S Data Width */
+#define I2S_DATABIT_8           (0 << SPI_I2SCTL_WDWIDTH_Pos)      /*!< I2S data width is 8-bit */
+#define I2S_DATABIT_16          (1 << SPI_I2SCTL_WDWIDTH_Pos)      /*!< I2S data width is 16-bit */
+#define I2S_DATABIT_24          (2 << SPI_I2SCTL_WDWIDTH_Pos)      /*!< I2S data width is 24-bit */
+#define I2S_DATABIT_32          (3 << SPI_I2SCTL_WDWIDTH_Pos)      /*!< I2S data width is 32-bit */
+
+/* I2S Audio Format */
+#define I2S_MONO                SPI_I2SCTL_MONO_Msk                /*!< Monaural channel */
+#define I2S_STEREO              0                                  /*!< Stereo channel */
+
+/* I2S Data Format */
+#define I2S_FORMAT_I2S          (0<<SPI_I2SCTL_FORMAT_Pos)         /*!< I2S data format */
+#define I2S_FORMAT_MSB          (1<<SPI_I2SCTL_FORMAT_Pos)         /*!< MSB justified data format */
+#define I2S_FORMAT_PCMA         (2<<SPI_I2SCTL_FORMAT_Pos)         /*!< PCM mode A data format */
+#define I2S_FORMAT_PCMB         (3<<SPI_I2SCTL_FORMAT_Pos)         /*!< PCM mode B data format */
+
+/* I2S Operation mode */
+#define I2S_MODE_SLAVE          SPI_I2SCTL_SLAVE_Msk               /*!< As slave mode */
+#define I2S_MODE_MASTER         0                                  /*!< As master mode */
+
+/* I2S TX FIFO Threshold */
+#define I2S_FIFO_TX_LEVEL_WORD_0    0                              /*!< TX threshold is 0 word */
+#define I2S_FIFO_TX_LEVEL_WORD_1    (1 << SPI_FIFOCTL_TXTH_Pos)    /*!< TX threshold is 1 word */
+#define I2S_FIFO_TX_LEVEL_WORD_2    (2 << SPI_FIFOCTL_TXTH_Pos)    /*!< TX threshold is 2 words */
+#define I2S_FIFO_TX_LEVEL_WORD_3    (3 << SPI_FIFOCTL_TXTH_Pos)    /*!< TX threshold is 3 words */
+/* I2S RX FIFO Threshold */
+#define I2S_FIFO_RX_LEVEL_WORD_1    0                              /*!< RX threshold is 1 word */
+#define I2S_FIFO_RX_LEVEL_WORD_2    (1 << SPI_FIFOCTL_RXTH_Pos)    /*!< RX threshold is 2 words */
+#define I2S_FIFO_RX_LEVEL_WORD_3    (2 << SPI_FIFOCTL_RXTH_Pos)    /*!< RX threshold is 3 words */
+#define I2S_FIFO_RX_LEVEL_WORD_4    (3 << SPI_FIFOCTL_RXTH_Pos)    /*!< RX threshold is 4 words */
+
+/* I2S Record Channel */
+#define I2S_MONO_RIGHT          0                                  /*!< Record mono right channel */
+#define I2S_MONO_LEFT           SPI_I2SCTL_RXLCH_Msk               /*!< Record mono left channel */
+
+/* I2S Channel */
+#define I2S_RIGHT               0                                  /*!< Select right channel */
+#define I2S_LEFT                1                                  /*!< Select left channel */
+
+/* I2S Interrupt Mask */
+#define I2S_FIFO_TXTH_INT_MASK           (0x01)                          /*!< TX FIFO threshold interrupt mask */
+#define I2S_FIFO_RXTH_INT_MASK           (0x02)                          /*!< RX FIFO threshold interrupt mask */
+#define I2S_FIFO_RXOV_INT_MASK           (0x04)                          /*!< RX FIFO overrun interrupt mask */
+#define I2S_FIFO_RXTO_INT_MASK           (0x08)                          /*!< RX FIFO time-out interrupt mask */
+#define I2S_TXUF_INT_MASK                (0x10)                          /*!< TX FIFO underflow interrupt mask */
+#define I2S_RIGHT_ZC_INT_MASK            (0x20)                          /*!< Right channel zero cross interrupt mask */
+#define I2S_LEFT_ZC_INT_MASK             (0x40)                          /*!< Left channel zero cross interrupt mask */
+
+/*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear the unit transfer interrupt flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
+  */
+#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi)   ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)
+
+/**
+  * @brief      Disable 2-bit Transfer mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear TWOBIT bit of SPI_CTL register to disable 2-bit Transfer mode.
+  */
+#define SPI_DISABLE_2BIT_MODE(spi)   ((spi)->CTL &= ~SPI_CTL_TWOBIT_Msk)
+
+/**
+  * @brief      Disable Slave 3-wire mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear SLV3WIRE bit of SPI_SSCTL register to disable Slave 3-wire mode.
+  */
+#define SPI_DISABLE_3WIRE_MODE(spi)   ((spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk)
+
+/**
+  * @brief      Disable Dual I/O mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear DUALIOEN bit of SPI_CTL register to disable Dual I/O mode.
+  */
+#define SPI_DISABLE_DUAL_MODE(spi)   ((spi)->CTL &= ~SPI_CTL_DUALIOEN_Msk)
+
+/**
+  * @brief      Disable Quad I/O mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear QUADIOEN bit of SPI_CTL register to disable Quad I/O mode.
+  */
+#define SPI_DISABLE_QUAD_MODE(spi)   ((spi)->CTL &= ~SPI_CTL_QUADIOEN_Msk)
+
+/**
+  * @brief      Enable 2-bit Transfer mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set TWOBIT bit of SPI_CTL register to enable 2-bit Transfer mode.
+  */
+#define SPI_ENABLE_2BIT_MODE(spi)   ((spi)->CTL |= SPI_CTL_TWOBIT_Msk)
+
+/**
+  * @brief      Enable Slave 3-wire mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set SLV3WIRE bit of SPI_SSCTL register to enable Slave 3-wire mode.
+  */
+#define SPI_ENABLE_3WIRE_MODE(spi)   ((spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk)
+
+/**
+  * @brief      Enable Dual input mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear QDIODIR bit and set DUALIOEN bit of SPI_CTL register to enable Dual input mode.
+  */
+#define SPI_ENABLE_DUAL_INPUT_MODE(spi)   ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_QDIODIR_Msk)) | SPI_CTL_DUALIOEN_Msk)
+
+/**
+  * @brief      Enable Dual output mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set QDIODIR bit and DUALIOEN bit of SPI_CTL register to enable Dual output mode.
+  */
+#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi)   ((spi)->CTL |= (SPI_CTL_QDIODIR_Msk | SPI_CTL_DUALIOEN_Msk))
+
+/**
+  * @brief      Enable Quad input mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear QDIODIR bit and set QUADIOEN bit of SPI_CTL register to enable Quad input mode.
+  */
+#define SPI_ENABLE_QUAD_INPUT_MODE(spi)   ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_QDIODIR_Msk)) | SPI_CTL_QUADIOEN_Msk)
+
+/**
+  * @brief      Enable Quad output mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set QDIODIR bit and QUADIOEN bit of SPI_CTL register to enable Quad output mode.
+  */
+#define SPI_ENABLE_QUAD_OUTPUT_MODE(spi)   ((spi)->CTL |= (SPI_CTL_QDIODIR_Msk | SPI_CTL_QUADIOEN_Msk))
+
+/**
+  * @brief      Trigger RX PDMA function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
+  */
+#define SPI_TRIGGER_RX_PDMA(spi)   ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
+
+/**
+  * @brief      Trigger TX PDMA function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
+  */
+#define SPI_TRIGGER_TX_PDMA(spi)   ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
+
+/**
+  * @brief      Disable RX PDMA transfer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
+  */
+#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief      Disable TX PDMA transfer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
+  */
+#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+  * @brief      Get the count of available data in RX FIFO.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     The count of available data in RX FIFO.
+  * @details    Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
+  */
+#define SPI_GET_RX_FIFO_COUNT(spi)   (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
+
+/**
+  * @brief      Get the RX FIFO empty flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @retval     0 RX FIFO is not empty.
+  * @retval     1 RX FIFO is empty.
+  * @details    Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
+  */
+#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi)   (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
+
+/**
+  * @brief      Get the TX FIFO empty flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @retval     0 TX FIFO is not empty.
+  * @retval     1 TX FIFO is empty.
+  * @details    Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
+  */
+#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi)   (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
+
+/**
+  * @brief      Get the TX FIFO full flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @retval     0 TX FIFO is not full.
+  * @retval     1 TX FIFO is full.
+  * @details    Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
+  */
+#define SPI_GET_TX_FIFO_FULL_FLAG(spi)   (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
+
+/**
+  * @brief      Get the datum read from RX register.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     Data in RX register.
+  * @details    Read SPI_RX register to get the received datum.
+  */
+#define SPI_READ_RX(spi)   ((spi)->RX)
+
+/**
+  * @brief      Write datum to TX register.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32TxData The datum which user attempt to transfer through SPI bus.
+  * @return     None.
+  * @details    Write u32TxData to SPI_TX register.
+  */
+#define SPI_WRITE_TX(spi, u32TxData)   ((spi)->TX = (u32TxData))
+
+/**
+  * @brief      Set SPIn_SS pin to high state.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set SPIn_SS pin to high state.
+  */
+#define SPI_SET_SS_HIGH(spi)   ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
+
+/**
+  * @brief      Set SPIn_SS pin to low state.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set SPIn_SS pin to low state.
+  */
+#define SPI_SET_SS_LOW(spi)   ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
+
+/**
+  * @brief      Enable Byte Reorder function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
+  */
+#define SPI_ENABLE_BYTE_REORDER(spi)   ((spi)->CTL |=  SPI_CTL_REORDER_Msk)
+
+/**
+  * @brief      Disable Byte Reorder function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
+  */
+#define SPI_DISABLE_BYTE_REORDER(spi)   ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
+
+/**
+  * @brief      Set the length of suspend interval.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
+  * @return     None.
+  * @details    Set the length of suspend interval according to u32SuspCycle.
+  *             The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
+  */
+#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle)   ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
+
+/**
+  * @brief      Set the SPI transfer sequence with LSB first.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
+  */
+#define SPI_SET_LSB_FIRST(spi)   ((spi)->CTL |= SPI_CTL_LSB_Msk)
+
+/**
+  * @brief      Set the SPI transfer sequence with MSB first.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
+  */
+#define SPI_SET_MSB_FIRST(spi)   ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
+
+/**
+  * @brief      Set the data width of a SPI transaction.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Width The bit width of one transaction.
+  * @return     None.
+  * @details    The data width can be 8 ~ 32 bits.
+  */
+#define SPI_SET_DATA_WIDTH(spi, u32Width)   ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
+
+/**
+  * @brief      Get the SPI busy state.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @retval     0 SPI controller is not busy.
+  * @retval     1 SPI controller is busy.
+  * @details    This macro will return the busy state of SPI controller.
+  */
+#define SPI_IS_BUSY(spi)   ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
+
+/**
+  * @brief      Enable SPI controller.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set SPIEN (SPI_CTL[0]) to enable SPI controller.
+  */
+#define SPI_ENABLE(spi)   ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
+
+/**
+  * @brief      Disable SPI controller.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
+  */
+#define SPI_DISABLE(spi)   ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
+
+
+/**
+  * @brief  Enable zero cross detection function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32ChMask The mask for left or right channel. Valid values are:
+  *                    - \ref I2S_RIGHT
+  *                    - \ref I2S_LEFT
+  * @return None
+  * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
+  */
+static __INLINE void I2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
+{
+    if(u32ChMask == I2S_RIGHT)
+        i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
+    else
+        i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
+}
+
+/**
+  * @brief  Disable zero cross detection function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32ChMask The mask for left or right channel. Valid values are:
+  *                    - \ref I2S_RIGHT
+  *                    - \ref I2S_LEFT
+  * @return None
+  * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
+  */
+static __INLINE void I2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
+{
+    if(u32ChMask == I2S_RIGHT)
+        i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
+    else
+        i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
+}
+
+/**
+  * @brief  Enable I2S TX DMA function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
+  */
+#define I2S_ENABLE_TXDMA(i2s)  ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+  * @brief  Disable I2S TX DMA function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
+  */
+#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+  * @brief  Enable I2S RX DMA function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
+  */
+#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief  Disable I2S RX DMA function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
+  */
+#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief  Enable I2S TX function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
+  */
+#define I2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
+
+/**
+  * @brief  Disable I2S TX function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
+  */
+#define I2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
+
+/**
+  * @brief  Enable I2S RX function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
+  */
+#define I2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
+
+/**
+  * @brief  Disable I2S RX function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
+  */
+#define I2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
+
+/**
+  * @brief  Enable TX Mute function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
+  */
+#define I2S_ENABLE_TX_MUTE(i2s)  ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
+
+/**
+  * @brief  Disable TX Mute function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
+  */
+#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
+
+/**
+  * @brief  Clear TX FIFO.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
+  */
+#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
+
+/**
+  * @brief  Clear RX FIFO.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
+  */
+#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
+
+/**
+  * @brief  This function sets the recording source channel when mono mode is used.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Ch left or right channel. Valid values are:
+  *                - \ref I2S_MONO_LEFT
+  *                - \ref I2S_MONO_RIGHT
+  * @return None
+  * @details This function selects the recording source channel of monaural mode.
+  */
+static __INLINE void I2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
+{
+    u32Ch == I2S_MONO_LEFT ?
+    (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
+    (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
+}
+
+/**
+  * @brief  Write data to I2S TX FIFO.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Data The value written to TX FIFO.
+  * @return None
+  * @details This macro will write a value to TX FIFO.
+  */
+#define I2S_WRITE_TX_FIFO(i2s, u32Data)  ( (i2s)->TX = (u32Data) )
+
+/**
+  * @brief  Read RX FIFO.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return The value read from RX FIFO.
+  * @details This function will return a value read from RX FIFO.
+  */
+#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
+
+/**
+  * @brief  Get the interrupt flag.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Mask The mask value for all interrupt flags.
+  * @return The interrupt flags specified by the u32mask parameter.
+  * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
+  */
+#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
+
+/**
+  * @brief  Clear the interrupt flag.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Mask The mask value for all interrupt flags.
+  * @return None
+  * @details This macro will clear the interrupt flags specified by the u32mask parameter.
+  * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
+  */
+#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
+
+/**
+  * @brief  Get transmit FIFO level
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return TX FIFO level
+  * @details This macro will return the number of available words in TX FIFO.
+  */
+#define I2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos  )
+
+/**
+  * @brief  Get receive FIFO level
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return RX FIFO level
+  * @details This macro will return the number of available words in RX FIFO.
+  */
+#define I2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
+
+
+
+/* Function prototype declaration */
+uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
+void SPI_Close(SPI_T *spi);
+void SPI_ClearRxFIFO(SPI_T *spi);
+void SPI_ClearTxFIFO(SPI_T *spi);
+void SPI_DisableAutoSS(SPI_T *spi);
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
+void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+uint32_t SPI_GetBusClock(SPI_T *spi);
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
+
+uint32_t I2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
+void I2S_Close(SPI_T *i2s);
+void I2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
+void I2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
+uint32_t I2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
+void I2S_DisableMCLK(SPI_T *i2s);
+void I2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+
+
+/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SPI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SPI_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sys.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sys.c
new file mode 100644
index 00000000000..bc127c7e3fd
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sys.c
@@ -0,0 +1,213 @@
+/**************************************************************************//**
+ * @file     sys.c
+ * @version  V3.00
+ * $Revision: 12 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series SYS driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SYS_Driver SYS Driver
+  @{
+*/
+
+
+/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear reset source
+  * @param[in]  u32Src is system reset source. Including :
+  *             - \ref SYS_RSTSTS_CPURF_Msk
+  *             - \ref SYS_RSTSTS_SYSRF_Msk
+  *             - \ref SYS_RSTSTS_BODRF_Msk
+  *             - \ref SYS_RSTSTS_LVRF_Msk
+  *             - \ref SYS_RSTSTS_WDTRF_Msk
+  *             - \ref SYS_RSTSTS_PINRF_Msk
+  *             - \ref SYS_RSTSTS_PORF_Msk
+  * @return     None
+  * @details    This function clear the selected system reset source.
+  */
+void SYS_ClearResetSrc(uint32_t u32Src)
+{
+    SYS->RSTSTS |= u32Src;
+}
+
+/**
+  * @brief      Get Brown-out detector output status
+  * @param      None
+  * @retval     0 System voltage is higher than BOD_VL setting or BOD_EN is 0.
+  * @retval     1 System voltage is lower than BOD_VL setting.
+  * @details    This function get Brown-out detector output status.
+  */
+uint32_t SYS_GetBODStatus(void)
+{
+    return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos);
+}
+
+/**
+  * @brief      Get reset status register value
+  * @param      None
+  * @return     Reset source
+  * @details    This function get the system reset status register value.
+  */
+uint32_t SYS_GetResetSrc(void)
+{
+    return (SYS->RSTSTS);
+}
+
+/**
+  * @brief      Check if register is locked nor not
+  * @param      None
+  * @retval     0 Write-protection function is disabled.
+  *             1 Write-protection function is enabled.
+  * @details    This function check register write-protection bit setting.
+  */
+uint32_t SYS_IsRegLocked(void)
+{
+    return !(SYS->REGLCTL & 0x1);
+}
+
+/**
+  * @brief      Get product ID
+  * @param      None
+  * @return     Product ID
+  * @details    This function get product ID.
+  */
+uint32_t  SYS_ReadPDID(void)
+{
+    return SYS->PDID;
+}
+
+/**
+  * @brief      Reset chip with chip reset
+  * @param      None
+  * @return     None
+  * @details    This function reset chip with chip reset.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_ResetChip(void)
+{
+    SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
+}
+
+/**
+  * @brief      Reset chip with CPU reset
+  * @param      None
+  * @return     None
+  * @details    This function reset CPU with CPU reset.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_ResetCPU(void)
+{
+    SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
+}
+
+/**
+  * @brief      Reset selected module
+  * @param[in]  u32ModuleIndex is module index. Including :
+  *             - \ref PDMA_RST
+  *             - \ref EBI_RST
+  *             - \ref USBH_RST
+  *             - \ref CRC_RST
+  *             - \ref GPIO_RST
+  *             - \ref TMR0_RST
+  *             - \ref TMR1_RST
+  *             - \ref TMR2_RST
+  *             - \ref TMR3_RST
+  *             - \ref ACMP01_RST
+  *             - \ref I2C0_RST
+  *             - \ref I2C1_RST
+  *             - \ref SPI0_RST
+  *             - \ref SPI1_RST
+  *             - \ref SPI2_RST
+  *             - \ref UART0_RST
+  *             - \ref UART1_RST
+  *             - \ref UART2_RST
+  *             - \ref UART3_RST
+  *             - \ref CAN0_RST
+  *             - \ref OTG_RST
+  *             - \ref USBD_RST
+  *             - \ref EADC_RST
+  *             - \ref SC0_RST
+  *             - \ref DAC_RST
+  *             - \ref PWM0_RST
+  *             - \ref PWM1_RST
+  *             - \ref TK_RST
+  * @return     None
+  * @details    This function reset selected module.
+  */
+void SYS_ResetModule(uint32_t u32ModuleIndex)
+{
+    /* Generate reset signal to the corresponding module */
+    *(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24))  |= 1 << (u32ModuleIndex & 0x00ffffff);
+
+    /* Release corresponding module from reset state */
+    *(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24))  &= ~(1 << (u32ModuleIndex & 0x00ffffff));
+}
+
+/**
+  * @brief      Enable and configure Brown-out detector function
+  * @param[in]  i32Mode is reset or interrupt mode. Including :
+  *             - \ref SYS_BODCTL_BOD_RST_EN
+  *             - \ref SYS_BODCTL_BOD_INTERRUPT_EN
+  * @param[in]  u32BODLevel is Brown-out voltage level. Including :
+  *             - \ref SYS_BODCTL_BODVL_4_5V
+  *             - \ref SYS_BODCTL_BODVL_3_7V
+  *             - \ref SYS_BODCTL_BODVL_2_7V
+  *             - \ref SYS_BODCTL_BODVL_2_2V
+  * @return     None
+  * @details    This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
+{
+    /* Enable Brown-out Detector function */
+    SYS->BODCTL |= SYS_BODCTL_BODEN_Msk;
+
+    /* Enable Brown-out interrupt or reset function */
+    SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | i32Mode;
+
+    /* Select Brown-out Detector threshold voltage */
+    SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel;
+}
+
+/**
+  * @brief      Disable Brown-out detector function
+  * @param      None
+  * @return     None
+  * @details    This function disable Brown-out detector function.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_DisableBOD(void)
+{
+    SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
+}
+
+
+
+/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SYS_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sys.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sys.h
new file mode 100644
index 00000000000..28b4a2618e3
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sys.h
@@ -0,0 +1,970 @@
+/**************************************************************************//**
+ * @file     SYS.h
+ * @version  V3.0
+ * $Revision  1 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 Series SYS Header File
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+
+#ifndef __SYS_H__
+#define __SYS_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SYS_Driver SYS Driver
+  @{
+*/
+
+/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants
+  @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Module Reset Control Resister constant definitions.                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_RST    ((0x0<<24) | SYS_IPRST0_PDMARST_Pos )   /*!< Reset PDMA */
+#define EBI_RST     ((0x0<<24) | SYS_IPRST0_EBIRST_Pos )    /*!< Reset EBI */
+#define USBH_RST    ((0x0<<24) | SYS_IPRST0_USBHRST_Pos )   /*!< Reset USBH */
+#define CRC_RST     ((0x0<<24) | SYS_IPRST0_CRCRST_Pos )    /*!< Reset CRC */
+
+#define GPIO_RST    ((0x4<<24) | SYS_IPRST1_GPIORST_Pos )   /*!< Reset GPIO */
+#define TMR0_RST    ((0x4<<24) | SYS_IPRST1_TMR0RST_Pos )   /*!< Reset TMR0 */
+#define TMR1_RST    ((0x4<<24) | SYS_IPRST1_TMR1RST_Pos )   /*!< Reset TMR1 */
+#define TMR2_RST    ((0x4<<24) | SYS_IPRST1_TMR2RST_Pos )   /*!< Reset TMR2 */
+#define TMR3_RST    ((0x4<<24) | SYS_IPRST1_TMR3RST_Pos )   /*!< Reset TMR3 */
+#define ACMP01_RST  ((0x4<<24) | SYS_IPRST1_ACMP01RST_Pos ) /*!< Reset ACMP01 */
+#define I2C0_RST    ((0x4<<24) | SYS_IPRST1_I2C0RST_Pos )   /*!< Reset I2C0 */
+#define I2C1_RST    ((0x4<<24) | SYS_IPRST1_I2C1RST_Pos )   /*!< Reset I2C1 */
+#define SPI0_RST    ((0x4<<24) | SYS_IPRST1_SPI0RST_Pos )   /*!< Reset SPI0 */
+#define SPI1_RST    ((0x4<<24) | SYS_IPRST1_SPI1RST_Pos )   /*!< Reset SPI1 */
+#define SPI2_RST    ((0x4<<24) | SYS_IPRST1_SPI2RST_Pos )   /*!< Reset SPI2 */
+#define UART0_RST   ((0x4<<24) | SYS_IPRST1_UART0RST_Pos )  /*!< Reset UART0 */
+#define UART1_RST   ((0x4<<24) | SYS_IPRST1_UART1RST_Pos )  /*!< Reset UART1 */
+#define UART2_RST   ((0x4<<24) | SYS_IPRST1_UART2RST_Pos )  /*!< Reset UART2 */
+#define UART3_RST   ((0x4<<24) | SYS_IPRST1_UART3RST_Pos )  /*!< Reset UART3 */
+#define CAN0_RST    ((0x4<<24) | SYS_IPRST1_CAN0RST_Pos )   /*!< Reset CAN0 */
+#define OTG_RST     ((0x4<<24) | SYS_IPRST1_OTGRST_Pos )    /*!< Reset OTG */
+#define USBD_RST    ((0x4<<24) | SYS_IPRST1_USBDRST_Pos )   /*!< Reset USBD */
+#define EADC_RST    ((0x4<<24) | SYS_IPRST1_EADCRST_Pos )   /*!< Reset EADC */
+
+#define SC0_RST     ((0x8<<24) | SYS_IPRST2_SC0RST_Pos )    /*!< Reset SC0 */
+#define DAC_RST     ((0x8<<24) | SYS_IPRST2_DACRST_Pos )    /*!< Reset DAC */
+#define PWM0_RST    ((0x8<<24) | SYS_IPRST2_PWM0RST_Pos )   /*!< Reset PWM0 */
+#define PWM1_RST    ((0x8<<24) | SYS_IPRST2_PWM1RST_Pos )   /*!< Reset PWM1 */
+#define TK_RST      ((0x8<<24) | SYS_IPRST2_TKRST_Pos )     /*!< Reset TK */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Brown Out Detector Threshold Voltage Selection constant definitions.                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_BODCTL_BOD_RST_EN           (1UL<<SYS_BODCTL_BODRSTEN_Pos)    /*!< Brown-out Reset Enable */
+#define SYS_BODCTL_BOD_INTERRUPT_EN     (0UL<<SYS_BODCTL_BODRSTEN_Pos)    /*!< Brown-out Interrupt Enable */
+#define SYS_BODCTL_BODVL_4_5V           (3UL<<SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 4.5V */
+#define SYS_BODCTL_BODVL_3_7V           (2UL<<SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 3.7V */
+#define SYS_BODCTL_BODVL_2_7V           (1UL<<SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 2.7V */
+#define SYS_BODCTL_BODVL_2_2V           (0UL<<SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 2.2V */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  VREFCTL constant definitions. (Write-Protection Register)                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_VREFCTL_VREF_2_56V      (0x3UL<<SYS_VREFCTL_VREFCTL_Pos)    /*!< VOUT = 2.56V */
+#define SYS_VREFCTL_VREF_2_048V     (0x7UL<<SYS_VREFCTL_VREFCTL_Pos)    /*!< VOUT = 2.048V */
+#define SYS_VREFCTL_VREF_3_072V     (0xBUL<<SYS_VREFCTL_VREFCTL_Pos)    /*!< VOUT = 3.072V */
+#define SYS_VREFCTL_VREF_4_096V     (0xFUL<<SYS_VREFCTL_VREFCTL_Pos)    /*!< VOUT = 4.096V */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  USBPHY constant definitions. (Write-Protection Register)                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_USBPHY_USBROLE_OTG_V33_EN (0x1UL<<SYS_USBPHY_LDO33EN_Pos)   /*!<  USB LDO33 Enabled  */
+#define SYS_USBPHY_USBROLE_STD_USBD   (0x0UL<<SYS_USBPHY_USBROLE_Pos)   /*!<  Standard USB device */
+#define SYS_USBPHY_USBROLE_STD_USBH   (0x1UL<<SYS_USBPHY_USBROLE_Pos)   /*!<  Standard USB host */
+#define SYS_USBPHY_USBROLE_ID_DEPH    (0x2UL<<SYS_USBPHY_USBROLE_Pos)   /*!<  ID dependent device */
+#define SYS_USBPHY_USBROLE_ON_THE_GO  (0x3UL<<SYS_USBPHY_USBROLE_Pos)   /*!<  On-The-Go device */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Multi-Function constant definitions.                                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+/* How to use below #define?
+Example 1: If user want to set PA.0 as SC0_CLK in initial function,
+           user can issue following command to achieve it.
+
+           SYS->GPA_MFPL  = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK  ;
+
+*/
+//PA0 MFP
+#define SYS_GPA_MFPL_PA0MFP_GPIO               (0ul << SYS_GPA_MFPL_PA0MFP_Pos)        /*!< GPA_MFPL PA0 setting for GPIO*/
+#define SYS_GPA_MFPL_PA0MFP_UART1_nCTS         (1ul << SYS_GPA_MFPL_PA0MFP_Pos)        /*!< GPA_MFPL PA0 setting for UART1_nCTS*/
+#define SYS_GPA_MFPL_PA0MFP_UART1_TXD          (3ul << SYS_GPA_MFPL_PA0MFP_Pos)        /*!< GPA_MFPL PA0 setting for UART1_TXD*/
+#define SYS_GPA_MFPL_PA0MFP_CAN0_RXD           (4ul << SYS_GPA_MFPL_PA0MFP_Pos)        /*!< GPA_MFPL PA0 setting for CAN0_RXD*/
+#define SYS_GPA_MFPL_PA0MFP_SC0_CLK            (5ul << SYS_GPA_MFPL_PA0MFP_Pos)        /*!< GPA_MFPL PA0 setting for SC0_CLK*/
+#define SYS_GPA_MFPL_PA0MFP_PWM1_CH5           (6ul << SYS_GPA_MFPL_PA0MFP_Pos)        /*!< GPA_MFPL PA0 setting for PWM1_CH5*/
+#define SYS_GPA_MFPL_PA0MFP_EBI_AD0            (7ul << SYS_GPA_MFPL_PA0MFP_Pos)        /*!< GPA_MFPL PA0 setting for EBI_AD0*/
+#define SYS_GPA_MFPL_PA0MFP_INT0               (8ul << SYS_GPA_MFPL_PA0MFP_Pos)        /*!< GPA_MFPL PA0 setting for INT0*/
+#define SYS_GPA_MFPL_PA0MFP_SPI1_I2SMCLK       (9ul << SYS_GPA_MFPL_PA0MFP_Pos)        /*!< GPA_MFPL PA0 setting for SPI1_I2SMCLK*/
+
+//PA1 MFP
+#define SYS_GPA_MFPL_PA1MFP_GPIO               (0ul << SYS_GPA_MFPL_PA1MFP_Pos)        /*!< GPA_MFPL PA1 setting for GPIO*/
+#define SYS_GPA_MFPL_PA1MFP_UART1_nRTS         (1ul << SYS_GPA_MFPL_PA1MFP_Pos)        /*!< GPA_MFPL PA1 setting for UART1_nRTS*/
+#define SYS_GPA_MFPL_PA1MFP_UART1_RXD          (3ul << SYS_GPA_MFPL_PA1MFP_Pos)        /*!< GPA_MFPL PA1 setting for UART1_RXD*/
+#define SYS_GPA_MFPL_PA1MFP_CAN0_TXD           (4ul << SYS_GPA_MFPL_PA1MFP_Pos)        /*!< GPA_MFPL PA1 setting for CAN0_TXD*/
+#define SYS_GPA_MFPL_PA1MFP_SC0_DAT            (5ul << SYS_GPA_MFPL_PA1MFP_Pos)        /*!< GPA_MFPL PA1 setting for SC0_DAT*/
+#define SYS_GPA_MFPL_PA1MFP_PWM1_CH4           (6ul << SYS_GPA_MFPL_PA1MFP_Pos)        /*!< GPA_MFPL PA1 setting for PWM1_CH4*/
+#define SYS_GPA_MFPL_PA1MFP_EBI_AD1            (7ul << SYS_GPA_MFPL_PA1MFP_Pos)        /*!< GPA_MFPL PA1 setting for EBI_AD1*/
+#define SYS_GPA_MFPL_PA1MFP_STADC              (10ul << SYS_GPA_MFPL_PA1MFP_Pos)       /*!< GPA_MFPL PA1 setting for STADC*/
+
+//PA2 MFP
+#define SYS_GPA_MFPL_PA2MFP_GPIO               (0ul << SYS_GPA_MFPL_PA2MFP_Pos)        /*!< GPA_MFPL PA2 setting for GPIO*/
+#define SYS_GPA_MFPL_PA2MFP_USB_VBUS_EN        (1ul << SYS_GPA_MFPL_PA2MFP_Pos)        /*!< GPA_MFPL PA2 setting for USB_VBUS_EN*/
+#define SYS_GPA_MFPL_PA2MFP_UART0_TXD          (2ul << SYS_GPA_MFPL_PA2MFP_Pos)        /*!< GPA_MFPL PA2 setting for UART0_TXD*/
+#define SYS_GPA_MFPL_PA2MFP_UART0_nCTS         (3ul << SYS_GPA_MFPL_PA2MFP_Pos)        /*!< GPA_MFPL PA2 setting for UART0_nCTS*/
+#define SYS_GPA_MFPL_PA2MFP_I2C0_SDA           (4ul << SYS_GPA_MFPL_PA2MFP_Pos)        /*!< GPA_MFPL PA2 setting for I2C0_SDA*/
+#define SYS_GPA_MFPL_PA2MFP_SC0_RST            (5ul << SYS_GPA_MFPL_PA2MFP_Pos)        /*!< GPA_MFPL PA2 setting for SC0_RST*/
+#define SYS_GPA_MFPL_PA2MFP_PWM1_CH3           (6ul << SYS_GPA_MFPL_PA2MFP_Pos)        /*!< GPA_MFPL PA2 setting for PWM1_CH3*/
+#define SYS_GPA_MFPL_PA2MFP_EBI_AD2            (7ul << SYS_GPA_MFPL_PA2MFP_Pos)        /*!< GPA_MFPL PA2 setting for EBI_AD2*/
+
+//PA3 MFP
+#define SYS_GPA_MFPL_PA3MFP_GPIO               (0ul << SYS_GPA_MFPL_PA3MFP_Pos)        /*!< GPA_MFPL PA3 setting for GPIO*/
+#define SYS_GPA_MFPL_PA3MFP_USB_VBUS_ST       (1ul << SYS_GPA_MFPL_PA3MFP_Pos)        /*!< GPA_MFPL PA3 setting for USB_VBUS_ST*/
+#define SYS_GPA_MFPL_PA3MFP_UART0_RXD          (2ul << SYS_GPA_MFPL_PA3MFP_Pos)        /*!< GPA_MFPL PA3 setting for UART0_RXD*/
+#define SYS_GPA_MFPL_PA3MFP_UART0_nRTS         (3ul << SYS_GPA_MFPL_PA3MFP_Pos)        /*!< GPA_MFPL PA3 setting for UART0_nRTS*/
+#define SYS_GPA_MFPL_PA3MFP_I2C0_SCL           (4ul << SYS_GPA_MFPL_PA3MFP_Pos)        /*!< GPA_MFPL PA3 setting for I2C0_SCL*/
+#define SYS_GPA_MFPL_PA3MFP_SC0_PWR            (5ul << SYS_GPA_MFPL_PA3MFP_Pos)        /*!< GPA_MFPL PA3 setting for SC0_PWR*/
+#define SYS_GPA_MFPL_PA3MFP_PWM1_CH2           (6ul << SYS_GPA_MFPL_PA3MFP_Pos)        /*!< GPA_MFPL PA3 setting for PWM1_CH2*/
+#define SYS_GPA_MFPL_PA3MFP_EBI_AD3            (7ul << SYS_GPA_MFPL_PA3MFP_Pos)        /*!< GPA_MFPL PA3 setting for EBI_AD3*/
+
+//PA4 MFP
+#define SYS_GPA_MFPL_PA4MFP_GPIO               (0ul << SYS_GPA_MFPL_PA4MFP_Pos)        /*!< GPA_MFPL PA4 setting for GPIO*/
+#define SYS_GPA_MFPL_PA4MFP_SPI1_SS            (2ul << SYS_GPA_MFPL_PA4MFP_Pos)        /*!< GPA_MFPL PA4 setting for SPI1_SS*/
+#define SYS_GPA_MFPL_PA4MFP_EBI_AD4            (7ul << SYS_GPA_MFPL_PA4MFP_Pos)        /*!< GPA_MFPL PA4 setting for EBI_AD4*/
+
+//PA5 MFP
+#define SYS_GPA_MFPL_PA5MFP_GPIO               (0ul << SYS_GPA_MFPL_PA5MFP_Pos)        /*!< GPA_MFPL PA5 setting for GPIO*/
+#define SYS_GPA_MFPL_PA5MFP_SPI1_MOSI          (2ul << SYS_GPA_MFPL_PA5MFP_Pos)        /*!< GPA_MFPL PA5 setting for SPI1_MOSI*/
+#define SYS_GPA_MFPL_PA5MFP_T2_EXT             (3ul << SYS_GPA_MFPL_PA5MFP_Pos)        /*!< GPA_MFPL PA5 setting for T2_EXT*/
+#define SYS_GPA_MFPL_PA5MFP_EBI_AD5            (7ul << SYS_GPA_MFPL_PA5MFP_Pos)        /*!< GPA_MFPL PA5 setting for EBI_AD5*/
+
+//PA6 MFP
+#define SYS_GPA_MFPL_PA6MFP_GPIO               (0ul << SYS_GPA_MFPL_PA6MFP_Pos)        /*!< GPA_MFPL PA6 setting for GPIO*/
+#define SYS_GPA_MFPL_PA6MFP_SPI1_MISO          (2ul << SYS_GPA_MFPL_PA6MFP_Pos)        /*!< GPA_MFPL PA6 setting for SPI1_MISO*/
+#define SYS_GPA_MFPL_PA6MFP_T1_EXT             (3ul << SYS_GPA_MFPL_PA6MFP_Pos)        /*!< GPA_MFPL PA6 setting for T1_EXT*/
+#define SYS_GPA_MFPL_PA6MFP_EBI_AD6            (7ul << SYS_GPA_MFPL_PA6MFP_Pos)        /*!< GPA_MFPL PA6 setting for EBI_AD6*/
+
+//PA7 MFP
+#define SYS_GPA_MFPL_PA7MFP_GPIO               (0ul << SYS_GPA_MFPL_PA7MFP_Pos)        /*!< GPA_MFPL PA7 setting for GPIO*/
+#define SYS_GPA_MFPL_PA7MFP_SPI1_CLK           (2ul << SYS_GPA_MFPL_PA7MFP_Pos)        /*!< GPA_MFPL PA7 setting for SPI1_CLK*/
+#define SYS_GPA_MFPL_PA7MFP_T0_EXT             (3ul << SYS_GPA_MFPL_PA7MFP_Pos)        /*!< GPA_MFPL PA7 setting for T0_EXT*/
+#define SYS_GPA_MFPL_PA7MFP_EBI_AD7            (7ul << SYS_GPA_MFPL_PA7MFP_Pos)        /*!< GPA_MFPL PA7 setting for EBI_AD7*/
+
+//PA8 MFP
+#define SYS_GPA_MFPH_PA8MFP_GPIO               (0ul << SYS_GPA_MFPH_PA8MFP_Pos)        /*!< GPA_MFPH PA8 setting for GPIO*/
+#define SYS_GPA_MFPH_PA8MFP_UART3_TXD          (3ul << SYS_GPA_MFPH_PA8MFP_Pos)        /*!< GPA_MFPH PA8 setting for UART3_TXD*/
+
+//PA9 MFP
+#define SYS_GPA_MFPH_PA9MFP_GPIO               (0ul << SYS_GPA_MFPH_PA9MFP_Pos)        /*!< GPA_MFPH PA9 setting for GPIO*/
+#define SYS_GPA_MFPH_PA9MFP_UART3_RXD          (3ul << SYS_GPA_MFPH_PA9MFP_Pos)        /*!< GPA_MFPH PA9 setting for UART3_RXD*/
+
+//PA10 MFP
+#define SYS_GPA_MFPH_PA10MFP_GPIO              (0ul << SYS_GPA_MFPH_PA10MFP_Pos)        /*!< GPA_MFPH PA10 setting for GPIO*/
+#define SYS_GPA_MFPH_PA10MFP_UART3_nCTS        (3ul << SYS_GPA_MFPH_PA10MFP_Pos)        /*!< GPA_MFPH PA10 setting for UART3_nCTS*/
+
+//PA11 MFP
+#define SYS_GPA_MFPH_PA11MFP_GPIO              (0ul << SYS_GPA_MFPH_PA11MFP_Pos)        /*!< GPA_MFPH PA11 setting for GPIO*/
+#define SYS_GPA_MFPH_PA11MFP_UART3_nRTS        (3ul << SYS_GPA_MFPH_PA11MFP_Pos)        /*!< GPA_MFPH PA11 setting for UART3_nRTS*/
+
+//PA12 MFP
+#define SYS_GPA_MFPH_PA12MFP_GPIO              (0ul << SYS_GPA_MFPH_PA12MFP_Pos)        /*!< GPA_MFPH PA12 setting for GPIO*/
+#define SYS_GPA_MFPH_PA12MFP_SPI1_I2SMCLK      (2ul << SYS_GPA_MFPH_PA12MFP_Pos)        /*!< GPA_MFPH PA12 setting for SPI1_I2SMCLK*/
+#define SYS_GPA_MFPH_PA12MFP_CAN0_TXD          (4ul << SYS_GPA_MFPH_PA12MFP_Pos)        /*!< GPA_MFPH PA12 setting for CAN0_TXD*/
+
+//PA13 MFP
+#define SYS_GPA_MFPH_PA13MFP_GPIO              (0ul << SYS_GPA_MFPH_PA13MFP_Pos)        /*!< GPA_MFPH PA13 setting for GPIO*/
+#define SYS_GPA_MFPH_PA13MFP_CAN0_RXD          (4ul << SYS_GPA_MFPH_PA13MFP_Pos)        /*!< GPA_MFPH PA13 setting for CAN0_RXD*/
+
+//PA14 MFP
+#define SYS_GPA_MFPH_PA14MFP_GPIO              (0ul << SYS_GPA_MFPH_PA14MFP_Pos)        /*!< GPA_MFPH PA14 setting for GPIO*/
+#define SYS_GPA_MFPH_PA14MFP_UART2_nCTS        (3ul << SYS_GPA_MFPH_PA14MFP_Pos)        /*!< GPA_MFPH PA14 setting for UART2_nCTS*/
+#define SYS_GPA_MFPH_PA14MFP_I2C0_SMBAL        (4ul << SYS_GPA_MFPH_PA14MFP_Pos)        /*!< GPA_MFPH PA14 setting for I2C0_SMBAL*/
+
+//PA15 MFP
+#define SYS_GPA_MFPH_PA15MFP_GPIO              (0ul << SYS_GPA_MFPH_PA15MFP_Pos)        /*!< GPA_MFPH PA15 setting for GPIO*/
+#define SYS_GPA_MFPH_PA15MFP_UART2_nRTS        (3ul << SYS_GPA_MFPH_PA15MFP_Pos)        /*!< GPA_MFPH PA15 setting for UART2_nRTS*/
+#define SYS_GPA_MFPH_PA15MFP_I2C0_SMBSUS       (4ul << SYS_GPA_MFPH_PA15MFP_Pos)        /*!< GPA_MFPH PA15 setting for I2C0_SMBSUS*/
+
+//PB0 MFP
+#define SYS_GPB_MFPL_PB0MFP_GPIO               (0ul << SYS_GPB_MFPL_PB0MFP_Pos)        /*!< GPB_MFPL PB0 setting for GPIO*/
+#define SYS_GPB_MFPL_PB0MFP_EADC_CH0           (1ul << SYS_GPB_MFPL_PB0MFP_Pos)        /*!< GPB_MFPL PB0 setting for EADC_CH0*/
+#define SYS_GPB_MFPL_PB0MFP_SPI0_MOSI1         (2ul << SYS_GPB_MFPL_PB0MFP_Pos)        /*!< GPB_MFPL PB0 setting for SPI0_MOSI1*/
+#define SYS_GPB_MFPL_PB0MFP_UART2_RXD          (3ul << SYS_GPB_MFPL_PB0MFP_Pos)        /*!< GPB_MFPL PB0 setting for UART2_RXD*/
+#define SYS_GPB_MFPL_PB0MFP_T2                 (4ul << SYS_GPB_MFPL_PB0MFP_Pos)        /*!< GPB_MFPL PB0 setting for T2*/
+#define SYS_GPB_MFPL_PB0MFP_DAC                (5ul << SYS_GPB_MFPL_PB0MFP_Pos)        /*!< GPB_MFPL PB0 setting for DAC*/
+#define SYS_GPB_MFPL_PB0MFP_EBI_nWRL           (7ul << SYS_GPB_MFPL_PB0MFP_Pos)        /*!< GPB_MFPL PB0 setting for EBI_nWRL*/
+#define SYS_GPB_MFPL_PB0MFP_INT1               (8ul << SYS_GPB_MFPL_PB0MFP_Pos)        /*!< GPB_MFPL PB0 setting for INT1*/
+
+//PB1 MFP
+#define SYS_GPB_MFPL_PB1MFP_GPIO               (0ul << SYS_GPB_MFPL_PB1MFP_Pos)        /*!< GPB_MFPL PB1 setting for GPIO*/
+#define SYS_GPB_MFPL_PB1MFP_EADC_CH1           (1ul << SYS_GPB_MFPL_PB1MFP_Pos)        /*!< GPB_MFPL PB1 setting for EADC_CH1*/
+#define SYS_GPB_MFPL_PB1MFP_SPI0_MISO1         (2ul << SYS_GPB_MFPL_PB1MFP_Pos)        /*!< GPB_MFPL PB1 setting for SPI0_MISO1*/
+#define SYS_GPB_MFPL_PB1MFP_UART2_TXD          (3ul << SYS_GPB_MFPL_PB1MFP_Pos)        /*!< GPB_MFPL PB1 setting for UART2_TXD*/
+#define SYS_GPB_MFPL_PB1MFP_T3                 (4ul << SYS_GPB_MFPL_PB1MFP_Pos)        /*!< GPB_MFPL PB1 setting for T3*/
+#define SYS_GPB_MFPL_PB1MFP_SC0_RST            (5ul << SYS_GPB_MFPL_PB1MFP_Pos)        /*!< GPB_MFPL PB1 setting for SC0_RST*/
+#define SYS_GPB_MFPL_PB1MFP_PWM0_SYNC_OUT      (6ul << SYS_GPB_MFPL_PB1MFP_Pos)        /*!< GPB_MFPL PB1 setting for PWM0_SYNC_OUT*/
+#define SYS_GPB_MFPL_PB1MFP_EBI_nWRH           (7ul << SYS_GPB_MFPL_PB1MFP_Pos)        /*!< GPB_MFPL PB1 setting for EBI_nWRH*/
+
+//PB2 MFP
+#define SYS_GPB_MFPL_PB2MFP_GPIO               (0ul << SYS_GPB_MFPL_PB2MFP_Pos)        /*!< GPB_MFPL PB2 setting for GPIO*/
+#define SYS_GPB_MFPL_PB2MFP_EADC_CH2           (1ul << SYS_GPB_MFPL_PB2MFP_Pos)        /*!< GPB_MFPL PB2 setting for EADC_CH2*/
+#define SYS_GPB_MFPL_PB2MFP_SPI0_CLK           (2ul << SYS_GPB_MFPL_PB2MFP_Pos)        /*!< GPB_MFPL PB2 setting for SPI0_CLK*/
+#define SYS_GPB_MFPL_PB2MFP_SPI1_CLK           (3ul << SYS_GPB_MFPL_PB2MFP_Pos)        /*!< GPB_MFPL PB2 setting for SPI1_CLK*/
+#define SYS_GPB_MFPL_PB2MFP_UART1_RXD          (4ul << SYS_GPB_MFPL_PB2MFP_Pos)        /*!< GPB_MFPL PB2 setting for UART1_RXD*/
+#define SYS_GPB_MFPL_PB2MFP_SC0_CD             (5ul << SYS_GPB_MFPL_PB2MFP_Pos)        /*!< GPB_MFPL PB2 setting for SC0_CD*/
+#define SYS_GPB_MFPL_PB2MFP_UART3_RXD          (9ul << SYS_GPB_MFPL_PB2MFP_Pos)        /*!< GPB_MFPL PB2 setting for UART3_RXD*/
+#define SYS_GPB_MFPL_PB2MFP_T2_EXT             (11ul << SYS_GPB_MFPL_PB2MFP_Pos)       /*!< GPB_MFPL PB2 setting for T2_EXT*/
+
+//PB3
+#define SYS_GPB_MFPL_PB3MFP_GPIO               (0ul << SYS_GPB_MFPL_PB3MFP_Pos)        /*!< GPB_MFPL PB3 setting for GPIO*/
+#define SYS_GPB_MFPL_PB3MFP_EADC_CH3           (1ul << SYS_GPB_MFPL_PB3MFP_Pos)        /*!< GPB_MFPL PB3 setting for EADC_CH3*/
+#define SYS_GPB_MFPL_PB3MFP_SPI0_MISO0         (2ul << SYS_GPB_MFPL_PB3MFP_Pos)        /*!< GPB_MFPL PB3 setting for SPI0_MISO0*/
+#define SYS_GPB_MFPL_PB3MFP_SPI1_MISO          (3ul << SYS_GPB_MFPL_PB3MFP_Pos)        /*!< GPB_MFPL PB3 setting for SPI1_MISO*/
+#define SYS_GPB_MFPL_PB3MFP_UART1_TXD          (4ul << SYS_GPB_MFPL_PB3MFP_Pos)        /*!< GPB_MFPL PB3 setting for UART1_TXD*/
+#define SYS_GPB_MFPL_PB3MFP_UART3_TXD          (9ul << SYS_GPB_MFPL_PB3MFP_Pos)        /*!< GPB_MFPL PB3 setting for UART3_TXD*/
+#define SYS_GPB_MFPL_PB3MFP_T0_EXT             (11ul << SYS_GPB_MFPL_PB3MFP_Pos)       /*!< GPB_MFPL PB3 setting for T0_EXT*/
+
+//PB4
+#define SYS_GPB_MFPL_PB4MFP_GPIO               (0ul << SYS_GPB_MFPL_PB4MFP_Pos)        /*!< GPB_MFPL PB4 setting for GPIO*/
+#define SYS_GPB_MFPL_PB4MFP_EADC_CH4           (1ul << SYS_GPB_MFPL_PB4MFP_Pos)        /*!< GPB_MFPL PB4 setting for EADC_CH4*/
+#define SYS_GPB_MFPL_PB4MFP_SPI0_SS            (2ul << SYS_GPB_MFPL_PB4MFP_Pos)        /*!< GPB_MFPL PB4 setting for SPI0_SS*/
+#define SYS_GPB_MFPL_PB4MFP_SPI1_SS            (3ul << SYS_GPB_MFPL_PB4MFP_Pos)        /*!< GPB_MFPL PB4 setting for SPI1_SS*/
+#define SYS_GPB_MFPL_PB4MFP_UART1_nCTS         (4ul << SYS_GPB_MFPL_PB4MFP_Pos)        /*!< GPB_MFPL PB4 setting for UART1_nCTS*/
+#define SYS_GPB_MFPL_PB4MFP_ACMP0_N            (5ul << SYS_GPB_MFPL_PB4MFP_Pos)        /*!< GPB_MFPL PB4 setting for ACMP0_N*/
+#define SYS_GPB_MFPL_PB4MFP_EBI_AD7            (7ul << SYS_GPB_MFPL_PB4MFP_Pos)        /*!< GPB_MFPL PB4 setting for EBI_AD7*/
+#define SYS_GPB_MFPL_PB4MFP_UART2_TXD          (9ul << SYS_GPB_MFPL_PB4MFP_Pos)        /*!< GPB_MFPL PB4 setting for UART2_TXD*/
+#define SYS_GPB_MFPL_PB4MFP_T1_EXT             (11ul << SYS_GPB_MFPL_PB4MFP_Pos)       /*!< GPB_MFPL PB4 setting for T1_EXT*/
+
+//PB5
+#define SYS_GPB_MFPL_PB5MFP_GPIO               (0ul << SYS_GPB_MFPL_PB5MFP_Pos)        /*!< GPB_MFPL PB5 setting for GPIO*/
+#define SYS_GPB_MFPL_PB5MFP_EADC_CH13          (1ul << SYS_GPB_MFPL_PB5MFP_Pos)        /*!< GPB_MFPL PB5 setting for EADC_CH13*/
+#define SYS_GPB_MFPL_PB5MFP_SPI0_MOSI0         (2ul << SYS_GPB_MFPL_PB5MFP_Pos)        /*!< GPB_MFPL PB5 setting for SPI0_MOSI0*/
+#define SYS_GPB_MFPL_PB5MFP_SPI1_MOSI          (3ul << SYS_GPB_MFPL_PB5MFP_Pos)        /*!< GPB_MFPL PB5 setting for SPI1_MOSI*/
+#define SYS_GPB_MFPL_PB5MFP_TK3                (4ul << SYS_GPB_MFPL_PB5MFP_Pos)        /*!< GPB_MFPL PB5 setting for TK3*/
+#define SYS_GPB_MFPL_PB5MFP_ACMP0_P2           (5ul << SYS_GPB_MFPL_PB5MFP_Pos)        /*!< GPB_MFPL PB5 setting for ACMP0_P2*/
+#define SYS_GPB_MFPL_PB5MFP_EBI_AD6            (7ul << SYS_GPB_MFPL_PB5MFP_Pos)        /*!< GPB_MFPL PB5 setting for EBI_AD6*/
+#define SYS_GPB_MFPL_PB5MFP_UART2_RXD          (9ul << SYS_GPB_MFPL_PB5MFP_Pos)        /*!< GPB_MFPL PB5 setting for UART2_RXD*/
+
+//PB6
+#define SYS_GPB_MFPL_PB6MFP_GPIO               (0ul << SYS_GPB_MFPL_PB6MFP_Pos)        /*!< GPB_MFPL PB6 setting for GPIO*/
+#define SYS_GPB_MFPL_PB6MFP_EADC_CH14          (1ul << SYS_GPB_MFPL_PB6MFP_Pos)        /*!< GPB_MFPL PB6 setting for EADC_CH14*/
+#define SYS_GPB_MFPL_PB6MFP_SPI0_MISO0         (2ul << SYS_GPB_MFPL_PB6MFP_Pos)        /*!< GPB_MFPL PB6 setting for SPI0_MISO0*/
+#define SYS_GPB_MFPL_PB6MFP_SPI1_MISO          (3ul << SYS_GPB_MFPL_PB6MFP_Pos)        /*!< GPB_MFPL PB6 setting for SPI1_MISO*/
+#define SYS_GPB_MFPL_PB6MFP_TK4                (4ul << SYS_GPB_MFPL_PB6MFP_Pos)        /*!< GPB_MFPL PB6 setting for TK4*/
+#define SYS_GPB_MFPL_PB6MFP_ACMP0_P1           (5ul << SYS_GPB_MFPL_PB6MFP_Pos)        /*!< GPB_MFPL PB6 setting for ACMP0_P1*/
+#define SYS_GPB_MFPL_PB6MFP_EBI_AD5            (7ul << SYS_GPB_MFPL_PB6MFP_Pos)        /*!< GPB_MFPL PB6 setting for EBI_AD5*/
+
+//PB7
+#define SYS_GPB_MFPL_PB7MFP_GPIO               (0ul << SYS_GPB_MFPL_PB7MFP_Pos)        /*!< GPB_MFPL PB7 setting for GPIO*/
+#define SYS_GPB_MFPL_PB7MFP_EADC_CH15          (1ul << SYS_GPB_MFPL_PB7MFP_Pos)        /*!< GPB_MFPL PB7 setting for EADC_CH15*/
+#define SYS_GPB_MFPL_PB7MFP_SPI0_CLK           (2ul << SYS_GPB_MFPL_PB7MFP_Pos)        /*!< GPB_MFPL PB7 setting for SPI0_CLK*/
+#define SYS_GPB_MFPL_PB7MFP_SPI1_CLK           (3ul << SYS_GPB_MFPL_PB7MFP_Pos)        /*!< GPB_MFPL PB7 setting for SPI1_CLK*/
+#define SYS_GPB_MFPL_PB7MFP_TK5                (4ul << SYS_GPB_MFPL_PB7MFP_Pos)        /*!< GPB_MFPL PB7 setting for TK5*/
+#define SYS_GPB_MFPL_PB7MFP_ACMP0_P0           (5ul << SYS_GPB_MFPL_PB7MFP_Pos)        /*!< GPB_MFPL PB7 setting for ACMP0_P0*/
+#define SYS_GPB_MFPL_PB7MFP_EBI_AD4            (7ul << SYS_GPB_MFPL_PB7MFP_Pos)        /*!< GPB_MFPL PB7 setting for EBI_AD4*/
+#define SYS_GPB_MFPL_PB7MFP_STADC              (10ul << SYS_GPB_MFPL_PB7MFP_Pos)       /*!< GPB_MFPL PB7 setting for STADC*/
+
+//PB8
+#define SYS_GPB_MFPH_PB8MFP_GPIO               (0ul << SYS_GPB_MFPH_PB8MFP_Pos)        /*!< GPB_MFPH PB8 setting for GPIO*/
+#define SYS_GPB_MFPH_PB8MFP_EADC_CH5           (1ul << SYS_GPB_MFPH_PB8MFP_Pos)        /*!< GPB_MFPH PB8 setting for EADC_CH5*/
+#define SYS_GPB_MFPH_PB8MFP_UART1_nRTS         (4ul << SYS_GPB_MFPH_PB8MFP_Pos)        /*!< GPB_MFPH PB8 setting for UART1_nRTS*/
+#define SYS_GPB_MFPH_PB8MFP_PWM0_CH2           (6ul << SYS_GPB_MFPH_PB8MFP_Pos)        /*!< GPB_MFPH PB8 setting for PWM0_CH2*/
+
+//PB9
+#define SYS_GPB_MFPH_PB9MFP_GPIO               (0ul << SYS_GPB_MFPH_PB9MFP_Pos)        /*!< GPB_MFPH PB9 setting for GPIO*/
+#define SYS_GPB_MFPH_PB9MFP_EADC_CH6           (1ul << SYS_GPB_MFPH_PB9MFP_Pos)        /*!< GPB_MFPH PB9 setting for EADC_CH6*/
+
+//PB10
+#define SYS_GPB_MFPH_PB10MFP_GPIO              (0ul << SYS_GPB_MFPH_PB10MFP_Pos)        /*!< GPB_MFPH_ PB10 setting for GPIO*/
+#define SYS_GPB_MFPH_PB10MFP_EADC_CH7          (1ul << SYS_GPB_MFPH_PB10MFP_Pos)        /*!< GPB_MFPH_ PB10 setting for EADC_CH7*/
+
+//PB11
+#define SYS_GPB_MFPH_PB11MFP_GPIO              (0ul << SYS_GPB_MFPH_PB11MFP_Pos)        /*!< GPB_MFPH_ PB11 setting for GPIO*/
+#define SYS_GPB_MFPH_PB11MFP_EADC_CH8          (1ul << SYS_GPB_MFPH_PB11MFP_Pos)        /*!< GPB_MFPH_ PB11 setting for EADC_CH8*/
+#define SYS_GPB_MFPH_PB11MFP_TK0               (4ul << SYS_GPB_MFPH_PB11MFP_Pos)        /*!< GPB_MFPH_ PB11 setting for TK0*/
+
+//PB12
+#define SYS_GPB_MFPH_PB12MFP_GPIO              (0ul << SYS_GPB_MFPH_PB12MFP_Pos)        /*!< GPB_MFPH_ PB12 setting for GPIO*/
+#define SYS_GPB_MFPH_PB12MFP_EADC_CH9          (1ul << SYS_GPB_MFPH_PB12MFP_Pos)        /*!< GPB_MFPH_ PB12 setting for EADC_CH9*/
+#define SYS_GPB_MFPH_PB12MFP_TK1               (4ul << SYS_GPB_MFPH_PB12MFP_Pos)        /*!< GPB_MFPH_ PB12 setting for TK1*/
+
+//PB13
+#define SYS_GPB_MFPH_PB13MFP_GPIO              (0ul << SYS_GPB_MFPH_PB13MFP_Pos)        /*!< GPB_MFPH PB13 setting for GPIO*/
+#define SYS_GPB_MFPH_PB13MFP_EADC_CH10         (1ul << SYS_GPB_MFPH_PB13MFP_Pos)        /*!< GPB_MFPH PB13 setting for EADC_CH10*/
+
+//PB14
+#define SYS_GPB_MFPH_PB14MFP_GPIO              (0ul << SYS_GPB_MFPH_PB14MFP_Pos)        /*!< GPB_MFPH PB14 setting for GPIO*/
+#define SYS_GPB_MFPH_PB14MFP_EADC_CH11         (1ul << SYS_GPB_MFPH_PB14MFP_Pos)        /*!< GPB_MFPH PB14 setting for EADC_CH11*/
+
+//PB15
+#define SYS_GPB_MFPH_PB15MFP_GPIO              (0ul << SYS_GPB_MFPH_PB15MFP_Pos)        /*!< GPB_MFPH PB15 setting for GPIO*/
+#define SYS_GPB_MFPH_PB15MFP_EADC_CH12         (1ul << SYS_GPB_MFPH_PB15MFP_Pos)        /*!< GPB_MFPH PB15 setting for EADC_CH12*/
+#define SYS_GPB_MFPH_PB15MFP_TK2               (4ul << SYS_GPB_MFPH_PB15MFP_Pos)        /*!< GPB_MFPH PB15 setting for TK2*/
+#define SYS_GPB_MFPH_PB15MFP_ACMP0_P3          (5ul << SYS_GPB_MFPH_PB15MFP_Pos)        /*!< GPB_MFPH PB15 setting for ACMP0_P3*/
+#define SYS_GPB_MFPH_PB15MFP_EBI_nCS1          (7ul << SYS_GPB_MFPH_PB15MFP_Pos)        /*!< GPB_MFPH PB15 setting for EBI_nCS1*/
+
+//PC0
+#define SYS_GPC_MFPL_PC0MFP_GPIO               (0ul << SYS_GPC_MFPL_PC0MFP_Pos)        /*!< GPC_MFPL PC0 setting for GPIO*/
+#define SYS_GPC_MFPL_PC0MFP_SPI2_CLK           (2ul << SYS_GPC_MFPL_PC0MFP_Pos)        /*!< GPC_MFPL PC0 setting for SPI2_CLK*/
+#define SYS_GPC_MFPL_PC0MFP_UART2_nCTS         (3ul << SYS_GPC_MFPL_PC0MFP_Pos)        /*!< GPC_MFPL PC0 setting for UART2_nCTS*/
+#define SYS_GPC_MFPL_PC0MFP_CAN0_TXD           (4ul << SYS_GPC_MFPL_PC0MFP_Pos)        /*!< GPC_MFPL PC0 setting for CAN0_TXD*/
+#define SYS_GPC_MFPL_PC0MFP_PWM0_CH0           (6ul << SYS_GPC_MFPL_PC0MFP_Pos)        /*!< GPC_MFPL PC0 setting for PWM0_CH0*/
+#define SYS_GPC_MFPL_PC0MFP_EBI_AD8            (7ul << SYS_GPC_MFPL_PC0MFP_Pos)        /*!< GPC_MFPL PC0 setting for EBI_AD8*/
+#define SYS_GPC_MFPL_PC0MFP_INT2               (8ul << SYS_GPC_MFPL_PC0MFP_Pos)        /*!< GPC_MFPL PC0 setting for INT2*/
+#define SYS_GPC_MFPL_PC0MFP_UART3_TXD          (9ul << SYS_GPC_MFPL_PC0MFP_Pos)        /*!< GPC_MFPL PC0 setting for UART3_TXD*/
+#define SYS_GPC_MFPL_PC0MFP_T3_EXT             (11ul << SYS_GPC_MFPL_PC0MFP_Pos)       /*!< GPC_MFPL PC0 setting for T3_EXT*/
+
+//PC1
+#define SYS_GPC_MFPL_PC1MFP_GPIO               (0ul << SYS_GPC_MFPL_PC1MFP_Pos)        /*!< GPC_MFPL PC1 setting for GPIO*/
+#define SYS_GPC_MFPL_PC1MFP_CLKO               (1ul << SYS_GPC_MFPL_PC1MFP_Pos)        /*!< GPC_MFPL PC1 setting for CLKO*/
+#define SYS_GPC_MFPL_PC1MFP_STDAC              (2ul << SYS_GPC_MFPL_PC1MFP_Pos)        /*!< GPC_MFPL PC1 setting for STDAC*/
+#define SYS_GPC_MFPL_PC1MFP_UART2_nRTS         (3ul << SYS_GPC_MFPL_PC1MFP_Pos)        /*!< GPC_MFPL PC1 setting for UART2_nRTS*/
+#define SYS_GPC_MFPL_PC1MFP_CAN0_RXD           (4ul << SYS_GPC_MFPL_PC1MFP_Pos)        /*!< GPC_MFPL PC1 setting for CAN0_RXD*/
+#define SYS_GPC_MFPL_PC1MFP_PWM0_CH1           (6ul << SYS_GPC_MFPL_PC1MFP_Pos)        /*!< GPC_MFPL PC1 setting for PWM0_CH1*/
+#define SYS_GPC_MFPL_PC1MFP_EBI_AD9            (7ul << SYS_GPC_MFPL_PC1MFP_Pos)        /*!< GPC_MFPL PC1 setting for EBI_AD9*/
+#define SYS_GPC_MFPL_PC1MFP_UART3_RXD          (9ul << SYS_GPC_MFPL_PC1MFP_Pos)        /*!< GPC_MFPL PC1 setting for UART3_RXD*/
+
+//PC2
+#define SYS_GPC_MFPL_PC2MFP_GPIO               (0ul << SYS_GPC_MFPL_PC2MFP_Pos)        /*!< GPC_MFPL PC2 setting for GPIO*/
+#define SYS_GPC_MFPL_PC2MFP_SPI2_SS            (2ul << SYS_GPC_MFPL_PC2MFP_Pos)        /*!< GPC_MFPL PC2 setting for SPI2_SS*/
+#define SYS_GPC_MFPL_PC2MFP_UART2_TXD          (3ul << SYS_GPC_MFPL_PC2MFP_Pos)        /*!< GPC_MFPL PC2 setting for UART2_TXD*/
+#define SYS_GPC_MFPL_PC2MFP_ACMP1_O            (5ul << SYS_GPC_MFPL_PC2MFP_Pos)        /*!< GPC_MFPL PC2 setting for ACMP1_O*/
+#define SYS_GPC_MFPL_PC2MFP_PWM0_CH2           (6ul << SYS_GPC_MFPL_PC2MFP_Pos)        /*!< GPC_MFPL PC2 setting for PWM0_CH2*/
+#define SYS_GPC_MFPL_PC2MFP_EBI_AD10           (7ul << SYS_GPC_MFPL_PC2MFP_Pos)        /*!< GPC_MFPL PC2 setting for EBI_AD10*/
+
+//PC3
+#define SYS_GPC_MFPL_PC3MFP_GPIO               (0ul << SYS_GPC_MFPL_PC3MFP_Pos)        /*!< GPC_MFPL PC3 setting for GPIO*/
+#define SYS_GPC_MFPL_PC3MFP_SPI2_MOSI          (2ul << SYS_GPC_MFPL_PC3MFP_Pos)        /*!< GPC_MFPL PC3 setting for SPI2_MOSI*/
+#define SYS_GPC_MFPL_PC3MFP_UART2_RXD          (3ul << SYS_GPC_MFPL_PC3MFP_Pos)        /*!< GPC_MFPL PC3 setting for UART2_RXD*/
+#define SYS_GPC_MFPL_PC3MFP_USB_VBUS_ST        (4ul << SYS_GPC_MFPL_PC3MFP_Pos)        /*!< GPC_MFPL PC3 setting for USB_VBUS_ST*/
+#define SYS_GPC_MFPL_PC3MFP_PWM0_CH3           (6ul << SYS_GPC_MFPL_PC3MFP_Pos)        /*!< GPC_MFPL PC3 setting for PWM0_CH3*/
+#define SYS_GPC_MFPL_PC3MFP_EBI_AD11           (7ul << SYS_GPC_MFPL_PC3MFP_Pos)        /*!< GPC_MFPL PC3 setting for EBI_AD11*/
+
+//PC4
+#define SYS_GPC_MFPL_PC4MFP_GPIO               (0ul << SYS_GPC_MFPL_PC4MFP_Pos)        /*!< GPC_MFPL PC4 setting for GPIO*/
+#define SYS_GPC_MFPL_PC4MFP_SPI2_MISO          (2ul << SYS_GPC_MFPL_PC4MFP_Pos)        /*!< GPC_MFPL PC4 setting for SPI2_MISO*/
+#define SYS_GPC_MFPL_PC4MFP_I2C1_SCL           (3ul << SYS_GPC_MFPL_PC4MFP_Pos)        /*!< GPC_MFPL PC4 setting for I2C1_SCL*/
+#define SYS_GPC_MFPL_PC4MFP_USB_VBUS_EN        (4ul << SYS_GPC_MFPL_PC4MFP_Pos)        /*!< GPC_MFPL PC4 setting for USB_VBUS_EN*/
+#define SYS_GPC_MFPL_PC4MFP_PWM0_CH4           (6ul << SYS_GPC_MFPL_PC4MFP_Pos)        /*!< GPC_MFPL PC4 setting for PWM0_CH4*/
+#define SYS_GPC_MFPL_PC4MFP_EBI_AD12           (7ul << SYS_GPC_MFPL_PC4MFP_Pos)        /*!< GPC_MFPL PC4 setting for EBI_AD12*/
+
+//PC5
+#define SYS_GPC_MFPL_PC5MFP_GPIO               (0ul << SYS_GPC_MFPL_PC5MFP_Pos)        /*!< GPC_MFPL PC5 setting for GPIO*/
+#define SYS_GPC_MFPL_PC5MFP_SPI2_I2SMCLK       (2ul << SYS_GPC_MFPL_PC5MFP_Pos)        /*!< GPC_MFPL PC5 setting for SPI2_I2SMCLK*/
+#define SYS_GPC_MFPL_PC5MFP_PWM0_CH5           (6ul << SYS_GPC_MFPL_PC5MFP_Pos)        /*!< GPC_MFPL PC5 setting for PWM0_CH5*/
+#define SYS_GPC_MFPL_PC5MFP_EBI_AD13           (7ul << SYS_GPC_MFPL_PC5MFP_Pos)        /*!< GPC_MFPL PC5 setting for EBI_AD13*/
+
+//PC6
+#define SYS_GPC_MFPL_PC6MFP_GPIO               (0ul << SYS_GPC_MFPL_PC6MFP_Pos)        /*!< GPC_MFPL PC6 setting for GPIO*/
+#define SYS_GPC_MFPL_PC6MFP_I2C1_SMBAL         (3ul << SYS_GPC_MFPL_PC6MFP_Pos)        /*!< GPC_MFPL PC6 setting for I2C1_SMBAL*/
+#define SYS_GPC_MFPL_PC6MFP_ACMP1_O            (5ul << SYS_GPC_MFPL_PC6MFP_Pos)        /*!< GPC_MFPL PC6 setting for ACMP1_O*/
+#define SYS_GPC_MFPL_PC6MFP_PWM1_CH0           (6ul << SYS_GPC_MFPL_PC6MFP_Pos)        /*!< GPC_MFPL PC6 setting for PWM1_CH0*/
+#define SYS_GPC_MFPL_PC6MFP_EBI_AD14           (7ul << SYS_GPC_MFPL_PC6MFP_Pos)        /*!< GPC_MFPL PC6 setting for EBI_AD14*/
+#define SYS_GPC_MFPL_PC6MFP_UART0_TXD          (9ul << SYS_GPC_MFPL_PC6MFP_Pos)        /*!< GPC_MFPL PC6 setting for UART0_TXD*/
+
+//PC7
+#define SYS_GPC_MFPL_PC7MFP_GPIO               (0ul << SYS_GPC_MFPL_PC7MFP_Pos)        /*!< GPC_MFPL PC7 setting for GPIO*/
+#define SYS_GPC_MFPL_PC7MFP_I2C1_SMBSUS        (3ul << SYS_GPC_MFPL_PC7MFP_Pos)        /*!< GPC_MFPL PC7 setting for I2C1_SMBSUS*/
+#define SYS_GPC_MFPL_PC7MFP_PWM1_CH1           (6ul << SYS_GPC_MFPL_PC7MFP_Pos)        /*!< GPC_MFPL PC7 setting for PWM1_CH1*/
+#define SYS_GPC_MFPL_PC7MFP_EBI_AD15           (7ul << SYS_GPC_MFPL_PC7MFP_Pos)        /*!< GPC_MFPL PC7 setting for EBI_AD15*/
+#define SYS_GPC_MFPL_PC7MFP_UART0_RXD          (9ul << SYS_GPC_MFPL_PC7MFP_Pos)        /*!< GPC_MFPL PC7 setting for UART0_RXD*/
+
+//PC8
+#define SYS_GPC_MFPH_PC8MFP_GPIO               (0ul << SYS_GPC_MFPH_PC8MFP_Pos)        /*!< GPC_MFPH_ PC8 setting for GPIO*/
+#define SYS_GPC_MFPH_PC8MFP_TK7                (4ul << SYS_GPC_MFPH_PC8MFP_Pos)        /*!< GPC_MFPH_ PC8 setting for TK7*/
+
+//PC9
+#define SYS_GPC_MFPH_PC9MFP_GPIO               (0ul << SYS_GPC_MFPH_PC9MFP_Pos)        /*!< GPC_MFPH PC9 setting for GPIO*/
+#define SYS_GPC_MFPH_PC9MFP_SPI2_I2SMCLK       (2ul << SYS_GPC_MFPH_PC9MFP_Pos)        /*!< GPC_MFPH PC9 setting for SPI2_I2SMCLK*/
+#define SYS_GPC_MFPH_PC9MFP_PWM1_CH0           (6ul << SYS_GPC_MFPH_PC9MFP_Pos)        /*!< GPC_MFPH PC9 setting for PWM1_CH0*/
+
+//PC10
+#define SYS_GPC_MFPH_PC10MFP_GPIO              (0ul << SYS_GPC_MFPH_PC10MFP_Pos)        /*!< GPC_MFPH PC10 setting for GPIO*/
+#define SYS_GPC_MFPH_PC10MFP_SPI2_MOSI         (2ul << SYS_GPC_MFPH_PC10MFP_Pos)        /*!< GPC_MFPH PC10 setting for SPI2_MOSI*/
+#define SYS_GPC_MFPH_PC10MFP_PWM1_CH1          (6ul << SYS_GPC_MFPH_PC10MFP_Pos)        /*!< GPC_MFPH PC10 setting for PWM1_CH1*/
+
+//PC11
+#define SYS_GPC_MFPH_PC11MFP_GPIO              (0ul << SYS_GPC_MFPH_PC11MFP_Pos)        /*!< GPC_MFPH PC11 setting for GPIO*/
+#define SYS_GPC_MFPH_PC11MFP_SPI2_MISO         (2ul << SYS_GPC_MFPH_PC11MFP_Pos)        /*!< GPC_MFPH PC11 setting for SPI2_MISO*/
+#define SYS_GPC_MFPH_PC11MFP_PWM1_CH2          (6ul << SYS_GPC_MFPH_PC11MFP_Pos)        /*!< GPC_MFPH PC11 setting for PWM1_CH2*/
+
+//PC12
+#define SYS_GPC_MFPH_PC12MFP_GPIO              (0ul << SYS_GPC_MFPH_PC12MFP_Pos)        /*!< GPC_MFPH PC12 setting for GPIO*/
+#define SYS_GPC_MFPH_PC12MFP_SPI2_CLK          (2ul << SYS_GPC_MFPH_PC12MFP_Pos)        /*!< GPC_MFPH PC12 setting for SPI2_CLK*/
+#define SYS_GPC_MFPH_PC12MFP_PWM1_CH3          (6ul << SYS_GPC_MFPH_PC12MFP_Pos)        /*!< GPC_MFPH PC12 setting for PWM1_CH3*/
+
+//PC13
+#define SYS_GPC_MFPH_PC13MFP_GPIO              (0ul << SYS_GPC_MFPH_PC13MFP_Pos)        /*!< GPC_MFPH PC13 setting for GPIO*/
+#define SYS_GPC_MFPH_PC13MFP_SPI2_SS           (2ul << SYS_GPC_MFPH_PC13MFP_Pos)        /*!< GPC_MFPH PC13 setting for SPI2_SS*/
+#define SYS_GPC_MFPH_PC13MFP_PWM1_CH4          (6ul << SYS_GPC_MFPH_PC13MFP_Pos)        /*!< GPC_MFPH PC13 setting for PWM1_CH4*/
+
+//PC14
+#define SYS_GPC_MFPH_PC14MFP_GPIO              (0ul << SYS_GPC_MFPH_PC14MFP_Pos)        /*!< GPC_MFPH PC14 setting for GPIO*/
+#define SYS_GPC_MFPH_PC14MFP_PWM1_CH5          (6ul << SYS_GPC_MFPH_PC14MFP_Pos)        /*!< GPC_MFPH PC14 setting for PWM1_CH5*/
+
+//PC15
+#define SYS_GPC_MFPH_PC15MFP_GPIO              (0ul << SYS_GPC_MFPH_PC15MFP_Pos)        /*!< GPC_MFPH PC15 setting for GPIO*/
+#define SYS_GPC_MFPH_PC15MFP_PWM1_CH0          (6ul << SYS_GPC_MFPH_PC15MFP_Pos)        /*!< GPC_MFPH PC15 setting for PWM1_CH0*/
+
+//PD0
+#define SYS_GPD_MFPL_PD0MFP_GPIO            (0ul << SYS_GPD_MFPL_PD0MFP_Pos)        /*!< GPD_MFPL PD0 setting for GPIO*/
+#define SYS_GPD_MFPL_PD0MFP_EADC_CH6        (1ul << SYS_GPD_MFPL_PD0MFP_Pos)        /*!< GPD_MFPL PD0 setting for EADC_CH6*/
+#define SYS_GPD_MFPL_PD0MFP_SPI1_I2SMCLK    (2ul << SYS_GPD_MFPL_PD0MFP_Pos)        /*!< GPD_MFPL PD0 setting for SPI1_I2SMCLK*/
+#define SYS_GPD_MFPL_PD0MFP_UART0_RXD       (3ul << SYS_GPD_MFPL_PD0MFP_Pos)        /*!< GPD_MFPL PD0 setting for UART0_RXD*/
+#define SYS_GPD_MFPL_PD0MFP_TK6             (4ul << SYS_GPD_MFPL_PD0MFP_Pos)        /*!< GPD_MFPL PD0 setting for TK6*/
+#define SYS_GPD_MFPL_PD0MFP_ACMP1_N         (5ul << SYS_GPD_MFPL_PD0MFP_Pos)        /*!< GPD_MFPL PD0 setting for ACMP1_N*/
+#define SYS_GPD_MFPL_PD0MFP_INT3            (8ul << SYS_GPD_MFPL_PD0MFP_Pos)        /*!< GPD_MFPL PD0 setting for INT3*/
+#define SYS_GPD_MFPL_PD0MFP_T3              (11ul << SYS_GPD_MFPL_PD0MFP_Pos)       /*!< GPD_MFPL PD0 setting for T3*/
+
+//PD1
+#define SYS_GPD_MFPL_PD1MFP_GPIO            (0ul << SYS_GPD_MFPL_PD1MFP_Pos)        /*!< GPD_MFPL PD1 setting for GPIO*/
+#define SYS_GPD_MFPL_PD1MFP_EADC_CH11       (1ul << SYS_GPD_MFPL_PD1MFP_Pos)        /*!< GPD_MFPL PD1 setting for EADC_CH11*/
+#define SYS_GPD_MFPL_PD1MFP_PWM0_SYNC_IN    (2ul << SYS_GPD_MFPL_PD1MFP_Pos)        /*!< GPD_MFPL PD1 setting for PWM0_SYNC_IN*/
+#define SYS_GPD_MFPL_PD1MFP_UART0_TXD       (3ul << SYS_GPD_MFPL_PD1MFP_Pos)        /*!< GPD_MFPL PD1 setting for UART0_TXD*/
+#define SYS_GPD_MFPL_PD1MFP_TK10            (4ul << SYS_GPD_MFPL_PD1MFP_Pos)        /*!< GPD_MFPL PD1 setting for TK10*/
+#define SYS_GPD_MFPL_PD1MFP_ACMP1_P2        (5ul << SYS_GPD_MFPL_PD1MFP_Pos)        /*!< GPD_MFPL PD1 setting for ACMP1_P2*/
+#define SYS_GPD_MFPL_PD1MFP_T0              (6ul << SYS_GPD_MFPL_PD1MFP_Pos)        /*!< GPD_MFPL PD1 setting for T0*/
+#define SYS_GPD_MFPL_PD1MFP_EBI_nRD         (7ul << SYS_GPD_MFPL_PD1MFP_Pos)        /*!< GPD_MFPL PD1 setting for EBI_nRD*/
+
+//PD2
+#define SYS_GPD_MFPL_PD2MFP_GPIO            (0ul << SYS_GPD_MFPL_PD2MFP_Pos)        /*!< GPD_MFPL PD2 setting for GPIO*/
+#define SYS_GPD_MFPL_PD2MFP_STADC           (1ul << SYS_GPD_MFPL_PD2MFP_Pos)        /*!< GPD_MFPL PD2 setting for STADC*/
+#define SYS_GPD_MFPL_PD2MFP_T0_EXT          (3ul << SYS_GPD_MFPL_PD2MFP_Pos)        /*!< GPD_MFPL PD2 setting for T0_EXT*/
+#define SYS_GPD_MFPL_PD2MFP_TK11            (4ul << SYS_GPD_MFPL_PD2MFP_Pos)        /*!< GPD_MFPL PD2 setting for TK11*/
+#define SYS_GPD_MFPL_PD2MFP_ACMP1_P1        (5ul << SYS_GPD_MFPL_PD2MFP_Pos)        /*!< GPD_MFPL PD2 setting for ACMP1_P1*/
+#define SYS_GPD_MFPL_PD2MFP_PWM0_BRAKE0     (6ul << SYS_GPD_MFPL_PD2MFP_Pos)        /*!< GPD_MFPL PD2 setting for PWM0_BRAKE0*/
+#define SYS_GPD_MFPL_PD2MFP_EBI_nWR         (7ul << SYS_GPD_MFPL_PD2MFP_Pos)        /*!< GPD_MFPL PD2 setting for EBI_nWR*/
+#define SYS_GPD_MFPL_PD2MFP_INT0            (8ul << SYS_GPD_MFPL_PD2MFP_Pos)        /*!< GPD_MFPL PD2 setting for INT0*/
+
+//PD3
+#define SYS_GPD_MFPL_PD3MFP_GPIO            (0ul << SYS_GPD_MFPL_PD3MFP_Pos)        /*!< GPD_MFPL PD3 setting for GPIO*/
+#define SYS_GPD_MFPL_PD3MFP_T2              (1ul << SYS_GPD_MFPL_PD3MFP_Pos)        /*!< GPD_MFPL PD3 setting for T2*/
+#define SYS_GPD_MFPL_PD3MFP_T1_EXT          (3ul << SYS_GPD_MFPL_PD3MFP_Pos)        /*!< GPD_MFPL PD3 setting for T1_EXT*/
+#define SYS_GPD_MFPL_PD3MFP_TK12            (4ul << SYS_GPD_MFPL_PD3MFP_Pos)        /*!< GPD_MFPL PD3 setting for TK12*/
+#define SYS_GPD_MFPL_PD3MFP_ACMP1_P0        (5ul << SYS_GPD_MFPL_PD3MFP_Pos)        /*!< GPD_MFPL PD3 setting for ACMP1_P0*/
+#define SYS_GPD_MFPL_PD3MFP_PWM0_BRAKE1     (6ul << SYS_GPD_MFPL_PD3MFP_Pos)        /*!< GPD_MFPL PD3 setting for PWM0_BRAKE1*/
+#define SYS_GPD_MFPL_PD3MFP_EBI_MCLK        (7ul << SYS_GPD_MFPL_PD3MFP_Pos)        /*!< GPD_MFPL PD3 setting for EBI_MCLK*/
+#define SYS_GPD_MFPL_PD3MFP_INT1            (8ul << SYS_GPD_MFPL_PD3MFP_Pos)        /*!< GPD_MFPL PD3 setting for INT1*/
+
+//PD4
+#define SYS_GPD_MFPL_PD4MFP_GPIO            (0ul << SYS_GPD_MFPL_PD4MFP_Pos)        /*!< GPD_MFPL PD4 setting for GPIO*/
+#define SYS_GPD_MFPL_PD4MFP_SPI1_CLK        (2ul << SYS_GPD_MFPL_PD4MFP_Pos)        /*!< GPD_MFPL PD4 setting for SPI1_CLK*/
+#define SYS_GPD_MFPL_PD4MFP_I2C0_SDA        (3ul << SYS_GPD_MFPL_PD4MFP_Pos)        /*!< GPD_MFPL PD4 setting for I2C0_SDA*/
+#define SYS_GPD_MFPL_PD4MFP_TK13            (4ul << SYS_GPD_MFPL_PD4MFP_Pos)        /*!< GPD_MFPL PD4 setting for TK13*/
+#define SYS_GPD_MFPL_PD4MFP_PWM0_BRAKE0     (5ul << SYS_GPD_MFPL_PD4MFP_Pos)        /*!< GPD_MFPL PD4 setting for PWM0_BRAKE0*/
+#define SYS_GPD_MFPL_PD4MFP_T0              (6ul << SYS_GPD_MFPL_PD4MFP_Pos)        /*!< GPD_MFPL PD4 setting for T0*/
+
+//PD5
+#define SYS_GPD_MFPL_PD5MFP_GPIO            (0ul << SYS_GPD_MFPL_PD5MFP_Pos)        /*!< GPD_MFPL PD5 setting for GPIO*/
+#define SYS_GPD_MFPL_PD5MFP_CLKO            (1ul << SYS_GPD_MFPL_PD5MFP_Pos)        /*!< GPD_MFPL PD5 setting for CLKO*/
+#define SYS_GPD_MFPL_PD5MFP_SPI1_MISO       (2ul << SYS_GPD_MFPL_PD5MFP_Pos)        /*!< GPD_MFPL PD5 setting for SPI1_MISO*/
+#define SYS_GPD_MFPL_PD5MFP_I2C0_SCL        (3ul << SYS_GPD_MFPL_PD5MFP_Pos)        /*!< GPD_MFPL PD5 setting for I2C0_SCL*/
+#define SYS_GPD_MFPL_PD5MFP_TK14            (4ul << SYS_GPD_MFPL_PD5MFP_Pos)        /*!< GPD_MFPL PD5 setting for TK14*/
+#define SYS_GPD_MFPL_PD5MFP_PWM0_BRAKE1     (5ul << SYS_GPD_MFPL_PD5MFP_Pos)        /*!< GPD_MFPL PD5 setting for PWM0_BRAKE1*/
+#define SYS_GPD_MFPL_PD5MFP_T1              (6ul << SYS_GPD_MFPL_PD5MFP_Pos)        /*!< GPD_MFPL PD5 setting for T1*/
+
+//PD6
+#define SYS_GPD_MFPL_PD6MFP_GPIO            (0ul << SYS_GPD_MFPL_PD6MFP_Pos)        /*!< GPD_MFPL PD6 setting for GPIO*/
+#define SYS_GPD_MFPL_PD6MFP_CLKO            (1ul << SYS_GPD_MFPL_PD6MFP_Pos)        /*!< GPD_MFPL PD6 setting for CLKO*/
+#define SYS_GPD_MFPL_PD6MFP_SPI1_SS         (2ul << SYS_GPD_MFPL_PD6MFP_Pos)        /*!< GPD_MFPL PD6 setting for SPI1_SS*/
+#define SYS_GPD_MFPL_PD6MFP_UART0_RXD       (3ul << SYS_GPD_MFPL_PD6MFP_Pos)        /*!< GPD_MFPL PD6 setting for UART0_RXD*/
+#define SYS_GPD_MFPL_PD6MFP_TK16            (4ul << SYS_GPD_MFPL_PD6MFP_Pos)        /*!< GPD_MFPL PD6 setting for TK16*/
+#define SYS_GPD_MFPL_PD6MFP_ACMP0_O         (5ul << SYS_GPD_MFPL_PD6MFP_Pos)        /*!< GPD_MFPL PD6 setting for ACMP0_O*/
+#define SYS_GPD_MFPL_PD6MFP_PWM0_CH5        (6ul << SYS_GPD_MFPL_PD6MFP_Pos)        /*!< GPD_MFPL PD6 setting for PWM0_CH5*/
+#define SYS_GPD_MFPL_PD6MFP_EBI_nWR         (7ul << SYS_GPD_MFPL_PD6MFP_Pos)        /*!< GPD_MFPL PD6 setting for EBI_nWR*/
+
+//PD7
+#define SYS_GPD_MFPL_PD7MFP_GPIO           (0ul << SYS_GPD_MFPL_PD7MFP_Pos)        /*!< GPD_MFPL PD7 setting for GPIO*/
+#define SYS_GPD_MFPL_PD7MFP_PWM0_SYNC_IN   (3ul << SYS_GPD_MFPL_PD7MFP_Pos)        /*!< GPD_MFPL PD7 setting for PWM0_SYNC_IN*/
+#define SYS_GPD_MFPL_PD7MFP_T1             (4ul << SYS_GPD_MFPL_PD7MFP_Pos)        /*!< GPD_MFPL PD7 setting for T1*/
+#define SYS_GPD_MFPL_PD7MFP_ACMP0_O        (5ul << SYS_GPD_MFPL_PD7MFP_Pos)        /*!< GPD_MFPL PD7 setting for ACMP0_O*/
+#define SYS_GPD_MFPL_PD7MFP_PWM0_CH5       (6ul << SYS_GPD_MFPL_PD7MFP_Pos)        /*!< GPD_MFPL PD7 setting for PWM0_CH5*/
+#define SYS_GPD_MFPL_PD7MFP_EBI_nRD        (7ul << SYS_GPD_MFPL_PD7MFP_Pos)        /*!< GPD_MFPL PD7 setting for EBI_nRD*/
+
+//PD8
+#define SYS_GPD_MFPH_PD8MFP_GPIO               (0ul << SYS_GPD_MFPH_PD8MFP_Pos)        /*!< GPD_MFPH PD8 setting for GPIO*/
+#define SYS_GPD_MFPH_PD8MFP_EADC_CH7           (1ul << SYS_GPD_MFPH_PD8MFP_Pos)        /*!< GPD_MFPH PD8 setting for EADC_CH7*/
+#define SYS_GPD_MFPH_PD8MFP_TK8                (4ul << SYS_GPD_MFPH_PD8MFP_Pos)        /*!< GPD_MFPH PD8 setting for TK8*/
+#define SYS_GPD_MFPH_PD8MFP_EBI_nCS0           (7ul << SYS_GPD_MFPH_PD8MFP_Pos)        /*!< GPD_MFPH PD8 setting for EBI_nCS0*/
+
+//PD9
+#define SYS_GPD_MFPH_PD9MFP_GPIO               (0ul << SYS_GPD_MFPH_PD9MFP_Pos)        /*!< GPD_MFPH PD9 setting for GPIO*/
+#define SYS_GPD_MFPH_PD9MFP_EADC_CH10          (1ul << SYS_GPD_MFPH_PD9MFP_Pos)        /*!< GPD_MFPH PD9 setting for EADC_CH10*/
+#define SYS_GPD_MFPH_PD9MFP_TK9                (4ul << SYS_GPD_MFPH_PD9MFP_Pos)        /*!< GPD_MFPH PD9 setting for TK9*/
+#define SYS_GPD_MFPH_PD9MFP_ACMP1_P3           (5ul << SYS_GPD_MFPH_PD9MFP_Pos)        /*!< GPD_MFPH PD9 setting for ACMP1_P3*/
+#define SYS_GPD_MFPH_PD9MFP_EBI_ALE            (7ul << SYS_GPD_MFPH_PD9MFP_Pos)        /*!< GPD_MFPH PD9 setting for EBI_ALE*/
+
+//PD10
+#define SYS_GPD_MFPH_PD10MFP_GPIO              (0ul << SYS_GPD_MFPH_PD10MFP_Pos)        /*!< GPD_MFPH PD10 setting for GPIO*/
+#define SYS_GPD_MFPH_PD10MFP_T2                (4ul << SYS_GPD_MFPH_PD10MFP_Pos)        /*!< GPD_MFPH PD10 setting for T2*/
+
+//PD11
+#define SYS_GPD_MFPH_PD11MFP_GPIO              (0ul << SYS_GPD_MFPH_PD11MFP_Pos)        /*!< GPD_MFPH PD11 setting for GPIO*/
+#define SYS_GPD_MFPH_PD11MFP_T3                (4ul << SYS_GPD_MFPH_PD11MFP_Pos)        /*!< GPD_MFPH PD11 setting for T3*/
+
+//PD12
+#define SYS_GPD_MFPH_PD12MFP_GPIO              (0ul << SYS_GPD_MFPH_PD12MFP_Pos)        /*!< GPD_MFPH PD12 setting for GPIO*/
+#define SYS_GPD_MFPH_PD12MFP_SPI2_SS           (2ul << SYS_GPD_MFPH_PD12MFP_Pos)        /*!< GPD_MFPH PD12 setting for SPI2_SS*/
+#define SYS_GPD_MFPH_PD12MFP_UART3_TXD         (3ul << SYS_GPD_MFPH_PD12MFP_Pos)        /*!< GPD_MFPH PD12 setting for UART3_TXD*/
+#define SYS_GPD_MFPH_PD12MFP_PWM1_CH0          (6ul << SYS_GPD_MFPH_PD12MFP_Pos)        /*!< GPD_MFPH PD12 setting for PWM1_CH0*/
+#define SYS_GPD_MFPH_PD12MFP_EBI_ADR16         (7ul << SYS_GPD_MFPH_PD12MFP_Pos)        /*!< GPD_MFPH PD12 setting for EBI_ADR16*/
+
+//PD13
+#define SYS_GPD_MFPH_PD13MFP_GPIO              (0ul << SYS_GPD_MFPH_PD13MFP_Pos)        /*!< GPD_MFPH PD13 setting for GPIO*/
+#define SYS_GPD_MFPH_PD13MFP_SPI2_MOSI         (2ul << SYS_GPD_MFPH_PD13MFP_Pos)        /*!< GPD_MFPH PD13 setting for SPI2_MOSI*/
+#define SYS_GPD_MFPH_PD13MFP_UART3_RXD         (3ul << SYS_GPD_MFPH_PD13MFP_Pos)        /*!< GPD_MFPH PD13 setting for UART3_RXD*/
+#define SYS_GPD_MFPH_PD13MFP_PWM1_CH1          (6ul << SYS_GPD_MFPH_PD13MFP_Pos)        /*!< GPD_MFPH PD13 setting for PWM1_CH1*/
+#define SYS_GPD_MFPH_PD13MFP_EBI_ADR17         (7ul << SYS_GPD_MFPH_PD13MFP_Pos)        /*!< GPD_MFPH PD13 setting for EBI_ADR17*/
+
+//PD14
+#define SYS_GPD_MFPH_PD14MFP_GPIO              (0ul << SYS_GPD_MFPH_PD14MFP_Pos)        /*!< GPD_MFPH_ PD14 setting for GPIO*/
+#define SYS_GPD_MFPH_PD14MFP_SPI2_MISO         (2ul << SYS_GPD_MFPH_PD14MFP_Pos)        /*!< GPD_MFPH_ PD14 setting for SPI2_MISO*/
+#define SYS_GPD_MFPH_PD14MFP_UART3_nCTS        (3ul << SYS_GPD_MFPH_PD14MFP_Pos)        /*!< GPD_MFPH_ PD14 setting for UART3_nCTS*/
+#define SYS_GPD_MFPH_PD14MFP_PWM1_CH2          (6ul << SYS_GPD_MFPH_PD14MFP_Pos)        /*!< GPD_MFPH_ PD14 setting for PWM1_CH2*/
+#define SYS_GPD_MFPH_PD14MFP_EBI_ADR18         (7ul << SYS_GPD_MFPH_PD14MFP_Pos)        /*!< GPD_MFPH_ PD14 setting for EBI_ADR18*/
+
+//PD15
+#define SYS_GPD_MFPH_PD15MFP_GPIO              (0ul << SYS_GPD_MFPH_PD15MFP_Pos)        /*!< GPD_MFPH_ PD15 setting for GPIO*/
+#define SYS_GPD_MFPH_PD15MFP_SPI2_CLK          (2ul << SYS_GPD_MFPH_PD15MFP_Pos)        /*!< GPD_MFPH_ PD15 setting for SPI2_CLK*/
+#define SYS_GPD_MFPH_PD15MFP_UART3_nRTS        (3ul << SYS_GPD_MFPH_PD15MFP_Pos)        /*!< GPD_MFPH_ PD15 setting for UART3_nRTS*/
+#define SYS_GPD_MFPH_PD15MFP_PWM1_CH3          (6ul << SYS_GPD_MFPH_PD15MFP_Pos)        /*!< GPD_MFPH_ PD15 setting for PWM1_CH3*/
+#define SYS_GPD_MFPH_PD15MFP_EBI_ADR19         (7ul << SYS_GPD_MFPH_PD15MFP_Pos)        /*!< GPD_MFPH_ PD15 setting for EBI_ADR19*/
+
+//PE0
+#define SYS_GPE_MFPL_PE0MFP_GPIO               (0ul << SYS_GPE_MFPL_PE0MFP_Pos)        /*!< GPE_MFPL PE0 setting for GPIO*/
+#define SYS_GPE_MFPL_PE0MFP_SPI2_CLK           (2ul << SYS_GPE_MFPL_PE0MFP_Pos)        /*!< GPE_MFPL PE0 setting for SPI2_CLK*/
+#define SYS_GPE_MFPL_PE0MFP_I2C1_SDA           (3ul << SYS_GPE_MFPL_PE0MFP_Pos)        /*!< GPE_MFPL PE0 setting for I2C1_SDA*/
+#define SYS_GPE_MFPL_PE0MFP_T2_EXT             (4ul << SYS_GPE_MFPL_PE0MFP_Pos)        /*!< GPE_MFPL PE0 setting for T2_EXT*/
+#define SYS_GPE_MFPL_PE0MFP_SC0_CD             (5ul << SYS_GPE_MFPL_PE0MFP_Pos)        /*!< GPE_MFPL PE0 setting for SC0_CD*/
+#define SYS_GPE_MFPL_PE0MFP_PWM0_CH0           (6ul << SYS_GPE_MFPL_PE0MFP_Pos)        /*!< GPE_MFPL PE0 setting for PWM0_CH0*/
+#define SYS_GPE_MFPL_PE0MFP_EBI_nCS1           (7ul << SYS_GPE_MFPL_PE0MFP_Pos)        /*!< GPE_MFPL PE0 setting for EBI_nCS1*/
+#define SYS_GPE_MFPL_PE0MFP_INT4               (8ul << SYS_GPE_MFPL_PE0MFP_Pos)        /*!< GPE_MFPL PE0 setting for INT4*/
+
+//PE1
+#define SYS_GPE_MFPL_PE1MFP_GPIO               (0ul << SYS_GPE_MFPL_PE1MFP_Pos)        /*!< GPE_MFPL PE1 setting for GPIO*/
+#define SYS_GPE_MFPL_PE1MFP_T3_EXT             (3ul << SYS_GPE_MFPL_PE1MFP_Pos)        /*!< GPE_MFPL PE1 setting for T3_EXT*/
+#define SYS_GPE_MFPL_PE1MFP_SC0_CD             (5ul << SYS_GPE_MFPL_PE1MFP_Pos)        /*!< GPE_MFPL PE1 setting for SC0_CD*/
+#define SYS_GPE_MFPL_PE1MFP_PWM0_CH1           (6ul << SYS_GPE_MFPL_PE1MFP_Pos)        /*!< GPE_MFPL PE1 setting for PWM0_CH1*/
+
+//PE2
+#define SYS_GPE_MFPL_PE2MFP_GPIO               (0ul << SYS_GPE_MFPL_PE2MFP_Pos)        /*!< GPE_MFPL PE2 setting for GPIO*/
+#define SYS_GPE_MFPL_PE2MFP_PWM1_CH1           (6ul << SYS_GPE_MFPL_PE2MFP_Pos)        /*!< GPE_MFPL PE2 setting for PWM1_CH1*/
+
+//PE3
+#define SYS_GPE_MFPL_PE3MFP_GPIO               (0ul << SYS_GPE_MFPL_PE3MFP_Pos)        /*!< GPE_MFPL PE3 setting for GPIO*/
+#define SYS_GPE_MFPL_PE3MFP_SPI1_MOSI          (2ul << SYS_GPE_MFPL_PE3MFP_Pos)        /*!< GPE_MFPL PE3 setting for SPI1_MOSI*/
+#define SYS_GPE_MFPL_PE3MFP_TK15               (4ul << SYS_GPE_MFPL_PE3MFP_Pos)        /*!< GPE_MFPL PE3 setting for TK15*/
+#define SYS_GPE_MFPL_PE3MFP_PWM0_CH3           (6ul << SYS_GPE_MFPL_PE3MFP_Pos)        /*!< GPE_MFPL PE3 setting for PWM0_CH3*/
+
+//PE4
+#define SYS_GPE_MFPL_PE4MFP_GPIO               (0ul << SYS_GPE_MFPL_PE4MFP_Pos)        /*!< GPE_MFPL PE4 setting for GPIO*/
+#define SYS_GPE_MFPL_PE4MFP_I2C1_SCL           (3ul << SYS_GPE_MFPL_PE4MFP_Pos)        /*!< GPE_MFPL PE4 setting for I2C1_SCL*/
+#define SYS_GPE_MFPL_PE4MFP_SC0_PWR            (5ul << SYS_GPE_MFPL_PE4MFP_Pos)        /*!< GPE_MFPL PE4 setting for SC0_PWR*/
+#define SYS_GPE_MFPL_PE4MFP_PWM1_BRAKE0        (6ul << SYS_GPE_MFPL_PE4MFP_Pos)        /*!< GPE_MFPL PE4 setting for PWM1_BRAKE0*/
+#define SYS_GPE_MFPL_PE4MFP_EBI_nCS0           (7ul << SYS_GPE_MFPL_PE4MFP_Pos)        /*!< GPE_MFPL PE4 setting for EBI_nCS0*/
+#define SYS_GPE_MFPL_PE4MFP_INT0               (8ul << SYS_GPE_MFPL_PE4MFP_Pos)        /*!< GPE_MFPL PE4 setting for INT0*/
+
+//PE5
+#define SYS_GPE_MFPL_PE5MFP_GPIO               (0ul << SYS_GPE_MFPL_PE5MFP_Pos)        /*!< GPE_MFPL PE5 setting for GPIO*/
+#define SYS_GPE_MFPL_PE5MFP_I2C1_SDA           (3ul << SYS_GPE_MFPL_PE5MFP_Pos)        /*!< GPE_MFPL PE5 setting for I2C1_SDA*/
+#define SYS_GPE_MFPL_PE5MFP_SC0_RST            (5ul << SYS_GPE_MFPL_PE5MFP_Pos)        /*!< GPE_MFPL PE5 setting for SC0_RST*/
+#define SYS_GPE_MFPL_PE5MFP_PWM1_BRAKE1        (6ul << SYS_GPE_MFPL_PE5MFP_Pos)        /*!< GPE_MFPL PE5 setting for PWM1_BRAKE1*/
+#define SYS_GPE_MFPL_PE5MFP_EBI_ALE            (7ul << SYS_GPE_MFPL_PE5MFP_Pos)        /*!< GPE_MFPL PE5 setting for EBI_ALE*/
+#define SYS_GPE_MFPL_PE5MFP_INT1               (8ul << SYS_GPE_MFPL_PE5MFP_Pos)        /*!< GPE_MFPL PE5 setting for INT1*/
+
+//PE6
+#define SYS_GPE_MFPL_PE6MFP_GPIO               (0ul << SYS_GPE_MFPL_PE6MFP_Pos)        /*!< GPE_MFPL PE6 setting for GPIO*/
+#define SYS_GPE_MFPL_PE6MFP_T3_EXT             (3ul << SYS_GPE_MFPL_PE6MFP_Pos)        /*!< GPE_MFPL PE6 setting for T3_EXT*/
+
+//PE7
+#define SYS_GPE_MFPL_PE7MFP_GPIO               (0ul << SYS_GPE_MFPL_PE7MFP_Pos)        /*!< GPE_MFPL PE7 setting for GPIO*/
+
+//PE8
+#define SYS_GPE_MFPH_PE8MFP_GPIO               (0ul << SYS_GPE_MFPH_PE8MFP_Pos)        /*!< GPE_MFPH PE8 setting for GPIO*/
+#define SYS_GPE_MFPH_PE8MFP_UART1_TXD          (1ul << SYS_GPE_MFPH_PE8MFP_Pos)        /*!< GPE_MFPH PE8 setting for UART1_TXD*/
+#define SYS_GPE_MFPH_PE8MFP_SPI0_MISO1         (2ul << SYS_GPE_MFPH_PE8MFP_Pos)        /*!< GPE_MFPH PE8 setting for SPI0_MISO1*/
+#define SYS_GPE_MFPH_PE8MFP_I2C1_SCL           (4ul << SYS_GPE_MFPH_PE8MFP_Pos)        /*!< GPE_MFPH PE8 setting for I2C1_SCL*/
+#define SYS_GPE_MFPH_PE8MFP_SC0_PWR            (5ul << SYS_GPE_MFPH_PE8MFP_Pos)        /*!< GPE_MFPH PE8 setting for SC0_PWR*/
+#define SYS_GPE_MFPH_PE8MFP_CLKO               (9ul << SYS_GPE_MFPH_PE8MFP_Pos)        /*!< GPE_MFPH PE8 setting for CLKO*/
+#define SYS_GPE_MFPH_PE8MFP_PWM0_BRAKE0        (10ul << SYS_GPE_MFPH_PE8MFP_Pos)       /*!< GPE_MFPH PE8 setting for PWM0_BRAKE0*/
+#define SYS_GPE_MFPH_PE8MFP_T1                 (11ul << SYS_GPE_MFPH_PE8MFP_Pos)       /*!< GPE_MFPH PE8 setting for T1*/
+
+//PE9
+#define SYS_GPE_MFPH_PE9MFP_GPIO               (0ul << SYS_GPE_MFPH_PE9MFP_Pos)        /*!< GPE_MFPH PE9 setting for GPIO*/
+#define SYS_GPE_MFPH_PE9MFP_UART1_RXD          (1ul << SYS_GPE_MFPH_PE9MFP_Pos)        /*!< GPE_MFPH PE9 setting for UART1_RXD*/
+#define SYS_GPE_MFPH_PE9MFP_SPI0_MOSI1         (2ul << SYS_GPE_MFPH_PE9MFP_Pos)        /*!< GPE_MFPH PE9 setting for SPI0_MOSI1*/
+#define SYS_GPE_MFPH_PE9MFP_I2C1_SDA           (4ul << SYS_GPE_MFPH_PE9MFP_Pos)        /*!< GPE_MFPH PE9 setting for I2C1_SDA*/
+#define SYS_GPE_MFPH_PE9MFP_SC0_RST            (5ul << SYS_GPE_MFPH_PE9MFP_Pos)        /*!< GPE_MFPH PE9 setting for SC0_RST*/
+#define SYS_GPE_MFPH_PE9MFP_SPI1_I2SMCLK       (9ul << SYS_GPE_MFPH_PE9MFP_Pos)        /*!< GPE_MFPH PE9 setting for SPI1_I2SMCLK*/
+#define SYS_GPE_MFPH_PE9MFP_PWM1_BRAKE1        (10ul << SYS_GPE_MFPH_PE9MFP_Pos)       /*!< GPE_MFPH PE9 setting for PWM1_BRAKE1*/
+#define SYS_GPE_MFPH_PE9MFP_T2                 (11ul << SYS_GPE_MFPH_PE9MFP_Pos)       /*!< GPE_MFPH PE9 setting for T2*/
+
+//PE10
+#define SYS_GPE_MFPH_PE10MFP_GPIO              (0ul << SYS_GPE_MFPH_PE10MFP_Pos)        /*!< GPE_MFPH PE10 setting for GPIO*/
+#define SYS_GPE_MFPH_PE10MFP_SPI1_MISO         (1ul << SYS_GPE_MFPH_PE10MFP_Pos)        /*!< GPE_MFPH PE10 setting for SPI1_MISO*/
+#define SYS_GPE_MFPH_PE10MFP_SPI0_MISO0        (2ul << SYS_GPE_MFPH_PE10MFP_Pos)        /*!< GPE_MFPH PE10 setting for SPI0_MISO0*/
+#define SYS_GPE_MFPH_PE10MFP_UART1_nCTS        (3ul << SYS_GPE_MFPH_PE10MFP_Pos)        /*!< GPE_MFPH PE10 setting for UART1_nCTS*/
+#define SYS_GPE_MFPH_PE10MFP_I2C0_SMBAL        (4ul << SYS_GPE_MFPH_PE10MFP_Pos)        /*!< GPE_MFPH PE10 setting for I2C0_SMBAL*/
+#define SYS_GPE_MFPH_PE10MFP_SC0_DAT           (5ul << SYS_GPE_MFPH_PE10MFP_Pos)        /*!< GPE_MFPH PE10 setting for SC0_DAT*/
+#define SYS_GPE_MFPH_PE10MFP_UART3_TXD         (9ul << SYS_GPE_MFPH_PE10MFP_Pos)        /*!< GPE_MFPH PE10 setting for UART3_TXD*/
+#define SYS_GPE_MFPH_PE10MFP_I2C1_SCL          (11ul << SYS_GPE_MFPH_PE10MFP_Pos)       /*!< GPE_MFPH PE10 setting for I2C1_SCL*/
+
+//PE11
+#define SYS_GPE_MFPH_PE11MFP_GPIO              (0ul << SYS_GPE_MFPH_PE11MFP_Pos)        /*!< GPE_MFPH PE11 setting for GPIO*/
+#define SYS_GPE_MFPH_PE11MFP_SPI1_MOSI         (1ul << SYS_GPE_MFPH_PE11MFP_Pos)        /*!< GPE_MFPH PE11 setting for SPI1_MOSI*/
+#define SYS_GPE_MFPH_PE11MFP_SPI0_MOSI0        (2ul << SYS_GPE_MFPH_PE11MFP_Pos)        /*!< GPE_MFPH PE11 setting for SPI0_MOSI0*/
+#define SYS_GPE_MFPH_PE11MFP_UART1_nRTS        (3ul << SYS_GPE_MFPH_PE11MFP_Pos)        /*!< GPE_MFPH PE11 setting for UART1_nRTS*/
+#define SYS_GPE_MFPH_PE11MFP_I2C0_SMBSUS       (4ul << SYS_GPE_MFPH_PE11MFP_Pos)        /*!< GPE_MFPH PE11 setting for I2C0_SMBSUS*/
+#define SYS_GPE_MFPH_PE11MFP_SC0_CLK           (5ul << SYS_GPE_MFPH_PE11MFP_Pos)        /*!< GPE_MFPH PE11 setting for SC0_CLK*/
+#define SYS_GPE_MFPH_PE11MFP_UART3_RXD         (9ul << SYS_GPE_MFPH_PE11MFP_Pos)        /*!< GPE_MFPH PE11 setting for UART3_RXD*/
+#define SYS_GPE_MFPH_PE11MFP_I2C1_SDA          (11ul << SYS_GPE_MFPH_PE11MFP_Pos)       /*!< GPE_MFPH PE11 setting for I2C1_SDA*/
+
+//PE12
+#define SYS_GPE_MFPH_PE12MFP_GPIO              (0ul << SYS_GPE_MFPH_PE12MFP_Pos)        /*!< GPE_MFPH PE12 setting for GPIO*/
+#define SYS_GPE_MFPH_PE12MFP_SPI1_SS           (1ul << SYS_GPE_MFPH_PE12MFP_Pos)        /*!< GPE_MFPH PE12 setting for SPI1_SS*/
+#define SYS_GPE_MFPH_PE12MFP_SPI0_SS           (2ul << SYS_GPE_MFPH_PE12MFP_Pos)        /*!< GPE_MFPH PE12 setting for SPI0_SS*/
+#define SYS_GPE_MFPH_PE12MFP_UART1_TXD         (3ul << SYS_GPE_MFPH_PE12MFP_Pos)        /*!< GPE_MFPH PE12 setting for UART1_TXD*/
+#define SYS_GPE_MFPH_PE12MFP_I2C0_SCL          (4ul << SYS_GPE_MFPH_PE12MFP_Pos)        /*!< GPE_MFPH PE12 setting for I2C0_SCL*/
+
+//PE13
+#define SYS_GPE_MFPH_PE13MFP_GPIO              (0ul << SYS_GPE_MFPH_PE13MFP_Pos)        /*!< GPE_MFPH PE13 setting for GPIO*/
+#define SYS_GPE_MFPH_PE13MFP_SPI1_CLK          (1ul << SYS_GPE_MFPH_PE13MFP_Pos)        /*!< GPE_MFPH PE13 setting for SPI1_CLK*/
+#define SYS_GPE_MFPH_PE13MFP_SPI0_CLK          (2ul << SYS_GPE_MFPH_PE13MFP_Pos)        /*!< GPE_MFPH PE13 setting for SPI0_CLK*/
+#define SYS_GPE_MFPH_PE13MFP_UART1_RXD         (3ul << SYS_GPE_MFPH_PE13MFP_Pos)        /*!< GPE_MFPH PE13 setting for UART1_RXD*/
+#define SYS_GPE_MFPH_PE13MFP_I2C0_SDA          (4ul << SYS_GPE_MFPH_PE13MFP_Pos)        /*!< GPE_MFPH PE13 setting for I2C0_SDA*/
+
+//PE14
+#define SYS_GPE_MFPH_PE14MFP_GPIO              (0ul << SYS_GPE_MFPH_PE14MFP_Pos)        /*!< GPE_MFPH PE14 setting for GPIO*/
+
+//PF0
+#define SYS_GPF_MFPL_PF0MFP_GPIO               (0ul << SYS_GPF_MFPL_PF0MFP_Pos)        /*!< GPF_MFPL PF0 setting for GPIO*/
+#define SYS_GPF_MFPL_PF0MFP_X32_OUT            (1ul << SYS_GPF_MFPL_PF0MFP_Pos)        /*!< GPF_MFPL PF0 setting for X32_OUT*/
+#define SYS_GPF_MFPL_PF0MFP_INT5               (8ul << SYS_GPF_MFPL_PF0MFP_Pos)        /*!< GPF_MFPL PF0 setting for INT5*/
+
+//PF1
+#define SYS_GPF_MFPL_PF1MFP_GPIO               (0ul << SYS_GPF_MFPL_PF1MFP_Pos)        /*!< GPF_MFPL PF1 setting for GPIO*/
+#define SYS_GPF_MFPL_PF1MFP_X32_IN             (1ul << SYS_GPF_MFPL_PF1MFP_Pos)        /*!< GPF_MFPL PF1 setting for X32_IN*/
+
+//PF2
+#define SYS_GPF_MFPL_PF2MFP_GPIO               (0ul << SYS_GPF_MFPL_PF2MFP_Pos)        /*!< GPF_MFPL PF2 setting for GPIO*/
+#define SYS_GPF_MFPL_PF2MFP_TAMPER             (1ul << SYS_GPF_MFPL_PF2MFP_Pos)        /*!< GPF_MFPL PF2 setting for TAMPER*/
+
+//PF3
+#define SYS_GPF_MFPL_PF3MFP_GPIO               (0ul << SYS_GPF_MFPL_PF3MFP_Pos)        /*!< GPF_MFPL PF3 setting for GPIO*/
+#define SYS_GPF_MFPL_PF3MFP_XT1_OUT            (1ul << SYS_GPF_MFPL_PF3MFP_Pos)        /*!< GPF_MFPL PF3 setting for XT1_OUT*/
+#define SYS_GPF_MFPL_PF3MFP_I2C1_SCL           (3ul << SYS_GPF_MFPL_PF3MFP_Pos)        /*!< GPF_MFPL PF3 setting for I2C1_SCL*/
+
+//PF4
+#define SYS_GPF_MFPL_PF4MFP_GPIO               (0ul << SYS_GPF_MFPL_PF4MFP_Pos)        /*!< GPF_MFPL PF4 setting for GPIO*/
+#define SYS_GPF_MFPL_PF4MFP_XT1_IN             (1ul << SYS_GPF_MFPL_PF4MFP_Pos)        /*!< GPF_MFPL PF4 setting for XT1_IN*/
+#define SYS_GPF_MFPL_PF4MFP_I2C1_SDA           (3ul << SYS_GPF_MFPL_PF4MFP_Pos)        /*!< GPF_MFPL PF4 setting for I2C1_SDA*/
+
+//PF5
+#define SYS_GPF_MFPL_PF5MFP_GPIO               (0ul << SYS_GPF_MFPL_PF5MFP_Pos)        /*!< GPF_MFPL PF5 setting for GPIO*/
+#define SYS_GPF_MFPL_PF5MFP_ICE_CLK            (1ul << SYS_GPF_MFPL_PF5MFP_Pos)        /*!< GPF_MFPL PF5 setting for ICE_CLK*/
+
+//PF6
+#define SYS_GPF_MFPL_PF6MFP_GPIO               (0ul << SYS_GPF_MFPL_PF6MFP_Pos)        /*!< GPF_MFPL PF6 setting for GPIO*/
+#define SYS_GPF_MFPL_PF6MFP_ICE_DAT            (1ul << SYS_GPF_MFPL_PF6MFP_Pos)        /*!< GPF_MFPL PF6 setting for ICE_DAT*/
+
+//PF7
+#define SYS_GPF_MFPL_PF7MFP_GPIO               (0ul << SYS_GPF_MFPL_PF7MFP_Pos)        /*!< GPF_MFPL PF7 setting for GPIO*/
+
+
+/*@}*/ /* end of group SYS_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief      Clear Brown-out detector interrupt flag
+  * @param      None
+  * @return     None
+  * @details    This macro clear Brown-out detector interrupt flag.
+  */
+#define SYS_CLEAR_BOD_INT_FLAG()        (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
+
+/**
+  * @brief      Set Brown-out detector function to normal mode
+  * @param      None
+  * @return     None
+  * @details    This macro set Brown-out detector to normal mode.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_CLEAR_BOD_LPM()             (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
+
+/**
+  * @brief      Disable Brown-out detector function
+  * @param      None
+  * @return     None
+  * @details    This macro disable Brown-out detector function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_DISABLE_BOD()               (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
+
+/**
+  * @brief      Enable Brown-out detector function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Brown-out detector function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_ENABLE_BOD()                (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
+
+/**
+  * @brief      Get Brown-out detector interrupt flag
+  * @param      None
+  * @retval     0   Brown-out detect interrupt flag is not set.
+  * @retval     >=1 Brown-out detect interrupt flag is set.
+  * @details    This macro get Brown-out detector interrupt flag.
+  */
+#define SYS_GET_BOD_INT_FLAG()          (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
+
+/**
+  * @brief      Get Brown-out detector status
+  * @param      None
+  * @retval     0   System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
+  * @retval     >=1 System voltage is lower than BOD threshold voltage setting.
+  * @details    This macro get Brown-out detector output status.
+  *             If the BOD function is disabled, this function always return 0.
+  */
+#define SYS_GET_BOD_OUTPUT()            (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
+
+/**
+  * @brief      Enable Brown-out detector interrupt function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Brown-out detector interrupt function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_DISABLE_BOD_RST()           (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
+
+/**
+  * @brief      Enable Brown-out detector reset function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Brown-out detect reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_ENABLE_BOD_RST()            (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
+
+/**
+  * @brief      Set Brown-out detector function low power mode
+  * @param      None
+  * @return     None
+  * @details    This macro set Brown-out detector to low power mode.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_SET_BOD_LPM()               (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
+
+/**
+  * @brief      Set Brown-out detector voltage level
+  * @param[in]  u32Level is Brown-out voltage level. Including :
+  *             - \ref SYS_BODCTL_BODVL_4_5V
+  *             - \ref SYS_BODCTL_BODVL_3_7V
+  *             - \ref SYS_BODCTL_BODVL_2_7V
+  *             - \ref SYS_BODCTL_BODVL_2_2V
+  * @return     None
+  * @details    This macro set Brown-out detector voltage level.
+  *             The write-protection function should be disabled before using this macro.
+  */
+#define SYS_SET_BOD_LEVEL(u32Level)     (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
+
+/**
+  * @brief      Get reset source is from Brown-out detector reset
+  * @param      None
+  * @retval     0   Previous reset source is not from Brown-out detector reset
+  * @retval     >=1 Previous reset source is from Brown-out detector reset
+  * @details    This macro get previous reset source is from Brown-out detect reset or not.
+  */
+#define SYS_IS_BOD_RST()                (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
+
+/**
+  * @brief      Get reset source is from CPU reset
+  * @param      None
+  * @retval     0   Previous reset source is not from CPU reset
+  * @retval     >=1 Previous reset source is from CPU reset
+  * @details    This macro get previous reset source is from CPU reset.
+  */
+#define SYS_IS_CPU_RST()                (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
+
+/**
+  * @brief      Get reset source is from LVR Reset
+  * @param      None     
+  * @retval     0   Previous reset source is not from Low-Voltage-Reset
+  * @retval     >=1 Previous reset source is from Low-Voltage-Reset
+  * @details    This macro get previous reset source is from Low-Voltage-Reset.   
+  */
+#define SYS_IS_LVR_RST()                (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
+
+/**
+  * @brief      Get reset source is from Power-on Reset
+  * @param      None
+  * @retval     0   Previous reset source is not from Power-on Reset
+  * @retval     >=1 Previous reset source is from Power-on Reset
+  * @details    This macro get previous reset source is from Power-on Reset.
+  */
+#define SYS_IS_POR_RST()                (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
+
+/**
+  * @brief      Get reset source is from reset pin reset
+  * @param      None
+  * @retval     0   Previous reset source is not from reset pin reset
+  * @retval     >=1 Previous reset source is from reset pin reset
+  * @details    This macro get previous reset source is from reset pin reset.
+  */
+#define SYS_IS_RSTPIN_RST()             (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
+
+/**
+  * @brief      Get reset source is from system reset
+  * @param      None
+  * @retval     0   Previous reset source is not from system reset
+  * @retval     >=1 Previous reset source is from system reset
+  * @details    This macro get previous reset source is from system reset.
+  */
+#define SYS_IS_SYSTEM_RST()             (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
+
+/**
+  * @brief      Get reset source is from window watch dog reset
+  * @param      None
+  * @retval     0   Previous reset source is not from window watch dog reset
+  * @retval     >=1 Previous reset source is from window watch dog reset
+  * @details    This macro get previous reset source is from window watch dog reset.
+  */
+#define SYS_IS_WDT_RST()                (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
+
+/**
+  * @brief      Disable Low-Voltage-Reset function
+  * @param      None
+  * @return     None
+  * @details    This macro disable Low-Voltage-Reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_DISABLE_LVR()               (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
+
+/**
+  * @brief      Enable Low-Voltage-Reset function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Low-Voltage-Reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_ENABLE_LVR()                (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
+
+/**
+  * @brief      Disable Power-on Reset function
+  * @param      None
+  * @return     None
+  * @details    This macro disable Power-on Reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_DISABLE_POR()               (SYS->PORCTL = 0x5AA5)
+
+/**
+  * @brief      Enable Power-on Reset function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Power-on Reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_ENABLE_POR()                (SYS->PORCTL = 0)
+
+/**
+  * @brief      Clear reset source flag
+  * @param[in]  u32RstSrc is reset source. Including :
+  *             - \ref SYS_RSTSTS_PORF_Msk
+  *             - \ref SYS_RSTSTS_PINRF_Msk
+  *             - \ref SYS_RSTSTS_WDTRF_Msk
+  *             - \ref SYS_RSTSTS_LVRF_Msk
+  *             - \ref SYS_RSTSTS_BODRF_Msk
+  *             - \ref SYS_RSTSTS_SYSRF_Msk
+  *             - \ref SYS_RSTSTS_CPURF_Msk
+  *             - \ref SYS_RSTSTS_CPULKRF_Msk
+  * @return     None
+  * @details    This macro clear reset source flag.
+  */
+#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+  * @brief      Disable register write-protection function
+  * @param      None
+  * @return     None
+  * @details    This function disable register write-protection function.
+  *             To unlock the protected register to allow write access.
+  */
+__STATIC_INLINE void SYS_UnlockReg(void)
+{
+    do
+    {
+        SYS->REGLCTL = 0x59;
+        SYS->REGLCTL = 0x16;
+        SYS->REGLCTL = 0x88;
+    }
+    while(SYS->REGLCTL == 0);
+}
+
+/**
+  * @brief      Enable register write-protection function
+  * @param      None
+  * @return     None
+  * @details    This function is used to enable register write-protection function.
+  *             To lock the protected register to forbid write access.
+  */
+__STATIC_INLINE void SYS_LockReg(void)
+{
+    SYS->REGLCTL = 0;
+}
+
+
+void SYS_ClearResetSrc(uint32_t u32Src);
+uint32_t SYS_GetBODStatus(void);
+uint32_t SYS_GetResetSrc(void);
+uint32_t SYS_IsRegLocked(void);
+uint32_t SYS_ReadPDID(void);
+void SYS_ResetChip(void);
+void SYS_ResetCPU(void);
+void SYS_ResetModule(uint32_t u32ModuleIndex);
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
+void SYS_DisableBOD(void);
+
+
+/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SYS_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  //__SYS_H__
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_timer.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_timer.c
new file mode 100644
index 00000000000..db8ce4225cc
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_timer.c
@@ -0,0 +1,292 @@
+/**************************************************************************//**
+ * @file     timer.c
+ * @version  V3.00
+ * $Revision: 6 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series Timer driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup TIMER_Driver TIMER Driver
+  @{
+*/
+
+/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Open Timer with Operate Mode and Frequency
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32Mode     Operation mode. Possible options are
+  *                         - \ref TIMER_ONESHOT_MODE
+  *                         - \ref TIMER_PERIODIC_MODE
+  *                         - \ref TIMER_TOGGLE_MODE
+  *                         - \ref TIMER_CONTINUOUS_MODE
+  * @param[in]  u32Freq     Target working frequency
+  *
+  * @return     Real timer working frequency
+  *
+  * @details    This API is used to configure timer to operate in specified mode and frequency.
+  *             If timer cannot work in target frequency, a closest frequency will be chose and returned.
+  * @note       After calling this API, Timer is \b NOT running yet. But could start timer running be calling
+  *             \ref TIMER_Start macro or program registers directly.
+  */
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
+{
+    uint32_t u32Clk = TIMER_GetModuleClock(timer);
+    uint32_t u32Cmpr = 0, u32Prescale = 0;
+
+    // Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, pre-scale = 0.
+    if(u32Freq > (u32Clk / 2))
+    {
+        u32Cmpr = 2;
+    }
+    else
+    {
+        if(u32Clk > 64000000)
+        {
+            u32Prescale = 7;    // real prescaler value is 8
+            u32Clk >>= 3;
+        }
+        else if(u32Clk > 32000000)
+        {
+            u32Prescale = 3;    // real prescaler value is 4
+            u32Clk >>= 2;
+        }
+        else if(u32Clk > 16000000)
+        {
+            u32Prescale = 1;    // real prescaler value is 2
+            u32Clk >>= 1;
+        }
+
+        u32Cmpr = u32Clk / u32Freq;
+    }
+
+    timer->CTL = u32Mode | u32Prescale;
+    timer->CMP = u32Cmpr;
+
+    return(u32Clk / (u32Cmpr * (u32Prescale + 1)));
+}
+
+/**
+  * @brief      Stop Timer Counting
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This API stops timer counting and disable all timer interrupt function.
+  */
+void TIMER_Close(TIMER_T *timer)
+{
+    timer->CTL = 0;
+    timer->EXTCTL = 0;
+}
+
+/**
+  * @brief      Create a specify Delay Time
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32Usec     Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second).
+  *
+  * @return     None
+  *
+  * @details    This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode.
+  * @note       This API overwrites the register setting of the timer used to count the delay time.
+  * @note       This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay.
+  */
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
+{
+    uint32_t u32Clk = TIMER_GetModuleClock(timer);
+    uint32_t u32Prescale = 0, delay = (SystemCoreClock / u32Clk) + 1;
+    uint32_t u32Cmpr, u32NsecPerTick;
+
+    // Clear current timer configuration/
+    timer->CTL = 0;
+    timer->EXTCTL = 0;
+
+    if(u32Clk <= 1000000)    // min delay is 1000 us if timer clock source is <= 1 MHz
+    {
+        if(u32Usec < 1000)
+            u32Usec = 1000;
+        if(u32Usec > 1000000)
+            u32Usec = 1000000;
+    }
+    else
+    {
+        if(u32Usec < 100)
+            u32Usec = 100;
+        if(u32Usec > 1000000)
+            u32Usec = 1000000;
+    }
+
+    if(u32Clk <= 1000000)
+    {
+        u32Prescale = 0;
+        u32NsecPerTick = 1000000000 / u32Clk;
+        u32Cmpr = (u32Usec * 1000) / u32NsecPerTick;
+    }
+    else
+    {
+        if(u32Clk > 64000000)
+        {
+            u32Prescale = 7;    // real prescaler value is 8
+            u32Clk >>= 3;
+        }
+        else if(u32Clk > 32000000)
+        {
+            u32Prescale = 3;    // real prescaler value is 4
+            u32Clk >>= 2;
+        }
+        else if(u32Clk > 16000000)
+        {
+            u32Prescale = 1;    // real prescaler value is 2
+            u32Clk >>= 1;
+        }
+
+        if(u32Usec < 250)
+        {
+            u32Cmpr = (u32Usec * u32Clk) / 1000000;
+        }
+        else
+        {
+            u32NsecPerTick = 1000000000 / u32Clk;
+            u32Cmpr = (u32Usec * 1000) / u32NsecPerTick;
+        }
+    }
+
+    timer->CMP = u32Cmpr;
+    timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale;
+
+    // When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
+    // And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
+    for(; delay > 0; delay--)
+    {
+        __NOP();
+    }
+
+    while(timer->CTL & TIMER_CTL_ACTSTS_Msk);
+}
+
+/**
+  * @brief      Enable Timer Capture Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32CapMode  Timer capture mode. Could be
+  *                         - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
+  *                         - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
+  * @param[in]  u32Edge     Timer capture trigger edge. Possible values are
+  *                         - \ref TIMER_CAPTURE_FALLING_EDGE
+  *                         - \ref TIMER_CAPTURE_RISING_EDGE
+  *                         - \ref TIMER_CAPTURE_FALLING_AND_RISING_EDGE
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable timer capture function with specify capture trigger edge \n
+  *             to get current counter value or reset counter value to 0.
+  * @note       Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly.
+  */
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
+{
+
+    timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) |
+                    u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+  * @brief      Disable Timer Capture Function
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the timer capture function.
+  */
+void TIMER_DisableCapture(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+  * @brief      Enable Timer Counter Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32Edge     Detection edge of counter pin. Could be ether
+  *                         - \ref TIMER_COUNTER_FALLING_EDGE, or
+  *                         - \ref TIMER_COUNTER_RISING_EDGE
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the timer counter function with specify detection edge.
+  * @note       Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly.
+  * @note       While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode.
+  */
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
+{
+    timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;
+    timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;
+}
+
+/**
+  * @brief      Disable Timer Counter Function
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the timer event counter function.
+  */
+void TIMER_DisableEventCounter(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;
+}
+
+/**
+  * @brief      Get Timer Clock Frequency
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     Timer clock frequency
+  *
+  * @details    This API is used to get the timer clock frequency.
+  * @note       This API cannot return correct clock rate if timer source is from external clock input.
+  */
+uint32_t TIMER_GetModuleClock(TIMER_T *timer)
+{
+    uint32_t u32Src;
+    const uint32_t au32Clk[] = {__HXT, __LXT, 0, 0, 0, __LIRC, 0, __HIRC};
+
+    if(timer == TIMER0)
+        u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos;
+    else if(timer == TIMER1)
+        u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos;
+    else if(timer == TIMER2)
+        u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos;
+    else  // Timer 3
+        u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos;
+
+    if(u32Src == 2)
+    {
+        return (SystemCoreClock);
+    }
+
+    return (au32Clk[u32Src]);
+}
+
+/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group TIMER_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_timer.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_timer.h
new file mode 100644
index 00000000000..de11f6774f8
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_timer.h
@@ -0,0 +1,415 @@
+/**************************************************************************//**
+ * @file     timer.h
+ * @version  V3.00
+ * $Revision: 10 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series Timer driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup TIMER_Driver TIMER Driver
+  @{
+*/
+
+/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  TIMER Operation Mode, External Counter and Capture Mode Constant Definitions                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TIMER_ONESHOT_MODE                      (0UL << TIMER_CTL_OPMODE_Pos)      /*!< Timer working in one-shot mode */
+#define TIMER_PERIODIC_MODE                     (1UL << TIMER_CTL_OPMODE_Pos)      /*!< Timer working in periodic mode */
+#define TIMER_TOGGLE_MODE                       (2UL << TIMER_CTL_OPMODE_Pos)      /*!< Timer working in toggle-output mode */
+#define TIMER_CONTINUOUS_MODE                   (3UL << TIMER_CTL_OPMODE_Pos)      /*!< Timer working in continuous counting mode */
+#define TIMER_TOUT_PIN_FROM_TX                  (0UL << TIMER_CTL_TGLPINSEL_Pos)   /*!< Timer toggle-output pin is from Tx pin */
+#define TIMER_TOUT_PIN_FROM_TX_EXT              (1UL << TIMER_CTL_TGLPINSEL_Pos)   /*!< Timer toggle-output pin is from Tx_EXT pin */
+#define TIMER_CAPTURE_FREE_COUNTING_MODE        (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value */
+#define TIMER_CAPTURE_COUNTER_RESET_MODE        (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter */
+#define TIMER_CAPTURE_FALLING_EDGE              (0UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< Falling edge detection to trigger timer capture */
+#define TIMER_CAPTURE_RISING_EDGE               (1UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< Rising edge detection to trigger timer capture */
+#define TIMER_CAPTURE_FALLING_AND_RISING_EDGE   (2UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< Both falling and rising edge detection to trigger timer capture */
+#define TIMER_COUNTER_FALLING_EDGE              (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection */
+#define TIMER_COUNTER_RISING_EDGE               (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection */
+
+/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Set Timer Compared Value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32Value    Timer compare value. Valid values are between 2 to 0xFFFFFF.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set timer compared value to adjust timer time-out interval.
+  * @note       1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n
+  *             2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n
+  *                But if timer is operating at other modes, the timer up counter will restart counting and start from 0.
+  */
+#define TIMER_SET_CMP_VALUE(timer, u32Value)        ((timer)->CMP = (u32Value))
+
+/**
+  * @brief      Set Timer Prescale Value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32Value    Timer prescale value. Valid values are between 0 to 0xFF.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n
+  *             before it is fed into timer.
+  */
+#define TIMER_SET_PRESCALE_VALUE(timer, u32Value)   ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
+
+/**
+  * @brief      Check specify Timer Status
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Timer 24-bit up counter is inactive
+  * @retval     1   Timer 24-bit up counter is active
+  *
+  * @details    This macro is used to check if specify Timer counter is inactive or active.
+  */
+#define TIMER_IS_ACTIVE(timer)                      (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0)
+
+/**
+  * @brief      Select Toggle-output Pin
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32ToutSel  Toggle-output pin selection, valid values are:
+  *                         - \ref TIMER_TOUT_PIN_FROM_TX
+  *                         - \ref TIMER_TOUT_PIN_FROM_TX_EXT
+  *
+  * @return     None
+  *
+  * @details    This macro is used to select timer toggle-output pin is output on Tx or Tx_EXT pin.
+  */
+#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel)    ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))
+
+/**
+  * @brief      Start Timer Counting
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to start Timer counting.
+  */
+static __INLINE void TIMER_Start(TIMER_T *timer)
+{
+    timer->CTL |= TIMER_CTL_CNTEN_Msk;
+}
+
+/**
+  * @brief      Stop Timer Counting
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to stop/suspend Timer counting.
+  */
+static __INLINE void TIMER_Stop(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_CNTEN_Msk;
+}
+
+/**
+  * @brief      Enable Timer Interrupt Wake-up Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n
+  *             counter event interrupt or capture trigger interrupt.
+  * @note       To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC.
+  */
+static __INLINE void TIMER_EnableWakeup(TIMER_T *timer)
+{
+    timer->CTL |= TIMER_CTL_WKEN_Msk;
+}
+
+/**
+  * @brief      Disable Timer Wake-up Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the timer interrupt wake-up function.
+  */
+static __INLINE void TIMER_DisableWakeup(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_WKEN_Msk;
+}
+
+/**
+  * @brief      Enable Capture Pin De-bounce
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the detect de-bounce function of capture pin.
+  */
+static __INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
+{
+    timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk;
+}
+
+/**
+  * @brief      Disable Capture Pin De-bounce
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the detect de-bounce function of capture pin.
+  */
+static __INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk;
+}
+
+/**
+  * @brief      Enable Counter Pin De-bounce
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the detect de-bounce function of counter pin.
+  */
+static __INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
+{
+    timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk;
+}
+
+/**
+  * @brief      Disable Counter Pin De-bounce
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the detect de-bounce function of counter pin.
+  */
+static __INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk;
+}
+
+/**
+  * @brief      Enable Timer Time-out Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the timer time-out interrupt function.
+  */
+static __INLINE void TIMER_EnableInt(TIMER_T *timer)
+{
+    timer->CTL |= TIMER_CTL_INTEN_Msk;
+}
+
+/**
+  * @brief      Disable Timer Time-out Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the timer time-out interrupt function.
+  */
+static __INLINE void TIMER_DisableInt(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_INTEN_Msk;
+}
+
+/**
+  * @brief      Enable Capture Trigger Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the timer capture trigger interrupt function.
+  */
+static __INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
+{
+    timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk;
+}
+
+/**
+  * @brief      Disable Capture Trigger Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the timer capture trigger interrupt function.
+  */
+static __INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk;
+}
+
+/**
+  * @brief      Get Timer Time-out Interrupt Flag
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Timer time-out interrupt did not occur
+  * @retval     1   Timer time-out interrupt occurred
+  *
+  * @details    This function indicates timer time-out interrupt occurred or not.
+  */
+static __INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
+{
+    return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0);
+}
+
+/**
+  * @brief      Clear Timer Time-out Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function clears timer time-out interrupt flag to 0.
+  */
+static __INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
+{
+    timer->INTSTS = (timer->INTSTS & ~TIMER_INTSTS_TWKF_Msk) | TIMER_INTSTS_TIF_Msk;
+}
+
+/**
+  * @brief      Get Timer Capture Interrupt Flag
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Timer capture interrupt did not occur
+  * @retval     1   Timer capture interrupt occurred
+  *
+  * @details    This function indicates timer capture trigger interrupt occurred or not.
+  */
+static __INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
+{
+    return timer->EINTSTS;
+}
+
+/**
+  * @brief      Clear Timer Capture Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function clears timer capture trigger interrupt flag to 0.
+  */
+static __INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
+{
+    timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk;
+}
+
+/**
+  * @brief      Get Timer Wake-up Flag
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Timer does not cause CPU wake-up
+  * @retval     1   Timer interrupt event cause CPU wake-up
+  *
+  * @details    This function indicates timer interrupt event has waked up system or not.
+  */
+static __INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
+{
+    return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1 : 0);
+}
+
+/**
+  * @brief      Clear Timer Wake-up Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function clears the timer wake-up system flag to 0.
+  */
+static __INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
+{
+    timer->INTSTS = (timer->INTSTS & ~TIMER_INTSTS_TIF_Msk) | TIMER_INTSTS_TWKF_Msk;
+}
+
+/**
+  * @brief      Get Capture value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     24-bit Capture Value
+  *
+  * @details    This function reports the current 24-bit timer capture value.
+  */
+static __INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
+{
+    return timer->CAP;
+}
+
+/**
+  * @brief      Get Counter value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     24-bit Counter Value
+  *
+  * @details    This function reports the current 24-bit timer counter value.
+  */
+static __INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
+{
+    return timer->CNT;
+}
+
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
+void TIMER_Close(TIMER_T *timer);
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
+void TIMER_DisableCapture(TIMER_T *timer);
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
+void TIMER_DisableEventCounter(TIMER_T *timer);
+uint32_t TIMER_GetModuleClock(TIMER_T *timer);
+
+/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group TIMER_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__TIMER_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_tk.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_tk.c
new file mode 100644
index 00000000000..4dcd0dc97d9
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_tk.c
@@ -0,0 +1,265 @@
+/**************************************************************************//**
+ * @file     tk.c
+ * @version  V1.00
+ * $Revision: 6 $
+ * $Date: 15/08/24 4:54p $
+ * @brief    M451 series TK driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+*****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup TK_Driver TK Driver
+  @{
+*/
+
+
+/** @addtogroup TK_EXPORTED_FUNCTIONS TK Exported Functions
+  @{
+*/
+
+
+/**
+ * @brief Enable touch key function
+ * @param None
+ * @return None
+ * @note This function will enable touch key function and initial idle and polarity state as GND first for all scan keys
+ * \hideinitializer
+ */
+
+void TK_Open(void)
+{
+    TK->CTL |= TK_CTL_TKEN_Msk;
+    //set idle and polarity state as GND
+    TK->IDLESEL = 0;
+    TK->POLSEL = 0;
+    TK->POLCTL &= ~(TK_POLCTL_IDLS16_Msk | TK_POLCTL_POLSEL16_Msk);
+}
+
+/**
+ * @brief Disable touch key function
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+void TK_Close(void)
+{
+    TK->CTL &= ~TK_CTL_TKEN_Msk;
+}
+
+/**
+ * @brief Set touch key scan mode
+ * @param[in] u32Mode Single ,periodic or all key scan mode
+ *              - \ref TK_SCAN_MODE_SINGLE
+ *              - \ref TK_SCAN_MODE_PERIODIC
+ *              - \ref TK_SCAN_MODE_ALL_KEY
+ *              - \ref TK_SCAN_MODE_PERIODIC_ALL_KEY
+ * @return None
+ * @details This function is used to set touch key scan mode.
+ * @note If touch key controller sets as periodic mode, touch key will be trigger scan by Timer0. So Timer0 must be enabled and operated in periodic mode.
+ *       If touch key controller sets as single scan mode, touch key can be trigger scan by calling TK_START_SCAN().
+ * \hideinitializer
+ */
+void TK_SetScanMode(uint32_t u32Mode)
+{
+    TK->CTL &= ~TK_CTL_TMRTRGEN_Msk;
+    TK->REFCTL &= ~TK_REFCTL_SCANALL_Msk;
+    if(u32Mode == TK_SCAN_MODE_PERIODIC)
+    {
+        TK->CTL |= u32Mode;
+    }
+    else if(u32Mode == TK_SCAN_MODE_ALL_KEY)
+    {
+        TK->REFCTL |= u32Mode;
+    }
+    else if(u32Mode == TK_SCAN_MODE_PERIODIC_ALL_KEY)
+    {
+        TK->CTL |= TK_CTL_TMRTRGEN_Msk;
+        TK->REFCTL |= TK_REFCTL_SCANALL_Msk;
+    }
+}
+
+/**
+ * @brief Configure touch key scan sensitivity
+ * @param[in] u32PulseWidth Sensing pulse width
+ *              - \ref TK_SENSE_PULSE_1
+ *              - \ref TK_SENSE_PULSE_2
+ *              - \ref TK_SENSE_PULSE_4
+ *              - \ref TK_SENSE_PULSE_8
+ * @param[in] u32SenseCnt Sensing count
+ *              - \ref TK_SENSE_CNT_128
+ *              - \ref TK_SENSE_CNT_255
+ *              - \ref TK_SENSE_CNT_511
+ *              - \ref TK_SENSE_CNT_1023
+ * @param[in] u32AVCCHSel voltage selection
+ *              - \ref TK_AVCCH_1_DIV_16
+ *              - \ref TK_AVCCH_1_DIV_8
+ *              - \ref TK_AVCCH_3_DIV_16
+ *              - \ref TK_AVCCH_1_DIV_4
+ *              - \ref TK_AVCCH_5_DIV_16
+ *              - \ref TK_AVCCH_3_DIV_8
+ *              - \ref TK_AVCCH_7_DIV_16
+ *              - \ref TK_AVCCH_1_DIV_2
+ * @return None
+ * @details This function is used to configure touch key scan sensitivity.
+ * \hideinitializer
+ */
+void TK_ConfigSensitivity(uint32_t u32PulseWidth, uint32_t u32SenseCnt, uint32_t u32AVCCHSel)
+{
+    TK->REFCTL = (TK->REFCTL & ~(TK_REFCTL_SENPTCTL_Msk | TK_REFCTL_SENTCTL_Msk)) | (u32PulseWidth | u32SenseCnt);
+    TK->CTL = (TK->CTL & ~TK_CTL_AVCCHSEL_Msk) | u32AVCCHSel;
+}
+
+/**
+ * @brief Set touch key capacitor bank polarity
+ * @param[in] u32CapBankPolSel capacitor bank polarity selection
+ *              - \ref TK_CAP_BANK_POL_SEL_GND
+ *              - \ref TK_CAP_BANK_POL_SEL_AVCCH
+ *              - \ref TK_CAP_BANK_POL_SEL_VDD
+ * @return None
+ * @details This function is used to set touch key capacitor bank polarity.
+ * \hideinitializer
+ */
+void TK_SetCapBankPol(uint32_t u32CapBankPolSel)
+{
+    TK->POLCTL = (TK->POLCTL & ~TK_POLCTL_CBPOLSEL_Msk) | u32CapBankPolSel;
+}
+
+/**
+ * @brief Configure touch key polarity
+ * @param[in] u32Mask Combination of touch keys which need to be configured
+ * @param[in] u32TKnPolSel touch key polarity selection
+ *              - \ref TK_TKn_POL_SEL_GND
+ *              - \ref TK_TKn_POL_SEL_AVCCH
+ *              - \ref TK_TKn_POL_SEL_VDD
+ * @return None
+ * @details This function is used to configure touch key polarity.
+ * \hideinitializer
+ */
+void TK_SetTkPol(uint32_t u32Mask, uint32_t u32PolSel)
+{
+    uint32_t i;
+
+    if((1ul << 16) & u32Mask)
+        TK->POLCTL = (TK->POLCTL & ~TK_POLCTL_POLSEL16_Msk) | (u32PolSel << TK_POLCTL_POLSEL16_Pos);
+
+    for(i = 0 ; i < 16 ; i++)
+    {
+        if((1ul << i) & u32Mask)
+            TK->POLSEL = (TK->POLSEL & ~(TK_POLSEL_POLSELn_Msk << (i*2))) | (u32PolSel << (i*2));
+    }
+}
+
+/**
+ * @brief Enable the polarity of specified touch key(s)
+ * @param[in] u32Mask Combination of enabled scan keys. Each bit corresponds to a touch key
+ *                           Bit 0 represents touch key 0, bit 1 represents touch key 1...
+ * @return None
+ * @details This function is used to enable the polarity of specified touch key(s).
+ * \hideinitializer
+ */
+void TK_EnableTkPolarity(uint32_t u32Mask)
+{
+    TK->POLCTL |= (u32Mask << TK_POLCTL_POLEN0_Pos);
+}
+
+/**
+ * @brief Disable the polarity of specified touch key(s)
+ * @param[in] u32Mask Combination of enabled scan keys. Each bit corresponds to a touch key
+ *                           Bit 0 represents touch key 0, bit 1 represents touch key 1...
+ * @return None
+ * @details This function is used to disable the polarity of specified touch key(s).
+ * \hideinitializer
+ */
+void TK_DisableTkPolarity(uint32_t u32Mask)
+{
+    TK->POLCTL &= ~(u32Mask << TK_POLCTL_POLEN0_Pos);
+}
+
+/**
+ * @brief Set complement capacitor bank data of specified touch key
+ * @param[in] u32TKNum Touch key number. The valid value is 0~16.
+ * @param[in] u32CapData Complement capacitor bank data. The valid value is 0~0xFF.
+ * @return None
+ * @details This function is used to set complement capacitor bank data of specified touch key.
+ * \hideinitializer
+ */
+void TK_SetCompCapBankData(uint32_t u32TKNum, uint32_t u32CapData)
+{
+    *(__IO uint32_t *)(&(TK->CCBDAT0) + (u32TKNum >> 2)) &= ~(TK_CCBDAT0_CCBDAT0_Msk << (u32TKNum % 4 * 8));
+    *(__IO uint32_t *)(&(TK->CCBDAT0) + (u32TKNum >> 2)) |= (u32CapData << (u32TKNum % 4 * 8));
+}
+
+/**
+ * @brief Set complement capacitor bank data of reference touch key
+ * @param[in] u32CapData Complement capacitor bank data. The valid value is 0~0xFF.
+ * @return None
+ * @details This function is used to set complement capacitor bank data of reference touch key.
+ * \hideinitializer
+ */
+void TK_SetRefKeyCapBankData(uint32_t u32CapData)
+{
+    TK->CCBDAT4 = (TK->CCBDAT4 & ~TK_CCBDAT4_REFCBDAT_Msk) | (u32CapData << TK_CCBDAT4_REFCBDAT_Pos);
+}
+
+/**
+ * @brief Set high and low threshold of specified touch key for threshold control interrupt
+ * @param[in] u32TKNum Touch key number. The valid value is 0~16.
+ * @param[in] u32HighLevel High level for touch key threshold control. The valid value is 0~0xFF.
+ * @param[in] u32LowLevel Low level for touch key threshold control. The valid value is 0~0xFF.
+ * @return None
+ * @details This function is used to set high and low threshold of specified touch key for threshold control interrupt.
+ * \hideinitializer
+ */
+void TK_SetScanThreshold(uint32_t u32TKNum, uint32_t u32HighLevel, uint32_t u32LowLevel)
+{
+    *(__IO uint32_t *)(&(TK->TH0_1) + (u32TKNum >> 1)) &= ~((TK_TH0_1_HTH0_Msk | TK_TH0_1_LTH0_Msk) << (u32TKNum % 2 * 16));
+    *(__IO uint32_t *)(&(TK->TH0_1) + (u32TKNum >> 1)) |= ((u32HighLevel << TK_TH0_1_HTH0_Pos) | (u32LowLevel << TK_TH0_1_LTH0_Pos)) << (u32TKNum % 2 * 16);
+}
+
+/**
+ * @brief Enable touch key scan interrupt
+ * @param[in] u32Msk Interrupt type selection.
+ *              - \ref TK_INT_EN_SCAN_COMPLETE
+ *              - \ref TK_INT_EN_SCAN_COMPLETE_EDGE_TH
+ *              - \ref TK_INT_EN_SCAN_COMPLETE_LEVEL_TH
+ * @return None
+ * @details This function is used to enable touch key scan interrupt.
+ * @note It need disable the enabled interrupt type first by TK_DisableInt() before to change enabled interrupt type.
+ * \hideinitializer
+ */
+void TK_EnableInt(uint32_t u32Msk)
+{
+    TK->INTEN |= u32Msk;
+}
+
+/**
+ * @brief Disable touch key scan interrupt
+ * @param[in] u32Msk Interrupt type selection.
+ *              - \ref TK_INT_EN_SCAN_COMPLETE
+ *              - \ref TK_INT_EN_SCAN_COMPLETE_EDGE_TH
+ *              - \ref TK_INT_EN_SCAN_COMPLETE_LEVEL_TH
+ * @return None
+ * @details This function is used to disable touch key scan interrupt.
+* @note It need disable the enabled interrupt type first by TK_DisableInt() before to change enabled interrupt type.
+ * \hideinitializer
+ */
+void TK_DisableInt(uint32_t u32Msk)
+{
+    TK->INTEN &= ~u32Msk;
+}
+
+
+/*@}*/ /* end of group TK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group TK_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_tk.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_tk.h
new file mode 100644
index 00000000000..ccbbadf6574
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_tk.h
@@ -0,0 +1,302 @@
+/**************************************************************************//**
+ * @file     tk.h
+ * @version  V1.00
+ * $Revision: 6 $
+ * $Date: 15/08/24 4:52p $
+ * @brief    M451 Series TK Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __TK_H__
+#define __TK_H__
+
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup TK_Driver TK Driver
+  @{
+*/
+
+/** @addtogroup TK_EXPORTED_CONSTANTS TK Exported Constants
+  @{
+*/
+
+#define TK_SCAN_MODE_SINGLE                 (0UL)  /*!< Touch key single scan mode */
+#define TK_SCAN_MODE_PERIODIC               (TK_CTL_TMRTRGEN_Msk)  /*!< Touch key periodic scan mode */
+#define TK_SCAN_MODE_ALL_KEY                (TK_REFCTL_SCANALL_Msk)  /*!< Touch key all keys scan mode */
+#define TK_SCAN_MODE_PERIODIC_ALL_KEY       (TK_CTL_TMRTRGEN_Msk | TK_REFCTL_SCANALL_Msk)  /*!< Touch key periodic with all keys scan mode */
+
+#define TK_SENSE_PULSE_1                    (0UL << TK_REFCTL_SENPTCTL_Pos)  /*!< Touch key sensing pulse width is 1us */
+#define TK_SENSE_PULSE_2                    (1UL << TK_REFCTL_SENPTCTL_Pos)  /*!< Touch key sensing pulse width is 2us */
+#define TK_SENSE_PULSE_4                    (2UL << TK_REFCTL_SENPTCTL_Pos)  /*!< Touch key sensing pulse width is 4us */
+#define TK_SENSE_PULSE_8                    (3UL << TK_REFCTL_SENPTCTL_Pos)  /*!< Touch key sensing pulse width is 8us */
+
+#define TK_SENSE_CNT_128                    (0UL << TK_REFCTL_SENTCTL_Pos)  /*!< Touch key sensing count is 128 */
+#define TK_SENSE_CNT_255                    (1UL << TK_REFCTL_SENTCTL_Pos)  /*!< Touch key sensing count is 255 */
+#define TK_SENSE_CNT_511                    (2UL << TK_REFCTL_SENTCTL_Pos)  /*!< Touch key sensing count is 511 */
+#define TK_SENSE_CNT_1023                   (3UL << TK_REFCTL_SENTCTL_Pos)  /*!< Touch key sensing count is 1023 */
+
+#define TK_AVCCH_1_DIV_16                   (0UL << TK_CTL_AVCCHSEL_Pos)  /*!< Touch key AVCCH voltage is 1/16 VDD */
+#define TK_AVCCH_1_DIV_8                    (1UL << TK_CTL_AVCCHSEL_Pos)  /*!< Touch key AVCCH voltage is 1/8 VDD */
+#define TK_AVCCH_3_DIV_16                   (2UL << TK_CTL_AVCCHSEL_Pos)  /*!< Touch key AVCCH voltage is 3/16 VDD */
+#define TK_AVCCH_1_DIV_4                    (3UL << TK_CTL_AVCCHSEL_Pos)  /*!< Touch key AVCCH voltage is 1/4 VDD */
+#define TK_AVCCH_5_DIV_16                   (4UL << TK_CTL_AVCCHSEL_Pos)  /*!< Touch key AVCCH voltage is 5/16 VDD */
+#define TK_AVCCH_3_DIV_8                    (5UL << TK_CTL_AVCCHSEL_Pos)  /*!< Touch key AVCCH voltage is 3/8 VDD */
+#define TK_AVCCH_7_DIV_16                   (6UL << TK_CTL_AVCCHSEL_Pos)  /*!< Touch key AVCCH voltage is 7/16 VDD */
+#define TK_AVCCH_1_DIV_2                    (7UL << TK_CTL_AVCCHSEL_Pos)  /*!< Touch key AVCCH voltage is 1/2 VDD */
+
+#define TK_CAP_BANK_POL_SEL_GND             (0UL << TK_POLCTL_CBPOLSEL_Pos)  /*!< Touch key capacitor bank polarity is GND */
+#define TK_CAP_BANK_POL_SEL_AVCCH           (1UL << TK_POLCTL_CBPOLSEL_Pos)  /*!< Touch key capacitor bank polarity is AVCCH */
+#define TK_CAP_BANK_POL_SEL_VDD             (2UL << TK_POLCTL_CBPOLSEL_Pos)  /*!< Touch key capacitor bank polarity is VDD */
+
+#define TK_TKn_POL_SEL_GND                  (0UL)  /*!< Touch key polarity is GND */
+#define TK_TKn_POL_SEL_AVCCH                (1UL)  /*!< Touch key polarity is AVCCH */
+#define TK_TKn_POL_SEL_VDD                  (2UL)  /*!< Touch key polarity is VDD */
+
+#define TK_INT_EN_SCAN_COMPLETE             (TK_INTEN_SCINTEN_Msk)  /*!< Touch key enable scan complete interrupt */
+#define TK_INT_EN_SCAN_COMPLETE_EDGE_TH     (TK_INTEN_SCTHIEN_Msk)  /*!< Touch key enable scan complete with threshold interrupt of edge trigger mode */
+#define TK_INT_EN_SCAN_COMPLETE_LEVEL_TH    (TK_INTEN_THIMOD_Msk | TK_INTEN_SCTHIEN_Msk)  /*!< Touch key enable scan complete with threshold interrupt of level trigger mode */
+
+#define TK_INT_SCAN_COMPLETE                (TK_STATUS_SCIF_Msk)  /*!< Touch key scan complete interrupt */
+#define TK_INT_SCAN_COMPLETE_TH_ALL         (0x1FFFF02UL)  /*!< Touch key scan complete or all touch keys threshold control interrupt */
+#define TK_INT_SCAN_TH_ALL                  (0x1FFFF00UL)  /*!< ALL Touch key threshold control interrupt */
+#define TK_INT_SCAN_TH_TK0                  (TK_STATUS_TKIF0_Msk)  /*!< Touch key 0 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK1                  (TK_STATUS_TKIF1_Msk)  /*!< Touch key 1 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK2                  (TK_STATUS_TKIF2_Msk)  /*!< Touch key 2 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK3                  (TK_STATUS_TKIF3_Msk)  /*!< Touch key 3 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK4                  (TK_STATUS_TKIF4_Msk)  /*!< Touch key 4 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK5                  (TK_STATUS_TKIF5_Msk)  /*!< Touch key 5 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK6                  (TK_STATUS_TKIF6_Msk)  /*!< Touch key 6 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK7                  (TK_STATUS_TKIF7_Msk)  /*!< Touch key 7 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK8                  (TK_STATUS_TKIF8_Msk)  /*!< Touch key 8 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK9                  (TK_STATUS_TKIF9_Msk)  /*!< Touch key 9 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK10                 (TK_STATUS_TKIF10_Msk)  /*!< Touch key 10 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK11                 (TK_STATUS_TKIF11_Msk)  /*!< Touch key 11 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK12                 (TK_STATUS_TKIF12_Msk)  /*!< Touch key 12 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK13                 (TK_STATUS_TKIF13_Msk)  /*!< Touch key 13 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK14                 (TK_STATUS_TKIF14_Msk)  /*!< Touch key 14 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK15                 (TK_STATUS_TKIF15_Msk)  /*!< Touch key 15 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK16                 (TK_STATUS_TKIF16_Msk)  /*!< Touch key 16 threshold control interrupt */
+
+
+/*@}*/ /* end of group TK_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup TK_EXPORTED_FUNCTIONS TK Exported Functions
+  @{
+*/
+
+/**
+ * @brief Enable scan key(s)
+ * @param[in] u32Mask Combination of enabled scan keys. Each bit corresponds to a touch key.
+ *                           Bit 0 represents touch key 0, bit 1 represents touch key 1...
+ * @return None
+ * @note Touch key 16 is the default reference key, so touch key 16 is enabled.
+ * \hideinitializer
+ */
+#define TK_ENABLE_SCAN_KEY(u32Mask) (TK->CTL |= (u32Mask))
+
+/**
+ * @brief Disable scan key(s)
+ * @param[in] u32Mask Combination of disabled scan keys. Each bit corresponds to a touch key.
+ *                           Bit 0 represents touch key 0, bit 1 represents touch key 1...
+ * @return None
+ * \hideinitializer
+ */
+#define TK_DISABLE_SCAN_KEY(u32Mask) (TK->CTL &= ~(u32Mask))
+
+/**
+ * @brief Enable reference key(s)
+ * @param[in] u32Mask Combination of enabled reference keys. Each bit corresponds to a touch key.
+ *                           Bit 0 represents touch key 0, bit 1 represents touch key 1...
+ * @return None
+ * @note Touch key 16 is the default reference key, so touch key 16 is enabled.
+ * \hideinitializer
+ */
+#define TK_ENABLE_REF_KEY(u32Mask) (TK->REFCTL |= (u32Mask))
+
+/**
+ * @brief Disable reference key(s)
+ * @param[in] u32Mask Combination of disabled reference keys. Each bit corresponds to a touch key.
+ *                           Bit 0 represents touch key 0, bit 1 represents touch key 1...
+ * @return None
+ * @note It must enable a reference key and touch key 16 is the default reference key.
+ *       If no any one touch key as reference key except touch key 16, then reference Touch key 16 can't be disable.
+ * \hideinitializer
+ */
+#define TK_DISABLE_REF_KEY(u32Mask) (TK->REFCTL &= ~(u32Mask))
+
+/**
+ * @brief Initiate enabled key(s) scan immediately.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define TK_START_SCAN() (TK->CTL |= TK_CTL_SCAN_Msk)
+
+/**
+ * @brief Set touch key Sensing pulse width.
+ * @param[in] u32PulseWidth Sensing pulse width.
+ *              - \ref TK_SENSE_PULSE_1
+ *              - \ref TK_SENSE_PULSE_2
+ *              - \ref TK_SENSE_PULSE_4
+ *              - \ref TK_SENSE_PULSE_8
+ * @return None
+ * \hideinitializer
+ */
+#define TK_SET_PULSE_WIDTH(u32PulseWidth) (TK->REFCTL = (TK->REFCTL & ~TK_REFCTL_SENPTCTL_Msk) | (u32PulseWidth))
+
+/**
+ * @brief Set touch key Sensing count.
+ * @param[in] u32SenseCnt Sensing count.
+ *              - \ref TK_SENSE_CNT_128
+ *              - \ref TK_SENSE_CNT_255
+ *              - \ref TK_SENSE_CNT_511
+ *              - \ref TK_SENSE_CNT_1023
+ * @return None
+ * \hideinitializer
+ */
+#define TK_SET_SENSING_CNT(u32SenseCnt) (TK->REFCTL = (TK->REFCTL & ~TK_REFCTL_SENTCTL_Msk) | (u32SenseCnt))
+
+
+/**
+ * @brief Set touch key AVCCH voltage.
+ * @param[in] u32AVCCHSel voltage selection.
+ *              - \ref TK_AVCCH_1_DIV_16
+ *              - \ref TK_AVCCH_1_DIV_8
+ *              - \ref TK_AVCCH_3_DIV_16
+ *              - \ref TK_AVCCH_1_DIV_4
+ *              - \ref TK_AVCCH_5_DIV_16
+ *              - \ref TK_AVCCH_3_DIV_8
+ *              - \ref TK_AVCCH_7_DIV_16
+ *              - \ref TK_AVCCH_1_DIV_2
+ * @return None
+ * \hideinitializer
+ */
+#define TK_SET_AVCCH(u32AVCCHSel) (TK->CTL = (TK->CTL & ~TK_CTL_AVCCHSEL_Msk) | (u32AVCCHSel))
+
+/**
+ * @brief Get touch key complement capacitor bank data.
+ * @param[in] u32TKNum Touch key number. The valid value is 0~16.
+ * @return Complement capacitor bank data
+ * \hideinitializer
+ */
+#define TK_GET_COMP_CAP_BANK_DATA(u32TKNum) (((*(__IO uint32_t *) (&(TK->CCBDAT0) + ((u32TKNum) >> 2))) >> ((u32TKNum) % 4 * 8) & TK_CCBDAT0_CCBDAT0_Msk))
+
+/**
+ * @brief Get touch key sensing result data.
+ * @param[in] u32TKNum Touch key number. The valid value is 0~16.
+ * @return Sensing result data
+ * \hideinitializer
+ */
+#define TK_GET_SENSE_DATA(u32TKNum) (((*(__IO uint32_t *) (&(TK->DAT0) + ((u32TKNum) >> 2))) >> ((u32TKNum) % 4 * 8) & TK_DAT0_TKDAT0_Msk))
+
+/**
+ * @brief Get touch key busy status.
+ * @param None
+ * @retval 0 Touch key is scan completed or stopped.
+ * @retval 1 Touch key is busy.
+ * \hideinitializer
+ */
+#define TK_IS_BUSY() ((TK->STATUS & TK_STATUS_BUSY_Msk) ? 1: 0)
+
+/**
+ * @brief Get touch key interrupt flag.
+ * @param[in] u32Mask Interrupt flag type selection.
+ *              - \ref TK_INT_SCAN_COMPLETE
+ *              - \ref TK_INT_SCAN_COMPLETE_TH_ALL
+ *              - \ref TK_INT_SCAN_TH_ALL
+ *              - \ref TK_INT_SCAN_TH_TK0
+ *              - \ref TK_INT_SCAN_TH_TK1
+ *              - \ref TK_INT_SCAN_TH_TK2
+ *              - \ref TK_INT_SCAN_TH_TK3
+ *              - \ref TK_INT_SCAN_TH_TK4
+ *              - \ref TK_INT_SCAN_TH_TK5
+ *              - \ref TK_INT_SCAN_TH_TK6
+ *              - \ref TK_INT_SCAN_TH_TK7
+ *              - \ref TK_INT_SCAN_TH_TK8
+ *              - \ref TK_INT_SCAN_TH_TK9
+ *              - \ref TK_INT_SCAN_TH_TK10
+ *              - \ref TK_INT_SCAN_TH_TK11
+ *              - \ref TK_INT_SCAN_TH_TK12
+ *              - \ref TK_INT_SCAN_TH_TK13
+ *              - \ref TK_INT_SCAN_TH_TK14
+ *              - \ref TK_INT_SCAN_TH_TK15
+ *              - \ref TK_INT_SCAN_TH_TK16
+ * @retval 0 Touch key has no interrupt.
+ * @retval 1 Touch key is scan completed or threshold control event occurs.
+ * \hideinitializer
+ */
+#define TK_GET_INT_STATUS(u32Mask) ((TK->STATUS & (u32Mask)) ? 1: 0)
+
+/**
+ * @brief Clear touch key interrupt flag.
+ * @param[in] u32Mask Interrupt flag type selection.
+ *              - \ref TK_INT_SCAN_COMPLETE
+ *              - \ref TK_INT_SCAN_COMPLETE_TH_ALL
+ *              - \ref TK_INT_SCAN_TH_ALL
+ *              - \ref TK_INT_SCAN_TH_TK0
+ *              - \ref TK_INT_SCAN_TH_TK1
+ *              - \ref TK_INT_SCAN_TH_TK2
+ *              - \ref TK_INT_SCAN_TH_TK3
+ *              - \ref TK_INT_SCAN_TH_TK4
+ *              - \ref TK_INT_SCAN_TH_TK5
+ *              - \ref TK_INT_SCAN_TH_TK6
+ *              - \ref TK_INT_SCAN_TH_TK7
+ *              - \ref TK_INT_SCAN_TH_TK8
+ *              - \ref TK_INT_SCAN_TH_TK9
+ *              - \ref TK_INT_SCAN_TH_TK10
+ *              - \ref TK_INT_SCAN_TH_TK11
+ *              - \ref TK_INT_SCAN_TH_TK12
+ *              - \ref TK_INT_SCAN_TH_TK13
+ *              - \ref TK_INT_SCAN_TH_TK14
+ *              - \ref TK_INT_SCAN_TH_TK15
+ *              - \ref TK_INT_SCAN_TH_TK16
+ * @return None
+ * \hideinitializer
+ */
+#define TK_CLR_INT_FLAG(u32Mask) (TK->STATUS = (u32Mask))
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define TK functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+void TK_Open(void);
+void TK_Close(void);
+void TK_SetScanMode(uint32_t u32Mode);
+void TK_ConfigSensitivity(uint32_t u32PulseWidth, uint32_t u32SenseCnt, uint32_t u32AVCCHSel);
+void TK_SetCapBankPol(uint32_t u32CapBankPolSel);
+void TK_EnableTkPolarity(uint32_t u32Mask);
+void TK_DisableTkPolarity(uint32_t u32Mask);
+void TK_SetCompCapBankData(uint32_t u32TKNum, uint32_t u32CapData);
+void TK_SetTkPol(uint32_t u32Mask, uint32_t u32PolSel);
+void TK_SetRefKeyCapBankData(uint32_t u32CapData);
+void TK_SetScanThreshold(uint32_t u32TKNum, uint32_t u32HighLevel, uint32_t u32LowLevel);
+void TK_EnableInt(uint32_t u32Msk);
+void TK_DisableInt(uint32_t u32Msk);
+
+
+/*@}*/ /* end of group TK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group TK_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__TK_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_uart.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_uart.c
new file mode 100644
index 00000000000..7b9047b70a9
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_uart.c
@@ -0,0 +1,512 @@
+/**************************************************************************//**
+ * @file     uart.c
+ * @version  V3.00
+ * $Revision: 22 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series UART driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <stdio.h>
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup UART_Driver UART Driver
+  @{
+*/
+
+/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
+  @{
+*/
+
+/**
+ *    @brief        Clear UART specified interrupt flag
+ *
+ *    @param[in]    uart                The pointer of the specified UART module.
+ *    @param[in]    u32InterruptFlag    The specified interrupt of UART module.
+ *                                      - \ref UART_INTSTS_LININT_Msk    : LIN bus interrupt
+ *                                      - \ref UART_INTSTS_DATWKIF_Msk   : Data Wake-up interrupt
+ *                                      - \ref UART_INTSTS_CTSWKIF_Msk   : CTS Wake-up interrupt
+ *                                      - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt
+ *                                      - \ref UART_INTSTS_MODEMINT_Msk  : Modem Status interrupt
+ *                                      - \ref UART_INTSTS_RLSINT_Msk    : Receive Line Status interrupt
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to clear UART specified interrupt flag.
+ */
+
+void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag)
+{
+
+    if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk)   /* Clear Receive Line Status Interrupt */
+    {
+        uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_FEF_Msk;
+        uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk)  /* Clear Modem Status Interrupt */
+        uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
+
+    if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk)   /* Clear Buffer Error Interrupt */
+    {
+        uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_CTSWKIF_Msk)   /* Clear CTS Wake-up Interrupt */
+    {
+        uart->INTSTS = UART_INTSTS_CTSWKIF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_DATWKIF_Msk)   /* Clear Data Wake-up Interrupt */
+    {
+        uart->INTSTS = UART_INTSTS_DATWKIF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_LININT_Msk)   /* Clear LIN Bus Interrupt */
+    {
+        uart->INTSTS = UART_INTSTS_LINIF_Msk;
+        uart->LINSTS = UART_LINSTS_BITEF_Msk    | UART_LINSTS_BRKDETF_Msk  |
+                       UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk |
+                       UART_LINSTS_SLVHEF_Msk   | UART_LINSTS_SLVHDETF_Msk ;
+    }
+}
+
+
+/**
+ *  @brief      Disable UART interrupt
+ *
+ *  @param[in]  uart The pointer of the specified UART module.
+ *
+ *  @return     None
+ *
+ *  @details    The function is used to disable UART interrupt.
+ */
+void UART_Close(UART_T* uart)
+{
+    uart->INTEN = 0;
+}
+
+
+/**
+ *  @brief      Disable UART auto flow control function
+ *
+ *  @param[in]  uart The pointer of the specified UART module.
+ *
+ *  @return     None
+ *
+ *  @details    The function is used to disable UART auto flow control.
+ */
+void UART_DisableFlowCtrl(UART_T* uart)
+{
+    uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
+}
+
+
+/**
+ *    @brief        Disable UART specified interrupt
+ *
+ *    @param[in]    uart                The pointer of the specified UART module.
+ *    @param[in]    u32InterruptFlag    The specified interrupt of UART module.
+ *                                      - \ref UART_INTEN_WKCTSIEN_Msk   : CTS wake-up interrupt
+ *                                      - \ref UART_INTEN_WKDATIEN_Msk   : Data wake-up interrupt
+ *                                      - \ref UART_INTEN_LINIEN_Msk     : Lin bus interrupt
+ *                                      - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                                      - \ref UART_INTEN_RXTOIEN_Msk    : Rx time-out interrupt
+ *                                      - \ref UART_INTEN_MODEMIEN_Msk   : Modem status interrupt
+ *                                      - \ref UART_INTEN_RLSIEN_Msk     : Receive Line status interrupt
+ *                                      - \ref UART_INTEN_THREIEN_Msk    : Tx empty interrupt
+ *                                      - \ref UART_INTEN_RDAIEN_Msk     : Rx ready interrupt *
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
+ */
+void UART_DisableInt(UART_T*  uart, uint32_t u32InterruptFlag)
+{
+    /* Disable UART specified interrupt */
+    UART_DISABLE_INT(uart, u32InterruptFlag);
+
+    /* Disable NVIC UART IRQ */
+    if(uart == UART0)
+        NVIC_DisableIRQ(UART0_IRQn);
+    else if(uart == UART1)
+        NVIC_DisableIRQ(UART1_IRQn);
+    else if(uart == UART2)
+        NVIC_DisableIRQ(UART2_IRQn);
+    else
+        NVIC_DisableIRQ(UART3_IRQn);
+}
+
+
+/**
+ *    @brief        Enable UART auto flow control function
+ *
+ *    @param[in]    uart    The pointer of the specified UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to Enable UART auto flow control.
+ */
+void UART_EnableFlowCtrl(UART_T* uart)
+{
+    /* Set RTS pin output is low level active */
+    uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
+
+    /* Set CTS pin input is low level active */
+    uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
+
+    /* Set RTS and CTS auto flow control enable */
+    uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
+}
+
+
+/**
+ *    @brief        The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
+ *
+ *    @param[in]    uart                The pointer of the specified UART module.
+ *    @param[in]    u32InterruptFlag    The specified interrupt of UART module:
+ *                                      - \ref UART_INTEN_WKCTSIEN_Msk   : CTS wake-up interrupt
+ *                                      - \ref UART_INTEN_WKDATIEN_Msk   : Data wake-up interrupt
+ *                                      - \ref UART_INTEN_LINIEN_Msk     : Lin bus interrupt
+ *                                      - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                                      - \ref UART_INTEN_RXTOIEN_Msk    : Rx time-out interrupt
+ *                                      - \ref UART_INTEN_MODEMIEN_Msk   : Modem status interrupt
+ *                                      - \ref UART_INTEN_RLSIEN_Msk     : Receive Line status interrupt
+ *                                      - \ref UART_INTEN_THREIEN_Msk    : Tx empty interrupt
+ *                                      - \ref UART_INTEN_RDAIEN_Msk     : Rx ready interrupt *
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
+ */
+void UART_EnableInt(UART_T*  uart, uint32_t u32InterruptFlag)
+{
+
+    /* Enable UART specified interrupt */
+    UART_ENABLE_INT(uart, u32InterruptFlag);
+
+    /* Enable NVIC UART IRQ */
+    if(uart == UART0)
+        NVIC_EnableIRQ(UART0_IRQn);
+    else if(uart == UART1)
+        NVIC_EnableIRQ(UART1_IRQn);
+    else if(uart == UART2)
+        NVIC_EnableIRQ(UART2_IRQn);
+    else
+        NVIC_EnableIRQ(UART3_IRQn);
+
+}
+
+
+/**
+ *    @brief        Open and set UART function
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32baudrate     The baudrate of UART module.
+ *
+ *    @return       None
+ *
+ *    @details      This function use to enable UART function and set baud-rate.
+ */
+void UART_Open(UART_T* uart, uint32_t u32baudrate)
+{
+    uint8_t u8UartClkSrcSel, u8UartClkDivNum;
+    uint32_t u32ClkTbl[4] = {__HXT, 0, __LXT, __HIRC};
+    uint32_t u32Baud_Div = 0;
+
+    /* Get UART clock source selection */
+    u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
+
+    /* Get UART clock divider number */
+    u8UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos;
+
+    /* Select UART function */
+    uart->FUNCSEL = UART_FUNCSEL_UART;
+
+    /* Set UART line configuration */
+    uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
+
+    /* Set UART Rx and RTS trigger level */
+    uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if(u8UartClkSrcSel == 1)
+        u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
+
+    /* Set UART baud rate */
+    if(u32baudrate != 0)
+    {
+        u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate);
+
+        if(u32Baud_Div > 0xFFFF)
+            uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate));
+        else
+            uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+    }
+}
+
+
+/**
+ *    @brief        Read UART data
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    pu8RxBuf        The buffer to receive the data of receive FIFO.
+ *    @param[in]    u32ReadBytes    The the read bytes number of data.
+ *
+ *    @return       u32Count Receive byte count
+ *
+ *    @details      The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
+ */
+uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
+{
+    uint32_t  u32Count, u32delayno;
+
+    for(u32Count = 0; u32Count < u32ReadBytes; u32Count++)
+    {
+        u32delayno = 0;
+
+        while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)   /* Check RX empty => failed */
+        {
+            u32delayno++;
+            if(u32delayno >= 0x40000000)
+                return FALSE;
+        }
+        pu8RxBuf[u32Count] = uart->DAT;    /* Get Data from UART RX  */
+    }
+
+    return u32Count;
+
+}
+
+
+/**
+ *    @brief        Set UART line configuration
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32baudrate     The register value of baudrate of UART module.
+ *                                  If u32baudrate = 0, UART baudrate will not change.
+ *    @param[in]    u32data_width   The data length of UART module.
+ *                                  - \ref UART_WORD_LEN_5
+ *                                  - \ref UART_WORD_LEN_6
+ *                                  - \ref UART_WORD_LEN_7
+ *                                  - \ref UART_WORD_LEN_8
+ *    @param[in]    u32parity       The parity setting (none/odd/even/mark/space) of UART module.
+ *                                  - \ref UART_PARITY_NONE
+ *                                  - \ref UART_PARITY_ODD
+ *                                  - \ref UART_PARITY_EVEN
+ *                                  - \ref UART_PARITY_MARK
+ *                                  - \ref UART_PARITY_SPACE
+ *    @param[in]    u32stop_bits    The stop bit length (1/1.5/2 bit) of UART module.
+ *                                  - \ref UART_STOP_BIT_1
+ *                                  - \ref UART_STOP_BIT_1_5
+ *                                  - \ref UART_STOP_BIT_2
+ *
+ *    @return       None
+ *
+ *    @details      This function use to config UART line setting.
+ */
+void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t  u32stop_bits)
+{
+    uint8_t u8UartClkSrcSel, u8UartClkDivNum;
+    uint32_t u32ClkTbl[4] = {__HXT, 0, __LXT, __HIRC};
+    uint32_t u32Baud_Div = 0;
+
+    /* Get UART clock source selection */
+    u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
+
+    /* Get UART clock divider number */
+    u8UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos;
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if(u8UartClkSrcSel == 1)
+        u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
+
+    /* Set UART baud rate */
+    if(u32baudrate != 0)
+    {
+        u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate);
+
+        if(u32Baud_Div > 0xFFFF)
+            uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate));
+        else
+            uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+    }
+
+    /* Set UART line configuration */
+    uart->LINE = u32data_width | u32parity | u32stop_bits;
+}
+
+
+/**
+ *    @brief        Set Rx timeout count
+ *
+ *    @param[in]    uart    The pointer of the specified UART module.
+ *    @param[in]    u32TOC  Rx timeout counter.
+ *
+ *    @return       None
+ *
+ *    @details      This function use to set Rx timeout count.
+ */
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
+{
+    /* Set time-out interrupt comparator */
+    uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
+
+    /* Set time-out counter enable */
+    uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
+}
+
+
+/**
+ *    @brief        Select and configure IrDA function
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32Buadrate     The baudrate of UART module.
+ *    @param[in]    u32Direction    The direction of UART module in IrDA mode:
+ *                                  - \ref UART_IRDA_TXEN
+ *                                  - \ref UART_IRDA_RXEN
+ *
+ *    @return       None
+  *
+ *    @details      The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
+ */
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
+{
+    uint8_t u8UartClkSrcSel, u8UartClkDivNum;
+    uint32_t u32ClkTbl[4] = {__HXT, 0, __LXT, __HIRC};
+    uint32_t u32Baud_Div;
+
+    /* Select IrDA function mode */
+    uart->FUNCSEL = UART_FUNCSEL_IrDA;
+
+    /* Get UART clock source selection */
+    u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
+
+    /* Get UART clock divider number */
+    u8UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos;
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if(u8UartClkSrcSel == 1)
+        u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
+
+    /* Set UART IrDA baud rate in mode 0 */
+    if(u32Buadrate != 0)
+    {
+        u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32Buadrate);
+
+        if(u32Baud_Div < 0xFFFF)
+            uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
+    }
+
+    /* Configure IrDA relative settings */
+    if(u32Direction == UART_IRDA_RXEN)
+    {
+        uart->IRDA |= UART_IRDA_RXINV_Msk;     //Rx signal is inverse
+        uart->IRDA &= ~UART_IRDA_TXEN_Msk;
+    }
+    else
+    {
+        uart->IRDA &= ~UART_IRDA_TXINV_Msk;    //Tx signal is not inverse
+        uart->IRDA |= UART_IRDA_TXEN_Msk;
+    }
+
+}
+
+
+/**
+ *    @brief        Select and configure RS485 function
+ *
+ *    @param[in]    uart        The pointer of the specified UART module.
+ *    @param[in]    u32Mode     The operation mode(NMM/AUD/AAD).
+ *                              - \ref UART_ALTCTL_RS485NMM_Msk
+ *                              - \ref UART_ALTCTL_RS485AUD_Msk
+ *                              - \ref UART_ALTCTL_RS485AAD_Msk
+ *    @param[in]    u32Addr     The RS485 address.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to set RS485 relative setting.
+ */
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
+{
+    /* Select UART RS485 function mode */
+    uart->FUNCSEL = UART_FUNCSEL_RS485;
+
+    /* Set RS585 configuration */
+    uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);
+    uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
+}
+
+
+/**
+ *    @brief        Select and configure LIN function
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32Mode         The LIN direction :
+ *                                  - \ref UART_ALTCTL_LINTXEN_Msk
+ *                                  - \ref UART_ALTCTL_LINRXEN_Msk
+ *    @param[in]    u32BreakLength  The breakfield length.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to set LIN relative setting.
+ */
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)
+{
+    /* Select LIN function mode */
+    uart->FUNCSEL = UART_FUNCSEL_LIN;
+
+    /* Select LIN function setting : Tx enable, Rx enable and break field length */
+    uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk);
+    uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));
+}
+
+
+/**
+ *    @brief        Write UART data
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    pu8TxBuf        The buffer to send the data to UART transmission FIFO.
+ *    @param[out]   u32WriteBytes   The byte number of data.
+ *
+ *    @return       u32Count transfer byte count
+ *
+ *    @details      The function is to write data into TX buffer to transmit data by UART.
+ */
+uint32_t UART_Write(UART_T* uart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
+{
+    uint32_t  u32Count, u32delayno;
+
+    for(u32Count = 0; u32Count != u32WriteBytes; u32Count++)
+    {
+        u32delayno = 0;
+        while((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) == 0)   /* Wait Tx empty and Time-out manner */
+        {
+            u32delayno++;
+            if(u32delayno >= 0x40000000)
+                return FALSE;
+        }
+        uart->DAT = pu8TxBuf[u32Count];    /* Send UART Data from buffer */
+    }
+
+    return u32Count;
+
+}
+
+
+/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group UART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2012~2015 Nuvoton Technology Corp. ***/
+
+
+
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_uart.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_uart.h
new file mode 100644
index 00000000000..071f4ff7b5d
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_uart.h
@@ -0,0 +1,460 @@
+/******************************************************************************
+ * @file     uart.h
+ * @version  V3.00
+ * $Revision: 36 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series UART driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __UART_H__
+#define __UART_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup UART_Driver UART Driver
+  @{
+*/
+
+/** @addtogroup UART_EXPORTED_CONSTANTS UART Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART FIFO size constants definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#define UART0_FIFO_SIZE 16 /*!< UART0 supports separated receive/transmit 16/16 bytes entry FIFO */
+#define UART1_FIFO_SIZE 16 /*!< UART1 supports separated receive/transmit 16/16 bytes entry FIFO */
+#define UART2_FIFO_SIZE 16 /*!< UART2 supports separated receive/transmit 16/16 bytes entry FIFO */    
+#define UART3_FIFO_SIZE 16 /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO */    
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_FIFO constants definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#define UART_FIFO_RFITL_1BYTE      (0x0 << UART_FIFO_RFITL_Pos)   /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte */
+#define UART_FIFO_RFITL_4BYTES     (0x1 << UART_FIFO_RFITL_Pos)   /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes */
+#define UART_FIFO_RFITL_8BYTES     (0x2 << UART_FIFO_RFITL_Pos)   /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes */
+#define UART_FIFO_RFITL_14BYTES    (0x3 << UART_FIFO_RFITL_Pos)   /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes */
+
+#define UART_FIFO_RTSTRGLV_1BYTE      (0x0 << UART_FIFO_RTSTRGLV_Pos)  /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte */
+#define UART_FIFO_RTSTRGLV_4BYTES     (0x1 << UART_FIFO_RTSTRGLV_Pos)  /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes */
+#define UART_FIFO_RTSTRGLV_8BYTES     (0x2 << UART_FIFO_RTSTRGLV_Pos)  /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes */
+#define UART_FIFO_RTSTRGLV_14BYTES    (0x3 << UART_FIFO_RTSTRGLV_Pos)  /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_LINE constants definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_WORD_LEN_5     (0) /*!< UART_LINE setting to set UART word length to 5 bits */
+#define UART_WORD_LEN_6     (1) /*!< UART_LINE setting to set UART word length to 6 bits */
+#define UART_WORD_LEN_7     (2) /*!< UART_LINE setting to set UART word length to 7 bits */
+#define UART_WORD_LEN_8     (3) /*!< UART_LINE setting to set UART word length to 8 bits */
+
+#define UART_PARITY_NONE    (0x0 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity   */
+#define UART_PARITY_ODD     (0x1 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity  */
+#define UART_PARITY_EVEN    (0x3 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity */
+#define UART_PARITY_MARK    (0x5 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1'  */
+#define UART_PARITY_SPACE   (0x7 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0'  */
+
+#define UART_STOP_BIT_1     (0x0 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit  */
+#define UART_STOP_BIT_1_5   (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length  */
+#define UART_STOP_BIT_2     (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART RTS ACTIVE LEVEL constants definitions                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_RTS_IS_LOW_LEV_ACTIVE   (0x1 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Active */
+#define UART_RTS_IS_HIGH_LEV_ACTIVE  (0x0 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Active */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_IRDA constants definitions                                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_IRDA_TXEN      (0x1 << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Tx mode */
+#define UART_IRDA_RXEN      (0x0 << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Rx mode */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_FUNCSEL constants definitions                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_FUNCSEL_UART  (0x0 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function  (Default) */
+#define UART_FUNCSEL_LIN   (0x1 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function             */
+#define UART_FUNCSEL_IrDA  (0x2 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function            */
+#define UART_FUNCSEL_RS485 (0x3 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function           */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_LINCTL constants definitions                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_LINCTL_BRKFL(x)    (((x)-1) << UART_LINCTL_BRKFL_Pos)  /*!< UART_LINCTL setting to set LIN Break Field Length, x = 10 ~ 15, default value is 12 */
+#define UART_LINCTL_BSL(x)      (((x)-1) << UART_LINCTL_BSL_Pos)    /*!< UART_LINCTL setting to set LIN Break/Sync Delimiter Length, x = 1 ~ 4 */
+#define UART_LINCTL_HSEL_BREAK             (0x0UL << UART_LINCTL_HSEL_Pos)    /*!< UART_LINCTL setting to set LIN Header Select to break field */
+#define UART_LINCTL_HSEL_BREAK_SYNC        (0x1UL << UART_LINCTL_HSEL_Pos)    /*!< UART_LINCTL setting to set LIN Header Select to break field and sync field */
+#define UART_LINCTL_HSEL_BREAK_SYNC_ID     (0x2UL << UART_LINCTL_HSEL_Pos)    /*!< UART_LINCTL setting to set LIN Header Select to break field, sync field and ID field*/
+#define UART_LINCTL_PID(x)      ((x) << UART_LINCTL_PID_Pos)       /*!< UART_LINCTL setting to set LIN PID value */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART BAUDRATE MODE constants definitions                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_BAUD_MODE0     (0) /*!< Set UART Baudrate Mode is Mode0 */
+#define UART_BAUD_MODE2     (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 */
+
+
+/*@}*/ /* end of group UART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
+  @{
+*/
+
+
+/**
+ *    @brief        Calculate UART baudrate mode0 divider
+ *
+ *    @param[in]    u32SrcFreq      UART clock frequency
+ *    @param[in]    u32BaudRate     Baudrate of UART module
+ *
+ *    @return       UART baudrate mode0 divider
+ *
+ *    @details      This macro calculate UART baudrate mode0 divider.
+ */
+#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate)    ((((u32SrcFreq) + ((u32BaudRate)*8)) / (u32BaudRate) >> 4)-2)
+
+
+/**
+ *    @brief        Calculate UART baudrate mode2 divider
+ *
+ *    @param[in]    u32SrcFreq      UART clock frequency
+ *    @param[in]    u32BaudRate     Baudrate of UART module
+ *
+ *    @return       UART baudrate mode2 divider
+ *
+ *    @details      This macro calculate UART baudrate mode2 divider.
+ */
+#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate)    ((((u32SrcFreq) + ((u32BaudRate)/2)) / (u32BaudRate))-2)
+
+
+/**
+ *    @brief        Write UART data
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *    @param[in]    u8Data  Data byte to transmit.
+ *
+ *    @return       None
+ *
+ *    @details      This macro write Data to Tx data register.
+ */
+#define UART_WRITE(uart, u8Data)    ((uart)->DAT = (u8Data))
+
+
+/**
+ *    @brief        Read UART data
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       The oldest data byte in RX FIFO.
+ *
+ *    @details      This macro read Rx data register.
+ */
+#define UART_READ(uart)    ((uart)->DAT)
+
+
+/**
+ *    @brief        Get Tx empty
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0   Tx FIFO is not empty
+ *    @retval       >=1 Tx FIFO is empty
+ *
+ *    @details      This macro get Transmitter FIFO empty register value.
+ */
+#define UART_GET_TX_EMPTY(uart)    ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)
+
+
+/**
+ *    @brief        Get Rx empty
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0   Rx FIFO is not empty
+ *    @retval       >=1 Rx FIFO is empty
+ *
+ *    @details      This macro get Receiver FIFO empty register value.
+ */
+#define UART_GET_RX_EMPTY(uart)    ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
+
+
+/**
+ *    @brief        Check specified uart port transmission is over.
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0 Tx transmission is not over
+ *    @retval       1 Tx transmission is over
+ *
+ *    @details      This macro return Transmitter Empty Flag register bit value.
+ *                  It indicates if specified uart port transmission is over nor not.
+ */
+#define UART_IS_TX_EMPTY(uart)    (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
+
+
+/**
+ *    @brief        Wait specified uart port transmission is over
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro wait specified uart port transmission is over.
+ */
+#define UART_WAIT_TX_EMPTY(uart)    while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
+
+
+/**
+ *    @brief        Check RX is ready or not
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0 The number of bytes in the RX FIFO is less than the RFITL
+ *    @retval       1 The number of bytes in the RX FIFO equals or larger than RFITL
+ *
+ *    @details      This macro check receive data available interrupt flag is set or not.
+ */
+#define UART_IS_RX_READY(uart)    (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
+
+
+/**
+ *    @brief        Check TX FIFO is full or not
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       1 TX FIFO is full
+ *    @retval       0 TX FIFO is not full
+ *
+ *    @details      This macro check TX FIFO is full or not.
+ */
+#define UART_IS_TX_FULL(uart)    (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
+
+
+/**
+ *    @brief        Check RX FIFO is full or not
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       1 RX FIFO is full
+ *    @retval       0 RX FIFO is not full
+ *
+ *    @details      This macro check RX FIFO is full or not.
+ */
+#define UART_IS_RX_FULL(uart)    (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
+
+
+/**
+ *    @brief        Get Tx full register value
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0   Tx FIFO is not full.
+ *    @retval       >=1 Tx FIFO is full.
+ *
+ *    @details      This macro get Tx full register value.
+ */
+#define UART_GET_TX_FULL(uart)    ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
+
+
+/**
+ *    @brief        Get Rx full register value
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0   Rx FIFO is not full.
+ *    @retval       >=1 Rx FIFO is full.
+ *
+ *    @details      This macro get Rx full register value.
+ */
+#define UART_GET_RX_FULL(uart)    ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
+
+
+/**
+ *    @brief        Enable specified UART interrupt
+ *
+ *    @param[in]    uart        The pointer of the specified UART module
+ *    @param[in]    u32eIntSel  Interrupt type select
+ *                              - \ref UART_INTEN_ABRIEN_Msk     : Auto baud rate interrupt
+ *                              - \ref UART_INTEN_WKCTSIEN_Msk   : CTS wakeup interrupt
+ *                              - \ref UART_INTEN_WKDATIEN_Msk   : Data wakeup interrupt
+ *                              - \ref UART_INTEN_LINIEN_Msk     : Lin bus interrupt
+ *                              - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                              - \ref UART_INTEN_RXTOIEN_Msk    : Rx time-out interrupt
+ *                              - \ref UART_INTEN_MODEMIEN_Msk   : Modem interrupt
+ *                              - \ref UART_INTEN_RLSIEN_Msk     : Rx Line status interrupt
+ *                              - \ref UART_INTEN_THREIEN_Msk    : Tx empty interrupt
+ *                              - \ref UART_INTEN_RDAIEN_Msk     : Rx ready interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified UART interrupt.
+ */
+#define UART_ENABLE_INT(uart, u32eIntSel)    ((uart)->INTEN |= (u32eIntSel))
+
+
+/**
+ *    @brief        Disable specified UART interrupt
+ *
+ *    @param[in]    uart        The pointer of the specified UART module
+ *    @param[in]    u32eIntSel  Interrupt type select
+ *                              - \ref UART_INTEN_ABRIEN_Msk     : Auto baud rate interrupt
+ *                              - \ref UART_INTEN_WKCTSIEN_Msk   : CTS wakeup interrupt
+ *                              - \ref UART_INTEN_WKDATIEN_Msk   : Data wakeup interrupt
+ *                              - \ref UART_INTEN_LINIEN_Msk     : Lin bus interrupt
+ *                              - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                              - \ref UART_INTEN_RXTOIEN_Msk    : Rx time-out interrupt
+ *                              - \ref UART_INTEN_MODEMIEN_Msk   : Modem status interrupt
+ *                              - \ref UART_INTEN_RLSIEN_Msk     : Receive Line status interrupt
+ *                              - \ref UART_INTEN_THREIEN_Msk    : Tx empty interrupt
+ *                              - \ref UART_INTEN_RDAIEN_Msk     : Rx ready interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified UART interrupt.
+ */
+#define UART_DISABLE_INT(uart, u32eIntSel)    ((uart)->INTEN &= ~ (u32eIntSel))
+
+
+/**
+ *    @brief        Get specified interrupt flag/status
+ *
+ *    @param[in]    uart            The pointer of the specified UART module
+ *    @param[in]    u32eIntTypeFlag Interrupt Type Flag, should be
+ *                                  - \ref UART_INTSTS_HWBUFEINT_Msk : In DMA Mode, Buffer Error Interrupt Indicator
+ *                                  - \ref UART_INTSTS_HWTOINT_Msk   : In DMA Mode, Time-out Interrupt Indicator
+ *                                  - \ref UART_INTSTS_HWMODINT_Msk  : In DMA Mode, MODEM Status Interrupt Indicator
+ *                                  - \ref UART_INTSTS_HWRLSINT_Msk  : In DMA Mode, Receive Line Status Interrupt Indicator
+ *                                  - \ref UART_INTSTS_HWBUFEIF_Msk  : In DMA Mode, Buffer Error Interrupt Flag
+ *                                  - \ref UART_INTSTS_HWTOIF_Msk    : In DMA Mode, Time-out Interrupt Flag
+ *                                  - \ref UART_INTSTS_HWMODIF_Msk   : In DMA Mode, MODEM Interrupt Flag
+ *                                  - \ref UART_INTSTS_HWRLSIF_Msk   : In DMA Mode, Receive Line Status Flag
+ *                                  - \ref UART_INTSTS_LININT_Msk    : LIN Bus Interrupt Indicator
+ *                                  - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator
+ *                                  - \ref UART_INTSTS_RXTOINT_Msk   : Time-out Interrupt Indicator
+ *                                  - \ref UART_INTSTS_MODEMINT_Msk  : Modem Status Interrupt Indicator
+ *                                  - \ref UART_INTSTS_RLSINT_Msk    : Receive Line Status Interrupt Indicator
+ *                                  - \ref UART_INTSTS_THREINT_Msk   : Transmit Holding Register Empty Interrupt Indicator
+ *                                  - \ref UART_INTSTS_RDAINT_Msk    : Receive Data Available Interrupt Indicator
+ *                                  - \ref UART_INTSTS_LINIF_Msk     : LIN Bus Flag
+ *                                  - \ref UART_INTSTS_BUFERRIF_Msk  : Buffer Error Interrupt Flag
+ *                                  - \ref UART_INTSTS_RXTOIF_Msk    : Rx Time-out Interrupt Flag
+ *                                  - \ref UART_INTSTS_MODEMIF_Msk   : Modem Interrupt Flag
+ *                                  - \ref UART_INTSTS_RLSIF_Msk     : Receive Line Status Interrupt Flag
+ *                                  - \ref UART_INTSTS_THREIF_Msk    : Tx Empty Interrupt Flag
+ *                                  - \ref UART_INTSTS_RDAIF_Msk     : Rx Ready Interrupt Flag
+ *
+ *    @retval       0 The specified interrupt is not happened.
+ *                  1 The specified interrupt is happened.
+ *
+ *    @details      This macro get specified interrupt flag or interrupt indicator status.
+ */
+#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag)    (((uart)->INTSTS & (u32eIntTypeFlag))?1:0)
+
+
+/**
+ *    @brief        Set RTS pin to low
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro set RTS pin to low.
+ */
+__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart)
+{
+    uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
+    uart->MODEM &= ~UART_MODEM_RTS_Msk;
+}
+
+
+/**
+ *    @brief        Set RTS pin to high
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro set RTS pin to high.
+ */
+__STATIC_INLINE void UART_SET_RTS(UART_T* uart)
+{
+    uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
+}
+
+
+/**
+ *    @brief        Clear RS-485 Address Byte Detection Flag
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro clear RS-485 address byte detection flag.
+ */
+#define UART_RS485_CLEAR_ADDR_FLAG(uart)    ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk)
+
+
+/**
+ *    @brief        Get RS-485 Address Byte Detection Flag
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0 Receiver detects a data that is not an address bit.
+ *    @retval       1 Receiver detects a data that is an address bit.
+ *
+ *    @details      This macro get RS-485 address byte detection flag.
+ */
+#define UART_RS485_GET_ADDR_FLAG(uart)    (((uart)->FIFOSTS  & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
+
+
+void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag);
+void UART_Close(UART_T* uart);
+void UART_DisableFlowCtrl(UART_T* uart);
+void UART_DisableInt(UART_T*  uart, uint32_t u32InterruptFlag);
+void UART_EnableFlowCtrl(UART_T* uart);
+void UART_EnableInt(UART_T*  uart, uint32_t u32InterruptFlag);
+void UART_Open(UART_T* uart, uint32_t u32baudrate);
+uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
+void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t  u32stop_bits);
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength);
+uint32_t UART_Write(UART_T* uart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
+
+
+
+
+/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group UART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__UART_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_usbd.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_usbd.c
new file mode 100644
index 00000000000..1759b1c82d6
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_usbd.c
@@ -0,0 +1,728 @@
+/**************************************************************************//**
+ * @file     usbd.c
+ * @version  V1.00
+ * $Revision: 21 $
+ * $Date: 15/08/21 3:34p $
+ * @brief    M451 series USBD driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include <string.h>
+#include "M451Series.h"
+
+#if 0
+#define DBG_PRINTF      printf
+#else
+#define DBG_PRINTF(...)
+#endif
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup USBD_Driver USBD Driver
+  @{
+*/
+
+
+/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions
+  @{
+*/
+
+/* Global variables for Control Pipe */
+uint8_t g_usbd_SetupPacket[8] = {0};        /*!< Setup packet buffer */
+volatile uint8_t g_usbd_RemoteWakeupEn = 0; /*!< Remote wake up function enable flag */
+
+/**
+ * @cond HIDDEN_SYMBOLS
+ */
+static volatile uint8_t *g_usbd_CtrlInPointer = 0;
+static volatile uint32_t g_usbd_CtrlInSize = 0;
+static volatile uint8_t *g_usbd_CtrlOutPointer = 0;
+static volatile uint32_t g_usbd_CtrlOutSize = 0;
+static volatile uint32_t g_usbd_CtrlOutSizeLimit = 0;
+static volatile uint32_t g_usbd_UsbAddr = 0;
+static volatile uint32_t g_usbd_UsbConfig = 0;
+static volatile uint32_t g_usbd_CtrlMaxPktSize = 8;
+static volatile uint32_t g_usbd_UsbAltInterface = 0;
+/**
+ * @endcond
+ */
+
+const S_USBD_INFO_T *g_usbd_sInfo;                  /*!< A pointer for USB information structure */
+
+VENDOR_REQ g_usbd_pfnVendorRequest       = NULL;    /*!< USB Vendor Request Functional Pointer */
+CLASS_REQ g_usbd_pfnClassRequest         = NULL;    /*!< USB Class Request Functional Pointer */
+SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL;    /*!< USB Set Interface Functional Pointer */
+SET_CONFIG_CB g_usbd_pfnSetConfigCallback = NULL;   /*!< USB Set configuration callback function pointer */
+uint32_t g_u32EpStallLock                = 0;       /*!< Bit map flag to lock specified EP when SET_FEATURE */
+
+/**
+  * @brief      This function makes USBD module to be ready to use
+  *
+  * @param[in]  param           The structure of USBD information.
+  * @param[in]  pfnClassReq     USB Class request callback function.
+  * @param[in]  pfnSetInterface USB Set Interface request callback function.
+  *
+  * @return     None
+  *
+  * @details    This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus.
+  */
+void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface)
+{
+    g_usbd_sInfo = param;
+    g_usbd_pfnClassRequest = pfnClassReq;
+    g_usbd_pfnSetInterface = pfnSetInterface;
+
+    /* get EP0 maximum packet size */
+    g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7];
+
+    /* Initial USB engine */
+    USBD->ATTR = 0x7D0;
+    /* Force SE0 */
+    USBD_SET_SE0();
+}
+
+/**
+  * @brief    This function makes USB host to recognize the device
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer.
+  */
+void USBD_Start(void)
+{
+    CLK_SysTickDelay(100000);
+    /* Disable software-disconnect function */
+    USBD_CLR_SE0();
+
+    /* Clear USB-related interrupts before enable interrupt */
+    USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
+
+    /* Enable USB-related interrupts. */
+    USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
+}
+
+/**
+  * @brief      Get the received SETUP packet
+  *
+  * @param[in]  buf A buffer pointer used to store 8-byte SETUP packet.
+  *
+  * @return     None
+  *
+  * @details    Store SETUP packet to a user-specified buffer.
+  *
+  */
+void USBD_GetSetupPacket(uint8_t *buf)
+{
+    USBD_MemCopy(buf, g_usbd_SetupPacket, 8);
+}
+
+/**
+  * @brief    Process SETUP packet
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Parse SETUP packet and perform the corresponding action.
+  *
+  */
+void USBD_ProcessSetupPacket(void)
+{
+    /* Get SETUP packet from USB buffer */
+    USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8);
+    /* Check the request type */
+    switch(g_usbd_SetupPacket[0] & 0x60)
+    {
+        case REQ_STANDARD:   // Standard
+        {
+            USBD_StandardRequest();
+            break;
+        }
+        case REQ_CLASS:   // Class
+        {
+            if(g_usbd_pfnClassRequest != NULL)
+            {
+                g_usbd_pfnClassRequest();
+            }
+            break;
+        }
+        case REQ_VENDOR:   // Vendor
+        {
+            if(g_usbd_pfnVendorRequest != NULL)
+            {
+                g_usbd_pfnVendorRequest();
+            }
+            break;
+        }
+        default:   // reserved
+        {
+            /* Setup error, stall the device */
+            USBD_SET_EP_STALL(EP0);
+            USBD_SET_EP_STALL(EP1);
+            break;
+        }
+    }
+}
+
+/**
+  * @brief    Process GetDescriptor request
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Parse GetDescriptor request and perform the corresponding action.
+  *
+  */
+void USBD_GetDescriptor(void)
+{
+    uint32_t u32Len;
+
+    u32Len = 0;
+    u32Len = g_usbd_SetupPacket[7];
+    u32Len <<= 8;
+    u32Len += g_usbd_SetupPacket[6];
+
+    switch(g_usbd_SetupPacket[3])
+    {
+        // Get Device Descriptor
+        case DESC_DEVICE:
+        {
+            u32Len = Minimum(u32Len, LEN_DEVICE);
+            DBG_PRINTF("Get device desc, %d\n", u32Len);
+
+            USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len);
+
+            break;
+        }
+        // Get Configuration Descriptor
+        case DESC_CONFIG:
+        {
+            uint32_t u32TotalLen;
+
+            u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3];
+            u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8);
+
+            DBG_PRINTF("Get config desc len %d, acture len %d\n", u32Len, u32TotalLen);
+            u32Len = Minimum(u32Len, u32TotalLen);
+            DBG_PRINTF("Minimum len %d\n", u32Len);
+
+            USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len);
+
+            break;
+        }
+        // Get HID Descriptor
+        case DESC_HID:
+        {
+            /* CV3.0 HID Class Descriptor Test, 
+               Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */
+            uint32_t u32ConfigDescOffset;   // u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index)
+            u32Len = Minimum(u32Len, LEN_HID);
+            DBG_PRINTF("Get HID desc, %d\n", u32Len);
+
+            u32ConfigDescOffset = g_usbd_sInfo->gu32ConfigHidDescIdx[g_usbd_SetupPacket[4]];
+            USBD_PrepareCtrlIn((uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len);
+
+            break;
+        }
+        // Get Report Descriptor
+        case DESC_HID_RPT:
+        {
+            DBG_PRINTF("Get HID report, %d\n", u32Len);
+
+            u32Len = Minimum(u32Len, g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]);
+            USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[g_usbd_SetupPacket[4]], u32Len);
+            break;
+        }
+        // Get String Descriptor
+        case DESC_STRING:
+        {
+            // Get String Descriptor
+            if(g_usbd_SetupPacket[2] < 4)
+            {
+                u32Len = Minimum(u32Len, g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]);
+                DBG_PRINTF("Get string desc %d\n", u32Len);
+
+                USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]], u32Len);
+
+
+                break;
+            }
+            else
+            {
+                // Not support. Reply STALL.
+                USBD_SET_EP_STALL(EP0);
+                USBD_SET_EP_STALL(EP1);
+
+                DBG_PRINTF("Unsupported string desc (%d). Stall ctrl pipe.\n", g_usbd_SetupPacket[2]);
+
+                break;
+            }
+        }
+        default:
+            // Not support. Reply STALL.
+            USBD_SET_EP_STALL(EP0);
+            USBD_SET_EP_STALL(EP1);
+
+            DBG_PRINTF("Unsupported get desc type. stall ctrl pipe\n");
+
+            break;
+    }
+}
+
+/**
+  * @brief    Process standard request
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Parse standard request and perform the corresponding action.
+  *
+  */
+void USBD_StandardRequest(void)
+{
+
+    /* clear global variables for new request */
+    g_usbd_CtrlInPointer = 0;
+    g_usbd_CtrlInSize = 0;
+
+    if(g_usbd_SetupPacket[0] & 0x80)    /* request data transfer direction */
+    {
+        // Device to host
+        switch(g_usbd_SetupPacket[1])
+        {
+            case GET_CONFIGURATION:
+            {
+                // Return current configuration setting
+                /* Data stage */
+                M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = g_usbd_UsbConfig;
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 1);
+                /* Status stage */
+                USBD_PrepareCtrlOut(0,0);
+
+                DBG_PRINTF("Get configuration\n");
+
+                break;
+            }
+            case GET_DESCRIPTOR:
+            {
+                USBD_GetDescriptor();
+                USBD_PrepareCtrlOut(0, 0); /* For status stage */
+                break;
+            }
+            case GET_INTERFACE:
+            {
+                // Return current interface setting
+                /* Data stage */
+                M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = g_usbd_UsbAltInterface;
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 1);
+                /* Status stage */
+                USBD_PrepareCtrlOut(0, 0);
+
+                DBG_PRINTF("Get interface\n");
+
+                break;
+            }
+            case GET_STATUS:
+            {
+                // Device
+                if(g_usbd_SetupPacket[0] == 0x80)
+                {
+                    uint8_t u8Tmp;
+
+                    u8Tmp = 0;
+                    if(g_usbd_sInfo->gu8ConfigDesc[7] & 0x40) u8Tmp |= 1; // Self-Powered/Bus-Powered.
+                    if(g_usbd_sInfo->gu8ConfigDesc[7] & 0x20) u8Tmp |= (g_usbd_RemoteWakeupEn << 1); // Remote wake up
+
+                    M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = u8Tmp;
+
+                }
+                // Interface
+                else if(g_usbd_SetupPacket[0] == 0x81)
+                    M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = 0;
+                // Endpoint
+                else if(g_usbd_SetupPacket[0] == 0x82)
+                {
+                    uint8_t ep = g_usbd_SetupPacket[4] & 0xF;
+                    M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = USBD_GetStall(ep) ? 1 : 0;
+                }
+
+                M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1) = 0;
+                /* Data stage */
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 2);
+                /* Status stage */
+                USBD_PrepareCtrlOut(0, 0);
+
+                DBG_PRINTF("Get status\n");
+
+                break;
+            }
+            default:
+            {
+                /* Setup error, stall the device */
+                USBD_SET_EP_STALL(EP0);
+                USBD_SET_EP_STALL(EP1);
+
+                DBG_PRINTF("Unknown request. stall ctrl pipe.\n");
+
+                break;
+            }
+        }
+    }
+    else
+    {
+        // Host to device
+        switch(g_usbd_SetupPacket[1])
+        {
+            case CLEAR_FEATURE:
+            {
+                if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT)
+                {
+                    int32_t epNum, i;
+
+                    /* EP number stall is not allow to be clear in MSC class "Error Recovery Test".
+                       a flag: g_u32EpStallLock is added to support it */
+                    epNum = g_usbd_SetupPacket[4] & 0xF;
+                    for(i = 0; i < USBD_MAX_EP; i++)
+                    {
+                        if(((USBD->EP[i].CFG & 0xF) == epNum) && ((g_u32EpStallLock & (1 << i)) == 0))
+                        {
+                            USBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk;
+                            DBG_PRINTF("Clr stall ep%d %x\n", i, USBD->EP[i].CFGP);
+                        }
+                    }
+                }
+                else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
+                    g_usbd_RemoteWakeupEn = 0;
+
+                /* Status stage */
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 0);
+
+                DBG_PRINTF("Clear feature op %d\n", g_usbd_SetupPacket[2]);
+
+                break;
+            }
+            case SET_ADDRESS:
+            {
+                g_usbd_UsbAddr = g_usbd_SetupPacket[2];
+                DBG_PRINTF("Set addr to %d\n", g_usbd_UsbAddr);
+
+                // DATA IN for end of setup
+                /* Status Stage */
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 0);
+
+                break;
+            }
+            case SET_CONFIGURATION:
+            {
+                g_usbd_UsbConfig = g_usbd_SetupPacket[2];
+
+                if(g_usbd_pfnSetConfigCallback)
+                    g_usbd_pfnSetConfigCallback();
+
+                // DATA IN for end of setup
+                /* Status stage */
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 0);
+
+                DBG_PRINTF("Set config to %d\n", g_usbd_UsbConfig);
+
+                break;
+            }
+            case SET_FEATURE:
+            {
+                if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT)
+                {
+                    USBD_SetStall(g_usbd_SetupPacket[4] & 0xF);
+                    DBG_PRINTF("Set feature. stall ep %d\n", g_usbd_SetupPacket[4] & 0xF);
+                }
+                else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
+                {
+                    g_usbd_RemoteWakeupEn = 1;
+                    DBG_PRINTF("Set feature. enable remote wakeup\n");
+                }
+
+                /* Status stage */
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 0);
+
+
+
+                break;
+            }
+            case SET_INTERFACE:
+            {
+                g_usbd_UsbAltInterface = g_usbd_SetupPacket[2];
+                if(g_usbd_pfnSetInterface != NULL)
+                    g_usbd_pfnSetInterface();
+                /* Status stage */
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 0);
+
+                DBG_PRINTF("Set interface to %d\n", g_usbd_UsbAltInterface);
+
+                break;
+            }
+            default:
+            {
+                /* Setup error, stall the device */
+                USBD_SET_EP_STALL(EP0);
+                USBD_SET_EP_STALL(EP1);
+
+                DBG_PRINTF("Unsupported request. stall ctrl pipe.\n");
+
+                break;
+            }
+        }
+    }
+}
+
+/**
+  * @brief      Prepare the first Control IN pipe
+  *
+  * @param[in]  pu8Buf  The pointer of data sent to USB host.
+  * @param[in]  u32Size The IN transfer size.
+  *
+  * @return     None
+  *
+  * @details    Prepare data for Control IN transfer.
+  *
+  */
+void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size)
+{
+    DBG_PRINTF("Prepare Ctrl In %d\n", u32Size);
+    if(u32Size > g_usbd_CtrlMaxPktSize)
+    {
+        // Data size > MXPLD
+        g_usbd_CtrlInPointer = pu8Buf + g_usbd_CtrlMaxPktSize;
+        g_usbd_CtrlInSize = u32Size - g_usbd_CtrlMaxPktSize;
+        USBD_SET_DATA1(EP0);
+        USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, g_usbd_CtrlMaxPktSize);
+        USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
+    }
+    else
+    {
+        // Data size <= MXPLD
+        g_usbd_CtrlInPointer = 0;
+        g_usbd_CtrlInSize = 0;
+        USBD_SET_DATA1(EP0);
+        USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, u32Size);
+        USBD_SET_PAYLOAD_LEN(EP0, u32Size);
+    }
+}
+
+/**
+  * @brief    Repeat Control IN pipe
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  This function processes the remained data of Control IN transfer.
+  *
+  */
+void USBD_CtrlIn(void)
+{
+    static uint8_t u8ZeroFlag = 0;
+    
+    DBG_PRINTF("Ctrl In Ack. residue %d\n", g_usbd_CtrlInSize);
+    if(g_usbd_CtrlInSize)
+    {
+        // Process remained data
+        if(g_usbd_CtrlInSize > g_usbd_CtrlMaxPktSize)
+        {
+            // Data size > MXPLD
+            USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlMaxPktSize);
+            USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
+            g_usbd_CtrlInPointer += g_usbd_CtrlMaxPktSize;
+            g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize;
+        }
+        else
+        {
+            // Data size <= MXPLD
+            USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlInSize);
+            USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlInSize);
+            if(g_usbd_CtrlInSize == g_usbd_CtrlMaxPktSize)
+                u8ZeroFlag = 1;
+            g_usbd_CtrlInPointer = 0;
+            g_usbd_CtrlInSize = 0;
+        }
+    }
+    else // No more data for IN token
+    {
+        // In ACK for Set address
+        if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS))
+        {
+            if((USBD_GET_ADDR() != g_usbd_UsbAddr) && (USBD_GET_ADDR() == 0))
+            {
+                USBD_SET_ADDR(g_usbd_UsbAddr);
+            }
+        }
+
+        /* For the case of data size is integral times maximum packet size */
+        if(u8ZeroFlag)
+        {
+            USBD_SET_PAYLOAD_LEN(EP0, 0);
+            u8ZeroFlag = 0;
+        }
+        
+        DBG_PRINTF("Ctrl In done.\n");
+
+    }
+}
+
+/**
+  * @brief      Prepare the first Control OUT pipe
+  *
+  * @param[in]  pu8Buf  The pointer of data received from USB host.
+  * @param[in]  u32Size The OUT transfer size.
+  *
+  * @return     None
+  *
+  * @details    This function is used to prepare the first Control OUT transfer.
+  *
+  */
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size)
+{
+    g_usbd_CtrlOutPointer = pu8Buf;
+    g_usbd_CtrlOutSize = 0;
+    g_usbd_CtrlOutSizeLimit = u32Size;
+    USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
+}
+
+/**
+  * @brief    Repeat Control OUT pipe
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  This function processes the successive Control OUT transfer.
+  *
+  */
+void USBD_CtrlOut(void)
+{
+    uint32_t u32Size;
+
+    DBG_PRINTF("Ctrl Out Ack %d\n", g_usbd_CtrlOutSize);
+
+    if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit)
+    {
+        u32Size = USBD_GET_PAYLOAD_LEN(EP1);
+        USBD_MemCopy((uint8_t *)g_usbd_CtrlOutPointer, (uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1), u32Size);
+        g_usbd_CtrlOutPointer += u32Size;
+        g_usbd_CtrlOutSize += u32Size;
+
+        if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit)
+            USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
+
+    }
+}
+
+/**
+  * @brief    Reset software flags
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  This function resets all variables for protocol and resets USB device address to 0.
+  *
+  */
+void USBD_SwReset(void)
+{
+    int i;
+    
+    // Reset all variables for protocol
+    g_usbd_CtrlInPointer = 0;
+    g_usbd_CtrlInSize = 0;
+    g_usbd_CtrlOutPointer = 0;
+    g_usbd_CtrlOutSize = 0;
+    g_usbd_CtrlOutSizeLimit = 0;
+    g_u32EpStallLock = 0;
+    memset(g_usbd_SetupPacket, 0, 8);
+
+    /* Reset PID DATA0 */
+    for(i=0; i<USBD_MAX_EP; i++)
+        USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;
+
+    // Reset USB device address
+    USBD_SET_ADDR(0);
+}
+
+/**
+ * @brief       USBD Set Vendor Request
+ *
+ * @param[in]   pfnVendorReq    Vendor Request Callback Function
+ *
+ * @return      None
+ *
+ * @details     This function is used to set USBD vendor request callback function
+ */
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq)
+{
+    g_usbd_pfnVendorRequest = pfnVendorReq;
+}
+
+/**
+ * @brief       The callback function which called when get SET CONFIGURATION request
+ *
+ * @param[in]   pfnSetConfigCallback    Callback function pointer for SET CONFIGURATION request
+ *
+ * @return      None
+ *
+ * @details     This function is used to set the callback function which will be called at SET CONFIGURATION request.
+ */
+void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback)
+{
+    g_usbd_pfnSetConfigCallback = pfnSetConfigCallback;
+}
+
+
+/**
+ * @brief       EP stall lock function to avoid stall clear by USB SET FEATURE request.
+ *
+ * @param[in]   u32EpBitmap    Use bitmap to select which endpoints will be locked
+ *
+ * @return      None
+ *
+ * @details     This function is used to lock relative endpoint to avoid stall clear by SET FEATURE requst.
+ *              If ep stall locked, user needs to reset USB device or re-configure device to clear it.
+ */
+void USBD_LockEpStall(uint32_t u32EpBitmap)
+{
+    g_u32EpStallLock = u32EpBitmap;
+}
+
+
+
+
+
+/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USBD_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_usbd.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_usbd.h
new file mode 100644
index 00000000000..55d6adbf359
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_usbd.h
@@ -0,0 +1,664 @@
+/******************************************************************************
+ * @file     usbd.h
+ * @brief    M451 series USB driver header file
+ * @version  2.0.0
+ * @date     10, January, 2014
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __USBD_H__
+#define __USBD_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup USBD_Driver USBD Driver
+  @{
+*/
+
+/** @addtogroup USBD_EXPORTED_STRUCTS USBD Exported Structs
+  @{
+*/
+typedef struct s_usbd_info
+{
+    const uint8_t *gu8DevDesc;            /*!< Pointer for USB Device Descriptor          */
+    const uint8_t *gu8ConfigDesc;         /*!< Pointer for USB Configuration Descriptor   */
+    const uint8_t **gu8StringDesc;        /*!< Pointer for USB String Descriptor pointers */
+    const uint8_t **gu8HidReportDesc;     /*!< Pointer for USB HID Report Descriptor      */
+    const uint32_t *gu32HidReportSize;    /*!< Pointer for HID Report descriptor Size */
+    const uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */	
+
+} S_USBD_INFO_T;
+
+extern const S_USBD_INFO_T gsInfo;
+
+/*@}*/ /* end of group USBD_EXPORTED_STRUCTS */
+
+
+
+
+/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants
+  @{
+*/
+#define USBD_BUF_BASE   (USBD_BASE+0x100)
+#define USBD_MAX_EP     8
+
+#define EP0     0       /*!< Endpoint 0 */
+#define EP1     1       /*!< Endpoint 1 */
+#define EP2     2       /*!< Endpoint 2 */
+#define EP3     3       /*!< Endpoint 3 */
+#define EP4     4       /*!< Endpoint 4 */
+#define EP5     5       /*!< Endpoint 5 */
+#define EP6     6       /*!< Endpoint 6 */
+#define EP7     7       /*!< Endpoint 7 */
+
+
+/*!<USB Request Type */
+#define REQ_STANDARD        0x00
+#define REQ_CLASS           0x20
+#define REQ_VENDOR          0x40
+
+/*!<USB Standard Request */
+#define GET_STATUS          0x00
+#define CLEAR_FEATURE       0x01
+#define SET_FEATURE         0x03
+#define SET_ADDRESS         0x05
+#define GET_DESCRIPTOR      0x06
+#define SET_DESCRIPTOR      0x07
+#define GET_CONFIGURATION   0x08
+#define SET_CONFIGURATION   0x09
+#define GET_INTERFACE       0x0A
+#define SET_INTERFACE       0x0B
+#define SYNC_FRAME          0x0C
+
+/*!<USB Descriptor Type */
+#define DESC_DEVICE         0x01
+#define DESC_CONFIG         0x02
+#define DESC_STRING         0x03
+#define DESC_INTERFACE      0x04
+#define DESC_ENDPOINT       0x05
+#define DESC_QUALIFIER      0x06
+#define DESC_OTHERSPEED     0x07
+
+/*!<USB HID Descriptor Type */
+#define DESC_HID            0x21
+#define DESC_HID_RPT        0x22
+
+/*!<USB Descriptor Length */
+#define LEN_DEVICE          18
+#define LEN_CONFIG          9
+#define LEN_INTERFACE       9
+#define LEN_ENDPOINT        7
+#define LEN_HID             9
+#define LEN_CCID            0x36
+
+/*!<USB Endpoint Type */
+#define EP_ISO              0x01
+#define EP_BULK             0x02
+#define EP_INT              0x03
+
+#define EP_INPUT            0x80
+#define EP_OUTPUT           0x00
+
+/*!<USB Feature Selector */
+#define FEATURE_DEVICE_REMOTE_WAKEUP    0x01
+#define FEATURE_ENDPOINT_HALT           0x00
+
+/******************************************************************************/
+/*                USB Specific Macros                                         */
+/******************************************************************************/
+
+#define USBD_WAKEUP_EN          USBD_INTEN_WKEN_Msk         /*!< USB Wake-up Enable */
+#define USBD_DRVSE0             USBD_SE0_SE0_Msk            /*!< Drive SE0 */
+
+#define USBD_DPPU_EN            USBD_ATTR_DPPUEN_Msk        /*!< USB D+ Pull-up Enable */
+#define USBD_PWRDN              USBD_ATTR_PWRDN_Msk         /*!< PHY Turn-On */
+#define USBD_PHY_EN             USBD_ATTR_PHYEN_Msk         /*!< PHY Enable */
+#define USBD_USB_EN             USBD_ATTR_USBEN_Msk         /*!< USB Enable */
+
+#define USBD_INT_BUS            USBD_INTEN_BUSIEN_Msk       /*!< USB Bus Event Interrupt */
+#define USBD_INT_USB            USBD_INTEN_USBIEN_Msk       /*!< USB Event Interrupt */
+#define USBD_INT_FLDET          USBD_INTEN_VBDETIEN_Msk     /*!< USB VBUS Detection Interrupt */
+#define USBD_INT_WAKEUP         (USBD_INTEN_NEVWKIEN_Msk | USBD_INTEN_WKEN_Msk)     /*!< USB No-Event-Wake-Up Interrupt */
+
+#define USBD_INTSTS_WAKEUP      USBD_INTSTS_NEVWKIF_Msk     /*!< USB No-Event-Wake-Up Interrupt Status */
+#define USBD_INTSTS_FLDET       USBD_INTSTS_VBDETIF_Msk     /*!< USB Float Detect Interrupt Status */
+#define USBD_INTSTS_BUS         USBD_INTSTS_BUSIF_Msk       /*!< USB Bus Event Interrupt Status */
+#define USBD_INTSTS_USB         USBD_INTSTS_USBIF_Msk       /*!< USB Event Interrupt Status */
+#define USBD_INTSTS_SETUP       USBD_INTSTS_SETUP_Msk       /*!< USB Setup Event */
+#define USBD_INTSTS_EP0         USBD_INTSTS_EPEVT0_Msk      /*!< USB Endpoint 0 Event */
+#define USBD_INTSTS_EP1         USBD_INTSTS_EPEVT1_Msk      /*!< USB Endpoint 1 Event */
+#define USBD_INTSTS_EP2         USBD_INTSTS_EPEVT2_Msk      /*!< USB Endpoint 2 Event */
+#define USBD_INTSTS_EP3         USBD_INTSTS_EPEVT3_Msk      /*!< USB Endpoint 3 Event */
+#define USBD_INTSTS_EP4         USBD_INTSTS_EPEVT4_Msk      /*!< USB Endpoint 4 Event */
+#define USBD_INTSTS_EP5         USBD_INTSTS_EPEVT5_Msk      /*!< USB Endpoint 5 Event */
+#define USBD_INTSTS_EP6         USBD_INTSTS_EPEVT6_Msk      /*!< USB Endpoint 6 Event */
+#define USBD_INTSTS_EP7         USBD_INTSTS_EPEVT7_Msk      /*!< USB Endpoint 7 Event */
+
+#define USBD_STATE_USBRST       USBD_ATTR_USBRST_Msk        /*!< USB Bus Reset */
+#define USBD_STATE_SUSPEND      USBD_ATTR_SUSPEND_Msk       /*!< USB Bus Suspend */
+#define USBD_STATE_RESUME       USBD_ATTR_RESUME_Msk        /*!< USB Bus Resume */
+#define USBD_STATE_TIMEOUT      USBD_ATTR_TOUT_Msk          /*!< USB Bus Timeout */
+
+#define USBD_CFGP_SSTALL        USBD_CFGP_SSTALL_Msk        /*!< Set Stall */
+#define USBD_CFG_CSTALL         USBD_CFG_CSTALL_Msk         /*!< Clear Stall */
+
+#define USBD_CFG_EPMODE_DISABLE (0ul << USBD_CFG_STATE_Pos)/*!< Endpoint Disable */
+#define USBD_CFG_EPMODE_OUT     (1ul << USBD_CFG_STATE_Pos)/*!< Out Endpoint */
+#define USBD_CFG_EPMODE_IN      (2ul << USBD_CFG_STATE_Pos)/*!< In Endpoint */
+#define USBD_CFG_TYPE_ISO       (1ul << USBD_CFG_ISOCH_Pos) /*!< Isochronous */
+
+
+
+/*@}*/ /* end of group USBD_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Compare two input numbers and return maximum one.
+  *
+  * @param[in]  a   First number to be compared.
+  * @param[in]  b   Second number to be compared.
+  *
+  * @return     Maximum value between a and b.
+  *
+  * @details    If a > b, then return a. Otherwise, return b.
+  */
+#define Maximum(a,b)        ((a)>(b) ? (a) : (b))
+
+
+/**
+  * @brief      Compare two input numbers and return minimum one
+  *
+  * @param[in]  a   First number to be compared
+  * @param[in]  b   Second number to be compared
+  *
+  * @return     Minimum value between a and b
+  *
+  * @details    If a < b, then return a. Otherwise, return b.
+  */
+#define Minimum(a,b)        ((a)<(b) ? (a) : (b))
+
+
+/**
+  * @brief    Enable USB
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  To set USB ATTR control register to enable USB and PHY.
+  *
+  */
+#define USBD_ENABLE_USB()           ((uint32_t)(USBD->ATTR |= (USBD_USB_EN|USBD_PHY_EN)))
+
+/**
+  * @brief    Disable USB
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  To set USB ATTR control register to disable USB.
+  *
+  */
+#define USBD_DISABLE_USB()          ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN))
+
+/**
+  * @brief    Enable USB PHY
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  To set USB ATTR control register to enable USB PHY.
+  *
+  */
+#define USBD_ENABLE_PHY()           ((uint32_t)(USBD->ATTR |= USBD_PHY_EN))
+
+/**
+  * @brief    Disable USB PHY
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  To set USB ATTR control register to disable USB PHY.
+  *
+  */
+#define USBD_DISABLE_PHY()          ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN))
+
+/**
+  * @brief    Enable SE0. Force USB PHY transceiver to drive SE0.
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus.
+  *
+  */
+#define USBD_SET_SE0()              ((uint32_t)(USBD->SE0 |= USBD_DRVSE0))
+
+/**
+  * @brief    Disable SE0
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function.
+  *
+  */
+#define USBD_CLR_SE0()              ((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0))
+
+/**
+  * @brief       Set USB device address
+  *
+  * @param[in]   addr The USB device address.
+  *
+  * @return      None
+  *
+  * @details     Write USB device address to USB_FADDR register.
+  *
+  */
+#define USBD_SET_ADDR(addr)         (USBD->FADDR = (addr))
+
+/**
+  * @brief    Get USB device address
+  *
+  * @param    None
+  *
+  * @return   USB device address
+  *
+  * @details  Read USB_FADDR register to get USB device address.
+  *
+  */
+#define USBD_GET_ADDR()             ((uint32_t)(USBD->FADDR))
+
+/**
+  * @brief      Enable USB interrupt function
+  *
+  * @param[in]  intr The combination of the specified interrupt enable bits.
+  *             Each bit corresponds to a interrupt enable bit.
+  *             This parameter decides which interrupts will be enabled.
+  *             (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS)
+  *
+  * @return     None
+  *
+  * @details    Enable USB related interrupt functions specified by intr parameter.
+  *
+  */
+#define USBD_ENABLE_INT(intr)       (USBD->INTEN |= (intr))
+
+/**
+  * @brief    Get interrupt status
+  *
+  * @param    None
+  *
+  * @return   The value of USB_INTSTS register
+  *
+  * @details  Return all interrupt flags of USB_INTSTS register.
+  *
+  */
+#define USBD_GET_INT_FLAG()         ((uint32_t)(USBD->INTSTS))
+
+/**
+  * @brief      Clear USB interrupt flag
+  *
+  * @param[in]  flag The combination of the specified interrupt flags.
+  *             Each bit corresponds to a interrupt source.
+  *             This parameter decides which interrupt flags will be cleared.
+  *             (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB)
+  *
+  * @return     None
+  *
+  * @details    Clear USB related interrupt flags specified by flag parameter.
+  *
+  */
+#define USBD_CLR_INT_FLAG(flag)     (USBD->INTSTS = (flag))
+
+/**
+  * @brief    Get endpoint status
+  *
+  * @param    None
+  *
+  * @return   The value of USB_EPSTS register.
+  *
+  * @details  Return all endpoint status.
+  *
+  */
+#define USBD_GET_EP_FLAG()          ((uint32_t)(USBD->EPSTS))
+
+/**
+  * @brief    Get USB bus state
+  *
+  * @param    None
+  *
+  * @return   The value of USB_ATTR[3:0].
+  *           Bit 0 indicates USB bus reset status.
+  *           Bit 1 indicates USB bus suspend status.
+  *           Bit 2 indicates USB bus resume status.
+  *           Bit 3 indicates USB bus time-out status.
+  *
+  * @details  Return USB_ATTR[3:0] for USB bus events.
+  *
+  */
+#define USBD_GET_BUS_STATE()        ((uint32_t)(USBD->ATTR & 0xf))
+
+/**
+  * @brief    Check cable connection state
+  *
+  * @param    None
+  *
+  * @retval   0 USB cable is not attached.
+  * @retval   1 USB cable is attached.
+  *
+  * @details  Check the connection state by FLDET bit of USB_FLDET register.
+  *
+  */
+#define USBD_IS_ATTACHED()          ((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk))
+
+/**
+  * @brief      Stop USB transaction of the specified endpoint ID
+  *
+  * @param[in]  ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+  *
+  * @return     None
+  *
+  * @details    Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID.
+  *
+  */
+#define USBD_STOP_TRANSACTION(ep)   (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk)
+
+/**
+  * @brief      Set USB DATA1 PID for the specified endpoint ID
+  *
+  * @param[in]  ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+  *
+  * @return     None
+  *
+  * @details    Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction.
+  *             Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
+  *
+  */
+#define USBD_SET_DATA1(ep)          (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk)
+
+/**
+  * @brief      Set USB DATA0 PID for the specified endpoint ID
+  *
+  * @param[in]  ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+  *
+  * @return     None
+  *
+  * @details    Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction.
+  *             Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
+  *
+  */
+#define USBD_SET_DATA0(ep)          (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk))
+
+/**
+  * @brief      Set USB payload size (IN data)
+  *
+  * @param[in]  ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+  *
+  * @param[in]  size The transfer length.
+  *
+  * @return     None
+  *
+  * @details    This macro will write the transfer length to USB_MXPLDx register for IN data transaction.
+  *
+  */
+#define USBD_SET_PAYLOAD_LEN(ep, size)  (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))
+
+/**
+  * @brief      Get USB payload size (OUT data)
+  *
+  * @param[in]  ep The USB endpoint ID. M451 Series supports 8 endpoint ID. This parameter could be 0 ~ 7.
+  *
+  * @return     The value of USB_MXPLDx register.
+  *
+  * @details    Get the data length of OUT data transaction by reading USB_MXPLDx register.
+  *
+  */
+#define USBD_GET_PAYLOAD_LEN(ep)        ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))))
+
+/**
+  * @brief      Configure endpoint
+  *
+  * @param[in]  ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+  *
+  * @param[in]  config The USB configuration.
+  *
+  * @return     None
+  *
+  * @details    This macro will write config parameter to USB_CFGx register of specified endpoint ID.
+  *
+  */
+#define USBD_CONFIG_EP(ep, config)      (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))
+
+/**
+  * @brief      Set USB endpoint buffer
+  *
+  * @param[in]  ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+  *
+  * @param[in]  offset The SRAM offset.
+  *
+  * @return     None
+  *
+  * @details    This macro will set the SRAM offset for the specified endpoint ID.
+  *
+  */
+#define USBD_SET_EP_BUF_ADDR(ep, offset)    (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))
+
+/**
+  * @brief      Get the offset of the specified USB endpoint buffer
+  *
+  * @param[in]  ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+  *
+  * @return     The offset of the specified endpoint buffer.
+  *
+  * @details    This macro will return the SRAM offset of the specified endpoint ID.
+  *
+  */
+#define USBD_GET_EP_BUF_ADDR(ep)        ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))))
+
+/**
+  * @brief       Set USB endpoint stall state
+  *
+  * @param[in]   ep  The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+  *
+  * @return      None
+  *
+  * @details     Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
+  *
+  */
+#define USBD_SET_EP_STALL(ep)        (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk)
+
+/**
+  * @brief       Clear USB endpoint stall state
+  *
+  * @param[in]   ep  The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+  *
+  * @return      None
+  *
+  * @details     Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
+  */
+#define USBD_CLR_EP_STALL(ep)        (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk)
+
+/**
+  * @brief       Get USB endpoint stall state
+  *
+  * @param[in]   ep  The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+  *
+  * @retval      0      USB endpoint is not stalled.
+  * @retval      Others USB endpoint is stalled.
+  *
+  * @details     Get USB endpoint stall state of the specified endpoint ID.
+  *
+  */
+#define USBD_GET_EP_STALL(ep)        (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk)
+
+/**
+  * @brief      To support byte access between USB SRAM and system SRAM
+  *
+  * @param[in]  dest Destination pointer.
+  *
+  * @param[in]  src  Source pointer.
+  *
+  * @param[in]  size Byte count.
+  *
+  * @return     None
+  *
+  * @details    This function will copy the number of data specified by size and src parameters to the address specified by dest parameter.
+  *
+  */
+static __INLINE void USBD_MemCopy(uint8_t *dest, uint8_t *src, int32_t size)
+{
+    while(size--) *dest++ = *src++;
+}
+
+
+/**
+  * @brief       Set USB endpoint stall state
+  *
+  * @param[in]   epnum  USB endpoint number
+  *
+  * @return      None
+  *
+  * @details     Set USB endpoint stall state. Endpoint will respond STALL token automatically.
+  *
+  */
+static __INLINE void USBD_SetStall(uint8_t epnum)
+{
+    uint32_t u32CfgAddr;
+    uint32_t u32Cfg;
+    int i;
+
+    for(i = 0; i < USBD_MAX_EP; i++)
+    {
+        u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+        u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+        if((u32Cfg & 0xf) == epnum)
+        {
+            u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
+            u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+            *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL);
+            break;
+        }
+    }
+}
+
+/**
+  * @brief       Clear USB endpoint stall state
+  *
+  * @param[in]   epnum  USB endpoint number
+  *
+  * @return      None
+  *
+  * @details     Clear USB endpoint stall state. Endpoint will respond ACK/NAK token.
+  */
+static __INLINE void USBD_ClearStall(uint8_t epnum)
+{
+    uint32_t u32CfgAddr;
+    uint32_t u32Cfg;
+    int i;
+
+    for(i = 0; i < USBD_MAX_EP; i++)
+    {
+        u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+        u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+        if((u32Cfg & 0xf) == epnum)
+        {
+            u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
+            u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+            *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL);
+            break;
+        }
+    }
+}
+
+/**
+  * @brief       Get USB endpoint stall state
+  *
+  * @param[in]   epnum  USB endpoint number
+  *
+  * @retval      0      USB endpoint is not stalled.
+  * @retval      Others USB endpoint is stalled.
+  *
+  * @details     Get USB endpoint stall state.
+  *
+  */
+static __INLINE uint32_t USBD_GetStall(uint8_t epnum)
+{
+    uint32_t u32CfgAddr;
+    uint32_t u32Cfg;
+    int i;
+
+    for(i = 0; i < USBD_MAX_EP; i++)
+    {
+        u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+        u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+        if((u32Cfg & 0xf) == epnum)
+        {
+            u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
+            break;
+        }
+    }
+
+    return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL);
+}
+
+
+extern volatile uint8_t g_usbd_RemoteWakeupEn;
+
+
+typedef void (*VENDOR_REQ)(void);           /*!< Functional pointer type definition for Vendor class */
+typedef void (*CLASS_REQ)(void);            /*!< Functional pointer type declaration for USB class request callback handler */
+typedef void (*SET_INTERFACE_REQ)(void);    /*!< Functional pointer type declaration for USB set interface request callback handler */
+typedef void (*SET_CONFIG_CB)(void);       /*!< Functional pointer type declaration for USB set configuration request callback handler */
+
+
+/*--------------------------------------------------------------------*/
+void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
+void USBD_Start(void);
+void USBD_GetSetupPacket(uint8_t *buf);
+void USBD_ProcessSetupPacket(void);
+void USBD_StandardRequest(void);
+void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size);
+void USBD_CtrlIn(void);
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size);
+void USBD_CtrlOut(void);
+void USBD_SwReset(void);
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);
+void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback);
+void USBD_LockEpStall(uint32_t u32EpBitmap);
+
+/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USBD_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__USBD_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wdt.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wdt.c
new file mode 100644
index 00000000000..b8718b55293
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wdt.c
@@ -0,0 +1,71 @@
+/**************************************************************************//**
+ * @file     wdt.c
+ * @version  V3.00
+ * $Revision: 5 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series WDT driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup WDT_Driver WDT Driver
+  @{
+*/
+
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Initialize WDT and start counting
+  *
+  * @param[in]  u32TimeoutInterval  Time-out interval period of WDT module. Valid values are:
+  *                                 - \ref WDT_TIMEOUT_2POW4
+  *                                 - \ref WDT_TIMEOUT_2POW6
+  *                                 - \ref WDT_TIMEOUT_2POW8
+  *                                 - \ref WDT_TIMEOUT_2POW10
+  *                                 - \ref WDT_TIMEOUT_2POW12
+  *                                 - \ref WDT_TIMEOUT_2POW14
+  *                                 - \ref WDT_TIMEOUT_2POW16
+  *                                 - \ref WDT_TIMEOUT_2POW18
+  * @param[in]  u32ResetDelay       Configure WDT time-out reset delay period. Valid values are:
+  *                                 - \ref WDT_RESET_DELAY_1026CLK
+  *                                 - \ref WDT_RESET_DELAY_130CLK
+  *                                 - \ref WDT_RESET_DELAY_18CLK
+  *                                 - \ref WDT_RESET_DELAY_3CLK
+  * @param[in]  u32EnableReset      Enable WDT time-out reset system function. Valid values are TRUE and FALSE.
+  * @param[in]  u32EnableWakeup     Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE.
+  *
+  * @return     None
+  *
+  * @details    This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n
+  *             enable or disable WDT time-out reset system or wake-up system.
+  * @note       Please make sure that Register Write-Protection Function has been disabled before using this function.
+  */
+void WDT_Open(uint32_t u32TimeoutInterval,
+              uint32_t u32ResetDelay,
+              uint32_t u32EnableReset,
+              uint32_t u32EnableWakeup)
+{
+    WDT->ALTCTL = u32ResetDelay;
+
+    WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk |
+               (u32EnableReset << WDT_CTL_RSTEN_Pos) |
+               (u32EnableWakeup << WDT_CTL_WKEN_Pos);
+    return;
+}
+
+/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wdt.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wdt.h
new file mode 100644
index 00000000000..3c22721916d
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wdt.h
@@ -0,0 +1,201 @@
+/**************************************************************************//**
+ * @file     wdt.h
+ * @version  V3.00
+ * $Revision: 7 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series WDT driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WDT_H__
+#define __WDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup WDT_Driver WDT Driver
+  @{
+*/
+
+/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WDT Time-out Interval Period Constant Definitions                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_TIMEOUT_2POW4           (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks */
+#define WDT_TIMEOUT_2POW6           (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks */
+#define WDT_TIMEOUT_2POW8           (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks */
+#define WDT_TIMEOUT_2POW10          (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks */
+#define WDT_TIMEOUT_2POW12          (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks */
+#define WDT_TIMEOUT_2POW14          (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks */
+#define WDT_TIMEOUT_2POW16          (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks */
+#define WDT_TIMEOUT_2POW18          (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WDT  Reset Delay Period Constant Definitions                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_RESET_DELAY_1026CLK     (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks */
+#define WDT_RESET_DELAY_130CLK      (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks */
+#define WDT_RESET_DELAY_18CLK       (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks */
+#define WDT_RESET_DELAY_3CLK        (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks */
+
+/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear WDT Reset System Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears WDT time-out reset system flag.
+  */
+#define WDT_CLEAR_RESET_FLAG()          (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
+
+/**
+  * @brief      Clear WDT Time-out Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears WDT time-out interrupt flag.
+  */
+#define WDT_CLEAR_TIMEOUT_INT_FLAG()    (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
+
+/**
+  * @brief      Clear WDT Wake-up Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears WDT time-out wake-up system flag.
+  */
+#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
+
+/**
+  * @brief      Get WDT Time-out Reset Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WDT time-out reset system did not occur
+  * @retval     1   WDT time-out reset system occurred
+  *
+  * @details    This macro indicates system has been reset by WDT time-out reset or not.
+  */
+#define WDT_GET_RESET_FLAG()            ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1 : 0)
+
+/**
+  * @brief      Get WDT Time-out Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WDT time-out interrupt did not occur
+  * @retval     1   WDT time-out interrupt occurred
+  *
+  * @details    This macro indicates WDT time-out interrupt occurred or not.
+  */
+#define WDT_GET_TIMEOUT_INT_FLAG()      ((WDT->CTL & WDT_CTL_IF_Msk)? 1 : 0)
+
+/**
+  * @brief      Get WDT Time-out Wake-up Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WDT time-out interrupt does not cause CPU wake-up
+  * @retval     1   WDT time-out interrupt event cause CPU wake-up
+  *
+  * @details    This macro indicates WDT time-out interrupt event has waked up system or not.
+  */
+#define WDT_GET_TIMEOUT_WAKEUP_FLAG()   ((WDT->CTL & WDT_CTL_WKF_Msk)? 1 : 0)
+
+/**
+  * @brief      Reset WDT Counter
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to reset the internal 18-bit WDT up counter value.
+  * @note       If WDT is activated and time-out reset system function is enabled also, user should \n
+  *             reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n
+  *             reset system before the WDT time-out reset delay period expires.
+  */
+#define WDT_RESET_COUNTER()             (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)
+
+/**
+  * @brief      Stop WDT Counting
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will stop WDT counting and disable WDT module.
+  */
+static __INLINE void WDT_Close(void)
+{
+    WDT->CTL = 0;
+    return;
+}
+
+/**
+  * @brief      Enable WDT Time-out Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will enable the WDT time-out interrupt function.
+  */
+static __INLINE void WDT_EnableInt(void)
+{
+    WDT->CTL |= WDT_CTL_INTEN_Msk;
+    return;
+}
+
+/**
+  * @brief      Disable WDT Time-out Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will disable the WDT time-out interrupt function.
+  */
+static __INLINE void WDT_DisableInt(void)
+{
+    // Do not touch another write 1 clear bits
+    WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk);
+    return;
+}
+
+void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);
+
+/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__WDT_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wwdt.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wwdt.c
new file mode 100644
index 00000000000..439dbaf8cbb
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wwdt.c
@@ -0,0 +1,71 @@
+/**************************************************************************//**
+ * @file     wwdt.c
+ * @version  V3.00
+ * $Revision: 4 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series WWDT driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup WWDT_Driver WWDT Driver
+  @{
+*/
+
+/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Open WWDT and start counting
+  *
+  * @param[in]  u32PreScale     Pre-scale setting of WWDT counter. Valid values are:
+  *                             - \ref WWDT_PRESCALER_1
+  *                             - \ref WWDT_PRESCALER_2
+  *                             - \ref WWDT_PRESCALER_4
+  *                             - \ref WWDT_PRESCALER_8
+  *                             - \ref WWDT_PRESCALER_16
+  *                             - \ref WWDT_PRESCALER_32
+  *                             - \ref WWDT_PRESCALER_64
+  *                             - \ref WWDT_PRESCALER_128
+  *                             - \ref WWDT_PRESCALER_192
+  *                             - \ref WWDT_PRESCALER_256
+  *                             - \ref WWDT_PRESCALER_384
+  *                             - \ref WWDT_PRESCALER_512
+  *                             - \ref WWDT_PRESCALER_768
+  *                             - \ref WWDT_PRESCALER_1024
+  *                             - \ref WWDT_PRESCALER_1536
+  *                             - \ref WWDT_PRESCALER_2048
+  * @param[in]  u32CmpValue     Setting the window compared value. Valid values are between 0x0 to 0x3F.
+  * @param[in]  u32EnableInt    Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE.
+  *
+  * @return     None
+  *
+  * @details    This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value.
+  * @note       This WWDT_CTL register can be write only one time after chip is powered on or reset.
+  */
+void WWDT_Open(uint32_t u32PreScale,
+               uint32_t u32CmpValue,
+               uint32_t u32EnableInt)
+{
+    WWDT->CTL = u32PreScale |
+                (u32CmpValue << WWDT_CTL_CMPDAT_Pos) |
+                ((u32EnableInt == TRUE) ? WWDT_CTL_INTEN_Msk : 0) |
+                WWDT_CTL_WWDTEN_Msk;
+    return;
+}
+
+/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WWDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wwdt.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wwdt.h
new file mode 100644
index 00000000000..56e8a831e15
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wwdt.h
@@ -0,0 +1,148 @@
+/**************************************************************************//**
+ * @file     wwdt.h
+ * @version  V3.00
+ * $Revision: 7 $
+ * $Date: 15/08/11 10:26a $
+ * @brief    M451 series WWDT driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WWDT_H__
+#define __WWDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup WWDT_Driver WWDT Driver
+  @{
+*/
+
+/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WWDT Prescale Period Constant Definitions                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WWDT_PRESCALER_1        (0 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 1 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_2        (1 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 2 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_4        (2 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 4 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_8        (3 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 8 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_16       (4 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 16 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_32       (5 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 32 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_64       (6 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 64 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_128      (7 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 128 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_192      (8 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 192 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_256      (9 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 256 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_384      (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_512      (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_768      (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_1024     (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_1536     (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_2048     (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WWDT Reload Counter Keyword Constant Definitions                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WWDT_RELOAD_WORD        (0x00005AA5)                /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter */
+
+/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear WWDT Reset System Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear WWDT time-out reset system flag.
+  */
+#define WWDT_CLEAR_RESET_FLAG()     (WWDT->STATUS = (WWDT->STATUS & ~WWDT_STATUS_WWDTIF_Msk) | WWDT_STATUS_WWDTRF_Msk)
+
+/**
+  * @brief      Clear WWDT Compared Match Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear WWDT compared match interrupt flag.
+  */
+#define WWDT_CLEAR_INT_FLAG()       (WWDT->STATUS = (WWDT->STATUS & ~WWDT_STATUS_WWDTRF_Msk) | WWDT_STATUS_WWDTIF_Msk)
+
+/**
+  * @brief      Get WWDT Reset System Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WWDT time-out reset system did not occur
+  * @retval     1   WWDT time-out reset system occurred
+  *
+  * @details    This macro is used to indicate system has been reset by WWDT time-out reset or not.
+  */
+#define WWDT_GET_RESET_FLAG()       ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0)
+
+/**
+  * @brief      Get WWDT Compared Match Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WWDT compare match interrupt did not occur
+  * @retval     1   WWDT compare match interrupt occurred
+  *
+  * @details    This macro is used to indicate WWDT counter value matches CMPDAT value or not.
+  */
+#define WWDT_GET_INT_FLAG()         ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0)
+
+/**
+  * @brief      Get WWDT Counter
+  *
+  * @param      None
+  *
+  * @return     WWDT Counter Value
+  *
+  * @details    This macro reflects the current WWDT counter value.
+  */
+#define WWDT_GET_COUNTER()          (WWDT->CNT)
+
+/**
+  * @brief      Reload WWDT Counter
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to reload the WWDT counter value to 0x3F.
+  * @note       User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n
+  *             between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n
+  *             WWDT reset signal will generate immediately to reset system.
+  */
+#define WWDT_RELOAD_COUNTER()       (WWDT->RLDCNT = WWDT_RELOAD_WORD)
+
+void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
+
+/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WWDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__WWDT_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_MICRO/M453.sct b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_MICRO/M453.sct
new file mode 100644
index 00000000000..0cb3c103deb
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_MICRO/M453.sct
@@ -0,0 +1,28 @@
+
+LR_IROM1 0x00000000 {
+  ER_IROM1 0x00000000 {  ; load address = execution address
+   *(RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  
+  ;UVISOR AlignExpr(+0, 16) {  ; 16 byte-aligned
+  ;  uvisor-lib.a (+RW +ZI)
+  ;}
+  
+  ARM_LIB_STACK 0x20000000 EMPTY 0x1000 {
+  }
+  
+  ER_IRAMVEC 0x20001000 EMPTY (4*(16 + 64)) {  ; Reserve for vectors
+  }
+  
+  RW_IRAM1 AlignExpr(+0, 16) {  ; 16 byte-aligned
+   .ANY (+RW +ZI)
+  }
+  
+  ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x8000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
+  }
+}
+ScatterAssert(LoadLimit(LR_IROM1) <= 0x00040000)    ; 256 KB APROM
+ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20008000)   ; 32 KB SRAM
+
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_MICRO/sys.cpp b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 00000000000..9060f11039a
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
+extern char Image$$ARM_LIB_HEAP$$Base[];
+extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+
+    struct __initial_stackheap r;
+    r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
+    r.heap_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_STD/M453.sct b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_STD/M453.sct
new file mode 100644
index 00000000000..0cb3c103deb
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_STD/M453.sct
@@ -0,0 +1,28 @@
+
+LR_IROM1 0x00000000 {
+  ER_IROM1 0x00000000 {  ; load address = execution address
+   *(RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  
+  ;UVISOR AlignExpr(+0, 16) {  ; 16 byte-aligned
+  ;  uvisor-lib.a (+RW +ZI)
+  ;}
+  
+  ARM_LIB_STACK 0x20000000 EMPTY 0x1000 {
+  }
+  
+  ER_IRAMVEC 0x20001000 EMPTY (4*(16 + 64)) {  ; Reserve for vectors
+  }
+  
+  RW_IRAM1 AlignExpr(+0, 16) {  ; 16 byte-aligned
+   .ANY (+RW +ZI)
+  }
+  
+  ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x8000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
+  }
+}
+ScatterAssert(LoadLimit(LR_IROM1) <= 0x00040000)    ; 256 KB APROM
+ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20008000)   ; 32 KB SRAM
+
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_STD/sys.cpp b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 00000000000..9060f11039a
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
+extern char Image$$ARM_LIB_HEAP$$Base[];
+extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+
+    struct __initial_stackheap r;
+    r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
+    r.heap_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/M453.ld b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/M453.ld
new file mode 100644
index 00000000000..a29952feb92
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/M453.ld
@@ -0,0 +1,255 @@
+/*
+ * Nuvoton M453 GCC linker script file
+ */
+
+StackSize = 0x1000;
+
+MEMORY
+{
+  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400
+  FLASH (rx)            : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400
+  RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00008000 - 0x00000000
+}
+
+/**
+ * Must match cmsis_nvic.h
+ */
+__vector_size = 4 * (16 + 64);
+
+ 
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .isr_vector :
+    {
+        __vector_table = .;
+        KEEP(*(.vector_table))
+         . = ALIGN(4);
+    } > VECTORS
+
+    /* ensure that uvisor bss is at the beginning of memory */
+    .uvisor.bss (NOLOAD):
+    {
+        . = ALIGN(32);
+        __uvisor_bss_start = .;
+
+        /* protected uvisor main bss */
+        . = ALIGN(32);
+        __uvisor_bss_main_start = .;
+        KEEP(*(.keep.uvisor.bss.main))
+        . = ALIGN(32);
+        __uvisor_bss_main_end = .;
+
+        /* protected uvisor secure boxes bss */
+        . = ALIGN(32);
+        __uvisor_bss_boxes_start = .;
+        KEEP(*(.keep.uvisor.bss.boxes))
+        . = ALIGN(32);
+        __uvisor_bss_boxes_end = .;
+
+        /* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. */
+        . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));
+        __uvisor_bss_end = .;
+    } > RAM_INTERN
+
+    .text :
+    {
+        /* uVisor code and data */
+        . = ALIGN(4);
+        __uvisor_main_start = .;
+        *(.uvisor.main)
+        __uvisor_main_end = .;
+
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    .ARM.exidx :
+    {
+       __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+       __exidx_end = .;
+    } > FLASH
+
+    /* .stack section doesn't contains any symbols. It is only
+     * used for linker to reserve space for the main stack section
+     * WARNING: .stack should come immediately after the last secure memory
+     * section.  This provides stack overflow detection. */
+    .stack (NOLOAD):
+    {
+        __StackLimit = .;
+        *(.stack*);
+        . += StackSize - (. - __StackLimit);
+    } > RAM_INTERN
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ADDR(.stack) + SIZEOF(.stack);
+    __StackLimit = ADDR(.stack);
+    PROVIDE(__stack = __StackTop);
+
+    /* Relocate vector table in SRAM */
+    .isr_vector.reloc (NOLOAD) :
+    {
+        . = ALIGN(1 << LOG2CEIL(__vector_size));
+        PROVIDE(__start_vector_table__ = .);
+        . += __vector_size;
+        PROVIDE(__end_vector_table__ = .);
+    } > RAM_INTERN
+    
+    .data :
+    {
+        PROVIDE( __etext = LOADADDR(.data) );
+
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        /* All data end */
+        . = ALIGN(32);
+        __data_end__ = .;
+
+    } >RAM_INTERN AT>FLASH
+
+    /* uvisor configuration data */
+    .uvisor.secure :
+    {
+        . = ALIGN(32);
+        __uvisor_secure_start = .;
+
+        /* uvisor secure boxes configuration tables */
+        . = ALIGN(32);
+        __uvisor_cfgtbl_start = .;
+        KEEP(*(.keep.uvisor.cfgtbl))
+        . = ALIGN(32);
+        __uvisor_cfgtbl_end = .;
+
+        /* pointers to uvisor secure boxes configuration tables */
+        /* note: no further alignment here, we need to have the exact list of pointers */
+        __uvisor_cfgtbl_ptr_start = .;
+        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
+        KEEP(*(.keep.uvisor.cfgtbl_ptr))
+        __uvisor_cfgtbl_ptr_end = .;
+
+        /* the following symbols are kept for backward compatibility and will be soon
+         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
+         * will need to use uVisor 0.8.x or above, or the security assertions will halt the
+         * system */
+        /************************/
+        __uvisor_data_src = .;
+        __uvisor_data_start = .;
+        __uvisor_data_end = .;
+        /************************/
+
+        . = ALIGN(32);
+        __uvisor_secure_end = .;
+    } >FLASH
+
+    .uninitialized (NOLOAD):
+    {
+        . = ALIGN(32);
+        __uninitialized_start = .;
+        *(.uninitialized)
+        KEEP(*(.keep.uninitialized))
+        . = ALIGN(32);
+        __uninitialized_end = .;
+    } > RAM_INTERN
+
+    .bss (NOLOAD):
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM_INTERN
+
+    .heap (NOLOAD):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*);
+        . += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
+        __HeapLimit = .;
+    } > RAM_INTERN
+    PROVIDE(__heap_size = SIZEOF(.heap));
+    PROVIDE(__mbed_sbrk_start = ADDR(.heap));
+    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
+    
+    /* Provide physical memory boundaries for uVisor. */
+    __uvisor_flash_start = ORIGIN(VECTORS);
+    __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
+    __uvisor_sram_start = ORIGIN(RAM_INTERN);
+    __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
+}
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c
new file mode 100644
index 00000000000..6e2642a5f68
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c
@@ -0,0 +1,35 @@
+/******************************************************************************
+ * @file     startup_NUC472_442.c
+ * @version  V0.10
+ * $Revision: 11 $
+ * $Date: 15/09/02 10:02a $
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Source File for NUC472/442 MCU
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M451Series.h"
+#include <errno.h>
+
+extern uint32_t __mbed_sbrk_start;
+extern uint32_t __mbed_krbs_start;
+
+// NOTE: The implementation of _sbrk (in common/retarget.cpp) for GCC_ARM requires one-region model for heap and stack, which doesn't
+//       meet the layout of e.g. Nu-mbed-NUC472 board where heap is located on external SRAM. 
+//       Because the symbol is not weak and cannot be overwritten, wrap calls to it by hooking command line linker with '-Wl,--wrap,_sbrk'.
+void *__wrap__sbrk(int incr)
+{
+    static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start;
+    uint32_t heap_ind_old = heap_ind;
+    uint32_t heap_ind_new = (heap_ind_old + incr + 7) & ~7;
+    
+    if (heap_ind_new > &__mbed_krbs_start) {
+        errno = ENOMEM;
+        return (void *) -1;
+    } 
+    
+    heap_ind = heap_ind_new;
+    
+    return (void *) heap_ind_old;
+}
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_IAR/M453.icf b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_IAR/M453.icf
new file mode 100644
index 00000000000..7411796dcf0
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_IAR/M453.icf
@@ -0,0 +1,36 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x00040000;
+define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_IRAM_end__   = 0x20008000;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x4000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region IRAM_region  = mem:[from __ICFEDIT_region_IRAM_start__  to __ICFEDIT_region_IRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
+define block IRAMVEC   with alignment = 1024, size = 4 * (16 + 64)          { };
+
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place at start of IRAM_region   { block CSTACK };
+place in IRAM_region   { block IRAMVEC };
+place in IRAM_region   { readwrite };
+place in IRAM_region   { block HEAP };
\ No newline at end of file
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/startup_M451Series.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/startup_M451Series.c
new file mode 100644
index 00000000000..d73e4eca81d
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/startup_M451Series.c
@@ -0,0 +1,326 @@
+/******************************************************************************
+ * @file     startup_M451Series.c
+ * @version  V0.10
+ * $Revision: 11 $
+ * $Date: 15/09/02 10:02a $
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M451 Series MCU
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M451Series.h"
+
+/* Macro Definitions */
+#if defined(__CC_ARM)
+#define WEAK            __attribute__ ((weak))
+#define ALIAS(f)        __attribute__ ((weak, alias(#f)))
+
+#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
+void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
+
+#elif defined(__ICCARM__)
+//#define STRINGIFY(x) #x
+//#define _STRINGIFY(x) STRINGIFY(x)
+#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
+void FUN(void);                         \
+_Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)))
+#define _WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) weak __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)
+#define __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) FUN##=##FUN_ALIAS
+
+#elif defined(__GNUC__)
+#define WEAK            __attribute__ ((weak))
+#define ALIAS(f)        __attribute__ ((weak, alias(#f)))
+
+#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
+void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
+
+#endif
+
+
+/* Initialize segments */
+#if defined(__CC_ARM)
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+extern void __main(void);
+#elif defined(__ICCARM__)
+void __iar_program_start(void);
+#elif defined(__GNUC__)
+extern uint32_t __StackTop;
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+
+extern void uvisor_init(void);
+//#if defined(TOOLCHAIN_GCC_ARM)
+//extern void _start(void);
+//#endif
+extern void software_init_hook(void) __attribute__((weak));
+extern void __libc_init_array(void);
+extern int main(void);
+#endif
+
+/* Default empty handler */
+void Default_Handler(void);
+
+/* Reset handler */
+void Reset_Handler(void);
+
+/* Cortex-M4 core handlers */
+WEAK_ALIAS_FUNC(NMI_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(HardFault_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(MemManage_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(BusFault_Handler , Default_Handler)
+WEAK_ALIAS_FUNC(UsageFault_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(SVC_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(DebugMon_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(PendSV_Handler, Default_Handler)
+WEAK_ALIAS_FUNC(SysTick_Handler, Default_Handler)
+
+/* Peripherals handlers */
+WEAK_ALIAS_FUNC(BOD_IRQHandler, Default_Handler)        // 0: Brown Out detection
+WEAK_ALIAS_FUNC(IRC_IRQHandler, Default_Handler)        // 1: Internal RC
+WEAK_ALIAS_FUNC(PWRWU_IRQHandler, Default_Handler)      // 2: Power down wake up 
+WEAK_ALIAS_FUNC(RAMPE_IRQHandler, Default_Handler)      // 3: RAM parity error
+WEAK_ALIAS_FUNC(CLKFAIL_IRQHandler, Default_Handler)    // 4: Clock detection fail
+                                                        // 5: Reserved
+WEAK_ALIAS_FUNC(RTC_IRQHandler, Default_Handler)        // 6: Real Time Clock 
+WEAK_ALIAS_FUNC(TAMPER_IRQHandler, Default_Handler)     // 7: Tamper detection
+WEAK_ALIAS_FUNC(WDT_IRQHandler, Default_Handler)        // 8: Watchdog timer
+WEAK_ALIAS_FUNC(WWDT_IRQHandler, Default_Handler)       // 9: Window watchdog timer
+WEAK_ALIAS_FUNC(EINT0_IRQHandler, Default_Handler)      // 10: External Input 0
+WEAK_ALIAS_FUNC(EINT1_IRQHandler, Default_Handler)      // 11: External Input 1
+WEAK_ALIAS_FUNC(EINT2_IRQHandler, Default_Handler)      // 12: External Input 2
+WEAK_ALIAS_FUNC(EINT3_IRQHandler, Default_Handler)      // 13: External Input 3
+WEAK_ALIAS_FUNC(EINT4_IRQHandler, Default_Handler)      // 14: External Input 4
+WEAK_ALIAS_FUNC(EINT5_IRQHandler, Default_Handler)      // 15: External Input 5
+WEAK_ALIAS_FUNC(GPA_IRQHandler, Default_Handler)        // 16: GPIO Port A
+WEAK_ALIAS_FUNC(GPB_IRQHandler, Default_Handler)        // 17: GPIO Port B
+WEAK_ALIAS_FUNC(GPC_IRQHandler, Default_Handler)        // 18: GPIO Port C
+WEAK_ALIAS_FUNC(GPD_IRQHandler, Default_Handler)        // 19: GPIO Port D
+WEAK_ALIAS_FUNC(GPE_IRQHandler, Default_Handler)        // 20: GPIO Port E
+WEAK_ALIAS_FUNC(GPF_IRQHandler, Default_Handler)        // 21: GPIO Port F
+WEAK_ALIAS_FUNC(SPI0_IRQHandler, Default_Handler)       // 22: SPI0
+WEAK_ALIAS_FUNC(SPI1_IRQHandler, Default_Handler)       // 23: SPI1
+WEAK_ALIAS_FUNC(BRAKE0_IRQHandler, Default_Handler)     // 24: 
+WEAK_ALIAS_FUNC(PWM0P0_IRQHandler, Default_Handler)     // 25: 
+WEAK_ALIAS_FUNC(PWM0P1_IRQHandler, Default_Handler)     // 26: 
+WEAK_ALIAS_FUNC(PWM0P2_IRQHandler, Default_Handler)     // 27: 
+WEAK_ALIAS_FUNC(BRAKE1_IRQHandler, Default_Handler)     // 28: 
+WEAK_ALIAS_FUNC(PWM1P0_IRQHandler, Default_Handler)     // 29: 
+WEAK_ALIAS_FUNC(PWM1P1_IRQHandler, Default_Handler)     // 30: 
+WEAK_ALIAS_FUNC(PWM1P2_IRQHandler, Default_Handler)     // 31: 
+WEAK_ALIAS_FUNC(TMR0_IRQHandler, Default_Handler)       // 32: Timer 0
+WEAK_ALIAS_FUNC(TMR1_IRQHandler, Default_Handler)       // 33: Timer 1
+WEAK_ALIAS_FUNC(TMR2_IRQHandler, Default_Handler)       // 34: Timer 2
+WEAK_ALIAS_FUNC(TMR3_IRQHandler, Default_Handler)       // 35: Timer 3
+WEAK_ALIAS_FUNC(UART0_IRQHandler, Default_Handler)      // 36: UART0
+WEAK_ALIAS_FUNC(UART1_IRQHandler, Default_Handler)      // 37: UART1
+WEAK_ALIAS_FUNC(I2C0_IRQHandler, Default_Handler)       // 38: I2C0
+WEAK_ALIAS_FUNC(I2C1_IRQHandler, Default_Handler)       // 39: I2C1
+WEAK_ALIAS_FUNC(PDMA_IRQHandler, Default_Handler)       // 40: Peripheral DMA
+WEAK_ALIAS_FUNC(DAC_IRQHandler, Default_Handler)        // 41: DAC
+WEAK_ALIAS_FUNC(ADC00_IRQHandler, Default_Handler)      // 42: ADC0 interrupt source 0
+WEAK_ALIAS_FUNC(ADC01_IRQHandler, Default_Handler)      // 43: ADC0 interrupt source 1
+WEAK_ALIAS_FUNC(ACMP01_IRQHandler, Default_Handler)     // 44: ACMP0 and ACMP1
+                                                        // 45: Reserved
+WEAK_ALIAS_FUNC(ADC02_IRQHandler, Default_Handler)      // 46: ADC0 interrupt source 2
+WEAK_ALIAS_FUNC(ADC03_IRQHandler, Default_Handler)      // 47: ADC0 interrupt source 3
+WEAK_ALIAS_FUNC(UART2_IRQHandler, Default_Handler)      // 48: UART2
+WEAK_ALIAS_FUNC(UART3_IRQHandler, Default_Handler)      // 49: UART3
+                                                        // 50: Reserved
+WEAK_ALIAS_FUNC(SPI2_IRQHandler, Default_Handler)       // 51: SPI2
+                                                        // 52: Reserved
+WEAK_ALIAS_FUNC(USBD_IRQHandler, Default_Handler)       // 53: USB device
+WEAK_ALIAS_FUNC(USBH_IRQHandler, Default_Handler)       // 54: USB host
+WEAK_ALIAS_FUNC(USBOTG_IRQHandler, Default_Handler)     // 55: USB OTG
+WEAK_ALIAS_FUNC(CAN0_IRQHandler, Default_Handler)       // 56: CAN0
+                                                        // 57: Reserved
+WEAK_ALIAS_FUNC(SC0_IRQHandler, Default_Handler)        // 58: 
+                                                        // 59: Reserved.
+                                                        // 60: 
+                                                        // 61: 
+                                                        // 62:
+WEAK_ALIAS_FUNC(TK_IRQHandler, Default_Handler)         // 63:
+
+/* Vector table */
+#if defined(__CC_ARM)
+__attribute__ ((section("RESET")))
+const uint32_t __vector_handlers[] = {
+#elif defined(__ICCARM__)
+extern uint32_t CSTACK$$Limit;
+const uint32_t __vector_table[] @ ".intvec" = {
+#elif defined(__GNUC__)
+__attribute__ ((section(".vector_table")))
+const uint32_t __vector_handlers[] = {
+#endif
+
+    /* Configure Initial Stack Pointer, using linker-generated symbols */
+#if defined(__CC_ARM)
+    &Image$$ARM_LIB_STACK$$ZI$$Limit,
+#elif defined(__ICCARM__)
+    //(uint32_t) __sfe("CSTACK"),
+    (uint32_t) &CSTACK$$Limit,
+#elif defined(__GNUC__)
+    &__StackTop,
+#endif
+
+    (uint32_t) Reset_Handler,           // Reset Handler
+    (uint32_t) NMI_Handler,             // NMI Handler
+    (uint32_t) HardFault_Handler,       // Hard Fault Handler
+    (uint32_t) MemManage_Handler,       // MPU Fault Handler
+    (uint32_t) BusFault_Handler,        // Bus Fault Handler
+    (uint32_t) UsageFault_Handler,      // Usage Fault Handler
+    0,                                  // Reserved
+    0,                                  // Reserved
+    0,                                  // Reserved
+    0,                                  // Reserved
+    (uint32_t) SVC_Handler,             // SVCall Handler
+    (uint32_t) DebugMon_Handler,        // Debug Monitor Handler
+    0,                                  // Reserved
+    (uint32_t) PendSV_Handler,          // PendSV Handler
+    (uint32_t) SysTick_Handler,         // SysTick Handler
+
+    /* External Interrupts */
+    (uint32_t) BOD_IRQHandler,          // 0: Brown Out detection
+    (uint32_t) IRC_IRQHandler,          // 1: Internal RC
+    (uint32_t) PWRWU_IRQHandler,        // 2: Power down wake up 
+    (uint32_t) RAMPE_IRQHandler,        // 3: RAM parity error
+    (uint32_t) CLKFAIL_IRQHandler,      // 4: Clock detection fail
+    (uint32_t) Default_Handler,         // 5: Reserved
+    (uint32_t) RTC_IRQHandler,          // 6: Real Time Clock 
+    (uint32_t) TAMPER_IRQHandler,       // 7: Tamper detection
+    (uint32_t) WDT_IRQHandler,          // 8: Watchdog timer
+    (uint32_t) WWDT_IRQHandler,         // 9: Window watchdog timer
+    (uint32_t) EINT0_IRQHandler,        // 10: External Input 0
+    (uint32_t) EINT1_IRQHandler,        // 11: External Input 1
+    (uint32_t) EINT2_IRQHandler,        // 12: External Input 2
+    (uint32_t) EINT3_IRQHandler,        // 13: External Input 3
+    (uint32_t) EINT4_IRQHandler,        // 14: External Input 4
+    (uint32_t) EINT5_IRQHandler,        // 15: External Input 5
+    (uint32_t) GPA_IRQHandler,          // 16: GPIO Port A
+    (uint32_t) GPB_IRQHandler,          // 17: GPIO Port B
+    (uint32_t) GPC_IRQHandler,          // 18: GPIO Port C
+    (uint32_t) GPD_IRQHandler,          // 19: GPIO Port D
+    (uint32_t) GPE_IRQHandler,          // 20: GPIO Port E
+    (uint32_t) GPF_IRQHandler,          // 21: GPIO Port F
+    (uint32_t) SPI0_IRQHandler,         // 22: SPI0
+    (uint32_t) SPI1_IRQHandler,         // 23: SPI1
+    (uint32_t) BRAKE0_IRQHandler,       // 24: 
+    (uint32_t) PWM0P0_IRQHandler,       // 25: 
+    (uint32_t) PWM0P1_IRQHandler,       // 26: 
+    (uint32_t) PWM0P2_IRQHandler,       // 27: 
+    (uint32_t) BRAKE1_IRQHandler,       // 28: 
+    (uint32_t) PWM1P0_IRQHandler,       // 29: 
+    (uint32_t) PWM1P1_IRQHandler,       // 30: 
+    (uint32_t) PWM1P2_IRQHandler,       // 31: 
+    (uint32_t) TMR0_IRQHandler,         // 32: Timer 0
+    (uint32_t) TMR1_IRQHandler,         // 33: Timer 1
+    (uint32_t) TMR2_IRQHandler,         // 34: Timer 2
+    (uint32_t) TMR3_IRQHandler,         // 35: Timer 3
+    (uint32_t) UART0_IRQHandler,        // 36: UART0
+    (uint32_t) UART1_IRQHandler,        // 37: UART1
+    (uint32_t) I2C0_IRQHandler,         // 38: I2C0
+    (uint32_t) I2C1_IRQHandler,         // 39: I2C1
+    (uint32_t) PDMA_IRQHandler,         // 40: Peripheral DMA
+    (uint32_t) DAC_IRQHandler,          // 41: DAC
+    (uint32_t) ADC00_IRQHandler,        // 42: ADC0 interrupt source 0
+    (uint32_t) ADC01_IRQHandler,        // 43: ADC0 interrupt source 1
+    (uint32_t) ACMP01_IRQHandler,       // 44: ACMP0 and ACMP1
+    (uint32_t) Default_Handler,         // 45: Reserved
+    (uint32_t) ADC02_IRQHandler,        // 46: ADC0 interrupt source 2
+    (uint32_t) ADC03_IRQHandler,        // 47: ADC0 interrupt source 3
+    (uint32_t) UART2_IRQHandler,        // 48: UART2
+    (uint32_t) UART3_IRQHandler,        // 49: UART3
+    (uint32_t) Default_Handler,         // 50: Reserved
+    (uint32_t) SPI2_IRQHandler,         // 51: SPI2
+    (uint32_t) Default_Handler,         // 52: Reserved
+    (uint32_t) USBD_IRQHandler,         // 53: USB device
+    (uint32_t) USBH_IRQHandler,         // 54: USB host
+    (uint32_t) USBOTG_IRQHandler,       // 55: USB OTG
+    (uint32_t) CAN0_IRQHandler,         // 56: CAN0
+    (uint32_t) Default_Handler,         // 57: Reserved
+    (uint32_t) SC0_IRQHandler,          // 58: 
+    (uint32_t) Default_Handler,         // 59: Reserved.
+    (uint32_t) Default_Handler,         // 60: 
+    (uint32_t) Default_Handler,         // 61: 
+    (uint32_t) Default_Handler,         // 62:
+    (uint32_t) TK_IRQHandler,           // 63:
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ */
+void Reset_Handler(void)
+{
+    /* Disable register write-protection function */
+    SYS_UnlockReg();
+    
+    /* Disable Power-on Reset function */
+    SYS_DISABLE_POR();
+    
+    /* HXT Crystal Type Select: INV */
+    CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
+    
+    /* Enable register write-protection function */
+    SYS_LockReg();
+    
+    /**
+     * Because EBI (external SRAM) init is done in SystemInit(), SystemInit() must be called at the very start.
+     */
+    SystemInit();
+    
+#if defined(__CC_ARM)
+    __main();
+    
+#elif defined(__ICCARM__)
+    __iar_program_start();
+
+#elif defined(__GNUC__)
+    uint32_t *src_ind = (uint32_t *) &__etext;
+    uint32_t *dst_ind = (uint32_t *) &__data_start__;
+    uint32_t *dst_end = (uint32_t *) &__data_end__;
+
+    /* Move .data section from ROM to RAM */
+    if (src_ind != dst_ind) {
+        for (; dst_ind < dst_end;) {
+            *dst_ind ++ = *src_ind ++;
+        }
+    }
+   
+    /* Initialize .bss section to zero */
+    dst_ind = (uint32_t *) &__bss_start__;
+    dst_end = (uint32_t *) &__bss_end__;
+    if (dst_ind != dst_end) {
+        for (; dst_ind < dst_end;) {
+            *dst_ind ++ = 0;
+        }
+    }
+    
+    //uvisor_init();
+    
+    if (software_init_hook) {
+        /**
+         * Give control to the RTOS via software_init_hook() which will also call __libc_init_array().
+         * Assume software_init_hook() is defined in libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h.
+         */
+        software_init_hook();
+    }
+    else {
+        __libc_init_array();
+        main();
+    }
+#endif
+
+    /* Infinite loop */
+    while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Default_Handler(void)
+{
+    while (1);
+}
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis.h
new file mode 100644
index 00000000000..c183fd04cd8
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis.h
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "M451Series.h"
+#include "cmsis_nvic.h"
+
+// Support linker-generated symbol as start of relocated vector table.
+#if defined(__CC_ARM)
+extern uint32_t Image$$ER_IRAMVEC$$ZI$$Base;
+#elif defined(__ICCARM__)
+
+#elif defined(__GNUC__)
+extern uint32_t __start_vector_table__;
+#endif
+
+
+#endif
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.c
new file mode 100644
index 00000000000..13e150669a0
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.c
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis_nvic.h"
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t *vectors = (uint32_t *) SCB->VTOR;
+    uint32_t i;
+
+    /* Copy and switch to dynamic vectors if the first time called */
+    if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = (uint32_t *) NVIC_FLASH_VECTOR_ADDRESS;
+        vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS;
+        for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t) NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t *vectors = (uint32_t *) SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.h
new file mode 100644
index 00000000000..128cfcf2138
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.h
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_USER_IRQ_OFFSET 16
+#define NVIC_USER_IRQ_NUMBER 64
+#define NVIC_NUM_VECTORS     (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
+
+#if defined(__CC_ARM)
+#   define NVIC_RAM_VECTOR_ADDRESS  &Image$$ER_IRAMVEC$$ZI$$Base
+#elif defined(__ICCARM__)
+#   pragma section = "IRAMVEC"
+#   define NVIC_RAM_VECTOR_ADDRESS  ((uint32_t) __section_begin("IRAMVEC"))
+#elif defined(__GNUC__)
+#   define NVIC_RAM_VECTOR_ADDRESS  &__start_vector_table__
+#endif
+
+
+#define NVIC_FLASH_VECTOR_ADDRESS 0
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Set the ISR for IRQn
+ *
+ * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM
+ * the first time this function is called
+ * @param[in] IRQn   The Interrupt Request number for which a vector will be registered
+ * @param[in] vector The ISR vector to register for IRQn
+ */
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+
+/** Get the ISR registered for IRQn
+ *
+ * Reads the Interrupt Service Routine currently registered for IRQn
+ * @param[in] IRQn   The Interrupt Request number the vector of which will be read
+ * @return           Returns the ISR registered for IRQn
+ */
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/system_M451Series.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/system_M451Series.c
new file mode 100644
index 00000000000..df23aec5685
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/system_M451Series.c
@@ -0,0 +1,111 @@
+/******************************************************************************
+ * @file     system_M451Series.c
+ * @version  V0.10
+ * $Revision: 11 $
+ * $Date: 15/09/02 10:02a $
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M451 Series MCU
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M451Series.h"
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock  = __SYSTEM_CLOCK;    /*!< System Clock Frequency (Core Clock)*/
+uint32_t CyclesPerUs      = (__HSI / 1000000); /* Cycles per micro second */
+uint32_t PllClock         = __HSI;             /*!< PLL Output Clock Frequency         */
+uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC};
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate(void)             /* Get Core Clock Frequency      */
+{
+#if 1
+    uint32_t u32Freq, u32ClkSrc;
+    uint32_t u32HclkDiv;
+
+    /* Update PLL Clock */
+    PllClock = CLK_GetPLLClockFreq();
+
+    u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
+
+    if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
+    {
+        /* Use PLL clock */
+        u32Freq = PllClock;
+    }
+    else
+    {
+        /* Use the clock sources directly */
+        u32Freq = gau32ClkSrcTbl[u32ClkSrc];
+    }
+
+    u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
+
+    /* Update System Core Clock */
+    SystemCoreClock = u32Freq / u32HclkDiv;
+
+
+    //if(SystemCoreClock == 0)
+    //    __BKPT(0);
+
+    CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
+#endif
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  None
+ * @return None
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit(void)
+{
+    /* ToDo: add code to initialize the system
+             do not use global variables because this function is called before
+             reaching pre-main. RW section maybe overwritten afterwards.          */
+    
+    SYS_UnlockReg();
+    /* One-time POR18 */
+    if((SYS->PDID >> 12) == 0x945)
+    {
+        M32(GCR_BASE+0x14) |= BIT7;
+    }
+    /* Force to use INV type with HXT */
+    CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
+    SYS_LockReg();
+
+
+#if 0
+    // NOTE: C-runtime not initialized yet. Ensure no static memory (global variable) are accessed in this function.
+    nu_ebi_init();
+#endif
+
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10 * 2) |               /* set CP10 Full Access */
+                   (3UL << 11 * 2));               /* set CP11 Full Access */
+#endif
+
+}
+
+#if 0
+void nu_ebi_init(void)
+{
+    // TO BE CONTINUED
+}
+#endif
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/system_M451Series.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/system_M451Series.h
new file mode 100644
index 00000000000..edb80e509a3
--- /dev/null
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/system_M451Series.h
@@ -0,0 +1,75 @@
+/******************************************************************************
+ * @file     system_M451Series.h
+ * @version  V0.10
+ * $Revision: 7 $
+ * $Date: 15/09/02 10:02a $
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M451 Series MCU
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __SYSTEM_M451SERIES_H__
+#define __SYSTEM_M451SERIES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macro Definition                                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#ifndef DEBUG_PORT
+# define DEBUG_PORT      UART0       /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+
+#define __HSI       (12000000UL)    /*!< PLL default output is 72MHz */
+#define __HXT       (12000000UL)    /*!< External Crystal Clock Frequency     */
+#define __LXT       (32768UL)       /*!< External Crystal Clock Frequency 32.768KHz */
+#define __HIRC      (22118400UL)    /*!< Internal 22M RC Oscillator Frequency */
+#define __LIRC      (10000UL)       /*!< Internal 10K RC Oscillator Frequency */
+#define __SYS_OSC_CLK     (    ___HSI)    /* Main oscillator frequency        */
+
+
+#define __SYSTEM_CLOCK    (1*__HXT)
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+extern uint32_t CyclesPerUs;         /*!< Cycles per micro second              */
+extern uint32_t PllClock;            /*!< PLL Output Clock Frequency           */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  None
+ * @return None
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit(void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  None
+ * @return None
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_M451SERIES_H__ */
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/targets/targets.json b/targets/targets.json
index e2b2f7f56ac..d6a85e24059 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -2022,5 +2022,16 @@
         "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
         "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI"],
         "release_versions": ["2", "5"]
-    }    
+    },
+    "NUMAKER_PFM_M453": {
+        "core": "Cortex-M4F",
+        "default_toolchain": "ARM",
+        "extra_labels": ["NUVOTON", "M451", "NUMAKER_PFM_M453"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "inherits": ["Target"],
+        "progen": {"target": "numaker-pfm-m453"},
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "release_versions": ["2", "5"]
+    }
 }

From 1541265cd85bc08bb56baa435c6c653f8f5a37c6 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Thu, 11 Aug 2016 10:58:56 +0800
Subject: [PATCH 22/89] NUMAKER_PFM_M453 support for USB host

---
 .../USBHost/USBHost/USBHostTypes.h            |   2 +
 libraries/USBHost/USBHost/USBHALHost_M451.cpp | 347 ++++++++++++++++++
 2 files changed, 349 insertions(+)
 create mode 100644 libraries/USBHost/USBHost/USBHALHost_M451.cpp

diff --git a/features/unsupported/USBHost/USBHost/USBHostTypes.h b/features/unsupported/USBHost/USBHost/USBHostTypes.h
index 5d9dd22968f..860e77d6c67 100644
--- a/features/unsupported/USBHost/USBHost/USBHostTypes.h
+++ b/features/unsupported/USBHost/USBHost/USBHostTypes.h
@@ -97,6 +97,8 @@ enum ENDPOINT_TYPE {
 #define  OR_RH_PORT_CSC                 0x00010000
 #define  OR_RH_PORT_PRSC                0x00100000
 #define  OR_RH_PORT_LSDA                0x00000200
+#define  OR_RH_PORT_PESC                0x00020000
+#define  OR_RH_PORT_OCIC                0x00080000
 
 #define  FI                     0x2EDF           // 12000 bits per frame (-1)
 #define  DEFAULT_FMINTERVAL     ((((6 * (FI - 210)) / 7) << 16) | FI)
diff --git a/libraries/USBHost/USBHost/USBHALHost_M451.cpp b/libraries/USBHost/USBHost/USBHALHost_M451.cpp
new file mode 100644
index 00000000000..9679297f5fb
--- /dev/null
+++ b/libraries/USBHost/USBHost/USBHALHost_M451.cpp
@@ -0,0 +1,347 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(TARGET_M451)
+
+#include "mbed.h"
+#include "USBHALHost.h"
+#include "dbg.h"
+#include "pinmap.h"
+
+#define HCCA_SIZE   sizeof(HCCA)
+#define ED_SIZE     sizeof(HCED)
+#define TD_SIZE     sizeof(HCTD)
+
+#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
+
+#ifndef USBH_HcRhDescriptorA_POTPGT_Pos
+#define USBH_HcRhDescriptorA_POTPGT_Pos  (24)
+#endif
+#ifndef USBH_HcRhDescriptorA_POTPGT_Msk
+#define USBH_HcRhDescriptorA_POTPGT_Msk  (0xfful << USBH_HcRhDescriptorA_POTPGT_Pos)
+#endif
+
+static volatile MBED_ALIGN(256) uint8_t usb_buf[TOTAL_SIZE];  // 256 bytes aligned!
+
+USBHALHost * USBHALHost::instHost;
+
+USBHALHost::USBHALHost()
+{
+    instHost = this;
+    memInit();
+    memset((void*)usb_hcca, 0, HCCA_SIZE);
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        edBufAlloc[i] = false;
+    }
+    for (int i = 0; i < MAX_TD; i++) {
+        tdBufAlloc[i] = false;
+    }
+}
+
+void USBHALHost::init()
+{
+    // Unlock protected registers
+    SYS_UnlockReg();
+
+    // Enable USBH clock
+    CLK_EnableModuleClock(USBH_MODULE);
+    // Set USBH clock source/divider
+    CLK_SetModuleClock(USBH_MODULE, 0, CLK_CLKDIV0_USB(3));
+    
+    // Configure OTG function as Host-Only
+    SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk | SYS_USBPHY_USBROLE_STD_USBH;
+    
+    /* Below settings is use power switch IC to enable/disable USB Host power.
+       Set PA.2 is VBUS_EN function pin and PA.3 VBUS_ST function pin */
+    pin_function(PA_3, SYS_GPA_MFPL_PA3MFP_USB_VBUS_ST);
+    pin_function(PA_2, SYS_GPA_MFPL_PA2MFP_USB_VBUS_EN);
+
+    // Enable OTG clock
+    CLK_EnableModuleClock(OTG_MODULE);
+
+    // Lock protected registers
+    SYS_LockReg();
+    
+    // Overcurrent flag is low active
+    USBH->HcMiscControl |= USBH_HcMiscControl_OCAL_Msk;
+    
+    // Disable HC interrupts
+    USBH->HcInterruptDisable = OR_INTR_ENABLE_MIE;
+
+    // Needed by some controllers
+    USBH->HcControl = 0;
+
+    // Software reset
+    USBH->HcCommandStatus = OR_CMD_STATUS_HCR;
+    while (USBH->HcCommandStatus & OR_CMD_STATUS_HCR);
+
+    // Put HC in reset state
+    USBH->HcControl = (USBH->HcControl & ~OR_CONTROL_HCFS) | OR_CONTROL_HC_RSET;
+    // HCD must wait 10ms for HC reset complete
+    wait_ms(100);
+    
+    USBH->HcControlHeadED = 0;                      // Initialize Control ED list head to 0
+    USBH->HcBulkHeadED = 0;                         // Initialize Bulk ED list head to 0
+    USBH->HcHCCA = (uint32_t) usb_hcca;
+
+    USBH->HcFmInterval = DEFAULT_FMINTERVAL;        // Frame interval = 12000 - 1
+                                                    // MPS = 10,104
+    USBH->HcPeriodicStart = FI * 90 / 100;          // 90% of frame interval
+    USBH->HcLSThreshold = 0x628;                    // Low speed threshold
+
+    // Put HC in operational state
+    USBH->HcControl  = (USBH->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
+
+    // FIXME
+    USBH->HcRhDescriptorA = USBH->HcRhDescriptorA & ~(USBH_HcRhDescriptorA_NOCP_Msk | USBH_HcRhDescriptorA_OCPM_Msk | USBH_HcRhDescriptorA_PSM_Msk);
+    // Issue SetGlobalPower command
+    USBH->HcRhStatus = USBH_HcRhStatus_LPSC_Msk;
+    // Power On To Power Good Time, in 2 ms units
+    wait_ms(((USBH->HcRhDescriptorA & USBH_HcRhDescriptorA_POTPGT_Msk) >> USBH_HcRhDescriptorA_POTPGT_Pos) * 2);
+    
+    // Clear Interrrupt Status
+    USBH->HcInterruptStatus |= USBH->HcInterruptStatus;
+    // Enable interrupts we care about
+    USBH->HcInterruptEnable  = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
+    
+    NVIC_SetVector(USBH_IRQn, (uint32_t)(_usbisr));
+    NVIC_EnableIRQ(USBH_IRQn);
+    
+    // Check for any connected devices
+    if (USBH->HcRhPortStatus[0] & OR_RH_PORT_CCS) {
+        // Device connected
+        wait_ms(150);
+        deviceConnected(0, 1, USBH->HcRhPortStatus[0] & OR_RH_PORT_LSDA);
+    }
+}
+
+uint32_t USBHALHost::controlHeadED()
+{
+    return USBH->HcControlHeadED;
+}
+
+uint32_t USBHALHost::bulkHeadED()
+{
+    return USBH->HcBulkHeadED;
+}
+
+uint32_t USBHALHost::interruptHeadED()
+{
+    // FIXME: Only support one INT ED?
+    return usb_hcca->IntTable[0];
+}
+
+void USBHALHost::updateBulkHeadED(uint32_t addr)
+{
+    USBH->HcBulkHeadED = addr;
+}
+
+
+void USBHALHost::updateControlHeadED(uint32_t addr)
+{
+    USBH->HcControlHeadED = addr;
+}
+
+void USBHALHost::updateInterruptHeadED(uint32_t addr)
+{
+    // FIXME: Only support one INT ED?
+    usb_hcca->IntTable[0] = addr;
+}
+
+
+void USBHALHost::enableList(ENDPOINT_TYPE type)
+{
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            USBH->HcCommandStatus = OR_CMD_STATUS_CLF;
+            USBH->HcControl |= OR_CONTROL_CLE;
+            break;
+        case ISOCHRONOUS_ENDPOINT:
+            // FIXME
+            break;
+        case BULK_ENDPOINT:
+            USBH->HcCommandStatus = OR_CMD_STATUS_BLF;
+            USBH->HcControl |= OR_CONTROL_BLE;
+            break;
+        case INTERRUPT_ENDPOINT:
+            USBH->HcControl |= OR_CONTROL_PLE;
+            break;
+    }
+}
+
+
+bool USBHALHost::disableList(ENDPOINT_TYPE type)
+{
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            if(USBH->HcControl & OR_CONTROL_CLE) {
+                USBH->HcControl &= ~OR_CONTROL_CLE;
+                return true;
+            }
+            return false;
+        case ISOCHRONOUS_ENDPOINT:
+            // FIXME
+            return false;
+        case BULK_ENDPOINT:
+            if(USBH->HcControl & OR_CONTROL_BLE){
+                USBH->HcControl &= ~OR_CONTROL_BLE;
+                return true;
+            }
+            return false;
+        case INTERRUPT_ENDPOINT:
+            if(USBH->HcControl & OR_CONTROL_PLE) {
+                USBH->HcControl &= ~OR_CONTROL_PLE;
+                return true;
+            }
+            return false;
+    }
+    return false;
+}
+
+
+void USBHALHost::memInit()
+{
+    usb_hcca = (volatile HCCA *)usb_buf;
+    usb_edBuf = usb_buf + HCCA_SIZE;
+    usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
+}
+
+volatile uint8_t * USBHALHost::getED()
+{
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        if ( !edBufAlloc[i] ) {
+            edBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
+        }
+    }
+    perror("Could not allocate ED\r\n");
+    return NULL; //Could not alloc ED
+}
+
+volatile uint8_t * USBHALHost::getTD()
+{
+    int i;
+    for (i = 0; i < MAX_TD; i++) {
+        if ( !tdBufAlloc[i] ) {
+            tdBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
+        }
+    }
+    perror("Could not allocate TD\r\n");
+    return NULL; //Could not alloc TD
+}
+
+
+void USBHALHost::freeED(volatile uint8_t * ed)
+{
+    int i;
+    i = (ed - usb_edBuf) / ED_SIZE;
+    edBufAlloc[i] = false;
+}
+
+void USBHALHost::freeTD(volatile uint8_t * td)
+{
+    int i;
+    i = (td - usb_tdBuf) / TD_SIZE;
+    tdBufAlloc[i] = false;
+}
+
+
+void USBHALHost::resetRootHub()
+{
+    // Reset port1
+    USBH->HcRhPortStatus[0] = OR_RH_PORT_PRS;
+    while (USBH->HcRhPortStatus[0] & OR_RH_PORT_PRS);
+    USBH->HcRhPortStatus[0] = OR_RH_PORT_PRSC;
+}
+
+
+void USBHALHost::_usbisr(void)
+{
+    if (instHost) {
+        instHost->UsbIrqhandler();
+    }
+}
+
+void USBHALHost::UsbIrqhandler()
+{
+    uint32_t ints = USBH->HcInterruptStatus;
+    
+    // Root hub status change interrupt
+    if (ints & OR_INTR_STATUS_RHSC) {
+        uint32_t ints_roothub = USBH->HcRhStatus;
+        uint32_t ints_port1 = USBH->HcRhPortStatus[0];
+        uint32_t ints_port2 = USBH->HcRhPortStatus[1];
+        
+        // Port1: ConnectStatusChange
+        if (ints_port1 & OR_RH_PORT_CSC) {
+            if (ints_roothub & OR_RH_STATUS_DRWE) {
+                // When DRWE is on, Connect Status Change means a remote wakeup event.
+            } else {
+                if (ints_port1 & OR_RH_PORT_CCS) {
+                    // Root device connected
+                    
+                    // wait 150ms to avoid bounce
+                    wait_ms(150);
+
+                    //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
+                    deviceConnected(0, 1, ints_port1 & OR_RH_PORT_LSDA);
+                } else {
+                    // Root device disconnected
+                    
+                    if (!(ints & OR_INTR_STATUS_WDH)) {
+                        usb_hcca->DoneHead = 0;
+                    }
+
+                    // wait 200ms to avoid bounce
+                    wait_ms(200);
+
+                    deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
+
+                    if (ints & OR_INTR_STATUS_WDH) {
+                        usb_hcca->DoneHead = 0;
+                        USBH->HcInterruptStatus = OR_INTR_STATUS_WDH;
+                    }
+                }
+            }
+            USBH->HcRhPortStatus[0] = OR_RH_PORT_CSC;
+        }
+        // Port1: Reset completed
+        if (ints_port1 & OR_RH_PORT_PRSC) {
+            USBH->HcRhPortStatus[0] = OR_RH_PORT_PRSC;
+        }
+        // Port1: PortEnableStatusChange
+        if (ints_port1 & OR_RH_PORT_PESC) {
+            USBH->HcRhPortStatus[0] = OR_RH_PORT_PESC;
+        }
+        
+        // Port2: PortOverCurrentIndicatorChange
+        if (ints_port2 & OR_RH_PORT_OCIC) {
+            USBH->HcRhPortStatus[1] = OR_RH_PORT_OCIC;
+        }
+        
+        USBH->HcInterruptStatus = OR_INTR_STATUS_RHSC;
+    }
+
+    // Writeback Done Head interrupt
+    if (ints & OR_INTR_STATUS_WDH) {
+        transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
+        USBH->HcInterruptStatus = OR_INTR_STATUS_WDH;
+    }
+    
+    
+}
+#endif

From 67e1ff989f4fa399ef7df11a9e58e202f0011523 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Thu, 11 Aug 2016 11:24:55 +0800
Subject: [PATCH 23/89] Fix USB re-plugin not detected in NUMAKER_PFM_NUC472

---
 libraries/USBHost/USBHost/USBHALHost_NUC472.cpp | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/libraries/USBHost/USBHost/USBHALHost_NUC472.cpp b/libraries/USBHost/USBHost/USBHALHost_NUC472.cpp
index e0fdca2c170..4aa25fe16d6 100644
--- a/libraries/USBHost/USBHost/USBHALHost_NUC472.cpp
+++ b/libraries/USBHost/USBHost/USBHALHost_NUC472.cpp
@@ -311,6 +311,7 @@ void USBHALHost::UsbIrqhandler()
         uint32_t ints_roothub = USBH->HcRhStatus;
         uint32_t ints_port1 = USBH->HcRhPortStatus[0];
         
+        // Port1: ConnectStatusChange
         if (ints_port1 & OR_RH_PORT_CSC) {
             if (ints_roothub & OR_RH_STATUS_DRWE) {
                 // When DRWE is on, Connect Status Change means a remote wakeup event.
@@ -343,11 +344,14 @@ void USBHALHost::UsbIrqhandler()
             }
             USBH->HcRhPortStatus[0] = OR_RH_PORT_CSC;
         }
-        
-        // Reset completed
+        // Port1: Reset completed
         if (ints_port1 & OR_RH_PORT_PRSC) {
             USBH->HcRhPortStatus[0] = OR_RH_PORT_PRSC;
         }
+        // Port1: PortEnableStatusChange
+        if (ints_port1 & OR_RH_PORT_PESC) {
+            USBH->HcRhPortStatus[0] = OR_RH_PORT_PESC;
+        }
         
         USBH->HcInterruptStatus = OR_INTR_STATUS_RHSC;
     }

From 1cdb46e9b44c4f52049f70523330370b2f336880 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Fri, 19 Aug 2016 18:33:19 +0800
Subject: [PATCH 24/89] Integrate NUC472 DES/TDES accelerator

---
 .../hal/TARGET_NUVOTON/TARGET_NUC472/crypto.c |  42 ++
 .../hal/TARGET_NUVOTON/TARGET_NUC472/crypto.h |  33 ++
 .../TARGET_NUVOTON/TARGET_NUC472/des_alt.c    | 410 ++++++++++++++++++
 .../TARGET_NUVOTON/TARGET_NUC472/des_alt.h    | 279 ++++++++++++
 4 files changed, 764 insertions(+)
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.c
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.h
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/des_alt.c
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/des_alt.h

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.c
new file mode 100644
index 00000000000..8d56325b0b4
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.c
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "cmsis.h"
+#include "mbed_assert.h"
+#include "nu_modutil.h"
+#include "nu_bitutil.h"
+
+static int crypto_inited = 0;
+
+void crypto_init(void)
+{
+    if (crypto_inited) {
+        return;
+    }
+    crypto_inited = 1;
+    
+    CLK_EnableModuleClock(CRPT_MODULE);
+}
+
+/* Implementation that should never be optimized out by the compiler */
+void crypto_zeroize(void *v, size_t n)
+{
+    volatile unsigned char *p = (unsigned char*) v;
+    while (n--) {
+        *p++ = 0;
+    }
+}
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.h
new file mode 100644
index 00000000000..0f674651665
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.h
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CRYPTO_H
+#define MBED_CRYPTO_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void crypto_init(void);
+void crypto_zeroize(void *v, size_t n);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/des_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/des_alt.c
new file mode 100644
index 00000000000..867e27b5f9a
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/des_alt.c
@@ -0,0 +1,410 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "mbedtls/config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_DES_C)
+#if defined(MBEDTLS_DES_ALT)
+
+#include <string.h>
+#include "mbedtls/des.h"
+#include "des_alt.h"
+#include "crypto.h"
+#include "nu_bitutil.h"
+#include "toolchain.h"
+
+// Must be a multiple of 64-bit block size
+#define MAXSIZE_DMABUF  (8 * 5)
+static uint8_t dmabuf_in[MAXSIZE_DMABUF] MBED_ALIGN(4);
+static uint8_t dmabuf_out[MAXSIZE_DMABUF] MBED_ALIGN(4);
+
+static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, 
+    unsigned char iv[8], const unsigned char *input, unsigned char *output);
+
+void mbedtls_des_init(mbedtls_des_context *ctx)
+{
+    crypto_init();
+    memset(ctx, 0, sizeof(mbedtls_des_context));
+}
+
+void mbedtls_des_free( mbedtls_des_context *ctx )
+{
+    if (ctx == NULL) {
+        return;
+    }
+
+    crypto_zeroize(ctx, sizeof(mbedtls_des_context));
+}
+
+void mbedtls_des3_init( mbedtls_des3_context *ctx )
+{
+    crypto_init();
+    memset(ctx, 0, sizeof(mbedtls_des3_context));
+}
+
+void mbedtls_des3_free( mbedtls_des3_context *ctx )
+{
+    if (ctx == NULL) {
+        return;
+    }
+
+    crypto_zeroize(ctx, sizeof (mbedtls_des3_context));
+}
+
+static const unsigned char odd_parity_table[128] = { 1,  2,  4,  7,  8,
+        11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44,
+        47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81,
+        82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112,
+        115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140,
+        143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168,
+        171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196,
+        199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224,
+        227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253,
+        254 };
+
+void mbedtls_des_key_set_parity(unsigned char key[MBEDTLS_DES_KEY_SIZE])
+{
+    int i;
+
+    for (i = 0; i < MBEDTLS_DES_KEY_SIZE; i++) {
+        key[i] = odd_parity_table[key[i] / 2];
+    }
+}
+
+/*
+ * Check the given key's parity, returns 1 on failure, 0 on SUCCESS
+ */
+int mbedtls_des_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
+{
+    int i;
+
+    for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ )
+        if( key[i] != odd_parity_table[key[i] / 2] )
+            return( 1 );
+
+    return( 0 );
+}
+
+/*
+ * Table of weak and semi-weak keys
+ *
+ * Source: http://en.wikipedia.org/wiki/Weak_key
+ *
+ * Weak:
+ * Alternating ones + zeros (0x0101010101010101)
+ * Alternating 'F' + 'E' (0xFEFEFEFEFEFEFEFE)
+ * '0xE0E0E0E0F1F1F1F1'
+ * '0x1F1F1F1F0E0E0E0E'
+ *
+ * Semi-weak:
+ * 0x011F011F010E010E and 0x1F011F010E010E01
+ * 0x01E001E001F101F1 and 0xE001E001F101F101
+ * 0x01FE01FE01FE01FE and 0xFE01FE01FE01FE01
+ * 0x1FE01FE00EF10EF1 and 0xE01FE01FF10EF10E
+ * 0x1FFE1FFE0EFE0EFE and 0xFE1FFE1FFE0EFE0E
+ * 0xE0FEE0FEF1FEF1FE and 0xFEE0FEE0FEF1FEF1
+ *
+ */
+
+#define WEAK_KEY_COUNT 16
+
+static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] =
+{
+    { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 },
+    { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
+    { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E },
+    { 0xE0, 0xE0, 0xE0, 0xE0, 0xF1, 0xF1, 0xF1, 0xF1 },
+
+    { 0x01, 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E },
+    { 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E, 0x01 },
+    { 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1 },
+    { 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1, 0x01 },
+    { 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE },
+    { 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01 },
+    { 0x1F, 0xE0, 0x1F, 0xE0, 0x0E, 0xF1, 0x0E, 0xF1 },
+    { 0xE0, 0x1F, 0xE0, 0x1F, 0xF1, 0x0E, 0xF1, 0x0E },
+    { 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E, 0xFE },
+    { 0xFE, 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E },
+    { 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1, 0xFE },
+    { 0xFE, 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1 }
+};
+
+int mbedtls_des_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
+{
+    int i;
+
+    for( i = 0; i < WEAK_KEY_COUNT; i++ )
+        if( memcmp( weak_key_table[i], key, MBEDTLS_DES_KEY_SIZE) == 0 )
+            return( 1 );
+
+    return( 0 );
+}
+
+/*
+ * DES key schedule (56-bit, encryption)
+ */
+int mbedtls_des_setkey_enc( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
+{
+    ctx->enc = 1;
+    // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3.
+    ctx->keyopt = 3;
+    memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
+    memcpy(ctx->key[1], key, MBEDTLS_DES_KEY_SIZE);
+    memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE);
+    
+    return 0;
+}
+
+/*
+ * DES key schedule (56-bit, decryption)
+ */
+int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
+{
+    ctx->enc = 0;
+    // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3.
+    ctx->keyopt = 3;
+    memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
+    memcpy(ctx->key[1], key, MBEDTLS_DES_KEY_SIZE);
+    memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE);
+
+    return 0;
+}
+
+/*
+ * Triple-DES key schedule (112-bit, encryption)
+ */
+int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] )
+{
+    ctx->enc = 1;
+    // Keying option 2: K1 and K2 are independent, and K3 = K1.
+    ctx->keyopt = 2;
+    memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
+    memcpy(ctx->key[1], key + MBEDTLS_DES_KEY_SIZE, MBEDTLS_DES_KEY_SIZE);
+    memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE);
+
+    return 0;
+}
+
+/*
+ * Triple-DES key schedule (112-bit, decryption)
+ */
+int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] )
+{
+    ctx->enc = 0;
+    // Keying option 2: K1 and K2 are independent, and K3 = K1.
+    ctx->keyopt = 2;
+    memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
+    memcpy(ctx->key[1], key + MBEDTLS_DES_KEY_SIZE, MBEDTLS_DES_KEY_SIZE);
+    memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE);
+
+    return 0;
+}
+
+/*
+ * Triple-DES key schedule (168-bit, encryption)
+ */
+int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] )
+{
+    ctx->enc = 1;
+    // Keying option 1: All three keys are independent.
+    ctx->keyopt = 1;
+    memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
+    memcpy(ctx->key[1], key + MBEDTLS_DES_KEY_SIZE, MBEDTLS_DES_KEY_SIZE);
+    memcpy(ctx->key[2], key + MBEDTLS_DES_KEY_SIZE * 2, MBEDTLS_DES_KEY_SIZE);
+
+    return 0;
+}
+
+/*
+ * Triple-DES key schedule (168-bit, decryption)
+ */
+int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] )
+{
+    ctx->enc = 0;
+    // Keying option 1: All three keys are independent.
+    ctx->keyopt = 1;
+    memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
+    memcpy(ctx->key[1], key + MBEDTLS_DES_KEY_SIZE, MBEDTLS_DES_KEY_SIZE);
+    memcpy(ctx->key[2], key + MBEDTLS_DES_KEY_SIZE * 2, MBEDTLS_DES_KEY_SIZE);
+
+    return 0;
+}
+
+/*
+ * DES-ECB block encryption/decryption
+ */
+int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx,
+                    const unsigned char input[8],
+                    unsigned char output[8] )
+{
+    unsigned char iv[8] = {0x00};
+    return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, DES_MODE_ECB, 8, iv, input, output);
+}
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/*
+ * DES-CBC buffer encryption/decryption
+ */
+int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[8],
+                    const unsigned char *input,
+                    unsigned char *output )
+{
+    return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, DES_MODE_CBC, length, iv, input, output);
+}
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+/*
+ * 3DES-ECB block encryption/decryption
+ */
+int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx,
+                     const unsigned char input[8],
+                     unsigned char output[8] )
+{
+    unsigned char iv[8] = {0x00};
+    return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, TDES_MODE_ECB, 8, iv, input, output);
+}
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/*
+ * 3DES-CBC buffer encryption/decryption
+ */
+int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx,
+                     int mode,
+                     size_t length,
+                     unsigned char iv[8],
+                     const unsigned char *input,
+                     unsigned char *output )
+{
+    return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, TDES_MODE_CBC, length, iv, input, output);
+}
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+
+
+static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length, 
+    unsigned char iv[8], const unsigned char *input, unsigned char *output)
+{
+    if (length % 8) {
+        return MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH;
+    }
+    
+    // NOTE: Don't call driver function TDES_Open in BSP because it doesn't support TDES_CTL[3KEYS] setting.
+    CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) |
+        tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos);
+
+    // Keying option 1: All three keys are independent.
+    // Keying option 2: K1 and K2 are independent, and K3 = K1.
+    // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3. 
+    if (keyopt == 1) {
+        CRPT->TDES_CTL |= CRPT_TDES_CTL_3KEYS_Msk;
+    }
+    else {
+        CRPT->TDES_CTL &= ~CRPT_TDES_CTL_3KEYS_Msk;
+    }
+
+    // Set DES/TDES keys
+    // NOTE: Don't call driver function TDES_SetKey in BSP because it doesn't support endian swap.
+    uint32_t val;
+    volatile uint32_t *tdes_key = (uint32_t *) ((uint32_t) &CRPT->TDES0_KEY1H + (0x40 * 0));
+    val = nu_get32_be(key[0] + 0);
+    *tdes_key ++ = val;
+    val = nu_get32_be(key[0] + 4);
+    *tdes_key ++ = val;
+    val = nu_get32_be(key[1] + 0);
+    *tdes_key ++ = val;
+    val = nu_get32_be(key[1] + 4);
+    *tdes_key ++ = val;
+    val = nu_get32_be(key[2] + 0);
+    *tdes_key ++ = val;
+    val = nu_get32_be(key[2] + 4);
+    *tdes_key ++ = val;
+    
+    uint32_t rmn = length;
+    const unsigned char *in_pos = input;
+    const unsigned char *out_pos = output;
+    
+    while (rmn) {
+        uint32_t data_len = (rmn <= MAXSIZE_DMABUF) ? rmn : MAXSIZE_DMABUF;
+        
+        uint32_t ivh, ivl;
+        ivh = nu_get32_be(iv);
+        ivl = nu_get32_be(iv + 4);
+        TDES_SetInitVect(0, ivh, ivl);
+    
+        memcpy(dmabuf_in, in_pos, data_len);
+        
+        TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len);
+        
+        // Start enc/dec.
+        // NOTE: Don't call driver function TDES_Start in BSP because it will override TDES_CTL[3KEYS] setting.
+        CRPT->TDES_CTL |= CRPT_TDES_CTL_START_Msk | (CRYPTO_DMA_ONE_SHOT << CRPT_TDES_CTL_DMALAST_Pos);
+        while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk);
+        
+        memcpy(out_pos, dmabuf_out, data_len);
+        in_pos += data_len;
+        out_pos += data_len;
+        rmn -= data_len;
+        
+        // Update IV for next block enc/dec in next function call
+        switch (tdes_opmode) {
+            case DES_MODE_OFB:
+            case TDES_MODE_OFB: {
+                // OFB: IV (enc/dec) = output block XOR input block
+                uint32_t lbh, lbl;
+                // Last block of input data
+                lbh = nu_get32_be(dmabuf_in + data_len - 8 + 4);
+                lbl = nu_get32_be(dmabuf_in + data_len - 8 + 0);
+                // Last block of output data
+                ivh = nu_get32_be(dmabuf_out + 4);
+                ivl = nu_get32_be(dmabuf_out + 0);
+                ivh = ivh ^ lbh;
+                ivl = ivl ^ lbl;
+                nu_set32_be(iv + 4, ivh);
+                nu_set32_be(iv, ivl);
+                break;
+            }
+            case DES_MODE_CBC:
+            case DES_MODE_CFB:
+            case TDES_MODE_CBC:
+            case TDES_MODE_CFB: {
+                // CBC/CFB: IV (enc) = output block
+                //          IV (dec) = input block
+                if (enc) {    
+                    memcpy(iv, dmabuf_out + data_len - 8, 8);
+                }
+                else {
+                    memcpy(iv, dmabuf_in + data_len - 8, 8);
+                }
+            }
+        }
+    }
+    
+    return 0;
+}
+
+#endif /* MBEDTLS_DES_ALT */
+#endif /* MBEDTLS_DES_C */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/des_alt.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/des_alt.h
new file mode 100644
index 00000000000..67a1420ece7
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/des_alt.h
@@ -0,0 +1,279 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#ifndef MBEDTLS_DES_ALT_H
+#define MBEDTLS_DES_ALT_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "mbedtls/config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_DES_ALT)
+
+#include <stddef.h>
+#include <stdint.h>
+#include "des.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          DES context structure
+ */
+typedef struct
+{
+    int enc;                                            /*!<  0: dec, 1: enc    */
+    uint16_t keyopt;
+    uint8_t key[3][MBEDTLS_DES_KEY_SIZE];               /*!<  3DES keys         */
+}
+mbedtls_des_context;
+
+/**
+ * \brief          Triple-DES context structure
+ */
+typedef struct
+{
+    int enc;                                            /*!<  0: dec, 1: enc    */
+    uint16_t keyopt;
+    uint8_t key[3][MBEDTLS_DES_KEY_SIZE];               /*!<  3DES keys         */
+}
+mbedtls_des3_context;
+
+/**
+ * \brief          Initialize DES context
+ *
+ * \param ctx      DES context to be initialized
+ */
+void mbedtls_des_init( mbedtls_des_context *ctx );
+
+/**
+ * \brief          Clear DES context
+ *
+ * \param ctx      DES context to be cleared
+ */
+void mbedtls_des_free( mbedtls_des_context *ctx );
+
+/**
+ * \brief          Initialize Triple-DES context
+ *
+ * \param ctx      DES3 context to be initialized
+ */
+void mbedtls_des3_init( mbedtls_des3_context *ctx );
+
+/**
+ * \brief          Clear Triple-DES context
+ *
+ * \param ctx      DES3 context to be cleared
+ */
+void mbedtls_des3_free( mbedtls_des3_context *ctx );
+
+/**
+ * \brief          Set key parity on the given key to odd.
+ *
+ *                 DES keys are 56 bits long, but each byte is padded with
+ *                 a parity bit to allow verification.
+ *
+ * \param key      8-byte secret key
+ */
+void mbedtls_des_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          Check that key parity on the given key is odd.
+ *
+ *                 DES keys are 56 bits long, but each byte is padded with
+ *                 a parity bit to allow verification.
+ *
+ * \param key      8-byte secret key
+ *
+ * \return         0 is parity was ok, 1 if parity was not correct.
+ */
+int mbedtls_des_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          Check that key is not a weak or semi-weak DES key
+ *
+ * \param key      8-byte secret key
+ *
+ * \return         0 if no weak key was found, 1 if a weak key was identified.
+ */
+int mbedtls_des_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          DES key schedule (56-bit, encryption)
+ *
+ * \param ctx      DES context to be initialized
+ * \param key      8-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des_setkey_enc( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          DES key schedule (56-bit, decryption)
+ *
+ * \param ctx      DES context to be initialized
+ * \param key      8-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          Triple-DES key schedule (112-bit, encryption)
+ *
+ * \param ctx      3DES context to be initialized
+ * \param key      16-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
+
+/**
+ * \brief          Triple-DES key schedule (112-bit, decryption)
+ *
+ * \param ctx      3DES context to be initialized
+ * \param key      16-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
+
+/**
+ * \brief          Triple-DES key schedule (168-bit, encryption)
+ *
+ * \param ctx      3DES context to be initialized
+ * \param key      24-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
+
+/**
+ * \brief          Triple-DES key schedule (168-bit, decryption)
+ *
+ * \param ctx      3DES context to be initialized
+ * \param key      24-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
+
+/**
+ * \brief          DES-ECB block encryption/decryption
+ *
+ * \param ctx      DES context
+ * \param input    64-bit input block
+ * \param output   64-bit output block
+ *
+ * \return         0 if successful
+ */
+int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx,
+                    const unsigned char input[8],
+                    unsigned char output[8] );
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/**
+ * \brief          DES-CBC buffer encryption/decryption
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      DES context
+ * \param mode     MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ */
+int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[8],
+                    const unsigned char *input,
+                    unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+/**
+ * \brief          3DES-ECB block encryption/decryption
+ *
+ * \param ctx      3DES context
+ * \param input    64-bit input block
+ * \param output   64-bit output block
+ *
+ * \return         0 if successful
+ */
+int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx,
+                     const unsigned char input[8],
+                     unsigned char output[8] );
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/**
+ * \brief          3DES-CBC buffer encryption/decryption
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      3DES context
+ * \param mode     MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH
+ */
+int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx,
+                     int mode,
+                     size_t length,
+                     unsigned char iv[8],
+                     const unsigned char *input,
+                     unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+/**
+ * \brief          Internal function for key expansion.
+ *                 (Only exposed to allow overriding it,
+ *                 see MBEDTLS_DES_SETKEY_ALT)
+ *
+ * \param SK       Round keys
+ * \param key      Base key
+ */
+void mbedtls_des_setkey( uint32_t SK[32],
+                         const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_DES_ALT */
+
+#endif /* des_alt.h */

From 01510da2b12ec2fc8bc1bccdd6f8adb95f297e4d Mon Sep 17 00:00:00 2001
From: cyliangtw <cyliang@nuvoton.com>
Date: Tue, 23 Aug 2016 19:05:03 +0800
Subject: [PATCH 25/89] Integrate NUC472 AES

---
 .../TARGET_NUVOTON/TARGET_NUC472/aes_alt.c    | 515 ++++++++++++++++++
 .../TARGET_NUVOTON/TARGET_NUC472/aes_alt.h    | 272 +++++++++
 2 files changed, 787 insertions(+)
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.c
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.h

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.c
new file mode 100644
index 00000000000..f6920f5ba09
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.c
@@ -0,0 +1,515 @@
+/*
+ *  AES hardware acceleration implementation
+ *
+ *  Copyright (C) 2015-2020, Nuvoton, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ */
+/*
+ *  The AES block cipher was designed by Vincent Rijmen and Joan Daemen.
+ *
+ *  http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf
+ *  http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
+ */
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "mbedtls/config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_AES_C)
+
+#include <string.h>
+
+#include "mbedtls/aes.h"
+#if defined(MBEDTLS_PADLOCK_C)
+#include "mbedtls/padlock.h"
+#endif
+#if defined(MBEDTLS_AESNI_C)
+#include "mbedtls/aesni.h"
+#endif
+
+#if defined(MBEDTLS_SELF_TEST)
+#if defined(MBEDTLS_PLATFORM_C)
+#include "mbedtls/platform.h"
+#else
+#include <stdio.h>
+#define mbedtls_printf printf
+#endif /* MBEDTLS_PLATFORM_C */
+#endif /* MBEDTLS_SELF_TEST */
+
+#include "NUC472_442.h"
+
+//static int aes_init_done = 0;
+
+#if defined(MBEDTLS_AES_ALT)
+
+#define mbedtls_trace  //printf
+
+
+/* Implementation that should never be optimized out by the compiler */
+static void mbedtls_zeroize( void *v, size_t n ) {
+    volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
+}
+
+
+static uint32_t au32MyAESIV[4] = {
+    0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+extern volatile int  g_AES_done;
+
+#ifdef __ICCARM__
+#pragma data_alignment=4
+uint8_t au8OutputData[16];
+#pragma data_alignment=4
+uint8_t au8InputData[16];
+#else
+__align(4) uint8_t au8OutputData[16];
+__align(4) uint8_t au8InputData[16];
+#endif
+
+static void dumpHex(uint8_t au8Data[], int len)
+{
+		int j;									
+		for (j = 0; j < len; j++) mbedtls_trace("%02x ", au8Data[j]);									
+		mbedtls_trace("\r\n");										
+}	
+
+//volatile void CRYPTO_IRQHandler()
+//{
+//    if (AES_GET_INT_FLAG()) {
+//        g_AES_done = 1;
+//        AES_CLR_INT_FLAG();
+//    }
+//}
+
+// AES available channel 0~3
+static unsigned char channel_flag[4]={0x00,0x00,0x00,0x00};  // 0: idle, 1: busy
+static int channel_alloc()
+{
+	int i;
+	for(i=0; i< sizeof(channel_flag); i++)
+	{
+		if( channel_flag[i] == 0x00 )
+		{
+			channel_flag[i] = 0x01;
+			return i;
+		}	
+	}
+	printf("%s: No available AES channel \r\n", __FUNCTION__);
+	return(-1);
+}
+
+static void channel_free(int i)
+{
+	if( i >=0 && i < sizeof(channel_flag) )
+		channel_flag[i] = 0x00;
+}
+
+
+void mbedtls_aes_init( mbedtls_aes_context *ctx )
+{
+	int i =-1;
+
+//	sw_mbedtls_aes_init(ctx); 
+//	return;
+	
+		mbedtls_trace("=== %s \r\n", __FUNCTION__);
+    memset( ctx, 0, sizeof( mbedtls_aes_context ) );
+	
+    ctx->swapType = AES_IN_OUT_SWAP;
+		while( (i = channel_alloc()) < 0 ) osDelay(300);
+
+    ctx->channel = i;
+    ctx->iv = au32MyAESIV;
+	
+    /* Unlock protected registers */
+    SYS_UnlockReg();
+	  CLK_EnableModuleClock(CRPT_MODULE);
+    /* Lock protected registers */
+    SYS_LockReg();
+
+    NVIC_EnableIRQ(CRPT_IRQn);
+    AES_ENABLE_INT();    	
+	  mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__, ctx->channel);
+}
+
+void mbedtls_aes_free( mbedtls_aes_context *ctx )
+{
+
+	  mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__,ctx->channel);	
+
+    if( ctx == NULL )
+        return;
+
+    /* Unlock protected registers */
+//    SYS_UnlockReg();
+//    CLK_DisableModuleClock(CRPT_MODULE);
+    /* Lock protected registers */
+//    SYS_LockReg();
+
+//    NVIC_DisableIRQ(CRPT_IRQn);
+//    AES_DISABLE_INT();       	
+		channel_free(ctx->channel);
+    mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) );
+}
+
+/*
+ * AES key schedule (encryption)
+ */
+#if defined(MBEDTLS_AES_SETKEY_ENC_ALT)
+int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
+                    unsigned int keybits )
+{
+    unsigned int i;
+	
+	mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits);
+	dumpHex(key,keybits/8);
+
+    switch( keybits )
+    {
+        case 128: 
+       	    ctx->keySize = AES_KEY_SIZE_128;
+            break;
+        case 192:  
+        	ctx->keySize = AES_KEY_SIZE_192;
+            break;
+        case 256:  
+            ctx->keySize = AES_KEY_SIZE_256;
+            break;
+        default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
+    }
+
+
+
+	// key swap
+		for( i = 0; i < ( keybits >> 5 ); i++ )
+		{
+						ctx->buf[i] = (*(key+i*4) << 24) |
+													(*(key+1+i*4) << 16) |
+													(*(key+2+i*4) << 8) |
+													(*(key+3+i*4) );
+		}
+    AES_SetKey(ctx->channel, ctx->buf, ctx->keySize);
+
+
+    return( 0 );
+}
+#endif /* MBEDTLS_AES_SETKEY_ENC_ALT */
+
+/*
+ * AES key schedule (decryption)
+ */
+#if defined(MBEDTLS_AES_SETKEY_DEC_ALT)
+int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
+                    unsigned int keybits )
+{
+    int ret;
+	
+	  mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits);
+	  dumpHex(key,keybits/8);
+	
+    /* Also checks keybits */
+    if( ( ret = mbedtls_aes_setkey_enc( ctx, key, keybits ) ) != 0 )
+        goto exit;    
+
+exit:
+
+    return( ret );
+}
+#endif /* MBEDTLS_AES_SETKEY_DEC_ALT */
+
+
+static void __nvt_aes_crypt( mbedtls_aes_context *ctx,
+                          const unsigned char input[16],
+                          unsigned char output[16])
+{
+    int i;
+		unsigned char* pIn;
+	  unsigned char* pOut;
+
+//	  mbedtls_trace("=== %s \r\n", __FUNCTION__);
+	  dumpHex(input,16);
+ 
+    AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType);
+    AES_SetInitVect(ctx->channel, ctx->iv);
+		if( ((uint32_t)input) & 0x03 )
+		{
+			memcpy(au8InputData, input, sizeof(au8InputData));
+			pIn = au8InputData;
+		}else{
+		  pIn = (uint32_t)input;
+    }
+		if( ((uint32_t)output) & 0x03 )
+		{		
+			pOut = au8OutputData;
+		} else {
+		  pOut = (uint32_t)output;
+    }			
+
+    AES_SetDMATransfer(ctx->channel, (uint32_t)pIn, (uint32_t)pOut, sizeof(au8InputData));		
+
+    g_AES_done = 0;
+    AES_Start(ctx->channel, CRYPTO_DMA_ONE_SHOT);
+    while (!g_AES_done);
+
+    if( pOut != (uint32_t)output ) memcpy(output, au8OutputData, sizeof(au8InputData));
+		dumpHex(output,16);
+
+
+}
+
+/*
+ * AES-ECB block encryption
+ */
+#if defined(MBEDTLS_AES_ENCRYPT_ALT)
+void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
+                          const unsigned char input[16],
+                          unsigned char output[16] )
+{
+    int i;
+
+	  mbedtls_trace("=== %s \r\n", __FUNCTION__);
+	
+	  ctx->encDec = 1;
+	  __nvt_aes_crypt(ctx, input, output);
+  
+}
+#endif /* MBEDTLS_AES_ENCRYPT_ALT */
+
+/*
+ * AES-ECB block decryption
+ */
+#if defined(MBEDTLS_AES_DECRYPT_ALT)
+void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
+                          const unsigned char input[16],
+                          unsigned char output[16] )
+{
+    int i;
+ 
+	  mbedtls_trace("=== %s \r\n", __FUNCTION__);
+
+	  ctx->encDec = 0;
+	  __nvt_aes_crypt(ctx, input, output);
+
+
+}
+#endif /* MBEDTLS_AES_DECRYPT_ALT */
+
+/*
+ * AES-ECB block encryption/decryption
+ */
+int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
+                    int mode,
+                    const unsigned char input[16],
+                    unsigned char output[16] )
+{
+  unsigned char sw_output[16];
+
+	
+	  mbedtls_trace("=== %s \r\n", __FUNCTION__);
+		
+	  ctx->opMode = AES_MODE_ECB;
+    if( mode == MBEDTLS_AES_ENCRYPT )
+        mbedtls_aes_encrypt( ctx, input, output );
+    else
+        mbedtls_aes_decrypt( ctx, input, output );
+		
+
+    return( 0 );
+}
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/*
+ * AES-CBC buffer encryption/decryption
+ */
+int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[16],
+                    const unsigned char *input,
+                    unsigned char *output )
+{
+    int i;
+    unsigned char temp[16];
+	  unsigned int* piv;
+
+		mbedtls_trace("=== %s \r\n", __FUNCTION__);
+    if( length % 16 )
+        return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
+
+
+        while( length > 0 )
+        {
+			      ctx->opMode = AES_MODE_CBC;
+			      ctx->iv = iv;
+    		    if( mode == MBEDTLS_AES_ENCRYPT )
+    		    {
+        		    mbedtls_aes_encrypt( ctx, input, output );
+        		    memcpy( iv, output, 16 );
+    		    }else{
+    			      memcpy( temp, input, 16 );
+								dumpHex(input,16);
+        		    mbedtls_aes_decrypt( ctx, input, output );
+							  dumpHex(iv,16);
+								dumpHex(output,16);
+        		    memcpy( iv, temp, 16 );            
+            }
+					
+					// iv SWAP
+					piv = (unsigned int*)iv;
+					for( i=0; i< 4; i++)
+					{
+						*piv = (((*piv) & 0x000000FF) << 24) |
+							(((*piv) & 0x0000FF00) << 8) |
+							(((*piv) & 0x00FF0000) >> 8) |
+							(((*piv) & 0xFF000000) >> 24);
+						piv++;
+					}
+            input  += 16;
+            output += 16;
+            length -= 16;
+        }
+
+
+    return( 0 );
+}
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+#if defined(MBEDTLS_CIPHER_MODE_CFB)
+/*
+ * AES-CFB128 buffer encryption/decryption
+ */
+int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
+                       int mode,
+                       size_t length,
+                       size_t *iv_off,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output )
+{
+    int c;
+    size_t n = *iv_off;
+
+		mbedtls_trace("=== %s \r\n", __FUNCTION__);
+    if( mode == MBEDTLS_AES_DECRYPT )
+    {
+        while( length-- )
+        {
+            if( n == 0 )
+                mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
+
+            c = *input++;
+            *output++ = (unsigned char)( c ^ iv[n] );
+            iv[n] = (unsigned char) c;
+
+            n = ( n + 1 ) & 0x0F;
+        }
+    }
+    else
+    {
+        while( length-- )
+        {
+            if( n == 0 )
+                mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
+
+            iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ );
+
+            n = ( n + 1 ) & 0x0F;
+        }
+    }
+
+    *iv_off = n;
+
+    return( 0 );
+}
+
+/*
+ * AES-CFB8 buffer encryption/decryption
+ */
+int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
+                       int mode,
+                       size_t length,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output )
+{
+    unsigned char c;
+    unsigned char ov[17];
+
+		mbedtls_trace("=== %s \r\n", __FUNCTION__);
+    while( length-- )
+    {
+        memcpy( ov, iv, 16 );
+        mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
+
+        if( mode == MBEDTLS_AES_DECRYPT )
+            ov[16] = *input;
+
+        c = *output++ = (unsigned char)( iv[0] ^ *input++ );
+
+        if( mode == MBEDTLS_AES_ENCRYPT )
+            ov[16] = c;
+
+        memcpy( iv, ov + 1, 16 );
+    }
+
+    return( 0 );
+}
+#endif /*MBEDTLS_CIPHER_MODE_CFB */
+
+#if defined(MBEDTLS_CIPHER_MODE_CTR)
+/*
+ * AES-CTR buffer encryption/decryption
+ */
+int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
+                       size_t length,
+                       size_t *nc_off,
+                       unsigned char nonce_counter[16],
+                       unsigned char stream_block[16],
+                       const unsigned char *input,
+                       unsigned char *output )
+{
+    int c, i;
+    size_t n = *nc_off;
+
+	mbedtls_trace("=== %s \r\n", __FUNCTION__);	
+    while( length-- )
+    {
+        if( n == 0 ) {
+            mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block );
+
+            for( i = 16; i > 0; i-- )
+                if( ++nonce_counter[i - 1] != 0 )
+                    break;
+        }
+        c = *input++;
+        *output++ = (unsigned char)( c ^ stream_block[n] );
+
+        n = ( n + 1 ) & 0x0F;
+    }
+
+    *nc_off = n;
+
+    return( 0 );
+}
+#endif /* MBEDTLS_CIPHER_MODE_CTR */
+
+#endif /* MBEDTLS_AES_ALT */
+
+
+#endif /* MBEDTLS_AES_C */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.h
new file mode 100644
index 00000000000..77d1837e9eb
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.h
@@ -0,0 +1,272 @@
+/**
+ * \file aes_alt.h
+ *
+ * \brief AES block cipher
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+
+#if defined(MBEDTLS_AES_ALT)
+// Regular implementation
+//
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          AES context structure
+ *
+ * \note           buf is able to hold 32 extra bytes, which can be used:
+ *                 - for alignment purposes if VIA padlock is used, and/or
+ *                 - to simplify key expansion in the 256-bit case by
+ *                 generating an extra round key
+ */
+typedef struct
+{
+    uint32_t keySize;
+    uint32_t encDec;
+    uint32_t opMode;
+    uint32_t channel;
+    uint32_t swapType;
+    uint32_t *iv;
+    uint32_t buf[8]; 
+/* For comparsion with software AES for correctness */ 
+#if 0
+    uint32_t buf[68];           /*!<  unaligned data    */    
+    int nr;                     /*!<  number of rounds  */
+    uint32_t *rk;               /*!<  AES round keys    */    
+#endif    
+}
+mbedtls_aes_context;
+
+/**
+ * \brief          Initialize AES context
+ *
+ * \param ctx      AES context to be initialized
+ */
+void mbedtls_aes_init( mbedtls_aes_context *ctx );
+
+/**
+ * \brief          Clear AES context
+ *
+ * \param ctx      AES context to be cleared
+ */
+void mbedtls_aes_free( mbedtls_aes_context *ctx );
+
+/**
+ * \brief          AES key schedule (encryption)
+ *
+ * \param ctx      AES context to be initialized
+ * \param key      encryption key
+ * \param keybits  must be 128, 192 or 256
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
+ */
+int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
+                    unsigned int keybits );
+
+/**
+ * \brief          AES key schedule (decryption)
+ *
+ * \param ctx      AES context to be initialized
+ * \param key      decryption key
+ * \param keybits  must be 128, 192 or 256
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
+ */
+int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
+                    unsigned int keybits );
+
+/**
+ * \brief          AES-ECB block encryption/decryption
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param input    16-byte input block
+ * \param output   16-byte output block
+ *
+ * \return         0 if successful
+ */
+int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
+                    int mode,
+                    const unsigned char input[16],
+                    unsigned char output[16] );
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/**
+ * \brief          AES-CBC buffer encryption/decryption
+ *                 Length should be a multiple of the block
+ *                 size (16 bytes)
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH
+ */
+int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[16],
+                    const unsigned char *input,
+                    unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+#if defined(MBEDTLS_CIPHER_MODE_CFB)
+/**
+ * \brief          AES-CFB128 buffer encryption/decryption.
+ *
+ * Note: Due to the nature of CFB you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv_off   offset in IV (updated after use)
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful
+ */
+int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
+                       int mode,
+                       size_t length,
+                       size_t *iv_off,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+
+/**
+ * \brief          AES-CFB8 buffer encryption/decryption.
+ *
+ * Note: Due to the nature of CFB you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful
+ */
+int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[16],
+                    const unsigned char *input,
+                    unsigned char *output );
+#endif /*MBEDTLS_CIPHER_MODE_CFB */
+
+#if defined(MBEDTLS_CIPHER_MODE_CTR)
+/**
+ * \brief               AES-CTR buffer encryption/decryption
+ *
+ * Warning: You have to keep the maximum use of your counter in mind!
+ *
+ * Note: Due to the nature of CTR you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
+ *
+ * \param ctx           AES context
+ * \param length        The length of the data
+ * \param nc_off        The offset in the current stream_block (for resuming
+ *                      within current cipher stream). The offset pointer to
+ *                      should be 0 at the start of a stream.
+ * \param nonce_counter The 128-bit nonce and counter.
+ * \param stream_block  The saved stream-block for resuming. Is overwritten
+ *                      by the function.
+ * \param input         The input data stream
+ * \param output        The output data stream
+ *
+ * \return         0 if successful
+ */
+int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
+                       size_t length,
+                       size_t *nc_off,
+                       unsigned char nonce_counter[16],
+                       unsigned char stream_block[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CTR */
+
+/**
+ * \brief           Internal AES block encryption function
+ *                  (Only exposed to allow overriding it,
+ *                  see MBEDTLS_AES_ENCRYPT_ALT)
+ *
+ * \param ctx       AES context
+ * \param input     Plaintext block
+ * \param output    Output (ciphertext) block
+ */
+void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
+                          const unsigned char input[16],
+                          unsigned char output[16] );
+
+/**
+ * \brief           Internal AES block decryption function
+ *                  (Only exposed to allow overriding it,
+ *                  see MBEDTLS_AES_DECRYPT_ALT)
+ *
+ * \param ctx       AES context
+ * \param input     Ciphertext block
+ * \param output    Output (plaintext) block
+ */
+void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
+                          const unsigned char input[16],
+                          unsigned char output[16] );
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* MBEDTLS_AES_ALT */
+
+

From cedb9ee154dd9fbc2e27f813d8dce6056c4b2e47 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Thu, 25 Aug 2016 09:59:13 +0800
Subject: [PATCH 26/89] Integrate NUC472 SHA accelerator

---
 .../hal/TARGET_NUVOTON/TARGET_NUC472/crypto.c |  20 +
 .../hal/TARGET_NUVOTON/TARGET_NUC472/crypto.h |   2 +
 .../TARGET_NUVOTON/TARGET_NUC472/sha1_alt.c   | 104 ++++++
 .../TARGET_NUVOTON/TARGET_NUC472/sha1_alt.h   | 115 ++++++
 .../TARGET_NUC472/sha1_alt_sw.c               | 345 ++++++++++++++++++
 .../TARGET_NUC472/sha1_alt_sw.h               | 112 ++++++
 .../TARGET_NUVOTON/TARGET_NUC472/sha256_alt.c | 104 ++++++
 .../TARGET_NUVOTON/TARGET_NUC472/sha256_alt.h | 117 ++++++
 .../TARGET_NUC472/sha256_alt_sw.c             | 316 ++++++++++++++++
 .../TARGET_NUC472/sha256_alt_sw.h             | 115 ++++++
 .../TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.c | 236 ++++++++++++
 .../TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.h |  86 +++++
 12 files changed, 1672 insertions(+)
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt.c
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt.h
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt_sw.c
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt_sw.h
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt.c
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt.h
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt_sw.c
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt_sw.h
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.c
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.h

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.c
index 8d56325b0b4..20f80783a55 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.c
@@ -21,6 +21,7 @@
 #include "nu_bitutil.h"
 
 static int crypto_inited = 0;
+static int crypto_sha_hw_avail = 1;
 
 void crypto_init(void)
 {
@@ -40,3 +41,22 @@ void crypto_zeroize(void *v, size_t n)
         *p++ = 0;
     }
 }
+
+int crypto_sha_hw_acquire(void)
+{
+    if (crypto_sha_hw_avail) {
+        crypto_sha_hw_avail = 0;
+        return 1;
+    }
+    else {
+        return 0;
+    }
+    
+}
+
+void crypto_sha_hw_release(void)
+{
+    if (! crypto_sha_hw_avail) {
+        crypto_sha_hw_avail = 1;
+    }
+}
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.h
index 0f674651665..2585a9936b1 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.h
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.h
@@ -25,6 +25,8 @@ extern "C" {
 
 void crypto_init(void);
 void crypto_zeroize(void *v, size_t n);
+int crypto_sha_hw_acquire(void);
+void crypto_sha_hw_release(void);
 
 #ifdef __cplusplus
 }
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt.c
new file mode 100644
index 00000000000..374228406b4
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt.c
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "mbedtls/config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_SHA1_C)
+#if defined(MBEDTLS_SHA1_ALT)
+
+#include "sha1_alt.h"
+#include "crypto.h"
+
+void mbedtls_sha1_init(mbedtls_sha1_context *ctx)
+{
+    if (crypto_sha_hw_acquire()) {
+        ctx->mbedtls_sha1_init = mbedtls_sha1_hw_init;
+        ctx->mbedtls_sha1_free = mbedtls_sha1_hw_free;
+        ctx->mbedtls_sha1_clone = mbedtls_sha1_hw_clone;
+        ctx->mbedtls_sha1_starts = mbedtls_sha1_hw_starts;
+        ctx->mbedtls_sha1_update = mbedtls_sha1_hw_update;
+        ctx->mbedtls_sha1_finish = mbedtls_sha1_hw_finish;
+        ctx->mbedtls_sha1_process = mbedtls_sha1_hw_process;
+    }
+    else {
+        ctx->mbedtls_sha1_init = mbedtls_sha1_sw_init;
+        ctx->mbedtls_sha1_free = mbedtls_sha1_sw_free;
+        ctx->mbedtls_sha1_clone = mbedtls_sha1_sw_clone;
+        ctx->mbedtls_sha1_starts = mbedtls_sha1_sw_starts;
+        ctx->mbedtls_sha1_update = mbedtls_sha1_sw_update;
+        ctx->mbedtls_sha1_finish = mbedtls_sha1_sw_finish;
+        ctx->mbedtls_sha1_process = mbedtls_sha1_sw_process;
+    }
+    
+    ctx->mbedtls_sha1_init(ctx);
+}
+
+void mbedtls_sha1_free(mbedtls_sha1_context *ctx)
+{
+    if (ctx == NULL) {
+        return;
+    }
+
+    ctx->mbedtls_sha1_free(ctx);
+    
+    if (ctx->mbedtls_sha1_init == mbedtls_sha1_hw_init) {
+        crypto_sha_hw_release();
+    }
+}
+
+void mbedtls_sha1_clone(mbedtls_sha1_context *dst,
+                        const mbedtls_sha1_context *src)
+{
+    *dst = *src;
+}
+
+/*
+ * SHA-1 context setup
+ */
+void mbedtls_sha1_starts(mbedtls_sha1_context *ctx)
+{
+    ctx->mbedtls_sha1_starts(ctx);
+    
+    return;
+}
+
+/*
+ * SHA-1 process buffer
+ */
+void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen)
+{
+    ctx->mbedtls_sha1_update(ctx, input, ilen);
+}
+
+/*
+ * SHA-1 final digest
+ */
+void mbedtls_sha1_finish(mbedtls_sha1_context *ctx, unsigned char output[20])
+{
+    ctx->mbedtls_sha1_finish(ctx, output);
+}
+
+void mbedtls_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[64])
+{
+    ctx->mbedtls_sha1_process(ctx, data);
+}
+
+#endif /* MBEDTLS_SHA1_ALT */
+#endif /* MBEDTLS_SHA1_C */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt.h
new file mode 100644
index 00000000000..a4c3c7e5ccb
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt.h
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBEDTLS_SHA1_ALT_H
+#define MBEDTLS_SHA1_ALT_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_SHA1_C)
+#if defined(MBEDTLS_SHA1_ALT)
+
+#include "sha1.h"
+#include "sha_alt_hw.h"
+#include "sha1_alt_sw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct mbedtls_sha1_context_s;
+
+/**
+ * \brief          SHA-1 context structure
+ */
+typedef struct mbedtls_sha1_context_s
+{
+    union {
+        crypto_sha_context hw_ctx;
+        mbedtls_sha1_sw_context sw_ctx;
+    };
+    
+    void (*mbedtls_sha1_init)(struct mbedtls_sha1_context_s *ctx);
+    void (*mbedtls_sha1_free)(struct mbedtls_sha1_context_s *ctx);
+    void (*mbedtls_sha1_clone)(struct mbedtls_sha1_context_s *dst, const struct mbedtls_sha1_context_s *src);
+    void (*mbedtls_sha1_starts)(struct mbedtls_sha1_context_s *ctx);
+    void (*mbedtls_sha1_update)(struct mbedtls_sha1_context_s *ctx, const unsigned char *input, size_t ilen);
+    void (*mbedtls_sha1_finish)(struct mbedtls_sha1_context_s *ctx, unsigned char output[20]);
+    void (*mbedtls_sha1_process)(struct mbedtls_sha1_context_s *ctx, const unsigned char data[64]);
+}
+mbedtls_sha1_context;
+
+/**
+ * \brief          Initialize SHA-1 context
+ *
+ * \param ctx      SHA-1 context to be initialized
+ */
+void mbedtls_sha1_init( mbedtls_sha1_context *ctx );
+
+/**
+ * \brief          Clear SHA-1 context
+ *
+ * \param ctx      SHA-1 context to be cleared
+ */
+void mbedtls_sha1_free( mbedtls_sha1_context *ctx );
+
+/**
+ * \brief          Clone (the state of) a SHA-1 context
+ *
+ * \param dst      The destination context
+ * \param src      The context to be cloned
+ */
+void mbedtls_sha1_clone( mbedtls_sha1_context *dst,
+                         const mbedtls_sha1_context *src );
+
+/**
+ * \brief          SHA-1 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void mbedtls_sha1_starts( mbedtls_sha1_context *ctx );
+
+/**
+ * \brief          SHA-1 process buffer
+ *
+ * \param ctx      SHA-1 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_sha1_update( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen );
+
+/**
+ * \brief          SHA-1 final digest
+ *
+ * \param ctx      SHA-1 context
+ * \param output   SHA-1 checksum result
+ */
+void mbedtls_sha1_finish( mbedtls_sha1_context *ctx, unsigned char output[20] );
+
+/* Internal use */
+void mbedtls_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[64] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_SHA1_ALT */
+#endif /* MBEDTLS_SHA1_C */
+
+#endif /* sha1_alt.h */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt_sw.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt_sw.c
new file mode 100644
index 00000000000..946366e1b06
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt_sw.c
@@ -0,0 +1,345 @@
+/*
+ *  FIPS-180-1 compliant SHA-1 implementation
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+/*
+ *  The SHA-1 standard was published by NIST in 1993.
+ *
+ *  http://www.itl.nist.gov/fipspubs/fip180-1.htm
+ */
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "mbedtls/config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_SHA1_C)
+#if defined(MBEDTLS_SHA1_ALT)
+
+#include "mbedtls/sha1.h"
+
+#include <string.h>
+
+/* Implementation that should never be optimized out by the compiler */
+static void mbedtls_zeroize( void *v, size_t n ) {
+    volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
+}
+
+/*
+ * 32-bit integer manipulation macros (big endian)
+ */
+#ifndef GET_UINT32_BE
+#define GET_UINT32_BE(n,b,i)                            \
+{                                                       \
+    (n) = ( (uint32_t) (b)[(i)    ] << 24 )             \
+        | ( (uint32_t) (b)[(i) + 1] << 16 )             \
+        | ( (uint32_t) (b)[(i) + 2] <<  8 )             \
+        | ( (uint32_t) (b)[(i) + 3]       );            \
+}
+#endif
+
+#ifndef PUT_UINT32_BE
+#define PUT_UINT32_BE(n,b,i)                            \
+{                                                       \
+    (b)[(i)    ] = (unsigned char) ( (n) >> 24 );       \
+    (b)[(i) + 1] = (unsigned char) ( (n) >> 16 );       \
+    (b)[(i) + 2] = (unsigned char) ( (n) >>  8 );       \
+    (b)[(i) + 3] = (unsigned char) ( (n)       );       \
+}
+#endif
+
+void mbedtls_sha1_sw_init( mbedtls_sha1_context *ctx )
+{
+    memset( &ctx->sw_ctx, 0, sizeof( ctx->sw_ctx ) );
+}
+
+void mbedtls_sha1_sw_free( mbedtls_sha1_context *ctx )
+{
+    if( ctx == NULL )
+        return;
+
+    mbedtls_zeroize( &ctx->sw_ctx, sizeof( ctx->sw_ctx ) );
+}
+
+void mbedtls_sha1_sw_clone( mbedtls_sha1_context *dst,
+                         const mbedtls_sha1_context *src )
+{
+    dst->sw_ctx = src->sw_ctx;
+}
+
+/*
+ * SHA-1 context setup
+ */
+void mbedtls_sha1_sw_starts( mbedtls_sha1_context *ctx_ )
+{
+    mbedtls_sha1_sw_context *ctx = &ctx_->sw_ctx;
+    
+    ctx->total[0] = 0;
+    ctx->total[1] = 0;
+
+    ctx->state[0] = 0x67452301;
+    ctx->state[1] = 0xEFCDAB89;
+    ctx->state[2] = 0x98BADCFE;
+    ctx->state[3] = 0x10325476;
+    ctx->state[4] = 0xC3D2E1F0;
+}
+
+void mbedtls_sha1_sw_process( mbedtls_sha1_context *ctx_, const unsigned char data[64] )
+{
+    mbedtls_sha1_sw_context *ctx = &ctx_->sw_ctx;
+    
+    uint32_t temp, W[16], A, B, C, D, E;
+
+    GET_UINT32_BE( W[ 0], data,  0 );
+    GET_UINT32_BE( W[ 1], data,  4 );
+    GET_UINT32_BE( W[ 2], data,  8 );
+    GET_UINT32_BE( W[ 3], data, 12 );
+    GET_UINT32_BE( W[ 4], data, 16 );
+    GET_UINT32_BE( W[ 5], data, 20 );
+    GET_UINT32_BE( W[ 6], data, 24 );
+    GET_UINT32_BE( W[ 7], data, 28 );
+    GET_UINT32_BE( W[ 8], data, 32 );
+    GET_UINT32_BE( W[ 9], data, 36 );
+    GET_UINT32_BE( W[10], data, 40 );
+    GET_UINT32_BE( W[11], data, 44 );
+    GET_UINT32_BE( W[12], data, 48 );
+    GET_UINT32_BE( W[13], data, 52 );
+    GET_UINT32_BE( W[14], data, 56 );
+    GET_UINT32_BE( W[15], data, 60 );
+
+#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
+
+#define R(t)                                            \
+(                                                       \
+    temp = W[( t -  3 ) & 0x0F] ^ W[( t - 8 ) & 0x0F] ^ \
+           W[( t - 14 ) & 0x0F] ^ W[  t       & 0x0F],  \
+    ( W[t & 0x0F] = S(temp,1) )                         \
+)
+
+#define P(a,b,c,d,e,x)                                  \
+{                                                       \
+    e += S(a,5) + F(b,c,d) + K + x; b = S(b,30);        \
+}
+
+    A = ctx->state[0];
+    B = ctx->state[1];
+    C = ctx->state[2];
+    D = ctx->state[3];
+    E = ctx->state[4];
+
+#define F(x,y,z) (z ^ (x & (y ^ z)))
+#define K 0x5A827999
+
+    P( A, B, C, D, E, W[0]  );
+    P( E, A, B, C, D, W[1]  );
+    P( D, E, A, B, C, W[2]  );
+    P( C, D, E, A, B, W[3]  );
+    P( B, C, D, E, A, W[4]  );
+    P( A, B, C, D, E, W[5]  );
+    P( E, A, B, C, D, W[6]  );
+    P( D, E, A, B, C, W[7]  );
+    P( C, D, E, A, B, W[8]  );
+    P( B, C, D, E, A, W[9]  );
+    P( A, B, C, D, E, W[10] );
+    P( E, A, B, C, D, W[11] );
+    P( D, E, A, B, C, W[12] );
+    P( C, D, E, A, B, W[13] );
+    P( B, C, D, E, A, W[14] );
+    P( A, B, C, D, E, W[15] );
+    P( E, A, B, C, D, R(16) );
+    P( D, E, A, B, C, R(17) );
+    P( C, D, E, A, B, R(18) );
+    P( B, C, D, E, A, R(19) );
+
+#undef K
+#undef F
+
+#define F(x,y,z) (x ^ y ^ z)
+#define K 0x6ED9EBA1
+
+    P( A, B, C, D, E, R(20) );
+    P( E, A, B, C, D, R(21) );
+    P( D, E, A, B, C, R(22) );
+    P( C, D, E, A, B, R(23) );
+    P( B, C, D, E, A, R(24) );
+    P( A, B, C, D, E, R(25) );
+    P( E, A, B, C, D, R(26) );
+    P( D, E, A, B, C, R(27) );
+    P( C, D, E, A, B, R(28) );
+    P( B, C, D, E, A, R(29) );
+    P( A, B, C, D, E, R(30) );
+    P( E, A, B, C, D, R(31) );
+    P( D, E, A, B, C, R(32) );
+    P( C, D, E, A, B, R(33) );
+    P( B, C, D, E, A, R(34) );
+    P( A, B, C, D, E, R(35) );
+    P( E, A, B, C, D, R(36) );
+    P( D, E, A, B, C, R(37) );
+    P( C, D, E, A, B, R(38) );
+    P( B, C, D, E, A, R(39) );
+
+#undef K
+#undef F
+
+#define F(x,y,z) ((x & y) | (z & (x | y)))
+#define K 0x8F1BBCDC
+
+    P( A, B, C, D, E, R(40) );
+    P( E, A, B, C, D, R(41) );
+    P( D, E, A, B, C, R(42) );
+    P( C, D, E, A, B, R(43) );
+    P( B, C, D, E, A, R(44) );
+    P( A, B, C, D, E, R(45) );
+    P( E, A, B, C, D, R(46) );
+    P( D, E, A, B, C, R(47) );
+    P( C, D, E, A, B, R(48) );
+    P( B, C, D, E, A, R(49) );
+    P( A, B, C, D, E, R(50) );
+    P( E, A, B, C, D, R(51) );
+    P( D, E, A, B, C, R(52) );
+    P( C, D, E, A, B, R(53) );
+    P( B, C, D, E, A, R(54) );
+    P( A, B, C, D, E, R(55) );
+    P( E, A, B, C, D, R(56) );
+    P( D, E, A, B, C, R(57) );
+    P( C, D, E, A, B, R(58) );
+    P( B, C, D, E, A, R(59) );
+
+#undef K
+#undef F
+
+#define F(x,y,z) (x ^ y ^ z)
+#define K 0xCA62C1D6
+
+    P( A, B, C, D, E, R(60) );
+    P( E, A, B, C, D, R(61) );
+    P( D, E, A, B, C, R(62) );
+    P( C, D, E, A, B, R(63) );
+    P( B, C, D, E, A, R(64) );
+    P( A, B, C, D, E, R(65) );
+    P( E, A, B, C, D, R(66) );
+    P( D, E, A, B, C, R(67) );
+    P( C, D, E, A, B, R(68) );
+    P( B, C, D, E, A, R(69) );
+    P( A, B, C, D, E, R(70) );
+    P( E, A, B, C, D, R(71) );
+    P( D, E, A, B, C, R(72) );
+    P( C, D, E, A, B, R(73) );
+    P( B, C, D, E, A, R(74) );
+    P( A, B, C, D, E, R(75) );
+    P( E, A, B, C, D, R(76) );
+    P( D, E, A, B, C, R(77) );
+    P( C, D, E, A, B, R(78) );
+    P( B, C, D, E, A, R(79) );
+
+#undef K
+#undef F
+
+    ctx->state[0] += A;
+    ctx->state[1] += B;
+    ctx->state[2] += C;
+    ctx->state[3] += D;
+    ctx->state[4] += E;
+}
+
+/*
+ * SHA-1 process buffer
+ */
+void mbedtls_sha1_sw_update( mbedtls_sha1_context *ctx_, const unsigned char *input, size_t ilen )
+{
+    mbedtls_sha1_sw_context *ctx = &ctx_->sw_ctx;
+    
+    size_t fill;
+    uint32_t left;
+
+    if( ilen == 0 )
+        return;
+
+    left = ctx->total[0] & 0x3F;
+    fill = 64 - left;
+
+    ctx->total[0] += (uint32_t) ilen;
+    ctx->total[0] &= 0xFFFFFFFF;
+
+    if( ctx->total[0] < (uint32_t) ilen )
+        ctx->total[1]++;
+
+    if( left && ilen >= fill )
+    {
+        memcpy( (void *) (ctx->buffer + left), input, fill );
+        mbedtls_sha1_sw_process( ctx_, ctx->buffer );
+        input += fill;
+        ilen  -= fill;
+        left = 0;
+    }
+
+    while( ilen >= 64 )
+    {
+        mbedtls_sha1_sw_process( ctx_, input );
+        input += 64;
+        ilen  -= 64;
+    }
+
+    if( ilen > 0 )
+        memcpy( (void *) (ctx->buffer + left), input, ilen );
+}
+
+static const unsigned char sha1_padding[64] =
+{
+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*
+ * SHA-1 final digest
+ */
+void mbedtls_sha1_sw_finish( mbedtls_sha1_context *ctx_, unsigned char output[20] )
+{
+    mbedtls_sha1_sw_context *ctx = &ctx_->sw_ctx;
+    
+    uint32_t last, padn;
+    uint32_t high, low;
+    unsigned char msglen[8];
+
+    high = ( ctx->total[0] >> 29 )
+         | ( ctx->total[1] <<  3 );
+    low  = ( ctx->total[0] <<  3 );
+
+    PUT_UINT32_BE( high, msglen, 0 );
+    PUT_UINT32_BE( low,  msglen, 4 );
+
+    last = ctx->total[0] & 0x3F;
+    padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
+
+    mbedtls_sha1_sw_update( ctx_, sha1_padding, padn );
+    mbedtls_sha1_sw_update( ctx_, msglen, 8 );
+
+    PUT_UINT32_BE( ctx->state[0], output,  0 );
+    PUT_UINT32_BE( ctx->state[1], output,  4 );
+    PUT_UINT32_BE( ctx->state[2], output,  8 );
+    PUT_UINT32_BE( ctx->state[3], output, 12 );
+    PUT_UINT32_BE( ctx->state[4], output, 16 );
+}
+
+#endif /* MBEDTLS_SHA1_ALT */
+
+#endif /* MBEDTLS_SHA1_C */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt_sw.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt_sw.h
new file mode 100644
index 00000000000..4b0ab56f509
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt_sw.h
@@ -0,0 +1,112 @@
+/**
+ * \file sha1.h
+ *
+ * \brief SHA-1 cryptographic hash function
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_SHA1_ALT_SW_H
+#define MBEDTLS_SHA1_ALT_SW_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_SHA1_C)
+#if defined(MBEDTLS_SHA1_ALT)
+
+#include <stddef.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct mbedtls_sha1_context_s;
+
+/**
+ * \brief          SHA-1 context structure
+ */
+typedef struct
+{
+    uint32_t total[2];          /*!< number of bytes processed  */
+    uint32_t state[5];          /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+}
+mbedtls_sha1_sw_context;
+
+/**
+ * \brief          Initialize SHA-1 context
+ *
+ * \param ctx      SHA-1 context to be initialized
+ */
+void mbedtls_sha1_sw_init( struct mbedtls_sha1_context_s *ctx );
+
+/**
+ * \brief          Clear SHA-1 context
+ *
+ * \param ctx      SHA-1 context to be cleared
+ */
+void mbedtls_sha1_sw_free( struct mbedtls_sha1_context_s *ctx );
+
+/**
+ * \brief          Clone (the state of) a SHA-1 context
+ *
+ * \param dst      The destination context
+ * \param src      The context to be cloned
+ */
+void mbedtls_sha1_sw_clone( struct mbedtls_sha1_context_s *dst,
+                         const struct mbedtls_sha1_context_s *src );
+
+/**
+ * \brief          SHA-1 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void mbedtls_sha1_sw_starts( struct mbedtls_sha1_context_s *ctx );
+
+/**
+ * \brief          SHA-1 process buffer
+ *
+ * \param ctx      SHA-1 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_sha1_sw_update( struct mbedtls_sha1_context_s *ctx, const unsigned char *input, size_t ilen );
+
+/**
+ * \brief          SHA-1 final digest
+ *
+ * \param ctx      SHA-1 context
+ * \param output   SHA-1 checksum result
+ */
+void mbedtls_sha1_sw_finish( struct mbedtls_sha1_context_s *ctx, unsigned char output[20] );
+
+/* Internal use */
+void mbedtls_sha1_sw_process( struct mbedtls_sha1_context_s *ctx, const unsigned char data[64] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_SHA1_ALT */
+#endif /* MBEDTLS_SHA1_C */
+
+#endif /* sha1_alt_sw.h */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt.c
new file mode 100644
index 00000000000..80e19f74063
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt.c
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "mbedtls/config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_SHA256_C)
+#if defined(MBEDTLS_SHA256_ALT)
+
+#include "sha256_alt.h"
+#include "crypto.h"
+
+void mbedtls_sha256_init(mbedtls_sha256_context *ctx)
+{
+    if (crypto_sha_hw_acquire()) {
+        ctx->mbedtls_sha256_init = mbedtls_sha256_hw_init;
+        ctx->mbedtls_sha256_free = mbedtls_sha256_hw_free;
+        ctx->mbedtls_sha256_clone = mbedtls_sha256_hw_clone;
+        ctx->mbedtls_sha256_starts = mbedtls_sha256_hw_starts;
+        ctx->mbedtls_sha256_update = mbedtls_sha256_hw_update;
+        ctx->mbedtls_sha256_finish = mbedtls_sha256_hw_finish;
+        ctx->mbedtls_sha256_process = mbedtls_sha256_hw_process;
+    }
+    else {
+        ctx->mbedtls_sha256_init = mbedtls_sha256_sw_init;
+        ctx->mbedtls_sha256_free = mbedtls_sha256_sw_free;
+        ctx->mbedtls_sha256_clone = mbedtls_sha256_sw_clone;
+        ctx->mbedtls_sha256_starts = mbedtls_sha256_sw_starts;
+        ctx->mbedtls_sha256_update = mbedtls_sha256_sw_update;
+        ctx->mbedtls_sha256_finish = mbedtls_sha256_sw_finish;
+        ctx->mbedtls_sha256_process = mbedtls_sha256_sw_process;
+    }
+    
+    ctx->mbedtls_sha256_init(ctx);
+}
+
+void mbedtls_sha256_free(mbedtls_sha256_context *ctx)
+{
+    if (ctx == NULL) {
+        return;
+    }
+
+    ctx->mbedtls_sha256_free(ctx);
+    
+    if (ctx->mbedtls_sha256_init == mbedtls_sha256_hw_init) {
+        crypto_sha_hw_release();
+    }
+}
+
+void mbedtls_sha256_clone(mbedtls_sha256_context *dst,
+                        const mbedtls_sha256_context *src)
+{
+    *dst = *src;
+}
+
+/*
+ * SHA-256 context setup
+ */
+void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224)
+{   
+    ctx->mbedtls_sha256_starts(ctx, is224);
+    
+    return;
+}
+
+/*
+ * SHA-256 process buffer
+ */
+void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen)
+{
+    ctx->mbedtls_sha256_update(ctx, input, ilen);
+}
+
+/*
+ * SHA-256 final digest
+ */
+void mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char output[20])
+{
+    ctx->mbedtls_sha256_finish(ctx, output);
+}
+
+void mbedtls_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[64])
+{
+    ctx->mbedtls_sha256_process(ctx, data);
+}
+
+#endif /* MBEDTLS_SHA256_ALT */
+#endif /* MBEDTLS_SHA256_C */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt.h
new file mode 100644
index 00000000000..4274fc86f33
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt.h
@@ -0,0 +1,117 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBEDTLS_SHA256_ALT_H
+#define MBEDTLS_SHA256_ALT_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_SHA1_C)
+#if defined(MBEDTLS_SHA256_ALT)
+
+#include "sha256.h"
+#include "sha_alt_hw.h"
+#include "sha256_alt_sw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct mbedtls_sha256_context_s;
+
+/**
+ * \brief          SHA-256 context structure
+ */
+typedef struct mbedtls_sha256_context_s
+{
+    union {
+        crypto_sha_context hw_ctx;
+        mbedtls_sha256_sw_context sw_ctx;
+    };
+    
+    void (*mbedtls_sha256_init)(struct mbedtls_sha256_context_s *ctx);
+    void (*mbedtls_sha256_free)(struct mbedtls_sha256_context_s *ctx);
+    void (*mbedtls_sha256_clone)(struct mbedtls_sha256_context_s *dst, const struct mbedtls_sha256_context_s *src);
+    void (*mbedtls_sha256_starts)(struct mbedtls_sha256_context_s *ctx, int is224);
+    void (*mbedtls_sha256_update)(struct mbedtls_sha256_context_s *ctx, const unsigned char *input, size_t ilen);
+    void (*mbedtls_sha256_finish)(struct mbedtls_sha256_context_s *ctx, unsigned char output[20]);
+    void (*mbedtls_sha256_process)(struct mbedtls_sha256_context_s *ctx, const unsigned char data[64]);
+}
+mbedtls_sha256_context;
+
+/**
+ * \brief          Initialize SHA-256 context
+ *
+ * \param ctx      SHA-256 context to be initialized
+ */
+void mbedtls_sha256_init( mbedtls_sha256_context *ctx );
+
+/**
+ * \brief          Clear SHA-256 context
+ *
+ * \param ctx      SHA-256 context to be cleared
+ */
+void mbedtls_sha256_free( mbedtls_sha256_context *ctx );
+
+/**
+ * \brief          Clone (the state of) a SHA-256 context
+ *
+ * \param dst      The destination context
+ * \param src      The context to be cloned
+ */
+void mbedtls_sha256_clone( mbedtls_sha256_context *dst,
+                           const mbedtls_sha256_context *src );
+
+/**
+ * \brief          SHA-256 context setup
+ *
+ * \param ctx      context to be initialized
+ * \param is224    0 = use SHA256, 1 = use SHA224
+ */
+void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, int is224 );
+
+/**
+ * \brief          SHA-256 process buffer
+ *
+ * \param ctx      SHA-256 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_sha256_update( mbedtls_sha256_context *ctx, const unsigned char *input,
+                    size_t ilen );
+
+/**
+ * \brief          SHA-256 final digest
+ *
+ * \param ctx      SHA-256 context
+ * \param output   SHA-224/256 checksum result
+ */
+void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, unsigned char output[32] );
+
+/* Internal use */
+void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[64] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_SHA256_ALT */
+#endif /* MBEDTLS_SHA1_C */
+
+#endif /* sha256_alt.h */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt_sw.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt_sw.c
new file mode 100644
index 00000000000..5d5a252c4af
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt_sw.c
@@ -0,0 +1,316 @@
+/*
+ *  FIPS-180-2 compliant SHA-256 implementation
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+/*
+ *  The SHA-256 Secure Hash Standard was published by NIST in 2002.
+ *
+ *  http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf
+ */
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "mbedtls/config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_SHA256_C)
+#if defined(MBEDTLS_SHA256_ALT)
+
+#include "mbedtls/sha256.h"
+
+#include <string.h>
+
+/* Implementation that should never be optimized out by the compiler */
+static void mbedtls_zeroize( void *v, size_t n ) {
+    volatile unsigned char *p = v; while( n-- ) *p++ = 0;
+}
+
+/*
+ * 32-bit integer manipulation macros (big endian)
+ */
+#ifndef GET_UINT32_BE
+#define GET_UINT32_BE(n,b,i)                            \
+do {                                                    \
+    (n) = ( (uint32_t) (b)[(i)    ] << 24 )             \
+        | ( (uint32_t) (b)[(i) + 1] << 16 )             \
+        | ( (uint32_t) (b)[(i) + 2] <<  8 )             \
+        | ( (uint32_t) (b)[(i) + 3]       );            \
+} while( 0 )
+#endif
+
+#ifndef PUT_UINT32_BE
+#define PUT_UINT32_BE(n,b,i)                            \
+do {                                                    \
+    (b)[(i)    ] = (unsigned char) ( (n) >> 24 );       \
+    (b)[(i) + 1] = (unsigned char) ( (n) >> 16 );       \
+    (b)[(i) + 2] = (unsigned char) ( (n) >>  8 );       \
+    (b)[(i) + 3] = (unsigned char) ( (n)       );       \
+} while( 0 )
+#endif
+
+void mbedtls_sha256_sw_init( mbedtls_sha256_context *ctx )
+{
+    memset( &ctx->sw_ctx, 0, sizeof( ctx->sw_ctx ) );
+}
+
+void mbedtls_sha256_sw_free( mbedtls_sha256_context *ctx )
+{
+    if( ctx == NULL )
+        return;
+
+    mbedtls_zeroize( &ctx->sw_ctx, sizeof( ctx->sw_ctx ) );
+}
+
+void mbedtls_sha256_sw_clone( mbedtls_sha256_context *dst,
+                           const mbedtls_sha256_context *src )
+{
+    dst->sw_ctx = src->sw_ctx;
+}
+
+/*
+ * SHA-256 context setup
+ */
+void mbedtls_sha256_sw_starts( mbedtls_sha256_context *ctx_, int is224 )
+{
+    mbedtls_sha256_sw_context *ctx = &ctx_->sw_ctx;
+    
+    ctx->total[0] = 0;
+    ctx->total[1] = 0;
+
+    if( is224 == 0 )
+    {
+        /* SHA-256 */
+        ctx->state[0] = 0x6A09E667;
+        ctx->state[1] = 0xBB67AE85;
+        ctx->state[2] = 0x3C6EF372;
+        ctx->state[3] = 0xA54FF53A;
+        ctx->state[4] = 0x510E527F;
+        ctx->state[5] = 0x9B05688C;
+        ctx->state[6] = 0x1F83D9AB;
+        ctx->state[7] = 0x5BE0CD19;
+    }
+    else
+    {
+        /* SHA-224 */
+        ctx->state[0] = 0xC1059ED8;
+        ctx->state[1] = 0x367CD507;
+        ctx->state[2] = 0x3070DD17;
+        ctx->state[3] = 0xF70E5939;
+        ctx->state[4] = 0xFFC00B31;
+        ctx->state[5] = 0x68581511;
+        ctx->state[6] = 0x64F98FA7;
+        ctx->state[7] = 0xBEFA4FA4;
+    }
+
+    ctx->is224 = is224;
+}
+
+static const uint32_t K[] =
+{
+    0x428A2F98, 0x71374491, 0xB5C0FBCF, 0xE9B5DBA5,
+    0x3956C25B, 0x59F111F1, 0x923F82A4, 0xAB1C5ED5,
+    0xD807AA98, 0x12835B01, 0x243185BE, 0x550C7DC3,
+    0x72BE5D74, 0x80DEB1FE, 0x9BDC06A7, 0xC19BF174,
+    0xE49B69C1, 0xEFBE4786, 0x0FC19DC6, 0x240CA1CC,
+    0x2DE92C6F, 0x4A7484AA, 0x5CB0A9DC, 0x76F988DA,
+    0x983E5152, 0xA831C66D, 0xB00327C8, 0xBF597FC7,
+    0xC6E00BF3, 0xD5A79147, 0x06CA6351, 0x14292967,
+    0x27B70A85, 0x2E1B2138, 0x4D2C6DFC, 0x53380D13,
+    0x650A7354, 0x766A0ABB, 0x81C2C92E, 0x92722C85,
+    0xA2BFE8A1, 0xA81A664B, 0xC24B8B70, 0xC76C51A3,
+    0xD192E819, 0xD6990624, 0xF40E3585, 0x106AA070,
+    0x19A4C116, 0x1E376C08, 0x2748774C, 0x34B0BCB5,
+    0x391C0CB3, 0x4ED8AA4A, 0x5B9CCA4F, 0x682E6FF3,
+    0x748F82EE, 0x78A5636F, 0x84C87814, 0x8CC70208,
+    0x90BEFFFA, 0xA4506CEB, 0xBEF9A3F7, 0xC67178F2,
+};
+
+#define  SHR(x,n) ((x & 0xFFFFFFFF) >> n)
+#define ROTR(x,n) (SHR(x,n) | (x << (32 - n)))
+
+#define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^  SHR(x, 3))
+#define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^  SHR(x,10))
+
+#define S2(x) (ROTR(x, 2) ^ ROTR(x,13) ^ ROTR(x,22))
+#define S3(x) (ROTR(x, 6) ^ ROTR(x,11) ^ ROTR(x,25))
+
+#define F0(x,y,z) ((x & y) | (z & (x | y)))
+#define F1(x,y,z) (z ^ (x & (y ^ z)))
+
+#define R(t)                                    \
+(                                               \
+    W[t] = S1(W[t -  2]) + W[t -  7] +          \
+           S0(W[t - 15]) + W[t - 16]            \
+)
+
+#define P(a,b,c,d,e,f,g,h,x,K)                  \
+{                                               \
+    temp1 = h + S3(e) + F1(e,f,g) + K + x;      \
+    temp2 = S2(a) + F0(a,b,c);                  \
+    d += temp1; h = temp1 + temp2;              \
+}
+
+void mbedtls_sha256_sw_process( mbedtls_sha256_context *ctx_, const unsigned char data[64] )
+{
+    mbedtls_sha256_sw_context *ctx = &ctx_->sw_ctx;
+    
+    uint32_t temp1, temp2, W[64];
+    uint32_t A[8];
+    unsigned int i;
+
+    for( i = 0; i < 8; i++ )
+        A[i] = ctx->state[i];
+
+#if defined(MBEDTLS_SHA256_SMALLER)
+    for( i = 0; i < 64; i++ )
+    {
+        if( i < 16 )
+            GET_UINT32_BE( W[i], data, 4 * i );
+        else
+            R( i );
+
+        P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i], K[i] );
+
+        temp1 = A[7]; A[7] = A[6]; A[6] = A[5]; A[5] = A[4]; A[4] = A[3];
+        A[3] = A[2]; A[2] = A[1]; A[1] = A[0]; A[0] = temp1;
+    }
+#else /* MBEDTLS_SHA256_SMALLER */
+    for( i = 0; i < 16; i++ )
+        GET_UINT32_BE( W[i], data, 4 * i );
+
+    for( i = 0; i < 16; i += 8 )
+    {
+        P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i+0], K[i+0] );
+        P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], W[i+1], K[i+1] );
+        P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], W[i+2], K[i+2] );
+        P( A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], W[i+3], K[i+3] );
+        P( A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], W[i+4], K[i+4] );
+        P( A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], W[i+5], K[i+5] );
+        P( A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], W[i+6], K[i+6] );
+        P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], W[i+7], K[i+7] );
+    }
+
+    for( i = 16; i < 64; i += 8 )
+    {
+        P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], R(i+0), K[i+0] );
+        P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], R(i+1), K[i+1] );
+        P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], R(i+2), K[i+2] );
+        P( A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], R(i+3), K[i+3] );
+        P( A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], R(i+4), K[i+4] );
+        P( A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], R(i+5), K[i+5] );
+        P( A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], R(i+6), K[i+6] );
+        P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], R(i+7), K[i+7] );
+    }
+#endif /* MBEDTLS_SHA256_SMALLER */
+
+    for( i = 0; i < 8; i++ )
+        ctx->state[i] += A[i];
+}
+
+/*
+ * SHA-256 process buffer
+ */
+void mbedtls_sha256_sw_update( mbedtls_sha256_context *ctx_, const unsigned char *input,
+                    size_t ilen )
+{
+    mbedtls_sha256_sw_context *ctx = &ctx_->sw_ctx;
+    
+    size_t fill;
+    uint32_t left;
+
+    if( ilen == 0 )
+        return;
+
+    left = ctx->total[0] & 0x3F;
+    fill = 64 - left;
+
+    ctx->total[0] += (uint32_t) ilen;
+    ctx->total[0] &= 0xFFFFFFFF;
+
+    if( ctx->total[0] < (uint32_t) ilen )
+        ctx->total[1]++;
+
+    if( left && ilen >= fill )
+    {
+        memcpy( (void *) (ctx->buffer + left), input, fill );
+        mbedtls_sha256_sw_process( ctx_, ctx->buffer );
+        input += fill;
+        ilen  -= fill;
+        left = 0;
+    }
+
+    while( ilen >= 64 )
+    {
+        mbedtls_sha256_sw_process( ctx_, input );
+        input += 64;
+        ilen  -= 64;
+    }
+
+    if( ilen > 0 )
+        memcpy( (void *) (ctx->buffer + left), input, ilen );
+}
+
+static const unsigned char sha256_padding[64] =
+{
+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*
+ * SHA-256 final digest
+ */
+void mbedtls_sha256_sw_finish( mbedtls_sha256_context *ctx_, unsigned char output[32] )
+{
+    mbedtls_sha256_sw_context *ctx = &ctx_->sw_ctx;
+    
+    uint32_t last, padn;
+    uint32_t high, low;
+    unsigned char msglen[8];
+
+    high = ( ctx->total[0] >> 29 )
+         | ( ctx->total[1] <<  3 );
+    low  = ( ctx->total[0] <<  3 );
+
+    PUT_UINT32_BE( high, msglen, 0 );
+    PUT_UINT32_BE( low,  msglen, 4 );
+
+    last = ctx->total[0] & 0x3F;
+    padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
+
+    mbedtls_sha256_sw_update( ctx_, sha256_padding, padn );
+    mbedtls_sha256_sw_update( ctx_, msglen, 8 );
+
+    PUT_UINT32_BE( ctx->state[0], output,  0 );
+    PUT_UINT32_BE( ctx->state[1], output,  4 );
+    PUT_UINT32_BE( ctx->state[2], output,  8 );
+    PUT_UINT32_BE( ctx->state[3], output, 12 );
+    PUT_UINT32_BE( ctx->state[4], output, 16 );
+    PUT_UINT32_BE( ctx->state[5], output, 20 );
+    PUT_UINT32_BE( ctx->state[6], output, 24 );
+
+    if( ctx->is224 == 0 )
+        PUT_UINT32_BE( ctx->state[7], output, 28 );
+}
+
+#endif /* MBEDTLS_SHA1_ALT */
+
+#endif /* MBEDTLS_SHA256_C */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt_sw.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt_sw.h
new file mode 100644
index 00000000000..938b5920fcc
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt_sw.h
@@ -0,0 +1,115 @@
+/**
+ * \file sha256.h
+ *
+ * \brief SHA-224 and SHA-256 cryptographic hash function
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_SHA256_ALT_SW_H
+#define MBEDTLS_SHA256_ALT_SW_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_SHA256_C)
+#if defined(MBEDTLS_SHA256_ALT)
+
+#include <stddef.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct mbedtls_sha256_context_s;
+
+/**
+ * \brief          SHA-256 context structure
+ */
+typedef struct
+{
+    uint32_t total[2];          /*!< number of bytes processed  */
+    uint32_t state[8];          /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+    int is224;                  /*!< 0 => SHA-256, else SHA-224 */
+}
+mbedtls_sha256_sw_context;
+
+/**
+ * \brief          Initialize SHA-256 context
+ *
+ * \param ctx      SHA-256 context to be initialized
+ */
+void mbedtls_sha256_sw_init( struct mbedtls_sha256_context_s *ctx );
+
+/**
+ * \brief          Clear SHA-256 context
+ *
+ * \param ctx      SHA-256 context to be cleared
+ */
+void mbedtls_sha256_sw_free( struct mbedtls_sha256_context_s *ctx );
+
+/**
+ * \brief          Clone (the state of) a SHA-256 context
+ *
+ * \param dst      The destination context
+ * \param src      The context to be cloned
+ */
+void mbedtls_sha256_sw_clone( struct mbedtls_sha256_context_s *dst,
+                           const struct mbedtls_sha256_context_s *src );
+
+/**
+ * \brief          SHA-256 context setup
+ *
+ * \param ctx      context to be initialized
+ * \param is224    0 = use SHA256, 1 = use SHA224
+ */
+void mbedtls_sha256_sw_starts( struct mbedtls_sha256_context_s *ctx, int is224 );
+
+/**
+ * \brief          SHA-256 process buffer
+ *
+ * \param ctx      SHA-256 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_sha256_sw_update( struct mbedtls_sha256_context_s *ctx, const unsigned char *input,
+                    size_t ilen );
+
+/**
+ * \brief          SHA-256 final digest
+ *
+ * \param ctx      SHA-256 context
+ * \param output   SHA-224/256 checksum result
+ */
+void mbedtls_sha256_sw_finish( struct mbedtls_sha256_context_s *ctx, unsigned char output[32] );
+
+/* Internal use */
+void mbedtls_sha256_sw_process( struct mbedtls_sha256_context_s *ctx, const unsigned char data[64] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_SHA256_ALT */
+#endif /* MBEDTLS_SHA256_C */
+
+#endif /* sha256_alt_sw.h */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.c
new file mode 100644
index 00000000000..99151713bef
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.c
@@ -0,0 +1,236 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "mbedtls/config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C)
+
+#if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT)
+
+#if defined(MBEDTLS_SHA1_ALT)
+#include "sha1_alt.h"
+#endif /* MBEDTLS_SHA1_ALT */
+
+#if defined(MBEDTLS_SHA256_ALT)
+#include "sha256_alt.h"
+#endif /* MBEDTLS_SHA256_ALT */
+
+#if defined(MBEDTLS_SHA512_ALT)
+#include "sha512_alt.h"
+#endif /* MBEDTLS_SHA512_ALT */
+
+#include "nu_bitutil.h"
+#include "mbed_assert.h"
+#include "crypto.h"
+
+#include <string.h>
+
+static void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen);
+static void crypto_sha_getinternstate(unsigned char output[], size_t olen);
+static void crypto_sha_lastword(crypto_sha_context *ctx, int islast);
+
+#endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */
+
+#if defined(MBEDTLS_SHA1_ALT)
+
+void mbedtls_sha1_hw_init(mbedtls_sha1_context *ctx)
+{
+    crypto_init();
+    memset(&ctx->hw_ctx, 0, sizeof(ctx->hw_ctx));
+}
+
+void mbedtls_sha1_hw_free(mbedtls_sha1_context *ctx)
+{
+    if (ctx == NULL) {
+        return;
+    }
+
+    crypto_zeroize(&ctx->hw_ctx, sizeof(ctx->hw_ctx));
+}
+
+void mbedtls_sha1_hw_clone(mbedtls_sha1_context *dst,
+                        const mbedtls_sha1_context *src)
+{
+    dst->hw_ctx = src->hw_ctx;
+}
+
+void mbedtls_sha1_hw_starts(mbedtls_sha1_context *ctx)
+{
+    ctx->hw_ctx.total = 0;
+    ctx->hw_ctx.lastword_size = 0;
+    ctx->hw_ctx.blocksize = 64;
+    ctx->hw_ctx.blocksize_mask = 0x3F;
+
+    SHA_Open(SHA_MODE_SHA1, SHA_NO_SWAP);
+    
+    return;
+}
+
+void mbedtls_sha1_hw_update(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen)
+{
+    crypto_sha_update(&ctx->hw_ctx, input, ilen);
+}
+
+void mbedtls_sha1_hw_finish(mbedtls_sha1_context *ctx, unsigned char output[20])
+{
+    crypto_sha_lastword(&ctx->hw_ctx, 1);
+    crypto_sha_getinternstate(output, 20);
+}
+
+void mbedtls_sha1_hw_process(mbedtls_sha1_context *ctx, const unsigned char data[64])
+{
+    mbedtls_sha1_hw_update(ctx, data, 64);
+}
+
+#endif /* MBEDTLS_SHA1_ALT */
+
+#if defined(MBEDTLS_SHA256_ALT)
+
+void mbedtls_sha256_hw_init(mbedtls_sha256_context *ctx)
+{
+    crypto_init();
+    memset(&ctx->hw_ctx, 0, sizeof(ctx->hw_ctx));
+}
+
+void mbedtls_sha256_hw_free(mbedtls_sha256_context *ctx)
+{
+    if (ctx == NULL) {
+        return;
+    }
+
+    crypto_zeroize(&ctx->hw_ctx, sizeof(ctx->hw_ctx));
+}
+
+void mbedtls_sha256_hw_clone(mbedtls_sha256_context *dst,
+                        const mbedtls_sha256_context *src)
+{
+    dst->hw_ctx = src->hw_ctx;
+}
+
+void mbedtls_sha256_hw_starts( mbedtls_sha256_context *ctx, int is224)
+{
+    ctx->hw_ctx.total = 0;
+    ctx->hw_ctx.lastword_size = 0;
+    ctx->hw_ctx.blocksize = 64;
+    ctx->hw_ctx.blocksize_mask = 0x3F;
+    ctx->hw_ctx.is224 = is224;
+
+    SHA_Open(is224 ? SHA_MODE_SHA224 : SHA_MODE_SHA256, SHA_NO_SWAP);
+    
+    return;
+}
+
+void mbedtls_sha256_hw_update(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen)
+{
+    crypto_sha_update(&ctx->hw_ctx, input, ilen);
+}
+
+void mbedtls_sha256_hw_finish(mbedtls_sha256_context *ctx, unsigned char output[32])
+{
+    crypto_sha_lastword(&ctx->hw_ctx, 1);
+    crypto_sha_getinternstate(output, ctx->hw_ctx.is224 ? 28 : 32);
+}
+
+void mbedtls_sha256_hw_process(mbedtls_sha256_context *ctx, const unsigned char data[64])
+{
+    mbedtls_sha256_hw_update(ctx, data, 64);
+}
+
+#endif /* MBEDTLS_SHA256_ALT */
+
+#if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT)
+
+void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen)
+{
+    if (ilen == 0) {
+        return;
+    }
+    
+    crypto_sha_lastword(ctx, 0);
+
+    ctx->total += (uint32_t) ilen;
+
+    const unsigned char *in_pos = input;
+    uint32_t rmn = ilen;
+    uint32_t sha_ctl_start = (CRPT->SHA_CTL & ~(CRPT_SHA_CTL_DMALAST_Msk | CRPT_SHA_CTL_DMAEN_Msk)) | CRPT_SHA_CTL_START_Msk;
+    
+    while (rmn > 4) {
+        CRPT->SHA_CTL = sha_ctl_start;
+        
+        uint32_t data = nu_get32_be(in_pos);
+        while (! (CRPT->SHA_STS & CRPT_SHA_STS_DATINREQ_Msk));
+        CRPT->SHA_DATIN = data;
+        
+        in_pos += 4;
+        rmn -= 4;
+    }
+    
+    MBED_ASSERT(rmn > 0 && rmn <= 4);
+    unsigned char lastword_buf[4];
+    memcpy(lastword_buf, in_pos, rmn);
+    memset(lastword_buf + rmn, 0x00, 4 - rmn);
+    ctx->lastword = nu_get32_be(lastword_buf);
+    ctx->lastword_size = rmn;
+}
+
+void crypto_sha_getinternstate(unsigned char output[], size_t olen)
+{
+    uint32_t *in_pos = (uint32_t *) &CRPT->SHA_DGST0;
+    unsigned char *out_pos = output;
+    uint32_t rmn = olen;
+    
+    while (rmn) {
+        uint32_t val = *in_pos ++;
+        nu_set32_be(out_pos, val);
+        out_pos += 4;
+        rmn -= 4;
+    }
+}
+
+void crypto_sha_lastword(crypto_sha_context *ctx, int islast)
+{
+    uint32_t sha_ctl_start = (CRPT->SHA_CTL & ~(CRPT_SHA_CTL_DMALAST_Msk | CRPT_SHA_CTL_DMAEN_Msk)) | CRPT_SHA_CTL_START_Msk;
+    
+    if (ctx->lastword_size) {
+        if (islast) {
+            uint32_t lastblock_size = ctx->total & ctx->blocksize_mask;
+            if (lastblock_size == 0) {
+                lastblock_size = ctx->blocksize;
+            }
+            CRPT->SHA_DMACNT = lastblock_size;
+            CRPT->SHA_CTL = sha_ctl_start | CRPT_SHA_CTL_DMALAST_Msk;
+        }
+        else {
+            CRPT->SHA_CTL = sha_ctl_start;
+        }
+        while (! (CRPT->SHA_STS & CRPT_SHA_STS_DATINREQ_Msk));
+        CRPT->SHA_DATIN = ctx->lastword;
+        
+        if (islast) {
+            while (CRPT->SHA_STS & CRPT_SHA_STS_BUSY_Msk);
+        }
+        
+        ctx->lastword_size = 0;
+    }
+}
+
+#endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */
+
+#endif /* MBEDTLS_SHA1_C || MBEDTLS_SHA256_C || MBEDTLS_SHA512_C */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.h
new file mode 100644
index 00000000000..070433a6312
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.h
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBEDTLS_SHA_ALT_HW_H
+#define MBEDTLS_SHA_ALT_HW_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C)
+
+#include <stddef.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          SHA context structure
+ */
+typedef struct
+{
+    uint32_t total;                 /*!< number of bytes processed  */
+    uint32_t lastword;              /*!< last word unprocessed */
+    uint16_t lastword_size;         /*!< number of bytes of last word unprocessed */
+    uint16_t blocksize;             /*!< block size */
+    uint32_t blocksize_mask;        /*!< block size mask */
+    
+    int is224;                      /*!< 0 => SHA-256, else SHA-224 */
+}
+crypto_sha_context;
+
+#if defined(MBEDTLS_SHA1_ALT)
+
+struct mbedtls_sha1_context_s;
+
+void mbedtls_sha1_hw_init( struct mbedtls_sha1_context_s *ctx );
+void mbedtls_sha1_hw_free( struct mbedtls_sha1_context_s *ctx );
+void mbedtls_sha1_hw_clone( struct mbedtls_sha1_context_s *dst,
+                         const struct mbedtls_sha1_context_s *src );
+void mbedtls_sha1_hw_starts( struct mbedtls_sha1_context_s *ctx );
+void mbedtls_sha1_hw_update( struct mbedtls_sha1_context_s *ctx, const unsigned char *input, size_t ilen );
+void mbedtls_sha1_hw_finish( struct mbedtls_sha1_context_s *ctx, unsigned char output[20] );
+void mbedtls_sha1_hw_process( struct mbedtls_sha1_context_s *ctx, const unsigned char data[64] );
+
+#endif /* MBEDTLS_SHA1_ALT */
+
+#if defined(MBEDTLS_SHA256_ALT)
+
+struct mbedtls_sha256_context_s;
+
+void mbedtls_sha256_hw_init( struct mbedtls_sha256_context_s *ctx );
+void mbedtls_sha256_hw_free( struct mbedtls_sha256_context_s *ctx );
+void mbedtls_sha256_hw_clone( struct mbedtls_sha256_context_s *dst,
+                           const struct mbedtls_sha256_context_s *src );
+void mbedtls_sha256_hw_starts( struct mbedtls_sha256_context_s *ctx, int is224 );
+void mbedtls_sha256_hw_update( struct mbedtls_sha256_context_s *ctx, const unsigned char *input,
+                    size_t ilen );
+void mbedtls_sha256_hw_finish( struct mbedtls_sha256_context_s *ctx, unsigned char output[32] );
+void mbedtls_sha256_hw_process( struct mbedtls_sha256_context_s *ctx, const unsigned char data[64] );
+
+#endif /* MBEDTLS_SHA256_ALT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_SHA1_C || MBEDTLS_SHA256_C || MBEDTLS_SHA512_C*/
+
+#endif /* sha_alt.h */

From 9915ad38af5323517003d8a114f7ae4a62b39fc2 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Thu, 25 Aug 2016 10:39:11 +0800
Subject: [PATCH 27/89] Fix aes compile error with gcc

---
 .../hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.c       | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.c
index f6920f5ba09..375657443d5 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.c
@@ -52,6 +52,7 @@
 #endif /* MBEDTLS_SELF_TEST */
 
 #include "NUC472_442.h"
+#include "toolchain.h"
 
 //static int aes_init_done = 0;
 
@@ -72,15 +73,8 @@ static uint32_t au32MyAESIV[4] = {
 
 extern volatile int  g_AES_done;
 
-#ifdef __ICCARM__
-#pragma data_alignment=4
-uint8_t au8OutputData[16];
-#pragma data_alignment=4
-uint8_t au8InputData[16];
-#else
-__align(4) uint8_t au8OutputData[16];
-__align(4) uint8_t au8InputData[16];
-#endif
+uint8_t au8OutputData[16] MBED_ALIGN(4);
+uint8_t au8InputData[16] MBED_ALIGN(4);
 
 static void dumpHex(uint8_t au8Data[], int len)
 {

From 0268ab24392392def06ebc26f584bf1af193c2e0 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Thu, 25 Aug 2016 13:52:24 +0800
Subject: [PATCH 28/89] Organize NUC472 crypto files

---
 .../TARGET_NUC472/{ => crypto/aes}/aes_alt.c      |  0
 .../TARGET_NUC472/{ => crypto/aes}/aes_alt.h      |  0
 .../{crypto.c => crypto/crypto-misc.c}            | 15 ++++++++-------
 .../{crypto.h => crypto/crypto-misc.h}            | 10 ++++------
 .../TARGET_NUC472/{ => crypto/des}/des_alt.c      |  2 +-
 .../TARGET_NUC472/{ => crypto/des}/des_alt.h      |  0
 .../TARGET_NUC472/{ => crypto/sha}/sha1_alt.c     |  6 +++---
 .../TARGET_NUC472/{ => crypto/sha}/sha1_alt.h     |  0
 .../TARGET_NUC472/{ => crypto/sha}/sha1_alt_sw.c  |  0
 .../TARGET_NUC472/{ => crypto/sha}/sha1_alt_sw.h  |  0
 .../TARGET_NUC472/{ => crypto/sha}/sha256_alt.c   |  6 +++---
 .../TARGET_NUC472/{ => crypto/sha}/sha256_alt.h   |  0
 .../{ => crypto/sha}/sha256_alt_sw.c              |  0
 .../{ => crypto/sha}/sha256_alt_sw.h              |  0
 .../TARGET_NUC472/{ => crypto/sha}/sha_alt_hw.c   |  2 +-
 .../TARGET_NUC472/{ => crypto/sha}/sha_alt_hw.h   |  0
 16 files changed, 20 insertions(+), 21 deletions(-)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/aes}/aes_alt.c (100%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/aes}/aes_alt.h (100%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{crypto.c => crypto/crypto-misc.c} (83%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{crypto.h => crypto/crypto-misc.h} (85%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/des}/des_alt.c (99%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/des}/des_alt.h (100%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/sha}/sha1_alt.c (96%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/sha}/sha1_alt.h (100%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/sha}/sha1_alt_sw.c (100%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/sha}/sha1_alt_sw.h (100%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/sha}/sha256_alt.c (97%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/sha}/sha256_alt.h (100%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/sha}/sha256_alt_sw.c (100%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/sha}/sha256_alt_sw.h (100%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/sha}/sha_alt_hw.c (99%)
 rename hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/{ => crypto/sha}/sha_alt_hw.h (100%)

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.c
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/aes_alt.h
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c
similarity index 83%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.c
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c
index 20f80783a55..7f6646f40b1 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c
@@ -19,9 +19,10 @@
 #include "mbed_assert.h"
 #include "nu_modutil.h"
 #include "nu_bitutil.h"
+#include "crypto-misc.h"
 
 static int crypto_inited = 0;
-static int crypto_sha_hw_avail = 1;
+static int crypto_sha_avail = 1;
 
 void crypto_init(void)
 {
@@ -42,10 +43,10 @@ void crypto_zeroize(void *v, size_t n)
     }
 }
 
-int crypto_sha_hw_acquire(void)
+int crypto_sha_acquire(void)
 {
-    if (crypto_sha_hw_avail) {
-        crypto_sha_hw_avail = 0;
+    if (crypto_sha_avail) {
+        crypto_sha_avail = 0;
         return 1;
     }
     else {
@@ -54,9 +55,9 @@ int crypto_sha_hw_acquire(void)
     
 }
 
-void crypto_sha_hw_release(void)
+void crypto_sha_release(void)
 {
-    if (! crypto_sha_hw_avail) {
-        crypto_sha_hw_avail = 1;
+    if (! crypto_sha_avail) {
+        crypto_sha_avail = 1;
     }
 }
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h
similarity index 85%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.h
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h
index 2585a9936b1..8d554497120 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto.h
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h
@@ -14,10 +14,8 @@
  * limitations under the License.
  */
 
-#ifndef MBED_CRYPTO_H
-#define MBED_CRYPTO_H
-
-#include "cmsis.h"
+#ifndef MBED_CRYPTO_MISC_H
+#define MBED_CRYPTO_MISC_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -25,8 +23,8 @@ extern "C" {
 
 void crypto_init(void);
 void crypto_zeroize(void *v, size_t n);
-int crypto_sha_hw_acquire(void);
-void crypto_sha_hw_release(void);
+int crypto_sha_acquire(void);
+void crypto_sha_release(void);
 
 #ifdef __cplusplus
 }
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/des_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.c
similarity index 99%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/des_alt.c
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.c
index 867e27b5f9a..fb75266a36f 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/des_alt.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.c
@@ -26,7 +26,7 @@
 #include <string.h>
 #include "mbedtls/des.h"
 #include "des_alt.h"
-#include "crypto.h"
+#include "crypto-misc.h"
 #include "nu_bitutil.h"
 #include "toolchain.h"
 
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/des_alt.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/des_alt.h
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c
similarity index 96%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt.c
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c
index 374228406b4..5f047164480 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c
@@ -24,11 +24,11 @@
 #if defined(MBEDTLS_SHA1_ALT)
 
 #include "sha1_alt.h"
-#include "crypto.h"
+#include "crypto-misc.h"
 
 void mbedtls_sha1_init(mbedtls_sha1_context *ctx)
 {
-    if (crypto_sha_hw_acquire()) {
+    if (crypto_sha_acquire()) {
         ctx->mbedtls_sha1_init = mbedtls_sha1_hw_init;
         ctx->mbedtls_sha1_free = mbedtls_sha1_hw_free;
         ctx->mbedtls_sha1_clone = mbedtls_sha1_hw_clone;
@@ -59,7 +59,7 @@ void mbedtls_sha1_free(mbedtls_sha1_context *ctx)
     ctx->mbedtls_sha1_free(ctx);
     
     if (ctx->mbedtls_sha1_init == mbedtls_sha1_hw_init) {
-        crypto_sha_hw_release();
+        crypto_sha_release();
     }
 }
 
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt.h
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt_sw.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt_sw.c
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt_sw.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha1_alt_sw.h
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c
similarity index 97%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt.c
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c
index 80e19f74063..96859ef47bd 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c
@@ -24,11 +24,11 @@
 #if defined(MBEDTLS_SHA256_ALT)
 
 #include "sha256_alt.h"
-#include "crypto.h"
+#include "crypto-misc.h"
 
 void mbedtls_sha256_init(mbedtls_sha256_context *ctx)
 {
-    if (crypto_sha_hw_acquire()) {
+    if (crypto_sha_acquire()) {
         ctx->mbedtls_sha256_init = mbedtls_sha256_hw_init;
         ctx->mbedtls_sha256_free = mbedtls_sha256_hw_free;
         ctx->mbedtls_sha256_clone = mbedtls_sha256_hw_clone;
@@ -59,7 +59,7 @@ void mbedtls_sha256_free(mbedtls_sha256_context *ctx)
     ctx->mbedtls_sha256_free(ctx);
     
     if (ctx->mbedtls_sha256_init == mbedtls_sha256_hw_init) {
-        crypto_sha_hw_release();
+        crypto_sha_release();
     }
 }
 
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt.h
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt_sw.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt_sw.c
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt_sw.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha256_alt_sw.h
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c
similarity index 99%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.c
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c
index 99151713bef..0c71ae87879 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c
@@ -38,7 +38,7 @@
 
 #include "nu_bitutil.h"
 #include "mbed_assert.h"
-#include "crypto.h"
+#include "crypto-misc.h"
 
 #include <string.h>
 
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/sha_alt_hw.h
rename to hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h

From 1a67f8401697a3d049049c41a5cfd42e3dfe1381 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Thu, 25 Aug 2016 16:40:24 +0800
Subject: [PATCH 29/89] Integrate AES S/W algorithm for verifying NUC472 AES
 accelerator

---
 .../TARGET_NUC472/crypto/des/des_alt.h        |   1 +
 .../TARGET_NUC472/crypto/des/des_alt_sw.c     | 797 ++++++++++++++++++
 .../TARGET_NUC472/crypto/des/des_alt_sw.h     | 283 +++++++
 3 files changed, 1081 insertions(+)
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.c
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.h

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h
index 67a1420ece7..4676ab93e12 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h
@@ -28,6 +28,7 @@
 #include <stddef.h>
 #include <stdint.h>
 #include "des.h"
+#include "des_alt_sw.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.c
new file mode 100644
index 00000000000..1e51151c862
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.c
@@ -0,0 +1,797 @@
+/*
+ *  FIPS-46-3 compliant Triple-DES implementation
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+/*
+ *  DES, on which TDES is based, was originally designed by Horst Feistel
+ *  at IBM in 1974, and was adopted as a standard by NIST (formerly NBS).
+ *
+ *  http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf
+ */
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "mbedtls/config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_DES_C)
+#if defined(MBEDTLS_DES_ALT)
+
+#include "mbedtls/des.h"
+
+#include <string.h>
+
+/* Implementation that should never be optimized out by the compiler */
+static void mbedtls_zeroize( void *v, size_t n ) {
+    volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
+}
+
+/*
+ * 32-bit integer manipulation macros (big endian)
+ */
+#ifndef GET_UINT32_BE
+#define GET_UINT32_BE(n,b,i)                            \
+{                                                       \
+    (n) = ( (uint32_t) (b)[(i)    ] << 24 )             \
+        | ( (uint32_t) (b)[(i) + 1] << 16 )             \
+        | ( (uint32_t) (b)[(i) + 2] <<  8 )             \
+        | ( (uint32_t) (b)[(i) + 3]       );            \
+}
+#endif
+
+#ifndef PUT_UINT32_BE
+#define PUT_UINT32_BE(n,b,i)                            \
+{                                                       \
+    (b)[(i)    ] = (unsigned char) ( (n) >> 24 );       \
+    (b)[(i) + 1] = (unsigned char) ( (n) >> 16 );       \
+    (b)[(i) + 2] = (unsigned char) ( (n) >>  8 );       \
+    (b)[(i) + 3] = (unsigned char) ( (n)       );       \
+}
+#endif
+
+/*
+ * Expanded DES S-boxes
+ */
+static const uint32_t SB1[64] =
+{
+    0x01010400, 0x00000000, 0x00010000, 0x01010404,
+    0x01010004, 0x00010404, 0x00000004, 0x00010000,
+    0x00000400, 0x01010400, 0x01010404, 0x00000400,
+    0x01000404, 0x01010004, 0x01000000, 0x00000004,
+    0x00000404, 0x01000400, 0x01000400, 0x00010400,
+    0x00010400, 0x01010000, 0x01010000, 0x01000404,
+    0x00010004, 0x01000004, 0x01000004, 0x00010004,
+    0x00000000, 0x00000404, 0x00010404, 0x01000000,
+    0x00010000, 0x01010404, 0x00000004, 0x01010000,
+    0x01010400, 0x01000000, 0x01000000, 0x00000400,
+    0x01010004, 0x00010000, 0x00010400, 0x01000004,
+    0x00000400, 0x00000004, 0x01000404, 0x00010404,
+    0x01010404, 0x00010004, 0x01010000, 0x01000404,
+    0x01000004, 0x00000404, 0x00010404, 0x01010400,
+    0x00000404, 0x01000400, 0x01000400, 0x00000000,
+    0x00010004, 0x00010400, 0x00000000, 0x01010004
+};
+
+static const uint32_t SB2[64] =
+{
+    0x80108020, 0x80008000, 0x00008000, 0x00108020,
+    0x00100000, 0x00000020, 0x80100020, 0x80008020,
+    0x80000020, 0x80108020, 0x80108000, 0x80000000,
+    0x80008000, 0x00100000, 0x00000020, 0x80100020,
+    0x00108000, 0x00100020, 0x80008020, 0x00000000,
+    0x80000000, 0x00008000, 0x00108020, 0x80100000,
+    0x00100020, 0x80000020, 0x00000000, 0x00108000,
+    0x00008020, 0x80108000, 0x80100000, 0x00008020,
+    0x00000000, 0x00108020, 0x80100020, 0x00100000,
+    0x80008020, 0x80100000, 0x80108000, 0x00008000,
+    0x80100000, 0x80008000, 0x00000020, 0x80108020,
+    0x00108020, 0x00000020, 0x00008000, 0x80000000,
+    0x00008020, 0x80108000, 0x00100000, 0x80000020,
+    0x00100020, 0x80008020, 0x80000020, 0x00100020,
+    0x00108000, 0x00000000, 0x80008000, 0x00008020,
+    0x80000000, 0x80100020, 0x80108020, 0x00108000
+};
+
+static const uint32_t SB3[64] =
+{
+    0x00000208, 0x08020200, 0x00000000, 0x08020008,
+    0x08000200, 0x00000000, 0x00020208, 0x08000200,
+    0x00020008, 0x08000008, 0x08000008, 0x00020000,
+    0x08020208, 0x00020008, 0x08020000, 0x00000208,
+    0x08000000, 0x00000008, 0x08020200, 0x00000200,
+    0x00020200, 0x08020000, 0x08020008, 0x00020208,
+    0x08000208, 0x00020200, 0x00020000, 0x08000208,
+    0x00000008, 0x08020208, 0x00000200, 0x08000000,
+    0x08020200, 0x08000000, 0x00020008, 0x00000208,
+    0x00020000, 0x08020200, 0x08000200, 0x00000000,
+    0x00000200, 0x00020008, 0x08020208, 0x08000200,
+    0x08000008, 0x00000200, 0x00000000, 0x08020008,
+    0x08000208, 0x00020000, 0x08000000, 0x08020208,
+    0x00000008, 0x00020208, 0x00020200, 0x08000008,
+    0x08020000, 0x08000208, 0x00000208, 0x08020000,
+    0x00020208, 0x00000008, 0x08020008, 0x00020200
+};
+
+static const uint32_t SB4[64] =
+{
+    0x00802001, 0x00002081, 0x00002081, 0x00000080,
+    0x00802080, 0x00800081, 0x00800001, 0x00002001,
+    0x00000000, 0x00802000, 0x00802000, 0x00802081,
+    0x00000081, 0x00000000, 0x00800080, 0x00800001,
+    0x00000001, 0x00002000, 0x00800000, 0x00802001,
+    0x00000080, 0x00800000, 0x00002001, 0x00002080,
+    0x00800081, 0x00000001, 0x00002080, 0x00800080,
+    0x00002000, 0x00802080, 0x00802081, 0x00000081,
+    0x00800080, 0x00800001, 0x00802000, 0x00802081,
+    0x00000081, 0x00000000, 0x00000000, 0x00802000,
+    0x00002080, 0x00800080, 0x00800081, 0x00000001,
+    0x00802001, 0x00002081, 0x00002081, 0x00000080,
+    0x00802081, 0x00000081, 0x00000001, 0x00002000,
+    0x00800001, 0x00002001, 0x00802080, 0x00800081,
+    0x00002001, 0x00002080, 0x00800000, 0x00802001,
+    0x00000080, 0x00800000, 0x00002000, 0x00802080
+};
+
+static const uint32_t SB5[64] =
+{
+    0x00000100, 0x02080100, 0x02080000, 0x42000100,
+    0x00080000, 0x00000100, 0x40000000, 0x02080000,
+    0x40080100, 0x00080000, 0x02000100, 0x40080100,
+    0x42000100, 0x42080000, 0x00080100, 0x40000000,
+    0x02000000, 0x40080000, 0x40080000, 0x00000000,
+    0x40000100, 0x42080100, 0x42080100, 0x02000100,
+    0x42080000, 0x40000100, 0x00000000, 0x42000000,
+    0x02080100, 0x02000000, 0x42000000, 0x00080100,
+    0x00080000, 0x42000100, 0x00000100, 0x02000000,
+    0x40000000, 0x02080000, 0x42000100, 0x40080100,
+    0x02000100, 0x40000000, 0x42080000, 0x02080100,
+    0x40080100, 0x00000100, 0x02000000, 0x42080000,
+    0x42080100, 0x00080100, 0x42000000, 0x42080100,
+    0x02080000, 0x00000000, 0x40080000, 0x42000000,
+    0x00080100, 0x02000100, 0x40000100, 0x00080000,
+    0x00000000, 0x40080000, 0x02080100, 0x40000100
+};
+
+static const uint32_t SB6[64] =
+{
+    0x20000010, 0x20400000, 0x00004000, 0x20404010,
+    0x20400000, 0x00000010, 0x20404010, 0x00400000,
+    0x20004000, 0x00404010, 0x00400000, 0x20000010,
+    0x00400010, 0x20004000, 0x20000000, 0x00004010,
+    0x00000000, 0x00400010, 0x20004010, 0x00004000,
+    0x00404000, 0x20004010, 0x00000010, 0x20400010,
+    0x20400010, 0x00000000, 0x00404010, 0x20404000,
+    0x00004010, 0x00404000, 0x20404000, 0x20000000,
+    0x20004000, 0x00000010, 0x20400010, 0x00404000,
+    0x20404010, 0x00400000, 0x00004010, 0x20000010,
+    0x00400000, 0x20004000, 0x20000000, 0x00004010,
+    0x20000010, 0x20404010, 0x00404000, 0x20400000,
+    0x00404010, 0x20404000, 0x00000000, 0x20400010,
+    0x00000010, 0x00004000, 0x20400000, 0x00404010,
+    0x00004000, 0x00400010, 0x20004010, 0x00000000,
+    0x20404000, 0x20000000, 0x00400010, 0x20004010
+};
+
+static const uint32_t SB7[64] =
+{
+    0x00200000, 0x04200002, 0x04000802, 0x00000000,
+    0x00000800, 0x04000802, 0x00200802, 0x04200800,
+    0x04200802, 0x00200000, 0x00000000, 0x04000002,
+    0x00000002, 0x04000000, 0x04200002, 0x00000802,
+    0x04000800, 0x00200802, 0x00200002, 0x04000800,
+    0x04000002, 0x04200000, 0x04200800, 0x00200002,
+    0x04200000, 0x00000800, 0x00000802, 0x04200802,
+    0x00200800, 0x00000002, 0x04000000, 0x00200800,
+    0x04000000, 0x00200800, 0x00200000, 0x04000802,
+    0x04000802, 0x04200002, 0x04200002, 0x00000002,
+    0x00200002, 0x04000000, 0x04000800, 0x00200000,
+    0x04200800, 0x00000802, 0x00200802, 0x04200800,
+    0x00000802, 0x04000002, 0x04200802, 0x04200000,
+    0x00200800, 0x00000000, 0x00000002, 0x04200802,
+    0x00000000, 0x00200802, 0x04200000, 0x00000800,
+    0x04000002, 0x04000800, 0x00000800, 0x00200002
+};
+
+static const uint32_t SB8[64] =
+{
+    0x10001040, 0x00001000, 0x00040000, 0x10041040,
+    0x10000000, 0x10001040, 0x00000040, 0x10000000,
+    0x00040040, 0x10040000, 0x10041040, 0x00041000,
+    0x10041000, 0x00041040, 0x00001000, 0x00000040,
+    0x10040000, 0x10000040, 0x10001000, 0x00001040,
+    0x00041000, 0x00040040, 0x10040040, 0x10041000,
+    0x00001040, 0x00000000, 0x00000000, 0x10040040,
+    0x10000040, 0x10001000, 0x00041040, 0x00040000,
+    0x00041040, 0x00040000, 0x10041000, 0x00001000,
+    0x00000040, 0x10040040, 0x00001000, 0x00041040,
+    0x10001000, 0x00000040, 0x10000040, 0x10040000,
+    0x10040040, 0x10000000, 0x00040000, 0x10001040,
+    0x00000000, 0x10041040, 0x00040040, 0x10000040,
+    0x10040000, 0x10001000, 0x10001040, 0x00000000,
+    0x10041040, 0x00041000, 0x00041000, 0x00001040,
+    0x00001040, 0x00040040, 0x10000000, 0x10041000
+};
+
+/*
+ * PC1: left and right halves bit-swap
+ */
+static const uint32_t LHs[16] =
+{
+    0x00000000, 0x00000001, 0x00000100, 0x00000101,
+    0x00010000, 0x00010001, 0x00010100, 0x00010101,
+    0x01000000, 0x01000001, 0x01000100, 0x01000101,
+    0x01010000, 0x01010001, 0x01010100, 0x01010101
+};
+
+static const uint32_t RHs[16] =
+{
+    0x00000000, 0x01000000, 0x00010000, 0x01010000,
+    0x00000100, 0x01000100, 0x00010100, 0x01010100,
+    0x00000001, 0x01000001, 0x00010001, 0x01010001,
+    0x00000101, 0x01000101, 0x00010101, 0x01010101,
+};
+
+/*
+ * Initial Permutation macro
+ */
+#define DES_IP(X,Y)                                             \
+{                                                               \
+    T = ((X >>  4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T <<  4);   \
+    T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16);   \
+    T = ((Y >>  2) ^ X) & 0x33333333; X ^= T; Y ^= (T <<  2);   \
+    T = ((Y >>  8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T <<  8);   \
+    Y = ((Y << 1) | (Y >> 31)) & 0xFFFFFFFF;                    \
+    T = (X ^ Y) & 0xAAAAAAAA; Y ^= T; X ^= T;                   \
+    X = ((X << 1) | (X >> 31)) & 0xFFFFFFFF;                    \
+}
+
+/*
+ * Final Permutation macro
+ */
+#define DES_FP(X,Y)                                             \
+{                                                               \
+    X = ((X << 31) | (X >> 1)) & 0xFFFFFFFF;                    \
+    T = (X ^ Y) & 0xAAAAAAAA; X ^= T; Y ^= T;                   \
+    Y = ((Y << 31) | (Y >> 1)) & 0xFFFFFFFF;                    \
+    T = ((Y >>  8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T <<  8);   \
+    T = ((Y >>  2) ^ X) & 0x33333333; X ^= T; Y ^= (T <<  2);   \
+    T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16);   \
+    T = ((X >>  4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T <<  4);   \
+}
+
+/*
+ * DES round macro
+ */
+#define DES_ROUND(X,Y)                          \
+{                                               \
+    T = *SK++ ^ X;                              \
+    Y ^= SB8[ (T      ) & 0x3F ] ^              \
+         SB6[ (T >>  8) & 0x3F ] ^              \
+         SB4[ (T >> 16) & 0x3F ] ^              \
+         SB2[ (T >> 24) & 0x3F ];               \
+                                                \
+    T = *SK++ ^ ((X << 28) | (X >> 4));         \
+    Y ^= SB7[ (T      ) & 0x3F ] ^              \
+         SB5[ (T >>  8) & 0x3F ] ^              \
+         SB3[ (T >> 16) & 0x3F ] ^              \
+         SB1[ (T >> 24) & 0x3F ];               \
+}
+
+#define SWAP(a,b) { uint32_t t = a; a = b; b = t; t = 0; }
+
+void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx )
+{
+    memset( ctx, 0, sizeof( mbedtls_des_sw_context ) );
+}
+
+void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx )
+{
+    if( ctx == NULL )
+        return;
+
+    mbedtls_zeroize( ctx, sizeof( mbedtls_des_sw_context ) );
+}
+
+void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx )
+{
+    memset( ctx, 0, sizeof( mbedtls_des3_sw_context ) );
+}
+
+void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx )
+{
+    if( ctx == NULL )
+        return;
+
+    mbedtls_zeroize( ctx, sizeof( mbedtls_des3_sw_context ) );
+}
+
+static const unsigned char odd_parity_table[128] = { 1,  2,  4,  7,  8,
+        11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44,
+        47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81,
+        82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112,
+        115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140,
+        143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168,
+        171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196,
+        199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224,
+        227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253,
+        254 };
+
+void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] )
+{
+    int i;
+
+    for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ )
+        key[i] = odd_parity_table[key[i] / 2];
+}
+
+/*
+ * Check the given key's parity, returns 1 on failure, 0 on SUCCESS
+ */
+int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
+{
+    int i;
+
+    for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ )
+        if( key[i] != odd_parity_table[key[i] / 2] )
+            return( 1 );
+
+    return( 0 );
+}
+
+/*
+ * Table of weak and semi-weak keys
+ *
+ * Source: http://en.wikipedia.org/wiki/Weak_key
+ *
+ * Weak:
+ * Alternating ones + zeros (0x0101010101010101)
+ * Alternating 'F' + 'E' (0xFEFEFEFEFEFEFEFE)
+ * '0xE0E0E0E0F1F1F1F1'
+ * '0x1F1F1F1F0E0E0E0E'
+ *
+ * Semi-weak:
+ * 0x011F011F010E010E and 0x1F011F010E010E01
+ * 0x01E001E001F101F1 and 0xE001E001F101F101
+ * 0x01FE01FE01FE01FE and 0xFE01FE01FE01FE01
+ * 0x1FE01FE00EF10EF1 and 0xE01FE01FF10EF10E
+ * 0x1FFE1FFE0EFE0EFE and 0xFE1FFE1FFE0EFE0E
+ * 0xE0FEE0FEF1FEF1FE and 0xFEE0FEE0FEF1FEF1
+ *
+ */
+
+#define WEAK_KEY_COUNT 16
+
+static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] =
+{
+    { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 },
+    { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
+    { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E },
+    { 0xE0, 0xE0, 0xE0, 0xE0, 0xF1, 0xF1, 0xF1, 0xF1 },
+
+    { 0x01, 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E },
+    { 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E, 0x01 },
+    { 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1 },
+    { 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1, 0x01 },
+    { 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE },
+    { 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01 },
+    { 0x1F, 0xE0, 0x1F, 0xE0, 0x0E, 0xF1, 0x0E, 0xF1 },
+    { 0xE0, 0x1F, 0xE0, 0x1F, 0xF1, 0x0E, 0xF1, 0x0E },
+    { 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E, 0xFE },
+    { 0xFE, 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E },
+    { 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1, 0xFE },
+    { 0xFE, 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1 }
+};
+
+int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
+{
+    int i;
+
+    for( i = 0; i < WEAK_KEY_COUNT; i++ )
+        if( memcmp( weak_key_table[i], key, MBEDTLS_DES_KEY_SIZE) == 0 )
+            return( 1 );
+
+    return( 0 );
+}
+
+void mbedtls_des_setkey( uint32_t SK[32], const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
+{
+    int i;
+    uint32_t X, Y, T;
+
+    GET_UINT32_BE( X, key, 0 );
+    GET_UINT32_BE( Y, key, 4 );
+
+    /*
+     * Permuted Choice 1
+     */
+    T =  ((Y >>  4) ^ X) & 0x0F0F0F0F;  X ^= T; Y ^= (T <<  4);
+    T =  ((Y      ) ^ X) & 0x10101010;  X ^= T; Y ^= (T      );
+
+    X =   (LHs[ (X      ) & 0xF] << 3) | (LHs[ (X >>  8) & 0xF ] << 2)
+        | (LHs[ (X >> 16) & 0xF] << 1) | (LHs[ (X >> 24) & 0xF ]     )
+        | (LHs[ (X >>  5) & 0xF] << 7) | (LHs[ (X >> 13) & 0xF ] << 6)
+        | (LHs[ (X >> 21) & 0xF] << 5) | (LHs[ (X >> 29) & 0xF ] << 4);
+
+    Y =   (RHs[ (Y >>  1) & 0xF] << 3) | (RHs[ (Y >>  9) & 0xF ] << 2)
+        | (RHs[ (Y >> 17) & 0xF] << 1) | (RHs[ (Y >> 25) & 0xF ]     )
+        | (RHs[ (Y >>  4) & 0xF] << 7) | (RHs[ (Y >> 12) & 0xF ] << 6)
+        | (RHs[ (Y >> 20) & 0xF] << 5) | (RHs[ (Y >> 28) & 0xF ] << 4);
+
+    X &= 0x0FFFFFFF;
+    Y &= 0x0FFFFFFF;
+
+    /*
+     * calculate subkeys
+     */
+    for( i = 0; i < 16; i++ )
+    {
+        if( i < 2 || i == 8 || i == 15 )
+        {
+            X = ((X <<  1) | (X >> 27)) & 0x0FFFFFFF;
+            Y = ((Y <<  1) | (Y >> 27)) & 0x0FFFFFFF;
+        }
+        else
+        {
+            X = ((X <<  2) | (X >> 26)) & 0x0FFFFFFF;
+            Y = ((Y <<  2) | (Y >> 26)) & 0x0FFFFFFF;
+        }
+
+        *SK++ =   ((X <<  4) & 0x24000000) | ((X << 28) & 0x10000000)
+                | ((X << 14) & 0x08000000) | ((X << 18) & 0x02080000)
+                | ((X <<  6) & 0x01000000) | ((X <<  9) & 0x00200000)
+                | ((X >>  1) & 0x00100000) | ((X << 10) & 0x00040000)
+                | ((X <<  2) & 0x00020000) | ((X >> 10) & 0x00010000)
+                | ((Y >> 13) & 0x00002000) | ((Y >>  4) & 0x00001000)
+                | ((Y <<  6) & 0x00000800) | ((Y >>  1) & 0x00000400)
+                | ((Y >> 14) & 0x00000200) | ((Y      ) & 0x00000100)
+                | ((Y >>  5) & 0x00000020) | ((Y >> 10) & 0x00000010)
+                | ((Y >>  3) & 0x00000008) | ((Y >> 18) & 0x00000004)
+                | ((Y >> 26) & 0x00000002) | ((Y >> 24) & 0x00000001);
+
+        *SK++ =   ((X << 15) & 0x20000000) | ((X << 17) & 0x10000000)
+                | ((X << 10) & 0x08000000) | ((X << 22) & 0x04000000)
+                | ((X >>  2) & 0x02000000) | ((X <<  1) & 0x01000000)
+                | ((X << 16) & 0x00200000) | ((X << 11) & 0x00100000)
+                | ((X <<  3) & 0x00080000) | ((X >>  6) & 0x00040000)
+                | ((X << 15) & 0x00020000) | ((X >>  4) & 0x00010000)
+                | ((Y >>  2) & 0x00002000) | ((Y <<  8) & 0x00001000)
+                | ((Y >> 14) & 0x00000808) | ((Y >>  9) & 0x00000400)
+                | ((Y      ) & 0x00000200) | ((Y <<  7) & 0x00000100)
+                | ((Y >>  7) & 0x00000020) | ((Y >>  3) & 0x00000011)
+                | ((Y <<  2) & 0x00000004) | ((Y >> 21) & 0x00000002);
+    }
+}
+
+/*
+ * DES key schedule (56-bit, encryption)
+ */
+int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
+{
+    mbedtls_des_setkey( ctx->sk, key );
+
+    return( 0 );
+}
+
+/*
+ * DES key schedule (56-bit, decryption)
+ */
+int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
+{
+    int i;
+
+    mbedtls_des_setkey( ctx->sk, key );
+
+    for( i = 0; i < 16; i += 2 )
+    {
+        SWAP( ctx->sk[i    ], ctx->sk[30 - i] );
+        SWAP( ctx->sk[i + 1], ctx->sk[31 - i] );
+    }
+
+    return( 0 );
+}
+
+static void des3_set2key( uint32_t esk[96],
+                          uint32_t dsk[96],
+                          const unsigned char key[MBEDTLS_DES_KEY_SIZE*2] )
+{
+    int i;
+
+    mbedtls_des_setkey( esk, key );
+    mbedtls_des_setkey( dsk + 32, key + 8 );
+
+    for( i = 0; i < 32; i += 2 )
+    {
+        dsk[i     ] = esk[30 - i];
+        dsk[i +  1] = esk[31 - i];
+
+        esk[i + 32] = dsk[62 - i];
+        esk[i + 33] = dsk[63 - i];
+
+        esk[i + 64] = esk[i    ];
+        esk[i + 65] = esk[i + 1];
+
+        dsk[i + 64] = dsk[i    ];
+        dsk[i + 65] = dsk[i + 1];
+    }
+}
+
+/*
+ * Triple-DES key schedule (112-bit, encryption)
+ */
+int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] )
+{
+    uint32_t sk[96];
+
+    des3_set2key( ctx->sk, sk, key );
+    mbedtls_zeroize( sk,  sizeof( sk ) );
+
+    return( 0 );
+}
+
+/*
+ * Triple-DES key schedule (112-bit, decryption)
+ */
+int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] )
+{
+    uint32_t sk[96];
+
+    des3_set2key( sk, ctx->sk, key );
+    mbedtls_zeroize( sk,  sizeof( sk ) );
+
+    return( 0 );
+}
+
+static void des3_set3key( uint32_t esk[96],
+                          uint32_t dsk[96],
+                          const unsigned char key[24] )
+{
+    int i;
+
+    mbedtls_des_setkey( esk, key );
+    mbedtls_des_setkey( dsk + 32, key +  8 );
+    mbedtls_des_setkey( esk + 64, key + 16 );
+
+    for( i = 0; i < 32; i += 2 )
+    {
+        dsk[i     ] = esk[94 - i];
+        dsk[i +  1] = esk[95 - i];
+
+        esk[i + 32] = dsk[62 - i];
+        esk[i + 33] = dsk[63 - i];
+
+        dsk[i + 64] = esk[30 - i];
+        dsk[i + 65] = esk[31 - i];
+    }
+}
+
+/*
+ * Triple-DES key schedule (168-bit, encryption)
+ */
+int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] )
+{
+    uint32_t sk[96];
+
+    des3_set3key( ctx->sk, sk, key );
+    mbedtls_zeroize( sk,  sizeof( sk ) );
+
+    return( 0 );
+}
+
+/*
+ * Triple-DES key schedule (168-bit, decryption)
+ */
+int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] )
+{
+    uint32_t sk[96];
+
+    des3_set3key( sk, ctx->sk, key );
+    mbedtls_zeroize( sk,  sizeof( sk ) );
+
+    return( 0 );
+}
+
+/*
+ * DES-ECB block encryption/decryption
+ */
+int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx,
+                    const unsigned char input[8],
+                    unsigned char output[8] )
+{
+    int i;
+    uint32_t X, Y, T, *SK;
+
+    SK = ctx->sk;
+
+    GET_UINT32_BE( X, input, 0 );
+    GET_UINT32_BE( Y, input, 4 );
+
+    DES_IP( X, Y );
+
+    for( i = 0; i < 8; i++ )
+    {
+        DES_ROUND( Y, X );
+        DES_ROUND( X, Y );
+    }
+
+    DES_FP( Y, X );
+
+    PUT_UINT32_BE( Y, output, 0 );
+    PUT_UINT32_BE( X, output, 4 );
+
+    return( 0 );
+}
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/*
+ * DES-CBC buffer encryption/decryption
+ */
+int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[8],
+                    const unsigned char *input,
+                    unsigned char *output )
+{
+    int i;
+    unsigned char temp[8];
+
+    if( length % 8 )
+        return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH );
+
+    if( mode == MBEDTLS_DES_ENCRYPT )
+    {
+        while( length > 0 )
+        {
+            for( i = 0; i < 8; i++ )
+                output[i] = (unsigned char)( input[i] ^ iv[i] );
+
+            mbedtls_des_sw_crypt_ecb( ctx, output, output );
+            memcpy( iv, output, 8 );
+
+            input  += 8;
+            output += 8;
+            length -= 8;
+        }
+    }
+    else /* MBEDTLS_DES_DECRYPT */
+    {
+        while( length > 0 )
+        {
+            memcpy( temp, input, 8 );
+            mbedtls_des_sw_crypt_ecb( ctx, input, output );
+
+            for( i = 0; i < 8; i++ )
+                output[i] = (unsigned char)( output[i] ^ iv[i] );
+
+            memcpy( iv, temp, 8 );
+
+            input  += 8;
+            output += 8;
+            length -= 8;
+        }
+    }
+
+    return( 0 );
+}
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+/*
+ * 3DES-ECB block encryption/decryption
+ */
+int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx,
+                     const unsigned char input[8],
+                     unsigned char output[8] )
+{
+    int i;
+    uint32_t X, Y, T, *SK;
+
+    SK = ctx->sk;
+
+    GET_UINT32_BE( X, input, 0 );
+    GET_UINT32_BE( Y, input, 4 );
+
+    DES_IP( X, Y );
+
+    for( i = 0; i < 8; i++ )
+    {
+        DES_ROUND( Y, X );
+        DES_ROUND( X, Y );
+    }
+
+    for( i = 0; i < 8; i++ )
+    {
+        DES_ROUND( X, Y );
+        DES_ROUND( Y, X );
+    }
+
+    for( i = 0; i < 8; i++ )
+    {
+        DES_ROUND( Y, X );
+        DES_ROUND( X, Y );
+    }
+
+    DES_FP( Y, X );
+
+    PUT_UINT32_BE( Y, output, 0 );
+    PUT_UINT32_BE( X, output, 4 );
+
+    return( 0 );
+}
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/*
+ * 3DES-CBC buffer encryption/decryption
+ */
+int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx,
+                     int mode,
+                     size_t length,
+                     unsigned char iv[8],
+                     const unsigned char *input,
+                     unsigned char *output )
+{
+    int i;
+    unsigned char temp[8];
+
+    if( length % 8 )
+        return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH );
+
+    if( mode == MBEDTLS_DES_ENCRYPT )
+    {
+        while( length > 0 )
+        {
+            for( i = 0; i < 8; i++ )
+                output[i] = (unsigned char)( input[i] ^ iv[i] );
+
+            mbedtls_des3_sw_crypt_ecb( ctx, output, output );
+            memcpy( iv, output, 8 );
+
+            input  += 8;
+            output += 8;
+            length -= 8;
+        }
+    }
+    else /* MBEDTLS_DES_DECRYPT */
+    {
+        while( length > 0 )
+        {
+            memcpy( temp, input, 8 );
+            mbedtls_des3_sw_crypt_ecb( ctx, input, output );
+
+            for( i = 0; i < 8; i++ )
+                output[i] = (unsigned char)( output[i] ^ iv[i] );
+
+            memcpy( iv, temp, 8 );
+
+            input  += 8;
+            output += 8;
+            length -= 8;
+        }
+    }
+
+    return( 0 );
+}
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+#endif /* MBEDTLS_DES_ALT */
+#endif /* MBEDTLS_DES_C */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.h
new file mode 100644
index 00000000000..d42aa2ba050
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.h
@@ -0,0 +1,283 @@
+/**
+ * \file des.h
+ *
+ * \brief DES block cipher
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ */
+#ifndef MBEDTLS_DES_ALT_SW_H
+#define MBEDTLS_DES_ALT_SW_H
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#if defined(MBEDTLS_DES_C)
+#if defined(MBEDTLS_DES_ALT)
+
+#include <stddef.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          DES context structure
+ */
+typedef struct
+{
+    uint32_t sk[32];            /*!<  DES subkeys       */
+}
+mbedtls_des_sw_context;
+
+/**
+ * \brief          Triple-DES context structure
+ */
+typedef struct
+{
+    uint32_t sk[96];            /*!<  3DES subkeys      */
+}
+mbedtls_des3_sw_context;
+
+/**
+ * \brief          Initialize DES context
+ *
+ * \param ctx      DES context to be initialized
+ */
+void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx );
+
+/**
+ * \brief          Clear DES context
+ *
+ * \param ctx      DES context to be cleared
+ */
+void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx );
+
+/**
+ * \brief          Initialize Triple-DES context
+ *
+ * \param ctx      DES3 context to be initialized
+ */
+void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx );
+
+/**
+ * \brief          Clear Triple-DES context
+ *
+ * \param ctx      DES3 context to be cleared
+ */
+void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx );
+
+/**
+ * \brief          Set key parity on the given key to odd.
+ *
+ *                 DES keys are 56 bits long, but each byte is padded with
+ *                 a parity bit to allow verification.
+ *
+ * \param key      8-byte secret key
+ */
+void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          Check that key parity on the given key is odd.
+ *
+ *                 DES keys are 56 bits long, but each byte is padded with
+ *                 a parity bit to allow verification.
+ *
+ * \param key      8-byte secret key
+ *
+ * \return         0 is parity was ok, 1 if parity was not correct.
+ */
+int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          Check that key is not a weak or semi-weak DES key
+ *
+ * \param key      8-byte secret key
+ *
+ * \return         0 if no weak key was found, 1 if a weak key was identified.
+ */
+int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          DES key schedule (56-bit, encryption)
+ *
+ * \param ctx      DES context to be initialized
+ * \param key      8-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          DES key schedule (56-bit, decryption)
+ *
+ * \param ctx      DES context to be initialized
+ * \param key      8-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+/**
+ * \brief          Triple-DES key schedule (112-bit, encryption)
+ *
+ * \param ctx      3DES context to be initialized
+ * \param key      16-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
+
+/**
+ * \brief          Triple-DES key schedule (112-bit, decryption)
+ *
+ * \param ctx      3DES context to be initialized
+ * \param key      16-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
+
+/**
+ * \brief          Triple-DES key schedule (168-bit, encryption)
+ *
+ * \param ctx      3DES context to be initialized
+ * \param key      24-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
+
+/**
+ * \brief          Triple-DES key schedule (168-bit, decryption)
+ *
+ * \param ctx      3DES context to be initialized
+ * \param key      24-byte secret key
+ *
+ * \return         0
+ */
+int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx,
+                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
+
+/**
+ * \brief          DES-ECB block encryption/decryption
+ *
+ * \param ctx      DES context
+ * \param input    64-bit input block
+ * \param output   64-bit output block
+ *
+ * \return         0 if successful
+ */
+int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx,
+                    const unsigned char input[8],
+                    unsigned char output[8] );
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/**
+ * \brief          DES-CBC buffer encryption/decryption
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      DES context
+ * \param mode     MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ */
+int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[8],
+                    const unsigned char *input,
+                    unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+/**
+ * \brief          3DES-ECB block encryption/decryption
+ *
+ * \param ctx      3DES context
+ * \param input    64-bit input block
+ * \param output   64-bit output block
+ *
+ * \return         0 if successful
+ */
+int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx,
+                     const unsigned char input[8],
+                     unsigned char output[8] );
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/**
+ * \brief          3DES-CBC buffer encryption/decryption
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      3DES context
+ * \param mode     MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH
+ */
+int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx,
+                     int mode,
+                     size_t length,
+                     unsigned char iv[8],
+                     const unsigned char *input,
+                     unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+/**
+ * \brief          Internal function for key expansion.
+ *                 (Only exposed to allow overriding it,
+ *                 see MBEDTLS_DES_SETKEY_ALT)
+ *
+ * \param SK       Round keys
+ * \param key      Base key
+ */
+void mbedtls_des_sw_setkey( uint32_t SK[32],
+                         const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_DES_ALT */
+#endif /* MBEDTLS_DES_C */
+
+#endif /* des.h */

From 8bab8e2f52295de9463502f281ef761588706703 Mon Sep 17 00:00:00 2001
From: cyliangtw <cyliang@nuvoton.com>
Date: Fri, 26 Aug 2016 19:45:27 +0800
Subject: [PATCH 30/89] Support HW AES CBC block chain & AES CFB

---
 .../TARGET_NUC472/crypto/aes/aes_alt.c        | 219 +++++++++++-------
 .../TARGET_NUC472/crypto/aes/aes_alt.h        |   3 +-
 2 files changed, 132 insertions(+), 90 deletions(-)

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
index 375657443d5..9e4c5434d0d 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
@@ -1,22 +1,19 @@
-/*
- *  AES hardware acceleration implementation
- *
- *  Copyright (C) 2015-2020, Nuvoton, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
  *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
+
 /*
  *  The AES block cipher was designed by Vincent Rijmen and Joan Daemen.
  *
@@ -31,32 +28,18 @@
 #endif
 
 #if defined(MBEDTLS_AES_C)
+#if defined(MBEDTLS_AES_ALT)
 
 #include <string.h>
 
 #include "mbedtls/aes.h"
-#if defined(MBEDTLS_PADLOCK_C)
-#include "mbedtls/padlock.h"
-#endif
-#if defined(MBEDTLS_AESNI_C)
-#include "mbedtls/aesni.h"
-#endif
-
-#if defined(MBEDTLS_SELF_TEST)
-#if defined(MBEDTLS_PLATFORM_C)
-#include "mbedtls/platform.h"
-#else
-#include <stdio.h>
-#define mbedtls_printf printf
-#endif /* MBEDTLS_PLATFORM_C */
-#endif /* MBEDTLS_SELF_TEST */
 
 #include "NUC472_442.h"
 #include "toolchain.h"
+#include "mbed_assert.h"
 
 //static int aes_init_done = 0;
 
-#if defined(MBEDTLS_AES_ALT)
 
 #define mbedtls_trace  //printf
 
@@ -73,16 +56,34 @@ static uint32_t au32MyAESIV[4] = {
 
 extern volatile int  g_AES_done;
 
-uint8_t au8OutputData[16] MBED_ALIGN(4);
-uint8_t au8InputData[16] MBED_ALIGN(4);
+// Must be a multiple of 16 bytes block size 
+#define MAX_DMA_CHAIN_SIZE (16*6)
+static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4);
+static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4);
 
-static void dumpHex(uint8_t au8Data[], int len)
+static void dumpHex(const unsigned char au8Data[], int len)
 {
 		int j;									
 		for (j = 0; j < len; j++) mbedtls_trace("%02x ", au8Data[j]);									
 		mbedtls_trace("\r\n");										
 }	
 
+static void swapInitVector(unsigned char iv[16])
+{
+	  unsigned int* piv;
+	  int i;
+		// iv SWAP
+		piv = (unsigned int*)iv;
+		for( i=0; i< 4; i++)
+		{
+				*piv = (((*piv) & 0x000000FF) << 24) |
+				(((*piv) & 0x0000FF00) << 8) |
+				(((*piv) & 0x00FF0000) >> 8) |
+				(((*piv) & 0xFF000000) >> 24);
+				piv++;
+		}			
+}	
+
 //volatile void CRYPTO_IRQHandler()
 //{
 //    if (AES_GET_INT_FLAG()) {
@@ -104,7 +105,6 @@ static int channel_alloc()
 			return i;
 		}	
 	}
-	printf("%s: No available AES channel \r\n", __FUNCTION__);
 	return(-1);
 }
 
@@ -126,8 +126,11 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx )
     memset( ctx, 0, sizeof( mbedtls_aes_context ) );
 	
     ctx->swapType = AES_IN_OUT_SWAP;
-		while( (i = channel_alloc()) < 0 ) osDelay(300);
-
+		while( (i = channel_alloc()) < 0 ) 	
+		{	
+		  mbed_assert_internal("No available AES channel", __FILE__, __LINE__);
+			//osDelay(300);
+    }
     ctx->channel = i;
     ctx->iv = au32MyAESIV;
 	
@@ -215,7 +218,7 @@ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
     int ret;
 	
 	  mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits);
-	  dumpHex(key,keybits/8);
+	  dumpHex((uint8_t *)key,keybits/8);
 	
     /* Also checks keybits */
     if( ( ret = mbedtls_aes_setkey_enc( ctx, key, keybits ) ) != 0 )
@@ -230,9 +233,8 @@ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
 
 static void __nvt_aes_crypt( mbedtls_aes_context *ctx,
                           const unsigned char input[16],
-                          unsigned char output[16])
+                          unsigned char output[16], int dataSize)
 {
-    int i;
 		unsigned char* pIn;
 	  unsigned char* pOut;
 
@@ -243,28 +245,27 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx,
     AES_SetInitVect(ctx->channel, ctx->iv);
 		if( ((uint32_t)input) & 0x03 )
 		{
-			memcpy(au8InputData, input, sizeof(au8InputData));
+			memcpy(au8InputData, input, dataSize);
 			pIn = au8InputData;
 		}else{
-		  pIn = (uint32_t)input;
+		  pIn = input;
     }
 		if( ((uint32_t)output) & 0x03 )
 		{		
 			pOut = au8OutputData;
 		} else {
-		  pOut = (uint32_t)output;
+		  pOut = output;
     }			
 
-    AES_SetDMATransfer(ctx->channel, (uint32_t)pIn, (uint32_t)pOut, sizeof(au8InputData));		
+    AES_SetDMATransfer(ctx->channel, (uint32_t)pIn, (uint32_t)pOut, dataSize);		
 
     g_AES_done = 0;
     AES_Start(ctx->channel, CRYPTO_DMA_ONE_SHOT);
     while (!g_AES_done);
 
-    if( pOut != (uint32_t)output ) memcpy(output, au8OutputData, sizeof(au8InputData));
+    if( pOut != output ) memcpy(output, au8OutputData, dataSize);
 		dumpHex(output,16);
 
-
 }
 
 /*
@@ -275,12 +276,11 @@ void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
                           const unsigned char input[16],
                           unsigned char output[16] )
 {
-    int i;
 
 	  mbedtls_trace("=== %s \r\n", __FUNCTION__);
 	
 	  ctx->encDec = 1;
-	  __nvt_aes_crypt(ctx, input, output);
+	  __nvt_aes_crypt(ctx, input, output, 16);
   
 }
 #endif /* MBEDTLS_AES_ENCRYPT_ALT */
@@ -293,12 +293,11 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
                           const unsigned char input[16],
                           unsigned char output[16] )
 {
-    int i;
  
 	  mbedtls_trace("=== %s \r\n", __FUNCTION__);
 
 	  ctx->encDec = 0;
-	  __nvt_aes_crypt(ctx, input, output);
+	  __nvt_aes_crypt(ctx, input, output, 16);
 
 
 }
@@ -312,8 +311,6 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
                     const unsigned char input[16],
                     unsigned char output[16] )
 {
-  unsigned char sw_output[16];
-
 	
 	  mbedtls_trace("=== %s \r\n", __FUNCTION__);
 		
@@ -333,52 +330,50 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
  */
 int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
                     int mode,
-                    size_t length,
+                    size_t len,
                     unsigned char iv[16],
                     const unsigned char *input,
                     unsigned char *output )
 {
-    int i;
     unsigned char temp[16];
-	  unsigned int* piv;
-
+    int length = len;
+	  int blockChainLen;
 		mbedtls_trace("=== %s \r\n", __FUNCTION__);
     if( length % 16 )
         return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
 
-
-        while( length > 0 )
-        {
-			      ctx->opMode = AES_MODE_CBC;
-			      ctx->iv = iv;
-    		    if( mode == MBEDTLS_AES_ENCRYPT )
-    		    {
-        		    mbedtls_aes_encrypt( ctx, input, output );
-        		    memcpy( iv, output, 16 );
-    		    }else{
-    			      memcpy( temp, input, 16 );
-								dumpHex(input,16);
-        		    mbedtls_aes_decrypt( ctx, input, output );
-							  dumpHex(iv,16);
-								dumpHex(output,16);
-        		    memcpy( iv, temp, 16 );            
-            }
-					
-					// iv SWAP
-					piv = (unsigned int*)iv;
-					for( i=0; i< 4; i++)
-					{
-						*piv = (((*piv) & 0x000000FF) << 24) |
-							(((*piv) & 0x0000FF00) << 8) |
-							(((*piv) & 0x00FF0000) >> 8) |
-							(((*piv) & 0xFF000000) >> 24);
-						piv++;
-					}
-            input  += 16;
-            output += 16;
-            length -= 16;
-        }
-
+    if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) )
+		{
+			  blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ?  MAX_DMA_CHAIN_SIZE : length );
+    } else {
+			  blockChainLen = length;
+    }			
+		
+    while( length > 0 )
+    {
+			  ctx->opMode = AES_MODE_CBC;
+			  swapInitVector(iv); // iv SWAP
+			  ctx->iv = (uint32_t *)iv;
+
+    		if( mode == MBEDTLS_AES_ENCRYPT )
+    		{					
+	            ctx->encDec = 1;
+	            __nvt_aes_crypt(ctx, input, output, blockChainLen);
+//					    if( blockChainLen == length ) break;		// finish last block chain but still need to prepare next iv for mbedtls_aes_self_test()
+							memcpy( iv, output+blockChainLen-16, 16 );
+				}else{
+					    memcpy( temp, input+blockChainLen-16, 16 );
+		          ctx->encDec = 0;
+	            __nvt_aes_crypt(ctx, input, output, blockChainLen);
+//					    if( blockChainLen == length ) break;		// finish last block chain but still need to prepare next iv for mbedtls_aes_self_test()
+					    memcpy( iv, temp, 16 );
+         }	
+         length -= blockChainLen;
+         input  += blockChainLen;
+         output += blockChainLen;
+			   if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length;		// For last remainder block chain				
+	
+    }
 
     return( 0 );
 }
@@ -396,6 +391,52 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
                        const unsigned char *input,
                        unsigned char *output )
 {
+ 
+    size_t n = *iv_off;
+    unsigned char temp[16];
+   	int ivLen;
+	
+		mbedtls_trace("=== %s \r\n", __FUNCTION__);
+		
+		// Over reserved Max DMA buffer size
+		if( length > MAX_DMA_CHAIN_SIZE ) 
+						return __aes_crypt_over_dma_size_cfb128(ctx, mode, length, iv_off, iv, input, output);
+	
+		ctx->opMode = AES_MODE_CFB;
+		swapInitVector(iv); // iv SWAP
+	
+		ctx->iv = (uint32_t *)iv;	
+    if( mode == MBEDTLS_AES_DECRYPT )
+    {
+				n= length%16;
+				ivLen = (( n > 0) ? n : 16);
+				memcpy(temp, input+length-ivLen, ivLen);
+	      ctx->encDec = 0;
+	      __nvt_aes_crypt(ctx, input, output, length);
+				memcpy(iv,temp,ivLen);
+    }
+    else
+    {
+				n= length%16;
+				ivLen = (( n > 0) ? n : 16);
+				ctx->encDec = 1;
+	      __nvt_aes_crypt(ctx, input, output, length);			
+				memcpy(iv, output+length-ivLen, ivLen);			
+    }
+		
+    *iv_off = n;
+
+    return( 0 );
+}
+
+static int __aes_crypt_over_dma_size_cfb128( mbedtls_aes_context *ctx,
+                       int mode,
+                       size_t length,
+                       size_t *iv_off,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output )
+{
     int c;
     size_t n = *iv_off;
 
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h
index 77d1837e9eb..0113f269f24 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h
@@ -44,9 +44,10 @@ typedef struct
     uint32_t channel;
     uint32_t swapType;
     uint32_t *iv;
+#if 1	
     uint32_t buf[8]; 
 /* For comparsion with software AES for correctness */ 
-#if 0
+#else
     uint32_t buf[68];           /*!<  unaligned data    */    
     int nr;                     /*!<  number of rounds  */
     uint32_t *rk;               /*!<  AES round keys    */    

From c59ef5c0b4f7eb010420eda8ed075e9731a07627 Mon Sep 17 00:00:00 2001
From: cyliangtw <cyliang@nuvoton.com>
Date: Mon, 29 Aug 2016 21:42:43 +0800
Subject: [PATCH 31/89] Support block chain & partial block in HW AES CFB mode

---
 .../TARGET_NUC472/crypto/aes/aes_alt.c        | 106 ++++++++++++------
 .../TARGET_NUC472/crypto/aes/aes_alt.h        |   1 +
 2 files changed, 73 insertions(+), 34 deletions(-)

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
index 9e4c5434d0d..82f2f4687a8 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
@@ -250,7 +250,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx,
 		}else{
 		  pIn = input;
     }
-		if( ((uint32_t)output) & 0x03 )
+		if( (((uint32_t)output) & 0x03) || (dataSize%4))   // HW CFB output byte count must be multiple of word
 		{		
 			pOut = au8OutputData;
 		} else {
@@ -385,51 +385,77 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
  */
 int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
                        int mode,
-                       size_t length,
+                       size_t len,
                        size_t *iv_off,
                        unsigned char iv[16],
                        const unsigned char *input,
                        unsigned char *output )
 {
- 
-    size_t n = *iv_off;
+		size_t n = *iv_off;
     unsigned char temp[16];
+   	int length=len;
+	  int blockChainLen;
+		int remLen=0;
    	int ivLen;
 	
 		mbedtls_trace("=== %s \r\n", __FUNCTION__);
 		
-		// Over reserved Max DMA buffer size
-		if( length > MAX_DMA_CHAIN_SIZE ) 
-						return __aes_crypt_over_dma_size_cfb128(ctx, mode, length, iv_off, iv, input, output);
+	// proceed: start with partial block by ECB mode first
+	  if( n !=0 ) {
+				__nvt_aes_crypt_partial_block_cfb128(ctx, mode, 16 - n , iv_off, iv, input, output);
+				input += (16 - n);
+				output += (16 - n);
+				length -= (16 - n);
+		}
+		
+		// For address or byte count non-word alignment, go through reserved DMA buffer.
+		if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) || (length%4) )  
+		{	
+			  blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ?  MAX_DMA_CHAIN_SIZE : length );
+    } else {
+			  blockChainLen = length;
+    }						
+		
+		// proceed: start with block alignment
+		while( length > 0 )
+		{
+
+				ctx->opMode = AES_MODE_CFB;
+
+				swapInitVector(iv); // iv SWAP
 	
-		ctx->opMode = AES_MODE_CFB;
-		swapInitVector(iv); // iv SWAP
+				ctx->iv = (uint32_t *)iv;
+				remLen = blockChainLen%16;
+				ivLen = (( remLen > 0) ? remLen: 16 );
 	
-		ctx->iv = (uint32_t *)iv;	
-    if( mode == MBEDTLS_AES_DECRYPT )
-    {
-				n= length%16;
-				ivLen = (( n > 0) ? n : 16);
-				memcpy(temp, input+length-ivLen, ivLen);
-	      ctx->encDec = 0;
-	      __nvt_aes_crypt(ctx, input, output, length);
-				memcpy(iv,temp,ivLen);
-    }
-    else
-    {
-				n= length%16;
-				ivLen = (( n > 0) ? n : 16);
-				ctx->encDec = 1;
-	      __nvt_aes_crypt(ctx, input, output, length);			
-				memcpy(iv, output+length-ivLen, ivLen);			
-    }
+				if( mode == MBEDTLS_AES_DECRYPT )
+				{
+						memcpy(temp, input+blockChainLen - ivLen, ivLen);
+						if(blockChainLen >= 16) memcpy(ctx->prv_iv, input+blockChainLen-remLen-16 , 16);
+						ctx->encDec = 0;
+						__nvt_aes_crypt(ctx, input, output, blockChainLen);
+						memcpy(iv,temp, ivLen);
+				}
+				else
+				{
+						ctx->encDec = 1;
+						__nvt_aes_crypt(ctx, input, output, blockChainLen);					
+						if(blockChainLen >= 16) memcpy(ctx->prv_iv, output+blockChainLen-remLen-16 , 16);
+						memcpy(iv,output+blockChainLen-ivLen,ivLen);
+				}
+				length -= blockChainLen;
+        input  += blockChainLen;
+        output += blockChainLen;
+			  if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length;		// For last remainder block chain							
+		}
 		
-    *iv_off = n;
+    *iv_off = remLen;
 
-    return( 0 );
+    return( 0 );		
 }
 
-static int __aes_crypt_over_dma_size_cfb128( mbedtls_aes_context *ctx,
+/* Support partial block encryption/decryption */
+static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx,
                        int mode,
                        size_t length,
                        size_t *iv_off,
@@ -439,15 +465,21 @@ static int __aes_crypt_over_dma_size_cfb128( mbedtls_aes_context *ctx,
 {
     int c;
     size_t n = *iv_off;
-
+		unsigned char iv_tmp[16];
 		mbedtls_trace("=== %s \r\n", __FUNCTION__);
     if( mode == MBEDTLS_AES_DECRYPT )
     {
         while( length-- )
         {
-            if( n == 0 )
+            if( n == 0)
                 mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
-
+						else if( ctx->opMode == AES_MODE_CFB)		// For previous cryption is CFB mode 
+						{
+							memcpy(iv_tmp, iv, n);
+							mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv );
+							memcpy(iv, iv_tmp, n);
+						}
+						
             c = *input++;
             *output++ = (unsigned char)( c ^ iv[n] );
             iv[n] = (unsigned char) c;
@@ -461,7 +493,13 @@ static int __aes_crypt_over_dma_size_cfb128( mbedtls_aes_context *ctx,
         {
             if( n == 0 )
                 mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
-
+						else if( ctx->opMode == AES_MODE_CFB)	// For previous cryption is CFB mode
+						{
+							memcpy(iv_tmp, iv, n);
+							mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv );
+							memcpy(iv, iv_tmp, n);
+						}
+						
             iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ );
 
             n = ( n + 1 ) & 0x0F;
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h
index 0113f269f24..25a8ca53116 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h
@@ -44,6 +44,7 @@ typedef struct
     uint32_t channel;
     uint32_t swapType;
     uint32_t *iv;
+		unsigned char prv_iv[16];
 #if 1	
     uint32_t buf[8]; 
 /* For comparsion with software AES for correctness */ 

From d4609a5166c6db3b65fddb719a7b6d1d0046b1ae Mon Sep 17 00:00:00 2001
From: cyliangtw <cyliang@nuvoton.com>
Date: Tue, 30 Aug 2016 18:09:36 +0800
Subject: [PATCH 32/89] Improve HW AES CFB mode performance for byte cnt
 non-word alignment

---
 .../hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c   | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
index 82f2f4687a8..b915f1ba96c 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
@@ -409,10 +409,12 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
 		}
 		
 		// For address or byte count non-word alignment, go through reserved DMA buffer.
-		if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) || (length%4) )  
+		if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) )  // Must reserved DMA buffer for each block
 		{	
 			  blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ?  MAX_DMA_CHAIN_SIZE : length );
-    } else {
+		} else if(length%4) {																						// Need reserved DMA buffer once for last chain
+				blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ?  (length - length%16) : length );
+    } else {																												// Not need reserved DMA buffer
 			  blockChainLen = length;
     }						
 		

From 77f231fb59fdd310ed806901e6c5433233671d47 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Wed, 31 Aug 2016 11:31:14 +0800
Subject: [PATCH 33/89] Fix SHA accelerator errors

1. Fix clone SHA context error. Convert SHA H/W context to SHA S/W context due to just one instance of SHA H/W.
2. Fix partial update error.
---
 .../TARGET_NUC472/crypto/sha/sha1_alt.c       |  84 +++++---
 .../TARGET_NUC472/crypto/sha/sha1_alt.h       |  15 +-
 .../TARGET_NUC472/crypto/sha/sha1_alt_sw.c    |  38 ++--
 .../TARGET_NUC472/crypto/sha/sha1_alt_sw.h    |  18 +-
 .../TARGET_NUC472/crypto/sha/sha256_alt.c     |  90 +++++---
 .../TARGET_NUC472/crypto/sha/sha256_alt.h     |  15 +-
 .../TARGET_NUC472/crypto/sha/sha256_alt_sw.c  |  38 ++--
 .../TARGET_NUC472/crypto/sha/sha256_alt_sw.h  |  18 +-
 .../TARGET_NUC472/crypto/sha/sha_alt_hw.c     | 200 +++++++++++-------
 .../TARGET_NUC472/crypto/sha/sha_alt_hw.h     |  44 ++--
 10 files changed, 318 insertions(+), 242 deletions(-)

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c
index 5f047164480..7a0c0990310 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c
@@ -25,29 +25,19 @@
 
 #include "sha1_alt.h"
 #include "crypto-misc.h"
+#include "nu_bitutil.h"
+#include "string.h"
 
 void mbedtls_sha1_init(mbedtls_sha1_context *ctx)
 {
     if (crypto_sha_acquire()) {
-        ctx->mbedtls_sha1_init = mbedtls_sha1_hw_init;
-        ctx->mbedtls_sha1_free = mbedtls_sha1_hw_free;
-        ctx->mbedtls_sha1_clone = mbedtls_sha1_hw_clone;
-        ctx->mbedtls_sha1_starts = mbedtls_sha1_hw_starts;
-        ctx->mbedtls_sha1_update = mbedtls_sha1_hw_update;
-        ctx->mbedtls_sha1_finish = mbedtls_sha1_hw_finish;
-        ctx->mbedtls_sha1_process = mbedtls_sha1_hw_process;
+        ctx->ishw = 1;
+        mbedtls_sha1_hw_init(&ctx->hw_ctx);
     }
     else {
-        ctx->mbedtls_sha1_init = mbedtls_sha1_sw_init;
-        ctx->mbedtls_sha1_free = mbedtls_sha1_sw_free;
-        ctx->mbedtls_sha1_clone = mbedtls_sha1_sw_clone;
-        ctx->mbedtls_sha1_starts = mbedtls_sha1_sw_starts;
-        ctx->mbedtls_sha1_update = mbedtls_sha1_sw_update;
-        ctx->mbedtls_sha1_finish = mbedtls_sha1_sw_finish;
-        ctx->mbedtls_sha1_process = mbedtls_sha1_sw_process;
+        ctx->ishw = 0;
+        mbedtls_sha1_sw_init(&ctx->sw_ctx);
     }
-    
-    ctx->mbedtls_sha1_init(ctx);
 }
 
 void mbedtls_sha1_free(mbedtls_sha1_context *ctx)
@@ -56,17 +46,41 @@ void mbedtls_sha1_free(mbedtls_sha1_context *ctx)
         return;
     }
 
-    ctx->mbedtls_sha1_free(ctx);
-    
-    if (ctx->mbedtls_sha1_init == mbedtls_sha1_hw_init) {
+    if (ctx->ishw) {
+        mbedtls_sha1_hw_free(&ctx->hw_ctx);
         crypto_sha_release();
     }
+    else {
+        mbedtls_sha1_sw_free(&ctx->sw_ctx);
+    }
 }
 
 void mbedtls_sha1_clone(mbedtls_sha1_context *dst,
                         const mbedtls_sha1_context *src)
 {
-    *dst = *src;
+    if (src->ishw) {
+        // Clone S/W ctx from H/W ctx
+        dst->ishw = 0;
+        dst->sw_ctx.total[0] = src->hw_ctx.total;
+        dst->sw_ctx.total[1] = 0;
+        {
+            unsigned char output[20];
+            crypto_sha_getinternstate(output, sizeof (output));
+            dst->sw_ctx.state[0] = nu_get32_be(output);
+            dst->sw_ctx.state[1] = nu_get32_be(output + 4);
+            dst->sw_ctx.state[2] = nu_get32_be(output + 8);
+            dst->sw_ctx.state[3] = nu_get32_be(output + 12);
+            dst->sw_ctx.state[4] = nu_get32_be(output + 16);
+        }
+        memcpy(dst->sw_ctx.buffer, src->hw_ctx.buffer, src->hw_ctx.buffer_left);
+        if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) {
+            mbedtls_sha1_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer);
+        }
+    }
+    else {
+        // Clone S/W ctx from S/W ctx
+        dst->sw_ctx = src->sw_ctx;
+    }
 }
 
 /*
@@ -74,9 +88,12 @@ void mbedtls_sha1_clone(mbedtls_sha1_context *dst,
  */
 void mbedtls_sha1_starts(mbedtls_sha1_context *ctx)
 {
-    ctx->mbedtls_sha1_starts(ctx);
-    
-    return;
+    if (ctx->ishw) {
+        mbedtls_sha1_hw_starts(&ctx->hw_ctx);
+    }
+    else {
+        mbedtls_sha1_sw_starts(&ctx->sw_ctx);
+    }
 }
 
 /*
@@ -84,7 +101,12 @@ void mbedtls_sha1_starts(mbedtls_sha1_context *ctx)
  */
 void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen)
 {
-    ctx->mbedtls_sha1_update(ctx, input, ilen);
+    if (ctx->ishw) {
+        mbedtls_sha1_hw_update(&ctx->hw_ctx, input, ilen);
+    }
+    else {
+        mbedtls_sha1_sw_update(&ctx->sw_ctx, input, ilen);
+    }
 }
 
 /*
@@ -92,12 +114,22 @@ void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input,
  */
 void mbedtls_sha1_finish(mbedtls_sha1_context *ctx, unsigned char output[20])
 {
-    ctx->mbedtls_sha1_finish(ctx, output);
+    if (ctx->ishw) {
+        mbedtls_sha1_hw_finish(&ctx->hw_ctx, output);
+    }
+    else {
+        mbedtls_sha1_sw_finish(&ctx->sw_ctx, output);
+    }
 }
 
 void mbedtls_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[64])
 {
-    ctx->mbedtls_sha1_process(ctx, data);
+    if (ctx->ishw) {
+        mbedtls_sha1_hw_process(&ctx->hw_ctx, data);
+    }
+    else {
+        mbedtls_sha1_sw_process(&ctx->sw_ctx, data);
+    }
 }
 
 #endif /* MBEDTLS_SHA1_ALT */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h
index a4c3c7e5ccb..620a007ee69 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h
@@ -40,18 +40,9 @@ struct mbedtls_sha1_context_s;
  */
 typedef struct mbedtls_sha1_context_s
 {
-    union {
-        crypto_sha_context hw_ctx;
-        mbedtls_sha1_sw_context sw_ctx;
-    };
-    
-    void (*mbedtls_sha1_init)(struct mbedtls_sha1_context_s *ctx);
-    void (*mbedtls_sha1_free)(struct mbedtls_sha1_context_s *ctx);
-    void (*mbedtls_sha1_clone)(struct mbedtls_sha1_context_s *dst, const struct mbedtls_sha1_context_s *src);
-    void (*mbedtls_sha1_starts)(struct mbedtls_sha1_context_s *ctx);
-    void (*mbedtls_sha1_update)(struct mbedtls_sha1_context_s *ctx, const unsigned char *input, size_t ilen);
-    void (*mbedtls_sha1_finish)(struct mbedtls_sha1_context_s *ctx, unsigned char output[20]);
-    void (*mbedtls_sha1_process)(struct mbedtls_sha1_context_s *ctx, const unsigned char data[64]);
+    int ishw;
+    crypto_sha_context hw_ctx;
+    mbedtls_sha1_sw_context sw_ctx;
 }
 mbedtls_sha1_context;
 
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c
index 946366e1b06..7f2d6d35cd1 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c
@@ -65,32 +65,30 @@ static void mbedtls_zeroize( void *v, size_t n ) {
 }
 #endif
 
-void mbedtls_sha1_sw_init( mbedtls_sha1_context *ctx )
+void mbedtls_sha1_sw_init( mbedtls_sha1_sw_context *ctx )
 {
-    memset( &ctx->sw_ctx, 0, sizeof( ctx->sw_ctx ) );
+    memset( ctx, 0, sizeof( mbedtls_sha1_sw_context ) );
 }
 
-void mbedtls_sha1_sw_free( mbedtls_sha1_context *ctx )
+void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx )
 {
     if( ctx == NULL )
         return;
 
-    mbedtls_zeroize( &ctx->sw_ctx, sizeof( ctx->sw_ctx ) );
+    mbedtls_zeroize( ctx, sizeof( mbedtls_sha1_sw_context ) );
 }
 
-void mbedtls_sha1_sw_clone( mbedtls_sha1_context *dst,
-                         const mbedtls_sha1_context *src )
+void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst,
+                         const mbedtls_sha1_sw_context *src )
 {
-    dst->sw_ctx = src->sw_ctx;
+    *dst = *src;
 }
 
 /*
  * SHA-1 context setup
  */
-void mbedtls_sha1_sw_starts( mbedtls_sha1_context *ctx_ )
+void mbedtls_sha1_sw_starts( mbedtls_sha1_sw_context *ctx )
 {
-    mbedtls_sha1_sw_context *ctx = &ctx_->sw_ctx;
-    
     ctx->total[0] = 0;
     ctx->total[1] = 0;
 
@@ -101,10 +99,8 @@ void mbedtls_sha1_sw_starts( mbedtls_sha1_context *ctx_ )
     ctx->state[4] = 0xC3D2E1F0;
 }
 
-void mbedtls_sha1_sw_process( mbedtls_sha1_context *ctx_, const unsigned char data[64] )
+void mbedtls_sha1_sw_process( mbedtls_sha1_sw_context *ctx, const unsigned char data[64] )
 {
-    mbedtls_sha1_sw_context *ctx = &ctx_->sw_ctx;
-    
     uint32_t temp, W[16], A, B, C, D, E;
 
     GET_UINT32_BE( W[ 0], data,  0 );
@@ -262,10 +258,8 @@ void mbedtls_sha1_sw_process( mbedtls_sha1_context *ctx_, const unsigned char da
 /*
  * SHA-1 process buffer
  */
-void mbedtls_sha1_sw_update( mbedtls_sha1_context *ctx_, const unsigned char *input, size_t ilen )
+void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char *input, size_t ilen )
 {
-    mbedtls_sha1_sw_context *ctx = &ctx_->sw_ctx;
-    
     size_t fill;
     uint32_t left;
 
@@ -284,7 +278,7 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_context *ctx_, const unsigned char *in
     if( left && ilen >= fill )
     {
         memcpy( (void *) (ctx->buffer + left), input, fill );
-        mbedtls_sha1_sw_process( ctx_, ctx->buffer );
+        mbedtls_sha1_sw_process( ctx, ctx->buffer );
         input += fill;
         ilen  -= fill;
         left = 0;
@@ -292,7 +286,7 @@ void mbedtls_sha1_sw_update( mbedtls_sha1_context *ctx_, const unsigned char *in
 
     while( ilen >= 64 )
     {
-        mbedtls_sha1_sw_process( ctx_, input );
+        mbedtls_sha1_sw_process( ctx, input );
         input += 64;
         ilen  -= 64;
     }
@@ -312,10 +306,8 @@ static const unsigned char sha1_padding[64] =
 /*
  * SHA-1 final digest
  */
-void mbedtls_sha1_sw_finish( mbedtls_sha1_context *ctx_, unsigned char output[20] )
+void mbedtls_sha1_sw_finish( mbedtls_sha1_sw_context *ctx, unsigned char output[20] )
 {
-    mbedtls_sha1_sw_context *ctx = &ctx_->sw_ctx;
-    
     uint32_t last, padn;
     uint32_t high, low;
     unsigned char msglen[8];
@@ -330,8 +322,8 @@ void mbedtls_sha1_sw_finish( mbedtls_sha1_context *ctx_, unsigned char output[20
     last = ctx->total[0] & 0x3F;
     padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
 
-    mbedtls_sha1_sw_update( ctx_, sha1_padding, padn );
-    mbedtls_sha1_sw_update( ctx_, msglen, 8 );
+    mbedtls_sha1_sw_update( ctx, sha1_padding, padn );
+    mbedtls_sha1_sw_update( ctx, msglen, 8 );
 
     PUT_UINT32_BE( ctx->state[0], output,  0 );
     PUT_UINT32_BE( ctx->state[1], output,  4 );
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h
index 4b0ab56f509..9d138abb8ac 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h
@@ -39,8 +39,6 @@
 extern "C" {
 #endif
 
-struct mbedtls_sha1_context_s;
-
 /**
  * \brief          SHA-1 context structure
  */
@@ -57,14 +55,14 @@ mbedtls_sha1_sw_context;
  *
  * \param ctx      SHA-1 context to be initialized
  */
-void mbedtls_sha1_sw_init( struct mbedtls_sha1_context_s *ctx );
+void mbedtls_sha1_sw_init( mbedtls_sha1_sw_context *ctx );
 
 /**
  * \brief          Clear SHA-1 context
  *
  * \param ctx      SHA-1 context to be cleared
  */
-void mbedtls_sha1_sw_free( struct mbedtls_sha1_context_s *ctx );
+void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx );
 
 /**
  * \brief          Clone (the state of) a SHA-1 context
@@ -72,15 +70,15 @@ void mbedtls_sha1_sw_free( struct mbedtls_sha1_context_s *ctx );
  * \param dst      The destination context
  * \param src      The context to be cloned
  */
-void mbedtls_sha1_sw_clone( struct mbedtls_sha1_context_s *dst,
-                         const struct mbedtls_sha1_context_s *src );
+void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst,
+                         const mbedtls_sha1_sw_context *src );
 
 /**
  * \brief          SHA-1 context setup
  *
  * \param ctx      context to be initialized
  */
-void mbedtls_sha1_sw_starts( struct mbedtls_sha1_context_s *ctx );
+void mbedtls_sha1_sw_starts( mbedtls_sha1_sw_context *ctx );
 
 /**
  * \brief          SHA-1 process buffer
@@ -89,7 +87,7 @@ void mbedtls_sha1_sw_starts( struct mbedtls_sha1_context_s *ctx );
  * \param input    buffer holding the  data
  * \param ilen     length of the input data
  */
-void mbedtls_sha1_sw_update( struct mbedtls_sha1_context_s *ctx, const unsigned char *input, size_t ilen );
+void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char *input, size_t ilen );
 
 /**
  * \brief          SHA-1 final digest
@@ -97,10 +95,10 @@ void mbedtls_sha1_sw_update( struct mbedtls_sha1_context_s *ctx, const unsigned
  * \param ctx      SHA-1 context
  * \param output   SHA-1 checksum result
  */
-void mbedtls_sha1_sw_finish( struct mbedtls_sha1_context_s *ctx, unsigned char output[20] );
+void mbedtls_sha1_sw_finish( mbedtls_sha1_sw_context *ctx, unsigned char output[20] );
 
 /* Internal use */
-void mbedtls_sha1_sw_process( struct mbedtls_sha1_context_s *ctx, const unsigned char data[64] );
+void mbedtls_sha1_sw_process( mbedtls_sha1_sw_context *ctx, const unsigned char data[64] );
 
 #ifdef __cplusplus
 }
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c
index 96859ef47bd..221a97ff3d4 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c
@@ -25,29 +25,19 @@
 
 #include "sha256_alt.h"
 #include "crypto-misc.h"
+#include "nu_bitutil.h"
+#include "string.h"
 
 void mbedtls_sha256_init(mbedtls_sha256_context *ctx)
 {
     if (crypto_sha_acquire()) {
-        ctx->mbedtls_sha256_init = mbedtls_sha256_hw_init;
-        ctx->mbedtls_sha256_free = mbedtls_sha256_hw_free;
-        ctx->mbedtls_sha256_clone = mbedtls_sha256_hw_clone;
-        ctx->mbedtls_sha256_starts = mbedtls_sha256_hw_starts;
-        ctx->mbedtls_sha256_update = mbedtls_sha256_hw_update;
-        ctx->mbedtls_sha256_finish = mbedtls_sha256_hw_finish;
-        ctx->mbedtls_sha256_process = mbedtls_sha256_hw_process;
+        ctx->ishw = 1;
+        mbedtls_sha256_hw_init(&ctx->hw_ctx);
     }
     else {
-        ctx->mbedtls_sha256_init = mbedtls_sha256_sw_init;
-        ctx->mbedtls_sha256_free = mbedtls_sha256_sw_free;
-        ctx->mbedtls_sha256_clone = mbedtls_sha256_sw_clone;
-        ctx->mbedtls_sha256_starts = mbedtls_sha256_sw_starts;
-        ctx->mbedtls_sha256_update = mbedtls_sha256_sw_update;
-        ctx->mbedtls_sha256_finish = mbedtls_sha256_sw_finish;
-        ctx->mbedtls_sha256_process = mbedtls_sha256_sw_process;
+        ctx->ishw = 0;
+        mbedtls_sha256_sw_init(&ctx->sw_ctx);
     }
-    
-    ctx->mbedtls_sha256_init(ctx);
 }
 
 void mbedtls_sha256_free(mbedtls_sha256_context *ctx)
@@ -56,17 +46,45 @@ void mbedtls_sha256_free(mbedtls_sha256_context *ctx)
         return;
     }
 
-    ctx->mbedtls_sha256_free(ctx);
-    
-    if (ctx->mbedtls_sha256_init == mbedtls_sha256_hw_init) {
+    if (ctx->ishw) {
+        mbedtls_sha256_hw_free(&ctx->hw_ctx);
         crypto_sha_release();
     }
+    else {
+        mbedtls_sha256_sw_free(&ctx->sw_ctx);
+    }
 }
 
 void mbedtls_sha256_clone(mbedtls_sha256_context *dst,
                         const mbedtls_sha256_context *src)
 {
-    *dst = *src;
+    if (src->ishw) {
+        // Clone S/W ctx from H/W ctx
+        dst->ishw = 0;
+        dst->sw_ctx.total[0] = src->hw_ctx.total;
+        dst->sw_ctx.total[1] = 0;
+        {
+            unsigned char output[32];
+            crypto_sha_getinternstate(output, sizeof (output));
+            dst->sw_ctx.state[0] = nu_get32_be(output);
+            dst->sw_ctx.state[1] = nu_get32_be(output + 4);
+            dst->sw_ctx.state[2] = nu_get32_be(output + 8);
+            dst->sw_ctx.state[3] = nu_get32_be(output + 12);
+            dst->sw_ctx.state[4] = nu_get32_be(output + 16);
+            dst->sw_ctx.state[5] = nu_get32_be(output + 20);
+            dst->sw_ctx.state[6] = nu_get32_be(output + 24);
+            dst->sw_ctx.state[7] = nu_get32_be(output + 28);
+        }
+        memcpy(dst->sw_ctx.buffer, src->hw_ctx.buffer, src->hw_ctx.buffer_left);
+        dst->sw_ctx.is224 = src->hw_ctx.is224;
+        if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) {
+            mbedtls_sha256_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer);
+        }
+    }
+    else {
+        // Clone S/W ctx from S/W ctx
+        dst->sw_ctx = src->sw_ctx;
+    }
 }
 
 /*
@@ -74,9 +92,12 @@ void mbedtls_sha256_clone(mbedtls_sha256_context *dst,
  */
 void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224)
 {   
-    ctx->mbedtls_sha256_starts(ctx, is224);
-    
-    return;
+    if (ctx->ishw) {
+        mbedtls_sha256_hw_starts(&ctx->hw_ctx, is224);
+    }
+    else {
+        mbedtls_sha256_sw_starts(&ctx->sw_ctx, is224);
+    }
 }
 
 /*
@@ -84,20 +105,35 @@ void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224)
  */
 void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen)
 {
-    ctx->mbedtls_sha256_update(ctx, input, ilen);
+    if (ctx->ishw) {
+        mbedtls_sha256_hw_update(&ctx->hw_ctx, input, ilen);
+    }
+    else {
+        mbedtls_sha256_sw_update(&ctx->sw_ctx, input, ilen);
+    }
 }
 
 /*
  * SHA-256 final digest
  */
-void mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char output[20])
+void mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char output[32])
 {
-    ctx->mbedtls_sha256_finish(ctx, output);
+    if (ctx->ishw) {
+        mbedtls_sha256_hw_finish(&ctx->hw_ctx, output);
+    }
+    else {
+        mbedtls_sha256_sw_finish(&ctx->sw_ctx, output);
+    }
 }
 
 void mbedtls_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[64])
 {
-    ctx->mbedtls_sha256_process(ctx, data);
+    if (ctx->ishw) {
+        mbedtls_sha256_hw_process(&ctx->hw_ctx, data);
+    }
+    else {
+        mbedtls_sha256_sw_process(&ctx->sw_ctx, data);
+    }
 }
 
 #endif /* MBEDTLS_SHA256_ALT */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h
index 4274fc86f33..6ea3c395610 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h
@@ -40,18 +40,9 @@ struct mbedtls_sha256_context_s;
  */
 typedef struct mbedtls_sha256_context_s
 {
-    union {
-        crypto_sha_context hw_ctx;
-        mbedtls_sha256_sw_context sw_ctx;
-    };
-    
-    void (*mbedtls_sha256_init)(struct mbedtls_sha256_context_s *ctx);
-    void (*mbedtls_sha256_free)(struct mbedtls_sha256_context_s *ctx);
-    void (*mbedtls_sha256_clone)(struct mbedtls_sha256_context_s *dst, const struct mbedtls_sha256_context_s *src);
-    void (*mbedtls_sha256_starts)(struct mbedtls_sha256_context_s *ctx, int is224);
-    void (*mbedtls_sha256_update)(struct mbedtls_sha256_context_s *ctx, const unsigned char *input, size_t ilen);
-    void (*mbedtls_sha256_finish)(struct mbedtls_sha256_context_s *ctx, unsigned char output[20]);
-    void (*mbedtls_sha256_process)(struct mbedtls_sha256_context_s *ctx, const unsigned char data[64]);
+    int ishw;
+    crypto_sha_context hw_ctx;
+    mbedtls_sha256_sw_context sw_ctx;
 }
 mbedtls_sha256_context;
 
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c
index 5d5a252c4af..f2dfb825c49 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c
@@ -65,32 +65,30 @@ do {                                                    \
 } while( 0 )
 #endif
 
-void mbedtls_sha256_sw_init( mbedtls_sha256_context *ctx )
+void mbedtls_sha256_sw_init( mbedtls_sha256_sw_context *ctx )
 {
-    memset( &ctx->sw_ctx, 0, sizeof( ctx->sw_ctx ) );
+    memset( ctx, 0, sizeof( mbedtls_sha256_sw_context ) );
 }
 
-void mbedtls_sha256_sw_free( mbedtls_sha256_context *ctx )
+void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx )
 {
     if( ctx == NULL )
         return;
 
-    mbedtls_zeroize( &ctx->sw_ctx, sizeof( ctx->sw_ctx ) );
+    mbedtls_zeroize( ctx, sizeof( mbedtls_sha256_sw_context ) );
 }
 
-void mbedtls_sha256_sw_clone( mbedtls_sha256_context *dst,
-                           const mbedtls_sha256_context *src )
+void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst,
+                           const mbedtls_sha256_sw_context *src )
 {
-    dst->sw_ctx = src->sw_ctx;
+    *dst = *src;
 }
 
 /*
  * SHA-256 context setup
  */
-void mbedtls_sha256_sw_starts( mbedtls_sha256_context *ctx_, int is224 )
+void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 )
 {
-    mbedtls_sha256_sw_context *ctx = &ctx_->sw_ctx;
-    
     ctx->total[0] = 0;
     ctx->total[1] = 0;
 
@@ -167,10 +165,8 @@ static const uint32_t K[] =
     d += temp1; h = temp1 + temp2;              \
 }
 
-void mbedtls_sha256_sw_process( mbedtls_sha256_context *ctx_, const unsigned char data[64] )
+void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned char data[64] )
 {
-    mbedtls_sha256_sw_context *ctx = &ctx_->sw_ctx;
-    
     uint32_t temp1, temp2, W[64];
     uint32_t A[8];
     unsigned int i;
@@ -227,11 +223,9 @@ void mbedtls_sha256_sw_process( mbedtls_sha256_context *ctx_, const unsigned cha
 /*
  * SHA-256 process buffer
  */
-void mbedtls_sha256_sw_update( mbedtls_sha256_context *ctx_, const unsigned char *input,
+void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input,
                     size_t ilen )
 {
-    mbedtls_sha256_sw_context *ctx = &ctx_->sw_ctx;
-    
     size_t fill;
     uint32_t left;
 
@@ -250,7 +244,7 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_context *ctx_, const unsigned char
     if( left && ilen >= fill )
     {
         memcpy( (void *) (ctx->buffer + left), input, fill );
-        mbedtls_sha256_sw_process( ctx_, ctx->buffer );
+        mbedtls_sha256_sw_process( ctx, ctx->buffer );
         input += fill;
         ilen  -= fill;
         left = 0;
@@ -258,7 +252,7 @@ void mbedtls_sha256_sw_update( mbedtls_sha256_context *ctx_, const unsigned char
 
     while( ilen >= 64 )
     {
-        mbedtls_sha256_sw_process( ctx_, input );
+        mbedtls_sha256_sw_process( ctx, input );
         input += 64;
         ilen  -= 64;
     }
@@ -278,10 +272,8 @@ static const unsigned char sha256_padding[64] =
 /*
  * SHA-256 final digest
  */
-void mbedtls_sha256_sw_finish( mbedtls_sha256_context *ctx_, unsigned char output[32] )
+void mbedtls_sha256_sw_finish( mbedtls_sha256_sw_context *ctx, unsigned char output[32] )
 {
-    mbedtls_sha256_sw_context *ctx = &ctx_->sw_ctx;
-    
     uint32_t last, padn;
     uint32_t high, low;
     unsigned char msglen[8];
@@ -296,8 +288,8 @@ void mbedtls_sha256_sw_finish( mbedtls_sha256_context *ctx_, unsigned char outpu
     last = ctx->total[0] & 0x3F;
     padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
 
-    mbedtls_sha256_sw_update( ctx_, sha256_padding, padn );
-    mbedtls_sha256_sw_update( ctx_, msglen, 8 );
+    mbedtls_sha256_sw_update( ctx, sha256_padding, padn );
+    mbedtls_sha256_sw_update( ctx, msglen, 8 );
 
     PUT_UINT32_BE( ctx->state[0], output,  0 );
     PUT_UINT32_BE( ctx->state[1], output,  4 );
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h
index 938b5920fcc..c1b72ea8f70 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h
@@ -39,8 +39,6 @@
 extern "C" {
 #endif
 
-struct mbedtls_sha256_context_s;
-
 /**
  * \brief          SHA-256 context structure
  */
@@ -58,14 +56,14 @@ mbedtls_sha256_sw_context;
  *
  * \param ctx      SHA-256 context to be initialized
  */
-void mbedtls_sha256_sw_init( struct mbedtls_sha256_context_s *ctx );
+void mbedtls_sha256_sw_init( mbedtls_sha256_sw_context *ctx );
 
 /**
  * \brief          Clear SHA-256 context
  *
  * \param ctx      SHA-256 context to be cleared
  */
-void mbedtls_sha256_sw_free( struct mbedtls_sha256_context_s *ctx );
+void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx );
 
 /**
  * \brief          Clone (the state of) a SHA-256 context
@@ -73,8 +71,8 @@ void mbedtls_sha256_sw_free( struct mbedtls_sha256_context_s *ctx );
  * \param dst      The destination context
  * \param src      The context to be cloned
  */
-void mbedtls_sha256_sw_clone( struct mbedtls_sha256_context_s *dst,
-                           const struct mbedtls_sha256_context_s *src );
+void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst,
+                           const mbedtls_sha256_sw_context *src );
 
 /**
  * \brief          SHA-256 context setup
@@ -82,7 +80,7 @@ void mbedtls_sha256_sw_clone( struct mbedtls_sha256_context_s *dst,
  * \param ctx      context to be initialized
  * \param is224    0 = use SHA256, 1 = use SHA224
  */
-void mbedtls_sha256_sw_starts( struct mbedtls_sha256_context_s *ctx, int is224 );
+void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 );
 
 /**
  * \brief          SHA-256 process buffer
@@ -91,7 +89,7 @@ void mbedtls_sha256_sw_starts( struct mbedtls_sha256_context_s *ctx, int is224 )
  * \param input    buffer holding the  data
  * \param ilen     length of the input data
  */
-void mbedtls_sha256_sw_update( struct mbedtls_sha256_context_s *ctx, const unsigned char *input,
+void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input,
                     size_t ilen );
 
 /**
@@ -100,10 +98,10 @@ void mbedtls_sha256_sw_update( struct mbedtls_sha256_context_s *ctx, const unsig
  * \param ctx      SHA-256 context
  * \param output   SHA-224/256 checksum result
  */
-void mbedtls_sha256_sw_finish( struct mbedtls_sha256_context_s *ctx, unsigned char output[32] );
+void mbedtls_sha256_sw_finish( mbedtls_sha256_sw_context *ctx, unsigned char output[32] );
 
 /* Internal use */
-void mbedtls_sha256_sw_process( struct mbedtls_sha256_context_s *ctx, const unsigned char data[64] );
+void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned char data[64] );
 
 #ifdef __cplusplus
 }
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c
index 0c71ae87879..3e1374aac75 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c
@@ -42,59 +42,79 @@
 
 #include <string.h>
 
-static void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen);
-static void crypto_sha_getinternstate(unsigned char output[], size_t olen);
-static void crypto_sha_lastword(crypto_sha_context *ctx, int islast);
+void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen);
+void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast);
+void crypto_sha_getinternstate(unsigned char output[], size_t olen);
 
 #endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */
 
 #if defined(MBEDTLS_SHA1_ALT)
 
-void mbedtls_sha1_hw_init(mbedtls_sha1_context *ctx)
+void mbedtls_sha1_hw_init(crypto_sha_context *ctx)
 {
     crypto_init();
-    memset(&ctx->hw_ctx, 0, sizeof(ctx->hw_ctx));
+    memset(ctx, 0, sizeof(crypto_sha_context));
 }
 
-void mbedtls_sha1_hw_free(mbedtls_sha1_context *ctx)
+void mbedtls_sha1_hw_free(crypto_sha_context *ctx)
 {
     if (ctx == NULL) {
         return;
     }
 
-    crypto_zeroize(&ctx->hw_ctx, sizeof(ctx->hw_ctx));
+    crypto_zeroize(ctx, sizeof(crypto_sha_context));
 }
 
-void mbedtls_sha1_hw_clone(mbedtls_sha1_context *dst,
-                        const mbedtls_sha1_context *src)
+void mbedtls_sha1_hw_clone(crypto_sha_context *dst,
+                        const crypto_sha_context *src)
 {
-    dst->hw_ctx = src->hw_ctx;
+    *dst = *src;
 }
 
-void mbedtls_sha1_hw_starts(mbedtls_sha1_context *ctx)
+void mbedtls_sha1_hw_starts(crypto_sha_context *ctx)
 {
-    ctx->hw_ctx.total = 0;
-    ctx->hw_ctx.lastword_size = 0;
-    ctx->hw_ctx.blocksize = 64;
-    ctx->hw_ctx.blocksize_mask = 0x3F;
+    // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it.
+    CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk;
+    
+    ctx->total = 0;
+    ctx->buffer_left = 0;
+    ctx->blocksize = 64;
+    ctx->blocksize_mask = 0x3F;
 
     SHA_Open(SHA_MODE_SHA1, SHA_NO_SWAP);
     
+    // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started.
+    CRPT->SHA_CTL |= CRPT_SHA_CTL_START_Msk;
+    
     return;
 }
 
-void mbedtls_sha1_hw_update(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen)
+void mbedtls_sha1_hw_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen)
 {
-    crypto_sha_update(&ctx->hw_ctx, input, ilen);
+    crypto_sha_update(ctx, input, ilen);
 }
 
-void mbedtls_sha1_hw_finish(mbedtls_sha1_context *ctx, unsigned char output[20])
+void mbedtls_sha1_hw_finish(crypto_sha_context *ctx, unsigned char output[20])
 {
-    crypto_sha_lastword(&ctx->hw_ctx, 1);
-    crypto_sha_getinternstate(output, 20);
+    // H/W SHA cannot handle zero data well. Fall back to S/W SHA.
+    if (ctx->total) {
+        crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1);
+        ctx->buffer_left = 0;
+        crypto_sha_getinternstate(output, 20);
+    
+        CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk;
+    }
+    else {
+        mbedtls_sha1_sw_context ctx_sw;
+    
+        mbedtls_sha1_sw_init(&ctx_sw);
+        mbedtls_sha1_sw_starts(&ctx_sw);
+        mbedtls_sha1_sw_finish(&ctx_sw, output);
+        mbedtls_sha1_sw_free(&ctx_sw);
+    }
 }
 
-void mbedtls_sha1_hw_process(mbedtls_sha1_context *ctx, const unsigned char data[64])
+void mbedtls_sha1_hw_process(crypto_sha_context *ctx, const unsigned char data[64])
 {
     mbedtls_sha1_hw_update(ctx, data, 64);
 }
@@ -103,52 +123,72 @@ void mbedtls_sha1_hw_process(mbedtls_sha1_context *ctx, const unsigned char data
 
 #if defined(MBEDTLS_SHA256_ALT)
 
-void mbedtls_sha256_hw_init(mbedtls_sha256_context *ctx)
+void mbedtls_sha256_hw_init(crypto_sha_context *ctx)
 {
     crypto_init();
-    memset(&ctx->hw_ctx, 0, sizeof(ctx->hw_ctx));
+    memset(ctx, 0, sizeof(crypto_sha_context));
 }
 
-void mbedtls_sha256_hw_free(mbedtls_sha256_context *ctx)
+void mbedtls_sha256_hw_free(crypto_sha_context *ctx)
 {
     if (ctx == NULL) {
         return;
     }
 
-    crypto_zeroize(&ctx->hw_ctx, sizeof(ctx->hw_ctx));
+    crypto_zeroize(ctx, sizeof(crypto_sha_context));
 }
 
-void mbedtls_sha256_hw_clone(mbedtls_sha256_context *dst,
-                        const mbedtls_sha256_context *src)
+void mbedtls_sha256_hw_clone(crypto_sha_context *dst,
+                        const crypto_sha_context *src)
 {
-    dst->hw_ctx = src->hw_ctx;
+    *dst = *src;
 }
 
-void mbedtls_sha256_hw_starts( mbedtls_sha256_context *ctx, int is224)
+void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224)
 {
-    ctx->hw_ctx.total = 0;
-    ctx->hw_ctx.lastword_size = 0;
-    ctx->hw_ctx.blocksize = 64;
-    ctx->hw_ctx.blocksize_mask = 0x3F;
-    ctx->hw_ctx.is224 = is224;
+    // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it.
+    CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk;
+     
+    ctx->total = 0;
+    ctx->buffer_left = 0;
+    ctx->blocksize = 64;
+    ctx->blocksize_mask = 0x3F;
+    ctx->is224 = is224;
 
     SHA_Open(is224 ? SHA_MODE_SHA224 : SHA_MODE_SHA256, SHA_NO_SWAP);
     
+    // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started.
+    CRPT->SHA_CTL |= CRPT_SHA_CTL_START_Msk;
+    
     return;
 }
 
-void mbedtls_sha256_hw_update(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen)
+void mbedtls_sha256_hw_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen)
 {
-    crypto_sha_update(&ctx->hw_ctx, input, ilen);
+    crypto_sha_update(ctx, input, ilen);
 }
 
-void mbedtls_sha256_hw_finish(mbedtls_sha256_context *ctx, unsigned char output[32])
+void mbedtls_sha256_hw_finish(crypto_sha_context *ctx, unsigned char output[32])
 {
-    crypto_sha_lastword(&ctx->hw_ctx, 1);
-    crypto_sha_getinternstate(output, ctx->hw_ctx.is224 ? 28 : 32);
+    // H/W SHA cannot handle zero data well. Fall back to S/W SHA.
+    if (ctx->total) {
+        crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1);
+        ctx->buffer_left = 0;
+        crypto_sha_getinternstate(output, ctx->is224 ? 28 : 32);
+    
+        CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk;
+    }
+    else {
+        mbedtls_sha256_sw_context ctx_sw;
+    
+        mbedtls_sha256_sw_init(&ctx_sw);
+        mbedtls_sha256_sw_starts(&ctx_sw, ctx->is224);
+        mbedtls_sha256_sw_finish(&ctx_sw, output);
+        mbedtls_sha256_sw_free(&ctx_sw);
+    }
 }
 
-void mbedtls_sha256_hw_process(mbedtls_sha256_context *ctx, const unsigned char data[64])
+void mbedtls_sha256_hw_process(crypto_sha_context *ctx, const unsigned char data[64])
 {
     mbedtls_sha256_hw_update(ctx, data, 64);
 }
@@ -163,18 +203,54 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size
         return;
     }
     
-    crypto_sha_lastword(ctx, 0);
+    size_t fill = ctx->blocksize - ctx->buffer_left;
 
     ctx->total += (uint32_t) ilen;
 
-    const unsigned char *in_pos = input;
-    uint32_t rmn = ilen;
+    if (ctx->buffer_left && ilen >= fill) {
+        memcpy((void *) (ctx->buffer + ctx->buffer_left), input, fill);
+        input += fill;
+        ilen  -= fill;
+        ctx->buffer_left += fill;
+        if (ilen) {
+            crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 0);
+            ctx->buffer_left = 0;
+        }
+    }
+    
+    while (ilen > ctx->blocksize) {
+        crypto_sha_update_nobuf(ctx, input, ctx->blocksize, 0);
+        input += ctx->blocksize;
+        ilen  -= ctx->blocksize;
+    }
+
+    if (ilen > 0) {
+        memcpy((void *) (ctx->buffer + ctx->buffer_left), input, ilen);
+        ctx->buffer_left += ilen;
+    }
+}
+
+void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast)
+{
+    unsigned char *in_pos = input;
+    int rmn = ilen;
     uint32_t sha_ctl_start = (CRPT->SHA_CTL & ~(CRPT_SHA_CTL_DMALAST_Msk | CRPT_SHA_CTL_DMAEN_Msk)) | CRPT_SHA_CTL_START_Msk;
     
-    while (rmn > 4) {
+    while (rmn > 0) {
         CRPT->SHA_CTL = sha_ctl_start;
         
         uint32_t data = nu_get32_be(in_pos);
+        if (islast && rmn <= 4) {
+            uint32_t lastblock_size = ctx->total & ctx->blocksize_mask;
+            if (lastblock_size == 0) {
+                lastblock_size = ctx->blocksize;
+            }
+            CRPT->SHA_DMACNT = lastblock_size;
+            CRPT->SHA_CTL = sha_ctl_start | CRPT_SHA_CTL_DMALAST_Msk;
+        }
+        else {
+            CRPT->SHA_CTL = sha_ctl_start;
+        }
         while (! (CRPT->SHA_STS & CRPT_SHA_STS_DATINREQ_Msk));
         CRPT->SHA_DATIN = data;
         
@@ -182,12 +258,9 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size
         rmn -= 4;
     }
     
-    MBED_ASSERT(rmn > 0 && rmn <= 4);
-    unsigned char lastword_buf[4];
-    memcpy(lastword_buf, in_pos, rmn);
-    memset(lastword_buf + rmn, 0x00, 4 - rmn);
-    ctx->lastword = nu_get32_be(lastword_buf);
-    ctx->lastword_size = rmn;
+    if (islast) {
+        while (CRPT->SHA_STS & CRPT_SHA_STS_BUSY_Msk);
+    }
 }
 
 void crypto_sha_getinternstate(unsigned char output[], size_t olen)
@@ -204,33 +277,6 @@ void crypto_sha_getinternstate(unsigned char output[], size_t olen)
     }
 }
 
-void crypto_sha_lastword(crypto_sha_context *ctx, int islast)
-{
-    uint32_t sha_ctl_start = (CRPT->SHA_CTL & ~(CRPT_SHA_CTL_DMALAST_Msk | CRPT_SHA_CTL_DMAEN_Msk)) | CRPT_SHA_CTL_START_Msk;
-    
-    if (ctx->lastword_size) {
-        if (islast) {
-            uint32_t lastblock_size = ctx->total & ctx->blocksize_mask;
-            if (lastblock_size == 0) {
-                lastblock_size = ctx->blocksize;
-            }
-            CRPT->SHA_DMACNT = lastblock_size;
-            CRPT->SHA_CTL = sha_ctl_start | CRPT_SHA_CTL_DMALAST_Msk;
-        }
-        else {
-            CRPT->SHA_CTL = sha_ctl_start;
-        }
-        while (! (CRPT->SHA_STS & CRPT_SHA_STS_DATINREQ_Msk));
-        CRPT->SHA_DATIN = ctx->lastword;
-        
-        if (islast) {
-            while (CRPT->SHA_STS & CRPT_SHA_STS_BUSY_Msk);
-        }
-        
-        ctx->lastword_size = 0;
-    }
-}
-
 #endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */
 
 #endif /* MBEDTLS_SHA1_C || MBEDTLS_SHA256_C || MBEDTLS_SHA512_C */
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h
index 070433a6312..fb423ca71eb 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h
@@ -37,8 +37,8 @@ extern "C" {
 typedef struct
 {
     uint32_t total;                 /*!< number of bytes processed  */
-    uint32_t lastword;              /*!< last word unprocessed */
-    uint16_t lastword_size;         /*!< number of bytes of last word unprocessed */
+    unsigned char buffer[128];      /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */
+    uint16_t buffer_left;
     uint16_t blocksize;             /*!< block size */
     uint32_t blocksize_mask;        /*!< block size mask */
     
@@ -46,34 +46,34 @@ typedef struct
 }
 crypto_sha_context;
 
-#if defined(MBEDTLS_SHA1_ALT)
+void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen);
+void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast);
+void crypto_sha_getinternstate(unsigned char output[], size_t olen);
 
-struct mbedtls_sha1_context_s;
+#if defined(MBEDTLS_SHA1_ALT)
 
-void mbedtls_sha1_hw_init( struct mbedtls_sha1_context_s *ctx );
-void mbedtls_sha1_hw_free( struct mbedtls_sha1_context_s *ctx );
-void mbedtls_sha1_hw_clone( struct mbedtls_sha1_context_s *dst,
-                         const struct mbedtls_sha1_context_s *src );
-void mbedtls_sha1_hw_starts( struct mbedtls_sha1_context_s *ctx );
-void mbedtls_sha1_hw_update( struct mbedtls_sha1_context_s *ctx, const unsigned char *input, size_t ilen );
-void mbedtls_sha1_hw_finish( struct mbedtls_sha1_context_s *ctx, unsigned char output[20] );
-void mbedtls_sha1_hw_process( struct mbedtls_sha1_context_s *ctx, const unsigned char data[64] );
+void mbedtls_sha1_hw_init( crypto_sha_context *ctx );
+void mbedtls_sha1_hw_free( crypto_sha_context *ctx );
+void mbedtls_sha1_hw_clone( crypto_sha_context *dst,
+                         const crypto_sha_context *src );
+void mbedtls_sha1_hw_starts( crypto_sha_context *ctx );
+void mbedtls_sha1_hw_update( crypto_sha_context *ctx, const unsigned char *input, size_t ilen );
+void mbedtls_sha1_hw_finish( crypto_sha_context *ctx, unsigned char output[20] );
+void mbedtls_sha1_hw_process( crypto_sha_context *ctx, const unsigned char data[64] );
 
 #endif /* MBEDTLS_SHA1_ALT */
 
 #if defined(MBEDTLS_SHA256_ALT)
 
-struct mbedtls_sha256_context_s;
-
-void mbedtls_sha256_hw_init( struct mbedtls_sha256_context_s *ctx );
-void mbedtls_sha256_hw_free( struct mbedtls_sha256_context_s *ctx );
-void mbedtls_sha256_hw_clone( struct mbedtls_sha256_context_s *dst,
-                           const struct mbedtls_sha256_context_s *src );
-void mbedtls_sha256_hw_starts( struct mbedtls_sha256_context_s *ctx, int is224 );
-void mbedtls_sha256_hw_update( struct mbedtls_sha256_context_s *ctx, const unsigned char *input,
+void mbedtls_sha256_hw_init( crypto_sha_context *ctx );
+void mbedtls_sha256_hw_free( crypto_sha_context *ctx );
+void mbedtls_sha256_hw_clone( crypto_sha_context *dst,
+                           const crypto_sha_context *src );
+void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224 );
+void mbedtls_sha256_hw_update( crypto_sha_context *ctx, const unsigned char *input,
                     size_t ilen );
-void mbedtls_sha256_hw_finish( struct mbedtls_sha256_context_s *ctx, unsigned char output[32] );
-void mbedtls_sha256_hw_process( struct mbedtls_sha256_context_s *ctx, const unsigned char data[64] );
+void mbedtls_sha256_hw_finish( crypto_sha_context *ctx, unsigned char output[32] );
+void mbedtls_sha256_hw_process( crypto_sha_context *ctx, const unsigned char data[64] );
 
 #endif /* MBEDTLS_SHA256_ALT */
 

From d77082f402ac9dfe02423d15b80c5eb87b13f643 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Mon, 5 Sep 2016 10:42:59 +0800
Subject: [PATCH 34/89] Fix no wait for finish of SHA block process

---
 .../TARGET_NUC472/crypto/sha/sha_alt_hw.c     | 69 ++++++++++++++++---
 1 file changed, 60 insertions(+), 9 deletions(-)

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c
index 3e1374aac75..4f26b808d59 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c
@@ -232,23 +232,49 @@ void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size
 
 void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast)
 {
-    unsigned char *in_pos = input;
+    // Accept only:
+    // 1. Last block which may be incomplete
+    // 2. Non-last block which is complete
+    MBED_ASSERT(islast || ilen == ctx->blocksize);
+    
+    const unsigned char *in_pos = input;
     int rmn = ilen;
     uint32_t sha_ctl_start = (CRPT->SHA_CTL & ~(CRPT_SHA_CTL_DMALAST_Msk | CRPT_SHA_CTL_DMAEN_Msk)) | CRPT_SHA_CTL_START_Msk;
+    uint32_t sha_opmode = (CRPT->SHA_CTL & CRPT_SHA_CTL_OPMODE_Msk) >> CRPT_SHA_CTL_OPMODE_Pos;
+    uint32_t DGST0_old, DGST1_old, DGST2_old, DGST3_old, DGST4_old, DGST5_old, DGST6_old, DGST7_old;
     
     while (rmn > 0) {
         CRPT->SHA_CTL = sha_ctl_start;
         
         uint32_t data = nu_get32_be(in_pos);
-        if (islast && rmn <= 4) {
-            uint32_t lastblock_size = ctx->total & ctx->blocksize_mask;
-            if (lastblock_size == 0) {
-                lastblock_size = ctx->blocksize;
+        if (rmn <= 4) { // Last word of a (in)complete block
+            if (islast) {
+                uint32_t lastblock_size = ctx->total & ctx->blocksize_mask;
+                if (lastblock_size == 0) {
+                    lastblock_size = ctx->blocksize;
+                }
+                CRPT->SHA_DMACNT = lastblock_size;
+                CRPT->SHA_CTL = sha_ctl_start | CRPT_SHA_CTL_DMALAST_Msk;
+            }
+            else {
+                switch (sha_opmode) {
+                    case SHA_MODE_SHA256:
+                        DGST7_old = CRPT->SHA_DGST7;
+                    case SHA_MODE_SHA224:
+                        DGST5_old = CRPT->SHA_DGST5;
+                        DGST6_old = CRPT->SHA_DGST6;
+                    case SHA_MODE_SHA1:
+                        DGST0_old = CRPT->SHA_DGST0;
+                        DGST1_old = CRPT->SHA_DGST1;
+                        DGST2_old = CRPT->SHA_DGST2;
+                        DGST3_old = CRPT->SHA_DGST3;
+                        DGST4_old = CRPT->SHA_DGST4;
+                }
+
+                CRPT->SHA_CTL = sha_ctl_start;
             }
-            CRPT->SHA_DMACNT = lastblock_size;
-            CRPT->SHA_CTL = sha_ctl_start | CRPT_SHA_CTL_DMALAST_Msk;
         }
-        else {
+        else {  // Non-last word of a complete block
             CRPT->SHA_CTL = sha_ctl_start;
         }
         while (! (CRPT->SHA_STS & CRPT_SHA_STS_DATINREQ_Msk));
@@ -258,9 +284,34 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input
         rmn -= 4;
     }
     
-    if (islast) {
+    if (islast) {   // Finish of last block
         while (CRPT->SHA_STS & CRPT_SHA_STS_BUSY_Msk);
     }
+    else {  // Finish of non-last block
+        // No H/W flag to indicate finish of non-last block process.
+        // Values of SHA_DGSTx registers will change as last word of the block is input, so use it for judgement.
+        int isfinish = 0;
+        while (! isfinish) {
+            switch (sha_opmode) {
+                case SHA_MODE_SHA256:
+                    if (DGST7_old != CRPT->SHA_DGST7) {
+                        isfinish = 1;
+                        break;
+                    }
+                case SHA_MODE_SHA224:
+                    if (DGST5_old != CRPT->SHA_DGST5 || DGST6_old != CRPT->SHA_DGST6) {
+                        isfinish = 1;
+                        break;
+                    }
+                case SHA_MODE_SHA1:
+                    if (DGST0_old != CRPT->SHA_DGST0 || DGST1_old != CRPT->SHA_DGST1 || DGST2_old != CRPT->SHA_DGST2 ||
+                        DGST3_old != CRPT->SHA_DGST3 || DGST4_old != CRPT->SHA_DGST4) {
+                        isfinish = 1;
+                        break;
+                    }
+            }
+        }
+    }
 }
 
 void crypto_sha_getinternstate(unsigned char output[], size_t olen)

From 31ed4137560bcddedb53f89bea1219d3aeec6e62 Mon Sep 17 00:00:00 2001
From: cyliangtw <cyliang@nuvoton.com>
Date: Mon, 5 Sep 2016 22:23:22 +0800
Subject: [PATCH 35/89] aes_alt support GCC

---
 .../TARGET_NUC472/crypto/aes/aes_alt.c        | 125 +++++++++---------
 1 file changed, 63 insertions(+), 62 deletions(-)

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
index b915f1ba96c..0430dbea0dd 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
@@ -97,7 +97,7 @@ static unsigned char channel_flag[4]={0x00,0x00,0x00,0x00};  // 0: idle, 1: busy
 static int channel_alloc()
 {
 	int i;
-	for(i=0; i< sizeof(channel_flag); i++)
+	for(i=0; i< (int)sizeof(channel_flag); i++)
 	{
 		if( channel_flag[i] == 0x00 )
 		{
@@ -110,7 +110,7 @@ static int channel_alloc()
 
 static void channel_free(int i)
 {
-	if( i >=0 && i < sizeof(channel_flag) )
+	if( i >=0 && i < (int)sizeof(channel_flag) )
 		channel_flag[i] = 0x00;
 }
 
@@ -142,13 +142,13 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx )
 
     NVIC_EnableIRQ(CRPT_IRQn);
     AES_ENABLE_INT();    	
-	  mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__, ctx->channel);
+	  mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__, (int)ctx->channel);
 }
 
 void mbedtls_aes_free( mbedtls_aes_context *ctx )
 {
 
-	  mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__,ctx->channel);	
+	  mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__,(int)ctx->channel);	
 
     if( ctx == NULL )
         return;
@@ -248,7 +248,7 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx,
 			memcpy(au8InputData, input, dataSize);
 			pIn = au8InputData;
 		}else{
-		  pIn = input;
+		  pIn = (unsigned char*)input;
     }
 		if( (((uint32_t)output) & 0x03) || (dataSize%4))   // HW CFB output byte count must be multiple of word
 		{		
@@ -338,7 +338,7 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
     unsigned char temp[16];
     int length = len;
 	  int blockChainLen;
-		mbedtls_trace("=== %s \r\n", __FUNCTION__);
+		mbedtls_trace("=== %s [0x%x]\r\n", __FUNCTION__,length);
     if( length % 16 )
         return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
 
@@ -383,6 +383,63 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
 /*
  * AES-CFB128 buffer encryption/decryption
  */
+/* Support partial block encryption/decryption */
+static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx,
+                       int mode,
+                       size_t length,
+                       size_t *iv_off,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output )
+{
+    int c;
+    size_t n = *iv_off;
+		unsigned char iv_tmp[16];
+		mbedtls_trace("=== %s \r\n", __FUNCTION__);
+    if( mode == MBEDTLS_AES_DECRYPT )
+    {
+        while( length-- )
+        {
+            if( n == 0)
+                mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
+						else if( ctx->opMode == AES_MODE_CFB)		// For previous cryption is CFB mode 
+						{
+							memcpy(iv_tmp, iv, n);
+							mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv );
+							memcpy(iv, iv_tmp, n);
+						}
+						
+            c = *input++;
+            *output++ = (unsigned char)( c ^ iv[n] );
+            iv[n] = (unsigned char) c;
+
+            n = ( n + 1 ) & 0x0F;
+        }
+    }
+    else
+    {
+        while( length-- )
+        {
+            if( n == 0 )
+                mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
+						else if( ctx->opMode == AES_MODE_CFB)	// For previous cryption is CFB mode
+						{
+							memcpy(iv_tmp, iv, n);
+							mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv );
+							memcpy(iv, iv_tmp, n);
+						}
+						
+            iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ );
+
+            n = ( n + 1 ) & 0x0F;
+        }
+    }
+
+    *iv_off = n;
+
+    return( 0 );
+}
+
 int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
                        int mode,
                        size_t len,
@@ -456,62 +513,6 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
     return( 0 );		
 }
 
-/* Support partial block encryption/decryption */
-static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx,
-                       int mode,
-                       size_t length,
-                       size_t *iv_off,
-                       unsigned char iv[16],
-                       const unsigned char *input,
-                       unsigned char *output )
-{
-    int c;
-    size_t n = *iv_off;
-		unsigned char iv_tmp[16];
-		mbedtls_trace("=== %s \r\n", __FUNCTION__);
-    if( mode == MBEDTLS_AES_DECRYPT )
-    {
-        while( length-- )
-        {
-            if( n == 0)
-                mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
-						else if( ctx->opMode == AES_MODE_CFB)		// For previous cryption is CFB mode 
-						{
-							memcpy(iv_tmp, iv, n);
-							mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv );
-							memcpy(iv, iv_tmp, n);
-						}
-						
-            c = *input++;
-            *output++ = (unsigned char)( c ^ iv[n] );
-            iv[n] = (unsigned char) c;
-
-            n = ( n + 1 ) & 0x0F;
-        }
-    }
-    else
-    {
-        while( length-- )
-        {
-            if( n == 0 )
-                mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
-						else if( ctx->opMode == AES_MODE_CFB)	// For previous cryption is CFB mode
-						{
-							memcpy(iv_tmp, iv, n);
-							mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv );
-							memcpy(iv, iv_tmp, n);
-						}
-						
-            iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ );
-
-            n = ( n + 1 ) & 0x0F;
-        }
-    }
-
-    *iv_off = n;
-
-    return( 0 );
-}
 
 /*
  * AES-CFB8 buffer encryption/decryption

From adac6c639af6c312d62954fd302cd8c79439e8fd Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Wed, 7 Sep 2016 14:53:53 +0800
Subject: [PATCH 36/89] Fix greentea lp_ticker failed tests

---
 .../TARGET_NUVOTON/TARGET_M451/lp_ticker.c    | 65 ++++++++++---------
 .../TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c  | 63 +++++++++---------
 2 files changed, 67 insertions(+), 61 deletions(-)

diff --git a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
index 3e510fc9eef..b926e8c3c94 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
@@ -24,16 +24,13 @@
 #include "critical.h"
 
 // lp_ticker tick = us = timestamp
-// clock of timer peripheral = ms
-#define US_PER_TICK         (1)
+#define US_PER_TICK             (1)
+#define US_PER_SEC              (1000 * 1000)
 
-#define MS_PER_TMR2_INT     (1000 * 10)
-#define TMR2_FIRE_FREQ      (1000 / MS_PER_TMR2_INT)
-#define MS_PER_TMR2_CLK     1
-#define TMR2_CLK_FREQ       (1000 / MS_PER_TMR2_CLK)
-
-#define MS_PER_TMR3_CLK     1
-#define TMR3_CLK_FREQ       (1000 / MS_PER_TMR3_CLK)
+#define US_PER_TMR2_INT         (US_PER_SEC * 10)
+#define TMR2_CLK_PER_SEC        (__LXT)
+#define TMR2_CLK_PER_TMR2_INT   ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
+#define TMR3_CLK_PER_SEC        (__LXT)
 
 static void tmr2_vec(void);
 static void tmr3_vec(void);
@@ -41,8 +38,8 @@ static void lp_ticker_arm_cd(void);
 
 static int lp_ticker_inited = 0;
 static volatile uint32_t counter_major = 0;
-static volatile int cd_major_minor_ms = 0;
-static volatile int cd_minor_ms = 0;
+static volatile int cd_major_minor_clks = 0;
+static volatile int cd_minor_clks = 0;
 static volatile uint32_t wakeup_tick = (uint32_t) -1;
 
 // NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
@@ -61,8 +58,8 @@ void lp_ticker_init(void)
     lp_ticker_inited = 1;
     
     counter_major = 0;
-    cd_major_minor_ms = 0;
-    cd_minor_ms = 0;
+    cd_major_minor_clks = 0;
+    cd_minor_clks = 0;
     wakeup_tick = (uint32_t) -1;
 
     // Reset module
@@ -78,9 +75,10 @@ void lp_ticker_init(void)
 
     // Configure clock
     uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
-    uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_FREQ - 1;
+    uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
-    uint32_t cmp_timer2 = MS_PER_TMR2_INT / MS_PER_TMR2_CLK;
+    MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
+    uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
     MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
     // Continuous mode
     // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
@@ -113,8 +111,8 @@ timestamp_t lp_ticker_read()
     TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
     
     do {
-        uint64_t major_minor_ms;
-        uint32_t minor_ms;
+        uint64_t major_minor_clks;
+        uint32_t minor_clks;
         
         // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
         // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
@@ -122,22 +120,22 @@ timestamp_t lp_ticker_read()
             core_util_critical_section_enter();
         
             // NOTE: Order of reading minor_us/carry here is significant.
-            minor_ms = TIMER_GetCounter(timer2_base) * MS_PER_TMR2_CLK;
+            minor_clks = TIMER_GetCounter(timer2_base);
             uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
             // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
-            if (carry && minor_ms > (MS_PER_TMR2_INT / 2)) {
-                major_minor_ms = (counter_major + 1) * MS_PER_TMR2_INT;
+            if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
+                major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
             }
             else {
-                major_minor_ms = (counter_major + carry) * MS_PER_TMR2_INT + minor_ms;
+                major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
             }
             
             core_util_critical_section_exit();
         }
-        while (minor_ms == 0 || minor_ms == MS_PER_TMR2_INT);
+        while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
 
         // Add power-down compensation
-        return (major_minor_ms * 1000 / US_PER_TICK);
+        return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
     }
     while (0);
 }
@@ -151,8 +149,8 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
     
     int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
     // NOTE: If this event was in the past, arm an interrupt to be triggered immediately.
-    cd_major_minor_ms = delta * US_PER_TICK / 1000;
-
+    cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
+    
     lp_ticker_arm_cd();
 }
 
@@ -177,8 +175,12 @@ static void tmr3_vec(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
     TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-    cd_major_minor_ms -= cd_minor_ms;
-    if (cd_major_minor_ms > 0) {
+    cd_major_minor_clks -= cd_minor_clks;
+    if (cd_major_minor_clks <= 0) {
+        // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
+        lp_ticker_irq_handler();
+    }
+    else {
         lp_ticker_arm_cd();
     }
 }
@@ -191,15 +193,16 @@ static void lp_ticker_arm_cd(void)
     timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk;
     // One-shot mode, Clock = 1 KHz 
     uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-    uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_FREQ - 1;
+    uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
+    MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
     // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
     timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
     timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/;
     
-    cd_minor_ms = cd_major_minor_ms;
-    cd_minor_ms = NU_CLAMP(cd_minor_ms, TMR_CMP_MIN * MS_PER_TMR3_CLK, TMR_CMP_MAX * MS_PER_TMR3_CLK);
-    timer3_base->CMP = cd_minor_ms / MS_PER_TMR3_CLK;
+    cd_minor_clks = cd_major_minor_clks;
+    cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
+    timer3_base->CMP = cd_minor_clks;
     
     TIMER_EnableInt(timer3_base);
     TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c
index 8e5611afc8c..4e969428d56 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c
@@ -24,16 +24,13 @@
 #include "critical.h"
 
 // lp_ticker tick = us = timestamp
-// clock of timer peripheral = ms
-#define US_PER_TICK         (1)
+#define US_PER_TICK             (1)
+#define US_PER_SEC              (1000 * 1000)
 
-#define MS_PER_TMR2_INT     (1000 * 10)
-#define TMR2_FIRE_FREQ      (1000 / MS_PER_TMR2_INT)
-#define MS_PER_TMR2_CLK     1
-#define TMR2_CLK_FREQ       (1000 / MS_PER_TMR2_CLK)
-
-#define MS_PER_TMR3_CLK     1
-#define TMR3_CLK_FREQ       (1000 / MS_PER_TMR3_CLK)
+#define US_PER_TMR2_INT         (US_PER_SEC * 10)
+#define TMR2_CLK_PER_SEC        (__LXT)
+#define TMR2_CLK_PER_TMR2_INT   ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
+#define TMR3_CLK_PER_SEC        (__LXT)
 
 static void tmr2_vec(void);
 static void tmr3_vec(void);
@@ -41,8 +38,8 @@ static void lp_ticker_arm_cd(void);
 
 static int lp_ticker_inited = 0;
 static volatile uint32_t counter_major = 0;
-static volatile int cd_major_minor_ms = 0;
-static volatile int cd_minor_ms = 0;
+static volatile int cd_major_minor_clks = 0;
+static volatile int cd_minor_clks = 0;
 static volatile uint32_t wakeup_tick = (uint32_t) -1;
 
 // NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
@@ -61,8 +58,8 @@ void lp_ticker_init(void)
     lp_ticker_inited = 1;
     
     counter_major = 0;
-    cd_major_minor_ms = 0;
-    cd_minor_ms = 0;
+    cd_major_minor_clks = 0;
+    cd_minor_clks = 0;
     wakeup_tick = (uint32_t) -1;
 
     // Reset module
@@ -78,9 +75,10 @@ void lp_ticker_init(void)
 
     // Configure clock
     uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
-    uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_FREQ - 1;
+    uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
-    uint32_t cmp_timer2 = MS_PER_TMR2_INT / MS_PER_TMR2_CLK;
+    MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
+    uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
     MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
     // Continuous mode
     ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2 | TIMER_CTL_CNTDATEN_Msk;
@@ -112,8 +110,8 @@ timestamp_t lp_ticker_read()
     TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
     
     do {
-        uint64_t major_minor_ms;
-        uint32_t minor_ms;
+        uint64_t major_minor_clks;
+        uint32_t minor_clks;
         
         // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
         // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
@@ -121,22 +119,22 @@ timestamp_t lp_ticker_read()
             core_util_critical_section_enter();
         
             // NOTE: Order of reading minor_us/carry here is significant.
-            minor_ms = TIMER_GetCounter(timer2_base) * MS_PER_TMR2_CLK;
+            minor_clks = TIMER_GetCounter(timer2_base);
             uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
             // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
-            if (carry && minor_ms > (MS_PER_TMR2_INT / 2)) {
-                major_minor_ms = (counter_major + 1) * MS_PER_TMR2_INT;
+            if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
+                major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
             }
             else {
-                major_minor_ms = (counter_major + carry) * MS_PER_TMR2_INT + minor_ms;
+                major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
             }
             
             core_util_critical_section_exit();
         }
-        while (minor_ms == 0 || minor_ms == MS_PER_TMR2_INT);
+        while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
 
         // Add power-down compensation
-        return (major_minor_ms * 1000 / US_PER_TICK);
+        return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
     }
     while (0);
 }
@@ -150,7 +148,7 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
     
     int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
     // NOTE: If this event was in the past, arm an interrupt to be triggered immediately.
-    cd_major_minor_ms = delta * US_PER_TICK / 1000;
+    cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
     
     lp_ticker_arm_cd();
 }
@@ -176,8 +174,12 @@ static void tmr3_vec(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
     TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-    cd_major_minor_ms -= cd_minor_ms;
-    if (cd_major_minor_ms > 0) {
+    cd_major_minor_clks -= cd_minor_clks;
+    if (cd_major_minor_clks <= 0) {
+        // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
+        lp_ticker_irq_handler();
+    }
+    else {
         lp_ticker_arm_cd();
     }
 }
@@ -190,14 +192,15 @@ static void lp_ticker_arm_cd(void)
     timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk;
     // One-shot mode, Clock = 1 KHz 
     uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-    uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_FREQ - 1;
+    uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
+    MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
     timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk | TIMER_CTL_CNTDATEN_Msk);
     timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3 | TIMER_CTL_CNTDATEN_Msk;
     
-    cd_minor_ms = cd_major_minor_ms;
-    cd_minor_ms = NU_CLAMP(cd_minor_ms, TMR_CMP_MIN * MS_PER_TMR3_CLK, TMR_CMP_MAX * MS_PER_TMR3_CLK);
-    timer3_base->CMP = cd_minor_ms / MS_PER_TMR3_CLK;
+    cd_minor_clks = cd_major_minor_clks;
+    cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
+    timer3_base->CMP = cd_minor_clks;
     
     TIMER_EnableInt(timer3_base);
     TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));

From 5ff2d6705fdb78a96a650eb0c305106d09473aa1 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Thu, 8 Sep 2016 13:45:41 +0800
Subject: [PATCH 37/89] Fix us_ticker/lp_ticker alarm error

Error occurs as newly scheduled alarm is behind now due to signed/unsigned comparison pitfall:
-1 < 1u ==> 0 or 1
---
 .../TARGET_NUVOTON/TARGET_M451/lp_ticker.c    | 24 +++++++++++------
 .../TARGET_NUVOTON/TARGET_M451/us_ticker.c    | 27 ++++++++++++-------
 .../TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c  | 24 +++++++++++------
 .../TARGET_NUVOTON/TARGET_NUC472/us_ticker.c  | 25 +++++++++++------
 4 files changed, 67 insertions(+), 33 deletions(-)

diff --git a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
index b926e8c3c94..84a4c9b36bd 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
@@ -38,8 +38,8 @@ static void lp_ticker_arm_cd(void);
 
 static int lp_ticker_inited = 0;
 static volatile uint32_t counter_major = 0;
-static volatile int cd_major_minor_clks = 0;
-static volatile int cd_minor_clks = 0;
+static volatile uint32_t cd_major_minor_clks = 0;
+static volatile uint32_t cd_minor_clks = 0;
 static volatile uint32_t wakeup_tick = (uint32_t) -1;
 
 // NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
@@ -148,10 +148,18 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
     TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
     
     int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
-    // NOTE: If this event was in the past, arm an interrupt to be triggered immediately.
-    cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
-    
-    lp_ticker_arm_cd();
+    if (delta > 0) {
+        cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
+        lp_ticker_arm_cd();
+    }
+    else {
+        cd_major_minor_clks = cd_minor_clks = 0;
+        /**
+         * This event was in the past. Set the interrupt as pending, but don't process it here.
+         * This prevents a recurive loop under heavy load which can lead to a stack overflow.
+         */  
+        NVIC_SetPendingIRQ(timer3_modinit.irq_n);
+    }
 }
 
 void lp_ticker_disable_interrupt(void)
@@ -175,8 +183,8 @@ static void tmr3_vec(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
     TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-    cd_major_minor_clks -= cd_minor_clks;
-    if (cd_major_minor_clks <= 0) {
+    cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
+    if (cd_major_minor_clks == 0) {
         // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
         lp_ticker_irq_handler();
     }
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c
index ab78dcca000..63f09670ea8 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c
@@ -45,8 +45,8 @@ static void us_ticker_arm_cd(void);
 static int us_ticker_inited = 0;
 static volatile uint32_t counter_major = 0;
 static volatile uint32_t pd_comp_us = 0;    // Power-down compenstaion for normal counter
-static volatile int cd_major_minor_us = 0;
-static volatile int cd_minor_us = 0;
+static volatile uint32_t cd_major_minor_us = 0;
+static volatile uint32_t cd_minor_us = 0;
 static volatile int cd_hires_tmr_armed = 0; // Flag of armed or not of hi-res timer for CD counter
 
 // NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details.
@@ -116,7 +116,7 @@ uint32_t us_ticker_read()
         
     do {
         uint32_t major_minor_us;
-        uint32_t minor_us; 
+        uint32_t minor_us;
 
         // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
         // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
@@ -157,12 +157,21 @@ void us_ticker_clear_interrupt(void)
 void us_ticker_set_interrupt(timestamp_t timestamp)
 {
     TIMER_Stop((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
+    cd_hires_tmr_armed = 0;
     
     int delta = (int) (timestamp - us_ticker_read());
-    // NOTE: If this event was in the past, arm an interrupt to be triggered immediately.
-    cd_major_minor_us = delta * US_PER_TICK;
-    
-    us_ticker_arm_cd();
+    if (delta > 0) {
+        cd_major_minor_us = delta * US_PER_TICK;
+        us_ticker_arm_cd();
+    }
+    else {
+        cd_major_minor_us = cd_minor_us = 0;
+        /**
+         * This event was in the past. Set the interrupt as pending, but don't process it here.
+         * This prevents a recurive loop under heavy load which can lead to a stack overflow.
+         */  
+        NVIC_SetPendingIRQ(timer1lores_modinit.irq_n);
+    }
 }
 
 void us_ticker_prepare_sleep(struct sleep_s *obj)
@@ -206,9 +215,9 @@ static void tmr0_vec(void)
 static void tmr1_vec(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
-    cd_major_minor_us -= cd_minor_us;
+    cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0;
     cd_hires_tmr_armed = 0;
-    if (cd_major_minor_us <= 0) {
+    if (cd_major_minor_us == 0) {
         // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
         us_ticker_irq_handler();
     }
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c
index 4e969428d56..2d05f33c502 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c
@@ -38,8 +38,8 @@ static void lp_ticker_arm_cd(void);
 
 static int lp_ticker_inited = 0;
 static volatile uint32_t counter_major = 0;
-static volatile int cd_major_minor_clks = 0;
-static volatile int cd_minor_clks = 0;
+static volatile uint32_t cd_major_minor_clks = 0;
+static volatile uint32_t cd_minor_clks = 0;
 static volatile uint32_t wakeup_tick = (uint32_t) -1;
 
 // NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
@@ -147,10 +147,18 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
     TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
     
     int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
-    // NOTE: If this event was in the past, arm an interrupt to be triggered immediately.
-    cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
-    
-    lp_ticker_arm_cd();
+    if (delta > 0) {
+        cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
+        lp_ticker_arm_cd();
+    }
+    else {
+        cd_major_minor_clks = cd_minor_clks = 0;
+        /**
+         * This event was in the past. Set the interrupt as pending, but don't process it here.
+         * This prevents a recurive loop under heavy load which can lead to a stack overflow.
+         */  
+        NVIC_SetPendingIRQ(timer3_modinit.irq_n);
+    }
 }
 
 void lp_ticker_disable_interrupt(void)
@@ -174,8 +182,8 @@ static void tmr3_vec(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
     TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-    cd_major_minor_clks -= cd_minor_clks;
-    if (cd_major_minor_clks <= 0) {
+    cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
+    if (cd_major_minor_clks == 0) {
         // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
         lp_ticker_irq_handler();
     }
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c
index f40474bbcd5..567c3ce7526 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c
@@ -45,8 +45,8 @@ static void us_ticker_arm_cd(void);
 static int us_ticker_inited = 0;
 static volatile uint32_t counter_major = 0;
 static volatile uint32_t pd_comp_us = 0;    // Power-down compenstaion for normal counter
-static volatile int cd_major_minor_us = 0;
-static volatile int cd_minor_us = 0;
+static volatile uint32_t cd_major_minor_us = 0;
+static volatile uint32_t cd_minor_us = 0;
 static volatile int cd_hires_tmr_armed = 0; // Flag of armed or not of hi-res timer for CD counter
 
 // NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details.
@@ -156,12 +156,21 @@ void us_ticker_clear_interrupt(void)
 void us_ticker_set_interrupt(timestamp_t timestamp)
 {
     TIMER_Stop((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
+    cd_hires_tmr_armed = 0;
     
     int delta = (int) (timestamp - us_ticker_read());
-    // NOTE: If this event was in the past, arm an interrupt to be triggered immediately.
-    cd_major_minor_us = delta * US_PER_TICK;
-    
-    us_ticker_arm_cd();
+    if (delta > 0) {
+        cd_major_minor_us = delta * US_PER_TICK;
+        us_ticker_arm_cd();
+    }
+    else {
+        cd_major_minor_us = cd_minor_us = 0;
+        /**
+         * This event was in the past. Set the interrupt as pending, but don't process it here.
+         * This prevents a recurive loop under heavy load which can lead to a stack overflow.
+         */  
+        NVIC_SetPendingIRQ(timer1lores_modinit.irq_n);
+    }
 }
 
 void us_ticker_prepare_sleep(struct sleep_s *obj)
@@ -205,9 +214,9 @@ static void tmr0_vec(void)
 static void tmr1_vec(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
-    cd_major_minor_us -= cd_minor_us;
+    cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0;
     cd_hires_tmr_armed = 0;
-    if (cd_major_minor_us <= 0) {
+    if (cd_major_minor_us == 0) {
         // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
         us_ticker_irq_handler();
     }

From b35adc65695bb790ed3efc8a43e9ea84836aed7d Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Thu, 8 Sep 2016 14:53:31 +0800
Subject: [PATCH 38/89] Remove fix of lp_ticker wrap-around

The original fix cannot handle both wrap-around and scheduled alarm behind now well.
Leave wrap-around as known issue.
---
 targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c   | 9 ++++++++-
 targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c | 9 ++++++++-
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
index 84a4c9b36bd..74cd964403c 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c
@@ -147,7 +147,14 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
     
     TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
     
-    int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
+    /**
+     * FIXME: Scheduled alarm may go off incorrectly due to wrap around.
+     * Conditions in which delta is negative:
+     * 1. Wrap around
+     * 2. Newly scheduled alarm is behind now
+     */ 
+    //int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
+    int delta = (int) (timestamp - now);
     if (delta > 0) {
         cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
         lp_ticker_arm_cd();
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c
index 2d05f33c502..5ed5a719c04 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c
@@ -146,7 +146,14 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
     
     TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
     
-    int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
+    /**
+     * FIXME: Scheduled alarm may go off incorrectly due to wrap around.
+     * Conditions in which delta is negative:
+     * 1. Wrap around
+     * 2. Newly scheduled alarm is behind now
+     */ 
+    //int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
+    int delta = (int) (timestamp - now);
     if (delta > 0) {
         cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
         lp_ticker_arm_cd();

From e478d243f2f44ab09e0b49ffb631ede60ef192c8 Mon Sep 17 00:00:00 2001
From: cyliangtw <cyliang@nuvoton.com>
Date: Thu, 8 Sep 2016 16:15:22 +0800
Subject: [PATCH 39/89] move aes ZI data into external SRAM for mbed client
 example

---
 .../TARGET_NUC472/device/TOOLCHAIN_ARM_STD/NUC472.sct           | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/NUC472.sct b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/NUC472.sct
index dec93e2c831..685017098df 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/NUC472.sct
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/NUC472.sct
@@ -23,6 +23,8 @@ LR_IROM1 0x00000000 {
   ; Too large to place into internal SRAM. So place into external SRAM instead.
   ER_XRAM1 0x60000000 {
     *lwip_* (+ZI)
+    aes.o (+ZI)
+    mesh_system.o (+ZI)
   }
   
   ; Extern SRAM for HEAP

From 54db3f4dec343baa6431e617c28c612e6989f3ae Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Fri, 9 Sep 2016 10:48:36 +0800
Subject: [PATCH 40/89] Refine us_ticker.c code

---
 .../TARGET_NUVOTON/TARGET_M451/us_ticker.c    | 57 ++++++++++---------
 .../TARGET_NUVOTON/TARGET_NUC472/us_ticker.c  | 57 ++++++++++---------
 2 files changed, 62 insertions(+), 52 deletions(-)

diff --git a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c
index 63f09670ea8..aecb2373c71 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c
@@ -21,22 +21,24 @@
 #include "nu_miscutil.h"
 #include "critical.h"
 
+// us_ticker tick = us = timestamp
 #define US_PER_TICK             1
+#define US_PER_SEC              (1000 * 1000)
 
-// NOTE: mbed-drivers-test-timeout test requires 100 us timer granularity.
-// NOTE: us_ticker will alarm the system for its counting, so make the counting period as long as possible for better power saving.
-#define US_PER_TMR0HIRES_INT    (1000 * 1000 * 10)
-#define TMR0HIRES_FIRE_FREQ     (1000 * 1000 / US_PER_TMR0HIRES_INT)
-#define US_PER_TMR0HIRES_CLK    1
-#define TMR0HIRES_CLK_FREQ      (1000 * 1000 / US_PER_TMR0HIRES_CLK)
+#define TMR0HIRES_CLK_PER_SEC           (1000 * 1000)
+#define TMR1HIRES_CLK_PER_SEC           (1000 * 1000)
+#define TMR1LORES_CLK_PER_SEC           (__LIRC)
+
+#define US_PER_TMR0HIRES_CLK            (US_PER_SEC / TMR0HIRES_CLK_PER_SEC)
+#define US_PER_TMR1HIRES_CLK            (US_PER_SEC / TMR1HIRES_CLK_PER_SEC)
+#define US_PER_TMR1LORES_CLK            (US_PER_SEC / TMR1LORES_CLK_PER_SEC)
+
+#define US_PER_TMR0HIRES_INT            (1000 * 1000 * 10)
+#define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC))
 
-#define US_PER_TMR1LORES_CLK    100
-#define TMR1LORES_CLK_FREQ      (1000 * 1000 / US_PER_TMR1LORES_CLK)
-#define US_PER_TMR1HIRES_CLK    1
-#define TMR1HIRES_CLK_FREQ      (1000 * 1000 / US_PER_TMR1HIRES_CLK)
 
 // Determine to use lo-res/hi-res timer according to CD period
-#define CD_TMR_SEP_US       1000
+#define US_TMR_SEP_CD       1000
 
 static void tmr0_vec(void);
 static void tmr1_vec(void);
@@ -88,9 +90,10 @@ void us_ticker_init(void)
 
     // Timer for normal counter
     uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
-    uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_FREQ - 1;
+    uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
-    uint32_t cmp_timer0 = US_PER_TMR0HIRES_INT / US_PER_TMR0HIRES_CLK;
+    MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0);
+    uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT;
     MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
     // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
     ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0/* | TIMER_CTL_CNTDATEN_Msk*/;
@@ -229,22 +232,22 @@ static void tmr1_vec(void)
 static void us_ticker_arm_cd(void)
 {
     TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1lores_modinit.modname);
-    uint32_t tmr1_clk_freq;
+    uint32_t tmr1_clk_per_sec;
     uint32_t us_per_tmr1_clk;
     
     /**
-     * Reserve CD_TMR_SEP_US-plus alarm period for hi-res timer
-     * 1. period >= CD_TMR_SEP_US * 2. Divide into two rounds:
-     *    CD_TMR_SEP_US * n (lo-res timer)
-     *    CD_TMR_SEP_US + period % CD_TMR_SEP_US (hi-res timer)
-     * 2. period < CD_TMR_SEP_US * 2. Just one round:
+     * Reserve US_TMR_SEP_CD-plus alarm period for hi-res timer
+     * 1. period >= US_TMR_SEP_CD * 2. Divide into two rounds:
+     *    US_TMR_SEP_CD * n (lo-res timer)
+     *    US_TMR_SEP_CD + period % US_TMR_SEP_CD (hi-res timer)
+     * 2. period < US_TMR_SEP_CD * 2. Just one round:
      *    period (hi-res timer)
      */
-    if (cd_major_minor_us >= CD_TMR_SEP_US * 2) {
-        cd_minor_us = cd_major_minor_us - cd_major_minor_us % CD_TMR_SEP_US - CD_TMR_SEP_US;
+    if (cd_major_minor_us >= US_TMR_SEP_CD * 2) {
+        cd_minor_us = cd_major_minor_us - cd_major_minor_us % US_TMR_SEP_CD - US_TMR_SEP_CD;
         
         CLK_SetModuleClock(timer1lores_modinit.clkidx, timer1lores_modinit.clksrc, timer1lores_modinit.clkdiv);
-        tmr1_clk_freq = TMR1LORES_CLK_FREQ;
+        tmr1_clk_per_sec = TMR1LORES_CLK_PER_SEC;
         us_per_tmr1_clk = US_PER_TMR1LORES_CLK;
         
         cd_hires_tmr_armed = 0;
@@ -253,7 +256,7 @@ static void us_ticker_arm_cd(void)
         cd_minor_us = cd_major_minor_us;
         
         CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
-        tmr1_clk_freq = TMR1HIRES_CLK_FREQ;
+        tmr1_clk_per_sec = TMR1HIRES_CLK_PER_SEC;
         us_per_tmr1_clk = US_PER_TMR1HIRES_CLK;
         
         cd_hires_tmr_armed = 1;
@@ -263,14 +266,16 @@ static void us_ticker_arm_cd(void)
     timer1_base->CTL |= TIMER_CTL_RSTCNT_Msk;
     // One-shot mode, Clock = 1 MHz 
     uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
-    uint32_t prescale_timer1 = clk_timer1 / tmr1_clk_freq - 1;
+    uint32_t prescale_timer1 = clk_timer1 / tmr1_clk_per_sec - 1;
     MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
+    MBED_ASSERT((clk_timer1 % tmr1_clk_per_sec) == 0);
     // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
     timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
     timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1/* | TIMER_CTL_CNTDATEN_Msk*/;
     
-    cd_minor_us = NU_CLAMP(cd_minor_us, TMR_CMP_MIN * us_per_tmr1_clk, TMR_CMP_MAX * us_per_tmr1_clk);
-    timer1_base->CMP = cd_minor_us / us_per_tmr1_clk;
+    uint32_t cmp_timer1 = cd_minor_us / us_per_tmr1_clk;
+    cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX);
+    timer1_base->CMP = cmp_timer1;
     
     TIMER_EnableInt(timer1_base);
     TIMER_Start(timer1_base);
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c
index 567c3ce7526..de647ecf4a3 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c
@@ -21,22 +21,24 @@
 #include "nu_miscutil.h"
 #include "critical.h"
 
+// us_ticker tick = us = timestamp
 #define US_PER_TICK             1
+#define US_PER_SEC              (1000 * 1000)
 
-// NOTE: mbed-drivers-test-timeout test requires 100 us timer granularity.
-// NOTE: us_ticker will alarm the system for its counting, so make the counting period as long as possible for better power saving.
-#define US_PER_TMR0HIRES_INT    (1000 * 1000 * 10)
-#define TMR0HIRES_FIRE_FREQ     (1000 * 1000 / US_PER_TMR0HIRES_INT)
-#define US_PER_TMR0HIRES_CLK    1
-#define TMR0HIRES_CLK_FREQ      (1000 * 1000 / US_PER_TMR0HIRES_CLK)
+#define TMR0HIRES_CLK_PER_SEC           (1000 * 1000)
+#define TMR1HIRES_CLK_PER_SEC           (1000 * 1000)
+#define TMR1LORES_CLK_PER_SEC           (__LIRC)
+
+#define US_PER_TMR0HIRES_CLK            (US_PER_SEC / TMR0HIRES_CLK_PER_SEC)
+#define US_PER_TMR1HIRES_CLK            (US_PER_SEC / TMR1HIRES_CLK_PER_SEC)
+#define US_PER_TMR1LORES_CLK            (US_PER_SEC / TMR1LORES_CLK_PER_SEC)
+
+#define US_PER_TMR0HIRES_INT            (1000 * 1000 * 10)
+#define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC))
 
-#define US_PER_TMR1LORES_CLK    100
-#define TMR1LORES_CLK_FREQ      (1000 * 1000 / US_PER_TMR1LORES_CLK)
-#define US_PER_TMR1HIRES_CLK    1
-#define TMR1HIRES_CLK_FREQ      (1000 * 1000 / US_PER_TMR1HIRES_CLK)
 
 // Determine to use lo-res/hi-res timer according to CD period
-#define CD_TMR_SEP_US       1000
+#define US_TMR_SEP_CD       1000
 
 static void tmr0_vec(void);
 static void tmr1_vec(void);
@@ -88,9 +90,10 @@ void us_ticker_init(void)
 
     // Timer for normal counter
     uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
-    uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_FREQ - 1;
+    uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
-    uint32_t cmp_timer0 = US_PER_TMR0HIRES_INT / US_PER_TMR0HIRES_CLK;
+    MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0);
+    uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT;
     MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
     ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0 | TIMER_CTL_CNTDATEN_Msk;
     ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0;
@@ -228,22 +231,22 @@ static void tmr1_vec(void)
 static void us_ticker_arm_cd(void)
 {
     TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1lores_modinit.modname);
-    uint32_t tmr1_clk_freq;
+    uint32_t tmr1_clk_per_sec;
     uint32_t us_per_tmr1_clk;
     
     /**
-     * Reserve CD_TMR_SEP_US-plus alarm period for hi-res timer
-     * 1. period >= CD_TMR_SEP_US * 2. Divide into two rounds:
-     *    CD_TMR_SEP_US * n (lo-res timer)
-     *    CD_TMR_SEP_US + period % CD_TMR_SEP_US (hi-res timer)
-     * 2. period < CD_TMR_SEP_US * 2. Just one round:
+     * Reserve US_TMR_SEP_CD-plus alarm period for hi-res timer
+     * 1. period >= US_TMR_SEP_CD * 2. Divide into two rounds:
+     *    US_TMR_SEP_CD * n (lo-res timer)
+     *    US_TMR_SEP_CD + period % US_TMR_SEP_CD (hi-res timer)
+     * 2. period < US_TMR_SEP_CD * 2. Just one round:
      *    period (hi-res timer)
      */
-    if (cd_major_minor_us >= CD_TMR_SEP_US * 2) {
-        cd_minor_us = cd_major_minor_us - cd_major_minor_us % CD_TMR_SEP_US - CD_TMR_SEP_US;
+    if (cd_major_minor_us >= US_TMR_SEP_CD * 2) {
+        cd_minor_us = cd_major_minor_us - cd_major_minor_us % US_TMR_SEP_CD - US_TMR_SEP_CD;
         
         CLK_SetModuleClock(timer1lores_modinit.clkidx, timer1lores_modinit.clksrc, timer1lores_modinit.clkdiv);
-        tmr1_clk_freq = TMR1LORES_CLK_FREQ;
+        tmr1_clk_per_sec = TMR1LORES_CLK_PER_SEC;
         us_per_tmr1_clk = US_PER_TMR1LORES_CLK;
         
         cd_hires_tmr_armed = 0;
@@ -252,7 +255,7 @@ static void us_ticker_arm_cd(void)
         cd_minor_us = cd_major_minor_us;
         
         CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
-        tmr1_clk_freq = TMR1HIRES_CLK_FREQ;
+        tmr1_clk_per_sec = TMR1HIRES_CLK_PER_SEC;
         us_per_tmr1_clk = US_PER_TMR1HIRES_CLK;
         
         cd_hires_tmr_armed = 1;
@@ -262,13 +265,15 @@ static void us_ticker_arm_cd(void)
     timer1_base->CTL |= TIMER_CTL_RSTCNT_Msk;
     // One-shot mode, Clock = 1 MHz 
     uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
-    uint32_t prescale_timer1 = clk_timer1 / tmr1_clk_freq - 1;
+    uint32_t prescale_timer1 = clk_timer1 / tmr1_clk_per_sec - 1;
     MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
+    MBED_ASSERT((clk_timer1 % tmr1_clk_per_sec) == 0);
     timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk | TIMER_CTL_CNTDATEN_Msk);
     timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1 | TIMER_CTL_CNTDATEN_Msk;
     
-    cd_minor_us = NU_CLAMP(cd_minor_us, TMR_CMP_MIN * us_per_tmr1_clk, TMR_CMP_MAX * us_per_tmr1_clk);
-    timer1_base->CMP = cd_minor_us / us_per_tmr1_clk;
+    uint32_t cmp_timer1 = cd_minor_us / us_per_tmr1_clk;
+    cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX);
+    timer1_base->CMP = cmp_timer1;
     
     TIMER_EnableInt(timer1_base);
     TIMER_Start(timer1_base);

From e54aad91830bdfebbc650bdb0e365173d0bd2e24 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Mon, 19 Sep 2016 13:29:52 +0800
Subject: [PATCH 41/89] Disable GPIO IRQ debounce by default

Some application requires GPIO IRQ to be low latency. To complement it, open up GPIO IRQ debounce configuration through mbed_lib.json.
---
 .../TARGET_NUVOTON/TARGET_M451/mbed_lib.json  | 18 +++++++++++
 .../TARGET_NUC472/mbed_lib.json               | 18 +++++++++++
 .../TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c | 29 ++++++++++++++---
 .../TARGET_NUC472/gpio_irq_api.c              | 31 ++++++++++++++++---
 4 files changed, 87 insertions(+), 9 deletions(-)
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_M451/mbed_lib.json
 create mode 100644 hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/mbed_lib.json

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_M451/mbed_lib.json b/hal/targets/hal/TARGET_NUVOTON/TARGET_M451/mbed_lib.json
new file mode 100644
index 00000000000..3832d8f9ec2
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_M451/mbed_lib.json
@@ -0,0 +1,18 @@
+{
+    "name": "M451",
+    "config": {
+        "gpio-irq-debounce-enable": {
+            "help": "Enable GPIO IRQ debounce",
+            "value": 0
+        },
+        "gpio-irq-debounce-clock-source": {
+            "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
+            "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
+        },
+
+        "gpio-irq-debounce-sample-rate": {
+            "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+            "value": "GPIO_DBCTL_DBCLKSEL_16"
+        }
+    }
+}
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/mbed_lib.json b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/mbed_lib.json
new file mode 100644
index 00000000000..533c883f100
--- /dev/null
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/mbed_lib.json
@@ -0,0 +1,18 @@
+{
+    "name": "NUC472",
+    "config": {
+        "gpio-irq-debounce-enable": {
+            "help": "Enable GPIO IRQ debounce",
+            "value": 0
+        },
+        "gpio-irq-debounce-clock-source": {
+            "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_IRC10K",
+            "value": "GPIO_DBCTL_DBCLKSRC_IRC10K"
+        },
+
+        "gpio-irq-debounce-sample-rate": {
+            "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+            "value": "GPIO_DBCTL_DBCLKSEL_16"
+        }
+    }
+}
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c
index c2adef9954b..f08a6b01914 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c
@@ -52,6 +52,24 @@ static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
 
 #define NU_MAX_PORT     (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
 
+#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
+#define M451_GPIO_IRQ_DEBOUNCE_ENABLE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
+#else
+#define M451_GPIO_IRQ_DEBOUNCE_ENABLE 0
+#endif
+
+#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
+#define M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
+#else
+#define M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
+#endif
+
+#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
+#define M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
+#else
+#define M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
+#endif
+
 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
 {
     if (pin == NC) {
@@ -68,14 +86,19 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
     obj->irq_handler = (uint32_t) handler;
     obj->irq_id = id;
 
+    GPIO_T *gpio_base = NU_PORT_BASE(port_index);
     //gpio_set(pin);
     
+#if M451_GPIO_IRQ_DEBOUNCE_ENABLE
     // Configure de-bounce clock source and sampling cycle time
-    GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_16);
+    GPIO_SET_DEBOUNCE_TIME(M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
+    GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
+#else
+    GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
+#endif
     
     struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
     
-    MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
     var->obj_arr[pin_index] = obj;
     
     // NOTE: InterruptIn requires IRQ enabled by default.
@@ -106,7 +129,6 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
     switch (event) {
         case IRQ_RISE:
             if (enable) {
-                GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
                 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
             }
             else {
@@ -116,7 +138,6 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
         
         case IRQ_FALL:
             if (enable) {
-                GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
                 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
             }
             else {
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c
index bf73913b5d8..62e036593c9 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c
@@ -58,6 +58,24 @@ static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
 
 #define NU_MAX_PORT     (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
 
+#ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
+#define NUC472_GPIO_IRQ_DEBOUNCE_ENABLE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
+#else
+#define NUC472_GPIO_IRQ_DEBOUNCE_ENABLE 0
+#endif
+
+#ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
+#define NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
+#else
+#define NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_IRC10K
+#endif
+
+#ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
+#define NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
+#else
+#define NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
+#endif
+
 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
 {
     if (pin == NC) {
@@ -74,14 +92,19 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
     obj->irq_handler = (uint32_t) handler;
     obj->irq_id = id;
 
+    GPIO_T *gpio_base = NU_PORT_BASE(port_index);
     //gpio_set(pin);
     
+#if NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
     // Configure de-bounce clock source and sampling cycle time
-    GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_IRC10K, GPIO_DBCTL_DBCLKSEL_16);
-    
+    GPIO_SET_DEBOUNCE_TIME(NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
+    GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
+#else
+    GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
+#endif
+
     struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
     
-    MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
     var->obj_arr[pin_index] = obj;
     
     // NOTE: InterruptIn requires IRQ enabled by default.
@@ -112,7 +135,6 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
     switch (event) {
         case IRQ_RISE:
             if (enable) {
-                GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
                 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
             }
             else {
@@ -122,7 +144,6 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
         
         case IRQ_FALL:
             if (enable) {
-                GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
                 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
             }
             else {

From c273b44d1796dd2d7eba3c32ccb438becfe4042e Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Mon, 19 Sep 2016 15:25:24 +0800
Subject: [PATCH 42/89] Refine comment for two-region model

---
 platform/retarget.cpp                                     | 5 ++++-
 .../TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/retarget.c     | 8 +++++---
 .../TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c  | 8 +++++---
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/platform/retarget.cpp b/platform/retarget.cpp
index 2bc1027139a..56dc02b2cae 100644
--- a/platform/retarget.cpp
+++ b/platform/retarget.cpp
@@ -574,7 +574,10 @@ register unsigned char * stack_ptr __asm ("sp");
 
 // Dynamic memory allocation related syscall.
 #if defined(TARGET_NUMAKER_PFM_NUC472) || defined(TARGET_NUMAKER_PFM_M453)
-// Overwrite _sbrk() to support two region model.
+// Overwrite _sbrk() to support two region model (heap and stack are two distinct regions).
+// __wrap__sbrk() is implemented in:
+// TARGET_NUMAKER_PFM_NUC472    hal/targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/TOOLCHAIN_GCC_ARM/retarget.c
+// TARGET_NUMAKER_PFM_M453      hal/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c
 extern "C" void *__wrap__sbrk(int incr);
 extern "C" caddr_t _sbrk(int incr) {
     return (caddr_t) __wrap__sbrk(incr);
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/retarget.c b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/retarget.c
index 67f3f8380dc..d5c3d874e82 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/retarget.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/retarget.c
@@ -15,9 +15,11 @@
 extern uint32_t __mbed_sbrk_start;
 extern uint32_t __mbed_krbs_start;
 
-// NOTE: The implementation of _sbrk (in common/retarget.cpp) for GCC_ARM requires one-region model for heap and stack, which doesn't
-//       meet the layout of e.g. Nu-mbed-NUC472 board where heap is located on external SRAM. 
-//       Because the symbol is not weak and cannot be overwritten, wrap calls to it by hooking command line linker with '-Wl,--wrap,_sbrk'.
+/**
+ * The default implementation of _sbrk() (in common/retarget.cpp) for GCC_ARM requires one-region model (heap and stack share one region), which doesn't
+ * fit two-region model (heap and stack are two distinct regions), for example, NUMAKER-PFM-NUC472 locates heap on external SRAM. Define __wrap__sbrk() to
+ * override the default _sbrk(). It is expected to get called through gcc hooking mechanism ('-Wl,--wrap,_sbrk') or in _sbrk().
+ */
 void *__wrap__sbrk(int incr)
 {
     static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start;
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c
index 6e2642a5f68..470af432b5c 100644
--- a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c
@@ -15,9 +15,11 @@
 extern uint32_t __mbed_sbrk_start;
 extern uint32_t __mbed_krbs_start;
 
-// NOTE: The implementation of _sbrk (in common/retarget.cpp) for GCC_ARM requires one-region model for heap and stack, which doesn't
-//       meet the layout of e.g. Nu-mbed-NUC472 board where heap is located on external SRAM. 
-//       Because the symbol is not weak and cannot be overwritten, wrap calls to it by hooking command line linker with '-Wl,--wrap,_sbrk'.
+/**
+ * The default implementation of _sbrk() (in common/retarget.cpp) for GCC_ARM requires one-region model (heap and stack share one region), which doesn't
+ * fit two-region model (heap and stack are two distinct regions), for example, NUMAKER-PFM-NUC472 locates heap on external SRAM. Define __wrap__sbrk() to
+ * override the default _sbrk(). It is expected to get called through gcc hooking mechanism ('-Wl,--wrap,_sbrk') or in _sbrk().
+ */
 void *__wrap__sbrk(int incr)
 {
     static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start;

From c9f031b6388a6f066a6b2ad4e5c13f5de75bce5a Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Mon, 19 Sep 2016 17:17:21 +0800
Subject: [PATCH 43/89] Fix warnings generated by armcc

---
 .../TARGET_NUC472/device/cmsis_nvic.h         |  4 ++--
 .../TARGET_NUC472/device/startup_NUC472_442.c | 12 ++++++++--
 .../TARGET_NUC472/device/system_NUC472_442.c  |  2 +-
 .../TARGET_NUVOTON/TARGET_NUC472/i2c_api.c    | 22 ++++++-------------
 .../TARGET_NUVOTON/TARGET_NUC472/spi_api.c    |  2 +-
 5 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis_nvic.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis_nvic.h
index 8cb8accc799..cc87b4a4acf 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis_nvic.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis_nvic.h
@@ -24,12 +24,12 @@
 #define NVIC_NUM_VECTORS     (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
 
 #if defined(__CC_ARM)
-#   define NVIC_RAM_VECTOR_ADDRESS  &Image$$ER_IRAMVEC$$ZI$$Base
+#   define NVIC_RAM_VECTOR_ADDRESS  ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base)
 #elif defined(__ICCARM__)
 #   pragma section = "IRAMVEC"
 #   define NVIC_RAM_VECTOR_ADDRESS  ((uint32_t) __section_begin("IRAMVEC"))
 #elif defined(__GNUC__)
-#   define NVIC_RAM_VECTOR_ADDRESS  &__start_vector_table__
+#   define NVIC_RAM_VECTOR_ADDRESS  ((uint32_t) &__start_vector_table__)
 #endif
 
 
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/startup_NUC472_442.c b/targets/TARGET_NUVOTON/TARGET_NUC472/device/startup_NUC472_442.c
index f339feafd94..4acab2847c0 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/startup_NUC472_442.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/startup_NUC472_442.c
@@ -11,6 +11,14 @@
 
 #include "NUC472_442.h"
 
+/* Suppress warning messages */
+#if defined(__CC_ARM)
+// Suppress warning message: extended constant initialiser used
+#pragma diag_suppress 1296
+#elif defined(__ICCARM__)
+#elif defined(__GNUC__)
+#endif
+
 /* Macro Definitions */
 #if defined(__CC_ARM)
 #define WEAK            __attribute__ ((weak))
@@ -238,12 +246,12 @@ const uint32_t __vector_handlers[] = {
 
     /* Configure Initial Stack Pointer, using linker-generated symbols */
 #if defined(__CC_ARM)
-    &Image$$ARM_LIB_STACK$$ZI$$Limit,
+    (uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
 #elif defined(__ICCARM__)
     //(uint32_t) __sfe("CSTACK"),
     (uint32_t) &CSTACK$$Limit,
 #elif defined(__GNUC__)
-    &__StackTop,
+    (uint32_t) &__StackTop,
 #endif
 
     (uint32_t) Reset_Handler,           // Reset Handler
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/system_NUC472_442.c b/targets/TARGET_NUVOTON/TARGET_NUC472/device/system_NUC472_442.c
index d8af018d39c..c1954ab405a 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/system_NUC472_442.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/system_NUC472_442.c
@@ -58,7 +58,7 @@ void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
  */
 void SystemInit (void)
 {
-    uint32_t u32RTC_EN_Flag = 0;
+    //uint32_t u32RTC_EN_Flag = 0;
 
     /* FPU settings ------------------------------------------------------------*/
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c
index 49c32f0a5b4..2bc453cc60d 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c
@@ -93,8 +93,8 @@ static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
 #define NU_I2C_TIMEOUT_STOP         500000
 static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout);
 static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout);
-static int i2c_is_stat_int(i2c_t *obj);
-static int i2c_is_stop_det(i2c_t *obj);
+//static int i2c_is_stat_int(i2c_t *obj);
+//static int i2c_is_stop_det(i2c_t *obj);
 static int i2c_is_trsn_done(i2c_t *obj);
 static int i2c_is_tran_started(i2c_t *obj);
 static int i2c_addr2data(int address, int read);
@@ -115,6 +115,8 @@ static void i2c_rollback_vector_interrupt(i2c_t *obj);
 #define TRANCTRL_STARTED        (1)
 #define TRANCTRL_NAKLASTDATA    (1 << 1)
 
+uint32_t us_ticker_read(void);
+
 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
 {
     uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
@@ -178,8 +180,6 @@ void i2c_frequency(i2c_t *obj, int hz)
 
 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
 {
-    int i;
-
     if (i2c_start(obj)) {
         i2c_stop(obj);
         return I2C_ERROR_BUS_BUSY;
@@ -203,8 +203,6 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
 
 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
 {
-    int i;
-    
     if (i2c_start(obj)) {
         i2c_stop(obj);
         return I2C_ERROR_BUS_BUSY;
@@ -306,7 +304,6 @@ static int i2c_addr2bspaddr(int address)
 
 static void i2c_enable_int(i2c_t *obj)
 {
-    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
     const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
     
     core_util_critical_section_enter();
@@ -320,7 +317,6 @@ static void i2c_enable_int(i2c_t *obj)
 
 static void i2c_disable_int(i2c_t *obj)
 {
-    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
     const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
     
     core_util_critical_section_enter();
@@ -334,7 +330,6 @@ static void i2c_disable_int(i2c_t *obj)
 
 static int i2c_set_int(i2c_t *obj, int inten)
 {
-    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
     int inten_back;
     
     core_util_critical_section_enter();
@@ -374,8 +369,6 @@ int i2c_allow_powerdown(void)
 
 static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
 {
-    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-    int err = 0;
     int tran_len = 0;
     
     i2c_disable_int(obj);
@@ -386,7 +379,6 @@ static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastd
     i2c_enable_int(obj);
     
     if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) {
-        err = I2C_ERROR_BUS_BUSY;
 #if NU_I2C_DEBUG
         MY_I2C_2 = obj->i2c;
         while (1);
@@ -502,7 +494,6 @@ static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uin
 static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
 {
     uint32_t t1, t2, elapsed = 0;
-    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
     int tran_started;
     char *tran_pos = NULL;
     char *tran_pos2 = NULL;
@@ -547,6 +538,7 @@ static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
     return (elapsed >= timeout);
 }
 
+#if 0
 static int i2c_is_stat_int(i2c_t *obj)
 {
     I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
@@ -554,12 +546,14 @@ static int i2c_is_stat_int(i2c_t *obj)
     return !! (i2c_base->CTL & I2C_CTL_SI_Msk);
 }
 
+
 static int i2c_is_stop_det(i2c_t *obj)
 {
     I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
 
     return ! (i2c_base->CTL & I2C_CTL_STO_Msk);
 }
+#endif
 
 static int i2c_is_trsn_done(i2c_t *obj)
 {
@@ -578,7 +572,6 @@ static int i2c_is_trsn_done(i2c_t *obj)
 
 static int i2c_is_tran_started(i2c_t *obj)
 {
-    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
     int started;
     int inten_back;
     
@@ -619,7 +612,6 @@ static void i2c_irq(i2c_t *obj)
 {
     I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
     uint32_t status;
-    int data_recv = 0;
     
     if (I2C_GET_TIMEOUT_FLAG(i2c_base)) {
         I2C_ClearTimeoutFlag(i2c_base);
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c
index ba87ebcf434..79a3296d2bb 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c
@@ -116,7 +116,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
     // Enable IP clock
     CLK_EnableModuleClock(modinit->clkidx);
 
-    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    //SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
     
     pinmap_pinout(mosi, PinMap_SPI_MOSI);
     pinmap_pinout(miso, PinMap_SPI_MISO);

From 2c675f94ab88f02ba10dc6bce5ac81eeafe3c8ab Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Mon, 19 Sep 2016 17:40:52 +0800
Subject: [PATCH 44/89] Fix warnings generated by armcc

---
 .../TARGET_NUMAKER_PFM_M453/PeripheralPins.c  |  2 +-
 targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c  | 22 ++++++-------------
 targets/TARGET_NUVOTON/TARGET_M451/spi_api.c  |  2 +-
 .../startup_M451Series.c                      | 12 ++++++++--
 .../TARGET_NUVOTON/TARGET_M451/cmsis_nvic.h   |  4 ++--
 5 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c
index 971bef3dbf2..7b58a28abe9 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c
@@ -256,7 +256,7 @@ const PinMap PinMap_UART_RX[] = {
     {PB_5, UART_2, SYS_GPB_MFPL_PB5MFP_UART2_RXD},
     {PC_1, UART_3, SYS_GPC_MFPL_PC1MFP_UART3_RXD},
     {PC_3, UART_2, SYS_GPC_MFPL_PC3MFP_UART2_RXD},
-    {PC_7, UART_0, SYS_GPC_MFPL_PC7MFP_UART0_RXD},
+    {PC_7, UART_0, (int) SYS_GPC_MFPL_PC7MFP_UART0_RXD},
     {PD_0, UART_0, SYS_GPD_MFPL_PD0MFP_UART0_RXD},
     {PD_6, UART_0, SYS_GPD_MFPL_PD6MFP_UART0_RXD},
     {PD_13, UART_3, SYS_GPD_MFPH_PD13MFP_UART3_RXD},
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c
index 92b5c7a9f0f..02808b49331 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c
@@ -75,8 +75,8 @@ static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
 #define NU_I2C_TIMEOUT_STOP         500000
 static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout);
 static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout);
-static int i2c_is_stat_int(i2c_t *obj);
-static int i2c_is_stop_det(i2c_t *obj);
+//static int i2c_is_stat_int(i2c_t *obj);
+//static int i2c_is_stop_det(i2c_t *obj);
 static int i2c_is_trsn_done(i2c_t *obj);
 static int i2c_is_tran_started(i2c_t *obj);
 static int i2c_addr2data(int address, int read);
@@ -98,6 +98,8 @@ static void i2c_rollback_vector_interrupt(i2c_t *obj);
 #define TRANCTRL_STARTED        (1)
 #define TRANCTRL_NAKLASTDATA    (1 << 1)
 
+uint32_t us_ticker_read(void);
+
 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
 {
     uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
@@ -161,8 +163,6 @@ void i2c_frequency(i2c_t *obj, int hz)
 
 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
 {
-    int i;
-
     if (i2c_start(obj)) {
         i2c_stop(obj);
         return I2C_ERROR_BUS_BUSY;
@@ -186,8 +186,6 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
 
 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
 {
-    int i;
-
     if (i2c_start(obj)) {
         i2c_stop(obj);
         return I2C_ERROR_BUS_BUSY;
@@ -289,7 +287,6 @@ static int i2c_addr2bspaddr(int address)
 
 static void i2c_enable_int(i2c_t *obj)
 {
-    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
     const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
     
     core_util_critical_section_enter();
@@ -303,7 +300,6 @@ static void i2c_enable_int(i2c_t *obj)
 
 static void i2c_disable_int(i2c_t *obj)
 {
-    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
     const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
     
     core_util_critical_section_enter();
@@ -317,7 +313,6 @@ static void i2c_disable_int(i2c_t *obj)
 
 static int i2c_set_int(i2c_t *obj, int inten)
 {
-    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
     int inten_back;
     
     core_util_critical_section_enter();
@@ -357,8 +352,6 @@ int i2c_allow_powerdown(void)
 
 static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
 {
-    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-    int err = 0;
     int tran_len = 0;
     
     i2c_disable_int(obj);
@@ -369,7 +362,6 @@ static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastd
     i2c_enable_int(obj);
     
     if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) {
-        err = I2C_ERROR_BUS_BUSY;
 #if NU_I2C_DEBUG
         MY_I2C_2 = obj->i2c;
         while (1);
@@ -485,7 +477,6 @@ static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uin
 static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
 {
     uint32_t t1, t2, elapsed = 0;
-    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
     int tran_started;
     char *tran_pos = NULL;
     char *tran_pos2 = NULL;
@@ -529,6 +520,8 @@ static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
     
     return (elapsed >= timeout);
 }
+
+#if 0
 static int i2c_is_stat_int(i2c_t *obj)
 {
     I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
@@ -542,6 +535,7 @@ static int i2c_is_stop_det(i2c_t *obj)
 
     return ! (i2c_base->CTL & I2C_CTL_STO_Msk);
 }
+#endif
 
 static int i2c_is_trsn_done(i2c_t *obj)
 {
@@ -560,7 +554,6 @@ static int i2c_is_trsn_done(i2c_t *obj)
 
 static int i2c_is_tran_started(i2c_t *obj)
 {
-    I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
     int started;
     int inten_back;
     
@@ -589,7 +582,6 @@ static void i2c_irq(i2c_t *obj)
 {
     I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
     uint32_t status;
-    int data_recv = 0;
     
     if (I2C_GET_TIMEOUT_FLAG(i2c_base)) {
         I2C_ClearTimeoutFlag(i2c_base);
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c
index fb2c28d39c8..63f8e6a5a27 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c
@@ -111,7 +111,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
     // Enable IP clock
     CLK_EnableModuleClock(modinit->clkidx);
 
-    SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
+    //SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
         
     pinmap_pinout(mosi, PinMap_SPI_MOSI);
     pinmap_pinout(miso, PinMap_SPI_MISO);
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/startup_M451Series.c b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/startup_M451Series.c
index d73e4eca81d..086c9af6976 100644
--- a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/startup_M451Series.c
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/startup_M451Series.c
@@ -11,6 +11,14 @@
 
 #include "M451Series.h"
 
+/* Suppress warning messages */
+#if defined(__CC_ARM)
+// Suppress warning message: extended constant initialiser used
+#pragma diag_suppress 1296
+#elif defined(__ICCARM__)
+#elif defined(__GNUC__)
+#endif
+
 /* Macro Definitions */
 #if defined(__CC_ARM)
 #define WEAK            __attribute__ ((weak))
@@ -158,12 +166,12 @@ const uint32_t __vector_handlers[] = {
 
     /* Configure Initial Stack Pointer, using linker-generated symbols */
 #if defined(__CC_ARM)
-    &Image$$ARM_LIB_STACK$$ZI$$Limit,
+    (uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
 #elif defined(__ICCARM__)
     //(uint32_t) __sfe("CSTACK"),
     (uint32_t) &CSTACK$$Limit,
 #elif defined(__GNUC__)
-    &__StackTop,
+    (uint32_t) &__StackTop,
 #endif
 
     (uint32_t) Reset_Handler,           // Reset Handler
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.h b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.h
index 128cfcf2138..77cc94d9864 100644
--- a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.h
+++ b/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.h
@@ -24,12 +24,12 @@
 #define NVIC_NUM_VECTORS     (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
 
 #if defined(__CC_ARM)
-#   define NVIC_RAM_VECTOR_ADDRESS  &Image$$ER_IRAMVEC$$ZI$$Base
+#   define NVIC_RAM_VECTOR_ADDRESS  ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base)
 #elif defined(__ICCARM__)
 #   pragma section = "IRAMVEC"
 #   define NVIC_RAM_VECTOR_ADDRESS  ((uint32_t) __section_begin("IRAMVEC"))
 #elif defined(__GNUC__)
-#   define NVIC_RAM_VECTOR_ADDRESS  &__start_vector_table__
+#   define NVIC_RAM_VECTOR_ADDRESS  ((uint32_t) &__start_vector_table__)
 #endif
 
 

From faae13e650b8296c3b15b318dd710aa004327641 Mon Sep 17 00:00:00 2001
From: cyliangtw <cyliang@nuvoton.com>
Date: Mon, 19 Sep 2016 22:10:59 +0800
Subject: [PATCH 45/89] remove warnings

---
 .../arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c     |  2 +-
 .../arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_netif.c   | 10 ++++++----
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c
index 97a1265fc46..441a1a0a5d7 100644
--- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c
+++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c
@@ -48,6 +48,7 @@ u8_t tx_buf[TX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
 
 extern void ethernetif_input(u16_t len, u8_t *buf, u32_t s, u32_t ns);
 extern void ethernetif_loopback_input(struct pbuf *p);
+extern void ack_emac_rx_isr(void);
 
 // PTP source clock is 84MHz (Real chip using PLL). Each tick is 11.90ns
 // Assume we want to set each tick to 100ns.
@@ -256,7 +257,6 @@ unsigned int m_status;
 
 void EMAC_RX_IRQHandler(void)
 {
-    unsigned int cur_entry, status;
 
     m_status = EMAC->INTSTS & 0xFFFF;
     EMAC->INTSTS = m_status;
diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_netif.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_netif.c
index 738b1411797..cd480c07fc8 100644
--- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_netif.c
+++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_netif.c
@@ -79,6 +79,8 @@ struct netif *_netif;
 
 unsigned char my_mac_addr[6] = {0x02, 0x00, 0xac, 0x55, 0x66, 0x77};
 extern u8_t my_mac_addr[6];
+extern int ETH_link_ok(void);
+extern void EMAC_RX_Action(void);
 
 sys_sem_t RxReadySem; /**< RX packet ready semaphore */
 
@@ -421,7 +423,7 @@ err_t
     /* Packet receive task */
 
     err = sys_sem_new(&RxReadySem, 0);
-    LWIP_ASSERT("RxReadySem creation error", (err == ERR_OK));
+    if(err != ERR_OK) LWIP_ASSERT("RxReadySem creation error", (err == ERR_OK));
 	// In GCC code, DEFAULT_THREAD_STACKSIZE 512 bytes is not enough for rx_task
 #if defined (__GNUC__)	
     // mbed OS 2.0, DEFAULT_THREAD_STACKSIZE*3
@@ -482,10 +484,10 @@ typedef struct {
 
 static void __phy_task(void *data) {
   struct netif *netif = (struct netif*)data;
-  PHY_STATE crt_state = {STATE_UNKNOWN, (phy_speed_t)STATE_UNKNOWN, (phy_duplex_t)STATE_UNKNOWN};
-  PHY_STATE prev_state;
+//  PHY_STATE crt_state = {STATE_UNKNOWN, (phy_speed_t)STATE_UNKNOWN, (phy_duplex_t)STATE_UNKNOWN};
+//  PHY_STATE prev_state;
 
-  prev_state = crt_state;
+//  prev_state = crt_state;
   while (1) {
     // Get current status
     // Get the actual PHY link speed

From 6685b4a8cef57cd7df5df635c6f31dfba441ac65 Mon Sep 17 00:00:00 2001
From: cyliangtw <cyliang@nuvoton.com>
Date: Tue, 20 Sep 2016 10:56:15 +0800
Subject: [PATCH 46/89] support mesh in GCC tool chain

---
 .../TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/NUC472.ld             | 1 +
 1 file changed, 1 insertion(+)

diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/NUC472.ld b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/NUC472.ld
index c9d2b2bca86..897bfd31c74 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/NUC472.ld
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/NUC472.ld
@@ -237,6 +237,7 @@ SECTIONS
          */
         *lwip_*.o(.bss*)
         *lwip_*.o(COMMON)
+        *mesh_system.o(.bss*)
        __bss_extern_end__ = .;
     } > RAM_EXTERN
     

From 5ed75ce940a5ac00779927199bcdcfad8035fdc3 Mon Sep 17 00:00:00 2001
From: cyliangtw <cyliang@nuvoton.com>
Date: Tue, 20 Sep 2016 11:02:10 +0800
Subject: [PATCH 47/89] support mesh in IAR tool chain

---
 .../TARGET_NUC472/device/TOOLCHAIN_IAR/NUC472_442.icf           | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/NUC472_442.icf b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/NUC472_442.icf
index 479e48eef88..86aa657a63b 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/NUC472_442.icf
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/NUC472_442.icf
@@ -26,7 +26,7 @@ define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
 /* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
 define block IRAMVEC   with alignment = 1024, size = 4 * (16 + 142)         { };
 /* Move non-critical libraries to external SRAM while internal SRAM is insufficient. */
-define block XRAM_NC   with alignment = 8                                   { zeroinit object *lwip_* };
+define block XRAM_NC   with alignment = 8                                   { zeroinit object *lwip_*, zeroinit object *mesh_system.o };
 
 
 initialize by copy { readwrite };

From c066b6ce75cfb84aaa3c16e2b5e657a13291e134 Mon Sep 17 00:00:00 2001
From: cyliangtw <cyliang@nuvoton.com>
Date: Thu, 29 Sep 2016 17:54:51 +0800
Subject: [PATCH 48/89] Fix warnings in aes_alt

---
 .../hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c      | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
index 0430dbea0dd..6df2663d162 100644
--- a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
+++ b/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
@@ -41,8 +41,7 @@
 //static int aes_init_done = 0;
 
 
-#define mbedtls_trace  //printf
-
+#define mbedtls_trace(...) //printf(__VA_ARGS__)
 
 /* Implementation that should never be optimized out by the compiler */
 static void mbedtls_zeroize( void *v, size_t n ) {

From 20ad95dea73515222e386736cb27fa52a13c980f Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Wed, 5 Oct 2016 17:22:32 +0800
Subject: [PATCH 49/89] Fix buffer overflow in BSP SD driver

---
 .../device/StdDriver/nuc472_sd.c              | 120 ++++++++++++------
 .../device/StdDriver/nuc472_sd.h              |   5 +-
 2 files changed, 86 insertions(+), 39 deletions(-)

diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sd.c b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sd.c
index edfdfec4cfb..b96d2296fb0 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sd.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sd.c
@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     SD.c
  * @version  V1.00
- * $Revision: 13 $
- * $Date: 14/10/08 9:02a $
+ * $Revision: 16 $
+ * $Date: 15/11/26 10:45a $
  * @brief    NUC472/NUC442 SD driver source file
  *
  * @note
@@ -41,12 +41,12 @@ uint8_t *_sd_pSDHCBuffer;
 uint32_t _sd_ReferenceClock;
 
 #if defined (__CC_ARM)
-__align(4096) uint8_t _sd_ucSDHCBuffer[64];
+__align(4096) uint8_t _sd_ucSDHCBuffer[512];
 #elif defined ( __ICCARM__ ) /*!< IAR Compiler */
 #pragma data_alignment = 4096
-uint8_t _sd_ucSDHCBuffer[64];
+uint8_t _sd_ucSDHCBuffer[512];
 #elif defined ( __GNUC__ )
-uint8_t _sd_ucSDHCBuffer[64] __attribute__((aligned (4096)));
+uint8_t _sd_ucSDHCBuffer[512] __attribute__((aligned (4096)));
 #endif
 
 int sd0_ok = 0;
@@ -371,14 +371,20 @@ int SD_Init(SD_INFO_T *pSD)
             for (i=0x100; i>0; i--);
 
             _sd_uR3_CMD = 1;
-            if (SD_SDCmdAndRsp(pSD, 1, 0x80ff8000, u32CmdTimeOut) != 2) { // MMC memory
+
+            if (SD_SDCmdAndRsp(pSD, 1, 0x40ff8000, u32CmdTimeOut) != 2) {  // eMMC memory
                 resp = SD->RESP0;
                 while (!(resp & 0x00800000)) {      // check if card is ready
                     _sd_uR3_CMD = 1;
-                    SD_SDCmdAndRsp(pSD, 1, 0x80ff8000, u32CmdTimeOut);      // high voltage
+
+                    SD_SDCmdAndRsp(pSD, 1, 0x40ff8000, u32CmdTimeOut);      // high voltage
                     resp = SD->RESP0;
                 }
-                pSD->CardType = SD_TYPE_MMC;
+
+                if(resp & 0x00400000)
+                    pSD->CardType = SD_TYPE_EMMC;
+                else
+                    pSD->CardType = SD_TYPE_MMC;
             } else {
                 pSD->CardType = SD_TYPE_UNKNOWN;
                 return SD_ERR_DEVICE;
@@ -403,7 +409,7 @@ int SD_Init(SD_INFO_T *pSD)
     // CMD2, CMD3
     if (pSD->CardType != SD_TYPE_UNKNOWN) {
         SD_SDCmdAndRsp2(pSD, 2, 0x00, CIDBuffer);
-        if (pSD->CardType == SD_TYPE_MMC) {
+        if ((pSD->CardType == SD_TYPE_MMC) || (pSD->CardType == SD_TYPE_EMMC)) {
             if ((status = SD_SDCmdAndRsp(pSD, 3, 0x10000, 0)) != Successful)        // set RCA
                 return status;
             pSD->RCA = 0x10000;
@@ -460,6 +466,7 @@ int SD_SwitchToHighSpeed(SD_INFO_T *pSD)
 int SD_SelectCardType(SD_INFO_T *pSD)
 {
     int volatile status=0;
+    unsigned int arg;
 
     if ((status = SD_SDCmdAndRsp(pSD, 7, pSD->RCA, 0)) != Successful)
         return status;
@@ -509,8 +516,20 @@ int SD_SelectCardType(SD_INFO_T *pSD)
             return status;
 
         SD->CTL |= SDH_CTL_DBW_Msk;
-    } else if (pSD->CardType == SD_TYPE_MMC) {
-        SD->CTL &= ~SDH_CTL_DBW_Msk;
+    } else if ((pSD->CardType == SD_TYPE_MMC) ||(pSD->CardType == SD_TYPE_EMMC)) {
+
+        if(pSD->CardType == SD_TYPE_MMC)
+            SD->CTL &= ~SDH_CTL_DBW_Msk;
+
+        //--- sent CMD6 to MMC card to set bus width to 4 bits mode
+        // set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode)
+        arg = (3 << 24) | (183 << 16) | (1 << 8);
+        if ((status = SD_SDCmdAndRsp(pSD, 6, arg, 0)) != Successful)
+            return status;
+        SD_CheckRB();
+
+        SD->CTL |= SDH_CTL_DBW_Msk;; // set bus width to 4-bit mode for SD host controller
+
     }
 
     if ((status = SD_SDCmdAndRsp(pSD, 16, SD_BLOCK_SIZE, 0)) != Successful) // set block length
@@ -518,9 +537,11 @@ int SD_SelectCardType(SD_INFO_T *pSD)
     SD->BLEN = SD_BLOCK_SIZE - 1;           // set the block size
 
     SD_SDCommand(pSD, 7, 0);
+    SD->CTL |= SDH_CTL_CLK8OEN_Msk;
+    while(SD->CTL & SDH_CTL_CLK8OEN_Msk);
 
 #ifdef _SD_USE_INT_
-    SD->INTEN |= SDH_INTEN_BLKD_IE_Msk;
+    SD->INTEN |= SDH_INTEN_BLKDIEN_Msk;
 #endif  //_SD_USE_INT_
 
     return Successful;
@@ -528,40 +549,61 @@ int SD_SelectCardType(SD_INFO_T *pSD)
 
 void SD_Get_SD_info(SD_INFO_T *pSD, DISK_DATA_T *_info)
 {
-    unsigned int i;
     unsigned int R_LEN, C_Size, MULT, size;
     unsigned int Buffer[4];
     unsigned char *ptr;
 
     SD_SDCmdAndRsp2(pSD, 9, pSD->RCA, Buffer);
 
-    if ((Buffer[0] & 0xc0000000) && (pSD->CardType != SD_TYPE_MMC)) {
-        C_Size = ((Buffer[1] & 0x0000003f) << 16) | ((Buffer[2] & 0xffff0000) >> 16);
-        size = (C_Size+1) * 512;    // Kbytes
+    if ((pSD->CardType == SD_TYPE_MMC) || (pSD->CardType == SD_TYPE_EMMC)) {
+        // for MMC/eMMC card
+        if ((Buffer[0] & 0xc0000000) == 0xc0000000) {
+            // CSD_STRUCTURE [127:126] is 3
+            // CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB
+            SD_SDCmdAndRsp(pSD, 7, pSD->RCA, 0);
+
+            ptr = (uint8_t *)((uint32_t)_sd_ucSDHCBuffer );
+            SD->DMASA = (uint32_t)ptr;  // set DMA transfer starting address
+            SD->BLEN = 511;  // read 512 bytes for EXT_CSD
+
+            if (SD_SDCmdAndRspDataIn(pSD, 8, 0x00) != Successful)
+                return;
 
-        _info->diskSize = size;
-        _info->totalSectorN = size << 1;
+            SD_SDCommand(pSD, 7, 0);
+            SD->CTL |= SDH_CTL_CLK8OEN_Msk;
+            while(SD->CTL & SDH_CTL_CLK8OEN_Msk);
+
+            _info->totalSectorN = (*(uint32_t *)(ptr+212));
+            _info->diskSize = _info->totalSectorN / 2;
+        } else {
+            // CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB
+            R_LEN = (Buffer[1] & 0x000f0000) >> 16;
+            C_Size = ((Buffer[1] & 0x000003ff) << 2) | ((Buffer[2] & 0xc0000000) >> 30);
+            MULT = (Buffer[2] & 0x00038000) >> 15;
+            size = (C_Size+1) * (1<<(MULT+2)) * (1<<R_LEN);
+
+            _info->diskSize = size / 1024;
+            _info->totalSectorN = size / 512;
+        }
     } else {
-        R_LEN = (Buffer[1] & 0x000f0000) >> 16;
-        C_Size = ((Buffer[1] & 0x000003ff) << 2) | ((Buffer[2] & 0xc0000000) >> 30);
-        MULT = (Buffer[2] & 0x00038000) >> 15;
-        size = (C_Size+1) * (1<<(MULT+2)) * (1<<R_LEN);
+        if (Buffer[0] & 0xc0000000) {
+            C_Size = ((Buffer[1] & 0x0000003f) << 16) | ((Buffer[2] & 0xffff0000) >> 16);
+            size = (C_Size+1) * 512;    // Kbytes
 
-        _info->diskSize = size / 1024;
-        _info->totalSectorN = size / 512;
-    }
-    _info->sectorSize = 512;
+            _info->diskSize = size;
+            _info->totalSectorN = size << 1;
+        } else {
+            R_LEN = (Buffer[1] & 0x000f0000) >> 16;
+            C_Size = ((Buffer[1] & 0x000003ff) << 2) | ((Buffer[2] & 0xc0000000) >> 30);
+            MULT = (Buffer[2] & 0x00038000) >> 15;
+            size = (C_Size+1) * (1<<(MULT+2)) * (1<<R_LEN);
 
-    SD_SDCmdAndRsp2(pSD, 10, pSD->RCA, Buffer);
+            _info->diskSize = size / 1024;
+            _info->totalSectorN = size / 512;
+        }
+    }
 
-    _info->vendor[0] = (Buffer[0] & 0xff000000) >> 24;
-    ptr = (unsigned char *)Buffer;
-    ptr = ptr + 4;
-    for (i=0; i<5; i++)
-        _info->product[i] = *ptr++;
-    ptr = ptr + 10;
-    for (i=0; i<4; i++)
-        _info->serial[i] = *ptr++;
+    _info->sectorSize = 512;
 }
 
 int SD_ChipErase(SD_INFO_T *pSD, DISK_DATA_T *_info)
@@ -743,7 +785,7 @@ uint32_t SD_Read(uint32_t u32CardNum, uint8_t *pu8BufAddr, uint32_t u32StartSec,
 
     SD->BLEN = blksize - 1;       // the actual byte count is equal to (SDBLEN+1)
 
-    if (pSD->CardType == SD_TYPE_SD_HIGH)
+    if ( (pSD->CardType == SD_TYPE_SD_HIGH) || (pSD->CardType == SD_TYPE_EMMC) )
         SD->CMDARG = u32StartSec;
     else
         SD->CMDARG = u32StartSec * blksize;
@@ -845,6 +887,8 @@ uint32_t SD_Read(uint32_t u32CardNum, uint8_t *pu8BufAddr, uint32_t u32StartSec,
     SD_CheckRB();
 
     SD_SDCommand(pSD, 7, 0);
+    SD->CTL |= SDH_CTL_CLK8OEN_Msk;
+    while(SD->CTL & SDH_CTL_CLK8OEN_Msk);
 
     return Successful;
 }
@@ -891,7 +935,7 @@ uint32_t SD_Write(uint32_t u32CardNum, uint8_t *pu8BufAddr, uint32_t u32StartSec
     // According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n.
     SD->BLEN = SD_BLOCK_SIZE - 1;           // set the block size
 
-    if (pSD->CardType == SD_TYPE_SD_HIGH)
+    if ((pSD->CardType == SD_TYPE_SD_HIGH) || (pSD->CardType == SD_TYPE_EMMC))
         SD->CMDARG = u32StartSec;
     else
         SD->CMDARG = u32StartSec * SD_BLOCK_SIZE;  // set start address for SD CMD
@@ -975,6 +1019,8 @@ uint32_t SD_Write(uint32_t u32CardNum, uint8_t *pu8BufAddr, uint32_t u32StartSec
     SD_CheckRB();
 
     SD_SDCommand(pSD, 7, 0);
+    SD->CTL |= SDH_CTL_CLK8OEN_Msk;
+    while(SD->CTL & SDH_CTL_CLK8OEN_Msk);
 
     return Successful;
 }
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sd.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sd.h
index 05295728bb3..27a4c4978dd 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sd.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sd.h
@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     sd.h
  * @version  V1.00
- * $Revision: 11 $
- * $Date: 14/10/03 2:25p $
+ * $Revision: 12 $
+ * $Date: 14/11/04 10:10a $
  * @brief    NUC472/NUC442 SD driver header file
  *
  * @note
@@ -41,6 +41,7 @@
 #define SD_TYPE_SD_HIGH 1
 #define SD_TYPE_SD_LOW      2
 #define SD_TYPE_MMC     3
+#define SD_TYPE_EMMC		4
 
 /* SD error */
 #define SD_NO_SD_CARD           (SD_ERR_ID|0x10)

From 0b6043432773974fe3483d674612ffd38fc9f8b5 Mon Sep 17 00:00:00 2001
From: cyliangtw <cyliang@nuvoton.com>
Date: Wed, 5 Oct 2016 20:26:36 +0800
Subject: [PATCH 50/89] EMAC buffer address word alignment

---
 .../arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c    | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c
index 441a1a0a5d7..22610c3209c 100644
--- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c
+++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c
@@ -24,7 +24,7 @@
 #include "nuc472_eth.h"
 #include "lwip/opt.h"
 #include "lwip/def.h"
-
+#include "toolchain.h"
 
 #define ETH_TRIGGER_RX()    do{EMAC->RXST = 0;}while(0)
 #define ETH_TRIGGER_TX()    do{EMAC->TXST = 0;}while(0)
@@ -33,6 +33,7 @@
 #define ETH_DISABLE_TX()    do{EMAC->CTL &= ~EMAC_CTL_TXON;}while(0)
 #define ETH_DISABLE_RX()    do{EMAC->CTL &= ~EMAC_CTL_RXON;}while(0)
 
+/*
 #ifdef __ICCARM__
 #pragma data_alignment=4
 struct eth_descriptor rx_desc[RX_DESCRIPTOR_NUM];
@@ -41,10 +42,14 @@ struct eth_descriptor tx_desc[TX_DESCRIPTOR_NUM];
 struct eth_descriptor rx_desc[RX_DESCRIPTOR_NUM] __attribute__ ((aligned(4)));
 struct eth_descriptor tx_desc[TX_DESCRIPTOR_NUM] __attribute__ ((aligned(4)));
 #endif
+*/
+struct eth_descriptor rx_desc[RX_DESCRIPTOR_NUM] MBED_ALIGN(4);
+struct eth_descriptor tx_desc[TX_DESCRIPTOR_NUM] MBED_ALIGN(4);
+
 struct eth_descriptor volatile *cur_tx_desc_ptr, *cur_rx_desc_ptr, *fin_tx_desc_ptr;
 
-u8_t rx_buf[RX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
-u8_t tx_buf[TX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
+u8_t rx_buf[RX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE]  MBED_ALIGN(4);
+u8_t tx_buf[TX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE]  MBED_ALIGN(4);
 
 extern void ethernetif_input(u16_t len, u8_t *buf, u32_t s, u32_t ns);
 extern void ethernetif_loopback_input(struct pbuf *p);

From 03d00df0ca63dca54d2e88e5b720d9d1070be0de Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Thu, 6 Oct 2016 17:30:20 +0800
Subject: [PATCH 51/89] Fix pin definition error regarding SD, I2C, and SPI

1. Fix pin definition error regarding SD.
2. Fix pin definition error regarding I2C.
3. Fix pin definition error regarding SPI.
4. Add pinmap for SD.
---
 .../TARGET_NUMAKER_PFM_M453/PeripheralPins.h  | 10 +++
 .../PeripheralNames.h                         |  5 ++
 .../PeripheralPins.c                          | 71 +++++++++++++++++--
 .../device/StdDriver/nuc472_sys.h             | 69 +++++++++---------
 4 files changed, 115 insertions(+), 40 deletions(-)

diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.h
index 5b1a453de9d..6c9a26b865e 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.h
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.h
@@ -55,6 +55,16 @@ extern const PinMap PinMap_SPI_MISO[];
 extern const PinMap PinMap_SPI_SCLK[];
 extern const PinMap PinMap_SPI_SSEL[];
 
+//*** SD ***
+
+extern const PinMap PinMap_SD_CD[];
+extern const PinMap PinMap_SD_CMD[];
+extern const PinMap PinMap_SD_CLK[];
+extern const PinMap PinMap_SD_DAT0[];
+extern const PinMap PinMap_SD_DAT1[];
+extern const PinMap PinMap_SD_DAT2[];
+extern const PinMap PinMap_SD_DAT3[];
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h
index fe3cb0ed96f..2cdc0bbc454 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h
@@ -115,6 +115,11 @@ typedef enum {
     DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0)
 } DMAName;
 
+typedef enum {
+    SD_0 = (int) NU_MODNAME(SD_BASE, 0),
+    SD_1 = (int) NU_MODNAME(SD_BASE, 1)
+} SDName;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.c
index 31779f32f50..4ab4693a68b 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.c
@@ -227,7 +227,7 @@ const PinMap PinMap_I2C_SDA[] = {
     {PD_3,  I2C_3, SYS_GPD_MFPL_PD3MFP_I2C3_SDA},
     {PD_9,  I2C_0, SYS_GPD_MFPH_PD9MFP_I2C0_SDA},
     {PD_12, I2C_4, SYS_GPD_MFPH_PD12MFP_I2C4_SDA},
-    {PG_15, I2C_1, SYS_GPG_MFPH_PG15MFP_I2C1_SDA},
+    {PG_14, I2C_1, SYS_GPG_MFPH_PG14MFP_I2C1_SDA},
     {PH_1, I2C_1, SYS_GPH_MFPL_PH1MFP_I2C1_SDA},
     {PH_4, I2C_3, SYS_GPH_MFPL_PH4MFP_I2C3_SDA},
     {PI_8, I2C_2, SYS_GPI_MFPH_PI8MFP_I2C2_SDA},
@@ -243,7 +243,7 @@ const PinMap PinMap_I2C_SCL[] = {
     {PD_2, I2C_3, SYS_GPD_MFPL_PD2MFP_I2C3_SCL},
     {PD_8, I2C_0, SYS_GPD_MFPH_PD8MFP_I2C0_SCL},
     {PD_10, I2C_4, SYS_GPD_MFPH_PD10MFP_I2C4_SCL},
-    {PG_14, I2C_1, SYS_GPG_MFPH_PG14MFP_I2C1_SCL},
+    {PG_15, I2C_1, SYS_GPG_MFPH_PG15MFP_I2C1_SCL},
     {PH_0, I2C_1, SYS_GPH_MFPL_PH0MFP_I2C1_SCL},
     {PH_3, I2C_3, SYS_GPH_MFPL_PH3MFP_I2C3_SCL},
     {PI_7, I2C_2, SYS_GPI_MFPL_PI7MFP_I2C2_SCL},
@@ -370,7 +370,7 @@ const PinMap PinMap_SPI_MOSI[] = {
     {PA_12, SPI_3, SYS_GPA_MFPH_PA12MFP_SPI3_MOSI1},
     {PB_5, SPI_2, SYS_GPB_MFPL_PB5MFP_SPI2_MOSI0},
     {PB_13, SPI_2, SYS_GPB_MFPH_PB13MFP_SPI2_MOSI1},
-    {PC_4, SPI_0, SYS_GPC_MFPL_PC4MFP_SPI0_MOSI0},
+    {PC_4, SPI_0, SYS_GPC_MFPL_PC4MFP_SPI0_MOSI1},
     {PC_7, SPI_0, SYS_GPC_MFPL_PC7MFP_SPI0_MOSI0},
     {PC_13, SPI_1, SYS_GPC_MFPH_PC13MFP_SPI1_MOSI1},
     {PC_15, SPI_1, SYS_GPC_MFPH_PC15MFP_SPI1_MOSI0},
@@ -379,7 +379,7 @@ const PinMap PinMap_SPI_MOSI[] = {
     {PE_7, SPI_0, SYS_GPE_MFPL_PE7MFP_SPI0_MOSI0},
     {PE_11, SPI_0, SYS_GPE_MFPH_PE11MFP_SPI0_MOSI1},
     {PF_0, SPI_1, SYS_GPF_MFPL_PF0MFP_SPI1_MOSI0},
-    {PF_1, SPI_2, SYS_GPF_MFPL_PF1MFP_SPI2_MOSI0},
+    {PF_1, SPI_2, SYS_GPF_MFPL_PF1MFP_SPI2_MOSI1},
     {PF_5, SPI_3, SYS_GPF_MFPL_PF5MFP_SPI3_MOSI0},
     {PG_8, SPI_2, SYS_GPG_MFPH_PG8MFP_SPI2_MOSI0},
     {PH_8, SPI_2, SYS_GPH_MFPH_PH8MFP_SPI2_MOSI0},
@@ -447,3 +447,66 @@ const PinMap PinMap_SPI_SSEL[] = {
     
     {NC,    NC,    0}
 };
+
+//*** SD ***
+
+const PinMap PinMap_SD_CD[] = {
+    {PC_12, SD_1, SYS_GPC_MFPH_PC12MFP_SD1_CDn},
+    {PD_3, SD_0, SYS_GPD_MFPL_PD3MFP_SD0_CDn},
+    {PE_5, SD_0, SYS_GPE_MFPL_PE5MFP_SD0_CDn},
+    {PF_6, SD_0, SYS_GPF_MFPL_PF6MFP_SD0_CDn},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SD_CMD[] = {
+    {PC_13, SD_1, SYS_GPC_MFPH_PC13MFP_SD1_CMD},
+    {PD_6, SD_0, SYS_GPD_MFPL_PD6MFP_SD0_CMD},
+    {PE_6, SD_0, SYS_GPE_MFPL_PE6MFP_SD0_CMD},
+    {PF_7, SD_0, SYS_GPF_MFPL_PF7MFP_SD0_CMD},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SD_CLK[] = {
+    {PC_14, SD_1, SYS_GPC_MFPH_PC14MFP_SD1_CLK},
+    {PD_7, SD_0, SYS_GPD_MFPL_PD7MFP_SD0_CLK},
+    {PE_7, SD_0, SYS_GPE_MFPL_PE7MFP_SD0_CLK},
+    {PF_8, SD_0, SYS_GPF_MFPH_PF8MFP_SD0_CLK},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SD_DAT0[] = {
+    {PC_9, SD_1, SYS_GPC_MFPH_PC9MFP_SD1_DAT0},
+    {PD_2, SD_1, SYS_GPD_MFPL_PD2MFP_SD1_DAT0},
+    {PE_11, SD_0, SYS_GPE_MFPH_PE11MFP_SD0_DAT0},
+    {PF_5, SD_0, SYS_GPF_MFPL_PF5MFP_SD0_DAT0},
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SD_DAT1[] = {
+    {PD_1, SD_1, SYS_GPD_MFPL_PD1MFP_SD1_DAT1},
+    {PE_10, SD_0, SYS_GPE_MFPH_PE10MFP_SD0_DAT1},
+    {PF_4, SD_0, SYS_GPF_MFPL_PF4MFP_SD0_DAT1},
+    
+    
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SD_DAT2[] = {
+    {PD_0, SD_1, SYS_GPD_MFPL_PD0MFP_SD1_DAT2},
+    {PE_9, SD_0, SYS_GPE_MFPH_PE9MFP_SD0_DAT2},
+    {PF_3, SD_0, SYS_GPF_MFPL_PF3MFP_SD0_DAT2},
+
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SD_DAT3[] = {
+    {PC_15, SD_1, SYS_GPC_MFPH_PC15MFP_SD1_DAT3},
+    {PE_8, SD_0, SYS_GPE_MFPH_PE8MFP_SD0_DAT3},
+    {PF_2, SD_0, SYS_GPF_MFPL_PF2MFP_SD0_DAT3},
+
+    {NC,    NC,    0}
+};
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sys.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sys.h
index ed4ce3ae5e0..bf6cc6995bf 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sys.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sys.h
@@ -2,7 +2,7 @@
  * @file     SYS.h
  * @version  V1.0
  * $Revision  1 $
- * $Date: 14/10/06 1:15p $
+ * $Date: 15/10/21 1:35p $
  * @brief    NUC472/NUC442 SYS Header File
  *
  * @note
@@ -32,16 +32,14 @@ extern "C"
 /*---------------------------------------------------------------------------------------------------------*/
 /*  Module Reset Control Resister constant definitions.                                                    */
 /*---------------------------------------------------------------------------------------------------------*/
-#define CHIP_RST  ((0x0<<24)|SYS_IPRST0_CHIPRST_Pos)    /*!<Reset CHIP  \hideinitializer */
-#define CPU_RST   ((0x0<<24)|SYS_IPRST0_CPURST_Pos)     /*!<Reset CPU  \hideinitializer  */
 #define PDMA_RST  ((0x0<<24)|SYS_IPRST0_PDMARST_Pos)    /*!<Reset PDMA  \hideinitializer */
 #define EBI_RST   ((0x0<<24)|SYS_IPRST0_EBIRST_Pos)     /*!<Reset EBI  \hideinitializer  */
-#define USBH_RST  ((0x0<<24)|SYS_IPRST0_USBHRST_Pos)     /*!<Reset USBH  \hideinitializer  */
+#define USBH_RST  ((0x0<<24)|SYS_IPRST0_USBHRST_Pos)    /*!<Reset USBH  \hideinitializer  */
 #define EMAC_RST  ((0x0<<24)|SYS_IPRST0_EMACRST_Pos)    /*!<Reset EMAC  \hideinitializer */
-#define SDH_RST   ((0x0<<24)|SYS_IPRST0_SDRST_Pos)      /*!<Reset SDIO  \hideinitializer */
+#define SDH_RST   ((0x0<<24)|SYS_IPRST0_SDHRST_Pos)     /*!<Reset SDIO  \hideinitializer */
 #define CRC_RST   ((0x0<<24)|SYS_IPRST0_CRCRST_Pos)     /*!<Reset CRC  \hideinitializer  */
 #define CAP_RST   ((0x0<<24)|SYS_IPRST0_CAPRST_Pos)     /*!<Reset CAP  \hideinitializer  */
-#define SPACC_RST ((0x0<<24)|SYS_IPRST0_SPACCRST_Pos)   /*!<Reset SPACC  \hideinitializer */
+#define CRYPTO_RST ((0x0<<24)|SYS_IPRST0_CRYPTORST_Pos)  /*!<Reset CRYPTO  \hideinitializer */
 #define GPIO_RST  ((0x4<<24)|SYS_IPRST1_GPIORST_Pos)    /*!<Reset GPIO  \hideinitializer  */
 #define TMR0_RST  ((0x4<<24)|SYS_IPRST1_TMR0RST_Pos)    /*!<Reset TMR0  \hideinitializer */
 #define TMR1_RST  ((0x4<<24)|SYS_IPRST1_TMR1RST_Pos)    /*!<Reset TMR1 \hideinitializer */
@@ -85,23 +83,16 @@ extern "C"
 /*---------------------------------------------------------------------------------------------------------*/
 /*  BODCTL constant definitions.                                                                            */
 /*---------------------------------------------------------------------------------------------------------*/
-#define  SYS_BODCTL_EN                (0x1UL<<SYS_BODCTL_BODEN_Pos)        /*!<Enable BOD IP \hideinitializer */
 #define  SYS_BODCTL_BODVL_2_2V        (0x0UL<<SYS_BODCTL_BODVL_Pos)        /*!<Threshold voltage of BOD is selected 2.2V \hideinitializer */
 #define  SYS_BODCTL_BODVL_2_7V        (0x1UL<<SYS_BODCTL_BODVL_Pos)        /*!<Threshold voltage of BOD is selected 2.7V \hideinitializer */
 #define  SYS_BODCTL_BODVL_3_8V        (0x2UL<<SYS_BODCTL_BODVL_Pos)        /*!<Threshold voltage of BOD is selected 3.82V \hideinitializer */
 #define  SYS_BODCTL_BODVL_4_5V        (0x3UL<<SYS_BODCTL_BODVL_Pos)        /*!<Threshold voltage of BOD is selected 4.5V \hideinitializer */
 #define  SYS_BODCTL_BODRSTEN          (0x1UL<<SYS_BODCTL_BODRSTEN_Pos)     /*!<Enable reset function of BOD. \hideinitializer */
 #define  SYS_BODCTL_BODINTEN          (0x0UL<<SYS_BODCTL_BODRSTEN_Pos)     /*!<Enable interrupt function of BOD. \hideinitializer */
-#define  SYS_BODCTL_BODINTF           (0x1UL<<SYS_BODCTL_BODINTF_Pos)      /*!<BOD caused a interrupt. \hideinitializer */
 #define  SYS_BODCTL_BODLPM            (0x1UL<<SYS_BODCTL_BODLPM_Pos)       /*!<BOD work in low power mode. \hideinitializer */
 #define  SYS_BODCTL_BODOUT            (0x1UL<<SYS_BODCTL_BODOUT_Pos)       /*!<Output of BOD IP. \hideinitializer */
 #define  SYS_BODCTL_LVREN             (0x1UL<<SYS_BODCTL_LVREN_Pos)        /*!<Enable LVR function. \hideinitializer */
 
-/*---------------------------------------------------------------------------------------------------------*/
-/*  TEMPCTL constant definitions.                                                                           */
-/*---------------------------------------------------------------------------------------------------------*/
-#define SYS_TEMPCTL_VTEMP_EN (0x1UL<<SYS_TEMPCTL_VTEMPEN_Pos)     /*!<Temperature sensor function Enabled \hideinitializer */
-
 /*---------------------------------------------------------------------------------------------------------*/
 /*  VREFCTL constant definitions. (Write-Protection Register)                                               */
 /*---------------------------------------------------------------------------------------------------------*/
@@ -144,7 +135,7 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
 
 //GPA_MFPL_PA1MFP
 #define SYS_GPA_MFPL_PA1MFP_GPIO        (0x0UL<<SYS_GPA_MFPL_PA1MFP_Pos)            /*!< GPA_MFPL PA1 setting for GPIO    \hideinitializer */
-#define SYS_GPA_MFPL_PA1MFP_TAMPER0     (0x1UL<<SYS_GPA_MFPL_PA1MFP_Pos)            /*!< GPA_MFPL PA1 setting for TAMPER1   \hideinitializer */
+#define SYS_GPA_MFPL_PA1MFP_TAMPER1     (0x1UL<<SYS_GPA_MFPL_PA1MFP_Pos)            /*!< GPA_MFPL PA1 setting for TAMPER1   \hideinitializer */
 #define SYS_GPA_MFPL_PA1MFP_SC5_CD      (0x2UL<<SYS_GPA_MFPL_PA1MFP_Pos)            /*!< GPA_MFPL PA1 setting for SC5_CD  \hideinitializer */
 #define SYS_GPA_MFPL_PA1MFP_CAN1_TXD    (0x3UL<<SYS_GPA_MFPL_PA1MFP_Pos)            /*!< GPA_MFPL PA1 setting for CAN1_TXD  \hideinitializer */
 #define SYS_GPA_MFPL_PA1MFP_EBI_A22     (0x7UL<<SYS_GPA_MFPL_PA1MFP_Pos)            /*!< GPA_MFPL PA1 setting for EBI_A22 \hideinitializer */
@@ -161,8 +152,8 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
 //GPA_MFPL_PA3MFP
 #define SYS_GPA_MFPL_PA3MFP_GPIO        (0x0UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for GPIO     \hideinitializer */
 #define SYS_GPA_MFPL_PA3MFP_SC2_CLK     (0x1UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for SC2_CLK      \hideinitializer */
-#define SYS_GPA_MFPL_PA3MFP_SP3_MOSI0   (0x2UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for SP3_MOSI0      \hideinitializer */
-#define SYS_GPA_MFPL_PA3MFP_I2S0_D0     (0x3UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for I2S0_D0     \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_SPI3_MOSI0  (0x2UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for SPI3_MOSI0      \hideinitializer */
+#define SYS_GPA_MFPL_PA3MFP_I2S0_DO     (0x3UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for I2S0_D0     \hideinitializer */
 #define SYS_GPA_MFPL_PA3MFP_BRAKE10     (0x4UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for BRAKE10    \hideinitializer */
 #define SYS_GPA_MFPL_PA3MFP_EBI_A13     (0x7UL<<SYS_GPA_MFPL_PA3MFP_Pos)           /*!< GPA_MFPL PA3 setting for EBI_A13    \hideinitializer */
 
@@ -182,7 +173,7 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
 #define SYS_GPA_MFPL_PA5MFP_I2S0_BCLK   (0x3UL<<SYS_GPA_MFPL_PA5MFP_Pos)          /*!< GPA_MFPL PA5 setting for I2S0_BCLK    \hideinitializer */
 #define SYS_GPA_MFPL_PA5MFP_PWM0_CH0    (0x4UL<<SYS_GPA_MFPL_PA5MFP_Pos)            /*!< GPA_MFPL PA5 setting for PWM0 CH0     \hideinitializer */
 #define SYS_GPA_MFPL_PA5MFP_QEI1_B      (0x5UL<<SYS_GPA_MFPL_PA5MFP_Pos)            /*!< GPA_MFPL PA5 setting for QEI1_B    \hideinitializer */
-#define SYS_GPA_MFPL_PA5MFP_EBIA15      (0x7UL<<SYS_GPA_MFPL_PA5MFP_Pos)            /*!< GPA_MFPL PA5 setting for EBIA15    \hideinitializer */
+#define SYS_GPA_MFPL_PA5MFP_EBI_A15     (0x7UL<<SYS_GPA_MFPL_PA5MFP_Pos)            /*!< GPA_MFPL PA5 setting for EBI_A15    \hideinitializer */
 #define SYS_GPA_MFPL_PA5MFP_ECAP1_IC1   (0x8UL<<SYS_GPA_MFPL_PA5MFP_Pos)            /*!< GPA_MFPL PA5 setting for ECAP1_IC1    \hideinitializer */
 
 //GPA_MFPL_PA6MFP
@@ -268,7 +259,7 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
 #define SYS_GPB_MFPL_PB0MFP_GPIO           (0x0UL<<SYS_GPB_MFPL_PB0MFP_Pos)           /*!< GPB_MFPL PB0 setting for GPIO     \hideinitializer */
 #define SYS_GPB_MFPL_PB0MFP_USB0_OTG5V_ST  (0x1UL<<SYS_GPB_MFPL_PB0MFP_Pos)           /*!< GPB_MFPL PB0 setting for USB0_OTG5V_ST    \hideinitializer */
 #define SYS_GPB_MFPL_PB0MFP_I2C4_SCL       (0x2UL<<SYS_GPB_MFPL_PB0MFP_Pos)           /*!< GPB_MFPL PB0 setting for I2C4_SCL     \hideinitializer */
-#define SYS_GPB_MFPL_PB0MFP_INT11          (0x8UL<<SYS_GPB_MFPL_PB0MFP_Pos)           /*!< GPB_MFPL PB0 setting for INT11    \hideinitializer */
+#define SYS_GPB_MFPL_PB0MFP_INT1           (0x8UL<<SYS_GPB_MFPL_PB0MFP_Pos)           /*!< GPB_MFPL PB0 setting for INT1     \hideinitializer */
 
 //GPB_MFPL_PB1MFP
 #define SYS_GPB_MFPL_PB1MFP_GPIO           (0x0UL<<SYS_GPB_MFPL_PB1MFP_Pos)           /*!< GPB_MFPL PB1 setting for GPIO     \hideinitializer */
@@ -426,7 +417,7 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
 #define SYS_GPC_MFPL_PC4MFP_GPIO             (0x0UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for GPIO     \hideinitializer */
 #define SYS_GPC_MFPL_PC4MFP_I2S1_DO          (0x1UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for I2S1_DO    \hideinitializer */
 #define SYS_GPC_MFPL_PC4MFP_SC1_RST          (0x2UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for SC1_RST    \hideinitializer */
-#define SYS_GPC_MFPL_PC4MFP_SPI0_MOSI0       (0x4UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for SPI0_MOSI0     \hideinitializer */
+#define SYS_GPC_MFPL_PC4MFP_SPI0_MOSI1       (0x4UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for SPI0_MOSI1     \hideinitializer */
 #define SYS_GPC_MFPL_PC4MFP_QEI0_B           (0x5UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for QEI0_B     \hideinitializer */
 #define SYS_GPC_MFPL_PC4MFP_EMAC_MII_RXD0    (0x6UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for EMAC_MII_RXD0    \hideinitializer */
 #define SYS_GPC_MFPL_PC4MFP_EBI_AD10         (0x7UL<<SYS_GPC_MFPL_PC4MFP_Pos)           /*!< GPC_MFPL PC4 setting for EBI_AD10     \hideinitializer */
@@ -555,7 +546,7 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
 #define SYS_GPD_MFPL_PD3MFP_SC5_CLK          (0x1UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for SC5_CLK    \hideinitializer */
 #define SYS_GPD_MFPL_PD3MFP_I2C3_SDA         (0x2UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for I2C3_SDA     \hideinitializer */
 #define SYS_GPD_MFPL_PD3MFP_ACMP2_O          (0x3UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for ACMP2_O    \hideinitializer */
-#define SYS_GPD_MFPL_PD3MFP_SD1_CDn          (0x4UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for SD1_CDn    \hideinitializer */
+#define SYS_GPD_MFPL_PD3MFP_SD0_CDn          (0x4UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for SD0_CDn    \hideinitializer */
 #define SYS_GPD_MFPL_PD3MFP_CAP_DATA0        (0x5UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for CAP_DATA0    \hideinitializer */
 #define SYS_GPD_MFPL_PD3MFP_JTAG_TDO         (0x6UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for JTAG_TDO     \hideinitializer */
 #define SYS_GPD_MFPL_PD3MFP_EBI_A7           (0x7UL<<SYS_GPD_MFPL_PD3MFP_Pos)           /*!< GPD_MFPL PD3 setting for EBI_A7     \hideinitializer */
@@ -669,14 +660,14 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
 #define SYS_GPE_MFPL_PE5MFP_ADC0_5          (0x1UL<<SYS_GPE_MFPL_PE5MFP_Pos)           /*!< GPE_MFPL PE5 setting for ADC0_5     \hideinitializer */
 #define SYS_GPE_MFPL_PE5MFP_ACMP0_P1        (0x2UL<<SYS_GPE_MFPL_PE5MFP_Pos)           /*!< GPE_MFPL PE5 setting for ACMP0_P1     \hideinitializer */
 #define SYS_GPE_MFPL_PE5MFP_SPI0_CLK        (0x3UL<<SYS_GPE_MFPL_PE5MFP_Pos)           /*!< GPE_MFPL PE5 setting for SPI0_CLK     \hideinitializer */
-#define SYS_GPE_MFPL_PE5MFP_SC0_CDn         (0x4UL<<SYS_GPE_MFPL_PE5MFP_Pos)           /*!< GPE_MFPL PE5 setting for SC0_CDn      \hideinitializer */
+#define SYS_GPE_MFPL_PE5MFP_SD0_CDn         (0x4UL<<SYS_GPE_MFPL_PE5MFP_Pos)           /*!< GPE_MFPL PE5 setting for SD0_CDn      \hideinitializer */
 
 //GPE_MFPL_PE6MFP
 #define SYS_GPE_MFPL_PE6MFP_GPIO            (0x0UL<<SYS_GPE_MFPL_PE6MFP_Pos)           /*!< GPE_MFPL PE6 setting for GPIO     \hideinitializer */
 #define SYS_GPE_MFPL_PE6MFP_ADC0_6          (0x1UL<<SYS_GPE_MFPL_PE6MFP_Pos)            /*!< GPE_MFPL PE6 setting for ADC0_6    \hideinitializer */
 #define SYS_GPE_MFPL_PE6MFP_ACMP0_P0        (0x2UL<<SYS_GPE_MFPL_PE6MFP_Pos)            /*!< GPE_MFPL PE6 setting for ACMP0_P0    \hideinitializer */
 #define SYS_GPE_MFPL_PE6MFP_SPI0_MISO0      (0x3UL<<SYS_GPE_MFPL_PE6MFP_Pos)            /*!< GPE_MFPL PE6 setting for SPI0_MISO0    \hideinitializer */
-#define SYS_GPE_MFPL_PE6MFP_SC0_CMD         (0x4UL<<SYS_GPE_MFPL_PE6MFP_Pos)            /*!< GPE_MFPL PE6 setting for SC0_CMD     \hideinitializer */
+#define SYS_GPE_MFPL_PE6MFP_SD0_CMD         (0x4UL<<SYS_GPE_MFPL_PE6MFP_Pos)            /*!< GPE_MFPL PE6 setting for SD0_CMD     \hideinitializer */
 #define SYS_GPE_MFPL_PE6MFP_EBI_nWR         (0x7UL<<SYS_GPE_MFPL_PE6MFP_Pos)            /*!< GPE_MFPL PE6 setting for EBI_nWR     \hideinitializer */
 
 //GPE_MFPL_PE7MFP
@@ -684,38 +675,43 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
 #define SYS_GPE_MFPL_PE7MFP_ADC0_7          (0x1UL<<SYS_GPE_MFPL_PE7MFP_Pos)           /*!< GPE_MFPL PE7 setting for ADC0_7     \hideinitializer */
 #define SYS_GPE_MFPL_PE7MFP_ACMP0_N         (0x2UL<<SYS_GPE_MFPL_PE7MFP_Pos)           /*!< GPE_MFPL PE7 setting for ACMP0_N      \hideinitializer */
 #define SYS_GPE_MFPL_PE7MFP_SPI0_MOSI0      (0x3UL<<SYS_GPE_MFPL_PE7MFP_Pos)           /*!< GPE_MFPL PE7 setting for SPI0_MOSI0     \hideinitializer */
-#define SYS_GPE_MFPL_PE7MFP_SC0_CLK         (0x4UL<<SYS_GPE_MFPL_PE7MFP_Pos)           /*!< GPE_MFPL PE7 setting for SC0_CLK      \hideinitializer */
+#define SYS_GPE_MFPL_PE7MFP_SD0_CLK         (0x4UL<<SYS_GPE_MFPL_PE7MFP_Pos)           /*!< GPE_MFPL PE7 setting for SD0_CLK      \hideinitializer */
 #define SYS_GPE_MFPL_PE7MFP_EBI_nRD         (0x7UL<<SYS_GPE_MFPL_PE7MFP_Pos)           /*!< GPE_MFPL PE7 setting for _EBI_nRD     \hideinitializer */
 
 //GPE_MFPL_PE8MFP
 #define SYS_GPE_MFPH_PE8MFP_GPIO            (0x0UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for GPIO     \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_ADC0_8          (0x1UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for ADC0_8     \hideinitializer */
 #define SYS_GPE_MFPH_PE8MFP_ADC1_0          (0x1UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for ADC1_0     \hideinitializer */
 #define SYS_GPE_MFPH_PE8MFP_ACMP1_N         (0x2UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for ACMP1_N    \hideinitializer */
 #define SYS_GPE_MFPH_PE8MFP_TM1_CNT_OUT     (0x3UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for TM1_CNT_OUT    \hideinitializer */
-#define SYS_GPE_MFPH_PE8MFP_SC0_DAT3        (0x4UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for SC0_DAT3     \hideinitializer */
+#define SYS_GPE_MFPH_PE8MFP_SD0_DAT3        (0x4UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for SD0_DAT3     \hideinitializer */
 #define SYS_GPE_MFPH_PE8MFP_EBI_ALE         (0x7UL<<SYS_GPE_MFPH_PE8MFP_Pos)           /*!< GPE_MFPH PE8 setting for EBI_ALE    \hideinitializer */
 
 //GPE_MFPH_PE9MFP
 #define SYS_GPE_MFPH_PE9MFP_GPIO            (0x0UL<<SYS_GPE_MFPH_PE9MFP_Pos)           /*!< GPE_MFPH PE9 setting for GPIO     \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_ADC0_9          (0x1UL<<SYS_GPE_MFPH_PE9MFP_Pos)           /*!< GPE_MFPH PE9 setting for ADC0_9     \hideinitializer */
 #define SYS_GPE_MFPH_PE9MFP_ADC1_1          (0x1UL<<SYS_GPE_MFPH_PE9MFP_Pos)           /*!< GPE_MFPH PE9 setting for ADC1_1     \hideinitializer */
 #define SYS_GPE_MFPH_PE9MFP_ACMP1_P0        (0x2UL<<SYS_GPE_MFPH_PE9MFP_Pos)           /*!< GPE_MFPH PE9 setting for ACMP1_P0     \hideinitializer */
-#define SYS_GPE_MFPH_PE9MFP_SC0_DAT2        (0x4UL<<SYS_GPE_MFPH_PE9MFP_Pos)           /*!< GPE_MFPH PE9 setting for SC0_DAT2     \hideinitializer */
+#define SYS_GPE_MFPH_PE9MFP_SD0_DAT2        (0x4UL<<SYS_GPE_MFPH_PE9MFP_Pos)           /*!< GPE_MFPH PE9 setting for SD0_DAT2     \hideinitializer */
 #define SYS_GPE_MFPH_PE9MFP_EBI_nWRH        (0x7UL<<SYS_GPE_MFPH_PE9MFP_Pos)           /*!< GPE_MFPH PE9 setting for EBI_nWRH     \hideinitializer */
 
 //GPE_MFPH_PE10MFP
 #define SYS_GPE_MFPH_PE10MFP_GPIO           (0x0UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for GPIO   \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_ADC0_10        (0x1UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for ADC0_10     \hideinitializer */
 #define SYS_GPE_MFPH_PE10MFP_ADC1_2         (0x1UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for ADC1_2   \hideinitializer */
 #define SYS_GPE_MFPH_PE10MFP_ACMP1_P1       (0x2UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for ACMP1_P1   \hideinitializer */
 #define SYS_GPE_MFPH_PE10MFP_SPI0_MISO1     (0x3UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for SPI0_MISO1   \hideinitializer */
+#define SYS_GPE_MFPH_PE10MFP_SD0_DAT1       (0x4UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for SD0_DAT1     \hideinitializer */
 #define SYS_GPE_MFPH_PE10MFP_EBI_nWRL       (0x7UL<<SYS_GPE_MFPH_PE10MFP_Pos)           /*!< GPE_MFPH PE10 setting for EBI_nWRL   \hideinitializer */
 
 //GPE_MFPH_PE11MFP
 #define SYS_GPE_MFPH_PE11MFP_GPIO           (0x0UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for GPIO   \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_ADC0_11        (0x1UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for ADC0_11     \hideinitializer */
 #define SYS_GPE_MFPH_PE11MFP_ADC1_3         (0x1UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for ADC1_3   \hideinitializer */
 #define SYS_GPE_MFPH_PE11MFP_ACMP1_P2       (0x2UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for ACMP1_P2   \hideinitializer */
 #define SYS_GPE_MFPH_PE11MFP_SPI0_MOSI1     (0x3UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for SPI0_MOSI1   \hideinitializer */
-#define SYS_GPE_MFPH_PE11MFP_SC0_DAT0       (0x4UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for SC0_DAT0   \hideinitializer */
-#define SYS_GPE_MFPH_PE11MFP_CMP2_P3        (0x5UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for CMP2_P3   \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_SD0_DAT0       (0x4UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for SD0_DAT0   \hideinitializer */
+#define SYS_GPE_MFPH_PE11MFP_ACMP2_P3       (0x5UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for ACMP2_P3   \hideinitializer */
 #define SYS_GPE_MFPH_PE11MFP_EBI_nCS0       (0x7UL<<SYS_GPE_MFPH_PE11MFP_Pos)           /*!< GPE_MFPH PE11 setting for EBI_nCS0   \hideinitializer */
 
 //GPE_MFPH_PE12MFP
@@ -749,7 +745,7 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
 
 //GPF_MFPL_PF1MFP
 #define SYS_GPF_MFPL_PF1MFP_GPIO            (0x0UL<<SYS_GPF_MFPL_PF1MFP_Pos)           /*!< GPF_MFPL PF1 setting for GPIO     \hideinitializer */
-#define SYS_GPF_MFPL_PF1MFP_SPI2_MOSI0      (0x1UL<<SYS_GPF_MFPL_PF1MFP_Pos)           /*!< GPF_MFPL PF1 setting for SPI2_MOSI0     \hideinitializer */
+#define SYS_GPF_MFPL_PF1MFP_SPI2_MOSI1      (0x1UL<<SYS_GPF_MFPL_PF1MFP_Pos)           /*!< GPF_MFPL PF1 setting for SPI2_MOSI1     \hideinitializer */
 
 //GPF_MFPL_PF2MFP
 #define SYS_GPF_MFPL_PF2MFP_GPIO            (0x0UL<<SYS_GPF_MFPL_PF2MFP_Pos)           /*!< GPF_MFPL PF2 setting for GPIO     \hideinitializer */
@@ -811,7 +807,7 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
 //GPF_MFPH_PF12MFP
 #define SYS_GPF_MFPH_PF12MFP_GPIO         (0x0UL<<SYS_GPF_MFPH_PF12MFP_Pos)           /*!< GPF_MFPH PF12 setting for GPIO   \hideinitializer */
 #define SYS_GPF_MFPH_PF12MFP_OPA1_IN_P    (0x1UL<<SYS_GPF_MFPH_PF12MFP_Pos)           /*!< GPF_MFPH PF12 setting for OPA1_IN_P   \hideinitializer */
-#define SYS_GPF_MFPH_PF12MFP_UART1_CTS    (0x4UL<<SYS_GPF_MFPH_PF12MFP_Pos)           /*!< GPF_MFPH PF12 setting for UART1_CTS   \hideinitializer */
+#define SYS_GPF_MFPH_PF12MFP_UART1_CTS    (0x2UL<<SYS_GPF_MFPH_PF12MFP_Pos)           /*!< GPF_MFPH PF12 setting for UART1_CTS   \hideinitializer */
 //GPF_MFPH_PF13MFP
 #define SYS_GPF_MFPH_PF13MFP_GPIO         (0x0UL<<SYS_GPF_MFPH_PF13MFP_Pos)           /*!< GPF_MFPH PF13 setting for GPIO   \hideinitializer */
 #define SYS_GPF_MFPH_PF13MFP_OPA1_IN_N    (0x1UL<<SYS_GPF_MFPH_PF13MFP_Pos)            /*!< GPF_MFPH PF13 setting for OPA1_IN_N  \hideinitializer */
@@ -901,13 +897,13 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
 
 //GPG_MFPH_PG14MFP
 #define SYS_GPG_MFPH_PG14MFP_GPIO         (0x0UL<<SYS_GPG_MFPH_PG14MFP_Pos)           /*!< GPG_MFPH PG14 setting for GPIO   \hideinitializer */
-#define SYS_GPG_MFPH_PG14MFP_X32K_IN      (0x1UL<<SYS_GPG_MFPH_PG14MFP_Pos)           /*!< GPG_MFPH PG14 setting for X32K_IN   \hideinitializer */
-#define SYS_GPG_MFPH_PG14MFP_I2C1_SCL     (0x3UL<<SYS_GPG_MFPH_PG14MFP_Pos)           /*!< GPG_MFPH PG14 setting for I2C1_SCL   \hideinitializer */
+#define SYS_GPG_MFPH_PG14MFP_X32K_OUT     (0x1UL<<SYS_GPG_MFPH_PG14MFP_Pos)           /*!< GPG_MFPH PG14 setting for X32K_OUT   \hideinitializer */
+#define SYS_GPG_MFPH_PG14MFP_I2C1_SDA     (0x3UL<<SYS_GPG_MFPH_PG14MFP_Pos)           /*!< GPG_MFPH PG14 setting for I2C1_SDA   \hideinitializer */
 
 //GPG_MFPH_PG15MFP
 #define SYS_GPG_MFPH_PG15MFP_GPIO         (0x0UL<<SYS_GPG_MFPH_PG15MFP_Pos)           /*!< GPG_MFPH PG15 setting for GPIO   \hideinitializer */
-#define SYS_GPG_MFPH_PG15MFP_X32K_OUT     (0x1UL<<SYS_GPG_MFPH_PG15MFP_Pos)           /*!< GPG_MFPH PG15 setting for X32K_OUT   \hideinitializer */
-#define SYS_GPG_MFPH_PG15MFP_I2C1_SDA     (0x3UL<<SYS_GPG_MFPH_PG15MFP_Pos)           /*!< GPG_MFPH PG15 setting for I2C1_SDA   \hideinitializer */
+#define SYS_GPG_MFPH_PG15MFP_X32K_IN      (0x1UL<<SYS_GPG_MFPH_PG15MFP_Pos)           /*!< GPG_MFPH PG15 setting for X32K_IN   \hideinitializer */
+#define SYS_GPG_MFPH_PG15MFP_I2C1_SCL     (0x3UL<<SYS_GPG_MFPH_PG15MFP_Pos)           /*!< GPG_MFPH PG15 setting for I2C1_SCL   \hideinitializer */
 
 
 //GPH_MFPL_PH0MFP
@@ -1019,6 +1015,7 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
 
 //GPI_MFPH_PI9MFP
 #define SYS_GPI_MFPH_PI9MFP_GPIO          (0x0UL<<SYS_GPI_MFPH_PI9MFP_Pos)           /*!< GPI_MFPH PI9 setting for GPIO     \hideinitializer */
+#define SYS_GPI_MFPH_PI9MFP_I2C4_SCL      (0x4UL<<SYS_GPI_MFPH_PI9MFP_Pos)           /*!< GPI_MFPH PI9 setting for I2C4_SCL     \hideinitializer */
 
 //GPI_MFPH_PI10MFP
 #define SYS_GPI_MFPH_PI10MFP_GPIO         (0x0UL<<SYS_GPI_MFPH_PI10MFP_Pos)           /*!< GPI_MFPH PI10 setting for GPIO   \hideinitializer */
@@ -1027,14 +1024,14 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
 #define SYS_GPI_MFPH_PI11MFP_GPIO         (0x0UL<<SYS_GPI_MFPH_PI11MFP_Pos)           /*!< GPI_MFPH PI11 setting for GPIO   \hideinitializer */
 #define SYS_GPI_MFPH_PI11MFP_SPI2_SS0     (0x1UL<<SYS_GPI_MFPH_PI11MFP_Pos)            /*!< GPI_MFPH PI11 setting for SPI2_SS0  \hideinitializer */
 #define SYS_GPI_MFPH_PI11MFP_I2S1_BCLK    (0x2UL<<SYS_GPI_MFPH_PI11MFP_Pos)            /*!< GPI_MFPH PI11 setting for I2S1_BCLK  \hideinitializer */
-#define SYS_GPI_MFPH_PI11MFP_I2S4_SCL     (0x3UL<<SYS_GPI_MFPH_PI11MFP_Pos)            /*!< GPI_MFPH PI11 setting for I2S4_SCL  \hideinitializer */
+#define SYS_GPI_MFPH_PI11MFP_I2C4_SCL     (0x3UL<<SYS_GPI_MFPH_PI11MFP_Pos)            /*!< GPI_MFPH PI11 setting for I2C4_SCL  \hideinitializer */
 #define SYS_GPI_MFPH_PI11MFP_SC3_PWR      (0x4UL<<SYS_GPI_MFPH_PI11MFP_Pos)            /*!< GPI_MFPH PI11 setting for SC3_PWR  \hideinitializer */
 
 //GPI_MFPH_PI12MFP
 #define SYS_GPI_MFPH_PI12MFP_GPIO         (0x0UL<<SYS_GPI_MFPH_PI12MFP_Pos)            /*!< GPI_MFPH PI12 setting for GPIO  \hideinitializer */
 #define SYS_GPI_MFPH_PI12MFP_SPI2_MISO1   (0x1UL<<SYS_GPI_MFPH_PI12MFP_Pos)            /*!< GPI_MFPH PI12 setting for SPI2_MISO1    \hideinitializer */
 #define SYS_GPI_MFPH_PI12MFP_I2S1_LRCK    (0x2UL<<SYS_GPI_MFPH_PI12MFP_Pos)            /*!< GPI_MFPH PI12 setting for I2S1_LRCK     \hideinitializer */
-#define SYS_GPI_MFPH_PI12MFP_I2S4_SDA     (0x3UL<<SYS_GPI_MFPH_PI12MFP_Pos)            /*!< GPI_MFPH PI12 setting for I2S4_SDA  \hideinitializer */
+#define SYS_GPI_MFPH_PI12MFP_I2C4_SDA     (0x3UL<<SYS_GPI_MFPH_PI12MFP_Pos)            /*!< GPI_MFPH PI12 setting for I2C4_SDA  \hideinitializer */
 #define SYS_GPI_MFPH_PI12MFP_SC3_CD       (0x4UL<<SYS_GPI_MFPH_PI12MFP_Pos)            /*!< GPI_MFPH PI12 setting for SC3_CD    \hideinitializer */
 
 //GPI_MFPH_PI13MFP
@@ -1058,7 +1055,7 @@ Example 1: If user want to set PA.0 as SC0_CD in initial function,
   * @return     None
   * @details    This macro clear Brown-out detector interrupt flag.
   */
-#define SYS_CLEAR_BOD_INT_FLAG()        (SYS->BODCTL &= ~SYS_BODCTL_BODINTF_Msk)
+#define SYS_CLEAR_BOD_INT_FLAG()        (SYS->BODCTL |= SYS_BODCTL_BODINTF_Msk)
 
 /**
   * @brief      Set Brown-out detector function to normal mode

From e06a7b2753021bfe9084bc601b365305d921fecc Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Fri, 7 Oct 2016 13:14:12 +0800
Subject: [PATCH 52/89] Move files to match ARM mbed's restructure

1. Move USBHALHost_M451.cpp and USBHALHost_NUC472.cpp.
2. Move TARGET_M451/mbed_lib.json.
3. Move TARGET_NUC472/crypto.
4. Move TARGET_NUC472/mbed_lib.json.
---
 .../unsupported}/USBHost/USBHost/USBHALHost_M451.cpp              | 0
 .../unsupported}/USBHost/USBHost/USBHALHost_NUC472.cpp            | 0
 .../hal => targets}/TARGET_NUVOTON/TARGET_M451/mbed_lib.json      | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c             | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h             | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c             | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h             | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.c             | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h             | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.c          | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.h          | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c            | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h            | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c         | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h         | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c          | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h          | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c       | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h       | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c          | 0
 .../TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h          | 0
 .../hal => targets}/TARGET_NUVOTON/TARGET_NUC472/mbed_lib.json    | 0
 22 files changed, 0 insertions(+), 0 deletions(-)
 rename {libraries => features/unsupported}/USBHost/USBHost/USBHALHost_M451.cpp (100%)
 rename {libraries => features/unsupported}/USBHost/USBHost/USBHALHost_NUC472.cpp (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_M451/mbed_lib.json (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.c (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.c (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.h (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h (100%)
 rename {hal/targets/hal => targets}/TARGET_NUVOTON/TARGET_NUC472/mbed_lib.json (100%)

diff --git a/libraries/USBHost/USBHost/USBHALHost_M451.cpp b/features/unsupported/USBHost/USBHost/USBHALHost_M451.cpp
similarity index 100%
rename from libraries/USBHost/USBHost/USBHALHost_M451.cpp
rename to features/unsupported/USBHost/USBHost/USBHALHost_M451.cpp
diff --git a/libraries/USBHost/USBHost/USBHALHost_NUC472.cpp b/features/unsupported/USBHost/USBHost/USBHALHost_NUC472.cpp
similarity index 100%
rename from libraries/USBHost/USBHost/USBHALHost_NUC472.cpp
rename to features/unsupported/USBHost/USBHost/USBHALHost_NUC472.cpp
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_M451/mbed_lib.json b/targets/TARGET_NUVOTON/TARGET_M451/mbed_lib.json
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_M451/mbed_lib.json
rename to targets/TARGET_NUVOTON/TARGET_M451/mbed_lib.json
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.c
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.c
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.c
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.c
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.c
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.c
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.h
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h
rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h
diff --git a/hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/mbed_lib.json b/targets/TARGET_NUVOTON/TARGET_NUC472/mbed_lib.json
similarity index 100%
rename from hal/targets/hal/TARGET_NUVOTON/TARGET_NUC472/mbed_lib.json
rename to targets/TARGET_NUVOTON/TARGET_NUC472/mbed_lib.json

From 928bdc4ae287c569376937e0b97aeed5ae7024ee Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Fri, 7 Oct 2016 13:43:41 +0800
Subject: [PATCH 53/89] Fix SD pinmaps are not extern'ed

---
 .../TARGET_NUMAKER_PFM_NUC472/PeripheralPins.h           | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.h b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.h
index 5b1a453de9d..104d38ee4fe 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.h
@@ -55,6 +55,15 @@ extern const PinMap PinMap_SPI_MISO[];
 extern const PinMap PinMap_SPI_SCLK[];
 extern const PinMap PinMap_SPI_SSEL[];
 
+//*** SD ***
+extern const PinMap PinMap_SD_CD[];
+extern const PinMap PinMap_SD_CMD[];
+extern const PinMap PinMap_SD_CLK[];
+extern const PinMap PinMap_SD_DAT0[];
+extern const PinMap PinMap_SD_DAT1[];
+extern const PinMap PinMap_SD_DAT2[];
+extern const PinMap PinMap_SD_DAT3[];
+
 #ifdef __cplusplus
 }
 #endif

From 5bb0d4030fd9a948a9c843f917e5137cf4bfaed1 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Fri, 7 Oct 2016 13:46:24 +0800
Subject: [PATCH 54/89] Add device_name into targets.json

---
 targets/targets.json | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/targets/targets.json b/targets/targets.json
index d6a85e24059..0e92aebb436 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -2032,6 +2032,7 @@
         "inherits": ["Target"],
         "progen": {"target": "numaker-pfm-m453"},
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
-        "release_versions": ["2", "5"]
+        "release_versions": ["2", "5"],
+        "device_name": "M453VG6AE"
     }
 }

From 84dbcc540df2753fffbd81de3eda4f7a829c6617 Mon Sep 17 00:00:00 2001
From: ccli8 <ccli8@nuvoton.com>
Date: Tue, 11 Oct 2016 13:49:25 +0800
Subject: [PATCH 55/89] Move files to match ARM mbed's restructure

1. Move M451Series.h to device.
2. Move StdDriver to device.
3. Move TOOLCHAIN_* to device.
4. Move cmsis*, startup_M451Series.c, and system_M451Series.c/h to device.
---
 .../TARGET_M451/device}/M451Series.h                              | 0
 .../TARGET_M451/device}/StdDriver/m451_acmp.c                     | 0
 .../TARGET_M451/device}/StdDriver/m451_acmp.h                     | 0
 .../TARGET_M451/device}/StdDriver/m451_can.c                      | 0
 .../TARGET_M451/device}/StdDriver/m451_can.h                      | 0
 .../TARGET_M451/device}/StdDriver/m451_clk.c                      | 0
 .../TARGET_M451/device}/StdDriver/m451_clk.h                      | 0
 .../TARGET_M451/device}/StdDriver/m451_crc.c                      | 0
 .../TARGET_M451/device}/StdDriver/m451_crc.h                      | 0
 .../TARGET_M451/device}/StdDriver/m451_dac.c                      | 0
 .../TARGET_M451/device}/StdDriver/m451_dac.h                      | 0
 .../TARGET_M451/device}/StdDriver/m451_eadc.c                     | 0
 .../TARGET_M451/device}/StdDriver/m451_eadc.h                     | 0
 .../TARGET_M451/device}/StdDriver/m451_ebi.c                      | 0
 .../TARGET_M451/device}/StdDriver/m451_ebi.h                      | 0
 .../TARGET_M451/device}/StdDriver/m451_fmc.c                      | 0
 .../TARGET_M451/device}/StdDriver/m451_fmc.h                      | 0
 .../TARGET_M451/device}/StdDriver/m451_gpio.c                     | 0
 .../TARGET_M451/device}/StdDriver/m451_gpio.h                     | 0
 .../TARGET_M451/device}/StdDriver/m451_i2c.c                      | 0
 .../TARGET_M451/device}/StdDriver/m451_i2c.h                      | 0
 .../TARGET_M451/device}/StdDriver/m451_otg.h                      | 0
 .../TARGET_M451/device}/StdDriver/m451_pdma.c                     | 0
 .../TARGET_M451/device}/StdDriver/m451_pdma.h                     | 0
 .../TARGET_M451/device}/StdDriver/m451_pwm.c                      | 0
 .../TARGET_M451/device}/StdDriver/m451_pwm.h                      | 0
 .../TARGET_M451/device}/StdDriver/m451_rtc.c                      | 0
 .../TARGET_M451/device}/StdDriver/m451_rtc.h                      | 0
 .../TARGET_M451/device}/StdDriver/m451_sc.c                       | 0
 .../TARGET_M451/device}/StdDriver/m451_sc.h                       | 0
 .../TARGET_M451/device}/StdDriver/m451_scuart.c                   | 0
 .../TARGET_M451/device}/StdDriver/m451_scuart.h                   | 0
 .../TARGET_M451/device}/StdDriver/m451_spi.c                      | 0
 .../TARGET_M451/device}/StdDriver/m451_spi.h                      | 0
 .../TARGET_M451/device}/StdDriver/m451_sys.c                      | 0
 .../TARGET_M451/device}/StdDriver/m451_sys.h                      | 0
 .../TARGET_M451/device}/StdDriver/m451_timer.c                    | 0
 .../TARGET_M451/device}/StdDriver/m451_timer.h                    | 0
 .../TARGET_M451/device}/StdDriver/m451_tk.c                       | 0
 .../TARGET_M451/device}/StdDriver/m451_tk.h                       | 0
 .../TARGET_M451/device}/StdDriver/m451_uart.c                     | 0
 .../TARGET_M451/device}/StdDriver/m451_uart.h                     | 0
 .../TARGET_M451/device}/StdDriver/m451_usbd.c                     | 0
 .../TARGET_M451/device}/StdDriver/m451_usbd.h                     | 0
 .../TARGET_M451/device}/StdDriver/m451_wdt.c                      | 0
 .../TARGET_M451/device}/StdDriver/m451_wdt.h                      | 0
 .../TARGET_M451/device}/StdDriver/m451_wwdt.c                     | 0
 .../TARGET_M451/device}/StdDriver/m451_wwdt.h                     | 0
 .../TARGET_M451/device}/TOOLCHAIN_ARM_MICRO/M453.sct              | 0
 .../TARGET_M451/device}/TOOLCHAIN_ARM_MICRO/sys.cpp               | 0
 .../TARGET_M451/device}/TOOLCHAIN_ARM_STD/M453.sct                | 0
 .../TARGET_M451/device}/TOOLCHAIN_ARM_STD/sys.cpp                 | 0
 .../TARGET_M451/device}/TOOLCHAIN_GCC_ARM/M453.ld                 | 0
 .../TARGET_M451/device}/TOOLCHAIN_GCC_ARM/retarget.c              | 0
 .../TARGET_M451/device}/TOOLCHAIN_IAR/M453.icf                    | 0
 .../TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/cmsis.h     | 0
 .../TARGET_M451/device}/cmsis_nvic.c                              | 0
 .../TARGET_M451/device}/cmsis_nvic.h                              | 0
 .../TARGET_M451/device}/startup_M451Series.c                      | 0
 .../TARGET_M451/device}/system_M451Series.c                       | 0
 .../TARGET_M451/device}/system_M451Series.h                       | 0
 61 files changed, 0 insertions(+), 0 deletions(-)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/M451Series.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_acmp.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_acmp.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_can.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_can.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_clk.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_clk.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_crc.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_crc.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_dac.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_dac.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_eadc.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_eadc.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_ebi.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_ebi.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_fmc.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_fmc.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_gpio.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_gpio.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_i2c.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_i2c.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_otg.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_pdma.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_pdma.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_pwm.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_pwm.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_rtc.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_rtc.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_sc.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_sc.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_scuart.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_scuart.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_spi.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_spi.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_sys.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_sys.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_timer.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_timer.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_tk.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_tk.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_uart.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_uart.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_usbd.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_usbd.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_wdt.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_wdt.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_wwdt.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/StdDriver/m451_wwdt.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453 => TARGET_NUVOTON/TARGET_M451/device}/TOOLCHAIN_ARM_MICRO/M453.sct (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453 => TARGET_NUVOTON/TARGET_M451/device}/TOOLCHAIN_ARM_MICRO/sys.cpp (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453 => TARGET_NUVOTON/TARGET_M451/device}/TOOLCHAIN_ARM_STD/M453.sct (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453 => TARGET_NUVOTON/TARGET_M451/device}/TOOLCHAIN_ARM_STD/sys.cpp (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453 => TARGET_NUVOTON/TARGET_M451/device}/TOOLCHAIN_GCC_ARM/M453.ld (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453 => TARGET_NUVOTON/TARGET_M451/device}/TOOLCHAIN_GCC_ARM/retarget.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453 => TARGET_NUVOTON/TARGET_M451/device}/TOOLCHAIN_IAR/M453.icf (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/cmsis.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/cmsis_nvic.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/cmsis_nvic.h (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453 => TARGET_NUVOTON/TARGET_M451/device}/startup_M451Series.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/system_M451Series.c (100%)
 rename targets/{cmsis/TARGET_NUVOTON/TARGET_M451 => TARGET_NUVOTON/TARGET_M451/device}/system_M451Series.h (100%)

diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/M451Series.h b/targets/TARGET_NUVOTON/TARGET_M451/device/M451Series.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/M451Series.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/M451Series.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_acmp.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_acmp.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_acmp.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_acmp.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_acmp.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_acmp.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_acmp.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_acmp.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_can.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_can.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_can.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_can.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_can.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_can.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_can.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_can.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_clk.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_clk.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_clk.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_clk.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_clk.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_clk.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_clk.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_clk.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_crc.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_crc.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_crc.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_crc.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_crc.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_crc.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_crc.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_crc.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_dac.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_dac.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_dac.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_dac.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_dac.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_dac.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_dac.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_dac.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_eadc.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_eadc.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_eadc.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_eadc.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_eadc.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_eadc.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_eadc.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_eadc.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_ebi.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_ebi.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_ebi.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_ebi.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_ebi.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_ebi.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_ebi.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_ebi.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_fmc.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_fmc.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_fmc.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_fmc.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_fmc.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_fmc.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_fmc.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_fmc.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_gpio.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_gpio.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_gpio.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_gpio.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_gpio.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_gpio.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_gpio.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_gpio.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_i2c.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_i2c.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_i2c.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_i2c.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_i2c.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_i2c.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_i2c.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_i2c.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_otg.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_otg.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_otg.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_otg.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pdma.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pdma.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pdma.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pdma.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pdma.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pdma.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pdma.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pdma.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pwm.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pwm.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pwm.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pwm.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pwm.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pwm.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_pwm.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pwm.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_rtc.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_rtc.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_rtc.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_rtc.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_rtc.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_rtc.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_rtc.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_rtc.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sc.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sc.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sc.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sc.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sc.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sc.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sc.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sc.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_scuart.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_scuart.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_scuart.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_scuart.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_scuart.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_scuart.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_scuart.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_scuart.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_spi.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_spi.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_spi.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_spi.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_spi.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_spi.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_spi.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_spi.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sys.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sys.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sys.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sys.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sys.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sys.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_sys.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sys.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_timer.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_timer.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_timer.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_timer.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_timer.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_timer.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_timer.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_timer.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_tk.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_tk.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_tk.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_tk.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_tk.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_tk.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_tk.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_tk.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_uart.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_uart.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_uart.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_uart.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_uart.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_uart.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_uart.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_uart.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_usbd.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_usbd.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_usbd.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_usbd.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_usbd.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_usbd.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_usbd.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_usbd.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wdt.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_wdt.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wdt.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_wdt.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wdt.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_wdt.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wdt.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_wdt.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wwdt.c b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_wwdt.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wwdt.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_wwdt.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wwdt.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_wwdt.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/StdDriver/m451_wwdt.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_wwdt.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_MICRO/M453.sct b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_MICRO/M453.sct
rename to targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_MICRO/sys.cpp b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/sys.cpp
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_MICRO/sys.cpp
rename to targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/sys.cpp
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_STD/M453.sct b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/M453.sct
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_STD/M453.sct
rename to targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/M453.sct
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/sys.cpp
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_ARM_STD/sys.cpp
rename to targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/sys.cpp
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/M453.ld b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/M453.ld
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/M453.ld
rename to targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/M453.ld
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/retarget.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/retarget.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/retarget.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_IAR/M453.icf b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_IAR/M453.icf
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_IAR/M453.icf
rename to targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_IAR/M453.icf
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis.h b/targets/TARGET_NUVOTON/TARGET_M451/device/cmsis.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/cmsis.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.c b/targets/TARGET_NUVOTON/TARGET_M451/device/cmsis_nvic.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/cmsis_nvic.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.h b/targets/TARGET_NUVOTON/TARGET_M451/device/cmsis_nvic.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/cmsis_nvic.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/cmsis_nvic.h
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/startup_M451Series.c b/targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/startup_M451Series.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/system_M451Series.c b/targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.c
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/system_M451Series.c
rename to targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.c
diff --git a/targets/cmsis/TARGET_NUVOTON/TARGET_M451/system_M451Series.h b/targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.h
similarity index 100%
rename from targets/cmsis/TARGET_NUVOTON/TARGET_M451/system_M451Series.h
rename to targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.h

From 0b2725e7cf7ef180955e4cfbbaeaff58fbeb0393 Mon Sep 17 00:00:00 2001
From: Laurent MEUNIER <laurent.meuniert.com>
Date: Mon, 11 Jul 2016 16:14:03 +0200
Subject: [PATCH 56/89] cmsis to device changes

---
 targets/TARGET_ONSEMI/TARGET_NCS36510/Pad.c   |  24 +--
 .../TARGET_NCS36510/PeripheralPins.c          |  24 ++-
 .../TARGET_ONSEMI/TARGET_NCS36510/PinNames.h  | 106 ++++++-------
 .../TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h   |  20 +--
 .../TARGET_NCS36510/adc_sar_map.h             |  16 +-
 .../TARGET_NCS36510/architecture.h            |  36 ++---
 .../TARGET_NCS36510/assert_onsemi.h           |   8 +-
 .../TARGET_NCS36510/char_driver.h             |   4 +-
 targets/TARGET_ONSEMI/TARGET_NCS36510/clock.h |  68 ++++----
 .../TARGET_ONSEMI/TARGET_NCS36510/clock_map.h |  26 +--
 .../TARGET_ONSEMI/TARGET_NCS36510/crossbar.h  |  16 +-
 .../TARGET_NCS36510/device/NCS36510.h         |  71 +++++----
 .../device/TOOLCHAIN_ARM/startup_NCS36510.s   |  38 ++---
 .../device/TOOLCHAIN_GCC_ARM/NCS36510.ld      |  92 ++++++-----
 .../TOOLCHAIN_GCC_ARM/startup_NCS36510.s      | 140 ++++++++---------
 .../device/TOOLCHAIN_IAR/startup_NCS36510.s   |  50 +++---
 .../TARGET_NCS36510/device/cmsis_nvic.c       |   4 +-
 .../TARGET_NCS36510/device/cmsis_nvic.h       |   2 +-
 .../TARGET_NCS36510/device/system_NCS36510.c  |   9 +-
 .../TARGET_NCS36510/device/system_NCS36510.h  |   8 +-
 .../TARGET_ONSEMI/TARGET_NCS36510/dma_map.h   |  60 +++----
 targets/TARGET_ONSEMI/TARGET_NCS36510/error.h |   2 +-
 .../TARGET_ONSEMI/TARGET_NCS36510/flash_map.h |  10 +-
 targets/TARGET_ONSEMI/TARGET_NCS36510/gpio.h  |  16 +-
 .../TARGET_NCS36510/gpio_irq_api.c            |   4 +-
 .../TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h  |  28 ++--
 targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h   |  80 +++++-----
 .../TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c   |   6 +-
 .../TARGET_NCS36510/i2c_ipc7208_map.h         |   6 +-
 .../TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h |  72 ++++-----
 .../TARGET_NCS36510/memory_map.h              | 148 +++++++++---------
 .../TARGET_NCS36510/ncs36510Init.c            |   8 +-
 .../TARGET_NCS36510/ncs36510_i2c.c            |   4 +-
 .../TARGET_NCS36510/ncs36510_lp_ticker_api.c  |  42 +----
 .../TARGET_NCS36510/ncs36510_spi.c            |  85 +++++-----
 .../TARGET_NCS36510/ncs36510_us_ticker_api.c  |  18 +--
 .../TARGET_ONSEMI/TARGET_NCS36510/objects.h   | 136 ++++++++--------
 .../TARGET_ONSEMI/TARGET_NCS36510/pad_map.h   |  28 ++--
 .../TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h   |  58 +++----
 .../TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h   |   8 +-
 .../TARGET_NCS36510/random_map.h              |  60 +++----
 .../TARGET_ONSEMI/TARGET_NCS36510/reset_map.h |  16 +-
 targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c |  20 +--
 targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h |   4 +-
 targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c   |  38 ++---
 targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.h   |  34 ++--
 .../TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h   |  48 +++---
 .../TARGET_NCS36510/serial_api.c              |  18 +--
 targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c |  16 +-
 targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.h |  20 +--
 .../TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c |  43 ++++-
 targets/TARGET_ONSEMI/TARGET_NCS36510/spi.h   |  32 +++-
 .../TARGET_ONSEMI/TARGET_NCS36510/spi_api.c   |  55 ++++---
 .../TARGET_ONSEMI/TARGET_NCS36510/swversion.c |  12 +-
 targets/TARGET_ONSEMI/TARGET_NCS36510/sys.h   |  18 +--
 .../TARGET_ONSEMI/TARGET_NCS36510/ticker.h    |  40 ++---
 targets/TARGET_ONSEMI/TARGET_NCS36510/timer.h |  68 ++++----
 .../TARGET_ONSEMI/TARGET_NCS36510/timer_map.h |  14 +-
 .../TARGET_ONSEMI/TARGET_NCS36510/trim_map.h  |  54 +++----
 targets/TARGET_ONSEMI/TARGET_NCS36510/types.h |  14 +-
 .../TARGET_NCS36510/uart_16c550.h             |  44 +++---
 .../TARGET_NCS36510/uart_16c550_map.h         |   4 +-
 .../TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h   |  18 +--
 targets/targets.json                          |   2 +-
 64 files changed, 1154 insertions(+), 1119 deletions(-)

diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/Pad.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/Pad.c
index 47e54bbeb5c..9a48bf31698 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/Pad.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/Pad.c
@@ -108,18 +108,18 @@ boolean fPadIOCtrl(uint8_t PadNum, uint8_t OutputDriveStrength, uint8_t OutputDr
 {
     PadReg_t *PadRegOffset;
     /** \verbatim
-    	Table: O/p drive strength
-
-    		Drive strength	3.3V (min/typ/max)	1V (min/typ/max)
-    		000  	 		1/1.4/2.1 mA		0.043/0.07/0.11 mA
-    		001  	 		2/2.7/4.1 mA		0.086/0.15/0.215 mA
-    		010  	 		4.1/5.3/7.8 mA		0.188/0.3/0.4 mA
-    		011  	 		8.1/10.4/15 8 mA	0.4/0.6/0.81 mA
-    		100  	 		20.8/26/37 mA*		1/1.6/2.2 mA
-    		101  	 		40.5/50/70 mA*	    2/3/4.3 mA
-    		11x  	 		57/73/102 mA*   	3/4.6/6.2 mA
-
-    	*Values are only accessible when CDBGPWRUPREQ is high.  This limits the maximum output current in functional mode. \endverbatim */
+        Table: O/p drive strength
+
+            Drive strength    3.3V (min/typ/max)    1V (min/typ/max)
+            000               1/1.4/2.1 mA        0.043/0.07/0.11 mA
+            001               2/2.7/4.1 mA        0.086/0.15/0.215 mA
+            010               4.1/5.3/7.8 mA        0.188/0.3/0.4 mA
+            011               8.1/10.4/15 8 mA    0.4/0.6/0.81 mA
+            100               20.8/26/37 mA*        1/1.6/2.2 mA
+            101               40.5/50/70 mA*        2/3/4.3 mA
+            11x               57/73/102 mA*       3/4.6/6.2 mA
+
+        *Values are only accessible when CDBGPWRUPREQ is high.  This limits the maximum output current in functional mode. \endverbatim */
 
 
     if((PadNum  <= PAD_NUM_OF_IO) &&
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.c
index 5df6553e08d..fa038667056 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.c
@@ -67,31 +67,39 @@ const PinMap PinMap_SPI_SCLK[] = {
     {SPI1_SCLK_2, SPI_0, 6},
     {SPI1_SCLK_3, SPI_0, 6},
     {SPI2_SCLK,   SPI_1, 6},
-    {NC, 		  NC,    0}
+    {NC,          NC,    0}
 };
 
 const PinMap PinMap_SPI_MOSI[] = {
     /*todo: other pins are possible, need to add */
     {SPI1_SDATAO_2, SPI_0, 6},
     {SPI1_SDATAO_3, SPI_0, 6},
-    {SPI2_SDATAO, 	SPI_1, 6},
-    {NC, 			NC,    0}
+    {SPI2_SDATAO,   SPI_1, 6},
+    {NC,            NC,    0}
 };
 
 const PinMap PinMap_SPI_MISO[] = {
     /*todo: other pins are possible, need to add */
     {SPI1_SDATAI_2, SPI_0, 6},
     {SPI1_SDATAI_3, SPI_0, 6},
-    {SPI2_SDATAI, 	SPI_1, 6},
-    {NC, 			NC,    0}
+    {SPI2_SDATAI,   SPI_1, 6},
+    {NC,            NC,    0}
 };
 
 const PinMap PinMap_SPI_SSEL[] = {
     /*todo: other pins are possible, need to add */
     /* TODO what about SSNO */
-    {SPI1_SSNI_2, SPI_0, 6},
-    {SPI2_SSNI,   SPI_1, 6},
-    {NC, 		  NC,    0}
+    {SPI1_SSNO0_1, SPI_0, 6},
+    {SPI1_SSNO1_1, SPI_0, 6},
+    {SPI1_SSNO2_1, SPI_0, 6},
+    {SPI1_SSNO3_1, SPI_0, 6},
+    {SPI1_SSNI_2,  SPI_0, 6},
+    {SPI1_SSNO0_2, SPI_0, 6},
+    {SPI1_SSNO1_2, SPI_0, 6},
+    {SPI1_SSNO2_2, SPI_0, 6},
+    {SPI2_SSNI,    SPI_1, 6},
+    {SPI2_SSNO0,   SPI_1, 6},
+    {NC,           NC,    0}
 };
 
 
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h
index 49536724d84..41b0f6b4f8c 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h
@@ -37,7 +37,7 @@ extern "C" {
 #endif
 
 typedef enum {
-    GPIO0	= 0,
+    GPIO0 = 0,
     GPIO1,
     GPIO2,
     GPIO3,
@@ -64,56 +64,56 @@ typedef enum {
     UART2_TX = GPIO8,
     UART2_RX = GPIO9,
 
-    I2C1_SCLK_1 	= GPIO2,
-    I2C1_SDATA_1 	= GPIO3,
-    I2C1_SCLK_2		= GPIO5,
-    I2C1_SDATA_2 	= GPIO4,
-    I2C1_SCLK 	= I2C1_SCLK_1,  /*Default*/
-    I2C1_SDATA 	= I2C1_SDATA_1,  /*Default*/
-
-    I2C2_SCLK_1 	= GPIO14,
-    I2C2_SDATA_1 	= GPIO15,
-    I2C2_SCLK_2 	= GPIO17,
-    I2C2_SDATA_2 	= GPIO16,
-    I2C2_SCLK 	= I2C2_SCLK_2,  /*Default*/
-    I2C2_SDATA 	= I2C2_SDATA_2,  /*Default*/
-    I2C_SCL 	= I2C1_SCLK_1,  /*Default*/
-    I2C_SDA 	= I2C1_SDATA_1,  /*Default*/
+    I2C1_SCLK_1    = GPIO2,
+    I2C1_SDATA_1   = GPIO3,
+    I2C1_SCLK_2    = GPIO5,
+    I2C1_SDATA_2   = GPIO4,
+    I2C1_SCLK      = I2C1_SCLK_1,   /*Default*/
+    I2C1_SDATA     = I2C1_SDATA_1,  /*Default*/
+
+    I2C2_SCLK_1    = GPIO14,
+    I2C2_SDATA_1   = GPIO15,
+    I2C2_SCLK_2    = GPIO17,
+    I2C2_SDATA_2   = GPIO16,
+    I2C2_SCLK      = I2C2_SCLK_2,  /*Default*/
+    I2C2_SDATA     = I2C2_SDATA_2, /*Default*/
+    I2C_SCL        = I2C1_SCLK_1,  /*Default*/
+    I2C_SDA        = I2C1_SDATA_1, /*Default*/
 
     /* SPI 1 with 1st set of CROSS BAR */
-    SPI1_SSNO0_1	= GPIO0,
-    SPI1_SSNO1_1	= GPIO1,
-    SPI1_SSNO2_1	= GPIO2,
-    SPI1_SSNO3_1	= GPIO3,
+    SPI1_SSNO0_1    = GPIO0,
+    SPI1_SSNO1_1    = GPIO1,
+    SPI1_SSNO2_1    = GPIO2,
+    SPI1_SSNO3_1    = GPIO3,
 
     /* SPI 1 with 2st set of CROSS BAR */
-    SPI1_SCLK_2 	= GPIO4,
-    SPI1_SDATAO_2	= GPIO5,
-    SPI1_SDATAI_2 	= GPIO6,
-    SPI1_SSNI_2 	= GPIO7,
-    SPI1_SSNO0_2 	= GPIO8,
-    SPI1_SSNO1_2 	= GPIO9,
-    SPI1_SSNO2_2 	= GPIO10,
-
-    SPI1_SCLK 	= SPI1_SCLK_2,  /*Default*/
-    SPI1_SDATAO	= SPI1_SDATAO_2, /*Default*/
-    SPI1_SDATAI 	= SPI1_SDATAI_2,  /*Default*/
-    SPI1_SSNI 	= SPI1_SSNI_2,  /*Default*/
-    SPI1_SSNO0 	= SPI1_SSNO0_2,  /*Default*/
-    SPI1_SSNO1 	= SPI1_SSNO1_2,  /*Default*/
-    SPI1_SSNO2 	= SPI1_SSNO2_2,  /*Default*/
+    SPI1_SCLK_2      = GPIO4,
+    SPI1_SDATAO_2    = GPIO5,
+    SPI1_SDATAI_2    = GPIO6,
+    SPI1_SSNI_2      = GPIO7,
+    SPI1_SSNO0_2     = GPIO8,
+    SPI1_SSNO1_2     = GPIO9,
+    SPI1_SSNO2_2     = GPIO10,
+
+    SPI1_SCLK    = SPI1_SCLK_2,   /*Default*/
+    SPI1_SDATAO  = SPI1_SDATAO_2, /*Default*/
+    SPI1_SDATAI  = SPI1_SDATAI_2, /*Default*/
+    SPI1_SSNI    = SPI1_SSNI_2,   /*Default*/
+    SPI1_SSNO0   = SPI1_SSNO0_2,  /*Default*/
+    SPI1_SSNO1   = SPI1_SSNO1_2,  /*Default*/
+    SPI1_SSNO2   = SPI1_SSNO2_2,  /*Default*/
 
     /* SPI 1 with 3rd set of CROSS BAR */
-    SPI1_SCLK_3 	= GPIO8,
-    SPI1_SDATAO_3	= GPIO9,
-    SPI1_SDATAI_3 	= GPIO10,
+    SPI1_SCLK_3     = GPIO8,
+    SPI1_SDATAO_3   = GPIO9,
+    SPI1_SDATAI_3   = GPIO10,
 
     /* SPI 2 */
-    SPI2_SCLK 	= GPIO14,
-    SPI2_SDATAO = GPIO15,
-    SPI2_SDATAI = GPIO16,
-    SPI2_SSNI 	= GPIO17,
-    SPI2_SSNO0 	= GPIO17,
+    SPI2_SCLK     = GPIO14,
+    SPI2_SDATAO   = GPIO15,
+    SPI2_SDATAI   = GPIO16,
+    SPI2_SSNI     = GPIO17,
+    SPI2_SSNO0    = GPIO17,
 
     // Generic signals namings
     LED1        = GPIO4,
@@ -157,17 +157,17 @@ typedef enum {
 } PinDirection;
 
 typedef enum {
-    PushPullPullDown = 0,
-    PushPullNoPull = 1,
-    PushPullPullUp = 2,
+    PushPullPullDown  = 0,
+    PushPullNoPull    = 1,
+    PushPullPullUp    = 2,
     OpenDrainPullDown = 3,
-    OpenDrainNoPull = 4,
-    OpenDrainPullUp = 5,
-    PullNone  = PushPullNoPull,
-    PullUp    = PushPullPullUp,
-    PullDown  = PushPullPullDown,
-    OpenDrain = OpenDrainPullUp,
-    PullDefault = PullNone
+    OpenDrainNoPull   = 4,
+    OpenDrainPullUp   = 5,
+    PullNone          = PushPullNoPull,
+    PullUp            = PushPullPullUp,
+    PullDown          = PushPullPullDown,
+    OpenDrain         = OpenDrainPullUp,
+    PullDefault       = PullNone
 
 } PinMode;
 
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h
index 0f6cfc5bfa7..98279357ef0 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h
@@ -43,16 +43,16 @@ extern "C" {
 #endif
 
 /* ADC register bits */
-#define ADC_CONTROL_MODE_BIT_POS		0
-#define ADC_CONTROL_MEASTYPE_BIT_POS	3
-#define ADC_CONTROL_INPUTSCALE_BIT_POS	4
-#define ADC_CONTROL_MEAS_CH_BIT_POS		8
-#define ADC_CONTROL_REF_CH_BIT_POS		12
-#define ADC_PRESCALE_VAL_BIT_POS		0
-#define ADC_PRESCALE_EN_BIT_POS			8
-#define ADC_DELAY_SAMPLE_RATE_BIT_POS	0
-#define ADC_DELAY_WARMUP_BIT_POS		16
-#define ADC_DELAY_SAMPLE_TIME_BIT_POS	24
+#define ADC_CONTROL_MODE_BIT_POS        0
+#define ADC_CONTROL_MEASTYPE_BIT_POS    3
+#define ADC_CONTROL_INPUTSCALE_BIT_POS  4
+#define ADC_CONTROL_MEAS_CH_BIT_POS     8
+#define ADC_CONTROL_REF_CH_BIT_POS      12
+#define ADC_PRESCALE_VAL_BIT_POS        0
+#define ADC_PRESCALE_EN_BIT_POS         8
+#define ADC_DELAY_SAMPLE_RATE_BIT_POS   0
+#define ADC_DELAY_WARMUP_BIT_POS        16
+#define ADC_DELAY_SAMPLE_TIME_BIT_POS   24
 
 typedef enum {
     ADC_CHANNEL0 = 0,
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h
index 95dc35b4d54..cb5793d4831 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h
@@ -45,13 +45,13 @@ typedef struct {
         struct {
             __IO uint32_t MODE :1;             /** 1= Continuous Conversion 0= Single Shot  */
             __IO uint32_t START_CONV :1;       /** 1= Start Conversion 0= No effect*/
-            __IO uint32_t ABORT :1;			   /** 1= Aborts the Continuous Conversion mode 0=No effect */
+            __IO uint32_t ABORT :1;            /** 1= Aborts the Continuous Conversion mode 0=No effect */
             __IO uint32_t MEASUREMENT_TYPE :1; /** 1= Absolute 0= Differential */
             __IO uint32_t INPUT_SCALE :3;      /** 000 � 1.0     001 � 0.6923 010 � 0.5294 011 � 0.4286 100 � 0.3600 101 � 0.3103  110 � 0.2728 111 � 0.2432 */
-            __I  uint32_t BIT7:1;			   /** NA Always read backs 0*/
-            __IO uint32_t CONV_CH :3;		   /** Selects 1 or 8 channels to do a conversion on. 000 � A[0] 000 � A[1] 010 � A[2] 011 � A[3] 100 � N/A 101 � N/A 110 � Temperature sensor      111 � Battery  */
-            __I uint32_t  NA :1;			   /** NA */
-            __IO uint32_t REF_CH :3;		   /** Selects 1 to 8 channels for reference channel  000 � A[0]  000 � A[1]   010 � A[2]  011 � A[3]  100 � N/A  101 � N/A 110 � Temperature sensor  111 � Battery */
+            __I  uint32_t BIT7:1;              /** NA Always read backs 0*/
+            __IO uint32_t CONV_CH :3;          /** Selects 1 or 8 channels to do a conversion on. 000 � A[0] 000 � A[1] 010 � A[2] 011 � A[3] 100 � N/A 101 � N/A 110 � Temperature sensor      111 � Battery  */
+            __I uint32_t  NA :1;               /** NA */
+            __IO uint32_t REF_CH :3;           /** Selects 1 to 8 channels for reference channel  000 � A[0]  000 � A[1]   010 � A[2]  011 � A[3]  100 � N/A  101 � N/A 110 � Temperature sensor  111 � Battery */
         } BITS;
         __IO uint32_t WORD;
     } CONTROL;
@@ -67,9 +67,9 @@ typedef struct {
     __IO uint32_t IR;
     union {
         struct {
-            __IO uint32_t PRESC_VAL  :8; /**Set the pre-scalar value. The SAR ADC nominally runs at 4MHz, so this value should be programmed to 32 Mhz/4mhz -1=7 */
-            __IO uint32_t PRESC_EN   :1; /** 1= enables PreScalar 0= Disable Prescalar */
-//			__IO uint32_t PHASE_CTRL :1; /** 1 = Phase 2 is delayed two 32MHz clock from phase 1. 0= Phase 2 is delayed one 32MHz clock from phase 1. */
+            __IO uint32_t PRESC_VAL  :8;   /**Set the pre-scalar value. The SAR ADC nominally runs at 4MHz, so this value should be programmed to 32 Mhz/4mhz -1=7 */
+            __IO uint32_t PRESC_EN   :1;   /** 1= enables PreScalar 0= Disable Prescalar */
+//            __IO uint32_t PHASE_CTRL :1; /** 1 = Phase 2 is delayed two 32MHz clock from phase 1. 0= Phase 2 is delayed one 32MHz clock from phase 1. */
         } BITS;
         __IO uint32_t WORD;
     } PRESCALE;
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/architecture.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/architecture.h
index 4306b8ed6ca..69652af0ee6 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/architecture.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/architecture.h
@@ -53,24 +53,24 @@
 *************************************************************************************************/
 
 /* Interrupt Control and State Register (0xE000ED04)
- * 31 		NMIPENDSET 			R/W 	0 		NMI pended
- * 28 		PENDSVSET 			R/W 	0 		Write 1 to pend system call; Read value
- * 												indicates pending status
- * 27 		PENDSVCLR 			W 		0 		Write 1 to clear PendSV pending status
- * 26 		PENDSTSET 			R/W 	0 		Write 1 to pend Systick exception; Read
- *												value indicates pending status
- * 25 		PENDSTCLR 			W 		0 		Write 1 to clear Systick pending status
- * 23 		ISRPREEMPT 			R 		0 		Indicate that a pending interrupt is going
- *												to be active in next step (for debug)
- * 22 		ISRPENDING 			R 		0 		External interrupt pending (excluding
- *												system exceptions such as NMI for
- *												fault)
- * 21:12 	VECTPENDING 		R 		0 		Pending ISR number
- * 11 		RETTOBASE 			R 		0 		Set to 1 when the processor is running
- * 												an exception handler and will return to
- *												thread level if interrupt return and no
- *												other exceptions pending
- * 9:0 		VECTACTIVE 			R 		0 		Current running interrupt service routine
+ * 31         NMIPENDSET            R/W     0     NMI pended
+ * 28         PENDSVSET             R/W     0     Write 1 to pend system call; Read value
+ *                                                indicates pending status
+ * 27         PENDSVCLR             W       0     Write 1 to clear PendSV pending status
+ * 26         PENDSTSET             R/W     0     Write 1 to pend Systick exception; Read
+ *                                                value indicates pending status
+ * 25         PENDSTCLR             W       0     Write 1 to clear Systick pending status
+ * 23         ISRPREEMPT            R       0     Indicate that a pending interrupt is going
+ *                                                to be active in next step (for debug)
+ * 22         ISRPENDING            R       0     External interrupt pending (excluding
+ *                                                system exceptions such as NMI for
+ *                                                fault)
+ * 21:12     VECTPENDING            R       0     Pending ISR number
+ * 11         RETTOBASE             R       0     Set to 1 when the processor is running
+ *                                                an exception handler and will return to
+ *                                                thread level if interrupt return and no
+ *                                                other exceptions pending
+ * 9:0         VECTACTIVE           R       0     Current running interrupt service routine
  */
 #define RUNNING_IN_ISR  (((SCB->ICSR & 0x3FF) > 0 ) ? 1 : 0)
 
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h
index 01ae0924240..b78089330ea 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h
@@ -55,15 +55,15 @@ void fOnAssert(const char *filename, unsigned int line);
 /** Can be assigned to hook into the assertion. */
 extern void (*assertCallback)(const char *filename, unsigned int line);
 
-#define ASSERT(test)		((test) ? (void)0 : fOnAssert(__FILE__, __LINE__))
+#define ASSERT(test)        ((test) ? (void)0 : fOnAssert(__FILE__, __LINE__))
 
-#define VERIFY(test)		ASSERT(test)
+#define VERIFY(test)        ASSERT(test)
 
 #else
 
-#define ASSERT(test)		((test) ? (void)0 : 1)
+#define ASSERT(test)        ((test) ? (void)0 : 1)
 
-#define VERIFY(test)		((void)(test))
+#define VERIFY(test)        ((void)(test))
 
 #endif // DEBUG
 
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h
index bbb160635b6..0f6ab4489dd 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h
@@ -42,8 +42,8 @@
 
 #include "driver.h"
 
-#define DRV_NO_ERROR			(True)
-#define DRV_ERROR				(False)
+#define DRV_NO_ERROR       (True)
+#define DRV_ERROR          (False)
 
 /** A character driver structure. */
 typedef struct char_driver {
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/clock.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/clock.h
index 30f5f77b388..5126a7cd955 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/clock.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/clock.h
@@ -47,41 +47,41 @@
 /** Peripherals clock disable defines  /
  * @details
  */
-#define CLOCK_TIMER0	        (0x0)  /**< <b> Timer 0 clock enable offset </b>*/
-#define CLOCK_TIMER1	        (0x1)  /**< <b> Timer 1 clock enable offset </b>: */
-#define CLOCK_TIMER2	        (0x2)  /**< <b> Timer 2 clock enable offset </b>: */
-#define CLOCK_PAD0_0	        (0x3)  /**< <b> Unused offset </b> */
-#define CLOCK_PAD0_1	        (0x4)  /**< <b> Unused offset </b> */
-#define CLOCK_UART1				(0x5)  /**< <b> UART 1 clock enable offset </b> */
-#define CLOCK_SPI				(0x6)  /**< <b> SPI clock enable offset </b> */
-#define CLOCK_I2C				(0x7)  /**< <b> I2C clock enable offset </b> */
-#define CLOCK_UART2				(0x8)  /**< <b> UART 2 clock enable offset </b> */
-#define CLOCK_SPI2	        	(0x9)  /**< <b> Unused offset </b>: */
-#define CLOCK_WDOG				(0xA)  /**< <b> Watchdog clock enable offset </b> */
-#define CLOCK_PWM				(0xB)  /**< <b> PWM clock enable offset </b> */
-#define CLOCK_GPIO				(0xC)  /**< <b> GPIO clock enable offset </b> */
-#define CLOCK_I2C2	        	(0xD)  /**< <b> Unused offset </b> */
-#define CLOCK_PAD2_1	        (0xE)  /**< <b> Unused offset </b> */
-#define CLOCK_RTC				(0xF)  /**< <b> RTC clock enable offset </b> */
-#define CLOCK_CROSSB	        (0x10) /**< <b> Crossbar clock enable offset </b> */
-#define CLOCK_RAND				(0x11) /**< <b> Randomizer clock enable offset </b> */
-#define CLOCK_PAD3_0	        (0x12) /**< <b> Unused offset </b> */
-#define CLOCK_PAD3_1	        (0x13) /**< <b> Unused offset </b> */
-#define CLOCK_MACHW				(0x14) /**< <b> macHw clock enable offset </b> */
-#define CLOCK_ADC				(0x15) /**< <b> ADC clock enable offset </b> */
-#define CLOCK_AES				(0x16) /**< <b> AES clock enable offset </b> */
-#define CLOCK_FLASH				(0x17) /**< <b> Flash controller clock enable offset</b> */
-#define CLOCK_PAD4_0	        (0x18) /**< <b> Unused offset </b> */
-#define CLOCK_RFANA				(0x19) /**< <b> rfAna clock enable offset </b> */
-#define CLOCK_IO				(0x1A) /**< <b> IO clock enable offset </b> */
-#define CLOCK_PAD5_0	        (0x1B) /**< <b> Unused offset </b> */
-#define CLOCK_PAD				(0x1C) /**< <b> Pad clock enable offset </b> */
-#define CLOCK_PMU				(0x1D) /**< <b> Pmu clock enable offset </b> */
-#define CLOCK_DMA	        	(0x1E) /**< <b> DMA clock enable offset </b> */
-#define CLOCK_TEST				(0x1F) /**< <b> Test controller clock enable offset </b> */
+#define CLOCK_TIMER0            (0x0)  /**< <b> Timer 0 clock enable offset </b>*/
+#define CLOCK_TIMER1            (0x1)  /**< <b> Timer 1 clock enable offset </b>: */
+#define CLOCK_TIMER2            (0x2)  /**< <b> Timer 2 clock enable offset </b>: */
+#define CLOCK_PAD0_0            (0x3)  /**< <b> Unused offset </b> */
+#define CLOCK_PAD0_1            (0x4)  /**< <b> Unused offset </b> */
+#define CLOCK_UART1             (0x5)  /**< <b> UART 1 clock enable offset </b> */
+#define CLOCK_SPI               (0x6)  /**< <b> SPI clock enable offset </b> */
+#define CLOCK_I2C               (0x7)  /**< <b> I2C clock enable offset </b> */
+#define CLOCK_UART2             (0x8)  /**< <b> UART 2 clock enable offset </b> */
+#define CLOCK_SPI2              (0x9)  /**< <b> Unused offset </b>: */
+#define CLOCK_WDOG              (0xA)  /**< <b> Watchdog clock enable offset </b> */
+#define CLOCK_PWM               (0xB)  /**< <b> PWM clock enable offset </b> */
+#define CLOCK_GPIO              (0xC)  /**< <b> GPIO clock enable offset </b> */
+#define CLOCK_I2C2              (0xD)  /**< <b> Unused offset </b> */
+#define CLOCK_PAD2_1            (0xE)  /**< <b> Unused offset </b> */
+#define CLOCK_RTC               (0xF)  /**< <b> RTC clock enable offset </b> */
+#define CLOCK_CROSSB            (0x10) /**< <b> Crossbar clock enable offset </b> */
+#define CLOCK_RAND              (0x11) /**< <b> Randomizer clock enable offset </b> */
+#define CLOCK_PAD3_0            (0x12) /**< <b> Unused offset </b> */
+#define CLOCK_PAD3_1            (0x13) /**< <b> Unused offset </b> */
+#define CLOCK_MACHW             (0x14) /**< <b> macHw clock enable offset </b> */
+#define CLOCK_ADC               (0x15) /**< <b> ADC clock enable offset </b> */
+#define CLOCK_AES               (0x16) /**< <b> AES clock enable offset </b> */
+#define CLOCK_FLASH             (0x17) /**< <b> Flash controller clock enable offset</b> */
+#define CLOCK_PAD4_0            (0x18) /**< <b> Unused offset </b> */
+#define CLOCK_RFANA             (0x19) /**< <b> rfAna clock enable offset </b> */
+#define CLOCK_IO                (0x1A) /**< <b> IO clock enable offset </b> */
+#define CLOCK_PAD5_0            (0x1B) /**< <b> Unused offset </b> */
+#define CLOCK_PAD               (0x1C) /**< <b> Pad clock enable offset </b> */
+#define CLOCK_PMU               (0x1D) /**< <b> Pmu clock enable offset </b> */
+#define CLOCK_DMA               (0x1E) /**< <b> DMA clock enable offset </b> */
+#define CLOCK_TEST              (0x1F) /**< <b> Test controller clock enable offset </b> */
 
-#define CLOCK_ENABLE(a)		CLOCKREG->PDIS.WORD &= ~(1 << a)
-#define CLOCK_DISABLE(a)	CLOCKREG->PDIS.WORD |= (uint32_t)(1 << a)
+#define CLOCK_ENABLE(a)         CLOCKREG->PDIS.WORD &= ~(1 << a)
+#define CLOCK_DISABLE(a)        CLOCKREG->PDIS.WORD |= (uint32_t)(1 << a)
 
 /*************************************************************************************************
 *                                                                                                *
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h
index dfc7056463f..e27d67d9d38 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h
@@ -57,7 +57,7 @@ typedef struct {
             __IO uint32_t RTCEN:1;
         } BITS;
         __IO uint32_t WORD;
-    } CCR; 													/**< 0x4001B000 Clock control register */
+    } CCR;                                                  /**< 0x4001B000 Clock control register */
     union {
         struct {
             __I uint32_t XTAL32M:1;
@@ -68,15 +68,15 @@ typedef struct {
             __I uint32_t CAL32MDONE:1;
         } BITS;
         __I uint32_t WORD;
-    } CSR; 													/**< 0x4001B004 Clock status register */
+    } CSR;                                                  /**< 0x4001B004 Clock status register */
     union {
         struct {
             __IO uint32_t IE32K:1;
             __IO uint32_t IE32M:1;
         } BITS;
         __IO uint32_t WORD;
-    } IER;													/**< 0x4001B008 Interrup enable register */
-    __IO uint32_t ICR; 										/**< 0x4001B00C Interrupt clear register */
+    } IER;                                                  /**< 0x4001B008 Interrup enable register */
+    __IO uint32_t ICR;                                      /**< 0x4001B00C Interrupt clear register */
     union {
         struct {
             __IO uint32_t TIMER0:1;
@@ -110,14 +110,14 @@ typedef struct {
             __IO uint32_t TEST:1;
         } BITS;
         __IO uint32_t WORD;
-    } PDIS; 												/**< 0x4001B010 Periphery disable */
-    __IO uint32_t FDIV; 									/**< 0x4001B014 FCLK divider */
-    __IO uint32_t TDIV; 									/**< 0x4001B01C Traceclk divider */
-    __IO uint32_t WDIV; 									/**< 0x4001B020 Watchdog clock divider */
-    __IO uint32_t TRIM_32M_INT; 							/**< 0x4001B024 32Mhz internal trim */
-    __IO uint32_t TRIM_32K_INT; 							/**< 0x4001B02C 32kHz internal trim */
-    __IO uint32_t TRIM_32M_EXT; 							/**< 0x4001B030 32Mhz external trim */
-    __IO uint32_t TRIM_32K_EXT; 							/**< 0x4001B034 32Khz external trim */
+    } PDIS;                                                 /**< 0x4001B010 Periphery disable */
+    __IO uint32_t FDIV;                                     /**< 0x4001B014 FCLK divider */
+    __IO uint32_t TDIV;                                     /**< 0x4001B01C Traceclk divider */
+    __IO uint32_t WDIV;                                     /**< 0x4001B020 Watchdog clock divider */
+    __IO uint32_t TRIM_32M_INT;                             /**< 0x4001B024 32Mhz internal trim */
+    __IO uint32_t TRIM_32K_INT;                             /**< 0x4001B02C 32kHz internal trim */
+    __IO uint32_t TRIM_32M_EXT;                             /**< 0x4001B030 32Mhz external trim */
+    __IO uint32_t TRIM_32K_EXT;                             /**< 0x4001B034 32Khz external trim */
     union {
         struct {
             __IO uint32_t OV32M;
@@ -126,7 +126,7 @@ typedef struct {
             __IO uint32_t EN32K;
         } BITS;
         __IO uint32_t WORD;
-    } CER; 													/**< 0x4001B038 clock enable register*/
+    } CER;                                                  /**< 0x4001B038 clock enable register*/
 } ClockReg_t, *ClockReg_pt;
 
 #endif /* CLOCK_MAP_H_ */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h
index e7347c39d4d..127944dd99e 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h
@@ -39,13 +39,13 @@
 *                                                                                                *
 *************************************************************************************************/
 
-#define CONFIGURE_AS_GPIO		(uint8_t)0x00
-#define CONFIGURE_AS_RESERVED_0	(uint8_t)0x01
-#define CONFIGURE_AS_RESERVED_1	(uint8_t)0x02
-#define CONFIGURE_AS_RESERVED_2	(uint8_t)0x03
-#define CONFIGURE_AS_PWM		(uint8_t)0x04
-#define CONFIGURE_AS_I2C		(uint8_t)0x05
-#define CONFIGURE_AS_SPI		(uint8_t)0x06
-#define CONFIGURE_AS_UART		(uint8_t)0x07
+#define CONFIGURE_AS_GPIO        (uint8_t)0x00
+#define CONFIGURE_AS_RESERVED_0  (uint8_t)0x01
+#define CONFIGURE_AS_RESERVED_1  (uint8_t)0x02
+#define CONFIGURE_AS_RESERVED_2  (uint8_t)0x03
+#define CONFIGURE_AS_PWM         (uint8_t)0x04
+#define CONFIGURE_AS_I2C         (uint8_t)0x05
+#define CONFIGURE_AS_SPI         (uint8_t)0x06
+#define CONFIGURE_AS_UART        (uint8_t)0x07
 
 #endif //_CROSSBAR_H_
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/NCS36510.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/NCS36510.h
index 15c5e94967a..ebe988add05 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/NCS36510.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/NCS36510.h
@@ -31,40 +31,39 @@
  * ---------- Interrupt Number Definition -----------------------------------
  * ==========================================================================
  */
-typedef enum IRQn
-{
-	/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
-	NonMaskableInt_IRQn 	= -14, 		/*!<  2 Cortex-M3 Non Maskable Interrupt                  */
-	HardFault_IRQn 			= -13, 		/*!<  3 Cortex-M3 Hard Fault Interrupt                    */
-	MemoryManagement_IRQn 	= -12, 		/*!<  4 Cortex-M3 Memory Management Interrupt             */
-	BusFault_IRQn 			= -11,		/*!<  5 Cortex-M3 Bus Fault Interrupt                     */
-	UsageFault_IRQn 		= -10, 		/*!<  6 Cortex-M3 Usage Fault Interrupt                   */
-	SVCall_IRQn 			= -5, 		/*!< 11 Cortex-M3 SV Call Interrupt                       */
-	DebugMonitor_IRQn 		= -4, 		/*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
-	PendSV_IRQn 			= -2, 		/*!< 14 Cortex-M3 Pend SV Interrupt                       */
-	SysTick_IRQn			= -1, 		/*!< 15 Cortex-M3 System Tick Interrupt                   */
+typedef enum IRQn {
+    /******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
+    NonMaskableInt_IRQn     = -14,        /*!<  2 Cortex-M3 Non Maskable Interrupt          */
+    HardFault_IRQn          = -13,        /*!<  3 Cortex-M3 Hard Fault Interrupt            */
+    MemoryManagement_IRQn   = -12,        /*!<  4 Cortex-M3 Memory Management Interrupt     */
+    BusFault_IRQn           = -11,        /*!<  5 Cortex-M3 Bus Fault Interrupt             */
+    UsageFault_IRQn         = -10,        /*!<  6 Cortex-M3 Usage Fault Interrupt           */
+    SVCall_IRQn             = -5,         /*!< 11 Cortex-M3 SV Call Interrupt               */
+    DebugMonitor_IRQn       = -4,         /*!< 12 Cortex-M3 Debug Monitor Interrupt         */
+    PendSV_IRQn             = -2,         /*!< 14 Cortex-M3 Pend SV Interrupt               */
+    SysTick_IRQn            = -1,         /*!< 15 Cortex-M3 System Tick Interrupt           */
 
-	/******  ARMCM3 specific Interrupt Numbers ********************************************************/
-	Tim0_IRQn 				= 0,
-	Tim1_IRQn 				= 1,
-	Tim2_IRQn 				= 2,
-	Uart1_IRQn 				= 3,
-	Spi_IRQn 				= 4,
-	I2C_IRQn 				= 5,
-	Gpio_IRQn 				= 6,
-	Rtc_IRQn 				= 7,
-	Flash_IRQn 				= 8,
-	MacHw_IRQn 				= 9,
-	Aes_IRQn 				= 10,
-	Adc_IRQn 				= 11,
-	ClockCal_IRQn 			= 12,
-	Uart2_IRQn 				= 13,
-	Uvi_IRQn				= 14,
-	Dma_IRQn 				= 15,
-	DbgPwrUp_IRQn 			= 16,
-	Spi2_IRQn 				= 17,
-	I2C2_IRQn 				= 18,
-	FVDDHComp_IRQn			= 19
+    /******  ARMCM3 specific Interrupt Numbers ********************************************************/
+    Tim0_IRQn               = 0,
+    Tim1_IRQn               = 1,
+    Tim2_IRQn               = 2,
+    Uart1_IRQn              = 3,
+    Spi_IRQn                = 4,
+    I2C_IRQn                = 5,
+    Gpio_IRQn               = 6,
+    Rtc_IRQn                = 7,
+    Flash_IRQn              = 8,
+    MacHw_IRQn              = 9,
+    Aes_IRQn                = 10,
+    Adc_IRQn                = 11,
+    ClockCal_IRQn           = 12,
+    Uart2_IRQn              = 13,
+    Uvi_IRQn                = 14,
+    Dma_IRQn                = 15,
+    DbgPwrUp_IRQn           = 16,
+    Spi2_IRQn               = 17,
+    I2C2_IRQn               = 18,
+    FVDDHComp_IRQn          = 19
 } IRQn_Type;
 
 /**
@@ -79,12 +78,12 @@ typedef enum IRQn
 #define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels          */
 #define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
 
-//#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_OFFSET	16
-//#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_NUMBER	20
+//#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_OFFSET    16
+//#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_NUMBER    20
 //#define NVIC_NUM_VECTORS     (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
 
 //#define YOTTA_CFG_CMSIS_NVIC_RAM_VECTOR_ADDRESS
-//#define YOTTA_CFG_CMSIS_NVIC_FLASH_VECTOR_ADDRESS	0x3000
+//#define YOTTA_CFG_CMSIS_NVIC_FLASH_VECTOR_ADDRESS    0x3000
 
 #include <core_cm3.h>                       /* Cortex-M3 processor and core peripherals           */
 #include "system_NCS36510.h"                  /* System Header                                      */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.s b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.s
index 8c47404d0c5..7478b2c3a96 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.s
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.s
@@ -64,25 +64,25 @@ __Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit|  ; Top of Stack
 
                 ; External Interrupts
                 DCD     fIrqTim0Handler
-              	DCD     fIrqTim1Handler
-              	DCD     fIrqTim2Handler
-              	DCD     fIrqUart1Handler
-              	DCD     fIrqSpiHandler
-              	DCD     fIrqI2CHandler
-              	DCD     fIrqGpioHandler
-              	DCD     fIrqRtcHandler
-              	DCD     fIrqFlashHandler
-              	DCD     fIrqMacHwHandler
-              	DCD     fIrqAesHandler
-              	DCD     fIrqAdcHandler
-              	DCD     fIrqClockCalHandler
-              	DCD     fIrqUart2Handler
-              	DCD     fIrqUviHandler
-              	DCD     fIrqDmaHandler
-               	DCD     fIrqDbgPwrUpHandler
-               	DCD     fIrqSpi2Handler
-               	DCD     fIrqI2C2Handler
-               	DCD     fIrqFVDDHCompHandler
+                DCD     fIrqTim1Handler
+                DCD     fIrqTim2Handler
+                DCD     fIrqUart1Handler
+                DCD     fIrqSpiHandler
+                DCD     fIrqI2CHandler
+                DCD     fIrqGpioHandler
+                DCD     fIrqRtcHandler
+                DCD     fIrqFlashHandler
+                DCD     fIrqMacHwHandler
+                DCD     fIrqAesHandler
+                DCD     fIrqAdcHandler
+                DCD     fIrqClockCalHandler
+                DCD     fIrqUart2Handler
+                DCD     fIrqUviHandler
+                DCD     fIrqDmaHandler
+                DCD     fIrqDbgPwrUpHandler
+                DCD     fIrqSpi2Handler
+                DCD     fIrqI2C2Handler
+                DCD     fIrqFVDDHCompHandler
 __Vectors_End
 
 __Vectors_Size  EQU     __Vectors_End - __Vectors
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld
index 122bebd1ef0..6076d11859d 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld
@@ -2,48 +2,46 @@
  * NCS36510 ARM GCC linker script file
  */
 
-MEMORY
-{
-  VECTORS (rx)          : ORIGIN = 0x00003000, LENGTH = 0x00000090
-  FLASH (rx)            : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90
-  RAM (rwx)             : ORIGIN = 0x3FFF4000, LENGTH = 48K 
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * _reset_init : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .isr_vector :
+MEMORY {
+    VECTORS (rx)          : ORIGIN = 0x00003000, LENGTH = 0x00000090
+        FLASH (rx)            : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90
+        RAM (rwx)             : ORIGIN = 0x3FFF4000, LENGTH = 48K
+    }
+
+    /* Linker script to place sections and symbol values. Should be used together
+     * with other linker script that defines memory regions FLASH and RAM.
+     * It references following symbols, which must be defined in code:
+     * _reset_init : Entry of reset handler
+     *
+     * It defines following symbols, which code can use without definition:
+     * __exidx_start
+     * __exidx_end
+     * __etext
+     * __data_start__
+     * __preinit_array_start
+     * __preinit_array_end
+     * __init_array_start
+     * __init_array_end
+     * __fini_array_start
+     * __fini_array_end
+     * __data_end__
+     * __bss_start__
+     * __bss_end__
+     * __end__
+     * end
+     * __HeapLimit
+     * __StackLimit
+     * __StackTop
+     * __stack
+     */
+    ENTRY(Reset_Handler)
+
+    SECTIONS {
+.isr_vector :
     {
         __vector_table = .;
         KEEP(*(.vector_table))
-         . = ALIGN(4);
+        . = ALIGN(4);
     } > VECTORS
 
     /* ensure that uvisor bss is at the beginning of memory */
@@ -70,7 +68,7 @@ SECTIONS
         __uvisor_bss_end = .;
     } > RAM
 
-    .text :
+.text :
     {
         /* uVisor code and data */
         . = ALIGN(4);
@@ -102,19 +100,19 @@ SECTIONS
         KEEP(*(.eh_frame*))
     } > FLASH
 
-    .ARM.extab :
+.ARM.extab :
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > FLASH
 
-    .ARM.exidx :
+.ARM.exidx :
     {
-       __exidx_start = .;
+        __exidx_start = .;
         *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-       __exidx_end = .;
+        __exidx_end = .;
     } > FLASH
 
-    .data :
+.data :
     {
         PROVIDE( __etext = LOADADDR(.data) );
 
@@ -149,7 +147,7 @@ SECTIONS
     } >RAM AT>FLASH
 
     /* uvisor configuration data */
-    .uvisor.secure :
+.uvisor.secure :
     {
         . = ALIGN(32);
         __uvisor_secure_start = .;
@@ -211,7 +209,7 @@ SECTIONS
     PROVIDE(__heap_size = SIZEOF(.heap));
     PROVIDE(__mbed_sbrk_start = ADDR(.heap));
     PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
-    
+
     /* .stack section doesn't contains any symbols. It is only
      * used for linker to reserve space for the main stack section
      * WARNING: .stack should come immediately after the last secure memory
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.s b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.s
index 56da62bf0fe..4ecaeb589c7 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.s
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.s
@@ -33,90 +33,90 @@
    ---------------------------------------------------------------------------*/
 
 
-	.syntax	unified
-	.arch	armv7-m
+.syntax    unified
+.arch    armv7-m
 
-  .section .stack
-  .align 3
+.section .stack
+.align 3
 #ifdef __STACK_SIZE
-  .equ    Stack_Size, __STACK_SIZE
+.equ    Stack_Size, __STACK_SIZE
 #else
-  .equ    Stack_Size, 0x400
+.equ    Stack_Size, 0x400
 #endif
-  .globl    __StackTop
-  .globl    __StackLimit
+.globl    __StackTop
+.globl    __StackLimit
 __StackLimit:
-  .space    Stack_Size
-  .size __StackLimit, . - __StackLimit
+.space    Stack_Size
+.size __StackLimit, . - __StackLimit
 __StackTop:
-  .size __StackTop, . - __StackTop
+.size __StackTop, . - __StackTop
 
-  .section .heap
-  .align 3
+.section .heap
+.align 3
 #ifdef __HEAP_SIZE
-  .equ    Heap_Size, __HEAP_SIZE
+.equ    Heap_Size, __HEAP_SIZE
 #else
-  .equ    Heap_Size, 0x400
+.equ    Heap_Size, 0x400
 #endif
-  .globl    __HeapBase
-  .globl    __HeapLimit
+.globl    __HeapBase
+.globl    __HeapLimit
 __HeapBase:
-  .space    Heap_Size
-  .size __HeapBase, . - __HeapBase
+.space    Heap_Size
+.size __HeapBase, . - __HeapBase
 __HeapLimit:
-  .size __HeapLimit, . - __HeapLimit
+.size __HeapLimit, . - __HeapLimit
 
-  .section .vector_table,"a",%progbits
-  .align 2
-  .globl __Vectors
+.section .vector_table,"a",%progbits
+.align 2
+.globl __Vectors
 __Vectors:
-  .long   __StackTop                  /* Top of Stack */
-  .long   Reset_Handler               /* Reset Handler */
-  .long   NMI_Handler                 /* NMI Handler                  */
-  .long   HardFault_Handler           /* Hard Fault Handler           */
-  .long   MemManage_Handler           /* MPU Fault Handler            */
-  .long   BusFault_Handler            /* Bus Fault Handler            */
-  .long   UsageFault_Handler          /* Usage Fault Handler          */
-  .long   0                           /* Reserved                     */
-  .long   0                           /* Reserved                     */
-  .long   0                           /* Reserved                     */
-  .long   0                           /* Reserved                     */
-  .long   SVC_Handler                 /* SVCall Handler               */
-  .long   DebugMon_Handler            /* Debug Monitor Handler        */
-  .long   0                           /* Reserved                     */
-  .long   PendSV_Handler              /* PendSV Handler               */
-  .long   SysTick_Handler             /* SysTick Handler              */
-
-  /* External Interrupts */
-  .long	fIrqTim0Handler
-	.long	fIrqTim1Handler
-	.long	fIrqTim2Handler
-	.long	fIrqUart1Handler
-	.long	fIrqSpiHandler
-	.long	fIrqI2CHandler
-	.long	fIrqGpioHandler
-	.long	fIrqRtcHandler
-	.long	fIrqFlashHandler
-	.long	fIrqMacHwHandler
-	.long	fIrqAesHandler
-	.long	fIrqAdcHandler
-	.long	fIrqClockCalHandler
-	.long	fIrqUart2Handler
-	.long	fIrqUviHandler
-	.long	fIrqDmaHandler
- 	.long	fIrqDbgPwrUpHandler
- 	.long	fIrqSpi2Handler	
- 	.long	fIrqI2C2Handler
- 	.long	fIrqFVDDHCompHandler
-  
-  .size    __Vectors, . - __Vectors
-
-  .section .text.Reset_Handler
-  .thumb
-  .thumb_func
-  .align  2
-  .globl   Reset_Handler
-  .type    Reset_Handler, %function
+.long   __StackTop                  /* Top of Stack */
+.long   Reset_Handler               /* Reset Handler */
+.long   NMI_Handler                 /* NMI Handler                  */
+.long   HardFault_Handler           /* Hard Fault Handler           */
+.long   MemManage_Handler           /* MPU Fault Handler            */
+.long   BusFault_Handler            /* Bus Fault Handler            */
+.long   UsageFault_Handler          /* Usage Fault Handler          */
+.long   0                           /* Reserved                     */
+.long   0                           /* Reserved                     */
+.long   0                           /* Reserved                     */
+.long   0                           /* Reserved                     */
+.long   SVC_Handler                 /* SVCall Handler               */
+.long   DebugMon_Handler            /* Debug Monitor Handler        */
+.long   0                           /* Reserved                     */
+.long   PendSV_Handler              /* PendSV Handler               */
+.long   SysTick_Handler             /* SysTick Handler              */
+
+/* External Interrupts */
+.long    fIrqTim0Handler
+.long    fIrqTim1Handler
+.long    fIrqTim2Handler
+.long    fIrqUart1Handler
+.long    fIrqSpiHandler
+.long    fIrqI2CHandler
+.long    fIrqGpioHandler
+.long    fIrqRtcHandler
+.long    fIrqFlashHandler
+.long    fIrqMacHwHandler
+.long    fIrqAesHandler
+.long    fIrqAdcHandler
+.long    fIrqClockCalHandler
+.long    fIrqUart2Handler
+.long    fIrqUviHandler
+.long    fIrqDmaHandler
+.long    fIrqDbgPwrUpHandler
+.long    fIrqSpi2Handler
+.long    fIrqI2C2Handler
+.long    fIrqFVDDHCompHandler
+
+.size    __Vectors, . - __Vectors
+
+.section .text.Reset_Handler
+.thumb
+.thumb_func
+.align  2
+.globl   Reset_Handler
+.type    Reset_Handler, %function
 Reset_Handler:
 /*     Loop to copy data from read only memory to RAM. The ranges
 *      of copy from/to are specified by following symbols evaluated in
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.s b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.s
index b0703744817..e6ca52d23ef 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.s
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.s
@@ -1,4 +1,4 @@
-;/**************************************************************************//**
+;/******************************************************************************
 ; * @file     startup_ARMCM3.s
 ; * @brief    CMSIS Cortex-M4 Core Device Startup File
 ; *           for CM3 Device Series
@@ -91,32 +91,32 @@ __vector_table_0x1c
         DCD     SysTick_Handler
 
         ; External Interrupts
-        DCD		fIrqTim0Handler
-        DCD		fIrqTim1Handler
-        DCD		fIrqTim2Handler
-        DCD		fIrqUart1Handler
-        DCD		fIrqSpiHandler
-        DCD		fIrqI2CHandler
-        DCD		fIrqGpioHandler
-        DCD		fIrqRtcHandler
-        DCD		fIrqFlashHandler
-        DCD		fIrqMacHwHandler
-        DCD		fIrqAesHandler
-        DCD		fIrqAdcHandler
-        DCD		fIrqClockCalHandler
-        DCD		fIrqUart2Handler
-        DCD		fIrqUviHandler
-        DCD		fIrqDmaHandler
-       	DCD		fIrqDbgPwrUpHandler
-       	/* REV C/D interrupts */
-       	DCD		fIrqSpi2Handler
-       	DCD		fIrqI2c2Handler
-       	DCD		FIrqFVDDHCompHandler	/* FVDDH Supply Comparator Trip */
+        DCD        fIrqTim0Handler
+        DCD        fIrqTim1Handler
+        DCD        fIrqTim2Handler
+        DCD        fIrqUart1Handler
+        DCD        fIrqSpiHandler
+        DCD        fIrqI2CHandler
+        DCD        fIrqGpioHandler
+        DCD        fIrqRtcHandler
+        DCD        fIrqFlashHandler
+        DCD        fIrqMacHwHandler
+        DCD        fIrqAesHandler
+        DCD        fIrqAdcHandler
+        DCD        fIrqClockCalHandler
+        DCD        fIrqUart2Handler
+        DCD        fIrqUviHandler
+        DCD        fIrqDmaHandler
+        DCD        fIrqDbgPwrUpHandler
+        /* REV C/D interrupts */
+        DCD        fIrqSpi2Handler
+        DCD        fIrqI2c2Handler
+        DCD        FIrqFVDDHCompHandler    /* FVDDH Supply Comparator Trip */
 #endif
 __Vectors_End
 
 __Vectors       EQU   __vector_table
-__Vectors_Size 	EQU   __Vectors_End - __Vectors
+__Vectors_Size  EQU   __Vectors_End - __Vectors
 
 opt:        DC32     0x2082353F /* Full featured device */
 opt_reg:    DC32     0x4001E000
@@ -292,7 +292,7 @@ fIrqUviHandler
 fIrqSpi2Handler
         B fIrqSpi2Handler
 
-	PUBWEAK fIrqI2c2Handler
+        PUBWEAK fIrqI2c2Handler
         SECTION .text:CODE:REORDER(1)
 fIrqI2c2Handler
         B fIrqI2c2Handler
@@ -302,7 +302,7 @@ fIrqI2c2Handler
 FIrqFVDDHCompHandler
         B FIrqFVDDHCompHandler
 
-	PUBWEAK DEF_IRQHandler
+        PUBWEAK DEF_IRQHandler
         SECTION .text:CODE:REORDER(1)
 DEF_IRQHandler
         B DEF_IRQHandler
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.c
index 94baebee658..06bbcd6759c 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.c
@@ -24,7 +24,7 @@
 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 * @endinternal
 *
-* @ingroup 
+* @ingroup
 *
 * @details
 */
@@ -35,7 +35,7 @@
 #define NVIC_FLASH_VECTOR_ADDRESS (0x00000000)  // Initial vector position in flash
 
 
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
 {
     static volatile uint32_t *vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
 
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.h
index 62f15e2e7db..792d4a2b7d1 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.h
@@ -24,7 +24,7 @@
 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 * @endinternal
 *
-* @ingroup 
+* @ingroup
 *
 * @details
 */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.c
index 8bf95ae8129..d3fa866265d 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.c
@@ -44,8 +44,9 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
   Clock functions
  *----------------------------------------------------------------------------*/
 void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
-{ /*Function not implimented */
-  SystemCoreClock = __SYSTEM_CLOCK;
+{
+    /*Function not implimented */
+    SystemCoreClock = __SYSTEM_CLOCK;
 }
 
 /**
@@ -60,7 +61,7 @@ void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
 void SystemInit (void)
 {
 
-  SystemCoreClock = __SYSTEM_CLOCK;
+    SystemCoreClock = __SYSTEM_CLOCK;
 
-  fNcs36510Init();
+    fNcs36510Init();
 }
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.h
index 0f277e9f1f4..f5dd20864d0 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.h
@@ -9,9 +9,9 @@
  * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
  *
  * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
  *
  * @par
  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -50,7 +50,7 @@ extern void SystemInit (void);
  * @param  none
  * @return none
  *
- * @brief  Updates the SystemCoreClock with current core Clock 
+ * @brief  Updates the SystemCoreClock with current core Clock
  *         retrieved from cpu registers.
  */
 extern void SystemCoreClockUpdate (void);
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h
index 84ef37fea01..6728c46f107 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h
@@ -49,60 +49,60 @@
 /** DMA control HW registers structure overlay */
 #ifdef REVB
 typedef struct {
-    __IO uint32_t CONTROL;				/**< Write 1 to enable DMA, write 0 to disable */
-    __IO uint32_t SOURCE;				/**< Address of source, read to get the number of bytes written */
-    __IO uint32_t DESTINATION;			/**< Address of destination, read to get the number of bytes written  */
-    __IO uint32_t SIZE;					/**< Lenght of the entire transfer */
-    __IO uint32_t STATUS;				/**< To be debined */
-    __IO uint32_t INT_ENABLE;			/**< Enable interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
-    __IO uint32_t INT_CLEAR_ENABLE;		/**< Clear Interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
-    __I  uint32_t INT_STATUS;			/**< Current interrupt status. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
+    __IO uint32_t CONTROL;               /**< Write 1 to enable DMA, write 0 to disable */
+    __IO uint32_t SOURCE;                /**< Address of source, read to get the number of bytes written */
+    __IO uint32_t DESTINATION;           /**< Address of destination, read to get the number of bytes written  */
+    __IO uint32_t SIZE;                  /**< Lenght of the entire transfer */
+    __IO uint32_t STATUS;                /**< To be debined */
+    __IO uint32_t INT_ENABLE;            /**< Enable interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
+    __IO uint32_t INT_CLEAR_ENABLE;      /**< Clear Interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
+    __I  uint32_t INT_STATUS;            /**< Current interrupt status. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
 } DmaReg_t, *DmaReg_pt;
 #endif /* REVB */
 #ifdef REVD
 typedef struct {
     union {
         struct {
-            __IO uint32_t ENABLE:1;		/**< DMA enable:  1 to enable; 0 to disable */
-            __IO uint32_t MODE	:2;		/**< DMA mode: 00 � Memory to memory; 01 � Memory to peripheral; 10 � Peripheral to memory; 11 � Peripheral to peripheral */
+            __IO uint32_t ENABLE:1;        /**< DMA enable:  1 to enable; 0 to disable */
+            __IO uint32_t MODE    :2;      /**< DMA mode: 00 � Memory to memory; 01 � Memory to peripheral; 10 � Peripheral to memory; 11 � Peripheral to peripheral */
         } BITS;
         __IO uint32_t WORD;
-    } CONTROL;							/**< Control register */
-    __IO uint32_t SOURCE;				/**< Address of source, read to get the number of bytes written */
-    __IO uint32_t DESTINATION;			/**< Address of destination, read to get the number of bytes written  */
-    __IO uint32_t SIZE;					/**< Lenght of the entire transfer */
+    } CONTROL;                           /**< Control register */
+    __IO uint32_t SOURCE;                /**< Address of source, read to get the number of bytes written */
+    __IO uint32_t DESTINATION;           /**< Address of destination, read to get the number of bytes written  */
+    __IO uint32_t SIZE;                  /**< Lenght of the entire transfer */
     union {
         struct {
-            __I uint32_t COMPLETED:1;			/**< Done: 0 � Not complete, 1 � Complete */
-            __I uint32_t SOURCE_ERROR:1;		/**< Source Error: 0 � No Error, 1 � Error */
-            __I uint32_t DESTINATION_ERROR:1;	/**< Destination Error: 0 � No Error, 1 � Source Error */
+            __I uint32_t COMPLETED:1;            /**< Done: 0 � Not complete, 1 � Complete */
+            __I uint32_t SOURCE_ERROR:1;         /**< Source Error: 0 � No Error, 1 � Error */
+            __I uint32_t DESTINATION_ERROR:1;    /**< Destination Error: 0 � No Error, 1 � Source Error */
         } BITS;
         __I uint32_t WORD;
-    } STATUS;									/**< Status register */
+    } STATUS;                                    /**< Status register */
     union {
         struct {
-            __IO uint32_t COMPLETED:1;			/**< A write of �1� enables the interrupt generated by a DMA transfer complete */
-            __IO uint32_t SOURCE_ERROR:1;		/**< A write of �1� enables the interrupt generated by an error on the source side of the DMA transfer */
-            __IO uint32_t DESTINATION_ERROR:1;	/**< A write of �1� enables the interrupt generated by an error on the destination side of the DMA transfer */
+            __IO uint32_t COMPLETED:1;            /**< A write of �1� enables the interrupt generated by a DMA transfer complete */
+            __IO uint32_t SOURCE_ERROR:1;         /**< A write of �1� enables the interrupt generated by an error on the source side of the DMA transfer */
+            __IO uint32_t DESTINATION_ERROR:1;    /**< A write of �1� enables the interrupt generated by an error on the destination side of the DMA transfer */
         } BITS;
         __IO uint32_t WORD;
-    } INT_ENABLE;								/**< Interrupt enable */
+    } INT_ENABLE;                                /**< Interrupt enable */
     union {
         struct {
-            __IO uint32_t COMPLETED:1;			/**< A write clears the interrupt generated by a DMA transfer complete */
-            __IO uint32_t SOURCE_ERROR:1;		/**< A write clears the interrupt generated by an error on the source side of the DMA transfer */
-            __IO uint32_t DESTINATION_ERROR:1;	/**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */
+            __IO uint32_t COMPLETED:1;            /**< A write clears the interrupt generated by a DMA transfer complete */
+            __IO uint32_t SOURCE_ERROR:1;         /**< A write clears the interrupt generated by an error on the source side of the DMA transfer */
+            __IO uint32_t DESTINATION_ERROR:1;    /**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */
         } BITS;
         __IO uint32_t WORD;
-    } INT_CLEAR;								/**< Interrupt clear */
+    } INT_CLEAR;                                /**< Interrupt clear */
     union {
         struct {
-            __I uint32_t COMPLETED:1;			/**< Transfer complete interrupt */
-            __I uint32_t SOURCE_ERROR:1;		/**< Source error interrupt */
-            __I uint32_t DESTINATION_ERROR:1;	/**< Destination error interrupt */
+            __I uint32_t COMPLETED:1;            /**< Transfer complete interrupt */
+            __I uint32_t SOURCE_ERROR:1;         /**< Source error interrupt */
+            __I uint32_t DESTINATION_ERROR:1;    /**< Destination error interrupt */
         } BITS;
         __I uint32_t WORD;
-    } INT_STATUS;								/**< Interrupt status */
+    } INT_STATUS;                                /**< Interrupt status */
 } DmaReg_t, *DmaReg_pt;
 #endif /* REVD */
 #endif /* DMA_MAP_H_ */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/error.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/error.h
index a76b7c17662..1c33cc3ea42 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/error.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/error.h
@@ -33,6 +33,6 @@
 #include <stdint.h>
 
 typedef uint8_t error;
-#define NO_ERROR		(0xFF)
+#define NO_ERROR        (0xFF)
 
 #endif /* ERROR_H_ */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h
index 19849ad24c3..35df77ffb8b 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h
@@ -41,11 +41,11 @@
 typedef struct {
     union {
         struct {
-            __I uint32_t FLASH_A_BUSY:1;		/**< Busy A */
-            __I uint32_t FLASH_B_BUSY:1;		/**< Busy B */
-            __I uint32_t FLASH_A_UNLOCK:1;	/**< Unlock A */
-            __I uint32_t FLASH_B_UNLOCK:1;	/**< Unlock B */
-            __I uint32_t FLASH_ERROR:3;		/**< 000 � No Error, 111 � Attempt to access an array while it is busy powering up, 001 � Attempt to erase bootloader in the field, 010 � Attempt to access array during erase, 100 � Attempt to access array during write */
+            __I uint32_t FLASH_A_BUSY:1;      /**< Busy A */
+            __I uint32_t FLASH_B_BUSY:1;      /**< Busy B */
+            __I uint32_t FLASH_A_UNLOCK:1;    /**< Unlock A */
+            __I uint32_t FLASH_B_UNLOCK:1;    /**< Unlock B */
+            __I uint32_t FLASH_ERROR:3;       /**< 000 � No Error, 111 � Attempt to access an array while it is busy powering up, 001 � Attempt to erase bootloader in the field, 010 � Attempt to access array during erase, 100 � Attempt to access array during write */
         } BITS;
         __I uint32_t WORD;
     } STATUS;
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio.h
index 8780f196c03..e10facf61bb 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio.h
@@ -55,26 +55,26 @@ extern "C" {
 
 
 /** output configuration push/pull */
-#define PAD_OUTCFG_PUSHPULL	                (uint8_t)0x00
+#define PAD_OUTCFG_PUSHPULL                    (uint8_t)0x00
 
 /** output configuration open drain */
-#define PAD_OOUTCFG_OPENDRAIN                   (uint8_t)0x01
+#define PAD_OOUTCFG_OPENDRAIN                  (uint8_t)0x01
 
 /** no pull up nor pull down */
-#define PAD_PULL_NONE	                        (uint8_t)0x01
+#define PAD_PULL_NONE                          (uint8_t)0x01
 
 /** pull down */
-#define PAD_PULL_DOWN	                        (uint8_t)0x00
+#define PAD_PULL_DOWN                          (uint8_t)0x00
 
 /** pull up */
-#define PAD_PULL_UP		                (uint8_t)0x03
+#define PAD_PULL_UP                            (uint8_t)0x03
 
 /* Number of DIO lines supported by NCS36510 */
-#define NUMBER_OF_GPIO		        ((uint8_t)0x12)
+#define NUMBER_OF_GPIO        ((uint8_t)0x12)
 
 /* All DIO lines set to 1 */
-#define IO_ALL				((uint32_t)0x3FFFF)
-#define IO_NONE				((uint32_t)0x00000)
+#define IO_ALL                ((uint32_t)0x3FFFF)
+#define IO_NONE               ((uint32_t)0x00000)
 
 /* Gpio handler */
 void fGpioHandler(void);
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c
index f8d6e7e6117..276d6861375 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c
@@ -79,8 +79,8 @@ static uint32_t gpioIds[NUMBER_OF_GPIO] = {0};
 
 /** Main GPIO IRQ handler called from vector table handler
  *
- * @param gpioBase	The GPIO register base address
- * @return 			void
+ * @param gpioBase    The GPIO register base address
+ * @return            void
  */
 void fGpioHandler(void)
 {
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h
index 0bc576e8fc1..831d73e4e58 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h
@@ -46,20 +46,20 @@
 /** Structure overlay for GPIO control registers, see memory_map.h
  * For most registers, bit lockations match GPIO numbers.*/
 typedef struct {
-    __IO uint32_t R_STATE_W_SET; 	    /**< Read synchronized input / Write ones to bits to set corresponding output IO's*/
-    __IO uint32_t R_IRQ_W_CLEAR; 	    /**< Read state of irq / Write ones to bits to clear corresponging output IO's */
-    __IO uint32_t W_OUT; 		        /**< Write ones to set direction to output */
-    __IO uint32_t W_IN; 		        /**< Write ones to set direction to input */
-    __IO uint32_t IRQ_ENABLE_SET; 	    /**< Read active high irq enable / Write ones to enable irq */
-    __IO uint32_t IRQ_ENABLE_CLEAR;     /**< Read active high irq enable / Write ones to disable irq */
-    __IO uint32_t IRQ_EDGE; 	        /**< Read irq configuration (edge or level) / Write ones to set irq to edge-sensitive */
-    __IO uint32_t IRQ_LEVEL; 	        /**< Read irq configuration (edge or level) / Write ones to set irq to level-sensitive */
-    __IO uint32_t IRQ_POLARITY_SET;     /**< Read irq polarity / Write ones to set irq to active high or rising edge */
-    __IO uint32_t IRQ_POLARITY_CLEAR;   /**< Read irq polarity / Write ones to set interrupts to active low or falling edge */
-    __IO uint32_t ANYEDGE_SET; 		    /**< Read irq anyedge configuration / Write ones to override irq edge selection & irq on any edge */
-    __IO uint32_t ANYEDGE_CLEAR; 	    /**< Read irq anyedge configuration / Write ones to clear edge selection override */
-    __IO uint32_t IRQ_CLEAR; 		    /**< Write ones to clear edge-sensitive irq */
-    __IO uint32_t CONTROL; 			    /**< Controls loopback/normal mode selection */
+    __IO uint32_t R_STATE_W_SET;         /**< Read synchronized input / Write ones to bits to set corresponding output IO's*/
+    __IO uint32_t R_IRQ_W_CLEAR;         /**< Read state of irq / Write ones to bits to clear corresponging output IO's */
+    __IO uint32_t W_OUT;                 /**< Write ones to set direction to output */
+    __IO uint32_t W_IN;                  /**< Write ones to set direction to input */
+    __IO uint32_t IRQ_ENABLE_SET;        /**< Read active high irq enable / Write ones to enable irq */
+    __IO uint32_t IRQ_ENABLE_CLEAR;      /**< Read active high irq enable / Write ones to disable irq */
+    __IO uint32_t IRQ_EDGE;              /**< Read irq configuration (edge or level) / Write ones to set irq to edge-sensitive */
+    __IO uint32_t IRQ_LEVEL;             /**< Read irq configuration (edge or level) / Write ones to set irq to level-sensitive */
+    __IO uint32_t IRQ_POLARITY_SET;      /**< Read irq polarity / Write ones to set irq to active high or rising edge */
+    __IO uint32_t IRQ_POLARITY_CLEAR;    /**< Read irq polarity / Write ones to set interrupts to active low or falling edge */
+    __IO uint32_t ANYEDGE_SET;           /**< Read irq anyedge configuration / Write ones to override irq edge selection & irq on any edge */
+    __IO uint32_t ANYEDGE_CLEAR;         /**< Read irq anyedge configuration / Write ones to clear edge selection override */
+    __IO uint32_t IRQ_CLEAR;             /**< Write ones to clear edge-sensitive irq */
+    __IO uint32_t CONTROL;               /**< Controls loopback/normal mode selection */
 } GpioReg_t, *GpioReg_pt;
 
 #endif /* GPIO_MAP_H_ */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h
index 3467f5def7e..15abc34edd2 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h
@@ -1,7 +1,7 @@
 /**
  ******************************************************************************
  * @file    i2c.h
- * @brief	(API) Public header of i2c driver
+ * @brief    (API) Public header of i2c driver
  * @internal
  * @author   ON Semiconductor
  * $Rev:  $
@@ -35,61 +35,61 @@
 #include "PeripheralPins.h"
 
 #ifndef I2C_H_
-#define	I2C_H_
+#define    I2C_H_
 
 /* Miscellaneous I/O and control operations codes */
-#define I2C_IPC7208_IOCTL_NOT_ACK		0x03
-#define I2C_IPC7208_IOCTL_NULL_CMD		0x04
-#define I2C_IPC7208_IOCTL_ACK			0x05
+#define I2C_IPC7208_IOCTL_NOT_ACK        0x03
+#define I2C_IPC7208_IOCTL_NULL_CMD       0x04
+#define I2C_IPC7208_IOCTL_ACK            0x05
 
 /* Definitions for the clock speed. */
-#define I2C_SPEED_100K_AT_8MHZ	(uint8_t)0x12
-#define I2C_SPEED_100K_AT_16MHZ	(uint8_t)0x26
-#define I2C_SPEED_400K_AT_8MHZ	(uint8_t)0x03
-#define I2C_SPEED_400K_AT_16MHZ	(uint8_t)0x08
+#define I2C_SPEED_100K_AT_8MHZ     (uint8_t)0x12
+#define I2C_SPEED_100K_AT_16MHZ    (uint8_t)0x26
+#define I2C_SPEED_400K_AT_8MHZ     (uint8_t)0x03
+#define I2C_SPEED_400K_AT_16MHZ    (uint8_t)0x08
 
 
 /* I2C commands */
-#define I2C_CMD_NULL  		0x00
-#define I2C_CMD_WDAT0 		0x10
-#define I2C_CMD_WDAT1 		0x11
-#define I2C_CMD_WDAT8 		0x12
-#define I2C_CMD_RDAT8 		0x13
-#define I2C_CMD_STOP  		0x14
-#define I2C_CMD_START 		0x15
-#define I2C_CMD_VRFY_ACK 	0x16
-#define I2C_CMD_VRFY_VACK  	0x17
+#define I2C_CMD_NULL          0x00
+#define I2C_CMD_WDAT0         0x10
+#define I2C_CMD_WDAT1         0x11
+#define I2C_CMD_WDAT8         0x12
+#define I2C_CMD_RDAT8         0x13
+#define I2C_CMD_STOP          0x14
+#define I2C_CMD_START         0x15
+#define I2C_CMD_VRFY_ACK      0x16
+#define I2C_CMD_VRFY_VACK     0x17
 
 /* Status register bits */
-#define I2C_STATUS_CMD_FIFO_MPTY_BIT 	0x01
-#define I2C_STATUS_RD_DATA_RDY_BIT 		0x02
-#define I2C_STATUS_BUS_ERR_BIT 			0x04
-#define I2C_STATUS_RD_DATA_UFL_BIT 		0x08
-#define I2C_STATUS_CMD_FIFO_OFL_BIT 	0x10
-#define I2C_STATUS_CMD_FIFO_FULL_BIT 	0x20
+#define I2C_STATUS_CMD_FIFO_MPTY_BIT     0x01
+#define I2C_STATUS_RD_DATA_RDY_BIT       0x02
+#define I2C_STATUS_BUS_ERR_BIT           0x04
+#define I2C_STATUS_RD_DATA_UFL_BIT       0x08
+#define I2C_STATUS_CMD_FIFO_OFL_BIT      0x10
+#define I2C_STATUS_CMD_FIFO_FULL_BIT     0x20
 
 /* I2C return status */
-#define I2C_STATUS_INVALID			0xFF
-#define I2C_STATUS_SUCCESS			0x00
-#define I2C_STATUS_FAIL				0x01
-#define I2C_STATUS_BUS_ERROR		0x02
-#define I2C_STATUS_RD_DATA_UFL		0x03
-#define I2C_STATUS_CMD_FIFO_OFL		0x04
-#define I2C_STATUS_INTERRUPT_ERROR	0x05
-#define I2C_STATUS_CMD_FIFO_EMPTY	0x06
+#define I2C_STATUS_INVALID            0xFF
+#define I2C_STATUS_SUCCESS            0x00
+#define I2C_STATUS_FAIL               0x01
+#define I2C_STATUS_BUS_ERROR          0x02
+#define I2C_STATUS_RD_DATA_UFL        0x03
+#define I2C_STATUS_CMD_FIFO_OFL       0x04
+#define I2C_STATUS_INTERRUPT_ERROR    0x05
+#define I2C_STATUS_CMD_FIFO_EMPTY     0x06
 
 /* I2C clock divider position */
-#define I2C_CLOCKDIVEDER_VAL_MASK 		0x1F
-#define I2C_APB_CLK_DIVIDER_VAL_MASK	0x1FE0
+#define I2C_CLOCKDIVEDER_VAL_MASK       0x1F
+#define I2C_APB_CLK_DIVIDER_VAL_MASK    0x1FE0
 
 /* Error check */
-#define I2C_UFL_CHECK 		(d->membase->STATUS.WORD & 0x80)
-#define FIFO_OFL_CHECK 		(d->membase->STATUS.WORD & 0x10)
-#define I2C_BUS_ERR_CHECK 	(d->membase->STATUS.WORD & 0x04)
-#define RD_DATA_READY 		(d->membase->STATUS.WORD & 0x02)
+#define I2C_UFL_CHECK         (d->membase->STATUS.WORD & 0x80)
+#define FIFO_OFL_CHECK        (d->membase->STATUS.WORD & 0x10)
+#define I2C_BUS_ERR_CHECK     (d->membase->STATUS.WORD & 0x04)
+#define RD_DATA_READY         (d->membase->STATUS.WORD & 0x02)
 
-#define I2C_API_STATUS_SUCCESS	0
-#define PAD_REG_ADRS_BYTE_SIZE	4
+#define I2C_API_STATUS_SUCCESS    0
+#define PAD_REG_ADRS_BYTE_SIZE    4
 
 /** Init I2C device.
  * @details
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c
index e710399eea4..8b254c8c907 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c
@@ -32,7 +32,7 @@
 #include "i2c.h"
 #include "i2c_api.h"
 
-#define I2C_READ_WRITE_BIT_MASK	0xFE
+#define I2C_READ_WRITE_BIT_MASK    0xFE
 
 /* See i2c_api.h for details */
 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
@@ -85,7 +85,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
         /* Error sending coomand/s */
         return Count;
     }
-    if(stop) {	/* Send stop bit if requested */
+    if(stop) {    /* Send stop bit if requested */
         status = fI2cStop(obj);
         if(status) {
             /* Error sending stop bit */
@@ -122,7 +122,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
         return Count;
     }
 
-    if(stop) {	/* If stop requested */
+    if(stop) {    /* If stop requested */
         /* Send stop bit */
         status = fI2cStop(obj);
         if(status) {
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h
index fc671c1a2be..c7bf1940a44 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h
@@ -66,9 +66,9 @@ typedef struct {
     union {
         struct {
             __IO uint32_t CMD_FIFO_INT :1; /**< Command FIFO empty interrupt : 0 = disable , 1 = enable */
-            __IO uint32_t RD_FIFO_INT :1; /**< Read Data FIFO Not Empty Interrupt :  0 = disable , 1 = enable */
-            __IO uint32_t I2C_ERR_INT :1; /**< I2C Error Interrupt : 0 = disable , 1 = enable */
-            //		__IO uint32_t PAD :4; /**< Reserved. Writes have no effect; Read as 0x00. */
+            __IO uint32_t RD_FIFO_INT :1;  /**< Read Data FIFO Not Empty Interrupt :  0 = disable , 1 = enable */
+            __IO uint32_t I2C_ERR_INT :1;  /**< I2C Error Interrupt : 0 = disable , 1 = enable */
+            //    __IO uint32_t PAD :4;    /**< Reserved. Writes have no effect; Read as 0x00. */
         } BITS;
         __IO uint32_t WORD;
     } IER;
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h
index 8dca4371cee..c0c6c9f8ba3 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h
@@ -190,9 +190,9 @@ typedef struct {
         } BITS;
         __I uint32_t WORD;
     } TIMER_STATUS;                                         /**< 0x40014054 */
-    __I uint32_t PROTOCOL_TIMER;                      		/**< 0x40014058 */
+    __I uint32_t PROTOCOL_TIMER;                            /**< 0x40014058 */
     __O uint32_t PAD4;                                      /**< 0x4001405C */
-    __I uint32_t FINISH_TIME;                              	/**< 0x40014060 */
+    __I uint32_t FINISH_TIME;                               /**< 0x40014060 */
     union {
         struct {
             __IO uint32_t TX_SLOT_OFFSET:12;
@@ -215,20 +215,20 @@ typedef struct {
         } BITS;
         __IO uint32_t WORD;
 #ifdef REVB
-    } CRD_SHORT_ADDR;                                  		/**< 0x40014070 */
-    __IO uint32_t CRD_LONG_ADDR_HI;                        	/**< 0x40014074 */
-    __IO uint32_t CRD_LONG_ADDR_LO;              			/**< 0x40014078 */
+    } CRD_SHORT_ADDR;                                   /**< 0x40014070 */
+    __IO uint32_t CRD_LONG_ADDR_HI;                     /**< 0x40014074 */
+    __IO uint32_t CRD_LONG_ADDR_LO;                     /**< 0x40014078 */
 #endif /* REVB */
 #ifdef REVD
-} CRD_SHORT_ADDR;                                  		/**< 0x4001406C */
-__IO uint32_t CRD_LONG_ADDR_HI;                        	/**< 0x40014070 */
-__IO uint32_t CRD_LONG_ADDR_LO;              			/**< 0x40014074 */
+} CRD_SHORT_ADDR;                                       /**< 0x4001406C */
+__IO uint32_t CRD_LONG_ADDR_HI;                         /**< 0x40014070 */
+__IO uint32_t CRD_LONG_ADDR_LO;                         /**< 0x40014074 */
 __O uint32_t PAD5;                                      /**< 0x40014078 */
 #endif /* REVD */
 __O uint32_t PAD9;                                      /**< 0x4001407C */
 __O uint32_t PAD10;                                     /**< 0x40014080 */
 __O uint32_t PAD11;                                     /**< 0x40014084 */
-__IO uint32_t RX_LENGTH;                         		/**< 0x40014088 */
+__IO uint32_t RX_LENGTH;                                /**< 0x40014088 */
 union {
     struct {
         __IO uint32_t TXLENGTH:7;
@@ -265,11 +265,11 @@ union {
     __IO uint32_t WORD;
 } ACK_STOP;                                             /**< 0x400140A4 */
 __IO uint32_t TXCCA;                                    /**< 0x400140A8 */
-__IO uint32_t ADDR_L_LOC;                         		/**< 0x400140AC */
-__IO uint32_t ADDR_S_LOC;                         		/**< 0x400140B0 */
-__IO uint32_t FRAME_MATCH_RESULT;                		/**< 0x400140B4 */
-__IO uint32_t FRAME_MATCH_ADDR_L;                   	/**< 0x400140B8 */
-__IO uint32_t FRAME_MATCH_ADDR_S;                    	/**< 0x400140BC */
+__IO uint32_t ADDR_L_LOC;                               /**< 0x400140AC */
+__IO uint32_t ADDR_S_LOC;                               /**< 0x400140B0 */
+__IO uint32_t FRAME_MATCH_RESULT;                       /**< 0x400140B4 */
+__IO uint32_t FRAME_MATCH_ADDR_L;                       /**< 0x400140B8 */
+__IO uint32_t FRAME_MATCH_ADDR_S;                       /**< 0x400140BC */
 union {
     struct {
         __IO uint32_t AA:1;
@@ -358,48 +358,48 @@ union {
 typedef struct {
     union {
         struct {
-            __IO uint32_t DRC:1;							/**< Reserved */
-            __IO uint32_t SWIQ:1; 							/**< Compensation for quadrature polarity. (set to 1 for RevB) */
-            __IO uint32_t LIF:1;							/**< Allows the receiver to use a low-IF frequency of +1.23 MHz (0) or -1.23 MHz (1). */
-            __IO uint32_t PM:1;								/**< Preamble Mode: Mode 0 (high sensitivity) � Preamble detection is based on observation of a regular pattern of correlation peaks over a span of 5 consecutive symbol periods.  Each symbol period produces a time index and frequency index corresponding to the largest correlation peak.  If 4 out of 5 symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared.  This mode improves preamble detection rate by tolerating one corrupt correlation result in the span of 5 symbols.  However, the relaxed detection rule allows a higher rate of false preamble detection when no signal is present. Mode 1 (low false detection) � Preamble detection is based on a span of 4 consecutive symbol periods.  Each symbol period produces a time index and frequency index corresponding to the largest correlation peak.  If all four symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared.  This mode enforces a more strict detection rule and therefore offers lower rate of false preamble detection at the expense of higher missed detection. */
-            __IO uint32_t ASM:1;							/**< This bit determines whether antenna selection is automatic (1) or manual (0).  For applications that do not use antenna diversity, this bit should be set to 0. */
-            __IO uint32_t AS:1;								/**< If automatic antenna selection mode is used, this bit determines the initial antenna selection.  If manual antenna selection mode is used, this bit determines the antenna selection, 0 or 1. */
-            __IO uint32_t DTC:1; 							/**< Sets the decay time constant used in the RSSI calculation and Digital Gain Control functions. 0: Time constant set to 1 symbol period.  This produces a slower response time but more stable RSSI values.  Not recommended for use with antenna diversity.  1: Time constant set to 1/4th of a symbol period.  This produces a faster response with slightly more variance in the RSSI calculation.  Recommended for most cases.  */
+            __IO uint32_t DRC:1;                            /**< Reserved */
+            __IO uint32_t SWIQ:1;                           /**< Compensation for quadrature polarity. (set to 1 for RevB) */
+            __IO uint32_t LIF:1;                            /**< Allows the receiver to use a low-IF frequency of +1.23 MHz (0) or -1.23 MHz (1). */
+            __IO uint32_t PM:1;                             /**< Preamble Mode: Mode 0 (high sensitivity) � Preamble detection is based on observation of a regular pattern of correlation peaks over a span of 5 consecutive symbol periods.  Each symbol period produces a time index and frequency index corresponding to the largest correlation peak.  If 4 out of 5 symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared.  This mode improves preamble detection rate by tolerating one corrupt correlation result in the span of 5 symbols.  However, the relaxed detection rule allows a higher rate of false preamble detection when no signal is present. Mode 1 (low false detection) � Preamble detection is based on a span of 4 consecutive symbol periods.  Each symbol period produces a time index and frequency index corresponding to the largest correlation peak.  If all four symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared.  This mode enforces a more strict detection rule and therefore offers lower rate of false preamble detection at the expense of higher missed detection. */
+            __IO uint32_t ASM:1;                            /**< This bit determines whether antenna selection is automatic (1) or manual (0).  For applications that do not use antenna diversity, this bit should be set to 0. */
+            __IO uint32_t AS:1;                             /**< If automatic antenna selection mode is used, this bit determines the initial antenna selection.  If manual antenna selection mode is used, this bit determines the antenna selection, 0 or 1. */
+            __IO uint32_t DTC:1;                            /**< Sets the decay time constant used in the RSSI calculation and Digital Gain Control functions. 0: Time constant set to 1 symbol period.  This produces a slower response time but more stable RSSI values.  Not recommended for use with antenna diversity.  1: Time constant set to 1/4th of a symbol period.  This produces a faster response with slightly more variance in the RSSI calculation.  Recommended for most cases.  */
             __IO uint32_t PAD1:9;
-            __IO uint32_t DFR:16;							/**<Selectively enables individual frequency offsets used during preamble search.  Each of the 15 bits in this field corresponds to one of 15 different frequency offsets.  A bit value of 0 removes a specific frequency offset from the search, while a bit value of 1 includes the frequency offset in the search. */
+            __IO uint32_t DFR:16;                           /**<Selectively enables individual frequency offsets used during preamble search.  Each of the 15 bits in this field corresponds to one of 15 different frequency offsets.  A bit value of 0 removes a specific frequency offset from the search, while a bit value of 1 includes the frequency offset in the search. */
         } BITS;
         __IO uint32_t WORD;
-    } DMD_CONTROL0;											/**< 0x40014100 */
+    } DMD_CONTROL0;                                         /**< 0x40014100 */
     union {
         struct {
-            __IO uint32_t DST:4;							/**< This value specifies the SFD search period in symbols.  After preamble detection, the demodulator begins symbol recovery and searches for the start-of-frame delimiter (SFD).  If the SFD is not found within the number of symbols specified, the preamble detection flag is cleared and a new preamble search is initiated.  The default value of 8 symbols should be sufficient for 802.15.4 compliant applications. Default 8 */
+            __IO uint32_t DST:4;                            /**< This value specifies the SFD search period in symbols.  After preamble detection, the demodulator begins symbol recovery and searches for the start-of-frame delimiter (SFD).  If the SFD is not found within the number of symbols specified, the preamble detection flag is cleared and a new preamble search is initiated.  The default value of 8 symbols should be sufficient for 802.15.4 compliant applications. Default 8 */
             __IO uint32_t PAD0:4;
-            __IO uint32_t DPT:6;							/**< The similarity criteria used for preamble detection includes a rule that all time index values must occupy a span equal to or less than this value.  The default span of 0011 means that the correlation peaks must span a range of 3Ts, where Ts is the sample period = 0.25 �s.  This value is recommended for typical multipath conditions.  Very long-range applications may benefit from a higher value. Default 3 */
+            __IO uint32_t DPT:6;                            /**< The similarity criteria used for preamble detection includes a rule that all time index values must occupy a span equal to or less than this value.  The default span of 0011 means that the correlation peaks must span a range of 3Ts, where Ts is the sample period = 0.25 �s.  This value is recommended for typical multipath conditions.  Very long-range applications may benefit from a higher value. Default 3 */
             __IO uint32_t PAD1:2;
-            __IO uint32_t DPF:4;							/**< The similarity criteria used for preamble detection includes a rule that all frequency index values must occupy a span equal to or less than this value.  The default span of 0001 means that the difference between largest frequency index and smallest frequency index must be less than or equal to 1. Default 1 */
+            __IO uint32_t DPF:4;                            /**< The similarity criteria used for preamble detection includes a rule that all frequency index values must occupy a span equal to or less than this value.  The default span of 0001 means that the difference between largest frequency index and smallest frequency index must be less than or equal to 1. Default 1 */
             __IO uint32_t PAD2:4;
-            __IO uint32_t DCT:4;							/**< In order for preamble detection to be declared, the correlation peaks must exceed a threshold.  The threshold is computed dynamically and includes a programmable scale factor:  1 + bit[27]/2 + bit[26]/4 + bit[25]/8 + bit[24]/16  The default value of 1.5 is recommended for manual-antenna selection, while a value of 1.75 is recommended for automatic antenna selection. */
+            __IO uint32_t DCT:4;                            /**< In order for preamble detection to be declared, the correlation peaks must exceed a threshold.  The threshold is computed dynamically and includes a programmable scale factor:  1 + bit[27]/2 + bit[26]/4 + bit[25]/8 + bit[24]/16  The default value of 1.5 is recommended for manual-antenna selection, while a value of 1.75 is recommended for automatic antenna selection. */
 
         } BITS;
         __IO uint32_t WORD;
-    } DMD_CONTROL1;											/**< 0x40014104 */
+    } DMD_CONTROL1;                                         /**< 0x40014104 */
     union {
         struct {
-            __IO uint32_t RSSI_THRESHOLD:8;					/**< Threshold value used to determine clear channel assessment (CCA) result.  The channel is declared busy if RSSI > threshold. Default 0xFF */
-            __IO uint32_t RSSI_OFFSET:6;					/**< Calibration constant added to the RSSI calculation.  The 6-bit field is treated as a signed value in two�s complement format with values from -32 to +31 dB. */
+            __IO uint32_t RSSI_THRESHOLD:8;                 /**< Threshold value used to determine clear channel assessment (CCA) result.  The channel is declared busy if RSSI > threshold. Default 0xFF */
+            __IO uint32_t RSSI_OFFSET:6;                    /**< Calibration constant added to the RSSI calculation.  The 6-bit field is treated as a signed value in two�s complement format with values from -32 to +31 dB. */
         } BITS;
         __IO uint32_t WORD;
-    } DMD_CONTROL2;											/**< 0x40014108 */
+    } DMD_CONTROL2;                                         /**< 0x40014108 */
     union {
         struct {
-            __I uint32_t RSSI_VALUE:8;						/**< The value is captured at the end of packet reception or at the end of ED/CCA measurements and is interpreted in dBm as follows: 00000000 -> 0127dBm (or below) ... 01111111 -> 0dBm (or above) */
-            __I uint32_t FREQUENCY_OFFSET:4;				/**< Frequency correction applied to the received packet.  The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
-            __I uint32_t ANT:1;								/**< Antenna used for reception.  The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
+            __I uint32_t RSSI_VALUE:8;                      /**< The value is captured at the end of packet reception or at the end of ED/CCA measurements and is interpreted in dBm as follows: 00000000 -> 0127dBm (or below) ... 01111111 -> 0dBm (or above) */
+            __I uint32_t FREQUENCY_OFFSET:4;                /**< Frequency correction applied to the received packet.  The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
+            __I uint32_t ANT:1;                             /**< Antenna used for reception.  The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
             __I uint32_t PAD0:3;
-            __I uint32_t RSSI_COMPONENT:4;					/**< Magnitude of the baseband digital signal (units are dB relative to A/D saturation).  The value is updated until AGC is frozen.  The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
+            __I uint32_t RSSI_COMPONENT:4;                  /**< Magnitude of the baseband digital signal (units are dB relative to A/D saturation).  The value is updated until AGC is frozen.  The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
         } BITS;
         __I uint32_t WORD;
-    } DMD_STATUS;											/**< 0x4001410C */
+    } DMD_STATUS;                                           /**< 0x4001410C */
 } DmdReg_t, *DmdReg_pt;
 
 #endif /* MACHW_MAP_H_ */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h
index 508fed1aa5c..f6e44148d32 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h
@@ -26,32 +26,32 @@
 *
 * @ingroup bsp
 @verbatim
-		 +-----------------+
-		 |                 |             ,_________________________
-		 | Private Per.    |             |PMUREG         0x4001D000|
+         +-----------------+
+         |                 |             ,_________________________
+         | Private Per.    |             |PMUREG         0x4001D000|
 0xE0000000 +-----------------+             |PADREG         0x4001C000|
-		 |                 |_____________|CLOCKREG       0x4001B000|
-		 |  PERIPHERALS    |             |RFANAREG       0x40019000|
-		 +-----------------+             |RESETREG       0x40018000|
-		 |                 |             |FLASHREG       0x40017000|
+         |                 |_____________|CLOCKREG       0x4001B000|
+         |  PERIPHERALS    |             |RFANAREG       0x40019000|
+         +-----------------+             |RESETREG       0x40018000|
+         |                 |             |FLASHREG       0x40017000|
 0x3FFF8000 |SRAM A     32K   |             |AESREG         0x40016000|
-		 +-----------------+             |ADCREG         0x40015000|
-		 |                 |             |MACHWREG       0x40014000|
-		 |SRAM B     16K   |             |RANDREG        0x40011000|
+         +-----------------+             |ADCREG         0x40015000|
+         |                 |             |MACHWREG       0x40014000|
+         |SRAM B     16K   |             |RANDREG        0x40011000|
 0x3FFF4000 +-----------------+             |CROSSBREG      0x40010000|
-		 |                 |             |RTCREG         0x4000F000|
+         |                 |             |RTCREG         0x4000F000|
 0x24000100 |SRAM DMA    7B   |             |GPIOREG        0x4000C000|
-		 +-----------------+             |PWMREG         0x4000B000|
+         +-----------------+             |PWMREG         0x4000B000|
 0x24000000 |SRAM MAC  256B   |             |WDTREG         0x4000A000|
-		 +-----------------+             |UARTREG        0x40008000|
-		 |          320K   |             |I2CREG         0x40007000|
+         +-----------------+             |UARTREG        0x40008000|
+         |          320K   |             |I2CREG         0x40007000|
 0x00102000 |FLASHB           |             |SPIREG         0x40006000|
 0x00100000 |FLASHB Inf Block |             |UARTREG        0x40005000|
-		 +-----------------+             |TIM2REG        0x40002000|
-		 |          320K   |             |TIM1REG        0x40001000|
+         +-----------------+             |TIM2REG        0x40002000|
+         |          320K   |             |TIM1REG        0x40001000|
 0x00002000 |FLASHA           |             |TIM0REG        0x40000000|
 0x00000000 |FLASHA Inf Block |             '`''''''''''''''''''''''''
-		 '`'''''''''''''''''
+         '`'''''''''''''''''
 
 @endverbatim
 */
@@ -117,52 +117,52 @@
 /** MAC MATCH HW Registers Offset */
 #define MACMATCHREG_BASE    ((uint32_t)0x24000100)
 /** MAC MATCH HW Structure Overlay */
-#define MACMATCHREG			((volatile uint8_t *)MACMATCHREG_BASE)
+#define MACMATCHREG         ((volatile uint8_t *)MACMATCHREG_BASE)
 
 /** MAC RX HW Registers Offset */
-#define MACRXREG_BASE     	((uint32_t)0x24000080)
+#define MACRXREG_BASE       ((uint32_t)0x24000080)
 /** MAC RX HW Structure Overlay */
-#define MACRXREG			((volatile uint8_t *)MACRXREG_BASE)
+#define MACRXREG            ((volatile uint8_t *)MACRXREG_BASE)
 
 /** MAC TX HW Registers Offset */
-#define MACTXREG_BASE     	((uint32_t)0x24000000)
+#define MACTXREG_BASE       ((uint32_t)0x24000000)
 /** MAC TX HW Structure Overlay */
-#define MACTXREG			((volatile uint8_t *)MACTXREG_BASE)
+#define MACTXREG            ((volatile uint8_t *)MACTXREG_BASE)
 
 /** TEST Interface for flash HW Registers Offset */
 #define TESTNVMREG_BASE     ((uint32_t)0x4001F140)
 /** TEST Interface for flash HW Structure Overlay */
-#define TESTNVMREG			((TestNvmReg_pt)TESTNVMREG_BASE)
+#define TESTNVMREG          ((TestNvmReg_pt)TESTNVMREG_BASE)
 
 /** Test Interface for digital HW Registers Offset */
 #define TESTDIGREG_BASE     ((uint32_t)0x4001F100)
 /** Test Interface for digital HW Structure Overlay */
-#define TESTDIGREG			((TestDigReg_pt)TESTDIGREG_BASE)
+#define TESTDIGREG          ((TestDigReg_pt)TESTDIGREG_BASE)
 
 /** Test Interface HW Registers Offset */
 #define TESTREG_BASE        ((uint32_t)0x4001F000)
 /** Test Interface HW Structure Overlay */
-#define TESTREG				((TestReg_pt)TESTREG_BASE)
+#define TESTREG             ((TestReg_pt)TESTREG_BASE)
 
 /** Device option HW Registers Offset */
-#define DEVOPTREG_BASE     	((uint32_t)0x4001E000)
+#define DEVOPTREG_BASE      ((uint32_t)0x4001E000)
 /** MAC TX HW Structure Overlay */
-#define DEVOPTREG			((volatile uint32_t *)DEVOPTREG_BASE)
+#define DEVOPTREG           ((volatile uint32_t *)DEVOPTREG_BASE)
 
 /** PMU HW Registers Offset */
 #define PMUREG_BASE         ((uint32_t)0x4001D000)
 /** PMU HW Structure Overlay */
-#define PMUREG				((PmuReg_pt)PMUREG_BASE)
+#define PMUREG              ((PmuReg_pt)PMUREG_BASE)
 
 /** PAD Control HW Registers Offset */
 #define PADREG_BASE         ((uint32_t)0x4001C000)
 /** PAD Control HW Structure Overlay */
-#define PADREG				((PadReg_pt)PADREG_BASE)
+#define PADREG              ((PadReg_pt)PADREG_BASE)
 
 /** Clock Control HW Registers Offset */
-#define CLOCKREG_BASE		((uint32_t)0x4001B000)
+#define CLOCKREG_BASE       ((uint32_t)0x4001B000)
 /** Clock Control HW Structure Overlay */
-#define CLOCKREG			((ClockReg_pt)CLOCKREG_BASE)
+#define CLOCKREG            ((ClockReg_pt)CLOCKREG_BASE)
 
 /** Analogue Trim HW Registers Offset */
 #define RFANATRIMREG_BASE   ((uint32_t)0x40019080)
@@ -170,29 +170,29 @@
 #define RFANATRIMREG        ((RfAnaTrimReg_pt)RFANATRIMREG_BASE)
 
 /** Analogue RF HW Registers Offset */
-#define RFANAREG_BASE		((uint32_t)0x40019000)
+#define RFANAREG_BASE       ((uint32_t)0x40019000)
 /** Analogue RF HW Structure Overlay */
-#define RFANAREG			((RfAnaReg_pt)RFANAREG_BASE)
+#define RFANAREG            ((RfAnaReg_pt)RFANAREG_BASE)
 
 /** Reset Cause HW Registers Offset */
-#define RESETREG_BASE		((uint32_t)0x40018000)
+#define RESETREG_BASE       ((uint32_t)0x40018000)
 /** Reset Cause HW Structure Overlay */
-#define RESETREG			((ResetReg_pt)RESETREG_BASE)
+#define RESETREG            ((ResetReg_pt)RESETREG_BASE)
 
 /** FLASH Control HW Registers Offset */
-#define FLASHREG_BASE		((uint32_t)0x40017000)
+#define FLASHREG_BASE       ((uint32_t)0x40017000)
 /** FLASH Control HW Structure Overlay */
-#define FLASHREG			((FlashReg_pt)FLASHREG_BASE)
+#define FLASHREG            ((FlashReg_pt)FLASHREG_BASE)
 
 /** AES Encryption HW Registers Offset */
-#define AESREG_BASE			((uint32_t)0x40016000)
+#define AESREG_BASE         ((uint32_t)0x40016000)
 /** AES Encryption HW Structure Overlay */
-#define AESREG				((AesReg_pt)AESREG_BASE)
+#define AESREG              ((AesReg_pt)AESREG_BASE)
 
 /** SAR ADC HW Registers Offset */
-#define ADCREG_BASE			((uint32_t)0x40015000)
+#define ADCREG_BASE         ((uint32_t)0x40015000)
 /** SAR ADC HW Structure Overlay */
-#define ADCREG				((AdcReg_pt)ADCREG_BASE)
+#define ADCREG              ((AdcReg_pt)ADCREG_BASE)
 
 /** Demodulator HW Registers Offset */
 #define DMDREG_BASE         ((uint32_t)0x40014100)
@@ -200,85 +200,85 @@
 #define DMDREG              ((DmdReg_pt)DMDREG_BASE)
 
 /** MAC Control HW Registers Offset */
-#define MACHWREG_BASE		((uint32_t)0x40014000)
+#define MACHWREG_BASE       ((uint32_t)0x40014000)
 /** MAC Control HW Structure Overlay */
-#define MACHWREG			((MacHwReg_pt)MACHWREG_BASE)
+#define MACHWREG            ((MacHwReg_pt)MACHWREG_BASE)
 
 /** Random Generator HW Registers Offset */
-#define RANDREG_BASE		((uint32_t)0x40011000)
+#define RANDREG_BASE        ((uint32_t)0x40011000)
 /** Random Generator HW Structure Overlay */
-#define RANDREG				((RandReg_pt)RANDREG_BASE)
+#define RANDREG             ((RandReg_pt)RANDREG_BASE)
 
 /** Cross Bar HW Registers Offset */
-#define CROSSBREG_BASE		((uint32_t)0x40010000)
+#define CROSSBREG_BASE      ((uint32_t)0x40010000)
 /** Cross Bar HW Structure Overlay */
-#define CROSSBREG			((CrossbReg_pt)CROSSBREG_BASE)
+#define CROSSBREG           ((CrossbReg_pt)CROSSBREG_BASE)
 
 /** Real Time Clock HW Registers Offset */
-#define RTCREG_BASE			((uint32_t)0x4000F000)
+#define RTCREG_BASE         ((uint32_t)0x4000F000)
 /** Real Time Clock HW Structure Overlay */
-#define RTCREG				((RtcReg_pt)RTCREG_BASE)
+#define RTCREG              ((RtcReg_pt)RTCREG_BASE)
 
 /** GPIO HW Registers Offset */
-#define GPIOREG_BASE		((uint32_t)0x4000C000)
+#define GPIOREG_BASE        ((uint32_t)0x4000C000)
 /** GPIO HW Structure Overlay */
-#define GPIOREG				((GpioReg_pt)GPIOREG_BASE)
+#define GPIOREG             ((GpioReg_pt)GPIOREG_BASE)
 
 /** PWM HW Registers Offset */
-#define PWMREG_BASE			((uint32_t)0x4000B000)
+#define PWMREG_BASE         ((uint32_t)0x4000B000)
 /** PWM HW Structure Overlay */
-#define PWMREG				((PwmReg_pt)PWMREG_BASE)
+#define PWMREG              ((PwmReg_pt)PWMREG_BASE)
 
 /** Watchdog Timer HW Registers Offset */
-#define WDTREG_BASE			((uint32_t)0x4000A000)
+#define WDTREG_BASE         ((uint32_t)0x4000A000)
 /** Watchdog Timer HW Structure Overlay */
-#define WDTREG				((WdtReg_pt)WDTREG_BASE)
+#define WDTREG              ((WdtReg_pt)WDTREG_BASE)
 
 /** UART 2 HW Registers Offset */
-#define UART2REG_BASE		((uint32_t)0x40008000)
+#define UART2REG_BASE       ((uint32_t)0x40008000)
 /** UART 2 HW Structure Overlay */
-#define UART2REG		    ((Uart16C550Reg_pt)UART2REG_BASE)
+#define UART2REG            ((Uart16C550Reg_pt)UART2REG_BASE)
 
 /** I2C HW Registers Offset */
-#define I2C1REG_BASE			((uint32_t)0x40007000)
+#define I2C1REG_BASE        ((uint32_t)0x40007000)
 /** I2C HW Structure Overlay */
-#define I2C1REG				((I2cIpc7208Reg_pt)I2C1REG_BASE)
+#define I2C1REG             ((I2cIpc7208Reg_pt)I2C1REG_BASE)
 
 /** SPI HW Registers Offset */
-#define SPI1REG_BASE			((uint32_t)0x40006000)
+#define SPI1REG_BASE        ((uint32_t)0x40006000)
 /** SPI HW Structure Overlay */
-#define SPI1REG				((SpiIpc7207Reg_pt)SPI1REG_BASE)
+#define SPI1REG             ((SpiIpc7207Reg_pt)SPI1REG_BASE)
 
 /** UART1 HW Registers Offset */
-#define UART1REG_BASE		((uint32_t)0x40005000)
+#define UART1REG_BASE       ((uint32_t)0x40005000)
 /** UART1 HW Structure Overlay */
-#define UART1REG			((Uart16C550Reg_pt)UART1REG_BASE)
+#define UART1REG            ((Uart16C550Reg_pt)UART1REG_BASE)
 
-#define UARTREG_BASES  { UART1REG_BASE, UART2REG_BASE}
+#define UARTREG_BASES       { UART1REG_BASE, UART2REG_BASE}
 
 /** Timer 2 HW Registers Offset */
-#define TIM2REG_BASE		((uint32_t)0x40002000)
+#define TIM2REG_BASE        ((uint32_t)0x40002000)
 /** Timer 2 HW Structure Overlay */
-#define TIM2REG				((TimerReg_pt)TIM2REG_BASE)
+#define TIM2REG             ((TimerReg_pt)TIM2REG_BASE)
 
 /** Timer 1 HW Registers Offset */
-#define TIM1REG_BASE		((uint32_t)0x40001000)
+#define TIM1REG_BASE        ((uint32_t)0x40001000)
 /** Timer 1 HW Structure Overlay */
-#define TIM1REG				((TimerReg_pt)TIM1REG_BASE)
+#define TIM1REG             ((TimerReg_pt)TIM1REG_BASE)
 
 /** Timer 0 HW Registers Offset */
-#define TIM0REG_BASE		((uint32_t)0x40000000)
+#define TIM0REG_BASE        ((uint32_t)0x40000000)
 /** Timer 0 HW Structure Overlay */
-#define TIM0REG				((TimerReg_pt)TIM0REG_BASE)
+#define TIM0REG             ((TimerReg_pt)TIM0REG_BASE)
 
 /** I2C2 HW Registers Offset */
-#define I2C2REG_BASE			((uint32_t)0x4000D000)
+#define I2C2REG_BASE        ((uint32_t)0x4000D000)
 /** I2C2 HW Structure Overlay */
-#define I2C2REG				((I2cIpc7208Reg_pt)I2C2REG_BASE)
+#define I2C2REG             ((I2cIpc7208Reg_pt)I2C2REG_BASE)
 
 /** SPI2 HW Registers Offset */
-#define SPI2REG_BASE			((uint32_t)0x40009000)
+#define SPI2REG_BASE        ((uint32_t)0x40009000)
 /** SPI2 HW Structure Overlay */
-#define SPI2REG				((SpiIpc7207Reg_pt)SPI2REG_BASE)
+#define SPI2REG             ((SpiIpc7207Reg_pt)SPI2REG_BASE)
 
 #endif /*_MEMORY_MAP_H_*/
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c
index 2487de64132..f4dfc64eed4 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c
@@ -158,15 +158,15 @@ void fPmuInit()
     SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
 
     /** Set regulator timings */
-    PMUREG->FVDD_TSETTLE 	= 160;
-    PMUREG->FVDD_TSTARTUP 	= 400;
+    PMUREG->FVDD_TSETTLE     = 160;
+    PMUREG->FVDD_TSTARTUP    = 400;
 
     /** Keep SRAMA & SRAMB powered in coma mode */
     PMUREG->CONTROL.BITS.SRAMA = False;
     PMUREG->CONTROL.BITS.SRAMB = False;
 
-    PMUREG->CONTROL.BITS.N1V1 = True;	/* Enable ACTIVE mode switching regulator */
-    PMUREG->CONTROL.BITS.C1V1 = True;	/* Enable COMA mode switching regulator */
+    PMUREG->CONTROL.BITS.N1V1 = True;    /* Enable ACTIVE mode switching regulator */
+    PMUREG->CONTROL.BITS.C1V1 = True;    /* Enable COMA mode switching regulator */
 
     /** Disable the clock for PMU peripheral device, all settings are done */
     CLOCK_DISABLE(CLOCK_PMU);
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c
index cc840d8215c..784ea31bc1c 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c
@@ -76,11 +76,11 @@ void fI2cInit(i2c_t *obj,PinName sda,PinName scl)
 
     /* enable interrupt associated with the device */
     if(obj->membase == I2C1REG) {
-        CLOCK_ENABLE(CLOCK_I2C); 			/* enable i2c peripheral */
+        CLOCK_ENABLE(CLOCK_I2C);             /* enable i2c peripheral */
         NVIC_ClearPendingIRQ(I2C_IRQn);
         NVIC_EnableIRQ(I2C_IRQn);
     } else {
-        CLOCK_ENABLE(CLOCK_I2C2); 			/* enable i2c peripheral */
+        CLOCK_ENABLE(CLOCK_I2C2);            /* enable i2c peripheral */
         NVIC_ClearPendingIRQ(I2C2_IRQn);
         NVIC_EnableIRQ(I2C2_IRQn);
     }
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c
index b5f6a159dda..9663cd66bea 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c
@@ -60,50 +60,12 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
     fRtcSetInterrupt(timestamp);
 }
 
-/*Return the time that gets cut off when you return just a 32 bit  us resolution number */
-uint32_t lp_ticker_get_overflows_counter(void)
-{
-    /* To check; do we need an counter in software in RTC to find overflows */
-    uint64_t now = fRtcRead();
-    uint32_t overflow = (now & 0xFFFFFFFF00000000) >> 32;
-    return overflow;
-}
-
-/* Return the RTC Match counter contents */
-uint32_t lp_ticker_get_compare_match()
-{
-    /* read the alarms and convert to us */
-    uint16_t sub_second_alarm = RTCREG->SUB_SECOND_ALARM;
-    uint32_t second_alarm = RTCREG->SECOND_ALARM;
-    uint64_t alarm_us = (uint64_t)((((float)sub_second_alarm / RTC_CLOCK_HZ) * RTC_SEC_TO_US) +
-                                   (second_alarm * RTC_SEC_TO_US));
-    /* TODO truncating to 32 bits */
-    return (uint32_t)(alarm_us & 0xFFFFFFFF);
-}
-
-/* sleep until alarm */
-void lp_ticker_sleep_until(uint32_t now, uint32_t time)
-{
-    /* Set the interrupt */
-    lp_ticker_set_interrupt(time);
-
-    /* Go to sleep */
-    sleep_t obj;
-    obj.SleepType 	 = SLEEP_TYPE_NONE;
-    obj.timeToSleep = time - now;
-
-    mbed_enter_sleep(&obj);
-    /* TBD: This is dummy exit for now; once the entered sleep it should be
-    removed and sleep exit should happen through interrupt */
-    mbed_exit_sleep(&obj);
-}
-
 /** Disable low power ticker interrupt
  *
  */
 void lp_ticker_disable_interrupt(void)
 {
-    /* TODO : This is an empty implementation for now */
+    fRtcDisableInterrupt();
 }
 
 /** Clear the low power ticker interrupt
@@ -111,7 +73,7 @@ void lp_ticker_disable_interrupt(void)
  */
 void lp_ticker_clear_interrupt(void)
 {
-    /* TODO : This is an empty implementation for now */
+    fRtcClearInterrupt();
 }
 
 #endif /* DEVICE_LOWPOWERTIMER */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c
index 17e842ef4e5..42441d5d8f1 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c
@@ -58,79 +58,78 @@ void fSpiInit(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
     SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
     SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
     SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SSEL);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
 
     SPIName spi_data_1 = (SPIName)pinmap_merge(spi_mosi, spi_miso);
     SPIName spi_data_2 = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
 
-    obj->membase 	 = (SpiIpc7207Reg_pt)pinmap_merge(spi_data_1, spi_data_2);
+    obj->membase      = (SpiIpc7207Reg_pt)pinmap_merge(spi_data_1, spi_data_2);
     MBED_ASSERT((int)obj->membase != NC);
 
     /* Check device to be activated */
     if(obj->membase == SPI1REG) {
         /* SPI 1 selected */
-        CLOCK_ENABLE(CLOCK_SPI); 		/* Enable clock */
+        CLOCK_ENABLE(CLOCK_SPI);         /* Enable clock */
     } else {
         /* SPI 2 selected */
-        CLOCK_ENABLE(CLOCK_SPI2);		/* Enable clock */
+        CLOCK_ENABLE(CLOCK_SPI2);        /* Enable clock */
     }
 
+    CLOCK_ENABLE(CLOCK_CROSSB);
     /* Cross bar setting: Map GPIOs to SPI */
     pinmap_pinout(sclk, PinMap_SPI_SCLK);
     pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(miso, PinMap_SPI_SSEL);/* TODO Need to implement as per morpheus */
 
-    /* TODO Do we need GPIO direction settings done here or at init phase? */
-    /* GPIO config */
+    /* Configure GPIO Direction  */
     CLOCK_ENABLE(CLOCK_GPIO);
-    GPIOREG->W_OUT |= ((0x1 << sclk) | (0x1 << mosi)); 	/* Set pins as output */
-    GPIOREG->W_IN  |= (0x1 << miso); 					/* Set pin as input */
+    GPIOREG->W_OUT |= ((True << sclk) | (True << mosi) | (True << ssel));    /* Set pins as output */
+    GPIOREG->W_IN  |= (True << miso);    /* Set pin as input */
 
-    pin_mode(sclk, PushPullNoPull);
-    pin_mode(mosi, PushPullPullUp);
-    pin_mode(miso, OpenDrainPullUp);
+    /* Pad settings */
+    CLOCK_ENABLE(CLOCK_PAD);
+    pin_mode(sclk, PushPullPullDown);
+    pin_mode(mosi, PushPullPullDown);
 
     /* PAD drive strength */
     PadReg_t *padRegOffset = (PadReg_t*)(PADREG_BASE + (sclk * PAD_REG_ADRS_BYTE_SIZE));
-    CLOCK_ENABLE(CLOCK_PAD);
-    padRegOffset->PADIO0.BITS.POWER = 1; /* sclk: Drive strength */
-    padRegOffset->PADIO1.BITS.POWER = 1; /* mosi: Drive strength */
-    padRegOffset->PADIO2.BITS.POWER = 1; /* miso: Drive strength */
+    padRegOffset->PADIO0.BITS.POWER = True; /* sclk: Drive strength */
+    padRegOffset->PADIO1.BITS.POWER = True; /* mosi: Drive strength */
+    if(miso != NC) {
+        pinmap_pinout(miso, PinMap_SPI_MISO); /* Cross bar settings */
+        pin_mode(miso, OpenDrainNoPull);      /* Pad setting */
+        padRegOffset->PADIO2.BITS.POWER = True;  /* miso: Drive strength */
+    }
+    if(ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);         /* Cross bar settings */
+        pin_mode(ssel, PushPullPullUp);               /* Pad setting */
+        padRegOffset->PADIO3.BITS.POWER      = True;      /* ssel: Drive strength */
+        SPI1REG->SLAVE_SELECT.BITS.SS_ENABLE = SPI_SLAVE_SELECT_NORM_BEHAVE; /* Slave select: Normal behavior */
+    }
     CLOCK_DISABLE(CLOCK_PAD);
+    CLOCK_DISABLE(CLOCK_GPIO);
+    CLOCK_DISABLE(CLOCK_CROSSB);
 
-    /* disable/reset the spi port */
-    obj->membase->CONTROL.BITS.ENABLE = False;
+    /* disable/reset the spi port: Clear control register*/
+    obj->membase->CONTROL.WORD = False;
 
     /* set default baud rate to 1MHz */
-    clockDivisor 		= ((fClockGetPeriphClockfrequency() / 1000000) >> 1) - 1;
-    obj->membase->FDIV  = clockDivisor;
+    clockDivisor         = ((fClockGetPeriphClockfrequency() / SPI_DEFAULT_SPEED) >> True) - True;
+    obj->membase->FDIV   = clockDivisor;
 
     /* set tx/rx fifos watermarks */ /* TODO water mark level 1 byte ?*/
-    obj->membase->TX_WATERMARK = 1;
-    obj->membase->RX_WATERMARK = 1;
+    obj->membase->TX_WATERMARK = True;
+    obj->membase->RX_WATERMARK = True;
 
     /* DIsable and clear IRQs */ /* TODO sync api, do not need irq ?*/
     obj->membase->IRQ_ENABLE = False;
-    obj->membase->IRQ_CLEAR  = 0xFF; /* Clear all */
+    obj->membase->IRQ_CLEAR  = SPI_BYTE_MASK; /* Clear all */
 
     /* configure slave select */
-    obj->membase->SLAVE_SELECT.BITS.SS_ENABLE = False;
-    obj->membase->SLAVE_SELECT.BITS.SS_BURST  = True;
-    obj->membase->SLAVE_SELECT_POLARITY 	  = False;
-
-    /* set control register parameters */
-    obj->membase->CONTROL.BITS.WORD_WIDTH 	  = False;	/* 8 bits */
-    obj->membase->CONTROL.BITS.MODE 	  	  = 1; 		/* master */
-    obj->membase->CONTROL.BITS.CPOL 	  	  = 0; 		/* CPOL = 0, Idle low */
-    obj->membase->CONTROL.BITS.CPHA 	  	  = 0; 		/* CPHA = 0, First transmit occurs before first edge of SCLK*/
-    obj->membase->CONTROL.BITS.ENDIAN 		  = 0; 		/* Little endian */
-    obj->membase->CONTROL.BITS.SAMPLING_EDGE  = False; 	/* Sample incoming data on opposite edge of SCLK from when outgoing data is driven */
-
-    /*	SPI1REG->SLAVE_SELECT.BITS.SS_ENABLE = 0; Slave select TODO do we need? */
-
-    /* enable the spi port */
-    obj->membase->CONTROL.BITS.ENABLE = True;
+    obj->membase->SLAVE_SELECT.WORD = SPI_SLAVE_SELECT_DEFAULT;
+    obj->membase->SLAVE_SELECT_POLARITY = False;
+
+    /* Configure control register parameters: 8 bits, master, CPOL = 0, Idle low. CPHA = 0, First transmit occurs before first edge of SCLK. MSB first. Sample incoming data on opposite edge of SCLK from when outgoing data is driven. enable the spi port */
+    obj->membase->CONTROL.WORD = SPI_DEFAULT_CONFIG;
 }
 
 /** Close a spi device.
@@ -161,12 +160,12 @@ int fSpiWriteB(spi_t *obj, uint32_t const buf)
 {
     int byte;
 
-    while((obj->membase->STATUS.BITS.TX_FULL == 1) && (obj->membase->STATUS.BITS.RX_FULL == 1)); /* Wait till Tx/Rx status is full */
+    while((obj->membase->STATUS.BITS.TX_FULL == True) && (obj->membase->STATUS.BITS.RX_FULL == True)); /* Wait till Tx/Rx status is full */
     obj->membase->TX_DATA = buf;
 
-    while (obj->membase->STATUS.BITS.RX_EMPTY == 1); /* Wait till Receive status is empty */
+    while (obj->membase->STATUS.BITS.RX_EMPTY == True); /* Wait till Receive status is empty */
     byte = obj->membase->RX_DATA;
     return byte;
 }
 
-#endif /* DEVICE_SPI */
+#endif /* DEVICE_SPI */
\ No newline at end of file
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c
index 16afcbcf930..8ba37597753 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c
@@ -78,17 +78,17 @@ static void us_timer_init(void)
     TIM0REG->LOAD = 0xFFFF;
 
     /* set timer prescale 32 (1 us), mode & enable */
-    TIM0REG->CONTROL.WORD = ((CLK_DIVIDER_32		<< TIMER_PRESCALE_BIT_POS) |
-                             (TIME_MODE_PERIODIC	<< TIMER_MODE_BIT_POS) |
-                             (TIMER_ENABLE_BIT 	<< TIMER_ENABLE_BIT_POS));
+    TIM0REG->CONTROL.WORD = ((CLK_DIVIDER_32        << TIMER_PRESCALE_BIT_POS) |
+                             (TIME_MODE_PERIODIC    << TIMER_MODE_BIT_POS) |
+                             (TIMER_ENABLE_BIT      << TIMER_ENABLE_BIT_POS));
 
     /* Ticker init */
     /* load timer value */
     TIM1REG->LOAD = 0xFFFF;
 
     /* set timer prescale 32 (1 us), mode & enable */
-    TIM1REG->CONTROL.WORD = ((CLK_DIVIDER_32		<< TIMER_PRESCALE_BIT_POS) |
-                             (TIME_MODE_PERIODIC	<< TIMER_MODE_BIT_POS));
+    TIM1REG->CONTROL.WORD = ((CLK_DIVIDER_32        << TIMER_PRESCALE_BIT_POS) |
+                             (TIME_MODE_PERIODIC    << TIMER_MODE_BIT_POS));
 
     /* Register & enable interrupt associated with the timer */
     NVIC_SetVector(Tim0_IRQn,(uint32_t)us_timer_isr);
@@ -115,17 +115,17 @@ uint32_t us_ticker_read()
     }
 
     /* Get the current tick from the hw and sw timers */
-    tim0cval = TIM0REG->VALUE; 		/* read current time */
-    retval = (0xFFFF - tim0cval);	/* subtract down count */
+    tim0cval = TIM0REG->VALUE;         /* read current time */
+    retval = (0xFFFF - tim0cval);      /* subtract down count */
 
     NVIC_DisableIRQ(Tim0_IRQn);
     if (TIM0REG->CONTROL.BITS.INT) {
         TIM0REG->CLEAR = 0;
         msb_counter++;
-        tim0cval = TIM0REG->VALUE;	/* read current time again after interrupt */
+        tim0cval = TIM0REG->VALUE;    /* read current time again after interrupt */
         retval = (0xFFFF - tim0cval);
     }
-    retval |= msb_counter << 16;	/* add software bits */
+    retval |= msb_counter << 16;      /* add software bits */
     NVIC_EnableIRQ(Tim0_IRQn);
     return retval;
 }
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h
index 915197ef3dc..b58c02c3d36 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h
@@ -50,9 +50,9 @@ typedef enum {
 } FlowControl_1;
 
 struct serial_s {
-    Uart16C550Reg_pt	UARTREG;
-    FlowControl_1		FlowCtrl;
-    IRQn_Type			IRQType;
+    Uart16C550Reg_pt    UARTREG;
+    FlowControl_1       FlowCtrl;
+    IRQn_Type           IRQType;
     int index;
 };
 
@@ -68,18 +68,18 @@ typedef struct _gpio_t {
  * with the sleep API implementation
  */
 typedef struct sleep_s {
-    uint32_t timeToSleep;	/* 0: Use sleep type variable; Noz-zero: Selects sleep type based on duration using table 1. sleep below */
-    uint8_t	 SleepType;		/* 0: Sleep; 1: DeepSleep; 2: Coma */
+    uint32_t timeToSleep;    /* 0: Use sleep type variable to select low power mode; Noz-zero: Selects sleep type based on timeToSleep duration using table 1. sleep below */
+    uint8_t     SleepType;   /* 0: Sleep; 1: DeepSleep; 2: Coma */
 } sleep_t;
 
 /* Table 1. Sleep
-	 ___________________________________________________________________________________
-	|	Sleep duration													|  Sleep Type	|
-	|-------------------------------------------------------------------|---------------|
-	|  > Zero AND <= SLEEP_DURATION_SLEEP_MAX							|  sleep		|
-	|  > SLEEP_DURATION_SLEEP_MAX AND <= SLEEP_DURATION_DEEPSLEEP_MAX	|  deepsleep	|
-	|  > SLEEP_DURATION_DEEPSLEEP_MAX									|  coma			|
-	|___________________________________________________________________|_______________|
+     ___________________________________________________________________________________
+    |    Sleep duration                                                 |  Sleep Type   |
+    |-------------------------------------------------------------------|---------------|
+    |  > Zero AND <= SLEEP_DURATION_SLEEP_MAX                           |  sleep        |
+    |  > SLEEP_DURATION_SLEEP_MAX AND <= SLEEP_DURATION_DEEPSLEEP_MAX   |  deepsleep    |
+    |  > SLEEP_DURATION_DEEPSLEEP_MAX                                   |  coma         |
+    |___________________________________________________________________|_______________|
 
 */
 
@@ -92,25 +92,25 @@ struct gpio_irq_s {
 typedef struct {
 
     /* options to configure the ADC */
-    uint8_t 			interruptConfig;    	/**< 1= interrupt Enable  0=Interrupt Disable  */
-    uint8_t 			PrescaleVal;			/**< Prescaler:    Sets the converter clock frequency.  Fclk = 32 MHz/(prescaler + 1) where prescaler is the value of this register segment. The minimum tested value is 07 (4 MHz clock) */
-    uint8_t 			measurementType;   	/**< 1= Absolute 0= Differential */
-    uint8_t 			mode;			  	/**< 1= Continuous Conversion 0= Single Shot  */
-    uint8_t 			referenceCh;		  	/**< Selects 1 to 8 channels for reference channel  */
-    uint8_t 			convCh;            	/**< Selects 1 or 8 channels to do a conversion on.*/
-    uint8_t 			inputScale;		  	/**< Sets the input scale, 000 ? 1.0, 001 ? 0.6923, 010 ? 0.5294, 011 ? 0.4286, 100 ? 0.3600, 101 ? 0.3103, 110 ? 0.2728, 111 ? 0.2432 */
-    uint8_t 			samplingTime;	  	/**< Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
-    uint8_t 			WarmUpTime;		  	/**< The number of converter clock cycles that the state machine dwells in the warm or warm_meas state */
-    uint16_t			samplingRate;      	/**< Sets the sample rate in units of PCLKperiod * (Prescale + 1).  */
+    uint8_t             interruptConfig;       /**< 1= interrupt Enable  0=Interrupt Disable  */
+    uint8_t             PrescaleVal;           /**< Prescaler:    Sets the converter clock frequency.  Fclk = 32 MHz/(prescaler + 1) where prescaler is the value of this register segment. The minimum tested value is 07 (4 MHz clock) */
+    uint8_t             measurementType;       /**< 1= Absolute 0= Differential */
+    uint8_t             mode;                  /**< 1= Continuous Conversion 0= Single Shot  */
+    uint8_t             referenceCh;           /**< Selects 1 to 8 channels for reference channel  */
+    uint8_t             convCh;                /**< Selects 1 or 8 channels to do a conversion on.*/
+    uint8_t             inputScale;            /**< Sets the input scale, 000 ? 1.0, 001 ? 0.6923, 010 ? 0.5294, 011 ? 0.4286, 100 ? 0.3600, 101 ? 0.3103, 110 ? 0.2728, 111 ? 0.2432 */
+    uint8_t             samplingTime;          /**< Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
+    uint8_t             WarmUpTime;            /**< The number of converter clock cycles that the state machine dwells in the warm or warm_meas state */
+    uint16_t            samplingRate;          /**< Sets the sample rate in units of PCLKperiod * (Prescale + 1).  */
 
 } analog_config_s;
 
 struct analogin_s {
 
-    analog_config_s		*adcConf;
-    AdcReg_pt			 adcReg;
-    PinName         	 pin;
-    uint8_t				 pinFlag;
+    analog_config_s      *adcConf;
+    AdcReg_pt             adcReg;
+    PinName               pin;
+    uint8_t               pinFlag;
 };
 
 struct pwmout_s {
@@ -142,55 +142,55 @@ typedef enum {
 } spi_clockPhase_t, *spi_clockPhase_pt;
 
 struct spi_s {
-    SpiIpc7207Reg_pt membase;		/* Register address */
-    IRQn_Type irq;				/* IRQ number of the IRQ associated to the device. */
-    uint8_t irqEnable;			/* IRQ enables for 8 IRQ sources:
-	 	 	 	 	 	 	 	 	 * - bit 7 = Receive FIFO Full
-	 	 	 	 	 	 	 	 	 * - bit 6 = Receive FIFO 'Half' Full (watermark level)
-	 	 	 	 	 	 	 	 	 * - bit 5 = Receive FIFO Not Empty
-	 	 	 	 	 	 	 	 	 * - bit 4 = Transmit FIFO Not Full
-	 	 	 	 	 	 	 	 	 * - bit 3 = Transmit FIFO 'Half' Empty (watermark level)
-	 	 	 	 	 	 	 	 	 * - bit 2 = Transmit FIFO Empty
-	 	 	 	 	 	 	 	 	 * - bit 1 = Transfer Error
-	 	 	 	 	 	 	 	 	 * - bit 0 = ssIn (conditionally inverted and synchronized to PCLK)
-									 * (unused option in current implementation / irq 6 and 7 used) */
-    uint8_t slaveSelectEnable;	/* Slave Select enables (x4):
-									* - 0 (x4) = Slave select enable
-									* - 1 (x4) = Slave select disable */
-    uint8_t slaveSelectBurst;	/* Slave Select burst mode:
-									* - NO_BURST_MODE = Burst mode disable
-									* - BURST_MODE = Burst mode enable */
-    uint8_t slaveSelectPolarity;/* Slave Select polarity (x4) for up to 4 slaves:
-									* - 0 (x4) = Slave select is active low
-									* - 1 (x4) = Slave select is active high */
-    uint8_t txWatermark;		/* Transmit FIFO Watermark: Defines level of RX Half Full Flag
-	 	 	 	 	 	 	 	 	* - Value between 1 and 15
-	 	 	 	 	 	 	 	 	* (unused option in current implementation / not txWatermark irq used) */
-    uint8_t rxWatermark;		/* Receive FIFO Watermark: Defines level of TX Half Full Flag:
-	 	 	 	 	 	 	 	 	* - Value between 1 and 15
-	 	 	 	 	 	 	 	 	* * (unused option in current implementation / rxWatermark fixed to 1) */
+    SpiIpc7207Reg_pt membase;     /* Register address */
+    IRQn_Type irq;                /* IRQ number of the IRQ associated to the device. */
+    uint8_t irqEnable;            /* IRQ enables for 8 IRQ sources:
+                                             * - bit 7 = Receive FIFO Full
+                                             * - bit 6 = Receive FIFO 'Half' Full (watermark level)
+                                             * - bit 5 = Receive FIFO Not Empty
+                                             * - bit 4 = Transmit FIFO Not Full
+                                             * - bit 3 = Transmit FIFO 'Half' Empty (watermark level)
+                                             * - bit 2 = Transmit FIFO Empty
+                                             * - bit 1 = Transfer Error
+                                             * - bit 0 = ssIn (conditionally inverted and synchronized to PCLK)
+                                     * (unused option in current implementation / irq 6 and 7 used) */
+    uint8_t slaveSelectEnable;    /* Slave Select enables (x4):
+                                    * - 0 (x4) = Slave select enable
+                                    * - 1 (x4) = Slave select disable */
+    uint8_t slaveSelectBurst;     /* Slave Select burst mode:
+                                    * - NO_BURST_MODE = Burst mode disable
+                                    * - BURST_MODE = Burst mode enable */
+    uint8_t slaveSelectPolarity;  /* Slave Select polarity (x4) for up to 4 slaves:
+                                    * - 0 (x4) = Slave select is active low
+                                    * - 1 (x4) = Slave select is active high */
+    uint8_t txWatermark;          /* Transmit FIFO Watermark: Defines level of RX Half Full Flag
+                                            * - Value between 1 and 15
+                                            * (unused option in current implementation / not txWatermark irq used) */
+    uint8_t rxWatermark;          /* Receive FIFO Watermark: Defines level of TX Half Full Flag:
+                                            * - Value between 1 and 15
+                                            * * (unused option in current implementation / rxWatermark fixed to 1) */
     spi_ipc7207_endian_t endian; /* Bits endianness:
-									* - LITTLE_ENDIAN = LSB first
-									* - BIG_ENDIAN = MSB first */
-    uint8_t samplingEdge;		/* SDI sampling edge (relative to SDO sampling edge):
-									* - 0 = opposite to SDO sampling edge
-									* - 1 = same as SDO sampling edge */
-    uint32_t baudrate; 					/* The expected baud rate. */
-    spi_clockPolarity_t clockPolarity; 	/* The clock polarity (active high or low). */
-    spi_clockPhase_t clockPhase; 		/* The clock phase (sample on rising or falling edge). */
-    uint8_t wordSize; 					/* The size word size in number of bits. */
+                                    * - LITTLE_ENDIAN = LSB first
+                                    * - BIG_ENDIAN = MSB first */
+    uint8_t samplingEdge;         /* SDI sampling edge (relative to SDO sampling edge):
+                                    * - 0 = opposite to SDO sampling edge
+                                    * - 1 = same as SDO sampling edge */
+    uint32_t baudrate;                     /* The expected baud rate. */
+    spi_clockPolarity_t clockPolarity;     /* The clock polarity (active high or low). */
+    spi_clockPhase_t clockPhase;           /* The clock phase (sample on rising or falling edge). */
+    uint8_t wordSize;                      /* The size word size in number of bits. */
     uint8_t Mode;
     uint32_t event;
 };
 
 struct i2c_s {
-    uint32_t baudrate; 			/**< The expected baud rate. */
+    uint32_t baudrate;             /**< The expected baud rate. */
     uint32_t I2cStatusFromInt;
-    uint8_t ClockSource; 		/**< I2C clock source, 0 � clkI2C pin, 1 � PCLK */
-    uint8_t irqEnable; 			/**< IRQs to be enabled */
-    I2cIpc7208Reg_pt membase; 	/**< The memory base for the device's registers. */
-    IRQn_Type irq; 				/**< The IRQ number of the IRQ associated to the device. */
-    //queue_pt rxQueue; 			/**< The receive queue for the device instance. */
+    uint8_t ClockSource;           /**< I2C clock source, 0 � clkI2C pin, 1 � PCLK */
+    uint8_t irqEnable;             /**< IRQs to be enabled */
+    I2cIpc7208Reg_pt membase;      /**< The memory base for the device's registers. */
+    IRQn_Type irq;                 /**< The IRQ number of the IRQ associated to the device. */
+    //queue_pt rxQueue;            /**< The receive queue for the device instance. */
 };
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h
index a41d693eb52..be718d48c01 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h
@@ -47,28 +47,28 @@
 *************************************************************************************************/
 
 /** no pull up nor pull down */
-#define PAD_PULL_NONE	(uint8_t)0x01
+#define PAD_PULL_NONE    (uint8_t)0x01
 /** pull down */
-#define PAD_PULL_DOWN	(uint8_t)0x00
+#define PAD_PULL_DOWN    (uint8_t)0x00
 /** pull up */
-#define PAD_PULL_UP		(uint8_t)0x03
+#define PAD_PULL_UP      (uint8_t)0x03
 
 /** Drive strength */
-#define PAD_DRIVE_L0		(uint8_t)0x00
-#define PAD_DRIVE_L1		(uint8_t)0x01
-#define PAD_DRIVE_L2		(uint8_t)0x02
-#define PAD_DRIVE_L3		(uint8_t)0x03
-#define PAD_DRIVE_L4		(uint8_t)0x04
-#define PAD_DRIVE_L5		(uint8_t)0x05
-#define PAD_DRIVE_L6		(uint8_t)0x06
+#define PAD_DRIVE_L0        (uint8_t)0x00
+#define PAD_DRIVE_L1        (uint8_t)0x01
+#define PAD_DRIVE_L2        (uint8_t)0x02
+#define PAD_DRIVE_L3        (uint8_t)0x03
+#define PAD_DRIVE_L4        (uint8_t)0x04
+#define PAD_DRIVE_L5        (uint8_t)0x05
+#define PAD_DRIVE_L6        (uint8_t)0x06
 
 /** output configuration push/pull */
-#define PAD_OUTCFG_PUSHPULL	(uint8_t)0x00
+#define PAD_OUTCFG_PUSHPULL    (uint8_t)0x00
 /** output configuration open drain */
 #define PAD_OOUTCFG_OPENDRAIN (uint8_t)0x01
 
 /** lowest power PAD configuration, shall be the default */
-#define PAD_LOW_POWER	(PAD_PULL_NONE | (PAD_DRIVE_L0<<2) | (PAD_OOUTCFG_OPENDRAIN<<5))
+#define PAD_LOW_POWER    (PAD_PULL_NONE | (PAD_DRIVE_L0<<2) | (PAD_OOUTCFG_OPENDRAIN<<5))
 
 /** custom Power PAD configuration */
 #ifdef REVD
@@ -76,8 +76,8 @@
 #define PAD_INPUT_PD_L1_PP  (PAD_PULL_DOWN | (PAD_DRIVE_L1<<2) | (PAD_OUTCFG_PUSHPULL<<5))
 #define PAD_UNUSED_PD_L0_PP (PAD_PULL_DOWN | (PAD_DRIVE_L0<<2) | (PAD_OUTCFG_PUSHPULL<<5))
 
-#define PAD_UART_TX	(PAD_PULL_UP | (PAD_DRIVE_L1<<2) | (PAD_OUTCFG_PUSHPULL<<5))
-#define PAD_UART_RX (PAD_PULL_UP | (PAD_DRIVE_L1<<2) | (PAD_OOUTCFG_OPENDRAIN<<5))
+#define PAD_UART_TX    (PAD_PULL_UP | (PAD_DRIVE_L1<<2) | (PAD_OUTCFG_PUSHPULL<<5))
+#define PAD_UART_RX    (PAD_PULL_UP | (PAD_DRIVE_L1<<2) | (PAD_OOUTCFG_OPENDRAIN<<5))
 #endif /* REVD */
 
 /**************************************************************************************************
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h
index 33913ed3188..d452fda6485 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h
@@ -53,61 +53,43 @@ typedef struct {
     union {
         struct {
             __IO uint32_t ENCOMA :1; /**< 0- Sleep or SleepDeep depending on System Control Register (see WFI and WFE instructions), 1 � Coma */
-            __IO uint32_t SRAMA :1; /**< SRAMA Powered in Coma Modes: 0 � SRAM Powered, 1 � SRAM Un-Powered */
-            __IO uint32_t SRAMB :1; /**< SRAMB Powered in Coma Modes: 0 � SRAM Powered, 1 � SRAM Un-Powered */
+            __IO uint32_t SRAMA :1;  /**< SRAMA Powered in Coma Modes: 0 � SRAM Powered, 1 � SRAM Un-Powered */
+            __IO uint32_t SRAMB :1;  /**< SRAMB Powered in Coma Modes: 0 � SRAM Powered, 1 � SRAM Un-Powered */
             __IO uint32_t EXT32K :1; /**< External 32.768kHz Enable: 0 � Disabled (off), 1 � Enabled (on), Hardware guarantees that this oscillator cannot be powered if the internal 32kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
             __IO uint32_t INT32K :1; /**< Internal 32kHz Enable: 0 � Enabled (on), 1 � Disabled (Off), Hardware guarantees that this oscillator cannot be powered down if the external 32.768kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
             __IO uint32_t INT32M :1; /**< Internal 32MHz Enable: 0 � Enabled (on), 1 � Disabled (off), This bit will automatically get cleared when exiting Coma, or SleepDeep modes of operation. This bit should be set by software after switching over to the external 32MHz oscillator using the Oscillator Select bit in the Clock Control register */
-            __IO uint32_t C1V1:1;	/**< Coma mode 1V1 regulator setting: 0 - Linear regulator, 1 - switching regulator */
-            __IO uint32_t N1V1:1;	/**< Regular mode (Run sleep and deepsleep) 1V1 regulator mode: 0 - Linear regulator, 1 - switching regulator */
+            __IO uint32_t C1V1:1;    /**< Coma mode 1V1 regulator setting: 0 - Linear regulator, 1 - switching regulator */
+            __IO uint32_t N1V1:1;    /**< Regular mode (Run sleep and deepsleep) 1V1 regulator mode: 0 - Linear regulator, 1 - switching regulator */
             __IO uint32_t DBGPOW :1; /**< Debugger Power Behavior: 0 � Normal power behavior when the debugger is present, 1 � When debugger is present the ASIC can only enter SleepDeep mode and FVDDH and FVDDL always remain powered. The 32MHz oscillators can never be powered down in this mode either. */
-            __IO uint32_t UVIC:1;	/**< Under voltage indicator control: 0 - disabled, 1 - enabled */
-            __IO uint32_t UVII:1;	/**< Under voltage indicator input: 0 - 1V1 regulator, 1 - FVDDH regulator */
-            __IO uint32_t UVIR:1;	/**< Under voltage indicator reset: 0 - do not reset, 1 - reset */
+            __IO uint32_t UVIC:1;    /**< Under voltage indicator control: 0 - disabled, 1 - enabled */
+            __IO uint32_t UVII:1;    /**< Under voltage indicator input: 0 - 1V1 regulator, 1 - FVDDH regulator */
+            __IO uint32_t UVIR:1;    /**< Under voltage indicator reset: 0 - do not reset, 1 - reset */
         } BITS;
         __IO uint32_t WORD;
-    } CONTROL;		/* 0x4001D000 */
+    } CONTROL;        /* 0x4001D000 */
     union {
         struct {
-            __I uint32_t BATTDET:1;	/**< Detected battery: 0 - 1V, 1 - 3V */
-            __I uint32_t UVIC:1;	/**< Under voltage status: 0 - normal, 1 - low */
+            __I uint32_t BATTDET:1;    /**< Detected battery: 0 - 1V, 1 - 3V */
+            __I uint32_t UVIC:1;       /**< Under voltage status: 0 - normal, 1 - low */
 
         } BITS;
         __IO uint32_t WORD;
-    } STATUS; 		/* 0x4001D004 */
+    } STATUS;         /* 0x4001D004 */
 
-#ifdef REVB
-    __IO uint32_t RAMBIAS;
-    __IO uint32_t RETAINA_T;	/**< RAM retain make/break time. This is clocked using FCLK, so it�s range & resolution are determined by the FCLK divider register in the Clock Control Section. */
-    __IO uint32_t RETAINB_T;	/**< RAM retain make/break time. This is clocked using FCLK, so it�s range & resolution are determined by the FCLK divider register in the Clock Control Section. */
-    __IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */
-    __IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */
+    __IO uint32_t PLACEHOLDER;      /* 0x4001D008 */
+    __IO uint32_t FVDD_TSTARTUP;    /**< Regulator start time. */    /* 0x4001D00C */
+    __IO uint32_t PLACEHOLDER1;     /* 0x4001D010 */
+    __IO uint32_t FVDD_TSETTLE;     /**< Regulator settle time. */    /* 0x4001D014 */
     union {
         struct {
-            __IO uint32_t TH:6;			/**< Threshold */
-            __I	 uint32_t PAD:2;
-            __I  uint32_t UVIVAL; 		/**< UVI value */
+            __IO uint32_t TH:6;       /**< Threshold */
+            __I  uint32_t PAD:2;
+            __I  uint32_t UVIVAL:6;   /**< UVI value */
         } BITS;
         __IO uint32_t WORD;
-    } UVI_TBASE;
-    __IO uint32_t UVI_LIM;
-#endif	/* REVB */
+    } UVI_TBASE;                     /* 0x4001D018 */
+    __IO uint32_t SRAM_TRIM;         /* 0x4001D01C */
 
-#ifdef REVD
-    __IO uint32_t PLACEHOLDER;	 	/* 0x4001D008 */
-    __IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */	/* 0x4001D00C */
-    __IO uint32_t PLACEHOLDER1; 	/* 0x4001D010 */
-    __IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */	/* 0x4001D014 */
-    union {
-        struct {
-            __IO uint32_t TH:6;			/**< Threshold */
-            __I	 uint32_t PAD:2;
-            __I  uint32_t UVIVAL:6; 	/**< UVI value */
-        } BITS;
-        __IO uint32_t WORD;
-    } UVI_TBASE; 					/* 0x4001D018 */
-    __IO uint32_t SRAM_TRIM;		/* 0x4001D01C */
-#endif /* REVD */
 } PmuReg_t, *PmuReg_pt;
 
 #endif /* PMU_MAP_H_ */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h
index 455a8cb56b1..e567848c02b 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h
@@ -79,10 +79,10 @@ typedef struct {
     __IO uint32_t DUTYCYCLE;
     union {
         struct {
-            __O uint32_t ENABLE :8;	/**< Write any value to enable PWM output */
-            __I uint32_t PAD :1;	/** < Pad */
-            __I uint32_t ENABLE_STATE :1;	/**< Current state of pwmEnable configuration bit.  �1� PWM output is enabled.  �0� PWN output is disabled. */
-            __I uint32_t OUTPUT_STATE :1;	/**< Current state of PWM output */
+            __O uint32_t ENABLE :8;          /**< Write any value to enable PWM output */
+            __I uint32_t PAD :1;             /** < Pad */
+            __I uint32_t ENABLE_STATE :1;    /**< Current state of pwmEnable configuration bit.  �1� PWM output is enabled.  �0� PWN output is disabled. */
+            __I uint32_t OUTPUT_STATE :1;    /**< Current state of PWM output */
         } BITS;
         __IO uint32_t WORD;
     } PWM_ENABLE;
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/random_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/random_map.h
index db395cc58a8..bc33441fb5a 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/random_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/random_map.h
@@ -48,59 +48,59 @@
 
 /** Random Number Generator Control HW Structure Overlay */
 typedef struct {
-    __IO uint32_t WR_SEED_RD_RAND; 		/* Seed set & random read reg - 0x40011000 */
+    __IO uint32_t WR_SEED_RD_RAND;         /* Seed set & random read reg - 0x40011000 */
 #ifdef REVB
     __IO uint32_t MODE;
 #endif /* REVB */
     union {
         struct {
-            __IO uint32_t MODE :1;					/**<Mode Register, 0 � LSFR is updated on every rising edge of PCLK, 1 � LSFR is only updated on a read event of the LSFR register */
-            __IO uint32_t BYTE_SWAP :1;				/**<Byte Swap Control, 0 � 32-bit byte swap, 1 � 64-bit byte swap  */
-            __IO uint32_t MEATSTABLE_SPEED :1;		/**<Meta-stable Latch TRNG Speed Control, 0 � Slow mode, 1 � Fast mode */
-            __IO uint32_t WHITENOISE_EN :1;			/**<White Noise TRNG Enable, 0 � Disabled, 1 � Enabled */
-            __IO uint32_t METASTABLE_LATCH_EN :1;	/**<Meta-stable Latch TRNG Enable, 0 � Disabled, 1 � Enabled */
-            __IO uint32_t JIC :1;					/**<JIC */
+            __IO uint32_t MODE :1;                    /**<Mode Register, 0 � LSFR is updated on every rising edge of PCLK, 1 � LSFR is only updated on a read event of the LSFR register */
+            __IO uint32_t BYTE_SWAP :1;               /**<Byte Swap Control, 0 � 32-bit byte swap, 1 � 64-bit byte swap  */
+            __IO uint32_t MEATSTABLE_SPEED :1;        /**<Meta-stable Latch TRNG Speed Control, 0 � Slow mode, 1 � Fast mode */
+            __IO uint32_t WHITENOISE_EN :1;           /**<White Noise TRNG Enable, 0 � Disabled, 1 � Enabled */
+            __IO uint32_t METASTABLE_LATCH_EN :1;     /**<Meta-stable Latch TRNG Enable, 0 � Disabled, 1 � Enabled */
+            __IO uint32_t JIC :1;                     /**<JIC */
         } BITS;
         __IO uint32_t WORD;
-    } CONTROL;										/* Control register - 0x40011004 */
+    } CONTROL;                                        /* Control register - 0x40011004 */
     union {
         struct {
-            __IO uint32_t BYTE_0 :8;	/**<Byte #0*/
-            __IO uint32_t BYTE_1 :8;	/**<Byte #1*/
-            __IO uint32_t BYTE_2 :8;	/**<Byte #2*/
-            __IO uint32_t BYTE_3 :8;	/**<Byte #3*/
+            __IO uint32_t BYTE_0 :8;    /**<Byte #0*/
+            __IO uint32_t BYTE_1 :8;    /**<Byte #1*/
+            __IO uint32_t BYTE_2 :8;    /**<Byte #2*/
+            __IO uint32_t BYTE_3 :8;    /**<Byte #3*/
         } BITS;
         __IO uint32_t WORD;
-    } WRITE_BUF_LSW; 					/* Byte swap write buffer � Least significant word - 0x40011008 */
+    } WRITE_BUF_LSW;                     /* Byte swap write buffer � Least significant word - 0x40011008 */
     union {
         struct {
-            __IO uint32_t BYTE_4 :8;	/**<Byte #4*/
-            __IO uint32_t BYTE_5 :8;	/**<Byte #5*/
-            __IO uint32_t BYTE_6 :8;	/**<Byte #6*/
-            __IO uint32_t BYTE_7 :8;	/**<Byte #7*/
+            __IO uint32_t BYTE_4 :8;    /**<Byte #4*/
+            __IO uint32_t BYTE_5 :8;    /**<Byte #5*/
+            __IO uint32_t BYTE_6 :8;    /**<Byte #6*/
+            __IO uint32_t BYTE_7 :8;    /**<Byte #7*/
         } BITS;
         __IO uint32_t WORD;
-    } WRITE_BUF_MSW;					/* Byte swap write buffer � Most significant word - 0x4001100C */
+    } WRITE_BUF_MSW;                    /* Byte swap write buffer � Most significant word - 0x4001100C */
     union {
         struct {
-            __IO uint32_t BYTE_7_3 :8;	/**<Byte Swap Control == 1? Byte #7 : Byte #3*/
-            __IO uint32_t BYTE_6_2 :8;	/**<Byte Swap Control == 1? Byte #6 : Byte #2*/
-            __IO uint32_t BYTE_5_1 :8;	/**<Byte Swap Control == 1? Byte #5 : Byte #1*/
-            __IO uint32_t BYTE_4_0 :8;	/**<Byte Swap Control == 1? Byte #4 : Byte #0*/
+            __IO uint32_t BYTE_7_3 :8;    /**<Byte Swap Control == 1? Byte #7 : Byte #3*/
+            __IO uint32_t BYTE_6_2 :8;    /**<Byte Swap Control == 1? Byte #6 : Byte #2*/
+            __IO uint32_t BYTE_5_1 :8;    /**<Byte Swap Control == 1? Byte #5 : Byte #1*/
+            __IO uint32_t BYTE_4_0 :8;    /**<Byte Swap Control == 1? Byte #4 : Byte #0*/
         } BITS;
         __IO uint32_t WORD;
-    } READ_BUF_LSW;						/* Byte swap read buffer � Least significant word - 0x40011010 */
+    } READ_BUF_LSW;                        /* Byte swap read buffer � Least significant word - 0x40011010 */
     union {
         struct {
-            __IO uint32_t BYTE_3 :8;	/**<Byte #3*/
-            __IO uint32_t BYTE_2 :8;	/**<Byte #2*/
-            __IO uint32_t BYTE_1 :8;	/**<Byte #1*/
-            __IO uint32_t BYTE_0 :8;	/**<Byte #0*/
+            __IO uint32_t BYTE_3 :8;    /**<Byte #3*/
+            __IO uint32_t BYTE_2 :8;    /**<Byte #2*/
+            __IO uint32_t BYTE_1 :8;    /**<Byte #1*/
+            __IO uint32_t BYTE_0 :8;    /**<Byte #0*/
         } BITS;
         __IO uint32_t WORD;
-    } READ_BUF_MSW;			/* Byte swap read buffer � Most significant word - 0x40011014 */
-    __I  uint32_t METASTABLE_LATCH_VAL;	/* Meta-stable latch TRNG value - 0x40011018 */
-    __I  uint32_t WHITENOISE_VAL;		/* White noise TRNG value - 0x4001101C */
+    } READ_BUF_MSW;                      /* Byte swap read buffer � Most significant word - 0x40011014 */
+    __I  uint32_t METASTABLE_LATCH_VAL;  /* Meta-stable latch TRNG value - 0x40011018 */
+    __I  uint32_t WHITENOISE_VAL;        /* White noise TRNG value - 0x4001101C */
 } RandReg_t, *RandReg_pt;
 
 #endif /* RANDOM_MAP_H_ */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/reset_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/reset_map.h
index 229d8e78a3e..b772918ab8e 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/reset_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/reset_map.h
@@ -52,17 +52,17 @@
 typedef struct {
     union {
         struct {
-            __I uint32_t LOCKUP:1; 	    /**< 1:Core did lock up */
-            __I uint32_t WDOGRES:1;	    /**< 1:Watchdog reset occurred */
-            __I uint32_t EXTRESET:1;	    /**< 1:External reset occurred */
-            __I uint32_t SYSRESETREQ:1;  /**< 1:System reset occurred */
-            __I uint32_t POR:1;	        /**< 1:POR reset occurred */
+            __I uint32_t LOCKUP:1;         /**< 1:Core did lock up */
+            __I uint32_t WDOGRES:1;        /**< 1:Watchdog reset occurred */
+            __I uint32_t EXTRESET:1;       /**< 1:External reset occurred */
+            __I uint32_t SYSRESETREQ:1;    /**< 1:System reset occurred */
+            __I uint32_t POR:1;            /**< 1:POR reset occurred */
         } BITS;
         __I uint32_t WORD;
     } SOURCE;
-    __O uint32_t CLEARSOURCE;	    /**< writing any value to this register will clear the reset source register */
-    __I uint32_t HWREVID;	    	/**< Hardware ID, 0x80215400 */
-    __IO uint32_t CONTROL; 		/**< External Reset & Watchdog behavior: 0 � External Reset & Watchdog will reset debug logic 1 � External Reset & Watchdog will not reset debug logic */
+    __O uint32_t CLEARSOURCE;        /**< writing any value to this register will clear the reset source register */
+    __I uint32_t HWREVID;            /**< Hardware ID, 0x80215400 */
+    __IO uint32_t CONTROL;           /**< External Reset & Watchdog behavior: 0 � External Reset & Watchdog will reset debug logic 1 � External Reset & Watchdog will not reset debug logic */
 
 } ResetReg_t, *ResetReg_pt;
 
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c
index 12f5127935f..f924f362876 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c
@@ -61,10 +61,10 @@
  *    Entry 16 <-> Channel 26
  *
  * Each entry is compound of 4 items.
- * 	  Item 0: Rx Frequency integer divide portion
- * 	  Item 1: Rx Frequency fractional divide portion
- * 	  Item 2: Tx Frequency integer divide portion
- * 	  Item 3: Tx Frequency fractional divide portion
+ *       Item 0: Rx Frequency integer divide portion
+ *       Item 1: Rx Frequency fractional divide portion
+ *       Item 2: Tx Frequency integer divide portion
+ *       Item 3: Tx Frequency fractional divide portion
  *
  * The tx power table is used to program internal hardware register for different 15.4 tx power levels.
  * It has 43 entries corresponding to tx power levels from -32dBm to +10dBm.
@@ -100,7 +100,7 @@ const uint32_t rfLut[16][4] =  {{0x50,0x00D4A7,0x4B,0x00A000},
     {0x53,0xFED4A6,0x4E,0xFDFFFE}
 };
 
-const uint8_t txPowerLut[43]  =	 {0,0,0, // -32dBm to -30dBm
+const uint8_t txPowerLut[43]  =  {0,0,0, // -32dBm to -30dBm
                                   0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
                                   0,0,0,0,0,0,0,0,1,2, // -19dBm to -10dBm
                                   3,4,5,6,7,8,9,10,11,12, // -9dBm to 0dBm
@@ -130,7 +130,7 @@ const uint32_t rfLut[16][4] =  {{0x47,0xFF15FC,0x4B,0x00A000},
     {0x49,0xFFE8CF,0x4E,0xFDFFFE}
 };
 
-const uint8_t txPowerLut[43]  =	 {0,0,0, // -32dBm to -30dBm
+const uint8_t txPowerLut[43]  =  {0,0,0, // -32dBm to -30dBm
                                   0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
                                   0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
                                   3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
@@ -141,7 +141,7 @@ const uint8_t txPowerLut[43]  =	 {0,0,0, // -32dBm to -30dBm
 #ifdef REVB
 /** This rf LUT is built for low side injection, using high side injection
  * would requiere to change this LUT. */
-const uint32_t rfLut[16][4] =	{{0x47,0xFF15FC,0x4B,0x00A000},
+const uint32_t rfLut[16][4] =  {{0x47,0xFF15FC,0x4B,0x00A000},
     {0x47,0xFFAC93,0x4B,0x014001},
     {0x47,0x00432A,0x4B,0x01E001},
     {0x47,0x00D9C1,0x4C,0xFE7FFF},
@@ -159,7 +159,7 @@ const uint32_t rfLut[16][4] =	{{0x47,0xFF15FC,0x4B,0x00A000},
     {0x49,0xFFE8CF,0x4E,0xFDFFFE}
 };
 
-const uint8_t txPowerLut[43]  =	 {0,0,0, // -32dBm to -30dBm
+const uint8_t txPowerLut[43]  =  {0,0,0, // -32dBm to -30dBm
                                   0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
                                   0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
                                   3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
@@ -168,7 +168,7 @@ const uint8_t txPowerLut[43]  =	 {0,0,0, // -32dBm to -30dBm
 #endif
 
 #ifdef REVA
-const uint32_t rfLut[16][4] =	{{0x57,0xFF5D2F,0x51,0x018001},
+const uint32_t rfLut[16][4] =  {{0x57,0xFF5D2F,0x51,0x018001},
     {0x57,0x0007DA,0x52,0xFE1FFF},
     {0x57,0x00B285,0x52,0xFEBFFF},
     {0x57,0x015D30,0x52,0xFF6000},
@@ -186,7 +186,7 @@ const uint32_t rfLut[16][4] =	{{0x57,0xFF5D2F,0x51,0x018001},
     {0x59,0x015D30,0x53,0xFEDFFF}
 };
 
-const uint8_t txPowerLut[43]  =	 {1,2,3, // -32dBm to -30dBm
+const uint8_t txPowerLut[43]  =  {1,2,3, // -32dBm to -30dBm
                                   4,5,5,5,5,5,5,5,5,5, // -29dBm to -20dBm (clamp at -28dB)
                                   5,5,5,5,5,5,5,5,5,5, // -19dBm to -10dBm
                                   5,5,5,5,5,5,5,5,5,5, // -9dBm to 0dBm
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h
index 21b10652f61..a2d5513d2dd 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h
@@ -47,8 +47,8 @@
 /** Miscellaneous I/O codes /
  * @details
  */
-#define SET_RF_CHANNEL		(0x0) /**< <b>Ioctl request code</b>: Set Rf channel frequency */
-#define SET_TX_POWER		(0x1) /**< <b>Ioctl request code</b>: Set Tx output power */
+#define SET_RF_CHANNEL      (0x0) /**< <b>Ioctl request code</b>: Set Rf channel frequency */
+#define SET_TX_POWER        (0x1) /**< <b>Ioctl request code</b>: Set Tx output power */
 
 /*************************************************************************************************
 *                                                                                                *
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c
index aad86ca8ef5..02b61de6286 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c
@@ -50,24 +50,24 @@ static uint64_t LastRtcTimeus;
 /* See rtc.h for details */
 void fRtcInit(void)
 {
-    CLOCK_ENABLE(CLOCK_RTC); 			/* enable rtc peripheral */
-    CLOCKREG->CCR.BITS.RTCEN = True; 	/* Enable RTC clock 32K */
+    CLOCK_ENABLE(CLOCK_RTC);             /* enable rtc peripheral */
+    CLOCKREG->CCR.BITS.RTCEN = True;     /* Enable RTC clock 32K */
 
     /* Reset RTC control register */
-    RTCREG->CONTROL.WORD 	= False;
+    RTCREG->CONTROL.WORD     = False;
 
     /* Initialize all counters */
-    RTCREG->SECOND_COUNTER		= False;
-    RTCREG->SUB_SECOND_COUNTER	= False;
-    RTCREG->SECOND_ALARM 		= False;
-    RTCREG->SUB_SECOND_ALARM 	= False;
+    RTCREG->SECOND_COUNTER       = False;
+    RTCREG->SUB_SECOND_COUNTER   = False;
+    RTCREG->SECOND_ALARM         = False;
+    RTCREG->SUB_SECOND_ALARM     = False;
     LastRtcTimeus = 0;
 
     /* Reset RTC Status register */
-    RTCREG->STATUS.WORD 	= False;
+    RTCREG->STATUS.WORD      = False;
 
     /* Clear interrupt status */
-    RTCREG->INT_CLEAR.WORD 	= False;
+    RTCREG->INT_CLEAR.WORD   = False;
 
     /* Start sec & sub_sec counter */
     while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);/* Wait previous write to complete */
@@ -99,8 +99,8 @@ void fRtcFree(void)
 /* See rtc.h for details */
 void fRtcSetInterrupt(uint32_t timestamp)
 {
-    SubSecond 		= False;
-    uint32_t Second	= False;
+    SubSecond          = False;
+    uint32_t Second    = False;
     uint8_t DividerAdjust = 1;
 
     if(timestamp) {
@@ -122,7 +122,7 @@ void fRtcSetInterrupt(uint32_t timestamp)
             }
 
             volatile uint64_t Temp = (timestamp / DividerAdjust * RTC_CLOCK_HZ);
-            timestamp = (uint64_t)(Temp / RTC_SEC_TO_US * DividerAdjust);
+            Temp = (uint64_t)(Temp / RTC_SEC_TO_US * DividerAdjust);
             SubSecond = Temp & RTC_SUB_SEC_MASK;
 
             if(SubSecond <= 5) {
@@ -134,7 +134,7 @@ void fRtcSetInterrupt(uint32_t timestamp)
                 /* Second interrupt not enabled */
 
                 /* Set SUB SEC_ALARM */
-                RTCREG->SUB_SECOND_ALARM = SubSecond;	/* Write to sub second alarm */
+                RTCREG->SUB_SECOND_ALARM = SubSecond;    /* Write to sub second alarm */
 
                 /* Enable sub second interrupt */
                 RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
@@ -190,8 +190,8 @@ uint64_t fRtcRead(void)
      */
 
     do {
-        Second		= RTCREG->SECOND_COUNTER;    	/* Get SEC_COUNTER reg value */
-        SubSecond	= (RTCREG->SUB_SECOND_COUNTER - 1) & 0x7FFF;      /* Get SUB_SEC_COUNTER reg value */
+        Second       = RTCREG->SECOND_COUNTER;        /* Get SEC_COUNTER reg value */
+        SubSecond    = (RTCREG->SUB_SECOND_COUNTER - 1) & 0x7FFF;      /* Get SUB_SEC_COUNTER reg value */
     } while (Second != RTCREG->SECOND_COUNTER);                     /* Repeat if the second has changed */
 
     //note: casting to float removed to avoid reduction in resolution
@@ -207,8 +207,8 @@ uint64_t fRtcRead(void)
 /* See rtc.h for details */
 void fRtcWrite(uint64_t RtcTimeus)
 {
-    uint32_t Second		= 0;
-    uint16_t SubSecond	= 0;
+    uint32_t Second       = 0;
+    uint16_t SubSecond    = 0;
     /* Stop RTC */
     RTCREG->CONTROL.WORD &= ~((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
                               (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
@@ -237,6 +237,7 @@ void fRtcWrite(uint64_t RtcTimeus)
 /* See rtc.h for details */
 void fRtcHandler(void)
 {
+	while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
     /* SUB_SECOND/SECOND interrupt occured */
     volatile uint32_t TempStatus = RTCREG->STATUS.WORD;
 
@@ -265,11 +266,12 @@ void fRtcHandler(void)
     } else {
         /* We reach here after sub_second or (Sub second + second) interrupt occured */
         while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
+		/* Disable Second and sub_second interrupt */
         RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
                                 (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
     }
 
-    while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
+	lp_ticker_irq_handler();
 }
 
 boolean fIsRtcEnabled(void)
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.h
index 2e7f210e84e..4843975d186 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.h
@@ -1,7 +1,7 @@
 /**
  ******************************************************************************
  * @file    rtc.h
- * @brief	(API) Public header of RTC driver
+ * @brief    (API) Public header of RTC driver
  * @internal
  * @author   ON Semiconductor
  * $Rev: 3485 $
@@ -34,26 +34,26 @@
 #include "clock.h"
 #include "memory_map.h"
 
-#define RTC_CLOCK_HZ				 			32768
-#define RTC_SEC_TO_US							1000000
-#define RTC_SUB_SEC_MASK						0x7FFF
-#define RTC_SEC_MASK							0xFFFFFFFF
-#define RTC_SEC_INT_STATUS_MASK					0x2
+#define RTC_CLOCK_HZ                            32768
+#define RTC_SEC_TO_US                           1000000
+#define RTC_SUB_SEC_MASK                        0x7FFF
+#define RTC_SEC_MASK                            0xFFFFFFFF
+#define RTC_SEC_INT_STATUS_MASK                 0x2
 
-#define RTC_SUBSEC_INTERRUPT_BIT_VAL			0x1
-#define RTC_SEC_INTERRUPT_BIT_VAL				0x2
-#define RTC_ALL_INTERRUPT_BIT_VAL				0x3
+#define RTC_SUBSEC_INTERRUPT_BIT_VAL            0x1
+#define RTC_SEC_INTERRUPT_BIT_VAL               0x2
+#define RTC_ALL_INTERRUPT_BIT_VAL               0x3
 
-#define RTC_INT_CLR_SUB_SEC_BIT_POS				0
-#define RTC_INT_CLR_SEC_BIT_POS					1
+#define RTC_INT_CLR_SUB_SEC_BIT_POS             0
+#define RTC_INT_CLR_SEC_BIT_POS                 1
 
-#define RTC_CONTROL_SUBSEC_CNT_START_BIT_POS	0
-#define RTC_CONTROL_SEC_CNT_START_BIT_POS		1
-#define RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS		2
-#define RTC_CONTROL_SEC_CNT_INT_BIT_POS			3
+#define RTC_CONTROL_SUBSEC_CNT_START_BIT_POS    0
+#define RTC_CONTROL_SEC_CNT_START_BIT_POS       1
+#define RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS      2
+#define RTC_CONTROL_SEC_CNT_INT_BIT_POS         3
 
-#define RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS	9
-#define RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS		10
+#define RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS  9
+#define RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS      10
 
 /* FUnction pointer for call back */
 typedef void (* fRtcCallBack)(void);
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h
index 64b06acbfdf..86f6325821b 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h
@@ -111,43 +111,43 @@ typedef struct {
     } INT_CLEAR;
 #endif /* REVB */
 #ifdef REVD
-    __IO uint32_t SUB_SECOND_COUNTER;	/**<SUB SECOND Counter */	/* 0x4000F000 */
-    __IO uint32_t SECOND_COUNTER;		/**<SECOND Counter */		/* 0x4000F004 */
-    __IO uint32_t SUB_SECOND_ALARM;		/**< SUB SECOND alarm */	/* 0x4000F008 */
-    __IO uint32_t SECOND_ALARM;			/**< SECOND alarm */		/* 0x4000F00c */
+    __IO uint32_t SUB_SECOND_COUNTER;    /**<SUB SECOND Counter */   /* 0x4000F000 */
+    __IO uint32_t SECOND_COUNTER;        /**<SECOND Counter */       /* 0x4000F004 */
+    __IO uint32_t SUB_SECOND_ALARM;      /**< SUB SECOND alarm */    /* 0x4000F008 */
+    __IO uint32_t SECOND_ALARM;          /**< SECOND alarm */        /* 0x4000F00c */
     union {
         struct {
-            __IO uint32_t SUB_SEC_COUNTER_EN :1;	/**<Sub-second counter enable.  (1=count is enabled, 0=retain count value) */
-            __IO uint32_t SEC_COUNTER_EN :1;		/**<Second counter enable. (1=count is enabled, 0=retain count value) */
-            __IO uint32_t SUB_SECOND_INT_EN :1;		/**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
-            __IO uint32_t SECOND_INT_EN :1;			/**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
+            __IO uint32_t SUB_SEC_COUNTER_EN :1;    /**<Sub-second counter enable.  (1=count is enabled, 0=retain count value) */
+            __IO uint32_t SEC_COUNTER_EN :1;        /**<Second counter enable. (1=count is enabled, 0=retain count value) */
+            __IO uint32_t SUB_SECOND_INT_EN :1;     /**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
+            __IO uint32_t SECOND_INT_EN :1;         /**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
         } BITS;
         __IO uint32_t WORD;
-    } CONTROL;			/* 0x4000F010 */
+    } CONTROL;            /* 0x4000F010 */
     union {
         struct {
             /**<Any write to the status register will clear the error bit. */
-            __IO uint32_t SUB_SECOND_INT:1;				/**<Sub-second interrupt status.  (1=interrupt active, 0=no interrupt)*/
-            __IO uint32_t SECOND_INT :1;				/**<Second interrupt status.  (1=interrupt active, 0=no interrupt)*/
-            __IO uint32_t WRITE_ERROR :1;				/**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
-            __IO uint32_t BSY_ANY_WRT :1;				/**<Busy with any write.*/
-            __IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1;	/**<Busy with a sub-second counter register write.*/
-            __IO uint32_t BSY_SEC_CNTR_REG_WRT :1;		/**<Busy with a second counter register write.*/
-            __IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1;	/**<Busy with a sub-second alarm register write.*/
-            __IO uint32_t BSY_SEC_ALRM_REG_WRT:1;		/**<Busy with a second alarm register write.*/
-            __IO uint32_t BSY_CTRL_REG_WRT :1;			/**<Busy with a control register write.*/
-            __IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1;	/**<Busy with a sub-second interrupt clear write.*/
-            __IO uint32_t BSY_SEC_INT_CLR_WRT :1;		/**<Busy with a second interrupt clear write.*/
+            __IO uint32_t SUB_SECOND_INT:1;             /**<Sub-second interrupt status.  (1=interrupt active, 0=no interrupt)*/
+            __IO uint32_t SECOND_INT :1;                /**<Second interrupt status.  (1=interrupt active, 0=no interrupt)*/
+            __IO uint32_t WRITE_ERROR :1;               /**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
+            __IO uint32_t BSY_ANY_WRT :1;               /**<Busy with any write.*/
+            __IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1;  /**<Busy with a sub-second counter register write.*/
+            __IO uint32_t BSY_SEC_CNTR_REG_WRT :1;      /**<Busy with a second counter register write.*/
+            __IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1;  /**<Busy with a sub-second alarm register write.*/
+            __IO uint32_t BSY_SEC_ALRM_REG_WRT:1;       /**<Busy with a second alarm register write.*/
+            __IO uint32_t BSY_CTRL_REG_WRT :1;          /**<Busy with a control register write.*/
+            __IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1;   /**<Busy with a sub-second interrupt clear write.*/
+            __IO uint32_t BSY_SEC_INT_CLR_WRT :1;       /**<Busy with a second interrupt clear write.*/
         } BITS;
         __IO uint32_t WORD;
-    } STATUS;			/* 0x4000F014 */
+    } STATUS;            /* 0x4000F014 */
     union {
         struct {
-            __O uint32_t SUB_SECOND :1;		/**<Write 1 to this register to clear the sub-second interrupt.*/
-            __O uint32_t SECOND :1;			/**<Write 1 to this register to clear the second interrupt.*/
+            __O uint32_t SUB_SECOND :1;        /**<Write 1 to this register to clear the sub-second interrupt.*/
+            __O uint32_t SECOND :1;            /**<Write 1 to this register to clear the second interrupt.*/
         } BITS;
         __O uint32_t WORD;
-    } INT_CLEAR;			/* 0x4000F018 */
+    } INT_CLEAR;            /* 0x4000F018 */
 #endif /* REVD */
 } RtcReg_t, *RtcReg_pt;
 
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c
index 1d57d654908..f1c7633f589 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c
@@ -89,12 +89,12 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
         memcpy(&stdio_uart, obj, sizeof(serial_t));
     }
     /*TODO: determine if pullups are needed/recommended */
-    /*	if (tx != NC) {
-    			pin_mode(tx, PullUp);
+    /*    if (tx != NC) {
+                pin_mode(tx, PullUp);
       }
-    	if (rx != NC) {
-    			pin_mode(rx, PullUp);
-    	}
+        if (rx != NC) {
+                pin_mode(rx, PullUp);
+        }
     */
     /* Configure IOs to UART using cross bar, pad and GPIO settings */
 
@@ -132,8 +132,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
     PadRegOffset = (PadReg_t*)(PADREG_BASE + (rx * PAD_REG_ADRS_BYTE_SIZE));
     PadRegOffset->PADIO0.WORD = PAD_UART_RX;  /* Pad settings for UART Rx */
 
-    GPIOREG->W_OUT	|= (True << tx); /* tx as OUT direction */
-    GPIOREG->W_IN 	|= (True << rx); /* rx as IN directon */
+    GPIOREG->W_OUT    |= (True << tx); /* tx as OUT direction */
+    GPIOREG->W_IN     |= (True << rx); /* rx as IN directon */
 
     CLOCK_DISABLE(CLOCK_PAD);
     CLOCK_DISABLE(CLOCK_CROSSB);
@@ -324,8 +324,8 @@ int serial_getc(serial_t *obj)
 {
     uint8_t c;
 
-    while(!obj->UARTREG->LSR.BITS.READY); 	/* Wait for received data is ready */
-    c = obj->UARTREG->RBR & 0xFF; 			/* Get received character */
+    while(!obj->UARTREG->LSR.BITS.READY);     /* Wait for received data is ready */
+    c = obj->UARTREG->RBR & 0xFF;             /* Get received character */
     return c;
 }
 
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c
index 9fce0d8de29..0713f7626ac 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c
@@ -35,14 +35,14 @@
 #include "sleep_api.h"
 #include "cmsis_nvic.h"
 
-#define ENABLE			(uint8_t)0x01
-#define DISABLE 		(uint8_t)0x00
-#define MAC_LUT_SIZE	(uint8_t)96
+#define ENABLE          (uint8_t)0x01
+#define DISABLE         (uint8_t)0x00
+#define MAC_LUT_SIZE    (uint8_t)96
 
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile unsigned long * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_CLK_BIT			( 1UL << 2UL )
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_CTRL_REG           ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_CLK_BIT            ( 1UL << 2UL )
+#define portNVIC_SYSTICK_INT_BIT            ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT         ( 1UL << 0UL )
 
 void sleep(void)
 {
@@ -79,7 +79,7 @@ void coma(void)
     PMUREG->CONTROL.BITS.ENCOMA = ENABLE;
 
     /* TODO Wait till MAC is idle */
-    //		while((MACHWREG->SEQUENCER == MACHW_SEQ_TX) || (MACHWREG->SEQUENCER == MACHW_SEQ_ED) || (MACHWREG->SEQUENCER == MACHW_SEQ_CCA));
+    //        while((MACHWREG->SEQUENCER == MACHW_SEQ_TX) || (MACHWREG->SEQUENCER == MACHW_SEQ_ED) || (MACHWREG->SEQUENCER == MACHW_SEQ_CCA));
 
     /* TODO Back up MAC_LUT *
     uint8_t MAC_LUT_BackUp[MAC_LUT_SIZE];
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.h
index f7e6cb8f8c2..f3f9ff1fc50 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.h
@@ -42,18 +42,18 @@
 #include "crossbar.h"
 #include "clock.h"
 
-#define SLEEP_TYPE_NONE			0
-#define SLEEP_TYPE_SLEEP		1
-#define SLEEP_TYPE_DEEPSLEEP	2
-#define SLEEP_TYPE_COMA			3
+#define SLEEP_TYPE_NONE            0
+#define SLEEP_TYPE_SLEEP        1
+#define SLEEP_TYPE_DEEPSLEEP    2
+#define SLEEP_TYPE_COMA            3
 
-#define SLEEP_DURATION_SLEEP_MIN		10  		/* msec */
-#define SLEEP_DURATION_SLEEP_MAX		200 		/* msec */
-#define SLEEP_DURATION_DEEPSLEEP_MAX	500 		/* msec */
-#define SLEEP_DURATION_COMA_MAX			1000000000 	/* TODO 1000 sec */
+#define SLEEP_TYPE_DEFAULT SLEEP_TYPE_DEEPSLEEP
+
+#define SLEEP_DURATION_SLEEP_MIN        10          /* msec */
+#define SLEEP_DURATION_SLEEP_MAX        200         /* msec */
+#define SLEEP_DURATION_DEEPSLEEP_MAX    500         /* msec */
+#define SLEEP_DURATION_COMA_MAX         1000000000  /* TODO 1000 sec */
 
-void sleep(void);
-void deepsleep(void);
 void coma(void);
 
 #endif // SLEEP_H_
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c
index 432c6e1ba16..a59dde1026d 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c
@@ -39,11 +39,52 @@
 
 void mbed_enter_sleep(sleep_t *obj)
 {
-    /* Empty implementation, this will be implemented for mbed5.0 */
+
+#ifdef SLEEP_TYPE_DEFAULT
+
+    if(SLEEP_TYPE_DEFAULT == SLEEP_TYPE_SLEEP) {
+        /* Sleep mode */
+        sleep();
+    } else if(SLEEP_TYPE_DEFAULT == SLEEP_TYPE_DEEPSLEEP) {
+        /* Deep Sleep mode */
+        deepsleep();
+    } else {
+        /* Coma mode */
+        coma();
+    }
+
+#else
+
+    if(obj->SleepType == SLEEP_TYPE_NONE) {
+        /* Select low power mode based on sleep duration */
+
+        if(obj->timeToSleep <= SLEEP_DURATION_SLEEP_MAX) {
+            /* Sleep mode */
+            sleep();
+        } else if(obj->timeToSleep <= SLEEP_DURATION_DEEPSLEEP_MAX) {
+            /* Deep sleep */
+            deepsleep();
+        } else {
+            /* Coma */
+            coma();
+        }
+    } else if(obj->SleepType == SLEEP_TYPE_SLEEP) {
+        /* Sleep mode */
+        sleep();
+    } else if(obj->SleepType == SLEEP_TYPE_DEEPSLEEP) {
+        /* Deep Sleep mode */
+        deepsleep();
+    } else {
+        /* Coma mode */
+        coma();
+    }
+
+#endif
 }
 
 void mbed_exit_sleep(sleep_t *obj)
 {
     (void)obj;
 }
+
 #endif /* DEVICE_SLEEP */
\ No newline at end of file
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/spi.h
index 7ca81c258fc..91c3b333668 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/spi.h
@@ -42,9 +42,35 @@ extern "C" {
 #endif
 
 /* Miscellaneous I/O and control operations codes */
-#define SPI_IPC7207_IOCTL_GET_SLAVE_SELECT	(0x1) /**< <b>Ioctl request code</b>: Reading slaveSelect register */
-#define SPI_IPC7207_IOCTL_SET_SLAVE_SELECT	(0x2) /**< <b>Ioctl request code</b>: Setting slaveSelect register */
-#define SPI_IPC7207_IOCTL_FLUSH				(0x3) /**< <b>Ioctl request code</b>: Flushin FIFOs and serial shift registers */
+#define SPI_IPC7207_IOCTL_GET_SLAVE_SELECT    (0x1) /**< <b>Ioctl request code</b>: Reading slaveSelect register */
+#define SPI_IPC7207_IOCTL_SET_SLAVE_SELECT    (0x2) /**< <b>Ioctl request code</b>: Setting slaveSelect register */
+#define SPI_IPC7207_IOCTL_FLUSH               (0x3) /**< <b>Ioctl request code</b>: Flushin FIFOs and serial shift registers */
+
+/* Control register bit positions */
+#define SPI_WORD_WIDTH_BIT_POS          6
+#define SPI_SLAVE_MASTER_BIT_POS        5
+#define SPI_CPOL_BIT_POS                4
+#define SPI_CPHA_BIT_POS                3
+#define SPI_ENDIAN_BIT_POS              2
+#define SPI_SAMPLE_EDGE_BIT_POS         1
+#define SPI_PORT_ENABLE_BIT_POS         0
+
+/* COntrol register bits */
+#define SPI_ENDIAN_MSB_FIRST            1
+#define SPI_CPOL_IDLE_LOW               0
+#define SPI_CPHA_BEFORE_1ST_EDGE        0
+#define SPI_MASTER_MODE                 1
+#define SPI_WORD_WIDTH_8_BITS           0
+#define SPI_SAMPLE_OPP_CLK_EDGE_DATA    0
+#define SPI_SLAVE_SELECT_NORM_BEHAVE    0
+#define SPI_PORT_ENABLE                 1
+
+#define SPI_SLAVE_SELECT_DEFAULT        0x10
+
+#define SPI_DEFAULT_CONFIG              0x25
+
+#define SPI_DEFAULT_SPEED               1000000
+#define SPI_BYTE_MASK                   0xFF
 
 extern void fSpiInit(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
 extern void fSpiClose(spi_t *obj);
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c
index 614e0c73358..af039865947 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c
@@ -43,10 +43,7 @@
 #include "cmsis_nvic.h"
 
 
-#define SPI_FREQ_MAX			4000000
-#define SPI_ENDIAN_LSB_FIRST	0
-#define SPI_MASTER_MODE			1
-#define SPI_SLAVE_MODE			0
+#define SPI_FREQ_MAX 4000000
 
 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
 {
@@ -59,18 +56,15 @@ void spi_free(spi_t *obj)
 
 void spi_format(spi_t *obj, int bits, int mode, int slave)
 {
-    if(slave) {
-        /* Slave mode */
-        obj->membase->CONTROL.BITS.MODE = SPI_SLAVE_MODE;
-    } else {
-        /* Master mode */
-        obj->membase->CONTROL.BITS.MODE = SPI_MASTER_MODE;
-    }
-    obj->membase->CONTROL.BITS.WORD_WIDTH = bits >> 0x4; 			/* word width */
-    obj->membase->CONTROL.BITS.CPOL 	  = mode >> 0x1; 			/* CPOL  */
-    obj->membase->CONTROL.BITS.CPHA 	  = mode & 0x1; 			/* CPHA */
-
-    obj->membase->CONTROL.BITS.ENDIAN 	  = SPI_ENDIAN_LSB_FIRST;	/* Endian */
+    /* Clear word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
+    obj->membase->CONTROL.WORD &= ~(uint32_t)((True >> SPI_WORD_WIDTH_BIT_POS) |
+                                  (True >> SPI_SLAVE_MASTER_BIT_POS) |
+                                  (True >> SPI_CPOL_BIT_POS) |
+                                  (True >> SPI_CPHA_BIT_POS));
+
+    /* Configure word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
+    obj->membase->CONTROL.WORD |= (uint32_t)(((bits >> 0x4) >> 6) | (!slave >> 5) |
+                                  ((mode >> 0x1) >> 4) | ((mode & 0x1) >> 3));
 }
 
 void spi_frequency(spi_t *obj, int hz)
@@ -103,6 +97,29 @@ uint8_t spi_get_module(spi_t *obj)
     }
 }
 
+int  spi_slave_receive(spi_t *obj)
+{
+	if(obj->membase->STATUS.BITS.RX_EMPTY != True){ /* if receive status is not empty */
+		return True;	/* Byte available to read */
+	}
+	return False; /* Byte not available to read */
+}
+
+int  spi_slave_read(spi_t *obj)
+{
+	int byte;
+	
+	while (obj->membase->STATUS.BITS.RX_EMPTY == True); /* Wait till Receive status is empty */
+    byte = obj->membase->RX_DATA;
+    return byte;
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+	while((obj->membase->STATUS.BITS.TX_FULL == True) && (obj->membase->STATUS.BITS.RX_FULL == True)); /* Wait till Tx/Rx status is full */
+    obj->membase->TX_DATA = value;
+}
+
 #if DEVICE_SPI_ASYNCH /* TODO Not implemented yet */
 
 void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t handler, uint32_t event, DMAUsage hint)
@@ -147,12 +164,12 @@ void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_
     }
 
 
-    //	enable events
+    //    enable events
 
     obj->spi.event |= event;
 
 
-    //		set sleep_level
+    //        set sleep_level
     enable irq
 
     //write async
@@ -193,4 +210,4 @@ void spi_abort_asynch(spi_t *obj)
 }
 
 #endif /* DEVICE_SPI_ASYNCH */
-#endif /* DEVICE_SPI */
+#endif /* DEVICE_SPI */
\ No newline at end of file
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/swversion.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/swversion.c
index 50f30ff12a5..f16cdac18d6 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/swversion.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/swversion.c
@@ -46,10 +46,10 @@ __root const fibtable_t fib_table @ "FIBTABLE" = { LOAD_ADDRESS,{0x0,0x00,0x00,0
 #endif /* IAR */
 
 const mib_systemRevision_t systemRevision = {
-    0x82,	/**< hardware revision */
-    0x00,	/**< patch level */
-    0x01,	/**< Build number */
-    0x00,	/**< feature set, Minor version */
-    0x01,	/**< generation, Major version */
-    'E'		/**< release */
+    0x82,    /**< hardware revision */
+    0x00,    /**< patch level */
+    0x01,    /**< Build number */
+    0x00,    /**< feature set, Minor version */
+    0x01,    /**< generation, Major version */
+    'E'      /**< release */
 };
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/sys.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/sys.h
index e55c0929a50..979b80ce268 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/sys.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/sys.h
@@ -39,18 +39,18 @@
 *                                                                                                *
 *************************************************************************************************/
 
-#define SYS_MODULE_ID		0x04
+#define SYS_MODULE_ID        0x04
 
-#define SYS_RESET_CODE		0x00
-#define SYS_SLEEP_CODE		0x10
-#define SYS_DEEPSLEEP_CODE	0x11
-#define SYS_COMA_CODE		0x12
+#define SYS_RESET_CODE       0x00
+#define SYS_SLEEP_CODE       0x10
+#define SYS_DEEPSLEEP_CODE   0x11
+#define SYS_COMA_CODE        0x12
 
-#define SYS_RESET_WATCHDOG		0x00
-#define SYS_RESET_CORTEX		0x01
+#define SYS_RESET_WATCHDOG   0x00
+#define SYS_RESET_CORTEX     0x01
 
-#define PWM_ACCESS_CODE     0x30
-#define PWM_IOCTLS_CODE		0x31
+#define PWM_ACCESS_CODE      0x30
+#define PWM_IOCTLS_CODE      0x31
 
 /*************************************************************************************************
 *                                                                                                *
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ticker.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/ticker.h
index 82f186d093c..f7be3c94fc1 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ticker.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ticker.h
@@ -36,41 +36,41 @@
  *
  * These definitions should be adjusted to setup Orion core frequencies.
  */
-#define	CPU_CLOCK_ROOT_HZ			( ( unsigned long ) 32000000) /**< <b> Orion 32MHz root frequency </b> */
-#define	CPU_CLOCK_DIV_32M			( 1 ) /**< <b> Divider to set up core frequency at 32MHz </b> */
-#define	CPU_CLOCK_DIV_16M			( 2 ) /**< <b> Divider to set up core frequency at 16MHz </b> */
-#define	CPU_CLOCK_DIV_8M			( 4 ) /**< <b> Divider to set up core frequency at 8MHz </b> */
-#define	CPU_CLOCK_DIV_4M			( 8 ) /**< <b> Divider to set up core frequency at 4MHz </b> */
+#define    CPU_CLOCK_ROOT_HZ           ( ( unsigned long ) 32000000) /**< <b> Orion 32MHz root frequency </b> */
+#define    CPU_CLOCK_DIV_32M           ( 1 ) /**< <b> Divider to set up core frequency at 32MHz </b> */
+#define    CPU_CLOCK_DIV_16M           ( 2 ) /**< <b> Divider to set up core frequency at 16MHz </b> */
+#define    CPU_CLOCK_DIV_8M            ( 4 ) /**< <b> Divider to set up core frequency at 8MHz </b> */
+#define    CPU_CLOCK_DIV_4M            ( 8 ) /**< <b> Divider to set up core frequency at 4MHz </b> */
 
-#define	CPU_CLOCK_DIV				CPU_CLOCK_DIV_32M /**< <b> Selected divider to be used by application code </b> */
+#define    CPU_CLOCK_DIV               CPU_CLOCK_DIV_32M /**< <b> Selected divider to be used by application code </b> */
 
-#define configCPU_CLOCK_HZ			( ( unsigned long ) (CPU_CLOCK_ROOT_HZ/CPU_CLOCK_DIV) )
-#define configTICK_RATE_HZ			( ( unsigned long ) 1000000 ) // 1uSec ticker rate
+#define configCPU_CLOCK_HZ             ( ( unsigned long ) (CPU_CLOCK_ROOT_HZ/CPU_CLOCK_DIV) )
+#define configTICK_RATE_HZ             ( ( unsigned long ) 1000000 ) // 1uSec ticker rate
 
 
 /* Lowest priority */
 
-#define configKERNEL_INTERRUPT_PRIORITY 		( 0xFF )
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( 0x8F )
+#define configKERNEL_INTERRUPT_PRIORITY         ( 0xFF )
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    ( 0x8F )
 
 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
 
 /* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile unsigned long * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile unsigned long * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	        ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
-#define portNVIC_INT_CTRL_REG				( * ( ( volatile unsigned long * ) 0xe000ed04 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_CTRL_REG            ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG            ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG   ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
+#define portNVIC_INT_CTRL_REG                ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )
+#define portNVIC_SYSPRI2_REG                 ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
 
 /* ...then bits in the registers. */
-#define portNVIC_SYSTICK_CLK_BIT			( 1UL << 2UL )
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		        ( 1UL << 16UL )
+#define portNVIC_SYSTICK_CLK_BIT            ( 1UL << 2UL )
+#define portNVIC_SYSTICK_INT_BIT            ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT         ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT     ( 1UL << 16UL )
 
 /* Orion has 4 interrupt priority bits
  */
-#define portNVIC_SYSTICK_PRI		        ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
+#define portNVIC_SYSTICK_PRI                ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
 
 /* API definitions */
 void fSysTickInit(void);
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/timer.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/timer.h
index 59b0d760625..58affbc1452 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/timer.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/timer.h
@@ -57,53 +57,53 @@ extern "C" {
 #include "cmsis_nvic.h"
 
 /* Miscellaneous I/O and control operations codes */
-#define TIMER_IOCTL_GET_LOAD	1 /**< <b>Ioctl request code</b>: Getting load value. */
-#define TIMER_IOCTL_SET_LOAD	2 /**< <b>Ioctl request code</b>: Seting load value. */
-#define TIMER_IOCTL_GET_VALUE	3 /**< <b>Ioctl request code</b>: Getting current timer value. */
+#define TIMER_IOCTL_GET_LOAD    1 /**< <b>Ioctl request code</b>: Getting load value. */
+#define TIMER_IOCTL_SET_LOAD    2 /**< <b>Ioctl request code</b>: Seting load value. */
+#define TIMER_IOCTL_GET_VALUE   3 /**< <b>Ioctl request code</b>: Getting current timer value. */
 
 /* Timer control bits */
-#define TIMER_ENABLE_BIT		0x1
-#define TIMER_PRESCALE_BIT_POS	0x2
-#define TIMER_MODE_BIT_POS		0x6
-#define TIMER_ENABLE_BIT_POS	0x7
+#define TIMER_ENABLE_BIT        0x1
+#define TIMER_PRESCALE_BIT_POS  0x2
+#define TIMER_MODE_BIT_POS      0x6
+#define TIMER_ENABLE_BIT_POS    0x7
 
 /* Options defines */
 // TODO (MIV): put this in an enumerated value
 typedef enum {
-    CLK_DIVIDER_1		=	0,
-    CLK_DIVIDER_2		=	3,
-    CLK_DIVIDER_8		=	4,
-    CLK_DIVIDER_16		=	1,
-    CLK_DIVIDER_32		=	5,
-    CLK_DIVIDER_128		=	6,
-    CLK_DIVIDER_256		=	2,
-    CLK_DIVIDER_1024	=	7
+    CLK_DIVIDER_1     = 0,
+    CLK_DIVIDER_2     = 3,
+    CLK_DIVIDER_8     = 4,
+    CLK_DIVIDER_16    = 1,
+    CLK_DIVIDER_32    = 5,
+    CLK_DIVIDER_128   = 6,
+    CLK_DIVIDER_256   = 2,
+    CLK_DIVIDER_1024  = 7
 } ClockDivider;
 
-#define TIME_MODE_FREE_RUNNING	0x0
-#define TIME_MODE_PERIODIC		0x1
+#define TIME_MODE_FREE_RUNNING    0x0
+#define TIME_MODE_PERIODIC        0x1
 
 typedef  void (*timer_irq_handlers_t)(void) ;
 
 /** Options to be passed when opening a timer device instance.*/
 typedef struct timer_options {
-    TimerReg_pt membase;	/**< Memory base for the device's registers. */
-    uint8_t irq;		/**< IRQ number of the IRQ associated to the device. */
-    boolean mode;		/**< Timer mode:
-	 	 	 	 	 	 	 * - 0 = Free Run mode (no interrupt generation)
-	 	 	 	 	 	 	 * <b> # timer duration = (65535 + 1) * prescaler  * peripheral clock (PCLK) period </b>
-	 	 	 	 	 	 	 * - 1 = Periodic mode (interrupt generation)
-	 	 	 	 	 	 	 * <b> # timer duration = (load  + 1) * prescaler  * peripheral clock (PCLK) period </b> */
-    uint8_t prescale;	/**< Timer prescaler: from 1 to 1024.
-	 	 	 	 	 	 	 * - CLK_DIVIDER_1 = clock not divided
-	 	 	 	 	 	 	 * - CLK_DIVIDER_2 = clock is divided by 2
-	 	 	 	 	 	 	 * - CLK_DIVIDER_8 = clock is divided by 8
-	 	 	 	 	 	 	 * - CLK_DIVIDER_16 = clock is divided by 16
-	 	 	 	 	 	 	 * - CLK_DIVIDER_32 = clock is divided by 32
-	 	 	 	 	 	 	 * - CLK_DIVIDER_128 = clock is divided by 128
-	 	 	 	 	 	 	 * - CLK_DIVIDER_256 = clock is divided by 256
-	 	 	 	 	 	 	 * - CLK_DIVIDER_1024 = clock is divided by 1024 */
-    uint16_t load;		/**< Timer load: from 0 to 65535. */
+    TimerReg_pt membase;    /**< Memory base for the device's registers. */
+    uint8_t irq;            /**< IRQ number of the IRQ associated to the device. */
+    boolean mode;           /**< Timer mode:
+                                   * - 0 = Free Run mode (no interrupt generation)
+                                   * <b> # timer duration = (65535 + 1) * prescaler  * peripheral clock (PCLK) period </b>
+                                   * - 1 = Periodic mode (interrupt generation)
+                                   * <b> # timer duration = (load  + 1) * prescaler  * peripheral clock (PCLK) period </b> */
+    uint8_t prescale;    /**< Timer prescaler: from 1 to 1024.
+                                   * - CLK_DIVIDER_1 = clock not divided
+                                   * - CLK_DIVIDER_2 = clock is divided by 2
+                                   * - CLK_DIVIDER_8 = clock is divided by 8
+                                   * - CLK_DIVIDER_16 = clock is divided by 16
+                                   * - CLK_DIVIDER_32 = clock is divided by 32
+                                   * - CLK_DIVIDER_128 = clock is divided by 128
+                                   * - CLK_DIVIDER_256 = clock is divided by 256
+                                   * - CLK_DIVIDER_1024 = clock is divided by 1024 */
+    uint16_t load;        /**< Timer load: from 0 to 65535. */
     timer_irq_handlers_t handler; /**< Timer handler or call-back */
 } timer_options_t, *timer_options_pt;
 
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h
index 28e172c2634..86fc51af46e 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h
@@ -53,16 +53,16 @@ typedef struct {
     __I uint32_t VALUE; /**< 16bit current counter value */
     union {
         struct {
-            __IO uint32_t PAD0 :2; 		/**< Always reads 0 */
-            __IO uint32_t PRESCALE :3; 	/**< 0:no division, 1..7: divide by 16, 256, 2, 8, 32, 128, 1024*/
-            __IO uint32_t PAD1 :1;		/**< Always reads 0 */
-            __IO uint32_t MODE :1; 		/**< 0:free-run, 1:periodic */
-            __IO uint32_t ENABLE :1; 	/**< 0: disable, 1:enable */
-            __I  uint32_t INT :1; 		/**< interrupt status */
+            __IO uint32_t PAD0 :2;         /**< Always reads 0 */
+            __IO uint32_t PRESCALE :3;     /**< 0:no division, 1..7: divide by 16, 256, 2, 8, 32, 128, 1024*/
+            __IO uint32_t PAD1 :1;        /**< Always reads 0 */
+            __IO uint32_t MODE :1;         /**< 0:free-run, 1:periodic */
+            __IO uint32_t ENABLE :1;     /**< 0: disable, 1:enable */
+            __I  uint32_t INT :1;         /**< interrupt status */
         } BITS;
         __IO uint32_t WORD;
     } CONTROL;
-    __O uint32_t CLEAR; 	/**< Write any value to clear the interrupt */
+    __O uint32_t CLEAR;     /**< Write any value to clear the interrupt */
 } TimerReg_t, *TimerReg_pt;
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h
index 560198916c3..1d8596c158e 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h
@@ -50,20 +50,20 @@
 **************************************************************************************************/
 
 /** trim register map */
-typedef struct {						/**< REV B 			REV D	*/
-    __I uint32_t PAD0;					/**< 0x1FA0 		0x1FA0	*/
-    __I uint32_t APP_RESERVED0;			/**< 0x1FA4 		0x1FA4	*/
-    __I uint32_t APP_RESERVED1;			/**< 0x1FA8 		0x1FA8	*/
+typedef struct {                          /**< REV B             REV D    */
+    __I uint32_t PAD0;                    /**< 0x1FA0         0x1FA0    */
+    __I uint32_t APP_RESERVED0;           /**< 0x1FA4         0x1FA4    */
+    __I uint32_t APP_RESERVED1;           /**< 0x1FA8         0x1FA8    */
 #ifdef REVB
-    __I uint32_t TX_POWER;				/**< 0x1FAC */
+    __I uint32_t TX_POWER;                /**< 0x1FAC */
 #endif
-    __I uint32_t TRIM_32K_EXT;			/**< 0x1FB0 		0x1FAC	*/
-    __I uint32_t TRIM_32M_EXT;			/**< 0x1FB4 		0x1FB0	*/
+    __I uint32_t TRIM_32K_EXT;            /**< 0x1FB0         0x1FAC    */
+    __I uint32_t TRIM_32M_EXT;            /**< 0x1FB4         0x1FB0    */
 #ifdef REVD
-    __I uint32_t FVVDH_COMP_TH;			/**< 				0x1FB4 */
+    __I uint32_t FVVDH_COMP_TH;           /**<                 0x1FB4 */
 #endif
     union {
-        struct {						/* Common to REV B & REV D */
+        struct {                          /* Common to REV B & REV D */
             __I uint32_t CHANNEL11:4;
             __I uint32_t CHANNEL12:4;
             __I uint32_t CHANNEL13:4;
@@ -74,7 +74,7 @@ typedef struct {						/**< REV B 			REV D	*/
             __I uint32_t CHANNEL18:4;
         } BITS;
         __I uint32_t WORD;
-    } TX_VCO_LUT1;						/**< 0x1FB8 */
+    } TX_VCO_LUT1;                        /**< 0x1FB8 */
     union {
         struct {
             __I uint32_t CHANNEL19:4;
@@ -87,7 +87,7 @@ typedef struct {						/**< REV B 			REV D	*/
             __I uint32_t CHANNEL26:4;
         } BITS;
         __I uint32_t WORD;
-    } TX_VCO_LUT2;						/**< 0x1FBC */
+    } TX_VCO_LUT2;                        /**< 0x1FBC */
     union {
         struct {
             __I uint32_t CHANNEL11:4;
@@ -100,7 +100,7 @@ typedef struct {						/**< REV B 			REV D	*/
             __I uint32_t CHANNEL18:4;
         } BITS;
         __I uint32_t WORD;
-    } RX_VCO_LUT1;						/**< 0x1FC0 */
+    } RX_VCO_LUT1;                        /**< 0x1FC0 */
     union {
         struct {
             __I uint32_t CHANNEL19:4;
@@ -113,21 +113,21 @@ typedef struct {						/**< REV B 			REV D	*/
             __I uint32_t CHANNEL26:4;
         } BITS;
         __I uint32_t WORD;
-    } RX_VCO_LUT2;						/**< 0x1FC4 */
-    __I uint32_t ON_RESERVED0;			/**< 0x1FC8 */
-    __I uint32_t ON_RESERVED1;			/**< 0x1FCC */
-    __I uint32_t ADC_OFFSET_TRIM;		/**< 0x1FD0 */
-    __I uint32_t TX_PRE_CHIPS;			/**< 0x1FD4 */
-    __I uint32_t TX_CHAIN_TRIM;			/**< 0x1FD8 */
-    __I uint32_t PLL_VCO_TAP_LOCATION;	/**< 0x1FDC */
-    __I uint32_t PLL_TRIM;				/**< 0x1FE0 */
-    __I uint32_t RSSI_OFFSET;			/**< 0x1FE4 */
-    __I uint32_t RX_CHAIN_TRIM;			/**< 0x1FE8 */
-    __I uint32_t PMU_TRIM;				/**< 0x1FEC */
-    __I uint32_t WR_SEED_RD_RAND;		/**< 0x1FF0 */
-    __I uint32_t WAFER_LOCATION;		/**< 0x1FF4 */
-    __I uint32_t LOT_NUMBER;			/**< 0x1FF8 */
-    __I uint32_t REVISION_CODE;			/**< 0x1FFC */
+    } RX_VCO_LUT2;                        /**< 0x1FC4 */
+    __I uint32_t ON_RESERVED0;            /**< 0x1FC8 */
+    __I uint32_t ON_RESERVED1;            /**< 0x1FCC */
+    __I uint32_t ADC_OFFSET_TRIM;         /**< 0x1FD0 */
+    __I uint32_t TX_PRE_CHIPS;            /**< 0x1FD4 */
+    __I uint32_t TX_CHAIN_TRIM;           /**< 0x1FD8 */
+    __I uint32_t PLL_VCO_TAP_LOCATION;    /**< 0x1FDC */
+    __I uint32_t PLL_TRIM;                /**< 0x1FE0 */
+    __I uint32_t RSSI_OFFSET;             /**< 0x1FE4 */
+    __I uint32_t RX_CHAIN_TRIM;           /**< 0x1FE8 */
+    __I uint32_t PMU_TRIM;                /**< 0x1FEC */
+    __I uint32_t WR_SEED_RD_RAND;         /**< 0x1FF0 */
+    __I uint32_t WAFER_LOCATION;          /**< 0x1FF4 */
+    __I uint32_t LOT_NUMBER;              /**< 0x1FF8 */
+    __I uint32_t REVISION_CODE;           /**< 0x1FFC */
 } TrimReg_t, *TrimReg_pt;
 
 #endif /* TRIM_MAP_H_ */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/types.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/types.h
index 88153af0807..d0e7757d9a2 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/types.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/types.h
@@ -35,17 +35,17 @@
 #include <stdint.h>
 #include <stdio.h>
 
-typedef unsigned char		BYTE;
-typedef unsigned short		WORD;
-typedef unsigned long		DWORD;
-typedef unsigned long long	QWORD;
+typedef unsigned char        BYTE;
+typedef unsigned short       WORD;
+typedef unsigned long        DWORD;
+typedef unsigned long long   QWORD;
 
 
 typedef unsigned char boolean;
 
-#define True		(1)
-#define False		(0)
+#define True        (1)
+#define False       (0)
 
-#define Null		NULL
+#define Null        NULL
 
 #endif /* _UTIL_TYPES_H_ */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h
index dcba674cdd7..6329156ccea 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h
@@ -59,45 +59,45 @@ typedef struct uart_16c550_options {
     uint8_t irq; /**< The IRQ number of the IRQ associated to the device. */
 } uart_16c550_options_t, *uart_16c550_options_pt;
 
-#define UART_NUM		2
+#define UART_NUM        2
 
-#define CTS_ASSERT		1
-#define CTS_UNASSERT	0
-#define RTS_ASSERT		1
-#define RTS_UNASSERT	0
+#define CTS_ASSERT      1
+#define CTS_UNASSERT    0
+#define RTS_ASSERT      1
+#define RTS_UNASSERT    0
 
-#define UART_ERROR_INSUFFICIENT_SPACE 	((uint8_t)0xF0)
+#define UART_ERROR_INSUFFICIENT_SPACE   ((uint8_t)0xF0)
 #define UART_ERROR_TOO_BIG              ((uint8_t)0xF1)
 
 /** The depth of the hardware FIFOs. */
-#define UART_HW_FIFO_DEPTH		16
+#define UART_HW_FIFO_DEPTH        16
 
 /** The length of the receive buffer in software. */
-#define UART_RX_BUFFER_LENGTH		(1<<8)
-#define UART_TX_BUFFER_LENGTH		(1<<8)
+#define UART_RX_BUFFER_LENGTH        (1<<8)
+#define UART_TX_BUFFER_LENGTH        (1<<8)
 
-#define STATUS_INVALID_PARAMETER	0x1
-#define STATUS_SUCCESS			 	0x1
+#define STATUS_INVALID_PARAMETER    0x1
+#define STATUS_SUCCESS              0x1
 
-#define UART_LCR_DATALEN_BIT_POS	0
-#define UART_LCR_STPBIT_BIT_POS		2
-#define UART_LCR_PARITY_BIT_POS		3
+#define UART_LCR_DATALEN_BIT_POS    0
+#define UART_LCR_STPBIT_BIT_POS     2
+#define UART_LCR_PARITY_BIT_POS     3
 
 #define UART_FCS_RX_FIFO_RST_BIT_POS 1
 #define UART_FCS_TX_FIFO_RST_BIT_POS 2
 
-#define UART_RX_IRQ		0x0
-#define UART_TX_IRQ		0x1
+#define UART_RX_IRQ        0x0
+#define UART_TX_IRQ        0x1
 
-#define UART_RX_BUFFER_LEN_MAX	16
+#define UART_RX_BUFFER_LEN_MAX    16
 
-#define UART_LSR_TX_EMPTY_MASK		0x40
-#define UART_LSR_RX_DATA_READY_MASK	0x01
+#define UART_LSR_TX_EMPTY_MASK        0x40
+#define UART_LSR_RX_DATA_READY_MASK   0x01
 
-#define UART_IER_TX_EMPTY_MASK		0x02
-#define UART_IER_RX_DATA_READY_MASK	0x01
+#define UART_IER_TX_EMPTY_MASK        0x02
+#define UART_IER_RX_DATA_READY_MASK   0x01
 
-#define UART_DEFAULT_BAUD	9600
+#define UART_DEFAULT_BAUD    9600
 
 /** Interrupt handler for 16C550 UART devices; to be called from an actual ISR.
  * @param membase The memory base for the device that corresponds to the IRQ.
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h
index b26e37d8faf..b33ca489fd9 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h
@@ -47,8 +47,8 @@
 #define DDSR (uint8_t)0x02
 #define TERI (uint8_t)0x04
 #define DDCD (uint8_t)0x08
-//#define CTS	 (uint8_t)0x10
-#define DSR	 (uint8_t)0x20
+//#define CTS   (uint8_t)0x10
+#define DSR     (uint8_t)0x20
 #define RI   (uint8_t)0x40
 #define DCD  (uint8_t)0x80
 #define IER_PWRDNENACTIVE          ((uint8_t)(1<<5))
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h
index 8b07f3adb48..fd63cc82204 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h
@@ -137,25 +137,25 @@ typedef struct {
 
 #ifdef REVD
 typedef struct {
-    __IO uint32_t LOAD; 		/**< 0x4000A000 Contains the value from which the counter is decremented.  When this register is written to the count is immediately restarted from the new value.  The minimum valid value is 1. */
+    __IO uint32_t LOAD;         /**< 0x4000A000 Contains the value from which the counter is decremented.  When this register is written to the count is immediately restarted from the new value.  The minimum valid value is 1. */
     __I uint32_t CURRENT_VALUE; /**< 0x4000A004 Gives the current value of the decrementing counter */
     union {
         struct {
-            __IO uint32_t WDT_EN :1; 	/**< Watchdog enable, 0 � Watchdog disabled, 1 � Watchdog enabled */
+            __IO uint32_t WDT_EN :1;     /**< Watchdog enable, 0 � Watchdog disabled, 1 � Watchdog enabled */
         } BITS;
         __IO uint32_t WORD;
-    } CONTROL;			/* 0x4000A008 */
-    __O uint32_t KICK; 	/**< 0x4000A00C A write of any value to this register reloads the value register from the load register */
-    __O uint32_t LOCK; 	/**< 0x4000A010 Use of this register causes write-access to all other registers to be disabled.  This is to prevent rogue software from disabling the watchdog functionality.  Writing a value of 0x1ACCE551 enables write access to all other registers.  Writing any other value disables write access.  A read from this register only returns the bottom bit�, 0 � Write access is enabled, 1 � Write access is disabled */
+    } CONTROL;             /* 0x4000A008 */
+    __O uint32_t KICK;     /**< 0x4000A00C A write of any value to this register reloads the value register from the load register */
+    __O uint32_t LOCK;     /**< 0x4000A010 Use of this register causes write-access to all other registers to be disabled.  This is to prevent rogue software from disabling the watchdog functionality.  Writing a value of 0x1ACCE551 enables write access to all other registers.  Writing any other value disables write access.  A read from this register only returns the bottom bit�, 0 � Write access is enabled, 1 � Write access is disabled */
     union {
         struct {
-            __I uint32_t WRITE_BUSY_ANY :1; 	/**< Busy writing any register */
-            __I uint32_t WRITE_BUSY_LOAD :1; 	/**< Busy writing the load register */
+            __I uint32_t WRITE_BUSY_ANY :1;     /**< Busy writing any register */
+            __I uint32_t WRITE_BUSY_LOAD :1;    /**< Busy writing the load register */
             __I uint32_t WRITE_BUSY_CONTROL :1; /**< Busy writing the control enable register */
-            __IO uint32_t WRITE_ERROR :1;		/**< Error bit.  Set when write occurs before previous write completes (busy) */
+            __IO uint32_t WRITE_ERROR :1;       /**< Error bit.  Set when write occurs before previous write completes (busy) */
         } BITS;
         __IO uint32_t WORD;
-    } STATUS;	/* 0x4000A014 */
+    } STATUS;    /* 0x4000A014 */
 } WdtReg_t, *WdtReg_pt;
 #endif /* REVD */
 #endif /* WDT_MAP_H_ */
diff --git a/targets/targets.json b/targets/targets.json
index 0e92aebb436..1869cf92755 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -2020,7 +2020,7 @@
         "post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"},
         "macros": ["REVD", "CM3", "CPU_NCS36510", "TARGET_NCS36510"],
         "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
-        "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI"],
+        "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "LOWPOWERTIMER"],
         "release_versions": ["2", "5"]
     },
     "NUMAKER_PFM_M453": {

From acd91ec0982c7b26d7acd58f9dc4e6e8d041068e Mon Sep 17 00:00:00 2001
From: pradeep-gr <pradeep.gr@onsemi.com>
Date: Wed, 12 Oct 2016 19:09:57 +0530
Subject: [PATCH 57/89] Low power timer fine tuned for smaller duration

---
 targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c | 27 +++++++++++----------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c
index 02b61de6286..a3e35b0b681 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c
@@ -79,7 +79,7 @@ void fRtcInit(void)
     NVIC_ClearPendingIRQ(Rtc_IRQn);
     NVIC_EnableIRQ(Rtc_IRQn);
 
-    while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
+    while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
 
     return;
 }
@@ -93,14 +93,14 @@ void fRtcFree(void)
     /* disable interruption associated with the rtc */
     NVIC_DisableIRQ(Rtc_IRQn);
 
-    while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
+    while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
 }
 
 /* See rtc.h for details */
 void fRtcSetInterrupt(uint32_t timestamp)
 {
-    SubSecond          = False;
-    uint32_t Second    = False;
+    SubSecond             = False;
+    uint32_t Second       = False;
     uint8_t DividerAdjust = 1;
 
     if(timestamp) {
@@ -137,6 +137,7 @@ void fRtcSetInterrupt(uint32_t timestamp)
                 RTCREG->SUB_SECOND_ALARM = SubSecond;    /* Write to sub second alarm */
 
                 /* Enable sub second interrupt */
+                while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
                 RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
             }
         }
@@ -151,7 +152,7 @@ void fRtcDisableInterrupt(void)
 {
     /* Disable subsec/sec interrupt */
     RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
-    while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
+    while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
 }
 
 /* See rtc.h for details */
@@ -159,7 +160,7 @@ void fRtcEnableInterrupt(void)
 {
     /* Disable subsec/sec interrupt */
     RTCREG->CONTROL.WORD |= ((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
-    while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
+    while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
 }
 
 /* See rtc.h for details */
@@ -237,40 +238,40 @@ void fRtcWrite(uint64_t RtcTimeus)
 /* See rtc.h for details */
 void fRtcHandler(void)
 {
-	while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
     /* SUB_SECOND/SECOND interrupt occured */
     volatile uint32_t TempStatus = RTCREG->STATUS.WORD;
 
-    /* disable all interrupts */
-    RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
+    /* Disable RTC interrupt */
+    NVIC_DisableIRQ(Rtc_IRQn);
 
     /* Clear sec & sub_sec interrupts */
     RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
                               (True << RTC_INT_CLR_SEC_BIT_POS));
 
-    /* TODO  ANDing SUB_SEC & SEC interrupt - work around for RTC issue - will be solved in REV G */
+    /* TODO  ANDing SUB_SEC & SEC interrupt - work around for RTC issue - will be resolved in REV G */
     if(TempStatus & RTC_SEC_INT_STATUS_MASK) {
         /* Second interrupt occured */
         if(SubSecond > False) {
             /* Set SUB SEC_ALARM */
             RTCREG->SUB_SECOND_ALARM = SubSecond + RTCREG->SUB_SECOND_COUNTER;
             /* Enable sub second interrupt */
-            while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
             RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
         } else {
             /* We reach here after second interrupt is occured */
-            while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
             RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
                                     (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
         }
     } else {
         /* We reach here after sub_second or (Sub second + second) interrupt occured */
-        while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
 		/* Disable Second and sub_second interrupt */
         RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
                                 (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
     }
 
+	NVIC_EnableIRQ(Rtc_IRQn);
+	
+	while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
+	
 	lp_ticker_irq_handler();
 }
 

From 7711f0a362562b89f0140bbf956e69e3e0649dae Mon Sep 17 00:00:00 2001
From: Alessandro Angelino <alessandro.angelino@arm.com>
Date: Fri, 16 Sep 2016 11:51:19 +0100
Subject: [PATCH 58/89] EFM32: Make NVIC functions virtualizable

With CMSIS 5, the NVIC functions are virtualizable. Rename the EFM32
NVIC functions to support being virtualized.
---
 .../TARGET_EFM32/TARGET_EFM32GG_STK3700/device/cmsis_nvic.c   | 4 ++--
 .../TARGET_EFM32/TARGET_EFM32GG_STK3700/device/cmsis_nvic.h   | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/cmsis_nvic.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/cmsis_nvic.c
index 1170f85a31f..b238daa7437 100644
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/cmsis_nvic.c
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/cmsis_nvic.c
@@ -12,7 +12,7 @@ extern uint32_t __start_vector_table__;		  // Dynamic vector positioning in GCC
 #define NVIC_RAM_VECTOR_ADDRESS (0x20000000)  // Vectors positioned at start of RAM
 #define NVIC_FLASH_VECTOR_ADDRESS (0x0)       // Initial vector position in flash
 
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
     uint32_t *vectors = (uint32_t*)SCB->VTOR;
     uint32_t i;
 
@@ -41,7 +41,7 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
     vectors[IRQn + 16] = vector;
 }
 
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
     uint32_t *vectors = (uint32_t*)SCB->VTOR;
     return vectors[IRQn + 16];
 }
diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/cmsis_nvic.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/cmsis_nvic.h
index 999cf80223f..a8cae966d3c 100644
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/cmsis_nvic.h
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/cmsis_nvic.h
@@ -16,8 +16,8 @@
 extern "C" {
 #endif
 
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
+void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t __NVIC_GetVector(IRQn_Type IRQn);
 
 #ifdef __cplusplus
 }

From ab1ed711ae7af8469ed41ffc85eb1a84ae6c645a Mon Sep 17 00:00:00 2001
From: Alessandro Angelino <alessandro.angelino@arm.com>
Date: Fri, 16 Sep 2016 11:51:19 +0100
Subject: [PATCH 59/89] EFM32: Use SECURE_ACCESS to access the ROM table

To allow enabling of uVisor on EFM32, the ROM table must be accessed
through the CMSIS-provided SECURE_ACCESS macro.
---
 .../TARGET_EFM32/emlib/src/em_system.c           | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c
index 661c384f4b8..d48273905ad 100644
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c
@@ -32,6 +32,7 @@
 
 #include "em_system.h"
 #include "em_assert.h"
+#include "core_cmSecureAccess.h"
 
 /***************************************************************************//**
  * @addtogroup EM_Library
@@ -61,19 +62,24 @@ void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev)
 
   EFM_ASSERT(rev);
 
+  uint32_t pid0 = SECURE_READ(&(ROMTABLE->PID0));
+  uint32_t pid1 = SECURE_READ(&(ROMTABLE->PID1));
+  uint32_t pid2 = SECURE_READ(&(ROMTABLE->PID2));
+  uint32_t pid3 = SECURE_READ(&(ROMTABLE->PID3));
+
   /* CHIP FAMILY bit [5:2] */
-  tmp  = (((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2);
+  tmp  = (((pid1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2);
   /* CHIP FAMILY bit [1:0] */
-  tmp |=  ((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT);
+  tmp |=  ((pid0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT);
   rev->family = tmp;
 
   /* CHIP MAJOR bit [3:0] */
-  rev->major = (ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT;
+  rev->major = (pid0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT;
 
   /* CHIP MINOR bit [7:4] */
-  tmp  = (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);
+  tmp  = (((pid2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);
   /* CHIP MINOR bit [3:0] */
-  tmp |=  ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);
+  tmp |=  ((pid3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT);
   rev->minor = tmp;
 }
 

From d190ec0b7d645210412300a4912703b4d2717c34 Mon Sep 17 00:00:00 2001
From: Alessandro Angelino <alessandro.angelino@arm.com>
Date: Fri, 16 Sep 2016 11:51:19 +0100
Subject: [PATCH 60/89] EFM32: Add support for uVisor

---
 .../device/TOOLCHAIN_GCC_ARM/efm32gg.ld       | 141 +++++++++++++++---
 .../TOOLCHAIN_GCC_ARM/startup_efm32gg.S       |  22 +--
 2 files changed, 124 insertions(+), 39 deletions(-)

diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/TOOLCHAIN_GCC_ARM/efm32gg.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/TOOLCHAIN_GCC_ARM/efm32gg.ld
index da5b10d6aa3..85b009eeb57 100644
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/TOOLCHAIN_GCC_ARM/efm32gg.ld
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/TOOLCHAIN_GCC_ARM/efm32gg.ld
@@ -9,6 +9,9 @@
 /* Version 4.2.0 */
 /*                                                                  */
 
+STACK_SIZE = 0x400;
+HEAP_SIZE = 0xC00;
+
 MEMORY
 {
   FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1048576
@@ -53,6 +56,11 @@ __vector_size = 0xDC;
  */
 ENTRY(Reset_Handler)
 
+/* Note: The uVisor expects the text section at a fixed location, as specified
+             by the porting process configuration parameter: FLASH_OFFSET. */
+__UVISOR_TEXT_OFFSET = 0x100;
+__UVISOR_TEXT_START = ORIGIN(FLASH) + __UVISOR_TEXT_OFFSET;
+
 SECTIONS
 {
   .text :
@@ -62,6 +70,13 @@ SECTIONS
     __Vectors_Size = __Vectors_End - __Vectors;
     __end__ = .;
 
+    /* uVisor code and data */
+    . = __UVISOR_TEXT_OFFSET;
+    . = ALIGN(4);
+    __uvisor_main_start = .;
+    *(.uvisor.main)
+    __uvisor_main_end = .;
+
     *(.text*)
 
     KEEP(*(.init))
@@ -132,10 +147,51 @@ SECTIONS
   } > FLASH
   */
 
-  __etext = .;
+  /* Ensure that the uVisor BSS section is put first in SRAM. */
+  /* Note: The uVisor expects this section at a fixed location, as specified
+           by the porting process configuration parameter: SRAM_OFFSET. */
+  __UVISOR_SRAM_OFFSET = 0x0;
+  __UVISOR_BSS_START = ORIGIN(RAM) + __UVISOR_SRAM_OFFSET;
+  .uvisor.bss __UVISOR_BSS_START (NOLOAD):
+  {
+    . = ALIGN(32);
+    __uvisor_bss_start = .;
+
+    /* uVisor main BSS section */
+    . = ALIGN(32);
+    __uvisor_bss_main_start = .;
+    KEEP(*(.keep.uvisor.bss.main))
+    . = ALIGN(32);
+    __uvisor_bss_main_end = .;
 
-  .data : AT (__etext)
+    /* Secure boxes BSS section */
+    . = ALIGN(32);
+    __uvisor_bss_boxes_start = .;
+    KEEP(*(.keep.uvisor.bss.boxes))
+    . = ALIGN(32);
+    __uvisor_bss_boxes_end = .;
+
+    . = ALIGN(32);
+    __uvisor_bss_end = .;
+  } > RAM
+
+  /* Heap space for the page allocator */
+  .page_heap (NOLOAD) :
   {
+    . = ALIGN(32);
+    __uvisor_page_start = .;
+    KEEP(*(.keep.uvisor.page_heap))
+
+    . = ALIGN( (1 << LOG2CEIL(LENGTH(RAM))) / 8);
+
+    __uvisor_page_end = .;
+  } > RAM
+
+  .data :
+  {
+    PROVIDE(__etext = LOADADDR(.data));    /* Define a global symbol at end of code, */
+    PROVIDE(__DATA_ROM = LOADADDR(.data)); /* Symbol is used by startup for data initialization. */
+
     __data_start__ = .;
     *("dma")
     PROVIDE( __start_vector_table__ = .);
@@ -171,6 +227,51 @@ SECTIONS
     /* All data end */
     __data_end__ = .;
 
+  } > RAM AT > FLASH
+
+  /* uVisor configuration section
+   * This section must be located after all other flash regions. */
+  .uvisor.secure :
+  {
+    . = ALIGN(32);
+    __uvisor_secure_start = .;
+
+    /* uVisor secure boxes configuration tables */
+    . = ALIGN(32);
+    __uvisor_cfgtbl_start = .;
+    KEEP(*(.keep.uvisor.cfgtbl))
+    . = ALIGN(32);
+    __uvisor_cfgtbl_end = .;
+
+    /* Pointers to the uVisor secure boxes configuration tables */
+    /* Note: Do not add any further alignment here, as uVisor will need to
+             have access to the exact list of pointers. */
+    __uvisor_cfgtbl_ptr_start = .;
+    KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
+    KEEP(*(.keep.uvisor.cfgtbl_ptr))
+    __uvisor_cfgtbl_ptr_end = .;
+
+    /* Pointers to all boxes register gateways. These are grouped here to
+       allow discoverability and firmware verification. */
+    __uvisor_register_gateway_ptr_start = .;
+    KEEP(*(.keep.uvisor.register_gateway_ptr))
+    __uvisor_register_gateway_ptr_end = .;
+
+    . = ALIGN(32);
+    __uvisor_secure_end = .;
+  } > FLASH
+
+  /* Uninitialized data section
+   * This region is not initialized by the C/C++ library and can be used to
+   * store state across soft reboots. */
+  .uninitialized (NOLOAD):
+  {
+    . = ALIGN(32);
+    __uninitialized_start = .;
+    *(.uninitialized)
+    KEEP(*(.keep.uninitialized))
+    . = ALIGN(32);
+    __uninitialized_end = .;
   } > RAM
 
   .bss :
@@ -183,33 +284,29 @@ SECTIONS
     __bss_end__ = .;
   } > RAM
 
-  .heap (COPY):
+  __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+  __stack = __StackTop;
+  __StackLimit = __StackTop - STACK_SIZE;
+
+  .heap (NOLOAD):
   {
+    __uvisor_heap_start = .;
     __HeapBase = .;
     __end__ = .;
     end = __end__;
     _end = __end__;
-    KEEP(*(.heap*))
-    __HeapLimit = .;
+    . += HEAP_SIZE;
   } > RAM
 
-  /* .stack_dummy section doesn't contains any symbols. It is only
-   * used for linker to calculate size of stack sections, and assign
-   * values to stack symbols later */
-  .stack_dummy (COPY):
-  {
-    KEEP(*(.stack*))
-  } > RAM
-
-  /* Set stack top to end of RAM, and stack limit move down by
-   * size of stack_dummy section */
-  __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-  __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-  PROVIDE(__stack = __StackTop);
+  __HeapLimit = __StackLimit;
+  __uvisor_heap_end = __StackLimit;
 
-  /* Check if data + heap + stack exceeds RAM limit */
-  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+  /* Provide physical memory boundaries for uVisor. */
+  __uvisor_flash_start = ORIGIN(FLASH);
+  __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
+  __uvisor_sram_start = ORIGIN(RAM);
+  __uvisor_sram_end = ORIGIN(RAM) + LENGTH(RAM);
 
-  /* Check if FLASH usage exceeds FLASH size */
-  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")
+  /* Check if FLASH usage exceeds FLASH size. */
+  ASSERT(LENGTH(FLASH) >= __uvisor_secure_end, "FLASH memory overflowed!")
 }
diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/TOOLCHAIN_GCC_ARM/startup_efm32gg.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/TOOLCHAIN_GCC_ARM/startup_efm32gg.S
index 0566657b2e9..2ef61c90261 100644
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/TOOLCHAIN_GCC_ARM/startup_efm32gg.S
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/TOOLCHAIN_GCC_ARM/startup_efm32gg.S
@@ -49,23 +49,6 @@ __StackLimit:
 __StackTop:
     .size       __StackTop, . - __StackTop
 
-    .section    .heap
-    .align      3
-#ifdef __HEAP_SIZE
-    .equ        Heap_Size, __HEAP_SIZE
-#else
-    .equ        Heap_Size, 0x00000C00
-#endif
-    .globl      __HeapBase
-    .globl      __HeapLimit
-__HeapBase:
-    .if Heap_Size
-    .space      Heap_Size
-    .endif
-    .size       __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size       __HeapLimit, . - __HeapLimit
-
     .section    .vectors
     .align      2
     .globl      __Vectors
@@ -144,6 +127,11 @@ Reset_Handler:
     blx     r0
 #endif
 
+#if defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)
+    ldr r0, =uvisor_init
+    blx r0
+#endif /* defined(FEATURE_UVISOR) && defined(UVISOR_SUPPORTED) */
+
 /*  Firstly it copies data from read only memory to RAM. There are two schemes
  *  to copy. One can copy more than one sections. Another can only copy
  *  one section.  The former scheme needs more instructions and read-only

From eb2b7f05f2ef103d3c61970e10aaa96fd26bef67 Mon Sep 17 00:00:00 2001
From: "andreas.larsson" <andreas.larsson@connectblue.com>
Date: Mon, 10 Oct 2016 15:42:47 +0200
Subject: [PATCH 61/89] Enabled TRNG functionality for UBLOX_EVK_ODIN_W2
 target.

---
 .../TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/objects.h         | 4 +++-
 targets/targets.json                                          | 4 ++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/objects.h
index 12cac5d31f2..d92fa159012 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/objects.h
@@ -60,7 +60,9 @@ struct analogin_s {
     uint8_t channel;
 };
 
-
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
 
 #include "common_objects.h"
 struct can_s {
diff --git a/targets/targets.json b/targets/targets.json
index 1869cf92755..a420d772925 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -1183,10 +1183,10 @@
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
-        "extra_labels": ["STM", "STM32F4", "STM32F439", "STM32F439ZI"],
+        "extra_labels": ["STM", "STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx"],
         "macros": ["HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED"],
         "inherits": ["Target"],
-        "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
         "features": ["LWIP"],
         "release_versions": ["5"],
         "device_name": "STM32F439ZI"

From e965c34e66372fae74579bed6d313a7dd6ba9186 Mon Sep 17 00:00:00 2001
From: "andreas.larsson" <andreas.larsson@connectblue.com>
Date: Mon, 10 Oct 2016 18:55:46 +0200
Subject: [PATCH 62/89] Fixed wrong stack pointer

---
 .../device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.S              | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.S
index 75bc33a56cf..2a04a2f6f01 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.S
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.S
@@ -39,7 +39,7 @@
 ; 
 ;*******************************************************************************
 
-__initial_sp    EQU     0x20020000 ; Top of RAM
+__initial_sp    EQU     0x20030000 ; Top of RAM
 
                 PRESERVE8
                 THUMB

From 857786e303a63637a543dde8a124c53d7f93d55c Mon Sep 17 00:00:00 2001
From: Wolfgang Betz <wolfgang.betz@st.com>
Date: Mon, 10 Oct 2016 11:54:33 +0200
Subject: [PATCH 63/89] I2C bugfix 'i2c_stop()' timeout

- Remove waiting for 'BTF' flag in 'i2c_stop()':
  When 'i2c_stop()' is called from 'i2c_read()' or 'i2c_write()' flag 'BTF'
  has already been cleared (indirectly) by the calling functions and therefore
  'i2c_stop()' would mistakenly always run into a timeout.
- Delay clock enabling until pins are configured:
  Enabling the I2C bus clock before configuring its pins might in rare
  cases lead to HW faults on the bus.
- Move initialization of 'handle->Instance' to function 'i2c_reset()':
  As 'i2c_reset()' uses '__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)' field
  'handle->Instance' must have been initialized before doing so. Therefore,
  this operation has been anticipated by moving it from function
  'i2c_frequency()' to function 'i2c_reset()'.
---
 targets/TARGET_STM/TARGET_STM32F4/i2c_api.c | 27 ++++++---------------
 1 file changed, 7 insertions(+), 20 deletions(-)

diff --git a/targets/TARGET_STM/TARGET_STM32F4/i2c_api.c b/targets/TARGET_STM/TARGET_STM32F4/i2c_api.c
index dc5f6cc4d50..90e1c5f5994 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/i2c_api.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/i2c_api.c
@@ -68,7 +68,6 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
     // Enable I2C1 clock and pinout if not done
     if ((obj_s->i2c == I2C_1) && !i2c1_inited) {
         i2c1_inited = 1;
-        __I2C1_CLK_ENABLE();
         // Configure I2C pins
         pinmap_pinout(sda, PinMap_I2C_SDA);
         pinmap_pinout(scl, PinMap_I2C_SCL);
@@ -78,11 +77,11 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
         obj_s->event_i2cIRQ = I2C1_EV_IRQn;
         obj_s->error_i2cIRQ = I2C1_ER_IRQn;
 #endif
+        __I2C1_CLK_ENABLE();
     }
     // Enable I2C2 clock and pinout if not done
     if ((obj_s->i2c == I2C_2) && !i2c2_inited) {
         i2c2_inited = 1;
-        __I2C2_CLK_ENABLE();
         // Configure I2C pins
         pinmap_pinout(sda, PinMap_I2C_SDA);
         pinmap_pinout(scl, PinMap_I2C_SCL);
@@ -92,12 +91,12 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
         obj_s->event_i2cIRQ = I2C2_EV_IRQn;
         obj_s->error_i2cIRQ = I2C2_ER_IRQn;
 #endif
+        __I2C2_CLK_ENABLE();
     }
 #if defined I2C3_BASE
     // Enable I2C3 clock and pinout if not done
     if ((obj_s->i2c == I2C_3) && !i2c3_inited) {
         i2c3_inited = 1;
-        __I2C3_CLK_ENABLE();
         // Configure I2C pins
         pinmap_pinout(sda, PinMap_I2C_SDA);
         pinmap_pinout(scl, PinMap_I2C_SCL);
@@ -107,6 +106,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
         obj_s->event_i2cIRQ = I2C3_EV_IRQn;
         obj_s->error_i2cIRQ = I2C3_ER_IRQn;
 #endif
+        __I2C3_CLK_ENABLE();
     }
 #endif
 
@@ -114,7 +114,6 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
     // Enable I2C3 clock and pinout if not done
     if ((obj_s->i2c == FMPI2C_1) && !fmpi2c1_inited) {
         fmpi2c1_inited = 1;
-        __HAL_RCC_FMPI2C1_CLK_ENABLE();
         // Configure I2C pins
         pinmap_pinout(sda, PinMap_I2C_SDA);
         pinmap_pinout(scl, PinMap_I2C_SCL);
@@ -124,6 +123,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
         obj_s->event_i2cIRQ = FMPI2C1_EV_IRQn;
         obj_s->error_i2cIRQ = FMPI2C1_ER_IRQn;
 #endif
+        __HAL_RCC_FMPI2C1_CLK_ENABLE();
     }
 #endif
 
@@ -151,8 +151,6 @@ void i2c_frequency(i2c_t *obj, int hz)
     struct i2c_s *obj_s = I2C_S(obj);
     I2C_HandleTypeDef *handle = &(obj_s->handle);
 
-    handle->Instance = (I2C_TypeDef *)(obj_s->i2c);
-
     MBED_ASSERT((hz > 0) && (hz <= 400000));
 
     // wait before init
@@ -212,20 +210,8 @@ inline int i2c_start(i2c_t *obj) {
 }
 
 inline int i2c_stop(i2c_t *obj) {
-
-    int timeout;
     struct i2c_s *obj_s = I2C_S(obj);
     I2C_TypeDef *i2c = (I2C_TypeDef *)obj_s->i2c;
-    I2C_HandleTypeDef *handle = &(obj_s->handle);
-
-    //Wait Byte transfer finished before sending stop
-    timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == RESET) {
-        timeout--;
-        if (timeout == 0) {
-            return 0;
-        }
-    }
 
     // Generate the STOP condition
     i2c->CR1 |= I2C_CR1_STOP;
@@ -361,7 +347,7 @@ int i2c_byte_write(i2c_t *obj, int data) {
 
     handle->Instance->DR = (uint8_t)data;
 
-    // Wait until the byte (might be the adress) is transmitted
+    // Wait until the byte (might be the address) is transmitted
     timeout = FLAG_TIMEOUT;
     while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE) == RESET) &&
             (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == RESET) &&
@@ -385,6 +371,8 @@ void i2c_reset(i2c_t *obj) {
     struct i2c_s *obj_s = I2C_S(obj);
     I2C_HandleTypeDef *handle = &(obj_s->handle);
 
+    handle->Instance = (I2C_TypeDef *)(obj_s->i2c);
+
     // wait before reset
     timeout = LONG_TIMEOUT;
     while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (timeout-- != 0));
@@ -570,7 +558,6 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) {
         }
     }
 
-
     /* Clear AF flag */
     __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_AF);
 

From b2671a367cbf5e5a281a66d8cc40d0495096134e Mon Sep 17 00:00:00 2001
From: Bartek Szatkowski <bulislaw@linux.com>
Date: Tue, 11 Oct 2016 13:30:20 -0500
Subject: [PATCH 64/89] Accept profile name as well as file path for
 tools/make.py --profile

--profile can be used with just a profile name eg. default, debug as
long as <name>.json file is in default profile directory.
---
 tools/options.py | 13 +++++++++++--
 tools/utils.py   | 15 ++++++++++++++-
 2 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/tools/options.py b/tools/options.py
index 0c3b016d95e..8ffab53bc91 100644
--- a/tools/options.py
+++ b/tools/options.py
@@ -16,12 +16,13 @@
 """
 from json import load
 from os.path import join, dirname
+from os import listdir
 from argparse import ArgumentParser
 from tools.toolchains import TOOLCHAINS
 from tools.targets import TARGET_NAMES
 from tools.utils import argparse_force_uppercase_type, \
     argparse_lowercase_hyphen_type, argparse_many, \
-    argparse_filestring_type, args_error
+    argparse_filestring_type, args_error, argparse_profile_filestring_type
 
 def get_default_options_parser(add_clean=True, add_options=True,
                                add_app_config=False):
@@ -73,7 +74,9 @@ def get_default_options_parser(add_clean=True, add_options=True,
 
     if add_options:
         parser.add_argument("--profile", dest="profile", action="append",
-                            type=argparse_filestring_type,
+                            type=argparse_profile_filestring_type,
+                            help="Build profile to use. Can be either path to json" \
+                            "file or one of the default one ({})".format(", ".join(list_profiles())),
                             default=[])
     if add_app_config:
         parser.add_argument("--app-config", default=None, dest="app_config",
@@ -82,6 +85,12 @@ def get_default_options_parser(add_clean=True, add_options=True,
 
     return parser
 
+def list_profiles():
+    """Lists available build profiles
+
+    Checks default profile directory (mbed-os/tools/profiles/) for all the json files and return list of names only
+    """
+    return [fn.replace(".json", "") for fn in listdir(join(dirname(__file__), "profiles")) if fn.endswith(".json")]
 
 def extract_profile(parser, options, toolchain):
     """Extract a Toolchain profile from parsed options
diff --git a/tools/utils.py b/tools/utils.py
index 9ad74de63dd..734dfae0e07 100644
--- a/tools/utils.py
+++ b/tools/utils.py
@@ -22,7 +22,7 @@
 from os import listdir, remove, makedirs
 from shutil import copyfile
 from os.path import isdir, join, exists, split, relpath, splitext, abspath
-from os.path import commonprefix, normpath
+from os.path import commonprefix, normpath, dirname
 from subprocess import Popen, PIPE, STDOUT, call
 import json
 from collections import OrderedDict
@@ -435,6 +435,19 @@ def argparse_filestring_type(string):
         raise argparse.ArgumentTypeError(
             "{0}"" does not exist in the filesystem.".format(string))
 
+def argparse_profile_filestring_type(string):
+    """ An argument parser that verifies that a string passed in is either
+    absolute path or a file name (expanded to
+    mbed-os/tools/profiles/<fname>.json) of a existing file"""
+    fpath = join(dirname(__file__), "profiles/{}.json".format(string))
+    if exists(string):
+        return string
+    elif exists(fpath):
+        return fpath
+    else:
+        raise argparse.ArgumentTypeError(
+            "{0} does not exist in the filesystem.".format(string))
+
 def columnate(strings, separator=", ", chars=80):
     """ render a list of strings as a in a bunch of columns
 

From ac93f9e41fabebbf89c3920793d377a702fc56f0 Mon Sep 17 00:00:00 2001
From: jeromecoutant <jerome.coutant@st.com>
Date: Wed, 12 Oct 2016 15:33:40 +0200
Subject: [PATCH 65/89] Add Arduino form factor for DISCO_F746NG and
 NUCLEO_F767ZI

---
 targets/targets.json | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/targets/targets.json b/targets/targets.json
index a420d772925..d4108cea399 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -866,6 +866,7 @@
         "extra_labels": ["STM", "STM32F7", "STM32F767", "STM32F767ZI"],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "default_toolchain": "ARM",
+        "supported_form_factors": ["ARDUINO"],
         "detect_code": ["0818"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
         "features": ["LWIP"],
@@ -1075,6 +1076,7 @@
         "extra_labels": ["STM", "STM32F7", "STM32F746", "STM32F746NG"],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "default_toolchain": "ARM",
+        "supported_form_factors": ["ARDUINO"],
         "detect_code": ["0815"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
         "features": ["LWIP"],

From 150caecf30f1e3f65ec53fed36f3af5944b62ff5 Mon Sep 17 00:00:00 2001
From: Russ Butler <russ.butler@arm.com>
Date: Wed, 12 Oct 2016 14:48:38 -0500
Subject: [PATCH 66/89] Revert "Allow max-depth specification in memap"

This reverts commit 8f9f4eefed50a60eac2f4b7004381a843f334cc2 since
it broke memory map info for IAR, ARMCC and on windows, GCC_ARM.
---
 tools/memap.py | 85 +++++++++++++++++++++++++-------------------------
 1 file changed, 43 insertions(+), 42 deletions(-)

diff --git a/tools/memap.py b/tools/memap.py
index f8bd3dd5e4d..f26e97a819f 100644
--- a/tools/memap.py
+++ b/tools/memap.py
@@ -20,7 +20,6 @@
 RE_IAR = re.compile(
     r'^\s+(.+)\s+(zero|const|ro code|inited|uninit)\s'
     r'+0x(\w{8})\s+0x(\w+)\s+(.+)\s.+$')
-RE_LIB_MATCH = re.compile("^.*/(.*\.a)\((.*)\)$")
 
 class MemapParser(object):
     """An object that represents parsed results, parses the memory map files,
@@ -38,16 +37,13 @@ class MemapParser(object):
 
     # sections to print info (generic for all toolchains)
     sections = ('.text', '.data', '.bss', '.heap', '.stack')
-    MAXDEPTH = object()
 
-    def __init__(self, depth=2):
+    def __init__(self, detailed_misc=False):
         """ General initialization
         """
-
-        self.depth = depth
-
-        self.mapfile = None
-
+        # 
+        self.detailed_misc = detailed_misc
+        
         # list of all modules and their sections
         self.modules = dict()
 
@@ -102,7 +98,7 @@ def check_new_section_gcc(self, line):
         else:
             return False         # everything else, means no change in section
 
-
+    
     def path_object_to_module_name(self, txt):
         """ Parse a path to object file to extract it's module and object data
 
@@ -111,25 +107,32 @@ def path_object_to_module_name(self, txt):
         """
 
         txt = txt.replace('\\', '/')
-        name = txt.split('/')
-        mapfile_beginning = os.path.dirname(self.mapfile).split('/')
-        if name[0] == "." or name[0] == "":
-            name = name[1:]
-        for thing in mapfile_beginning:
-            if name[0] == thing:
-                name = name[1:]
-            elif name[0] in mapfile_beginning:
-                pass
+        rex_mbed_os_name = r'^.+mbed-os\/(.+)\/(.+\.o)$'
+        test_rex_mbed_os_name = re.match(rex_mbed_os_name, txt)
+
+        if test_rex_mbed_os_name:
+
+            object_name = test_rex_mbed_os_name.group(2)
+            data = test_rex_mbed_os_name.group(1).split('/')
+            ndata = len(data)
+
+            if ndata == 1:
+                module_name = data[0]
             else:
-                break
-        if name[0] == "mbed-os":
-            name = name[1:]
-        if name[0] == "features":
-            name = name[1:]
-        is_lib = RE_LIB_MATCH.match(txt)
-        if is_lib:
-            name = ["libraries", is_lib.group(1), is_lib.group(2)]
-        return "/".join(name), name[-1]
+                module_name = data[0] + '/' + data[1]
+
+            return [module_name, object_name]
+            
+        elif self.detailed_misc:           
+            rex_obj_name = r'^.+\/(.+\.o\)*)$'
+            test_rex_obj_name = re.match(rex_obj_name, txt)
+            if test_rex_obj_name:
+                object_name = test_rex_obj_name.group(1)
+                return ['Misc/' + object_name, ""]        
+                
+            return ['Misc', ""]
+        else: 
+            return ['Misc', ""]
 
     def parse_section_gcc(self, line):
         """ Parse data from a section of gcc map file
@@ -364,7 +367,15 @@ def search_objects(self, path):
 
         path = path.replace('\\', '/')
 
-        search_path = os.path.dirname(path)
+        # check location of map file
+        rex = r'^(.+)' + r'\/(.+\.map)$'
+        test_rex = re.match(rex, path)
+
+        if test_rex:
+            search_path = test_rex.group(1) + '/mbed-os/'
+        else:
+            print "Warning: this doesn't look like an mbed project"
+            return
 
         for root, _, obj_files in os.walk(search_path):
             for obj_file in obj_files:
@@ -479,19 +490,11 @@ def generate_table(self, file_desc):
         for i in list(self.print_sections):
             table.align[i] = 'r'
 
-        local_modules = {}
         for i in sorted(self.modules):
-            module_name = "/".join(i.split("/")[:self.depth])
-            local_modules.setdefault(module_name,
-                                     {k: 0 for k in self.print_sections})
-            for k in self.print_sections:
-                local_modules[module_name][k] += self.modules[i][k]
-
-        for i in sorted(local_modules.keys()):
             row = [i]
 
             for k in self.print_sections:
-                row.append(local_modules[i][k])
+                row.append(self.modules[i][k])
 
             table.add_row(row)
 
@@ -572,8 +575,6 @@ def parse(self, mapfile, toolchain):
         toolchain - the toolchain used to create the file
         """
 
-        self.mapfile = mapfile
-
         result = True
         try:
             with open(mapfile, 'r') as file_input:
@@ -588,8 +589,9 @@ def parse(self, mapfile, toolchain):
                     self.parse_map_file_iar(file_input)
                 else:
                     result = False
+            
             self.compute_report()
-
+        
         except IOError as error:
             print "I/O error({0}): {1}".format(error.errno, error.strerror)
             result = False
@@ -629,7 +631,6 @@ def main():
     
     parser.add_argument('-d', '--detailed', action='store_true', help='Displays the elements in "Misc" in a detailed fashion', required=False)
 
-    parser.add_argument('--max-depth', dest='max_depth', type=int, help='Displays the elements in "Misc" in a detailed fashion', required=False, default=None)
     # Parse/run command
     if len(sys.argv) <= 1:
         parser.print_help()
@@ -639,7 +640,7 @@ def main():
     args = parser.parse_args()
 
     # Create memap object
-    memap = MemapParser(depth=(args.max_depth or (MemapParser.MAXDEPTH if args.detailed else 2)))
+    memap = MemapParser(detailed_misc=args.detailed)
 
     # Parse and decode a map file
     if args.file and args.toolchain:

From eac9244eabe9a1cf92e7bd1aa6904173eaa2b3bf Mon Sep 17 00:00:00 2001
From: Mahadevan Mahesh <Mahesh.Mahadevan@nxp.com>
Date: Thu, 15 Sep 2016 15:58:12 -0500
Subject: [PATCH 67/89] Add support for KL82Z FRDM board

Signed-off-by: Mahadevan Mahesh <Mahesh.Mahadevan@nxp.com>
---
 .../TARGET_FRDM/PeripheralNames.h             |   102 +
 .../TARGET_KL82Z/TARGET_FRDM/PeripheralPins.c |   160 +
 .../TARGET_KL82Z/TARGET_FRDM/PinNames.h       |   171 +
 .../TARGET_KL82Z/TARGET_FRDM/device.h         |    39 +
 .../TARGET_FRDM/fsl_clock_config.c            |   178 +
 .../TARGET_FRDM/fsl_clock_config.h            |    56 +
 .../TARGET_KL82Z/TARGET_FRDM/mbed_overrides.c |    41 +
 .../TARGET_KL82Z/device/MKL82Z7.h             | 11451 ++++++++++++++++
 .../TARGET_KL82Z/device/MKL82Z7_features.h    |  2166 +++
 .../TOOLCHAIN_ARM_STD/MKL82Z128xxx7.sct       |   143 +
 .../TOOLCHAIN_ARM_STD/startup_MKL82Z7.s       |   616 +
 .../device/TOOLCHAIN_ARM_STD/sys.cpp          |    31 +
 .../device/TOOLCHAIN_GCC_ARM/MKL82Z128xxx7.ld |   287 +
 .../TOOLCHAIN_GCC_ARM/startup_MKL82Z7.S       |   545 +
 .../device/TOOLCHAIN_IAR/MKL82Z128xxx7.icf    |   139 +
 .../device/TOOLCHAIN_IAR/startup_MKL82Z7.s    |   479 +
 .../TARGET_KL82Z/device/cmsis.h               |    13 +
 .../TARGET_KL82Z/device/cmsis_nvic.c          |    42 +
 .../TARGET_KL82Z/device/cmsis_nvic.h          |    51 +
 .../device/fsl_device_registers.h             |    57 +
 .../TARGET_KL82Z/device/system_MKL82Z7.c      |   293 +
 .../TARGET_KL82Z/device/system_MKL82Z7.h      |   148 +
 .../TARGET_KL82Z/drivers/fsl_adc16.c          |   364 +
 .../TARGET_KL82Z/drivers/fsl_adc16.h          |   526 +
 .../TARGET_KL82Z/drivers/fsl_clock.c          |  1794 +++
 .../TARGET_KL82Z/drivers/fsl_clock.h          |  1505 ++
 .../TARGET_KL82Z/drivers/fsl_cmp.c            |   279 +
 .../TARGET_KL82Z/drivers/fsl_cmp.h            |   345 +
 .../TARGET_KL82Z/drivers/fsl_common.c         |   101 +
 .../TARGET_KL82Z/drivers/fsl_common.h         |   254 +
 .../TARGET_KL82Z/drivers/fsl_crc.c            |   280 +
 .../TARGET_KL82Z/drivers/fsl_crc.h            |   192 +
 .../TARGET_KL82Z/drivers/fsl_dac.c            |   214 +
 .../TARGET_KL82Z/drivers/fsl_dac.h            |   378 +
 .../TARGET_KL82Z/drivers/fsl_dmamux.c         |    87 +
 .../TARGET_KL82Z/drivers/fsl_dmamux.h         |   175 +
 .../TARGET_KL82Z/drivers/fsl_dspi.c           |  1661 +++
 .../TARGET_KL82Z/drivers/fsl_dspi.h           |  1181 ++
 .../TARGET_KL82Z/drivers/fsl_dspi_edma.c      |  1263 ++
 .../TARGET_KL82Z/drivers/fsl_dspi_edma.h      |   282 +
 .../TARGET_KL82Z/drivers/fsl_edma.c           |  1313 ++
 .../TARGET_KL82Z/drivers/fsl_edma.h           |   880 ++
 .../TARGET_KL82Z/drivers/fsl_ewm.c            |    92 +
 .../TARGET_KL82Z/drivers/fsl_ewm.h            |   241 +
 .../TARGET_KL82Z/drivers/fsl_flash.c          |  2630 ++++
 .../TARGET_KL82Z/drivers/fsl_flash.h          |  1209 ++
 .../TARGET_KL82Z/drivers/fsl_flexio.c         |   262 +
 .../TARGET_KL82Z/drivers/fsl_flexio.h         |   706 +
 .../TARGET_KL82Z/drivers/fsl_flexio_camera.c  |   157 +
 .../TARGET_KL82Z/drivers/fsl_flexio_camera.h  |   259 +
 .../drivers/fsl_flexio_camera_edma.c          |   218 +
 .../drivers/fsl_flexio_camera_edma.h          |   147 +
 .../drivers/fsl_flexio_i2c_master.c           |   763 +
 .../drivers/fsl_flexio_i2c_master.h           |   486 +
 .../TARGET_KL82Z/drivers/fsl_flexio_i2s.c     |   635 +
 .../TARGET_KL82Z/drivers/fsl_flexio_i2s.h     |   569 +
 .../drivers/fsl_flexio_i2s_edma.c             |   353 +
 .../drivers/fsl_flexio_i2s_edma.h             |   218 +
 .../TARGET_KL82Z/drivers/fsl_flexio_spi.c     |   935 ++
 .../TARGET_KL82Z/drivers/fsl_flexio_spi.h     |   707 +
 .../drivers/fsl_flexio_spi_edma.c             |   418 +
 .../drivers/fsl_flexio_spi_edma.h             |   222 +
 .../TARGET_KL82Z/drivers/fsl_flexio_uart.c    |   690 +
 .../TARGET_KL82Z/drivers/fsl_flexio_uart.h    |   585 +
 .../drivers/fsl_flexio_uart_edma.c            |   348 +
 .../drivers/fsl_flexio_uart_edma.h            |   190 +
 .../TARGET_KL82Z/drivers/fsl_gpio.c           |   179 +
 .../TARGET_KL82Z/drivers/fsl_gpio.h           |   389 +
 .../TARGET_KL82Z/drivers/fsl_i2c.c            |  1633 +++
 .../TARGET_KL82Z/drivers/fsl_i2c.h            |   788 ++
 .../TARGET_KL82Z/drivers/fsl_i2c_edma.c       |   526 +
 .../TARGET_KL82Z/drivers/fsl_i2c_edma.h       |   132 +
 .../TARGET_KL82Z/drivers/fsl_intmux.c         |   177 +
 .../TARGET_KL82Z/drivers/fsl_intmux.h         |   186 +
 .../TARGET_KL82Z/drivers/fsl_llwu.c           |   404 +
 .../TARGET_KL82Z/drivers/fsl_llwu.h           |   320 +
 .../TARGET_KL82Z/drivers/fsl_lptmr.c          |   117 +
 .../TARGET_KL82Z/drivers/fsl_lptmr.h          |   370 +
 .../TARGET_KL82Z/drivers/fsl_lpuart.c         |  1266 ++
 .../TARGET_KL82Z/drivers/fsl_lpuart.h         |   792 ++
 .../TARGET_KL82Z/drivers/fsl_lpuart_edma.c    |   331 +
 .../TARGET_KL82Z/drivers/fsl_lpuart_edma.h    |   189 +
 .../TARGET_KL82Z/drivers/fsl_ltc.c            |  4292 ++++++
 .../TARGET_KL82Z/drivers/fsl_ltc.h            |  1575 +++
 .../TARGET_KL82Z/drivers/fsl_ltc_edma.c       |  1247 ++
 .../TARGET_KL82Z/drivers/fsl_ltc_edma.h       |   850 ++
 .../TARGET_KL82Z/drivers/fsl_mpu.c            |   239 +
 .../TARGET_KL82Z/drivers/fsl_mpu.h            |   422 +
 .../TARGET_KL82Z/drivers/fsl_pit.c            |   119 +
 .../TARGET_KL82Z/drivers/fsl_pit.h            |   354 +
 .../TARGET_KL82Z/drivers/fsl_pmc.c            |    93 +
 .../TARGET_KL82Z/drivers/fsl_pmc.h            |   421 +
 .../TARGET_KL82Z/drivers/fsl_port.h           |   381 +
 .../TARGET_KL82Z/drivers/fsl_qspi.c           |   345 +
 .../TARGET_KL82Z/drivers/fsl_qspi.h           |   629 +
 .../TARGET_KL82Z/drivers/fsl_qspi_edma.c      |   321 +
 .../TARGET_KL82Z/drivers/fsl_qspi_edma.h      |   175 +
 .../TARGET_KL82Z/drivers/fsl_rcm.c            |    65 +
 .../TARGET_KL82Z/drivers/fsl_rcm.h            |   431 +
 .../TARGET_KL82Z/drivers/fsl_rtc.c            |   379 +
 .../TARGET_KL82Z/drivers/fsl_rtc.h            |   412 +
 .../TARGET_KL82Z/drivers/fsl_sim.c            |    53 +
 .../TARGET_KL82Z/drivers/fsl_sim.h            |   127 +
 .../TARGET_KL82Z/drivers/fsl_smartcard.h      |   296 +
 .../drivers/fsl_smartcard_emvsim.c            |   955 ++
 .../drivers/fsl_smartcard_emvsim.h            |   205 +
 .../drivers/fsl_smartcard_phy_emvsim.c        |   234 +
 .../drivers/fsl_smartcard_phy_emvsim.h        |   140 +
 .../drivers/fsl_smartcard_phy_tda8035.c       |   543 +
 .../drivers/fsl_smartcard_phy_tda8035.h       |   153 +
 .../TARGET_KL82Z/drivers/fsl_smc.c            |   366 +
 .../TARGET_KL82Z/drivers/fsl_smc.h            |   418 +
 .../TARGET_KL82Z/drivers/fsl_tpm.c            |   729 +
 .../TARGET_KL82Z/drivers/fsl_tpm.h            |   589 +
 .../TARGET_KL82Z/drivers/fsl_trng.c           |  1618 +++
 .../TARGET_KL82Z/drivers/fsl_trng.h           |   239 +
 .../TARGET_KL82Z/drivers/fsl_tsi_v4.c         |   190 +
 .../TARGET_KL82Z/drivers/fsl_tsi_v4.h         |   710 +
 .../TARGET_KL82Z/drivers/fsl_vref.c           |   224 +
 .../TARGET_KL82Z/drivers/fsl_vref.h           |   256 +
 .../TARGET_KL82Z/drivers/fsl_wdog.c           |   153 +
 .../TARGET_KL82Z/drivers/fsl_wdog.h           |   433 +
 .../TARGET_KL82Z/peripheral_clock_defines.h   |    54 +
 .../TARGET_KL82Z/pwmout_api.c                 |   139 +
 .../TARGET_KL82Z/serial_api.c                 |   262 +
 .../TARGET_KSDK2_MCUS/TARGET_KL82Z/spi_api.c  |   132 +
 .../TARGET_KL82Z/us_ticker.c                  |    90 +
 targets/TARGET_Freescale/mbed_rtx.h           |    15 +
 targets/targets.json                          |    13 +
 129 files changed, 73207 insertions(+)
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/PeripheralNames.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/PeripheralPins.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/PinNames.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/device.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/fsl_clock_config.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/fsl_clock_config.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/mbed_overrides.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/MKL82Z7.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/MKL82Z7_features.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/MKL82Z128xxx7.sct
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/startup_MKL82Z7.s
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/sys.cpp
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_GCC_ARM/MKL82Z128xxx7.ld
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_GCC_ARM/startup_MKL82Z7.S
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/MKL82Z128xxx7.icf
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/startup_MKL82Z7.s
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis_nvic.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis_nvic.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/fsl_device_registers.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/system_MKL82Z7.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/system_MKL82Z7.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_adc16.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_adc16.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_clock.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_clock.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_cmp.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_cmp.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_common.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_common.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_crc.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_crc.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dac.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dac.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dmamux.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dmamux.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi_edma.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi_edma.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_edma.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_edma.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ewm.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ewm.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flash.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flash.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera_edma.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera_edma.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2c_master.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2c_master.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s_edma.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s_edma.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi_edma.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi_edma.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart_edma.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart_edma.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_gpio.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_gpio.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c_edma.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c_edma.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_intmux.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_intmux.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_llwu.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_llwu.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lptmr.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lptmr.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart_edma.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart_edma.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc_edma.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc_edma.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_mpu.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_mpu.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pit.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pit.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pmc.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pmc.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_port.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi_edma.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi_edma.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rcm.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rcm.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rtc.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rtc.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_sim.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_sim.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_emvsim.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_emvsim.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_emvsim.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_emvsim.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_tda8035.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_tda8035.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smc.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smc.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tpm.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tpm.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_trng.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_trng.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tsi_v4.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tsi_v4.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_vref.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_vref.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_wdog.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_wdog.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/peripheral_clock_defines.h
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/pwmout_api.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/serial_api.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/spi_api.c
 create mode 100644 targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/us_ticker.c

diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/PeripheralNames.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/PeripheralNames.h
new file mode 100644
index 00000000000..ac0c713d853
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/PeripheralNames.h
@@ -0,0 +1,102 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    OSC32KCLK = 0,
+} RTCName;
+
+/* LPUART */
+typedef enum {
+    LPUART_0 = 0,
+    LPUART_1 = 1,
+    LPUART_2 = 2,
+} UARTName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        LPUART_0
+
+typedef enum {
+    I2C_0 = 0,
+    I2C_1 = 1,
+} I2CName;
+
+#define TPM_SHIFT   8
+typedef enum {
+    PWM_1  = (0 << TPM_SHIFT) | (0),  // TPM0 CH0
+    PWM_2  = (0 << TPM_SHIFT) | (1),  // TPM0 CH1
+    PWM_3  = (0 << TPM_SHIFT) | (2),  // TPM0 CH2
+    PWM_4  = (0 << TPM_SHIFT) | (3),  // TPM0 CH3
+    PWM_5  = (0 << TPM_SHIFT) | (4),  // TPM0 CH4
+    PWM_6  = (0 << TPM_SHIFT) | (5),  // TPM0 CH5
+    PWM_7  = (1 << TPM_SHIFT) | (0),  // TPM1 CH0
+    PWM_8  = (1 << TPM_SHIFT) | (1),  // TPM1 CH1
+    PWM_9  = (2 << TPM_SHIFT) | (0),  // TPM2 CH0
+    PWM_10 = (2 << TPM_SHIFT) | (1),  // TPM2 CH1
+} PWMName;
+
+#define ADC_INSTANCE_SHIFT           8
+#define ADC_B_CHANNEL_SHIFT          5
+typedef enum {
+    ADC0_SE0  = (0 << ADC_INSTANCE_SHIFT) | 0,
+    ADC0_SE1  = (0 << ADC_INSTANCE_SHIFT) | 1,
+    ADC0_SE2  = (0 << ADC_INSTANCE_SHIFT) | 2,
+    ADC0_SE3  = (0 << ADC_INSTANCE_SHIFT) | 3,
+    ADC0_SE4a = (0 << ADC_INSTANCE_SHIFT) | 4,
+    ADC0_SE5a = (0 << ADC_INSTANCE_SHIFT) | 5,
+    ADC0_SE6a = (0 << ADC_INSTANCE_SHIFT) | 6,
+    ADC0_SE7a = (0 << ADC_INSTANCE_SHIFT) | 7,
+    ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
+    ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
+    ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
+    ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
+    ADC0_SE8  = (0 << ADC_INSTANCE_SHIFT) | 8,
+    ADC0_SE9  = (0 << ADC_INSTANCE_SHIFT) | 9,
+    ADC0_SE11  = (0 << ADC_INSTANCE_SHIFT) | 11,
+    ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
+    ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
+    ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
+    ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
+    ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16,
+    ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17,
+    ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18,
+    ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21,
+    ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22,
+    ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23,
+} ADCName;
+
+typedef enum {
+    SPI_0 = 0,
+    SPI_1 = 1,
+} SPIName;
+
+typedef enum {
+    DAC_0 = 0
+} DACName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/PeripheralPins.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/PeripheralPins.c
new file mode 100644
index 00000000000..1f3749556cd
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/PeripheralPins.c
@@ -0,0 +1,160 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+/************RTC***************/
+const PinMap PinMap_RTC[] = {
+    {NC, OSC32KCLK, 0},
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+    {PTB0, ADC0_SE8, 0},
+    {PTB1, ADC0_SE9, 0},
+    {PTB2, ADC0_SE12, 0},
+    {PTB3, ADC0_SE13, 0},
+    {PTC0, ADC0_SE14, 0},
+    {PTC1, ADC0_SE15, 0},
+    {PTC2, ADC0_SE4b, 0},
+    {PTD1, ADC0_SE5b, 0},
+    {PTD5, ADC0_SE6b, 0},
+    {PTD6, ADC0_SE7b, 0},
+    {NC,   NC,        0}
+};
+
+/************DAC***************/
+const PinMap PinMap_DAC[] = {
+    {DAC0_OUT, DAC_0, 0},
+    {NC,       NC,    0}
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+    {PTB1,  I2C_0, 2},
+    {PTB3,  I2C_0, 2},
+    {PTC11, I2C_1, 2},
+    {PTD3,  I2C_0, 7},
+    {PTD9,  I2C_0, 2},
+    {PTE0,  I2C_1, 6},
+    {NC,    NC   , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PTB0,  I2C_0, 2},
+    {PTB2,  I2C_0, 2},
+    {PTC10, I2C_1, 2},
+    {PTD2,  I2C_0, 7},
+    {PTD8,  I2C_0, 2},
+    {PTE1,  I2C_1, 6},
+    {NC,    NC,    0}
+};
+
+/************LPUART***************/
+const PinMap PinMap_UART_TX[] = {
+    {PTA2,  LPUART_0, 2},
+    {PTA14, LPUART_0, 3},
+    {PTB17, LPUART_0, 3},
+    {PTC4,  LPUART_1, 3},
+    {PTD3,  LPUART_2, 3},
+    {PTD7,  LPUART_0, 3},
+    {PTE0,  LPUART_1, 3},
+    {NC,    NC,       0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PTA1,  LPUART_0, 2},
+    {PTA15, LPUART_0, 3},
+    {PTB16, LPUART_0, 3},
+    {PTC3,  LPUART_1, 3},
+    {PTD2,  LPUART_2, 3},
+    {PTD6,  LPUART_0, 3},
+    {PTE1,  LPUART_1, 3},
+    {NC,    NC,       0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+    {PTE1,  SPI_1, 2},
+    {PTE2,  SPI_1, 7},
+    {PTA15, SPI_1, 2},
+    {PTB11, SPI_1, 2},
+    {PTC5,  SPI_0, 2},
+    {PTD1,  SPI_0, 2},
+    {PTD5,  SPI_1, 7},
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PTE2,  SPI_1, 2},
+    {PTE3,  SPI_1, 7},
+    {PTA16, SPI_1, 2},
+    {PTB16, SPI_1, 2},
+    {PTC6,  SPI_0, 2},
+    {PTD2,  SPI_0, 2},
+    {PTD6,  SPI_1, 7},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PTE1,  SPI_1, 7},
+    {PTE4,  SPI_1, 2},
+    {PTA17, SPI_1, 2},
+    {PTB17, SPI_1, 2},
+    {PTC7,  SPI_0, 2},
+    {PTD3,  SPI_0, 2},
+    {PTD7,  SPI_1, 7},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PTE5,  SPI_1, 2},
+    {PTA14, SPI_1, 2},
+    {PTB10, SPI_1, 2},
+    {PTC4, SPI_0, 2},
+    {PTD0, SPI_0, 2},
+    {PTD4, SPI_1, 7},
+    {NC,   NC,    0}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+    {PTA0,  PWM_6,  3}, // PTA0 , TPM0 CH5
+    {PTA3,  PWM_1,  3}, // PTA3 , TPM0 CH0
+    {PTA4,  PWM_2 , 3}, // PTA4 , TPM0 CH1
+    {PTA5,  PWM_3 , 3}, // PTA5 , TPM0 CH2
+    {PTA10, PWM_9,  3}, // PTA10, TPM2 CH0
+    {PTA11, PWM_10, 3}, // PTA11, TPM2 CH1
+    {PTA12, PWM_7 , 3}, // PTA12, TPM1 CH0
+    {PTA13, PWM_8 , 3}, // PTA13, TPM1 CH1
+
+    {PTB0,  PWM_7,  3}, // PTB0 , TPM1 CH0
+    {PTB1,  PWM_8,  3}, // PTB1 , TPM1 CH1
+    {PTB18, PWM_9,  3}, // PTB18, TPM2 CH0
+    {PTB19, PWM_10, 3}, // PTB18, TPM2 CH1
+
+    {PTC1,  PWM_1,  4}, // PTC1 , TPM0 CH0
+    {PTC2,  PWM_2,  4}, // PTC2 , TPM0 CH1
+    {PTC3,  PWM_3,  4}, // PTC3 , TPM0 CH2
+    {PTC4,  PWM_4,  4}, // PTC4 , TPM0 CH3
+    {PTC5,  PWM_3,  7}, // PTC4 , TPM0 CH2
+
+    {PTD4,  PWM_5 , 4}, // PTD4 , TPM0 CH4
+    {PTD5,  PWM_6 , 4}, // PTD5 , TPM0 CH5
+
+    {NC   , NC    , 0}
+};
+
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/PinNames.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/PinNames.h
new file mode 100644
index 00000000000..55ad0cf4f5a
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/PinNames.h
@@ -0,0 +1,171 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define GPIO_PORT_SHIFT 12
+
+typedef enum {
+    PTA0  = (0 << GPIO_PORT_SHIFT | 0),
+    PTA1  = (0 << GPIO_PORT_SHIFT | 1),
+    PTA2  = (0 << GPIO_PORT_SHIFT | 2),
+    PTA3  = (0 << GPIO_PORT_SHIFT | 3),
+    PTA4  = (0 << GPIO_PORT_SHIFT | 4),
+    PTA5  = (0 << GPIO_PORT_SHIFT | 5),
+    PTA10 = (0 << GPIO_PORT_SHIFT | 10),
+    PTA11 = (0 << GPIO_PORT_SHIFT | 11),
+    PTA12 = (0 << GPIO_PORT_SHIFT | 12),
+    PTA13 = (0 << GPIO_PORT_SHIFT | 13),
+    PTA14 = (0 << GPIO_PORT_SHIFT | 14),
+    PTA15 = (0 << GPIO_PORT_SHIFT | 15),
+    PTA16 = (0 << GPIO_PORT_SHIFT | 16),
+    PTA17 = (0 << GPIO_PORT_SHIFT | 17),
+    PTA18 = (0 << GPIO_PORT_SHIFT | 18),
+    PTA19 = (0 << GPIO_PORT_SHIFT | 19),
+
+    PTB0  = (1 << GPIO_PORT_SHIFT | 0),
+    PTB1  = (1 << GPIO_PORT_SHIFT | 1),
+    PTB2  = (1 << GPIO_PORT_SHIFT | 2),
+    PTB3  = (1 << GPIO_PORT_SHIFT | 3),
+    PTB9  = (1 << GPIO_PORT_SHIFT | 9),
+    PTB10 = (1 << GPIO_PORT_SHIFT | 10),
+    PTB11 = (1 << GPIO_PORT_SHIFT | 11),
+    PTB16 = (1 << GPIO_PORT_SHIFT | 16),
+    PTB17 = (1 << GPIO_PORT_SHIFT | 17),
+    PTB18 = (1 << GPIO_PORT_SHIFT | 18),
+    PTB19 = (1 << GPIO_PORT_SHIFT | 19),
+    PTB20 = (1 << GPIO_PORT_SHIFT | 20),
+    PTB21 = (1 << GPIO_PORT_SHIFT | 21),
+    PTB22 = (1 << GPIO_PORT_SHIFT | 22),
+    PTB23 = (1 << GPIO_PORT_SHIFT | 23),
+
+    PTC0  = (2 << GPIO_PORT_SHIFT | 0 ),
+    PTC1  = (2 << GPIO_PORT_SHIFT | 1 ),
+    PTC2  = (2 << GPIO_PORT_SHIFT | 2 ),
+    PTC3  = (2 << GPIO_PORT_SHIFT | 3 ),
+    PTC4  = (2 << GPIO_PORT_SHIFT | 4 ),
+    PTC5  = (2 << GPIO_PORT_SHIFT | 5 ),
+    PTC6  = (2 << GPIO_PORT_SHIFT | 6 ),
+    PTC7  = (2 << GPIO_PORT_SHIFT | 7 ),
+    PTC8  = (2 << GPIO_PORT_SHIFT | 8 ),
+    PTC9  = (2 << GPIO_PORT_SHIFT | 9 ),
+    PTC10 = (2 << GPIO_PORT_SHIFT | 10),
+    PTC11 = (2 << GPIO_PORT_SHIFT | 11),
+    PTC12 = (2 << GPIO_PORT_SHIFT | 12),
+    PTC13 = (2 << GPIO_PORT_SHIFT | 13),
+    PTC14 = (2 << GPIO_PORT_SHIFT | 14),
+    PTC15 = (2 << GPIO_PORT_SHIFT | 15),
+    PTC17 = (2 << GPIO_PORT_SHIFT | 17),
+
+    PTD0  = (3 << GPIO_PORT_SHIFT | 0),
+    PTD1  = (3 << GPIO_PORT_SHIFT | 1),
+    PTD2  = (3 << GPIO_PORT_SHIFT | 2),
+    PTD3  = (3 << GPIO_PORT_SHIFT | 3),
+    PTD4  = (3 << GPIO_PORT_SHIFT | 4),
+    PTD5  = (3 << GPIO_PORT_SHIFT | 5),
+    PTD6  = (3 << GPIO_PORT_SHIFT | 6),
+    PTD7  = (3 << GPIO_PORT_SHIFT | 7),
+    PTD8  = (3 << GPIO_PORT_SHIFT | 8),
+    PTD9  = (3 << GPIO_PORT_SHIFT | 9),
+
+    PTE0  = (4 << GPIO_PORT_SHIFT | 0),
+    PTE1  = (4 << GPIO_PORT_SHIFT | 1),
+    PTE2  = (4 << GPIO_PORT_SHIFT | 2),
+    PTE3  = (4 << GPIO_PORT_SHIFT | 3),
+    PTE4  = (4 << GPIO_PORT_SHIFT | 4),
+    PTE5  = (4 << GPIO_PORT_SHIFT | 5),
+    PTE6  = (4 << GPIO_PORT_SHIFT | 6),
+    PTE7  = (4 << GPIO_PORT_SHIFT | 7),
+    PTE8  = (4 << GPIO_PORT_SHIFT | 9),
+    PTE9  = (4 << GPIO_PORT_SHIFT | 9),
+    PTE10 = (4 << GPIO_PORT_SHIFT | 10),
+    PTE11 = (4 << GPIO_PORT_SHIFT | 11),
+
+    LED_RED   = PTC1,
+    LED_GREEN = PTC2,
+    LED_BLUE  = PTC0,
+
+    // mbed original LED naming
+    LED1 = LED_RED,
+    LED2 = LED_GREEN,
+    LED3 = LED_BLUE,
+    LED4 = LED_RED,
+
+    //Push buttons
+    SW2 = PTA4,
+    SW3 = PTD0,
+
+    // USB Pins
+    USBTX = PTB17,
+    USBRX = PTB16,
+
+    DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
+
+    // Arduino Headers
+    D0 = PTB16,
+    D1 = PTB17,
+    D2 = PTD7,
+    D3 = PTC1,
+    D4 = PTC12,
+    D5 = PTC2,
+    D6 = PTC3,
+    D7 = PTC9,
+    D8 = PTD4,
+    D9 = PTD5,
+    D10 = PTC4,
+    D11 = PTC6,
+    D12 = PTC7,
+    D13 = PTC5,
+    D14 = PTC11,
+    D15 = PTC10,
+
+    I2C_SCL = D15,
+    I2C_SDA = D14,
+
+    A0 = DAC0_OUT,
+    A1 = PTD1,
+    A2 = PTC0,
+    A3 = PTD6,
+    A4 = PTB1,
+    A5 = PTB0,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp   = 2,
+    PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/device.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/device.h
new file mode 100644
index 00000000000..29a4e7a0b18
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/device.h
@@ -0,0 +1,39 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+
+
+
+
+
+
+
+
+
+
+#define DEVICE_ID_LENGTH       24
+
+
+
+
+
+#include "objects.h"
+
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/fsl_clock_config.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/fsl_clock_config.c
new file mode 100644
index 00000000000..1ad6e17866d
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/fsl_clock_config.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_smc.h"
+#include "fsl_clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ *    internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ *        explicitly to setup MCGIRCLK.
+ *
+ *    3). Don't need to configure FLL explicitly, because if target mode is FLL
+ *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ *        if the target mode is not FLL mode, the FLL is disabled.
+ *
+ *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+
+void BOARD_BootClockVLPR(void)
+{
+    /*
+    * Core clock: 4MHz
+    */
+    const sim_clock_config_t simConfig = {
+        .pllFllSel = 3U,        /* PLLFLLSEL select IRC48MCLK. */
+        .pllFllDiv = 0U,        /* PLLFLLSEL clock divider divisor. */
+        .pllFllFrac = 0U,       /* PLLFLLSEL clock divider fraction. */
+        .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
+        .clkdiv1 = 0x03040000U, /* SIM_CLKDIV1. */
+    };
+
+    CLOCK_SetSimSafeDivs();
+
+    CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable);
+
+    CLOCK_SetSimConfig(&simConfig);
+
+    SystemCoreClock = 4000000U;
+
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeVlpr(SMC);
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+}
+
+void BOARD_BootClockRUN(void)
+{
+    /*
+    * Core clock: 72MHz
+    */
+    const mcg_pll_config_t pll0Config = {
+        .enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x08U,
+    };
+    const sim_clock_config_t simConfig = {
+        .pllFllSel = 1U,        /* PLLFLLSEL select PLL. */
+        .pllFllDiv = 0U,        /* PLLFLLSEL clock divider divisor. */
+        .pllFllFrac = 0U,       /* PLLFLLSEL clock divider fraction. */
+        .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
+        .clkdiv1 = 0x15051000U, /* SIM_CLKDIV1. */
+    };
+
+    CLOCK_SetSimSafeDivs();
+    BOARD_InitOsc0();
+
+    CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
+
+    CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
+    CLOCK_SetSimConfig(&simConfig);
+
+    SystemCoreClock = 72000000U;
+}
+
+void BOARD_BootClockHSRUN(void)
+{
+    /*
+    * Core clock: 96MHz
+    */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeHsrun(SMC);
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
+    {
+    }
+    CLOCK_SetSimSafeDivs();
+    BOARD_InitOsc0();
+    const sim_clock_config_t simConfig = {
+        .pllFllSel = 1U,        /* PLLFLLSEL select PLL. */
+        .pllFllDiv = 0U,        /* PLLFLLSEL clock divider divisor. */
+        .pllFllFrac = 0U,       /* PLLFLLSEL clock divider fraction. */
+        .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
+        .clkdiv1 = 0x03030000U, /* SIM_CLKDIV1. */
+    };
+
+    const mcg_pll_config_t pll0Config = {
+        .enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x00U,
+    };
+    CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
+
+    CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
+    CLOCK_SetSimConfig(&simConfig);
+    SystemCoreClock = 96000000U;
+}
+
+void BOARD_InitOsc0(void)
+{
+    const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
+                                    .capLoad = 0,
+                                    .workMode = kOSC_ModeOscLowPower,
+                                    .oscerConfig = {
+                                        .enableMode = kOSC_ErClkEnable,
+#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
+                                        .erclkDiv = 0U,
+#endif
+                                    }};
+
+    CLOCK_InitOsc0(&oscConfig);
+
+    /* Passing the XTAL0 frequency to clock driver. */
+    CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
+    CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ);
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/fsl_clock_config.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/fsl_clock_config.h
new file mode 100644
index 00000000000..e41723ab2aa
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/fsl_clock_config.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+/*******************************************************************************
+ * DEFINITION
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 12000000U
+#define BOARD_XTAL32K_CLK_HZ 32768U
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void BOARD_BootClockVLPR(void);
+void BOARD_BootClockRUN(void);
+void BOARD_BootClockHSRUN(void);
+void BOARD_InitOsc0(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/mbed_overrides.c
new file mode 100644
index 00000000000..d4577de95fd
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/TARGET_FRDM/mbed_overrides.c
@@ -0,0 +1,41 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "fsl_clock_config.h"
+
+// called before main - implement here if board needs it otherwise, let
+//  the application override this if necessary
+void mbed_sdk_init()
+{
+    BOARD_BootClockRUN();
+}
+
+// Enable the RTC oscillator if available on the board
+void rtc_setup_oscillator(RTC_Type *base)
+{
+    /* Enable the RTC oscillator */
+    RTC->CR |= RTC_CR_OSCE_MASK;
+}
+
+// Change the NMI pin to an input. This allows NMI pin to
+//  be used as a low power mode wakeup.  The application will
+//  need to change the pin back to NMI_b or wakeup only occurs once!
+void NMI_Handler(void)
+{
+    gpio_t gpio;
+    gpio_init_in(&gpio, PTA4);
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/MKL82Z7.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/MKL82Z7.h
new file mode 100644
index 00000000000..e790851f6dc
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/MKL82Z7.h
@@ -0,0 +1,11451 @@
+/*
+** ###################################################################
+**     Processors:          MKL82Z128VLH7
+**                          MKL82Z128VLK7
+**                          MKL82Z128VLL7
+**                          MKL82Z128VMC7
+**                          MKL82Z128VMP7
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL82P121M72SF0RM, Rev.2 November 2015
+**     Version:             rev. 1.5, 2015-09-24
+**     Build:               b160201
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MKL82Z7
+**
+**     Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-18)
+**         Initial version.
+**     - rev. 1.1 (2015-05-04)
+**         Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
+**     - rev. 1.2 (2015-08-11)
+**         Correct clock configuration.
+**     - rev. 1.3 (2015-08-20)
+**         Align with RM Rev.1.
+**     - rev. 1.4 (2015-08-28)
+**         Update LPUART to add FIFO.
+**     - rev. 1.5 (2015-09-24)
+**         Update to align with RM Rev.1.2.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL82Z7.h
+ * @version 1.5
+ * @date 2015-09-24
+ * @brief CMSIS Peripheral Access Layer for MKL82Z7
+ *
+ * CMSIS Peripheral Access Layer for MKL82Z7
+ */
+
+#ifndef _MKL82Z7_H_
+#define _MKL82Z7_H_                              /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0005U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 80                 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M0 SV Hard Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M0 SV Call Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M0 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M0 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_DMA4_IRQn               = 0,                /**< DMA channel 0, 4 transfer complete */
+  DMA1_DMA5_IRQn               = 1,                /**< DMA channel 1, 5 transfer complete */
+  DMA2_DMA6_IRQn               = 2,                /**< DMA channel 2, 6 transfer complete */
+  DMA3_DMA7_IRQn               = 3,                /**< DMA channel 3, 7 transfer complete */
+  DMA_Error_IRQn               = 4,                /**< DMA channel 0 - 7 error */
+  FLEXIO0_IRQn                 = 5,                /**< Flexible IO */
+  TPM0_IRQn                    = 6,                /**< Timer/PWM module 0 */
+  TPM1_IRQn                    = 7,                /**< Timer/PWM module 1 */
+  TPM2_IRQn                    = 8,                /**< Timer/PWM module 2 */
+  PIT0_IRQn                    = 9,                /**< Periodic Interrupt Timer 0 */
+  SPI0_IRQn                    = 10,               /**< Serial Peripheral Interface 0 */
+  EMVSIM0_IRQn                 = 11,               /**< EMVSIM0 common interrupt */
+  LPUART0_IRQn                 = 12,               /**< LPUART0 status and error */
+  LPUART1_IRQn                 = 13,               /**< LPUART1 status and error */
+  I2C0_IRQn                    = 14,               /**< Inter-Integrated Circuit 0 */
+  QSPI0_IRQn                   = 15,               /**< QuadSPI0 interrupt */
+  Reserved32_IRQn              = 16,               /**< DryIce tamper detect */
+  PORTA_IRQn                   = 17,               /**< Pin detect Port A */
+  PORTB_IRQn                   = 18,               /**< Pin detect Port B */
+  PORTC_IRQn                   = 19,               /**< Pin detect Port C */
+  PORTD_IRQn                   = 20,               /**< Pin detect Port D */
+  PORTE_IRQn                   = 21,               /**< Pin detect Port E */
+  LLWU_IRQn                    = 22,               /**< Low Leakage Wakeup */
+  LTC0_IRQn                    = 23,               /**< Low power trusted cryptographic */
+  USB0_IRQn                    = 24,               /**< USB OTG interrupt */
+  ADC0_IRQn                    = 25,               /**< Analog-to-Digital Converter 0 */
+  LPTMR0_IRQn                  = 26,               /**< Low-Power Timer 0 */
+  RTC_Seconds_IRQn             = 27,               /**< RTC seconds */
+  INTMUX0_0_IRQn               = 28,               /**< Selectable peripheral interrupt INTMUX0-0 */
+  INTMUX0_1_IRQn               = 29,               /**< Selectable peripheral interrupt INTMUX0-1 */
+  INTMUX0_2_IRQn               = 30,               /**< Selectable peripheral interrupt INTMUX0-2 */
+  INTMUX0_3_IRQn               = 31,               /**< Selectable peripheral interrupt INTMUX0-3 */
+  LPTMR1_IRQn                  = 32,               /**< Low-Power Timer 1 (INTMUX source IRQ0) */
+  Reserved49_IRQn              = 33,               /**< Reserved interrupt (INTMUX source IRQ1) */
+  Reserved50_IRQn              = 34,               /**< Reserved interrupt (INTMUX source IRQ2) */
+  Reserved51_IRQn              = 35,               /**< Reserved interrupt (INTMUX source IRQ3) */
+  SPI1_IRQn                    = 36,               /**< Serial Peripheral Interface 1 (INTMUX source IRQ4) */
+  LPUART2_IRQn                 = 37,               /**< LPUART2 status and error (INTMUX source IRQ5) */
+  EMVSIM1_IRQn                 = 38,               /**< EMVSIM1 common interrupt (INTMUX source IRQ6) */
+  I2C1_IRQn                    = 39,               /**< Inter-Integrated Circuit 1 (INTMUX source IRQ7) */
+  TSI0_IRQn                    = 40,               /**< Touch Sensing Input 0 (INTMUX source IRQ8) */
+  PMC_IRQn                     = 41,               /**< PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9) */
+  FTFA_IRQn                    = 42,               /**< FTFA command complete/read collision (INTMUX source IRQ10) */
+  MCG_IRQn                     = 43,               /**< Multipurpose clock generator (INTMUX source IRQ11) */
+  WDOG_EWM_IRQn                = 44,               /**< Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12) */
+  DAC0_IRQn                    = 45,               /**< Digital-to-analog converter 0 (INTMUX source IRQ13) */
+  TRNG0_IRQn                   = 46,               /**< True randon number generator (INTMUX source IRQ14) */
+  Reserved63_IRQn              = 47,               /**< Reserved interrupt (INTMUX source IRQ15) */
+  CMP0_IRQn                    = 48,               /**< Comparator 0 (INTMUX source IRQ16) */
+  Reserved65_IRQn              = 49,               /**< Reserved interrupt (INTMUX source IRQ17) */
+  RTC_Alarm_IRQn               = 50,               /**< Real time clock (INTMUX source IRQ18) */
+  Reserved67_IRQn              = 51,               /**< Reserved interrupt (INTMUX source IRQ19) */
+  Reserved68_IRQn              = 52,               /**< Reserved interrupt (INTMUX source IRQ20) */
+  Reserved69_IRQn              = 53,               /**< Reserved interrupt (INTMUX source IRQ21) */
+  Reserved70_IRQn              = 54,               /**< Reserved interrupt (INTMUX source IRQ22) */
+  Reserved71_IRQn              = 55,               /**< Reserved interrupt (INTMUX source IRQ23) */
+  DMA4_IRQn                    = 56,               /**< DMA channel 4 transfer complete (INTMUX source IRQ24) */
+  DMA5_IRQn                    = 57,               /**< DMA channel 5 transfer complete (INTMUX source IRQ25) */
+  DMA6_IRQn                    = 58,               /**< DMA channel 6 transfer complete (INTMUX source IRQ26) */
+  DMA7_IRQn                    = 59,               /**< DMA channel 7 transfer complete (INTMUX source IRQ27) */
+  Reserved76_IRQn              = 60,               /**< Reserved interrupt (INTMUX source IRQ28) */
+  Reserved77_IRQn              = 61,               /**< Reserved interrupt (INTMUX source IRQ29) */
+  Reserved78_IRQn              = 62,               /**< Reserved interrupt (INTMUX source IRQ30) */
+  Reserved79_IRQn              = 63                /**< Reserved interrupt (INTMUX source IRQ31) */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M0 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV                  0x0000    /**< Core revision r0p0 */
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT                 1         /**< Defines if VTOR is present or not */
+#define __NVIC_PRIO_BITS               2         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h"              /* Core Peripheral Access Layer */
+#include "system_MKL82Z7.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestMux0Disable          = 0|0x100U,    /**< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0FlexIO0Channel0  = 1|0x100U,    /**< FLEXIO0. */
+    kDmaRequestMux0FlexIO0Channel1  = 2|0x100U,    /**< FLEXIO0. */
+    kDmaRequestMux0FlexIO0Channel2  = 3|0x100U,    /**< FLEXIO0. */
+    kDmaRequestMux0FlexIO0Channel3  = 4|0x100U,    /**< FLEXIO0. */
+    kDmaRequestMux0FlexIO0Channel4  = 5|0x100U,    /**< FLEXIO0. */
+    kDmaRequestMux0FlexIO0Channel5  = 6|0x100U,    /**< FLEXIO0. */
+    kDmaRequestMux0FlexIO0Channel6  = 7|0x100U,    /**< FLEXIO0. */
+    kDmaRequestMux0FlexIO0Channel7  = 8|0x100U,    /**< FLEXIO0. */
+    kDmaRequestMux0I2C0             = 9|0x100U,    /**< I2C0 Transmit or Receive. */
+    kDmaRequestMux0I2C1             = 10|0x100U,   /**< I2C1 Transmit or Receive. */
+    kDmaRequestMux0Reserved11       = 11|0x100U,   /**< Reserved11 */
+    kDmaRequestMux0Reserved12       = 12|0x100U,   /**< Reserved12 */
+    kDmaRequestMux0Reserved13       = 13|0x100U,   /**< Reserved13 */
+    kDmaRequestMux0Reserved14       = 14|0x100U,   /**< Reserved14 */
+    kDmaRequestMux0LPUART0Rx        = 15|0x100U,   /**< LPUART0 Receive. */
+    kDmaRequestMux0LPUART0Tx        = 16|0x100U,   /**< LPUART0 Transmit. */
+    kDmaRequestMux0LPUART1Rx        = 17|0x100U,   /**< LPUART1 Receive. */
+    kDmaRequestMux0LPUART1Tx        = 18|0x100U,   /**< LPUART1 Transmit. */
+    kDmaRequestMux0LPUART2Rx        = 19|0x100U,   /**< LPUART2 Receive. */
+    kDmaRequestMux0LPUART2Tx        = 20|0x100U,   /**< LPUART2 Transmit. */
+    kDmaRequestMux0SPI0Rx           = 21|0x100U,   /**< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx           = 22|0x100U,   /**< SPI0 Transmit. */
+    kDmaRequestMux0SPI1Rx           = 23|0x100U,   /**< SPI1 Receive. */
+    kDmaRequestMux0SPI1Tx           = 24|0x100U,   /**< SPI1 Transmit. */
+    kDmaRequestMux0QSPI0Rx          = 25|0x100U,   /**< QuadSPI0 Receive. */
+    kDmaRequestMux0QSPI0Tx          = 26|0x100U,   /**< QuadSPI0 Transmit. */
+    kDmaRequestMux0TPM0Channel0     = 27|0x100U,   /**< TPM0 C0V. */
+    kDmaRequestMux0TPM0Channel1     = 28|0x100U,   /**< TPM0 C1V. */
+    kDmaRequestMux0TPM0Channel2     = 29|0x100U,   /**< TPM0 C2V. */
+    kDmaRequestMux0TPM0Channel3     = 30|0x100U,   /**< TPM0 C3V. */
+    kDmaRequestMux0TPM0Channel4     = 31|0x100U,   /**< TPM0 C4V. */
+    kDmaRequestMux0TPM0Channel5     = 32|0x100U,   /**< TPM0 C5V. */
+    kDmaRequestMux0Reserved33       = 33|0x100U,   /**< Reserved33 */
+    kDmaRequestMux0Reserved34       = 34|0x100U,   /**< Reserved34 */
+    kDmaRequestMux0TPM0Overflow     = 35|0x100U,   /**< TPM0. */
+    kDmaRequestMux0TPM1Channel0     = 36|0x100U,   /**< TPM1 C0V. */
+    kDmaRequestMux0TPM1Channel1     = 37|0x100U,   /**< TPM1 C1V. */
+    kDmaRequestMux0TPM1Overflow     = 38|0x100U,   /**< TPM1. */
+    kDmaRequestMux0TPM2Channel0     = 39|0x100U,   /**< TPM2 C0V. */
+    kDmaRequestMux0TPM2Channel1     = 40|0x100U,   /**< TPM2 C1V. */
+    kDmaRequestMux0TPM2Overflow     = 41|0x100U,   /**< TPM2. */
+    kDmaRequestMux0TSI0             = 42|0x100U,   /**< TSI0. */
+    kDmaRequestMux0EMVSIM0Rx        = 43|0x100U,   /**< EMVSIM0 Receive. */
+    kDmaRequestMux0EMVSIM0Tx        = 44|0x100U,   /**< EMVSIM0 Transmit. */
+    kDmaRequestMux0EMVSIM1Rx        = 45|0x100U,   /**< EMVSIM1 Receive. */
+    kDmaRequestMux0EMVSIM1Tx        = 46|0x100U,   /**< EMVSIM1 Transmit. */
+    kDmaRequestMux0PortA            = 47|0x100U,   /**< PTA. */
+    kDmaRequestMux0PortB            = 48|0x100U,   /**< PTB. */
+    kDmaRequestMux0PortC            = 49|0x100U,   /**< PTC. */
+    kDmaRequestMux0PortD            = 50|0x100U,   /**< PTD. */
+    kDmaRequestMux0PortE            = 51|0x100U,   /**< PTE. */
+    kDmaRequestMux0ADC0             = 52|0x100U,   /**< ADC0. */
+    kDmaRequestMux0Reserved53       = 53|0x100U,   /**< Reserved53 */
+    kDmaRequestMux0DAC0             = 54|0x100U,   /**< DAC0. */
+    kDmaRequestMux0LTC0PKHA         = 55|0x100U,   /**< LTC0 PKHA. */
+    kDmaRequestMux0CMP0             = 56|0x100U,   /**< CMP0. */
+    kDmaRequestMux0Reserved57       = 57|0x100U,   /**< Reserved57 */
+    kDmaRequestMux0LTC0InputFIFO    = 58|0x100U,   /**< LTC0 Input FIFO. */
+    kDmaRequestMux0LTC0OutputFIFO   = 59|0x100U,   /**< LTC0 Output FIFO. */
+    kDmaRequestMux0AlwaysOn60       = 60|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn61       = 61|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn62       = 62|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn63       = 63|0x100U,   /**< DMAMUX Always Enabled slot. */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name SC1 - ADC Status and Control Registers 1 */
+#define ADC_SC1_ADCH_MASK                        (0x1FU)
+#define ADC_SC1_ADCH_SHIFT                       (0U)
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK                        (0x20U)
+#define ADC_SC1_DIFF_SHIFT                       (5U)
+#define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK                        (0x40U)
+#define ADC_SC1_AIEN_SHIFT                       (6U)
+#define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK                        (0x80U)
+#define ADC_SC1_COCO_SHIFT                       (7U)
+#define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
+
+/* The count of ADC_SC1 */
+#define ADC_SC1_COUNT                            (2U)
+
+/*! @name CFG1 - ADC Configuration Register 1 */
+#define ADC_CFG1_ADICLK_MASK                     (0x3U)
+#define ADC_CFG1_ADICLK_SHIFT                    (0U)
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK                       (0xCU)
+#define ADC_CFG1_MODE_SHIFT                      (2U)
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK                     (0x10U)
+#define ADC_CFG1_ADLSMP_SHIFT                    (4U)
+#define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK                       (0x60U)
+#define ADC_CFG1_ADIV_SHIFT                      (5U)
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK                      (0x80U)
+#define ADC_CFG1_ADLPC_SHIFT                     (7U)
+#define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
+
+/*! @name CFG2 - ADC Configuration Register 2 */
+#define ADC_CFG2_ADLSTS_MASK                     (0x3U)
+#define ADC_CFG2_ADLSTS_SHIFT                    (0U)
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK                      (0x4U)
+#define ADC_CFG2_ADHSC_SHIFT                     (2U)
+#define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK                    (0x8U)
+#define ADC_CFG2_ADACKEN_SHIFT                   (3U)
+#define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK                     (0x10U)
+#define ADC_CFG2_MUXSEL_SHIFT                    (4U)
+#define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
+
+/*! @name R - ADC Data Result Register */
+#define ADC_R_D_MASK                             (0xFFFFU)
+#define ADC_R_D_SHIFT                            (0U)
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
+
+/* The count of ADC_R */
+#define ADC_R_COUNT                              (2U)
+
+/*! @name CV1 - Compare Value Registers */
+#define ADC_CV1_CV_MASK                          (0xFFFFU)
+#define ADC_CV1_CV_SHIFT                         (0U)
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
+
+/*! @name CV2 - Compare Value Registers */
+#define ADC_CV2_CV_MASK                          (0xFFFFU)
+#define ADC_CV2_CV_SHIFT                         (0U)
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
+
+/*! @name SC2 - Status and Control Register 2 */
+#define ADC_SC2_REFSEL_MASK                      (0x3U)
+#define ADC_SC2_REFSEL_SHIFT                     (0U)
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK                       (0x4U)
+#define ADC_SC2_DMAEN_SHIFT                      (2U)
+#define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK                       (0x8U)
+#define ADC_SC2_ACREN_SHIFT                      (3U)
+#define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK                       (0x10U)
+#define ADC_SC2_ACFGT_SHIFT                      (4U)
+#define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK                        (0x20U)
+#define ADC_SC2_ACFE_SHIFT                       (5U)
+#define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK                       (0x40U)
+#define ADC_SC2_ADTRG_SHIFT                      (6U)
+#define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK                       (0x80U)
+#define ADC_SC2_ADACT_SHIFT                      (7U)
+#define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
+
+/*! @name SC3 - Status and Control Register 3 */
+#define ADC_SC3_AVGS_MASK                        (0x3U)
+#define ADC_SC3_AVGS_SHIFT                       (0U)
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK                        (0x4U)
+#define ADC_SC3_AVGE_SHIFT                       (2U)
+#define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK                        (0x8U)
+#define ADC_SC3_ADCO_SHIFT                       (3U)
+#define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK                        (0x40U)
+#define ADC_SC3_CALF_SHIFT                       (6U)
+#define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK                         (0x80U)
+#define ADC_SC3_CAL_SHIFT                        (7U)
+#define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
+
+/*! @name OFS - ADC Offset Correction Register */
+#define ADC_OFS_OFS_MASK                         (0xFFFFU)
+#define ADC_OFS_OFS_SHIFT                        (0U)
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
+
+/*! @name PG - ADC Plus-Side Gain Register */
+#define ADC_PG_PG_MASK                           (0xFFFFU)
+#define ADC_PG_PG_SHIFT                          (0U)
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
+
+/*! @name MG - ADC Minus-Side Gain Register */
+#define ADC_MG_MG_MASK                           (0xFFFFU)
+#define ADC_MG_MG_SHIFT                          (0U)
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
+
+/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPD_CLPD_MASK                       (0x3FU)
+#define ADC_CLPD_CLPD_SHIFT                      (0U)
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
+
+/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPS_CLPS_MASK                       (0x3FU)
+#define ADC_CLPS_CLPS_SHIFT                      (0U)
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
+
+/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP4_CLP4_MASK                       (0x3FFU)
+#define ADC_CLP4_CLP4_SHIFT                      (0U)
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
+
+/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP3_CLP3_MASK                       (0x1FFU)
+#define ADC_CLP3_CLP3_SHIFT                      (0U)
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
+
+/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP2_CLP2_MASK                       (0xFFU)
+#define ADC_CLP2_CLP2_SHIFT                      (0U)
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
+
+/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP1_CLP1_MASK                       (0x7FU)
+#define ADC_CLP1_CLP1_SHIFT                      (0U)
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
+
+/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP0_CLP0_MASK                       (0x3FU)
+#define ADC_CLP0_CLP0_SHIFT                      (0U)
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
+
+/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMD_CLMD_MASK                       (0x3FU)
+#define ADC_CLMD_CLMD_SHIFT                      (0U)
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
+
+/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMS_CLMS_MASK                       (0x3FU)
+#define ADC_CLMS_CLMS_SHIFT                      (0U)
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
+
+/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM4_CLM4_MASK                       (0x3FFU)
+#define ADC_CLM4_CLM4_SHIFT                      (0U)
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
+
+/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM3_CLM3_MASK                       (0x1FFU)
+#define ADC_CLM3_CLM3_SHIFT                      (0U)
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
+
+/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM2_CLM2_MASK                       (0xFFU)
+#define ADC_CLM2_CLM2_SHIFT                      (0U)
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
+
+/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM1_CLM1_MASK                       (0x7FU)
+#define ADC_CLM1_CLM1_SHIFT                      (0U)
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
+
+/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM0_CLM0_MASK                       (0x3FU)
+#define ADC_CLM0_CLM0_SHIFT                      (0U)
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MPRA;                              /**< Master Privilege Register A, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PACRA;                             /**< Peripheral Access Control Register, offset: 0x20 */
+  __IO uint32_t PACRB;                             /**< Peripheral Access Control Register, offset: 0x24 */
+  __IO uint32_t PACRC;                             /**< Peripheral Access Control Register, offset: 0x28 */
+  __IO uint32_t PACRD;                             /**< Peripheral Access Control Register, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PACRE;                             /**< Peripheral Access Control Register, offset: 0x40 */
+  __IO uint32_t PACRF;                             /**< Peripheral Access Control Register, offset: 0x44 */
+  __IO uint32_t PACRG;                             /**< Peripheral Access Control Register, offset: 0x48 */
+  __IO uint32_t PACRH;                             /**< Peripheral Access Control Register, offset: 0x4C */
+  __IO uint32_t PACRI;                             /**< Peripheral Access Control Register, offset: 0x50 */
+  __IO uint32_t PACRJ;                             /**< Peripheral Access Control Register, offset: 0x54 */
+  __IO uint32_t PACRK;                             /**< Peripheral Access Control Register, offset: 0x58 */
+  __IO uint32_t PACRL;                             /**< Peripheral Access Control Register, offset: 0x5C */
+  __IO uint32_t PACRM;                             /**< Peripheral Access Control Register, offset: 0x60 */
+  __IO uint32_t PACRN;                             /**< Peripheral Access Control Register, offset: 0x64 */
+  __IO uint32_t PACRO;                             /**< Peripheral Access Control Register, offset: 0x68 */
+  __IO uint32_t PACRP;                             /**< Peripheral Access Control Register, offset: 0x6C */
+} AIPS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/*! @name MPRA - Master Privilege Register A */
+#define AIPS_MPRA_MPL4_MASK                      (0x1000U)
+#define AIPS_MPRA_MPL4_SHIFT                     (12U)
+#define AIPS_MPRA_MPL4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
+#define AIPS_MPRA_MTW4_MASK                      (0x2000U)
+#define AIPS_MPRA_MTW4_SHIFT                     (13U)
+#define AIPS_MPRA_MTW4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
+#define AIPS_MPRA_MTR4_MASK                      (0x4000U)
+#define AIPS_MPRA_MTR4_SHIFT                     (14U)
+#define AIPS_MPRA_MTR4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
+#define AIPS_MPRA_MPL3_MASK                      (0x10000U)
+#define AIPS_MPRA_MPL3_SHIFT                     (16U)
+#define AIPS_MPRA_MPL3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
+#define AIPS_MPRA_MTW3_MASK                      (0x20000U)
+#define AIPS_MPRA_MTW3_SHIFT                     (17U)
+#define AIPS_MPRA_MTW3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
+#define AIPS_MPRA_MTR3_MASK                      (0x40000U)
+#define AIPS_MPRA_MTR3_SHIFT                     (18U)
+#define AIPS_MPRA_MTR3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
+#define AIPS_MPRA_MPL2_MASK                      (0x100000U)
+#define AIPS_MPRA_MPL2_SHIFT                     (20U)
+#define AIPS_MPRA_MPL2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MTW2_MASK                      (0x200000U)
+#define AIPS_MPRA_MTW2_SHIFT                     (21U)
+#define AIPS_MPRA_MTW2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTR2_MASK                      (0x400000U)
+#define AIPS_MPRA_MTR2_SHIFT                     (22U)
+#define AIPS_MPRA_MTR2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MPL1_MASK                      (0x1000000U)
+#define AIPS_MPRA_MPL1_SHIFT                     (24U)
+#define AIPS_MPRA_MPL1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MTW1_MASK                      (0x2000000U)
+#define AIPS_MPRA_MTW1_SHIFT                     (25U)
+#define AIPS_MPRA_MTW1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTR1_MASK                      (0x4000000U)
+#define AIPS_MPRA_MTR1_SHIFT                     (26U)
+#define AIPS_MPRA_MTR1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MPL0_MASK                      (0x10000000U)
+#define AIPS_MPRA_MPL0_SHIFT                     (28U)
+#define AIPS_MPRA_MPL0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MTW0_MASK                      (0x20000000U)
+#define AIPS_MPRA_MTW0_SHIFT                     (29U)
+#define AIPS_MPRA_MTW0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTR0_MASK                      (0x40000000U)
+#define AIPS_MPRA_MTR0_SHIFT                     (30U)
+#define AIPS_MPRA_MTR0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
+
+/*! @name PACRA - Peripheral Access Control Register */
+#define AIPS_PACRA_TP7_MASK                      (0x1U)
+#define AIPS_PACRA_TP7_SHIFT                     (0U)
+#define AIPS_PACRA_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_WP7_MASK                      (0x2U)
+#define AIPS_PACRA_WP7_SHIFT                     (1U)
+#define AIPS_PACRA_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_SP7_MASK                      (0x4U)
+#define AIPS_PACRA_SP7_SHIFT                     (2U)
+#define AIPS_PACRA_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_TP6_MASK                      (0x10U)
+#define AIPS_PACRA_TP6_SHIFT                     (4U)
+#define AIPS_PACRA_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_WP6_MASK                      (0x20U)
+#define AIPS_PACRA_WP6_SHIFT                     (5U)
+#define AIPS_PACRA_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_SP6_MASK                      (0x40U)
+#define AIPS_PACRA_SP6_SHIFT                     (6U)
+#define AIPS_PACRA_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_TP5_MASK                      (0x100U)
+#define AIPS_PACRA_TP5_SHIFT                     (8U)
+#define AIPS_PACRA_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_WP5_MASK                      (0x200U)
+#define AIPS_PACRA_WP5_SHIFT                     (9U)
+#define AIPS_PACRA_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_SP5_MASK                      (0x400U)
+#define AIPS_PACRA_SP5_SHIFT                     (10U)
+#define AIPS_PACRA_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_TP4_MASK                      (0x1000U)
+#define AIPS_PACRA_TP4_SHIFT                     (12U)
+#define AIPS_PACRA_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_WP4_MASK                      (0x2000U)
+#define AIPS_PACRA_WP4_SHIFT                     (13U)
+#define AIPS_PACRA_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_SP4_MASK                      (0x4000U)
+#define AIPS_PACRA_SP4_SHIFT                     (14U)
+#define AIPS_PACRA_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_TP3_MASK                      (0x10000U)
+#define AIPS_PACRA_TP3_SHIFT                     (16U)
+#define AIPS_PACRA_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_WP3_MASK                      (0x20000U)
+#define AIPS_PACRA_WP3_SHIFT                     (17U)
+#define AIPS_PACRA_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_SP3_MASK                      (0x40000U)
+#define AIPS_PACRA_SP3_SHIFT                     (18U)
+#define AIPS_PACRA_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_TP2_MASK                      (0x100000U)
+#define AIPS_PACRA_TP2_SHIFT                     (20U)
+#define AIPS_PACRA_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_WP2_MASK                      (0x200000U)
+#define AIPS_PACRA_WP2_SHIFT                     (21U)
+#define AIPS_PACRA_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_SP2_MASK                      (0x400000U)
+#define AIPS_PACRA_SP2_SHIFT                     (22U)
+#define AIPS_PACRA_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRA_TP1_SHIFT                     (24U)
+#define AIPS_PACRA_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRA_WP1_SHIFT                     (25U)
+#define AIPS_PACRA_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRA_SP1_SHIFT                     (26U)
+#define AIPS_PACRA_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRA_TP0_SHIFT                     (28U)
+#define AIPS_PACRA_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRA_WP0_SHIFT                     (29U)
+#define AIPS_PACRA_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRA_SP0_SHIFT                     (30U)
+#define AIPS_PACRA_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
+
+/*! @name PACRB - Peripheral Access Control Register */
+#define AIPS_PACRB_TP7_MASK                      (0x1U)
+#define AIPS_PACRB_TP7_SHIFT                     (0U)
+#define AIPS_PACRB_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_WP7_MASK                      (0x2U)
+#define AIPS_PACRB_WP7_SHIFT                     (1U)
+#define AIPS_PACRB_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_SP7_MASK                      (0x4U)
+#define AIPS_PACRB_SP7_SHIFT                     (2U)
+#define AIPS_PACRB_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_TP6_MASK                      (0x10U)
+#define AIPS_PACRB_TP6_SHIFT                     (4U)
+#define AIPS_PACRB_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_WP6_MASK                      (0x20U)
+#define AIPS_PACRB_WP6_SHIFT                     (5U)
+#define AIPS_PACRB_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
+#define AIPS_PACRB_SP6_MASK                      (0x40U)
+#define AIPS_PACRB_SP6_SHIFT                     (6U)
+#define AIPS_PACRB_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
+#define AIPS_PACRB_TP5_MASK                      (0x100U)
+#define AIPS_PACRB_TP5_SHIFT                     (8U)
+#define AIPS_PACRB_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
+#define AIPS_PACRB_WP5_MASK                      (0x200U)
+#define AIPS_PACRB_WP5_SHIFT                     (9U)
+#define AIPS_PACRB_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
+#define AIPS_PACRB_SP5_MASK                      (0x400U)
+#define AIPS_PACRB_SP5_SHIFT                     (10U)
+#define AIPS_PACRB_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
+#define AIPS_PACRB_TP4_MASK                      (0x1000U)
+#define AIPS_PACRB_TP4_SHIFT                     (12U)
+#define AIPS_PACRB_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
+#define AIPS_PACRB_WP4_MASK                      (0x2000U)
+#define AIPS_PACRB_WP4_SHIFT                     (13U)
+#define AIPS_PACRB_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
+#define AIPS_PACRB_SP4_MASK                      (0x4000U)
+#define AIPS_PACRB_SP4_SHIFT                     (14U)
+#define AIPS_PACRB_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
+#define AIPS_PACRB_TP3_MASK                      (0x10000U)
+#define AIPS_PACRB_TP3_SHIFT                     (16U)
+#define AIPS_PACRB_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
+#define AIPS_PACRB_WP3_MASK                      (0x20000U)
+#define AIPS_PACRB_WP3_SHIFT                     (17U)
+#define AIPS_PACRB_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
+#define AIPS_PACRB_SP3_MASK                      (0x40000U)
+#define AIPS_PACRB_SP3_SHIFT                     (18U)
+#define AIPS_PACRB_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
+#define AIPS_PACRB_TP2_MASK                      (0x100000U)
+#define AIPS_PACRB_TP2_SHIFT                     (20U)
+#define AIPS_PACRB_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
+#define AIPS_PACRB_WP2_MASK                      (0x200000U)
+#define AIPS_PACRB_WP2_SHIFT                     (21U)
+#define AIPS_PACRB_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
+#define AIPS_PACRB_SP2_MASK                      (0x400000U)
+#define AIPS_PACRB_SP2_SHIFT                     (22U)
+#define AIPS_PACRB_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
+#define AIPS_PACRB_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRB_TP1_SHIFT                     (24U)
+#define AIPS_PACRB_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
+#define AIPS_PACRB_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRB_WP1_SHIFT                     (25U)
+#define AIPS_PACRB_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
+#define AIPS_PACRB_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRB_SP1_SHIFT                     (26U)
+#define AIPS_PACRB_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
+#define AIPS_PACRB_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRB_TP0_SHIFT                     (28U)
+#define AIPS_PACRB_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
+#define AIPS_PACRB_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRB_WP0_SHIFT                     (29U)
+#define AIPS_PACRB_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
+#define AIPS_PACRB_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRB_SP0_SHIFT                     (30U)
+#define AIPS_PACRB_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
+
+/*! @name PACRC - Peripheral Access Control Register */
+#define AIPS_PACRC_TP7_MASK                      (0x1U)
+#define AIPS_PACRC_TP7_SHIFT                     (0U)
+#define AIPS_PACRC_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
+#define AIPS_PACRC_WP7_MASK                      (0x2U)
+#define AIPS_PACRC_WP7_SHIFT                     (1U)
+#define AIPS_PACRC_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
+#define AIPS_PACRC_SP7_MASK                      (0x4U)
+#define AIPS_PACRC_SP7_SHIFT                     (2U)
+#define AIPS_PACRC_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
+#define AIPS_PACRC_TP6_MASK                      (0x10U)
+#define AIPS_PACRC_TP6_SHIFT                     (4U)
+#define AIPS_PACRC_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
+#define AIPS_PACRC_WP6_MASK                      (0x20U)
+#define AIPS_PACRC_WP6_SHIFT                     (5U)
+#define AIPS_PACRC_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
+#define AIPS_PACRC_SP6_MASK                      (0x40U)
+#define AIPS_PACRC_SP6_SHIFT                     (6U)
+#define AIPS_PACRC_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
+#define AIPS_PACRC_TP5_MASK                      (0x100U)
+#define AIPS_PACRC_TP5_SHIFT                     (8U)
+#define AIPS_PACRC_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
+#define AIPS_PACRC_WP5_MASK                      (0x200U)
+#define AIPS_PACRC_WP5_SHIFT                     (9U)
+#define AIPS_PACRC_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
+#define AIPS_PACRC_SP5_MASK                      (0x400U)
+#define AIPS_PACRC_SP5_SHIFT                     (10U)
+#define AIPS_PACRC_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
+#define AIPS_PACRC_TP4_MASK                      (0x1000U)
+#define AIPS_PACRC_TP4_SHIFT                     (12U)
+#define AIPS_PACRC_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
+#define AIPS_PACRC_WP4_MASK                      (0x2000U)
+#define AIPS_PACRC_WP4_SHIFT                     (13U)
+#define AIPS_PACRC_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
+#define AIPS_PACRC_SP4_MASK                      (0x4000U)
+#define AIPS_PACRC_SP4_SHIFT                     (14U)
+#define AIPS_PACRC_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
+#define AIPS_PACRC_TP3_MASK                      (0x10000U)
+#define AIPS_PACRC_TP3_SHIFT                     (16U)
+#define AIPS_PACRC_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
+#define AIPS_PACRC_WP3_MASK                      (0x20000U)
+#define AIPS_PACRC_WP3_SHIFT                     (17U)
+#define AIPS_PACRC_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
+#define AIPS_PACRC_SP3_MASK                      (0x40000U)
+#define AIPS_PACRC_SP3_SHIFT                     (18U)
+#define AIPS_PACRC_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
+#define AIPS_PACRC_TP2_MASK                      (0x100000U)
+#define AIPS_PACRC_TP2_SHIFT                     (20U)
+#define AIPS_PACRC_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
+#define AIPS_PACRC_WP2_MASK                      (0x200000U)
+#define AIPS_PACRC_WP2_SHIFT                     (21U)
+#define AIPS_PACRC_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
+#define AIPS_PACRC_SP2_MASK                      (0x400000U)
+#define AIPS_PACRC_SP2_SHIFT                     (22U)
+#define AIPS_PACRC_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
+#define AIPS_PACRC_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRC_TP1_SHIFT                     (24U)
+#define AIPS_PACRC_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
+#define AIPS_PACRC_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRC_WP1_SHIFT                     (25U)
+#define AIPS_PACRC_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
+#define AIPS_PACRC_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRC_SP1_SHIFT                     (26U)
+#define AIPS_PACRC_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
+#define AIPS_PACRC_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRC_TP0_SHIFT                     (28U)
+#define AIPS_PACRC_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
+#define AIPS_PACRC_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRC_WP0_SHIFT                     (29U)
+#define AIPS_PACRC_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
+#define AIPS_PACRC_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRC_SP0_SHIFT                     (30U)
+#define AIPS_PACRC_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
+
+/*! @name PACRD - Peripheral Access Control Register */
+#define AIPS_PACRD_TP7_MASK                      (0x1U)
+#define AIPS_PACRD_TP7_SHIFT                     (0U)
+#define AIPS_PACRD_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
+#define AIPS_PACRD_WP7_MASK                      (0x2U)
+#define AIPS_PACRD_WP7_SHIFT                     (1U)
+#define AIPS_PACRD_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
+#define AIPS_PACRD_SP7_MASK                      (0x4U)
+#define AIPS_PACRD_SP7_SHIFT                     (2U)
+#define AIPS_PACRD_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
+#define AIPS_PACRD_TP6_MASK                      (0x10U)
+#define AIPS_PACRD_TP6_SHIFT                     (4U)
+#define AIPS_PACRD_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
+#define AIPS_PACRD_WP6_MASK                      (0x20U)
+#define AIPS_PACRD_WP6_SHIFT                     (5U)
+#define AIPS_PACRD_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
+#define AIPS_PACRD_SP6_MASK                      (0x40U)
+#define AIPS_PACRD_SP6_SHIFT                     (6U)
+#define AIPS_PACRD_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
+#define AIPS_PACRD_TP5_MASK                      (0x100U)
+#define AIPS_PACRD_TP5_SHIFT                     (8U)
+#define AIPS_PACRD_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
+#define AIPS_PACRD_WP5_MASK                      (0x200U)
+#define AIPS_PACRD_WP5_SHIFT                     (9U)
+#define AIPS_PACRD_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
+#define AIPS_PACRD_SP5_MASK                      (0x400U)
+#define AIPS_PACRD_SP5_SHIFT                     (10U)
+#define AIPS_PACRD_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
+#define AIPS_PACRD_TP4_MASK                      (0x1000U)
+#define AIPS_PACRD_TP4_SHIFT                     (12U)
+#define AIPS_PACRD_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
+#define AIPS_PACRD_WP4_MASK                      (0x2000U)
+#define AIPS_PACRD_WP4_SHIFT                     (13U)
+#define AIPS_PACRD_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
+#define AIPS_PACRD_SP4_MASK                      (0x4000U)
+#define AIPS_PACRD_SP4_SHIFT                     (14U)
+#define AIPS_PACRD_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
+#define AIPS_PACRD_TP3_MASK                      (0x10000U)
+#define AIPS_PACRD_TP3_SHIFT                     (16U)
+#define AIPS_PACRD_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
+#define AIPS_PACRD_WP3_MASK                      (0x20000U)
+#define AIPS_PACRD_WP3_SHIFT                     (17U)
+#define AIPS_PACRD_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
+#define AIPS_PACRD_SP3_MASK                      (0x40000U)
+#define AIPS_PACRD_SP3_SHIFT                     (18U)
+#define AIPS_PACRD_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
+#define AIPS_PACRD_TP2_MASK                      (0x100000U)
+#define AIPS_PACRD_TP2_SHIFT                     (20U)
+#define AIPS_PACRD_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
+#define AIPS_PACRD_WP2_MASK                      (0x200000U)
+#define AIPS_PACRD_WP2_SHIFT                     (21U)
+#define AIPS_PACRD_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
+#define AIPS_PACRD_SP2_MASK                      (0x400000U)
+#define AIPS_PACRD_SP2_SHIFT                     (22U)
+#define AIPS_PACRD_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
+#define AIPS_PACRD_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRD_TP1_SHIFT                     (24U)
+#define AIPS_PACRD_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
+#define AIPS_PACRD_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRD_WP1_SHIFT                     (25U)
+#define AIPS_PACRD_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
+#define AIPS_PACRD_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRD_SP1_SHIFT                     (26U)
+#define AIPS_PACRD_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
+#define AIPS_PACRD_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRD_TP0_SHIFT                     (28U)
+#define AIPS_PACRD_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
+#define AIPS_PACRD_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRD_WP0_SHIFT                     (29U)
+#define AIPS_PACRD_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
+#define AIPS_PACRD_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRD_SP0_SHIFT                     (30U)
+#define AIPS_PACRD_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
+
+/*! @name PACRE - Peripheral Access Control Register */
+#define AIPS_PACRE_TP7_MASK                      (0x1U)
+#define AIPS_PACRE_TP7_SHIFT                     (0U)
+#define AIPS_PACRE_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
+#define AIPS_PACRE_WP7_MASK                      (0x2U)
+#define AIPS_PACRE_WP7_SHIFT                     (1U)
+#define AIPS_PACRE_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
+#define AIPS_PACRE_SP7_MASK                      (0x4U)
+#define AIPS_PACRE_SP7_SHIFT                     (2U)
+#define AIPS_PACRE_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
+#define AIPS_PACRE_TP6_MASK                      (0x10U)
+#define AIPS_PACRE_TP6_SHIFT                     (4U)
+#define AIPS_PACRE_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
+#define AIPS_PACRE_WP6_MASK                      (0x20U)
+#define AIPS_PACRE_WP6_SHIFT                     (5U)
+#define AIPS_PACRE_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
+#define AIPS_PACRE_SP6_MASK                      (0x40U)
+#define AIPS_PACRE_SP6_SHIFT                     (6U)
+#define AIPS_PACRE_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
+#define AIPS_PACRE_TP5_MASK                      (0x100U)
+#define AIPS_PACRE_TP5_SHIFT                     (8U)
+#define AIPS_PACRE_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
+#define AIPS_PACRE_WP5_MASK                      (0x200U)
+#define AIPS_PACRE_WP5_SHIFT                     (9U)
+#define AIPS_PACRE_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
+#define AIPS_PACRE_SP5_MASK                      (0x400U)
+#define AIPS_PACRE_SP5_SHIFT                     (10U)
+#define AIPS_PACRE_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
+#define AIPS_PACRE_TP4_MASK                      (0x1000U)
+#define AIPS_PACRE_TP4_SHIFT                     (12U)
+#define AIPS_PACRE_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
+#define AIPS_PACRE_WP4_MASK                      (0x2000U)
+#define AIPS_PACRE_WP4_SHIFT                     (13U)
+#define AIPS_PACRE_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
+#define AIPS_PACRE_SP4_MASK                      (0x4000U)
+#define AIPS_PACRE_SP4_SHIFT                     (14U)
+#define AIPS_PACRE_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
+#define AIPS_PACRE_TP3_MASK                      (0x10000U)
+#define AIPS_PACRE_TP3_SHIFT                     (16U)
+#define AIPS_PACRE_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
+#define AIPS_PACRE_WP3_MASK                      (0x20000U)
+#define AIPS_PACRE_WP3_SHIFT                     (17U)
+#define AIPS_PACRE_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
+#define AIPS_PACRE_SP3_MASK                      (0x40000U)
+#define AIPS_PACRE_SP3_SHIFT                     (18U)
+#define AIPS_PACRE_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
+#define AIPS_PACRE_TP2_MASK                      (0x100000U)
+#define AIPS_PACRE_TP2_SHIFT                     (20U)
+#define AIPS_PACRE_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
+#define AIPS_PACRE_WP2_MASK                      (0x200000U)
+#define AIPS_PACRE_WP2_SHIFT                     (21U)
+#define AIPS_PACRE_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
+#define AIPS_PACRE_SP2_MASK                      (0x400000U)
+#define AIPS_PACRE_SP2_SHIFT                     (22U)
+#define AIPS_PACRE_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
+#define AIPS_PACRE_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRE_TP1_SHIFT                     (24U)
+#define AIPS_PACRE_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
+#define AIPS_PACRE_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRE_WP1_SHIFT                     (25U)
+#define AIPS_PACRE_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
+#define AIPS_PACRE_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRE_SP1_SHIFT                     (26U)
+#define AIPS_PACRE_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
+#define AIPS_PACRE_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRE_TP0_SHIFT                     (28U)
+#define AIPS_PACRE_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
+#define AIPS_PACRE_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRE_WP0_SHIFT                     (29U)
+#define AIPS_PACRE_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
+#define AIPS_PACRE_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRE_SP0_SHIFT                     (30U)
+#define AIPS_PACRE_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
+
+/*! @name PACRF - Peripheral Access Control Register */
+#define AIPS_PACRF_TP7_MASK                      (0x1U)
+#define AIPS_PACRF_TP7_SHIFT                     (0U)
+#define AIPS_PACRF_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
+#define AIPS_PACRF_WP7_MASK                      (0x2U)
+#define AIPS_PACRF_WP7_SHIFT                     (1U)
+#define AIPS_PACRF_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
+#define AIPS_PACRF_SP7_MASK                      (0x4U)
+#define AIPS_PACRF_SP7_SHIFT                     (2U)
+#define AIPS_PACRF_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
+#define AIPS_PACRF_TP6_MASK                      (0x10U)
+#define AIPS_PACRF_TP6_SHIFT                     (4U)
+#define AIPS_PACRF_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
+#define AIPS_PACRF_WP6_MASK                      (0x20U)
+#define AIPS_PACRF_WP6_SHIFT                     (5U)
+#define AIPS_PACRF_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
+#define AIPS_PACRF_SP6_MASK                      (0x40U)
+#define AIPS_PACRF_SP6_SHIFT                     (6U)
+#define AIPS_PACRF_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
+#define AIPS_PACRF_TP5_MASK                      (0x100U)
+#define AIPS_PACRF_TP5_SHIFT                     (8U)
+#define AIPS_PACRF_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
+#define AIPS_PACRF_WP5_MASK                      (0x200U)
+#define AIPS_PACRF_WP5_SHIFT                     (9U)
+#define AIPS_PACRF_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
+#define AIPS_PACRF_SP5_MASK                      (0x400U)
+#define AIPS_PACRF_SP5_SHIFT                     (10U)
+#define AIPS_PACRF_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
+#define AIPS_PACRF_TP4_MASK                      (0x1000U)
+#define AIPS_PACRF_TP4_SHIFT                     (12U)
+#define AIPS_PACRF_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
+#define AIPS_PACRF_WP4_MASK                      (0x2000U)
+#define AIPS_PACRF_WP4_SHIFT                     (13U)
+#define AIPS_PACRF_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
+#define AIPS_PACRF_SP4_MASK                      (0x4000U)
+#define AIPS_PACRF_SP4_SHIFT                     (14U)
+#define AIPS_PACRF_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
+#define AIPS_PACRF_TP3_MASK                      (0x10000U)
+#define AIPS_PACRF_TP3_SHIFT                     (16U)
+#define AIPS_PACRF_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
+#define AIPS_PACRF_WP3_MASK                      (0x20000U)
+#define AIPS_PACRF_WP3_SHIFT                     (17U)
+#define AIPS_PACRF_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
+#define AIPS_PACRF_SP3_MASK                      (0x40000U)
+#define AIPS_PACRF_SP3_SHIFT                     (18U)
+#define AIPS_PACRF_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
+#define AIPS_PACRF_TP2_MASK                      (0x100000U)
+#define AIPS_PACRF_TP2_SHIFT                     (20U)
+#define AIPS_PACRF_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
+#define AIPS_PACRF_WP2_MASK                      (0x200000U)
+#define AIPS_PACRF_WP2_SHIFT                     (21U)
+#define AIPS_PACRF_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
+#define AIPS_PACRF_SP2_MASK                      (0x400000U)
+#define AIPS_PACRF_SP2_SHIFT                     (22U)
+#define AIPS_PACRF_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
+#define AIPS_PACRF_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRF_TP1_SHIFT                     (24U)
+#define AIPS_PACRF_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
+#define AIPS_PACRF_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRF_WP1_SHIFT                     (25U)
+#define AIPS_PACRF_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
+#define AIPS_PACRF_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRF_SP1_SHIFT                     (26U)
+#define AIPS_PACRF_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
+#define AIPS_PACRF_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRF_TP0_SHIFT                     (28U)
+#define AIPS_PACRF_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
+#define AIPS_PACRF_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRF_WP0_SHIFT                     (29U)
+#define AIPS_PACRF_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
+#define AIPS_PACRF_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRF_SP0_SHIFT                     (30U)
+#define AIPS_PACRF_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
+
+/*! @name PACRG - Peripheral Access Control Register */
+#define AIPS_PACRG_TP7_MASK                      (0x1U)
+#define AIPS_PACRG_TP7_SHIFT                     (0U)
+#define AIPS_PACRG_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
+#define AIPS_PACRG_WP7_MASK                      (0x2U)
+#define AIPS_PACRG_WP7_SHIFT                     (1U)
+#define AIPS_PACRG_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
+#define AIPS_PACRG_SP7_MASK                      (0x4U)
+#define AIPS_PACRG_SP7_SHIFT                     (2U)
+#define AIPS_PACRG_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
+#define AIPS_PACRG_TP6_MASK                      (0x10U)
+#define AIPS_PACRG_TP6_SHIFT                     (4U)
+#define AIPS_PACRG_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
+#define AIPS_PACRG_WP6_MASK                      (0x20U)
+#define AIPS_PACRG_WP6_SHIFT                     (5U)
+#define AIPS_PACRG_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
+#define AIPS_PACRG_SP6_MASK                      (0x40U)
+#define AIPS_PACRG_SP6_SHIFT                     (6U)
+#define AIPS_PACRG_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
+#define AIPS_PACRG_TP5_MASK                      (0x100U)
+#define AIPS_PACRG_TP5_SHIFT                     (8U)
+#define AIPS_PACRG_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
+#define AIPS_PACRG_WP5_MASK                      (0x200U)
+#define AIPS_PACRG_WP5_SHIFT                     (9U)
+#define AIPS_PACRG_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
+#define AIPS_PACRG_SP5_MASK                      (0x400U)
+#define AIPS_PACRG_SP5_SHIFT                     (10U)
+#define AIPS_PACRG_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
+#define AIPS_PACRG_TP4_MASK                      (0x1000U)
+#define AIPS_PACRG_TP4_SHIFT                     (12U)
+#define AIPS_PACRG_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
+#define AIPS_PACRG_WP4_MASK                      (0x2000U)
+#define AIPS_PACRG_WP4_SHIFT                     (13U)
+#define AIPS_PACRG_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
+#define AIPS_PACRG_SP4_MASK                      (0x4000U)
+#define AIPS_PACRG_SP4_SHIFT                     (14U)
+#define AIPS_PACRG_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
+#define AIPS_PACRG_TP3_MASK                      (0x10000U)
+#define AIPS_PACRG_TP3_SHIFT                     (16U)
+#define AIPS_PACRG_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
+#define AIPS_PACRG_WP3_MASK                      (0x20000U)
+#define AIPS_PACRG_WP3_SHIFT                     (17U)
+#define AIPS_PACRG_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
+#define AIPS_PACRG_SP3_MASK                      (0x40000U)
+#define AIPS_PACRG_SP3_SHIFT                     (18U)
+#define AIPS_PACRG_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
+#define AIPS_PACRG_TP2_MASK                      (0x100000U)
+#define AIPS_PACRG_TP2_SHIFT                     (20U)
+#define AIPS_PACRG_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
+#define AIPS_PACRG_WP2_MASK                      (0x200000U)
+#define AIPS_PACRG_WP2_SHIFT                     (21U)
+#define AIPS_PACRG_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
+#define AIPS_PACRG_SP2_MASK                      (0x400000U)
+#define AIPS_PACRG_SP2_SHIFT                     (22U)
+#define AIPS_PACRG_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
+#define AIPS_PACRG_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRG_TP1_SHIFT                     (24U)
+#define AIPS_PACRG_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
+#define AIPS_PACRG_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRG_WP1_SHIFT                     (25U)
+#define AIPS_PACRG_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
+#define AIPS_PACRG_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRG_SP1_SHIFT                     (26U)
+#define AIPS_PACRG_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
+#define AIPS_PACRG_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRG_TP0_SHIFT                     (28U)
+#define AIPS_PACRG_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
+#define AIPS_PACRG_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRG_WP0_SHIFT                     (29U)
+#define AIPS_PACRG_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
+#define AIPS_PACRG_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRG_SP0_SHIFT                     (30U)
+#define AIPS_PACRG_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
+
+/*! @name PACRH - Peripheral Access Control Register */
+#define AIPS_PACRH_TP7_MASK                      (0x1U)
+#define AIPS_PACRH_TP7_SHIFT                     (0U)
+#define AIPS_PACRH_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
+#define AIPS_PACRH_WP7_MASK                      (0x2U)
+#define AIPS_PACRH_WP7_SHIFT                     (1U)
+#define AIPS_PACRH_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
+#define AIPS_PACRH_SP7_MASK                      (0x4U)
+#define AIPS_PACRH_SP7_SHIFT                     (2U)
+#define AIPS_PACRH_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
+#define AIPS_PACRH_TP6_MASK                      (0x10U)
+#define AIPS_PACRH_TP6_SHIFT                     (4U)
+#define AIPS_PACRH_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
+#define AIPS_PACRH_WP6_MASK                      (0x20U)
+#define AIPS_PACRH_WP6_SHIFT                     (5U)
+#define AIPS_PACRH_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
+#define AIPS_PACRH_SP6_MASK                      (0x40U)
+#define AIPS_PACRH_SP6_SHIFT                     (6U)
+#define AIPS_PACRH_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
+#define AIPS_PACRH_TP5_MASK                      (0x100U)
+#define AIPS_PACRH_TP5_SHIFT                     (8U)
+#define AIPS_PACRH_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
+#define AIPS_PACRH_WP5_MASK                      (0x200U)
+#define AIPS_PACRH_WP5_SHIFT                     (9U)
+#define AIPS_PACRH_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
+#define AIPS_PACRH_SP5_MASK                      (0x400U)
+#define AIPS_PACRH_SP5_SHIFT                     (10U)
+#define AIPS_PACRH_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
+#define AIPS_PACRH_TP4_MASK                      (0x1000U)
+#define AIPS_PACRH_TP4_SHIFT                     (12U)
+#define AIPS_PACRH_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
+#define AIPS_PACRH_WP4_MASK                      (0x2000U)
+#define AIPS_PACRH_WP4_SHIFT                     (13U)
+#define AIPS_PACRH_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
+#define AIPS_PACRH_SP4_MASK                      (0x4000U)
+#define AIPS_PACRH_SP4_SHIFT                     (14U)
+#define AIPS_PACRH_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
+#define AIPS_PACRH_TP3_MASK                      (0x10000U)
+#define AIPS_PACRH_TP3_SHIFT                     (16U)
+#define AIPS_PACRH_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
+#define AIPS_PACRH_WP3_MASK                      (0x20000U)
+#define AIPS_PACRH_WP3_SHIFT                     (17U)
+#define AIPS_PACRH_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
+#define AIPS_PACRH_SP3_MASK                      (0x40000U)
+#define AIPS_PACRH_SP3_SHIFT                     (18U)
+#define AIPS_PACRH_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
+#define AIPS_PACRH_TP2_MASK                      (0x100000U)
+#define AIPS_PACRH_TP2_SHIFT                     (20U)
+#define AIPS_PACRH_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
+#define AIPS_PACRH_WP2_MASK                      (0x200000U)
+#define AIPS_PACRH_WP2_SHIFT                     (21U)
+#define AIPS_PACRH_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
+#define AIPS_PACRH_SP2_MASK                      (0x400000U)
+#define AIPS_PACRH_SP2_SHIFT                     (22U)
+#define AIPS_PACRH_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
+#define AIPS_PACRH_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRH_TP1_SHIFT                     (24U)
+#define AIPS_PACRH_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
+#define AIPS_PACRH_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRH_WP1_SHIFT                     (25U)
+#define AIPS_PACRH_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
+#define AIPS_PACRH_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRH_SP1_SHIFT                     (26U)
+#define AIPS_PACRH_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
+#define AIPS_PACRH_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRH_TP0_SHIFT                     (28U)
+#define AIPS_PACRH_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
+#define AIPS_PACRH_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRH_WP0_SHIFT                     (29U)
+#define AIPS_PACRH_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
+#define AIPS_PACRH_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRH_SP0_SHIFT                     (30U)
+#define AIPS_PACRH_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
+
+/*! @name PACRI - Peripheral Access Control Register */
+#define AIPS_PACRI_TP7_MASK                      (0x1U)
+#define AIPS_PACRI_TP7_SHIFT                     (0U)
+#define AIPS_PACRI_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
+#define AIPS_PACRI_WP7_MASK                      (0x2U)
+#define AIPS_PACRI_WP7_SHIFT                     (1U)
+#define AIPS_PACRI_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
+#define AIPS_PACRI_SP7_MASK                      (0x4U)
+#define AIPS_PACRI_SP7_SHIFT                     (2U)
+#define AIPS_PACRI_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
+#define AIPS_PACRI_TP6_MASK                      (0x10U)
+#define AIPS_PACRI_TP6_SHIFT                     (4U)
+#define AIPS_PACRI_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
+#define AIPS_PACRI_WP6_MASK                      (0x20U)
+#define AIPS_PACRI_WP6_SHIFT                     (5U)
+#define AIPS_PACRI_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
+#define AIPS_PACRI_SP6_MASK                      (0x40U)
+#define AIPS_PACRI_SP6_SHIFT                     (6U)
+#define AIPS_PACRI_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
+#define AIPS_PACRI_TP5_MASK                      (0x100U)
+#define AIPS_PACRI_TP5_SHIFT                     (8U)
+#define AIPS_PACRI_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
+#define AIPS_PACRI_WP5_MASK                      (0x200U)
+#define AIPS_PACRI_WP5_SHIFT                     (9U)
+#define AIPS_PACRI_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
+#define AIPS_PACRI_SP5_MASK                      (0x400U)
+#define AIPS_PACRI_SP5_SHIFT                     (10U)
+#define AIPS_PACRI_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
+#define AIPS_PACRI_TP4_MASK                      (0x1000U)
+#define AIPS_PACRI_TP4_SHIFT                     (12U)
+#define AIPS_PACRI_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
+#define AIPS_PACRI_WP4_MASK                      (0x2000U)
+#define AIPS_PACRI_WP4_SHIFT                     (13U)
+#define AIPS_PACRI_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
+#define AIPS_PACRI_SP4_MASK                      (0x4000U)
+#define AIPS_PACRI_SP4_SHIFT                     (14U)
+#define AIPS_PACRI_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
+#define AIPS_PACRI_TP3_MASK                      (0x10000U)
+#define AIPS_PACRI_TP3_SHIFT                     (16U)
+#define AIPS_PACRI_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
+#define AIPS_PACRI_WP3_MASK                      (0x20000U)
+#define AIPS_PACRI_WP3_SHIFT                     (17U)
+#define AIPS_PACRI_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
+#define AIPS_PACRI_SP3_MASK                      (0x40000U)
+#define AIPS_PACRI_SP3_SHIFT                     (18U)
+#define AIPS_PACRI_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
+#define AIPS_PACRI_TP2_MASK                      (0x100000U)
+#define AIPS_PACRI_TP2_SHIFT                     (20U)
+#define AIPS_PACRI_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
+#define AIPS_PACRI_WP2_MASK                      (0x200000U)
+#define AIPS_PACRI_WP2_SHIFT                     (21U)
+#define AIPS_PACRI_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
+#define AIPS_PACRI_SP2_MASK                      (0x400000U)
+#define AIPS_PACRI_SP2_SHIFT                     (22U)
+#define AIPS_PACRI_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
+#define AIPS_PACRI_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRI_TP1_SHIFT                     (24U)
+#define AIPS_PACRI_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
+#define AIPS_PACRI_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRI_WP1_SHIFT                     (25U)
+#define AIPS_PACRI_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
+#define AIPS_PACRI_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRI_SP1_SHIFT                     (26U)
+#define AIPS_PACRI_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
+#define AIPS_PACRI_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRI_TP0_SHIFT                     (28U)
+#define AIPS_PACRI_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
+#define AIPS_PACRI_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRI_WP0_SHIFT                     (29U)
+#define AIPS_PACRI_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
+#define AIPS_PACRI_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRI_SP0_SHIFT                     (30U)
+#define AIPS_PACRI_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
+
+/*! @name PACRJ - Peripheral Access Control Register */
+#define AIPS_PACRJ_TP7_MASK                      (0x1U)
+#define AIPS_PACRJ_TP7_SHIFT                     (0U)
+#define AIPS_PACRJ_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
+#define AIPS_PACRJ_WP7_MASK                      (0x2U)
+#define AIPS_PACRJ_WP7_SHIFT                     (1U)
+#define AIPS_PACRJ_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
+#define AIPS_PACRJ_SP7_MASK                      (0x4U)
+#define AIPS_PACRJ_SP7_SHIFT                     (2U)
+#define AIPS_PACRJ_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
+#define AIPS_PACRJ_TP6_MASK                      (0x10U)
+#define AIPS_PACRJ_TP6_SHIFT                     (4U)
+#define AIPS_PACRJ_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
+#define AIPS_PACRJ_WP6_MASK                      (0x20U)
+#define AIPS_PACRJ_WP6_SHIFT                     (5U)
+#define AIPS_PACRJ_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
+#define AIPS_PACRJ_SP6_MASK                      (0x40U)
+#define AIPS_PACRJ_SP6_SHIFT                     (6U)
+#define AIPS_PACRJ_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
+#define AIPS_PACRJ_TP5_MASK                      (0x100U)
+#define AIPS_PACRJ_TP5_SHIFT                     (8U)
+#define AIPS_PACRJ_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
+#define AIPS_PACRJ_WP5_MASK                      (0x200U)
+#define AIPS_PACRJ_WP5_SHIFT                     (9U)
+#define AIPS_PACRJ_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
+#define AIPS_PACRJ_SP5_MASK                      (0x400U)
+#define AIPS_PACRJ_SP5_SHIFT                     (10U)
+#define AIPS_PACRJ_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
+#define AIPS_PACRJ_TP4_MASK                      (0x1000U)
+#define AIPS_PACRJ_TP4_SHIFT                     (12U)
+#define AIPS_PACRJ_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
+#define AIPS_PACRJ_WP4_MASK                      (0x2000U)
+#define AIPS_PACRJ_WP4_SHIFT                     (13U)
+#define AIPS_PACRJ_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
+#define AIPS_PACRJ_SP4_MASK                      (0x4000U)
+#define AIPS_PACRJ_SP4_SHIFT                     (14U)
+#define AIPS_PACRJ_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
+#define AIPS_PACRJ_TP3_MASK                      (0x10000U)
+#define AIPS_PACRJ_TP3_SHIFT                     (16U)
+#define AIPS_PACRJ_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
+#define AIPS_PACRJ_WP3_MASK                      (0x20000U)
+#define AIPS_PACRJ_WP3_SHIFT                     (17U)
+#define AIPS_PACRJ_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
+#define AIPS_PACRJ_SP3_MASK                      (0x40000U)
+#define AIPS_PACRJ_SP3_SHIFT                     (18U)
+#define AIPS_PACRJ_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
+#define AIPS_PACRJ_TP2_MASK                      (0x100000U)
+#define AIPS_PACRJ_TP2_SHIFT                     (20U)
+#define AIPS_PACRJ_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
+#define AIPS_PACRJ_WP2_MASK                      (0x200000U)
+#define AIPS_PACRJ_WP2_SHIFT                     (21U)
+#define AIPS_PACRJ_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
+#define AIPS_PACRJ_SP2_MASK                      (0x400000U)
+#define AIPS_PACRJ_SP2_SHIFT                     (22U)
+#define AIPS_PACRJ_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
+#define AIPS_PACRJ_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRJ_TP1_SHIFT                     (24U)
+#define AIPS_PACRJ_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
+#define AIPS_PACRJ_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRJ_WP1_SHIFT                     (25U)
+#define AIPS_PACRJ_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
+#define AIPS_PACRJ_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRJ_SP1_SHIFT                     (26U)
+#define AIPS_PACRJ_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
+#define AIPS_PACRJ_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRJ_TP0_SHIFT                     (28U)
+#define AIPS_PACRJ_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
+#define AIPS_PACRJ_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRJ_WP0_SHIFT                     (29U)
+#define AIPS_PACRJ_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
+#define AIPS_PACRJ_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRJ_SP0_SHIFT                     (30U)
+#define AIPS_PACRJ_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
+
+/*! @name PACRK - Peripheral Access Control Register */
+#define AIPS_PACRK_TP7_MASK                      (0x1U)
+#define AIPS_PACRK_TP7_SHIFT                     (0U)
+#define AIPS_PACRK_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
+#define AIPS_PACRK_WP7_MASK                      (0x2U)
+#define AIPS_PACRK_WP7_SHIFT                     (1U)
+#define AIPS_PACRK_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
+#define AIPS_PACRK_SP7_MASK                      (0x4U)
+#define AIPS_PACRK_SP7_SHIFT                     (2U)
+#define AIPS_PACRK_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
+#define AIPS_PACRK_TP6_MASK                      (0x10U)
+#define AIPS_PACRK_TP6_SHIFT                     (4U)
+#define AIPS_PACRK_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
+#define AIPS_PACRK_WP6_MASK                      (0x20U)
+#define AIPS_PACRK_WP6_SHIFT                     (5U)
+#define AIPS_PACRK_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
+#define AIPS_PACRK_SP6_MASK                      (0x40U)
+#define AIPS_PACRK_SP6_SHIFT                     (6U)
+#define AIPS_PACRK_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
+#define AIPS_PACRK_TP5_MASK                      (0x100U)
+#define AIPS_PACRK_TP5_SHIFT                     (8U)
+#define AIPS_PACRK_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
+#define AIPS_PACRK_WP5_MASK                      (0x200U)
+#define AIPS_PACRK_WP5_SHIFT                     (9U)
+#define AIPS_PACRK_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
+#define AIPS_PACRK_SP5_MASK                      (0x400U)
+#define AIPS_PACRK_SP5_SHIFT                     (10U)
+#define AIPS_PACRK_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
+#define AIPS_PACRK_TP4_MASK                      (0x1000U)
+#define AIPS_PACRK_TP4_SHIFT                     (12U)
+#define AIPS_PACRK_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
+#define AIPS_PACRK_WP4_MASK                      (0x2000U)
+#define AIPS_PACRK_WP4_SHIFT                     (13U)
+#define AIPS_PACRK_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
+#define AIPS_PACRK_SP4_MASK                      (0x4000U)
+#define AIPS_PACRK_SP4_SHIFT                     (14U)
+#define AIPS_PACRK_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
+#define AIPS_PACRK_TP3_MASK                      (0x10000U)
+#define AIPS_PACRK_TP3_SHIFT                     (16U)
+#define AIPS_PACRK_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
+#define AIPS_PACRK_WP3_MASK                      (0x20000U)
+#define AIPS_PACRK_WP3_SHIFT                     (17U)
+#define AIPS_PACRK_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
+#define AIPS_PACRK_SP3_MASK                      (0x40000U)
+#define AIPS_PACRK_SP3_SHIFT                     (18U)
+#define AIPS_PACRK_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
+#define AIPS_PACRK_TP2_MASK                      (0x100000U)
+#define AIPS_PACRK_TP2_SHIFT                     (20U)
+#define AIPS_PACRK_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
+#define AIPS_PACRK_WP2_MASK                      (0x200000U)
+#define AIPS_PACRK_WP2_SHIFT                     (21U)
+#define AIPS_PACRK_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
+#define AIPS_PACRK_SP2_MASK                      (0x400000U)
+#define AIPS_PACRK_SP2_SHIFT                     (22U)
+#define AIPS_PACRK_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
+#define AIPS_PACRK_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRK_TP1_SHIFT                     (24U)
+#define AIPS_PACRK_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
+#define AIPS_PACRK_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRK_WP1_SHIFT                     (25U)
+#define AIPS_PACRK_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
+#define AIPS_PACRK_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRK_SP1_SHIFT                     (26U)
+#define AIPS_PACRK_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
+#define AIPS_PACRK_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRK_TP0_SHIFT                     (28U)
+#define AIPS_PACRK_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
+#define AIPS_PACRK_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRK_WP0_SHIFT                     (29U)
+#define AIPS_PACRK_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
+#define AIPS_PACRK_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRK_SP0_SHIFT                     (30U)
+#define AIPS_PACRK_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
+
+/*! @name PACRL - Peripheral Access Control Register */
+#define AIPS_PACRL_TP7_MASK                      (0x1U)
+#define AIPS_PACRL_TP7_SHIFT                     (0U)
+#define AIPS_PACRL_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
+#define AIPS_PACRL_WP7_MASK                      (0x2U)
+#define AIPS_PACRL_WP7_SHIFT                     (1U)
+#define AIPS_PACRL_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
+#define AIPS_PACRL_SP7_MASK                      (0x4U)
+#define AIPS_PACRL_SP7_SHIFT                     (2U)
+#define AIPS_PACRL_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
+#define AIPS_PACRL_TP6_MASK                      (0x10U)
+#define AIPS_PACRL_TP6_SHIFT                     (4U)
+#define AIPS_PACRL_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
+#define AIPS_PACRL_WP6_MASK                      (0x20U)
+#define AIPS_PACRL_WP6_SHIFT                     (5U)
+#define AIPS_PACRL_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
+#define AIPS_PACRL_SP6_MASK                      (0x40U)
+#define AIPS_PACRL_SP6_SHIFT                     (6U)
+#define AIPS_PACRL_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
+#define AIPS_PACRL_TP5_MASK                      (0x100U)
+#define AIPS_PACRL_TP5_SHIFT                     (8U)
+#define AIPS_PACRL_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
+#define AIPS_PACRL_WP5_MASK                      (0x200U)
+#define AIPS_PACRL_WP5_SHIFT                     (9U)
+#define AIPS_PACRL_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
+#define AIPS_PACRL_SP5_MASK                      (0x400U)
+#define AIPS_PACRL_SP5_SHIFT                     (10U)
+#define AIPS_PACRL_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
+#define AIPS_PACRL_TP4_MASK                      (0x1000U)
+#define AIPS_PACRL_TP4_SHIFT                     (12U)
+#define AIPS_PACRL_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
+#define AIPS_PACRL_WP4_MASK                      (0x2000U)
+#define AIPS_PACRL_WP4_SHIFT                     (13U)
+#define AIPS_PACRL_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
+#define AIPS_PACRL_SP4_MASK                      (0x4000U)
+#define AIPS_PACRL_SP4_SHIFT                     (14U)
+#define AIPS_PACRL_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
+#define AIPS_PACRL_TP3_MASK                      (0x10000U)
+#define AIPS_PACRL_TP3_SHIFT                     (16U)
+#define AIPS_PACRL_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
+#define AIPS_PACRL_WP3_MASK                      (0x20000U)
+#define AIPS_PACRL_WP3_SHIFT                     (17U)
+#define AIPS_PACRL_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
+#define AIPS_PACRL_SP3_MASK                      (0x40000U)
+#define AIPS_PACRL_SP3_SHIFT                     (18U)
+#define AIPS_PACRL_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
+#define AIPS_PACRL_TP2_MASK                      (0x100000U)
+#define AIPS_PACRL_TP2_SHIFT                     (20U)
+#define AIPS_PACRL_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
+#define AIPS_PACRL_WP2_MASK                      (0x200000U)
+#define AIPS_PACRL_WP2_SHIFT                     (21U)
+#define AIPS_PACRL_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
+#define AIPS_PACRL_SP2_MASK                      (0x400000U)
+#define AIPS_PACRL_SP2_SHIFT                     (22U)
+#define AIPS_PACRL_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
+#define AIPS_PACRL_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRL_TP1_SHIFT                     (24U)
+#define AIPS_PACRL_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
+#define AIPS_PACRL_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRL_WP1_SHIFT                     (25U)
+#define AIPS_PACRL_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
+#define AIPS_PACRL_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRL_SP1_SHIFT                     (26U)
+#define AIPS_PACRL_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
+#define AIPS_PACRL_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRL_TP0_SHIFT                     (28U)
+#define AIPS_PACRL_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
+#define AIPS_PACRL_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRL_WP0_SHIFT                     (29U)
+#define AIPS_PACRL_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
+#define AIPS_PACRL_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRL_SP0_SHIFT                     (30U)
+#define AIPS_PACRL_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
+
+/*! @name PACRM - Peripheral Access Control Register */
+#define AIPS_PACRM_TP7_MASK                      (0x1U)
+#define AIPS_PACRM_TP7_SHIFT                     (0U)
+#define AIPS_PACRM_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
+#define AIPS_PACRM_WP7_MASK                      (0x2U)
+#define AIPS_PACRM_WP7_SHIFT                     (1U)
+#define AIPS_PACRM_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
+#define AIPS_PACRM_SP7_MASK                      (0x4U)
+#define AIPS_PACRM_SP7_SHIFT                     (2U)
+#define AIPS_PACRM_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
+#define AIPS_PACRM_TP6_MASK                      (0x10U)
+#define AIPS_PACRM_TP6_SHIFT                     (4U)
+#define AIPS_PACRM_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
+#define AIPS_PACRM_WP6_MASK                      (0x20U)
+#define AIPS_PACRM_WP6_SHIFT                     (5U)
+#define AIPS_PACRM_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
+#define AIPS_PACRM_SP6_MASK                      (0x40U)
+#define AIPS_PACRM_SP6_SHIFT                     (6U)
+#define AIPS_PACRM_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
+#define AIPS_PACRM_TP5_MASK                      (0x100U)
+#define AIPS_PACRM_TP5_SHIFT                     (8U)
+#define AIPS_PACRM_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
+#define AIPS_PACRM_WP5_MASK                      (0x200U)
+#define AIPS_PACRM_WP5_SHIFT                     (9U)
+#define AIPS_PACRM_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
+#define AIPS_PACRM_SP5_MASK                      (0x400U)
+#define AIPS_PACRM_SP5_SHIFT                     (10U)
+#define AIPS_PACRM_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
+#define AIPS_PACRM_TP4_MASK                      (0x1000U)
+#define AIPS_PACRM_TP4_SHIFT                     (12U)
+#define AIPS_PACRM_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
+#define AIPS_PACRM_WP4_MASK                      (0x2000U)
+#define AIPS_PACRM_WP4_SHIFT                     (13U)
+#define AIPS_PACRM_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
+#define AIPS_PACRM_SP4_MASK                      (0x4000U)
+#define AIPS_PACRM_SP4_SHIFT                     (14U)
+#define AIPS_PACRM_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
+#define AIPS_PACRM_TP3_MASK                      (0x10000U)
+#define AIPS_PACRM_TP3_SHIFT                     (16U)
+#define AIPS_PACRM_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
+#define AIPS_PACRM_WP3_MASK                      (0x20000U)
+#define AIPS_PACRM_WP3_SHIFT                     (17U)
+#define AIPS_PACRM_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
+#define AIPS_PACRM_SP3_MASK                      (0x40000U)
+#define AIPS_PACRM_SP3_SHIFT                     (18U)
+#define AIPS_PACRM_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
+#define AIPS_PACRM_TP2_MASK                      (0x100000U)
+#define AIPS_PACRM_TP2_SHIFT                     (20U)
+#define AIPS_PACRM_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
+#define AIPS_PACRM_WP2_MASK                      (0x200000U)
+#define AIPS_PACRM_WP2_SHIFT                     (21U)
+#define AIPS_PACRM_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
+#define AIPS_PACRM_SP2_MASK                      (0x400000U)
+#define AIPS_PACRM_SP2_SHIFT                     (22U)
+#define AIPS_PACRM_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
+#define AIPS_PACRM_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRM_TP1_SHIFT                     (24U)
+#define AIPS_PACRM_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
+#define AIPS_PACRM_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRM_WP1_SHIFT                     (25U)
+#define AIPS_PACRM_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
+#define AIPS_PACRM_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRM_SP1_SHIFT                     (26U)
+#define AIPS_PACRM_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
+#define AIPS_PACRM_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRM_TP0_SHIFT                     (28U)
+#define AIPS_PACRM_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
+#define AIPS_PACRM_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRM_WP0_SHIFT                     (29U)
+#define AIPS_PACRM_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
+#define AIPS_PACRM_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRM_SP0_SHIFT                     (30U)
+#define AIPS_PACRM_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
+
+/*! @name PACRN - Peripheral Access Control Register */
+#define AIPS_PACRN_TP7_MASK                      (0x1U)
+#define AIPS_PACRN_TP7_SHIFT                     (0U)
+#define AIPS_PACRN_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
+#define AIPS_PACRN_WP7_MASK                      (0x2U)
+#define AIPS_PACRN_WP7_SHIFT                     (1U)
+#define AIPS_PACRN_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
+#define AIPS_PACRN_SP7_MASK                      (0x4U)
+#define AIPS_PACRN_SP7_SHIFT                     (2U)
+#define AIPS_PACRN_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
+#define AIPS_PACRN_TP6_MASK                      (0x10U)
+#define AIPS_PACRN_TP6_SHIFT                     (4U)
+#define AIPS_PACRN_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
+#define AIPS_PACRN_WP6_MASK                      (0x20U)
+#define AIPS_PACRN_WP6_SHIFT                     (5U)
+#define AIPS_PACRN_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
+#define AIPS_PACRN_SP6_MASK                      (0x40U)
+#define AIPS_PACRN_SP6_SHIFT                     (6U)
+#define AIPS_PACRN_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
+#define AIPS_PACRN_TP5_MASK                      (0x100U)
+#define AIPS_PACRN_TP5_SHIFT                     (8U)
+#define AIPS_PACRN_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
+#define AIPS_PACRN_WP5_MASK                      (0x200U)
+#define AIPS_PACRN_WP5_SHIFT                     (9U)
+#define AIPS_PACRN_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
+#define AIPS_PACRN_SP5_MASK                      (0x400U)
+#define AIPS_PACRN_SP5_SHIFT                     (10U)
+#define AIPS_PACRN_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
+#define AIPS_PACRN_TP4_MASK                      (0x1000U)
+#define AIPS_PACRN_TP4_SHIFT                     (12U)
+#define AIPS_PACRN_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
+#define AIPS_PACRN_WP4_MASK                      (0x2000U)
+#define AIPS_PACRN_WP4_SHIFT                     (13U)
+#define AIPS_PACRN_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
+#define AIPS_PACRN_SP4_MASK                      (0x4000U)
+#define AIPS_PACRN_SP4_SHIFT                     (14U)
+#define AIPS_PACRN_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
+#define AIPS_PACRN_TP3_MASK                      (0x10000U)
+#define AIPS_PACRN_TP3_SHIFT                     (16U)
+#define AIPS_PACRN_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
+#define AIPS_PACRN_WP3_MASK                      (0x20000U)
+#define AIPS_PACRN_WP3_SHIFT                     (17U)
+#define AIPS_PACRN_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
+#define AIPS_PACRN_SP3_MASK                      (0x40000U)
+#define AIPS_PACRN_SP3_SHIFT                     (18U)
+#define AIPS_PACRN_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
+#define AIPS_PACRN_TP2_MASK                      (0x100000U)
+#define AIPS_PACRN_TP2_SHIFT                     (20U)
+#define AIPS_PACRN_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
+#define AIPS_PACRN_WP2_MASK                      (0x200000U)
+#define AIPS_PACRN_WP2_SHIFT                     (21U)
+#define AIPS_PACRN_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
+#define AIPS_PACRN_SP2_MASK                      (0x400000U)
+#define AIPS_PACRN_SP2_SHIFT                     (22U)
+#define AIPS_PACRN_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
+#define AIPS_PACRN_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRN_TP1_SHIFT                     (24U)
+#define AIPS_PACRN_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
+#define AIPS_PACRN_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRN_WP1_SHIFT                     (25U)
+#define AIPS_PACRN_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
+#define AIPS_PACRN_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRN_SP1_SHIFT                     (26U)
+#define AIPS_PACRN_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
+#define AIPS_PACRN_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRN_TP0_SHIFT                     (28U)
+#define AIPS_PACRN_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
+#define AIPS_PACRN_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRN_WP0_SHIFT                     (29U)
+#define AIPS_PACRN_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
+#define AIPS_PACRN_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRN_SP0_SHIFT                     (30U)
+#define AIPS_PACRN_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
+
+/*! @name PACRO - Peripheral Access Control Register */
+#define AIPS_PACRO_TP7_MASK                      (0x1U)
+#define AIPS_PACRO_TP7_SHIFT                     (0U)
+#define AIPS_PACRO_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
+#define AIPS_PACRO_WP7_MASK                      (0x2U)
+#define AIPS_PACRO_WP7_SHIFT                     (1U)
+#define AIPS_PACRO_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
+#define AIPS_PACRO_SP7_MASK                      (0x4U)
+#define AIPS_PACRO_SP7_SHIFT                     (2U)
+#define AIPS_PACRO_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
+#define AIPS_PACRO_TP6_MASK                      (0x10U)
+#define AIPS_PACRO_TP6_SHIFT                     (4U)
+#define AIPS_PACRO_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
+#define AIPS_PACRO_WP6_MASK                      (0x20U)
+#define AIPS_PACRO_WP6_SHIFT                     (5U)
+#define AIPS_PACRO_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
+#define AIPS_PACRO_SP6_MASK                      (0x40U)
+#define AIPS_PACRO_SP6_SHIFT                     (6U)
+#define AIPS_PACRO_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
+#define AIPS_PACRO_TP5_MASK                      (0x100U)
+#define AIPS_PACRO_TP5_SHIFT                     (8U)
+#define AIPS_PACRO_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
+#define AIPS_PACRO_WP5_MASK                      (0x200U)
+#define AIPS_PACRO_WP5_SHIFT                     (9U)
+#define AIPS_PACRO_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
+#define AIPS_PACRO_SP5_MASK                      (0x400U)
+#define AIPS_PACRO_SP5_SHIFT                     (10U)
+#define AIPS_PACRO_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
+#define AIPS_PACRO_TP4_MASK                      (0x1000U)
+#define AIPS_PACRO_TP4_SHIFT                     (12U)
+#define AIPS_PACRO_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
+#define AIPS_PACRO_WP4_MASK                      (0x2000U)
+#define AIPS_PACRO_WP4_SHIFT                     (13U)
+#define AIPS_PACRO_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
+#define AIPS_PACRO_SP4_MASK                      (0x4000U)
+#define AIPS_PACRO_SP4_SHIFT                     (14U)
+#define AIPS_PACRO_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
+#define AIPS_PACRO_TP3_MASK                      (0x10000U)
+#define AIPS_PACRO_TP3_SHIFT                     (16U)
+#define AIPS_PACRO_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
+#define AIPS_PACRO_WP3_MASK                      (0x20000U)
+#define AIPS_PACRO_WP3_SHIFT                     (17U)
+#define AIPS_PACRO_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
+#define AIPS_PACRO_SP3_MASK                      (0x40000U)
+#define AIPS_PACRO_SP3_SHIFT                     (18U)
+#define AIPS_PACRO_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
+#define AIPS_PACRO_TP2_MASK                      (0x100000U)
+#define AIPS_PACRO_TP2_SHIFT                     (20U)
+#define AIPS_PACRO_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
+#define AIPS_PACRO_WP2_MASK                      (0x200000U)
+#define AIPS_PACRO_WP2_SHIFT                     (21U)
+#define AIPS_PACRO_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
+#define AIPS_PACRO_SP2_MASK                      (0x400000U)
+#define AIPS_PACRO_SP2_SHIFT                     (22U)
+#define AIPS_PACRO_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
+#define AIPS_PACRO_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRO_TP1_SHIFT                     (24U)
+#define AIPS_PACRO_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
+#define AIPS_PACRO_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRO_WP1_SHIFT                     (25U)
+#define AIPS_PACRO_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
+#define AIPS_PACRO_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRO_SP1_SHIFT                     (26U)
+#define AIPS_PACRO_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
+#define AIPS_PACRO_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRO_TP0_SHIFT                     (28U)
+#define AIPS_PACRO_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
+#define AIPS_PACRO_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRO_WP0_SHIFT                     (29U)
+#define AIPS_PACRO_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
+#define AIPS_PACRO_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRO_SP0_SHIFT                     (30U)
+#define AIPS_PACRO_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
+
+/*! @name PACRP - Peripheral Access Control Register */
+#define AIPS_PACRP_TP7_MASK                      (0x1U)
+#define AIPS_PACRP_TP7_SHIFT                     (0U)
+#define AIPS_PACRP_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
+#define AIPS_PACRP_WP7_MASK                      (0x2U)
+#define AIPS_PACRP_WP7_SHIFT                     (1U)
+#define AIPS_PACRP_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
+#define AIPS_PACRP_SP7_MASK                      (0x4U)
+#define AIPS_PACRP_SP7_SHIFT                     (2U)
+#define AIPS_PACRP_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
+#define AIPS_PACRP_TP6_MASK                      (0x10U)
+#define AIPS_PACRP_TP6_SHIFT                     (4U)
+#define AIPS_PACRP_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
+#define AIPS_PACRP_WP6_MASK                      (0x20U)
+#define AIPS_PACRP_WP6_SHIFT                     (5U)
+#define AIPS_PACRP_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
+#define AIPS_PACRP_SP6_MASK                      (0x40U)
+#define AIPS_PACRP_SP6_SHIFT                     (6U)
+#define AIPS_PACRP_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
+#define AIPS_PACRP_TP5_MASK                      (0x100U)
+#define AIPS_PACRP_TP5_SHIFT                     (8U)
+#define AIPS_PACRP_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
+#define AIPS_PACRP_WP5_MASK                      (0x200U)
+#define AIPS_PACRP_WP5_SHIFT                     (9U)
+#define AIPS_PACRP_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
+#define AIPS_PACRP_SP5_MASK                      (0x400U)
+#define AIPS_PACRP_SP5_SHIFT                     (10U)
+#define AIPS_PACRP_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
+#define AIPS_PACRP_TP4_MASK                      (0x1000U)
+#define AIPS_PACRP_TP4_SHIFT                     (12U)
+#define AIPS_PACRP_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
+#define AIPS_PACRP_WP4_MASK                      (0x2000U)
+#define AIPS_PACRP_WP4_SHIFT                     (13U)
+#define AIPS_PACRP_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
+#define AIPS_PACRP_SP4_MASK                      (0x4000U)
+#define AIPS_PACRP_SP4_SHIFT                     (14U)
+#define AIPS_PACRP_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
+#define AIPS_PACRP_TP3_MASK                      (0x10000U)
+#define AIPS_PACRP_TP3_SHIFT                     (16U)
+#define AIPS_PACRP_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
+#define AIPS_PACRP_WP3_MASK                      (0x20000U)
+#define AIPS_PACRP_WP3_SHIFT                     (17U)
+#define AIPS_PACRP_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
+#define AIPS_PACRP_SP3_MASK                      (0x40000U)
+#define AIPS_PACRP_SP3_SHIFT                     (18U)
+#define AIPS_PACRP_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
+#define AIPS_PACRP_TP2_MASK                      (0x100000U)
+#define AIPS_PACRP_TP2_SHIFT                     (20U)
+#define AIPS_PACRP_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
+#define AIPS_PACRP_WP2_MASK                      (0x200000U)
+#define AIPS_PACRP_WP2_SHIFT                     (21U)
+#define AIPS_PACRP_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
+#define AIPS_PACRP_SP2_MASK                      (0x400000U)
+#define AIPS_PACRP_SP2_SHIFT                     (22U)
+#define AIPS_PACRP_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
+#define AIPS_PACRP_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRP_TP1_SHIFT                     (24U)
+#define AIPS_PACRP_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
+#define AIPS_PACRP_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRP_WP1_SHIFT                     (25U)
+#define AIPS_PACRP_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
+#define AIPS_PACRP_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRP_SP1_SHIFT                     (26U)
+#define AIPS_PACRP_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
+#define AIPS_PACRP_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRP_TP0_SHIFT                     (28U)
+#define AIPS_PACRP_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
+#define AIPS_PACRP_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRP_WP0_SHIFT                     (29U)
+#define AIPS_PACRP_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
+#define AIPS_PACRP_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRP_SP0_SHIFT                     (30U)
+#define AIPS_PACRP_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS base address */
+#define AIPS_BASE                                (0x40000000u)
+/** Peripheral AIPS base pointer */
+#define AIPS                                     ((AIPS_Type *)AIPS_BASE)
+/** Array initializer of AIPS peripheral base addresses */
+#define AIPS_BASE_ADDRS                          { AIPS_BASE }
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASE_PTRS                           { AIPS }
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/*! @name CR0 - CMP Control Register 0 */
+#define CMP_CR0_HYSTCTR_MASK                     (0x3U)
+#define CMP_CR0_HYSTCTR_SHIFT                    (0U)
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  (0x70U)
+#define CMP_CR0_FILTER_CNT_SHIFT                 (4U)
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+
+/*! @name CR1 - CMP Control Register 1 */
+#define CMP_CR1_EN_MASK                          (0x1U)
+#define CMP_CR1_EN_SHIFT                         (0U)
+#define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK                         (0x2U)
+#define CMP_CR1_OPE_SHIFT                        (1U)
+#define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK                         (0x4U)
+#define CMP_CR1_COS_SHIFT                        (2U)
+#define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK                         (0x8U)
+#define CMP_CR1_INV_SHIFT                        (3U)
+#define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK                       (0x10U)
+#define CMP_CR1_PMODE_SHIFT                      (4U)
+#define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+#define CMP_CR1_TRIGM_MASK                       (0x20U)
+#define CMP_CR1_TRIGM_SHIFT                      (5U)
+#define CMP_CR1_TRIGM(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
+#define CMP_CR1_WE_MASK                          (0x40U)
+#define CMP_CR1_WE_SHIFT                         (6U)
+#define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK                          (0x80U)
+#define CMP_CR1_SE_SHIFT                         (7U)
+#define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+
+/*! @name FPR - CMP Filter Period Register */
+#define CMP_FPR_FILT_PER_MASK                    (0xFFU)
+#define CMP_FPR_FILT_PER_SHIFT                   (0U)
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+
+/*! @name SCR - CMP Status and Control Register */
+#define CMP_SCR_COUT_MASK                        (0x1U)
+#define CMP_SCR_COUT_SHIFT                       (0U)
+#define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK                         (0x2U)
+#define CMP_SCR_CFF_SHIFT                        (1U)
+#define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK                         (0x4U)
+#define CMP_SCR_CFR_SHIFT                        (2U)
+#define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK                         (0x8U)
+#define CMP_SCR_IEF_SHIFT                        (3U)
+#define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK                         (0x10U)
+#define CMP_SCR_IER_SHIFT                        (4U)
+#define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK                       (0x40U)
+#define CMP_SCR_DMAEN_SHIFT                      (6U)
+#define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+
+/*! @name DACCR - DAC Control Register */
+#define CMP_DACCR_VOSEL_MASK                     (0x3FU)
+#define CMP_DACCR_VOSEL_SHIFT                    (0U)
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK                     (0x40U)
+#define CMP_DACCR_VRSEL_SHIFT                    (6U)
+#define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK                     (0x80U)
+#define CMP_DACCR_DACEN_SHIFT                    (7U)
+#define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+
+/*! @name MUXCR - MUX Control Register */
+#define CMP_MUXCR_MSEL_MASK                      (0x7U)
+#define CMP_MUXCR_MSEL_SHIFT                     (0U)
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      (0x38U)
+#define CMP_MUXCR_PSEL_SHIFT                     (3U)
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS                           { CMP0_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS                            { CMP0 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t CRCL;                              /**< CRC_CRCL register., offset: 0x0 */
+      __IO uint16_t CRCH;                              /**< CRC_CRCH register., offset: 0x2 */
+    } ACCESS16BIT;
+    __IO uint32_t CRC;                               /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t CRCLL;                              /**< CRC_CRCLL register., offset: 0x0 */
+      __IO uint8_t CRCLU;                              /**< CRC_CRCLU register., offset: 0x1 */
+      __IO uint8_t CRCHL;                              /**< CRC_CRCHL register., offset: 0x2 */
+      __IO uint8_t CRCHU;                              /**< CRC_CRCHU register., offset: 0x3 */
+    } ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name CRCL - CRC_CRCL register. */
+#define CRC_CRCL_CRCL_MASK                       (0xFFFFU)
+#define CRC_CRCL_CRCL_SHIFT                      (0U)
+#define CRC_CRCL_CRCL(x)                         (((uint16_t)(((uint16_t)(x)) << CRC_CRCL_CRCL_SHIFT)) & CRC_CRCL_CRCL_MASK)
+
+/*! @name CRCH - CRC_CRCH register. */
+#define CRC_CRCH_CRCH_MASK                       (0xFFFFU)
+#define CRC_CRCH_CRCH_SHIFT                      (0U)
+#define CRC_CRCH_CRCH(x)                         (((uint16_t)(((uint16_t)(x)) << CRC_CRCH_CRCH_SHIFT)) & CRC_CRCH_CRCH_MASK)
+
+/*! @name CRC - CRC Data register */
+#define CRC_CRC_LL_MASK                          (0xFFU)
+#define CRC_CRC_LL_SHIFT                         (0U)
+#define CRC_CRC_LL(x)                            (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LL_SHIFT)) & CRC_CRC_LL_MASK)
+#define CRC_CRC_LU_MASK                          (0xFF00U)
+#define CRC_CRC_LU_SHIFT                         (8U)
+#define CRC_CRC_LU(x)                            (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LU_SHIFT)) & CRC_CRC_LU_MASK)
+#define CRC_CRC_HL_MASK                          (0xFF0000U)
+#define CRC_CRC_HL_SHIFT                         (16U)
+#define CRC_CRC_HL(x)                            (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HL_SHIFT)) & CRC_CRC_HL_MASK)
+#define CRC_CRC_HU_MASK                          (0xFF000000U)
+#define CRC_CRC_HU_SHIFT                         (24U)
+#define CRC_CRC_HU(x)                            (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HU_SHIFT)) & CRC_CRC_HU_MASK)
+
+/*! @name CRCLL - CRC_CRCLL register. */
+#define CRC_CRCLL_CRCLL_MASK                     (0xFFU)
+#define CRC_CRCLL_CRCLL_SHIFT                    (0U)
+#define CRC_CRCLL_CRCLL(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CRCLL_CRCLL_SHIFT)) & CRC_CRCLL_CRCLL_MASK)
+
+/*! @name CRCLU - CRC_CRCLU register. */
+#define CRC_CRCLU_CRCLU_MASK                     (0xFFU)
+#define CRC_CRCLU_CRCLU_SHIFT                    (0U)
+#define CRC_CRCLU_CRCLU(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CRCLU_CRCLU_SHIFT)) & CRC_CRCLU_CRCLU_MASK)
+
+/*! @name CRCHL - CRC_CRCHL register. */
+#define CRC_CRCHL_CRCHL_MASK                     (0xFFU)
+#define CRC_CRCHL_CRCHL_SHIFT                    (0U)
+#define CRC_CRCHL_CRCHL(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CRCHL_CRCHL_SHIFT)) & CRC_CRCHL_CRCHL_MASK)
+
+/*! @name CRCHU - CRC_CRCHU register. */
+#define CRC_CRCHU_CRCHU_MASK                     (0xFFU)
+#define CRC_CRCHU_CRCHU_SHIFT                    (0U)
+#define CRC_CRCHU_CRCHU(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CRCHU_CRCHU_SHIFT)) & CRC_CRCHU_CRCHU_MASK)
+
+/*! @name GPOLYL - CRC_GPOLYL register. */
+#define CRC_GPOLYL_GPOLYL_MASK                   (0xFFFFU)
+#define CRC_GPOLYL_GPOLYL_SHIFT                  (0U)
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+
+/*! @name GPOLYH - CRC_GPOLYH register. */
+#define CRC_GPOLYH_GPOLYH_MASK                   (0xFFFFU)
+#define CRC_GPOLYH_GPOLYH_SHIFT                  (0U)
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+
+/*! @name GPOLY - CRC Polynomial register */
+#define CRC_GPOLY_LOW_MASK                       (0xFFFFU)
+#define CRC_GPOLY_LOW_SHIFT                      (0U)
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      (0xFFFF0000U)
+#define CRC_GPOLY_HIGH_SHIFT                     (16U)
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+
+/*! @name GPOLYLL - CRC_GPOLYLL register. */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 (0xFFU)
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                (0U)
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+
+/*! @name GPOLYLU - CRC_GPOLYLU register. */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 (0xFFU)
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                (0U)
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+
+/*! @name GPOLYHL - CRC_GPOLYHL register. */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 (0xFFU)
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                (0U)
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+
+/*! @name GPOLYHU - CRC_GPOLYHU register. */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 (0xFFU)
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                (0U)
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+
+/*! @name CTRL - CRC Control register */
+#define CRC_CTRL_TCRC_MASK                       (0x1000000U)
+#define CRC_CTRL_TCRC_SHIFT                      (24U)
+#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK                        (0x2000000U)
+#define CRC_CTRL_WAS_SHIFT                       (25U)
+#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK                       (0x4000000U)
+#define CRC_CTRL_FXOR_SHIFT                      (26U)
+#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK                       (0x30000000U)
+#define CRC_CTRL_TOTR_SHIFT                      (28U)
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        (0xC0000000U)
+#define CRC_CTRL_TOT_SHIFT                       (30U)
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+
+/*! @name CTRLHU - CRC_CTRLHU register. */
+#define CRC_CTRLHU_TCRC_MASK                     (0x1U)
+#define CRC_CTRLHU_TCRC_SHIFT                    (0U)
+#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK                      (0x2U)
+#define CRC_CTRLHU_WAS_SHIFT                     (1U)
+#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK                     (0x4U)
+#define CRC_CTRLHU_FXOR_SHIFT                    (2U)
+#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK                     (0x30U)
+#define CRC_CTRLHU_TOTR_SHIFT                    (4U)
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      (0xC0U)
+#define CRC_CTRLHU_TOT_SHIFT                     (6U)
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_Type *)CRC_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC0 }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[16];
+  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/*! @name DATL - DAC Data Low Register */
+#define DAC_DATL_DATA0_MASK                      (0xFFU)
+#define DAC_DATL_DATA0_SHIFT                     (0U)
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
+
+/* The count of DAC_DATL */
+#define DAC_DATL_COUNT                           (16U)
+
+/*! @name DATH - DAC Data High Register */
+#define DAC_DATH_DATA1_MASK                      (0xFU)
+#define DAC_DATH_DATA1_SHIFT                     (0U)
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
+
+/* The count of DAC_DATH */
+#define DAC_DATH_COUNT                           (16U)
+
+/*! @name SR - DAC Status Register */
+#define DAC_SR_DACBFRPBF_MASK                    (0x1U)
+#define DAC_SR_DACBFRPBF_SHIFT                   (0U)
+#define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK                    (0x2U)
+#define DAC_SR_DACBFRPTF_SHIFT                   (1U)
+#define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFWMF_MASK                     (0x4U)
+#define DAC_SR_DACBFWMF_SHIFT                    (2U)
+#define DAC_SR_DACBFWMF(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
+
+/*! @name C0 - DAC Control Register */
+#define DAC_C0_DACBBIEN_MASK                     (0x1U)
+#define DAC_C0_DACBBIEN_SHIFT                    (0U)
+#define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK                     (0x2U)
+#define DAC_C0_DACBTIEN_SHIFT                    (1U)
+#define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBWIEN_MASK                     (0x4U)
+#define DAC_C0_DACBWIEN_SHIFT                    (2U)
+#define DAC_C0_DACBWIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_LPEN_MASK                         (0x8U)
+#define DAC_C0_LPEN_SHIFT                        (3U)
+#define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK                     (0x10U)
+#define DAC_C0_DACSWTRG_SHIFT                    (4U)
+#define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK                    (0x20U)
+#define DAC_C0_DACTRGSEL_SHIFT                   (5U)
+#define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK                       (0x40U)
+#define DAC_C0_DACRFS_SHIFT                      (6U)
+#define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK                        (0x80U)
+#define DAC_C0_DACEN_SHIFT                       (7U)
+#define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
+
+/*! @name C1 - DAC Control Register 1 */
+#define DAC_C1_DACBFEN_MASK                      (0x1U)
+#define DAC_C1_DACBFEN_SHIFT                     (0U)
+#define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK                      (0x6U)
+#define DAC_C1_DACBFMD_SHIFT                     (1U)
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK                      (0x18U)
+#define DAC_C1_DACBFWM_SHIFT                     (3U)
+#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK                        (0x80U)
+#define DAC_C1_DMAEN_SHIFT                       (7U)
+#define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
+
+/*! @name C2 - DAC Control Register 2 */
+#define DAC_C2_DACBFUP_MASK                      (0xFU)
+#define DAC_C2_DACBFUP_SHIFT                     (0U)
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK                      (0xF0U)
+#define DAC_C2_DACBFRP_SHIFT                     (4U)
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS                           { DAC0_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS                            { DAC0 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+  __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
+  __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+  __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
+  __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
+  __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
+  __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
+  __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
+  __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
+  __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
+       uint8_t RESERVED_4[4];
+  __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
+       uint8_t RESERVED_5[12];
+  __IO uint32_t EARS;                              /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
+       uint8_t RESERVED_6[184];
+  __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
+  __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
+  __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
+  __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
+  __IO uint8_t DCHPRI7;                            /**< Channel n Priority Register, offset: 0x104 */
+  __IO uint8_t DCHPRI6;                            /**< Channel n Priority Register, offset: 0x105 */
+  __IO uint8_t DCHPRI5;                            /**< Channel n Priority Register, offset: 0x106 */
+  __IO uint8_t DCHPRI4;                            /**< Channel n Priority Register, offset: 0x107 */
+       uint8_t RESERVED_7[3832];
+  struct {                                         /* offset: 0x1000, array step: 0x20 */
+    __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+    __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+    __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+    union {                                          /* offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+    };
+    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+    __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+    union {                                          /* offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+    };
+    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+    union {                                          /* offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+    };
+  } TCD[8];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CR - Control Register */
+#define DMA_CR_EDBG_MASK                         (0x2U)
+#define DMA_CR_EDBG_SHIFT                        (1U)
+#define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK                         (0x4U)
+#define DMA_CR_ERCA_SHIFT                        (2U)
+#define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK                          (0x10U)
+#define DMA_CR_HOE_SHIFT                         (4U)
+#define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK                         (0x20U)
+#define DMA_CR_HALT_SHIFT                        (5U)
+#define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK                          (0x40U)
+#define DMA_CR_CLM_SHIFT                         (6U)
+#define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK                         (0x80U)
+#define DMA_CR_EMLM_SHIFT                        (7U)
+#define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK                          (0x10000U)
+#define DMA_CR_ECX_SHIFT                         (16U)
+#define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK                           (0x20000U)
+#define DMA_CR_CX_SHIFT                          (17U)
+#define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
+#define DMA_CR_ACTIVE_MASK                       (0x80000000U)
+#define DMA_CR_ACTIVE_SHIFT                      (31U)
+#define DMA_CR_ACTIVE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
+
+/*! @name ES - Error Status Register */
+#define DMA_ES_DBE_MASK                          (0x1U)
+#define DMA_ES_DBE_SHIFT                         (0U)
+#define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK                          (0x2U)
+#define DMA_ES_SBE_SHIFT                         (1U)
+#define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK                          (0x4U)
+#define DMA_ES_SGE_SHIFT                         (2U)
+#define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK                          (0x8U)
+#define DMA_ES_NCE_SHIFT                         (3U)
+#define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK                          (0x10U)
+#define DMA_ES_DOE_SHIFT                         (4U)
+#define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK                          (0x20U)
+#define DMA_ES_DAE_SHIFT                         (5U)
+#define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK                          (0x40U)
+#define DMA_ES_SOE_SHIFT                         (6U)
+#define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK                          (0x80U)
+#define DMA_ES_SAE_SHIFT                         (7U)
+#define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK                       (0x700U)
+#define DMA_ES_ERRCHN_SHIFT                      (8U)
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK                          (0x4000U)
+#define DMA_ES_CPE_SHIFT                         (14U)
+#define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK                          (0x10000U)
+#define DMA_ES_ECX_SHIFT                         (16U)
+#define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK                          (0x80000000U)
+#define DMA_ES_VLD_SHIFT                         (31U)
+#define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
+
+/*! @name ERQ - Enable Request Register */
+#define DMA_ERQ_ERQ0_MASK                        (0x1U)
+#define DMA_ERQ_ERQ0_SHIFT                       (0U)
+#define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK                        (0x2U)
+#define DMA_ERQ_ERQ1_SHIFT                       (1U)
+#define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK                        (0x4U)
+#define DMA_ERQ_ERQ2_SHIFT                       (2U)
+#define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK                        (0x8U)
+#define DMA_ERQ_ERQ3_SHIFT                       (3U)
+#define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK                        (0x10U)
+#define DMA_ERQ_ERQ4_SHIFT                       (4U)
+#define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK                        (0x20U)
+#define DMA_ERQ_ERQ5_SHIFT                       (5U)
+#define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK                        (0x40U)
+#define DMA_ERQ_ERQ6_SHIFT                       (6U)
+#define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK                        (0x80U)
+#define DMA_ERQ_ERQ7_SHIFT                       (7U)
+#define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
+
+/*! @name EEI - Enable Error Interrupt Register */
+#define DMA_EEI_EEI0_MASK                        (0x1U)
+#define DMA_EEI_EEI0_SHIFT                       (0U)
+#define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK                        (0x2U)
+#define DMA_EEI_EEI1_SHIFT                       (1U)
+#define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK                        (0x4U)
+#define DMA_EEI_EEI2_SHIFT                       (2U)
+#define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK                        (0x8U)
+#define DMA_EEI_EEI3_SHIFT                       (3U)
+#define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK                        (0x10U)
+#define DMA_EEI_EEI4_SHIFT                       (4U)
+#define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK                        (0x20U)
+#define DMA_EEI_EEI5_SHIFT                       (5U)
+#define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK                        (0x40U)
+#define DMA_EEI_EEI6_SHIFT                       (6U)
+#define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK                        (0x80U)
+#define DMA_EEI_EEI7_SHIFT                       (7U)
+#define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
+
+/*! @name CEEI - Clear Enable Error Interrupt Register */
+#define DMA_CEEI_CEEI_MASK                       (0x7U)
+#define DMA_CEEI_CEEI_SHIFT                      (0U)
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK                       (0x40U)
+#define DMA_CEEI_CAEE_SHIFT                      (6U)
+#define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK                        (0x80U)
+#define DMA_CEEI_NOP_SHIFT                       (7U)
+#define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
+
+/*! @name SEEI - Set Enable Error Interrupt Register */
+#define DMA_SEEI_SEEI_MASK                       (0x7U)
+#define DMA_SEEI_SEEI_SHIFT                      (0U)
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK                       (0x40U)
+#define DMA_SEEI_SAEE_SHIFT                      (6U)
+#define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK                        (0x80U)
+#define DMA_SEEI_NOP_SHIFT                       (7U)
+#define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
+
+/*! @name CERQ - Clear Enable Request Register */
+#define DMA_CERQ_CERQ_MASK                       (0x7U)
+#define DMA_CERQ_CERQ_SHIFT                      (0U)
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK                       (0x40U)
+#define DMA_CERQ_CAER_SHIFT                      (6U)
+#define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK                        (0x80U)
+#define DMA_CERQ_NOP_SHIFT                       (7U)
+#define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
+
+/*! @name SERQ - Set Enable Request Register */
+#define DMA_SERQ_SERQ_MASK                       (0x7U)
+#define DMA_SERQ_SERQ_SHIFT                      (0U)
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK                       (0x40U)
+#define DMA_SERQ_SAER_SHIFT                      (6U)
+#define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK                        (0x80U)
+#define DMA_SERQ_NOP_SHIFT                       (7U)
+#define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
+
+/*! @name CDNE - Clear DONE Status Bit Register */
+#define DMA_CDNE_CDNE_MASK                       (0x7U)
+#define DMA_CDNE_CDNE_SHIFT                      (0U)
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK                       (0x40U)
+#define DMA_CDNE_CADN_SHIFT                      (6U)
+#define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK                        (0x80U)
+#define DMA_CDNE_NOP_SHIFT                       (7U)
+#define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
+
+/*! @name SSRT - Set START Bit Register */
+#define DMA_SSRT_SSRT_MASK                       (0x7U)
+#define DMA_SSRT_SSRT_SHIFT                      (0U)
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK                       (0x40U)
+#define DMA_SSRT_SAST_SHIFT                      (6U)
+#define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK                        (0x80U)
+#define DMA_SSRT_NOP_SHIFT                       (7U)
+#define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
+
+/*! @name CERR - Clear Error Register */
+#define DMA_CERR_CERR_MASK                       (0x7U)
+#define DMA_CERR_CERR_SHIFT                      (0U)
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK                       (0x40U)
+#define DMA_CERR_CAEI_SHIFT                      (6U)
+#define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK                        (0x80U)
+#define DMA_CERR_NOP_SHIFT                       (7U)
+#define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
+
+/*! @name CINT - Clear Interrupt Request Register */
+#define DMA_CINT_CINT_MASK                       (0x7U)
+#define DMA_CINT_CINT_SHIFT                      (0U)
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK                       (0x40U)
+#define DMA_CINT_CAIR_SHIFT                      (6U)
+#define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK                        (0x80U)
+#define DMA_CINT_NOP_SHIFT                       (7U)
+#define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
+
+/*! @name INT - Interrupt Request Register */
+#define DMA_INT_INT0_MASK                        (0x1U)
+#define DMA_INT_INT0_SHIFT                       (0U)
+#define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK                        (0x2U)
+#define DMA_INT_INT1_SHIFT                       (1U)
+#define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK                        (0x4U)
+#define DMA_INT_INT2_SHIFT                       (2U)
+#define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK                        (0x8U)
+#define DMA_INT_INT3_SHIFT                       (3U)
+#define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK                        (0x10U)
+#define DMA_INT_INT4_SHIFT                       (4U)
+#define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK                        (0x20U)
+#define DMA_INT_INT5_SHIFT                       (5U)
+#define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK                        (0x40U)
+#define DMA_INT_INT6_SHIFT                       (6U)
+#define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK                        (0x80U)
+#define DMA_INT_INT7_SHIFT                       (7U)
+#define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
+
+/*! @name ERR - Error Register */
+#define DMA_ERR_ERR0_MASK                        (0x1U)
+#define DMA_ERR_ERR0_SHIFT                       (0U)
+#define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK                        (0x2U)
+#define DMA_ERR_ERR1_SHIFT                       (1U)
+#define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK                        (0x4U)
+#define DMA_ERR_ERR2_SHIFT                       (2U)
+#define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK                        (0x8U)
+#define DMA_ERR_ERR3_SHIFT                       (3U)
+#define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK                        (0x10U)
+#define DMA_ERR_ERR4_SHIFT                       (4U)
+#define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK                        (0x20U)
+#define DMA_ERR_ERR5_SHIFT                       (5U)
+#define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK                        (0x40U)
+#define DMA_ERR_ERR6_SHIFT                       (6U)
+#define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK                        (0x80U)
+#define DMA_ERR_ERR7_SHIFT                       (7U)
+#define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
+
+/*! @name HRS - Hardware Request Status Register */
+#define DMA_HRS_HRS0_MASK                        (0x1U)
+#define DMA_HRS_HRS0_SHIFT                       (0U)
+#define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK                        (0x2U)
+#define DMA_HRS_HRS1_SHIFT                       (1U)
+#define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK                        (0x4U)
+#define DMA_HRS_HRS2_SHIFT                       (2U)
+#define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK                        (0x8U)
+#define DMA_HRS_HRS3_SHIFT                       (3U)
+#define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK                        (0x10U)
+#define DMA_HRS_HRS4_SHIFT                       (4U)
+#define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK                        (0x20U)
+#define DMA_HRS_HRS5_SHIFT                       (5U)
+#define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK                        (0x40U)
+#define DMA_HRS_HRS6_SHIFT                       (6U)
+#define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK                        (0x80U)
+#define DMA_HRS_HRS7_SHIFT                       (7U)
+#define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
+
+/*! @name EARS - Enable Asynchronous Request in Stop Register */
+#define DMA_EARS_EDREQ_0_MASK                    (0x1U)
+#define DMA_EARS_EDREQ_0_SHIFT                   (0U)
+#define DMA_EARS_EDREQ_0(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
+#define DMA_EARS_EDREQ_1_MASK                    (0x2U)
+#define DMA_EARS_EDREQ_1_SHIFT                   (1U)
+#define DMA_EARS_EDREQ_1(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
+#define DMA_EARS_EDREQ_2_MASK                    (0x4U)
+#define DMA_EARS_EDREQ_2_SHIFT                   (2U)
+#define DMA_EARS_EDREQ_2(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
+#define DMA_EARS_EDREQ_3_MASK                    (0x8U)
+#define DMA_EARS_EDREQ_3_SHIFT                   (3U)
+#define DMA_EARS_EDREQ_3(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
+#define DMA_EARS_EDREQ_4_MASK                    (0x10U)
+#define DMA_EARS_EDREQ_4_SHIFT                   (4U)
+#define DMA_EARS_EDREQ_4(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
+#define DMA_EARS_EDREQ_5_MASK                    (0x20U)
+#define DMA_EARS_EDREQ_5_SHIFT                   (5U)
+#define DMA_EARS_EDREQ_5(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
+#define DMA_EARS_EDREQ_6_MASK                    (0x40U)
+#define DMA_EARS_EDREQ_6_SHIFT                   (6U)
+#define DMA_EARS_EDREQ_6(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
+#define DMA_EARS_EDREQ_7_MASK                    (0x80U)
+#define DMA_EARS_EDREQ_7_SHIFT                   (7U)
+#define DMA_EARS_EDREQ_7(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
+
+/*! @name DCHPRI3 - Channel n Priority Register */
+#define DMA_DCHPRI3_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI3_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI3_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI3_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
+
+/*! @name DCHPRI2 - Channel n Priority Register */
+#define DMA_DCHPRI2_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI2_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI2_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI2_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
+
+/*! @name DCHPRI1 - Channel n Priority Register */
+#define DMA_DCHPRI1_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI1_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI1_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI1_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
+
+/*! @name DCHPRI0 - Channel n Priority Register */
+#define DMA_DCHPRI0_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI0_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI0_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI0_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
+
+/*! @name DCHPRI7 - Channel n Priority Register */
+#define DMA_DCHPRI7_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI7_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI7_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI7_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
+
+/*! @name DCHPRI6 - Channel n Priority Register */
+#define DMA_DCHPRI6_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI6_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI6_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI6_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
+
+/*! @name DCHPRI5 - Channel n Priority Register */
+#define DMA_DCHPRI5_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI5_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI5_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI5_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
+
+/*! @name DCHPRI4 - Channel n Priority Register */
+#define DMA_DCHPRI4_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI4_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI4_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI4_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
+
+/*! @name SADDR - TCD Source Address */
+#define DMA_SADDR_SADDR_MASK                     (0xFFFFFFFFU)
+#define DMA_SADDR_SADDR_SHIFT                    (0U)
+#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
+
+/* The count of DMA_SADDR */
+#define DMA_SADDR_COUNT                          (8U)
+
+/*! @name SOFF - TCD Signed Source Address Offset */
+#define DMA_SOFF_SOFF_MASK                       (0xFFFFU)
+#define DMA_SOFF_SOFF_SHIFT                      (0U)
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
+
+/* The count of DMA_SOFF */
+#define DMA_SOFF_COUNT                           (8U)
+
+/*! @name ATTR - TCD Transfer Attributes */
+#define DMA_ATTR_DSIZE_MASK                      (0x7U)
+#define DMA_ATTR_DSIZE_SHIFT                     (0U)
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       (0xF8U)
+#define DMA_ATTR_DMOD_SHIFT                      (3U)
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      (0x700U)
+#define DMA_ATTR_SSIZE_SHIFT                     (8U)
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       (0xF800U)
+#define DMA_ATTR_SMOD_SHIFT                      (11U)
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
+
+/* The count of DMA_ATTR */
+#define DMA_ATTR_COUNT                           (8U)
+
+/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
+#define DMA_NBYTES_MLNO_NBYTES_MASK              (0xFFFFFFFFU)
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT             (0U)
+#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
+
+/* The count of DMA_NBYTES_MLNO */
+#define DMA_NBYTES_MLNO_COUNT                    (8U)
+
+/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           (0x3FFFFFFFU)
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          (0U)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            (0x40000000U)
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           (30U)
+#define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            (0x80000000U)
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           (31U)
+#define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFNO */
+#define DMA_NBYTES_MLOFFNO_COUNT                 (8U)
+
+/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          (0x3FFU)
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         (0U)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           (0x3FFFFC00U)
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          (10U)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           (0x40000000U)
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          (30U)
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           (0x80000000U)
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          (31U)
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFYES */
+#define DMA_NBYTES_MLOFFYES_COUNT                (8U)
+
+/*! @name SLAST - TCD Last Source Address Adjustment */
+#define DMA_SLAST_SLAST_MASK                     (0xFFFFFFFFU)
+#define DMA_SLAST_SLAST_SHIFT                    (0U)
+#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
+
+/* The count of DMA_SLAST */
+#define DMA_SLAST_COUNT                          (8U)
+
+/*! @name DADDR - TCD Destination Address */
+#define DMA_DADDR_DADDR_MASK                     (0xFFFFFFFFU)
+#define DMA_DADDR_DADDR_SHIFT                    (0U)
+#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
+
+/* The count of DMA_DADDR */
+#define DMA_DADDR_COUNT                          (8U)
+
+/*! @name DOFF - TCD Signed Destination Address Offset */
+#define DMA_DOFF_DOFF_MASK                       (0xFFFFU)
+#define DMA_DOFF_DOFF_SHIFT                      (0U)
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
+
+/* The count of DMA_DOFF */
+#define DMA_DOFF_COUNT                           (8U)
+
+/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_CITER_ELINKNO_CITER_MASK             (0x7FFFU)
+#define DMA_CITER_ELINKNO_CITER_SHIFT            (0U)
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK             (0x8000U)
+#define DMA_CITER_ELINKNO_ELINK_SHIFT            (15U)
+#define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKNO */
+#define DMA_CITER_ELINKNO_COUNT                  (8U)
+
+/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_CITER_ELINKYES_CITER_MASK            (0x1FFU)
+#define DMA_CITER_ELINKYES_CITER_SHIFT           (0U)
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           (0xE00U)
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          (9U)
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK            (0x8000U)
+#define DMA_CITER_ELINKYES_ELINK_SHIFT           (15U)
+#define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKYES */
+#define DMA_CITER_ELINKYES_COUNT                 (8U)
+
+/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
+#define DMA_DLAST_SGA_DLASTSGA_MASK              (0xFFFFFFFFU)
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT             (0U)
+#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
+
+/* The count of DMA_DLAST_SGA */
+#define DMA_DLAST_SGA_COUNT                      (8U)
+
+/*! @name CSR - TCD Control and Status */
+#define DMA_CSR_START_MASK                       (0x1U)
+#define DMA_CSR_START_SHIFT                      (0U)
+#define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK                    (0x2U)
+#define DMA_CSR_INTMAJOR_SHIFT                   (1U)
+#define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK                     (0x4U)
+#define DMA_CSR_INTHALF_SHIFT                    (2U)
+#define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK                        (0x8U)
+#define DMA_CSR_DREQ_SHIFT                       (3U)
+#define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK                         (0x10U)
+#define DMA_CSR_ESG_SHIFT                        (4U)
+#define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK                  (0x20U)
+#define DMA_CSR_MAJORELINK_SHIFT                 (5U)
+#define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK                      (0x40U)
+#define DMA_CSR_ACTIVE_SHIFT                     (6U)
+#define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK                        (0x80U)
+#define DMA_CSR_DONE_SHIFT                       (7U)
+#define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK                 (0x700U)
+#define DMA_CSR_MAJORLINKCH_SHIFT                (8U)
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         (0xC000U)
+#define DMA_CSR_BWC_SHIFT                        (14U)
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
+
+/* The count of DMA_CSR */
+#define DMA_CSR_COUNT                            (8U)
+
+/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_BITER_ELINKNO_BITER_MASK             (0x7FFFU)
+#define DMA_BITER_ELINKNO_BITER_SHIFT            (0U)
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK             (0x8000U)
+#define DMA_BITER_ELINKNO_ELINK_SHIFT            (15U)
+#define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKNO */
+#define DMA_BITER_ELINKNO_COUNT                  (8U)
+
+/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_BITER_ELINKYES_BITER_MASK            (0x1FFU)
+#define DMA_BITER_ELINKYES_BITER_SHIFT           (0U)
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           (0xE00U)
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          (9U)
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK            (0x8000U)
+#define DMA_BITER_ELINKYES_ELINK_SHIFT           (15U)
+#define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKYES */
+#define DMA_BITER_ELINKYES_COUNT                 (8U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0                                     ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { DMA0_DMA4_IRQn, DMA1_DMA5_IRQn, DMA2_DMA6_IRQn, DMA3_DMA7_IRQn, DMA0_DMA4_IRQn, DMA1_DMA5_IRQn, DMA2_DMA6_IRQn, DMA3_DMA7_IRQn }
+#define DMA_ERROR_IRQS                           { DMA_Error_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[8];                           /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/*! @name CHCFG - Channel Configuration register */
+#define DMAMUX_CHCFG_SOURCE_MASK                 (0x3FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   (0x40U)
+#define DMAMUX_CHCFG_TRIG_SHIFT                  (6U)
+#define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK                   (0x80U)
+#define DMAMUX_CHCFG_ENBL_SHIFT                  (7U)
+#define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT                       (8U)
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE                              (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS                         { DMAMUX }
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EMVSIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
+ * @{
+ */
+
+/** EMVSIM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VER_ID;                            /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t CLKCFG;                            /**< Clock Configuration Register, offset: 0x8 */
+  __IO uint32_t DIVISOR;                           /**< Baud Rate Divisor Register, offset: 0xC */
+  __IO uint32_t CTRL;                              /**< Control Register, offset: 0x10 */
+  __IO uint32_t INT_MASK;                          /**< Interrupt Mask Register, offset: 0x14 */
+  __IO uint32_t RX_THD;                            /**< Receiver Threshold Register, offset: 0x18 */
+  __IO uint32_t TX_THD;                            /**< Transmitter Threshold Register, offset: 0x1C */
+  __IO uint32_t RX_STATUS;                         /**< Receive Status Register, offset: 0x20 */
+  __IO uint32_t TX_STATUS;                         /**< Transmitter Status Register, offset: 0x24 */
+  __IO uint32_t PCSR;                              /**< Port Control and Status Register, offset: 0x28 */
+  __I  uint32_t RX_BUF;                            /**< Receive Data Read Buffer, offset: 0x2C */
+  __IO uint32_t TX_BUF;                            /**< Transmit Data Buffer, offset: 0x30 */
+  __IO uint32_t TX_GETU;                           /**< Transmitter Guard ETU Value Register, offset: 0x34 */
+  __IO uint32_t CWT_VAL;                           /**< Character Wait Time Value Register, offset: 0x38 */
+  __IO uint32_t BWT_VAL;                           /**< Block Wait Time Value Register, offset: 0x3C */
+  __IO uint32_t BGT_VAL;                           /**< Block Guard Time Value Register, offset: 0x40 */
+  __IO uint32_t GPCNT0_VAL;                        /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
+  __IO uint32_t GPCNT1_VAL;                        /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
+} EMVSIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EMVSIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
+ * @{
+ */
+
+/*! @name VER_ID - Version ID Register */
+#define EMVSIM_VER_ID_VER_MASK                   (0xFFFFFFFFU)
+#define EMVSIM_VER_ID_VER_SHIFT                  (0U)
+#define EMVSIM_VER_ID_VER(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
+
+/*! @name PARAM - Parameter Register */
+#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK          (0xFFU)
+#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT         (0U)
+#define EMVSIM_PARAM_RX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
+#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK          (0xFF00U)
+#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT         (8U)
+#define EMVSIM_PARAM_TX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
+
+/*! @name CLKCFG - Clock Configuration Register */
+#define EMVSIM_CLKCFG_CLK_PRSC_MASK              (0xFFU)
+#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT             (0U)
+#define EMVSIM_CLKCFG_CLK_PRSC(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
+#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK        (0x300U)
+#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT       (8U)
+#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
+#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK        (0xC00U)
+#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT       (10U)
+#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
+
+/*! @name DIVISOR - Baud Rate Divisor Register */
+#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK        (0x1FFU)
+#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT       (0U)
+#define EMVSIM_DIVISOR_DIVISOR_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
+
+/*! @name CTRL - Control Register */
+#define EMVSIM_CTRL_IC_MASK                      (0x1U)
+#define EMVSIM_CTRL_IC_SHIFT                     (0U)
+#define EMVSIM_CTRL_IC(x)                        (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
+#define EMVSIM_CTRL_ICM_MASK                     (0x2U)
+#define EMVSIM_CTRL_ICM_SHIFT                    (1U)
+#define EMVSIM_CTRL_ICM(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
+#define EMVSIM_CTRL_ANACK_MASK                   (0x4U)
+#define EMVSIM_CTRL_ANACK_SHIFT                  (2U)
+#define EMVSIM_CTRL_ANACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
+#define EMVSIM_CTRL_ONACK_MASK                   (0x8U)
+#define EMVSIM_CTRL_ONACK_SHIFT                  (3U)
+#define EMVSIM_CTRL_ONACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
+#define EMVSIM_CTRL_FLSH_RX_MASK                 (0x100U)
+#define EMVSIM_CTRL_FLSH_RX_SHIFT                (8U)
+#define EMVSIM_CTRL_FLSH_RX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
+#define EMVSIM_CTRL_FLSH_TX_MASK                 (0x200U)
+#define EMVSIM_CTRL_FLSH_TX_SHIFT                (9U)
+#define EMVSIM_CTRL_FLSH_TX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
+#define EMVSIM_CTRL_SW_RST_MASK                  (0x400U)
+#define EMVSIM_CTRL_SW_RST_SHIFT                 (10U)
+#define EMVSIM_CTRL_SW_RST(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
+#define EMVSIM_CTRL_KILL_CLOCKS_MASK             (0x800U)
+#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT            (11U)
+#define EMVSIM_CTRL_KILL_CLOCKS(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
+#define EMVSIM_CTRL_DOZE_EN_MASK                 (0x1000U)
+#define EMVSIM_CTRL_DOZE_EN_SHIFT                (12U)
+#define EMVSIM_CTRL_DOZE_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
+#define EMVSIM_CTRL_STOP_EN_MASK                 (0x2000U)
+#define EMVSIM_CTRL_STOP_EN_SHIFT                (13U)
+#define EMVSIM_CTRL_STOP_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
+#define EMVSIM_CTRL_RCV_EN_MASK                  (0x10000U)
+#define EMVSIM_CTRL_RCV_EN_SHIFT                 (16U)
+#define EMVSIM_CTRL_RCV_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
+#define EMVSIM_CTRL_XMT_EN_MASK                  (0x20000U)
+#define EMVSIM_CTRL_XMT_EN_SHIFT                 (17U)
+#define EMVSIM_CTRL_XMT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
+#define EMVSIM_CTRL_RCVR_11_MASK                 (0x40000U)
+#define EMVSIM_CTRL_RCVR_11_SHIFT                (18U)
+#define EMVSIM_CTRL_RCVR_11(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
+#define EMVSIM_CTRL_RX_DMA_EN_MASK               (0x80000U)
+#define EMVSIM_CTRL_RX_DMA_EN_SHIFT              (19U)
+#define EMVSIM_CTRL_RX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
+#define EMVSIM_CTRL_TX_DMA_EN_MASK               (0x100000U)
+#define EMVSIM_CTRL_TX_DMA_EN_SHIFT              (20U)
+#define EMVSIM_CTRL_TX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
+#define EMVSIM_CTRL_INV_CRC_VAL_MASK             (0x1000000U)
+#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT            (24U)
+#define EMVSIM_CTRL_INV_CRC_VAL(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
+#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK            (0x2000000U)
+#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT           (25U)
+#define EMVSIM_CTRL_CRC_OUT_FLIP(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
+#define EMVSIM_CTRL_CRC_IN_FLIP_MASK             (0x4000000U)
+#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT            (26U)
+#define EMVSIM_CTRL_CRC_IN_FLIP(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
+#define EMVSIM_CTRL_CWT_EN_MASK                  (0x8000000U)
+#define EMVSIM_CTRL_CWT_EN_SHIFT                 (27U)
+#define EMVSIM_CTRL_CWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
+#define EMVSIM_CTRL_LRC_EN_MASK                  (0x10000000U)
+#define EMVSIM_CTRL_LRC_EN_SHIFT                 (28U)
+#define EMVSIM_CTRL_LRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
+#define EMVSIM_CTRL_CRC_EN_MASK                  (0x20000000U)
+#define EMVSIM_CTRL_CRC_EN_SHIFT                 (29U)
+#define EMVSIM_CTRL_CRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
+#define EMVSIM_CTRL_XMT_CRC_LRC_MASK             (0x40000000U)
+#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT            (30U)
+#define EMVSIM_CTRL_XMT_CRC_LRC(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
+#define EMVSIM_CTRL_BWT_EN_MASK                  (0x80000000U)
+#define EMVSIM_CTRL_BWT_EN_SHIFT                 (31U)
+#define EMVSIM_CTRL_BWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
+
+/*! @name INT_MASK - Interrupt Mask Register */
+#define EMVSIM_INT_MASK_RDT_IM_MASK              (0x1U)
+#define EMVSIM_INT_MASK_RDT_IM_SHIFT             (0U)
+#define EMVSIM_INT_MASK_RDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
+#define EMVSIM_INT_MASK_TC_IM_MASK               (0x2U)
+#define EMVSIM_INT_MASK_TC_IM_SHIFT              (1U)
+#define EMVSIM_INT_MASK_TC_IM(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
+#define EMVSIM_INT_MASK_RFO_IM_MASK              (0x4U)
+#define EMVSIM_INT_MASK_RFO_IM_SHIFT             (2U)
+#define EMVSIM_INT_MASK_RFO_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
+#define EMVSIM_INT_MASK_ETC_IM_MASK              (0x8U)
+#define EMVSIM_INT_MASK_ETC_IM_SHIFT             (3U)
+#define EMVSIM_INT_MASK_ETC_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
+#define EMVSIM_INT_MASK_TFE_IM_MASK              (0x10U)
+#define EMVSIM_INT_MASK_TFE_IM_SHIFT             (4U)
+#define EMVSIM_INT_MASK_TFE_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
+#define EMVSIM_INT_MASK_TNACK_IM_MASK            (0x20U)
+#define EMVSIM_INT_MASK_TNACK_IM_SHIFT           (5U)
+#define EMVSIM_INT_MASK_TNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
+#define EMVSIM_INT_MASK_TFF_IM_MASK              (0x40U)
+#define EMVSIM_INT_MASK_TFF_IM_SHIFT             (6U)
+#define EMVSIM_INT_MASK_TFF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
+#define EMVSIM_INT_MASK_TDT_IM_MASK              (0x80U)
+#define EMVSIM_INT_MASK_TDT_IM_SHIFT             (7U)
+#define EMVSIM_INT_MASK_TDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
+#define EMVSIM_INT_MASK_GPCNT0_IM_MASK           (0x100U)
+#define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT          (8U)
+#define EMVSIM_INT_MASK_GPCNT0_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
+#define EMVSIM_INT_MASK_CWT_ERR_IM_MASK          (0x200U)
+#define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT         (9U)
+#define EMVSIM_INT_MASK_CWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
+#define EMVSIM_INT_MASK_RNACK_IM_MASK            (0x400U)
+#define EMVSIM_INT_MASK_RNACK_IM_SHIFT           (10U)
+#define EMVSIM_INT_MASK_RNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
+#define EMVSIM_INT_MASK_BWT_ERR_IM_MASK          (0x800U)
+#define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT         (11U)
+#define EMVSIM_INT_MASK_BWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
+#define EMVSIM_INT_MASK_BGT_ERR_IM_MASK          (0x1000U)
+#define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT         (12U)
+#define EMVSIM_INT_MASK_BGT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
+#define EMVSIM_INT_MASK_GPCNT1_IM_MASK           (0x2000U)
+#define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT          (13U)
+#define EMVSIM_INT_MASK_GPCNT1_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
+#define EMVSIM_INT_MASK_RX_DATA_IM_MASK          (0x4000U)
+#define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT         (14U)
+#define EMVSIM_INT_MASK_RX_DATA_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
+#define EMVSIM_INT_MASK_PEF_IM_MASK              (0x8000U)
+#define EMVSIM_INT_MASK_PEF_IM_SHIFT             (15U)
+#define EMVSIM_INT_MASK_PEF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
+
+/*! @name RX_THD - Receiver Threshold Register */
+#define EMVSIM_RX_THD_RDT_MASK                   (0xFU)
+#define EMVSIM_RX_THD_RDT_SHIFT                  (0U)
+#define EMVSIM_RX_THD_RDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
+#define EMVSIM_RX_THD_RNCK_THD_MASK              (0xF00U)
+#define EMVSIM_RX_THD_RNCK_THD_SHIFT             (8U)
+#define EMVSIM_RX_THD_RNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
+
+/*! @name TX_THD - Transmitter Threshold Register */
+#define EMVSIM_TX_THD_TDT_MASK                   (0xFU)
+#define EMVSIM_TX_THD_TDT_SHIFT                  (0U)
+#define EMVSIM_TX_THD_TDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
+#define EMVSIM_TX_THD_TNCK_THD_MASK              (0xF00U)
+#define EMVSIM_TX_THD_TNCK_THD_SHIFT             (8U)
+#define EMVSIM_TX_THD_TNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
+
+/*! @name RX_STATUS - Receive Status Register */
+#define EMVSIM_RX_STATUS_RFO_MASK                (0x1U)
+#define EMVSIM_RX_STATUS_RFO_SHIFT               (0U)
+#define EMVSIM_RX_STATUS_RFO(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
+#define EMVSIM_RX_STATUS_RX_DATA_MASK            (0x10U)
+#define EMVSIM_RX_STATUS_RX_DATA_SHIFT           (4U)
+#define EMVSIM_RX_STATUS_RX_DATA(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
+#define EMVSIM_RX_STATUS_RDTF_MASK               (0x20U)
+#define EMVSIM_RX_STATUS_RDTF_SHIFT              (5U)
+#define EMVSIM_RX_STATUS_RDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
+#define EMVSIM_RX_STATUS_LRC_OK_MASK             (0x40U)
+#define EMVSIM_RX_STATUS_LRC_OK_SHIFT            (6U)
+#define EMVSIM_RX_STATUS_LRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
+#define EMVSIM_RX_STATUS_CRC_OK_MASK             (0x80U)
+#define EMVSIM_RX_STATUS_CRC_OK_SHIFT            (7U)
+#define EMVSIM_RX_STATUS_CRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
+#define EMVSIM_RX_STATUS_CWT_ERR_MASK            (0x100U)
+#define EMVSIM_RX_STATUS_CWT_ERR_SHIFT           (8U)
+#define EMVSIM_RX_STATUS_CWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
+#define EMVSIM_RX_STATUS_RTE_MASK                (0x200U)
+#define EMVSIM_RX_STATUS_RTE_SHIFT               (9U)
+#define EMVSIM_RX_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
+#define EMVSIM_RX_STATUS_BWT_ERR_MASK            (0x400U)
+#define EMVSIM_RX_STATUS_BWT_ERR_SHIFT           (10U)
+#define EMVSIM_RX_STATUS_BWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
+#define EMVSIM_RX_STATUS_BGT_ERR_MASK            (0x800U)
+#define EMVSIM_RX_STATUS_BGT_ERR_SHIFT           (11U)
+#define EMVSIM_RX_STATUS_BGT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
+#define EMVSIM_RX_STATUS_PEF_MASK                (0x1000U)
+#define EMVSIM_RX_STATUS_PEF_SHIFT               (12U)
+#define EMVSIM_RX_STATUS_PEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
+#define EMVSIM_RX_STATUS_FEF_MASK                (0x2000U)
+#define EMVSIM_RX_STATUS_FEF_SHIFT               (13U)
+#define EMVSIM_RX_STATUS_FEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
+#define EMVSIM_RX_STATUS_RX_WPTR_MASK            (0xF0000U)
+#define EMVSIM_RX_STATUS_RX_WPTR_SHIFT           (16U)
+#define EMVSIM_RX_STATUS_RX_WPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
+#define EMVSIM_RX_STATUS_RX_CNT_MASK             (0xFF000000U)
+#define EMVSIM_RX_STATUS_RX_CNT_SHIFT            (24U)
+#define EMVSIM_RX_STATUS_RX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
+
+/*! @name TX_STATUS - Transmitter Status Register */
+#define EMVSIM_TX_STATUS_TNTE_MASK               (0x1U)
+#define EMVSIM_TX_STATUS_TNTE_SHIFT              (0U)
+#define EMVSIM_TX_STATUS_TNTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
+#define EMVSIM_TX_STATUS_TFE_MASK                (0x8U)
+#define EMVSIM_TX_STATUS_TFE_SHIFT               (3U)
+#define EMVSIM_TX_STATUS_TFE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
+#define EMVSIM_TX_STATUS_ETCF_MASK               (0x10U)
+#define EMVSIM_TX_STATUS_ETCF_SHIFT              (4U)
+#define EMVSIM_TX_STATUS_ETCF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
+#define EMVSIM_TX_STATUS_TCF_MASK                (0x20U)
+#define EMVSIM_TX_STATUS_TCF_SHIFT               (5U)
+#define EMVSIM_TX_STATUS_TCF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
+#define EMVSIM_TX_STATUS_TFF_MASK                (0x40U)
+#define EMVSIM_TX_STATUS_TFF_SHIFT               (6U)
+#define EMVSIM_TX_STATUS_TFF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
+#define EMVSIM_TX_STATUS_TDTF_MASK               (0x80U)
+#define EMVSIM_TX_STATUS_TDTF_SHIFT              (7U)
+#define EMVSIM_TX_STATUS_TDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
+#define EMVSIM_TX_STATUS_GPCNT0_TO_MASK          (0x100U)
+#define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT         (8U)
+#define EMVSIM_TX_STATUS_GPCNT0_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
+#define EMVSIM_TX_STATUS_GPCNT1_TO_MASK          (0x200U)
+#define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT         (9U)
+#define EMVSIM_TX_STATUS_GPCNT1_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
+#define EMVSIM_TX_STATUS_TX_RPTR_MASK            (0xF0000U)
+#define EMVSIM_TX_STATUS_TX_RPTR_SHIFT           (16U)
+#define EMVSIM_TX_STATUS_TX_RPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
+#define EMVSIM_TX_STATUS_TX_CNT_MASK             (0xFF000000U)
+#define EMVSIM_TX_STATUS_TX_CNT_SHIFT            (24U)
+#define EMVSIM_TX_STATUS_TX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
+
+/*! @name PCSR - Port Control and Status Register */
+#define EMVSIM_PCSR_SAPD_MASK                    (0x1U)
+#define EMVSIM_PCSR_SAPD_SHIFT                   (0U)
+#define EMVSIM_PCSR_SAPD(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
+#define EMVSIM_PCSR_SVCC_EN_MASK                 (0x2U)
+#define EMVSIM_PCSR_SVCC_EN_SHIFT                (1U)
+#define EMVSIM_PCSR_SVCC_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
+#define EMVSIM_PCSR_VCCENP_MASK                  (0x4U)
+#define EMVSIM_PCSR_VCCENP_SHIFT                 (2U)
+#define EMVSIM_PCSR_VCCENP(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
+#define EMVSIM_PCSR_SRST_MASK                    (0x8U)
+#define EMVSIM_PCSR_SRST_SHIFT                   (3U)
+#define EMVSIM_PCSR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
+#define EMVSIM_PCSR_SCEN_MASK                    (0x10U)
+#define EMVSIM_PCSR_SCEN_SHIFT                   (4U)
+#define EMVSIM_PCSR_SCEN(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
+#define EMVSIM_PCSR_SCSP_MASK                    (0x20U)
+#define EMVSIM_PCSR_SCSP_SHIFT                   (5U)
+#define EMVSIM_PCSR_SCSP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
+#define EMVSIM_PCSR_SPD_MASK                     (0x80U)
+#define EMVSIM_PCSR_SPD_SHIFT                    (7U)
+#define EMVSIM_PCSR_SPD(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
+#define EMVSIM_PCSR_SPDIM_MASK                   (0x1000000U)
+#define EMVSIM_PCSR_SPDIM_SHIFT                  (24U)
+#define EMVSIM_PCSR_SPDIM(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
+#define EMVSIM_PCSR_SPDIF_MASK                   (0x2000000U)
+#define EMVSIM_PCSR_SPDIF_SHIFT                  (25U)
+#define EMVSIM_PCSR_SPDIF(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
+#define EMVSIM_PCSR_SPDP_MASK                    (0x4000000U)
+#define EMVSIM_PCSR_SPDP_SHIFT                   (26U)
+#define EMVSIM_PCSR_SPDP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
+#define EMVSIM_PCSR_SPDES_MASK                   (0x8000000U)
+#define EMVSIM_PCSR_SPDES_SHIFT                  (27U)
+#define EMVSIM_PCSR_SPDES(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
+
+/*! @name RX_BUF - Receive Data Read Buffer */
+#define EMVSIM_RX_BUF_RX_BYTE_MASK               (0xFFU)
+#define EMVSIM_RX_BUF_RX_BYTE_SHIFT              (0U)
+#define EMVSIM_RX_BUF_RX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
+
+/*! @name TX_BUF - Transmit Data Buffer */
+#define EMVSIM_TX_BUF_TX_BYTE_MASK               (0xFFU)
+#define EMVSIM_TX_BUF_TX_BYTE_SHIFT              (0U)
+#define EMVSIM_TX_BUF_TX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
+
+/*! @name TX_GETU - Transmitter Guard ETU Value Register */
+#define EMVSIM_TX_GETU_GETU_MASK                 (0xFFU)
+#define EMVSIM_TX_GETU_GETU_SHIFT                (0U)
+#define EMVSIM_TX_GETU_GETU(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
+
+/*! @name CWT_VAL - Character Wait Time Value Register */
+#define EMVSIM_CWT_VAL_CWT_MASK                  (0xFFFFU)
+#define EMVSIM_CWT_VAL_CWT_SHIFT                 (0U)
+#define EMVSIM_CWT_VAL_CWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
+
+/*! @name BWT_VAL - Block Wait Time Value Register */
+#define EMVSIM_BWT_VAL_BWT_MASK                  (0xFFFFFFFFU)
+#define EMVSIM_BWT_VAL_BWT_SHIFT                 (0U)
+#define EMVSIM_BWT_VAL_BWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
+
+/*! @name BGT_VAL - Block Guard Time Value Register */
+#define EMVSIM_BGT_VAL_BGT_MASK                  (0xFFFFU)
+#define EMVSIM_BGT_VAL_BGT_SHIFT                 (0U)
+#define EMVSIM_BGT_VAL_BGT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
+
+/*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */
+#define EMVSIM_GPCNT0_VAL_GPCNT0_MASK            (0xFFFFU)
+#define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT           (0U)
+#define EMVSIM_GPCNT0_VAL_GPCNT0(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
+
+/*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
+#define EMVSIM_GPCNT1_VAL_GPCNT1_MASK            (0xFFFFU)
+#define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT           (0U)
+#define EMVSIM_GPCNT1_VAL_GPCNT1(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group EMVSIM_Register_Masks */
+
+
+/* EMVSIM - Peripheral instance base addresses */
+/** Peripheral EMVSIM0 base address */
+#define EMVSIM0_BASE                             (0x4004E000u)
+/** Peripheral EMVSIM0 base pointer */
+#define EMVSIM0                                  ((EMVSIM_Type *)EMVSIM0_BASE)
+/** Peripheral EMVSIM1 base address */
+#define EMVSIM1_BASE                             (0x4004F000u)
+/** Peripheral EMVSIM1 base pointer */
+#define EMVSIM1                                  ((EMVSIM_Type *)EMVSIM1_BASE)
+/** Array initializer of EMVSIM peripheral base addresses */
+#define EMVSIM_BASE_ADDRS                        { EMVSIM0_BASE, EMVSIM1_BASE }
+/** Array initializer of EMVSIM peripheral base pointers */
+#define EMVSIM_BASE_PTRS                         { EMVSIM0, EMVSIM1 }
+/** Interrupt vectors for the EMVSIM peripheral type */
+#define EMVSIM_IRQS                              { EMVSIM0_IRQn, EMVSIM1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group EMVSIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
+  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
+  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
+  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler Register, offset: 0x5 */
+} EWM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+#define EWM_CTRL_EWMEN_MASK                      (0x1U)
+#define EWM_CTRL_EWMEN_SHIFT                     (0U)
+#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK                      (0x2U)
+#define EWM_CTRL_ASSIN_SHIFT                     (1U)
+#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK                       (0x4U)
+#define EWM_CTRL_INEN_SHIFT                      (2U)
+#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK                      (0x8U)
+#define EWM_CTRL_INTEN_SHIFT                     (3U)
+#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
+
+/*! @name SERV - Service Register */
+#define EWM_SERV_SERVICE_MASK                    (0xFFU)
+#define EWM_SERV_SERVICE_SHIFT                   (0U)
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
+
+/*! @name CMPL - Compare Low Register */
+#define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
+#define EWM_CMPL_COMPAREL_SHIFT                  (0U)
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
+
+/*! @name CMPH - Compare High Register */
+#define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
+#define EWM_CMPH_COMPAREH_SHIFT                  (0U)
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
+
+/*! @name CLKPRESCALER - Clock Prescaler Register */
+#define EWM_CLKPRESCALER_CLK_DIV_MASK            (0xFFU)
+#define EWM_CLKPRESCALER_CLK_DIV_SHIFT           (0U)
+#define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE                                 (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM                                      ((EWM_Type *)EWM_BASE)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS                           { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS                            { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS                                 { WDOG_EWM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FGPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FGPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+#define FGPIO_PDOR_PDO_MASK                      (0xFFFFFFFFU)
+#define FGPIO_PDOR_PDO_SHIFT                     (0U)
+#define FGPIO_PDOR_PDO(x)                        (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
+
+/*! @name PSOR - Port Set Output Register */
+#define FGPIO_PSOR_PTSO_MASK                     (0xFFFFFFFFU)
+#define FGPIO_PSOR_PTSO_SHIFT                    (0U)
+#define FGPIO_PSOR_PTSO(x)                       (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
+
+/*! @name PCOR - Port Clear Output Register */
+#define FGPIO_PCOR_PTCO_MASK                     (0xFFFFFFFFU)
+#define FGPIO_PCOR_PTCO_SHIFT                    (0U)
+#define FGPIO_PCOR_PTCO(x)                       (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
+
+/*! @name PTOR - Port Toggle Output Register */
+#define FGPIO_PTOR_PTTO_MASK                     (0xFFFFFFFFU)
+#define FGPIO_PTOR_PTTO_SHIFT                    (0U)
+#define FGPIO_PTOR_PTTO(x)                       (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
+
+/*! @name PDIR - Port Data Input Register */
+#define FGPIO_PDIR_PDI_MASK                      (0xFFFFFFFFU)
+#define FGPIO_PDIR_PDI_SHIFT                     (0U)
+#define FGPIO_PDIR_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
+
+/*! @name PDDR - Port Data Direction Register */
+#define FGPIO_PDDR_PDD_MASK                      (0xFFFFFFFFU)
+#define FGPIO_PDDR_PDD_SHIFT                     (0U)
+#define FGPIO_PDDR_PDD(x)                        (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FGPIOA base address */
+#define FGPIOA_BASE                              (0xF8000000u)
+/** Peripheral FGPIOA base pointer */
+#define FGPIOA                                   ((FGPIO_Type *)FGPIOA_BASE)
+/** Peripheral FGPIOB base address */
+#define FGPIOB_BASE                              (0xF8000040u)
+/** Peripheral FGPIOB base pointer */
+#define FGPIOB                                   ((FGPIO_Type *)FGPIOB_BASE)
+/** Peripheral FGPIOC base address */
+#define FGPIOC_BASE                              (0xF8000080u)
+/** Peripheral FGPIOC base pointer */
+#define FGPIOC                                   ((FGPIO_Type *)FGPIOC_BASE)
+/** Peripheral FGPIOD base address */
+#define FGPIOD_BASE                              (0xF80000C0u)
+/** Peripheral FGPIOD base pointer */
+#define FGPIOD                                   ((FGPIO_Type *)FGPIOD_BASE)
+/** Peripheral FGPIOE base address */
+#define FGPIOE_BASE                              (0xF8000100u)
+/** Peripheral FGPIOE base pointer */
+#define FGPIOE                                   ((FGPIO_Type *)FGPIOE_BASE)
+/** Array initializer of FGPIO peripheral base addresses */
+#define FGPIO_BASE_ADDRS                         { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE }
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASE_PTRS                          { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE }
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FLEXIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXIO - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t CTRL;                              /**< FlexIO Control Register, offset: 0x8 */
+  __I  uint32_t PIN;                               /**< Pin State Register, offset: 0xC */
+  __IO uint32_t SHIFTSTAT;                         /**< Shifter Status Register, offset: 0x10 */
+  __IO uint32_t SHIFTERR;                          /**< Shifter Error Register, offset: 0x14 */
+  __IO uint32_t TIMSTAT;                           /**< Timer Status Register, offset: 0x18 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
+  __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
+  __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable Register, offset: 0x28 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t SHIFTSTATE;                        /**< Shifter State Register, offset: 0x40 */
+       uint8_t RESERVED_3[60];
+  __IO uint32_t SHIFTCTL[8];                       /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
+       uint8_t RESERVED_4[96];
+  __IO uint32_t SHIFTCFG[8];                       /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_5[224];
+  __IO uint32_t SHIFTBUF[8];                       /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_6[96];
+  __IO uint32_t SHIFTBUFBIS[8];                    /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
+       uint8_t RESERVED_7[96];
+  __IO uint32_t SHIFTBUFBYS[8];                    /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
+       uint8_t RESERVED_8[96];
+  __IO uint32_t SHIFTBUFBBS[8];                    /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
+       uint8_t RESERVED_9[96];
+  __IO uint32_t TIMCTL[8];                         /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
+       uint8_t RESERVED_10[96];
+  __IO uint32_t TIMCFG[8];                         /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
+       uint8_t RESERVED_11[96];
+  __IO uint32_t TIMCMP[8];                         /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
+       uint8_t RESERVED_12[352];
+  __IO uint32_t SHIFTBUFNBS[8];                    /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
+       uint8_t RESERVED_13[96];
+  __IO uint32_t SHIFTBUFHWS[8];                    /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
+       uint8_t RESERVED_14[96];
+  __IO uint32_t SHIFTBUFNIS[8];                    /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
+} FLEXIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FLEXIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+#define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
+#define FLEXIO_VERID_FEATURE_SHIFT               (0U)
+#define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
+#define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
+#define FLEXIO_VERID_MINOR_SHIFT                 (16U)
+#define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
+#define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
+#define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
+#define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
+
+/*! @name PARAM - Parameter Register */
+#define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
+#define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
+#define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
+#define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
+#define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
+#define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
+#define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
+#define FLEXIO_PARAM_PIN_SHIFT                   (16U)
+#define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
+#define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
+#define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
+#define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
+
+/*! @name CTRL - FlexIO Control Register */
+#define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
+#define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
+#define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
+#define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
+#define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
+#define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
+#define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
+#define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
+#define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
+#define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
+#define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
+#define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
+#define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
+#define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
+#define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
+
+/*! @name PIN - Pin State Register */
+#define FLEXIO_PIN_PDI_MASK                      (0xFFFFFFFFU)
+#define FLEXIO_PIN_PDI_SHIFT                     (0U)
+#define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
+
+/*! @name SHIFTSTAT - Shifter Status Register */
+#define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFFU)
+#define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
+#define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
+
+/*! @name SHIFTERR - Shifter Error Register */
+#define FLEXIO_SHIFTERR_SEF_MASK                 (0xFFU)
+#define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
+#define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
+
+/*! @name TIMSTAT - Timer Status Register */
+#define FLEXIO_TIMSTAT_TSF_MASK                  (0xFFU)
+#define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
+#define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
+
+/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
+#define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFFU)
+#define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
+#define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
+
+/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
+#define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFFU)
+#define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
+#define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
+
+/*! @name TIMIEN - Timer Interrupt Enable Register */
+#define FLEXIO_TIMIEN_TEIE_MASK                  (0xFFU)
+#define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
+#define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
+
+/*! @name SHIFTSDEN - Shifter Status DMA Enable */
+#define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFFU)
+#define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
+#define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
+
+/*! @name SHIFTSTATE - Shifter State Register */
+#define FLEXIO_SHIFTSTATE_STATE_MASK             (0x7U)
+#define FLEXIO_SHIFTSTATE_STATE_SHIFT            (0U)
+#define FLEXIO_SHIFTSTATE_STATE(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
+
+/*! @name SHIFTCTL - Shifter Control N Register */
+#define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
+#define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
+#define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
+#define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
+#define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
+#define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
+#define FLEXIO_SHIFTCTL_PINSEL_MASK              (0x1F00U)
+#define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
+#define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
+#define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
+#define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
+#define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
+#define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
+#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
+#define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
+#define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x7000000U)
+#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
+#define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
+
+/* The count of FLEXIO_SHIFTCTL */
+#define FLEXIO_SHIFTCTL_COUNT                    (8U)
+
+/*! @name SHIFTCFG - Shifter Configuration N Register */
+#define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
+#define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
+#define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
+#define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
+#define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
+#define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
+#define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
+#define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
+#define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
+#define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0x1F0000U)
+#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
+#define FLEXIO_SHIFTCFG_PWIDTH(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
+
+/* The count of FLEXIO_SHIFTCFG */
+#define FLEXIO_SHIFTCFG_COUNT                    (8U)
+
+/*! @name SHIFTBUF - Shifter Buffer N Register */
+#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
+#define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
+
+/* The count of FLEXIO_SHIFTBUF */
+#define FLEXIO_SHIFTBUF_COUNT                    (8U)
+
+/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
+
+/* The count of FLEXIO_SHIFTBUFBIS */
+#define FLEXIO_SHIFTBUFBIS_COUNT                 (8U)
+
+/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
+
+/* The count of FLEXIO_SHIFTBUFBYS */
+#define FLEXIO_SHIFTBUFBYS_COUNT                 (8U)
+
+/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
+
+/* The count of FLEXIO_SHIFTBUFBBS */
+#define FLEXIO_SHIFTBUFBBS_COUNT                 (8U)
+
+/*! @name TIMCTL - Timer Control N Register */
+#define FLEXIO_TIMCTL_TIMOD_MASK                 (0x3U)
+#define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
+#define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
+#define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
+#define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
+#define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
+#define FLEXIO_TIMCTL_PINSEL_MASK                (0x1F00U)
+#define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
+#define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
+#define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
+#define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
+#define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
+#define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
+#define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
+#define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
+#define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
+#define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
+#define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
+#define FLEXIO_TIMCTL_TRGSEL_MASK                (0x3F000000U)
+#define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
+#define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
+
+/* The count of FLEXIO_TIMCTL */
+#define FLEXIO_TIMCTL_COUNT                      (8U)
+
+/*! @name TIMCFG - Timer Configuration N Register */
+#define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
+#define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
+#define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
+#define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
+#define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
+#define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
+#define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
+#define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
+#define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
+#define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
+#define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
+#define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
+#define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
+#define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
+#define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
+#define FLEXIO_TIMCFG_TIMDEC_MASK                (0x300000U)
+#define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
+#define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
+#define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
+#define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
+#define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
+
+/* The count of FLEXIO_TIMCFG */
+#define FLEXIO_TIMCFG_COUNT                      (8U)
+
+/*! @name TIMCMP - Timer Compare N Register */
+#define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
+#define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
+#define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
+
+/* The count of FLEXIO_TIMCMP */
+#define FLEXIO_TIMCMP_COUNT                      (8U)
+
+/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
+#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
+
+/* The count of FLEXIO_SHIFTBUFNBS */
+#define FLEXIO_SHIFTBUFNBS_COUNT                 (8U)
+
+/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
+#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
+
+/* The count of FLEXIO_SHIFTBUFHWS */
+#define FLEXIO_SHIFTBUFHWS_COUNT                 (8U)
+
+/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
+#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
+
+/* The count of FLEXIO_SHIFTBUFNIS */
+#define FLEXIO_SHIFTBUFNIS_COUNT                 (8U)
+
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Masks */
+
+
+/* FLEXIO - Peripheral instance base addresses */
+/** Peripheral FLEXIO0 base address */
+#define FLEXIO0_BASE                             (0x4005F000u)
+/** Peripheral FLEXIO0 base pointer */
+#define FLEXIO0                                  ((FLEXIO_Type *)FLEXIO0_BASE)
+/** Array initializer of FLEXIO peripheral base addresses */
+#define FLEXIO_BASE_ADDRS                        { FLEXIO0_BASE }
+/** Array initializer of FLEXIO peripheral base pointers */
+#define FLEXIO_BASE_PTRS                         { FLEXIO0 }
+/** Interrupt vectors for the FLEXIO peripheral type */
+#define FLEXIO_IRQS                              { FLEXIO0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
+       uint8_t RESERVED_0[4];
+  __I  uint8_t XACCH3;                             /**< Execute-only Access Registers, offset: 0x18 */
+  __I  uint8_t XACCH2;                             /**< Execute-only Access Registers, offset: 0x19 */
+  __I  uint8_t XACCH1;                             /**< Execute-only Access Registers, offset: 0x1A */
+  __I  uint8_t XACCH0;                             /**< Execute-only Access Registers, offset: 0x1B */
+  __I  uint8_t XACCL3;                             /**< Execute-only Access Registers, offset: 0x1C */
+  __I  uint8_t XACCL2;                             /**< Execute-only Access Registers, offset: 0x1D */
+  __I  uint8_t XACCL1;                             /**< Execute-only Access Registers, offset: 0x1E */
+  __I  uint8_t XACCL0;                             /**< Execute-only Access Registers, offset: 0x1F */
+  __I  uint8_t SACCH3;                             /**< Supervisor-only Access Registers, offset: 0x20 */
+  __I  uint8_t SACCH2;                             /**< Supervisor-only Access Registers, offset: 0x21 */
+  __I  uint8_t SACCH1;                             /**< Supervisor-only Access Registers, offset: 0x22 */
+  __I  uint8_t SACCH0;                             /**< Supervisor-only Access Registers, offset: 0x23 */
+  __I  uint8_t SACCL3;                             /**< Supervisor-only Access Registers, offset: 0x24 */
+  __I  uint8_t SACCL2;                             /**< Supervisor-only Access Registers, offset: 0x25 */
+  __I  uint8_t SACCL1;                             /**< Supervisor-only Access Registers, offset: 0x26 */
+  __I  uint8_t SACCL0;                             /**< Supervisor-only Access Registers, offset: 0x27 */
+  __I  uint8_t FACSS;                              /**< Flash Access Segment Size Register, offset: 0x28 */
+       uint8_t RESERVED_1[2];
+  __I  uint8_t FACSN;                              /**< Flash Access Segment Number Register, offset: 0x2B */
+} FTFA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FTFA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/*! @name FSTAT - Flash Status Register */
+#define FTFA_FSTAT_MGSTAT0_MASK                  (0x1U)
+#define FTFA_FSTAT_MGSTAT0_SHIFT                 (0U)
+#define FTFA_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
+#define FTFA_FSTAT_FPVIOL_MASK                   (0x10U)
+#define FTFA_FSTAT_FPVIOL_SHIFT                  (4U)
+#define FTFA_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
+#define FTFA_FSTAT_ACCERR_MASK                   (0x20U)
+#define FTFA_FSTAT_ACCERR_SHIFT                  (5U)
+#define FTFA_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
+#define FTFA_FSTAT_RDCOLERR_MASK                 (0x40U)
+#define FTFA_FSTAT_RDCOLERR_SHIFT                (6U)
+#define FTFA_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
+#define FTFA_FSTAT_CCIF_MASK                     (0x80U)
+#define FTFA_FSTAT_CCIF_SHIFT                    (7U)
+#define FTFA_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
+
+/*! @name FCNFG - Flash Configuration Register */
+#define FTFA_FCNFG_ERSSUSP_MASK                  (0x10U)
+#define FTFA_FCNFG_ERSSUSP_SHIFT                 (4U)
+#define FTFA_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
+#define FTFA_FCNFG_ERSAREQ_MASK                  (0x20U)
+#define FTFA_FCNFG_ERSAREQ_SHIFT                 (5U)
+#define FTFA_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
+#define FTFA_FCNFG_RDCOLLIE_MASK                 (0x40U)
+#define FTFA_FCNFG_RDCOLLIE_SHIFT                (6U)
+#define FTFA_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
+#define FTFA_FCNFG_CCIE_MASK                     (0x80U)
+#define FTFA_FCNFG_CCIE_SHIFT                    (7U)
+#define FTFA_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
+
+/*! @name FSEC - Flash Security Register */
+#define FTFA_FSEC_SEC_MASK                       (0x3U)
+#define FTFA_FSEC_SEC_SHIFT                      (0U)
+#define FTFA_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK                    (0xCU)
+#define FTFA_FSEC_FSLACC_SHIFT                   (2U)
+#define FTFA_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK                      (0x30U)
+#define FTFA_FSEC_MEEN_SHIFT                     (4U)
+#define FTFA_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK                     (0xC0U)
+#define FTFA_FSEC_KEYEN_SHIFT                    (6U)
+#define FTFA_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Flash Option Register */
+#define FTFA_FOPT_OPT_MASK                       (0xFFU)
+#define FTFA_FOPT_OPT_SHIFT                      (0U)
+#define FTFA_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+#define FTFA_FCCOB3_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB3_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+#define FTFA_FCCOB2_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB2_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+#define FTFA_FCCOB1_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB1_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+#define FTFA_FCCOB0_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB0_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+#define FTFA_FCCOB7_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB7_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+#define FTFA_FCCOB6_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB6_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+#define FTFA_FCCOB5_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB5_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+#define FTFA_FCCOB4_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB4_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+#define FTFA_FCCOBB_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOBB_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+#define FTFA_FCCOBA_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOBA_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+#define FTFA_FCCOB9_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB9_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+#define FTFA_FCCOB8_CCOBn_MASK                   (0xFFU)
+#define FTFA_FCCOB8_CCOBn_SHIFT                  (0U)
+#define FTFA_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
+
+/*! @name FPROT3 - Program Flash Protection Registers */
+#define FTFA_FPROT3_PROT_MASK                    (0xFFU)
+#define FTFA_FPROT3_PROT_SHIFT                   (0U)
+#define FTFA_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Program Flash Protection Registers */
+#define FTFA_FPROT2_PROT_MASK                    (0xFFU)
+#define FTFA_FPROT2_PROT_SHIFT                   (0U)
+#define FTFA_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Program Flash Protection Registers */
+#define FTFA_FPROT1_PROT_MASK                    (0xFFU)
+#define FTFA_FPROT1_PROT_SHIFT                   (0U)
+#define FTFA_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Program Flash Protection Registers */
+#define FTFA_FPROT0_PROT_MASK                    (0xFFU)
+#define FTFA_FPROT0_PROT_SHIFT                   (0U)
+#define FTFA_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
+
+/*! @name XACCH3 - Execute-only Access Registers */
+#define FTFA_XACCH3_XA_MASK                      (0xFFU)
+#define FTFA_XACCH3_XA_SHIFT                     (0U)
+#define FTFA_XACCH3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK)
+
+/*! @name XACCH2 - Execute-only Access Registers */
+#define FTFA_XACCH2_XA_MASK                      (0xFFU)
+#define FTFA_XACCH2_XA_SHIFT                     (0U)
+#define FTFA_XACCH2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK)
+
+/*! @name XACCH1 - Execute-only Access Registers */
+#define FTFA_XACCH1_XA_MASK                      (0xFFU)
+#define FTFA_XACCH1_XA_SHIFT                     (0U)
+#define FTFA_XACCH1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK)
+
+/*! @name XACCH0 - Execute-only Access Registers */
+#define FTFA_XACCH0_XA_MASK                      (0xFFU)
+#define FTFA_XACCH0_XA_SHIFT                     (0U)
+#define FTFA_XACCH0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK)
+
+/*! @name XACCL3 - Execute-only Access Registers */
+#define FTFA_XACCL3_XA_MASK                      (0xFFU)
+#define FTFA_XACCL3_XA_SHIFT                     (0U)
+#define FTFA_XACCL3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK)
+
+/*! @name XACCL2 - Execute-only Access Registers */
+#define FTFA_XACCL2_XA_MASK                      (0xFFU)
+#define FTFA_XACCL2_XA_SHIFT                     (0U)
+#define FTFA_XACCL2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK)
+
+/*! @name XACCL1 - Execute-only Access Registers */
+#define FTFA_XACCL1_XA_MASK                      (0xFFU)
+#define FTFA_XACCL1_XA_SHIFT                     (0U)
+#define FTFA_XACCL1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK)
+
+/*! @name XACCL0 - Execute-only Access Registers */
+#define FTFA_XACCL0_XA_MASK                      (0xFFU)
+#define FTFA_XACCL0_XA_SHIFT                     (0U)
+#define FTFA_XACCL0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK)
+
+/*! @name SACCH3 - Supervisor-only Access Registers */
+#define FTFA_SACCH3_SA_MASK                      (0xFFU)
+#define FTFA_SACCH3_SA_SHIFT                     (0U)
+#define FTFA_SACCH3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK)
+
+/*! @name SACCH2 - Supervisor-only Access Registers */
+#define FTFA_SACCH2_SA_MASK                      (0xFFU)
+#define FTFA_SACCH2_SA_SHIFT                     (0U)
+#define FTFA_SACCH2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK)
+
+/*! @name SACCH1 - Supervisor-only Access Registers */
+#define FTFA_SACCH1_SA_MASK                      (0xFFU)
+#define FTFA_SACCH1_SA_SHIFT                     (0U)
+#define FTFA_SACCH1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK)
+
+/*! @name SACCH0 - Supervisor-only Access Registers */
+#define FTFA_SACCH0_SA_MASK                      (0xFFU)
+#define FTFA_SACCH0_SA_SHIFT                     (0U)
+#define FTFA_SACCH0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK)
+
+/*! @name SACCL3 - Supervisor-only Access Registers */
+#define FTFA_SACCL3_SA_MASK                      (0xFFU)
+#define FTFA_SACCL3_SA_SHIFT                     (0U)
+#define FTFA_SACCL3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK)
+
+/*! @name SACCL2 - Supervisor-only Access Registers */
+#define FTFA_SACCL2_SA_MASK                      (0xFFU)
+#define FTFA_SACCL2_SA_SHIFT                     (0U)
+#define FTFA_SACCL2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK)
+
+/*! @name SACCL1 - Supervisor-only Access Registers */
+#define FTFA_SACCL1_SA_MASK                      (0xFFU)
+#define FTFA_SACCL1_SA_SHIFT                     (0U)
+#define FTFA_SACCL1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK)
+
+/*! @name SACCL0 - Supervisor-only Access Registers */
+#define FTFA_SACCL0_SA_MASK                      (0xFFU)
+#define FTFA_SACCL0_SA_SHIFT                     (0U)
+#define FTFA_SACCL0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK)
+
+/*! @name FACSS - Flash Access Segment Size Register */
+#define FTFA_FACSS_SGSIZE_MASK                   (0xFFU)
+#define FTFA_FACSS_SGSIZE_SHIFT                  (0U)
+#define FTFA_FACSS_SGSIZE(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK)
+
+/*! @name FACSN - Flash Access Segment Number Register */
+#define FTFA_FACSN_NUMSG_MASK                    (0xFFU)
+#define FTFA_FACSN_NUMSG_SHIFT                   (0U)
+#define FTFA_FACSN_NUMSG(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE                                (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA                                     ((FTFA_Type *)FTFA_BASE)
+/** Array initializer of FTFA peripheral base addresses */
+#define FTFA_BASE_ADDRS                          { FTFA_BASE }
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASE_PTRS                           { FTFA }
+/** Interrupt vectors for the FTFA peripheral type */
+#define FTFA_COMMAND_COMPLETE_IRQS               { FTFA_IRQn }
+#define FTFA_READ_COLLISION_IRQS                 { FTFA_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+#define GPIO_PDOR_PDO_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDOR_PDO_SHIFT                      (0U)
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
+
+/*! @name PSOR - Port Set Output Register */
+#define GPIO_PSOR_PTSO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PSOR_PTSO_SHIFT                     (0U)
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
+
+/*! @name PCOR - Port Clear Output Register */
+#define GPIO_PCOR_PTCO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PCOR_PTCO_SHIFT                     (0U)
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+
+/*! @name PTOR - Port Toggle Output Register */
+#define GPIO_PTOR_PTTO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PTOR_PTTO_SHIFT                     (0U)
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
+
+/*! @name PDIR - Port Data Input Register */
+#define GPIO_PDIR_PDI_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDIR_PDI_SHIFT                      (0U)
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
+
+/*! @name PDDR - Port Data Direction Register */
+#define GPIO_PDDR_PDD_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDDR_PDD_SHIFT                      (0U)
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE                               (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE                               (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE                               (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC                                    ((GPIO_Type *)GPIOC_BASE)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE                               (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD                                    ((GPIO_Type *)GPIOD_BASE)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE                               (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE                                    ((GPIO_Type *)GPIOE_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+  __IO uint8_t S2;                                 /**< I2C Status register 2, offset: 0xC */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name A1 - I2C Address Register 1 */
+#define I2C_A1_AD_MASK                           (0xFEU)
+#define I2C_A1_AD_SHIFT                          (1U)
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
+
+/*! @name F - I2C Frequency Divider register */
+#define I2C_F_ICR_MASK                           (0x3FU)
+#define I2C_F_ICR_SHIFT                          (0U)
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          (0xC0U)
+#define I2C_F_MULT_SHIFT                         (6U)
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
+
+/*! @name C1 - I2C Control Register 1 */
+#define I2C_C1_DMAEN_MASK                        (0x1U)
+#define I2C_C1_DMAEN_SHIFT                       (0U)
+#define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK                         (0x2U)
+#define I2C_C1_WUEN_SHIFT                        (1U)
+#define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK                         (0x4U)
+#define I2C_C1_RSTA_SHIFT                        (2U)
+#define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK                         (0x8U)
+#define I2C_C1_TXAK_SHIFT                        (3U)
+#define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK                           (0x10U)
+#define I2C_C1_TX_SHIFT                          (4U)
+#define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK                          (0x20U)
+#define I2C_C1_MST_SHIFT                         (5U)
+#define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK                        (0x40U)
+#define I2C_C1_IICIE_SHIFT                       (6U)
+#define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK                        (0x80U)
+#define I2C_C1_IICEN_SHIFT                       (7U)
+#define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
+
+/*! @name S - I2C Status register */
+#define I2C_S_RXAK_MASK                          (0x1U)
+#define I2C_S_RXAK_SHIFT                         (0U)
+#define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK                         (0x2U)
+#define I2C_S_IICIF_SHIFT                        (1U)
+#define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK                           (0x4U)
+#define I2C_S_SRW_SHIFT                          (2U)
+#define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK                           (0x8U)
+#define I2C_S_RAM_SHIFT                          (3U)
+#define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK                          (0x10U)
+#define I2C_S_ARBL_SHIFT                         (4U)
+#define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK                          (0x20U)
+#define I2C_S_BUSY_SHIFT                         (5U)
+#define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK                          (0x40U)
+#define I2C_S_IAAS_SHIFT                         (6U)
+#define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK                           (0x80U)
+#define I2C_S_TCF_SHIFT                          (7U)
+#define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
+
+/*! @name D - I2C Data I/O register */
+#define I2C_D_DATA_MASK                          (0xFFU)
+#define I2C_D_DATA_SHIFT                         (0U)
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
+
+/*! @name C2 - I2C Control Register 2 */
+#define I2C_C2_AD_MASK                           (0x7U)
+#define I2C_C2_AD_SHIFT                          (0U)
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         (0x8U)
+#define I2C_C2_RMEN_SHIFT                        (3U)
+#define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK                         (0x10U)
+#define I2C_C2_SBRC_SHIFT                        (4U)
+#define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK                         (0x20U)
+#define I2C_C2_HDRS_SHIFT                        (5U)
+#define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK                        (0x40U)
+#define I2C_C2_ADEXT_SHIFT                       (6U)
+#define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK                        (0x80U)
+#define I2C_C2_GCAEN_SHIFT                       (7U)
+#define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
+
+/*! @name FLT - I2C Programmable Input Glitch Filter Register */
+#define I2C_FLT_FLT_MASK                         (0xFU)
+#define I2C_FLT_FLT_SHIFT                        (0U)
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK                      (0x10U)
+#define I2C_FLT_STARTF_SHIFT                     (4U)
+#define I2C_FLT_STARTF(x)                        (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK                        (0x20U)
+#define I2C_FLT_SSIE_SHIFT                       (5U)
+#define I2C_FLT_SSIE(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK                       (0x40U)
+#define I2C_FLT_STOPF_SHIFT                      (6U)
+#define I2C_FLT_STOPF(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK                        (0x80U)
+#define I2C_FLT_SHEN_SHIFT                       (7U)
+#define I2C_FLT_SHEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
+
+/*! @name RA - I2C Range Address register */
+#define I2C_RA_RAD_MASK                          (0xFEU)
+#define I2C_RA_RAD_SHIFT                         (1U)
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
+
+/*! @name SMB - I2C SMBus Control and Status register */
+#define I2C_SMB_SHTF2IE_MASK                     (0x1U)
+#define I2C_SMB_SHTF2IE_SHIFT                    (0U)
+#define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK                       (0x2U)
+#define I2C_SMB_SHTF2_SHIFT                      (1U)
+#define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK                       (0x4U)
+#define I2C_SMB_SHTF1_SHIFT                      (2U)
+#define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK                        (0x8U)
+#define I2C_SMB_SLTF_SHIFT                       (3U)
+#define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK                      (0x10U)
+#define I2C_SMB_TCKSEL_SHIFT                     (4U)
+#define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK                     (0x20U)
+#define I2C_SMB_SIICAEN_SHIFT                    (5U)
+#define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK                     (0x40U)
+#define I2C_SMB_ALERTEN_SHIFT                    (6U)
+#define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK                        (0x80U)
+#define I2C_SMB_FACK_SHIFT                       (7U)
+#define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
+
+/*! @name A2 - I2C Address Register 2 */
+#define I2C_A2_SAD_MASK                          (0xFEU)
+#define I2C_A2_SAD_SHIFT                         (1U)
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
+
+/*! @name SLTH - I2C SCL Low Timeout Register High */
+#define I2C_SLTH_SSLT_MASK                       (0xFFU)
+#define I2C_SLTH_SSLT_SHIFT                      (0U)
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
+
+/*! @name SLTL - I2C SCL Low Timeout Register Low */
+#define I2C_SLTL_SSLT_MASK                       (0xFFU)
+#define I2C_SLTL_SSLT_SHIFT                      (0U)
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
+
+/*! @name S2 - I2C Status register 2 */
+#define I2C_S2_EMPTY_MASK                        (0x1U)
+#define I2C_S2_EMPTY_SHIFT                       (0U)
+#define I2C_S2_EMPTY(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK)
+#define I2C_S2_ERROR_MASK                        (0x2U)
+#define I2C_S2_ERROR_SHIFT                       (1U)
+#define I2C_S2_ERROR(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK)
+#define I2C_S2_DFEN_MASK                         (0x4U)
+#define I2C_S2_DFEN_SHIFT                        (2U)
+#define I2C_S2_DFEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_S2_DFEN_SHIFT)) & I2C_S2_DFEN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- INTMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INTMUX_Peripheral_Access_Layer INTMUX Peripheral Access Layer
+ * @{
+ */
+
+/** INTMUX - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x40 */
+    __IO uint32_t CHn_CSR;                           /**< Channel n Control Status Register, array offset: 0x0, array step: 0x40 */
+    __I  uint32_t CHn_VEC;                           /**< Channel n Vector Number Register, array offset: 0x4, array step: 0x40 */
+         uint8_t RESERVED_0[8];
+    __IO uint32_t CHn_IER_31_0;                      /**< Channel n Interrupt Enable Register, array offset: 0x10, array step: 0x40 */
+         uint8_t RESERVED_1[12];
+    __I  uint32_t CHn_IPR_31_0;                      /**< Channel n Interrupt Pending Register, array offset: 0x20, array step: 0x40 */
+         uint8_t RESERVED_2[28];
+  } CHANNEL[4];
+} INTMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- INTMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INTMUX_Register_Masks INTMUX Register Masks
+ * @{
+ */
+
+/*! @name CHn_CSR - Channel n Control Status Register */
+#define INTMUX_CHn_CSR_RST_MASK                  (0x1U)
+#define INTMUX_CHn_CSR_RST_SHIFT                 (0U)
+#define INTMUX_CHn_CSR_RST(x)                    (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_RST_SHIFT)) & INTMUX_CHn_CSR_RST_MASK)
+#define INTMUX_CHn_CSR_AND_MASK                  (0x2U)
+#define INTMUX_CHn_CSR_AND_SHIFT                 (1U)
+#define INTMUX_CHn_CSR_AND(x)                    (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_AND_SHIFT)) & INTMUX_CHn_CSR_AND_MASK)
+#define INTMUX_CHn_CSR_IRQN_MASK                 (0x30U)
+#define INTMUX_CHn_CSR_IRQN_SHIFT                (4U)
+#define INTMUX_CHn_CSR_IRQN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQN_SHIFT)) & INTMUX_CHn_CSR_IRQN_MASK)
+#define INTMUX_CHn_CSR_CHIN_MASK                 (0xF00U)
+#define INTMUX_CHn_CSR_CHIN_SHIFT                (8U)
+#define INTMUX_CHn_CSR_CHIN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_CHIN_SHIFT)) & INTMUX_CHn_CSR_CHIN_MASK)
+#define INTMUX_CHn_CSR_IRQP_MASK                 (0x80000000U)
+#define INTMUX_CHn_CSR_IRQP_SHIFT                (31U)
+#define INTMUX_CHn_CSR_IRQP(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK)
+
+/* The count of INTMUX_CHn_CSR */
+#define INTMUX_CHn_CSR_COUNT                     (4U)
+
+/*! @name CHn_VEC - Channel n Vector Number Register */
+#define INTMUX_CHn_VEC_VECN_MASK                 (0x3FFCU)
+#define INTMUX_CHn_VEC_VECN_SHIFT                (2U)
+#define INTMUX_CHn_VEC_VECN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_VEC_VECN_SHIFT)) & INTMUX_CHn_VEC_VECN_MASK)
+
+/* The count of INTMUX_CHn_VEC */
+#define INTMUX_CHn_VEC_COUNT                     (4U)
+
+/*! @name CHn_IER_31_0 - Channel n Interrupt Enable Register */
+#define INTMUX_CHn_IER_31_0_INTE_MASK            (0xFFFFFFFFU)
+#define INTMUX_CHn_IER_31_0_INTE_SHIFT           (0U)
+#define INTMUX_CHn_IER_31_0_INTE(x)              (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IER_31_0_INTE_SHIFT)) & INTMUX_CHn_IER_31_0_INTE_MASK)
+
+/* The count of INTMUX_CHn_IER_31_0 */
+#define INTMUX_CHn_IER_31_0_COUNT                (4U)
+
+/*! @name CHn_IPR_31_0 - Channel n Interrupt Pending Register */
+#define INTMUX_CHn_IPR_31_0_INTP_MASK            (0xFFFFFFFFU)
+#define INTMUX_CHn_IPR_31_0_INTP_SHIFT           (0U)
+#define INTMUX_CHn_IPR_31_0_INTP(x)              (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IPR_31_0_INTP_SHIFT)) & INTMUX_CHn_IPR_31_0_INTP_MASK)
+
+/* The count of INTMUX_CHn_IPR_31_0 */
+#define INTMUX_CHn_IPR_31_0_COUNT                (4U)
+
+
+/*!
+ * @}
+ */ /* end of group INTMUX_Register_Masks */
+
+
+/* INTMUX - Peripheral instance base addresses */
+/** Peripheral INTMUX0 base address */
+#define INTMUX0_BASE                             (0x40024000u)
+/** Peripheral INTMUX0 base pointer */
+#define INTMUX0                                  ((INTMUX_Type *)INTMUX0_BASE)
+/** Array initializer of INTMUX peripheral base addresses */
+#define INTMUX_BASE_ADDRS                        { INTMUX0_BASE }
+/** Array initializer of INTMUX peripheral base pointers */
+#define INTMUX_BASE_PTRS                         { INTMUX0 }
+/** Interrupt vectors for the INTMUX peripheral type */
+#define INTMUX_IRQS                              { INTMUX0_0_IRQn, INTMUX0_1_IRQn, INTMUX0_2_IRQn, INTMUX0_3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group INTMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
+  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
+  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
+  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
+  __IO uint8_t PE5;                                /**< LLWU Pin Enable 5 register, offset: 0x4 */
+  __IO uint8_t PE6;                                /**< LLWU Pin Enable 6 register, offset: 0x5 */
+  __IO uint8_t PE7;                                /**< LLWU Pin Enable 7 register, offset: 0x6 */
+  __IO uint8_t PE8;                                /**< LLWU Pin Enable 8 register, offset: 0x7 */
+  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x8 */
+  __IO uint8_t PF1;                                /**< LLWU Pin Flag 1 register, offset: 0x9 */
+  __IO uint8_t PF2;                                /**< LLWU Pin Flag 2 register, offset: 0xA */
+  __IO uint8_t PF3;                                /**< LLWU Pin Flag 3 register, offset: 0xB */
+  __IO uint8_t PF4;                                /**< LLWU Pin Flag 4 register, offset: 0xC */
+  __I  uint8_t MF5;                                /**< LLWU Module Flag 5 register, offset: 0xD */
+  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0xE */
+  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0xF */
+  __IO uint8_t FILT3;                              /**< LLWU Pin Filter 3 register, offset: 0x10 */
+  __IO uint8_t FILT4;                              /**< LLWU Pin Filter 4 register, offset: 0x11 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/*! @name PE1 - LLWU Pin Enable 1 register */
+#define LLWU_PE1_WUPE0_MASK                      (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT                     (0U)
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT                     (2U)
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT                     (4U)
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT                     (6U)
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+
+/*! @name PE2 - LLWU Pin Enable 2 register */
+#define LLWU_PE2_WUPE4_MASK                      (0x3U)
+#define LLWU_PE2_WUPE4_SHIFT                     (0U)
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      (0xCU)
+#define LLWU_PE2_WUPE5_SHIFT                     (2U)
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      (0x30U)
+#define LLWU_PE2_WUPE6_SHIFT                     (4U)
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      (0xC0U)
+#define LLWU_PE2_WUPE7_SHIFT                     (6U)
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+
+/*! @name PE3 - LLWU Pin Enable 3 register */
+#define LLWU_PE3_WUPE8_MASK                      (0x3U)
+#define LLWU_PE3_WUPE8_SHIFT                     (0U)
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      (0xCU)
+#define LLWU_PE3_WUPE9_SHIFT                     (2U)
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     (0x30U)
+#define LLWU_PE3_WUPE10_SHIFT                    (4U)
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     (0xC0U)
+#define LLWU_PE3_WUPE11_SHIFT                    (6U)
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+
+/*! @name PE4 - LLWU Pin Enable 4 register */
+#define LLWU_PE4_WUPE12_MASK                     (0x3U)
+#define LLWU_PE4_WUPE12_SHIFT                    (0U)
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     (0xCU)
+#define LLWU_PE4_WUPE13_SHIFT                    (2U)
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     (0x30U)
+#define LLWU_PE4_WUPE14_SHIFT                    (4U)
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     (0xC0U)
+#define LLWU_PE4_WUPE15_SHIFT                    (6U)
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+
+/*! @name PE5 - LLWU Pin Enable 5 register */
+#define LLWU_PE5_WUPE16_MASK                     (0x3U)
+#define LLWU_PE5_WUPE16_SHIFT                    (0U)
+#define LLWU_PE5_WUPE16(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK)
+#define LLWU_PE5_WUPE17_MASK                     (0xCU)
+#define LLWU_PE5_WUPE17_SHIFT                    (2U)
+#define LLWU_PE5_WUPE17(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK)
+#define LLWU_PE5_WUPE18_MASK                     (0x30U)
+#define LLWU_PE5_WUPE18_SHIFT                    (4U)
+#define LLWU_PE5_WUPE18(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK)
+#define LLWU_PE5_WUPE19_MASK                     (0xC0U)
+#define LLWU_PE5_WUPE19_SHIFT                    (6U)
+#define LLWU_PE5_WUPE19(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK)
+
+/*! @name PE6 - LLWU Pin Enable 6 register */
+#define LLWU_PE6_WUPE20_MASK                     (0x3U)
+#define LLWU_PE6_WUPE20_SHIFT                    (0U)
+#define LLWU_PE6_WUPE20(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK)
+#define LLWU_PE6_WUPE21_MASK                     (0xCU)
+#define LLWU_PE6_WUPE21_SHIFT                    (2U)
+#define LLWU_PE6_WUPE21(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK)
+#define LLWU_PE6_WUPE22_MASK                     (0x30U)
+#define LLWU_PE6_WUPE22_SHIFT                    (4U)
+#define LLWU_PE6_WUPE22(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK)
+#define LLWU_PE6_WUPE23_MASK                     (0xC0U)
+#define LLWU_PE6_WUPE23_SHIFT                    (6U)
+#define LLWU_PE6_WUPE23(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK)
+
+/*! @name PE7 - LLWU Pin Enable 7 register */
+#define LLWU_PE7_WUPE24_MASK                     (0x3U)
+#define LLWU_PE7_WUPE24_SHIFT                    (0U)
+#define LLWU_PE7_WUPE24(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK)
+#define LLWU_PE7_WUPE25_MASK                     (0xCU)
+#define LLWU_PE7_WUPE25_SHIFT                    (2U)
+#define LLWU_PE7_WUPE25(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK)
+#define LLWU_PE7_WUPE26_MASK                     (0x30U)
+#define LLWU_PE7_WUPE26_SHIFT                    (4U)
+#define LLWU_PE7_WUPE26(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK)
+#define LLWU_PE7_WUPE27_MASK                     (0xC0U)
+#define LLWU_PE7_WUPE27_SHIFT                    (6U)
+#define LLWU_PE7_WUPE27(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK)
+
+/*! @name PE8 - LLWU Pin Enable 8 register */
+#define LLWU_PE8_WUPE28_MASK                     (0x3U)
+#define LLWU_PE8_WUPE28_SHIFT                    (0U)
+#define LLWU_PE8_WUPE28(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK)
+#define LLWU_PE8_WUPE29_MASK                     (0xCU)
+#define LLWU_PE8_WUPE29_SHIFT                    (2U)
+#define LLWU_PE8_WUPE29(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK)
+#define LLWU_PE8_WUPE30_MASK                     (0x30U)
+#define LLWU_PE8_WUPE30_SHIFT                    (4U)
+#define LLWU_PE8_WUPE30(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK)
+#define LLWU_PE8_WUPE31_MASK                     (0xC0U)
+#define LLWU_PE8_WUPE31_SHIFT                    (6U)
+#define LLWU_PE8_WUPE31(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK)
+
+/*! @name ME - LLWU Module Enable register */
+#define LLWU_ME_WUME0_MASK                       (0x1U)
+#define LLWU_ME_WUME0_SHIFT                      (0U)
+#define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK                       (0x2U)
+#define LLWU_ME_WUME1_SHIFT                      (1U)
+#define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK                       (0x4U)
+#define LLWU_ME_WUME2_SHIFT                      (2U)
+#define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK                       (0x8U)
+#define LLWU_ME_WUME3_SHIFT                      (3U)
+#define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK                       (0x10U)
+#define LLWU_ME_WUME4_SHIFT                      (4U)
+#define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK                       (0x20U)
+#define LLWU_ME_WUME5_SHIFT                      (5U)
+#define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK                       (0x40U)
+#define LLWU_ME_WUME6_SHIFT                      (6U)
+#define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK                       (0x80U)
+#define LLWU_ME_WUME7_SHIFT                      (7U)
+#define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+
+/*! @name PF1 - LLWU Pin Flag 1 register */
+#define LLWU_PF1_WUF0_MASK                       (0x1U)
+#define LLWU_PF1_WUF0_SHIFT                      (0U)
+#define LLWU_PF1_WUF0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK)
+#define LLWU_PF1_WUF1_MASK                       (0x2U)
+#define LLWU_PF1_WUF1_SHIFT                      (1U)
+#define LLWU_PF1_WUF1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK)
+#define LLWU_PF1_WUF2_MASK                       (0x4U)
+#define LLWU_PF1_WUF2_SHIFT                      (2U)
+#define LLWU_PF1_WUF2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK)
+#define LLWU_PF1_WUF3_MASK                       (0x8U)
+#define LLWU_PF1_WUF3_SHIFT                      (3U)
+#define LLWU_PF1_WUF3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK)
+#define LLWU_PF1_WUF4_MASK                       (0x10U)
+#define LLWU_PF1_WUF4_SHIFT                      (4U)
+#define LLWU_PF1_WUF4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK)
+#define LLWU_PF1_WUF5_MASK                       (0x20U)
+#define LLWU_PF1_WUF5_SHIFT                      (5U)
+#define LLWU_PF1_WUF5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK)
+#define LLWU_PF1_WUF6_MASK                       (0x40U)
+#define LLWU_PF1_WUF6_SHIFT                      (6U)
+#define LLWU_PF1_WUF6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK)
+#define LLWU_PF1_WUF7_MASK                       (0x80U)
+#define LLWU_PF1_WUF7_SHIFT                      (7U)
+#define LLWU_PF1_WUF7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK)
+
+/*! @name PF2 - LLWU Pin Flag 2 register */
+#define LLWU_PF2_WUF8_MASK                       (0x1U)
+#define LLWU_PF2_WUF8_SHIFT                      (0U)
+#define LLWU_PF2_WUF8(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK)
+#define LLWU_PF2_WUF9_MASK                       (0x2U)
+#define LLWU_PF2_WUF9_SHIFT                      (1U)
+#define LLWU_PF2_WUF9(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK)
+#define LLWU_PF2_WUF10_MASK                      (0x4U)
+#define LLWU_PF2_WUF10_SHIFT                     (2U)
+#define LLWU_PF2_WUF10(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK)
+#define LLWU_PF2_WUF11_MASK                      (0x8U)
+#define LLWU_PF2_WUF11_SHIFT                     (3U)
+#define LLWU_PF2_WUF11(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK)
+#define LLWU_PF2_WUF12_MASK                      (0x10U)
+#define LLWU_PF2_WUF12_SHIFT                     (4U)
+#define LLWU_PF2_WUF12(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK)
+#define LLWU_PF2_WUF13_MASK                      (0x20U)
+#define LLWU_PF2_WUF13_SHIFT                     (5U)
+#define LLWU_PF2_WUF13(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK)
+#define LLWU_PF2_WUF14_MASK                      (0x40U)
+#define LLWU_PF2_WUF14_SHIFT                     (6U)
+#define LLWU_PF2_WUF14(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK)
+#define LLWU_PF2_WUF15_MASK                      (0x80U)
+#define LLWU_PF2_WUF15_SHIFT                     (7U)
+#define LLWU_PF2_WUF15(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK)
+
+/*! @name PF3 - LLWU Pin Flag 3 register */
+#define LLWU_PF3_WUF16_MASK                      (0x1U)
+#define LLWU_PF3_WUF16_SHIFT                     (0U)
+#define LLWU_PF3_WUF16(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK)
+#define LLWU_PF3_WUF17_MASK                      (0x2U)
+#define LLWU_PF3_WUF17_SHIFT                     (1U)
+#define LLWU_PF3_WUF17(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK)
+#define LLWU_PF3_WUF18_MASK                      (0x4U)
+#define LLWU_PF3_WUF18_SHIFT                     (2U)
+#define LLWU_PF3_WUF18(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK)
+#define LLWU_PF3_WUF19_MASK                      (0x8U)
+#define LLWU_PF3_WUF19_SHIFT                     (3U)
+#define LLWU_PF3_WUF19(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK)
+#define LLWU_PF3_WUF20_MASK                      (0x10U)
+#define LLWU_PF3_WUF20_SHIFT                     (4U)
+#define LLWU_PF3_WUF20(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK)
+#define LLWU_PF3_WUF21_MASK                      (0x20U)
+#define LLWU_PF3_WUF21_SHIFT                     (5U)
+#define LLWU_PF3_WUF21(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK)
+#define LLWU_PF3_WUF22_MASK                      (0x40U)
+#define LLWU_PF3_WUF22_SHIFT                     (6U)
+#define LLWU_PF3_WUF22(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK)
+#define LLWU_PF3_WUF23_MASK                      (0x80U)
+#define LLWU_PF3_WUF23_SHIFT                     (7U)
+#define LLWU_PF3_WUF23(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK)
+
+/*! @name PF4 - LLWU Pin Flag 4 register */
+#define LLWU_PF4_WUF24_MASK                      (0x1U)
+#define LLWU_PF4_WUF24_SHIFT                     (0U)
+#define LLWU_PF4_WUF24(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK)
+#define LLWU_PF4_WUF25_MASK                      (0x2U)
+#define LLWU_PF4_WUF25_SHIFT                     (1U)
+#define LLWU_PF4_WUF25(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK)
+#define LLWU_PF4_WUF26_MASK                      (0x4U)
+#define LLWU_PF4_WUF26_SHIFT                     (2U)
+#define LLWU_PF4_WUF26(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK)
+#define LLWU_PF4_WUF27_MASK                      (0x8U)
+#define LLWU_PF4_WUF27_SHIFT                     (3U)
+#define LLWU_PF4_WUF27(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK)
+#define LLWU_PF4_WUF28_MASK                      (0x10U)
+#define LLWU_PF4_WUF28_SHIFT                     (4U)
+#define LLWU_PF4_WUF28(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK)
+#define LLWU_PF4_WUF29_MASK                      (0x20U)
+#define LLWU_PF4_WUF29_SHIFT                     (5U)
+#define LLWU_PF4_WUF29(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK)
+#define LLWU_PF4_WUF30_MASK                      (0x40U)
+#define LLWU_PF4_WUF30_SHIFT                     (6U)
+#define LLWU_PF4_WUF30(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK)
+#define LLWU_PF4_WUF31_MASK                      (0x80U)
+#define LLWU_PF4_WUF31_SHIFT                     (7U)
+#define LLWU_PF4_WUF31(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK)
+
+/*! @name MF5 - LLWU Module Flag 5 register */
+#define LLWU_MF5_MWUF0_MASK                      (0x1U)
+#define LLWU_MF5_MWUF0_SHIFT                     (0U)
+#define LLWU_MF5_MWUF0(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK)
+#define LLWU_MF5_MWUF1_MASK                      (0x2U)
+#define LLWU_MF5_MWUF1_SHIFT                     (1U)
+#define LLWU_MF5_MWUF1(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK)
+#define LLWU_MF5_MWUF2_MASK                      (0x4U)
+#define LLWU_MF5_MWUF2_SHIFT                     (2U)
+#define LLWU_MF5_MWUF2(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK)
+#define LLWU_MF5_MWUF3_MASK                      (0x8U)
+#define LLWU_MF5_MWUF3_SHIFT                     (3U)
+#define LLWU_MF5_MWUF3(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK)
+#define LLWU_MF5_MWUF4_MASK                      (0x10U)
+#define LLWU_MF5_MWUF4_SHIFT                     (4U)
+#define LLWU_MF5_MWUF4(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK)
+#define LLWU_MF5_MWUF5_MASK                      (0x20U)
+#define LLWU_MF5_MWUF5_SHIFT                     (5U)
+#define LLWU_MF5_MWUF5(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK)
+#define LLWU_MF5_MWUF6_MASK                      (0x40U)
+#define LLWU_MF5_MWUF6_SHIFT                     (6U)
+#define LLWU_MF5_MWUF6(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK)
+#define LLWU_MF5_MWUF7_MASK                      (0x80U)
+#define LLWU_MF5_MWUF7_SHIFT                     (7U)
+#define LLWU_MF5_MWUF7(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK)
+
+/*! @name FILT1 - LLWU Pin Filter 1 register */
+#define LLWU_FILT1_FILTSEL_MASK                  (0x1FU)
+#define LLWU_FILT1_FILTSEL_SHIFT                 (0U)
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK                    (0x60U)
+#define LLWU_FILT1_FILTE_SHIFT                   (5U)
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK                    (0x80U)
+#define LLWU_FILT1_FILTF_SHIFT                   (7U)
+#define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
+
+/*! @name FILT2 - LLWU Pin Filter 2 register */
+#define LLWU_FILT2_FILTSEL_MASK                  (0x1FU)
+#define LLWU_FILT2_FILTSEL_SHIFT                 (0U)
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK                    (0x60U)
+#define LLWU_FILT2_FILTE_SHIFT                   (5U)
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK                    (0x80U)
+#define LLWU_FILT2_FILTF_SHIFT                   (7U)
+#define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
+
+/*! @name FILT3 - LLWU Pin Filter 3 register */
+#define LLWU_FILT3_FILTSEL_MASK                  (0x1FU)
+#define LLWU_FILT3_FILTSEL_SHIFT                 (0U)
+#define LLWU_FILT3_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTSEL_SHIFT)) & LLWU_FILT3_FILTSEL_MASK)
+#define LLWU_FILT3_FILTE_MASK                    (0x60U)
+#define LLWU_FILT3_FILTE_SHIFT                   (5U)
+#define LLWU_FILT3_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTE_SHIFT)) & LLWU_FILT3_FILTE_MASK)
+#define LLWU_FILT3_FILTF_MASK                    (0x80U)
+#define LLWU_FILT3_FILTF_SHIFT                   (7U)
+#define LLWU_FILT3_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTF_SHIFT)) & LLWU_FILT3_FILTF_MASK)
+
+/*! @name FILT4 - LLWU Pin Filter 4 register */
+#define LLWU_FILT4_FILTSEL_MASK                  (0x1FU)
+#define LLWU_FILT4_FILTSEL_SHIFT                 (0U)
+#define LLWU_FILT4_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTSEL_SHIFT)) & LLWU_FILT4_FILTSEL_MASK)
+#define LLWU_FILT4_FILTE_MASK                    (0x60U)
+#define LLWU_FILT4_FILTE_SHIFT                   (5U)
+#define LLWU_FILT4_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTE_SHIFT)) & LLWU_FILT4_FILTE_MASK)
+#define LLWU_FILT4_FILTF_MASK                    (0x80U)
+#define LLWU_FILT4_FILTF_SHIFT                   (7U)
+#define LLWU_FILT4_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTF_SHIFT)) & LLWU_FILT4_FILTF_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS                          { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/*! @name CSR - Low Power Timer Control Status Register */
+#define LPTMR_CSR_TEN_MASK                       (0x1U)
+#define LPTMR_CSR_TEN_SHIFT                      (0U)
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK                       (0x2U)
+#define LPTMR_CSR_TMS_SHIFT                      (1U)
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK                       (0x4U)
+#define LPTMR_CSR_TFC_SHIFT                      (2U)
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK                       (0x8U)
+#define LPTMR_CSR_TPP_SHIFT                      (3U)
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK                       (0x30U)
+#define LPTMR_CSR_TPS_SHIFT                      (4U)
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       (0x40U)
+#define LPTMR_CSR_TIE_SHIFT                      (6U)
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK                       (0x80U)
+#define LPTMR_CSR_TCF_SHIFT                      (7U)
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+
+/*! @name PSR - Low Power Timer Prescale Register */
+#define LPTMR_PSR_PCS_MASK                       (0x3U)
+#define LPTMR_PSR_PCS_SHIFT                      (0U)
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT                     (2U)
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+
+/*! @name CMR - Low Power Timer Compare Register */
+#define LPTMR_CMR_COMPARE_MASK                   (0xFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT                  (0U)
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+
+/*! @name CNR - Low Power Timer Counter Register */
+#define LPTMR_CNR_COUNTER_MASK                   (0xFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT                  (0U)
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+/** Peripheral LPTMR1 base address */
+#define LPTMR1_BASE                              (0x40044000u)
+/** Peripheral LPTMR1 base pointer */
+#define LPTMR1                                   ((LPTMR_Type *)LPTMR1_BASE)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE, LPTMR1_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0, LPTMR1 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn, LPTMR1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @{
+ */
+
+/** LPUART - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x0 */
+  __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x4 */
+  __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x8 */
+  __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0xC */
+  __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x10 */
+  __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x14 */
+  __IO uint32_t FIFO;                              /**< LPUART FIFO Register, offset: 0x18 */
+  __IO uint32_t WATER;                             /**< LPUART Watermark Register, offset: 0x1C */
+} LPUART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @{
+ */
+
+/*! @name BAUD - LPUART Baud Rate Register */
+#define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
+#define LPUART_BAUD_SBR_SHIFT                    (0U)
+#define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
+#define LPUART_BAUD_SBNS_MASK                    (0x2000U)
+#define LPUART_BAUD_SBNS_SHIFT                   (13U)
+#define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
+#define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
+#define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
+#define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
+#define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
+#define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
+#define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
+#define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
+#define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
+#define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
+#define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
+#define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
+#define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
+#define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
+#define LPUART_BAUD_MATCFG_SHIFT                 (18U)
+#define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
+#define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
+#define LPUART_BAUD_RDMAE_SHIFT                  (21U)
+#define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
+#define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
+#define LPUART_BAUD_TDMAE_SHIFT                  (23U)
+#define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
+#define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
+#define LPUART_BAUD_OSR_SHIFT                    (24U)
+#define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
+#define LPUART_BAUD_M10_MASK                     (0x20000000U)
+#define LPUART_BAUD_M10_SHIFT                    (29U)
+#define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
+#define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
+#define LPUART_BAUD_MAEN2_SHIFT                  (30U)
+#define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
+#define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
+#define LPUART_BAUD_MAEN1_SHIFT                  (31U)
+#define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
+
+/*! @name STAT - LPUART Status Register */
+#define LPUART_STAT_MA2F_MASK                    (0x4000U)
+#define LPUART_STAT_MA2F_SHIFT                   (14U)
+#define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
+#define LPUART_STAT_MA1F_MASK                    (0x8000U)
+#define LPUART_STAT_MA1F_SHIFT                   (15U)
+#define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
+#define LPUART_STAT_PF_MASK                      (0x10000U)
+#define LPUART_STAT_PF_SHIFT                     (16U)
+#define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
+#define LPUART_STAT_FE_MASK                      (0x20000U)
+#define LPUART_STAT_FE_SHIFT                     (17U)
+#define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
+#define LPUART_STAT_NF_MASK                      (0x40000U)
+#define LPUART_STAT_NF_SHIFT                     (18U)
+#define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
+#define LPUART_STAT_OR_MASK                      (0x80000U)
+#define LPUART_STAT_OR_SHIFT                     (19U)
+#define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
+#define LPUART_STAT_IDLE_MASK                    (0x100000U)
+#define LPUART_STAT_IDLE_SHIFT                   (20U)
+#define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
+#define LPUART_STAT_RDRF_MASK                    (0x200000U)
+#define LPUART_STAT_RDRF_SHIFT                   (21U)
+#define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
+#define LPUART_STAT_TC_MASK                      (0x400000U)
+#define LPUART_STAT_TC_SHIFT                     (22U)
+#define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
+#define LPUART_STAT_TDRE_MASK                    (0x800000U)
+#define LPUART_STAT_TDRE_SHIFT                   (23U)
+#define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
+#define LPUART_STAT_RAF_MASK                     (0x1000000U)
+#define LPUART_STAT_RAF_SHIFT                    (24U)
+#define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
+#define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
+#define LPUART_STAT_LBKDE_SHIFT                  (25U)
+#define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
+#define LPUART_STAT_BRK13_MASK                   (0x4000000U)
+#define LPUART_STAT_BRK13_SHIFT                  (26U)
+#define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
+#define LPUART_STAT_RWUID_MASK                   (0x8000000U)
+#define LPUART_STAT_RWUID_SHIFT                  (27U)
+#define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
+#define LPUART_STAT_RXINV_MASK                   (0x10000000U)
+#define LPUART_STAT_RXINV_SHIFT                  (28U)
+#define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
+#define LPUART_STAT_MSBF_MASK                    (0x20000000U)
+#define LPUART_STAT_MSBF_SHIFT                   (29U)
+#define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
+#define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
+#define LPUART_STAT_RXEDGIF_SHIFT                (30U)
+#define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
+#define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
+#define LPUART_STAT_LBKDIF_SHIFT                 (31U)
+#define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
+
+/*! @name CTRL - LPUART Control Register */
+#define LPUART_CTRL_PT_MASK                      (0x1U)
+#define LPUART_CTRL_PT_SHIFT                     (0U)
+#define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
+#define LPUART_CTRL_PE_MASK                      (0x2U)
+#define LPUART_CTRL_PE_SHIFT                     (1U)
+#define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
+#define LPUART_CTRL_ILT_MASK                     (0x4U)
+#define LPUART_CTRL_ILT_SHIFT                    (2U)
+#define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
+#define LPUART_CTRL_WAKE_MASK                    (0x8U)
+#define LPUART_CTRL_WAKE_SHIFT                   (3U)
+#define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
+#define LPUART_CTRL_M_MASK                       (0x10U)
+#define LPUART_CTRL_M_SHIFT                      (4U)
+#define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
+#define LPUART_CTRL_RSRC_MASK                    (0x20U)
+#define LPUART_CTRL_RSRC_SHIFT                   (5U)
+#define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
+#define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
+#define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
+#define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
+#define LPUART_CTRL_LOOPS_MASK                   (0x80U)
+#define LPUART_CTRL_LOOPS_SHIFT                  (7U)
+#define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
+#define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
+#define LPUART_CTRL_IDLECFG_SHIFT                (8U)
+#define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
+#define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
+#define LPUART_CTRL_MA2IE_SHIFT                  (14U)
+#define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
+#define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
+#define LPUART_CTRL_MA1IE_SHIFT                  (15U)
+#define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
+#define LPUART_CTRL_SBK_MASK                     (0x10000U)
+#define LPUART_CTRL_SBK_SHIFT                    (16U)
+#define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
+#define LPUART_CTRL_RWU_MASK                     (0x20000U)
+#define LPUART_CTRL_RWU_SHIFT                    (17U)
+#define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
+#define LPUART_CTRL_RE_MASK                      (0x40000U)
+#define LPUART_CTRL_RE_SHIFT                     (18U)
+#define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
+#define LPUART_CTRL_TE_MASK                      (0x80000U)
+#define LPUART_CTRL_TE_SHIFT                     (19U)
+#define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
+#define LPUART_CTRL_ILIE_MASK                    (0x100000U)
+#define LPUART_CTRL_ILIE_SHIFT                   (20U)
+#define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
+#define LPUART_CTRL_RIE_MASK                     (0x200000U)
+#define LPUART_CTRL_RIE_SHIFT                    (21U)
+#define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
+#define LPUART_CTRL_TCIE_MASK                    (0x400000U)
+#define LPUART_CTRL_TCIE_SHIFT                   (22U)
+#define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
+#define LPUART_CTRL_TIE_MASK                     (0x800000U)
+#define LPUART_CTRL_TIE_SHIFT                    (23U)
+#define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
+#define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
+#define LPUART_CTRL_PEIE_SHIFT                   (24U)
+#define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
+#define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
+#define LPUART_CTRL_FEIE_SHIFT                   (25U)
+#define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
+#define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
+#define LPUART_CTRL_NEIE_SHIFT                   (26U)
+#define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
+#define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
+#define LPUART_CTRL_ORIE_SHIFT                   (27U)
+#define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
+#define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
+#define LPUART_CTRL_TXINV_SHIFT                  (28U)
+#define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
+#define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
+#define LPUART_CTRL_TXDIR_SHIFT                  (29U)
+#define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
+#define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
+#define LPUART_CTRL_R9T8_SHIFT                   (30U)
+#define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
+#define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
+#define LPUART_CTRL_R8T9_SHIFT                   (31U)
+#define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
+
+/*! @name DATA - LPUART Data Register */
+#define LPUART_DATA_R0T0_MASK                    (0x1U)
+#define LPUART_DATA_R0T0_SHIFT                   (0U)
+#define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
+#define LPUART_DATA_R1T1_MASK                    (0x2U)
+#define LPUART_DATA_R1T1_SHIFT                   (1U)
+#define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
+#define LPUART_DATA_R2T2_MASK                    (0x4U)
+#define LPUART_DATA_R2T2_SHIFT                   (2U)
+#define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
+#define LPUART_DATA_R3T3_MASK                    (0x8U)
+#define LPUART_DATA_R3T3_SHIFT                   (3U)
+#define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
+#define LPUART_DATA_R4T4_MASK                    (0x10U)
+#define LPUART_DATA_R4T4_SHIFT                   (4U)
+#define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
+#define LPUART_DATA_R5T5_MASK                    (0x20U)
+#define LPUART_DATA_R5T5_SHIFT                   (5U)
+#define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
+#define LPUART_DATA_R6T6_MASK                    (0x40U)
+#define LPUART_DATA_R6T6_SHIFT                   (6U)
+#define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
+#define LPUART_DATA_R7T7_MASK                    (0x80U)
+#define LPUART_DATA_R7T7_SHIFT                   (7U)
+#define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
+#define LPUART_DATA_R8T8_MASK                    (0x100U)
+#define LPUART_DATA_R8T8_SHIFT                   (8U)
+#define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
+#define LPUART_DATA_R9T9_MASK                    (0x200U)
+#define LPUART_DATA_R9T9_SHIFT                   (9U)
+#define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
+#define LPUART_DATA_IDLINE_MASK                  (0x800U)
+#define LPUART_DATA_IDLINE_SHIFT                 (11U)
+#define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
+#define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
+#define LPUART_DATA_RXEMPT_SHIFT                 (12U)
+#define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
+#define LPUART_DATA_FRETSC_MASK                  (0x2000U)
+#define LPUART_DATA_FRETSC_SHIFT                 (13U)
+#define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
+#define LPUART_DATA_PARITYE_MASK                 (0x4000U)
+#define LPUART_DATA_PARITYE_SHIFT                (14U)
+#define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
+#define LPUART_DATA_NOISY_MASK                   (0x8000U)
+#define LPUART_DATA_NOISY_SHIFT                  (15U)
+#define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
+
+/*! @name MATCH - LPUART Match Address Register */
+#define LPUART_MATCH_MA1_MASK                    (0x3FFU)
+#define LPUART_MATCH_MA1_SHIFT                   (0U)
+#define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
+#define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
+#define LPUART_MATCH_MA2_SHIFT                   (16U)
+#define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
+
+/*! @name MODIR - LPUART Modem IrDA Register */
+#define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
+#define LPUART_MODIR_TXCTSE_SHIFT                (0U)
+#define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
+#define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
+#define LPUART_MODIR_TXRTSE_SHIFT                (1U)
+#define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
+#define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
+#define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
+#define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
+#define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
+#define LPUART_MODIR_RXRTSE_SHIFT                (3U)
+#define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
+#define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
+#define LPUART_MODIR_TXCTSC_SHIFT                (4U)
+#define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
+#define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
+#define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
+#define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
+#define LPUART_MODIR_RTSWATER_MASK               (0xFF00U)
+#define LPUART_MODIR_RTSWATER_SHIFT              (8U)
+#define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
+#define LPUART_MODIR_TNP_MASK                    (0x30000U)
+#define LPUART_MODIR_TNP_SHIFT                   (16U)
+#define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
+#define LPUART_MODIR_IREN_MASK                   (0x40000U)
+#define LPUART_MODIR_IREN_SHIFT                  (18U)
+#define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
+
+/*! @name FIFO - LPUART FIFO Register */
+#define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
+#define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
+#define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
+#define LPUART_FIFO_RXFE_MASK                    (0x8U)
+#define LPUART_FIFO_RXFE_SHIFT                   (3U)
+#define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
+#define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
+#define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
+#define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
+#define LPUART_FIFO_TXFE_MASK                    (0x80U)
+#define LPUART_FIFO_TXFE_SHIFT                   (7U)
+#define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
+#define LPUART_FIFO_RXUFE_MASK                   (0x100U)
+#define LPUART_FIFO_RXUFE_SHIFT                  (8U)
+#define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
+#define LPUART_FIFO_TXOFE_MASK                   (0x200U)
+#define LPUART_FIFO_TXOFE_SHIFT                  (9U)
+#define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
+#define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
+#define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
+#define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
+#define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
+#define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
+#define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
+#define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
+#define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
+#define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
+#define LPUART_FIFO_RXUF_MASK                    (0x10000U)
+#define LPUART_FIFO_RXUF_SHIFT                   (16U)
+#define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
+#define LPUART_FIFO_TXOF_MASK                    (0x20000U)
+#define LPUART_FIFO_TXOF_SHIFT                   (17U)
+#define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
+#define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
+#define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
+#define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
+#define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
+#define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
+#define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
+
+/*! @name WATER - LPUART Watermark Register */
+#define LPUART_WATER_TXWATER_MASK                (0xFFU)
+#define LPUART_WATER_TXWATER_SHIFT               (0U)
+#define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
+#define LPUART_WATER_TXCOUNT_MASK                (0xFF00U)
+#define LPUART_WATER_TXCOUNT_SHIFT               (8U)
+#define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
+#define LPUART_WATER_RXWATER_MASK                (0xFF0000U)
+#define LPUART_WATER_RXWATER_SHIFT               (16U)
+#define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
+#define LPUART_WATER_RXCOUNT_MASK                (0xFF000000U)
+#define LPUART_WATER_RXCOUNT_SHIFT               (24U)
+#define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Masks */
+
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE                             (0x40054000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
+/** Peripheral LPUART1 base address */
+#define LPUART1_BASE                             (0x40055000u)
+/** Peripheral LPUART1 base pointer */
+#define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
+/** Peripheral LPUART2 base address */
+#define LPUART2_BASE                             (0x40056000u)
+/** Peripheral LPUART2 base pointer */
+#define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS                         { LPUART0, LPUART1, LPUART2 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS                        { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn }
+#define LPUART_ERR_IRQS                          { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPUART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LTC_Peripheral_Access_Layer LTC Peripheral Access Layer
+ * @{
+ */
+
+/** LTC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    __IO uint32_t MD;                                /**< LTC Mode Register (non-PKHA/non-RNG use), offset: 0x0 */
+    __IO uint32_t MDPK;                              /**< LTC Mode Register (PublicKey), offset: 0x0 */
+  };
+       uint8_t RESERVED_0[4];
+  __IO uint32_t KS;                                /**< LTC Key Size Register, offset: 0x8 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t DS;                                /**< LTC Data Size Register, offset: 0x10 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t ICVS;                              /**< LTC ICV Size Register, offset: 0x18 */
+       uint8_t RESERVED_3[20];
+  __IO uint32_t COM;                               /**< LTC Command Register, offset: 0x30 */
+  __IO uint32_t CTL;                               /**< LTC Control Register, offset: 0x34 */
+       uint8_t RESERVED_4[8];
+  __IO uint32_t CW;                                /**< LTC Clear Written Register, offset: 0x40 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t STA;                               /**< LTC Status Register, offset: 0x48 */
+  __I  uint32_t ESTA;                              /**< LTC Error Status Register, offset: 0x4C */
+       uint8_t RESERVED_6[8];
+  __IO uint32_t AADSZ;                             /**< LTC AAD Size Register, offset: 0x58 */
+       uint8_t RESERVED_7[4];
+  __IO uint32_t IVSZ;                              /**< LTC IV Size Register, offset: 0x60 */
+       uint8_t RESERVED_8[4];
+  __O  uint32_t DPAMS;                             /**< LTC DPA Mask Seed Register, offset: 0x68 */
+       uint8_t RESERVED_9[20];
+  __IO uint32_t PKASZ;                             /**< LTC PKHA A Size Register, offset: 0x80 */
+       uint8_t RESERVED_10[4];
+  __IO uint32_t PKBSZ;                             /**< LTC PKHA B Size Register, offset: 0x88 */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t PKNSZ;                             /**< LTC PKHA N Size Register, offset: 0x90 */
+       uint8_t RESERVED_12[4];
+  __IO uint32_t PKESZ;                             /**< LTC PKHA E Size Register, offset: 0x98 */
+       uint8_t RESERVED_13[100];
+  __IO uint32_t CTX[16];                           /**< LTC Context Register, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_14[192];
+  __IO uint32_t KEY[8];                            /**< LTC Key Registers, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_15[720];
+  __I  uint32_t VID1;                              /**< LTC Version ID Register, offset: 0x4F0 */
+  __I  uint32_t VID2;                              /**< LTC Version ID 2 Register, offset: 0x4F4 */
+  __I  uint32_t CHAVID;                            /**< LTC CHA Version ID Register, offset: 0x4F8 */
+       uint8_t RESERVED_16[708];
+  __I  uint32_t FIFOSTA;                           /**< LTC FIFO Status Register, offset: 0x7C0 */
+       uint8_t RESERVED_17[28];
+  __O  uint32_t IFIFO;                             /**< LTC Input Data FIFO, offset: 0x7E0 */
+       uint8_t RESERVED_18[12];
+  __I  uint32_t OFIFO;                             /**< LTC Output Data FIFO, offset: 0x7F0 */
+       uint8_t RESERVED_19[12];
+  union {                                          /* offset: 0x800 */
+    __IO uint32_t PKA[64];                           /**< LTC PKHA A 0 Register..LTC PKHA A 63 Register, array offset: 0x800, array step: 0x4 */
+    struct {                                         /* offset: 0x800 */
+      __IO uint32_t PKA0[16];                          /**< LTC PKHA A0 0 Register..LTC PKHA A0 15 Register, array offset: 0x800, array step: 0x4 */
+      __IO uint32_t PKA1[16];                          /**< LTC PKHA A1 0 Register..LTC PKHA A1 15 Register, array offset: 0x840, array step: 0x4 */
+      __IO uint32_t PKA2[16];                          /**< LTC PKHA A2 0 Register..LTC PKHA A2 15 Register, array offset: 0x880, array step: 0x4 */
+      __IO uint32_t PKA3[16];                          /**< LTC PKHA A3 0 Register..LTC PKHA A3 15 Register, array offset: 0x8C0, array step: 0x4 */
+    } PKA_SHORT;
+  };
+       uint8_t RESERVED_20[256];
+  union {                                          /* offset: 0xA00 */
+    __IO uint32_t PKB[64];                           /**< LTC PKHA B 0 Register..LTC PKHA B 63 Register, array offset: 0xA00, array step: 0x4 */
+    struct {                                         /* offset: 0xA00 */
+      __IO uint32_t PKB0[16];                          /**< LTC PKHA B0 0 Register..LTC PKHA B0 15 Register, array offset: 0xA00, array step: 0x4 */
+      __IO uint32_t PKB1[16];                          /**< LTC PKHA B1 0 Register..LTC PKHA B1 15 Register, array offset: 0xA40, array step: 0x4 */
+      __IO uint32_t PKB2[16];                          /**< LTC PKHA B2 0 Register..LTC PKHA B2 15 Register, array offset: 0xA80, array step: 0x4 */
+      __IO uint32_t PKB3[16];                          /**< LTC PKHA B3 0 Register..LTC PKHA B3 15 Register, array offset: 0xAC0, array step: 0x4 */
+    } PKB_SHORT;
+  };
+       uint8_t RESERVED_21[256];
+  union {                                          /* offset: 0xC00 */
+    __IO uint32_t PKN[64];                           /**< LTC PKHA N 0 Register..LTC PKHA N 63 Register, array offset: 0xC00, array step: 0x4 */
+    struct {                                         /* offset: 0xC00 */
+      __IO uint32_t PKN0[16];                          /**< LTC PKHA N0 0 Register..LTC PKHA N0 15 Register, array offset: 0xC00, array step: 0x4 */
+      __IO uint32_t PKN1[16];                          /**< LTC PKHA N1 0 Register..LTC PKHA N1 15 Register, array offset: 0xC40, array step: 0x4 */
+      __IO uint32_t PKN2[16];                          /**< LTC PKHA N2 0 Register..LTC PKHA N2 15 Register, array offset: 0xC80, array step: 0x4 */
+      __IO uint32_t PKN3[16];                          /**< LTC PKHA N3 0 Register..LTC PKHA N3 15 Register, array offset: 0xCC0, array step: 0x4 */
+    } PKN_SHORT;
+  };
+       uint8_t RESERVED_22[256];
+  union {                                          /* offset: 0xE00 */
+    __IO uint32_t PKE[64];                           /**< LTC PKHA E 0 Register..LTC PKHA E 63 Register, array offset: 0xE00, array step: 0x4 */
+    struct {                                         /* offset: 0xE00 */
+      __IO uint32_t PKE0[16];                          /**< LTC PKHA E0 0 Register..LTC PKHA E0 15 Register, array offset: 0xE00, array step: 0x4 */
+      __IO uint32_t PKE1[16];                          /**< LTC PKHA E1 0 Register..LTC PKHA E1 15 Register, array offset: 0xE40, array step: 0x4 */
+      __IO uint32_t PKE2[16];                          /**< LTC PKHA E2 0 Register..LTC PKHA E2 15 Register, array offset: 0xE80, array step: 0x4 */
+      __IO uint32_t PKE3[16];                          /**< LTC PKHA E3 0 Register..LTC PKHA E3 15 Register, array offset: 0xEC0, array step: 0x4 */
+    } PKE_SHORT;
+  };
+} LTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LTC_Register_Masks LTC Register Masks
+ * @{
+ */
+
+/*! @name MD - LTC Mode Register (non-PKHA/non-RNG use) */
+#define LTC_MD_ENC_MASK                          (0x1U)
+#define LTC_MD_ENC_SHIFT                         (0U)
+#define LTC_MD_ENC(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_MD_ENC_SHIFT)) & LTC_MD_ENC_MASK)
+#define LTC_MD_ICV_TEST_MASK                     (0x2U)
+#define LTC_MD_ICV_TEST_SHIFT                    (1U)
+#define LTC_MD_ICV_TEST(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
+#define LTC_MD_AS_MASK                           (0xCU)
+#define LTC_MD_AS_SHIFT                          (2U)
+#define LTC_MD_AS(x)                             (((uint32_t)(((uint32_t)(x)) << LTC_MD_AS_SHIFT)) & LTC_MD_AS_MASK)
+#define LTC_MD_AAI_MASK                          (0x1FF0U)
+#define LTC_MD_AAI_SHIFT                         (4U)
+#define LTC_MD_AAI(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_MD_AAI_SHIFT)) & LTC_MD_AAI_MASK)
+#define LTC_MD_ALG_MASK                          (0xFF0000U)
+#define LTC_MD_ALG_SHIFT                         (16U)
+#define LTC_MD_ALG(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_MD_ALG_SHIFT)) & LTC_MD_ALG_MASK)
+
+/*! @name MDPK - LTC Mode Register (PublicKey) */
+#define LTC_MDPK_PKHA_MODE_LS_MASK               (0xFFFU)
+#define LTC_MDPK_PKHA_MODE_LS_SHIFT              (0U)
+#define LTC_MDPK_PKHA_MODE_LS(x)                 (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_PKHA_MODE_LS_SHIFT)) & LTC_MDPK_PKHA_MODE_LS_MASK)
+#define LTC_MDPK_PKHA_MODE_MS_MASK               (0xF0000U)
+#define LTC_MDPK_PKHA_MODE_MS_SHIFT              (16U)
+#define LTC_MDPK_PKHA_MODE_MS(x)                 (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_PKHA_MODE_MS_SHIFT)) & LTC_MDPK_PKHA_MODE_MS_MASK)
+#define LTC_MDPK_ALG_MASK                        (0xF00000U)
+#define LTC_MDPK_ALG_SHIFT                       (20U)
+#define LTC_MDPK_ALG(x)                          (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_ALG_SHIFT)) & LTC_MDPK_ALG_MASK)
+
+/*! @name KS - LTC Key Size Register */
+#define LTC_KS_KS_MASK                           (0x3FU)
+#define LTC_KS_KS_SHIFT                          (0U)
+#define LTC_KS_KS(x)                             (((uint32_t)(((uint32_t)(x)) << LTC_KS_KS_SHIFT)) & LTC_KS_KS_MASK)
+
+/*! @name DS - LTC Data Size Register */
+#define LTC_DS_DS_MASK                           (0xFFFU)
+#define LTC_DS_DS_SHIFT                          (0U)
+#define LTC_DS_DS(x)                             (((uint32_t)(((uint32_t)(x)) << LTC_DS_DS_SHIFT)) & LTC_DS_DS_MASK)
+
+/*! @name ICVS - LTC ICV Size Register */
+#define LTC_ICVS_ICVS_MASK                       (0x1FU)
+#define LTC_ICVS_ICVS_SHIFT                      (0U)
+#define LTC_ICVS_ICVS(x)                         (((uint32_t)(((uint32_t)(x)) << LTC_ICVS_ICVS_SHIFT)) & LTC_ICVS_ICVS_MASK)
+
+/*! @name COM - LTC Command Register */
+#define LTC_COM_ALL_MASK                         (0x1U)
+#define LTC_COM_ALL_SHIFT                        (0U)
+#define LTC_COM_ALL(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_COM_ALL_SHIFT)) & LTC_COM_ALL_MASK)
+#define LTC_COM_AES_MASK                         (0x2U)
+#define LTC_COM_AES_SHIFT                        (1U)
+#define LTC_COM_AES(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_COM_AES_SHIFT)) & LTC_COM_AES_MASK)
+#define LTC_COM_DES_MASK                         (0x4U)
+#define LTC_COM_DES_SHIFT                        (2U)
+#define LTC_COM_DES(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_COM_DES_SHIFT)) & LTC_COM_DES_MASK)
+#define LTC_COM_PK_MASK                          (0x40U)
+#define LTC_COM_PK_SHIFT                         (6U)
+#define LTC_COM_PK(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_COM_PK_SHIFT)) & LTC_COM_PK_MASK)
+#define LTC_COM_MD_MASK                          (0x80U)
+#define LTC_COM_MD_SHIFT                         (7U)
+#define LTC_COM_MD(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_COM_MD_SHIFT)) & LTC_COM_MD_MASK)
+
+/*! @name CTL - LTC Control Register */
+#define LTC_CTL_IM_MASK                          (0x1U)
+#define LTC_CTL_IM_SHIFT                         (0U)
+#define LTC_CTL_IM(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IM_SHIFT)) & LTC_CTL_IM_MASK)
+#define LTC_CTL_PDE_MASK                         (0x10U)
+#define LTC_CTL_PDE_SHIFT                        (4U)
+#define LTC_CTL_PDE(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_PDE_SHIFT)) & LTC_CTL_PDE_MASK)
+#define LTC_CTL_IFE_MASK                         (0x100U)
+#define LTC_CTL_IFE_SHIFT                        (8U)
+#define LTC_CTL_IFE(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFE_SHIFT)) & LTC_CTL_IFE_MASK)
+#define LTC_CTL_IFR_MASK                         (0x200U)
+#define LTC_CTL_IFR_SHIFT                        (9U)
+#define LTC_CTL_IFR(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
+#define LTC_CTL_OFE_MASK                         (0x1000U)
+#define LTC_CTL_OFE_SHIFT                        (12U)
+#define LTC_CTL_OFE(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFE_SHIFT)) & LTC_CTL_OFE_MASK)
+#define LTC_CTL_OFR_MASK                         (0x2000U)
+#define LTC_CTL_OFR_SHIFT                        (13U)
+#define LTC_CTL_OFR(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFR_SHIFT)) & LTC_CTL_OFR_MASK)
+#define LTC_CTL_IFS_MASK                         (0x10000U)
+#define LTC_CTL_IFS_SHIFT                        (16U)
+#define LTC_CTL_IFS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFS_SHIFT)) & LTC_CTL_IFS_MASK)
+#define LTC_CTL_OFS_MASK                         (0x20000U)
+#define LTC_CTL_OFS_SHIFT                        (17U)
+#define LTC_CTL_OFS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFS_SHIFT)) & LTC_CTL_OFS_MASK)
+#define LTC_CTL_KIS_MASK                         (0x100000U)
+#define LTC_CTL_KIS_SHIFT                        (20U)
+#define LTC_CTL_KIS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KIS_SHIFT)) & LTC_CTL_KIS_MASK)
+#define LTC_CTL_KOS_MASK                         (0x200000U)
+#define LTC_CTL_KOS_SHIFT                        (21U)
+#define LTC_CTL_KOS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KOS_SHIFT)) & LTC_CTL_KOS_MASK)
+#define LTC_CTL_CIS_MASK                         (0x400000U)
+#define LTC_CTL_CIS_SHIFT                        (22U)
+#define LTC_CTL_CIS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_CIS_SHIFT)) & LTC_CTL_CIS_MASK)
+#define LTC_CTL_COS_MASK                         (0x800000U)
+#define LTC_CTL_COS_SHIFT                        (23U)
+#define LTC_CTL_COS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_COS_SHIFT)) & LTC_CTL_COS_MASK)
+#define LTC_CTL_KAL_MASK                         (0x80000000U)
+#define LTC_CTL_KAL_SHIFT                        (31U)
+#define LTC_CTL_KAL(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KAL_SHIFT)) & LTC_CTL_KAL_MASK)
+
+/*! @name CW - LTC Clear Written Register */
+#define LTC_CW_CM_MASK                           (0x1U)
+#define LTC_CW_CM_SHIFT                          (0U)
+#define LTC_CW_CM(x)                             (((uint32_t)(((uint32_t)(x)) << LTC_CW_CM_SHIFT)) & LTC_CW_CM_MASK)
+#define LTC_CW_CDS_MASK                          (0x4U)
+#define LTC_CW_CDS_SHIFT                         (2U)
+#define LTC_CW_CDS(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_CDS_SHIFT)) & LTC_CW_CDS_MASK)
+#define LTC_CW_CICV_MASK                         (0x8U)
+#define LTC_CW_CICV_SHIFT                        (3U)
+#define LTC_CW_CICV(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CW_CICV_SHIFT)) & LTC_CW_CICV_MASK)
+#define LTC_CW_CCR_MASK                          (0x20U)
+#define LTC_CW_CCR_SHIFT                         (5U)
+#define LTC_CW_CCR(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_CCR_SHIFT)) & LTC_CW_CCR_MASK)
+#define LTC_CW_CKR_MASK                          (0x40U)
+#define LTC_CW_CKR_SHIFT                         (6U)
+#define LTC_CW_CKR(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_CKR_SHIFT)) & LTC_CW_CKR_MASK)
+#define LTC_CW_CPKA_MASK                         (0x1000U)
+#define LTC_CW_CPKA_SHIFT                        (12U)
+#define LTC_CW_CPKA(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKA_SHIFT)) & LTC_CW_CPKA_MASK)
+#define LTC_CW_CPKB_MASK                         (0x2000U)
+#define LTC_CW_CPKB_SHIFT                        (13U)
+#define LTC_CW_CPKB(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKB_SHIFT)) & LTC_CW_CPKB_MASK)
+#define LTC_CW_CPKN_MASK                         (0x4000U)
+#define LTC_CW_CPKN_SHIFT                        (14U)
+#define LTC_CW_CPKN(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKN_SHIFT)) & LTC_CW_CPKN_MASK)
+#define LTC_CW_CPKE_MASK                         (0x8000U)
+#define LTC_CW_CPKE_SHIFT                        (15U)
+#define LTC_CW_CPKE(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKE_SHIFT)) & LTC_CW_CPKE_MASK)
+#define LTC_CW_COF_MASK                          (0x40000000U)
+#define LTC_CW_COF_SHIFT                         (30U)
+#define LTC_CW_COF(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_COF_SHIFT)) & LTC_CW_COF_MASK)
+#define LTC_CW_CIF_MASK                          (0x80000000U)
+#define LTC_CW_CIF_SHIFT                         (31U)
+#define LTC_CW_CIF(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_CIF_SHIFT)) & LTC_CW_CIF_MASK)
+
+/*! @name STA - LTC Status Register */
+#define LTC_STA_AB_MASK                          (0x2U)
+#define LTC_STA_AB_SHIFT                         (1U)
+#define LTC_STA_AB(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_STA_AB_SHIFT)) & LTC_STA_AB_MASK)
+#define LTC_STA_DB_MASK                          (0x4U)
+#define LTC_STA_DB_SHIFT                         (2U)
+#define LTC_STA_DB(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_STA_DB_SHIFT)) & LTC_STA_DB_MASK)
+#define LTC_STA_PB_MASK                          (0x40U)
+#define LTC_STA_PB_SHIFT                         (6U)
+#define LTC_STA_PB(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_STA_PB_SHIFT)) & LTC_STA_PB_MASK)
+#define LTC_STA_MB_MASK                          (0x80U)
+#define LTC_STA_MB_SHIFT                         (7U)
+#define LTC_STA_MB(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_STA_MB_SHIFT)) & LTC_STA_MB_MASK)
+#define LTC_STA_DI_MASK                          (0x10000U)
+#define LTC_STA_DI_SHIFT                         (16U)
+#define LTC_STA_DI(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_STA_DI_SHIFT)) & LTC_STA_DI_MASK)
+#define LTC_STA_EI_MASK                          (0x100000U)
+#define LTC_STA_EI_SHIFT                         (20U)
+#define LTC_STA_EI(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_STA_EI_SHIFT)) & LTC_STA_EI_MASK)
+#define LTC_STA_DPARRN_MASK                      (0x1000000U)
+#define LTC_STA_DPARRN_SHIFT                     (24U)
+#define LTC_STA_DPARRN(x)                        (((uint32_t)(((uint32_t)(x)) << LTC_STA_DPARRN_SHIFT)) & LTC_STA_DPARRN_MASK)
+#define LTC_STA_PKP_MASK                         (0x10000000U)
+#define LTC_STA_PKP_SHIFT                        (28U)
+#define LTC_STA_PKP(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKP_SHIFT)) & LTC_STA_PKP_MASK)
+#define LTC_STA_PKO_MASK                         (0x20000000U)
+#define LTC_STA_PKO_SHIFT                        (29U)
+#define LTC_STA_PKO(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKO_SHIFT)) & LTC_STA_PKO_MASK)
+#define LTC_STA_PKZ_MASK                         (0x40000000U)
+#define LTC_STA_PKZ_SHIFT                        (30U)
+#define LTC_STA_PKZ(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKZ_SHIFT)) & LTC_STA_PKZ_MASK)
+
+/*! @name ESTA - LTC Error Status Register */
+#define LTC_ESTA_ERRID1_MASK                     (0xFU)
+#define LTC_ESTA_ERRID1_SHIFT                    (0U)
+#define LTC_ESTA_ERRID1(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_ERRID1_SHIFT)) & LTC_ESTA_ERRID1_MASK)
+#define LTC_ESTA_CL1_MASK                        (0xF00U)
+#define LTC_ESTA_CL1_SHIFT                       (8U)
+#define LTC_ESTA_CL1(x)                          (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_CL1_SHIFT)) & LTC_ESTA_CL1_MASK)
+
+/*! @name AADSZ - LTC AAD Size Register */
+#define LTC_AADSZ_AADSZ_MASK                     (0xFU)
+#define LTC_AADSZ_AADSZ_SHIFT                    (0U)
+#define LTC_AADSZ_AADSZ(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AADSZ_SHIFT)) & LTC_AADSZ_AADSZ_MASK)
+#define LTC_AADSZ_AL_MASK                        (0x80000000U)
+#define LTC_AADSZ_AL_SHIFT                       (31U)
+#define LTC_AADSZ_AL(x)                          (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AL_SHIFT)) & LTC_AADSZ_AL_MASK)
+
+/*! @name IVSZ - LTC IV Size Register */
+#define LTC_IVSZ_IVSZ_MASK                       (0xFU)
+#define LTC_IVSZ_IVSZ_SHIFT                      (0U)
+#define LTC_IVSZ_IVSZ(x)                         (((uint32_t)(((uint32_t)(x)) << LTC_IVSZ_IVSZ_SHIFT)) & LTC_IVSZ_IVSZ_MASK)
+#define LTC_IVSZ_IL_MASK                         (0x80000000U)
+#define LTC_IVSZ_IL_SHIFT                        (31U)
+#define LTC_IVSZ_IL(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_IVSZ_IL_SHIFT)) & LTC_IVSZ_IL_MASK)
+
+/*! @name DPAMS - LTC DPA Mask Seed Register */
+#define LTC_DPAMS_DPAMS_MASK                     (0xFFFFFFFFU)
+#define LTC_DPAMS_DPAMS_SHIFT                    (0U)
+#define LTC_DPAMS_DPAMS(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_DPAMS_DPAMS_SHIFT)) & LTC_DPAMS_DPAMS_MASK)
+
+/*! @name PKASZ - LTC PKHA A Size Register */
+#define LTC_PKASZ_PKASZ_MASK                     (0x1FFU)
+#define LTC_PKASZ_PKASZ_SHIFT                    (0U)
+#define LTC_PKASZ_PKASZ(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_PKASZ_PKASZ_SHIFT)) & LTC_PKASZ_PKASZ_MASK)
+
+/*! @name PKBSZ - LTC PKHA B Size Register */
+#define LTC_PKBSZ_PKBSZ_MASK                     (0x1FFU)
+#define LTC_PKBSZ_PKBSZ_SHIFT                    (0U)
+#define LTC_PKBSZ_PKBSZ(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_PKBSZ_PKBSZ_SHIFT)) & LTC_PKBSZ_PKBSZ_MASK)
+
+/*! @name PKNSZ - LTC PKHA N Size Register */
+#define LTC_PKNSZ_PKNSZ_MASK                     (0x1FFU)
+#define LTC_PKNSZ_PKNSZ_SHIFT                    (0U)
+#define LTC_PKNSZ_PKNSZ(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_PKNSZ_PKNSZ_SHIFT)) & LTC_PKNSZ_PKNSZ_MASK)
+
+/*! @name PKESZ - LTC PKHA E Size Register */
+#define LTC_PKESZ_PKESZ_MASK                     (0x1FFU)
+#define LTC_PKESZ_PKESZ_SHIFT                    (0U)
+#define LTC_PKESZ_PKESZ(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_PKESZ_PKESZ_SHIFT)) & LTC_PKESZ_PKESZ_MASK)
+
+/*! @name CTX - LTC Context Register */
+#define LTC_CTX_CTX_MASK                         (0xFFFFFFFFU)
+#define LTC_CTX_CTX_SHIFT                        (0U)
+#define LTC_CTX_CTX(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTX_CTX_SHIFT)) & LTC_CTX_CTX_MASK)
+
+/* The count of LTC_CTX */
+#define LTC_CTX_COUNT                            (16U)
+
+/*! @name KEY - LTC Key Registers */
+#define LTC_KEY_KEY_MASK                         (0xFFFFFFFFU)
+#define LTC_KEY_KEY_SHIFT                        (0U)
+#define LTC_KEY_KEY(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_KEY_KEY_SHIFT)) & LTC_KEY_KEY_MASK)
+
+/* The count of LTC_KEY */
+#define LTC_KEY_COUNT                            (8U)
+
+/*! @name VID1 - LTC Version ID Register */
+#define LTC_VID1_MIN_REV_MASK                    (0xFFU)
+#define LTC_VID1_MIN_REV_SHIFT                   (0U)
+#define LTC_VID1_MIN_REV(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MIN_REV_SHIFT)) & LTC_VID1_MIN_REV_MASK)
+#define LTC_VID1_MAJ_REV_MASK                    (0xFF00U)
+#define LTC_VID1_MAJ_REV_SHIFT                   (8U)
+#define LTC_VID1_MAJ_REV(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MAJ_REV_SHIFT)) & LTC_VID1_MAJ_REV_MASK)
+#define LTC_VID1_IP_ID_MASK                      (0xFFFF0000U)
+#define LTC_VID1_IP_ID_SHIFT                     (16U)
+#define LTC_VID1_IP_ID(x)                        (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
+
+/*! @name VID2 - LTC Version ID 2 Register */
+#define LTC_VID2_ECO_REV_MASK                    (0xFFU)
+#define LTC_VID2_ECO_REV_SHIFT                   (0U)
+#define LTC_VID2_ECO_REV(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ECO_REV_SHIFT)) & LTC_VID2_ECO_REV_MASK)
+#define LTC_VID2_ARCH_ERA_MASK                   (0xFF00U)
+#define LTC_VID2_ARCH_ERA_SHIFT                  (8U)
+#define LTC_VID2_ARCH_ERA(x)                     (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ARCH_ERA_SHIFT)) & LTC_VID2_ARCH_ERA_MASK)
+
+/*! @name CHAVID - LTC CHA Version ID Register */
+#define LTC_CHAVID_AESREV_MASK                   (0xFU)
+#define LTC_CHAVID_AESREV_SHIFT                  (0U)
+#define LTC_CHAVID_AESREV(x)                     (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESREV_SHIFT)) & LTC_CHAVID_AESREV_MASK)
+#define LTC_CHAVID_AESVID_MASK                   (0xF0U)
+#define LTC_CHAVID_AESVID_SHIFT                  (4U)
+#define LTC_CHAVID_AESVID(x)                     (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
+#define LTC_CHAVID_DESREV_MASK                   (0xF00U)
+#define LTC_CHAVID_DESREV_SHIFT                  (8U)
+#define LTC_CHAVID_DESREV(x)                     (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_DESREV_SHIFT)) & LTC_CHAVID_DESREV_MASK)
+#define LTC_CHAVID_DESVID_MASK                   (0xF000U)
+#define LTC_CHAVID_DESVID_SHIFT                  (12U)
+#define LTC_CHAVID_DESVID(x)                     (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_DESVID_SHIFT)) & LTC_CHAVID_DESVID_MASK)
+#define LTC_CHAVID_PKHAREV_MASK                  (0xF0000U)
+#define LTC_CHAVID_PKHAREV_SHIFT                 (16U)
+#define LTC_CHAVID_PKHAREV(x)                    (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_PKHAREV_SHIFT)) & LTC_CHAVID_PKHAREV_MASK)
+#define LTC_CHAVID_PKHAVID_MASK                  (0xF00000U)
+#define LTC_CHAVID_PKHAVID_SHIFT                 (20U)
+#define LTC_CHAVID_PKHAVID(x)                    (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_PKHAVID_SHIFT)) & LTC_CHAVID_PKHAVID_MASK)
+#define LTC_CHAVID_MDHAREV_MASK                  (0xF000000U)
+#define LTC_CHAVID_MDHAREV_SHIFT                 (24U)
+#define LTC_CHAVID_MDHAREV(x)                    (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_MDHAREV_SHIFT)) & LTC_CHAVID_MDHAREV_MASK)
+#define LTC_CHAVID_MDHAVID_MASK                  (0xF0000000U)
+#define LTC_CHAVID_MDHAVID_SHIFT                 (28U)
+#define LTC_CHAVID_MDHAVID(x)                    (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_MDHAVID_SHIFT)) & LTC_CHAVID_MDHAVID_MASK)
+
+/*! @name FIFOSTA - LTC FIFO Status Register */
+#define LTC_FIFOSTA_IFL_MASK                     (0x7FU)
+#define LTC_FIFOSTA_IFL_SHIFT                    (0U)
+#define LTC_FIFOSTA_IFL(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFL_SHIFT)) & LTC_FIFOSTA_IFL_MASK)
+#define LTC_FIFOSTA_IFF_MASK                     (0x8000U)
+#define LTC_FIFOSTA_IFF_SHIFT                    (15U)
+#define LTC_FIFOSTA_IFF(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFF_SHIFT)) & LTC_FIFOSTA_IFF_MASK)
+#define LTC_FIFOSTA_OFL_MASK                     (0x7F0000U)
+#define LTC_FIFOSTA_OFL_SHIFT                    (16U)
+#define LTC_FIFOSTA_OFL(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFL_SHIFT)) & LTC_FIFOSTA_OFL_MASK)
+#define LTC_FIFOSTA_OFF_MASK                     (0x80000000U)
+#define LTC_FIFOSTA_OFF_SHIFT                    (31U)
+#define LTC_FIFOSTA_OFF(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFF_SHIFT)) & LTC_FIFOSTA_OFF_MASK)
+
+/*! @name IFIFO - LTC Input Data FIFO */
+#define LTC_IFIFO_IFIFO_MASK                     (0xFFFFFFFFU)
+#define LTC_IFIFO_IFIFO_SHIFT                    (0U)
+#define LTC_IFIFO_IFIFO(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_IFIFO_IFIFO_SHIFT)) & LTC_IFIFO_IFIFO_MASK)
+
+/*! @name OFIFO - LTC Output Data FIFO */
+#define LTC_OFIFO_OFIFO_MASK                     (0xFFFFFFFFU)
+#define LTC_OFIFO_OFIFO_SHIFT                    (0U)
+#define LTC_OFIFO_OFIFO(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_OFIFO_OFIFO_SHIFT)) & LTC_OFIFO_OFIFO_MASK)
+
+/* The count of LTC_PKA */
+#define LTC_PKA_COUNT                            (64U)
+
+/*! @name PKA0 - LTC PKHA A0 0 Register..LTC PKHA A0 15 Register */
+#define LTC_PKA0_PKHA_A0_MASK                    (0xFFFFFFFFU)
+#define LTC_PKA0_PKHA_A0_SHIFT                   (0U)
+#define LTC_PKA0_PKHA_A0(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKA0_PKHA_A0_SHIFT)) & LTC_PKA0_PKHA_A0_MASK)
+
+/* The count of LTC_PKA0 */
+#define LTC_PKA0_COUNT                           (16U)
+
+/*! @name PKA1 - LTC PKHA A1 0 Register..LTC PKHA A1 15 Register */
+#define LTC_PKA1_PKHA_A1_MASK                    (0xFFFFFFFFU)
+#define LTC_PKA1_PKHA_A1_SHIFT                   (0U)
+#define LTC_PKA1_PKHA_A1(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKA1_PKHA_A1_SHIFT)) & LTC_PKA1_PKHA_A1_MASK)
+
+/* The count of LTC_PKA1 */
+#define LTC_PKA1_COUNT                           (16U)
+
+/*! @name PKA2 - LTC PKHA A2 0 Register..LTC PKHA A2 15 Register */
+#define LTC_PKA2_PKHA_A2_MASK                    (0xFFFFFFFFU)
+#define LTC_PKA2_PKHA_A2_SHIFT                   (0U)
+#define LTC_PKA2_PKHA_A2(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKA2_PKHA_A2_SHIFT)) & LTC_PKA2_PKHA_A2_MASK)
+
+/* The count of LTC_PKA2 */
+#define LTC_PKA2_COUNT                           (16U)
+
+/*! @name PKA3 - LTC PKHA A3 0 Register..LTC PKHA A3 15 Register */
+#define LTC_PKA3_PKHA_A3_MASK                    (0xFFFFFFFFU)
+#define LTC_PKA3_PKHA_A3_SHIFT                   (0U)
+#define LTC_PKA3_PKHA_A3(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKA3_PKHA_A3_SHIFT)) & LTC_PKA3_PKHA_A3_MASK)
+
+/* The count of LTC_PKA3 */
+#define LTC_PKA3_COUNT                           (16U)
+
+/* The count of LTC_PKB */
+#define LTC_PKB_COUNT                            (64U)
+
+/*! @name PKB0 - LTC PKHA B0 0 Register..LTC PKHA B0 15 Register */
+#define LTC_PKB0_PKHA_B0_MASK                    (0xFFFFFFFFU)
+#define LTC_PKB0_PKHA_B0_SHIFT                   (0U)
+#define LTC_PKB0_PKHA_B0(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKB0_PKHA_B0_SHIFT)) & LTC_PKB0_PKHA_B0_MASK)
+
+/* The count of LTC_PKB0 */
+#define LTC_PKB0_COUNT                           (16U)
+
+/*! @name PKB1 - LTC PKHA B1 0 Register..LTC PKHA B1 15 Register */
+#define LTC_PKB1_PKHA_B1_MASK                    (0xFFFFFFFFU)
+#define LTC_PKB1_PKHA_B1_SHIFT                   (0U)
+#define LTC_PKB1_PKHA_B1(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKB1_PKHA_B1_SHIFT)) & LTC_PKB1_PKHA_B1_MASK)
+
+/* The count of LTC_PKB1 */
+#define LTC_PKB1_COUNT                           (16U)
+
+/*! @name PKB2 - LTC PKHA B2 0 Register..LTC PKHA B2 15 Register */
+#define LTC_PKB2_PKHA_B2_MASK                    (0xFFFFFFFFU)
+#define LTC_PKB2_PKHA_B2_SHIFT                   (0U)
+#define LTC_PKB2_PKHA_B2(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKB2_PKHA_B2_SHIFT)) & LTC_PKB2_PKHA_B2_MASK)
+
+/* The count of LTC_PKB2 */
+#define LTC_PKB2_COUNT                           (16U)
+
+/*! @name PKB3 - LTC PKHA B3 0 Register..LTC PKHA B3 15 Register */
+#define LTC_PKB3_PKHA_B3_MASK                    (0xFFFFFFFFU)
+#define LTC_PKB3_PKHA_B3_SHIFT                   (0U)
+#define LTC_PKB3_PKHA_B3(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKB3_PKHA_B3_SHIFT)) & LTC_PKB3_PKHA_B3_MASK)
+
+/* The count of LTC_PKB3 */
+#define LTC_PKB3_COUNT                           (16U)
+
+/* The count of LTC_PKN */
+#define LTC_PKN_COUNT                            (64U)
+
+/*! @name PKN0 - LTC PKHA N0 0 Register..LTC PKHA N0 15 Register */
+#define LTC_PKN0_PKHA_N0_MASK                    (0xFFFFFFFFU)
+#define LTC_PKN0_PKHA_N0_SHIFT                   (0U)
+#define LTC_PKN0_PKHA_N0(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKN0_PKHA_N0_SHIFT)) & LTC_PKN0_PKHA_N0_MASK)
+
+/* The count of LTC_PKN0 */
+#define LTC_PKN0_COUNT                           (16U)
+
+/*! @name PKN1 - LTC PKHA N1 0 Register..LTC PKHA N1 15 Register */
+#define LTC_PKN1_PKHA_N1_MASK                    (0xFFFFFFFFU)
+#define LTC_PKN1_PKHA_N1_SHIFT                   (0U)
+#define LTC_PKN1_PKHA_N1(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKN1_PKHA_N1_SHIFT)) & LTC_PKN1_PKHA_N1_MASK)
+
+/* The count of LTC_PKN1 */
+#define LTC_PKN1_COUNT                           (16U)
+
+/*! @name PKN2 - LTC PKHA N2 0 Register..LTC PKHA N2 15 Register */
+#define LTC_PKN2_PKHA_N2_MASK                    (0xFFFFFFFFU)
+#define LTC_PKN2_PKHA_N2_SHIFT                   (0U)
+#define LTC_PKN2_PKHA_N2(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKN2_PKHA_N2_SHIFT)) & LTC_PKN2_PKHA_N2_MASK)
+
+/* The count of LTC_PKN2 */
+#define LTC_PKN2_COUNT                           (16U)
+
+/*! @name PKN3 - LTC PKHA N3 0 Register..LTC PKHA N3 15 Register */
+#define LTC_PKN3_PKHA_N3_MASK                    (0xFFFFFFFFU)
+#define LTC_PKN3_PKHA_N3_SHIFT                   (0U)
+#define LTC_PKN3_PKHA_N3(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKN3_PKHA_N3_SHIFT)) & LTC_PKN3_PKHA_N3_MASK)
+
+/* The count of LTC_PKN3 */
+#define LTC_PKN3_COUNT                           (16U)
+
+/* The count of LTC_PKE */
+#define LTC_PKE_COUNT                            (64U)
+
+/*! @name PKE0 - LTC PKHA E0 0 Register..LTC PKHA E0 15 Register */
+#define LTC_PKE0_PKHA_E0_MASK                    (0xFFFFFFFFU)
+#define LTC_PKE0_PKHA_E0_SHIFT                   (0U)
+#define LTC_PKE0_PKHA_E0(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKE0_PKHA_E0_SHIFT)) & LTC_PKE0_PKHA_E0_MASK)
+
+/* The count of LTC_PKE0 */
+#define LTC_PKE0_COUNT                           (16U)
+
+/*! @name PKE1 - LTC PKHA E1 0 Register..LTC PKHA E1 15 Register */
+#define LTC_PKE1_PKHA_E1_MASK                    (0xFFFFFFFFU)
+#define LTC_PKE1_PKHA_E1_SHIFT                   (0U)
+#define LTC_PKE1_PKHA_E1(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKE1_PKHA_E1_SHIFT)) & LTC_PKE1_PKHA_E1_MASK)
+
+/* The count of LTC_PKE1 */
+#define LTC_PKE1_COUNT                           (16U)
+
+/*! @name PKE2 - LTC PKHA E2 0 Register..LTC PKHA E2 15 Register */
+#define LTC_PKE2_PKHA_E2_MASK                    (0xFFFFFFFFU)
+#define LTC_PKE2_PKHA_E2_SHIFT                   (0U)
+#define LTC_PKE2_PKHA_E2(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKE2_PKHA_E2_SHIFT)) & LTC_PKE2_PKHA_E2_MASK)
+
+/* The count of LTC_PKE2 */
+#define LTC_PKE2_COUNT                           (16U)
+
+/*! @name PKE3 - LTC PKHA E3 0 Register..LTC PKHA E3 15 Register */
+#define LTC_PKE3_PKHA_E3_MASK                    (0xFFFFFFFFU)
+#define LTC_PKE3_PKHA_E3_SHIFT                   (0U)
+#define LTC_PKE3_PKHA_E3(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_PKE3_PKHA_E3_SHIFT)) & LTC_PKE3_PKHA_E3_MASK)
+
+/* The count of LTC_PKE3 */
+#define LTC_PKE3_COUNT                           (16U)
+
+
+/*!
+ * @}
+ */ /* end of group LTC_Register_Masks */
+
+
+/* LTC - Peripheral instance base addresses */
+/** Peripheral LTC0 base address */
+#define LTC0_BASE                                (0x40051000u)
+/** Peripheral LTC0 base pointer */
+#define LTC0                                     ((LTC_Type *)LTC0_BASE)
+/** Array initializer of LTC peripheral base addresses */
+#define LTC_BASE_ADDRS                           { LTC0_BASE }
+/** Array initializer of LTC peripheral base pointers */
+#define LTC_BASE_PTRS                            { LTC0 }
+/** Interrupt vectors for the LTC peripheral type */
+#define LTC_IRQS                                 { LTC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
+  __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
+  __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
+  __IO uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
+  __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
+  __IO uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+  __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+  __IO uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
+  __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/*! @name C1 - MCG Control 1 Register */
+#define MCG_C1_IREFSTEN_MASK                     (0x1U)
+#define MCG_C1_IREFSTEN_SHIFT                    (0U)
+#define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK                      (0x2U)
+#define MCG_C1_IRCLKEN_SHIFT                     (1U)
+#define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK                        (0x4U)
+#define MCG_C1_IREFS_SHIFT                       (2U)
+#define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK                        (0x38U)
+#define MCG_C1_FRDIV_SHIFT                       (3U)
+#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK                         (0xC0U)
+#define MCG_C1_CLKS_SHIFT                        (6U)
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+
+/*! @name C2 - MCG Control 2 Register */
+#define MCG_C2_IRCS_MASK                         (0x1U)
+#define MCG_C2_IRCS_SHIFT                        (0U)
+#define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK                           (0x2U)
+#define MCG_C2_LP_SHIFT                          (1U)
+#define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
+#define MCG_C2_EREFS_MASK                        (0x4U)
+#define MCG_C2_EREFS_SHIFT                       (2U)
+#define MCG_C2_EREFS(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
+#define MCG_C2_HGO_MASK                          (0x8U)
+#define MCG_C2_HGO_SHIFT                         (3U)
+#define MCG_C2_HGO(x)                            (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
+#define MCG_C2_RANGE_MASK                        (0x30U)
+#define MCG_C2_RANGE_SHIFT                       (4U)
+#define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK                      (0x40U)
+#define MCG_C2_FCFTRIM_SHIFT                     (6U)
+#define MCG_C2_FCFTRIM(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_LOCRE0_MASK                       (0x80U)
+#define MCG_C2_LOCRE0_SHIFT                      (7U)
+#define MCG_C2_LOCRE0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
+
+/*! @name C3 - MCG Control 3 Register */
+#define MCG_C3_SCTRIM_MASK                       (0xFFU)
+#define MCG_C3_SCTRIM_SHIFT                      (0U)
+#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
+
+/*! @name C4 - MCG Control 4 Register */
+#define MCG_C4_SCFTRIM_MASK                      (0x1U)
+#define MCG_C4_SCFTRIM_SHIFT                     (0U)
+#define MCG_C4_SCFTRIM(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK                       (0x1EU)
+#define MCG_C4_FCTRIM_SHIFT                      (1U)
+#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK                     (0x60U)
+#define MCG_C4_DRST_DRS_SHIFT                    (5U)
+#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK                        (0x80U)
+#define MCG_C4_DMX32_SHIFT                       (7U)
+#define MCG_C4_DMX32(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
+
+/*! @name C5 - MCG Control 5 Register */
+#define MCG_C5_PRDIV_MASK                        (0x7U)
+#define MCG_C5_PRDIV_SHIFT                       (0U)
+#define MCG_C5_PRDIV(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
+#define MCG_C5_PLLSTEN_MASK                      (0x20U)
+#define MCG_C5_PLLSTEN_SHIFT                     (5U)
+#define MCG_C5_PLLSTEN(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
+#define MCG_C5_PLLCLKEN_MASK                     (0x40U)
+#define MCG_C5_PLLCLKEN_SHIFT                    (6U)
+#define MCG_C5_PLLCLKEN(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
+
+/*! @name C6 - MCG Control 6 Register */
+#define MCG_C6_VDIV_MASK                         (0x1FU)
+#define MCG_C6_VDIV_SHIFT                        (0U)
+#define MCG_C6_VDIV(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
+#define MCG_C6_CME0_MASK                         (0x20U)
+#define MCG_C6_CME0_SHIFT                        (5U)
+#define MCG_C6_CME0(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK                         (0x40U)
+#define MCG_C6_PLLS_SHIFT                        (6U)
+#define MCG_C6_PLLS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK                       (0x80U)
+#define MCG_C6_LOLIE0_SHIFT                      (7U)
+#define MCG_C6_LOLIE0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
+
+/*! @name S - MCG Status Register */
+#define MCG_S_IRCST_MASK                         (0x1U)
+#define MCG_S_IRCST_SHIFT                        (0U)
+#define MCG_S_IRCST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK                      (0x2U)
+#define MCG_S_OSCINIT0_SHIFT                     (1U)
+#define MCG_S_OSCINIT0(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK                         (0xCU)
+#define MCG_S_CLKST_SHIFT                        (2U)
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK                        (0x10U)
+#define MCG_S_IREFST_SHIFT                       (4U)
+#define MCG_S_IREFST(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK                         (0x20U)
+#define MCG_S_PLLST_SHIFT                        (5U)
+#define MCG_S_PLLST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK                         (0x40U)
+#define MCG_S_LOCK0_SHIFT                        (6U)
+#define MCG_S_LOCK0(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS0_MASK                         (0x80U)
+#define MCG_S_LOLS0_SHIFT                        (7U)
+#define MCG_S_LOLS0(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
+
+/*! @name SC - MCG Status and Control Register */
+#define MCG_SC_LOCS0_MASK                        (0x1U)
+#define MCG_SC_LOCS0_SHIFT                       (0U)
+#define MCG_SC_LOCS0(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK                       (0xEU)
+#define MCG_SC_FCRDIV_SHIFT                      (1U)
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK                     (0x10U)
+#define MCG_SC_FLTPRSRV_SHIFT                    (4U)
+#define MCG_SC_FLTPRSRV(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK                         (0x20U)
+#define MCG_SC_ATMF_SHIFT                        (5U)
+#define MCG_SC_ATMF(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK                         (0x40U)
+#define MCG_SC_ATMS_SHIFT                        (6U)
+#define MCG_SC_ATMS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK                         (0x80U)
+#define MCG_SC_ATME_SHIFT                        (7U)
+#define MCG_SC_ATME(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
+
+/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
+#define MCG_ATCVH_ATCVH_MASK                     (0xFFU)
+#define MCG_ATCVH_ATCVH_SHIFT                    (0U)
+#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
+
+/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
+#define MCG_ATCVL_ATCVL_MASK                     (0xFFU)
+#define MCG_ATCVL_ATCVL_SHIFT                    (0U)
+#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
+
+/*! @name C7 - MCG Control 7 Register */
+#define MCG_C7_OSCSEL_MASK                       (0x3U)
+#define MCG_C7_OSCSEL_SHIFT                      (0U)
+#define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
+
+/*! @name C8 - MCG Control 8 Register */
+#define MCG_C8_LOCS1_MASK                        (0x1U)
+#define MCG_C8_LOCS1_SHIFT                       (0U)
+#define MCG_C8_LOCS1(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK                         (0x20U)
+#define MCG_C8_CME1_SHIFT                        (5U)
+#define MCG_C8_CME1(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
+#define MCG_C8_LOLRE_MASK                        (0x40U)
+#define MCG_C8_LOLRE_SHIFT                       (6U)
+#define MCG_C8_LOLRE(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOCRE1_MASK                       (0x80U)
+#define MCG_C8_LOCRE1_SHIFT                      (7U)
+#define MCG_C8_LOCRE1(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG                                      ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS                           { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS                            { MCG }
+/** Interrupt vectors for the MCG peripheral type */
+#define MCG_IRQS                                 { MCG_IRQn }
+/* MCG C5[PLLCLKEN0] backward compatibility */
+#define MCG_C5_PLLCLKEN0_MASK         (MCG_C5_PLLCLKEN_MASK)
+#define MCG_C5_PLLCLKEN0_SHIFT        (MCG_C5_PLLCLKEN_SHIFT)
+#define MCG_C5_PLLCLKEN0_WIDTH        (MCG_C5_PLLCLKEN_WIDTH)
+#define MCG_C5_PLLCLKEN0(x)           (MCG_C5_PLLCLKEN(x))
+
+/* MCG C5[PLLSTEN0] backward compatibility */
+#define MCG_C5_PLLSTEN0_MASK         (MCG_C5_PLLSTEN_MASK)
+#define MCG_C5_PLLSTEN0_SHIFT        (MCG_C5_PLLSTEN_SHIFT)
+#define MCG_C5_PLLSTEN0_WIDTH        (MCG_C5_PLLSTEN_WIDTH)
+#define MCG_C5_PLLSTEN0(x)           (MCG_C5_PLLSTEN(x))
+
+/* MCG C5[PRDIV0] backward compatibility */
+#define MCG_C5_PRDIV0_MASK         (MCG_C5_PRDIV_MASK)
+#define MCG_C5_PRDIV0_SHIFT        (MCG_C5_PRDIV_SHIFT)
+#define MCG_C5_PRDIV0_WIDTH        (MCG_C5_PRDIV_WIDTH)
+#define MCG_C5_PRDIV0(x)           (MCG_C5_PRDIV(x))
+
+/* MCG C6[VDIV0] backward compatibility */
+#define MCG_C6_VDIV0_MASK         (MCG_C6_VDIV_MASK)
+#define MCG_C6_VDIV0_SHIFT        (MCG_C6_VDIV_SHIFT)
+#define MCG_C6_VDIV0_WIDTH        (MCG_C6_VDIV_WIDTH)
+#define MCG_C6_VDIV0(x)           (MCG_C6_VDIV(x))
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t PLACR;                             /**< Platform Control Register, offset: 0xC */
+       uint8_t RESERVED_1[48];
+  __IO uint32_t CPO;                               /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
+#define MCM_PLASC_ASC_MASK                       (0xFFU)
+#define MCM_PLASC_ASC_SHIFT                      (0U)
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+
+/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
+#define MCM_PLAMC_AMC_MASK                       (0xFFU)
+#define MCM_PLAMC_AMC_SHIFT                      (0U)
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+
+/*! @name PLACR - Platform Control Register */
+#define MCM_PLACR_ARB_MASK                       (0x200U)
+#define MCM_PLACR_ARB_SHIFT                      (9U)
+#define MCM_PLACR_ARB(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
+#define MCM_PLACR_CFCC_MASK                      (0x400U)
+#define MCM_PLACR_CFCC_SHIFT                     (10U)
+#define MCM_PLACR_CFCC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK)
+#define MCM_PLACR_DFCDA_MASK                     (0x800U)
+#define MCM_PLACR_DFCDA_SHIFT                    (11U)
+#define MCM_PLACR_DFCDA(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK)
+#define MCM_PLACR_DFCIC_MASK                     (0x1000U)
+#define MCM_PLACR_DFCIC_SHIFT                    (12U)
+#define MCM_PLACR_DFCIC(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK)
+#define MCM_PLACR_DFCC_MASK                      (0x2000U)
+#define MCM_PLACR_DFCC_SHIFT                     (13U)
+#define MCM_PLACR_DFCC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK)
+#define MCM_PLACR_EFDS_MASK                      (0x4000U)
+#define MCM_PLACR_EFDS_SHIFT                     (14U)
+#define MCM_PLACR_EFDS(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
+#define MCM_PLACR_DFCS_MASK                      (0x8000U)
+#define MCM_PLACR_DFCS_SHIFT                     (15U)
+#define MCM_PLACR_DFCS(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
+#define MCM_PLACR_ESFC_MASK                      (0x10000U)
+#define MCM_PLACR_ESFC_SHIFT                     (16U)
+#define MCM_PLACR_ESFC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
+
+/*! @name CPO - Compute Operation Control Register */
+#define MCM_CPO_CPOREQ_MASK                      (0x1U)
+#define MCM_CPO_CPOREQ_SHIFT                     (0U)
+#define MCM_CPO_CPOREQ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
+#define MCM_CPO_CPOACK_MASK                      (0x2U)
+#define MCM_CPO_CPOACK_SHIFT                     (1U)
+#define MCM_CPO_CPOACK(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
+#define MCM_CPO_CPOWOI_MASK                      (0x4U)
+#define MCM_CPO_CPOWOI_SHIFT                     (2U)
+#define MCM_CPO_CPOWOI(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS                           { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS                            { MCM }
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
+ * @{
+ */
+
+/** MPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[8][4];                        /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[896];
+  __IO uint32_t RGDAAC[8];                         /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} MPU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Masks MPU Register Masks
+ * @{
+ */
+
+/*! @name CESR - Control/Error Status Register */
+#define MPU_CESR_VLD_MASK                        (0x1U)
+#define MPU_CESR_VLD_SHIFT                       (0U)
+#define MPU_CESR_VLD(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_CESR_VLD_SHIFT)) & MPU_CESR_VLD_MASK)
+#define MPU_CESR_NRGD_MASK                       (0xF00U)
+#define MPU_CESR_NRGD_SHIFT                      (8U)
+#define MPU_CESR_NRGD(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK)
+#define MPU_CESR_NSP_MASK                        (0xF000U)
+#define MPU_CESR_NSP_SHIFT                       (12U)
+#define MPU_CESR_NSP(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK)
+#define MPU_CESR_HRL_MASK                        (0xF0000U)
+#define MPU_CESR_HRL_SHIFT                       (16U)
+#define MPU_CESR_HRL(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK)
+#define MPU_CESR_SPERR_MASK                      (0xF8000000U)
+#define MPU_CESR_SPERR_SHIFT                     (27U)
+#define MPU_CESR_SPERR(x)                        (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK)
+
+/*! @name EAR - Error Address Register, slave port n */
+#define MPU_EAR_EADDR_MASK                       (0xFFFFFFFFU)
+#define MPU_EAR_EADDR_SHIFT                      (0U)
+#define MPU_EAR_EADDR(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_EAR_EADDR_SHIFT)) & MPU_EAR_EADDR_MASK)
+
+/* The count of MPU_EAR */
+#define MPU_EAR_COUNT                            (5U)
+
+/*! @name EDR - Error Detail Register, slave port n */
+#define MPU_EDR_ERW_MASK                         (0x1U)
+#define MPU_EDR_ERW_SHIFT                        (0U)
+#define MPU_EDR_ERW(x)                           (((uint32_t)(((uint32_t)(x)) << MPU_EDR_ERW_SHIFT)) & MPU_EDR_ERW_MASK)
+#define MPU_EDR_EATTR_MASK                       (0xEU)
+#define MPU_EDR_EATTR_SHIFT                      (1U)
+#define MPU_EDR_EATTR(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK)
+#define MPU_EDR_EMN_MASK                         (0xF0U)
+#define MPU_EDR_EMN_SHIFT                        (4U)
+#define MPU_EDR_EMN(x)                           (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK)
+#define MPU_EDR_EPID_MASK                        (0xFF00U)
+#define MPU_EDR_EPID_SHIFT                       (8U)
+#define MPU_EDR_EPID(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK)
+#define MPU_EDR_EACD_MASK                        (0xFFFF0000U)
+#define MPU_EDR_EACD_SHIFT                       (16U)
+#define MPU_EDR_EACD(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK)
+
+/* The count of MPU_EDR */
+#define MPU_EDR_COUNT                            (5U)
+
+/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
+#define MPU_WORD_VLD_MASK                        (0x1U)
+#define MPU_WORD_VLD_SHIFT                       (0U)
+#define MPU_WORD_VLD(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_WORD_VLD_SHIFT)) & MPU_WORD_VLD_MASK)
+#define MPU_WORD_M0UM_MASK                       (0x7U)
+#define MPU_WORD_M0UM_SHIFT                      (0U)
+#define MPU_WORD_M0UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK)
+#define MPU_WORD_M0SM_MASK                       (0x18U)
+#define MPU_WORD_M0SM_SHIFT                      (3U)
+#define MPU_WORD_M0SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK)
+#define MPU_WORD_M0PE_MASK                       (0x20U)
+#define MPU_WORD_M0PE_SHIFT                      (5U)
+#define MPU_WORD_M0PE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0PE_SHIFT)) & MPU_WORD_M0PE_MASK)
+#define MPU_WORD_ENDADDR_MASK                    (0xFFFFFFE0U)
+#define MPU_WORD_ENDADDR_SHIFT                   (5U)
+#define MPU_WORD_ENDADDR(x)                      (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK)
+#define MPU_WORD_SRTADDR_MASK                    (0xFFFFFFE0U)
+#define MPU_WORD_SRTADDR_SHIFT                   (5U)
+#define MPU_WORD_SRTADDR(x)                      (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK)
+#define MPU_WORD_M1UM_MASK                       (0x1C0U)
+#define MPU_WORD_M1UM_SHIFT                      (6U)
+#define MPU_WORD_M1UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK)
+#define MPU_WORD_M1SM_MASK                       (0x600U)
+#define MPU_WORD_M1SM_SHIFT                      (9U)
+#define MPU_WORD_M1SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK)
+#define MPU_WORD_M1PE_MASK                       (0x800U)
+#define MPU_WORD_M1PE_SHIFT                      (11U)
+#define MPU_WORD_M1PE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1PE_SHIFT)) & MPU_WORD_M1PE_MASK)
+#define MPU_WORD_M2UM_MASK                       (0x7000U)
+#define MPU_WORD_M2UM_SHIFT                      (12U)
+#define MPU_WORD_M2UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK)
+#define MPU_WORD_M2SM_MASK                       (0x18000U)
+#define MPU_WORD_M2SM_SHIFT                      (15U)
+#define MPU_WORD_M2SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK)
+#define MPU_WORD_PIDMASK_MASK                    (0xFF0000U)
+#define MPU_WORD_PIDMASK_SHIFT                   (16U)
+#define MPU_WORD_PIDMASK(x)                      (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK)
+#define MPU_WORD_M2PE_MASK                       (0x20000U)
+#define MPU_WORD_M2PE_SHIFT                      (17U)
+#define MPU_WORD_M2PE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2PE_SHIFT)) & MPU_WORD_M2PE_MASK)
+#define MPU_WORD_M3UM_MASK                       (0x1C0000U)
+#define MPU_WORD_M3UM_SHIFT                      (18U)
+#define MPU_WORD_M3UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK)
+#define MPU_WORD_M3SM_MASK                       (0x600000U)
+#define MPU_WORD_M3SM_SHIFT                      (21U)
+#define MPU_WORD_M3SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK)
+#define MPU_WORD_M3PE_MASK                       (0x800000U)
+#define MPU_WORD_M3PE_SHIFT                      (23U)
+#define MPU_WORD_M3PE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3PE_SHIFT)) & MPU_WORD_M3PE_MASK)
+#define MPU_WORD_PID_MASK                        (0xFF000000U)
+#define MPU_WORD_PID_SHIFT                       (24U)
+#define MPU_WORD_PID(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK)
+#define MPU_WORD_M4WE_MASK                       (0x1000000U)
+#define MPU_WORD_M4WE_SHIFT                      (24U)
+#define MPU_WORD_M4WE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4WE_SHIFT)) & MPU_WORD_M4WE_MASK)
+#define MPU_WORD_M4RE_MASK                       (0x2000000U)
+#define MPU_WORD_M4RE_SHIFT                      (25U)
+#define MPU_WORD_M4RE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4RE_SHIFT)) & MPU_WORD_M4RE_MASK)
+#define MPU_WORD_M5WE_MASK                       (0x4000000U)
+#define MPU_WORD_M5WE_SHIFT                      (26U)
+#define MPU_WORD_M5WE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5WE_SHIFT)) & MPU_WORD_M5WE_MASK)
+#define MPU_WORD_M5RE_MASK                       (0x8000000U)
+#define MPU_WORD_M5RE_SHIFT                      (27U)
+#define MPU_WORD_M5RE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5RE_SHIFT)) & MPU_WORD_M5RE_MASK)
+#define MPU_WORD_M6WE_MASK                       (0x10000000U)
+#define MPU_WORD_M6WE_SHIFT                      (28U)
+#define MPU_WORD_M6WE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6WE_SHIFT)) & MPU_WORD_M6WE_MASK)
+#define MPU_WORD_M6RE_MASK                       (0x20000000U)
+#define MPU_WORD_M6RE_SHIFT                      (29U)
+#define MPU_WORD_M6RE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6RE_SHIFT)) & MPU_WORD_M6RE_MASK)
+#define MPU_WORD_M7WE_MASK                       (0x40000000U)
+#define MPU_WORD_M7WE_SHIFT                      (30U)
+#define MPU_WORD_M7WE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7WE_SHIFT)) & MPU_WORD_M7WE_MASK)
+#define MPU_WORD_M7RE_MASK                       (0x80000000U)
+#define MPU_WORD_M7RE_SHIFT                      (31U)
+#define MPU_WORD_M7RE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7RE_SHIFT)) & MPU_WORD_M7RE_MASK)
+
+/* The count of MPU_WORD */
+#define MPU_WORD_COUNT                           (8U)
+
+/* The count of MPU_WORD */
+#define MPU_WORD_COUNT2                          (4U)
+
+/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
+#define MPU_RGDAAC_M0UM_MASK                     (0x7U)
+#define MPU_RGDAAC_M0UM_SHIFT                    (0U)
+#define MPU_RGDAAC_M0UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK)
+#define MPU_RGDAAC_M0SM_MASK                     (0x18U)
+#define MPU_RGDAAC_M0SM_SHIFT                    (3U)
+#define MPU_RGDAAC_M0SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK)
+#define MPU_RGDAAC_M0PE_MASK                     (0x20U)
+#define MPU_RGDAAC_M0PE_SHIFT                    (5U)
+#define MPU_RGDAAC_M0PE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0PE_SHIFT)) & MPU_RGDAAC_M0PE_MASK)
+#define MPU_RGDAAC_M1UM_MASK                     (0x1C0U)
+#define MPU_RGDAAC_M1UM_SHIFT                    (6U)
+#define MPU_RGDAAC_M1UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK)
+#define MPU_RGDAAC_M1SM_MASK                     (0x600U)
+#define MPU_RGDAAC_M1SM_SHIFT                    (9U)
+#define MPU_RGDAAC_M1SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK)
+#define MPU_RGDAAC_M1PE_MASK                     (0x800U)
+#define MPU_RGDAAC_M1PE_SHIFT                    (11U)
+#define MPU_RGDAAC_M1PE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1PE_SHIFT)) & MPU_RGDAAC_M1PE_MASK)
+#define MPU_RGDAAC_M2UM_MASK                     (0x7000U)
+#define MPU_RGDAAC_M2UM_SHIFT                    (12U)
+#define MPU_RGDAAC_M2UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK)
+#define MPU_RGDAAC_M2SM_MASK                     (0x18000U)
+#define MPU_RGDAAC_M2SM_SHIFT                    (15U)
+#define MPU_RGDAAC_M2SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK)
+#define MPU_RGDAAC_M2PE_MASK                     (0x20000U)
+#define MPU_RGDAAC_M2PE_SHIFT                    (17U)
+#define MPU_RGDAAC_M2PE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2PE_SHIFT)) & MPU_RGDAAC_M2PE_MASK)
+#define MPU_RGDAAC_M3UM_MASK                     (0x1C0000U)
+#define MPU_RGDAAC_M3UM_SHIFT                    (18U)
+#define MPU_RGDAAC_M3UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK)
+#define MPU_RGDAAC_M3SM_MASK                     (0x600000U)
+#define MPU_RGDAAC_M3SM_SHIFT                    (21U)
+#define MPU_RGDAAC_M3SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK)
+#define MPU_RGDAAC_M3PE_MASK                     (0x800000U)
+#define MPU_RGDAAC_M3PE_SHIFT                    (23U)
+#define MPU_RGDAAC_M3PE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3PE_SHIFT)) & MPU_RGDAAC_M3PE_MASK)
+#define MPU_RGDAAC_M4WE_MASK                     (0x1000000U)
+#define MPU_RGDAAC_M4WE_SHIFT                    (24U)
+#define MPU_RGDAAC_M4WE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4WE_SHIFT)) & MPU_RGDAAC_M4WE_MASK)
+#define MPU_RGDAAC_M4RE_MASK                     (0x2000000U)
+#define MPU_RGDAAC_M4RE_SHIFT                    (25U)
+#define MPU_RGDAAC_M4RE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4RE_SHIFT)) & MPU_RGDAAC_M4RE_MASK)
+#define MPU_RGDAAC_M5WE_MASK                     (0x4000000U)
+#define MPU_RGDAAC_M5WE_SHIFT                    (26U)
+#define MPU_RGDAAC_M5WE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5WE_SHIFT)) & MPU_RGDAAC_M5WE_MASK)
+#define MPU_RGDAAC_M5RE_MASK                     (0x8000000U)
+#define MPU_RGDAAC_M5RE_SHIFT                    (27U)
+#define MPU_RGDAAC_M5RE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5RE_SHIFT)) & MPU_RGDAAC_M5RE_MASK)
+#define MPU_RGDAAC_M6WE_MASK                     (0x10000000U)
+#define MPU_RGDAAC_M6WE_SHIFT                    (28U)
+#define MPU_RGDAAC_M6WE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6WE_SHIFT)) & MPU_RGDAAC_M6WE_MASK)
+#define MPU_RGDAAC_M6RE_MASK                     (0x20000000U)
+#define MPU_RGDAAC_M6RE_SHIFT                    (29U)
+#define MPU_RGDAAC_M6RE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6RE_SHIFT)) & MPU_RGDAAC_M6RE_MASK)
+#define MPU_RGDAAC_M7WE_MASK                     (0x40000000U)
+#define MPU_RGDAAC_M7WE_SHIFT                    (30U)
+#define MPU_RGDAAC_M7WE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7WE_SHIFT)) & MPU_RGDAAC_M7WE_MASK)
+#define MPU_RGDAAC_M7RE_MASK                     (0x80000000U)
+#define MPU_RGDAAC_M7RE_SHIFT                    (31U)
+#define MPU_RGDAAC_M7RE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7RE_SHIFT)) & MPU_RGDAAC_M7RE_MASK)
+
+/* The count of MPU_RGDAAC */
+#define MPU_RGDAAC_COUNT                         (8U)
+
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Masks */
+
+
+/* MPU - Peripheral instance base addresses */
+/** Peripheral MPU base address */
+#define MPU_BASE                                 (0x4000D000u)
+/** Peripheral MPU base pointer */
+#define MPU                                      ((MPU_Type *)MPU_BASE)
+/** Array initializer of MPU peripheral base addresses */
+#define MPU_BASE_ADDRS                           { MPU_BASE }
+/** Array initializer of MPU peripheral base pointers */
+#define MPU_BASE_PTRS                            { MPU }
+
+/*!
+ * @}
+ */ /* end of group MPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MTB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t POSITION;                          /**< MTB Position Register, offset: 0x0 */
+  __IO uint32_t MASTER;                            /**< MTB Master Register, offset: 0x4 */
+  __IO uint32_t FLOW;                              /**< MTB Flow Register, offset: 0x8 */
+  __I  uint32_t BASE;                              /**< MTB Base Register, offset: 0xC */
+       uint8_t RESERVED_0[3824];
+  __I  uint32_t MODECTRL;                          /**< Integration Mode Control Register, offset: 0xF00 */
+       uint8_t RESERVED_1[156];
+  __I  uint32_t TAGSET;                            /**< Claim TAG Set Register, offset: 0xFA0 */
+  __I  uint32_t TAGCLEAR;                          /**< Claim TAG Clear Register, offset: 0xFA4 */
+       uint8_t RESERVED_2[8];
+  __I  uint32_t LOCKACCESS;                        /**< Lock Access Register, offset: 0xFB0 */
+  __I  uint32_t LOCKSTAT;                          /**< Lock Status Register, offset: 0xFB4 */
+  __I  uint32_t AUTHSTAT;                          /**< Authentication Status Register, offset: 0xFB8 */
+  __I  uint32_t DEVICEARCH;                        /**< Device Architecture Register, offset: 0xFBC */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
+  __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
+  __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
+  __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
+  __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
+  __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
+  __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
+  __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
+  __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MTB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/*! @name POSITION - MTB Position Register */
+#define MTB_POSITION_WRAP_MASK                   (0x4U)
+#define MTB_POSITION_WRAP_SHIFT                  (2U)
+#define MTB_POSITION_WRAP(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
+#define MTB_POSITION_POINTER_MASK                (0xFFFFFFF8U)
+#define MTB_POSITION_POINTER_SHIFT               (3U)
+#define MTB_POSITION_POINTER(x)                  (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
+
+/*! @name MASTER - MTB Master Register */
+#define MTB_MASTER_MASK_MASK                     (0x1FU)
+#define MTB_MASTER_MASK_SHIFT                    (0U)
+#define MTB_MASTER_MASK(x)                       (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK                 (0x20U)
+#define MTB_MASTER_TSTARTEN_SHIFT                (5U)
+#define MTB_MASTER_TSTARTEN(x)                   (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
+#define MTB_MASTER_TSTOPEN_MASK                  (0x40U)
+#define MTB_MASTER_TSTOPEN_SHIFT                 (6U)
+#define MTB_MASTER_TSTOPEN(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
+#define MTB_MASTER_SFRWPRIV_MASK                 (0x80U)
+#define MTB_MASTER_SFRWPRIV_SHIFT                (7U)
+#define MTB_MASTER_SFRWPRIV(x)                   (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
+#define MTB_MASTER_RAMPRIV_MASK                  (0x100U)
+#define MTB_MASTER_RAMPRIV_SHIFT                 (8U)
+#define MTB_MASTER_RAMPRIV(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
+#define MTB_MASTER_HALTREQ_MASK                  (0x200U)
+#define MTB_MASTER_HALTREQ_SHIFT                 (9U)
+#define MTB_MASTER_HALTREQ(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
+#define MTB_MASTER_EN_MASK                       (0x80000000U)
+#define MTB_MASTER_EN_SHIFT                      (31U)
+#define MTB_MASTER_EN(x)                         (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
+
+/*! @name FLOW - MTB Flow Register */
+#define MTB_FLOW_AUTOSTOP_MASK                   (0x1U)
+#define MTB_FLOW_AUTOSTOP_SHIFT                  (0U)
+#define MTB_FLOW_AUTOSTOP(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
+#define MTB_FLOW_AUTOHALT_MASK                   (0x2U)
+#define MTB_FLOW_AUTOHALT_SHIFT                  (1U)
+#define MTB_FLOW_AUTOHALT(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
+#define MTB_FLOW_WATERMARK_MASK                  (0xFFFFFFF8U)
+#define MTB_FLOW_WATERMARK_SHIFT                 (3U)
+#define MTB_FLOW_WATERMARK(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
+
+/*! @name BASE - MTB Base Register */
+#define MTB_BASE_BASEADDR_MASK                   (0xFFFFFFFFU)
+#define MTB_BASE_BASEADDR_SHIFT                  (0U)
+#define MTB_BASE_BASEADDR(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
+
+/*! @name MODECTRL - Integration Mode Control Register */
+#define MTB_MODECTRL_MODECTRL_MASK               (0xFFFFFFFFU)
+#define MTB_MODECTRL_MODECTRL_SHIFT              (0U)
+#define MTB_MODECTRL_MODECTRL(x)                 (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
+
+/*! @name TAGSET - Claim TAG Set Register */
+#define MTB_TAGSET_TAGSET_MASK                   (0xFFFFFFFFU)
+#define MTB_TAGSET_TAGSET_SHIFT                  (0U)
+#define MTB_TAGSET_TAGSET(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
+
+/*! @name TAGCLEAR - Claim TAG Clear Register */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK               (0xFFFFFFFFU)
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT              (0U)
+#define MTB_TAGCLEAR_TAGCLEAR(x)                 (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
+
+/*! @name LOCKACCESS - Lock Access Register */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK           (0xFFFFFFFFU)
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT          (0U)
+#define MTB_LOCKACCESS_LOCKACCESS(x)             (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
+
+/*! @name LOCKSTAT - Lock Status Register */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK               (0xFFFFFFFFU)
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT              (0U)
+#define MTB_LOCKSTAT_LOCKSTAT(x)                 (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
+
+/*! @name AUTHSTAT - Authentication Status Register */
+#define MTB_AUTHSTAT_BIT0_MASK                   (0x1U)
+#define MTB_AUTHSTAT_BIT0_SHIFT                  (0U)
+#define MTB_AUTHSTAT_BIT0(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
+#define MTB_AUTHSTAT_BIT2_MASK                   (0x4U)
+#define MTB_AUTHSTAT_BIT2_SHIFT                  (2U)
+#define MTB_AUTHSTAT_BIT2(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
+
+/*! @name DEVICEARCH - Device Architecture Register */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK           (0xFFFFFFFFU)
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT          (0U)
+#define MTB_DEVICEARCH_DEVICEARCH(x)             (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
+
+/*! @name DEVICECFG - Device Configuration Register */
+#define MTB_DEVICECFG_DEVICECFG_MASK             (0xFFFFFFFFU)
+#define MTB_DEVICECFG_DEVICECFG_SHIFT            (0U)
+#define MTB_DEVICECFG_DEVICECFG(x)               (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
+
+/*! @name DEVICETYPID - Device Type Identifier Register */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK         (0xFFFFFFFFU)
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT        (0U)
+#define MTB_DEVICETYPID_DEVICETYPID(x)           (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+#define MTB_PERIPHID4_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID4_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID4_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK)
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+#define MTB_PERIPHID5_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID5_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID5_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK)
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+#define MTB_PERIPHID6_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID6_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID6_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK)
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+#define MTB_PERIPHID7_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID7_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID7_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK)
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+#define MTB_PERIPHID0_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID0_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID0_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK)
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+#define MTB_PERIPHID1_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID1_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID1_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK)
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+#define MTB_PERIPHID2_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID2_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID2_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK)
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+#define MTB_PERIPHID3_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID3_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID3_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK)
+
+/*! @name COMPID - Component ID Register */
+#define MTB_COMPID_COMPID_MASK                   (0xFFFFFFFFU)
+#define MTB_COMPID_COMPID_SHIFT                  (0U)
+#define MTB_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
+
+/* The count of MTB_COMPID */
+#define MTB_COMPID_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE                                 (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB                                      ((MTB_Type *)MTB_BASE)
+/** Array initializer of MTB peripheral base addresses */
+#define MTB_BASE_ADDRS                           { MTB_BASE }
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASE_PTRS                            { MTB }
+
+/*!
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MTBDWT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t CTRL;                              /**< MTB DWT Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  struct {                                         /* offset: 0x20, array step: 0x10 */
+    __IO uint32_t COMP;                              /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+    __IO uint32_t MASK;                              /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+    __IO uint32_t FCT;                               /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } COMPARATOR[2];
+       uint8_t RESERVED_1[448];
+  __IO uint32_t TBCTRL;                            /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+       uint8_t RESERVED_2[3524];
+  __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
+  __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
+  __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
+  __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
+  __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
+  __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
+  __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
+  __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
+  __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MTBDWT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/*! @name CTRL - MTB DWT Control Register */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK              (0xFFFFFFFU)
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT             (0U)
+#define MTBDWT_CTRL_DWTCFGCTRL(x)                (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK                  (0xF0000000U)
+#define MTBDWT_CTRL_NUMCMP_SHIFT                 (28U)
+#define MTBDWT_CTRL_NUMCMP(x)                    (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK)
+
+/*! @name COMP - MTB_DWT Comparator Register */
+#define MTBDWT_COMP_COMP_MASK                    (0xFFFFFFFFU)
+#define MTBDWT_COMP_COMP_SHIFT                   (0U)
+#define MTBDWT_COMP_COMP(x)                      (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK)
+
+/* The count of MTBDWT_COMP */
+#define MTBDWT_COMP_COUNT                        (2U)
+
+/*! @name MASK - MTB_DWT Comparator Mask Register */
+#define MTBDWT_MASK_MASK_MASK                    (0x1FU)
+#define MTBDWT_MASK_MASK_SHIFT                   (0U)
+#define MTBDWT_MASK_MASK(x)                      (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK)
+
+/* The count of MTBDWT_MASK */
+#define MTBDWT_MASK_COUNT                        (2U)
+
+/*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */
+#define MTBDWT_FCT_FUNCTION_MASK                 (0xFU)
+#define MTBDWT_FCT_FUNCTION_SHIFT                (0U)
+#define MTBDWT_FCT_FUNCTION(x)                   (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK               (0x100U)
+#define MTBDWT_FCT_DATAVMATCH_SHIFT              (8U)
+#define MTBDWT_FCT_DATAVMATCH(x)                 (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK)
+#define MTBDWT_FCT_DATAVSIZE_MASK                (0xC00U)
+#define MTBDWT_FCT_DATAVSIZE_SHIFT               (10U)
+#define MTBDWT_FCT_DATAVSIZE(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK               (0xF000U)
+#define MTBDWT_FCT_DATAVADDR0_SHIFT              (12U)
+#define MTBDWT_FCT_DATAVADDR0(x)                 (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK                  (0x1000000U)
+#define MTBDWT_FCT_MATCHED_SHIFT                 (24U)
+#define MTBDWT_FCT_MATCHED(x)                    (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK)
+
+/* The count of MTBDWT_FCT */
+#define MTBDWT_FCT_COUNT                         (2U)
+
+/*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */
+#define MTBDWT_TBCTRL_ACOMP0_MASK                (0x1U)
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT               (0U)
+#define MTBDWT_TBCTRL_ACOMP0(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK)
+#define MTBDWT_TBCTRL_ACOMP1_MASK                (0x2U)
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT               (1U)
+#define MTBDWT_TBCTRL_ACOMP1(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK)
+#define MTBDWT_TBCTRL_NUMCOMP_MASK               (0xF0000000U)
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT              (28U)
+#define MTBDWT_TBCTRL_NUMCOMP(x)                 (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK)
+
+/*! @name DEVICECFG - Device Configuration Register */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK          (0xFFFFFFFFU)
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT         (0U)
+#define MTBDWT_DEVICECFG_DEVICECFG(x)            (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK)
+
+/*! @name DEVICETYPID - Device Type Identifier Register */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK      (0xFFFFFFFFU)
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT     (0U)
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x)        (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+#define MTBDWT_PERIPHID4_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID4_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID4_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK)
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+#define MTBDWT_PERIPHID5_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID5_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID5_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK)
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+#define MTBDWT_PERIPHID6_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID6_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID6_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK)
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+#define MTBDWT_PERIPHID7_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID7_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID7_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK)
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+#define MTBDWT_PERIPHID0_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID0_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID0_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK)
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+#define MTBDWT_PERIPHID1_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID1_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID1_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK)
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+#define MTBDWT_PERIPHID2_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID2_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID2_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK)
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+#define MTBDWT_PERIPHID3_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID3_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID3_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK)
+
+/*! @name COMPID - Component ID Register */
+#define MTBDWT_COMPID_COMPID_MASK                (0xFFFFFFFFU)
+#define MTBDWT_COMPID_COMPID_SHIFT               (0U)
+#define MTBDWT_COMPID_COMPID(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK)
+
+/* The count of MTBDWT_COMPID */
+#define MTBDWT_COMPID_COUNT                      (4U)
+
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE                              (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT                                   ((MTBDWT_Type *)MTBDWT_BASE)
+/** Array initializer of MTBDWT peripheral base addresses */
+#define MTBDWT_BASE_ADDRS                        { MTBDWT_BASE }
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASE_PTRS                         { MTBDWT }
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
+#define NV_BACKKEY3_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY3_KEY_SHIFT                    (0U)
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
+
+/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
+#define NV_BACKKEY2_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY2_KEY_SHIFT                    (0U)
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
+
+/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
+#define NV_BACKKEY1_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY1_KEY_SHIFT                    (0U)
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
+
+/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
+#define NV_BACKKEY0_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY0_KEY_SHIFT                    (0U)
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
+
+/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
+#define NV_BACKKEY7_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY7_KEY_SHIFT                    (0U)
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
+
+/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
+#define NV_BACKKEY6_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY6_KEY_SHIFT                    (0U)
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
+
+/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
+#define NV_BACKKEY5_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY5_KEY_SHIFT                    (0U)
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
+
+/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
+#define NV_BACKKEY4_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY4_KEY_SHIFT                    (0U)
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
+
+/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
+#define NV_FPROT3_PROT_MASK                      (0xFFU)
+#define NV_FPROT3_PROT_SHIFT                     (0U)
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
+#define NV_FPROT2_PROT_MASK                      (0xFFU)
+#define NV_FPROT2_PROT_SHIFT                     (0U)
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
+#define NV_FPROT1_PROT_MASK                      (0xFFU)
+#define NV_FPROT1_PROT_SHIFT                     (0U)
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
+#define NV_FPROT0_PROT_MASK                      (0xFFU)
+#define NV_FPROT0_PROT_SHIFT                     (0U)
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
+
+/*! @name FSEC - Non-volatile Flash Security Register */
+#define NV_FSEC_SEC_MASK                         (0x3U)
+#define NV_FSEC_SEC_SHIFT                        (0U)
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      (0xCU)
+#define NV_FSEC_FSLACC_SHIFT                     (2U)
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        (0x30U)
+#define NV_FSEC_MEEN_SHIFT                       (4U)
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       (0xC0U)
+#define NV_FSEC_KEYEN_SHIFT                      (6U)
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Non-volatile Flash Option Register */
+#define NV_FOPT_LPBOOT_MASK                      (0x1U)
+#define NV_FOPT_LPBOOT_SHIFT                     (0U)
+#define NV_FOPT_LPBOOT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_BOOTPIN_OPT_MASK                 (0x2U)
+#define NV_FOPT_BOOTPIN_OPT_SHIFT                (1U)
+#define NV_FOPT_BOOTPIN_OPT(x)                   (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK)
+#define NV_FOPT_NMI_DIS_MASK                     (0x4U)
+#define NV_FOPT_NMI_DIS_SHIFT                    (2U)
+#define NV_FOPT_NMI_DIS(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
+#define NV_FOPT_FAST_INIT_MASK                   (0x20U)
+#define NV_FOPT_FAST_INIT_SHIFT                  (5U)
+#define NV_FOPT_FAST_INIT(x)                     (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
+#define NV_FOPT_BOOTSRC_SEL_MASK                 (0xC0U)
+#define NV_FOPT_BOOTSRC_SEL_SHIFT                (6U)
+#define NV_FOPT_BOOTSRC_SEL(x)                   (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE                    (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig                         ((NV_Type *)FTFA_FlashConfig_BASE)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS                            { FTFA_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS                             { FTFA_FlashConfig }
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t DIV;                                /**< OSC_DIV, offset: 0x2 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/*! @name CR - OSC Control Register */
+#define OSC_CR_SC16P_MASK                        (0x1U)
+#define OSC_CR_SC16P_SHIFT                       (0U)
+#define OSC_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK                         (0x2U)
+#define OSC_CR_SC8P_SHIFT                        (1U)
+#define OSC_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK                         (0x4U)
+#define OSC_CR_SC4P_SHIFT                        (2U)
+#define OSC_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK                         (0x8U)
+#define OSC_CR_SC2P_SHIFT                        (3U)
+#define OSC_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK                     (0x20U)
+#define OSC_CR_EREFSTEN_SHIFT                    (5U)
+#define OSC_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK                      (0x80U)
+#define OSC_CR_ERCLKEN_SHIFT                     (7U)
+#define OSC_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
+
+/*! @name DIV - OSC_DIV */
+#define OSC_DIV_ERPS_MASK                        (0xC0U)
+#define OSC_DIV_ERPS_SHIFT                       (6U)
+#define OSC_DIV_ERPS(x)                          (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE                                 (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC                                      ((OSC_Type *)OSC_BASE)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS                           { OSC_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS                            { OSC }
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[220];
+  __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+  __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+       uint8_t RESERVED_1[24];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[4];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/*! @name MCR - PIT Module Control Register */
+#define PIT_MCR_FRZ_MASK                         (0x1U)
+#define PIT_MCR_FRZ_SHIFT                        (0U)
+#define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK                        (0x2U)
+#define PIT_MCR_MDIS_SHIFT                       (1U)
+#define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
+
+/*! @name LTMR64H - PIT Upper Lifetime Timer Register */
+#define PIT_LTMR64H_LTH_MASK                     (0xFFFFFFFFU)
+#define PIT_LTMR64H_LTH_SHIFT                    (0U)
+#define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
+
+/*! @name LTMR64L - PIT Lower Lifetime Timer Register */
+#define PIT_LTMR64L_LTL_MASK                     (0xFFFFFFFFU)
+#define PIT_LTMR64L_LTL_SHIFT                    (0U)
+#define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
+
+/*! @name LDVAL - Timer Load Value Register */
+#define PIT_LDVAL_TSV_MASK                       (0xFFFFFFFFU)
+#define PIT_LDVAL_TSV_SHIFT                      (0U)
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
+
+/* The count of PIT_LDVAL */
+#define PIT_LDVAL_COUNT                          (4U)
+
+/*! @name CVAL - Current Timer Value Register */
+#define PIT_CVAL_TVL_MASK                        (0xFFFFFFFFU)
+#define PIT_CVAL_TVL_SHIFT                       (0U)
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
+
+/* The count of PIT_CVAL */
+#define PIT_CVAL_COUNT                           (4U)
+
+/*! @name TCTRL - Timer Control Register */
+#define PIT_TCTRL_TEN_MASK                       (0x1U)
+#define PIT_TCTRL_TEN_SHIFT                      (0U)
+#define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK                       (0x2U)
+#define PIT_TCTRL_TIE_SHIFT                      (1U)
+#define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK                       (0x4U)
+#define PIT_TCTRL_CHN_SHIFT                      (2U)
+#define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
+
+/* The count of PIT_TCTRL */
+#define PIT_TCTRL_COUNT                          (4U)
+
+/*! @name TFLG - Timer Flag Register */
+#define PIT_TFLG_TIF_MASK                        (0x1U)
+#define PIT_TFLG_TIF_SHIFT                       (0U)
+#define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
+
+/* The count of PIT_TFLG */
+#define PIT_TFLG_COUNT                           (4U)
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT0 base address */
+#define PIT0_BASE                                (0x40037000u)
+/** Peripheral PIT0 base pointer */
+#define PIT0                                     ((PIT_Type *)PIT0_BASE)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS                           { PIT0_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS                            { PIT0 }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { PIT0_IRQn, PIT0_IRQn, PIT0_IRQn, PIT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
+       uint8_t RESERVED_0[8];
+  __IO uint8_t HVDSC1;                             /**< High Voltage Detect Status And Control 1 register, offset: 0xB */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
+#define PMC_LVDSC1_LVDV_MASK                     (0x3U)
+#define PMC_LVDSC1_LVDV_SHIFT                    (0U)
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK                    (0x10U)
+#define PMC_LVDSC1_LVDRE_SHIFT                   (4U)
+#define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK                    (0x20U)
+#define PMC_LVDSC1_LVDIE_SHIFT                   (5U)
+#define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK                   (0x40U)
+#define PMC_LVDSC1_LVDACK_SHIFT                  (6U)
+#define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK                     (0x80U)
+#define PMC_LVDSC1_LVDF_SHIFT                    (7U)
+#define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
+
+/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
+#define PMC_LVDSC2_LVWV_MASK                     (0x3U)
+#define PMC_LVDSC2_LVWV_SHIFT                    (0U)
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK                    (0x20U)
+#define PMC_LVDSC2_LVWIE_SHIFT                   (5U)
+#define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK                   (0x40U)
+#define PMC_LVDSC2_LVWACK_SHIFT                  (6U)
+#define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK                     (0x80U)
+#define PMC_LVDSC2_LVWF_SHIFT                    (7U)
+#define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
+
+/*! @name REGSC - Regulator Status And Control register */
+#define PMC_REGSC_BGBE_MASK                      (0x1U)
+#define PMC_REGSC_BGBE_SHIFT                     (0U)
+#define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK                    (0x4U)
+#define PMC_REGSC_REGONS_SHIFT                   (2U)
+#define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK                    (0x8U)
+#define PMC_REGSC_ACKISO_SHIFT                   (3U)
+#define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK                      (0x10U)
+#define PMC_REGSC_BGEN_SHIFT                     (4U)
+#define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
+#define PMC_REGSC_VLPO_MASK                      (0x40U)
+#define PMC_REGSC_VLPO_SHIFT                     (6U)
+#define PMC_REGSC_VLPO(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_VLPO_SHIFT)) & PMC_REGSC_VLPO_MASK)
+
+/*! @name HVDSC1 - High Voltage Detect Status And Control 1 register */
+#define PMC_HVDSC1_HVDV_MASK                     (0x1U)
+#define PMC_HVDSC1_HVDV_SHIFT                    (0U)
+#define PMC_HVDSC1_HVDV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDV_SHIFT)) & PMC_HVDSC1_HVDV_MASK)
+#define PMC_HVDSC1_HVDRE_MASK                    (0x10U)
+#define PMC_HVDSC1_HVDRE_SHIFT                   (4U)
+#define PMC_HVDSC1_HVDRE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDRE_SHIFT)) & PMC_HVDSC1_HVDRE_MASK)
+#define PMC_HVDSC1_HVDIE_MASK                    (0x20U)
+#define PMC_HVDSC1_HVDIE_SHIFT                   (5U)
+#define PMC_HVDSC1_HVDIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDIE_SHIFT)) & PMC_HVDSC1_HVDIE_MASK)
+#define PMC_HVDSC1_HVDACK_MASK                   (0x40U)
+#define PMC_HVDSC1_HVDACK_SHIFT                  (6U)
+#define PMC_HVDSC1_HVDACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDACK_SHIFT)) & PMC_HVDSC1_HVDACK_MASK)
+#define PMC_HVDSC1_HVDF_MASK                     (0x80U)
+#define PMC_HVDSC1_HVDF_SHIFT                    (7U)
+#define PMC_HVDSC1_HVDF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDF_SHIFT)) & PMC_HVDSC1_HVDF_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS                           { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { PMC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+  __O  uint32_t GICLR;                             /**< Global Interrupt Control Low Register, offset: 0x88 */
+  __O  uint32_t GICHR;                             /**< Global Interrupt Control High Register, offset: 0x8C */
+       uint8_t RESERVED_0[16];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/*! @name PCR - Pin Control Register n */
+#define PORT_PCR_PS_MASK                         (0x1U)
+#define PORT_PCR_PS_SHIFT                        (0U)
+#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK                         (0x2U)
+#define PORT_PCR_PE_SHIFT                        (1U)
+#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK                        (0x4U)
+#define PORT_PCR_SRE_SHIFT                       (2U)
+#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK                        (0x10U)
+#define PORT_PCR_PFE_SHIFT                       (4U)
+#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK                        (0x20U)
+#define PORT_PCR_ODE_SHIFT                       (5U)
+#define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
+#define PORT_PCR_MUX_MASK                        (0x700U)
+#define PORT_PCR_MUX_SHIFT                       (8U)
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK                         (0x8000U)
+#define PORT_PCR_LK_SHIFT                        (15U)
+#define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK                       (0xF0000U)
+#define PORT_PCR_IRQC_SHIFT                      (16U)
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        (0x1000000U)
+#define PORT_PCR_ISF_SHIFT                       (24U)
+#define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
+
+/* The count of PORT_PCR */
+#define PORT_PCR_COUNT                           (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+#define PORT_GPCLR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT                    (0U)
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT                    (16U)
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+
+/*! @name GPCHR - Global Pin Control High Register */
+#define PORT_GPCHR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT                    (0U)
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT                    (16U)
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+
+/*! @name GICLR - Global Interrupt Control Low Register */
+#define PORT_GICLR_GIWE_MASK                     (0xFFFFU)
+#define PORT_GICLR_GIWE_SHIFT                    (0U)
+#define PORT_GICLR_GIWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWE_SHIFT)) & PORT_GICLR_GIWE_MASK)
+#define PORT_GICLR_GIWD_MASK                     (0xFFFF0000U)
+#define PORT_GICLR_GIWD_SHIFT                    (16U)
+#define PORT_GICLR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWD_SHIFT)) & PORT_GICLR_GIWD_MASK)
+
+/*! @name GICHR - Global Interrupt Control High Register */
+#define PORT_GICHR_GIWE_MASK                     (0xFFFFU)
+#define PORT_GICHR_GIWE_SHIFT                    (0U)
+#define PORT_GICHR_GIWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWE_SHIFT)) & PORT_GICHR_GIWE_MASK)
+#define PORT_GICHR_GIWD_MASK                     (0xFFFF0000U)
+#define PORT_GICHR_GIWD_SHIFT                    (16U)
+#define PORT_GICHR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWD_SHIFT)) & PORT_GICHR_GIWD_MASK)
+
+/*! @name ISFR - Interrupt Status Flag Register */
+#define PORT_ISFR_ISF_MASK                       (0xFFFFFFFFU)
+#define PORT_ISFR_ISF_SHIFT                      (0U)
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- QuadSPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer
+ * @{
+ */
+
+/** QuadSPI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t IPCR;                              /**< IP Configuration Register, offset: 0x8 */
+  __IO uint32_t FLSHCR;                            /**< Flash Configuration Register, offset: 0xC */
+  __IO uint32_t BUF0CR;                            /**< Buffer0 Configuration Register, offset: 0x10 */
+  __IO uint32_t BUF1CR;                            /**< Buffer1 Configuration Register, offset: 0x14 */
+  __IO uint32_t BUF2CR;                            /**< Buffer2 Configuration Register, offset: 0x18 */
+  __IO uint32_t BUF3CR;                            /**< Buffer3 Configuration Register, offset: 0x1C */
+  __IO uint32_t BFGENCR;                           /**< Buffer Generic Configuration Register, offset: 0x20 */
+  __IO uint32_t SOCCR;                             /**< SOC Configuration Register, offset: 0x24 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t BUF0IND;                           /**< Buffer0 Top Index Register, offset: 0x30 */
+  __IO uint32_t BUF1IND;                           /**< Buffer1 Top Index Register, offset: 0x34 */
+  __IO uint32_t BUF2IND;                           /**< Buffer2 Top Index Register, offset: 0x38 */
+       uint8_t RESERVED_2[196];
+  __IO uint32_t SFAR;                              /**< Serial Flash Address Register, offset: 0x100 */
+  __IO uint32_t SFACR;                             /**< Serial Flash Address Configuration Register, offset: 0x104 */
+  __IO uint32_t SMPR;                              /**< Sampling Register, offset: 0x108 */
+  __I  uint32_t RBSR;                              /**< RX Buffer Status Register, offset: 0x10C */
+  __IO uint32_t RBCT;                              /**< RX Buffer Control Register, offset: 0x110 */
+       uint8_t RESERVED_3[60];
+  __I  uint32_t TBSR;                              /**< TX Buffer Status Register, offset: 0x150 */
+  __IO uint32_t TBDR;                              /**< TX Buffer Data Register, offset: 0x154 */
+  __IO uint32_t TBCT;                              /**< Tx Buffer Control Register, offset: 0x158 */
+  __I  uint32_t SR;                                /**< Status Register, offset: 0x15C */
+  __IO uint32_t FR;                                /**< Flag Register, offset: 0x160 */
+  __IO uint32_t RSER;                              /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */
+  __I  uint32_t SPNDST;                            /**< Sequence Suspend Status Register, offset: 0x168 */
+  __IO uint32_t SPTRCLR;                           /**< Sequence Pointer Clear Register, offset: 0x16C */
+       uint8_t RESERVED_4[16];
+  __IO uint32_t SFA1AD;                            /**< Serial Flash A1 Top Address, offset: 0x180 */
+  __IO uint32_t SFA2AD;                            /**< Serial Flash A2 Top Address, offset: 0x184 */
+  __IO uint32_t SFB1AD;                            /**< Serial Flash B1Top Address, offset: 0x188 */
+  __IO uint32_t SFB2AD;                            /**< Serial Flash B2Top Address, offset: 0x18C */
+  __IO uint32_t DLPR;                              /**< Data Learn Pattern Register, offset: 0x190 */
+       uint8_t RESERVED_5[108];
+  __I  uint32_t RBDR[16];                          /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_6[192];
+  __IO uint32_t LUTKEY;                            /**< LUT Key Register, offset: 0x300 */
+  __IO uint32_t LCKCR;                             /**< LUT Lock Configuration Register, offset: 0x304 */
+       uint8_t RESERVED_7[8];
+  __IO uint32_t LUT[64];                           /**< Look-up Table register, array offset: 0x310, array step: 0x4 */
+} QuadSPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- QuadSPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks
+ * @{
+ */
+
+/*! @name MCR - Module Configuration Register */
+#define QuadSPI_MCR_SWRSTSD_MASK                 (0x1U)
+#define QuadSPI_MCR_SWRSTSD_SHIFT                (0U)
+#define QuadSPI_MCR_SWRSTSD(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK)
+#define QuadSPI_MCR_SWRSTHD_MASK                 (0x2U)
+#define QuadSPI_MCR_SWRSTHD_SHIFT                (1U)
+#define QuadSPI_MCR_SWRSTHD(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
+#define QuadSPI_MCR_END_CFG_MASK                 (0xCU)
+#define QuadSPI_MCR_END_CFG_SHIFT                (2U)
+#define QuadSPI_MCR_END_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK)
+#define QuadSPI_MCR_DQS_LAT_EN_MASK              (0x20U)
+#define QuadSPI_MCR_DQS_LAT_EN_SHIFT             (5U)
+#define QuadSPI_MCR_DQS_LAT_EN(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LAT_EN_SHIFT)) & QuadSPI_MCR_DQS_LAT_EN_MASK)
+#define QuadSPI_MCR_DQS_EN_MASK                  (0x40U)
+#define QuadSPI_MCR_DQS_EN_SHIFT                 (6U)
+#define QuadSPI_MCR_DQS_EN(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK)
+#define QuadSPI_MCR_DDR_EN_MASK                  (0x80U)
+#define QuadSPI_MCR_DDR_EN_SHIFT                 (7U)
+#define QuadSPI_MCR_DDR_EN(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK)
+#define QuadSPI_MCR_CLR_RXF_MASK                 (0x400U)
+#define QuadSPI_MCR_CLR_RXF_SHIFT                (10U)
+#define QuadSPI_MCR_CLR_RXF(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK)
+#define QuadSPI_MCR_CLR_TXF_MASK                 (0x800U)
+#define QuadSPI_MCR_CLR_TXF_SHIFT                (11U)
+#define QuadSPI_MCR_CLR_TXF(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK)
+#define QuadSPI_MCR_MDIS_MASK                    (0x4000U)
+#define QuadSPI_MCR_MDIS_SHIFT                   (14U)
+#define QuadSPI_MCR_MDIS(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK)
+#define QuadSPI_MCR_SCLKCFG_MASK                 (0xFF000000U)
+#define QuadSPI_MCR_SCLKCFG_SHIFT                (24U)
+#define QuadSPI_MCR_SCLKCFG(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SCLKCFG_SHIFT)) & QuadSPI_MCR_SCLKCFG_MASK)
+
+/*! @name IPCR - IP Configuration Register */
+#define QuadSPI_IPCR_IDATSZ_MASK                 (0xFFFFU)
+#define QuadSPI_IPCR_IDATSZ_SHIFT                (0U)
+#define QuadSPI_IPCR_IDATSZ(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK)
+#define QuadSPI_IPCR_PAR_EN_MASK                 (0x10000U)
+#define QuadSPI_IPCR_PAR_EN_SHIFT                (16U)
+#define QuadSPI_IPCR_PAR_EN(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_PAR_EN_SHIFT)) & QuadSPI_IPCR_PAR_EN_MASK)
+#define QuadSPI_IPCR_SEQID_MASK                  (0xF000000U)
+#define QuadSPI_IPCR_SEQID_SHIFT                 (24U)
+#define QuadSPI_IPCR_SEQID(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
+
+/*! @name FLSHCR - Flash Configuration Register */
+#define QuadSPI_FLSHCR_TCSS_MASK                 (0xFU)
+#define QuadSPI_FLSHCR_TCSS_SHIFT                (0U)
+#define QuadSPI_FLSHCR_TCSS(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK)
+#define QuadSPI_FLSHCR_TCSH_MASK                 (0xF00U)
+#define QuadSPI_FLSHCR_TCSH_SHIFT                (8U)
+#define QuadSPI_FLSHCR_TCSH(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK)
+#define QuadSPI_FLSHCR_TDH_MASK                  (0x30000U)
+#define QuadSPI_FLSHCR_TDH_SHIFT                 (16U)
+#define QuadSPI_FLSHCR_TDH(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
+
+/*! @name BUF0CR - Buffer0 Configuration Register */
+#define QuadSPI_BUF0CR_MSTRID_MASK               (0xFU)
+#define QuadSPI_BUF0CR_MSTRID_SHIFT              (0U)
+#define QuadSPI_BUF0CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK)
+#define QuadSPI_BUF0CR_ADATSZ_MASK               (0x7F00U)
+#define QuadSPI_BUF0CR_ADATSZ_SHIFT              (8U)
+#define QuadSPI_BUF0CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK)
+#define QuadSPI_BUF0CR_HP_EN_MASK                (0x80000000U)
+#define QuadSPI_BUF0CR_HP_EN_SHIFT               (31U)
+#define QuadSPI_BUF0CR_HP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK)
+
+/*! @name BUF1CR - Buffer1 Configuration Register */
+#define QuadSPI_BUF1CR_MSTRID_MASK               (0xFU)
+#define QuadSPI_BUF1CR_MSTRID_SHIFT              (0U)
+#define QuadSPI_BUF1CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK)
+#define QuadSPI_BUF1CR_ADATSZ_MASK               (0x7F00U)
+#define QuadSPI_BUF1CR_ADATSZ_SHIFT              (8U)
+#define QuadSPI_BUF1CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK)
+
+/*! @name BUF2CR - Buffer2 Configuration Register */
+#define QuadSPI_BUF2CR_MSTRID_MASK               (0xFU)
+#define QuadSPI_BUF2CR_MSTRID_SHIFT              (0U)
+#define QuadSPI_BUF2CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK)
+#define QuadSPI_BUF2CR_ADATSZ_MASK               (0x7F00U)
+#define QuadSPI_BUF2CR_ADATSZ_SHIFT              (8U)
+#define QuadSPI_BUF2CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK)
+
+/*! @name BUF3CR - Buffer3 Configuration Register */
+#define QuadSPI_BUF3CR_MSTRID_MASK               (0xFU)
+#define QuadSPI_BUF3CR_MSTRID_SHIFT              (0U)
+#define QuadSPI_BUF3CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK)
+#define QuadSPI_BUF3CR_ADATSZ_MASK               (0x7F00U)
+#define QuadSPI_BUF3CR_ADATSZ_SHIFT              (8U)
+#define QuadSPI_BUF3CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK)
+#define QuadSPI_BUF3CR_ALLMST_MASK               (0x80000000U)
+#define QuadSPI_BUF3CR_ALLMST_SHIFT              (31U)
+#define QuadSPI_BUF3CR_ALLMST(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK)
+
+/*! @name BFGENCR - Buffer Generic Configuration Register */
+#define QuadSPI_BFGENCR_SEQID_MASK               (0xF000U)
+#define QuadSPI_BFGENCR_SEQID_SHIFT              (12U)
+#define QuadSPI_BFGENCR_SEQID(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK)
+#define QuadSPI_BFGENCR_PAR_EN_MASK              (0x10000U)
+#define QuadSPI_BFGENCR_PAR_EN_SHIFT             (16U)
+#define QuadSPI_BFGENCR_PAR_EN(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_PAR_EN_SHIFT)) & QuadSPI_BFGENCR_PAR_EN_MASK)
+
+/*! @name SOCCR - SOC Configuration Register */
+#define QuadSPI_SOCCR_QSPISRC_MASK               (0x7U)
+#define QuadSPI_SOCCR_QSPISRC_SHIFT              (0U)
+#define QuadSPI_SOCCR_QSPISRC(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_QSPISRC_SHIFT)) & QuadSPI_SOCCR_QSPISRC_MASK)
+#define QuadSPI_SOCCR_DQSLPEN_MASK               (0x100U)
+#define QuadSPI_SOCCR_DQSLPEN_SHIFT              (8U)
+#define QuadSPI_SOCCR_DQSLPEN(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSLPEN_SHIFT)) & QuadSPI_SOCCR_DQSLPEN_MASK)
+#define QuadSPI_SOCCR_DQSPADLPEN_MASK            (0x200U)
+#define QuadSPI_SOCCR_DQSPADLPEN_SHIFT           (9U)
+#define QuadSPI_SOCCR_DQSPADLPEN(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSPADLPEN_SHIFT)) & QuadSPI_SOCCR_DQSPADLPEN_MASK)
+#define QuadSPI_SOCCR_DQSPHASEL_MASK             (0xC00U)
+#define QuadSPI_SOCCR_DQSPHASEL_SHIFT            (10U)
+#define QuadSPI_SOCCR_DQSPHASEL(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSPHASEL_SHIFT)) & QuadSPI_SOCCR_DQSPHASEL_MASK)
+#define QuadSPI_SOCCR_DQSINVSEL_MASK             (0x1000U)
+#define QuadSPI_SOCCR_DQSINVSEL_SHIFT            (12U)
+#define QuadSPI_SOCCR_DQSINVSEL(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSINVSEL_SHIFT)) & QuadSPI_SOCCR_DQSINVSEL_MASK)
+#define QuadSPI_SOCCR_CK2EN_MASK                 (0x2000U)
+#define QuadSPI_SOCCR_CK2EN_SHIFT                (13U)
+#define QuadSPI_SOCCR_CK2EN(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_CK2EN_SHIFT)) & QuadSPI_SOCCR_CK2EN_MASK)
+#define QuadSPI_SOCCR_DIFFCKEN_MASK              (0x4000U)
+#define QuadSPI_SOCCR_DIFFCKEN_SHIFT             (14U)
+#define QuadSPI_SOCCR_DIFFCKEN(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DIFFCKEN_SHIFT)) & QuadSPI_SOCCR_DIFFCKEN_MASK)
+#define QuadSPI_SOCCR_OCTEN_MASK                 (0x8000U)
+#define QuadSPI_SOCCR_OCTEN_SHIFT                (15U)
+#define QuadSPI_SOCCR_OCTEN(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_OCTEN_SHIFT)) & QuadSPI_SOCCR_OCTEN_MASK)
+#define QuadSPI_SOCCR_DLYTAPSELA_MASK            (0x3F0000U)
+#define QuadSPI_SOCCR_DLYTAPSELA_SHIFT           (16U)
+#define QuadSPI_SOCCR_DLYTAPSELA(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DLYTAPSELA_SHIFT)) & QuadSPI_SOCCR_DLYTAPSELA_MASK)
+#define QuadSPI_SOCCR_DLYTAPSELB_MASK            (0x3F000000U)
+#define QuadSPI_SOCCR_DLYTAPSELB_SHIFT           (24U)
+#define QuadSPI_SOCCR_DLYTAPSELB(x)              (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DLYTAPSELB_SHIFT)) & QuadSPI_SOCCR_DLYTAPSELB_MASK)
+
+/*! @name BUF0IND - Buffer0 Top Index Register */
+#define QuadSPI_BUF0IND_TPINDX0_MASK             (0xFFFFFFF8U)
+#define QuadSPI_BUF0IND_TPINDX0_SHIFT            (3U)
+#define QuadSPI_BUF0IND_TPINDX0(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK)
+
+/*! @name BUF1IND - Buffer1 Top Index Register */
+#define QuadSPI_BUF1IND_TPINDX1_MASK             (0xFFFFFFF8U)
+#define QuadSPI_BUF1IND_TPINDX1_SHIFT            (3U)
+#define QuadSPI_BUF1IND_TPINDX1(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK)
+
+/*! @name BUF2IND - Buffer2 Top Index Register */
+#define QuadSPI_BUF2IND_TPINDX2_MASK             (0xFFFFFFF8U)
+#define QuadSPI_BUF2IND_TPINDX2_SHIFT            (3U)
+#define QuadSPI_BUF2IND_TPINDX2(x)               (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
+
+/*! @name SFAR - Serial Flash Address Register */
+#define QuadSPI_SFAR_SFADR_MASK                  (0xFFFFFFFFU)
+#define QuadSPI_SFAR_SFADR_SHIFT                 (0U)
+#define QuadSPI_SFAR_SFADR(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK)
+
+/*! @name SFACR - Serial Flash Address Configuration Register */
+#define QuadSPI_SFACR_CAS_MASK                   (0xFU)
+#define QuadSPI_SFACR_CAS_SHIFT                  (0U)
+#define QuadSPI_SFACR_CAS(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_CAS_SHIFT)) & QuadSPI_SFACR_CAS_MASK)
+#define QuadSPI_SFACR_WA_MASK                    (0x10000U)
+#define QuadSPI_SFACR_WA_SHIFT                   (16U)
+#define QuadSPI_SFACR_WA(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_WA_SHIFT)) & QuadSPI_SFACR_WA_MASK)
+
+/*! @name SMPR - Sampling Register */
+#define QuadSPI_SMPR_HSENA_MASK                  (0x1U)
+#define QuadSPI_SMPR_HSENA_SHIFT                 (0U)
+#define QuadSPI_SMPR_HSENA(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSENA_SHIFT)) & QuadSPI_SMPR_HSENA_MASK)
+#define QuadSPI_SMPR_HSPHS_MASK                  (0x2U)
+#define QuadSPI_SMPR_HSPHS_SHIFT                 (1U)
+#define QuadSPI_SMPR_HSPHS(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSPHS_SHIFT)) & QuadSPI_SMPR_HSPHS_MASK)
+#define QuadSPI_SMPR_HSDLY_MASK                  (0x4U)
+#define QuadSPI_SMPR_HSDLY_SHIFT                 (2U)
+#define QuadSPI_SMPR_HSDLY(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSDLY_SHIFT)) & QuadSPI_SMPR_HSDLY_MASK)
+#define QuadSPI_SMPR_FSPHS_MASK                  (0x20U)
+#define QuadSPI_SMPR_FSPHS_SHIFT                 (5U)
+#define QuadSPI_SMPR_FSPHS(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSPHS_SHIFT)) & QuadSPI_SMPR_FSPHS_MASK)
+#define QuadSPI_SMPR_FSDLY_MASK                  (0x40U)
+#define QuadSPI_SMPR_FSDLY_SHIFT                 (6U)
+#define QuadSPI_SMPR_FSDLY(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSDLY_SHIFT)) & QuadSPI_SMPR_FSDLY_MASK)
+#define QuadSPI_SMPR_DDRSMP_MASK                 (0x70000U)
+#define QuadSPI_SMPR_DDRSMP_SHIFT                (16U)
+#define QuadSPI_SMPR_DDRSMP(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DDRSMP_SHIFT)) & QuadSPI_SMPR_DDRSMP_MASK)
+
+/*! @name RBSR - RX Buffer Status Register */
+#define QuadSPI_RBSR_RDBFL_MASK                  (0x1F00U)
+#define QuadSPI_RBSR_RDBFL_SHIFT                 (8U)
+#define QuadSPI_RBSR_RDBFL(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK)
+#define QuadSPI_RBSR_RDCTR_MASK                  (0xFFFF0000U)
+#define QuadSPI_RBSR_RDCTR_SHIFT                 (16U)
+#define QuadSPI_RBSR_RDCTR(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK)
+
+/*! @name RBCT - RX Buffer Control Register */
+#define QuadSPI_RBCT_WMRK_MASK                   (0xFU)
+#define QuadSPI_RBCT_WMRK_SHIFT                  (0U)
+#define QuadSPI_RBCT_WMRK(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK)
+#define QuadSPI_RBCT_RXBRD_MASK                  (0x100U)
+#define QuadSPI_RBCT_RXBRD_SHIFT                 (8U)
+#define QuadSPI_RBCT_RXBRD(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK)
+
+/*! @name TBSR - TX Buffer Status Register */
+#define QuadSPI_TBSR_TRBFL_MASK                  (0x1F00U)
+#define QuadSPI_TBSR_TRBFL_SHIFT                 (8U)
+#define QuadSPI_TBSR_TRBFL(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK)
+#define QuadSPI_TBSR_TRCTR_MASK                  (0xFFFF0000U)
+#define QuadSPI_TBSR_TRCTR_SHIFT                 (16U)
+#define QuadSPI_TBSR_TRCTR(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK)
+
+/*! @name TBDR - TX Buffer Data Register */
+#define QuadSPI_TBDR_TXDATA_MASK                 (0xFFFFFFFFU)
+#define QuadSPI_TBDR_TXDATA_SHIFT                (0U)
+#define QuadSPI_TBDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK)
+
+/*! @name TBCT - Tx Buffer Control Register */
+#define QuadSPI_TBCT_WMRK_MASK                   (0xFU)
+#define QuadSPI_TBCT_WMRK_SHIFT                  (0U)
+#define QuadSPI_TBCT_WMRK(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBCT_WMRK_SHIFT)) & QuadSPI_TBCT_WMRK_MASK)
+
+/*! @name SR - Status Register */
+#define QuadSPI_SR_BUSY_MASK                     (0x1U)
+#define QuadSPI_SR_BUSY_SHIFT                    (0U)
+#define QuadSPI_SR_BUSY(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK)
+#define QuadSPI_SR_IP_ACC_MASK                   (0x2U)
+#define QuadSPI_SR_IP_ACC_SHIFT                  (1U)
+#define QuadSPI_SR_IP_ACC(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK)
+#define QuadSPI_SR_AHB_ACC_MASK                  (0x4U)
+#define QuadSPI_SR_AHB_ACC_SHIFT                 (2U)
+#define QuadSPI_SR_AHB_ACC(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK)
+#define QuadSPI_SR_AHBGNT_MASK                   (0x20U)
+#define QuadSPI_SR_AHBGNT_SHIFT                  (5U)
+#define QuadSPI_SR_AHBGNT(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBGNT_SHIFT)) & QuadSPI_SR_AHBGNT_MASK)
+#define QuadSPI_SR_AHBTRN_MASK                   (0x40U)
+#define QuadSPI_SR_AHBTRN_SHIFT                  (6U)
+#define QuadSPI_SR_AHBTRN(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK)
+#define QuadSPI_SR_AHB0NE_MASK                   (0x80U)
+#define QuadSPI_SR_AHB0NE_SHIFT                  (7U)
+#define QuadSPI_SR_AHB0NE(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
+#define QuadSPI_SR_AHB1NE_MASK                   (0x100U)
+#define QuadSPI_SR_AHB1NE_SHIFT                  (8U)
+#define QuadSPI_SR_AHB1NE(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK)
+#define QuadSPI_SR_AHB2NE_MASK                   (0x200U)
+#define QuadSPI_SR_AHB2NE_SHIFT                  (9U)
+#define QuadSPI_SR_AHB2NE(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK)
+#define QuadSPI_SR_AHB3NE_MASK                   (0x400U)
+#define QuadSPI_SR_AHB3NE_SHIFT                  (10U)
+#define QuadSPI_SR_AHB3NE(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK)
+#define QuadSPI_SR_AHB0FUL_MASK                  (0x800U)
+#define QuadSPI_SR_AHB0FUL_SHIFT                 (11U)
+#define QuadSPI_SR_AHB0FUL(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
+#define QuadSPI_SR_AHB1FUL_MASK                  (0x1000U)
+#define QuadSPI_SR_AHB1FUL_SHIFT                 (12U)
+#define QuadSPI_SR_AHB1FUL(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK)
+#define QuadSPI_SR_AHB2FUL_MASK                  (0x2000U)
+#define QuadSPI_SR_AHB2FUL_SHIFT                 (13U)
+#define QuadSPI_SR_AHB2FUL(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK)
+#define QuadSPI_SR_AHB3FUL_MASK                  (0x4000U)
+#define QuadSPI_SR_AHB3FUL_SHIFT                 (14U)
+#define QuadSPI_SR_AHB3FUL(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK)
+#define QuadSPI_SR_RXWE_MASK                     (0x10000U)
+#define QuadSPI_SR_RXWE_SHIFT                    (16U)
+#define QuadSPI_SR_RXWE(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
+#define QuadSPI_SR_RXFULL_MASK                   (0x80000U)
+#define QuadSPI_SR_RXFULL_SHIFT                  (19U)
+#define QuadSPI_SR_RXFULL(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
+#define QuadSPI_SR_RXDMA_MASK                    (0x800000U)
+#define QuadSPI_SR_RXDMA_SHIFT                   (23U)
+#define QuadSPI_SR_RXDMA(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK)
+#define QuadSPI_SR_TXEDA_MASK                    (0x1000000U)
+#define QuadSPI_SR_TXEDA_SHIFT                   (24U)
+#define QuadSPI_SR_TXEDA(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK)
+#define QuadSPI_SR_TXWA_MASK                     (0x2000000U)
+#define QuadSPI_SR_TXWA_SHIFT                    (25U)
+#define QuadSPI_SR_TXWA(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXWA_SHIFT)) & QuadSPI_SR_TXWA_MASK)
+#define QuadSPI_SR_TXDMA_MASK                    (0x4000000U)
+#define QuadSPI_SR_TXDMA_SHIFT                   (26U)
+#define QuadSPI_SR_TXDMA(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXDMA_SHIFT)) & QuadSPI_SR_TXDMA_MASK)
+#define QuadSPI_SR_TXFULL_MASK                   (0x8000000U)
+#define QuadSPI_SR_TXFULL_SHIFT                  (27U)
+#define QuadSPI_SR_TXFULL(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
+#define QuadSPI_SR_DLPSMP_MASK                   (0xE0000000U)
+#define QuadSPI_SR_DLPSMP_SHIFT                  (29U)
+#define QuadSPI_SR_DLPSMP(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
+
+/*! @name FR - Flag Register */
+#define QuadSPI_FR_TFF_MASK                      (0x1U)
+#define QuadSPI_FR_TFF_SHIFT                     (0U)
+#define QuadSPI_FR_TFF(x)                        (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK)
+#define QuadSPI_FR_IPGEF_MASK                    (0x10U)
+#define QuadSPI_FR_IPGEF_SHIFT                   (4U)
+#define QuadSPI_FR_IPGEF(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPGEF_SHIFT)) & QuadSPI_FR_IPGEF_MASK)
+#define QuadSPI_FR_IPIEF_MASK                    (0x40U)
+#define QuadSPI_FR_IPIEF_SHIFT                   (6U)
+#define QuadSPI_FR_IPIEF(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK)
+#define QuadSPI_FR_IPAEF_MASK                    (0x80U)
+#define QuadSPI_FR_IPAEF_SHIFT                   (7U)
+#define QuadSPI_FR_IPAEF(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK)
+#define QuadSPI_FR_IUEF_MASK                     (0x800U)
+#define QuadSPI_FR_IUEF_SHIFT                    (11U)
+#define QuadSPI_FR_IUEF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IUEF_SHIFT)) & QuadSPI_FR_IUEF_MASK)
+#define QuadSPI_FR_ABOF_MASK                     (0x1000U)
+#define QuadSPI_FR_ABOF_SHIFT                    (12U)
+#define QuadSPI_FR_ABOF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK)
+#define QuadSPI_FR_AIBSEF_MASK                   (0x2000U)
+#define QuadSPI_FR_AIBSEF_SHIFT                  (13U)
+#define QuadSPI_FR_AIBSEF(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK)
+#define QuadSPI_FR_AITEF_MASK                    (0x4000U)
+#define QuadSPI_FR_AITEF_SHIFT                   (14U)
+#define QuadSPI_FR_AITEF(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AITEF_SHIFT)) & QuadSPI_FR_AITEF_MASK)
+#define QuadSPI_FR_ABSEF_MASK                    (0x8000U)
+#define QuadSPI_FR_ABSEF_SHIFT                   (15U)
+#define QuadSPI_FR_ABSEF(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
+#define QuadSPI_FR_RBDF_MASK                     (0x10000U)
+#define QuadSPI_FR_RBDF_SHIFT                    (16U)
+#define QuadSPI_FR_RBDF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK)
+#define QuadSPI_FR_RBOF_MASK                     (0x20000U)
+#define QuadSPI_FR_RBOF_SHIFT                    (17U)
+#define QuadSPI_FR_RBOF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK)
+#define QuadSPI_FR_ILLINE_MASK                   (0x800000U)
+#define QuadSPI_FR_ILLINE_SHIFT                  (23U)
+#define QuadSPI_FR_ILLINE(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
+#define QuadSPI_FR_TBUF_MASK                     (0x4000000U)
+#define QuadSPI_FR_TBUF_SHIFT                    (26U)
+#define QuadSPI_FR_TBUF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK)
+#define QuadSPI_FR_TBFF_MASK                     (0x8000000U)
+#define QuadSPI_FR_TBFF_SHIFT                    (27U)
+#define QuadSPI_FR_TBFF(x)                       (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK)
+#define QuadSPI_FR_DLPFF_MASK                    (0x80000000U)
+#define QuadSPI_FR_DLPFF_SHIFT                   (31U)
+#define QuadSPI_FR_DLPFF(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK)
+
+/*! @name RSER - Interrupt and DMA Request Select and Enable Register */
+#define QuadSPI_RSER_TFIE_MASK                   (0x1U)
+#define QuadSPI_RSER_TFIE_SHIFT                  (0U)
+#define QuadSPI_RSER_TFIE(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK)
+#define QuadSPI_RSER_IPGEIE_MASK                 (0x10U)
+#define QuadSPI_RSER_IPGEIE_SHIFT                (4U)
+#define QuadSPI_RSER_IPGEIE(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPGEIE_SHIFT)) & QuadSPI_RSER_IPGEIE_MASK)
+#define QuadSPI_RSER_IPIEIE_MASK                 (0x40U)
+#define QuadSPI_RSER_IPIEIE_SHIFT                (6U)
+#define QuadSPI_RSER_IPIEIE(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK)
+#define QuadSPI_RSER_IPAEIE_MASK                 (0x80U)
+#define QuadSPI_RSER_IPAEIE_SHIFT                (7U)
+#define QuadSPI_RSER_IPAEIE(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK)
+#define QuadSPI_RSER_IUEIE_MASK                  (0x800U)
+#define QuadSPI_RSER_IUEIE_SHIFT                 (11U)
+#define QuadSPI_RSER_IUEIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IUEIE_SHIFT)) & QuadSPI_RSER_IUEIE_MASK)
+#define QuadSPI_RSER_ABOIE_MASK                  (0x1000U)
+#define QuadSPI_RSER_ABOIE_SHIFT                 (12U)
+#define QuadSPI_RSER_ABOIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK)
+#define QuadSPI_RSER_AIBSIE_MASK                 (0x2000U)
+#define QuadSPI_RSER_AIBSIE_SHIFT                (13U)
+#define QuadSPI_RSER_AIBSIE(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AIBSIE_SHIFT)) & QuadSPI_RSER_AIBSIE_MASK)
+#define QuadSPI_RSER_AITIE_MASK                  (0x4000U)
+#define QuadSPI_RSER_AITIE_SHIFT                 (14U)
+#define QuadSPI_RSER_AITIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AITIE_SHIFT)) & QuadSPI_RSER_AITIE_MASK)
+#define QuadSPI_RSER_ABSEIE_MASK                 (0x8000U)
+#define QuadSPI_RSER_ABSEIE_SHIFT                (15U)
+#define QuadSPI_RSER_ABSEIE(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK)
+#define QuadSPI_RSER_RBDIE_MASK                  (0x10000U)
+#define QuadSPI_RSER_RBDIE_SHIFT                 (16U)
+#define QuadSPI_RSER_RBDIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK)
+#define QuadSPI_RSER_RBOIE_MASK                  (0x20000U)
+#define QuadSPI_RSER_RBOIE_SHIFT                 (17U)
+#define QuadSPI_RSER_RBOIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK)
+#define QuadSPI_RSER_RBDDE_MASK                  (0x200000U)
+#define QuadSPI_RSER_RBDDE_SHIFT                 (21U)
+#define QuadSPI_RSER_RBDDE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK)
+#define QuadSPI_RSER_ILLINIE_MASK                (0x800000U)
+#define QuadSPI_RSER_ILLINIE_SHIFT               (23U)
+#define QuadSPI_RSER_ILLINIE(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK)
+#define QuadSPI_RSER_TBFDE_MASK                  (0x2000000U)
+#define QuadSPI_RSER_TBFDE_SHIFT                 (25U)
+#define QuadSPI_RSER_TBFDE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFDE_SHIFT)) & QuadSPI_RSER_TBFDE_MASK)
+#define QuadSPI_RSER_TBUIE_MASK                  (0x4000000U)
+#define QuadSPI_RSER_TBUIE_SHIFT                 (26U)
+#define QuadSPI_RSER_TBUIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK)
+#define QuadSPI_RSER_TBFIE_MASK                  (0x8000000U)
+#define QuadSPI_RSER_TBFIE_SHIFT                 (27U)
+#define QuadSPI_RSER_TBFIE(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK)
+#define QuadSPI_RSER_DLPFIE_MASK                 (0x80000000U)
+#define QuadSPI_RSER_DLPFIE_SHIFT                (31U)
+#define QuadSPI_RSER_DLPFIE(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK)
+
+/*! @name SPNDST - Sequence Suspend Status Register */
+#define QuadSPI_SPNDST_SUSPND_MASK               (0x1U)
+#define QuadSPI_SPNDST_SUSPND_SHIFT              (0U)
+#define QuadSPI_SPNDST_SUSPND(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK)
+#define QuadSPI_SPNDST_SPDBUF_MASK               (0xC0U)
+#define QuadSPI_SPNDST_SPDBUF_SHIFT              (6U)
+#define QuadSPI_SPNDST_SPDBUF(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK)
+#define QuadSPI_SPNDST_DATLFT_MASK               (0x7E00U)
+#define QuadSPI_SPNDST_DATLFT_SHIFT              (9U)
+#define QuadSPI_SPNDST_DATLFT(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK)
+
+/*! @name SPTRCLR - Sequence Pointer Clear Register */
+#define QuadSPI_SPTRCLR_BFPTRC_MASK              (0x1U)
+#define QuadSPI_SPTRCLR_BFPTRC_SHIFT             (0U)
+#define QuadSPI_SPTRCLR_BFPTRC(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK)
+#define QuadSPI_SPTRCLR_IPPTRC_MASK              (0x100U)
+#define QuadSPI_SPTRCLR_IPPTRC_SHIFT             (8U)
+#define QuadSPI_SPTRCLR_IPPTRC(x)                (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK)
+
+/*! @name SFA1AD - Serial Flash A1 Top Address */
+#define QuadSPI_SFA1AD_TPADA1_MASK               (0xFFFFFC00U)
+#define QuadSPI_SFA1AD_TPADA1_SHIFT              (10U)
+#define QuadSPI_SFA1AD_TPADA1(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK)
+
+/*! @name SFA2AD - Serial Flash A2 Top Address */
+#define QuadSPI_SFA2AD_TPADA2_MASK               (0xFFFFFC00U)
+#define QuadSPI_SFA2AD_TPADA2_SHIFT              (10U)
+#define QuadSPI_SFA2AD_TPADA2(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK)
+
+/*! @name SFB1AD - Serial Flash B1Top Address */
+#define QuadSPI_SFB1AD_TPADB1_MASK               (0xFFFFFC00U)
+#define QuadSPI_SFB1AD_TPADB1_SHIFT              (10U)
+#define QuadSPI_SFB1AD_TPADB1(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK)
+
+/*! @name SFB2AD - Serial Flash B2Top Address */
+#define QuadSPI_SFB2AD_TPADB2_MASK               (0xFFFFFC00U)
+#define QuadSPI_SFB2AD_TPADB2_SHIFT              (10U)
+#define QuadSPI_SFB2AD_TPADB2(x)                 (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK)
+
+/*! @name DLPR - Data Learn Pattern Register */
+#define QuadSPI_DLPR_DLPV_MASK                   (0xFFFFFFFFU)
+#define QuadSPI_DLPR_DLPV_SHIFT                  (0U)
+#define QuadSPI_DLPR_DLPV(x)                     (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLPR_DLPV_SHIFT)) & QuadSPI_DLPR_DLPV_MASK)
+
+/*! @name RBDR - RX Buffer Data Register */
+#define QuadSPI_RBDR_RXDATA_MASK                 (0xFFFFFFFFU)
+#define QuadSPI_RBDR_RXDATA_SHIFT                (0U)
+#define QuadSPI_RBDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK)
+
+/* The count of QuadSPI_RBDR */
+#define QuadSPI_RBDR_COUNT                       (16U)
+
+/*! @name LUTKEY - LUT Key Register */
+#define QuadSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
+#define QuadSPI_LUTKEY_KEY_SHIFT                 (0U)
+#define QuadSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK)
+
+/*! @name LCKCR - LUT Lock Configuration Register */
+#define QuadSPI_LCKCR_LOCK_MASK                  (0x1U)
+#define QuadSPI_LCKCR_LOCK_SHIFT                 (0U)
+#define QuadSPI_LCKCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
+#define QuadSPI_LCKCR_UNLOCK_MASK                (0x2U)
+#define QuadSPI_LCKCR_UNLOCK_SHIFT               (1U)
+#define QuadSPI_LCKCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK)
+
+/*! @name LUT - Look-up Table register */
+#define QuadSPI_LUT_OPRND0_MASK                  (0xFFU)
+#define QuadSPI_LUT_OPRND0_SHIFT                 (0U)
+#define QuadSPI_LUT_OPRND0(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK)
+#define QuadSPI_LUT_PAD0_MASK                    (0x300U)
+#define QuadSPI_LUT_PAD0_SHIFT                   (8U)
+#define QuadSPI_LUT_PAD0(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK)
+#define QuadSPI_LUT_INSTR0_MASK                  (0xFC00U)
+#define QuadSPI_LUT_INSTR0_SHIFT                 (10U)
+#define QuadSPI_LUT_INSTR0(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK)
+#define QuadSPI_LUT_OPRND1_MASK                  (0xFF0000U)
+#define QuadSPI_LUT_OPRND1_SHIFT                 (16U)
+#define QuadSPI_LUT_OPRND1(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK)
+#define QuadSPI_LUT_PAD1_MASK                    (0x3000000U)
+#define QuadSPI_LUT_PAD1_SHIFT                   (24U)
+#define QuadSPI_LUT_PAD1(x)                      (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK)
+#define QuadSPI_LUT_INSTR1_MASK                  (0xFC000000U)
+#define QuadSPI_LUT_INSTR1_SHIFT                 (26U)
+#define QuadSPI_LUT_INSTR1(x)                    (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK)
+
+/* The count of QuadSPI_LUT */
+#define QuadSPI_LUT_COUNT                        (64U)
+
+
+/*!
+ * @}
+ */ /* end of group QuadSPI_Register_Masks */
+
+
+/* QuadSPI - Peripheral instance base addresses */
+/** Peripheral QuadSPI0 base address */
+#define QuadSPI0_BASE                            (0x4005A000u)
+/** Peripheral QuadSPI0 base pointer */
+#define QuadSPI0                                 ((QuadSPI_Type *)QuadSPI0_BASE)
+/** Array initializer of QuadSPI peripheral base addresses */
+#define QuadSPI_BASE_ADDRS                       { QuadSPI0_BASE }
+/** Array initializer of QuadSPI peripheral base pointers */
+#define QuadSPI_BASE_PTRS                        { QuadSPI0 }
+/** Interrupt vectors for the QuadSPI peripheral type */
+#define QuadSPI_IRQS                             { QSPI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group QuadSPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
+  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
+  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
+  __IO uint8_t FM;                                 /**< Force Mode Register, offset: 0x6 */
+  __IO uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
+  __IO uint8_t SSRS0;                              /**< Sticky System Reset Status Register 0, offset: 0x8 */
+  __IO uint8_t SSRS1;                              /**< Sticky System Reset Status Register 1, offset: 0x9 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/*! @name SRS0 - System Reset Status Register 0 */
+#define RCM_SRS0_WAKEUP_MASK                     (0x1U)
+#define RCM_SRS0_WAKEUP_SHIFT                    (0U)
+#define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK                        (0x2U)
+#define RCM_SRS0_LVD_SHIFT                       (1U)
+#define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK                        (0x4U)
+#define RCM_SRS0_LOC_SHIFT                       (2U)
+#define RCM_SRS0_LOC(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK                        (0x8U)
+#define RCM_SRS0_LOL_SHIFT                       (3U)
+#define RCM_SRS0_LOL(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK                       (0x20U)
+#define RCM_SRS0_WDOG_SHIFT                      (5U)
+#define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK                        (0x40U)
+#define RCM_SRS0_PIN_SHIFT                       (6U)
+#define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK                        (0x80U)
+#define RCM_SRS0_POR_SHIFT                       (7U)
+#define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
+
+/*! @name SRS1 - System Reset Status Register 1 */
+#define RCM_SRS1_LOCKUP_MASK                     (0x2U)
+#define RCM_SRS1_LOCKUP_SHIFT                    (1U)
+#define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK                         (0x4U)
+#define RCM_SRS1_SW_SHIFT                        (2U)
+#define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK                     (0x8U)
+#define RCM_SRS1_MDM_AP_SHIFT                    (3U)
+#define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_SACKERR_MASK                    (0x20U)
+#define RCM_SRS1_SACKERR_SHIFT                   (5U)
+#define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
+
+/*! @name RPFC - Reset Pin Filter Control register */
+#define RCM_RPFC_RSTFLTSRW_MASK                  (0x3U)
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 (0U)
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK                   (0x4U)
+#define RCM_RPFC_RSTFLTSS_SHIFT                  (2U)
+#define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
+
+/*! @name RPFW - Reset Pin Filter Width register */
+#define RCM_RPFW_RSTFLTSEL_MASK                  (0x1FU)
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 (0U)
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+
+/*! @name FM - Force Mode Register */
+#define RCM_FM_FORCEROM_MASK                     (0x6U)
+#define RCM_FM_FORCEROM_SHIFT                    (1U)
+#define RCM_FM_FORCEROM(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK)
+
+/*! @name MR - Mode Register */
+#define RCM_MR_BOOTROM_MASK                      (0x6U)
+#define RCM_MR_BOOTROM_SHIFT                     (1U)
+#define RCM_MR_BOOTROM(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK)
+
+/*! @name SSRS0 - Sticky System Reset Status Register 0 */
+#define RCM_SSRS0_SWAKEUP_MASK                   (0x1U)
+#define RCM_SSRS0_SWAKEUP_SHIFT                  (0U)
+#define RCM_SSRS0_SWAKEUP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
+#define RCM_SSRS0_SLVD_MASK                      (0x2U)
+#define RCM_SSRS0_SLVD_SHIFT                     (1U)
+#define RCM_SSRS0_SLVD(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
+#define RCM_SSRS0_SLOC_MASK                      (0x4U)
+#define RCM_SSRS0_SLOC_SHIFT                     (2U)
+#define RCM_SSRS0_SLOC(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
+#define RCM_SSRS0_SLOL_MASK                      (0x8U)
+#define RCM_SSRS0_SLOL_SHIFT                     (3U)
+#define RCM_SSRS0_SLOL(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
+#define RCM_SSRS0_SWDOG_MASK                     (0x20U)
+#define RCM_SSRS0_SWDOG_SHIFT                    (5U)
+#define RCM_SSRS0_SWDOG(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
+#define RCM_SSRS0_SPIN_MASK                      (0x40U)
+#define RCM_SSRS0_SPIN_SHIFT                     (6U)
+#define RCM_SSRS0_SPIN(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
+#define RCM_SSRS0_SPOR_MASK                      (0x80U)
+#define RCM_SSRS0_SPOR_SHIFT                     (7U)
+#define RCM_SSRS0_SPOR(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
+
+/*! @name SSRS1 - Sticky System Reset Status Register 1 */
+#define RCM_SSRS1_SLOCKUP_MASK                   (0x2U)
+#define RCM_SSRS1_SLOCKUP_SHIFT                  (1U)
+#define RCM_SSRS1_SLOCKUP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
+#define RCM_SSRS1_SSW_MASK                       (0x4U)
+#define RCM_SSRS1_SSW_SHIFT                      (2U)
+#define RCM_SSRS1_SSW(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
+#define RCM_SSRS1_SMDM_AP_MASK                   (0x8U)
+#define RCM_SSRS1_SMDM_AP_SHIFT                  (3U)
+#define RCM_SSRS1_SMDM_AP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
+#define RCM_SSRS1_SSACKERR_MASK                  (0x20U)
+#define RCM_SSRS1_SSACKERR_SHIFT                 (5U)
+#define RCM_SSRS1_SSACKERR(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE                                 (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM                                      ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS                           { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS                            { RCM }
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/*! @name REG - Register file register */
+#define RFSYS_REG_LL_MASK                        (0xFFU)
+#define RFSYS_REG_LL_SHIFT                       (0U)
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK                        (0xFF00U)
+#define RFSYS_REG_LH_SHIFT                       (8U)
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK                        (0xFF0000U)
+#define RFSYS_REG_HL_SHIFT                       (16U)
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK                        (0xFF000000U)
+#define RFSYS_REG_HH_SHIFT                       (24U)
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
+
+/* The count of RFSYS_REG */
+#define RFSYS_REG_COUNT                          (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE                               (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS                          { RFSYS }
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/*! @name REG - VBAT register file register */
+#define RFVBAT_REG_LL_MASK                       (0xFFU)
+#define RFVBAT_REG_LL_SHIFT                      (0U)
+#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK                       (0xFF00U)
+#define RFVBAT_REG_LH_SHIFT                      (8U)
+#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK                       (0xFF0000U)
+#define RFVBAT_REG_HL_SHIFT                      (16U)
+#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK                       (0xFF000000U)
+#define RFVBAT_REG_HH_SHIFT                      (24U)
+#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
+
+/* The count of RFVBAT_REG */
+#define RFVBAT_REG_COUNT                         (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE                              (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT                                   ((RFVBAT_Type *)RFVBAT_BASE)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS                        { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS                         { RFVBAT }
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ROM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t ENTRY[3];                          /**< Entry, array offset: 0x0, array step: 0x4 */
+  __I  uint32_t TABLEMARK;                         /**< End of Table Marker Register, offset: 0xC */
+       uint8_t RESERVED_0[4028];
+  __I  uint32_t SYSACCESS;                         /**< System Access Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
+  __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
+  __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
+  __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
+  __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
+  __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
+  __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
+  __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ROM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/*! @name ENTRY - Entry */
+#define ROM_ENTRY_ENTRY_MASK                     (0xFFFFFFFFU)
+#define ROM_ENTRY_ENTRY_SHIFT                    (0U)
+#define ROM_ENTRY_ENTRY(x)                       (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK)
+
+/* The count of ROM_ENTRY */
+#define ROM_ENTRY_COUNT                          (3U)
+
+/*! @name TABLEMARK - End of Table Marker Register */
+#define ROM_TABLEMARK_MARK_MASK                  (0xFFFFFFFFU)
+#define ROM_TABLEMARK_MARK_SHIFT                 (0U)
+#define ROM_TABLEMARK_MARK(x)                    (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK)
+
+/*! @name SYSACCESS - System Access Register */
+#define ROM_SYSACCESS_SYSACCESS_MASK             (0xFFFFFFFFU)
+#define ROM_SYSACCESS_SYSACCESS_SHIFT            (0U)
+#define ROM_SYSACCESS_SYSACCESS(x)               (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK)
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+#define ROM_PERIPHID4_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID4_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID4_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK)
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+#define ROM_PERIPHID5_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID5_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID5_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK)
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+#define ROM_PERIPHID6_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID6_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID6_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK)
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+#define ROM_PERIPHID7_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID7_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID7_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK)
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+#define ROM_PERIPHID0_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID0_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID0_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK)
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+#define ROM_PERIPHID1_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID1_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID1_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK)
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+#define ROM_PERIPHID2_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID2_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID2_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK)
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+#define ROM_PERIPHID3_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID3_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID3_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK)
+
+/*! @name COMPID - Component ID Register */
+#define ROM_COMPID_COMPID_MASK                   (0xFFFFFFFFU)
+#define ROM_COMPID_COMPID_SHIFT                  (0U)
+#define ROM_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK)
+
+/* The count of ROM_COMPID */
+#define ROM_COMPID_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE                                 (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM                                      ((ROM_Type *)ROM_BASE)
+/** Array initializer of ROM peripheral base addresses */
+#define ROM_BASE_ADDRS                           { ROM_BASE }
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASE_PTRS                            { ROM }
+
+/*!
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+       uint8_t RESERVED_0[2016];
+  __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
+  __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name TSR - RTC Time Seconds Register */
+#define RTC_TSR_TSR_MASK                         (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT                        (0U)
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+
+/*! @name TPR - RTC Time Prescaler Register */
+#define RTC_TPR_TPR_MASK                         (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT                        (0U)
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+
+/*! @name TAR - RTC Time Alarm Register */
+#define RTC_TAR_TAR_MASK                         (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT                        (0U)
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+
+/*! @name TCR - RTC Time Compensation Register */
+#define RTC_TCR_TCR_MASK                         (0xFFU)
+#define RTC_TCR_TCR_SHIFT                        (0U)
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         (0xFF00U)
+#define RTC_TCR_CIR_SHIFT                        (8U)
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT                        (16U)
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT                        (24U)
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+
+/*! @name CR - RTC Control Register */
+#define RTC_CR_SWR_MASK                          (0x1U)
+#define RTC_CR_SWR_SHIFT                         (0U)
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK                          (0x2U)
+#define RTC_CR_WPE_SHIFT                         (1U)
+#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK                          (0x4U)
+#define RTC_CR_SUP_SHIFT                         (2U)
+#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK                           (0x8U)
+#define RTC_CR_UM_SHIFT                          (3U)
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK                          (0x10U)
+#define RTC_CR_WPS_SHIFT                         (4U)
+#define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK                         (0x100U)
+#define RTC_CR_OSCE_SHIFT                        (8U)
+#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK                         (0x200U)
+#define RTC_CR_CLKO_SHIFT                        (9U)
+#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK                        (0x400U)
+#define RTC_CR_SC16P_SHIFT                       (10U)
+#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK                         (0x800U)
+#define RTC_CR_SC8P_SHIFT                        (11U)
+#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK                         (0x1000U)
+#define RTC_CR_SC4P_SHIFT                        (12U)
+#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK                         (0x2000U)
+#define RTC_CR_SC2P_SHIFT                        (13U)
+#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+
+/*! @name SR - RTC Status Register */
+#define RTC_SR_TIF_MASK                          (0x1U)
+#define RTC_SR_TIF_SHIFT                         (0U)
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK                          (0x2U)
+#define RTC_SR_TOF_SHIFT                         (1U)
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK                          (0x4U)
+#define RTC_SR_TAF_SHIFT                         (2U)
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK                          (0x10U)
+#define RTC_SR_TCE_SHIFT                         (4U)
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+
+/*! @name LR - RTC Lock Register */
+#define RTC_LR_TCL_MASK                          (0x8U)
+#define RTC_LR_TCL_SHIFT                         (3U)
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK                          (0x10U)
+#define RTC_LR_CRL_SHIFT                         (4U)
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK                          (0x20U)
+#define RTC_LR_SRL_SHIFT                         (5U)
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK                          (0x40U)
+#define RTC_LR_LRL_SHIFT                         (6U)
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+
+/*! @name IER - RTC Interrupt Enable Register */
+#define RTC_IER_TIIE_MASK                        (0x1U)
+#define RTC_IER_TIIE_SHIFT                       (0U)
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK                        (0x2U)
+#define RTC_IER_TOIE_SHIFT                       (1U)
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK                        (0x4U)
+#define RTC_IER_TAIE_SHIFT                       (2U)
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK                        (0x10U)
+#define RTC_IER_TSIE_SHIFT                       (4U)
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK                        (0x80U)
+#define RTC_IER_WPON_SHIFT                       (7U)
+#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+
+/*! @name WAR - RTC Write Access Register */
+#define RTC_WAR_TSRW_MASK                        (0x1U)
+#define RTC_WAR_TSRW_SHIFT                       (0U)
+#define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK                        (0x2U)
+#define RTC_WAR_TPRW_SHIFT                       (1U)
+#define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK                        (0x4U)
+#define RTC_WAR_TARW_SHIFT                       (2U)
+#define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK                        (0x8U)
+#define RTC_WAR_TCRW_SHIFT                       (3U)
+#define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK                         (0x10U)
+#define RTC_WAR_CRW_SHIFT                        (4U)
+#define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK                         (0x20U)
+#define RTC_WAR_SRW_SHIFT                        (5U)
+#define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK                         (0x40U)
+#define RTC_WAR_LRW_SHIFT                        (6U)
+#define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK                        (0x80U)
+#define RTC_WAR_IERW_SHIFT                       (7U)
+#define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
+
+/*! @name RAR - RTC Read Access Register */
+#define RTC_RAR_TSRR_MASK                        (0x1U)
+#define RTC_RAR_TSRR_SHIFT                       (0U)
+#define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK                        (0x2U)
+#define RTC_RAR_TPRR_SHIFT                       (1U)
+#define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK                        (0x4U)
+#define RTC_RAR_TARR_SHIFT                       (2U)
+#define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK                        (0x8U)
+#define RTC_RAR_TCRR_SHIFT                       (3U)
+#define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK                         (0x10U)
+#define RTC_RAR_CRR_SHIFT                        (4U)
+#define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK                         (0x20U)
+#define RTC_RAR_SRR_SHIFT                        (5U)
+#define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK                         (0x40U)
+#define RTC_RAR_LRR_SHIFT                        (6U)
+#define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK                        (0x80U)
+#define RTC_RAR_IERR_SHIFT                       (7U)
+#define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_Alarm_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
+       uint8_t RESERVED_0[4096];
+  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t SOPT9;                             /**< System Options Register 9, offset: 0x1020 */
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
+       uint8_t RESERVED_4[12];
+  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
+  __IO uint32_t CLKDIV2;                           /**< System Clock Divider Register 2, offset: 0x1048 */
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
+  __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x1054 */
+  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
+  __IO uint32_t CLKDIV3;                           /**< System Clock Divider Register 3, offset: 0x1064 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t MISCCTRL;                          /**< Misc Control Register, offset: 0x106C */
+       uint8_t RESERVED_6[32];
+  __I  uint32_t SECKEY0;                           /**< Secure Key Register 0, offset: 0x1090 */
+  __I  uint32_t SECKEY1;                           /**< Secure Key Register 1, offset: 0x1094 */
+  __I  uint32_t SECKEY2;                           /**< Secure Key Register 2, offset: 0x1098 */
+  __I  uint32_t SECKEY3;                           /**< Secure Key Register 3, offset: 0x109C */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/*! @name SOPT1 - System Options Register 1 */
+#define SIM_SOPT1_RAMSIZE_MASK                   (0xF000U)
+#define SIM_SOPT1_RAMSIZE_SHIFT                  (12U)
+#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK                 (0xC0000U)
+#define SIM_SOPT1_OSC32KSEL_SHIFT                (18U)
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+
+/*! @name SOPT2 - System Options Register 2 */
+#define SIM_SOPT2_RTCCLKOUTS_MASK                (0x10U)
+#define SIM_SOPT2_RTCCLKOUTS_SHIFT               (4U)
+#define SIM_SOPT2_RTCCLKOUTS(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTS_SHIFT)) & SIM_SOPT2_RTCCLKOUTS_MASK)
+#define SIM_SOPT2_CLKOUT_MASK                    (0xE0U)
+#define SIM_SOPT2_CLKOUT_SHIFT                   (5U)
+#define SIM_SOPT2_CLKOUT(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUT_SHIFT)) & SIM_SOPT2_CLKOUT_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK                 (0x30000U)
+#define SIM_SOPT2_PLLFLLSEL_SHIFT                (16U)
+#define SIM_SOPT2_PLLFLLSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK                    (0x40000U)
+#define SIM_SOPT2_USBSRC_SHIFT                   (18U)
+#define SIM_SOPT2_USBSRC(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_FLEXIOSRC_MASK                 (0xC00000U)
+#define SIM_SOPT2_FLEXIOSRC_SHIFT                (22U)
+#define SIM_SOPT2_FLEXIOSRC(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FLEXIOSRC_SHIFT)) & SIM_SOPT2_FLEXIOSRC_MASK)
+#define SIM_SOPT2_TPMSRC_MASK                    (0x3000000U)
+#define SIM_SOPT2_TPMSRC_SHIFT                   (24U)
+#define SIM_SOPT2_TPMSRC(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_LPUARTSRC_MASK                 (0xC000000U)
+#define SIM_SOPT2_LPUARTSRC_SHIFT                (26U)
+#define SIM_SOPT2_LPUARTSRC(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
+#define SIM_SOPT2_EMVSIMSRC_MASK                 (0xC0000000U)
+#define SIM_SOPT2_EMVSIMSRC_SHIFT                (30U)
+#define SIM_SOPT2_EMVSIMSRC(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_EMVSIMSRC_SHIFT)) & SIM_SOPT2_EMVSIMSRC_MASK)
+
+/*! @name SOPT5 - System Options Register 5 */
+#define SIM_SOPT5_LPUART0TXSRC_MASK              (0x30000U)
+#define SIM_SOPT5_LPUART0TXSRC_SHIFT             (16U)
+#define SIM_SOPT5_LPUART0TXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
+#define SIM_SOPT5_LPUART0RXSRC_MASK              (0xC0000U)
+#define SIM_SOPT5_LPUART0RXSRC_SHIFT             (18U)
+#define SIM_SOPT5_LPUART0RXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
+#define SIM_SOPT5_LPUART1TXSRC_MASK              (0x300000U)
+#define SIM_SOPT5_LPUART1TXSRC_SHIFT             (20U)
+#define SIM_SOPT5_LPUART1TXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1TXSRC_SHIFT)) & SIM_SOPT5_LPUART1TXSRC_MASK)
+#define SIM_SOPT5_LPUART1RXSRC_MASK              (0xC00000U)
+#define SIM_SOPT5_LPUART1RXSRC_SHIFT             (22U)
+#define SIM_SOPT5_LPUART1RXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1RXSRC_SHIFT)) & SIM_SOPT5_LPUART1RXSRC_MASK)
+
+/*! @name SOPT7 - System Options Register 7 */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                (0xFU)
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               (0U)
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             (0x10U)
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            (4U)
+#define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
+
+/*! @name SOPT9 - System Options Register 9 */
+#define SIM_SOPT9_TPM1CH0SRC_MASK                (0xC0000U)
+#define SIM_SOPT9_TPM1CH0SRC_SHIFT               (18U)
+#define SIM_SOPT9_TPM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)
+#define SIM_SOPT9_TPM2CH0SRC_MASK                (0x300000U)
+#define SIM_SOPT9_TPM2CH0SRC_SHIFT               (20U)
+#define SIM_SOPT9_TPM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)
+#define SIM_SOPT9_TPM0CLKSEL_MASK                (0x1000000U)
+#define SIM_SOPT9_TPM0CLKSEL_SHIFT               (24U)
+#define SIM_SOPT9_TPM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM0CLKSEL_SHIFT)) & SIM_SOPT9_TPM0CLKSEL_MASK)
+#define SIM_SOPT9_TPM1CLKSEL_MASK                (0x2000000U)
+#define SIM_SOPT9_TPM1CLKSEL_SHIFT               (25U)
+#define SIM_SOPT9_TPM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)
+#define SIM_SOPT9_TPM2CLKSEL_MASK                (0x4000000U)
+#define SIM_SOPT9_TPM2CLKSEL_SHIFT               (26U)
+#define SIM_SOPT9_TPM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)
+
+/*! @name SDID - System Device Identification Register */
+#define SIM_SDID_PINID_MASK                      (0xFU)
+#define SIM_SDID_PINID_SHIFT                     (0U)
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK                      (0x70U)
+#define SIM_SDID_FAMID_SHIFT                     (4U)
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK                      (0xF80U)
+#define SIM_SDID_DIEID_SHIFT                     (7U)
+#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK                      (0xF000U)
+#define SIM_SDID_REVID_SHIFT                     (12U)
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   (0xF000000U)
+#define SIM_SDID_SUBFAMID_SHIFT                  (24U)
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK                   (0xF0000000U)
+#define SIM_SDID_FAMILYID_SHIFT                  (28U)
+#define SIM_SDID_FAMILYID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
+
+/*! @name SCGC4 - System Clock Gating Control Register 4 */
+#define SIM_SCGC4_EWM_MASK                       (0x2U)
+#define SIM_SCGC4_EWM_SHIFT                      (1U)
+#define SIM_SCGC4_EWM(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_I2C0_MASK                      (0x40U)
+#define SIM_SCGC4_I2C0_SHIFT                     (6U)
+#define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK                      (0x80U)
+#define SIM_SCGC4_I2C1_SHIFT                     (7U)
+#define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_USBOTG_MASK                    (0x40000U)
+#define SIM_SCGC4_USBOTG_SHIFT                   (18U)
+#define SIM_SCGC4_USBOTG(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK                       (0x80000U)
+#define SIM_SCGC4_CMP_SHIFT                      (19U)
+#define SIM_SCGC4_CMP(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK                      (0x100000U)
+#define SIM_SCGC4_VREF_SHIFT                     (20U)
+#define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
+
+/*! @name SCGC5 - System Clock Gating Control Register 5 */
+#define SIM_SCGC5_LPTMR0_MASK                    (0x1U)
+#define SIM_SCGC5_LPTMR0_SHIFT                   (0U)
+#define SIM_SCGC5_LPTMR0(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR0_SHIFT)) & SIM_SCGC5_LPTMR0_MASK)
+#define SIM_SCGC5_SECREG_MASK                    (0x8U)
+#define SIM_SCGC5_SECREG_SHIFT                   (3U)
+#define SIM_SCGC5_SECREG(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_SECREG_SHIFT)) & SIM_SCGC5_SECREG_MASK)
+#define SIM_SCGC5_LPTMR1_MASK                    (0x10U)
+#define SIM_SCGC5_LPTMR1_SHIFT                   (4U)
+#define SIM_SCGC5_LPTMR1(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR1_SHIFT)) & SIM_SCGC5_LPTMR1_MASK)
+#define SIM_SCGC5_TSI_MASK                       (0x20U)
+#define SIM_SCGC5_TSI_SHIFT                      (5U)
+#define SIM_SCGC5_TSI(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
+#define SIM_SCGC5_PTA_MASK                       (0x200U)
+#define SIM_SCGC5_PTA_SHIFT                      (9U)
+#define SIM_SCGC5_PTA(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PTA_SHIFT)) & SIM_SCGC5_PTA_MASK)
+#define SIM_SCGC5_PTB_MASK                       (0x400U)
+#define SIM_SCGC5_PTB_SHIFT                      (10U)
+#define SIM_SCGC5_PTB(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PTB_SHIFT)) & SIM_SCGC5_PTB_MASK)
+#define SIM_SCGC5_PTC_MASK                       (0x800U)
+#define SIM_SCGC5_PTC_SHIFT                      (11U)
+#define SIM_SCGC5_PTC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PTC_SHIFT)) & SIM_SCGC5_PTC_MASK)
+#define SIM_SCGC5_PTD_MASK                       (0x1000U)
+#define SIM_SCGC5_PTD_SHIFT                      (12U)
+#define SIM_SCGC5_PTD(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PTD_SHIFT)) & SIM_SCGC5_PTD_MASK)
+#define SIM_SCGC5_PTE_MASK                       (0x2000U)
+#define SIM_SCGC5_PTE_SHIFT                      (13U)
+#define SIM_SCGC5_PTE(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PTE_SHIFT)) & SIM_SCGC5_PTE_MASK)
+#define SIM_SCGC5_EMVSIM0_MASK                   (0x4000U)
+#define SIM_SCGC5_EMVSIM0_SHIFT                  (14U)
+#define SIM_SCGC5_EMVSIM0(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_EMVSIM0_SHIFT)) & SIM_SCGC5_EMVSIM0_MASK)
+#define SIM_SCGC5_EMVSIM1_MASK                   (0x8000U)
+#define SIM_SCGC5_EMVSIM1_SHIFT                  (15U)
+#define SIM_SCGC5_EMVSIM1(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_EMVSIM1_SHIFT)) & SIM_SCGC5_EMVSIM1_MASK)
+#define SIM_SCGC5_LTC_MASK                       (0x20000U)
+#define SIM_SCGC5_LTC_SHIFT                      (17U)
+#define SIM_SCGC5_LTC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LTC_SHIFT)) & SIM_SCGC5_LTC_MASK)
+#define SIM_SCGC5_LPUART0_MASK                   (0x100000U)
+#define SIM_SCGC5_LPUART0_SHIFT                  (20U)
+#define SIM_SCGC5_LPUART0(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART0_SHIFT)) & SIM_SCGC5_LPUART0_MASK)
+#define SIM_SCGC5_LPUART1_MASK                   (0x200000U)
+#define SIM_SCGC5_LPUART1_SHIFT                  (21U)
+#define SIM_SCGC5_LPUART1(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART1_SHIFT)) & SIM_SCGC5_LPUART1_MASK)
+#define SIM_SCGC5_LPUART2_MASK                   (0x400000U)
+#define SIM_SCGC5_LPUART2_SHIFT                  (22U)
+#define SIM_SCGC5_LPUART2(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART2_SHIFT)) & SIM_SCGC5_LPUART2_MASK)
+#define SIM_SCGC5_QSPI0_MASK                     (0x4000000U)
+#define SIM_SCGC5_QSPI0_SHIFT                    (26U)
+#define SIM_SCGC5_QSPI0(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_QSPI0_SHIFT)) & SIM_SCGC5_QSPI0_MASK)
+#define SIM_SCGC5_FLEXIO0_MASK                   (0x80000000U)
+#define SIM_SCGC5_FLEXIO0_SHIFT                  (31U)
+#define SIM_SCGC5_FLEXIO0(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_FLEXIO0_SHIFT)) & SIM_SCGC5_FLEXIO0_MASK)
+
+/*! @name SCGC6 - System Clock Gating Control Register 6 */
+#define SIM_SCGC6_NVM_MASK                       (0x1U)
+#define SIM_SCGC6_NVM_SHIFT                      (0U)
+#define SIM_SCGC6_NVM(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_NVM_SHIFT)) & SIM_SCGC6_NVM_MASK)
+#define SIM_SCGC6_DMACHMUX_MASK                  (0x2U)
+#define SIM_SCGC6_DMACHMUX_SHIFT                 (1U)
+#define SIM_SCGC6_DMACHMUX(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMACHMUX_SHIFT)) & SIM_SCGC6_DMACHMUX_MASK)
+#define SIM_SCGC6_INTMUX0_MASK                   (0x10U)
+#define SIM_SCGC6_INTMUX0_SHIFT                  (4U)
+#define SIM_SCGC6_INTMUX0(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_INTMUX0_SHIFT)) & SIM_SCGC6_INTMUX0_MASK)
+#define SIM_SCGC6_TRNG_MASK                      (0x20U)
+#define SIM_SCGC6_TRNG_SHIFT                     (5U)
+#define SIM_SCGC6_TRNG(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TRNG_SHIFT)) & SIM_SCGC6_TRNG_MASK)
+#define SIM_SCGC6_SPI0_MASK                      (0x1000U)
+#define SIM_SCGC6_SPI0_SHIFT                     (12U)
+#define SIM_SCGC6_SPI0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI1_MASK                      (0x2000U)
+#define SIM_SCGC6_SPI1_SHIFT                     (13U)
+#define SIM_SCGC6_SPI1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_CRC_MASK                       (0x40000U)
+#define SIM_SCGC6_CRC_SHIFT                      (18U)
+#define SIM_SCGC6_CRC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_PIT0_MASK                      (0x800000U)
+#define SIM_SCGC6_PIT0_SHIFT                     (23U)
+#define SIM_SCGC6_PIT0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT0_SHIFT)) & SIM_SCGC6_PIT0_MASK)
+#define SIM_SCGC6_TPM0_MASK                      (0x1000000U)
+#define SIM_SCGC6_TPM0_SHIFT                     (24U)
+#define SIM_SCGC6_TPM0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
+#define SIM_SCGC6_TPM1_MASK                      (0x2000000U)
+#define SIM_SCGC6_TPM1_SHIFT                     (25U)
+#define SIM_SCGC6_TPM1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
+#define SIM_SCGC6_TPM2_MASK                      (0x4000000U)
+#define SIM_SCGC6_TPM2_SHIFT                     (26U)
+#define SIM_SCGC6_TPM2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK)
+#define SIM_SCGC6_ADC0_MASK                      (0x8000000U)
+#define SIM_SCGC6_ADC0_SHIFT                     (27U)
+#define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK                       (0x20000000U)
+#define SIM_SCGC6_RTC_SHIFT                      (29U)
+#define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_RTC_RF_MASK                    (0x40000000U)
+#define SIM_SCGC6_RTC_RF_SHIFT                   (30U)
+#define SIM_SCGC6_RTC_RF(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_RF_SHIFT)) & SIM_SCGC6_RTC_RF_MASK)
+#define SIM_SCGC6_DAC0_MASK                      (0x80000000U)
+#define SIM_SCGC6_DAC0_SHIFT                     (31U)
+#define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
+
+/*! @name SCGC7 - System Clock Gating Control Register 7 */
+#define SIM_SCGC7_DMA_MASK                       (0x2U)
+#define SIM_SCGC7_DMA_SHIFT                      (1U)
+#define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
+#define SIM_SCGC7_MPU_MASK                       (0x4U)
+#define SIM_SCGC7_MPU_SHIFT                      (2U)
+#define SIM_SCGC7_MPU(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
+
+/*! @name CLKDIV1 - System Clock Divider Register 1 */
+#define SIM_CLKDIV1_OUTDIV5_MASK                 (0xF000U)
+#define SIM_CLKDIV1_OUTDIV5_SHIFT                (12U)
+#define SIM_CLKDIV1_OUTDIV5(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV5_SHIFT)) & SIM_CLKDIV1_OUTDIV5_MASK)
+#define SIM_CLKDIV1_OUTDIV4_MASK                 (0xF0000U)
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                (16U)
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK                 (0xF000000U)
+#define SIM_CLKDIV1_OUTDIV2_SHIFT                (24U)
+#define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 (0xF0000000U)
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                (28U)
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
+
+/*! @name CLKDIV2 - System Clock Divider Register 2 */
+#define SIM_CLKDIV2_USBFRAC_MASK                 (0x1U)
+#define SIM_CLKDIV2_USBFRAC_SHIFT                (0U)
+#define SIM_CLKDIV2_USBFRAC(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBDIV_MASK                  (0xEU)
+#define SIM_CLKDIV2_USBDIV_SHIFT                 (1U)
+#define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+#define SIM_FCFG1_FLASHDIS_MASK                  (0x1U)
+#define SIM_FCFG1_FLASHDIS_SHIFT                 (0U)
+#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK                 (0x2U)
+#define SIM_FCFG1_FLASHDOZE_SHIFT                (1U)
+#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK                    (0xF000000U)
+#define SIM_FCFG1_PFSIZE_SHIFT                   (24U)
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+#define SIM_FCFG2_MAXADDR0_MASK                  (0x7F000000U)
+#define SIM_FCFG2_MAXADDR0_SHIFT                 (24U)
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+
+/*! @name UIDH - Unique Identification Register High */
+#define SIM_UIDH_UID_MASK                        (0xFFFFFFFFU)
+#define SIM_UIDH_UID_SHIFT                       (0U)
+#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
+
+/*! @name UIDMH - Unique Identification Register Mid-High */
+#define SIM_UIDMH_UID_MASK                       (0xFFFFFFFFU)
+#define SIM_UIDMH_UID_SHIFT                      (0U)
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
+
+/*! @name UIDML - Unique Identification Register Mid Low */
+#define SIM_UIDML_UID_MASK                       (0xFFFFFFFFU)
+#define SIM_UIDML_UID_SHIFT                      (0U)
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
+
+/*! @name UIDL - Unique Identification Register Low */
+#define SIM_UIDL_UID_MASK                        (0xFFFFFFFFU)
+#define SIM_UIDL_UID_SHIFT                       (0U)
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+
+/*! @name CLKDIV3 - System Clock Divider Register 3 */
+#define SIM_CLKDIV3_PLLFLLFRAC_MASK              (0x1U)
+#define SIM_CLKDIV3_PLLFLLFRAC_SHIFT             (0U)
+#define SIM_CLKDIV3_PLLFLLFRAC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK)
+#define SIM_CLKDIV3_PLLFLLDIV_MASK               (0xEU)
+#define SIM_CLKDIV3_PLLFLLDIV_SHIFT              (1U)
+#define SIM_CLKDIV3_PLLFLLDIV(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK)
+
+/*! @name MISCCTRL - Misc Control Register */
+#define SIM_MISCCTRL_DMAINTSEL0_MASK             (0x1U)
+#define SIM_MISCCTRL_DMAINTSEL0_SHIFT            (0U)
+#define SIM_MISCCTRL_DMAINTSEL0(x)               (((uint32_t)(((uint32_t)(x)) << SIM_MISCCTRL_DMAINTSEL0_SHIFT)) & SIM_MISCCTRL_DMAINTSEL0_MASK)
+#define SIM_MISCCTRL_DMAINTSEL1_MASK             (0x2U)
+#define SIM_MISCCTRL_DMAINTSEL1_SHIFT            (1U)
+#define SIM_MISCCTRL_DMAINTSEL1(x)               (((uint32_t)(((uint32_t)(x)) << SIM_MISCCTRL_DMAINTSEL1_SHIFT)) & SIM_MISCCTRL_DMAINTSEL1_MASK)
+#define SIM_MISCCTRL_DMAINTSEL2_MASK             (0x4U)
+#define SIM_MISCCTRL_DMAINTSEL2_SHIFT            (2U)
+#define SIM_MISCCTRL_DMAINTSEL2(x)               (((uint32_t)(((uint32_t)(x)) << SIM_MISCCTRL_DMAINTSEL2_SHIFT)) & SIM_MISCCTRL_DMAINTSEL2_MASK)
+#define SIM_MISCCTRL_DMAINTSEL3_MASK             (0x8U)
+#define SIM_MISCCTRL_DMAINTSEL3_SHIFT            (3U)
+#define SIM_MISCCTRL_DMAINTSEL3(x)               (((uint32_t)(((uint32_t)(x)) << SIM_MISCCTRL_DMAINTSEL3_SHIFT)) & SIM_MISCCTRL_DMAINTSEL3_MASK)
+#define SIM_MISCCTRL_LTCEN_MASK                  (0x10000U)
+#define SIM_MISCCTRL_LTCEN_SHIFT                 (16U)
+#define SIM_MISCCTRL_LTCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_MISCCTRL_LTCEN_SHIFT)) & SIM_MISCCTRL_LTCEN_MASK)
+
+/*! @name SECKEY0 - Secure Key Register 0 */
+#define SIM_SECKEY0_SECKEY_MASK                  (0xFFFFFFFFU)
+#define SIM_SECKEY0_SECKEY_SHIFT                 (0U)
+#define SIM_SECKEY0_SECKEY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SECKEY0_SECKEY_SHIFT)) & SIM_SECKEY0_SECKEY_MASK)
+
+/*! @name SECKEY1 - Secure Key Register 1 */
+#define SIM_SECKEY1_SECKEY_MASK                  (0xFFFFFFFFU)
+#define SIM_SECKEY1_SECKEY_SHIFT                 (0U)
+#define SIM_SECKEY1_SECKEY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SECKEY1_SECKEY_SHIFT)) & SIM_SECKEY1_SECKEY_MASK)
+
+/*! @name SECKEY2 - Secure Key Register 2 */
+#define SIM_SECKEY2_SECKEY_MASK                  (0xFFFFFFFFU)
+#define SIM_SECKEY2_SECKEY_SHIFT                 (0U)
+#define SIM_SECKEY2_SECKEY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SECKEY2_SECKEY_SHIFT)) & SIM_SECKEY2_SECKEY_MASK)
+
+/*! @name SECKEY3 - Secure Key Register 3 */
+#define SIM_SECKEY3_SECKEY_MASK                  (0xFFFFFFFFU)
+#define SIM_SECKEY3_SECKEY_SHIFT                 (0U)
+#define SIM_SECKEY3_SECKEY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SECKEY3_SECKEY_SHIFT)) & SIM_SECKEY3_SECKEY_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
+  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
+  __IO uint8_t STOPCTRL;                           /**< Stop Control Register, offset: 0x2 */
+  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/*! @name PMPROT - Power Mode Protection register */
+#define SMC_PMPROT_AVLLS_MASK                    (0x2U)
+#define SMC_PMPROT_AVLLS_SHIFT                   (1U)
+#define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK                     (0x8U)
+#define SMC_PMPROT_ALLS_SHIFT                    (3U)
+#define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK                     (0x20U)
+#define SMC_PMPROT_AVLP_SHIFT                    (5U)
+#define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+#define SMC_PMPROT_AHSRUN_MASK                   (0x80U)
+#define SMC_PMPROT_AHSRUN_SHIFT                  (7U)
+#define SMC_PMPROT_AHSRUN(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
+
+/*! @name PMCTRL - Power Mode Control register */
+#define SMC_PMCTRL_STOPM_MASK                    (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT                   (0U)
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK                    (0x8U)
+#define SMC_PMCTRL_STOPA_SHIFT                   (3U)
+#define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK                     (0x60U)
+#define SMC_PMCTRL_RUNM_SHIFT                    (5U)
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+
+/*! @name STOPCTRL - Stop Control Register */
+#define SMC_STOPCTRL_LLSM_MASK                   (0x7U)
+#define SMC_STOPCTRL_LLSM_SHIFT                  (0U)
+#define SMC_STOPCTRL_LLSM(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
+#define SMC_STOPCTRL_LPOPO_MASK                  (0x8U)
+#define SMC_STOPCTRL_LPOPO_SHIFT                 (3U)
+#define SMC_STOPCTRL_LPOPO(x)                    (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LPOPO_SHIFT)) & SMC_STOPCTRL_LPOPO_MASK)
+#define SMC_STOPCTRL_PORPO_MASK                  (0x20U)
+#define SMC_STOPCTRL_PORPO_SHIFT                 (5U)
+#define SMC_STOPCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
+#define SMC_STOPCTRL_PSTOPO_MASK                 (0xC0U)
+#define SMC_STOPCTRL_PSTOPO_SHIFT                (6U)
+#define SMC_STOPCTRL_PSTOPO(x)                   (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
+
+/*! @name PMSTAT - Power Mode Status register */
+#define SMC_PMSTAT_PMSTAT_MASK                   (0xFFU)
+#define SMC_PMSTAT_PMSTAT_SHIFT                  (0U)
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE                                 (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC                                      ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS                           { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS                            { SMC }
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t CTAR[2];                           /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+    __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+  };
+       uint8_t RESERVED_1[24];
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x2C */
+  __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+  union {                                          /* offset: 0x34 */
+    __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+    __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+  };
+  __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
+  __I  uint32_t TXFR0;                             /**< Transmit FIFO Registers, offset: 0x3C */
+  __I  uint32_t TXFR1;                             /**< Transmit FIFO Registers, offset: 0x40 */
+  __I  uint32_t TXFR2;                             /**< Transmit FIFO Registers, offset: 0x44 */
+  __I  uint32_t TXFR3;                             /**< Transmit FIFO Registers, offset: 0x48 */
+       uint8_t RESERVED_2[48];
+  __I  uint32_t RXFR0;                             /**< Receive FIFO Registers, offset: 0x7C */
+  __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
+  __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
+  __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name MCR - Module Configuration Register */
+#define SPI_MCR_HALT_MASK                        (0x1U)
+#define SPI_MCR_HALT_SHIFT                       (0U)
+#define SPI_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK                     (0x300U)
+#define SPI_MCR_SMPL_PT_SHIFT                    (8U)
+#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK                     (0x400U)
+#define SPI_MCR_CLR_RXF_SHIFT                    (10U)
+#define SPI_MCR_CLR_RXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK                     (0x800U)
+#define SPI_MCR_CLR_TXF_SHIFT                    (11U)
+#define SPI_MCR_CLR_TXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK                     (0x1000U)
+#define SPI_MCR_DIS_RXF_SHIFT                    (12U)
+#define SPI_MCR_DIS_RXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK                     (0x2000U)
+#define SPI_MCR_DIS_TXF_SHIFT                    (13U)
+#define SPI_MCR_DIS_TXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK                        (0x4000U)
+#define SPI_MCR_MDIS_SHIFT                       (14U)
+#define SPI_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK                        (0x8000U)
+#define SPI_MCR_DOZE_SHIFT                       (15U)
+#define SPI_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK                       (0x3F0000U)
+#define SPI_MCR_PCSIS_SHIFT                      (16U)
+#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK                        (0x1000000U)
+#define SPI_MCR_ROOE_SHIFT                       (24U)
+#define SPI_MCR_ROOE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK                       (0x2000000U)
+#define SPI_MCR_PCSSE_SHIFT                      (25U)
+#define SPI_MCR_PCSSE(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK                        (0x4000000U)
+#define SPI_MCR_MTFE_SHIFT                       (26U)
+#define SPI_MCR_MTFE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK                         (0x8000000U)
+#define SPI_MCR_FRZ_SHIFT                        (27U)
+#define SPI_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK                       (0x30000000U)
+#define SPI_MCR_DCONF_SHIFT                      (28U)
+#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK                   (0x40000000U)
+#define SPI_MCR_CONT_SCKE_SHIFT                  (30U)
+#define SPI_MCR_CONT_SCKE(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK                        (0x80000000U)
+#define SPI_MCR_MSTR_SHIFT                       (31U)
+#define SPI_MCR_MSTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
+
+/*! @name TCR - Transfer Count Register */
+#define SPI_TCR_SPI_TCNT_MASK                    (0xFFFF0000U)
+#define SPI_TCR_SPI_TCNT_SHIFT                   (16U)
+#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
+
+/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
+#define SPI_CTAR_BR_MASK                         (0xFU)
+#define SPI_CTAR_BR_SHIFT                        (0U)
+#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK                         (0xF0U)
+#define SPI_CTAR_DT_SHIFT                        (4U)
+#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK                        (0xF00U)
+#define SPI_CTAR_ASC_SHIFT                       (8U)
+#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK                      (0xF000U)
+#define SPI_CTAR_CSSCK_SHIFT                     (12U)
+#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK                        (0x30000U)
+#define SPI_CTAR_PBR_SHIFT                       (16U)
+#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK                        (0xC0000U)
+#define SPI_CTAR_PDT_SHIFT                       (18U)
+#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK                       (0x300000U)
+#define SPI_CTAR_PASC_SHIFT                      (20U)
+#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK                     (0xC00000U)
+#define SPI_CTAR_PCSSCK_SHIFT                    (22U)
+#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK                      (0x1000000U)
+#define SPI_CTAR_LSBFE_SHIFT                     (24U)
+#define SPI_CTAR_LSBFE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK                       (0x2000000U)
+#define SPI_CTAR_CPHA_SHIFT                      (25U)
+#define SPI_CTAR_CPHA(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK                       (0x4000000U)
+#define SPI_CTAR_CPOL_SHIFT                      (26U)
+#define SPI_CTAR_CPOL(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK                       (0x78000000U)
+#define SPI_CTAR_FMSZ_SHIFT                      (27U)
+#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK                        (0x80000000U)
+#define SPI_CTAR_DBR_SHIFT                       (31U)
+#define SPI_CTAR_DBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
+
+/* The count of SPI_CTAR */
+#define SPI_CTAR_COUNT                           (2U)
+
+/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
+#define SPI_CTAR_SLAVE_CPHA_MASK                 (0x2000000U)
+#define SPI_CTAR_SLAVE_CPHA_SHIFT                (25U)
+#define SPI_CTAR_SLAVE_CPHA(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK                 (0x4000000U)
+#define SPI_CTAR_SLAVE_CPOL_SHIFT                (26U)
+#define SPI_CTAR_SLAVE_CPOL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK                 (0x78000000U)
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT                (27U)
+#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
+
+/* The count of SPI_CTAR_SLAVE */
+#define SPI_CTAR_SLAVE_COUNT                     (1U)
+
+/*! @name SR - Status Register */
+#define SPI_SR_POPNXTPTR_MASK                    (0xFU)
+#define SPI_SR_POPNXTPTR_SHIFT                   (0U)
+#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK                        (0xF0U)
+#define SPI_SR_RXCTR_SHIFT                       (4U)
+#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK                     (0xF00U)
+#define SPI_SR_TXNXTPTR_SHIFT                    (8U)
+#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK                        (0xF000U)
+#define SPI_SR_TXCTR_SHIFT                       (12U)
+#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK                         (0x20000U)
+#define SPI_SR_RFDF_SHIFT                        (17U)
+#define SPI_SR_RFDF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK                         (0x80000U)
+#define SPI_SR_RFOF_SHIFT                        (19U)
+#define SPI_SR_RFOF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK                         (0x2000000U)
+#define SPI_SR_TFFF_SHIFT                        (25U)
+#define SPI_SR_TFFF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK                         (0x8000000U)
+#define SPI_SR_TFUF_SHIFT                        (27U)
+#define SPI_SR_TFUF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK                         (0x10000000U)
+#define SPI_SR_EOQF_SHIFT                        (28U)
+#define SPI_SR_EOQF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK                        (0x40000000U)
+#define SPI_SR_TXRXS_SHIFT                       (30U)
+#define SPI_SR_TXRXS(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK                          (0x80000000U)
+#define SPI_SR_TCF_SHIFT                         (31U)
+#define SPI_SR_TCF(x)                            (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
+
+/*! @name RSER - DMA/Interrupt Request Select and Enable Register */
+#define SPI_RSER_RFDF_DIRS_MASK                  (0x10000U)
+#define SPI_RSER_RFDF_DIRS_SHIFT                 (16U)
+#define SPI_RSER_RFDF_DIRS(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK                    (0x20000U)
+#define SPI_RSER_RFDF_RE_SHIFT                   (17U)
+#define SPI_RSER_RFDF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK                    (0x80000U)
+#define SPI_RSER_RFOF_RE_SHIFT                   (19U)
+#define SPI_RSER_RFOF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK                  (0x1000000U)
+#define SPI_RSER_TFFF_DIRS_SHIFT                 (24U)
+#define SPI_RSER_TFFF_DIRS(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK                    (0x2000000U)
+#define SPI_RSER_TFFF_RE_SHIFT                   (25U)
+#define SPI_RSER_TFFF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK                    (0x8000000U)
+#define SPI_RSER_TFUF_RE_SHIFT                   (27U)
+#define SPI_RSER_TFUF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK                    (0x10000000U)
+#define SPI_RSER_EOQF_RE_SHIFT                   (28U)
+#define SPI_RSER_EOQF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK                     (0x80000000U)
+#define SPI_RSER_TCF_RE_SHIFT                    (31U)
+#define SPI_RSER_TCF_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
+
+/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
+#define SPI_PUSHR_TXDATA_MASK                    (0xFFFFU)
+#define SPI_PUSHR_TXDATA_SHIFT                   (0U)
+#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK                       (0x3F0000U)
+#define SPI_PUSHR_PCS_SHIFT                      (16U)
+#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK                     (0x4000000U)
+#define SPI_PUSHR_CTCNT_SHIFT                    (26U)
+#define SPI_PUSHR_CTCNT(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK                       (0x8000000U)
+#define SPI_PUSHR_EOQ_SHIFT                      (27U)
+#define SPI_PUSHR_EOQ(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK                      (0x70000000U)
+#define SPI_PUSHR_CTAS_SHIFT                     (28U)
+#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK                      (0x80000000U)
+#define SPI_PUSHR_CONT_SHIFT                     (31U)
+#define SPI_PUSHR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
+
+/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK              (0xFFFFU)
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             (0U)
+#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
+
+/*! @name POPR - POP RX FIFO Register */
+#define SPI_POPR_RXDATA_MASK                     (0xFFFFFFFFU)
+#define SPI_POPR_RXDATA_SHIFT                    (0U)
+#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
+
+/*! @name TXFR0 - Transmit FIFO Registers */
+#define SPI_TXFR0_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR0_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR1 - Transmit FIFO Registers */
+#define SPI_TXFR1_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR1_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR2 - Transmit FIFO Registers */
+#define SPI_TXFR2_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR2_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR3 - Transmit FIFO Registers */
+#define SPI_TXFR3_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR3_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
+
+/*! @name RXFR0 - Receive FIFO Registers */
+#define SPI_RXFR0_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPI_RXFR0_RXDATA_SHIFT                   (0U)
+#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
+
+/*! @name RXFR1 - Receive FIFO Registers */
+#define SPI_RXFR1_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPI_RXFR1_RXDATA_SHIFT                   (0U)
+#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
+
+/*! @name RXFR2 - Receive FIFO Registers */
+#define SPI_RXFR2_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPI_RXFR2_RXDATA_SHIFT                   (0U)
+#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
+
+/*! @name RXFR3 - Receive FIFO Registers */
+#define SPI_RXFR3_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPI_RXFR3_RXDATA_SHIFT                   (0U)
+#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TPM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[6];
+       uint8_t RESERVED_0[20];
+  __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x50 */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t COMBINE;                           /**< Combine Channel Register, offset: 0x64 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t POL;                               /**< Channel Polarity, offset: 0x70 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FILTER;                            /**< Filter Control, offset: 0x78 */
+       uint8_t RESERVED_4[8];
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TPM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/*! @name SC - Status and Control */
+#define TPM_SC_PS_MASK                           (0x7U)
+#define TPM_SC_PS_SHIFT                          (0U)
+#define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK                         (0x18U)
+#define TPM_SC_CMOD_SHIFT                        (3U)
+#define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK                        (0x20U)
+#define TPM_SC_CPWMS_SHIFT                       (5U)
+#define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
+#define TPM_SC_TOIE_MASK                         (0x40U)
+#define TPM_SC_TOIE_SHIFT                        (6U)
+#define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
+#define TPM_SC_TOF_MASK                          (0x80U)
+#define TPM_SC_TOF_SHIFT                         (7U)
+#define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
+#define TPM_SC_DMA_MASK                          (0x100U)
+#define TPM_SC_DMA_SHIFT                         (8U)
+#define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
+
+/*! @name CNT - Counter */
+#define TPM_CNT_COUNT_MASK                       (0xFFFFU)
+#define TPM_CNT_COUNT_SHIFT                      (0U)
+#define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
+
+/*! @name MOD - Modulo */
+#define TPM_MOD_MOD_MASK                         (0xFFFFU)
+#define TPM_MOD_MOD_SHIFT                        (0U)
+#define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
+
+/*! @name CnSC - Channel (n) Status and Control */
+#define TPM_CnSC_DMA_MASK                        (0x1U)
+#define TPM_CnSC_DMA_SHIFT                       (0U)
+#define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
+#define TPM_CnSC_ELSA_MASK                       (0x4U)
+#define TPM_CnSC_ELSA_SHIFT                      (2U)
+#define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
+#define TPM_CnSC_ELSB_MASK                       (0x8U)
+#define TPM_CnSC_ELSB_SHIFT                      (3U)
+#define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
+#define TPM_CnSC_MSA_MASK                        (0x10U)
+#define TPM_CnSC_MSA_SHIFT                       (4U)
+#define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
+#define TPM_CnSC_MSB_MASK                        (0x20U)
+#define TPM_CnSC_MSB_SHIFT                       (5U)
+#define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
+#define TPM_CnSC_CHIE_MASK                       (0x40U)
+#define TPM_CnSC_CHIE_SHIFT                      (6U)
+#define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
+#define TPM_CnSC_CHF_MASK                        (0x80U)
+#define TPM_CnSC_CHF_SHIFT                       (7U)
+#define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
+
+/* The count of TPM_CnSC */
+#define TPM_CnSC_COUNT                           (6U)
+
+/*! @name CnV - Channel (n) Value */
+#define TPM_CnV_VAL_MASK                         (0xFFFFU)
+#define TPM_CnV_VAL_SHIFT                        (0U)
+#define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
+
+/* The count of TPM_CnV */
+#define TPM_CnV_COUNT                            (6U)
+
+/*! @name STATUS - Capture and Compare Status */
+#define TPM_STATUS_CH0F_MASK                     (0x1U)
+#define TPM_STATUS_CH0F_SHIFT                    (0U)
+#define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
+#define TPM_STATUS_CH1F_MASK                     (0x2U)
+#define TPM_STATUS_CH1F_SHIFT                    (1U)
+#define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
+#define TPM_STATUS_CH2F_MASK                     (0x4U)
+#define TPM_STATUS_CH2F_SHIFT                    (2U)
+#define TPM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
+#define TPM_STATUS_CH3F_MASK                     (0x8U)
+#define TPM_STATUS_CH3F_SHIFT                    (3U)
+#define TPM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
+#define TPM_STATUS_CH4F_MASK                     (0x10U)
+#define TPM_STATUS_CH4F_SHIFT                    (4U)
+#define TPM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
+#define TPM_STATUS_CH5F_MASK                     (0x20U)
+#define TPM_STATUS_CH5F_SHIFT                    (5U)
+#define TPM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
+#define TPM_STATUS_TOF_MASK                      (0x100U)
+#define TPM_STATUS_TOF_SHIFT                     (8U)
+#define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
+
+/*! @name COMBINE - Combine Channel Register */
+#define TPM_COMBINE_COMBINE0_MASK                (0x1U)
+#define TPM_COMBINE_COMBINE0_SHIFT               (0U)
+#define TPM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
+#define TPM_COMBINE_COMSWAP0_MASK                (0x2U)
+#define TPM_COMBINE_COMSWAP0_SHIFT               (1U)
+#define TPM_COMBINE_COMSWAP0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
+#define TPM_COMBINE_COMBINE1_MASK                (0x100U)
+#define TPM_COMBINE_COMBINE1_SHIFT               (8U)
+#define TPM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK)
+#define TPM_COMBINE_COMSWAP1_MASK                (0x200U)
+#define TPM_COMBINE_COMSWAP1_SHIFT               (9U)
+#define TPM_COMBINE_COMSWAP1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK)
+#define TPM_COMBINE_COMBINE2_MASK                (0x10000U)
+#define TPM_COMBINE_COMBINE2_SHIFT               (16U)
+#define TPM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK)
+#define TPM_COMBINE_COMSWAP2_MASK                (0x20000U)
+#define TPM_COMBINE_COMSWAP2_SHIFT               (17U)
+#define TPM_COMBINE_COMSWAP2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK)
+
+/*! @name POL - Channel Polarity */
+#define TPM_POL_POL0_MASK                        (0x1U)
+#define TPM_POL_POL0_SHIFT                       (0U)
+#define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
+#define TPM_POL_POL1_MASK                        (0x2U)
+#define TPM_POL_POL1_SHIFT                       (1U)
+#define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
+#define TPM_POL_POL2_MASK                        (0x4U)
+#define TPM_POL_POL2_SHIFT                       (2U)
+#define TPM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)
+#define TPM_POL_POL3_MASK                        (0x8U)
+#define TPM_POL_POL3_SHIFT                       (3U)
+#define TPM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)
+#define TPM_POL_POL4_MASK                        (0x10U)
+#define TPM_POL_POL4_SHIFT                       (4U)
+#define TPM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK)
+#define TPM_POL_POL5_MASK                        (0x20U)
+#define TPM_POL_POL5_SHIFT                       (5U)
+#define TPM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK)
+
+/*! @name FILTER - Filter Control */
+#define TPM_FILTER_CH0FVAL_MASK                  (0xFU)
+#define TPM_FILTER_CH0FVAL_SHIFT                 (0U)
+#define TPM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
+#define TPM_FILTER_CH1FVAL_MASK                  (0xF0U)
+#define TPM_FILTER_CH1FVAL_SHIFT                 (4U)
+#define TPM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
+#define TPM_FILTER_CH2FVAL_MASK                  (0xF00U)
+#define TPM_FILTER_CH2FVAL_SHIFT                 (8U)
+#define TPM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK)
+#define TPM_FILTER_CH3FVAL_MASK                  (0xF000U)
+#define TPM_FILTER_CH3FVAL_SHIFT                 (12U)
+#define TPM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK)
+#define TPM_FILTER_CH4FVAL_MASK                  (0xF0000U)
+#define TPM_FILTER_CH4FVAL_SHIFT                 (16U)
+#define TPM_FILTER_CH4FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK)
+#define TPM_FILTER_CH5FVAL_MASK                  (0xF00000U)
+#define TPM_FILTER_CH5FVAL_SHIFT                 (20U)
+#define TPM_FILTER_CH5FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK)
+
+/*! @name CONF - Configuration */
+#define TPM_CONF_DOZEEN_MASK                     (0x20U)
+#define TPM_CONF_DOZEEN_SHIFT                    (5U)
+#define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
+#define TPM_CONF_DBGMODE_MASK                    (0xC0U)
+#define TPM_CONF_DBGMODE_SHIFT                   (6U)
+#define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBSYNC_MASK                    (0x100U)
+#define TPM_CONF_GTBSYNC_SHIFT                   (8U)
+#define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
+#define TPM_CONF_GTBEEN_MASK                     (0x200U)
+#define TPM_CONF_GTBEEN_SHIFT                    (9U)
+#define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
+#define TPM_CONF_CSOT_MASK                       (0x10000U)
+#define TPM_CONF_CSOT_SHIFT                      (16U)
+#define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
+#define TPM_CONF_CSOO_MASK                       (0x20000U)
+#define TPM_CONF_CSOO_SHIFT                      (17U)
+#define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
+#define TPM_CONF_CROT_MASK                       (0x40000U)
+#define TPM_CONF_CROT_SHIFT                      (18U)
+#define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
+#define TPM_CONF_CPOT_MASK                       (0x80000U)
+#define TPM_CONF_CPOT_SHIFT                      (19U)
+#define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
+#define TPM_CONF_TRGPOL_MASK                     (0x400000U)
+#define TPM_CONF_TRGPOL_SHIFT                    (22U)
+#define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
+#define TPM_CONF_TRGSRC_MASK                     (0x800000U)
+#define TPM_CONF_TRGSRC_SHIFT                    (23U)
+#define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
+#define TPM_CONF_TRGSEL_MASK                     (0xF000000U)
+#define TPM_CONF_TRGSEL_SHIFT                    (24U)
+#define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE                                (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0                                     ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE                                (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1                                     ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE                                (0x4003A000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2                                     ((TPM_Type *)TPM2_BASE)
+/** Array initializer of TPM peripheral base addresses */
+#define TPM_BASE_ADDRS                           { TPM0_BASE, TPM1_BASE, TPM2_BASE }
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASE_PTRS                            { TPM0, TPM1, TPM2 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS                                 { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TRNG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
+ * @{
+ */
+
+/** TRNG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCTL;                              /**< TRNG0 Miscellaneous Control Register, offset: 0x0 */
+  __IO uint32_t SCMISC;                            /**< TRNG0 Statistical Check Miscellaneous Register, offset: 0x4 */
+  __IO uint32_t PKRRNG;                            /**< TRNG0 Poker Range Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t PKRMAX;                            /**< TRNG0 Poker Maximum Limit Register, offset: 0xC */
+    __I  uint32_t PKRSQ;                             /**< TRNG0 Poker Square Calculation Result Register, offset: 0xC */
+  };
+  __IO uint32_t SDCTL;                             /**< TRNG0 Seed Control Register, offset: 0x10 */
+  union {                                          /* offset: 0x14 */
+    __IO uint32_t SBLIM;                             /**< TRNG0 Sparse Bit Limit Register, offset: 0x14 */
+    __I  uint32_t TOTSAM;                            /**< TRNG0 Total Samples Register, offset: 0x14 */
+  };
+  __IO uint32_t FRQMIN;                            /**< TRNG0 Frequency Count Minimum Limit Register, offset: 0x18 */
+  union {                                          /* offset: 0x1C */
+    __I  uint32_t FRQCNT;                            /**< TRNG0 Frequency Count Register, offset: 0x1C */
+    __IO uint32_t FRQMAX;                            /**< TRNG0 Frequency Count Maximum Limit Register, offset: 0x1C */
+  };
+  union {                                          /* offset: 0x20 */
+    __I  uint32_t SCMC;                              /**< TRNG0 Statistical Check Monobit Count Register, offset: 0x20 */
+    __IO uint32_t SCML;                              /**< TRNG0 Statistical Check Monobit Limit Register, offset: 0x20 */
+  };
+  union {                                          /* offset: 0x24 */
+    __I  uint32_t SCR1C;                             /**< TRNG0 Statistical Check Run Length 1 Count Register, offset: 0x24 */
+    __IO uint32_t SCR1L;                             /**< TRNG0 Statistical Check Run Length 1 Limit Register, offset: 0x24 */
+  };
+  union {                                          /* offset: 0x28 */
+    __I  uint32_t SCR2C;                             /**< TRNG0 Statistical Check Run Length 2 Count Register, offset: 0x28 */
+    __IO uint32_t SCR2L;                             /**< TRNG0 Statistical Check Run Length 2 Limit Register, offset: 0x28 */
+  };
+  union {                                          /* offset: 0x2C */
+    __I  uint32_t SCR3C;                             /**< TRNG0 Statistical Check Run Length 3 Count Register, offset: 0x2C */
+    __IO uint32_t SCR3L;                             /**< TRNG0 Statistical Check Run Length 3 Limit Register, offset: 0x2C */
+  };
+  union {                                          /* offset: 0x30 */
+    __I  uint32_t SCR4C;                             /**< TRNG0 Statistical Check Run Length 4 Count Register, offset: 0x30 */
+    __IO uint32_t SCR4L;                             /**< TRNG0 Statistical Check Run Length 4 Limit Register, offset: 0x30 */
+  };
+  union {                                          /* offset: 0x34 */
+    __I  uint32_t SCR5C;                             /**< TRNG0 Statistical Check Run Length 5 Count Register, offset: 0x34 */
+    __IO uint32_t SCR5L;                             /**< TRNG0 Statistical Check Run Length 5 Limit Register, offset: 0x34 */
+  };
+  union {                                          /* offset: 0x38 */
+    __I  uint32_t SCR6PC;                            /**< TRNG0 Statistical Check Run Length 6+ Count Register, offset: 0x38 */
+    __IO uint32_t SCR6PL;                            /**< TRNG0 Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
+  };
+  __I  uint32_t STATUS;                            /**< TRNG0 Status Register, offset: 0x3C */
+  __I  uint32_t ENT[16];                           /**< RNG TRNG Entropy Read Register, array offset: 0x40, array step: 0x4 */
+  __I  uint32_t PKRCNT10;                          /**< TRNG0 Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
+  __I  uint32_t PKRCNT32;                          /**< TRNG0 Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
+  __I  uint32_t PKRCNT54;                          /**< TRNG0 Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
+  __I  uint32_t PKRCNT76;                          /**< TRNG0 Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
+  __I  uint32_t PKRCNT98;                          /**< TRNG0 Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
+  __I  uint32_t PKRCNTBA;                          /**< TRNG0 Statistical Check Poker Count B and A Register, offset: 0x94 */
+  __I  uint32_t PKRCNTDC;                          /**< TRNG0 Statistical Check Poker Count D and C Register, offset: 0x98 */
+  __I  uint32_t PKRCNTFE;                          /**< TRNG0 Statistical Check Poker Count F and E Register, offset: 0x9C */
+  __IO uint32_t SEC_CFG;                           /**< TRNG0 Security Configuration Register, offset: 0xA0 */
+  __IO uint32_t INT_CTRL;                          /**< TRNG0 Interrupt Control Register, offset: 0xA4 */
+  __IO uint32_t INT_MASK;                          /**< TRNG0 Mask Register, offset: 0xA8 */
+  __IO uint32_t INT_STATUS;                        /**< TRNG0 Interrupt Status Register, offset: 0xAC */
+       uint8_t RESERVED_0[64];
+  __I  uint32_t VID1;                              /**< TRNG0 Version ID Register (MS), offset: 0xF0 */
+  __I  uint32_t VID2;                              /**< TRNG0 Version ID Register (LS), offset: 0xF4 */
+} TRNG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TRNG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRNG_Register_Masks TRNG Register Masks
+ * @{
+ */
+
+/*! @name MCTL - TRNG0 Miscellaneous Control Register */
+#define TRNG_MCTL_SAMP_MODE_MASK                 (0x3U)
+#define TRNG_MCTL_SAMP_MODE_SHIFT                (0U)
+#define TRNG_MCTL_SAMP_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
+#define TRNG_MCTL_OSC_DIV_MASK                   (0xCU)
+#define TRNG_MCTL_OSC_DIV_SHIFT                  (2U)
+#define TRNG_MCTL_OSC_DIV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
+#define TRNG_MCTL_UNUSED_MASK                    (0x10U)
+#define TRNG_MCTL_UNUSED_SHIFT                   (4U)
+#define TRNG_MCTL_UNUSED(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED_SHIFT)) & TRNG_MCTL_UNUSED_MASK)
+#define TRNG_MCTL_TRNG_ACC_MASK                  (0x20U)
+#define TRNG_MCTL_TRNG_ACC_SHIFT                 (5U)
+#define TRNG_MCTL_TRNG_ACC(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)
+#define TRNG_MCTL_RST_DEF_MASK                   (0x40U)
+#define TRNG_MCTL_RST_DEF_SHIFT                  (6U)
+#define TRNG_MCTL_RST_DEF(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
+#define TRNG_MCTL_FOR_SCLK_MASK                  (0x80U)
+#define TRNG_MCTL_FOR_SCLK_SHIFT                 (7U)
+#define TRNG_MCTL_FOR_SCLK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
+#define TRNG_MCTL_FCT_FAIL_MASK                  (0x100U)
+#define TRNG_MCTL_FCT_FAIL_SHIFT                 (8U)
+#define TRNG_MCTL_FCT_FAIL(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
+#define TRNG_MCTL_FCT_VAL_MASK                   (0x200U)
+#define TRNG_MCTL_FCT_VAL_SHIFT                  (9U)
+#define TRNG_MCTL_FCT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
+#define TRNG_MCTL_ENT_VAL_MASK                   (0x400U)
+#define TRNG_MCTL_ENT_VAL_SHIFT                  (10U)
+#define TRNG_MCTL_ENT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
+#define TRNG_MCTL_TST_OUT_MASK                   (0x800U)
+#define TRNG_MCTL_TST_OUT_SHIFT                  (11U)
+#define TRNG_MCTL_TST_OUT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
+#define TRNG_MCTL_ERR_MASK                       (0x1000U)
+#define TRNG_MCTL_ERR_SHIFT                      (12U)
+#define TRNG_MCTL_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
+#define TRNG_MCTL_TSTOP_OK_MASK                  (0x2000U)
+#define TRNG_MCTL_TSTOP_OK_SHIFT                 (13U)
+#define TRNG_MCTL_TSTOP_OK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
+#define TRNG_MCTL_PRGM_MASK                      (0x10000U)
+#define TRNG_MCTL_PRGM_SHIFT                     (16U)
+#define TRNG_MCTL_PRGM(x)                        (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
+
+/*! @name SCMISC - TRNG0 Statistical Check Miscellaneous Register */
+#define TRNG_SCMISC_LRUN_MAX_MASK                (0xFFU)
+#define TRNG_SCMISC_LRUN_MAX_SHIFT               (0U)
+#define TRNG_SCMISC_LRUN_MAX(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
+#define TRNG_SCMISC_RTY_CT_MASK                  (0xF0000U)
+#define TRNG_SCMISC_RTY_CT_SHIFT                 (16U)
+#define TRNG_SCMISC_RTY_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
+
+/*! @name PKRRNG - TRNG0 Poker Range Register */
+#define TRNG_PKRRNG_PKR_RNG_MASK                 (0xFFFFU)
+#define TRNG_PKRRNG_PKR_RNG_SHIFT                (0U)
+#define TRNG_PKRRNG_PKR_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
+
+/*! @name PKRMAX - TRNG0 Poker Maximum Limit Register */
+#define TRNG_PKRMAX_PKR_MAX_MASK                 (0xFFFFFFU)
+#define TRNG_PKRMAX_PKR_MAX_SHIFT                (0U)
+#define TRNG_PKRMAX_PKR_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
+
+/*! @name PKRSQ - TRNG0 Poker Square Calculation Result Register */
+#define TRNG_PKRSQ_PKR_SQ_MASK                   (0xFFFFFFU)
+#define TRNG_PKRSQ_PKR_SQ_SHIFT                  (0U)
+#define TRNG_PKRSQ_PKR_SQ(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
+
+/*! @name SDCTL - TRNG0 Seed Control Register */
+#define TRNG_SDCTL_SAMP_SIZE_MASK                (0xFFFFU)
+#define TRNG_SDCTL_SAMP_SIZE_SHIFT               (0U)
+#define TRNG_SDCTL_SAMP_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
+#define TRNG_SDCTL_ENT_DLY_MASK                  (0xFFFF0000U)
+#define TRNG_SDCTL_ENT_DLY_SHIFT                 (16U)
+#define TRNG_SDCTL_ENT_DLY(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
+
+/*! @name SBLIM - TRNG0 Sparse Bit Limit Register */
+#define TRNG_SBLIM_SB_LIM_MASK                   (0x3FFU)
+#define TRNG_SBLIM_SB_LIM_SHIFT                  (0U)
+#define TRNG_SBLIM_SB_LIM(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
+
+/*! @name TOTSAM - TRNG0 Total Samples Register */
+#define TRNG_TOTSAM_TOT_SAM_MASK                 (0xFFFFFU)
+#define TRNG_TOTSAM_TOT_SAM_SHIFT                (0U)
+#define TRNG_TOTSAM_TOT_SAM(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
+
+/*! @name FRQMIN - TRNG0 Frequency Count Minimum Limit Register */
+#define TRNG_FRQMIN_FRQ_MIN_MASK                 (0x3FFFFFU)
+#define TRNG_FRQMIN_FRQ_MIN_SHIFT                (0U)
+#define TRNG_FRQMIN_FRQ_MIN(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
+
+/*! @name FRQCNT - TRNG0 Frequency Count Register */
+#define TRNG_FRQCNT_FRQ_CT_MASK                  (0x3FFFFFU)
+#define TRNG_FRQCNT_FRQ_CT_SHIFT                 (0U)
+#define TRNG_FRQCNT_FRQ_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
+
+/*! @name FRQMAX - TRNG0 Frequency Count Maximum Limit Register */
+#define TRNG_FRQMAX_FRQ_MAX_MASK                 (0x3FFFFFU)
+#define TRNG_FRQMAX_FRQ_MAX_SHIFT                (0U)
+#define TRNG_FRQMAX_FRQ_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
+
+/*! @name SCMC - TRNG0 Statistical Check Monobit Count Register */
+#define TRNG_SCMC_MONO_CT_MASK                   (0xFFFFU)
+#define TRNG_SCMC_MONO_CT_SHIFT                  (0U)
+#define TRNG_SCMC_MONO_CT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
+
+/*! @name SCML - TRNG0 Statistical Check Monobit Limit Register */
+#define TRNG_SCML_MONO_MAX_MASK                  (0xFFFFU)
+#define TRNG_SCML_MONO_MAX_SHIFT                 (0U)
+#define TRNG_SCML_MONO_MAX(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
+#define TRNG_SCML_MONO_RNG_MASK                  (0xFFFF0000U)
+#define TRNG_SCML_MONO_RNG_SHIFT                 (16U)
+#define TRNG_SCML_MONO_RNG(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
+
+/*! @name SCR1C - TRNG0 Statistical Check Run Length 1 Count Register */
+#define TRNG_SCR1C_R1_0_CT_MASK                  (0x7FFFU)
+#define TRNG_SCR1C_R1_0_CT_SHIFT                 (0U)
+#define TRNG_SCR1C_R1_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
+#define TRNG_SCR1C_R1_1_CT_MASK                  (0x7FFF0000U)
+#define TRNG_SCR1C_R1_1_CT_SHIFT                 (16U)
+#define TRNG_SCR1C_R1_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
+
+/*! @name SCR1L - TRNG0 Statistical Check Run Length 1 Limit Register */
+#define TRNG_SCR1L_RUN1_MAX_MASK                 (0x7FFFU)
+#define TRNG_SCR1L_RUN1_MAX_SHIFT                (0U)
+#define TRNG_SCR1L_RUN1_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
+#define TRNG_SCR1L_RUN1_RNG_MASK                 (0x7FFF0000U)
+#define TRNG_SCR1L_RUN1_RNG_SHIFT                (16U)
+#define TRNG_SCR1L_RUN1_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
+
+/*! @name SCR2C - TRNG0 Statistical Check Run Length 2 Count Register */
+#define TRNG_SCR2C_R2_0_CT_MASK                  (0x3FFFU)
+#define TRNG_SCR2C_R2_0_CT_SHIFT                 (0U)
+#define TRNG_SCR2C_R2_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
+#define TRNG_SCR2C_R2_1_CT_MASK                  (0x3FFF0000U)
+#define TRNG_SCR2C_R2_1_CT_SHIFT                 (16U)
+#define TRNG_SCR2C_R2_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
+
+/*! @name SCR2L - TRNG0 Statistical Check Run Length 2 Limit Register */
+#define TRNG_SCR2L_RUN2_MAX_MASK                 (0x3FFFU)
+#define TRNG_SCR2L_RUN2_MAX_SHIFT                (0U)
+#define TRNG_SCR2L_RUN2_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
+#define TRNG_SCR2L_RUN2_RNG_MASK                 (0x3FFF0000U)
+#define TRNG_SCR2L_RUN2_RNG_SHIFT                (16U)
+#define TRNG_SCR2L_RUN2_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
+
+/*! @name SCR3C - TRNG0 Statistical Check Run Length 3 Count Register */
+#define TRNG_SCR3C_R3_0_CT_MASK                  (0x1FFFU)
+#define TRNG_SCR3C_R3_0_CT_SHIFT                 (0U)
+#define TRNG_SCR3C_R3_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
+#define TRNG_SCR3C_R3_1_CT_MASK                  (0x1FFF0000U)
+#define TRNG_SCR3C_R3_1_CT_SHIFT                 (16U)
+#define TRNG_SCR3C_R3_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
+
+/*! @name SCR3L - TRNG0 Statistical Check Run Length 3 Limit Register */
+#define TRNG_SCR3L_RUN3_MAX_MASK                 (0x1FFFU)
+#define TRNG_SCR3L_RUN3_MAX_SHIFT                (0U)
+#define TRNG_SCR3L_RUN3_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
+#define TRNG_SCR3L_RUN3_RNG_MASK                 (0x1FFF0000U)
+#define TRNG_SCR3L_RUN3_RNG_SHIFT                (16U)
+#define TRNG_SCR3L_RUN3_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
+
+/*! @name SCR4C - TRNG0 Statistical Check Run Length 4 Count Register */
+#define TRNG_SCR4C_R4_0_CT_MASK                  (0xFFFU)
+#define TRNG_SCR4C_R4_0_CT_SHIFT                 (0U)
+#define TRNG_SCR4C_R4_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
+#define TRNG_SCR4C_R4_1_CT_MASK                  (0xFFF0000U)
+#define TRNG_SCR4C_R4_1_CT_SHIFT                 (16U)
+#define TRNG_SCR4C_R4_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
+
+/*! @name SCR4L - TRNG0 Statistical Check Run Length 4 Limit Register */
+#define TRNG_SCR4L_RUN4_MAX_MASK                 (0xFFFU)
+#define TRNG_SCR4L_RUN4_MAX_SHIFT                (0U)
+#define TRNG_SCR4L_RUN4_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
+#define TRNG_SCR4L_RUN4_RNG_MASK                 (0xFFF0000U)
+#define TRNG_SCR4L_RUN4_RNG_SHIFT                (16U)
+#define TRNG_SCR4L_RUN4_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
+
+/*! @name SCR5C - TRNG0 Statistical Check Run Length 5 Count Register */
+#define TRNG_SCR5C_R5_0_CT_MASK                  (0x7FFU)
+#define TRNG_SCR5C_R5_0_CT_SHIFT                 (0U)
+#define TRNG_SCR5C_R5_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
+#define TRNG_SCR5C_R5_1_CT_MASK                  (0x7FF0000U)
+#define TRNG_SCR5C_R5_1_CT_SHIFT                 (16U)
+#define TRNG_SCR5C_R5_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
+
+/*! @name SCR5L - TRNG0 Statistical Check Run Length 5 Limit Register */
+#define TRNG_SCR5L_RUN5_MAX_MASK                 (0x7FFU)
+#define TRNG_SCR5L_RUN5_MAX_SHIFT                (0U)
+#define TRNG_SCR5L_RUN5_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
+#define TRNG_SCR5L_RUN5_RNG_MASK                 (0x7FF0000U)
+#define TRNG_SCR5L_RUN5_RNG_SHIFT                (16U)
+#define TRNG_SCR5L_RUN5_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
+
+/*! @name SCR6PC - TRNG0 Statistical Check Run Length 6+ Count Register */
+#define TRNG_SCR6PC_R6P_0_CT_MASK                (0x7FFU)
+#define TRNG_SCR6PC_R6P_0_CT_SHIFT               (0U)
+#define TRNG_SCR6PC_R6P_0_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
+#define TRNG_SCR6PC_R6P_1_CT_MASK                (0x7FF0000U)
+#define TRNG_SCR6PC_R6P_1_CT_SHIFT               (16U)
+#define TRNG_SCR6PC_R6P_1_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
+
+/*! @name SCR6PL - TRNG0 Statistical Check Run Length 6+ Limit Register */
+#define TRNG_SCR6PL_RUN6P_MAX_MASK               (0x7FFU)
+#define TRNG_SCR6PL_RUN6P_MAX_SHIFT              (0U)
+#define TRNG_SCR6PL_RUN6P_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
+#define TRNG_SCR6PL_RUN6P_RNG_MASK               (0x7FF0000U)
+#define TRNG_SCR6PL_RUN6P_RNG_SHIFT              (16U)
+#define TRNG_SCR6PL_RUN6P_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
+
+/*! @name STATUS - TRNG0 Status Register */
+#define TRNG_STATUS_TF1BR0_MASK                  (0x1U)
+#define TRNG_STATUS_TF1BR0_SHIFT                 (0U)
+#define TRNG_STATUS_TF1BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
+#define TRNG_STATUS_TF1BR1_MASK                  (0x2U)
+#define TRNG_STATUS_TF1BR1_SHIFT                 (1U)
+#define TRNG_STATUS_TF1BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
+#define TRNG_STATUS_TF2BR0_MASK                  (0x4U)
+#define TRNG_STATUS_TF2BR0_SHIFT                 (2U)
+#define TRNG_STATUS_TF2BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
+#define TRNG_STATUS_TF2BR1_MASK                  (0x8U)
+#define TRNG_STATUS_TF2BR1_SHIFT                 (3U)
+#define TRNG_STATUS_TF2BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
+#define TRNG_STATUS_TF3BR0_MASK                  (0x10U)
+#define TRNG_STATUS_TF3BR0_SHIFT                 (4U)
+#define TRNG_STATUS_TF3BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
+#define TRNG_STATUS_TF3BR1_MASK                  (0x20U)
+#define TRNG_STATUS_TF3BR1_SHIFT                 (5U)
+#define TRNG_STATUS_TF3BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
+#define TRNG_STATUS_TF4BR0_MASK                  (0x40U)
+#define TRNG_STATUS_TF4BR0_SHIFT                 (6U)
+#define TRNG_STATUS_TF4BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
+#define TRNG_STATUS_TF4BR1_MASK                  (0x80U)
+#define TRNG_STATUS_TF4BR1_SHIFT                 (7U)
+#define TRNG_STATUS_TF4BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
+#define TRNG_STATUS_TF5BR0_MASK                  (0x100U)
+#define TRNG_STATUS_TF5BR0_SHIFT                 (8U)
+#define TRNG_STATUS_TF5BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
+#define TRNG_STATUS_TF5BR1_MASK                  (0x200U)
+#define TRNG_STATUS_TF5BR1_SHIFT                 (9U)
+#define TRNG_STATUS_TF5BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
+#define TRNG_STATUS_TF6PBR0_MASK                 (0x400U)
+#define TRNG_STATUS_TF6PBR0_SHIFT                (10U)
+#define TRNG_STATUS_TF6PBR0(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
+#define TRNG_STATUS_TF6PBR1_MASK                 (0x800U)
+#define TRNG_STATUS_TF6PBR1_SHIFT                (11U)
+#define TRNG_STATUS_TF6PBR1(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
+#define TRNG_STATUS_TFSB_MASK                    (0x1000U)
+#define TRNG_STATUS_TFSB_SHIFT                   (12U)
+#define TRNG_STATUS_TFSB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
+#define TRNG_STATUS_TFLR_MASK                    (0x2000U)
+#define TRNG_STATUS_TFLR_SHIFT                   (13U)
+#define TRNG_STATUS_TFLR(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
+#define TRNG_STATUS_TFP_MASK                     (0x4000U)
+#define TRNG_STATUS_TFP_SHIFT                    (14U)
+#define TRNG_STATUS_TFP(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
+#define TRNG_STATUS_TFMB_MASK                    (0x8000U)
+#define TRNG_STATUS_TFMB_SHIFT                   (15U)
+#define TRNG_STATUS_TFMB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
+#define TRNG_STATUS_RETRY_CT_MASK                (0xF0000U)
+#define TRNG_STATUS_RETRY_CT_SHIFT               (16U)
+#define TRNG_STATUS_RETRY_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
+
+/*! @name ENT - RNG TRNG Entropy Read Register */
+#define TRNG_ENT_ENT_MASK                        (0xFFFFFFFFU)
+#define TRNG_ENT_ENT_SHIFT                       (0U)
+#define TRNG_ENT_ENT(x)                          (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
+
+/* The count of TRNG_ENT */
+#define TRNG_ENT_COUNT                           (16U)
+
+/*! @name PKRCNT10 - TRNG0 Statistical Check Poker Count 1 and 0 Register */
+#define TRNG_PKRCNT10_PKR_0_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT10_PKR_0_CT_SHIFT             (0U)
+#define TRNG_PKRCNT10_PKR_0_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
+#define TRNG_PKRCNT10_PKR_1_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT10_PKR_1_CT_SHIFT             (16U)
+#define TRNG_PKRCNT10_PKR_1_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
+
+/*! @name PKRCNT32 - TRNG0 Statistical Check Poker Count 3 and 2 Register */
+#define TRNG_PKRCNT32_PKR_2_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT32_PKR_2_CT_SHIFT             (0U)
+#define TRNG_PKRCNT32_PKR_2_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
+#define TRNG_PKRCNT32_PKR_3_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT32_PKR_3_CT_SHIFT             (16U)
+#define TRNG_PKRCNT32_PKR_3_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
+
+/*! @name PKRCNT54 - TRNG0 Statistical Check Poker Count 5 and 4 Register */
+#define TRNG_PKRCNT54_PKR_4_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT54_PKR_4_CT_SHIFT             (0U)
+#define TRNG_PKRCNT54_PKR_4_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
+#define TRNG_PKRCNT54_PKR_5_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT54_PKR_5_CT_SHIFT             (16U)
+#define TRNG_PKRCNT54_PKR_5_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
+
+/*! @name PKRCNT76 - TRNG0 Statistical Check Poker Count 7 and 6 Register */
+#define TRNG_PKRCNT76_PKR_6_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT76_PKR_6_CT_SHIFT             (0U)
+#define TRNG_PKRCNT76_PKR_6_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
+#define TRNG_PKRCNT76_PKR_7_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT76_PKR_7_CT_SHIFT             (16U)
+#define TRNG_PKRCNT76_PKR_7_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
+
+/*! @name PKRCNT98 - TRNG0 Statistical Check Poker Count 9 and 8 Register */
+#define TRNG_PKRCNT98_PKR_8_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT98_PKR_8_CT_SHIFT             (0U)
+#define TRNG_PKRCNT98_PKR_8_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
+#define TRNG_PKRCNT98_PKR_9_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT98_PKR_9_CT_SHIFT             (16U)
+#define TRNG_PKRCNT98_PKR_9_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
+
+/*! @name PKRCNTBA - TRNG0 Statistical Check Poker Count B and A Register */
+#define TRNG_PKRCNTBA_PKR_A_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT             (0U)
+#define TRNG_PKRCNTBA_PKR_A_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
+#define TRNG_PKRCNTBA_PKR_B_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT             (16U)
+#define TRNG_PKRCNTBA_PKR_B_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
+
+/*! @name PKRCNTDC - TRNG0 Statistical Check Poker Count D and C Register */
+#define TRNG_PKRCNTDC_PKR_C_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT             (0U)
+#define TRNG_PKRCNTDC_PKR_C_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
+#define TRNG_PKRCNTDC_PKR_D_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT             (16U)
+#define TRNG_PKRCNTDC_PKR_D_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
+
+/*! @name PKRCNTFE - TRNG0 Statistical Check Poker Count F and E Register */
+#define TRNG_PKRCNTFE_PKR_E_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT             (0U)
+#define TRNG_PKRCNTFE_PKR_E_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
+#define TRNG_PKRCNTFE_PKR_F_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT             (16U)
+#define TRNG_PKRCNTFE_PKR_F_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
+
+/*! @name SEC_CFG - TRNG0 Security Configuration Register */
+#define TRNG_SEC_CFG_SH0_MASK                    (0x1U)
+#define TRNG_SEC_CFG_SH0_SHIFT                   (0U)
+#define TRNG_SEC_CFG_SH0(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK)
+#define TRNG_SEC_CFG_NO_PRGM_MASK                (0x2U)
+#define TRNG_SEC_CFG_NO_PRGM_SHIFT               (1U)
+#define TRNG_SEC_CFG_NO_PRGM(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
+#define TRNG_SEC_CFG_SK_VAL_MASK                 (0x4U)
+#define TRNG_SEC_CFG_SK_VAL_SHIFT                (2U)
+#define TRNG_SEC_CFG_SK_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK)
+
+/*! @name INT_CTRL - TRNG0 Interrupt Control Register */
+#define TRNG_INT_CTRL_HW_ERR_MASK                (0x1U)
+#define TRNG_INT_CTRL_HW_ERR_SHIFT               (0U)
+#define TRNG_INT_CTRL_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
+#define TRNG_INT_CTRL_ENT_VAL_MASK               (0x2U)
+#define TRNG_INT_CTRL_ENT_VAL_SHIFT              (1U)
+#define TRNG_INT_CTRL_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
+#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK           (0x4U)
+#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT          (2U)
+#define TRNG_INT_CTRL_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
+#define TRNG_INT_CTRL_UNUSED_MASK                (0xFFFFFFF8U)
+#define TRNG_INT_CTRL_UNUSED_SHIFT               (3U)
+#define TRNG_INT_CTRL_UNUSED(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
+
+/*! @name INT_MASK - TRNG0 Mask Register */
+#define TRNG_INT_MASK_HW_ERR_MASK                (0x1U)
+#define TRNG_INT_MASK_HW_ERR_SHIFT               (0U)
+#define TRNG_INT_MASK_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
+#define TRNG_INT_MASK_ENT_VAL_MASK               (0x2U)
+#define TRNG_INT_MASK_ENT_VAL_SHIFT              (1U)
+#define TRNG_INT_MASK_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
+#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK           (0x4U)
+#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT          (2U)
+#define TRNG_INT_MASK_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
+
+/*! @name INT_STATUS - TRNG0 Interrupt Status Register */
+#define TRNG_INT_STATUS_HW_ERR_MASK              (0x1U)
+#define TRNG_INT_STATUS_HW_ERR_SHIFT             (0U)
+#define TRNG_INT_STATUS_HW_ERR(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
+#define TRNG_INT_STATUS_ENT_VAL_MASK             (0x2U)
+#define TRNG_INT_STATUS_ENT_VAL_SHIFT            (1U)
+#define TRNG_INT_STATUS_ENT_VAL(x)               (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
+#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK         (0x4U)
+#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT        (2U)
+#define TRNG_INT_STATUS_FRQ_CT_FAIL(x)           (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
+
+/*! @name VID1 - TRNG0 Version ID Register (MS) */
+#define TRNG_VID1_TRNG0_MIN_REV_MASK             (0xFFU)
+#define TRNG_VID1_TRNG0_MIN_REV_SHIFT            (0U)
+#define TRNG_VID1_TRNG0_MIN_REV(x)               (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_TRNG0_MIN_REV_SHIFT)) & TRNG_VID1_TRNG0_MIN_REV_MASK)
+#define TRNG_VID1_TRNG0_MAJ_REV_MASK             (0xFF00U)
+#define TRNG_VID1_TRNG0_MAJ_REV_SHIFT            (8U)
+#define TRNG_VID1_TRNG0_MAJ_REV(x)               (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_TRNG0_MAJ_REV_SHIFT)) & TRNG_VID1_TRNG0_MAJ_REV_MASK)
+#define TRNG_VID1_TRNG0_IP_ID_MASK               (0xFFFF0000U)
+#define TRNG_VID1_TRNG0_IP_ID_SHIFT              (16U)
+#define TRNG_VID1_TRNG0_IP_ID(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_TRNG0_IP_ID_SHIFT)) & TRNG_VID1_TRNG0_IP_ID_MASK)
+
+/*! @name VID2 - TRNG0 Version ID Register (LS) */
+#define TRNG_VID2_TRNG0_CONFIG_OPT_MASK          (0xFFU)
+#define TRNG_VID2_TRNG0_CONFIG_OPT_SHIFT         (0U)
+#define TRNG_VID2_TRNG0_CONFIG_OPT(x)            (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_TRNG0_CONFIG_OPT_SHIFT)) & TRNG_VID2_TRNG0_CONFIG_OPT_MASK)
+#define TRNG_VID2_TRNG0_ECO_REV_MASK             (0xFF00U)
+#define TRNG_VID2_TRNG0_ECO_REV_SHIFT            (8U)
+#define TRNG_VID2_TRNG0_ECO_REV(x)               (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_TRNG0_ECO_REV_SHIFT)) & TRNG_VID2_TRNG0_ECO_REV_MASK)
+#define TRNG_VID2_TRNG0_INTG_OPT_MASK            (0xFF0000U)
+#define TRNG_VID2_TRNG0_INTG_OPT_SHIFT           (16U)
+#define TRNG_VID2_TRNG0_INTG_OPT(x)              (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_TRNG0_INTG_OPT_SHIFT)) & TRNG_VID2_TRNG0_INTG_OPT_MASK)
+#define TRNG_VID2_TRNG0_ERA_MASK                 (0xFF000000U)
+#define TRNG_VID2_TRNG0_ERA_SHIFT                (24U)
+#define TRNG_VID2_TRNG0_ERA(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_TRNG0_ERA_SHIFT)) & TRNG_VID2_TRNG0_ERA_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group TRNG_Register_Masks */
+
+
+/* TRNG - Peripheral instance base addresses */
+/** Peripheral TRNG0 base address */
+#define TRNG0_BASE                               (0x40025000u)
+/** Peripheral TRNG0 base pointer */
+#define TRNG0                                    ((TRNG_Type *)TRNG0_BASE)
+/** Array initializer of TRNG peripheral base addresses */
+#define TRNG_BASE_ADDRS                          { TRNG0_BASE }
+/** Array initializer of TRNG peripheral base pointers */
+#define TRNG_BASE_PTRS                           { TRNG0 }
+/** Interrupt vectors for the TRNG peripheral type */
+#define TRNG_IRQS                                { TRNG0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TRNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TSI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t GENCS;                             /**< TSI General Control and Status Register, offset: 0x0 */
+  __IO uint32_t DATA;                              /**< TSI DATA Register, offset: 0x4 */
+  __IO uint32_t TSHD;                              /**< TSI Threshold Register, offset: 0x8 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TSI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/*! @name GENCS - TSI General Control and Status Register */
+#define TSI_GENCS_EOSDMEO_MASK                   (0x1U)
+#define TSI_GENCS_EOSDMEO_SHIFT                  (0U)
+#define TSI_GENCS_EOSDMEO(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
+#define TSI_GENCS_CURSW_MASK                     (0x2U)
+#define TSI_GENCS_CURSW_SHIFT                    (1U)
+#define TSI_GENCS_CURSW(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
+#define TSI_GENCS_EOSF_MASK                      (0x4U)
+#define TSI_GENCS_EOSF_SHIFT                     (2U)
+#define TSI_GENCS_EOSF(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
+#define TSI_GENCS_SCNIP_MASK                     (0x8U)
+#define TSI_GENCS_SCNIP_SHIFT                    (3U)
+#define TSI_GENCS_SCNIP(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
+#define TSI_GENCS_STM_MASK                       (0x10U)
+#define TSI_GENCS_STM_SHIFT                      (4U)
+#define TSI_GENCS_STM(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
+#define TSI_GENCS_STPE_MASK                      (0x20U)
+#define TSI_GENCS_STPE_SHIFT                     (5U)
+#define TSI_GENCS_STPE(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
+#define TSI_GENCS_TSIIEN_MASK                    (0x40U)
+#define TSI_GENCS_TSIIEN_SHIFT                   (6U)
+#define TSI_GENCS_TSIIEN(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
+#define TSI_GENCS_TSIEN_MASK                     (0x80U)
+#define TSI_GENCS_TSIEN_SHIFT                    (7U)
+#define TSI_GENCS_TSIEN(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
+#define TSI_GENCS_NSCN_MASK                      (0x1F00U)
+#define TSI_GENCS_NSCN_SHIFT                     (8U)
+#define TSI_GENCS_NSCN(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_PS_MASK                        (0xE000U)
+#define TSI_GENCS_PS_SHIFT                       (13U)
+#define TSI_GENCS_PS(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
+#define TSI_GENCS_EXTCHRG_MASK                   (0x70000U)
+#define TSI_GENCS_EXTCHRG_SHIFT                  (16U)
+#define TSI_GENCS_EXTCHRG(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_DVOLT_MASK                     (0x180000U)
+#define TSI_GENCS_DVOLT_SHIFT                    (19U)
+#define TSI_GENCS_DVOLT(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_REFCHRG_MASK                   (0xE00000U)
+#define TSI_GENCS_REFCHRG_SHIFT                  (21U)
+#define TSI_GENCS_REFCHRG(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_MODE_MASK                      (0xF000000U)
+#define TSI_GENCS_MODE_SHIFT                     (24U)
+#define TSI_GENCS_MODE(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_ESOR_MASK                      (0x10000000U)
+#define TSI_GENCS_ESOR_SHIFT                     (28U)
+#define TSI_GENCS_ESOR(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
+#define TSI_GENCS_OUTRGF_MASK                    (0x80000000U)
+#define TSI_GENCS_OUTRGF_SHIFT                   (31U)
+#define TSI_GENCS_OUTRGF(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
+
+/*! @name DATA - TSI DATA Register */
+#define TSI_DATA_TSICNT_MASK                     (0xFFFFU)
+#define TSI_DATA_TSICNT_SHIFT                    (0U)
+#define TSI_DATA_TSICNT(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_SWTS_MASK                       (0x400000U)
+#define TSI_DATA_SWTS_SHIFT                      (22U)
+#define TSI_DATA_SWTS(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
+#define TSI_DATA_DMAEN_MASK                      (0x800000U)
+#define TSI_DATA_DMAEN_SHIFT                     (23U)
+#define TSI_DATA_DMAEN(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
+#define TSI_DATA_TSICH_MASK                      (0xF0000000U)
+#define TSI_DATA_TSICH_SHIFT                     (28U)
+#define TSI_DATA_TSICH(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
+
+/*! @name TSHD - TSI Threshold Register */
+#define TSI_TSHD_THRESL_MASK                     (0xFFFFU)
+#define TSI_TSHD_THRESL_SHIFT                    (0U)
+#define TSI_TSHD_THRESL(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESH_MASK                     (0xFFFF0000U)
+#define TSI_TSHD_THRESH_SHIFT                    (16U)
+#define TSI_TSHD_THRESH(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE                                (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0                                     ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base addresses */
+#define TSI_BASE_ADDRS                           { TSI0_BASE }
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASE_PTRS                            { TSI0 }
+/** Interrupt vectors for the TSI peripheral type */
+#define TSI_IRQS                                 { TSI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[3];
+  __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status register, offset: 0x10 */
+       uint8_t RESERVED_4[3];
+  __IO uint8_t OTGICR;                             /**< OTG Interrupt Control register, offset: 0x14 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t OTGSTAT;                            /**< OTG Status register, offset: 0x18 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_7[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_8[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_11[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_14[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_16[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_17[3];
+  __IO uint8_t TOKEN;                              /**< Token register, offset: 0xA8 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t SOFTHLD;                            /**< SOF Threshold register, offset: 0xAC */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_20[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_21[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_22[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_25[7];
+  __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
+       uint8_t RESERVED_26[15];
+  __IO uint8_t KEEP_ALIVE_CTRL;                    /**< Keep Alive mode control, offset: 0x124 */
+       uint8_t RESERVED_27[3];
+  __IO uint8_t KEEP_ALIVE_WKCTRL;                  /**< Keep Alive mode wakeup control, offset: 0x128 */
+       uint8_t RESERVED_28[3];
+  __IO uint8_t MISCCTRL;                           /**< Miscellaneous Control register, offset: 0x12C */
+       uint8_t RESERVED_29[3];
+  __IO uint8_t STALL_IL_DIS;                       /**< Peripheral mode stall disable for endpoints 7 to 0 in IN direction, offset: 0x130 */
+       uint8_t RESERVED_30[3];
+  __IO uint8_t STALL_IH_DIS;                       /**< Peripheral mode stall disable for endpoints 15 to 8 in IN direction, offset: 0x134 */
+       uint8_t RESERVED_31[3];
+  __IO uint8_t STALL_OL_DIS;                       /**< Peripheral mode stall disable for endpoints 7 to 0 in OUT direction, offset: 0x138 */
+       uint8_t RESERVED_32[3];
+  __IO uint8_t STALL_OH_DIS;                       /**< Peripheral mode stall disable for endpoints 15 to 8 in OUT direction, offset: 0x13C */
+       uint8_t RESERVED_33[3];
+  __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
+       uint8_t RESERVED_34[3];
+  __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48M oscillator enable register, offset: 0x144 */
+       uint8_t RESERVED_35[15];
+  __IO uint8_t CLK_RECOVER_INT_EN;                 /**< Clock recovery combined interrupt enable, offset: 0x154 */
+       uint8_t RESERVED_36[7];
+  __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name PERID - Peripheral ID register */
+#define USB_PERID_ID_MASK                        (0x3FU)
+#define USB_PERID_ID_SHIFT                       (0U)
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+#define USB_IDCOMP_NID_MASK                      (0x3FU)
+#define USB_IDCOMP_NID_SHIFT                     (0U)
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+
+/*! @name REV - Peripheral Revision register */
+#define USB_REV_REV_MASK                         (0xFFU)
+#define USB_REV_REV_SHIFT                        (0U)
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+#define USB_ADDINFO_IEHOST_MASK                  (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT                 (0U)
+#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+
+/*! @name OTGISTAT - OTG Interrupt Status register */
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK         (0x20U)
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        (5U)
+#define USB_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK                (0x40U)
+#define USB_OTGISTAT_ONEMSEC_SHIFT               (6U)
+#define USB_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
+
+/*! @name OTGICR - OTG Interrupt Control register */
+#define USB_OTGICR_LINESTATEEN_MASK              (0x20U)
+#define USB_OTGICR_LINESTATEEN_SHIFT             (5U)
+#define USB_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK                (0x40U)
+#define USB_OTGICR_ONEMSECEN_SHIFT               (6U)
+#define USB_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
+
+/*! @name OTGSTAT - OTG Status register */
+#define USB_OTGSTAT_LINESTATESTABLE_MASK         (0x20U)
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        (5U)
+#define USB_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK               (0x40U)
+#define USB_OTGSTAT_ONEMSECEN_SHIFT              (6U)
+#define USB_OTGSTAT_ONEMSECEN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
+
+/*! @name OTGCTL - OTG Control register */
+#define USB_OTGCTL_OTGEN_MASK                    (0x4U)
+#define USB_OTGCTL_OTGEN_SHIFT                   (2U)
+#define USB_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK                    (0x10U)
+#define USB_OTGCTL_DMLOW_SHIFT                   (4U)
+#define USB_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK                    (0x20U)
+#define USB_OTGCTL_DPLOW_SHIFT                   (5U)
+#define USB_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK                   (0x80U)
+#define USB_OTGCTL_DPHIGH_SHIFT                  (7U)
+#define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
+
+/*! @name ISTAT - Interrupt Status register */
+#define USB_ISTAT_USBRST_MASK                    (0x1U)
+#define USB_ISTAT_USBRST_SHIFT                   (0U)
+#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK                     (0x2U)
+#define USB_ISTAT_ERROR_SHIFT                    (1U)
+#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK                    (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT                   (2U)
+#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK                    (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT                   (3U)
+#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK                     (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT                    (4U)
+#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK                    (0x20U)
+#define USB_ISTAT_RESUME_SHIFT                   (5U)
+#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK                    (0x40U)
+#define USB_ISTAT_ATTACH_SHIFT                   (6U)
+#define USB_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK                     (0x80U)
+#define USB_ISTAT_STALL_SHIFT                    (7U)
+#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+
+/*! @name INTEN - Interrupt Enable register */
+#define USB_INTEN_USBRSTEN_MASK                  (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT                 (0U)
+#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK                   (0x2U)
+#define USB_INTEN_ERROREN_SHIFT                  (1U)
+#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK                  (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT                 (2U)
+#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK                  (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT                 (3U)
+#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK                   (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT                  (4U)
+#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK                  (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT                 (5U)
+#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK                  (0x40U)
+#define USB_INTEN_ATTACHEN_SHIFT                 (6U)
+#define USB_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK                   (0x80U)
+#define USB_INTEN_STALLEN_SHIFT                  (7U)
+#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+#define USB_ERRSTAT_PIDERR_MASK                  (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT                 (0U)
+#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK                 (0x2U)
+#define USB_ERRSTAT_CRC5EOF_SHIFT                (1U)
+#define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK                   (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT                  (2U)
+#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK                    (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT                   (3U)
+#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK                  (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT                 (4U)
+#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK                  (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT                 (5U)
+#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_OWNERR_MASK                  (0x40U)
+#define USB_ERRSTAT_OWNERR_SHIFT                 (6U)
+#define USB_ERRSTAT_OWNERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK                  (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT                 (7U)
+#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+
+/*! @name ERREN - Error Interrupt Enable register */
+#define USB_ERREN_PIDERREN_MASK                  (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT                 (0U)
+#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK                 (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT                (1U)
+#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK                   (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT                  (2U)
+#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK                    (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT                   (3U)
+#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK                  (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT                 (4U)
+#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK                  (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT                 (5U)
+#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_OWNERREN_MASK                  (0x40U)
+#define USB_ERREN_OWNERREN_SHIFT                 (6U)
+#define USB_ERREN_OWNERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK                  (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT                 (7U)
+#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+
+/*! @name STAT - Status register */
+#define USB_STAT_ODD_MASK                        (0x4U)
+#define USB_STAT_ODD_SHIFT                       (2U)
+#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK                         (0x8U)
+#define USB_STAT_TX_SHIFT                        (3U)
+#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK                       (0xF0U)
+#define USB_STAT_ENDP_SHIFT                      (4U)
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+
+/*! @name CTL - Control register */
+#define USB_CTL_USBENSOFEN_MASK                  (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT                 (0U)
+#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK                      (0x2U)
+#define USB_CTL_ODDRST_SHIFT                     (1U)
+#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK                      (0x4U)
+#define USB_CTL_RESUME_SHIFT                     (2U)
+#define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK                  (0x8U)
+#define USB_CTL_HOSTMODEEN_SHIFT                 (3U)
+#define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK                       (0x10U)
+#define USB_CTL_RESET_SHIFT                      (4U)
+#define USB_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK                         (0x40U)
+#define USB_CTL_SE0_SHIFT                        (6U)
+#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK                      (0x80U)
+#define USB_CTL_JSTATE_SHIFT                     (7U)
+#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+
+/*! @name ADDR - Address register */
+#define USB_ADDR_ADDR_MASK                       (0x7FU)
+#define USB_ADDR_ADDR_SHIFT                      (0U)
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK                       (0x80U)
+#define USB_ADDR_LSEN_SHIFT                      (7U)
+#define USB_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+#define USB_BDTPAGE1_BDTBA_MASK                  (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT                 (1U)
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+
+/*! @name FRMNUML - Frame Number register Low */
+#define USB_FRMNUML_FRM_MASK                     (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT                    (0U)
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+
+/*! @name FRMNUMH - Frame Number register High */
+#define USB_FRMNUMH_FRM_MASK                     (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT                    (0U)
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+
+/*! @name TOKEN - Token register */
+#define USB_TOKEN_TOKENENDPT_MASK                (0xFU)
+#define USB_TOKEN_TOKENENDPT_SHIFT               (0U)
+#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK                  (0xF0U)
+#define USB_TOKEN_TOKENPID_SHIFT                 (4U)
+#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
+
+/*! @name SOFTHLD - SOF Threshold register */
+#define USB_SOFTHLD_CNT_MASK                     (0xFFU)
+#define USB_SOFTHLD_CNT_SHIFT                    (0U)
+#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+#define USB_BDTPAGE2_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+#define USB_BDTPAGE3_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+
+/*! @name ENDPT - Endpoint Control register */
+#define USB_ENDPT_EPHSHK_MASK                    (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT                   (0U)
+#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK                   (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT                  (1U)
+#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK                    (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT                   (2U)
+#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK                    (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT                   (3U)
+#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK                  (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT                 (4U)
+#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK                  (0x40U)
+#define USB_ENDPT_RETRYDIS_SHIFT                 (6U)
+#define USB_ENDPT_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK                 (0x80U)
+#define USB_ENDPT_HOSTWOHUB_SHIFT                (7U)
+#define USB_ENDPT_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT                          (16U)
+
+/*! @name USBCTRL - USB Control register */
+#define USB_USBCTRL_UARTSEL_MASK                 (0x10U)
+#define USB_USBCTRL_UARTSEL_SHIFT                (4U)
+#define USB_USBCTRL_UARTSEL(x)                   (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK)
+#define USB_USBCTRL_UARTCHLS_MASK                (0x20U)
+#define USB_USBCTRL_UARTCHLS_SHIFT               (5U)
+#define USB_USBCTRL_UARTCHLS(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK)
+#define USB_USBCTRL_PDE_MASK                     (0x40U)
+#define USB_USBCTRL_PDE_SHIFT                    (6U)
+#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK                    (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT                   (7U)
+#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+
+/*! @name OBSERVE - USB OTG Observe register */
+#define USB_OBSERVE_DMPD_MASK                    (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT                   (4U)
+#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK                    (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT                   (6U)
+#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK                    (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT                   (7U)
+#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+
+/*! @name CONTROL - USB OTG Control register */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         (4U)
+#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         (0U)
+#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK                (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT               (1U)
+#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    (0x4U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   (2U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_VREDG_DET_MASK               (0x8U)
+#define USB_USBTRC0_VREDG_DET_SHIFT              (3U)
+#define USB_USBTRC0_VREDG_DET(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK)
+#define USB_USBTRC0_VFEDG_DET_MASK               (0x10U)
+#define USB_USBTRC0_VFEDG_DET_SHIFT              (4U)
+#define USB_USBTRC0_VFEDG_DET(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK               (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT              (5U)
+#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK                (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT               (7U)
+#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+#define USB_USBFRMADJUST_ADJ_MASK                (0xFFU)
+#define USB_USBFRMADJUST_ADJ_SHIFT               (0U)
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
+
+/*! @name KEEP_ALIVE_CTRL - Keep Alive mode control */
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK   (0x1U)
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT  (0U)
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x)     (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK   (0x2U)
+#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT  (1U)
+#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x)     (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK     (0x8U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT    (3U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN(x)       (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK     (0x10U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT    (4U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x)       (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK    (0x80U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT   (7U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x)      (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK)
+
+/*! @name KEEP_ALIVE_WKCTRL - Keep Alive mode wakeup control */
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK  (0xFU)
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U)
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x)    (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK)
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK    (0xF0U)
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT   (4U)
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x)      (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK)
+
+/*! @name MISCCTRL - Miscellaneous Control register */
+#define USB_MISCCTRL_SOFDYNTHLD_MASK             (0x1U)
+#define USB_MISCCTRL_SOFDYNTHLD_SHIFT            (0U)
+#define USB_MISCCTRL_SOFDYNTHLD(x)               (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK)
+#define USB_MISCCTRL_SOFBUSSET_MASK              (0x2U)
+#define USB_MISCCTRL_SOFBUSSET_SHIFT             (1U)
+#define USB_MISCCTRL_SOFBUSSET(x)                (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK)
+#define USB_MISCCTRL_OWNERRISODIS_MASK           (0x4U)
+#define USB_MISCCTRL_OWNERRISODIS_SHIFT          (2U)
+#define USB_MISCCTRL_OWNERRISODIS(x)             (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK)
+#define USB_MISCCTRL_VREDG_EN_MASK               (0x8U)
+#define USB_MISCCTRL_VREDG_EN_SHIFT              (3U)
+#define USB_MISCCTRL_VREDG_EN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK)
+#define USB_MISCCTRL_VFEDG_EN_MASK               (0x10U)
+#define USB_MISCCTRL_VFEDG_EN_SHIFT              (4U)
+#define USB_MISCCTRL_VFEDG_EN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK)
+#define USB_MISCCTRL_STL_ADJ_EN_MASK             (0x80U)
+#define USB_MISCCTRL_STL_ADJ_EN_SHIFT            (7U)
+#define USB_MISCCTRL_STL_ADJ_EN(x)               (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK)
+
+/*! @name STALL_IL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in IN direction */
+#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK       (0x1U)
+#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT      (0U)
+#define USB_STALL_IL_DIS_STALL_I_DIS0(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK       (0x2U)
+#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT      (1U)
+#define USB_STALL_IL_DIS_STALL_I_DIS1(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK       (0x4U)
+#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT      (2U)
+#define USB_STALL_IL_DIS_STALL_I_DIS2(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK       (0x8U)
+#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT      (3U)
+#define USB_STALL_IL_DIS_STALL_I_DIS3(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK       (0x10U)
+#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT      (4U)
+#define USB_STALL_IL_DIS_STALL_I_DIS4(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK       (0x20U)
+#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT      (5U)
+#define USB_STALL_IL_DIS_STALL_I_DIS5(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK       (0x40U)
+#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT      (6U)
+#define USB_STALL_IL_DIS_STALL_I_DIS6(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK       (0x80U)
+#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT      (7U)
+#define USB_STALL_IL_DIS_STALL_I_DIS7(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK)
+
+/*! @name STALL_IH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in IN direction */
+#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK       (0x1U)
+#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT      (0U)
+#define USB_STALL_IH_DIS_STALL_I_DIS8(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK       (0x2U)
+#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT      (1U)
+#define USB_STALL_IH_DIS_STALL_I_DIS9(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK      (0x4U)
+#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT     (2U)
+#define USB_STALL_IH_DIS_STALL_I_DIS10(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK      (0x8U)
+#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT     (3U)
+#define USB_STALL_IH_DIS_STALL_I_DIS11(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK      (0x10U)
+#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT     (4U)
+#define USB_STALL_IH_DIS_STALL_I_DIS12(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK      (0x20U)
+#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT     (5U)
+#define USB_STALL_IH_DIS_STALL_I_DIS13(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK      (0x40U)
+#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT     (6U)
+#define USB_STALL_IH_DIS_STALL_I_DIS14(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK      (0x80U)
+#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT     (7U)
+#define USB_STALL_IH_DIS_STALL_I_DIS15(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK)
+
+/*! @name STALL_OL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in OUT direction */
+#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK       (0x1U)
+#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT      (0U)
+#define USB_STALL_OL_DIS_STALL_O_DIS0(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK       (0x2U)
+#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT      (1U)
+#define USB_STALL_OL_DIS_STALL_O_DIS1(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK       (0x4U)
+#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT      (2U)
+#define USB_STALL_OL_DIS_STALL_O_DIS2(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK       (0x8U)
+#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT      (3U)
+#define USB_STALL_OL_DIS_STALL_O_DIS3(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK       (0x10U)
+#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT      (4U)
+#define USB_STALL_OL_DIS_STALL_O_DIS4(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK       (0x20U)
+#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT      (5U)
+#define USB_STALL_OL_DIS_STALL_O_DIS5(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK       (0x40U)
+#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT      (6U)
+#define USB_STALL_OL_DIS_STALL_O_DIS6(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK       (0x80U)
+#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT      (7U)
+#define USB_STALL_OL_DIS_STALL_O_DIS7(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK)
+
+/*! @name STALL_OH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in OUT direction */
+#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK       (0x1U)
+#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT      (0U)
+#define USB_STALL_OH_DIS_STALL_O_DIS8(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK       (0x2U)
+#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT      (1U)
+#define USB_STALL_OH_DIS_STALL_O_DIS9(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK      (0x4U)
+#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT     (2U)
+#define USB_STALL_OH_DIS_STALL_O_DIS10(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK      (0x8U)
+#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT     (3U)
+#define USB_STALL_OH_DIS_STALL_O_DIS11(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK      (0x10U)
+#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT     (4U)
+#define USB_STALL_OH_DIS_STALL_O_DIS12(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK      (0x20U)
+#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT     (5U)
+#define USB_STALL_OH_DIS_STALL_O_DIS13(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK      (0x40U)
+#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT     (6U)
+#define USB_STALL_OH_DIS_STALL_O_DIS14(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK      (0x80U)
+#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT     (7U)
+#define USB_STALL_OH_DIS_STALL_O_DIS15(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK)
+
+/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+
+/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK       (0x1U)
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT      (0U)
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x)         (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       (0x2U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      (1U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+
+/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x)   (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
+
+/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type;
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/*! @name TRM - VREF Trim Register */
+#define VREF_TRM_TRIM_MASK                       (0x3FU)
+#define VREF_TRM_TRIM_SHIFT                      (0U)
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK                     (0x40U)
+#define VREF_TRM_CHOPEN_SHIFT                    (6U)
+#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
+
+/*! @name SC - VREF Status and Control Register */
+#define VREF_SC_MODE_LV_MASK                     (0x3U)
+#define VREF_SC_MODE_LV_SHIFT                    (0U)
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      (0x4U)
+#define VREF_SC_VREFST_SHIFT                     (2U)
+#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK                     (0x20U)
+#define VREF_SC_ICOMPEN_SHIFT                    (5U)
+#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK                       (0x40U)
+#define VREF_SC_REGEN_SHIFT                      (6U)
+#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK                      (0x80U)
+#define VREF_SC_VREFEN_SHIFT                     (7U)
+#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS                          { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS                           { VREF }
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint16_t STCTRLH;                           /**< Watchdog Status and Control Register High, offset: 0x0 */
+  __IO uint16_t STCTRLL;                           /**< Watchdog Status and Control Register Low, offset: 0x2 */
+  __IO uint16_t TOVALH;                            /**< Watchdog Time-out Value Register High, offset: 0x4 */
+  __IO uint16_t TOVALL;                            /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+  __IO uint16_t WINH;                              /**< Watchdog Window Register High, offset: 0x8 */
+  __IO uint16_t WINL;                              /**< Watchdog Window Register Low, offset: 0xA */
+  __IO uint16_t REFRESH;                           /**< Watchdog Refresh register, offset: 0xC */
+  __IO uint16_t UNLOCK;                            /**< Watchdog Unlock register, offset: 0xE */
+  __IO uint16_t TMROUTH;                           /**< Watchdog Timer Output Register High, offset: 0x10 */
+  __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
+  __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
+  __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/*! @name STCTRLH - Watchdog Status and Control Register High */
+#define WDOG_STCTRLH_WDOGEN_MASK                 (0x1U)
+#define WDOG_STCTRLH_WDOGEN_SHIFT                (0U)
+#define WDOG_STCTRLH_WDOGEN(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_CLKSRC_MASK                 (0x2U)
+#define WDOG_STCTRLH_CLKSRC_SHIFT                (1U)
+#define WDOG_STCTRLH_CLKSRC(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK               (0x4U)
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT              (2U)
+#define WDOG_STCTRLH_IRQRSTEN(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK                  (0x8U)
+#define WDOG_STCTRLH_WINEN_SHIFT                 (3U)
+#define WDOG_STCTRLH_WINEN(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK            (0x10U)
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           (4U)
+#define WDOG_STCTRLH_ALLOWUPDATE(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK                  (0x20U)
+#define WDOG_STCTRLH_DBGEN_SHIFT                 (5U)
+#define WDOG_STCTRLH_DBGEN(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK                 (0x40U)
+#define WDOG_STCTRLH_STOPEN_SHIFT                (6U)
+#define WDOG_STCTRLH_STOPEN(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK                 (0x80U)
+#define WDOG_STCTRLH_WAITEN_SHIFT                (7U)
+#define WDOG_STCTRLH_WAITEN(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK               (0x400U)
+#define WDOG_STCTRLH_TESTWDOG_SHIFT              (10U)
+#define WDOG_STCTRLH_TESTWDOG(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK                (0x800U)
+#define WDOG_STCTRLH_TESTSEL_SHIFT               (11U)
+#define WDOG_STCTRLH_TESTSEL(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK                (0x3000U)
+#define WDOG_STCTRLH_BYTESEL_SHIFT               (12U)
+#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK            (0x4000U)
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT           (14U)
+#define WDOG_STCTRLH_DISTESTWDOG(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
+
+/*! @name STCTRLL - Watchdog Status and Control Register Low */
+#define WDOG_STCTRLL_INTFLG_MASK                 (0x8000U)
+#define WDOG_STCTRLL_INTFLG_SHIFT                (15U)
+#define WDOG_STCTRLL_INTFLG(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
+
+/*! @name TOVALH - Watchdog Time-out Value Register High */
+#define WDOG_TOVALH_TOVALHIGH_MASK               (0xFFFFU)
+#define WDOG_TOVALH_TOVALHIGH_SHIFT              (0U)
+#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
+
+/*! @name TOVALL - Watchdog Time-out Value Register Low */
+#define WDOG_TOVALL_TOVALLOW_MASK                (0xFFFFU)
+#define WDOG_TOVALL_TOVALLOW_SHIFT               (0U)
+#define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
+
+/*! @name WINH - Watchdog Window Register High */
+#define WDOG_WINH_WINHIGH_MASK                   (0xFFFFU)
+#define WDOG_WINH_WINHIGH_SHIFT                  (0U)
+#define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
+
+/*! @name WINL - Watchdog Window Register Low */
+#define WDOG_WINL_WINLOW_MASK                    (0xFFFFU)
+#define WDOG_WINL_WINLOW_SHIFT                   (0U)
+#define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
+
+/*! @name REFRESH - Watchdog Refresh register */
+#define WDOG_REFRESH_WDOGREFRESH_MASK            (0xFFFFU)
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT           (0U)
+#define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
+
+/*! @name UNLOCK - Watchdog Unlock register */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK              (0xFFFFU)
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             (0U)
+#define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
+
+/*! @name TMROUTH - Watchdog Timer Output Register High */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK           (0xFFFFU)
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          (0U)
+#define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+
+/*! @name TMROUTL - Watchdog Timer Output Register Low */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK            (0xFFFFU)
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           (0U)
+#define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
+
+/*! @name RSTCNT - Watchdog Reset Count register */
+#define WDOG_RSTCNT_RSTCNT_MASK                  (0xFFFFU)
+#define WDOG_RSTCNT_RSTCNT_SHIFT                 (0U)
+#define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
+
+/*! @name PRESC - Watchdog Prescaler register */
+#define WDOG_PRESC_PRESCVAL_MASK                 (0x700U)
+#define WDOG_PRESC_PRESCVAL_SHIFT                (8U)
+#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE                                (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS                          { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS                           { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS                                { WDOG_EWM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+#define DSPI0                                    SPI0
+#define DSPI1                                    SPI1
+#define DMAMUX0                                  DMAMUX
+#define DMA0_04_IRQn                             DMA0_DMA4_IRQn
+#define DMA0_15_IRQn                             DMA1_DMA5_IRQn
+#define DMA0_26_IRQn                             DMA2_DMA6_IRQn
+#define DMA0_37_IRQn                             DMA3_DMA7_IRQn
+#define DMA0_04_DriverIRQHandler                 DMA0_DMA4_DriverIRQHandler
+#define DMA0_15_DriverIRQHandler                 DMA1_DMA5_DriverIRQHandler
+#define DMA0_26_DriverIRQHandler                 DMA2_DMA6_DriverIRQHandler
+#define DMA0_37_DriverIRQHandler                 DMA3_DMA7_DriverIRQHandler
+#define PIT                                      PIT0
+#define RTC_IRQn                                 RTC_Alarm_IRQn
+#define RTC_IRQHandler                           RTC_Alarm_IRQHandler
+#define kDmaRequestMux0Group1LTC0InputFIFO       kDmaRequestMux0LTC0InputFIFO
+#define kDmaRequestMux0Group1LTC0OutputFIFO      kDmaRequestMux0LTC0OutputFIFO
+#define kDmaRequestMux0Group1LTC0PKHA            kDmaRequestMux0LTC0PKHA
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif  /* _MKL82Z7_H_ */
+
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/MKL82Z7_features.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/MKL82Z7_features.h
new file mode 100644
index 00000000000..e3f7271353f
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/MKL82Z7_features.h
@@ -0,0 +1,2166 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.6, 2015-12-15
+**     Build:               b160415
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-20)
+**         Initial version.
+**     - rev. 1.1 (2015-04-24)
+**         Add feature for QSPI
+**     - rev. 1.2 (2015-07-29)
+**         Add features for LTC and USB KHCI
+**     - rev. 1.3 (2015-08-10)
+**         Add features for INTMUX and align with 1.3 REL stream
+**     - rev. 1.4 (2015-08-13)
+**         Add new SIM feature FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER for ADC
+**     - rev. 1.5 (2015-08-20)
+**         Update according to latest RM Rev.1 and RDP
+**     - rev. 1.6 (2015-12-15)
+**         Correct USB RAM
+**
+** ###################################################################
+*/
+
+#ifndef _MKL82Z7_FEATURES_H_
+#define _MKL82Z7_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ACMP availability on the SoC. */
+#define FSL_FEATURE_SOC_ACMP_COUNT (0)
+/* @brief ADC16 availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC16_COUNT (1)
+/* @brief ADC12 availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC12_COUNT (0)
+/* @brief AFE availability on the SoC. */
+#define FSL_FEATURE_SOC_AFE_COUNT (0)
+/* @brief AIPS availability on the SoC. */
+#define FSL_FEATURE_SOC_AIPS_COUNT (1)
+/* @brief AOI availability on the SoC. */
+#define FSL_FEATURE_SOC_AOI_COUNT (0)
+/* @brief AXBS availability on the SoC. */
+#define FSL_FEATURE_SOC_AXBS_COUNT (0)
+/* @brief ASMC availability on the SoC. */
+#define FSL_FEATURE_SOC_ASMC_COUNT (0)
+/* @brief CADC availability on the SoC. */
+#define FSL_FEATURE_SOC_CADC_COUNT (0)
+/* @brief FLEXCAN availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0)
+/* @brief MMCAU availability on the SoC. */
+#define FSL_FEATURE_SOC_MMCAU_COUNT (0)
+/* @brief CMP availability on the SoC. */
+#define FSL_FEATURE_SOC_CMP_COUNT (1)
+/* @brief CMT availability on the SoC. */
+#define FSL_FEATURE_SOC_CMT_COUNT (0)
+/* @brief CNC availability on the SoC. */
+#define FSL_FEATURE_SOC_CNC_COUNT (0)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief DAC availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC_COUNT (1)
+/* @brief DAC32 availability on the SoC. */
+#define FSL_FEATURE_SOC_DAC32_COUNT (0)
+/* @brief DCDC availability on the SoC. */
+#define FSL_FEATURE_SOC_DCDC_COUNT (0)
+/* @brief DDR availability on the SoC. */
+#define FSL_FEATURE_SOC_DDR_COUNT (0)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (0)
+/* @brief EDMA availability on the SoC. */
+#define FSL_FEATURE_SOC_EDMA_COUNT (1)
+/* @brief DMAMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+/* @brief DRY availability on the SoC. */
+#define FSL_FEATURE_SOC_DRY_COUNT (0)
+/* @brief DSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_DSPI_COUNT (2)
+/* @brief EMVSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_EMVSIM_COUNT (2)
+/* @brief ENC availability on the SoC. */
+#define FSL_FEATURE_SOC_ENC_COUNT (0)
+/* @brief ENET availability on the SoC. */
+#define FSL_FEATURE_SOC_ENET_COUNT (0)
+/* @brief EWM availability on the SoC. */
+#define FSL_FEATURE_SOC_EWM_COUNT (1)
+/* @brief FB availability on the SoC. */
+#define FSL_FEATURE_SOC_FB_COUNT (0)
+/* @brief FGPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FGPIO_COUNT (5)
+/* @brief FLEXIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXIO_COUNT (1)
+/* @brief FMC availability on the SoC. */
+#define FSL_FEATURE_SOC_FMC_COUNT (1)
+/* @brief FSKDT availability on the SoC. */
+#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+/* @brief FTFA availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFA_COUNT (1)
+/* @brief FTFE availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFE_COUNT (0)
+/* @brief FTFL availability on the SoC. */
+#define FSL_FEATURE_SOC_FTFL_COUNT (0)
+/* @brief FTM availability on the SoC. */
+#define FSL_FEATURE_SOC_FTM_COUNT (0)
+/* @brief FTMRA availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+/* @brief FTMRE availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+/* @brief FTMRH availability on the SoC. */
+#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (5)
+/* @brief HSADC availability on the SoC. */
+#define FSL_FEATURE_SOC_HSADC_COUNT (0)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (2)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (0)
+/* @brief ICS availability on the SoC. */
+#define FSL_FEATURE_SOC_ICS_COUNT (0)
+/* @brief INTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INTMUX_COUNT (1)
+/* @brief IRQ availability on the SoC. */
+#define FSL_FEATURE_SOC_IRQ_COUNT (0)
+/* @brief KBI availability on the SoC. */
+#define FSL_FEATURE_SOC_KBI_COUNT (0)
+/* @brief SLCD availability on the SoC. */
+#define FSL_FEATURE_SOC_SLCD_COUNT (0)
+/* @brief LCDC availability on the SoC. */
+#define FSL_FEATURE_SOC_LCDC_COUNT (0)
+/* @brief LDO availability on the SoC. */
+#define FSL_FEATURE_SOC_LDO_COUNT (0)
+/* @brief LLWU availability on the SoC. */
+#define FSL_FEATURE_SOC_LLWU_COUNT (1)
+/* @brief LMEM availability on the SoC. */
+#define FSL_FEATURE_SOC_LMEM_COUNT (0)
+/* @brief LPI2C availability on the SoC. */
+#define FSL_FEATURE_SOC_LPI2C_COUNT (0)
+/* @brief LPIT availability on the SoC. */
+#define FSL_FEATURE_SOC_LPIT_COUNT (0)
+/* @brief LPSCI availability on the SoC. */
+#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+/* @brief LPSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_LPSPI_COUNT (0)
+/* @brief LPTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTMR_COUNT (2)
+/* @brief LPTPM availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+/* @brief LPUART availability on the SoC. */
+#define FSL_FEATURE_SOC_LPUART_COUNT (3)
+/* @brief LTC availability on the SoC. */
+#define FSL_FEATURE_SOC_LTC_COUNT (1)
+/* @brief MC availability on the SoC. */
+#define FSL_FEATURE_SOC_MC_COUNT (0)
+/* @brief MCG availability on the SoC. */
+#define FSL_FEATURE_SOC_MCG_COUNT (1)
+/* @brief MCGLITE availability on the SoC. */
+#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+/* @brief MCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MCM_COUNT (1)
+/* @brief MMAU availability on the SoC. */
+#define FSL_FEATURE_SOC_MMAU_COUNT (0)
+/* @brief MMDVSQ availability on the SoC. */
+#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+/* @brief MPU availability on the SoC. */
+#define FSL_FEATURE_SOC_MPU_COUNT (1)
+/* @brief MSCAN availability on the SoC. */
+#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+/* @brief MSCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MSCM_COUNT (0)
+/* @brief MTB availability on the SoC. */
+#define FSL_FEATURE_SOC_MTB_COUNT (1)
+/* @brief MTBDWT availability on the SoC. */
+#define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
+/* @brief MU availability on the SoC. */
+#define FSL_FEATURE_SOC_MU_COUNT (0)
+/* @brief NFC availability on the SoC. */
+#define FSL_FEATURE_SOC_NFC_COUNT (0)
+/* @brief OPAMP availability on the SoC. */
+#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+/* @brief OSC availability on the SoC. */
+#define FSL_FEATURE_SOC_OSC_COUNT (1)
+/* @brief OSC32 availability on the SoC. */
+#define FSL_FEATURE_SOC_OSC32_COUNT (0)
+/* @brief OTFAD availability on the SoC. */
+#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+/* @brief PDB availability on the SoC. */
+#define FSL_FEATURE_SOC_PDB_COUNT (0)
+/* @brief PCC availability on the SoC. */
+#define FSL_FEATURE_SOC_PCC_COUNT (0)
+/* @brief PGA availability on the SoC. */
+#define FSL_FEATURE_SOC_PGA_COUNT (0)
+/* @brief PIT availability on the SoC. */
+#define FSL_FEATURE_SOC_PIT_COUNT (1)
+/* @brief PMC availability on the SoC. */
+#define FSL_FEATURE_SOC_PMC_COUNT (1)
+/* @brief PORT availability on the SoC. */
+#define FSL_FEATURE_SOC_PORT_COUNT (5)
+/* @brief PWM availability on the SoC. */
+#define FSL_FEATURE_SOC_PWM_COUNT (0)
+/* @brief PWT availability on the SoC. */
+#define FSL_FEATURE_SOC_PWT_COUNT (0)
+/* @brief QuadSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_QuadSPI_COUNT (1)
+/* @brief RCM availability on the SoC. */
+#define FSL_FEATURE_SOC_RCM_COUNT (1)
+/* @brief RFSYS availability on the SoC. */
+#define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+/* @brief RFVBAT availability on the SoC. */
+#define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
+/* @brief RNG availability on the SoC. */
+#define FSL_FEATURE_SOC_RNG_COUNT (0)
+/* @brief RNGB availability on the SoC. */
+#define FSL_FEATURE_SOC_RNGB_COUNT (0)
+/* @brief ROM availability on the SoC. */
+#define FSL_FEATURE_SOC_ROM_COUNT (1)
+/* @brief RSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_RSIM_COUNT (0)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCG availability on the SoC. */
+#define FSL_FEATURE_SOC_SCG_COUNT (0)
+/* @brief SCI availability on the SoC. */
+#define FSL_FEATURE_SOC_SCI_COUNT (0)
+/* @brief SDHC availability on the SoC. */
+#define FSL_FEATURE_SOC_SDHC_COUNT (0)
+/* @brief SDRAM availability on the SoC. */
+#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+/* @brief SEMA42 availability on the SoC. */
+#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
+/* @brief SIM availability on the SoC. */
+#define FSL_FEATURE_SOC_SIM_COUNT (1)
+/* @brief SMC availability on the SoC. */
+#define FSL_FEATURE_SOC_SMC_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (0)
+/* @brief TMR availability on the SoC. */
+#define FSL_FEATURE_SOC_TMR_COUNT (0)
+/* @brief TPM availability on the SoC. */
+#define FSL_FEATURE_SOC_TPM_COUNT (3)
+/* @brief TRGMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
+/* @brief TRIAMP availability on the SoC. */
+#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+/* @brief TRNG availability on the SoC. */
+#define FSL_FEATURE_SOC_TRNG_COUNT (1)
+/* @brief TSI availability on the SoC. */
+#define FSL_FEATURE_SOC_TSI_COUNT (1)
+/* @brief TSTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
+/* @brief UART availability on the SoC. */
+#define FSL_FEATURE_SOC_UART_COUNT (0)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief USBDCD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
+/* @brief USBHSDCD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+/* @brief USBPHY availability on the SoC. */
+#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+/* @brief VREF availability on the SoC. */
+#define FSL_FEATURE_SOC_VREF_COUNT (1)
+/* @brief WDOG availability on the SoC. */
+#define FSL_FEATURE_SOC_WDOG_COUNT (1)
+/* @brief XBAR availability on the SoC. */
+#define FSL_FEATURE_SOC_XBAR_COUNT (0)
+/* @brief XBARA availability on the SoC. */
+#define FSL_FEATURE_SOC_XBARA_COUNT (0)
+/* @brief XBARB availability on the SoC. */
+#define FSL_FEATURE_SOC_XBARB_COUNT (0)
+/* @brief XCVR availability on the SoC. */
+#define FSL_FEATURE_SOC_XCVR_COUNT (0)
+/* @brief XRDC availability on the SoC. */
+#define FSL_FEATURE_SOC_XRDC_COUNT (0)
+/* @brief ZLL availability on the SoC. */
+#define FSL_FEATURE_SOC_ZLL_COUNT (0)
+
+/* ADC16 module features */
+
+/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
+#define FSL_FEATURE_ADC16_HAS_PGA (0)
+/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
+/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
+/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
+#define FSL_FEATURE_ADC16_HAS_DMA (1)
+/* @brief Has differential mode (bitfield SC1x[DIFF]). */
+#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
+/* @brief Has FIFO (bit SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_HAS_FIFO (0)
+/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
+/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
+#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
+/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
+#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
+/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
+#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
+/* @brief Has HW averaging (bit SC3[AVGE]). */
+#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
+/* @brief Has offset correction (register OFS). */
+#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
+/* @brief Maximum ADC resolution. */
+#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
+/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
+#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
+
+/* CMP module features */
+
+/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
+#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
+/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
+#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
+/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
+#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
+/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
+#define FSL_FEATURE_CMP_HAS_DMA (1)
+/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
+#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
+/* @brief Has DAC Test function in CMP (register DACTEST). */
+#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
+
+/* CRC module features */
+
+/* @brief Has data register with name CRC */
+#define FSL_FEATURE_CRC_HAS_CRC_REG (1)
+
+/* DAC module features */
+
+/* @brief Define the size of hardware buffer */
+#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
+/* @brief Define whether the buffer supports watermark event detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
+/* @brief Define whether the buffer supports watermark selection detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
+/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
+/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
+/* @brief Define whether FIFO buffer mode is available or not. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1)
+/* @brief Define whether swing buffer mode is available or not.. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 8)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief Has DMA_Error interrupt vector. */
+#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
+/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (8)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (8)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 8)
+/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+
+/* EWM module features */
+
+/* @brief Has clock select (register CLKCTRL). */
+#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT  (0)
+/* @brief Has clock prescaler (register CLKPRESCALER). */
+#define FSL_FEATURE_EWM_HAS_PRESCALER  (1)
+
+/* FLEXIO module features */
+
+/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
+#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
+/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
+#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
+/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
+/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
+/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
+/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
+/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
+/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
+#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
+/* @brief Reset value of the FLEXIO_VERID register */
+#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
+/* @brief Reset value of the FLEXIO_PARAM register */
+#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10200808)
+/* @brief Flexio DMA request base channel */
+#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
+
+/* FLASH module features */
+
+/* @brief Is of type FTFA. */
+#define FSL_FEATURE_FLASH_IS_FTFA (1)
+/* @brief Is of type FTFE. */
+#define FSL_FEATURE_FLASH_IS_FTFE (0)
+/* @brief Is of type FTFL. */
+#define FSL_FEATURE_FLASH_IS_FTFL (0)
+/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
+/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
+/* @brief Has EEPROM region protection (register FEPROT). */
+#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+/* @brief Has data flash region protection (register FDPROT). */
+#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
+/* @brief Has flash cache control in FMC module. */
+#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+/* @brief Has flash cache control in MCM module. */
+#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
+/* @brief Has flash cache control in MSCM module. */
+#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+/* @brief P-Flash start address. */
+#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+/* @brief P-Flash block count. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+/* @brief P-Flash block size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
+/* @brief P-Flash sector size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
+/* @brief P-Flash write unit size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
+/* @brief P-Flash data path width. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
+/* @brief P-Flash block swap feature. */
+#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+/* @brief Has FlexNVM memory. */
+#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+/* @brief FlexNVM block count. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+/* @brief FlexNVM block size. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+/* @brief FlexNVM sector size. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+/* @brief FlexNVM write unit size. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+/* @brief FlexNVM data path width. */
+#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+/* @brief Has FlexRAM memory. */
+#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
+/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
+/* @brief FlexRAM size. */
+#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
+/* @brief Has 0x00 Read 1s Block command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
+/* @brief Has 0x01 Read 1s Section command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+/* @brief Has 0x02 Program Check command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+/* @brief Has 0x03 Read Resource command. */
+#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+/* @brief Has 0x06 Program Longword command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
+/* @brief Has 0x07 Program Phrase command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
+/* @brief Has 0x08 Erase Flash Block command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
+/* @brief Has 0x09 Erase Flash Sector command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+/* @brief Has 0x0B Program Section command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
+/* @brief Has 0x40 Read 1s All Blocks command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+/* @brief Has 0x41 Read Once command. */
+#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+/* @brief Has 0x43 Program Once command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+/* @brief Has 0x44 Erase All Blocks command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+/* @brief Has 0x45 Verify Backdoor Access Key command. */
+#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+/* @brief Has 0x46 Swap Control command. */
+#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+/* @brief Has 0x49 Erase All Blocks Unsecure command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
+/* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+/* @brief Has 0x4B Erase All Execute-only Segments command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1)
+/* @brief Has 0x80 Program Partition command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+/* @brief Has 0x81 Set FlexRAM Function command. */
+#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+/* @brief P-Flash Erase/Read 1st all block command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
+/* @brief P-Flash Erase sector command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
+/* @brief P-Flash Rrogram/Verify section command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
+/* @brief P-Flash Read resource command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
+/* @brief P-Flash Program check command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+/* @brief P-Flash Program check command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Erase sector command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Rrogram/Verify section command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Read resource command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Program check command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
+/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
+/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
+/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
+/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
+/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
+/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
+/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
+/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
+
+/* I2C module features */
+
+/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
+#define FSL_FEATURE_I2C_HAS_SMBUS (1)
+/* @brief Maximum supported baud rate in kilobit per second. */
+#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
+/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
+#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
+/* @brief Has DMA support (register bit C1[DMAEN]). */
+#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
+/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
+/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
+/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
+#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
+/* @brief Maximum width of the glitch filter in number of bus clocks. */
+#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
+/* @brief Has control of the drive capability of the I2C pins. */
+#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
+/* @brief Has double buffering support (register S2). */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1)
+/* @brief Has double buffer enable. */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1)
+
+/* INTMUX module features */
+
+/* @brief Number of INTMUX channels (related to number of register CHn_CSR). */
+#define FSL_FEATURE_INTMUX_CHANNEL_COUNT (4)
+/* @brief Number of INTMUX IRQ source. */
+#define FSL_FEATURE_INTMUX_IRQ_COUNT (32)
+/* @brief The start IRQ index of first INTMUX source IRQ. */
+#define FSL_FEATURE_INTMUX_IRQ_START_INDEX (32)
+
+/* LLWU module features */
+
+#if defined(CPU_MKL82Z128VLH7) || defined(CPU_MKL82Z128VLK7) || defined(CPU_MKL82Z128VMP7)
+    /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+    /* @brief Has pins 8-15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+    /* @brief Maximum number of internal modules connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+    /* @brief Number of digital filters. */
+    #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4)
+    /* @brief Has MF register. */
+    #define FSL_FEATURE_LLWU_HAS_MF (1)
+    /* @brief Has PF register. */
+    #define FSL_FEATURE_LLWU_HAS_PF (1)
+    /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+    #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+    /* @brief Has external pin 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
+    /* @brief Has external pin 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
+    /* @brief Has external pin 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
+    /* @brief Has external pin 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
+    /* @brief Has external pin 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0)
+    /* @brief Has external pin 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
+    /* @brief Has external pin 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
+    /* @brief Has external pin 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
+    /* @brief Has external pin 8 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
+    /* @brief Has external pin 9 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
+    /* @brief Has external pin 10 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
+    /* @brief Has external pin 11 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
+    /* @brief Has external pin 12 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
+    /* @brief Has external pin 13 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
+    /* @brief Has external pin 14 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
+    /* @brief Has external pin 15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
+    /* @brief Has external pin 16 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+    /* @brief Has external pin 17 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+    /* @brief Has external pin 18 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+    /* @brief Has external pin 19 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+    /* @brief Has external pin 20 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+    /* @brief Has external pin 21 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+    /* @brief Has external pin 22 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+    /* @brief Has external pin 23 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+    /* @brief Has external pin 24 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+    /* @brief Has external pin 25 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+    /* @brief Has external pin 26 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+    /* @brief Has external pin 27 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+    /* @brief Has external pin 28 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+    /* @brief Has external pin 29 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+    /* @brief Has external pin 30 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+    /* @brief Has external pin 31 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+    /* @brief Has internal module 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+    /* @brief Has internal module 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+    /* @brief Has internal module 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0)
+    /* @brief Has internal module 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
+    /* @brief Has internal module 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
+    /* @brief Has internal module 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+    /* @brief Has internal module 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+    /* @brief Has internal module 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+    /* @brief Has Version ID Register (LLWU_VERID). */
+    #define FSL_FEATURE_LLWU_HAS_VERID (0)
+    /* @brief Has Parameter Register (LLWU_PARAM). */
+    #define FSL_FEATURE_LLWU_HAS_PARAM (0)
+    /* @brief Width of registers of the LLWU. */
+    #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
+    /* @brief Has DMA Enable register (LLWU_DE). */
+    #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
+#elif defined(CPU_MKL82Z128VLL7)
+    /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (19)
+    /* @brief Has pins 8-15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+    /* @brief Maximum number of internal modules connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+    /* @brief Number of digital filters. */
+    #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4)
+    /* @brief Has MF register. */
+    #define FSL_FEATURE_LLWU_HAS_MF (1)
+    /* @brief Has PF register. */
+    #define FSL_FEATURE_LLWU_HAS_PF (1)
+    /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+    #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+    /* @brief Has external pin 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
+    /* @brief Has external pin 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
+    /* @brief Has external pin 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
+    /* @brief Has external pin 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
+    /* @brief Has external pin 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
+    /* @brief Has external pin 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
+    /* @brief Has external pin 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
+    /* @brief Has external pin 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
+    /* @brief Has external pin 8 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
+    /* @brief Has external pin 9 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
+    /* @brief Has external pin 10 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
+    /* @brief Has external pin 11 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
+    /* @brief Has external pin 12 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
+    /* @brief Has external pin 13 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
+    /* @brief Has external pin 14 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
+    /* @brief Has external pin 15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
+    /* @brief Has external pin 16 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6)
+    /* @brief Has external pin 17 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9)
+    /* @brief Has external pin 18 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10)
+    /* @brief Has external pin 19 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+    /* @brief Has external pin 20 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+    /* @brief Has external pin 21 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+    /* @brief Has external pin 22 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+    /* @brief Has external pin 23 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+    /* @brief Has external pin 24 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+    /* @brief Has external pin 25 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+    /* @brief Has external pin 26 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+    /* @brief Has external pin 27 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+    /* @brief Has external pin 28 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+    /* @brief Has external pin 29 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+    /* @brief Has external pin 30 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+    /* @brief Has external pin 31 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+    /* @brief Has internal module 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+    /* @brief Has internal module 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+    /* @brief Has internal module 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0)
+    /* @brief Has internal module 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
+    /* @brief Has internal module 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
+    /* @brief Has internal module 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+    /* @brief Has internal module 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+    /* @brief Has internal module 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+    /* @brief Has Version ID Register (LLWU_VERID). */
+    #define FSL_FEATURE_LLWU_HAS_VERID (0)
+    /* @brief Has Parameter Register (LLWU_PARAM). */
+    #define FSL_FEATURE_LLWU_HAS_PARAM (0)
+    /* @brief Width of registers of the LLWU. */
+    #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
+    /* @brief Has DMA Enable register (LLWU_DE). */
+    #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
+#elif defined(CPU_MKL82Z128VMC7)
+    /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (26)
+    /* @brief Has pins 8-15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+    /* @brief Maximum number of internal modules connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+    /* @brief Number of digital filters. */
+    #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4)
+    /* @brief Has MF register. */
+    #define FSL_FEATURE_LLWU_HAS_MF (1)
+    /* @brief Has PF register. */
+    #define FSL_FEATURE_LLWU_HAS_PF (1)
+    /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+    #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+    /* @brief Has external pin 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
+    /* @brief Has external pin 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
+    /* @brief Has external pin 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
+    /* @brief Has external pin 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
+    /* @brief Has external pin 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
+    /* @brief Has external pin 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
+    /* @brief Has external pin 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
+    /* @brief Has external pin 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
+    /* @brief Has external pin 8 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
+    /* @brief Has external pin 9 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
+    /* @brief Has external pin 10 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
+    /* @brief Has external pin 11 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
+    /* @brief Has external pin 12 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
+    /* @brief Has external pin 13 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
+    /* @brief Has external pin 14 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
+    /* @brief Has external pin 15 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
+    /* @brief Has external pin 16 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6)
+    /* @brief Has external pin 17 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9)
+    /* @brief Has external pin 18 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10)
+    /* @brief Has external pin 19 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+    /* @brief Has external pin 20 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+    /* @brief Has external pin 21 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+    /* @brief Has external pin 22 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10)
+    /* @brief Has external pin 23 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11)
+    /* @brief Has external pin 24 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8)
+    /* @brief Has external pin 25 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11)
+    /* @brief Has external pin 26 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+    /* @brief Has external pin 27 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+    /* @brief Has external pin 28 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+    /* @brief Has external pin 29 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+    /* @brief Has external pin 30 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+    /* @brief Has external pin 31 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+    /* @brief Index of port of external pin. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+    /* @brief Number of external pin port on specified port. */
+    #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+    /* @brief Has internal module 0 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+    /* @brief Has internal module 1 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+    /* @brief Has internal module 2 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0)
+    /* @brief Has internal module 3 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
+    /* @brief Has internal module 4 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
+    /* @brief Has internal module 5 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+    /* @brief Has internal module 6 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+    /* @brief Has internal module 7 connected to LLWU device. */
+    #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+    /* @brief Has Version ID Register (LLWU_VERID). */
+    #define FSL_FEATURE_LLWU_HAS_VERID (0)
+    /* @brief Has Parameter Register (LLWU_PARAM). */
+    #define FSL_FEATURE_LLWU_HAS_PARAM (0)
+    /* @brief Width of registers of the LLWU. */
+    #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
+    /* @brief Has DMA Enable register (LLWU_DE). */
+    #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
+#endif /* defined(CPU_MKL82Z128VLH7) || defined(CPU_MKL82Z128VLK7) || defined(CPU_MKL82Z128VMP7) */
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+
+/* LPUART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_HAS_FIFO (1)
+/* @brief Has 32-bit register MODIR */
+#define FSL_FEATURE_LPUART_HAS_MODIR (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief If 7-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_LPUART_IS_SCI (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \
+    ((x) == LPUART0 ? (8) : \
+    ((x) == LPUART1 ? (8) : \
+    ((x) == LPUART2 ? (1) : (-1))))
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
+/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
+#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Has separate RX and TX interrupts. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
+/* @brief Has LPAURT_PARAM. */
+#define FSL_FEATURE_LPUART_HAS_PARAM (0)
+/* @brief Has LPUART_VERID. */
+#define FSL_FEATURE_LPUART_HAS_VERID (0)
+/* @brief Has LPUART_GLOBAL. */
+#define FSL_FEATURE_LPUART_HAS_GLOBAL (0)
+/* @brief Has LPUART_PINCFG. */
+#define FSL_FEATURE_LPUART_HAS_PINCFG (0)
+
+/* LTC module features */
+
+/* @brief LTC module supports DES algorithm. */
+#define FSL_FEATURE_LTC_HAS_DES (1)
+/* @brief LTC module supports PKHA algorithm. */
+#define FSL_FEATURE_LTC_HAS_PKHA (1)
+/* @brief LTC module supports SHA algorithm. */
+#define FSL_FEATURE_LTC_HAS_SHA (1)
+/* @brief LTC module supports AES GCM mode. */
+#define FSL_FEATURE_LTC_HAS_GCM (1)
+/* @brief LTC module supports DPAMS registers. */
+#define FSL_FEATURE_LTC_HAS_DPAMS (1)
+/* @brief LTC module supports AES with 24 bytes key. */
+#define FSL_FEATURE_LTC_HAS_AES192 (1)
+/* @brief LTC module supports AES with 32 bytes key. */
+#define FSL_FEATURE_LTC_HAS_AES256 (1)
+
+/* MCG module features */
+
+/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
+/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (7)
+/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_VDIV_BASE (16)
+/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MIN (8000000)
+/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MAX (16000000)
+/* @brief The PLL clock is divided by 2 before VCO divider. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (1)
+/* @brief FRDIV supports 1280. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
+/* @brief FRDIV supports 1536. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
+/* @brief MCGFFCLK divider. */
+#define FSL_FEATURE_MCG_FFCLK_DIV (1)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
+#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
+/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
+#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
+/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_PLL1 (0)
+/* @brief Has 48MHz internal oscillator. */
+#define FSL_FEATURE_MCG_HAS_IRC_48M (1)
+/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_OSC1 (0)
+/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
+#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
+/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
+#define FSL_FEATURE_MCG_HAS_LOLRE (1)
+/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
+#define FSL_FEATURE_MCG_USE_OSCSEL (1)
+/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
+#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
+/* @brief TBD */
+#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
+/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL (1)
+/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
+/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
+/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
+#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
+/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
+#define FSL_FEATURE_MCG_HAS_FLL (1)
+/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
+/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
+#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
+/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
+/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
+/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
+#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
+/* @brief Has external clock monitor (register bit C6[CME]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
+/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
+#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
+/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
+#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
+/* @brief Has PEI mode or PBI mode. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
+/* @brief Reset clock mode is BLPI. */
+#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
+
+/* MPU module features */
+
+/* @brief Specifies number of descriptors available. */
+#define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (8)
+/* @brief Has process identifier support. */
+#define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1)
+/* @brief Total number of MPU master. */
+#define FSL_FEATURE_MPU_MASTER_COUNT (8)
+/* @brief Total number of MPU master with privileged rights */
+#define FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT (4)
+/* @brief Max index of used MPU master. */
+#define FSL_FEATURE_MPU_MASTER_MAX_INDEX (4)
+/* @brief Max index of used MPU master with privileged rights */
+#define FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX (2)
+/* @brief Has master 0. */
+#define FSL_FEATURE_MPU_HAS_MASTER0 (1)
+/* @brief Has master 1. */
+#define FSL_FEATURE_MPU_HAS_MASTER1 (1)
+/* @brief Has master 2. */
+#define FSL_FEATURE_MPU_HAS_MASTER2 (1)
+/* @brief Has master 3. */
+#define FSL_FEATURE_MPU_HAS_MASTER3 (0)
+/* @brief Has master 4. */
+#define FSL_FEATURE_MPU_HAS_MASTER4 (1)
+/* @brief Has master 5. */
+#define FSL_FEATURE_MPU_HAS_MASTER5 (0)
+/* @brief Has master 6. */
+#define FSL_FEATURE_MPU_HAS_MASTER6 (0)
+/* @brief Has master 7. */
+#define FSL_FEATURE_MPU_HAS_MASTER7 (0)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
+
+/* OSC module features */
+
+/* @brief Has OSC1 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC1 (0)
+/* @brief Has OSC0 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC0 (0)
+/* @brief Has OSC external oscillator (without index). */
+#define FSL_FEATURE_OSC_HAS_OSC (1)
+/* @brief Number of OSC external oscillators. */
+#define FSL_FEATURE_OSC_OSC_COUNT (1)
+/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
+#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1)
+
+/* PIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_PIT_TIMER_COUNT (4)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
+
+/* PMC module features */
+
+/* @brief Has Bandgap Enable In VLPx Operation support. */
+#define FSL_FEATURE_PMC_HAS_BGEN (1)
+/* @brief Has Bandgap Buffer Enable. */
+#define FSL_FEATURE_PMC_HAS_BGBE (1)
+/* @brief Has Bandgap Buffer Drive Select. */
+#define FSL_FEATURE_PMC_HAS_BGBDS (0)
+/* @brief Has Low-Voltage Detect Voltage Select support. */
+#define FSL_FEATURE_PMC_HAS_LVDV (1)
+/* @brief Has Low-Voltage Warning Voltage Select support. */
+#define FSL_FEATURE_PMC_HAS_LVWV (1)
+/* @brief Has LPO. */
+#define FSL_FEATURE_PMC_HAS_LPO (0)
+/* @brief Has VLPx option PMC_REGSC[VLPO]. */
+#define FSL_FEATURE_PMC_HAS_VLPO (1)
+/* @brief Has acknowledge isolation support. */
+#define FSL_FEATURE_PMC_HAS_ACKISO (1)
+/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
+#define FSL_FEATURE_PMC_HAS_REGFPM (0)
+/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
+#define FSL_FEATURE_PMC_HAS_REGONS (1)
+/* @brief Has PMC_HVDSC1. */
+#define FSL_FEATURE_PMC_HAS_HVDSC1 (1)
+/* @brief Has PMC_PARAM. */
+#define FSL_FEATURE_PMC_HAS_PARAM (0)
+/* @brief Has PMC_VERID. */
+#define FSL_FEATURE_PMC_HAS_VERID (0)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
+/* @brief Has DMA request (register bit field PCR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (0)
+/* @brief Has separate drive strength register (HDRVE). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
+/* @brief Has glitch filter (register IOFLT). */
+#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (1)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (1)
+
+/* QSPI module features */
+
+/* @brief QSPI lookup table depth. */
+#define FSL_FEATURE_QSPI_LUT_DEPTH (64)
+/* @brief QSPI Tx FIFO depth. */
+#define FSL_FEATURE_QSPI_TXFIFO_DEPTH (16)
+/* @brief QSPI Rx FIFO depth. */
+#define FSL_FEATURE_QSPI_RXFIFO_DEPTH (16)
+/* @brief QSPI AHB buffer count. */
+#define FSL_FEATURE_QSPI_AHB_BUFFER_COUNT (4)
+/* @brief QSPI AMBA base address. */
+#define FSL_FEATURE_QSPI_AMBA_BASE (0x68000000U)
+/* @brief QSPI AHB buffer ARDB base address. */
+#define FSL_FEATURE_QSPI_ARDB_BASE (0x67000000U)
+
+/* RCM module features */
+
+/* @brief Has Loss-of-Lock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOL (1)
+/* @brief Has Loss-of-Clock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOC (1)
+/* @brief Has JTAG generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_JTAG (0)
+/* @brief Has EzPort generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_EZPORT (0)
+/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
+#define FSL_FEATURE_RCM_HAS_EZPMS (0)
+/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
+#define FSL_FEATURE_RCM_HAS_BOOTROM (1)
+/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
+#define FSL_FEATURE_RCM_HAS_SSRS (1)
+/* @brief Has Version ID Register (RCM_VERID). */
+#define FSL_FEATURE_RCM_HAS_VERID (0)
+/* @brief Has Parameter Register (RCM_PARAM). */
+#define FSL_FEATURE_RCM_HAS_PARAM (0)
+/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
+#define FSL_FEATURE_RCM_HAS_SRIE (0)
+/* @brief Width of registers of the RCM. */
+#define FSL_FEATURE_RCM_REG_WIDTH (8)
+/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
+#define FSL_FEATURE_RCM_HAS_CORE1 (0)
+/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
+#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
+/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
+#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
+
+/* RTC module features */
+
+/* @brief Has wakeup pin. */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+/* @brief Has wakeup pin selection (bit field CR[WPS]). */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
+/* @brief Has low power features (registers MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+/* @brief Has read/write access control (registers WAR and RAR). */
+#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_SECURITY (1)
+/* @brief Has RTC_CLKIN available. */
+#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
+/* @brief Has prescaler adjust for LPO. */
+#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
+/* @brief Has Clock Pin Enable field. */
+#define FSL_FEATURE_RTC_HAS_CPE (0)
+/* @brief Has Timer Seconds Interrupt Configuration field. */
+#define FSL_FEATURE_RTC_HAS_TSIC (0)
+/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
+#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
+/* @brief ADC module has alternate trigger (register bit SOPT7[ADC0ALTTRGEN]). */
+#define FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER (0)
+/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0)
+/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
+/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
+/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
+/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
+/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (1)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (1)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+/* @brief Has MISCCTRL reg. */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL (1)
+/* @brief Has LTCEN bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_LTCEN (1)
+/* @brief Has DMAINTSEL0 bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL0 (1)
+/* @brief Has DMAINTSEL1 bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL1 (1)
+/* @brief Has DMAINTSEL2 bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL2 (1)
+/* @brief Has DMAINTSEL3 bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL3 (1)
+/* @brief Has SECKEY0 reg. */
+#define FSL_FEATURE_SIM_HAS_SECKEY0 (1)
+/* @brief Has SECKEY bit (e.g SIM_SECKEY0). */
+#define FSL_FEATURE_SIM_HAS_SECKEY0_SECKEY (1)
+/* @brief Has SECKEY1 reg. */
+#define FSL_FEATURE_SIM_HAS_SECKEY1 (1)
+/* @brief Has SECKEY bit (e.g SIM_SECKEY1). */
+#define FSL_FEATURE_SIM_HAS_SECKEY1_SECKEY (1)
+/* @brief Has SECKEY2 reg. */
+#define FSL_FEATURE_SIM_HAS_SECKEY2 (1)
+/* @brief Has SECKEY bit (e.g SIM_SECKEY2). */
+#define FSL_FEATURE_SIM_HAS_SECKEY2_SECKEY (1)
+/* @brief Has SECKEY3 reg. */
+#define FSL_FEATURE_SIM_HAS_SECKEY3 (1)
+/* @brief Has SECKEY bit (e.g SIM_SECKEY3). */
+#define FSL_FEATURE_SIM_HAS_SECKEY3_SECKEY (1)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (1)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (1)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (1)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (0)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
+#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode. */
+#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
+/* @brief Has SMC_PARAM. */
+#define FSL_FEATURE_SMC_HAS_PARAM (0)
+/* @brief Has SMC_VERID. */
+#define FSL_FEATURE_SMC_HAS_VERID (0)
+
+/* DSPI module features */
+
+#if defined(CPU_MKL82Z128VLH7) || defined(CPU_MKL82Z128VLK7) || defined(CPU_MKL82Z128VMP7)
+    /* @brief Receive/transmit FIFO size in number of items. */
+    #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
+        ((x) == DSPI0 ? (4) : \
+        ((x) == DSPI1 ? (1) : (-1)))
+    /* @brief Maximum transfer data width in bits. */
+    #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
+    /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
+    #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
+    /* @brief Number of chip select pins. */
+    #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5)
+    /* @brief Has chip select strobe capability on the PCS5 pin. */
+    #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
+    /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+    #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+    /* @brief Has 16-bit data transfer support. */
+    #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
+    /* @brief Has separate DMA RX and TX requests. */
+    #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+#elif defined(CPU_MKL82Z128VLL7) || defined(CPU_MKL82Z128VMC7)
+    /* @brief Receive/transmit FIFO size in number of items. */
+    #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
+        ((x) == DSPI0 ? (4) : \
+        ((x) == DSPI1 ? (1) : (-1)))
+    /* @brief Maximum transfer data width in bits. */
+    #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
+    /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
+    #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
+    /* @brief Number of chip select pins. */
+    #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
+    /* @brief Has chip select strobe capability on the PCS5 pin. */
+    #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
+    /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+    #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+    /* @brief Has 16-bit data transfer support. */
+    #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
+    /* @brief Has separate DMA RX and TX requests. */
+    #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+#endif /* defined(CPU_MKL82Z128VLH7) || defined(CPU_MKL82Z128VLK7) || defined(CPU_MKL82Z128VMP7) */
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
+
+/* TPM module features */
+
+/* @brief Bus clock is the source clock for the module. */
+#define FSL_FEATURE_TPM_BUS_CLOCK (0)
+/* @brief Number of channels. */
+#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
+    ((x) == TPM0 ? (6) : \
+    ((x) == TPM1 ? (2) : \
+    ((x) == TPM2 ? (2) : (-1))))
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+/* @brief Has TPM_PARAM. */
+#define FSL_FEATURE_TPM_HAS_PARAM (0)
+/* @brief Has TPM_VERID. */
+#define FSL_FEATURE_TPM_HAS_VERID (0)
+/* @brief Has TPM_GLOBAL. */
+#define FSL_FEATURE_TPM_HAS_GLOBAL (0)
+/* @brief Has TPM_TRIG. */
+#define FSL_FEATURE_TPM_HAS_TRIG (0)
+/* @brief Has counter pause on trigger. */
+#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
+/* @brief Has external trigger selection. */
+#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
+/* @brief Has TPM_COMBINE. */
+#define FSL_FEATURE_TPM_HAS_COMBINE (1)
+/* @brief Has TPM_POL. */
+#define FSL_FEATURE_TPM_HAS_POL (1)
+/* @brief Has TPM_FILTER. */
+#define FSL_FEATURE_TPM_HAS_FILTER (1)
+/* @brief Has TPM_QDCTRL. */
+#define FSL_FEATURE_TPM_HAS_QDCTRL (0)
+
+/* TSI module features */
+
+/* @brief TSI module version. */
+#define FSL_FEATURE_TSI_VERSION (4)
+/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */
+#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (1)
+/* @brief Number of TSI channels. */
+#define FSL_FEATURE_TSI_CHANNEL_COUNT (16)
+
+/* USB module features */
+
+/* @brief HOST mode enabled */
+#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
+/* @brief OTG mode enabled */
+#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM (2048)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1074790400)
+/* @brief Has KEEP_ALIVE_CTRL register */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1)
+/* @brief Mode control of the USB Keep Alive */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK)
+/* @brief Has the Dynamic SOF threshold compare support */
+#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1)
+/* @brief Has the VBUS detect support */
+#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1)
+/* @brief Has the IRC48M module clock support */
+#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
+/* @brief Number of endpoints supported */
+#define FSL_FEATURE_USB_ENDPT_COUNT (16)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief If high/low buffer mode supported */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+/* @brief Has VREF_TRM4. */
+#define FSL_FEATURE_VREF_HAS_TRM4 (0)
+
+/* WDOG module features */
+
+/* @brief Watchdog is available. */
+#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
+/* @brief Has Wait mode support. */
+#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
+
+#endif /* _MKL82Z7_FEATURES_H_ */
+
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/MKL82Z128xxx7.sct b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/MKL82Z128xxx7.sct
new file mode 100644
index 00000000000..a7fd0ecc526
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/MKL82Z128xxx7.sct
@@ -0,0 +1,143 @@
+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          MKL82Z128VLH7
+**                          MKL82Z128VLK7
+**                          MKL82Z128VLL7
+**                          MKL82Z128VMC7
+**                          MKL82Z128VMP7
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    KL82P121M72SF0RM, Rev.2 November 2015
+**     Version:             rev. 1.5, 2015-09-24
+**     Build:               b160406
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+** ###################################################################
+*/
+#define __ram_vector_table__            1
+
+/* Heap 1/4 of ram and stack 1/8 */
+#define __stack_size__       0x3000
+#define __heap_size__        0x6000
+
+#if (defined(__ram_vector_table__))
+  #define __ram_vector_table_size__    0x00000140
+#else
+  #define __ram_vector_table_size__    0x00000000
+#endif
+
+#define m_interrupts_start             0x00000000
+#define m_interrupts_size              0x00000140
+
+#define m_bootloader_config_start      0x000003C0
+#define m_bootloader_config_size       0x00000040
+
+#define m_flash_config_start           0x00000400
+#define m_flash_config_size            0x00000010
+
+#define m_text_start                   0x00000410
+#define m_text_size                    0x0001FBF0
+
+#define m_interrupts_ram_start         0x1FFFA000
+#define m_interrupts_ram_size          __ram_vector_table_size__
+
+#define m_data_start                   (m_interrupts_ram_start + m_interrupts_ram_size)
+#define m_data_size                    (0x00018000 - m_interrupts_ram_size)
+
+#if (defined(__usb_use_usbram__))
+#define m_usb_sram_start               0x40100000
+#define m_usb_sram_size                0x00000800
+#endif
+
+/* USB BDT size */
+#define usb_bdt_size                   0x200
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (RESET,+FIRST)
+  }
+  ER_m_bootloader_config m_bootloader_config_start FIXED m_bootloader_config_size { ; load address = execution address
+    * (BootloaderConfig)
+  }
+  ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
+    * (FlashConfig)
+  }
+  ER_m_text m_text_start m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+#if (defined(__ram_vector_table__))
+  VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
+  }
+#else
+  VECTOR_RAM m_interrupts_start EMPTY 0 {
+  }
+#endif
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  RW_IRAM1 +0 {    ; Heap region growing up
+  }
+}
+
+#if (defined(__usb_use_usbram__))
+LR_m_usb_bdt m_usb_sram_start usb_bdt_size {
+  ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (m_usb_bdt)
+  }
+}
+
+LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) {
+  ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (m_usb_global)
+  }
+}
+#endif
+
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/startup_MKL82Z7.s b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/startup_MKL82Z7.s
new file mode 100644
index 00000000000..aa7fdb13384
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/startup_MKL82Z7.s
@@ -0,0 +1,616 @@
+; * ---------------------------------------------------------------------------------------
+; *  @file:    startup_MKL82Z7.s
+; *  @purpose: CMSIS Cortex-M0P Core Device Startup File
+; *            MKL82Z7
+; *  @version: 1.5
+; *  @date:    2015-9-24
+; *  @build:   b151217
+; * ---------------------------------------------------------------------------------------
+; *
+; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without modification,
+; * are permitted provided that the following conditions are met:
+; *
+; * o Redistributions of source code must retain the above copyright notice, this list
+; *   of conditions and the following disclaimer.
+; *
+; * o Redistributions in binary form must reproduce the above copyright notice, this
+; *   list of conditions and the following disclaimer in the documentation and/or
+; *   other materials provided with the distribution.
+; *
+; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; *   contributors may be used to endorse or promote products derived from this
+; *   software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+__initial_sp        EQU     0x20012000  ; Top of RAM
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler                         ;NMI Handler
+                DCD     HardFault_Handler                   ;Hard Fault Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     SVC_Handler                         ;SVCall Handler
+                DCD     0                                   ;Reserved
+                DCD     0                                   ;Reserved
+                DCD     PendSV_Handler                      ;PendSV Handler
+                DCD     SysTick_Handler                     ;SysTick Handler
+
+                                                            ;External Interrupts
+                DCD     DMA0_DMA4_IRQHandler                ;DMA channel 0, 4 transfer complete
+                DCD     DMA1_DMA5_IRQHandler                ;DMA channel 1, 5 transfer complete
+                DCD     DMA2_DMA6_IRQHandler                ;DMA channel 2, 6 transfer complete
+                DCD     DMA3_DMA7_IRQHandler                ;DMA channel 3, 7 transfer complete
+                DCD     DMA_Error_IRQHandler                ;DMA channel 0 - 7 error
+                DCD     FLEXIO0_IRQHandler                  ;Flexible IO
+                DCD     TPM0_IRQHandler                     ;Timer/PWM module 0
+                DCD     TPM1_IRQHandler                     ;Timer/PWM module 1
+                DCD     TPM2_IRQHandler                     ;Timer/PWM module 2
+                DCD     PIT0_IRQHandler                     ;Periodic Interrupt Timer 0
+                DCD     SPI0_IRQHandler                     ;Serial Peripheral Interface 0
+                DCD     EMVSIM0_IRQHandler                  ;EMVSIM0 common interrupt
+                DCD     LPUART0_IRQHandler                  ;LPUART0 status and error
+                DCD     LPUART1_IRQHandler                  ;LPUART1 status and error
+                DCD     I2C0_IRQHandler                     ;Inter-Integrated Circuit 0
+                DCD     QSPI0_IRQHandler                    ;QuadSPI0 interrupt
+                DCD     Reserved32_IRQHandler               ;DryIce tamper detect
+                DCD     PORTA_IRQHandler                    ;Pin detect Port A
+                DCD     PORTB_IRQHandler                    ;Pin detect Port B
+                DCD     PORTC_IRQHandler                    ;Pin detect Port C
+                DCD     PORTD_IRQHandler                    ;Pin detect Port D
+                DCD     PORTE_IRQHandler                    ;Pin detect Port E
+                DCD     LLWU_IRQHandler                     ;Low Leakage Wakeup
+                DCD     LTC0_IRQHandler                     ;Low power trusted cryptographic
+                DCD     USB0_IRQHandler                     ;USB OTG interrupt
+                DCD     ADC0_IRQHandler                     ;Analog-to-Digital Converter 0
+                DCD     LPTMR0_IRQHandler                   ;Low-Power Timer 0
+                DCD     RTC_Seconds_IRQHandler              ;RTC seconds
+                DCD     INTMUX0_0_IRQHandler                ;Selectable peripheral interrupt INTMUX0-0
+                DCD     INTMUX0_1_IRQHandler                ;Selectable peripheral interrupt INTMUX0-1
+                DCD     INTMUX0_2_IRQHandler                ;Selectable peripheral interrupt INTMUX0-2
+                DCD     INTMUX0_3_IRQHandler                ;Selectable peripheral interrupt INTMUX0-3
+                DCD     LPTMR1_IRQHandler                   ;Low-Power Timer 1 (INTMUX source IRQ0)
+                DCD     Reserved49_IRQHandler               ;Reserved interrupt (INTMUX source IRQ1)
+                DCD     Reserved50_IRQHandler               ;Reserved interrupt (INTMUX source IRQ2)
+                DCD     Reserved51_IRQHandler               ;Reserved interrupt (INTMUX source IRQ3)
+                DCD     SPI1_IRQHandler                     ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+                DCD     LPUART2_IRQHandler                  ;LPUART2 status and error (INTMUX source IRQ5)
+                DCD     EMVSIM1_IRQHandler                  ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+                DCD     I2C1_IRQHandler                     ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+                DCD     TSI0_IRQHandler                     ;Touch Sensing Input 0 (INTMUX source IRQ8)
+                DCD     PMC_IRQHandler                      ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+                DCD     FTFA_IRQHandler                     ;FTFA command complete/read collision (INTMUX source IRQ10)
+                DCD     MCG_IRQHandler                      ;Multipurpose clock generator (INTMUX source IRQ11)
+                DCD     WDOG_EWM_IRQHandler                 ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+                DCD     DAC0_IRQHandler                     ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+                DCD     TRNG0_IRQHandler                    ;True randon number generator (INTMUX source IRQ14)
+                DCD     Reserved63_IRQHandler               ;Reserved interrupt (INTMUX source IRQ15)
+                DCD     CMP0_IRQHandler                     ;Comparator 0 (INTMUX source IRQ16)
+                DCD     Reserved65_IRQHandler               ;Reserved interrupt (INTMUX source IRQ17)
+                DCD     RTC_Alarm_IRQHandler                ;Real time clock (INTMUX source IRQ18)
+                DCD     Reserved67_IRQHandler               ;Reserved interrupt (INTMUX source IRQ19)
+                DCD     Reserved68_IRQHandler               ;Reserved interrupt (INTMUX source IRQ20)
+                DCD     Reserved69_IRQHandler               ;Reserved interrupt (INTMUX source IRQ21)
+                DCD     Reserved70_IRQHandler               ;Reserved interrupt (INTMUX source IRQ22)
+                DCD     Reserved71_IRQHandler               ;Reserved interrupt (INTMUX source IRQ23)
+                DCD     DMA4_IRQHandler                     ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+                DCD     DMA5_IRQHandler                     ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+                DCD     DMA6_IRQHandler                     ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+                DCD     DMA7_IRQHandler                     ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+                DCD     Reserved76_IRQHandler               ;Reserved interrupt (INTMUX source IRQ28)
+                DCD     Reserved77_IRQHandler               ;Reserved interrupt (INTMUX source IRQ29)
+                DCD     Reserved78_IRQHandler               ;Reserved interrupt (INTMUX source IRQ30)
+                DCD     Reserved79_IRQHandler               ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict access to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Comparison Key 0.  <0x0-0xFF:2>
+;     <o1>  Backdoor Comparison Key 1.  <0x0-0xFF:2>
+;     <o2>  Backdoor Comparison Key 2.  <0x0-0xFF:2>
+;     <o3>  Backdoor Comparison Key 3.  <0x0-0xFF:2>
+;     <o4>  Backdoor Comparison Key 4.  <0x0-0xFF:2>
+;     <o5>  Backdoor Comparison Key 5.  <0x0-0xFF:2>
+;     <o6>  Backdoor Comparison Key 6.  <0x0-0xFF:2>
+;     <o7>  Backdoor Comparison Key 7.  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> Program flash protection bytes (FPROT)
+;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+;     <i> Each bit protects a 1/32 region of the program flash memory.
+;     <h> FPROT0
+;       <i> Program Flash Region Protect Register 0
+;       <i> 1/32 - 8/32 region
+;       <o.0>   FPROT0.0
+;       <o.1>   FPROT0.1
+;       <o.2>   FPROT0.2
+;       <o.3>   FPROT0.3
+;       <o.4>   FPROT0.4
+;       <o.5>   FPROT0.5
+;       <o.6>   FPROT0.6
+;       <o.7>   FPROT0.7
+nFPROT0         EQU     0x00
+FPROT0          EQU     nFPROT0:EOR:0xFF
+;     </h>
+;     <h> FPROT1
+;       <i> Program Flash Region Protect Register 1
+;       <i> 9/32 - 16/32 region
+;       <o.0>   FPROT1.0
+;       <o.1>   FPROT1.1
+;       <o.2>   FPROT1.2
+;       <o.3>   FPROT1.3
+;       <o.4>   FPROT1.4
+;       <o.5>   FPROT1.5
+;       <o.6>   FPROT1.6
+;       <o.7>   FPROT1.7
+nFPROT1         EQU     0x00
+FPROT1          EQU     nFPROT1:EOR:0xFF
+;     </h>
+;     <h> FPROT2
+;       <i> Program Flash Region Protect Register 2
+;       <i> 17/32 - 24/32 region
+;       <o.0>   FPROT2.0
+;       <o.1>   FPROT2.1
+;       <o.2>   FPROT2.2
+;       <o.3>   FPROT2.3
+;       <o.4>   FPROT2.4
+;       <o.5>   FPROT2.5
+;       <o.6>   FPROT2.6
+;       <o.7>   FPROT2.7
+nFPROT2         EQU     0x00
+FPROT2          EQU     nFPROT2:EOR:0xFF
+;     </h>
+;     <h> FPROT3
+;       <i> Program Flash Region Protect Register 3
+;       <i> 25/32 - 32/32 region
+;       <o.0>   FPROT3.0
+;       <o.1>   FPROT3.1
+;       <o.2>   FPROT3.2
+;       <o.3>   FPROT3.3
+;       <o.4>   FPROT3.4
+;       <o.5>   FPROT3.5
+;       <o.6>   FPROT3.6
+;       <o.7>   FPROT3.7
+nFPROT3         EQU     0x00
+FPROT3          EQU     nFPROT3:EOR:0xFF
+;     </h>
+;   </h>
+;   <h> Flash nonvolatile option byte (FOPT)
+;     <i> Allows the user to customize the operation of the MCU at boot time.
+;     <o.0> LPBOOT
+;       <0=> Low-power boot
+;       <1=> Normal boot
+;     <o.1> BOOTPIN_OPT
+;       <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
+;       <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
+;     <o.2> NMI_DIS
+;       <0=> NMI interrupts are always blocked
+;       <1=> NMI_b pin/interrupts reset default to enabled
+;     <o.5> FAST_INIT
+;       <0=> Slower initialization
+;       <1=> Fast Initialization
+;     <o.6..7> BOOTSRC_SEL
+;       <0=> Boot from Flash
+;       <2=> Boot from ROM, configure QSPI0, and enter boot loader mode.
+;       <3=> Boot from ROM and enter boot loader mode.
+;         <i> Boot source selection
+FOPT          EQU     0x3D
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;     <o.2..3> FSLACC
+;       <2=> Freescale factory access denied
+;       <3=> Freescale factory access granted
+;         <i> Freescale Failure Analysis Access Code
+;     <o.4..5> MEEN
+;       <2=> Mass erase is disabled
+;       <3=> Mass erase is enabled
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor Key Security Enable
+FSEC          EQU     0xFE
+;   </h>
+; </h>
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    FlashConfig, DATA, READONLY
+__FlashConfig
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     FPROT0    , FPROT1    , FPROT2    , FPROT3
+                DCB     FSEC      , FOPT      , 0xFF      , 0xFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+
+                IF      :LNOT::DEF:RAM_TARGET
+                REQUIRE FlashConfig
+                ENDIF
+
+                CPSID   I               ; Mask interrupts
+                LDR     R0, =0xE000ED08
+                LDR     R1, =__Vectors
+                STR     R1, [R0]
+                LDR     R0, =SystemInit
+                BLX     R0
+                CPSIE   i               ; Unmask interrupts
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler         [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler         [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler         [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+DMA0_DMA4_IRQHandler\
+                PROC
+                EXPORT  DMA0_DMA4_IRQHandler         [WEAK]
+                LDR     R0, =DMA0_DMA4_DriverIRQHandler
+                BX      R0
+                ENDP
+
+DMA1_DMA5_IRQHandler\
+                PROC
+                EXPORT  DMA1_DMA5_IRQHandler         [WEAK]
+                LDR     R0, =DMA1_DMA5_DriverIRQHandler
+                BX      R0
+                ENDP
+
+DMA2_DMA6_IRQHandler\
+                PROC
+                EXPORT  DMA2_DMA6_IRQHandler         [WEAK]
+                LDR     R0, =DMA2_DMA6_DriverIRQHandler
+                BX      R0
+                ENDP
+
+DMA3_DMA7_IRQHandler\
+                PROC
+                EXPORT  DMA3_DMA7_IRQHandler         [WEAK]
+                LDR     R0, =DMA3_DMA7_DriverIRQHandler
+                BX      R0
+                ENDP
+
+DMA_Error_IRQHandler\
+                PROC
+                EXPORT  DMA_Error_IRQHandler         [WEAK]
+                LDR     R0, =DMA_Error_DriverIRQHandler
+                BX      R0
+                ENDP
+
+FLEXIO0_IRQHandler\
+                PROC
+                EXPORT  FLEXIO0_IRQHandler         [WEAK]
+                LDR     R0, =FLEXIO0_DriverIRQHandler
+                BX      R0
+                ENDP
+
+SPI0_IRQHandler\
+                PROC
+                EXPORT  SPI0_IRQHandler         [WEAK]
+                LDR     R0, =SPI0_DriverIRQHandler
+                BX      R0
+                ENDP
+
+LPUART0_IRQHandler\
+                PROC
+                EXPORT  LPUART0_IRQHandler         [WEAK]
+                LDR     R0, =LPUART0_DriverIRQHandler
+                BX      R0
+                ENDP
+
+LPUART1_IRQHandler\
+                PROC
+                EXPORT  LPUART1_IRQHandler         [WEAK]
+                LDR     R0, =LPUART1_DriverIRQHandler
+                BX      R0
+                ENDP
+
+I2C0_IRQHandler\
+                PROC
+                EXPORT  I2C0_IRQHandler         [WEAK]
+                LDR     R0, =I2C0_DriverIRQHandler
+                BX      R0
+                ENDP
+
+QSPI0_IRQHandler\
+                PROC
+                EXPORT  QSPI0_IRQHandler         [WEAK]
+                LDR     R0, =QSPI0_DriverIRQHandler
+                BX      R0
+                ENDP
+
+INTMUX0_0_IRQHandler\
+                PROC
+                EXPORT  INTMUX0_0_IRQHandler         [WEAK]
+                LDR     R0, =INTMUX0_0_DriverIRQHandler
+                BX      R0
+                ENDP
+
+INTMUX0_1_IRQHandler\
+                PROC
+                EXPORT  INTMUX0_1_IRQHandler         [WEAK]
+                LDR     R0, =INTMUX0_1_DriverIRQHandler
+                BX      R0
+                ENDP
+
+INTMUX0_2_IRQHandler\
+                PROC
+                EXPORT  INTMUX0_2_IRQHandler         [WEAK]
+                LDR     R0, =INTMUX0_2_DriverIRQHandler
+                BX      R0
+                ENDP
+
+INTMUX0_3_IRQHandler\
+                PROC
+                EXPORT  INTMUX0_3_IRQHandler         [WEAK]
+                LDR     R0, =INTMUX0_3_DriverIRQHandler
+                BX      R0
+                ENDP
+
+SPI1_IRQHandler\
+                PROC
+                EXPORT  SPI1_IRQHandler         [WEAK]
+                LDR     R0, =SPI1_DriverIRQHandler
+                BX      R0
+                ENDP
+
+LPUART2_IRQHandler\
+                PROC
+                EXPORT  LPUART2_IRQHandler         [WEAK]
+                LDR     R0, =LPUART2_DriverIRQHandler
+                BX      R0
+                ENDP
+
+I2C1_IRQHandler\
+                PROC
+                EXPORT  I2C1_IRQHandler         [WEAK]
+                LDR     R0, =I2C1_DriverIRQHandler
+                BX      R0
+                ENDP
+
+DMA4_IRQHandler\
+                PROC
+                EXPORT  DMA4_IRQHandler         [WEAK]
+                LDR     R0, =DMA4_DriverIRQHandler
+                BX      R0
+                ENDP
+
+DMA5_IRQHandler\
+                PROC
+                EXPORT  DMA5_IRQHandler         [WEAK]
+                LDR     R0, =DMA5_DriverIRQHandler
+                BX      R0
+                ENDP
+
+DMA6_IRQHandler\
+                PROC
+                EXPORT  DMA6_IRQHandler         [WEAK]
+                LDR     R0, =DMA6_DriverIRQHandler
+                BX      R0
+                ENDP
+
+DMA7_IRQHandler\
+                PROC
+                EXPORT  DMA7_IRQHandler         [WEAK]
+                LDR     R0, =DMA7_DriverIRQHandler
+                BX      R0
+                ENDP
+
+Default_Handler\
+                PROC
+                EXPORT  DMA0_DMA4_DriverIRQHandler         [WEAK]
+                EXPORT  DMA1_DMA5_DriverIRQHandler         [WEAK]
+                EXPORT  DMA2_DMA6_DriverIRQHandler         [WEAK]
+                EXPORT  DMA3_DMA7_DriverIRQHandler         [WEAK]
+                EXPORT  DMA_Error_DriverIRQHandler         [WEAK]
+                EXPORT  FLEXIO0_DriverIRQHandler         [WEAK]
+                EXPORT  TPM0_IRQHandler         [WEAK]
+                EXPORT  TPM1_IRQHandler         [WEAK]
+                EXPORT  TPM2_IRQHandler         [WEAK]
+                EXPORT  PIT0_IRQHandler         [WEAK]
+                EXPORT  SPI0_DriverIRQHandler         [WEAK]
+                EXPORT  EMVSIM0_IRQHandler         [WEAK]
+                EXPORT  LPUART0_DriverIRQHandler         [WEAK]
+                EXPORT  LPUART1_DriverIRQHandler         [WEAK]
+                EXPORT  I2C0_DriverIRQHandler         [WEAK]
+                EXPORT  QSPI0_DriverIRQHandler         [WEAK]
+                EXPORT  Reserved32_IRQHandler         [WEAK]
+                EXPORT  PORTA_IRQHandler         [WEAK]
+                EXPORT  PORTB_IRQHandler         [WEAK]
+                EXPORT  PORTC_IRQHandler         [WEAK]
+                EXPORT  PORTD_IRQHandler         [WEAK]
+                EXPORT  PORTE_IRQHandler         [WEAK]
+                EXPORT  LLWU_IRQHandler         [WEAK]
+                EXPORT  LTC0_IRQHandler         [WEAK]
+                EXPORT  USB0_IRQHandler         [WEAK]
+                EXPORT  ADC0_IRQHandler         [WEAK]
+                EXPORT  LPTMR0_IRQHandler         [WEAK]
+                EXPORT  RTC_Seconds_IRQHandler         [WEAK]
+                EXPORT  INTMUX0_0_DriverIRQHandler         [WEAK]
+                EXPORT  INTMUX0_1_DriverIRQHandler         [WEAK]
+                EXPORT  INTMUX0_2_DriverIRQHandler         [WEAK]
+                EXPORT  INTMUX0_3_DriverIRQHandler         [WEAK]
+                EXPORT  LPTMR1_IRQHandler         [WEAK]
+                EXPORT  Reserved49_IRQHandler         [WEAK]
+                EXPORT  Reserved50_IRQHandler         [WEAK]
+                EXPORT  Reserved51_IRQHandler         [WEAK]
+                EXPORT  SPI1_DriverIRQHandler         [WEAK]
+                EXPORT  LPUART2_DriverIRQHandler         [WEAK]
+                EXPORT  EMVSIM1_IRQHandler         [WEAK]
+                EXPORT  I2C1_DriverIRQHandler         [WEAK]
+                EXPORT  TSI0_IRQHandler         [WEAK]
+                EXPORT  PMC_IRQHandler         [WEAK]
+                EXPORT  FTFA_IRQHandler         [WEAK]
+                EXPORT  MCG_IRQHandler         [WEAK]
+                EXPORT  WDOG_EWM_IRQHandler         [WEAK]
+                EXPORT  DAC0_IRQHandler         [WEAK]
+                EXPORT  TRNG0_IRQHandler         [WEAK]
+                EXPORT  Reserved63_IRQHandler         [WEAK]
+                EXPORT  CMP0_IRQHandler         [WEAK]
+                EXPORT  Reserved65_IRQHandler         [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler         [WEAK]
+                EXPORT  Reserved67_IRQHandler         [WEAK]
+                EXPORT  Reserved68_IRQHandler         [WEAK]
+                EXPORT  Reserved69_IRQHandler         [WEAK]
+                EXPORT  Reserved70_IRQHandler         [WEAK]
+                EXPORT  Reserved71_IRQHandler         [WEAK]
+                EXPORT  DMA4_DriverIRQHandler         [WEAK]
+                EXPORT  DMA5_DriverIRQHandler         [WEAK]
+                EXPORT  DMA6_DriverIRQHandler         [WEAK]
+                EXPORT  DMA7_DriverIRQHandler         [WEAK]
+                EXPORT  Reserved76_IRQHandler         [WEAK]
+                EXPORT  Reserved77_IRQHandler         [WEAK]
+                EXPORT  Reserved78_IRQHandler         [WEAK]
+                EXPORT  Reserved79_IRQHandler         [WEAK]
+                EXPORT  DefaultISR         [WEAK]
+DMA0_DMA4_DriverIRQHandler
+DMA1_DMA5_DriverIRQHandler
+DMA2_DMA6_DriverIRQHandler
+DMA3_DMA7_DriverIRQHandler
+DMA_Error_DriverIRQHandler
+FLEXIO0_DriverIRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_DriverIRQHandler
+EMVSIM0_IRQHandler
+LPUART0_DriverIRQHandler
+LPUART1_DriverIRQHandler
+I2C0_DriverIRQHandler
+QSPI0_DriverIRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_DriverIRQHandler
+INTMUX0_1_DriverIRQHandler
+INTMUX0_2_DriverIRQHandler
+INTMUX0_3_DriverIRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_DriverIRQHandler
+LPUART2_DriverIRQHandler
+EMVSIM1_IRQHandler
+I2C1_DriverIRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_DriverIRQHandler
+DMA5_DriverIRQHandler
+DMA6_DriverIRQHandler
+DMA7_DriverIRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+                LDR    R0, =DefaultISR
+                BX     R0
+                ENDP
+                  ALIGN
+
+
+                END
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 00000000000..b129b2c2a5b
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_GCC_ARM/MKL82Z128xxx7.ld b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_GCC_ARM/MKL82Z128xxx7.ld
new file mode 100644
index 00000000000..53fa9d29a46
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_GCC_ARM/MKL82Z128xxx7.ld
@@ -0,0 +1,287 @@
+/*
+** ###################################################################
+**     Processors:          MKL82Z128VLH7
+**                          MKL82Z128VLK7
+**                          MKL82Z128VLL7
+**                          MKL82Z128VMC7
+**                          MKL82Z128VMP7
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    KL82P121M72SF0RM, Rev.2 November 2015
+**     Version:             rev. 1.5, 2015-09-24
+**     Build:               b160406
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+__ram_vector_table__ = 1;
+
+/* Heap 1/4 of ram and stack 1/8 */
+__stack_size__ = 0x3000;
+__heap_size__ = 0x6000;
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0140 : 0x0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000140
+  m_bootloader_config   (RX)  : ORIGIN = 0x000003C0, LENGTH = 0x00000040
+  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
+  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x0001FBF0
+  m_data                (RW)  : ORIGIN = 0x1FFFA000, LENGTH = 0x00018000
+  m_usb_sram            (RW)  : ORIGIN = 0x40100000, LENGTH = 0x00000800
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  .bootloader_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.BootloaderConfig)) /* Bootloader Configuration Area (BCA) */
+    . = ALIGN(4);
+  } > m_bootloader_config
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  /* reserve MTB memory at the beginning of m_data */
+  .mtb : /* MTB buffer address as defined by the hardware */
+  {
+    . = ALIGN(8);
+    _mtb_start = .;
+    KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
+    . = ALIGN(8);
+    _mtb_end = .;
+  } > m_data
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  USB_RAM_GAP = DEFINED(__usb_use_usbram__) ? 0 : (DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800);
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    . = ALIGN(512);
+    USB_RAM_START = .;
+    . += USB_RAM_GAP;
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+    __heap_limit = .; /* Add for _sbrk */
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  USB_RAM_START = DEFINED(__usb_use_usbram__) ? ORIGIN(m_usb_sram) : USB_RAM_START;
+  m_usb_bdt USB_RAM_START (NOLOAD) :
+  {
+    *(m_usb_bdt)
+    USB_RAM_BDT_END = .;
+  }
+
+  m_usb_global USB_RAM_BDT_END (NOLOAD) :
+  {
+    *(m_usb_global)
+  }
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_GCC_ARM/startup_MKL82Z7.S b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_GCC_ARM/startup_MKL82Z7.S
new file mode 100644
index 00000000000..daeabc59ce9
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_GCC_ARM/startup_MKL82Z7.S
@@ -0,0 +1,545 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MKL82Z7.s                                                           */
+/*  @purpose: CMSIS Cortex-M0P Core Device Startup File                                   */
+/*            MKL82Z7                                                                     */
+/*  @version: 1.5                                                                         */
+/*  @date:    2015-9-24                                                                   */
+/*  @build:   b151217                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv6-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_DMA4_IRQHandler                            /* DMA channel 0, 4 transfer complete*/
+    .long   DMA1_DMA5_IRQHandler                            /* DMA channel 1, 5 transfer complete*/
+    .long   DMA2_DMA6_IRQHandler                            /* DMA channel 2, 6 transfer complete*/
+    .long   DMA3_DMA7_IRQHandler                            /* DMA channel 3, 7 transfer complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA channel 0 - 7 error*/
+    .long   FLEXIO0_IRQHandler                              /* Flexible IO*/
+    .long   TPM0_IRQHandler                                 /* Timer/PWM module 0*/
+    .long   TPM1_IRQHandler                                 /* Timer/PWM module 1*/
+    .long   TPM2_IRQHandler                                 /* Timer/PWM module 2*/
+    .long   PIT0_IRQHandler                                 /* Periodic Interrupt Timer 0*/
+    .long   SPI0_IRQHandler                                 /* Serial Peripheral Interface 0*/
+    .long   EMVSIM0_IRQHandler                              /* EMVSIM0 common interrupt*/
+    .long   LPUART0_IRQHandler                              /* LPUART0 status and error*/
+    .long   LPUART1_IRQHandler                              /* LPUART1 status and error*/
+    .long   I2C0_IRQHandler                                 /* Inter-Integrated Circuit 0*/
+    .long   QSPI0_IRQHandler                                /* QuadSPI0 interrupt*/
+    .long   Reserved32_IRQHandler                           /* DryIce tamper detect*/
+    .long   PORTA_IRQHandler                                /* Pin detect Port A*/
+    .long   PORTB_IRQHandler                                /* Pin detect Port B*/
+    .long   PORTC_IRQHandler                                /* Pin detect Port C*/
+    .long   PORTD_IRQHandler                                /* Pin detect Port D*/
+    .long   PORTE_IRQHandler                                /* Pin detect Port E*/
+    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup*/
+    .long   LTC0_IRQHandler                                 /* Low power trusted cryptographic*/
+    .long   USB0_IRQHandler                                 /* USB OTG interrupt*/
+    .long   ADC0_IRQHandler                                 /* Analog-to-Digital Converter 0*/
+    .long   LPTMR0_IRQHandler                               /* Low-Power Timer 0*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds*/
+    .long   INTMUX0_0_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-0*/
+    .long   INTMUX0_1_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-1*/
+    .long   INTMUX0_2_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-2*/
+    .long   INTMUX0_3_IRQHandler                            /* Selectable peripheral interrupt INTMUX0-3*/
+    .long   LPTMR1_IRQHandler                               /* Low-Power Timer 1 (INTMUX source IRQ0)*/
+    .long   Reserved49_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ1)*/
+    .long   Reserved50_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ2)*/
+    .long   Reserved51_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ3)*/
+    .long   SPI1_IRQHandler                                 /* Serial Peripheral Interface 1 (INTMUX source IRQ4)*/
+    .long   LPUART2_IRQHandler                              /* LPUART2 status and error (INTMUX source IRQ5)*/
+    .long   EMVSIM1_IRQHandler                              /* EMVSIM1 common interrupt (INTMUX source IRQ6)*/
+    .long   I2C1_IRQHandler                                 /* Inter-Integrated Circuit 1 (INTMUX source IRQ7)*/
+    .long   TSI0_IRQHandler                                 /* Touch Sensing Input 0 (INTMUX source IRQ8)*/
+    .long   PMC_IRQHandler                                  /* PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)*/
+    .long   FTFA_IRQHandler                                 /* FTFA command complete/read collision (INTMUX source IRQ10)*/
+    .long   MCG_IRQHandler                                  /* Multipurpose clock generator (INTMUX source IRQ11)*/
+    .long   WDOG_EWM_IRQHandler                             /* Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)*/
+    .long   DAC0_IRQHandler                                 /* Digital-to-analog converter 0 (INTMUX source IRQ13)*/
+    .long   TRNG0_IRQHandler                                /* True randon number generator (INTMUX source IRQ14)*/
+    .long   Reserved63_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ15)*/
+    .long   CMP0_IRQHandler                                 /* Comparator 0 (INTMUX source IRQ16)*/
+    .long   Reserved65_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ17)*/
+    .long   RTC_Alarm_IRQHandler                            /* Real time clock (INTMUX source IRQ18)*/
+    .long   Reserved67_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ19)*/
+    .long   Reserved68_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ20)*/
+    .long   Reserved69_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ21)*/
+    .long   Reserved70_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ22)*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ23)*/
+    .long   DMA4_IRQHandler                                 /* DMA channel 4 transfer complete (INTMUX source IRQ24)*/
+    .long   DMA5_IRQHandler                                 /* DMA channel 5 transfer complete (INTMUX source IRQ25)*/
+    .long   DMA6_IRQHandler                                 /* DMA channel 6 transfer complete (INTMUX source IRQ26)*/
+    .long   DMA7_IRQHandler                                 /* DMA channel 7 transfer complete (INTMUX source IRQ27)*/
+    .long   Reserved76_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ28)*/
+    .long   Reserved77_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ29)*/
+    .long   Reserved78_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ30)*/
+    .long   Reserved79_IRQHandler                           /* Reserved interrupt (INTMUX source IRQ31)*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFF3DFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+    .equ    VTOR, 0xE000ED08
+    ldr     r0, =VTOR
+    ldr     r1, =__isr_vector
+    str     r1, [r0]
+#ifndef __NO_SYSTEM_INIT
+    ldr   r0,=SystemInit
+    blx   r0
+#endif
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble     .LC0
+
+.LC1:
+    subs    r3, 4
+    ldr    r0, [r1,r3]
+    str    r0, [r2,r3]
+    bgt    .LC1
+.LC0:
+
+#ifdef __STARTUP_CLEAR_BSS
+/*     This part of work usually is done in C library startup code. Otherwise,
+ *     define this macro to enable it in this startup.
+ *
+ *     Loop to zero out BSS section, which uses following symbols
+ *     in linker script:
+ *      __bss_start__: start of BSS section. Must align to 4
+ *      __bss_end__: end of BSS section. Must align to 4
+ */
+    ldr r1, =__bss_start__
+    ldr r2, =__bss_end__
+
+    subs    r2, r1
+    ble .LC3
+
+    movs    r0, 0
+.LC2:
+    str r0, [r1, r2]
+    subs    r2, 4
+    bge .LC2
+.LC3:
+#endif
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    ldr   r0,=__START
+    blx   r0
+#else
+    ldr   r0,=__libc_init_array
+    blx   r0
+    ldr   r0,=main
+    bx    r0
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    ldr r0, =DefaultISR
+    bx r0
+    .size DefaultISR, . - DefaultISR
+
+    .align 1
+    .thumb_func
+    .weak NMI_Handler
+    .type NMI_Handler, %function
+NMI_Handler:
+    ldr   r0,=NMI_Handler
+    bx    r0
+    .size NMI_Handler, . - NMI_Handler
+
+    .align 1
+    .thumb_func
+    .weak HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    ldr   r0,=HardFault_Handler
+    bx    r0
+    .size HardFault_Handler, . - HardFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak SVC_Handler
+    .type SVC_Handler, %function
+SVC_Handler:
+    ldr   r0,=SVC_Handler
+    bx    r0
+    .size SVC_Handler, . - SVC_Handler
+
+    .align 1
+    .thumb_func
+    .weak PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    ldr   r0,=PendSV_Handler
+    bx    r0
+    .size PendSV_Handler, . - PendSV_Handler
+
+    .align 1
+    .thumb_func
+    .weak SysTick_Handler
+    .type SysTick_Handler, %function
+SysTick_Handler:
+    ldr   r0,=SysTick_Handler
+    bx    r0
+    .size SysTick_Handler, . - SysTick_Handler
+
+    .align 1
+    .thumb_func
+    .weak DMA0_DMA4_IRQHandler
+    .type DMA0_DMA4_IRQHandler, %function
+DMA0_DMA4_IRQHandler:
+    ldr   r0,=DMA0_DMA4_DriverIRQHandler
+    bx    r0
+    .size DMA0_DMA4_IRQHandler, . - DMA0_DMA4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA1_DMA5_IRQHandler
+    .type DMA1_DMA5_IRQHandler, %function
+DMA1_DMA5_IRQHandler:
+    ldr   r0,=DMA1_DMA5_DriverIRQHandler
+    bx    r0
+    .size DMA1_DMA5_IRQHandler, . - DMA1_DMA5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA2_DMA6_IRQHandler
+    .type DMA2_DMA6_IRQHandler, %function
+DMA2_DMA6_IRQHandler:
+    ldr   r0,=DMA2_DMA6_DriverIRQHandler
+    bx    r0
+    .size DMA2_DMA6_IRQHandler, . - DMA2_DMA6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA3_DMA7_IRQHandler
+    .type DMA3_DMA7_IRQHandler, %function
+DMA3_DMA7_IRQHandler:
+    ldr   r0,=DMA3_DMA7_DriverIRQHandler
+    bx    r0
+    .size DMA3_DMA7_IRQHandler, . - DMA3_DMA7_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA_Error_IRQHandler
+    .type DMA_Error_IRQHandler, %function
+DMA_Error_IRQHandler:
+    ldr   r0,=DMA_Error_DriverIRQHandler
+    bx    r0
+    .size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXIO0_IRQHandler
+    .type FLEXIO0_IRQHandler, %function
+FLEXIO0_IRQHandler:
+    ldr   r0,=FLEXIO0_DriverIRQHandler
+    bx    r0
+    .size FLEXIO0_IRQHandler, . - FLEXIO0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SPI0_IRQHandler
+    .type SPI0_IRQHandler, %function
+SPI0_IRQHandler:
+    ldr   r0,=SPI0_DriverIRQHandler
+    bx    r0
+    .size SPI0_IRQHandler, . - SPI0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART0_IRQHandler
+    .type LPUART0_IRQHandler, %function
+LPUART0_IRQHandler:
+    ldr   r0,=LPUART0_DriverIRQHandler
+    bx    r0
+    .size LPUART0_IRQHandler, . - LPUART0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART1_IRQHandler
+    .type LPUART1_IRQHandler, %function
+LPUART1_IRQHandler:
+    ldr   r0,=LPUART1_DriverIRQHandler
+    bx    r0
+    .size LPUART1_IRQHandler, . - LPUART1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak I2C0_IRQHandler
+    .type I2C0_IRQHandler, %function
+I2C0_IRQHandler:
+    ldr   r0,=I2C0_DriverIRQHandler
+    bx    r0
+    .size I2C0_IRQHandler, . - I2C0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak QSPI0_IRQHandler
+    .type QSPI0_IRQHandler, %function
+QSPI0_IRQHandler:
+    ldr   r0,=QSPI0_DriverIRQHandler
+    bx    r0
+    .size QSPI0_IRQHandler, . - QSPI0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak INTMUX0_0_IRQHandler
+    .type INTMUX0_0_IRQHandler, %function
+INTMUX0_0_IRQHandler:
+    ldr   r0,=INTMUX0_0_DriverIRQHandler
+    bx    r0
+    .size INTMUX0_0_IRQHandler, . - INTMUX0_0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak INTMUX0_1_IRQHandler
+    .type INTMUX0_1_IRQHandler, %function
+INTMUX0_1_IRQHandler:
+    ldr   r0,=INTMUX0_1_DriverIRQHandler
+    bx    r0
+    .size INTMUX0_1_IRQHandler, . - INTMUX0_1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak INTMUX0_2_IRQHandler
+    .type INTMUX0_2_IRQHandler, %function
+INTMUX0_2_IRQHandler:
+    ldr   r0,=INTMUX0_2_DriverIRQHandler
+    bx    r0
+    .size INTMUX0_2_IRQHandler, . - INTMUX0_2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak INTMUX0_3_IRQHandler
+    .type INTMUX0_3_IRQHandler, %function
+INTMUX0_3_IRQHandler:
+    ldr   r0,=INTMUX0_3_DriverIRQHandler
+    bx    r0
+    .size INTMUX0_3_IRQHandler, . - INTMUX0_3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SPI1_IRQHandler
+    .type SPI1_IRQHandler, %function
+SPI1_IRQHandler:
+    ldr   r0,=SPI1_DriverIRQHandler
+    bx    r0
+    .size SPI1_IRQHandler, . - SPI1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak LPUART2_IRQHandler
+    .type LPUART2_IRQHandler, %function
+LPUART2_IRQHandler:
+    ldr   r0,=LPUART2_DriverIRQHandler
+    bx    r0
+    .size LPUART2_IRQHandler, . - LPUART2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak I2C1_IRQHandler
+    .type I2C1_IRQHandler, %function
+I2C1_IRQHandler:
+    ldr   r0,=I2C1_DriverIRQHandler
+    bx    r0
+    .size I2C1_IRQHandler, . - I2C1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA4_IRQHandler
+    .type DMA4_IRQHandler, %function
+DMA4_IRQHandler:
+    ldr   r0,=DMA4_DriverIRQHandler
+    bx    r0
+    .size DMA4_IRQHandler, . - DMA4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA5_IRQHandler
+    .type DMA5_IRQHandler, %function
+DMA5_IRQHandler:
+    ldr   r0,=DMA5_DriverIRQHandler
+    bx    r0
+    .size DMA5_IRQHandler, . - DMA5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA6_IRQHandler
+    .type DMA6_IRQHandler, %function
+DMA6_IRQHandler:
+    ldr   r0,=DMA6_DriverIRQHandler
+    bx    r0
+    .size DMA6_IRQHandler, . - DMA6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA7_IRQHandler
+    .type DMA7_IRQHandler, %function
+DMA7_IRQHandler:
+    ldr   r0,=DMA7_DriverIRQHandler
+    bx    r0
+    .size DMA7_IRQHandler, . - DMA7_IRQHandler
+
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler  handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    DMA0_DMA4_DriverIRQHandler
+    def_irq_handler    DMA1_DMA5_DriverIRQHandler
+    def_irq_handler    DMA2_DMA6_DriverIRQHandler
+    def_irq_handler    DMA3_DMA7_DriverIRQHandler
+    def_irq_handler    DMA_Error_DriverIRQHandler
+    def_irq_handler    FLEXIO0_DriverIRQHandler
+    def_irq_handler    TPM0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    PIT0_IRQHandler
+    def_irq_handler    SPI0_DriverIRQHandler
+    def_irq_handler    EMVSIM0_IRQHandler
+    def_irq_handler    LPUART0_DriverIRQHandler
+    def_irq_handler    LPUART1_DriverIRQHandler
+    def_irq_handler    I2C0_DriverIRQHandler
+    def_irq_handler    QSPI0_DriverIRQHandler
+    def_irq_handler    Reserved32_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    LTC0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    INTMUX0_0_DriverIRQHandler
+    def_irq_handler    INTMUX0_1_DriverIRQHandler
+    def_irq_handler    INTMUX0_2_DriverIRQHandler
+    def_irq_handler    INTMUX0_3_DriverIRQHandler
+    def_irq_handler    LPTMR1_IRQHandler
+    def_irq_handler    Reserved49_IRQHandler
+    def_irq_handler    Reserved50_IRQHandler
+    def_irq_handler    Reserved51_IRQHandler
+    def_irq_handler    SPI1_DriverIRQHandler
+    def_irq_handler    LPUART2_DriverIRQHandler
+    def_irq_handler    EMVSIM1_IRQHandler
+    def_irq_handler    I2C1_DriverIRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    PMC_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    TRNG0_IRQHandler
+    def_irq_handler    Reserved63_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    Reserved65_IRQHandler
+    def_irq_handler    RTC_Alarm_IRQHandler
+    def_irq_handler    Reserved67_IRQHandler
+    def_irq_handler    Reserved68_IRQHandler
+    def_irq_handler    Reserved69_IRQHandler
+    def_irq_handler    Reserved70_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DMA4_DriverIRQHandler
+    def_irq_handler    DMA5_DriverIRQHandler
+    def_irq_handler    DMA6_DriverIRQHandler
+    def_irq_handler    DMA7_DriverIRQHandler
+    def_irq_handler    Reserved76_IRQHandler
+    def_irq_handler    Reserved77_IRQHandler
+    def_irq_handler    Reserved78_IRQHandler
+    def_irq_handler    Reserved79_IRQHandler
+
+    .end
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/MKL82Z128xxx7.icf b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/MKL82Z128xxx7.icf
new file mode 100644
index 00000000000..0fd080af98b
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/MKL82Z128xxx7.icf
@@ -0,0 +1,139 @@
+/*
+** ###################################################################
+**     Processors:          MKL82Z128VLH7
+**                          MKL82Z128VLK7
+**                          MKL82Z128VLL7
+**                          MKL82Z128VMC7
+**                          MKL82Z128VMP7
+**
+**     Compiler:            IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    KL82P121M72SF0RM, Rev.2 November 2015
+**     Version:             rev. 1.5, 2015-09-24
+**     Build:               b160406
+**
+**     Abstract:
+**         Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+** ###################################################################
+*/
+define symbol __ram_vector_table__ = 1;
+
+/* Heap 1/4 of ram and stack 1/8 */
+define symbol __stack_size__=0x3000;
+define symbol __heap_size__=0x6000;
+
+define symbol __ram_vector_table_size__ =  isdefinedsymbol(__ram_vector_table__) ? 0x00000140 : 0;
+define symbol __ram_vector_table_offset__ =  isdefinedsymbol(__ram_vector_table__) ? 0x0000013F : 0;
+
+define symbol m_interrupts_start       = 0x00000000;
+define symbol m_interrupts_end         = 0x0000013F;
+
+define symbol m_bootloader_config_start = 0x000003C0;
+define symbol m_bootloader_config_end  = 0x000003FF;
+
+define symbol m_flash_config_start     = 0x00000400;
+define symbol m_flash_config_end       = 0x0000040F;
+
+define symbol m_text_start             = 0x00000410;
+define symbol m_text_end               = 0x0001FFFF;
+
+define symbol m_interrupts_ram_start   = 0x1FFFA000;
+define symbol m_interrupts_ram_end     = 0x1FFFA000 + __ram_vector_table_offset__;
+
+define symbol m_data_start             = m_interrupts_ram_start + __ram_vector_table_size__;
+define symbol m_data_end               = 0x20011FFF;
+
+if (isdefinedsymbol(__usb_use_usbram__)) {
+  define symbol m_usb_sram_start       = 0x40100000;
+  define symbol m_usb_sram_end         = 0x401007FF;
+}
+
+/* USB BDT size */
+define symbol usb_bdt_size             = 0x200;
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+  define symbol __size_cstack__        = __stack_size__;
+} else {
+  define symbol __size_cstack__        = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+  define symbol __size_heap__          = __heap_size__;
+} else {
+  define symbol __size_heap__          = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE  = m_interrupts_start;
+define exported symbol __VECTOR_RAM    = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
+
+define memory mem with size = 4G;
+define region m_bootloader_config_region = mem:[from m_bootloader_config_start to m_bootloader_config_end];
+define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end];
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+                          | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block RW        { readwrite };
+define block ZI        { zi };
+
+/* regions for USB */
+if (isdefinedsymbol(__usb_use_usbram__)) {
+  define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
+  define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
+  place in USB_BDT_region                   { section m_usb_bdt };
+  place in USB_SRAM_region                  { section m_usb_global };
+}
+
+initialize by copy { readwrite, section .textrw };
+if (isdefinedsymbol(__usb_use_usbram__)) {
+  do not initialize  { section .noinit, section m_usb_bdt, section m_usb_global };
+} else {
+  do not initialize  { section .noinit };
+}
+
+place at address mem: m_interrupts_start    { readonly section .intvec };
+place in m_bootloader_config_region         { section BootloaderConfig };
+place in m_flash_config_region              { section FlashConfig };
+place in TEXT_region                        { readonly };
+place in DATA_region                        { block RW };
+place in DATA_region                        { block ZI };
+place in DATA_region                        { last block HEAP };
+place in CSTACK_region                      { block CSTACK };
+place in m_interrupts_ram_region            { section m_interrupts_ram };
+
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/startup_MKL82Z7.s b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/startup_MKL82Z7.s
new file mode 100644
index 00000000000..8e9c43da553
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/startup_MKL82Z7.s
@@ -0,0 +1,479 @@
+; ---------------------------------------------------------------------------------------
+;  @file:    startup_MKL82Z7.s
+;  @purpose: CMSIS Cortex-M0P Core Device Startup File
+;            MKL82Z7
+;  @version: 1.5
+;  @date:    2015-9-24
+;  @build:   b151217
+; ---------------------------------------------------------------------------------------
+;
+; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; o Redistributions of source code must retain the above copyright notice, this list
+;   of conditions and the following disclaimer.
+;
+; o Redistributions in binary form must reproduce the above copyright notice, this
+;   list of conditions and the following disclaimer in the documentation and/or
+;   other materials provided with the distribution.
+;
+; o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+;   contributors may be used to endorse or promote products derived from this
+;   software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler                                   ;NMI Handler
+        DCD     HardFault_Handler                             ;Hard Fault Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+__vector_table_0x1c
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     SVC_Handler                                   ;SVCall Handler
+        DCD     0                                             ;Reserved
+        DCD     0                                             ;Reserved
+        DCD     PendSV_Handler                                ;PendSV Handler
+        DCD     SysTick_Handler                               ;SysTick Handler
+
+                                                              ;External Interrupts
+        DCD     DMA0_DMA4_IRQHandler                          ;DMA channel 0, 4 transfer complete
+        DCD     DMA1_DMA5_IRQHandler                          ;DMA channel 1, 5 transfer complete
+        DCD     DMA2_DMA6_IRQHandler                          ;DMA channel 2, 6 transfer complete
+        DCD     DMA3_DMA7_IRQHandler                          ;DMA channel 3, 7 transfer complete
+        DCD     DMA_Error_IRQHandler                          ;DMA channel 0 - 7 error
+        DCD     FLEXIO0_IRQHandler                            ;Flexible IO
+        DCD     TPM0_IRQHandler                               ;Timer/PWM module 0
+        DCD     TPM1_IRQHandler                               ;Timer/PWM module 1
+        DCD     TPM2_IRQHandler                               ;Timer/PWM module 2
+        DCD     PIT0_IRQHandler                               ;Periodic Interrupt Timer 0
+        DCD     SPI0_IRQHandler                               ;Serial Peripheral Interface 0
+        DCD     EMVSIM0_IRQHandler                            ;EMVSIM0 common interrupt
+        DCD     LPUART0_IRQHandler                            ;LPUART0 status and error
+        DCD     LPUART1_IRQHandler                            ;LPUART1 status and error
+        DCD     I2C0_IRQHandler                               ;Inter-Integrated Circuit 0
+        DCD     QSPI0_IRQHandler                              ;QuadSPI0 interrupt
+        DCD     Reserved32_IRQHandler                         ;DryIce tamper detect
+        DCD     PORTA_IRQHandler                              ;Pin detect Port A
+        DCD     PORTB_IRQHandler                              ;Pin detect Port B
+        DCD     PORTC_IRQHandler                              ;Pin detect Port C
+        DCD     PORTD_IRQHandler                              ;Pin detect Port D
+        DCD     PORTE_IRQHandler                              ;Pin detect Port E
+        DCD     LLWU_IRQHandler                               ;Low Leakage Wakeup
+        DCD     LTC0_IRQHandler                               ;Low power trusted cryptographic
+        DCD     USB0_IRQHandler                               ;USB OTG interrupt
+        DCD     ADC0_IRQHandler                               ;Analog-to-Digital Converter 0
+        DCD     LPTMR0_IRQHandler                             ;Low-Power Timer 0
+        DCD     RTC_Seconds_IRQHandler                        ;RTC seconds
+        DCD     INTMUX0_0_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-0
+        DCD     INTMUX0_1_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-1
+        DCD     INTMUX0_2_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-2
+        DCD     INTMUX0_3_IRQHandler                          ;Selectable peripheral interrupt INTMUX0-3
+        DCD     LPTMR1_IRQHandler                             ;Low-Power Timer 1 (INTMUX source IRQ0)
+        DCD     Reserved49_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ1)
+        DCD     Reserved50_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ2)
+        DCD     Reserved51_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ3)
+        DCD     SPI1_IRQHandler                               ;Serial Peripheral Interface 1 (INTMUX source IRQ4)
+        DCD     LPUART2_IRQHandler                            ;LPUART2 status and error (INTMUX source IRQ5)
+        DCD     EMVSIM1_IRQHandler                            ;EMVSIM1 common interrupt (INTMUX source IRQ6)
+        DCD     I2C1_IRQHandler                               ;Inter-Integrated Circuit 1 (INTMUX source IRQ7)
+        DCD     TSI0_IRQHandler                               ;Touch Sensing Input 0 (INTMUX source IRQ8)
+        DCD     PMC_IRQHandler                                ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9)
+        DCD     FTFA_IRQHandler                               ;FTFA command complete/read collision (INTMUX source IRQ10)
+        DCD     MCG_IRQHandler                                ;Multipurpose clock generator (INTMUX source IRQ11)
+        DCD     WDOG_EWM_IRQHandler                           ;Single interrupt vector for  WDOG and EWM (INTMUX source IRQ12)
+        DCD     DAC0_IRQHandler                               ;Digital-to-analog converter 0 (INTMUX source IRQ13)
+        DCD     TRNG0_IRQHandler                              ;True randon number generator (INTMUX source IRQ14)
+        DCD     Reserved63_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ15)
+        DCD     CMP0_IRQHandler                               ;Comparator 0 (INTMUX source IRQ16)
+        DCD     Reserved65_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ17)
+        DCD     RTC_Alarm_IRQHandler                          ;Real time clock (INTMUX source IRQ18)
+        DCD     Reserved67_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ19)
+        DCD     Reserved68_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ20)
+        DCD     Reserved69_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ21)
+        DCD     Reserved70_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ22)
+        DCD     Reserved71_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ23)
+        DCD     DMA4_IRQHandler                               ;DMA channel 4 transfer complete (INTMUX source IRQ24)
+        DCD     DMA5_IRQHandler                               ;DMA channel 5 transfer complete (INTMUX source IRQ25)
+        DCD     DMA6_IRQHandler                               ;DMA channel 6 transfer complete (INTMUX source IRQ26)
+        DCD     DMA7_IRQHandler                               ;DMA channel 7 transfer complete (INTMUX source IRQ27)
+        DCD     Reserved76_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ28)
+        DCD     Reserved77_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ29)
+        DCD     Reserved78_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ30)
+        DCD     Reserved79_IRQHandler                         ;Reserved interrupt (INTMUX source IRQ31)
+__Vectors_End
+
+        SECTION FlashConfig:CODE
+__FlashConfig
+        DCD 0xFFFFFFFF
+        DCD 0xFFFFFFFF
+        DCD 0xFFFFFFFF
+        DCD 0xFFFF3DFE
+__FlashConfig_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        CPSID   I               ; Mask interrupts
+        LDR     R0, =0xE000ED08
+        LDR     R1, =__vector_table
+        STR     R1, [R0]
+        LDR     R0, =SystemInit
+        BLX     R0
+        CPSIE   I               ; Unmask interrupts
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK DMA0_DMA4_IRQHandler
+        PUBWEAK DMA0_DMA4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_DMA4_IRQHandler
+        LDR     R0, =DMA0_DMA4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA1_DMA5_IRQHandler
+        PUBWEAK DMA1_DMA5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA1_DMA5_IRQHandler
+        LDR     R0, =DMA1_DMA5_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA2_DMA6_IRQHandler
+        PUBWEAK DMA2_DMA6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA2_DMA6_IRQHandler
+        LDR     R0, =DMA2_DMA6_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA3_DMA7_IRQHandler
+        PUBWEAK DMA3_DMA7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA3_DMA7_IRQHandler
+        LDR     R0, =DMA3_DMA7_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA_Error_IRQHandler
+        PUBWEAK DMA_Error_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA_Error_IRQHandler
+        LDR     R0, =DMA_Error_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK FLEXIO0_IRQHandler
+        PUBWEAK FLEXIO0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXIO0_IRQHandler
+        LDR     R0, =FLEXIO0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK TPM0_IRQHandler
+        PUBWEAK TPM1_IRQHandler
+        PUBWEAK TPM2_IRQHandler
+        PUBWEAK PIT0_IRQHandler
+        PUBWEAK SPI0_IRQHandler
+        PUBWEAK SPI0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SPI0_IRQHandler
+        LDR     R0, =SPI0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK EMVSIM0_IRQHandler
+        PUBWEAK LPUART0_IRQHandler
+        PUBWEAK LPUART0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+LPUART0_IRQHandler
+        LDR     R0, =LPUART0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK LPUART1_IRQHandler
+        PUBWEAK LPUART1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+LPUART1_IRQHandler
+        LDR     R0, =LPUART1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK I2C0_IRQHandler
+        PUBWEAK I2C0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+I2C0_IRQHandler
+        LDR     R0, =I2C0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK QSPI0_IRQHandler
+        PUBWEAK QSPI0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+QSPI0_IRQHandler
+        LDR     R0, =QSPI0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK Reserved32_IRQHandler
+        PUBWEAK PORTA_IRQHandler
+        PUBWEAK PORTB_IRQHandler
+        PUBWEAK PORTC_IRQHandler
+        PUBWEAK PORTD_IRQHandler
+        PUBWEAK PORTE_IRQHandler
+        PUBWEAK LLWU_IRQHandler
+        PUBWEAK LTC0_IRQHandler
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK ADC0_IRQHandler
+        PUBWEAK LPTMR0_IRQHandler
+        PUBWEAK RTC_Seconds_IRQHandler
+        PUBWEAK INTMUX0_0_IRQHandler
+        PUBWEAK INTMUX0_0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+INTMUX0_0_IRQHandler
+        LDR     R0, =INTMUX0_0_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK INTMUX0_1_IRQHandler
+        PUBWEAK INTMUX0_1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+INTMUX0_1_IRQHandler
+        LDR     R0, =INTMUX0_1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK INTMUX0_2_IRQHandler
+        PUBWEAK INTMUX0_2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+INTMUX0_2_IRQHandler
+        LDR     R0, =INTMUX0_2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK INTMUX0_3_IRQHandler
+        PUBWEAK INTMUX0_3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+INTMUX0_3_IRQHandler
+        LDR     R0, =INTMUX0_3_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK LPTMR1_IRQHandler
+        PUBWEAK Reserved49_IRQHandler
+        PUBWEAK Reserved50_IRQHandler
+        PUBWEAK Reserved51_IRQHandler
+        PUBWEAK SPI1_IRQHandler
+        PUBWEAK SPI1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SPI1_IRQHandler
+        LDR     R0, =SPI1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK LPUART2_IRQHandler
+        PUBWEAK LPUART2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+LPUART2_IRQHandler
+        LDR     R0, =LPUART2_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK EMVSIM1_IRQHandler
+        PUBWEAK I2C1_IRQHandler
+        PUBWEAK I2C1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+I2C1_IRQHandler
+        LDR     R0, =I2C1_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK TSI0_IRQHandler
+        PUBWEAK PMC_IRQHandler
+        PUBWEAK FTFA_IRQHandler
+        PUBWEAK MCG_IRQHandler
+        PUBWEAK WDOG_EWM_IRQHandler
+        PUBWEAK DAC0_IRQHandler
+        PUBWEAK TRNG0_IRQHandler
+        PUBWEAK Reserved63_IRQHandler
+        PUBWEAK CMP0_IRQHandler
+        PUBWEAK Reserved65_IRQHandler
+        PUBWEAK RTC_Alarm_IRQHandler
+        PUBWEAK Reserved67_IRQHandler
+        PUBWEAK Reserved68_IRQHandler
+        PUBWEAK Reserved69_IRQHandler
+        PUBWEAK Reserved70_IRQHandler
+        PUBWEAK Reserved71_IRQHandler
+        PUBWEAK DMA4_IRQHandler
+        PUBWEAK DMA4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA4_IRQHandler
+        LDR     R0, =DMA4_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA5_IRQHandler
+        PUBWEAK DMA5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA5_IRQHandler
+        LDR     R0, =DMA5_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA6_IRQHandler
+        PUBWEAK DMA6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA6_IRQHandler
+        LDR     R0, =DMA6_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK DMA7_IRQHandler
+        PUBWEAK DMA7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA7_IRQHandler
+        LDR     R0, =DMA7_DriverIRQHandler
+        BX      R0
+
+        PUBWEAK Reserved76_IRQHandler
+        PUBWEAK Reserved77_IRQHandler
+        PUBWEAK Reserved78_IRQHandler
+        PUBWEAK Reserved79_IRQHandler
+        PUBWEAK DefaultISR
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_DMA4_DriverIRQHandler
+DMA1_DMA5_DriverIRQHandler
+DMA2_DMA6_DriverIRQHandler
+DMA3_DMA7_DriverIRQHandler
+DMA_Error_DriverIRQHandler
+FLEXIO0_DriverIRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+PIT0_IRQHandler
+SPI0_DriverIRQHandler
+EMVSIM0_IRQHandler
+LPUART0_DriverIRQHandler
+LPUART1_DriverIRQHandler
+I2C0_DriverIRQHandler
+QSPI0_DriverIRQHandler
+Reserved32_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+LLWU_IRQHandler
+LTC0_IRQHandler
+USB0_IRQHandler
+ADC0_IRQHandler
+LPTMR0_IRQHandler
+RTC_Seconds_IRQHandler
+INTMUX0_0_DriverIRQHandler
+INTMUX0_1_DriverIRQHandler
+INTMUX0_2_DriverIRQHandler
+INTMUX0_3_DriverIRQHandler
+LPTMR1_IRQHandler
+Reserved49_IRQHandler
+Reserved50_IRQHandler
+Reserved51_IRQHandler
+SPI1_DriverIRQHandler
+LPUART2_DriverIRQHandler
+EMVSIM1_IRQHandler
+I2C1_DriverIRQHandler
+TSI0_IRQHandler
+PMC_IRQHandler
+FTFA_IRQHandler
+MCG_IRQHandler
+WDOG_EWM_IRQHandler
+DAC0_IRQHandler
+TRNG0_IRQHandler
+Reserved63_IRQHandler
+CMP0_IRQHandler
+Reserved65_IRQHandler
+RTC_Alarm_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+DMA4_DriverIRQHandler
+DMA5_DriverIRQHandler
+DMA6_DriverIRQHandler
+DMA7_DriverIRQHandler
+Reserved76_IRQHandler
+Reserved77_IRQHandler
+Reserved78_IRQHandler
+Reserved79_IRQHandler
+DefaultISR
+        LDR R0, =DefaultISR
+        BX R0
+
+        END
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis.h
new file mode 100644
index 00000000000..7423a125ba6
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "fsl_device_registers.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis_nvic.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis_nvic.c
new file mode 100644
index 00000000000..59b37502b22
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis_nvic.c
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    InstallIRQHandler(IRQn, vector);
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + 16];
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis_nvic.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis_nvic.h
new file mode 100644
index 00000000000..64f36b31671
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS      (16 + 32)   // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET  16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/fsl_device_registers.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/fsl_device_registers.h
new file mode 100644
index 00000000000..3ecd672c3cb
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/fsl_device_registers.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MKL82Z128VLH7) || defined(CPU_MKL82Z128VLK7) || defined(CPU_MKL82Z128VLL7) || \
+    defined(CPU_MKL82Z128VMC7) || defined(CPU_MKL82Z128VMP7))
+
+#define KL82Z7_SERIES
+
+/* CMSIS-style register definitions */
+#include "MKL82Z7.h"
+/* CPU specific feature definitions */
+#include "MKL82Z7_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/system_MKL82Z7.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/system_MKL82Z7.c
new file mode 100644
index 00000000000..223fce6b56b
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/system_MKL82Z7.c
@@ -0,0 +1,293 @@
+/*
+** ###################################################################
+**     Processors:          MKL82Z128VLH7
+**                          MKL82Z128VLK7
+**                          MKL82Z128VLL7
+**                          MKL82Z128VMC7
+**                          MKL82Z128VMP7
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL82P121M72SF0RM, Rev.2 November 2015
+**     Version:             rev. 1.5, 2015-09-24
+**     Build:               b151217
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-18)
+**         Initial version.
+**     - rev. 1.1 (2015-05-04)
+**         Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
+**     - rev. 1.2 (2015-08-11)
+**         Correct clock configuration.
+**     - rev. 1.3 (2015-08-20)
+**         Align with RM Rev.1.
+**     - rev. 1.4 (2015-08-28)
+**         Update LPUART to add FIFO.
+**     - rev. 1.5 (2015-09-24)
+**         Update to align with RM Rev.1.2.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL82Z7
+ * @version 1.5
+ * @date 2015-09-24
+ * @brief Device specific configuration file for MKL82Z7 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+
+
+/*!
+ * @brief Defines the structure to set the Bootloader Configuration Area
+ *
+ * This type of variable is used to set the Bootloader Configuration Area
+ * of the chip.
+ */
+typedef struct SystemBootloaderConfig
+{
+  uint32_t      tag;                /*!< Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
+  uint32_t      crcStartAddress;    /*!< Start address for application image CRC check. If the bits are all set then Kinetis bootloader by default will not perform any CRC check. */
+  uint32_t      crcByteCount;       /*!< Byte count for application image CRC check. If the bits are all set then Kinetis bootloader by default will not prform any CRC check. */
+  uint32_t      crcExpectedValue;   /*!< Expected CRC value for application CRC check. If the bits are all set then Kinetis bootloader by default will not perform any CRC check.*/
+  uint8_t       enabledPeripherals; /*!< Bitfield of peripherals to enable.
+                                         bit 0 - LPUART, bit 1 - I2C, bit 2 - SPI, bit 4 - USB
+                                         Kinetis bootloader will enable the peripheral if corresponding bit is set to 1. */
+  uint8_t       i2cSlaveAddress;    /*!< If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C slave address */
+  uint16_t      peripheralDetectionTimeoutMs; /*!< Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds. */
+  uint16_t      usbVid;             /*!< Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to 0x15A2. */
+  uint16_t      usbPid;             /*!< Sets the USB Product ID reported by the device during enumeration. */
+  uint32_t      usbStringsPointer;  /*!< Sets the USB Strings reported by the device during enumeration. */
+  uint8_t       clockFlags;         /*!< The flags in the clockFlags configuration field are enabled if the corresponding bit is cleared (0).
+	                                       bit 0 - HighSpeed Enable high speed mode (i.e., 48 MHz).	*/
+  uint8_t       clockDivider;       /*!< Inverted value of the divider to use for core and bus clocks when in high speed mode */
+  uint8_t       bootFlags;          /*!< If bit 0 is cleared, then Kinetis bootloader will jump to either Quad SPI Flash or internal flash image depending on FOPT BOOTSRC_SEL bits.
+	                                       If the bit is set, then Kinetis bootloader will prepare for host communication over serial peripherals. */
+  uint8_t       RESERVED1;
+  uint32_t      RESERVED2;
+  uint32_t      keyBlobPointer;     /*!< A pointer to the keyblob data in memory. */
+  uint8_t       RESERVED3[8];
+  uint32_t      qspiConfigBlockPtr; /*!< A pointer to the QSPI config block in internal flash array. */
+  uint8_t       RESERVED4[12];
+} system_bootloader_config_t;
+
+#ifdef BOOTLOADER_CONFIG
+/* Bootlader configuration area */
+  #if defined(__IAR_SYSTEMS_ICC__)
+/* Pragma to place the Bootloader Configuration Array on correct location defined in linker file. */
+#pragma language=extended
+#pragma location = "BootloaderConfig"
+__root const system_bootloader_config_t BootloaderConfig @ "BootloaderConfig" =
+  #elif defined(__GNUC__)
+__attribute__ ((section (".BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig =
+  #elif defined(__CC_ARM)
+__attribute__ ((section ("BootloaderConfig"))) const system_bootloader_config_t BootloaderConfig __attribute__((used)) =
+  #else
+    #error Unsupported compiler!
+  #endif
+{
+    .tag                        = 0x6766636BU, /* Magic Number */
+    .crcStartAddress            = 0xFFFFFFFFU, /* Disable CRC check */
+    .crcByteCount               = 0xFFFFFFFFU, /* Disable CRC check */
+    .crcExpectedValue           = 0xFFFFFFFFU, /* Disable CRC check */
+    .enabledPeripherals         = 0x17,        /* Enable all peripherals */
+    .i2cSlaveAddress            = 0xFF,        /* Use default I2C address */
+    .peripheralDetectionTimeoutMs = 0xFFFFU,   /* Use default timeout */
+    .usbVid                     = 0xFFFFU,     /* Use default USB Vendor ID */
+    .usbPid                     = 0xFFFFU,     /* Use default USB Product ID */
+    .usbStringsPointer          = 0xFFFFFFFFU, /* Use default USB Strings */
+    .clockFlags                 = 0x01,        /* Enable High speed mode */
+    .clockDivider               = 0xFF,        /* Use clock divider 1 */
+    .bootFlags                  = 0x01,        /* Enable communication with host */
+    .keyBlobPointer             = 0xFFFFFFFFU, /* No keyblob data */
+    .qspiConfigBlockPtr         = 0xFFFFFFFFU  /* No QSPI configuration */
+};
+#endif
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+
+#if (DISABLE_WDOG)
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+  /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+  WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
+                 WDOG_STCTRLH_WAITEN_MASK |
+                 WDOG_STCTRLH_STOPEN_MASK |
+                 WDOG_STCTRLH_ALLOWUPDATE_MASK |
+                 WDOG_STCTRLH_CLKSRC_MASK |
+                 0x0100U;
+#endif /* (DISABLE_WDOG) */
+
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+  uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
+  uint16_t Divider;
+
+  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
+    /* Output of FLL or PLL is selected */
+    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
+      /* FLL is selected */
+      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+        case 0x00U:
+          MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+          break;
+        case 0x01U:
+          MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+          break;
+        case 0x02U:
+        default:
+          MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+          break;
+        }
+        if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
+          switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
+          case 0x38U:
+            Divider = 1536U;
+            break;
+          case 0x30U:
+            Divider = 1280U;
+            break;
+          default:
+            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+            break;
+          }
+        } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+          Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+        }
+        MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+        MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+      /* Select correct multiplier to calculate the MCG output clock  */
+      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+        case 0x00U:
+          MCGOUTClock *= 640U;
+          break;
+        case 0x20U:
+          MCGOUTClock *= 1280U;
+          break;
+        case 0x40U:
+          MCGOUTClock *= 1920U;
+          break;
+        case 0x60U:
+          MCGOUTClock *= 2560U;
+          break;
+        case 0x80U:
+          MCGOUTClock *= 732U;
+          break;
+        case 0xA0U:
+          MCGOUTClock *= 1464U;
+          break;
+        case 0xC0U:
+          MCGOUTClock *= 2197U;
+          break;
+        case 0xE0U:
+          MCGOUTClock *= 2929U;
+          break;
+        default:
+          break;
+      }
+    } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+      /* PLL is selected */
+      Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
+      MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+      Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
+      MCGOUTClock *= Divider;          /* Calculate the VCO output clock */
+      MCGOUTClock /= 2;                /* Calculate the MCG output clock */
+    } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
+    /* Internal reference clock is selected */
+    if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
+      MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+      Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+      MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
+    /* External reference clock is selected */
+    switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+    case 0x00U:
+      MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
+      break;
+    case 0x01U:
+      MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+      break;
+    case 0x02U:
+    default:
+      MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+      break;
+    }
+  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    /* Reserved value */
+    return;
+  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+  SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/system_MKL82Z7.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/system_MKL82Z7.h
new file mode 100644
index 00000000000..dedec8709ef
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/device/system_MKL82Z7.h
@@ -0,0 +1,148 @@
+/*
+** ###################################################################
+**     Processors:          MKL82Z128VLH7
+**                          MKL82Z128VLK7
+**                          MKL82Z128VLL7
+**                          MKL82Z128VMC7
+**                          MKL82Z128VMP7
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL82P121M72SF0RM, Rev.2 November 2015
+**     Version:             rev. 1.5, 2015-09-24
+**     Build:               b151217
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2015-04-18)
+**         Initial version.
+**     - rev. 1.1 (2015-05-04)
+**         Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document.
+**     - rev. 1.2 (2015-08-11)
+**         Correct clock configuration.
+**     - rev. 1.3 (2015-08-20)
+**         Align with RM Rev.1.
+**     - rev. 1.4 (2015-08-28)
+**         Update LPUART to add FIFO.
+**     - rev. 1.5 (2015-09-24)
+**         Update to align with RM Rev.1.2.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL82Z7
+ * @version 1.5
+ * @date 2015-09-24
+ * @brief Device specific configuration file for MKL82Z7 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_MKL82Z7_H_
+#define _SYSTEM_MKL82Z7_H_                       /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG                 1
+#endif
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ                12000000U           /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
+#define CPU_XTAL32k_CLK_HZ             32768U              /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz */
+#define CPU_INT_SLOW_CLK_HZ            32768U              /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ            4000000U            /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ             48000000U           /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE            0x0300U             /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE        0xAAU               /* SMC_PMPROT */
+
+#define DEFAULT_SYSTEM_CLOCK           20971520u
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_MKL82Z7_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_adc16.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_adc16.c
new file mode 100644
index 00000000000..4fee1a8503d
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_adc16.c
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_adc16.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for ADC16 module.
+ *
+ * @param base ADC16 peripheral base address
+ */
+static uint32_t ADC16_GetInstance(ADC_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to ADC16 bases for each instance. */
+static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS;
+
+/*! @brief Pointers to ADC16 clocks for each instance. */
+static const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t ADC16_GetInstance(ADC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_ADC16_COUNT; instance++)
+    {
+        if (s_adc16Bases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_ADC16_COUNT);
+
+    return instance;
+}
+
+void ADC16_Init(ADC_Type *base, const adc16_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t tmp32;
+
+    /* Enable the clock. */
+    CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
+
+    /* ADCx_CFG1. */
+    tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution);
+    if (kADC16_LongSampleDisabled != config->longSampleMode)
+    {
+        tmp32 |= ADC_CFG1_ADLSMP_MASK;
+    }
+    tmp32 |= ADC_CFG1_ADIV(config->clockDivider);
+    if (config->enableLowPower)
+    {
+        tmp32 |= ADC_CFG1_ADLPC_MASK;
+    }
+    base->CFG1 = tmp32;
+
+    /* ADCx_CFG2. */
+    tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK);
+    if (kADC16_LongSampleDisabled != config->longSampleMode)
+    {
+        tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode);
+    }
+    if (config->enableHighSpeed)
+    {
+        tmp32 |= ADC_CFG2_ADHSC_MASK;
+    }
+    if (config->enableAsynchronousClock)
+    {
+        tmp32 |= ADC_CFG2_ADACKEN_MASK;
+    }
+    base->CFG2 = tmp32;
+
+    /* ADCx_SC2. */
+    tmp32 = base->SC2 & ~(ADC_SC2_REFSEL_MASK);
+    tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource);
+    base->SC2 = tmp32;
+
+    /* ADCx_SC3. */
+    if (config->enableContinuousConversion)
+    {
+        base->SC3 |= ADC_SC3_ADCO_MASK;
+    }
+    else
+    {
+        base->SC3 &= ~ADC_SC3_ADCO_MASK;
+    }
+}
+
+void ADC16_Deinit(ADC_Type *base)
+{
+    /* Disable the clock. */
+    CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
+}
+
+void ADC16_GetDefaultConfig(adc16_config_t *config)
+{
+    assert(NULL != config);
+
+    config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
+    config->clockSource = kADC16_ClockSourceAsynchronousClock;
+    config->enableAsynchronousClock = true;
+    config->clockDivider = kADC16_ClockDivider8;
+    config->resolution = kADC16_ResolutionSE12Bit;
+    config->longSampleMode = kADC16_LongSampleDisabled;
+    config->enableHighSpeed = false;
+    config->enableLowPower = false;
+    config->enableContinuousConversion = false;
+}
+
+#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
+status_t ADC16_DoAutoCalibration(ADC_Type *base)
+{
+    bool bHWTrigger = false;
+    volatile uint32_t tmp32; /* 'volatile' here is for the dummy read of ADCx_R[0] register. */
+    status_t status = kStatus_Success;
+
+    /* The calibration would be failed when in hardwar mode.
+     * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/
+    if (0U != (ADC_SC2_ADTRG_MASK & base->SC2))
+    {
+        bHWTrigger = true;
+        base->SC2 &= ~ADC_SC2_ADTRG_MASK;
+    }
+
+    /* Clear the CALF and launch the calibration. */
+    base->SC3 |= ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK;
+    while (0U == (kADC16_ChannelConversionDoneFlag & ADC16_GetChannelStatusFlags(base, 0U)))
+    {
+        /* Check the CALF when the calibration is active. */
+        if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base)))
+        {
+            status = kStatus_Fail;
+            break;
+        }
+    }
+    tmp32 = base->R[0]; /* Dummy read to clear COCO caused by calibration. */
+
+    /* Restore the hardware trigger setting if it was enabled before. */
+    if (bHWTrigger)
+    {
+        base->SC2 |= ADC_SC2_ADTRG_MASK;
+    }
+    /* Check the CALF at the end of calibration. */
+    if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base)))
+    {
+        status = kStatus_Fail;
+    }
+    if (kStatus_Success != status) /* Check if the calibration process is succeed. */
+    {
+        return status;
+    }
+
+    /* Calculate the calibration values. */
+    tmp32 = base->CLP0 + base->CLP1 + base->CLP2 + base->CLP3 + base->CLP4 + base->CLPS;
+    tmp32 = 0x8000U | (tmp32 >> 1U);
+    base->PG = tmp32;
+
+#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    tmp32 = base->CLM0 + base->CLM1 + base->CLM2 + base->CLM3 + base->CLM4 + base->CLMS;
+    tmp32 = 0x8000U | (tmp32 >> 1U);
+    base->MG = tmp32;
+#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+
+    return kStatus_Success;
+}
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+
+#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
+void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode)
+{
+    if (kADC16_ChannelMuxA == mode)
+    {
+        base->CFG2 &= ~ADC_CFG2_MUXSEL_MASK;
+    }
+    else /* kADC16_ChannelMuxB. */
+    {
+        base->CFG2 |= ADC_CFG2_MUXSEL_MASK;
+    }
+}
+#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
+
+void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config)
+{
+    uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK);
+
+    if (!config) /* Pass "NULL" to disable the feature. */
+    {
+        base->SC2 = tmp32;
+        return;
+    }
+    /* Enable the feature. */
+    tmp32 |= ADC_SC2_ACFE_MASK;
+
+    /* Select the hardware compare working mode. */
+    switch (config->hardwareCompareMode)
+    {
+        case kADC16_HardwareCompareMode0:
+            break;
+        case kADC16_HardwareCompareMode1:
+            tmp32 |= ADC_SC2_ACFGT_MASK;
+            break;
+        case kADC16_HardwareCompareMode2:
+            tmp32 |= ADC_SC2_ACREN_MASK;
+            break;
+        case kADC16_HardwareCompareMode3:
+            tmp32 |= ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK;
+            break;
+        default:
+            break;
+    }
+    base->SC2 = tmp32;
+
+    /* Load the compare values. */
+    base->CV1 = ADC_CV1_CV(config->value1);
+    base->CV2 = ADC_CV2_CV(config->value2);
+}
+
+#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode)
+{
+    uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK);
+
+    if (kADC16_HardwareAverageDisabled != mode)
+    {
+        tmp32 |= ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(mode);
+    }
+    base->SC3 = tmp32;
+}
+#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+
+#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
+void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config)
+{
+    uint32_t tmp32;
+
+    if (!config) /* Passing "NULL" is to disable the feature. */
+    {
+        base->PGA = 0U;
+        return;
+    }
+
+    /* Enable the PGA and set the gain value. */
+    tmp32 = ADC_PGA_PGAEN_MASK | ADC_PGA_PGAG(config->pgaGain);
+
+    /* Configure the misc features for PGA. */
+    if (config->enableRunInNormalMode)
+    {
+        tmp32 |= ADC_PGA_PGALPb_MASK;
+    }
+#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
+    if (config->disablePgaChopping)
+    {
+        tmp32 |= ADC_PGA_PGACHPb_MASK;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
+#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
+    if (config->enableRunInOffsetMeasurement)
+    {
+        tmp32 |= ADC_PGA_PGAOFSM_MASK;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
+    base->PGA = tmp32;
+}
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+
+uint32_t ADC16_GetStatusFlags(ADC_Type *base)
+{
+    uint32_t ret = 0;
+
+    if (0U != (base->SC2 & ADC_SC2_ADACT_MASK))
+    {
+        ret |= kADC16_ActiveFlag;
+    }
+#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
+    if (0U != (base->SC3 & ADC_SC3_CALF_MASK))
+    {
+        ret |= kADC16_CalibrationFailedFlag;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+    return ret;
+}
+
+void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask)
+{
+#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
+    if (0U != (mask & kADC16_CalibrationFailedFlag))
+    {
+        base->SC3 |= ADC_SC3_CALF_MASK;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+}
+
+void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config)
+{
+    assert(channelGroup < ADC_SC1_COUNT);
+    assert(NULL != config);
+
+    uint32_t sc1 = ADC_SC1_ADCH(config->channelNumber); /* Set the channel number. */
+
+#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    /* Enable the differential conversion. */
+    if (config->enableDifferentialConversion)
+    {
+        sc1 |= ADC_SC1_DIFF_MASK;
+    }
+#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+    /* Enable the interrupt when the conversion is done. */
+    if (config->enableInterruptOnConversionCompleted)
+    {
+        sc1 |= ADC_SC1_AIEN_MASK;
+    }
+    base->SC1[channelGroup] = sc1;
+}
+
+uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup)
+{
+    assert(channelGroup < ADC_SC1_COUNT);
+
+    uint32_t ret = 0U;
+
+    if (0U != (base->SC1[channelGroup] & ADC_SC1_COCO_MASK))
+    {
+        ret |= kADC16_ChannelConversionDoneFlag;
+    }
+    return ret;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_adc16.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_adc16.h
new file mode 100644
index 00000000000..7f5169a33ba
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_adc16.h
@@ -0,0 +1,526 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_ADC16_H_
+#define _FSL_ADC16_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup adc16
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief ADC16 driver version 2.0.0. */
+#define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*!
+ * @brief Channel status flags.
+ */
+enum _adc16_channel_status_flags
+{
+    kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */
+};
+
+/*!
+ * @brief Converter status flags.
+ */
+enum _adc16_status_flags
+{
+    kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */
+#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
+    kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */
+#endif                                                /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+};
+
+#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
+/*!
+ * @brief Channel multiplexer mode for each channel.
+ *
+ * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b
+ * are the different channels but share the same channel number.
+ */
+typedef enum _adc_channel_mux_mode
+{
+    kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */
+    kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */
+} adc16_channel_mux_mode_t;
+#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
+
+/*!
+ * @brief Clock divider for the converter.
+ */
+typedef enum _adc16_clock_divider
+{
+    kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */
+    kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */
+    kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */
+    kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */
+} adc16_clock_divider_t;
+
+/*!
+ *@brief Converter's resolution.
+ */
+typedef enum _adc16_resolution
+{
+    /* This group of enumeration is for internal use which is related to register setting. */
+    kADC16_Resolution8or9Bit = 0U,   /*!< Single End 8-bit or Differential Sample 9-bit. */
+    kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */
+    kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */
+
+    /* This group of enumeration is for public user. */
+    kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit,    /*!< Single End 8-bit. */
+    kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */
+    kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */
+#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    kADC16_ResolutionDF9Bit = kADC16_Resolution8or9Bit,    /*!< Differential Sample 9-bit. */
+    kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */
+    kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */
+#endif                                                     /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+
+#if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
+    /* 16-bit is supported by default. */
+    kADC16_Resolution16Bit = 3U,                       /*!< Single End 16-bit or Differential Sample 16-bit. */
+    kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */
+#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */
+#endif                                                 /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+#endif                                                 /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */
+} adc16_resolution_t;
+
+/*!
+ * @brief Clock source.
+ */
+typedef enum _adc16_clock_source
+{
+    kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */
+    kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */
+    kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */
+    kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */
+
+    /* Chip defined clock source */
+    kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */
+} adc16_clock_source_t;
+
+/*!
+ * @brief Long sample mode.
+ */
+typedef enum _adc16_long_sample_mode
+{
+    kADC16_LongSampleCycle24 = 0U,  /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */
+    kADC16_LongSampleCycle16 = 1U,  /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */
+    kADC16_LongSampleCycle10 = 2U,  /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */
+    kADC16_LongSampleCycle6 = 3U,   /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */
+    kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */
+} adc16_long_sample_mode_t;
+
+/*!
+ * @brief Reference voltage source.
+ */
+typedef enum _adc16_reference_voltage_source
+{
+    kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */
+    kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */
+} adc16_reference_voltage_source_t;
+
+#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+/*!
+ * @brief Hardware average mode.
+ */
+typedef enum _adc16_hardware_average_mode
+{
+    kADC16_HardwareAverageCount4 = 0U,   /*!< For hardware average with 4 samples. */
+    kADC16_HardwareAverageCount8 = 1U,   /*!< For hardware average with 8 samples. */
+    kADC16_HardwareAverageCount16 = 2U,  /*!< For hardware average with 16 samples. */
+    kADC16_HardwareAverageCount32 = 3U,  /*!< For hardware average with 32 samples. */
+    kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/
+} adc16_hardware_average_mode_t;
+#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+
+/*!
+ * @brief Hardware compare mode.
+ */
+typedef enum _adc16_hardware_compare_mode
+{
+    kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */
+    kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */
+    kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2;
+                                           else, value1 > x > value2. */
+    kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2;
+                                           else x >= value1 || x <= value2. */
+} adc16_hardware_compare_mode_t;
+
+#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
+/*!
+ * @brief PGA's Gain mode.
+ */
+typedef enum _adc16_pga_gain
+{
+    kADC16_PGAGainValueOf1 = 0U,  /*!< For amplifier gain of 1.  */
+    kADC16_PGAGainValueOf2 = 1U,  /*!< For amplifier gain of 2.  */
+    kADC16_PGAGainValueOf4 = 2U,  /*!< For amplifier gain of 4.  */
+    kADC16_PGAGainValueOf8 = 3U,  /*!< For amplifier gain of 8.  */
+    kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */
+    kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */
+    kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */
+} adc16_pga_gain_t;
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+
+/*!
+ * @brief ADC16 converter configuration .
+ */
+typedef struct _adc16_config
+{
+    adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */
+    adc16_clock_source_t clockSource;                        /*!< Select the input clock source to converter. */
+    bool enableAsynchronousClock;                            /*!< Enable the asynchronous clock output. */
+    adc16_clock_divider_t clockDivider;                      /*!< Select the divider of input clock source. */
+    adc16_resolution_t resolution;                           /*!< Select the sample resolution mode. */
+    adc16_long_sample_mode_t longSampleMode;                 /*!< Select the long sample mode. */
+    bool enableHighSpeed;                                    /*!< Enable the high-speed mode. */
+    bool enableLowPower;                                     /*!< Enable low power. */
+    bool enableContinuousConversion;                         /*!< Enable continuous conversion mode. */
+} adc16_config_t;
+
+/*!
+ * @brief ADC16 Hardware compare configuration.
+ */
+typedef struct _adc16_hardware_compare_config
+{
+    adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode.
+                                                            See "adc16_hardware_compare_mode_t". */
+    int16_t value1;                                    /*!< Setting value1 for hardware compare mode. */
+    int16_t value2;                                    /*!< Setting value2 for hardware compare mode. */
+} adc16_hardware_compare_config_t;
+
+/*!
+ * @brief ADC16 channel conversion configuration.
+ */
+typedef struct _adc16_channel_config
+{
+    uint32_t channelNumber;                    /*!< Setting the conversion channel number. The available range is 0-31.
+                                                    See channel connection information for each chip in Reference
+                                                    Manual document. */
+    bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */
+#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
+    bool enableDifferentialConversion; /*!< Using Differential sample mode. */
+#endif                                 /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
+} adc16_channel_config_t;
+
+#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
+/*!
+ * @brief ADC16 programmable gain amplifier configuration.
+ */
+typedef struct _adc16_pga_config
+{
+    adc16_pga_gain_t pgaGain;   /*!< Setting PGA gain. */
+    bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */
+#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
+    bool disablePgaChopping; /*!< Disable the PGA chopping function.
+                                  The PGA employs chopping to remove/reduce offset and 1/f noise and offers
+                                  an offset measurement configuration that aids the offset calibration. */
+#endif                       /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
+#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
+    bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode.
+                                            When this feature is enabled, the PGA disconnects itself from the external
+                                            inputs and auto-configures into offset measurement mode. With this field
+                                            set, run the ADC in the recommended settings and enable the maximum hardware
+                                            averaging to get the PGA offset number. The output is the
+                                            (PGA offset * (64+1)) for the given PGA setting. */
+#endif                                 /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
+} adc16_pga_config_t;
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the ADC16 module.
+ *
+ * @param base   ADC16 peripheral base address.
+ * @param config Pointer to configuration structure. See "adc16_config_t".
+ */
+void ADC16_Init(ADC_Type *base, const adc16_config_t *config);
+
+/*!
+ * @brief De-initializes the ADC16 module.
+ *
+ * @param base ADC16 peripheral base address.
+ */
+void ADC16_Deinit(ADC_Type *base);
+
+/*!
+ * @brief Gets an available pre-defined settings for converter's configuration.
+ *
+ * This function initializes the converter configuration structure with an available settings. The default values are:
+ * @code
+ *   config->referenceVoltageSource     = kADC16_ReferenceVoltageSourceVref;
+ *   config->clockSource                = kADC16_ClockSourceAsynchronousClock;
+ *   config->enableAsynchronousClock    = true;
+ *   config->clockDivider               = kADC16_ClockDivider8;
+ *   config->resolution                 = kADC16_ResolutionSE12Bit;
+ *   config->longSampleMode             = kADC16_LongSampleDisabled;
+ *   config->enableHighSpeed            = false;
+ *   config->enableLowPower             = false;
+ *   config->enableContinuousConversion = false;
+ * @endcode
+ * @param config Pointer to configuration structure.
+ */
+void ADC16_GetDefaultConfig(adc16_config_t *config);
+
+#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
+/*!
+ * @brief  Automates the hardware calibration.
+ *
+ * This auto calibration helps to adjust the plus/minus side gain automatically on the converter's working situation.
+ * Execute the calibration before using the converter. Note that the hardware trigger should be used
+ * during calibration.
+ *
+ * @param  base ADC16 peripheral base address.
+ *
+ * @return                 Execution status.
+ * @retval kStatus_Success Calibration is done successfully.
+ * @retval kStatus_Fail    Calibration is failed.
+ */
+status_t ADC16_DoAutoCalibration(ADC_Type *base);
+#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
+
+#if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION
+/*!
+ * @brief Sets the offset value for the conversion result.
+ *
+ * This offset value takes effect on the conversion result. If the offset value is not zero, the reading result
+ * is subtracted by it. Note, the hardware calibration fills the offset value automatically.
+ *
+ * @param base  ADC16 peripheral base address.
+ * @param value Setting offset value.
+ */
+static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value)
+{
+    base->OFS = (uint32_t)(value);
+}
+#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */
+
+/* @} */
+
+/*!
+ * @name Advanced Feature
+ * @{
+ */
+
+#if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA
+/*!
+ * @brief Enables generating the DMA trigger when conversion is completed.
+ *
+ * @param base   ADC16 peripheral base address.
+ * @param enable Switcher of DMA feature. "true" means to enable, "false" means not.
+ */
+static inline void ADC16_EnableDMA(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SC2 |= ADC_SC2_DMAEN_MASK;
+    }
+    else
+    {
+        base->SC2 &= ~ADC_SC2_DMAEN_MASK;
+    }
+}
+#endif /* FSL_FEATURE_ADC16_HAS_DMA */
+
+/*!
+ * @brief Enables the hardware trigger mode.
+ *
+ * @param base   ADC16 peripheral base address.
+ * @param enable Switcher of hardware trigger feature. "true" means to enable, "false" means not.
+ */
+static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SC2 |= ADC_SC2_ADTRG_MASK;
+    }
+    else
+    {
+        base->SC2 &= ~ADC_SC2_ADTRG_MASK;
+    }
+}
+
+#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
+/*!
+ * @brief Sets the channel mux mode.
+ *
+ * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an
+ * indicated channel.
+ *
+ * @param base ADC16 peripheral base address.
+ * @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t".
+ */
+void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode);
+#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
+
+/*!
+ * @brief Configures the hardware compare mode.
+ *
+ * The hardware compare mode provides a way to process the conversion result automatically by hardware. Only the result
+ * in
+ * compare range is available. To compare the range, see "adc16_hardware_compare_mode_t", or the reference
+ * manual document for more detailed information.
+ *
+ * @param base     ADC16 peripheral base address.
+ * @param config   Pointer to "adc16_hardware_compare_config_t" structure. Passing "NULL" is to disable the feature.
+ */
+void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config);
+
+#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
+/*!
+ * @brief Sets the hardware average mode.
+ *
+ * Hardware average mode provides a way to process the conversion result automatically by hardware. The multiple
+ * conversion results are accumulated and averaged internally. This aids  reading results.
+ *
+ * @param base  ADC16 peripheral base address.
+ * @param mode  Setting hardware average mode. See "adc16_hardware_average_mode_t".
+ */
+void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode);
+#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
+
+#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
+/*!
+ * @brief Configures the PGA for converter's front end.
+ *
+ * @param base    ADC16 peripheral base address.
+ * @param config  Pointer to "adc16_pga_config_t" structure. Passing "NULL" is to disable the feature.
+ */
+void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config);
+#endif /* FSL_FEATURE_ADC16_HAS_PGA */
+
+/*!
+ * @brief  Gets the status flags of the converter.
+ *
+ * @param  base ADC16 peripheral base address.
+ *
+ * @return      Flags' mask if indicated flags are asserted. See "_adc16_status_flags".
+ */
+uint32_t ADC16_GetStatusFlags(ADC_Type *base);
+
+/*!
+ * @brief  Clears the status flags of the converter.
+ *
+ * @param  base ADC16 peripheral base address.
+ * @param  mask Mask value for the cleared flags. See "_adc16_status_flags".
+ */
+void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name Conversion Channel
+ * @{
+ */
+
+/*!
+ * @brief Configures the conversion channel.
+ *
+ * This operation triggers the conversion if in software trigger mode. When in hardware trigger mode, this API
+ * configures the channel while the external trigger source helps to trigger the conversion.
+ *
+ * Note that the "Channel Group" has a detailed description.
+ * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more than one
+ * group of status and control register, one for each conversion. The channel group parameter indicates which group of
+ * registers are used channel group 0 is for Group A registers and channel group 1 is for Group B registers.  The
+ * channel groups are used in a "ping-pong" approach to control the ADC operation.  At any point, only one of
+ * the channel groups is actively controlling ADC conversions. Channel group 0 is used for both software and hardware
+ * trigger modes of operation. Channel groups 1 and greater indicate potentially multiple channel group registers for
+ * use only in hardware trigger mode. See the chip configuration information in the MCU reference manual about the
+ * number of SC1n registers (channel groups) specific to this device.  None of the channel groups 1 or greater are used
+ * for software trigger operation and therefore writes to these channel groups do not initiate a new conversion.
+ * Updating channel group 0 while a different channel group is actively controlling a conversion is allowed and
+ * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
+ * conversion aborts the current conversion.
+ *
+ * @param base          ADC16 peripheral base address.
+ * @param channelGroup  Channel group index.
+ * @param config        Pointer to "adc16_channel_config_t" structure for conversion channel.
+ */
+void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config);
+
+/*!
+ * @brief  Gets the conversion value.
+ *
+ * @param  base         ADC16 peripheral base address.
+ * @param  channelGroup Channel group index.
+ *
+ * @return              Conversion value.
+ */
+static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)
+{
+    assert(channelGroup < ADC_R_COUNT);
+
+    return base->R[channelGroup];
+}
+
+/*!
+ * @brief  Gets the status flags of channel.
+ *
+ * @param  base         ADC16 peripheral base address.
+ * @param  channelGroup Channel group index.
+ *
+ * @return              Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags".
+ */
+uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+/*!
+ * @}
+ */
+#endif /* _FSL_ADC16_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_clock.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_clock.c
new file mode 100644
index 00000000000..6861c4db544
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_clock.c
@@ -0,0 +1,1794 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Macro definition remap workaround. */
+#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
+#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
+#endif
+#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
+#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
+#endif
+#if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
+#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
+#endif
+#if (defined(MCG_C6_CME_MASK) && !(defined(MCG_C6_CME0_MASK)))
+#define MCG_C6_CME0_MASK MCG_C6_CME_MASK
+#endif
+
+/* PLL fixed multiplier when there is not PRDIV and VDIV. */
+#define PLL_FIXED_MULT (375U)
+/* Max frequency of the reference clock used for internal clock trim. */
+#define TRIM_REF_CLK_MIN (8000000U)
+/* Min frequency of the reference clock used for internal clock trim. */
+#define TRIM_REF_CLK_MAX (16000000U)
+/* Max trim value of fast internal reference clock. */
+#define TRIM_FIRC_MAX (5000000U)
+/* Min trim value of fast internal reference clock. */
+#define TRIM_FIRC_MIN (3000000U)
+/* Max trim value of fast internal reference clock. */
+#define TRIM_SIRC_MAX (39063U)
+/* Min trim value of fast internal reference clock. */
+#define TRIM_SIRC_MIN (31250U)
+
+#define MCG_S_IRCST_VAL ((MCG->S & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT)
+#define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
+#define MCG_S_IREFST_VAL ((MCG->S & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)
+#define MCG_S_PLLST_VAL ((MCG->S & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT)
+#define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
+#define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
+#define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
+#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
+#define MCG_S2_PLLCST_VAL ((MCG->S2 & MCG_S2_PLLCST_MASK) >> MCG_S2_PLLCST_SHIFT)
+#define MCG_C7_OSCSEL_VAL ((MCG->C7 & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
+#define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
+#define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
+#define MCG_C7_PLL32KREFSEL_VAL ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT)
+#define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
+#define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT)
+#define MCG_C11_PRDIV1_VAL ((MCG->C11 & MCG_C11_PRDIV1_MASK) >> MCG_C11_PRDIV1_SHIFT)
+#define MCG_C12_VDIV1_VAL ((MCG->C12 & MCG_C12_VDIV1_MASK) >> MCG_C12_VDIV1_SHIFT)
+#define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
+#define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
+
+#define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
+
+#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
+#define SIM_CLKDIV1_OUTDIV2_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
+#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
+#define SIM_CLKDIV1_OUTDIV5_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV5_MASK) >> SIM_CLKDIV1_OUTDIV5_SHIFT)
+#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
+#define SIM_SOPT2_PLLFLLSEL_VAL ((SIM->SOPT2 & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
+#define SIM_CLKDIV3_PLLFLLDIV_VAL ((SIM->CLKDIV3 & SIM_CLKDIV3_PLLFLLDIV_MASK) >> SIM_CLKDIV3_PLLFLLDIV_SHIFT)
+#define SIM_CLKDIV3_PLLFLLFRAC_VAL ((SIM->CLKDIV3 & SIM_CLKDIV3_PLLFLLFRAC_MASK) >> SIM_CLKDIV3_PLLFLLFRAC_SHIFT)
+
+/* MCG_S_CLKST definition. */
+enum _mcg_clkout_stat
+{
+    kMCG_ClkOutStatFll, /* FLL.            */
+    kMCG_ClkOutStatInt, /* Internal clock. */
+    kMCG_ClkOutStatExt, /* External clock. */
+    kMCG_ClkOutStatPll  /* PLL.            */
+};
+
+/* MCG_S_PLLST definition. */
+enum _mcg_pllst
+{
+    kMCG_PllstFll, /* FLL is used. */
+    kMCG_PllstPll  /* PLL is used. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Slow internal reference clock frequency. */
+static uint32_t s_slowIrcFreq = 32768U;
+/* Fast internal reference clock frequency. */
+static uint32_t s_fastIrcFreq = 4000000U;
+
+/* External XTAL0 (OSC0) clock frequency. */
+uint32_t g_xtal0Freq;
+/* External XTAL32K clock frequency. */
+uint32_t g_xtal32Freq;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the MCG external reference clock frequency.
+ *
+ * Get the current MCG external reference clock frequency in Hz. It is
+ * the frequency select by MCG_C7[OSCSEL]. This is an internal function.
+ *
+ * @return MCG external reference clock frequency in Hz.
+ */
+static uint32_t CLOCK_GetMcgExtClkFreq(void);
+
+/*!
+ * @brief Get the MCG FLL external reference clock frequency.
+ *
+ * Get the current MCG FLL external reference clock frequency in Hz. It is
+ * the frequency after by MCG_C1[FRDIV]. This is an internal function.
+ *
+ * @return MCG FLL external reference clock frequency in Hz.
+ */
+static uint32_t CLOCK_GetFllExtRefClkFreq(void);
+
+/*!
+ * @brief Get the MCG FLL reference clock frequency.
+ *
+ * Get the current MCG FLL reference clock frequency in Hz. It is
+ * the frequency select by MCG_C1[IREFS]. This is an internal function.
+ *
+ * @return MCG FLL reference clock frequency in Hz.
+ */
+static uint32_t CLOCK_GetFllRefClkFreq(void);
+
+/*!
+ * @brief Get the frequency of clock selected by MCG_C2[IRCS].
+ *
+ * This clock's two output:
+ *  1. MCGOUTCLK when MCG_S[CLKST]=0.
+ *  2. MCGIRCLK when MCG_C1[IRCLKEN]=1.
+ *
+ * @return The frequency in Hz.
+ */
+static uint32_t CLOCK_GetInternalRefClkSelectFreq(void);
+
+/*!
+ * @brief Get the MCG PLL/PLL0 reference clock frequency.
+ *
+ * Get the current MCG PLL/PLL0 reference clock frequency in Hz.
+ * This is an internal function.
+ *
+ * @return MCG PLL/PLL0 reference clock frequency in Hz.
+ */
+static uint32_t CLOCK_GetPll0RefFreq(void);
+
+/*!
+ * @brief Calculate the RANGE value base on crystal frequency.
+ *
+ * To setup external crystal oscillator, must set the register bits RANGE
+ * base on the crystal frequency. This function returns the RANGE base on the
+ * input frequency. This is an internal function.
+ *
+ * @param freq Crystal frequency in Hz.
+ * @return The RANGE value.
+ */
+static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq);
+
+/*!
+ * @brief Delay function to wait FLL stable.
+ *
+ * Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least
+ * 1ms. Every time changes FLL setting, should wait this time for FLL stable.
+ */
+static void CLOCK_FllStableDelay(void);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t CLOCK_GetMcgExtClkFreq(void)
+{
+    uint32_t freq;
+
+    switch (MCG_C7_OSCSEL_VAL)
+    {
+        case 0U:
+            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
+            assert(g_xtal0Freq);
+            freq = g_xtal0Freq;
+            break;
+        case 1U:
+            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
+            assert(g_xtal32Freq);
+            freq = g_xtal32Freq;
+            break;
+        case 2U:
+            freq = MCG_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+static uint32_t CLOCK_GetFllExtRefClkFreq(void)
+{
+    /* FllExtRef = McgExtRef / FllExtRefDiv */
+    uint8_t frdiv;
+    uint8_t range;
+    uint8_t oscsel;
+
+    uint32_t freq = CLOCK_GetMcgExtClkFreq();
+
+    if (!freq)
+    {
+        return freq;
+    }
+
+    frdiv = MCG_C1_FRDIV_VAL;
+    freq >>= frdiv;
+
+    range = MCG_C2_RANGE_VAL;
+    oscsel = MCG_C7_OSCSEL_VAL;
+
+    /*
+       When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536.
+       1. MCG_C7[OSCSEL] selects IRC48M.
+       2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0.
+    */
+    if (((0U != range) && (kMCG_OscselOsc == oscsel)) || (kMCG_OscselIrc == oscsel))
+    {
+        switch (frdiv)
+        {
+            case 0:
+            case 1:
+            case 2:
+            case 3:
+            case 4:
+            case 5:
+                freq >>= 5u;
+                break;
+            case 6:
+                /* 64*20=1280 */
+                freq /= 20u;
+                break;
+            case 7:
+                /* 128*12=1536 */
+                freq /= 12u;
+                break;
+            default:
+                freq = 0u;
+                break;
+        }
+    }
+
+    return freq;
+}
+
+static uint32_t CLOCK_GetInternalRefClkSelectFreq(void)
+{
+    if (kMCG_IrcSlow == MCG_S_IRCST_VAL)
+    {
+        /* Slow internal reference clock selected*/
+        return s_slowIrcFreq;
+    }
+    else
+    {
+        /* Fast internal reference clock selected*/
+        return s_fastIrcFreq >> MCG_SC_FCRDIV_VAL;
+    }
+}
+
+static uint32_t CLOCK_GetFllRefClkFreq(void)
+{
+    /* If use external reference clock. */
+    if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
+    {
+        return CLOCK_GetFllExtRefClkFreq();
+    }
+    /* If use internal reference clock. */
+    else
+    {
+        return s_slowIrcFreq;
+    }
+}
+
+static uint32_t CLOCK_GetPll0RefFreq(void)
+{
+    /* MCG external reference clock. */
+    return CLOCK_GetMcgExtClkFreq();
+}
+
+static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
+{
+    uint8_t range;
+
+    if (freq <= 39063U)
+    {
+        range = 0U;
+    }
+    else if (freq <= 8000000U)
+    {
+        range = 1U;
+    }
+    else
+    {
+        range = 2U;
+    }
+
+    return range;
+}
+
+static void CLOCK_FllStableDelay(void)
+{
+    /*
+       Should wait at least 1ms. Because in these modes, the core clock is 100MHz
+       at most, so this function could obtain the 1ms delay.
+     */
+    volatile uint32_t i = 30000U;
+    while (i--)
+    {
+        __NOP();
+    }
+}
+
+uint32_t CLOCK_GetOsc0ErClkUndivFreq(void)
+{
+    if (OSC0->CR & OSC_CR_ERCLKEN_MASK)
+    {
+        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
+        assert(g_xtal0Freq);
+        return g_xtal0Freq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+uint32_t CLOCK_GetOsc0ErClkDivFreq(void)
+{
+    if (OSC0->CR & OSC_CR_ERCLKEN_MASK)
+    {
+        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
+        assert(g_xtal0Freq);
+        return g_xtal0Freq >> ((OSC0->DIV & OSC_DIV_ERPS_MASK) >> OSC_DIV_ERPS_SHIFT);
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+uint32_t CLOCK_GetEr32kClkFreq(void)
+{
+    uint32_t freq;
+
+    switch (SIM_SOPT1_OSC32KSEL_VAL)
+    {
+        case 0U: /* OSC 32k clock  */
+            freq = (CLOCK_GetOsc0ErClkUndivFreq() == 32768U) ? 32768U : 0U;
+            break;
+        case 2U: /* RTC 32k clock  */
+            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
+            assert(g_xtal32Freq);
+            freq = g_xtal32Freq;
+            break;
+        case 3U: /* LPO clock      */
+            freq = LPO_CLK_FREQ;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+uint32_t CLOCK_GetPllFllSelClkFreq(void)
+{
+    uint32_t freq;
+
+    switch (SIM_SOPT2_PLLFLLSEL_VAL)
+    {
+        case 0U: /* FLL. */
+            freq = CLOCK_GetFllFreq();
+            break;
+        case 1U: /* PLL. */
+            freq = CLOCK_GetPll0Freq();
+            break;
+        case 3U: /* MCG IRC48M. */
+            freq = MCG_INTERNAL_IRC_48M;
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    freq *= (SIM_CLKDIV3_PLLFLLFRAC_VAL + 1U);
+    freq /= (SIM_CLKDIV3_PLLFLLDIV_VAL + 1U);
+    return freq;
+}
+
+uint32_t CLOCK_GetOsc0ErClkFreq(void)
+{
+    return CLOCK_GetOsc0ErClkDivFreq();
+}
+
+uint32_t CLOCK_GetPlatClkFreq(void)
+{
+    return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1);
+}
+
+uint32_t CLOCK_GetFlashClkFreq(void)
+{
+    return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1);
+}
+
+uint32_t CLOCK_GetQspiBusClkFreq(void)
+{
+    return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV5_VAL + 1);
+}
+
+uint32_t CLOCK_GetBusClkFreq(void)
+{
+    return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1);
+}
+
+uint32_t CLOCK_GetCoreSysClkFreq(void)
+{
+    return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1);
+}
+
+uint32_t CLOCK_GetFreq(clock_name_t clockName)
+{
+    uint32_t freq;
+
+    switch (clockName)
+    {
+        case kCLOCK_CoreSysClk:
+        case kCLOCK_PlatClk:
+            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1);
+            break;
+        case kCLOCK_BusClk:
+            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1);
+            break;
+        case kCLOCK_FlashClk:
+            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1);
+            break;
+        case kCLOCK_PllFllSelClk:
+            freq = CLOCK_GetPllFllSelClkFreq();
+            break;
+        case kCLOCK_QspiBusClk:
+            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV5_VAL + 1);
+            break;
+        case kCLOCK_Er32kClk:
+            freq = CLOCK_GetEr32kClkFreq();
+            break;
+        case kCLOCK_McgFixedFreqClk:
+            freq = CLOCK_GetFixedFreqClkFreq();
+            break;
+        case kCLOCK_McgInternalRefClk:
+            freq = CLOCK_GetInternalRefClkFreq();
+            break;
+        case kCLOCK_McgFllClk:
+            freq = CLOCK_GetFllFreq();
+            break;
+        case kCLOCK_McgPll0Clk:
+            freq = CLOCK_GetPll0Freq();
+            break;
+        case kCLOCK_McgIrc48MClk:
+            freq = MCG_INTERNAL_IRC_48M;
+            break;
+        case kCLOCK_LpoClk:
+            freq = LPO_CLK_FREQ;
+            break;
+        case kCLOCK_Osc0ErClkUndiv:
+            freq = CLOCK_GetOsc0ErClkUndivFreq();
+            break;
+        case kCLOCK_Osc0ErClk:
+            freq = CLOCK_GetOsc0ErClkDivFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+void CLOCK_SetSimConfig(sim_clock_config_t const *config)
+{
+    SIM->CLKDIV1 = config->clkdiv1;
+    CLOCK_SetPllFllSelClock(config->pllFllSel, config->pllFllDiv, config->pllFllFrac);
+    CLOCK_SetEr32kClock(config->er32kSrc);
+}
+
+bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+
+    CLOCK_DisableClock(kCLOCK_Usbfs0);
+
+    if (kCLOCK_UsbSrcExt == src)
+    {
+        SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
+    }
+    else
+    {
+        switch (freq)
+        {
+            case 144000000U:
+                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(0);
+                break;
+            case 96000000U:
+                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
+                break;
+            case 72000000U:
+                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
+                break;
+            case 48000000U:
+                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
+                break;
+            default:
+                ret = false;
+                break;
+        }
+
+        SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
+    }
+
+    CLOCK_EnableClock(kCLOCK_Usbfs0);
+
+    if (kCLOCK_UsbSrcIrc48M == src)
+    {
+        USB0->CLK_RECOVER_IRC_EN = 0x03U;
+        USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
+    }
+    return ret;
+}
+
+uint32_t CLOCK_GetOutClkFreq(void)
+{
+    uint32_t mcgoutclk;
+    uint32_t clkst = MCG_S_CLKST_VAL;
+
+    switch (clkst)
+    {
+        case kMCG_ClkOutStatPll:
+            mcgoutclk = CLOCK_GetPll0Freq();
+            break;
+        case kMCG_ClkOutStatFll:
+            mcgoutclk = CLOCK_GetFllFreq();
+            break;
+        case kMCG_ClkOutStatInt:
+            mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
+            break;
+        case kMCG_ClkOutStatExt:
+            mcgoutclk = CLOCK_GetMcgExtClkFreq();
+            break;
+        default:
+            mcgoutclk = 0U;
+            break;
+    }
+    return mcgoutclk;
+}
+
+uint32_t CLOCK_GetFllFreq(void)
+{
+    static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
+
+    uint8_t drs, dmx32;
+    uint32_t freq;
+
+    /* If FLL is not enabled currently, then return 0U. */
+    if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK))
+    {
+        return 0U;
+    }
+
+    /* Get FLL reference clock frequency. */
+    freq = CLOCK_GetFllRefClkFreq();
+    if (!freq)
+    {
+        return freq;
+    }
+
+    drs = MCG_C4_DRST_DRS_VAL;
+    dmx32 = MCG_C4_DMX32_VAL;
+
+    return freq * fllFactorTable[drs][dmx32];
+}
+
+uint32_t CLOCK_GetInternalRefClkFreq(void)
+{
+    /* If MCGIRCLK is gated. */
+    if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK))
+    {
+        return 0U;
+    }
+
+    return CLOCK_GetInternalRefClkSelectFreq();
+}
+
+uint32_t CLOCK_GetFixedFreqClkFreq(void)
+{
+    uint32_t freq = CLOCK_GetFllRefClkFreq();
+
+    /* MCGFFCLK must be no more than MCGOUTCLK/8. */
+    if ((freq) && (freq <= (CLOCK_GetOutClkFreq() / 8U)))
+    {
+        return freq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+uint32_t CLOCK_GetPll0Freq(void)
+{
+    uint32_t mcgpll0clk;
+
+    /* If PLL0 is not enabled, return 0. */
+    if (!(MCG->S & MCG_S_LOCK0_MASK))
+    {
+        return 0U;
+    }
+
+    mcgpll0clk = CLOCK_GetPll0RefFreq();
+
+    /*
+     * Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock.
+     * Please call CLOCK_SetXtal1Freq base on board setting before using OSC1 clock.
+     */
+    assert(mcgpll0clk);
+
+    mcgpll0clk /= (FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_C5_PRDIV0_VAL);
+    mcgpll0clk *= (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL);
+
+    mcgpll0clk >>= 1U;
+    return mcgpll0clk;
+}
+
+status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
+{
+    bool needDelay;
+    uint32_t i;
+
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+    /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */
+    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK)))
+    {
+        return kStatus_MCG_SourceUsed;
+    }
+#endif /* MCG_CONFIG_CHECK_PARAM */
+
+    if (MCG_C7_OSCSEL_VAL != oscsel)
+    {
+        /* If change OSCSEL, need to delay, ERR009878. */
+        needDelay = true;
+    }
+    else
+    {
+        needDelay = false;
+    }
+
+    MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
+    if (kMCG_OscselOsc == oscsel)
+    {
+        if (MCG->C2 & MCG_C2_EREFS_MASK)
+        {
+            while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+            {
+            }
+        }
+    }
+
+    if (needDelay)
+    {
+        /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
+        i = 1500U;
+        while (i--)
+        {
+            __NOP();
+        }
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
+{
+    uint32_t mcgOutClkState = MCG_S_CLKST_VAL;
+    mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)MCG_S_IRCST_VAL;
+    uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;
+
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+    /* If MCGIRCLK is used as system clock source. */
+    if (kMCG_ClkOutStatInt == mcgOutClkState)
+    {
+        /* If need to change MCGIRCLK source or driver, return error. */
+        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs))
+        {
+            return kStatus_MCG_SourceUsed;
+        }
+    }
+#endif
+
+    /* If need to update the FCRDIV. */
+    if (fcrdiv != curFcrdiv)
+    {
+        /* If fast IRC is in use currently, change to slow IRC. */
+        if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCLKEN_MASK)))
+        {
+            MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
+            while (MCG_S_IRCST_VAL != kMCG_IrcSlow)
+            {
+            }
+        }
+        /* Update FCRDIV. */
+        MCG->SC = (MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv);
+    }
+
+    /* Set internal reference clock selection. */
+    MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs));
+    MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode;
+
+    /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
+    if ((mcgOutClkState == kMCG_ClkOutStatInt) || (enableMode & kMCG_IrclkEnable))
+    {
+        while (MCG_S_IRCST_VAL != ircs)
+        {
+        }
+    }
+
+    return kStatus_Success;
+}
+
+uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
+{
+    uint8_t ret_prdiv;           /* PRDIV to return. */
+    uint8_t ret_vdiv;            /* VDIV to return.  */
+    uint8_t prdiv_min;           /* Min PRDIV value to make reference clock in allowed range. */
+    uint8_t prdiv_max;           /* Max PRDIV value to make reference clock in allowed range. */
+    uint8_t prdiv_cur;           /* PRDIV value for iteration.    */
+    uint8_t vdiv_cur;            /* VDIV value for iteration.     */
+    uint32_t ret_freq = 0U;      /* PLL output fequency to return. */
+    uint32_t diff = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
+    uint32_t ref_div;            /* Reference frequency after PRDIV. */
+
+    /*
+       Steps:
+       1. Get allowed prdiv with such rules:
+          1). refFreq / prdiv >= FSL_FEATURE_MCG_PLL_REF_MIN.
+          2). refFreq / prdiv <= FSL_FEATURE_MCG_PLL_REF_MAX.
+       2. For each allowed prdiv, there are two candidate vdiv values:
+          1). (desireFreq / (refFreq / prdiv)).
+          2). (desireFreq / (refFreq / prdiv)) + 1.
+          If could get the precise desired frequency, return current prdiv and
+          vdiv directly. Otherwise choose the one which is closer to desired
+          frequency.
+     */
+
+    /* Reference frequency is out of range. */
+    if ((refFreq < FSL_FEATURE_MCG_PLL_REF_MIN) ||
+        (refFreq > (FSL_FEATURE_MCG_PLL_REF_MAX * (FSL_FEATURE_MCG_PLL_PRDIV_MAX + FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
+    {
+        return 0U;
+    }
+
+    /* refFreq/PRDIV must in a range. First get the allowed PRDIV range. */
+    prdiv_max = refFreq / FSL_FEATURE_MCG_PLL_REF_MIN;
+    prdiv_min = (refFreq + FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / FSL_FEATURE_MCG_PLL_REF_MAX;
+
+    desireFreq *= 2U;
+
+    /* PRDIV traversal. */
+    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--)
+    {
+        /* Reference frequency after PRDIV. */
+        ref_div = refFreq / prdiv_cur;
+
+        vdiv_cur = desireFreq / ref_div;
+
+        if ((vdiv_cur < FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U) || (vdiv_cur > FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
+        {
+            /* No VDIV is available with this PRDIV. */
+            continue;
+        }
+
+        ret_freq = vdiv_cur * ref_div;
+
+        if (vdiv_cur >= FSL_FEATURE_MCG_PLL_VDIV_BASE)
+        {
+            if (ret_freq == desireFreq) /* If desire frequency is got. */
+            {
+                *prdiv = prdiv_cur - FSL_FEATURE_MCG_PLL_PRDIV_BASE;
+                *vdiv = vdiv_cur - FSL_FEATURE_MCG_PLL_VDIV_BASE;
+                return ret_freq / 2U;
+            }
+            /* New PRDIV/VDIV is closer. */
+            if (diff > desireFreq - ret_freq)
+            {
+                diff = desireFreq - ret_freq;
+                ret_prdiv = prdiv_cur;
+                ret_vdiv = vdiv_cur;
+            }
+        }
+        vdiv_cur++;
+        if (vdiv_cur <= (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
+        {
+            ret_freq += ref_div;
+            /* New PRDIV/VDIV is closer. */
+            if (diff > ret_freq - desireFreq)
+            {
+                diff = ret_freq - desireFreq;
+                ret_prdiv = prdiv_cur;
+                ret_vdiv = vdiv_cur;
+            }
+        }
+    }
+
+    if (0xFFFFFFFFU != diff)
+    {
+        /* PRDIV/VDIV found. */
+        *prdiv = ret_prdiv - FSL_FEATURE_MCG_PLL_PRDIV_BASE;
+        *vdiv = ret_vdiv - FSL_FEATURE_MCG_PLL_VDIV_BASE;
+        ret_freq = (refFreq / ret_prdiv) * ret_vdiv;
+        return ret_freq / 2U;
+    }
+    else
+    {
+        /* No proper PRDIV/VDIV found. */
+        return 0U;
+    }
+}
+
+void CLOCK_EnablePll0(mcg_pll_config_t const *config)
+{
+    assert(config);
+
+    uint8_t mcg_c5 = 0U;
+
+    mcg_c5 |= MCG_C5_PRDIV0(config->prdiv);
+    MCG->C5 = mcg_c5; /* Disable the PLL first. */
+
+    MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv);
+
+    /* Set enable mode. */
+    MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode);
+
+    /* Wait for PLL lock. */
+    while (!(MCG->S & MCG_S_LOCK0_MASK))
+    {
+    }
+}
+
+void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
+{
+    /* Clear the previous flag, MCG_SC[LOCS0]. */
+    MCG->SC &= ~MCG_SC_ATMF_MASK;
+
+    if (kMCG_MonitorNone == mode)
+    {
+        MCG->C6 &= ~MCG_C6_CME0_MASK;
+    }
+    else
+    {
+        if (kMCG_MonitorInt == mode)
+        {
+            MCG->C2 &= ~MCG_C2_LOCRE0_MASK;
+        }
+        else
+        {
+            MCG->C2 |= MCG_C2_LOCRE0_MASK;
+        }
+        MCG->C6 |= MCG_C6_CME0_MASK;
+    }
+}
+
+void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
+{
+    uint8_t mcg_c8 = MCG->C8;
+
+    mcg_c8 &= ~(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
+
+    if (kMCG_MonitorNone != mode)
+    {
+        if (kMCG_MonitorReset == mode)
+        {
+            mcg_c8 |= MCG_C8_LOCRE1_MASK;
+        }
+        mcg_c8 |= MCG_C8_CME1_MASK;
+    }
+    MCG->C8 = mcg_c8;
+}
+
+void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
+{
+    uint8_t mcg_c8;
+
+    /* Clear previous flag. */
+    MCG->S = MCG_S_LOLS0_MASK;
+
+    if (kMCG_MonitorNone == mode)
+    {
+        MCG->C6 &= ~MCG_C6_LOLIE0_MASK;
+    }
+    else
+    {
+        mcg_c8 = MCG->C8;
+
+        mcg_c8 &= ~MCG_C8_LOCS1_MASK;
+
+        if (kMCG_MonitorInt == mode)
+        {
+            mcg_c8 &= ~MCG_C8_LOLRE_MASK;
+        }
+        else
+        {
+            mcg_c8 |= MCG_C8_LOLRE_MASK;
+        }
+        MCG->C8 = mcg_c8;
+        MCG->C6 |= MCG_C6_LOLIE0_MASK;
+    }
+}
+
+uint32_t CLOCK_GetStatusFlags(void)
+{
+    uint32_t ret = 0U;
+    uint8_t mcg_s = MCG->S;
+
+    if (MCG->SC & MCG_SC_LOCS0_MASK)
+    {
+        ret |= kMCG_Osc0LostFlag;
+    }
+    if (mcg_s & MCG_S_OSCINIT0_MASK)
+    {
+        ret |= kMCG_Osc0InitFlag;
+    }
+    if (MCG->C8 & MCG_C8_LOCS1_MASK)
+    {
+        ret |= kMCG_RtcOscLostFlag;
+    }
+    if (mcg_s & MCG_S_LOLS0_MASK)
+    {
+        ret |= kMCG_Pll0LostFlag;
+    }
+    if (mcg_s & MCG_S_LOCK0_MASK)
+    {
+        ret |= kMCG_Pll0LockFlag;
+    }
+    return ret;
+}
+
+void CLOCK_ClearStatusFlags(uint32_t mask)
+{
+    uint8_t reg;
+
+    if (mask & kMCG_Osc0LostFlag)
+    {
+        MCG->SC &= ~MCG_SC_ATMF_MASK;
+    }
+    if (mask & kMCG_RtcOscLostFlag)
+    {
+        reg = MCG->C8;
+        MCG->C8 = reg;
+    }
+    if (mask & kMCG_Pll0LostFlag)
+    {
+        MCG->S = MCG_S_LOLS0_MASK;
+    }
+}
+
+void CLOCK_InitOsc0(osc_config_t const *config)
+{
+    uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
+
+    OSC_SetCapLoad(OSC0, config->capLoad);
+    OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
+
+    MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
+
+    if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK))
+    {
+        /* Wait for stable. */
+        while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+        {
+        }
+    }
+}
+
+void CLOCK_DeinitOsc0(void)
+{
+    OSC0->CR = 0U;
+    MCG->C2 &= ~OSC_MODE_MASK;
+}
+
+status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
+{
+    uint32_t multi; /* extFreq / desireFreq */
+    uint32_t actv;  /* Auto trim value. */
+    uint8_t mcg_sc;
+
+    static const uint32_t trimRange[2][2] = {
+        /*     Min           Max      */
+        {TRIM_SIRC_MIN, TRIM_SIRC_MAX}, /* Slow IRC. */
+        {TRIM_FIRC_MIN, TRIM_FIRC_MAX}  /* Fast IRC. */
+    };
+
+    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN))
+    {
+        return kStatus_MCG_AtmBusClockInvalid;
+    }
+
+    /* Check desired frequency range. */
+    if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1]))
+    {
+        return kStatus_MCG_AtmDesiredFreqInvalid;
+    }
+
+    /*
+       Make sure internal reference clock is not used to generate bus clock.
+       Here only need to check (MCG_S_IREFST == 1).
+     */
+    if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK))
+    {
+        return kStatus_MCG_AtmIrcUsed;
+    }
+
+    multi = extFreq / desireFreq;
+    actv = multi * 21U;
+
+    if (kMCG_AtmSel4m == atms)
+    {
+        actv *= 128U;
+    }
+
+    /* Now begin to start trim. */
+    MCG->ATCVL = (uint8_t)actv;
+    MCG->ATCVH = (uint8_t)(actv >> 8U);
+
+    mcg_sc = MCG->SC;
+    mcg_sc &= ~(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK);
+    mcg_sc |= (MCG_SC_ATMF_MASK | MCG_SC_ATMS(atms));
+    MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
+
+    /* Wait for finished. */
+    while (MCG->SC & MCG_SC_ATME_MASK)
+    {
+    }
+
+    /* Error occurs? */
+    if (MCG->SC & MCG_SC_ATMF_MASK)
+    {
+        /* Clear the failed flag. */
+        MCG->SC = mcg_sc;
+        return kStatus_MCG_AtmHardwareFail;
+    }
+
+    *actualFreq = extFreq / multi;
+
+    if (kMCG_AtmSel4m == atms)
+    {
+        s_fastIrcFreq = *actualFreq;
+    }
+    else
+    {
+        s_slowIrcFreq = *actualFreq;
+    }
+
+    return kStatus_Success;
+}
+
+mcg_mode_t CLOCK_GetMode(void)
+{
+    mcg_mode_t mode = kMCG_ModeError;
+    uint32_t clkst = MCG_S_CLKST_VAL;
+    uint32_t irefst = MCG_S_IREFST_VAL;
+    uint32_t lp = MCG_C2_LP_VAL;
+    uint32_t pllst = MCG_S_PLLST_VAL;
+
+    /*------------------------------------------------------------------
+                           Mode and Registers
+    ____________________________________________________________________
+
+      Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
+    ____________________________________________________________________
+
+      FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
+    ____________________________________________________________________
+
+      FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
+    ____________________________________________________________________
+
+      FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
+    ____________________________________________________________________
+
+      FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
+    ____________________________________________________________________
+
+      BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
+    ____________________________________________________________________
+
+      BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
+    ____________________________________________________________________
+
+      PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
+    ____________________________________________________________________
+
+      PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
+    ____________________________________________________________________
+
+      PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
+    ____________________________________________________________________
+
+      PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
+    ____________________________________________________________________
+
+    ----------------------------------------------------------------------*/
+
+    switch (clkst)
+    {
+        case kMCG_ClkOutStatFll:
+            if (kMCG_FllSrcExternal == irefst)
+            {
+                mode = kMCG_ModeFEE;
+            }
+            else
+            {
+                mode = kMCG_ModeFEI;
+            }
+            break;
+        case kMCG_ClkOutStatInt:
+            if (lp)
+            {
+                mode = kMCG_ModeBLPI;
+            }
+            else
+            {
+                {
+                    mode = kMCG_ModeFBI;
+                }
+            }
+            break;
+        case kMCG_ClkOutStatExt:
+            if (lp)
+            {
+                mode = kMCG_ModeBLPE;
+            }
+            else
+            {
+                if (kMCG_PllstPll == pllst)
+                {
+                    mode = kMCG_ModePBE;
+                }
+                else
+                {
+                    mode = kMCG_ModeFBE;
+                }
+            }
+            break;
+        case kMCG_ClkOutStatPll:
+        {
+            mode = kMCG_ModePEE;
+        }
+        break;
+        default:
+            break;
+    }
+
+    return mode;
+}
+
+status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
+{
+    uint8_t mcg_c4;
+    bool change_drs = false;
+
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+    mcg_mode_t mode = CLOCK_GetMode();
+    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode)))
+    {
+        return kStatus_MCG_ModeUnreachable;
+    }
+#endif
+    mcg_c4 = MCG->C4;
+
+    /*
+       Errata: ERR007993
+       Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
+       reference clock source changes, then reset to previous value after
+       reference clock changes.
+     */
+    if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
+    {
+        change_drs = true;
+        /* Change the LSB of DRST_DRS. */
+        MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
+    }
+
+    /* Set CLKS and IREFS. */
+    MCG->C1 =
+        ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut)        /* CLKS = 0 */
+                                                                 | MCG_C1_IREFS(kMCG_FllSrcInternal)); /* IREFS = 1 */
+
+    /* Wait and check status. */
+    while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
+    {
+    }
+
+    /* Errata: ERR007993 */
+    if (change_drs)
+    {
+        MCG->C4 = mcg_c4;
+    }
+
+    /* In FEI mode, the MCG_C4[DMX32] is set to 0U. */
+    MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs));
+
+    /* Check MCG_S[CLKST] */
+    while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
+    {
+    }
+
+    /* Wait for FLL stable time. */
+    if (fllStableDelay)
+    {
+        fllStableDelay();
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
+{
+    uint8_t mcg_c4;
+    bool change_drs = false;
+
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+    mcg_mode_t mode = CLOCK_GetMode();
+    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode)))
+    {
+        return kStatus_MCG_ModeUnreachable;
+    }
+#endif
+    mcg_c4 = MCG->C4;
+
+    /*
+       Errata: ERR007993
+       Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
+       reference clock source changes, then reset to previous value after
+       reference clock changes.
+     */
+    if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
+    {
+        change_drs = true;
+        /* Change the LSB of DRST_DRS. */
+        MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
+    }
+
+    /* Set CLKS and IREFS. */
+    MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
+               (MCG_C1_CLKS(kMCG_ClkOutSrcOut)         /* CLKS = 0 */
+                | MCG_C1_FRDIV(frdiv)                  /* FRDIV */
+                | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
+
+    /* Wait and check status. */
+    while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
+    {
+    }
+
+    /* Errata: ERR007993 */
+    if (change_drs)
+    {
+        MCG->C4 = mcg_c4;
+    }
+
+    /* Set DRS and DMX32. */
+    mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
+    MCG->C4 = mcg_c4;
+
+    /* Wait for DRST_DRS update. */
+    while (MCG->C4 != mcg_c4)
+    {
+    }
+
+    /* Check MCG_S[CLKST] */
+    while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
+    {
+    }
+
+    /* Wait for FLL stable time. */
+    if (fllStableDelay)
+    {
+        fllStableDelay();
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
+{
+    uint8_t mcg_c4;
+    bool change_drs = false;
+
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+    mcg_mode_t mode = CLOCK_GetMode();
+
+    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
+          (kMCG_ModeBLPI == mode)))
+
+    {
+        return kStatus_MCG_ModeUnreachable;
+    }
+#endif
+
+    mcg_c4 = MCG->C4;
+
+    MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
+
+    /*
+       Errata: ERR007993
+       Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
+       reference clock source changes, then reset to previous value after
+       reference clock changes.
+     */
+    if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
+    {
+        change_drs = true;
+        /* Change the LSB of DRST_DRS. */
+        MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
+    }
+
+    /* Set CLKS and IREFS. */
+    MCG->C1 =
+        ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal)    /* CLKS = 1 */
+                                                                | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
+
+    /* Wait and check status. */
+    while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
+    {
+    }
+
+    /* Errata: ERR007993 */
+    if (change_drs)
+    {
+        MCG->C4 = mcg_c4;
+    }
+
+    while (kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
+    {
+    }
+
+    MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs));
+
+    /* Wait for FLL stable time. */
+    if (fllStableDelay)
+    {
+        fllStableDelay();
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
+{
+    uint8_t mcg_c4;
+    bool change_drs = false;
+
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+    mcg_mode_t mode = CLOCK_GetMode();
+    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
+          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
+    {
+        return kStatus_MCG_ModeUnreachable;
+    }
+#endif
+
+    /* Change to FLL mode. */
+    MCG->C6 &= ~MCG_C6_PLLS_MASK;
+    while (MCG->S & MCG_S_PLLST_MASK)
+    {
+    }
+
+    /* Set LP bit to enable the FLL */
+    MCG->C2 &= ~MCG_C2_LP_MASK;
+
+    mcg_c4 = MCG->C4;
+
+    /*
+       Errata: ERR007993
+       Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
+       reference clock source changes, then reset to previous value after
+       reference clock changes.
+     */
+    if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
+    {
+        change_drs = true;
+        /* Change the LSB of DRST_DRS. */
+        MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
+    }
+
+    /* Set CLKS and IREFS. */
+    MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
+               (MCG_C1_CLKS(kMCG_ClkOutSrcExternal)    /* CLKS = 2 */
+                | MCG_C1_FRDIV(frdiv)                  /* FRDIV = frdiv */
+                | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
+
+    /* Wait for Reference clock Status bit to clear */
+    while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
+    {
+    }
+
+    /* Errata: ERR007993 */
+    if (change_drs)
+    {
+        MCG->C4 = mcg_c4;
+    }
+
+    /* Set DRST_DRS and DMX32. */
+    mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
+
+    /* Wait for clock status bits to show clock source is ext ref clk */
+    while (kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
+    {
+    }
+
+    /* Wait for fll stable time. */
+    if (fllStableDelay)
+    {
+        fllStableDelay();
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_SetBlpiMode(void)
+{
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+    if (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
+    {
+        return kStatus_MCG_ModeUnreachable;
+    }
+#endif /* MCG_CONFIG_CHECK_PARAM */
+
+    /* Set LP. */
+    MCG->C2 |= MCG_C2_LP_MASK;
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_SetBlpeMode(void)
+{
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+    if (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
+    {
+        return kStatus_MCG_ModeUnreachable;
+    }
+#endif
+
+    /* Set LP bit to enter BLPE mode. */
+    MCG->C2 |= MCG_C2_LP_MASK;
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
+{
+    /*
+       This function is designed to change MCG to PBE mode from PEE/BLPE/FBE,
+       but with this workflow, the source mode could be all modes except PEI/PBI.
+     */
+    MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
+
+    /* Change to use external clock first. */
+    MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
+
+    /* Wait for CLKST clock status bits to show clock source is ext ref clk */
+    while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
+           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
+    {
+    }
+
+    /* Disable PLL first, then configure PLL. */
+    MCG->C6 &= ~MCG_C6_PLLS_MASK;
+    while (MCG->S & MCG_S_PLLST_MASK)
+    {
+    }
+
+    /* Configure the PLL. */
+    {
+        CLOCK_EnablePll0(config);
+    }
+
+    /* Change to PLL mode. */
+    MCG->C6 |= MCG_C6_PLLS_MASK;
+    while (!(MCG->S & MCG_S_PLLST_MASK))
+    {
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_SetPeeMode(void)
+{
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+    mcg_mode_t mode = CLOCK_GetMode();
+    if (kMCG_ModePBE != mode)
+    {
+        return kStatus_MCG_ModeUnreachable;
+    }
+#endif
+
+    /* Change to use PLL/FLL output clock first. */
+    MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut);
+
+    /* Wait for clock status bits to update */
+    while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll)
+    {
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_ExternalModeToFbeModeQuick(void)
+{
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+    if (MCG->S & MCG_S_IREFST_MASK)
+    {
+        return kStatus_MCG_ModeInvalid;
+    }
+#endif /* MCG_CONFIG_CHECK_PARAM */
+
+    /* Disable low power */
+    MCG->C2 &= ~MCG_C2_LP_MASK;
+
+    MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
+    while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
+    {
+    }
+
+    /* Disable PLL. */
+    MCG->C6 &= ~MCG_C6_PLLS_MASK;
+    while (MCG->S & MCG_S_PLLST_MASK)
+    {
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_InternalModeToFbiModeQuick(void)
+{
+#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
+    if (!(MCG->S & MCG_S_IREFST_MASK))
+    {
+        return kStatus_MCG_ModeInvalid;
+    }
+#endif
+
+    /* Disable low power */
+    MCG->C2 &= ~MCG_C2_LP_MASK;
+
+    MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
+    while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
+    {
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
+{
+    return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
+}
+
+status_t CLOCK_BootToFeeMode(
+    mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
+{
+    CLOCK_SetExternalRefClkConfig(oscsel);
+
+    return CLOCK_SetFeeMode(frdiv, dmx32, drs, fllStableDelay);
+}
+
+status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
+{
+    /* If reset mode is FEI mode, set MCGIRCLK and always success. */
+    CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
+
+    /* If reset mode is not BLPI, first enter FBI mode. */
+    MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal);
+    while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
+    {
+    }
+
+    /* Enter BLPI mode. */
+    MCG->C2 |= MCG_C2_LP_MASK;
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
+{
+    CLOCK_SetExternalRefClkConfig(oscsel);
+
+    /* Set to FBE mode. */
+    MCG->C1 =
+        ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal)    /* CLKS = 2 */
+                                                                | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
+
+    /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
+    while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
+           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
+    {
+    }
+
+    /* In FBE now, start to enter BLPE. */
+    MCG->C2 |= MCG_C2_LP_MASK;
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
+{
+    assert(config);
+
+    CLOCK_SetExternalRefClkConfig(oscsel);
+
+    CLOCK_SetPbeMode(pllcs, config);
+
+    /* Change to use PLL output clock. */
+    MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut);
+    while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll)
+    {
+    }
+
+    return kStatus_Success;
+}
+
+/*
+   The transaction matrix. It defines the path for mode switch, the row is for
+   current mode and the column is target mode.
+   For example, switch from FEI to PEE:
+   1. Current mode FEI, next mode is mcgModeMatrix[FEI][PEE] = FBE, so swith to FBE.
+   2. Current mode FBE, next mode is mcgModeMatrix[FBE][PEE] = PBE, so swith to PBE.
+   3. Current mode PBE, next mode is mcgModeMatrix[PBE][PEE] = PEE, so swith to PEE.
+   Thus the MCG mode has changed from FEI to PEE.
+ */
+static const mcg_mode_t mcgModeMatrix[8][8] = {
+    {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE,
+     kMCG_ModeFBE}, /* FEI */
+    {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE,
+     kMCG_ModeFBE}, /* FBI */
+    {kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI,
+     kMCG_ModeFBI}, /* BLPI */
+    {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE,
+     kMCG_ModeFBE}, /* FEE */
+    {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE,
+     kMCG_ModePBE}, /* FBE */
+    {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE,
+     kMCG_ModePBE}, /* BLPE */
+    {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE,
+     kMCG_ModePEE}, /* PBE */
+    {kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE,
+     kMCG_ModePBE} /* PEE */
+    /*    FEI           FBI           BLPI           FEE           FBE           BLPE           PBE           PEE */
+};
+
+status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
+{
+    mcg_mode_t next_mode;
+    status_t status = kStatus_Success;
+
+    mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0;
+
+    /* If need to change external clock, MCG_C7[OSCSEL]. */
+    if (MCG_C7_OSCSEL_VAL != config->oscsel)
+    {
+        /* If external clock is in use, change to FEI first. */
+        if (!(MCG->S & MCG_S_IRCST_MASK))
+        {
+            CLOCK_ExternalModeToFbeModeQuick();
+            CLOCK_SetFeiMode(config->dmx32, config->drs, (void (*)(void))0);
+        }
+
+        CLOCK_SetExternalRefClkConfig(config->oscsel);
+    }
+
+    /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
+    if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt)
+    {
+        MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
+
+        {
+            CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
+        }
+    }
+
+    /* Configure MCGIRCLK. */
+    CLOCK_SetInternalRefClkConfig(config->irclkEnableMode, config->ircs, config->fcrdiv);
+
+    next_mode = CLOCK_GetMode();
+
+    do
+    {
+        next_mode = mcgModeMatrix[next_mode][config->mcgMode];
+
+        switch (next_mode)
+        {
+            case kMCG_ModeFEI:
+                status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
+                break;
+            case kMCG_ModeFEE:
+                status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
+                break;
+            case kMCG_ModeFBI:
+                status = CLOCK_SetFbiMode(config->dmx32, config->drs, (void (*)(void))0);
+                break;
+            case kMCG_ModeFBE:
+                status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0);
+                break;
+            case kMCG_ModeBLPI:
+                status = CLOCK_SetBlpiMode();
+                break;
+            case kMCG_ModeBLPE:
+                status = CLOCK_SetBlpeMode();
+                break;
+            case kMCG_ModePBE:
+                /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
+                if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
+                {
+                    {
+                        status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
+                    }
+                }
+                else
+                {
+                    MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
+                    while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
+                    {
+                    }
+                }
+                break;
+            case kMCG_ModePEE:
+                status = CLOCK_SetPeeMode();
+                break;
+            default:
+                break;
+        }
+        if (kStatus_Success != status)
+        {
+            return status;
+        }
+    } while (next_mode != config->mcgMode);
+
+    if (config->pll0Config.enableMode & kMCG_PllEnableIndependent)
+    {
+        CLOCK_EnablePll0(&config->pll0Config);
+    }
+    else
+    {
+        MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent;
+    }
+    return kStatus_Success;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_clock.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_clock.h
new file mode 100644
index 00000000000..ba7428f4c24
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_clock.h
@@ -0,0 +1,1505 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_device_registers.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.2.0. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*@}*/
+
+/*! @brief External XTAL0 (OSC0) clock frequency.
+ *
+ * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
+ * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
+ * if XTAL0 is 8 MHz:
+ * @code
+ * CLOCK_InitOsc0(...); // Set up the OSC0
+ * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to the clock driver.
+ * @endcode
+ *
+ * This is important for the multicore platforms where only one core needs to set up the
+ * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
+ * to get a valid clock frequency.
+ */
+extern uint32_t g_xtal0Freq;
+
+/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
+ *
+ * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
+ * function CLOCK_SetXtal32Freq to set the value in the clock driver.
+ *
+ * This is important for the multicore platforms where only one core needs to set up
+ * the clock. All other cores need to call the CLOCK_SetXtal32Freq
+ * to get a valid clock frequency.
+ */
+extern uint32_t g_xtal32Freq;
+
+/*! @brief IRC48M clock frequency in Hz. */
+#define MCG_INTERNAL_IRC_48M 48000000U
+
+#if (defined(OSC) && !(defined(OSC0)))
+#define OSC0 OSC
+#endif
+
+/*! @brief Clock ip name array for DMAMUX. */
+#define DMAMUX_CLOCKS  \
+    {                  \
+        kCLOCK_Dmamux0 \
+    }
+
+/*! @brief Clock ip name array for RTC. */
+#define RTC_CLOCKS  \
+    {               \
+        kCLOCK_Rtc0 \
+    }
+
+/*! @brief Clock ip name array for PORT. */
+#define PORT_CLOCKS                                                          \
+    {                                                                        \
+        kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
+    }
+
+/*! @brief Clock ip name array for EWM. */
+#define EWM_CLOCKS  \
+    {               \
+        kCLOCK_Ewm0 \
+    }
+
+/*! @brief Clock ip name array for PIT. */
+#define PIT_CLOCKS  \
+    {               \
+        kCLOCK_Pit0 \
+    }
+
+/*! @brief Clock ip name array for DSPI. */
+#define DSPI_CLOCKS              \
+    {                            \
+        kCLOCK_Spi0, kCLOCK_Spi1 \
+    }
+
+/*! @brief Clock ip name array for EMVSIM. */
+#define EMVSIM_CLOCKS                  \
+    {                                  \
+        kCLOCK_Emvsim0, kCLOCK_Emvsim1 \
+    }
+
+/*! @brief Clock ip name array for QSPI. */
+#define QSPI_CLOCKS  \
+    {                \
+        kCLOCK_Qspi0 \
+    }
+
+/*! @brief Clock ip name array for EDMA. */
+#define EDMA_CLOCKS \
+    {               \
+        kCLOCK_Dma0 \
+    }
+
+/*! @brief Clock ip name array for LPUART. */
+#define LPUART_CLOCKS                                  \
+    {                                                  \
+        kCLOCK_Lpuart0, kCLOCK_Lpuart1, kCLOCK_Lpuart2 \
+    }
+
+/*! @brief Clock ip name array for DAC. */
+#define DAC_CLOCKS  \
+    {               \
+        kCLOCK_Dac0 \
+    }
+
+/*! @brief Clock ip name array for LPTMR. */
+#define LPTMR_CLOCKS                 \
+    {                                \
+        kCLOCK_Lptmr0, kCLOCK_Lptmr1 \
+    }
+
+/*! @brief Clock ip name array for ADC16. */
+#define ADC16_CLOCKS \
+    {                \
+        kCLOCK_Adc0  \
+    }
+
+/*! @brief Clock ip name array for TRNG. */
+#define TRNG_CLOCKS  \
+    {                \
+        kCLOCK_Trng0 \
+    }
+
+/*! @brief Clock ip name array for MPU. */
+#define MPU_CLOCKS  \
+    {               \
+        kCLOCK_Mpu0 \
+    }
+
+/*! @brief Clock ip name array for FLEXIO. */
+#define FLEXIO_CLOCKS  \
+    {                  \
+        kCLOCK_Flexio0 \
+    }
+
+/*! @brief Clock ip name array for VREF. */
+#define VREF_CLOCKS  \
+    {                \
+        kCLOCK_Vref0 \
+    }
+
+/*! @brief Clock ip name array for TPM. */
+#define TPM_CLOCKS                            \
+    {                                         \
+        kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2 \
+    }
+
+/*! @brief Clock ip name array for TSI. */
+#define TSI_CLOCKS  \
+    {               \
+        kCLOCK_Tsi0 \
+    }
+
+/*! @brief Clock ip name array for LTC. */
+#define LTC_CLOCKS  \
+    {               \
+        kCLOCK_Ltc0 \
+    }
+
+/*! @brief Clock ip name array for CRC. */
+#define CRC_CLOCKS  \
+    {               \
+        kCLOCK_Crc0 \
+    }
+
+/*! @brief Clock ip name array for I2C. */
+#define I2C_CLOCKS               \
+    {                            \
+        kCLOCK_I2c0, kCLOCK_I2c1 \
+    }
+
+/*! @brief Clock ip name array for CMP. */
+#define CMP_CLOCKS  \
+    {               \
+        kCLOCK_Cmp0 \
+    }
+
+/*! @brief Clock ip name array for INTMUX. */
+#define INTMUX_CLOCKS  \
+    {                  \
+        kCLOCK_Intmux0 \
+    }
+
+/*!
+ * @brief LPO clock frequency.
+ */
+#define LPO_CLK_FREQ 1000U
+
+/*! @brief Peripherals clock source definition. */
+#define SYS_CLK kCLOCK_CoreSysClk
+#define BUS_CLK kCLOCK_BusClk
+
+#define I2C0_CLK_SRC BUS_CLK
+#define I2C1_CLK_SRC BUS_CLK
+#define DSPI0_CLK_SRC SYS_CLK
+#define DSPI1_CLK_SRC SYS_CLK
+
+/*! @brief Clock name used to get clock frequency. */
+typedef enum _clock_name
+{
+
+    /* ----------------------------- System layer clock -------------------------------*/
+    kCLOCK_CoreSysClk,    /*!< Core/system clock                                         */
+    kCLOCK_PlatClk,       /*!< Platform clock                                            */
+    kCLOCK_BusClk,        /*!< Bus clock                                                 */
+    kCLOCK_FlashClk,      /*!< Flash clock                                               */
+    kCLOCK_FastPeriphClk, /*!< Fast peripheral clock                                     */
+    kCLOCK_PllFllSelClk,  /*!< The clock after SIM[PLLFLLSEL]                            */
+    kCLOCK_QspiBusClk,    /*!< QSPI bus interface clock                                  */
+
+    /* ---------------------------------- OSC clock -----------------------------------*/
+    kCLOCK_Er32kClk,       /*!< External reference 32K clock (ERCLK32K)                   */
+    kCLOCK_Osc0ErClk,      /*!< OSC0 external reference clock (OSC0ERCLK)                 */
+    kCLOCK_Osc1ErClk,      /*!< OSC1 external reference clock (OSC1ERCLK)                 */
+    kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
+
+    /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
+    kCLOCK_McgFixedFreqClk,   /*!< MCG fixed frequency clock (MCGFFCLK)                      */
+    kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK)                   */
+    kCLOCK_McgFllClk,         /*!< MCGFLLCLK                                                 */
+    kCLOCK_McgPll0Clk,        /*!< MCGPLL0CLK                                                */
+    kCLOCK_McgPll1Clk,        /*!< MCGPLL1CLK                                                */
+    kCLOCK_McgExtPllClk,      /*!< EXT_PLLCLK                                                */
+    kCLOCK_McgPeriphClk,      /*!< MCG peripheral clock (MCGPCLK)                            */
+    kCLOCK_McgIrc48MClk,      /*!< MCG IRC48M clock                                          */
+
+    /* --------------------------------- Other clock ----------------------------------*/
+    kCLOCK_LpoClk, /*!< LPO clock                                                 */
+
+} clock_name_t;
+
+/*! @brief USB clock source definition. */
+typedef enum _clock_usb_src
+{
+    kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U),   /*!< Use PLL0.      */
+    kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M.    */
+    kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U)                               /*!< Use USB_CLKIN. */
+} clock_usb_src_t;
+
+/*------------------------------------------------------------------------------
+
+ clock_gate_t definition:
+
+ 31                              16                              0
+ -----------------------------------------------------------------
+ | SIM_SCGC register offset       |   control bit offset in SCGC |
+ -----------------------------------------------------------------
+
+ For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
+ SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
+
+              kClockGateSdhc0 = (0x1030 << 16) | 17;
+
+------------------------------------------------------------------------------*/
+
+#define CLK_GATE_REG_OFFSET_SHIFT 16U
+#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U
+#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
+
+#define CLK_GATE_DEFINE(reg_offset, bit_shift)                                  \
+    ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
+     (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
+
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+typedef enum _clock_ip_name
+{
+    kCLOCK_IpInvalid = 0U,
+
+    kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
+    kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
+    kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
+    kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
+    kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
+    kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
+
+    kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
+    kCLOCK_Secreg0 = CLK_GATE_DEFINE(0x1038U, 3U),
+    kCLOCK_Lptmr1 = CLK_GATE_DEFINE(0x1038U, 4U),
+    kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U),
+    kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
+    kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
+    kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
+    kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
+    kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
+    kCLOCK_Emvsim0 = CLK_GATE_DEFINE(0x1038U, 14U),
+    kCLOCK_Emvsim1 = CLK_GATE_DEFINE(0x1038U, 15U),
+    kCLOCK_Ltc0 = CLK_GATE_DEFINE(0x1038U, 17U),
+    kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x1038U, 20U),
+    kCLOCK_Lpuart1 = CLK_GATE_DEFINE(0x1038U, 21U),
+    kCLOCK_Lpuart2 = CLK_GATE_DEFINE(0x1038U, 22U),
+    kCLOCK_Qspi0 = CLK_GATE_DEFINE(0x1038U, 26U),
+    kCLOCK_Flexio0 = CLK_GATE_DEFINE(0x1038U, 31U),
+
+    kCLOCK_Nvm0 = CLK_GATE_DEFINE(0x103CU, 0U),
+    kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
+    kCLOCK_Intmux0 = CLK_GATE_DEFINE(0x103CU, 4U),
+    kCLOCK_Trng0 = CLK_GATE_DEFINE(0x103CU, 5U),
+    kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
+    kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
+    kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
+    kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
+    kCLOCK_Tpm0 = CLK_GATE_DEFINE(0x103CU, 24U),
+    kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x103CU, 25U),
+    kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x103CU, 26U),
+    kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
+    kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
+    kCLOCK_Rtc_Rf0 = CLK_GATE_DEFINE(0x103CU, 30U),
+    kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
+
+    kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
+    kCLOCK_Mpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
+} clock_ip_name_t;
+
+/*!@brief SIM configuration structure for clock setting. */
+typedef struct _sim_clock_config
+{
+    uint8_t pllFllSel;  /*!< PLL/FLL/IRC48M selection.         */
+    uint8_t pllFllDiv;  /*!< PLLFLLSEL clock divider divisor.  */
+    uint8_t pllFllFrac; /*!< PLLFLLSEL clock divider fraction. */
+    uint8_t er32kSrc;   /*!< ERCLK32K source selection.        */
+    uint32_t clkdiv1;   /*!< SIM_CLKDIV1.                      */
+} sim_clock_config_t;
+
+/*! @brief OSC work mode. */
+typedef enum _osc_mode
+{
+    kOSC_ModeExt = 0U, /*!< Use an external clock.   */
+#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
+    kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
+#else
+    kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
+#endif
+    kOSC_ModeOscHighGain = 0U
+#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
+                           |
+                           MCG_C2_EREFS_MASK
+#else
+                           |
+                           MCG_C2_EREFS0_MASK
+#endif
+#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
+                           |
+                           MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
+#else
+                           |
+                           MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
+#endif
+} osc_mode_t;
+
+/*! @brief Oscillator capacitor load setting.*/
+enum _osc_cap_load
+{
+    kOSC_Cap2P = OSC_CR_SC2P_MASK,  /*!< 2  pF capacitor load */
+    kOSC_Cap4P = OSC_CR_SC4P_MASK,  /*!< 4  pF capacitor load */
+    kOSC_Cap8P = OSC_CR_SC8P_MASK,  /*!< 8  pF capacitor load */
+    kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
+};
+
+/*! @brief OSCERCLK enable mode. */
+enum _oscer_enable_mode
+{
+    kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK,       /*!< Enable.              */
+    kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
+};
+
+/*! @brief OSC configuration for OSCERCLK. */
+typedef struct _oscer_config
+{
+    uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
+
+    uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/
+} oscer_config_t;
+
+/*!
+ * @brief OSC Initialization Configuration Structure
+ *
+ * Defines the configuration data structure to initialize the OSC.
+ * When porting to a new board, set the following members
+ * according to the board setting:
+ * 1. freq: The external frequency.
+ * 2. workMode: The OSC module mode.
+ */
+typedef struct _osc_config
+{
+    uint32_t freq;              /*!< External clock frequency.    */
+    uint8_t capLoad;            /*!< Capacitor load setting.      */
+    osc_mode_t workMode;        /*!< OSC work mode setting.       */
+    oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK.  */
+} osc_config_t;
+
+/*! @brief MCG FLL reference clock source select. */
+typedef enum _mcg_fll_src
+{
+    kMCG_FllSrcExternal, /*!< External reference clock is selected          */
+    kMCG_FllSrcInternal  /*!< The slow internal reference clock is selected */
+} mcg_fll_src_t;
+
+/*! @brief MCG internal reference clock select */
+typedef enum _mcg_irc_mode
+{
+    kMCG_IrcSlow, /*!< Slow internal reference clock selected */
+    kMCG_IrcFast  /*!< Fast internal reference clock selected */
+} mcg_irc_mode_t;
+
+/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
+typedef enum _mcg_dmx32
+{
+    kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
+    kMCG_Dmx32Fine     /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
+} mcg_dmx32_t;
+
+/*! @brief MCG DCO range select */
+typedef enum _mcg_drs
+{
+    kMCG_DrsLow,     /*!< Low frequency range       */
+    kMCG_DrsMid,     /*!< Mid frequency range       */
+    kMCG_DrsMidHigh, /*!< Mid-High frequency range  */
+    kMCG_DrsHigh     /*!< High frequency range      */
+} mcg_drs_t;
+
+/*! @brief MCG PLL reference clock select */
+typedef enum _mcg_pll_ref_src
+{
+    kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock                 */
+    kMCG_PllRefOsc1  /*!< Selects OSC1 as PLL reference clock                 */
+} mcg_pll_ref_src_t;
+
+/*! @brief MCGOUT clock source. */
+typedef enum _mcg_clkout_src
+{
+    kMCG_ClkOutSrcOut,      /*!< Output of the FLL is selected (reset default)  */
+    kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected           */
+    kMCG_ClkOutSrcExternal, /*!< External reference clock is selected           */
+} mcg_clkout_src_t;
+
+/*! @brief MCG Automatic Trim Machine Select */
+typedef enum _mcg_atm_select
+{
+    kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected  */
+    kMCG_AtmSel4m   /*!< 4 MHz Internal Reference Clock selected   */
+} mcg_atm_select_t;
+
+/*! @brief MCG OSC Clock Select */
+typedef enum _mcg_oscsel
+{
+    kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
+    kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator      */
+    kMCG_OscselIrc  /*!< Selects 48 MHz IRC Oscillator      */
+} mcg_oscsel_t;
+
+/*! @brief MCG PLLCS select */
+typedef enum _mcg_pll_clk_select
+{
+    kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected  */
+    kMCG_PllClkSelPll1  /* PLL1 output clock is selected    */
+} mcg_pll_clk_select_t;
+
+/*! @brief MCG clock monitor mode. */
+typedef enum _mcg_monitor_mode
+{
+    kMCG_MonitorNone, /*!< Clock monitor is disabled.         */
+    kMCG_MonitorInt,  /*!< Trigger interrupt when clock lost. */
+    kMCG_MonitorReset /*!< System reset when clock lost.      */
+} mcg_monitor_mode_t;
+
+/*! @brief MCG status. */
+enum _mcg_status
+{
+    kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0),       /*!< Can't switch to target mode. */
+    kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1),           /*!< Current mode invalid for the specific
+                                                                               function. */
+    kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2),    /*!< Invalid bus clock for ATM. */
+    kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */
+    kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4),            /*!< IRC is used when using ATM. */
+    kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5),       /*!< Hardware fail occurs during ATM. */
+    kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6)             /*!< Can't change the clock source because
+                                                                               it is in use. */
+};
+
+/*! @brief MCG status flags. */
+enum _mcg_status_flags_t
+{
+    kMCG_Osc0LostFlag = (1U << 0U),   /*!< OSC0 lost.         */
+    kMCG_Osc0InitFlag = (1U << 1U),   /*!< OSC0 crystal initialized. */
+    kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost.      */
+    kMCG_Pll0LostFlag = (1U << 5U),   /*!< PLL0 lost.         */
+    kMCG_Pll0LockFlag = (1U << 6U),   /*!< PLL0 locked.       */
+};
+
+/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
+enum _mcg_irclk_enable_mode
+{
+    kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK,       /*!< MCGIRCLK enable.              */
+    kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
+};
+
+/*! @brief MCG PLL clock enable mode definition. */
+enum _mcg_pll_enable_mode
+{
+    kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
+                                                           MCG clock mode. Generally, the PLL
+                                                           is disabled in FLL modes
+                                                           (FEI/FBI/FEE/FBE). Setting the PLL clock
+                                                           enable independent, enables the
+                                                           PLL in the FLL modes.          */
+    kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK        /*!< MCGPLLCLK enable in STOP mode. */
+};
+
+/*! @brief MCG mode definitions */
+typedef enum _mcg_mode
+{
+    kMCG_ModeFEI = 0U, /*!< FEI   - FLL Engaged Internal         */
+    kMCG_ModeFBI,      /*!< FBI   - FLL Bypassed Internal        */
+    kMCG_ModeBLPI,     /*!< BLPI  - Bypassed Low Power Internal  */
+    kMCG_ModeFEE,      /*!< FEE   - FLL Engaged External         */
+    kMCG_ModeFBE,      /*!< FBE   - FLL Bypassed External        */
+    kMCG_ModeBLPE,     /*!< BLPE  - Bypassed Low Power External  */
+    kMCG_ModePBE,      /*!< PBE   - PLL Bypassed External        */
+    kMCG_ModePEE,      /*!< PEE   - PLL Engaged External         */
+    kMCG_ModeError     /*!< Unknown mode                         */
+} mcg_mode_t;
+
+/*! @brief MCG PLL configuration. */
+typedef struct _mcg_pll_config
+{
+    uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */
+    uint8_t prdiv;      /*!< Reference divider PRDIV.    */
+    uint8_t vdiv;       /*!< VCO divider VDIV.           */
+} mcg_pll_config_t;
+
+/*! @brief MCG mode change configuration structure
+ *
+ * When porting to a new board, set the following members
+ * according to the board setting:
+ * 1. frdiv: If the FLL uses the external reference clock, set this
+ *    value to ensure that the external reference clock divided by frdiv is
+ *    in the 31.25 kHz to 39.0625 kHz range.
+ * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
+ *    PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
+ *    FSL_FEATURE_MCG_PLL_REF_MAX range.
+ */
+typedef struct _mcg_config
+{
+    mcg_mode_t mcgMode; /*!< MCG mode.                   */
+
+    /* ----------------------- MCGIRCCLK settings ------------------------ */
+    uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode.       */
+    mcg_irc_mode_t ircs;     /*!< Source, MCG_C2[IRCS].       */
+    uint8_t fcrdiv;          /*!< Divider, MCG_SC[FCRDIV].    */
+
+    /* ------------------------ MCG FLL settings ------------------------- */
+    uint8_t frdiv;       /*!< Divider MCG_C1[FRDIV].      */
+    mcg_drs_t drs;       /*!< DCO range MCG_C4[DRST_DRS]. */
+    mcg_dmx32_t dmx32;   /*!< MCG_C4[DMX32].              */
+    mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL].  */
+
+    /* ------------------------ MCG PLL settings ------------------------- */
+    mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration.   */
+
+} mcg_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief Enable the clock for specific IP.
+ *
+ * @param name  Which clock to enable, see \ref clock_ip_name_t.
+ */
+static inline void CLOCK_EnableClock(clock_ip_name_t name)
+{
+    uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
+    (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
+}
+
+/*!
+ * @brief Disable the clock for specific IP.
+ *
+ * @param name  Which clock to disable, see \ref clock_ip_name_t.
+ */
+static inline void CLOCK_DisableClock(clock_ip_name_t name)
+{
+    uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
+    (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
+}
+
+/*!
+ * @brief Set ERCLK32K source.
+ *
+ * @param src The value to set ERCLK32K clock source.
+ */
+static inline void CLOCK_SetEr32kClock(uint32_t src)
+{
+    SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
+}
+
+/*!
+ * @brief Set EMVSIM clock source.
+ *
+ * @param src The value to set EMVSIM clock source.
+ */
+static inline void CLOCK_SetEmvsimClock(uint32_t src)
+{
+    SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_EMVSIMSRC_MASK) | SIM_SOPT2_EMVSIMSRC(src));
+}
+
+/*!
+ * @brief Set LPUART clock source.
+ *
+ * @param src The value to set LPUART clock source.
+ */
+static inline void CLOCK_SetLpuartClock(uint32_t src)
+{
+    SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) | SIM_SOPT2_LPUARTSRC(src));
+}
+
+/*!
+ * @brief Set TPM clock source.
+ *
+ * @param src The value to set TPM clock source.
+ */
+static inline void CLOCK_SetTpmClock(uint32_t src)
+{
+    SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src));
+}
+
+/*!
+ * @brief Set FLEXIO clock source.
+ *
+ * @param src The value to set FLEXIO clock source.
+ */
+static inline void CLOCK_SetFlexio0Clock(uint32_t src)
+{
+    SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_FLEXIOSRC_MASK) | SIM_SOPT2_FLEXIOSRC(src));
+}
+
+/*!
+ * @brief Set PLLFLLSEL clock source.
+ *
+ * @param src The value to set PLLFLLSEL clock source.
+ */
+static inline void CLOCK_SetPllFllSelClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
+{
+    SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
+    SIM->CLKDIV3 = SIM_CLKDIV3_PLLFLLDIV(divValue) | SIM_CLKDIV3_PLLFLLFRAC(fracValue);
+}
+
+/*!
+ * @brief Set CLKOUT source.
+ *
+ * @param src The value to set CLKOUT source.
+ */
+static inline void CLOCK_SetClkOutClock(uint32_t src)
+{
+    SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUT_MASK) | SIM_SOPT2_CLKOUT(src));
+}
+
+/*!
+ * @brief Set RTC_CLKOUT source.
+ *
+ * @param src The value to set RTC_CLKOUT source.
+ */
+static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
+{
+    SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTS_MASK) | SIM_SOPT2_RTCCLKOUTS(src));
+}
+
+/*! @brief Enable USB FS clock.
+ *
+ * @param src  USB FS clock source.
+ * @param freq The frequency specified by src.
+ * @retval true The clock is set successfully.
+ * @retval false The clock source is invalid to get proper USB FS clock.
+ */
+bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Disable USB FS clock.
+ *
+ * Disable USB FS clock.
+ */
+static inline void CLOCK_DisableUsbfs0Clock(void)
+{
+    CLOCK_DisableClock(kCLOCK_Usbfs0);
+}
+
+/*!
+ * @brief System clock divider
+ *
+ * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV4], SIM_CLKDIV1[OUTDIV5].
+ *
+ * @param outdiv1 Clock 1 output divider value.
+ *
+ * @param outdiv2 Clock 2 output divider value.
+ *
+ * @param outdiv4 Clock 4 output divider value.
+ *
+ * @param outdiv5 Clock 5 output divider value.
+ */
+static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv4, uint32_t outdiv5)
+{
+    SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV4(outdiv4) |
+                   SIM_CLKDIV1_OUTDIV5(outdiv5);
+}
+
+/*!
+ * @brief Gets the clock frequency for a specific clock name.
+ *
+ * This function checks the current clock configurations and then calculates
+ * the clock frequency for a specific clock name defined in clock_name_t.
+ * The MCG must be properly configured before using this function.
+ *
+ * @param clockName Clock names defined in clock_name_t
+ * @return Clock frequency value in Hertz
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName);
+
+/*!
+ * @brief Get the core clock or system clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void);
+
+/*!
+ * @brief Get the platform clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetPlatClkFreq(void);
+
+/*!
+ * @brief Get the bus clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetBusClkFreq(void);
+
+/*!
+ * @brief Get the flash clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetFlashClkFreq(void);
+
+/*!
+ * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetPllFllSelClkFreq(void);
+
+/*!
+ * @brief Get the QSPI bus interface clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetQspiBusClkFreq(void);
+
+/*!
+ * @brief Get the external reference 32K clock frequency (ERCLK32K).
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetEr32kClkFreq(void);
+
+/*!
+ * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV).
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetOsc0ErClkUndivFreq(void);
+
+/*!
+ * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetOsc0ErClkFreq(void);
+
+/*!
+ * @brief Set the clock configure in SIM module.
+ *
+ * This function sets system layer clock settings in SIM module.
+ *
+ * @param config Pointer to the configure structure.
+ */
+void CLOCK_SetSimConfig(sim_clock_config_t const *config);
+
+/*!
+ * @brief Set the system clock dividers in SIM to safe value.
+ *
+ * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
+ * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
+ * changes then the system level clocks may be out of range. This function could
+ * be used before MCG mode change, to make sure system level clocks are in allowed
+ * range.
+ *
+ * @param config Pointer to the configure structure.
+ */
+static inline void CLOCK_SetSimSafeDivs(void)
+{
+    SIM->CLKDIV1 = 0x15051000U;
+}
+
+/*! @name MCG frequency functions. */
+/*@{*/
+
+/*!
+ * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
+ *
+ * This function gets the MCG output clock frequency in Hz based on the current MCG
+ * register value.
+ *
+ * @return The frequency of MCGOUTCLK.
+ */
+uint32_t CLOCK_GetOutClkFreq(void);
+
+/*!
+ * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
+ *
+ * This function gets the MCG FLL clock frequency in Hz based on the current MCG
+ * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
+ * disabled in low power state in other modes.
+ *
+ * @return The frequency of MCGFLLCLK.
+ */
+uint32_t CLOCK_GetFllFreq(void);
+
+/*!
+ * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
+ *
+ * This function gets the MCG internal reference clock frequency in Hz based
+ * on the current MCG register value.
+ *
+ * @return The frequency of MCGIRCLK.
+ */
+uint32_t CLOCK_GetInternalRefClkFreq(void);
+
+/*!
+ * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
+ *
+ * This function gets the MCG fixed frequency clock frequency in Hz based
+ * on the current MCG register value.
+ *
+ * @return The frequency of MCGFFCLK.
+ */
+uint32_t CLOCK_GetFixedFreqClkFreq(void);
+
+/*!
+ * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
+ *
+ * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
+ * register value.
+ *
+ * @return The frequency of MCGPLL0CLK.
+ */
+uint32_t CLOCK_GetPll0Freq(void);
+
+/*@}*/
+
+/*! @name MCG clock configuration. */
+/*@{*/
+
+/*!
+ * @brief Enables or disables the MCG low power.
+ *
+ * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
+ * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
+ * PBI modes, enabling low power sets the MCG to BLPI mode.
+ * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
+ *
+ * @param enable True to enable MCG low power, false to disable MCG low power.
+ */
+static inline void CLOCK_SetLowPowerEnable(bool enable)
+{
+    if (enable)
+    {
+        MCG->C2 |= MCG_C2_LP_MASK;
+    }
+    else
+    {
+        MCG->C2 &= ~MCG_C2_LP_MASK;
+    }
+}
+
+/*!
+ * @brief Configures the Internal Reference clock (MCGIRCLK).
+ *
+ * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
+ * source. If the fast IRC is used, this function sets the fast IRC divider.
+ * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
+ * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
+ * using the function in these modes it is not allowed.
+ *
+ * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
+ * @param ircs       MCGIRCLK clock source, choose fast or slow.
+ * @param fcrdiv     Fast IRC divider setting (\c FCRDIV).
+ * @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source,
+ * the confuration should not be changed. Otherwise, a glitch occurs.
+ * @retval kStatus_Success MCGIRCLK configuration finished successfully.
+ */
+status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
+
+/*!
+ * @brief Selects the MCG external reference clock.
+ *
+ * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
+ * and waits for the clock source to be stable. Because the external reference
+ * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
+ *
+ * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
+ * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
+ * the confuration should not be changed. Otherwise, a glitch occurs.
+ * @retval kStatus_Success External reference clock set successfully.
+ */
+status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
+
+/*!
+ * @brief Enables the PLL0 in FLL mode.
+ *
+ * This function sets us the PLL0 in FLL mode and reconfigures
+ * the PLL0. Ensure that the PLL reference
+ * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
+ * The function CLOCK_CalcPllDiv gets the correct PLL
+ * divider values.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CLOCK_EnablePll0(mcg_pll_config_t const *config);
+
+/*!
+ * @brief Disables the PLL0 in FLL mode.
+ *
+ * This function disables the PLL0 in FLL mode. It should be used together with the
+ * @ref CLOCK_EnablePll0.
+ */
+static inline void CLOCK_DisablePll0(void)
+{
+    MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK);
+}
+
+/*!
+ * @brief Calculates the PLL divider setting for a desired output frequency.
+ *
+ * This function calculates the correct reference clock divider (\c PRDIV) and
+ * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
+ * closest frequency match with the corresponding \c PRDIV/VDIV
+ * returned from parameters. If a desired frequency is not valid, this function
+ * returns 0.
+ *
+ * @param refFreq    PLL reference clock frequency.
+ * @param desireFreq Desired PLL output frequency.
+ * @param prdiv      PRDIV value to generate desired PLL frequency.
+ * @param vdiv       VDIV value to generate desired PLL frequency.
+ * @return Closest frequency match that the PLL was able generate.
+ */
+uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
+
+/*@}*/
+
+/*! @name MCG clock lock monitor functions. */
+/*@{*/
+
+/*!
+ * @brief Sets the OSC0 clock monitor mode.
+ *
+ * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
+ *
+ * @param mode Monitor mode to set.
+ */
+void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
+
+/*!
+ * @brief Sets the RTC OSC clock monitor mode.
+ *
+ * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
+ *
+ * @param mode Monitor mode to set.
+ */
+void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
+
+/*!
+ * @brief Sets the PLL0 clock monitor mode.
+ *
+ * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
+ *
+ * @param mode Monitor mode to set.
+ */
+void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
+
+/*!
+ * @brief Gets the MCG status flags.
+ *
+ * This function gets the MCG clock status flags. All status flags are
+ * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
+ * check a specific flag, compare the return value with the flag.
+ *
+ * Example:
+ * @code
+   // To check the clock lost lock status of OSC0 and PLL0.
+   uint32_t mcgFlags;
+
+   mcgFlags = CLOCK_GetStatusFlags();
+
+   if (mcgFlags & kMCG_Osc0LostFlag)
+   {
+       // OSC0 clock lock lost. Do something.
+   }
+   if (mcgFlags & kMCG_Pll0LostFlag)
+   {
+       // PLL0 clock lock lost. Do something.
+   }
+   @endcode
+ *
+ * @return  Logical OR value of the @ref _mcg_status_flags_t.
+ */
+uint32_t CLOCK_GetStatusFlags(void);
+
+/*!
+ * @brief Clears the MCG status flags.
+ *
+ * This function clears the MCG clock lock lost status. The parameter is a logical
+ * OR value of the flags to clear. See @ref _mcg_status_flags_t.
+ *
+ * Example:
+ * @code
+   // To clear the clock lost lock status flags of OSC0 and PLL0.
+
+   CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
+   @endcode
+ *
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration @ref _mcg_status_flags_t.
+ */
+void CLOCK_ClearStatusFlags(uint32_t mask);
+
+/*@}*/
+
+/*!
+ * @name OSC configuration
+ * @{
+ */
+
+/*!
+ * @brief Configures the OSC external reference clock (OSCERCLK).
+ *
+ * This function configures the OSC external reference clock (OSCERCLK).
+ * This is an example to enable the OSCERCLK in normal and stop modes and also set
+ * the output divider to 1:
+ *
+   @code
+   oscer_config_t config =
+   {
+       .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
+       .erclkDiv   = 1U,
+   };
+
+   OSC_SetExtRefClkConfig(OSC, &config);
+   @endcode
+ *
+ * @param base   OSC peripheral address.
+ * @param config Pointer to the configuration structure.
+ */
+static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
+{
+    uint8_t reg = base->CR;
+
+    reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK);
+    reg |= config->enableMode;
+
+    base->CR = reg;
+
+    base->DIV = OSC_DIV_ERPS(config->erclkDiv);
+}
+
+/*!
+ * @brief Sets the capacitor load configuration for the oscillator.
+ *
+ * This function sets the specified capacitors configuration for the oscillator.
+ * This should be done in the early system level initialization function call
+ * based on the system configuration.
+ *
+ * @param base   OSC peripheral address.
+ * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
+ *
+ * Example:
+   @code
+   // To enable only 2 pF and 8 pF capacitor load, please use like this.
+   OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
+   @endcode
+ */
+static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
+{
+    uint8_t reg = base->CR;
+
+    reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK);
+    reg |= capLoad;
+
+    base->CR = reg;
+}
+
+/*!
+ * @brief Initializes the OSC0.
+ *
+ * This function initializes the OSC0 according to the board configuration.
+ *
+ * @param  config Pointer to the OSC0 configuration structure.
+ */
+void CLOCK_InitOsc0(osc_config_t const *config);
+
+/*!
+ * @brief Deinitializes the OSC0.
+ *
+ * This function deinitializes the OSC0.
+ */
+void CLOCK_DeinitOsc0(void);
+
+/* @} */
+
+/*!
+ * @name External clock frequency
+ * @{
+ */
+
+/*!
+ * @brief Sets the XTAL0 frequency based on board settings.
+ *
+ * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
+ */
+static inline void CLOCK_SetXtal0Freq(uint32_t freq)
+{
+    g_xtal0Freq = freq;
+}
+
+/*!
+ * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
+ *
+ * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
+ */
+static inline void CLOCK_SetXtal32Freq(uint32_t freq)
+{
+    g_xtal32Freq = freq;
+}
+/* @} */
+
+/*!
+ * @name MCG auto-trim machine.
+ * @{
+ */
+
+/*!
+ * @brief Auto trims the internal reference clock.
+ *
+ * This function trims the internal reference clock by using the external clock. If
+ * successful, it returns the kStatus_Success and the frequency after
+ * trimming is received in the parameter @p actualFreq. If an error occurs,
+ * the error code is returned.
+ *
+ * @param extFreq      External clock frequency, which should be a bus clock.
+ * @param desireFreq   Frequency to trim to.
+ * @param actualFreq   Actual frequency after trimming.
+ * @param atms         Trim fast or slow internal reference clock.
+ * @retval kStatus_Success ATM success.
+ * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
+ * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
+ * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
+ * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
+ */
+status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
+/* @} */
+
+/*! @name MCG mode functions. */
+/*@{*/
+
+/*!
+ * @brief Gets the current MCG mode.
+ *
+ * This function checks the MCG registers and determines the current MCG mode.
+ *
+ * @return Current MCG mode or error code; See @ref mcg_mode_t.
+ */
+mcg_mode_t CLOCK_GetMode(void);
+
+/*!
+ * @brief Sets the MCG to FEI mode.
+ *
+ * This function sets the MCG to FEI mode. If setting to FEI mode fails
+ * from the current mode, this function returns an error.
+ *
+ * @param       dmx32  DMX32 in FEI mode.
+ * @param       drs The DCO range selection.
+ * @param       fllStableDelay Delay function to  ensure that the FLL is stable. Passing
+ *              NULL does not cause a delay.
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
+ * to a frequency above 32768 Hz.
+ */
+status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
+
+/*!
+ * @brief Sets the MCG to FEE mode.
+ *
+ * This function sets the MCG to FEE mode. If setting to FEE mode fails
+ * from the current mode, this function returns an error.
+ *
+ * @param   frdiv  FLL reference clock divider setting, FRDIV.
+ * @param   dmx32  DMX32 in FEE mode.
+ * @param   drs    The DCO range selection.
+ * @param   fllStableDelay Delay function to make sure FLL is stable. Passing
+ *          NULL does not cause a delay.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ */
+status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
+
+/*!
+ * @brief Sets the MCG to FBI mode.
+ *
+ * This function sets the MCG to FBI mode. If setting to FBI mode fails
+ * from the current mode, this function returns an error.
+ *
+ * @param  dmx32  DMX32 in FBI mode.
+ * @param  drs  The DCO range selection.
+ * @param  fllStableDelay Delay function to make sure FLL is stable. If the FLL
+ *         is not used in FBI mode, this parameter can be NULL. Passing
+ *         NULL does not cause a delay.
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
+ * to frequency above 32768 Hz.
+ */
+status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
+
+/*!
+ * @brief Sets the MCG to FBE mode.
+ *
+ * This function sets the MCG to FBE mode. If setting to FBE mode fails
+ * from the current mode, this function returns an error.
+ *
+ * @param   frdiv  FLL reference clock divider setting, FRDIV.
+ * @param   dmx32  DMX32 in FBE mode.
+ * @param   drs    The DCO range selection.
+ * @param   fllStableDelay Delay function to make sure FLL is stable. If the FLL
+ *          is not used in FBE mode, this parameter can be NULL. Passing NULL
+ *          does not cause a delay.
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ */
+status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
+
+/*!
+ * @brief Sets the MCG to BLPI mode.
+ *
+ * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
+ * from the current mode, this function returns an error.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ */
+status_t CLOCK_SetBlpiMode(void);
+
+/*!
+ * @brief Sets the MCG to BLPE mode.
+ *
+ * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
+ * from the current mode, this function returns an error.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ */
+status_t CLOCK_SetBlpeMode(void);
+
+/*!
+ * @brief Sets the MCG to PBE mode.
+ *
+ * This function sets the MCG to PBE mode. If setting to PBE mode fails
+ * from the current mode, this function returns an error.
+ *
+ * @param   pllcs  The PLL selection, PLLCS.
+ * @param   config Pointer to the PLL configuration.
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ *
+ * @note
+ * 1. The parameter \c pllcs selects the PLL. For platforms with
+ * only one PLL, the parameter pllcs is kept for interface compatibility.
+ * 2. The parameter \c config is the PLL configuration structure. On some
+ * platforms,  it is possible to choose the external PLL directly, which renders the
+ * configuration structure not necessary. In this case, pass in NULL.
+ * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
+ */
+status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
+
+/*!
+ * @brief Sets the MCG to PEE mode.
+ *
+ * This function sets the MCG to PEE mode.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ *
+ * @note This function only changes the CLKS to use the PLL/FLL output. If the
+ *       PRDIV/VDIV are different than in the PBE mode, set them up
+ *       in PBE mode and wait. When the clock is stable, switch to PEE mode.
+ */
+status_t CLOCK_SetPeeMode(void);
+
+/*!
+ * @brief Switches the MCG to FBE mode from the external mode.
+ *
+ * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
+ * The external clock is used as the system clock souce and PLL is disabled. However,
+ * the FLL settings are not configured. This is a lite function with a small code size, which is useful
+ * during the mode switch. For example, to switch from PEE mode to FEI mode:
+ *
+ * @code
+ * CLOCK_ExternalModeToFbeModeQuick();
+ * CLOCK_SetFeiMode(...);
+ * @endcode
+ *
+ * @retval kStatus_Success Switched successfully.
+ * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
+ */
+status_t CLOCK_ExternalModeToFbeModeQuick(void);
+
+/*!
+ * @brief Switches the MCG to FBI mode from internal modes.
+ *
+ * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
+ * The MCGIRCLK is used as the system clock souce and PLL is disabled. However,
+ * FLL settings are not configured. This is a lite function with a small code size, which is useful
+ * during the mode switch. For example, to switch from PEI mode to FEE mode:
+ *
+ * @code
+ * CLOCK_InternalModeToFbiModeQuick();
+ * CLOCK_SetFeeMode(...);
+ * @endcode
+ *
+ * @retval kStatus_Success Switched successfully.
+ * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
+ */
+status_t CLOCK_InternalModeToFbiModeQuick(void);
+
+/*!
+ * @brief Sets the MCG to FEI mode during system boot up.
+ *
+ * This function sets the MCG to FEI mode from the reset mode. It can also be used to
+ * set up MCG during system boot up.
+ *
+ * @param  dmx32  DMX32 in FEI mode.
+ * @param  drs The DCO range selection.
+ * @param  fllStableDelay Delay function to ensure that the FLL is stable.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
+ * to frequency above 32768 Hz.
+ */
+status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
+
+/*!
+ * @brief Sets the MCG to FEE mode during system bootup.
+ *
+ * This function sets MCG to FEE mode from the reset mode. It can also be used to
+ * set up the MCG during system boot up.
+ *
+ * @param   oscsel OSC clock select, OSCSEL.
+ * @param   frdiv  FLL reference clock divider setting, FRDIV.
+ * @param   dmx32  DMX32 in FEE mode.
+ * @param   drs    The DCO range selection.
+ * @param   fllStableDelay Delay function to ensure that the FLL is stable.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ */
+status_t CLOCK_BootToFeeMode(
+    mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
+
+/*!
+ * @brief Sets the MCG to BLPI mode during system boot up.
+ *
+ * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
+ * set up the MCG during sytem boot up.
+ *
+ * @param  fcrdiv Fast IRC divider, FCRDIV.
+ * @param  ircs   The internal reference clock to select, IRCS.
+ * @param  ircEnableMode  The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
+ *
+ * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ */
+status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
+
+/*!
+ * @brief Sets the MCG to BLPE mode during sytem boot up.
+ *
+ * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
+ * set up the MCG during sytem boot up.
+ *
+ * @param  oscsel OSC clock select, MCG_C7[OSCSEL].
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ */
+status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
+
+/*!
+ * @brief Sets the MCG to PEE mode during system boot up.
+ *
+ * This function sets the MCG to PEE mode from reset mode. It can also be used to
+ * set up the MCG during system boot up.
+ *
+ * @param   oscsel OSC clock select, MCG_C7[OSCSEL].
+ * @param   pllcs  The PLL selection, PLLCS.
+ * @param   config Pointer to the PLL configuration.
+ *
+ * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ */
+status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
+
+/*!
+ * @brief Sets the MCG to a target mode.
+ *
+ * This function sets MCG to a target mode defined by the configuration
+ * structure. If switching to the target mode fails, this function
+ * chooses the correct path.
+ *
+ * @param  config Pointer to the target MCG mode configuration structure.
+ * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
+ *
+ * @note If the external clock is used in the target mode, ensure that it is
+ * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
+ * function.
+ */
+status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_cmp.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_cmp.c
new file mode 100644
index 00000000000..557a0c58202
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_cmp.c
@@ -0,0 +1,279 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_cmp.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for CMP module.
+ *
+ * @param base CMP peripheral base address
+ */
+static uint32_t CMP_GetInstance(CMP_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to CMP bases for each instance. */
+static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS;
+/*! @brief Pointers to CMP clocks for each instance. */
+static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS;
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+static uint32_t CMP_GetInstance(CMP_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_CMP_COUNT; instance++)
+    {
+        if (s_cmpBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_CMP_COUNT);
+
+    return instance;
+}
+
+void CMP_Init(CMP_Type *base, const cmp_config_t *config)
+{
+    assert(NULL != config);
+
+    uint8_t tmp8;
+
+    /* Enable the clock. */
+    CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]);
+
+    /* Configure. */
+    CMP_Enable(base, false); /* Disable the CMP module during configuring. */
+    /* CMPx_CR1. */
+    tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK);
+    if (config->enableHighSpeed)
+    {
+        tmp8 |= CMP_CR1_PMODE_MASK;
+    }
+    if (config->enableInvertOutput)
+    {
+        tmp8 |= CMP_CR1_INV_MASK;
+    }
+    if (config->useUnfilteredOutput)
+    {
+        tmp8 |= CMP_CR1_COS_MASK;
+    }
+    if (config->enablePinOut)
+    {
+        tmp8 |= CMP_CR1_OPE_MASK;
+    }
+#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
+    if (config->enableTriggerMode)
+    {
+        tmp8 |= CMP_CR1_TRIGM_MASK;
+    }
+    else
+    {
+        tmp8 &= ~CMP_CR1_TRIGM_MASK;
+    }
+#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
+    base->CR1 = tmp8;
+
+    /* CMPx_CR0. */
+    tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK;
+    tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode);
+    base->CR0 = tmp8;
+
+    CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */
+}
+
+void CMP_Deinit(CMP_Type *base)
+{
+    /* Disable the CMP module. */
+    CMP_Enable(base, false);
+
+    /* Disable the clock. */
+    CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]);
+}
+
+void CMP_GetDefaultConfig(cmp_config_t *config)
+{
+    assert(NULL != config);
+
+    config->enableCmp = true; /* Enable the CMP module after initialization. */
+    config->hysteresisMode = kCMP_HysteresisLevel0;
+    config->enableHighSpeed = false;
+    config->enableInvertOutput = false;
+    config->useUnfilteredOutput = false;
+    config->enablePinOut = false;
+#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
+    config->enableTriggerMode = false;
+#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
+}
+
+void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel)
+{
+    uint8_t tmp8 = base->MUXCR;
+
+    tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK);
+    tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel);
+    base->MUXCR = tmp8;
+}
+
+#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
+void CMP_EnableDMA(CMP_Type *base, bool enable)
+{
+    uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
+
+    if (enable)
+    {
+        tmp8 |= CMP_SCR_DMAEN_MASK;
+    }
+    else
+    {
+        tmp8 &= ~CMP_SCR_DMAEN_MASK;
+    }
+    base->SCR = tmp8;
+}
+#endif /* FSL_FEATURE_CMP_HAS_DMA */
+
+void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
+{
+    assert(NULL != config);
+
+    uint8_t tmp8;
+
+#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
+    /* Choose the clock source for sampling. */
+    if (config->enableSample)
+    {
+        base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */
+    }
+    else
+    {
+        base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */
+    }
+#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
+    /* Set the filter count. */
+    tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK;
+    tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount);
+    base->CR0 = tmp8;
+    /* Set the filter period. It is used as the divider to bus clock. */
+    base->FPR = CMP_FPR_FILT_PER(config->filterPeriod);
+}
+
+void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
+{
+    uint8_t tmp8 = 0U;
+
+    if (NULL == config)
+    {
+        /* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/
+        base->DACCR = 0U;
+        return;
+    }
+    /* CMPx_DACCR. */
+    tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */
+    if (kCMP_VrefSourceVin2 == config->referenceVoltageSource)
+    {
+        tmp8 |= CMP_DACCR_VRSEL_MASK;
+    }
+    tmp8 |= CMP_DACCR_VOSEL(config->DACValue);
+
+    base->DACCR = tmp8;
+}
+
+void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
+{
+    uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
+
+    if (0U != (kCMP_OutputRisingInterruptEnable & mask))
+    {
+        tmp8 |= CMP_SCR_IER_MASK;
+    }
+    if (0U != (kCMP_OutputFallingInterruptEnable & mask))
+    {
+        tmp8 |= CMP_SCR_IEF_MASK;
+    }
+    base->SCR = tmp8;
+}
+
+void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
+{
+    uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
+
+    if (0U != (kCMP_OutputRisingInterruptEnable & mask))
+    {
+        tmp8 &= ~CMP_SCR_IER_MASK;
+    }
+    if (0U != (kCMP_OutputFallingInterruptEnable & mask))
+    {
+        tmp8 &= ~CMP_SCR_IEF_MASK;
+    }
+    base->SCR = tmp8;
+}
+
+uint32_t CMP_GetStatusFlags(CMP_Type *base)
+{
+    uint32_t ret32 = 0U;
+
+    if (0U != (CMP_SCR_CFR_MASK & base->SCR))
+    {
+        ret32 |= kCMP_OutputRisingEventFlag;
+    }
+    if (0U != (CMP_SCR_CFF_MASK & base->SCR))
+    {
+        ret32 |= kCMP_OutputFallingEventFlag;
+    }
+    if (0U != (CMP_SCR_COUT_MASK & base->SCR))
+    {
+        ret32 |= kCMP_OutputAssertEventFlag;
+    }
+    return ret32;
+}
+
+void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)
+{
+    uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
+
+    if (0U != (kCMP_OutputRisingEventFlag & mask))
+    {
+        tmp8 |= CMP_SCR_CFR_MASK;
+    }
+    if (0U != (kCMP_OutputFallingEventFlag & mask))
+    {
+        tmp8 |= CMP_SCR_CFF_MASK;
+    }
+    base->SCR = tmp8;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_cmp.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_cmp.h
new file mode 100644
index 00000000000..4c85bba3917
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_cmp.h
@@ -0,0 +1,345 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_CMP_H_
+#define _FSL_CMP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup cmp
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CMP driver version 2.0.0. */
+#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*!
+* @brief Interrupt enable/disable mask.
+*/
+enum _cmp_interrupt_enable
+{
+    kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK,  /*!< Comparator interrupt enable rising. */
+    kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */
+};
+
+/*!
+ * @brief Status flags' mask.
+ */
+enum _cmp_status_flags
+{
+    kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK,  /*!< Rising-edge on compare output has occurred. */
+    kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on compare output has occurred. */
+    kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */
+};
+
+/*!
+ * @brief CMP Hysteresis mode.
+ */
+typedef enum _cmp_hysteresis_mode
+{
+    kCMP_HysteresisLevel0 = 0U, /*!< Hysteresis level 0. */
+    kCMP_HysteresisLevel1 = 1U, /*!< Hysteresis level 1. */
+    kCMP_HysteresisLevel2 = 2U, /*!< Hysteresis level 2. */
+    kCMP_HysteresisLevel3 = 3U, /*!< Hysteresis level 3. */
+} cmp_hysteresis_mode_t;
+
+/*!
+ * @brief CMP Voltage Reference source.
+ */
+typedef enum _cmp_reference_voltage_source
+{
+    kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as resistor ladder network supply reference Vin. */
+    kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as resistor ladder network supply reference Vin. */
+} cmp_reference_voltage_source_t;
+
+/*!
+ * @brief Configuration for the comparator.
+ */
+typedef struct _cmp_config
+{
+    bool enableCmp;                       /*!< Enable the CMP module. */
+    cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */
+    bool enableHighSpeed;                 /*!< Enable High-speed comparison mode. */
+    bool enableInvertOutput;              /*!< Enable inverted comparator output. */
+    bool useUnfilteredOutput;             /*!< Set compare output(COUT) to equal COUTA(true) or COUT(false). */
+    bool enablePinOut;                    /*!< The comparator output is available on the associated pin. */
+#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
+    bool enableTriggerMode; /*!< Enable the trigger mode. */
+#endif                      /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
+} cmp_config_t;
+
+/*!
+ * @brief Configuration for the filter.
+ */
+typedef struct _cmp_filter_config
+{
+#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
+    bool enableSample;    /*!< Using external SAMPLE as sampling clock input, or using divided bus clock. */
+#endif                    /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
+    uint8_t filterCount;  /*!< Filter Sample Count. Available range is 1-7, 0 would cause the filter disabled.*/
+    uint8_t filterPeriod; /*!< Filter Sample Period. The divider to bus clock. Available range is 0-255. */
+} cmp_filter_config_t;
+
+/*!
+ * @brief Configuration for the internal DAC.
+ */
+typedef struct _cmp_dac_config
+{
+    cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */
+    uint8_t DACValue;                                      /*!< Value for DAC Output Voltage. Available range is 0-63.*/
+} cmp_dac_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the CMP.
+ *
+ * This function initializes the CMP module. The operations included are:
+ * - Enabling the clock for CMP module.
+ * - Configuring the comparator.
+ * - Enabling the CMP module.
+ * Note: For some devices, multiple CMP instance share the same clock gate. In this case, to enable the clock for
+ * any instance enables all the CMPs. Check the chip reference manual for the clock assignment of the CMP.
+ *
+ * @param base   CMP peripheral base address.
+ * @param config Pointer to configuration structure.
+ */
+void CMP_Init(CMP_Type *base, const cmp_config_t *config);
+
+/*!
+ * @brief De-initializes the CMP module.
+ *
+ * This function de-initializes the CMP module. The operations included are:
+ * - Disabling the CMP module.
+ * - Disabling the clock for CMP module.
+ *
+ * This function disables the clock for the CMP.
+ * Note: For some devices, multiple CMP instance shares the same clock gate. In this case, before disabling the
+ * clock for the CMP,  ensure that all the CMP instances are not used.
+ *
+ * @param base CMP peripheral base address.
+ */
+void CMP_Deinit(CMP_Type *base);
+
+/*!
+ * @brief Enables/disables the CMP module.
+ *
+ * @param base CMP peripheral base address.
+ * @param enable Enable the module or not.
+ */
+static inline void CMP_Enable(CMP_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CR1 |= CMP_CR1_EN_MASK;
+    }
+    else
+    {
+        base->CR1 &= ~CMP_CR1_EN_MASK;
+    }
+}
+
+/*!
+* @brief Initializes the CMP user configuration structure.
+*
+* This function initializes the user configuration structure to these default values:
+* @code
+*   config->enableCmp           = true;
+*   config->hysteresisMode      = kCMP_HysteresisLevel0;
+*   config->enableHighSpeed     = false;
+*   config->enableInvertOutput  = false;
+*   config->useUnfilteredOutput = false;
+*   config->enablePinOut        = false;
+*   config->enableTriggerMode   = false;
+* @endcode
+* @param config Pointer to the configuration structure.
+*/
+void CMP_GetDefaultConfig(cmp_config_t *config);
+
+/*!
+ * @brief  Sets the input channels for the comparator.
+ *
+ * This function sets the input channels for the comparator.
+ * Note that two input channels cannot be set as same in the application. When the user selects the same input
+ * from the analog mux to the positive and negative port, the comparator is disabled automatically.
+ *
+ * @param  base            CMP peripheral base address.
+ * @param  positiveChannel Positive side input channel number. Available range is 0-7.
+ * @param  negativeChannel Negative side input channel number. Available range is 0-7.
+ */
+void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel);
+
+/* @} */
+
+/*!
+ * @name Advanced Features
+ * @{
+ */
+
+#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
+/*!
+ * @brief Enables/disables the DMA request for rising/falling events.
+ *
+ * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
+ * the DMA
+ * request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP
+ * if the
+ * DMA is disabled.
+ *
+ * @param base CMP peripheral base address.
+ * @param enable Enable the feature or not.
+ */
+void CMP_EnableDMA(CMP_Type *base, bool enable);
+#endif /* FSL_FEATURE_CMP_HAS_DMA */
+
+#if defined(FSL_FEATURE_CMP_HAS_WINDOW_MODE) && FSL_FEATURE_CMP_HAS_WINDOW_MODE
+/*!
+ * @brief Enables/disables the window mode.
+ *
+ * @param base CMP peripheral base address.
+ * @param enable Enable the feature or not.
+ */
+static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CR1 |= CMP_CR1_WE_MASK;
+    }
+    else
+    {
+        base->CR1 &= ~CMP_CR1_WE_MASK;
+    }
+}
+#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */
+
+#if defined(FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE) && FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE
+/*!
+ * @brief Enables/disables the pass through mode.
+ *
+ * @param base CMP peripheral base address.
+ * @param enable Enable the feature or not.
+ */
+static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->MUXCR |= CMP_MUXCR_PSTM_MASK;
+    }
+    else
+    {
+        base->MUXCR &= ~CMP_MUXCR_PSTM_MASK;
+    }
+}
+#endif /* FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE */
+
+/*!
+ * @brief  Configures the filter.
+ *
+ * @param  base   CMP peripheral base address.
+ * @param  config Pointer to configuration structure.
+ */
+void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config);
+
+/*!
+ * @brief Configures the internal DAC.
+ *
+ * @param base   CMP peripheral base address.
+ * @param config Pointer to configuration structure. "NULL" is for disabling the feature.
+ */
+void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config);
+
+/*!
+ * @brief Enables the interrupts.
+ *
+ * @param base    CMP peripheral base address.
+ * @param mask    Mask value for interrupts. See "_cmp_interrupt_enable".
+ */
+void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the interrupts.
+ *
+ * @param base    CMP peripheral base address.
+ * @param mask    Mask value for interrupts. See "_cmp_interrupt_enable".
+ */
+void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name Results
+ * @{
+ */
+
+/*!
+ * @brief  Gets the status flags.
+ *
+ * @param  base     CMP peripheral base address.
+ *
+ * @return          Mask value for the asserted flags. See "_cmp_status_flags".
+ */
+uint32_t CMP_GetStatusFlags(CMP_Type *base);
+
+/*!
+ * @brief Clears the status flags.
+ *
+ * @param base     CMP peripheral base address.
+ * @param mask     Mask value for the flags. See "_cmp_status_flags".
+ */
+void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask);
+
+/* @} */
+#if defined(__cplusplus)
+}
+#endif
+/*!
+ * @}
+ */
+#endif /* _FSL_CMP_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_common.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_common.c
new file mode 100644
index 00000000000..9e21f7594d0
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_common.c
@@ -0,0 +1,101 @@
+/*
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_common.h"
+/* This is not needed for mbed */
+#if 0
+#include "fsl_debug_console.h"
+
+#ifndef NDEBUG
+#if (defined(__CC_ARM)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+    for (;;)
+    {
+        __asm("bkpt #0");
+    }
+}
+#elif(defined(__GNUC__))
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
+    for (;;)
+    {
+        __asm("bkpt #0");
+    }
+}
+#endif /* (defined(__CC_ARM)) ||  (defined (__ICCARM__)) */
+#endif /* NDEBUG */
+#endif
+void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) */
+    uint32_t n;
+    uint32_t interrupts_disabled;
+
+    interrupts_disabled = __get_PRIMASK();
+    __disable_irq();
+    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    {
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+
+    /* make sure the __VECTOR_RAM is noncachable */
+    __VECTOR_RAM[irq + 16] = irqHandler;
+
+    if (!interrupts_disabled) {
+        __enable_irq();
+    }
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_common.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_common.h
new file mode 100644
index 00000000000..a843078c6df
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_common.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+
+/*! @brief Construct the version number for drivers. */
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U   /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U   /*!< Debug console base on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U  /*!< Debug console base on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+    kStatusGroup_Generic = 0,                 /*!< Group number for generic status codes. */
+    kStatusGroup_FLASH = 1,                   /*!< Group number for FLASH status codes. */
+    kStatusGroup_LPSPI = 4,                   /*!< Group number for LPSPI status codes. */
+    kStatusGroup_FLEXIO_SPI = 5,              /*!< Group number for FLEXIO SPI status codes. */
+    kStatusGroup_DSPI = 6,                    /*!< Group number for DSPI status codes. */
+    kStatusGroup_FLEXIO_UART = 7,             /*!< Group number for FLEXIO UART status codes. */
+    kStatusGroup_FLEXIO_I2C = 8,              /*!< Group number for FLEXIO I2C status codes. */
+    kStatusGroup_LPI2C = 9,                   /*!< Group number for LPI2C status codes. */
+    kStatusGroup_UART = 10,                   /*!< Group number for UART status codes. */
+    kStatusGroup_I2C = 11,                    /*!< Group number for UART status codes. */
+    kStatusGroup_LPSCI = 12,                  /*!< Group number for LPSCI status codes. */
+    kStatusGroup_LPUART = 13,                 /*!< Group number for LPUART status codes. */
+    kStatusGroup_SPI = 14,                    /*!< Group number for SPI status code.*/
+    kStatusGroup_XRDC = 15,                   /*!< Group number for XRDC status code.*/
+    kStatusGroup_SEMA42 = 16,                 /*!< Group number for SEMA42 status code.*/
+    kStatusGroup_SDHC = 17,                   /*!< Group number for SDHC status code */
+    kStatusGroup_SDMMC = 18,                  /*!< Group number for SDMMC status code */
+    kStatusGroup_SAI = 19,                    /*!< Group number for SAI status code */
+    kStatusGroup_MCG = 20,                    /*!< Group number for MCG status codes. */
+    kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */
+    kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */
+    kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */
+    kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */
+    kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */
+    kStatusGroup_PHY = 41,                    /*!< Group number for PHY status codes. */
+    kStatusGroup_TRGMUX = 42,                 /*!< Group number for TRGMUX status codes. */
+    kStatusGroup_SMARTCARD = 43,              /*!< Group number for SMARTCARD status codes. */
+    kStatusGroup_LMEM = 44,                   /*!< Group number for LMEM status codes. */
+    kStatusGroup_QSPI = 45,                   /*!< Group number for QSPI status codes. */
+    kStatusGroup_DMA = 50,                    /*!< Group number for DMA status codes. */
+    kStatusGroup_EDMA = 51,                   /*!< Group number for EDMA status codes. */
+    kStatusGroup_DMAMGR = 52,                 /*!< Group number for DMAMGR status codes. */
+    kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */
+    kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */
+    kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
+    kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
+    kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
+};
+
+/*! @brief Generic status return codes. */
+enum _generic_status
+{
+    kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
+    kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
+    kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
+    kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
+    kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
+    kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*! @name Min/max macros */
+/* @{ */
+#if !defined(MIN)
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#endif
+/* @} */
+
+/*! @brief Computes the number of elements in an array. */
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/* @{ */
+#if !defined(UINT16_MAX)
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
+/* @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable the interrupt not routed from intmux.
+ *
+ * @param interrupt The IRQ number.
+ */
+static inline void EnableIRQ(IRQn_Type interrupt)
+{
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
+    if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+#endif
+    {
+        NVIC_EnableIRQ(interrupt);
+    }
+}
+
+/*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable the interrupt not routed from intmux.
+ *
+ * @param interrupt The IRQ number.
+ */
+static inline void DisableIRQ(IRQn_Type interrupt)
+{
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
+    if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+#endif
+    {
+        NVIC_DisableIRQ(interrupt);
+    }
+}
+
+/*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+static inline uint32_t DisableGlobalIRQ(void)
+{
+    uint32_t regPrimask = __get_PRIMASK();
+
+    __disable_irq();
+
+    return regPrimask;
+}
+
+/*!
+ * @brief Enaable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+static inline void EnableGlobalIRQ(uint32_t primask)
+{
+    __set_PRIMASK(primask);
+}
+
+/*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ */
+void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_COMMON_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_crc.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_crc.c
new file mode 100644
index 00000000000..de86e3297a7
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_crc.c
@@ -0,0 +1,280 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_crc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @internal @brief Has data register with name CRC. */
+#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG
+#define DATA CRC
+#define DATALL CRCLL
+#endif
+
+#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT
+/* @brief Default user configuration structure for CRC-16-CCITT */
+#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U
+/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */
+#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
+/*< Default initial checksum */
+#define CRC_DRIVER_DEFAULT_REFLECT_IN false
+/*< Default is no transpose */
+#define CRC_DRIVER_DEFAULT_REFLECT_OUT false
+/*< Default is transpose bytes */
+#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false
+/*< Default is without complement of CRC data register read data */
+#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16
+/*< Default is 16-bit CRC protocol */
+#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum
+/*< Default is resutl type is final checksum */
+#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */
+
+/*! @brief CRC type of transpose of read write data */
+typedef enum _crc_transpose_type
+{
+    kCrcTransposeNone = 0U,         /*! No transpose  */
+    kCrcTransposeBits = 1U,         /*! Tranpose bits in bytes  */
+    kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */
+    kCrcTransposeBytes = 3U,        /*! Transpose bytes */
+} crc_transpose_type_t;
+
+/*!
+* @brief CRC module configuration.
+*
+* This structure holds the configuration for the CRC module.
+*/
+typedef struct _crc_module_config
+{
+    uint32_t polynomial;                 /*!< CRC Polynomial, MSBit first.@n
+                                              Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */
+    uint32_t seed;                       /*!< Starting checksum value */
+    crc_transpose_type_t readTranspose;  /*!< Type of transpose when reading CRC result. */
+    crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */
+    bool complementChecksum;             /*!< True if the result shall be complement of the actual checksum. */
+    crc_bits_t crcBits;                  /*!< Selects 16- or 32- bit CRC protocol. */
+} crc_module_config_t;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Returns transpose type for CRC protocol reflect in parameter.
+ *
+ * This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter.
+ *
+ * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter.
+ */
+static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectIn(bool enable)
+{
+    return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes);
+}
+
+/*!
+ * @brief Returns transpose type for CRC protocol reflect out parameter.
+ *
+ * This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter.
+ *
+ * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter.
+ */
+static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectOut(bool enable)
+{
+    return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone);
+}
+
+/*!
+ * @brief Starts checksum computation.
+ *
+ * Configures the CRC module for the specified CRC protocol. @n
+ * Starts the checksum computation by writing the seed value
+ *
+ * @param base CRC peripheral address.
+ * @param config Pointer to protocol configuration structure.
+ */
+static void crc_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config)
+{
+    uint32_t crcControl;
+
+    /* pre-compute value for CRC control registger based on user configuraton without WAS field */
+    crcControl = 0 | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) |
+                 CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits);
+
+    /* make sure the control register is clear - WAS is deasserted, and protocol is set */
+    base->CTRL = crcControl;
+
+    /* write polynomial register */
+    base->GPOLY = config->polynomial;
+
+    /* write pre-computed control register value along with WAS to start checksum computation */
+    base->CTRL = crcControl | CRC_CTRL_WAS(true);
+
+    /* write seed (initial checksum) */
+    base->DATA = config->seed;
+
+    /* deassert WAS by writing pre-computed CRC control register value */
+    base->CTRL = crcControl;
+}
+
+/*!
+ * @brief Starts final checksum computation.
+ *
+ * Configures the CRC module for the specified CRC protocol. @n
+ * Starts final checksum computation by writing the seed value.
+ * @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum
+ *       (output reflection and xor functions are applied).
+ *
+ * @param base CRC peripheral address.
+ * @param protocolConfig Pointer to protocol configuration structure.
+ */
+static void crc_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
+{
+    crc_module_config_t moduleConfig;
+    /* convert protocol to CRC peripheral module configuration, prepare for final checksum */
+    moduleConfig.polynomial = protocolConfig->polynomial;
+    moduleConfig.seed = protocolConfig->seed;
+    moduleConfig.readTranspose = crc_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut);
+    moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
+    moduleConfig.complementChecksum = protocolConfig->complementChecksum;
+    moduleConfig.crcBits = protocolConfig->crcBits;
+
+    crc_ConfigureAndStart(base, &moduleConfig);
+}
+
+/*!
+ * @brief Starts intermediate checksum computation.
+ *
+ * Configures the CRC module for the specified CRC protocol. @n
+ * Starts intermediate checksum computation by writing the seed value.
+ * @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value).
+ *
+ * @param base CRC peripheral address.
+ * @param protocolConfig Pointer to protocol configuration structure.
+ */
+static void crc_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
+{
+    crc_module_config_t moduleConfig;
+    /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */
+    moduleConfig.polynomial = protocolConfig->polynomial;
+    moduleConfig.seed = protocolConfig->seed;
+    moduleConfig.readTranspose =
+        kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */
+    moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
+    moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */
+    moduleConfig.crcBits = protocolConfig->crcBits;
+
+    crc_ConfigureAndStart(base, &moduleConfig);
+}
+
+void CRC_Init(CRC_Type *base, const crc_config_t *config)
+{
+    /* ungate clock */
+    CLOCK_EnableClock(kCLOCK_Crc0);
+    /* configure CRC module and write the seed */
+    if (config->crcResult == kCrcFinalChecksum)
+    {
+        crc_SetProtocolConfig(base, config);
+    }
+    else
+    {
+        crc_SetRawProtocolConfig(base, config);
+    }
+}
+
+void CRC_GetDefaultConfig(crc_config_t *config)
+{
+    static const crc_config_t crc16ccit = {
+        CRC_DRIVER_DEFAULT_POLYNOMIAL,          CRC_DRIVER_DEFAULT_SEED,
+        CRC_DRIVER_DEFAULT_REFLECT_IN,          CRC_DRIVER_DEFAULT_REFLECT_OUT,
+        CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS,
+        CRC_DRIVER_DEFAULT_CRC_RESULT,
+    };
+
+    *config = crc16ccit;
+}
+
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
+{
+    const uint32_t *data32;
+
+    /* 8-bit reads and writes till source address is aligned 4 bytes */
+    while ((dataSize) && ((uint32_t)data & 3U))
+    {
+        base->ACCESS8BIT.DATALL = *data;
+        data++;
+        dataSize--;
+    }
+
+    /* use 32-bit reads and writes as long as possible */
+    data32 = (const uint32_t *)data;
+    while (dataSize >= sizeof(uint32_t))
+    {
+        base->DATA = *data32;
+        data32++;
+        dataSize -= sizeof(uint32_t);
+    }
+
+    data = (const uint8_t *)data32;
+
+    /* 8-bit reads and writes till end of data buffer */
+    while (dataSize)
+    {
+        base->ACCESS8BIT.DATALL = *data;
+        data++;
+        dataSize--;
+    }
+}
+
+uint32_t CRC_Get32bitResult(CRC_Type *base)
+{
+    return base->DATA;
+}
+
+uint16_t CRC_Get16bitResult(CRC_Type *base)
+{
+    uint32_t retval;
+    uint32_t totr; /* type of transpose read bitfield */
+
+    retval = base->DATA;
+    totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT;
+
+    /* check transpose type to get 16-bit out of 32-bit register */
+    if (totr >= 2U)
+    {
+        /* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */
+        retval &= 0xFFFF0000U;
+        retval = retval >> 16U;
+    }
+    else
+    {
+        /* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */
+        retval &= 0x0000FFFFU;
+    }
+    return (uint16_t)retval;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_crc.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_crc.h
new file mode 100644
index 00000000000..9d767315d47
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_crc.h
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_CRC_H_
+#define _FSL_CRC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup crc
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CRC driver version. Version 2.0.1.
+ *
+ * Current version: 2.0.1
+ *
+ * Change log:
+ * - Version 2.0.1
+ *   - move DATA and DATALL macro definition from header file to source file
+ */
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
+/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */
+#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1
+#endif
+
+/*! @brief CRC bit width */
+typedef enum _crc_bits
+{
+    kCrcBits16 = 0U, /*!< Generate 16-bit CRC code  */
+    kCrcBits32 = 1U  /*!< Generate 32-bit CRC code  */
+} crc_bits_t;
+
+/*! @brief CRC result type */
+typedef enum _crc_result
+{
+    kCrcFinalChecksum = 0U,       /*!< CRC data register read value is the final checksum.
+                                      Reflect out and final xor protocol features are applied. */
+    kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value).
+                                      Reflect out and final xor protocol feature are not applied.
+                                      Intermediate checksum can be used as a seed for CRC_Init()
+                                      to continue adding data to this checksum. */
+} crc_result_t;
+
+/*!
+* @brief CRC protocol configuration.
+*
+* This structure holds the configuration for the CRC protocol.
+*
+*/
+typedef struct _crc_config
+{
+    uint32_t polynomial;     /*!< CRC Polynomial, MSBit first.
+                                  Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */
+    uint32_t seed;           /*!< Starting checksum value */
+    bool reflectIn;          /*!< Reflect bits on input. */
+    bool reflectOut;         /*!< Reflect bits on output. */
+    bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */
+    crc_bits_t crcBits;      /*!< Selects 16- or 32- bit CRC protocol. */
+    crc_result_t crcResult;  /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or
+                                CRC_Get32bitResult() */
+} crc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enables and configures the CRC peripheral module.
+ *
+ * This functions enables the clock gate in the Kinetis SIM module for the CRC peripheral.
+ * It also configures the CRC module and starts checksum computation by writing the seed.
+ *
+ * @param base CRC peripheral address.
+ * @param config CRC module configuration structure
+ */
+void CRC_Init(CRC_Type *base, const crc_config_t *config);
+
+/*!
+ * @brief Disables the CRC peripheral module.
+ *
+ * This functions disables the clock gate in the Kinetis SIM module for the CRC peripheral.
+ *
+ * @param base CRC peripheral address.
+ */
+static inline void CRC_Deinit(CRC_Type *base)
+{
+    /* gate clock */
+    CLOCK_DisableClock(kCLOCK_Crc0);
+}
+
+/*!
+ * @brief Loads default values to CRC protocol configuration structure.
+ *
+ * Loads default values to CRC protocol configuration structure. The default values are:
+ * @code
+ *   config->polynomial = 0x1021;
+ *   config->seed = 0xFFFF;
+ *   config->reflectIn = false;
+ *   config->reflectOut = false;
+ *   config->complementChecksum = false;
+ *   config->crcBits = kCrcBits16;
+ *   config->crcResult = kCrcFinalChecksum;
+ * @endcode
+ *
+ * @param config CRC protocol configuration structure
+ */
+void CRC_GetDefaultConfig(crc_config_t *config);
+
+/*!
+ * @brief Writes data to the CRC module.
+ *
+ * Writes input data buffer bytes to CRC data register.
+ * The configured type of transpose is applied.
+ *
+ * @param base CRC peripheral address.
+ * @param data Input data stream, MSByte in data[0].
+ * @param dataSize Size in bytes of the input data buffer.
+ */
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
+
+/*!
+ * @brief Reads 32-bit checksum from the CRC module.
+ *
+ * Reads CRC data register (intermediate or final checksum).
+ * The configured type of transpose and complement are applied.
+ *
+ * @param base CRC peripheral address.
+ * @return intermediate or final 32-bit checksum, after configured transpose and complement operations.
+ */
+uint32_t CRC_Get32bitResult(CRC_Type *base);
+
+/*!
+ * @brief Reads 16-bit checksum from the CRC module.
+ *
+ * Reads CRC data register (intermediate or final checksum).
+ * The configured type of transpose and complement are applied.
+ *
+ * @param base CRC peripheral address.
+ * @return intermediate or final 16-bit checksum, after configured transpose and complement operations.
+ */
+uint16_t CRC_Get16bitResult(CRC_Type *base);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* _FSL_CRC_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dac.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dac.c
new file mode 100644
index 00000000000..55e55176649
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dac.c
@@ -0,0 +1,214 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dac.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for DAC module.
+ *
+ * @param base DAC peripheral base address
+ */
+static uint32_t DAC_GetInstance(DAC_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to DAC bases for each instance. */
+static DAC_Type *const s_dacBases[] = DAC_BASE_PTRS;
+/*! @brief Pointers to DAC clocks for each instance. */
+static const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS;
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+static uint32_t DAC_GetInstance(DAC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_DAC_COUNT; instance++)
+    {
+        if (s_dacBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_DAC_COUNT);
+
+    return instance;
+}
+
+void DAC_Init(DAC_Type *base, const dac_config_t *config)
+{
+    assert(NULL != config);
+
+    uint8_t tmp8;
+
+    /* Enable the clock. */
+    CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]);
+
+    /* Configure. */
+    /* DACx_C0. */
+    tmp8 = base->C0 & ~(DAC_C0_DACRFS_MASK | DAC_C0_LPEN_MASK);
+    if (kDAC_ReferenceVoltageSourceVref2 == config->referenceVoltageSource)
+    {
+        tmp8 |= DAC_C0_DACRFS_MASK;
+    }
+    if (config->enableLowPowerMode)
+    {
+        tmp8 |= DAC_C0_LPEN_MASK;
+    }
+    base->C0 = tmp8;
+
+    /* DAC_Enable(base, true); */
+    /* Tip: The DAC output can be enabled till then after user sets their own available data in application. */
+}
+
+void DAC_Deinit(DAC_Type *base)
+{
+    DAC_Enable(base, false);
+
+    /* Disable the clock. */
+    CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]);
+}
+
+void DAC_GetDefaultConfig(dac_config_t *config)
+{
+    assert(NULL != config);
+
+    config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2;
+    config->enableLowPowerMode = false;
+}
+
+void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config)
+{
+    assert(NULL != config);
+
+    uint8_t tmp8;
+
+    /* DACx_C0. */
+    tmp8 = base->C0 & ~(DAC_C0_DACTRGSEL_MASK);
+    if (kDAC_BufferTriggerBySoftwareMode == config->triggerMode)
+    {
+        tmp8 |= DAC_C0_DACTRGSEL_MASK;
+    }
+    base->C0 = tmp8;
+
+    /* DACx_C1. */
+    tmp8 = base->C1 &
+           ~(
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+               DAC_C1_DACBFWM_MASK |
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+               DAC_C1_DACBFMD_MASK);
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+    tmp8 |= DAC_C1_DACBFWM(config->watermark);
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+    tmp8 |= DAC_C1_DACBFMD(config->workMode);
+    base->C1 = tmp8;
+
+    /* DACx_C2. */
+    tmp8 = base->C2 & ~DAC_C2_DACBFUP_MASK;
+    tmp8 |= DAC_C2_DACBFUP(config->upperLimit);
+    base->C2 = tmp8;
+}
+
+void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config)
+{
+    assert(NULL != config);
+
+    config->triggerMode = kDAC_BufferTriggerBySoftwareMode;
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+    config->watermark = kDAC_BufferWatermark1Word;
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+    config->workMode = kDAC_BufferWorkAsNormalMode;
+    config->upperLimit = DAC_DATL_COUNT - 1U;
+}
+
+void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value)
+{
+    assert(index < DAC_DATL_COUNT);
+
+    base->DAT[index].DATL = (uint8_t)(0xFFU & value);         /* Low 8-bit. */
+    base->DAT[index].DATH = (uint8_t)((0xF00U & value) >> 8); /* High 4-bit. */
+}
+
+void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index)
+{
+    assert(index < DAC_DATL_COUNT);
+
+    uint8_t tmp8 = base->C2 & ~DAC_C2_DACBFRP_MASK;
+
+    tmp8 |= DAC_C2_DACBFRP(index);
+    base->C2 = tmp8;
+}
+
+void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask)
+{
+    mask &= (
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+        DAC_C0_DACBWIEN_MASK |
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+        DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK);
+    base->C0 |= ((uint8_t)mask); /* Write 1 to enable. */
+}
+
+void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask)
+{
+    mask &= (
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+        DAC_C0_DACBWIEN_MASK |
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+        DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK);
+    base->C0 &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to disable. */
+}
+
+uint32_t DAC_GetBufferStatusFlags(DAC_Type *base)
+{
+    return (uint32_t)(base->SR & (
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+                                     DAC_SR_DACBFWMF_MASK |
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+                                     DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK));
+}
+
+void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask)
+{
+    mask &= (
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+        DAC_SR_DACBFWMF_MASK |
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+        DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK);
+    base->SR &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to clear flags. */
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dac.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dac.h
new file mode 100644
index 00000000000..925ca197c5e
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dac.h
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_DAC_H_
+#define _FSL_DAC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dac
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief DAC driver version 2.0.1. */
+#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*!
+ * @brief DAC buffer flags.
+ */
+enum _dac_buffer_status_flags
+{
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+    kDAC_BufferWatermarkFlag = DAC_SR_DACBFWMF_MASK,                  /*!< DAC Buffer Watermark Flag. */
+#endif                                                                /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+    kDAC_BufferReadPointerTopPositionFlag = DAC_SR_DACBFRPTF_MASK,    /*!< DAC Buffer Read Pointer Top Position Flag. */
+    kDAC_BufferReadPointerBottomPositionFlag = DAC_SR_DACBFRPBF_MASK, /*!< DAC Buffer Read Pointer Bottom Position
+                                                                           Flag. */
+};
+
+/*!
+ * @brief DAC buffer interrupts.
+ */
+enum _dac_buffer_interrupt_enable
+{
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION
+    kDAC_BufferWatermarkInterruptEnable = DAC_C0_DACBWIEN_MASK,         /*!< DAC Buffer Watermark Interrupt Enable. */
+#endif                                                                  /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */
+    kDAC_BufferReadPointerTopInterruptEnable = DAC_C0_DACBTIEN_MASK,    /*!< DAC Buffer Read Pointer Top Flag Interrupt
+                                                                             Enable. */
+    kDAC_BufferReadPointerBottomInterruptEnable = DAC_C0_DACBBIEN_MASK, /*!< DAC Buffer Read Pointer Bottom Flag
+                                                                             Interrupt Enable */
+};
+
+/*!
+ * @brief DAC reference voltage source.
+ */
+typedef enum _dac_reference_voltage_source
+{
+    kDAC_ReferenceVoltageSourceVref1 = 0U, /*!< The DAC selects DACREF_1 as the reference voltage. */
+    kDAC_ReferenceVoltageSourceVref2 = 1U, /*!< The DAC selects DACREF_2 as the reference voltage. */
+} dac_reference_voltage_source_t;
+
+/*!
+ * @brief DAC buffer trigger mode.
+ */
+typedef enum _dac_buffer_trigger_mode
+{
+    kDAC_BufferTriggerByHardwareMode = 0U, /*!< The DAC hardware trigger is selected. */
+    kDAC_BufferTriggerBySoftwareMode = 1U, /*!< The DAC software trigger is selected. */
+} dac_buffer_trigger_mode_t;
+
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+/*!
+ * @brief DAC buffer watermark.
+ */
+typedef enum _dac_buffer_watermark
+{
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD
+    kDAC_BufferWatermark1Word = 0U, /*!< 1 word  away from the upper limit. */
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD */
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS
+    kDAC_BufferWatermark2Word = 1U, /*!< 2 words away from the upper limit. */
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS */
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS
+    kDAC_BufferWatermark3Word = 2U, /*!< 3 words away from the upper limit. */
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS */
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS
+    kDAC_BufferWatermark4Word = 3U, /*!< 4 words away from the upper limit. */
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS */
+} dac_buffer_watermark_t;
+#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+
+/*!
+ * @brief DAC buffer work mode.
+ */
+typedef enum _dac_buffer_work_mode
+{
+    kDAC_BufferWorkAsNormalMode = 0U, /*!< Normal mode. */
+#if defined(FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE
+    kDAC_BufferWorkAsSwingMode,       /*!< Swing mode. */
+#endif                                /* FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE */
+    kDAC_BufferWorkAsOneTimeScanMode, /*!< One-Time Scan mode. */
+#if defined(FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE
+    kDAC_BufferWorkAsFIFOMode, /*!< FIFO mode. */
+#endif                         /* FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE */
+} dac_buffer_work_mode_t;
+
+/*!
+ * @brief DAC module configuration.
+ */
+typedef struct _dac_config
+{
+    dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the DAC reference voltage source. */
+    bool enableLowPowerMode;                               /*!< Enable the low-power mode. */
+} dac_config_t;
+
+/*!
+ * @brief DAC buffer configuration.
+ */
+typedef struct _dac_buffer_config
+{
+    dac_buffer_trigger_mode_t triggerMode; /*!< Select the buffer's trigger mode. */
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION
+    dac_buffer_watermark_t watermark; /*!< Select the buffer's watermark. */
+#endif                                /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
+    dac_buffer_work_mode_t workMode;  /*!< Select the buffer's work mode. */
+    uint8_t upperLimit;               /*!< Set the upper limit for buffer index.
+                                           Normally, 0-15 is available for buffer with 16 item. */
+} dac_buffer_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the DAC module.
+ *
+ * This function initializes the DAC module, including:
+ *  - Enabling the clock for DAC module.
+ *  - Configuring the DAC converter with a user configuration.
+ *  - Enabling the DAC module.
+ *
+ * @param base DAC peripheral base address.
+ * @param config Pointer to the configuration structure. See "dac_config_t".
+ */
+void DAC_Init(DAC_Type *base, const dac_config_t *config);
+
+/*!
+ * @brief De-initializes the DAC module.
+ *
+ * This function de-initializes the DAC module, including:
+ *  - Disabling the DAC module.
+ *  - Disabling the clock for the DAC module.
+ *
+ * @param base DAC peripheral base address.
+ */
+void DAC_Deinit(DAC_Type *base);
+
+/*!
+ * @brief Initializes the DAC user configuration structure.
+ *
+ * This function initializes the user configuration structure to a default value. The default values are:
+ * @code
+ *   config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2;
+ *   config->enableLowPowerMode = false;
+ * @endcode
+ * @param config Pointer to the configuration structure. See "dac_config_t".
+ */
+void DAC_GetDefaultConfig(dac_config_t *config);
+
+/*!
+ * @brief Enables the DAC module.
+ *
+ * @param base DAC peripheral base address.
+ * @param enable Enables/disables the feature.
+ */
+static inline void DAC_Enable(DAC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->C0 |= DAC_C0_DACEN_MASK;
+    }
+    else
+    {
+        base->C0 &= ~DAC_C0_DACEN_MASK;
+    }
+}
+
+/* @} */
+
+/*!
+ * @name Buffer
+ * @{
+ */
+
+/*!
+ * @brief Enables the DAC buffer.
+ *
+ * @param base DAC peripheral base address.
+ * @param enable Enables/disables the feature.
+ */
+static inline void DAC_EnableBuffer(DAC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->C1 |= DAC_C1_DACBFEN_MASK;
+    }
+    else
+    {
+        base->C1 &= ~DAC_C1_DACBFEN_MASK;
+    }
+}
+
+/*!
+ * @brief Configures the CMP buffer.
+ *
+ * @param base   DAC peripheral base address.
+ * @param config Pointer to the configuration structure. See "dac_buffer_config_t".
+ */
+void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config);
+
+/*!
+ * @brief Initializes the DAC buffer configuration structure.
+ *
+ * This function initializes the DAC buffer configuration structure to a default value. The default values are:
+ * @code
+ *   config->triggerMode = kDAC_BufferTriggerBySoftwareMode;
+ *   config->watermark   = kDAC_BufferWatermark1Word;
+ *   config->workMode    = kDAC_BufferWorkAsNormalMode;
+ *   config->upperLimit  = DAC_DATL_COUNT - 1U;
+ * @endcode
+ * @param config Pointer to the configuration structure. See "dac_buffer_config_t".
+ */
+void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config);
+
+/*!
+ * @brief Enables the DMA for DAC buffer.
+ *
+ * @param base DAC peripheral base address.
+ * @param enable Enables/disables the feature.
+ */
+static inline void DAC_EnableBufferDMA(DAC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->C1 |= DAC_C1_DMAEN_MASK;
+    }
+    else
+    {
+        base->C1 &= ~DAC_C1_DMAEN_MASK;
+    }
+}
+
+/*!
+ * @brief Sets the value for  items in the buffer.
+ *
+ * @param base  DAC peripheral base address.
+ * @param index Setting index for items in the buffer. The available index should not exceed the size of the DAC buffer.
+ * @param value Setting value for items in the buffer. 12-bits are available.
+ */
+void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value);
+
+/*!
+ * @brief Triggers the buffer by software and updates the read pointer of the DAC buffer.
+ *
+ * This function triggers the function by software. The read pointer of the DAC buffer is updated with one step
+ * after this function is called. Changing the read pointer depends on the buffer's work mode.
+ *
+ * @param base DAC peripheral base address.
+ */
+static inline void DAC_DoSoftwareTriggerBuffer(DAC_Type *base)
+{
+    base->C0 |= DAC_C0_DACSWTRG_MASK;
+}
+
+/*!
+ * @brief Gets the current read pointer of the DAC buffer.
+ *
+ * This function gets the current read pointer of the DAC buffer.
+ * The current output value depends on the item indexed by the read pointer. It is updated
+ * by software trigger or hardware trigger.
+ *
+ * @param  base DAC peripheral base address.
+ *
+ * @return      Current read pointer of DAC buffer.
+ */
+static inline uint8_t DAC_GetBufferReadPointer(DAC_Type *base)
+{
+    return ((base->C2 & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT);
+}
+
+/*!
+ * @brief Sets the current read pointer of the DAC buffer.
+ *
+ * This function sets the current read pointer of the DAC buffer.
+ * The current output value depends on the item indexed by the read pointer. It is updated by
+ * software trigger or hardware trigger. After the read pointer changes, the DAC output value also changes.
+ *
+ * @param base  DAC peripheral base address.
+ * @param index Setting index value for the pointer.
+ */
+void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index);
+
+/*!
+ * @brief Enables interrupts for the DAC buffer.
+ *
+ * @param base DAC peripheral base address.
+ * @param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable".
+ */
+void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables interrupts for the DAC buffer.
+ *
+ * @param base DAC peripheral base address.
+ * @param mask Mask value for interrupts. See  "_dac_buffer_interrupt_enable".
+ */
+void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets the flags of events for the DAC buffer.
+ *
+ * @param  base DAC peripheral base address.
+ *
+ * @return      Mask value for the asserted flags. See  "_dac_buffer_status_flags".
+ */
+uint32_t DAC_GetBufferStatusFlags(DAC_Type *base);
+
+/*!
+ * @brief Clears the flags of events for the DAC buffer.
+ *
+ * @param base DAC peripheral base address.
+ * @param mask Mask value for flags. See "_dac_buffer_status_flags_t".
+ */
+void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+/*!
+ * @}
+ */
+#endif /* _FSL_DAC_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dmamux.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dmamux.c
new file mode 100644
index 00000000000..a288b9f22fc
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dmamux.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dmamux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get instance number for DMAMUX.
+ *
+ * @param base DMAMUX peripheral base address.
+ */
+static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map DMAMUX instance number to base pointer. */
+static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS;
+
+/*! @brief Array to map DMAMUX instance number to clock name. */
+static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_DMAMUX_COUNT; instance++)
+    {
+        if (s_dmamuxBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_DMAMUX_COUNT);
+
+    return instance;
+}
+
+void DMAMUX_Init(DMAMUX_Type *base)
+{
+    CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
+}
+
+void DMAMUX_Deinit(DMAMUX_Type *base)
+{
+    CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dmamux.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dmamux.h
new file mode 100644
index 00000000000..5dce5629166
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dmamux.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_DMAMUX_H_
+#define _FSL_DMAMUX_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dmamux
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief DMAMUX driver version 2.0.1. */
+#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name DMAMUX Initialize and De-initialize
+ * @{
+ */
+
+/*!
+ * @brief Initializes DMAMUX peripheral.
+ *
+ * This function ungate the DMAMUX clock.
+ *
+ * @param base DMAMUX peripheral base address.
+ *
+ */
+void DMAMUX_Init(DMAMUX_Type *base);
+
+/*!
+ * @brief Deinitializes DMAMUX peripheral.
+ *
+ * This function gate the DMAMUX clock.
+ *
+ * @param base DMAMUX peripheral base address.
+ */
+void DMAMUX_Deinit(DMAMUX_Type *base);
+
+/* @} */
+/*!
+ * @name DMAMUX Channel Operation
+ * @{
+ */
+
+/*!
+ * @brief Enable DMAMUX channel.
+ *
+ * This function enable DMAMUX channel to work.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ */
+static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK;
+}
+
+/*!
+ * @brief Disable DMAMUX channel.
+ *
+ * This function disable DMAMUX channel.
+ *
+ * @note User must disable DMAMUX channel before configuring it.
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ */
+static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK;
+}
+
+/*!
+ * @brief Configure DMAMUX channel source.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ * @param source Channel source which is used to trigger DMA transfer.
+ */
+static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
+}
+
+#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U
+/*!
+ * @brief Enable DMAMUX period trigger.
+ *
+ * This function enable DMAMUX period trigger feature.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ */
+static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK;
+}
+
+/*!
+ * @brief Disable DMAMUX period trigger.
+ *
+ * This function disable DMAMUX period trigger.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ */
+static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK;
+}
+#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/* @} */
+
+#endif /* _FSL_DMAMUX_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi.c
new file mode 100644
index 00000000000..b2f28ed51ae
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi.c
@@ -0,0 +1,1661 @@
+/*
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_dspi.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Typedef for master interrupt handler. */
+typedef void (*dspi_master_isr_t)(SPI_Type *base, dspi_master_handle_t *handle);
+
+/*! @brief Typedef for slave interrupt handler. */
+typedef void (*dspi_slave_isr_t)(SPI_Type *base, dspi_slave_handle_t *handle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for DSPI module.
+ *
+ * @param base DSPI peripheral base address.
+ */
+uint32_t DSPI_GetInstance(SPI_Type *base);
+
+/*!
+ * @brief Configures the DSPI peripheral chip select polarity.
+ *
+ * This function  takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and
+ * configures the Pcs signal to operate with the desired characteristic.
+ *
+ * @param base DSPI peripheral address.
+ * @param pcs The particular peripheral chip select (parameter value is of type dspi_which_pcs_t) for which we wish to
+ *            apply the active high or active low characteristic.
+ * @param activeLowOrHigh The setting for either "active high, inactive low (0)"  or "active low, inactive high(1)" of
+ *                        type dspi_pcs_polarity_config_t.
+ */
+static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh);
+
+/*!
+ * @brief Master fill up the TX FIFO with data.
+ * This is not a public API as it is called from other driver functions.
+ */
+static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle);
+
+/*!
+ * @brief Master finish up a transfer.
+ * It would call back if there is callback function and set the state to idle.
+ * This is not a public API as it is called from other driver functions.
+ */
+static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle);
+
+/*!
+ * @brief Slave fill up the TX FIFO with data.
+ * This is not a public API as it is called from other driver functions.
+ */
+static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle);
+
+/*!
+ * @brief Slave finish up a transfer.
+ * It would call back if there is callback function and set the state to idle.
+ * This is not a public API as it is called from other driver functions.
+ */
+static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle);
+
+/*!
+ * @brief DSPI common interrupt handler.
+ *
+ * @param base DSPI peripheral address.
+ * @param handle pointer to g_dspiHandle which stores the transfer state.
+ */
+static void DSPI_CommonIRQHandler(SPI_Type *base, void *param);
+
+/*!
+ * @brief Master prepare the transfer.
+ * Basically it set up dspi_master_handle .
+ * This is not a public API as it is called from other driver functions. fsl_dspi_edma.c also call this function.
+ */
+static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/
+static const uint32_t s_baudratePrescaler[] = {2, 3, 5, 7};
+static const uint32_t s_baudrateScaler[] = {2,   4,   6,    8,    16,   32,   64,    128,
+                                            256, 512, 1024, 2048, 4096, 8192, 16384, 32768};
+
+static const uint32_t s_delayPrescaler[] = {1, 3, 5, 7};
+static const uint32_t s_delayScaler[] = {2,   4,    8,    16,   32,   64,    128,   256,
+                                         512, 1024, 2048, 4096, 8192, 16384, 32768, 65536};
+
+/*! @brief Pointers to dspi bases for each instance. */
+static SPI_Type *const s_dspiBases[] = SPI_BASE_PTRS;
+
+/*! @brief Pointers to dspi IRQ number for each instance. */
+static IRQn_Type const s_dspiIRQ[] = SPI_IRQS;
+
+/*! @brief Pointers to dspi clocks for each instance. */
+static clock_ip_name_t const s_dspiClock[] = DSPI_CLOCKS;
+
+/*! @brief Pointers to dspi handles for each instance. */
+static void *g_dspiHandle[FSL_FEATURE_SOC_DSPI_COUNT];
+
+/*! @brief Pointer to master IRQ handler for each instance. */
+static dspi_master_isr_t s_dspiMasterIsr;
+
+/*! @brief Pointer to slave IRQ handler for each instance. */
+static dspi_slave_isr_t s_dspiSlaveIsr;
+
+/**********************************************************************************************************************
+* Code
+*********************************************************************************************************************/
+uint32_t DSPI_GetInstance(SPI_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_DSPI_COUNT; instance++)
+    {
+        if (s_dspiBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_DSPI_COUNT);
+
+    return instance;
+}
+
+void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
+{
+    uint32_t temp;
+    /* enable DSPI clock */
+    CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]);
+
+    DSPI_Enable(base, true);
+    DSPI_StopTransfer(base);
+
+    DSPI_SetMasterSlaveMode(base, kDSPI_Master);
+
+    temp = base->MCR & (~(SPI_MCR_CONT_SCKE_MASK | SPI_MCR_MTFE_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_SMPL_PT_MASK |
+                          SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK));
+
+    base->MCR = temp | SPI_MCR_CONT_SCKE(masterConfig->enableContinuousSCK) |
+                SPI_MCR_MTFE(masterConfig->enableModifiedTimingFormat) |
+                SPI_MCR_ROOE(masterConfig->enableRxFifoOverWrite) | SPI_MCR_SMPL_PT(masterConfig->samplePoint) |
+                SPI_MCR_DIS_TXF(false) | SPI_MCR_DIS_RXF(false);
+
+    DSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow);
+
+    if (0 == DSPI_MasterSetBaudRate(base, masterConfig->whichCtar, masterConfig->ctarConfig.baudRate, srcClock_Hz))
+    {
+        assert(false);
+    }
+
+    temp = base->CTAR[masterConfig->whichCtar] &
+           ~(SPI_CTAR_FMSZ_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK | SPI_CTAR_LSBFE_MASK);
+
+    base->CTAR[masterConfig->whichCtar] =
+        temp | SPI_CTAR_FMSZ(masterConfig->ctarConfig.bitsPerFrame - 1) | SPI_CTAR_CPOL(masterConfig->ctarConfig.cpol) |
+        SPI_CTAR_CPHA(masterConfig->ctarConfig.cpha) | SPI_CTAR_LSBFE(masterConfig->ctarConfig.direction);
+
+    DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_PcsToSck, srcClock_Hz,
+                             masterConfig->ctarConfig.pcsToSckDelayInNanoSec);
+    DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_LastSckToPcs, srcClock_Hz,
+                             masterConfig->ctarConfig.lastSckToPcsDelayInNanoSec);
+    DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_BetweenTransfer, srcClock_Hz,
+                             masterConfig->ctarConfig.betweenTransferDelayInNanoSec);
+
+    DSPI_StartTransfer(base);
+}
+
+void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig)
+{
+    masterConfig->whichCtar = kDSPI_Ctar0;
+    masterConfig->ctarConfig.baudRate = 500000;
+    masterConfig->ctarConfig.bitsPerFrame = 8;
+    masterConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
+    masterConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
+    masterConfig->ctarConfig.direction = kDSPI_MsbFirst;
+
+    masterConfig->ctarConfig.pcsToSckDelayInNanoSec = 1000;
+    masterConfig->ctarConfig.lastSckToPcsDelayInNanoSec = 1000;
+    masterConfig->ctarConfig.betweenTransferDelayInNanoSec = 1000;
+
+    masterConfig->whichPcs = kDSPI_Pcs0;
+    masterConfig->pcsActiveHighOrLow = kDSPI_PcsActiveLow;
+
+    masterConfig->enableContinuousSCK = false;
+    masterConfig->enableRxFifoOverWrite = false;
+    masterConfig->enableModifiedTimingFormat = false;
+    masterConfig->samplePoint = kDSPI_SckToSin0Clock;
+}
+
+void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig)
+{
+    uint32_t temp = 0;
+
+    /* enable DSPI clock */
+    CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]);
+
+    DSPI_Enable(base, true);
+    DSPI_StopTransfer(base);
+
+    DSPI_SetMasterSlaveMode(base, kDSPI_Slave);
+
+    temp = base->MCR & (~(SPI_MCR_CONT_SCKE_MASK | SPI_MCR_MTFE_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_SMPL_PT_MASK |
+                          SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK));
+
+    base->MCR = temp | SPI_MCR_CONT_SCKE(slaveConfig->enableContinuousSCK) |
+                SPI_MCR_MTFE(slaveConfig->enableModifiedTimingFormat) |
+                SPI_MCR_ROOE(slaveConfig->enableRxFifoOverWrite) | SPI_MCR_SMPL_PT(slaveConfig->samplePoint) |
+                SPI_MCR_DIS_TXF(false) | SPI_MCR_DIS_RXF(false);
+
+    DSPI_SetOnePcsPolarity(base, kDSPI_Pcs0, kDSPI_PcsActiveLow);
+
+    temp = base->CTAR[slaveConfig->whichCtar] &
+           ~(SPI_CTAR_FMSZ_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK | SPI_CTAR_LSBFE_MASK);
+
+    base->CTAR[slaveConfig->whichCtar] = temp | SPI_CTAR_SLAVE_FMSZ(slaveConfig->ctarConfig.bitsPerFrame - 1) |
+                                         SPI_CTAR_SLAVE_CPOL(slaveConfig->ctarConfig.cpol) |
+                                         SPI_CTAR_SLAVE_CPHA(slaveConfig->ctarConfig.cpha);
+
+    DSPI_StartTransfer(base);
+}
+
+void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig)
+{
+    slaveConfig->whichCtar = kDSPI_Ctar0;
+    slaveConfig->ctarConfig.bitsPerFrame = 8;
+    slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
+    slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
+
+    slaveConfig->enableContinuousSCK = false;
+    slaveConfig->enableRxFifoOverWrite = false;
+    slaveConfig->enableModifiedTimingFormat = false;
+    slaveConfig->samplePoint = kDSPI_SckToSin0Clock;
+}
+
+void DSPI_Deinit(SPI_Type *base)
+{
+    DSPI_StopTransfer(base);
+    DSPI_Enable(base, false);
+
+    /* disable DSPI clock */
+    CLOCK_DisableClock(s_dspiClock[DSPI_GetInstance(base)]);
+}
+
+static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh)
+{
+    uint32_t temp;
+
+    temp = base->MCR;
+
+    if (activeLowOrHigh == kDSPI_PcsActiveLow)
+    {
+        temp |= SPI_MCR_PCSIS(pcs);
+    }
+    else
+    {
+        temp &= ~SPI_MCR_PCSIS(pcs);
+    }
+
+    base->MCR = temp;
+}
+
+uint32_t DSPI_MasterSetBaudRate(SPI_Type *base,
+                                dspi_ctar_selection_t whichCtar,
+                                uint32_t baudRate_Bps,
+                                uint32_t srcClock_Hz)
+{
+    /* for master mode configuration, if slave mode detected, return 0*/
+    if (!DSPI_IsMaster(base))
+    {
+        return 0;
+    }
+    uint32_t temp;
+    uint32_t prescaler, bestPrescaler;
+    uint32_t scaler, bestScaler;
+    uint32_t dbr, bestDbr;
+    uint32_t realBaudrate, bestBaudrate;
+    uint32_t diff, min_diff;
+    uint32_t baudrate = baudRate_Bps;
+
+    /* find combination of prescaler and scaler resulting in baudrate closest to the requested value */
+    min_diff = 0xFFFFFFFFU;
+    bestPrescaler = 0;
+    bestScaler = 0;
+    bestDbr = 1;
+    bestBaudrate = 0; /* required to avoid compilation warning */
+
+    /* In all for loops, if min_diff = 0, the exit for loop*/
+    for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++)
+    {
+        for (scaler = 0; (scaler < 16) && min_diff; scaler++)
+        {
+            for (dbr = 1; (dbr < 3) && min_diff; dbr++)
+            {
+                realBaudrate = ((srcClock_Hz * dbr) / (s_baudratePrescaler[prescaler] * (s_baudrateScaler[scaler])));
+
+                /* calculate the baud rate difference based on the conditional statement that states that the calculated
+                * baud rate must not exceed the desired baud rate.
+                */
+                if (baudrate >= realBaudrate)
+                {
+                    diff = baudrate - realBaudrate;
+                    if (min_diff > diff)
+                    {
+                        /* a better match found */
+                        min_diff = diff;
+                        bestPrescaler = prescaler;
+                        bestScaler = scaler;
+                        bestBaudrate = realBaudrate;
+                        bestDbr = dbr;
+                    }
+                }
+            }
+        }
+    }
+
+    /* write the best dbr, prescalar, and baud rate scalar to the CTAR */
+    temp = base->CTAR[whichCtar] & ~(SPI_CTAR_DBR_MASK | SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK);
+
+    base->CTAR[whichCtar] = temp | ((bestDbr - 1) << SPI_CTAR_DBR_SHIFT) | (bestPrescaler << SPI_CTAR_PBR_SHIFT) |
+                            (bestScaler << SPI_CTAR_BR_SHIFT);
+
+    /* return the actual calculated baud rate */
+    return bestBaudrate;
+}
+
+void DSPI_MasterSetDelayScaler(
+    SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay)
+{
+    /* these settings are only relevant in master mode */
+    if (DSPI_IsMaster(base))
+    {
+        switch (whichDelay)
+        {
+            case kDSPI_PcsToSck:
+                base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PCSSCK_MASK) & (~SPI_CTAR_CSSCK_MASK)) |
+                                        SPI_CTAR_PCSSCK(prescaler) | SPI_CTAR_CSSCK(scaler);
+                break;
+            case kDSPI_LastSckToPcs:
+                base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PASC_MASK) & (~SPI_CTAR_ASC_MASK)) |
+                                        SPI_CTAR_PASC(prescaler) | SPI_CTAR_ASC(scaler);
+                break;
+            case kDSPI_BetweenTransfer:
+                base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PDT_MASK) & (~SPI_CTAR_DT_MASK)) |
+                                        SPI_CTAR_PDT(prescaler) | SPI_CTAR_DT(scaler);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
+uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base,
+                                  dspi_ctar_selection_t whichCtar,
+                                  dspi_delay_type_t whichDelay,
+                                  uint32_t srcClock_Hz,
+                                  uint32_t delayTimeInNanoSec)
+{
+    /* for master mode configuration, if slave mode detected, return 0 */
+    if (!DSPI_IsMaster(base))
+    {
+        return 0;
+    }
+
+    uint32_t prescaler, bestPrescaler;
+    uint32_t scaler, bestScaler;
+    uint32_t realDelay, bestDelay;
+    uint32_t diff, min_diff;
+    uint32_t initialDelayNanoSec;
+
+    /* find combination of prescaler and scaler resulting in the delay closest to the
+    * requested value
+    */
+    min_diff = 0xFFFFFFFFU;
+    /* Initialize prescaler and scaler to their max values to generate the max delay */
+    bestPrescaler = 0x3;
+    bestScaler = 0xF;
+    bestDelay = (((1000000000U * 4) / srcClock_Hz) * s_delayPrescaler[bestPrescaler] * s_delayScaler[bestScaler]) / 4;
+
+    /* First calculate the initial, default delay */
+    initialDelayNanoSec = 1000000000U / srcClock_Hz * 2;
+
+    /* If the initial, default delay is already greater than the desired delay, then
+    * set the delays to their initial value (0) and return the delay. In other words,
+    * there is no way to decrease the delay value further.
+    */
+    if (initialDelayNanoSec >= delayTimeInNanoSec)
+    {
+        DSPI_MasterSetDelayScaler(base, whichCtar, 0, 0, whichDelay);
+        return initialDelayNanoSec;
+    }
+
+    /* In all for loops, if min_diff = 0, the exit for loop */
+    for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++)
+    {
+        for (scaler = 0; (scaler < 16) && min_diff; scaler++)
+        {
+            realDelay = ((4000000000U / srcClock_Hz) * s_delayPrescaler[prescaler] * s_delayScaler[scaler]) / 4;
+
+            /* calculate the delay difference based on the conditional statement
+            * that states that the calculated delay must not be less then the desired delay
+            */
+            if (realDelay >= delayTimeInNanoSec)
+            {
+                diff = realDelay - delayTimeInNanoSec;
+                if (min_diff > diff)
+                {
+                    /* a better match found */
+                    min_diff = diff;
+                    bestPrescaler = prescaler;
+                    bestScaler = scaler;
+                    bestDelay = realDelay;
+                }
+            }
+        }
+    }
+
+    /* write the best dbr, prescalar, and baud rate scalar to the CTAR */
+    DSPI_MasterSetDelayScaler(base, whichCtar, bestPrescaler, bestScaler, whichDelay);
+
+    /* return the actual calculated baud rate */
+    return bestDelay;
+}
+
+void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command)
+{
+    command->isPcsContinuous = false;
+    command->whichCtar = kDSPI_Ctar0;
+    command->whichPcs = kDSPI_Pcs0;
+    command->isEndOfQueue = false;
+    command->clearTransferCount = false;
+}
+
+void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data)
+{
+    /* First, clear Transmit Complete Flag (TCF) */
+    DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag);
+
+    while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag))
+    {
+        DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+    }
+
+    base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) |
+                  SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) |
+                  SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data);
+    DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+
+    /* Wait till TCF sets */
+    while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag))
+    {
+    }
+}
+
+void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data)
+{
+    /* First, clear Transmit Complete Flag (TCF) */
+    DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag);
+
+    while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag))
+    {
+        DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+    }
+
+    base->PUSHR = data;
+
+    DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+
+    /* Wait till TCF sets */
+    while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag))
+    {
+    }
+}
+
+void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data)
+{
+    /* First, clear Transmit Complete Flag (TCF) */
+    DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag);
+
+    while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag))
+    {
+        DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+    }
+
+    base->PUSHR_SLAVE = data;
+
+    DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+
+    /* Wait till TCF sets */
+    while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag))
+    {
+    }
+}
+
+void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask)
+{
+    if (mask & SPI_RSER_TFFF_RE_MASK)
+    {
+        base->RSER &= ~SPI_RSER_TFFF_DIRS_MASK;
+    }
+    if (mask & SPI_RSER_RFDF_RE_MASK)
+    {
+        base->RSER &= ~SPI_RSER_RFDF_DIRS_MASK;
+    }
+    base->RSER |= mask;
+}
+
+/*Transactional APIs -- Master*/
+
+void DSPI_MasterTransferCreateHandle(SPI_Type *base,
+                                     dspi_master_handle_t *handle,
+                                     dspi_master_transfer_callback_t callback,
+                                     void *userData)
+{
+    assert(handle);
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    g_dspiHandle[DSPI_GetInstance(base)] = handle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+}
+
+status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer)
+{
+    assert(transfer);
+
+    uint16_t wordToSend = 0;
+    uint16_t wordReceived = 0;
+    uint8_t dummyData = DSPI_DUMMY_DATA;
+    uint8_t bitsPerFrame;
+
+    uint32_t command;
+    uint32_t lastCommand;
+
+    uint8_t *txData;
+    uint8_t *rxData;
+    uint32_t remainingSendByteCount;
+    uint32_t remainingReceiveByteCount;
+
+    uint32_t fifoSize;
+    dspi_command_data_config_t commandStruct;
+
+    /* If the transfer count is zero, then return immediately.*/
+    if (transfer->dataSize == 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    DSPI_StopTransfer(base);
+    DSPI_DisableInterrupts(base, kDSPI_AllInterruptEnable);
+    DSPI_FlushFifo(base, true, true);
+    DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag);
+
+    /*Calculate the command and lastCommand*/
+    commandStruct.whichPcs =
+        (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT));
+    commandStruct.isEndOfQueue = false;
+    commandStruct.clearTransferCount = false;
+    commandStruct.whichCtar =
+        (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT);
+    commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous);
+
+    command = DSPI_MasterGetFormattedCommand(&(commandStruct));
+
+    commandStruct.isEndOfQueue = true;
+    commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer);
+    lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct));
+
+    /*Calculate the bitsPerFrame*/
+    bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1;
+
+    txData = transfer->txData;
+    rxData = transfer->rxData;
+    remainingSendByteCount = transfer->dataSize;
+    remainingReceiveByteCount = transfer->dataSize;
+
+    if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK))
+    {
+        fifoSize = 1;
+    }
+    else
+    {
+        fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base);
+    }
+
+    DSPI_StartTransfer(base);
+
+    if (bitsPerFrame <= 8)
+    {
+        while (remainingSendByteCount > 0)
+        {
+            if (remainingSendByteCount == 1)
+            {
+                while ((remainingReceiveByteCount - remainingSendByteCount) >= fifoSize)
+                {
+                    if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
+                    {
+                        if (rxData != NULL)
+                        {
+                            *(rxData) = DSPI_ReadData(base);
+                            rxData++;
+                        }
+                        else
+                        {
+                            DSPI_ReadData(base);
+                        }
+                        remainingReceiveByteCount--;
+
+                        DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
+                    }
+                }
+
+                while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag))
+                {
+                    DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+                }
+
+                if (txData != NULL)
+                {
+                    base->PUSHR = (*txData) | (lastCommand);
+                    txData++;
+                }
+                else
+                {
+                    base->PUSHR = (lastCommand) | (dummyData);
+                }
+                DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+                remainingSendByteCount--;
+
+                while (remainingReceiveByteCount > 0)
+                {
+                    if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
+                    {
+                        if (rxData != NULL)
+                        {
+                            /* Read data from POPR*/
+                            *(rxData) = DSPI_ReadData(base);
+                            rxData++;
+                        }
+                        else
+                        {
+                            DSPI_ReadData(base);
+                        }
+                        remainingReceiveByteCount--;
+
+                        DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
+                    }
+                }
+            }
+            else
+            {
+                /*Wait until Tx Fifo is not full*/
+                while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag))
+                {
+                    DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+                }
+                if (txData != NULL)
+                {
+                    base->PUSHR = command | (uint16_t)(*txData);
+                    txData++;
+                }
+                else
+                {
+                    base->PUSHR = command | dummyData;
+                }
+                remainingSendByteCount--;
+
+                DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+
+                if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
+                {
+                    if (rxData != NULL)
+                    {
+                        *(rxData) = DSPI_ReadData(base);
+                        rxData++;
+                    }
+                    else
+                    {
+                        DSPI_ReadData(base);
+                    }
+                    remainingReceiveByteCount--;
+
+                    DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
+                }
+            }
+        }
+    }
+    else
+    {
+        while (remainingSendByteCount > 0)
+        {
+            if (remainingSendByteCount <= 2)
+            {
+                while (((remainingReceiveByteCount - remainingSendByteCount) / 2) >= fifoSize)
+                {
+                    if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
+                    {
+                        wordReceived = DSPI_ReadData(base);
+
+                        if (rxData != NULL)
+                        {
+                            *rxData = wordReceived;
+                            ++rxData;
+                            *rxData = wordReceived >> 8;
+                            ++rxData;
+                        }
+                        remainingReceiveByteCount -= 2;
+
+                        DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
+                    }
+                }
+
+                while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag))
+                {
+                    DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+                }
+
+                if (txData != NULL)
+                {
+                    wordToSend = *(txData);
+                    ++txData;
+
+                    if (remainingSendByteCount > 1)
+                    {
+                        wordToSend |= (unsigned)(*(txData)) << 8U;
+                        ++txData;
+                    }
+                }
+                else
+                {
+                    wordToSend = dummyData;
+                }
+
+                base->PUSHR = lastCommand | wordToSend;
+
+                DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+                remainingSendByteCount = 0;
+
+                while (remainingReceiveByteCount > 0)
+                {
+                    if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
+                    {
+                        wordReceived = DSPI_ReadData(base);
+
+                        if (remainingReceiveByteCount != 1)
+                        {
+                            if (rxData != NULL)
+                            {
+                                *(rxData) = wordReceived;
+                                ++rxData;
+                                *(rxData) = wordReceived >> 8;
+                                ++rxData;
+                            }
+                            remainingReceiveByteCount -= 2;
+                        }
+                        else
+                        {
+                            if (rxData != NULL)
+                            {
+                                *(rxData) = wordReceived;
+                                ++rxData;
+                            }
+                            remainingReceiveByteCount--;
+                        }
+                        DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
+                    }
+                }
+            }
+            else
+            {
+                /*Wait until Tx Fifo is not full*/
+                while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag))
+                {
+                    DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+                }
+
+                if (txData != NULL)
+                {
+                    wordToSend = *(txData);
+                    ++txData;
+                    wordToSend |= (unsigned)(*(txData)) << 8U;
+                    ++txData;
+                }
+                else
+                {
+                    wordToSend = dummyData;
+                }
+                base->PUSHR = command | wordToSend;
+                remainingSendByteCount -= 2;
+
+                DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+
+                if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
+                {
+                    wordReceived = DSPI_ReadData(base);
+
+                    if (rxData != NULL)
+                    {
+                        *rxData = wordReceived;
+                        ++rxData;
+                        *rxData = wordReceived >> 8;
+                        ++rxData;
+                    }
+                    remainingReceiveByteCount -= 2;
+
+                    DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
+                }
+            }
+        }
+    }
+
+    return kStatus_Success;
+}
+
+static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer)
+{
+    dspi_command_data_config_t commandStruct;
+
+    DSPI_StopTransfer(base);
+    DSPI_FlushFifo(base, true, true);
+    DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag);
+
+    commandStruct.whichPcs =
+        (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT));
+    commandStruct.isEndOfQueue = false;
+    commandStruct.clearTransferCount = false;
+    commandStruct.whichCtar =
+        (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT);
+    commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous);
+    handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct));
+
+    commandStruct.isEndOfQueue = true;
+    commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer);
+    handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct));
+
+    handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1;
+
+    if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK))
+    {
+        handle->fifoSize = 1;
+    }
+    else
+    {
+        handle->fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base);
+    }
+    handle->txData = transfer->txData;
+    handle->rxData = transfer->rxData;
+    handle->remainingSendByteCount = transfer->dataSize;
+    handle->remainingReceiveByteCount = transfer->dataSize;
+    handle->totalByteCount = transfer->dataSize;
+}
+
+status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer)
+{
+    assert(handle && transfer);
+
+    /* If the transfer count is zero, then return immediately.*/
+    if (transfer->dataSize == 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check that we're not busy.*/
+    if (handle->state == kDSPI_Busy)
+    {
+        return kStatus_DSPI_Busy;
+    }
+
+    handle->state = kDSPI_Busy;
+
+    DSPI_MasterTransferPrepare(base, handle, transfer);
+    DSPI_StartTransfer(base);
+
+    /* Enable the NVIC for DSPI peripheral. */
+    EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]);
+
+    DSPI_MasterTransferFillUpTxFifo(base, handle);
+
+    /* RX FIFO Drain request: RFDF_RE to enable RFDF interrupt
+    * Since SPI is a synchronous interface, we only need to enable the RX interrupt.
+    * The IRQ handler will get the status of RX and TX interrupt flags.
+    */
+    s_dspiMasterIsr = DSPI_MasterTransferHandleIRQ;
+
+    DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable);
+
+    return kStatus_Success;
+}
+
+status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state != kDSPI_Busy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->totalByteCount - handle->remainingReceiveByteCount;
+    return kStatus_Success;
+}
+
+static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle)
+{
+    /* Disable interrupt requests*/
+    DSPI_DisableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable);
+
+    status_t status = 0;
+    if (handle->state == kDSPI_Error)
+    {
+        status = kStatus_DSPI_Error;
+    }
+    else
+    {
+        status = kStatus_Success;
+    }
+
+    if (handle->callback)
+    {
+        handle->callback(base, handle, status, handle->userData);
+    }
+
+    /* The transfer is complete.*/
+    handle->state = kDSPI_Idle;
+}
+
+static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle)
+{
+    uint16_t wordToSend = 0;
+    uint8_t dummyData = DSPI_DUMMY_DATA;
+
+    /* If bits/frame is greater than one byte */
+    if (handle->bitsPerFrame > 8)
+    {
+        /* Fill the fifo until it is full or until the send word count is 0 or until the difference
+        * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth.
+        * The reason for checking the difference is to ensure we only send as much as the
+        * RX FIFO can receive.
+        * For this case where bitsPerFrame > 8, each entry in the FIFO contains 2 bytes of the
+        * send data, hence the difference between the remainingReceiveByteCount and
+        * remainingSendByteCount must be divided by 2 to convert this difference into a
+        * 16-bit (2 byte) value.
+        */
+        while ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) &&
+               ((handle->remainingReceiveByteCount - handle->remainingSendByteCount) / 2 < handle->fifoSize))
+        {
+            if (handle->remainingSendByteCount <= 2)
+            {
+                if (handle->txData)
+                {
+                    if (handle->remainingSendByteCount == 1)
+                    {
+                        wordToSend = *(handle->txData);
+                    }
+                    else
+                    {
+                        wordToSend = *(handle->txData);
+                        ++handle->txData; /* increment to next data byte */
+                        wordToSend |= (unsigned)(*(handle->txData)) << 8U;
+                    }
+                }
+                else
+                {
+                    wordToSend = dummyData;
+                }
+                handle->remainingSendByteCount = 0;
+                base->PUSHR = handle->lastCommand | wordToSend;
+            }
+            /* For all words except the last word */
+            else
+            {
+                if (handle->txData)
+                {
+                    wordToSend = *(handle->txData);
+                    ++handle->txData; /* increment to next data byte */
+                    wordToSend |= (unsigned)(*(handle->txData)) << 8U;
+                    ++handle->txData; /* increment to next data byte */
+                }
+                else
+                {
+                    wordToSend = dummyData;
+                }
+                handle->remainingSendByteCount -= 2; /* decrement remainingSendByteCount by 2 */
+                base->PUSHR = handle->command | wordToSend;
+            }
+
+            /* Try to clear the TFFF; if the TX FIFO is full this will clear */
+            DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+
+            /* exit loop if send count is zero, else update local variables for next loop */
+            if (handle->remainingSendByteCount == 0)
+            {
+                break;
+            }
+        } /* End of TX FIFO fill while loop */
+    }
+    /* Optimized for bits/frame less than or equal to one byte. */
+    else
+    {
+        /* Fill the fifo until it is full or until the send word count is 0 or until the difference
+        * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth.
+        * The reason for checking the difference is to ensure we only send as much as the
+        * RX FIFO can receive.
+        */
+        while ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) &&
+               ((handle->remainingReceiveByteCount - handle->remainingSendByteCount) < handle->fifoSize))
+        {
+            if (handle->txData)
+            {
+                wordToSend = *(handle->txData);
+                ++handle->txData;
+            }
+            else
+            {
+                wordToSend = dummyData;
+            }
+
+            if (handle->remainingSendByteCount == 1)
+            {
+                base->PUSHR = handle->lastCommand | wordToSend;
+            }
+            else
+            {
+                base->PUSHR = handle->command | wordToSend;
+            }
+
+            /* Try to clear the TFFF; if the TX FIFO is full this will clear */
+            DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+
+            --handle->remainingSendByteCount;
+
+            /* exit loop if send count is zero, else update local variables for next loop */
+            if (handle->remainingSendByteCount == 0)
+            {
+                break;
+            }
+        }
+    }
+}
+
+void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle)
+{
+    DSPI_StopTransfer(base);
+
+    /* Disable interrupt requests*/
+    DSPI_DisableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable);
+
+    handle->state = kDSPI_Idle;
+}
+
+void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle)
+{
+    /* RECEIVE IRQ handler: Check read buffer only if there are remaining bytes to read. */
+    if (handle->remainingReceiveByteCount)
+    {
+        /* Check read buffer.*/
+        uint16_t wordReceived; /* Maximum supported data bit length in master mode is 16-bits */
+
+        /* If bits/frame is greater than one byte */
+        if (handle->bitsPerFrame > 8)
+        {
+            while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
+            {
+                wordReceived = DSPI_ReadData(base);
+                /* clear the rx fifo drain request, needed for non-DMA applications as this flag
+                * will remain set even if the rx fifo is empty. By manually clearing this flag, it
+                * either remain clear if no more data is in the fifo, or it will set if there is
+                * more data in the fifo.
+                */
+                DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
+
+                /* Store read bytes into rx buffer only if a buffer pointer was provided */
+                if (handle->rxData)
+                {
+                    /* For the last word received, if there is an extra byte due to the odd transfer
+                    * byte count, only save the the last byte and discard the upper byte
+                    */
+                    if (handle->remainingReceiveByteCount == 1)
+                    {
+                        *handle->rxData = wordReceived; /* Write first data byte */
+                        --handle->remainingReceiveByteCount;
+                    }
+                    else
+                    {
+                        *handle->rxData = wordReceived;      /* Write first data byte */
+                        ++handle->rxData;                    /* increment to next data byte */
+                        *handle->rxData = wordReceived >> 8; /* Write second data byte */
+                        ++handle->rxData;                    /* increment to next data byte */
+                        handle->remainingReceiveByteCount -= 2;
+                    }
+                }
+                else
+                {
+                    if (handle->remainingReceiveByteCount == 1)
+                    {
+                        --handle->remainingReceiveByteCount;
+                    }
+                    else
+                    {
+                        handle->remainingReceiveByteCount -= 2;
+                    }
+                }
+                if (handle->remainingReceiveByteCount == 0)
+                {
+                    break;
+                }
+            } /* End of RX FIFO drain while loop */
+        }
+        /* Optimized for bits/frame less than or equal to one byte. */
+        else
+        {
+            while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
+            {
+                wordReceived = DSPI_ReadData(base);
+                /* clear the rx fifo drain request, needed for non-DMA applications as this flag
+                * will remain set even if the rx fifo is empty. By manually clearing this flag, it
+                * either remain clear if no more data is in the fifo, or it will set if there is
+                * more data in the fifo.
+                */
+                DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
+
+                /* Store read bytes into rx buffer only if a buffer pointer was provided */
+                if (handle->rxData)
+                {
+                    *handle->rxData = wordReceived;
+                    ++handle->rxData;
+                }
+
+                --handle->remainingReceiveByteCount;
+
+                if (handle->remainingReceiveByteCount == 0)
+                {
+                    break;
+                }
+            } /* End of RX FIFO drain while loop */
+        }
+    }
+
+    /* Check write buffer. We always have to send a word in order to keep the transfer
+    * moving. So if the caller didn't provide a send buffer, we just send a zero.
+    */
+    if (handle->remainingSendByteCount)
+    {
+        DSPI_MasterTransferFillUpTxFifo(base, handle);
+    }
+
+    /* Check if we're done with this transfer.*/
+    if ((handle->remainingSendByteCount == 0) && (handle->remainingReceiveByteCount == 0))
+    {
+        /* Complete the transfer and disable the interrupts */
+        DSPI_MasterTransferComplete(base, handle);
+    }
+}
+
+/*Transactional APIs -- Slave*/
+void DSPI_SlaveTransferCreateHandle(SPI_Type *base,
+                                    dspi_slave_handle_t *handle,
+                                    dspi_slave_transfer_callback_t callback,
+                                    void *userData)
+{
+    assert(handle);
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    g_dspiHandle[DSPI_GetInstance(base)] = handle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+}
+
+status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer)
+{
+    assert(handle && transfer);
+
+    /* If receive length is zero */
+    if (transfer->dataSize == 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If both send buffer and receive buffer is null */
+    if ((!(transfer->txData)) && (!(transfer->rxData)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check that we're not busy.*/
+    if (handle->state == kDSPI_Busy)
+    {
+        return kStatus_DSPI_Busy;
+    }
+    handle->state = kDSPI_Busy;
+
+    /* Enable the NVIC for DSPI peripheral. */
+    EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]);
+
+    /* Store transfer information */
+    handle->txData = transfer->txData;
+    handle->rxData = transfer->rxData;
+    handle->remainingSendByteCount = transfer->dataSize;
+    handle->remainingReceiveByteCount = transfer->dataSize;
+    handle->totalByteCount = transfer->dataSize;
+
+    handle->errorCount = 0;
+
+    uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT;
+    handle->bitsPerFrame =
+        (((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1;
+
+    DSPI_StopTransfer(base);
+
+    DSPI_FlushFifo(base, true, true);
+    DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag);
+
+    DSPI_StartTransfer(base);
+
+    /* Prepare data to transmit */
+    DSPI_SlaveTransferFillUpTxFifo(base, handle);
+
+    s_dspiSlaveIsr = DSPI_SlaveTransferHandleIRQ;
+
+    /* Enable RX FIFO drain request, the slave only use this interrupt */
+    DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable);
+
+    if (handle->rxData)
+    {
+        /* RX FIFO overflow request enable */
+        DSPI_EnableInterrupts(base, kDSPI_RxFifoOverflowInterruptEnable);
+    }
+    if (handle->txData)
+    {
+        /* TX FIFO underflow request enable */
+        DSPI_EnableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable);
+    }
+
+    return kStatus_Success;
+}
+
+status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state != kDSPI_Busy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->totalByteCount - handle->remainingReceiveByteCount;
+    return kStatus_Success;
+}
+
+static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle)
+{
+    uint16_t transmitData = 0;
+    uint8_t dummyPattern = DSPI_DUMMY_DATA;
+
+    /* Service the transmitter, if transmit buffer provided, transmit the data,
+    * else transmit dummy pattern
+    */
+    while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)
+    {
+        /* Transmit data */
+        if (handle->remainingSendByteCount > 0)
+        {
+            /* Have data to transmit, update the transmit data and push to FIFO */
+            if (handle->bitsPerFrame <= 8)
+            {
+                /* bits/frame is 1 byte */
+                if (handle->txData)
+                {
+                    /* Update transmit data and transmit pointer */
+                    transmitData = *handle->txData;
+                    handle->txData++;
+                }
+                else
+                {
+                    transmitData = dummyPattern;
+                }
+
+                /* Decrease remaining dataSize */
+                --handle->remainingSendByteCount;
+            }
+            /* bits/frame is 2 bytes */
+            else
+            {
+                /* With multibytes per frame transmission, the transmit frame contains data from
+                * transmit buffer until sent dataSize matches user request. Other bytes will set to
+                * dummy pattern value.
+                */
+                if (handle->txData)
+                {
+                    /* Update first byte of transmit data and transmit pointer */
+                    transmitData = *handle->txData;
+                    handle->txData++;
+
+                    if (handle->remainingSendByteCount == 1)
+                    {
+                        /* Decrease remaining dataSize */
+                        --handle->remainingSendByteCount;
+                        /* Update second byte of transmit data to second byte of dummy pattern */
+                        transmitData = transmitData | (uint16_t)(((uint16_t)dummyPattern) << 8);
+                    }
+                    else
+                    {
+                        /* Update second byte of transmit data and transmit pointer */
+                        transmitData = transmitData | (uint16_t)((uint16_t)(*handle->txData) << 8);
+                        handle->txData++;
+                        handle->remainingSendByteCount -= 2;
+                    }
+                }
+                else
+                {
+                    if (handle->remainingSendByteCount == 1)
+                    {
+                        --handle->remainingSendByteCount;
+                    }
+                    else
+                    {
+                        handle->remainingSendByteCount -= 2;
+                    }
+                    transmitData = (uint16_t)((uint16_t)(dummyPattern) << 8) | dummyPattern;
+                }
+            }
+        }
+        else
+        {
+            break;
+        }
+
+        /* Write the data to the DSPI data register */
+        base->PUSHR_SLAVE = transmitData;
+
+        /* Try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */
+        DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+    }
+}
+
+static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle)
+{
+    /* Disable interrupt requests */
+    DSPI_DisableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable |
+                                     kDSPI_RxFifoOverflowInterruptEnable | kDSPI_RxFifoDrainRequestInterruptEnable);
+
+    /* The transfer is complete. */
+    handle->txData = NULL;
+    handle->rxData = NULL;
+    handle->remainingReceiveByteCount = 0;
+    handle->remainingSendByteCount = 0;
+
+    status_t status = 0;
+    if (handle->state == kDSPI_Error)
+    {
+        status = kStatus_DSPI_Error;
+    }
+    else
+    {
+        status = kStatus_Success;
+    }
+
+    if (handle->callback)
+    {
+        handle->callback(base, handle, status, handle->userData);
+    }
+
+    handle->state = kDSPI_Idle;
+}
+
+void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle)
+{
+    DSPI_StopTransfer(base);
+
+    /* Disable interrupt requests */
+    DSPI_DisableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable |
+                                     kDSPI_RxFifoOverflowInterruptEnable | kDSPI_RxFifoDrainRequestInterruptEnable);
+
+    handle->state = kDSPI_Idle;
+    handle->remainingSendByteCount = 0;
+    handle->remainingReceiveByteCount = 0;
+}
+
+void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle)
+{
+    uint8_t dummyPattern = DSPI_DUMMY_DATA;
+    uint32_t dataReceived;
+    uint32_t dataSend = 0;
+
+    /* Because SPI protocol is synchronous, the number of bytes that that slave received from the
+    * master is the actual number of bytes that the slave transmitted to the master. So we only
+    * monitor the received dataSize to know when the transfer is complete.
+    */
+    if (handle->remainingReceiveByteCount > 0)
+    {
+        while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
+        {
+            /* Have received data in the buffer. */
+            dataReceived = base->POPR;
+            /*Clear the rx fifo drain request, needed for non-DMA applications as this flag
+            * will remain set even if the rx fifo is empty. By manually clearing this flag, it
+            * either remain clear if no more data is in the fifo, or it will set if there is
+            * more data in the fifo.
+            */
+            DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
+
+            /* If bits/frame is one byte */
+            if (handle->bitsPerFrame <= 8)
+            {
+                if (handle->rxData)
+                {
+                    /* Receive buffer is not null, store data into it */
+                    *handle->rxData = dataReceived;
+                    ++handle->rxData;
+                }
+                /* Descrease remaining receive byte count */
+                --handle->remainingReceiveByteCount;
+
+                if (handle->remainingSendByteCount > 0)
+                {
+                    if (handle->txData)
+                    {
+                        dataSend = *handle->txData;
+                        ++handle->txData;
+                    }
+                    else
+                    {
+                        dataSend = dummyPattern;
+                    }
+
+                    --handle->remainingSendByteCount;
+                    /* Write the data to the DSPI data register */
+                    base->PUSHR_SLAVE = dataSend;
+                }
+            }
+            else /* If bits/frame is 2 bytes */
+            {
+                /* With multibytes frame receiving, we only receive till the received dataSize
+                * matches user request. Other bytes will be ignored.
+                */
+                if (handle->rxData)
+                {
+                    /* Receive buffer is not null, store first byte into it */
+                    *handle->rxData = dataReceived;
+                    ++handle->rxData;
+
+                    if (handle->remainingReceiveByteCount == 1)
+                    {
+                        /* Decrease remaining receive byte count */
+                        --handle->remainingReceiveByteCount;
+                    }
+                    else
+                    {
+                        /* Receive buffer is not null, store second byte into it */
+                        *handle->rxData = dataReceived >> 8;
+                        ++handle->rxData;
+                        handle->remainingReceiveByteCount -= 2;
+                    }
+                }
+                /* If no handle->rxData*/
+                else
+                {
+                    if (handle->remainingReceiveByteCount == 1)
+                    {
+                        /* Decrease remaining receive byte count */
+                        --handle->remainingReceiveByteCount;
+                    }
+                    else
+                    {
+                        handle->remainingReceiveByteCount -= 2;
+                    }
+                }
+
+                if (handle->remainingSendByteCount > 0)
+                {
+                    if (handle->txData)
+                    {
+                        dataSend = *handle->txData;
+                        ++handle->txData;
+
+                        if (handle->remainingSendByteCount == 1)
+                        {
+                            --handle->remainingSendByteCount;
+                            dataSend |= (uint16_t)((uint16_t)(dummyPattern) << 8);
+                        }
+                        else
+                        {
+                            dataSend |= (uint32_t)(*handle->txData) << 8;
+                            ++handle->txData;
+                            handle->remainingSendByteCount -= 2;
+                        }
+                    }
+                    /* If no handle->txData*/
+                    else
+                    {
+                        if (handle->remainingSendByteCount == 1)
+                        {
+                            --handle->remainingSendByteCount;
+                        }
+                        else
+                        {
+                            handle->remainingSendByteCount -= 2;
+                        }
+                        dataSend = (uint16_t)((uint16_t)(dummyPattern) << 8) | dummyPattern;
+                    }
+                    /* Write the data to the DSPI data register */
+                    base->PUSHR_SLAVE = dataSend;
+                }
+            }
+            /* Try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */
+            DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+
+            if (handle->remainingReceiveByteCount == 0)
+            {
+                break;
+            }
+        }
+    }
+    /* Check if remaining receive byte count matches user request */
+    if ((handle->remainingReceiveByteCount == 0) || (handle->state == kDSPI_Error))
+    {
+        /* Other cases, stop the transfer. */
+        DSPI_SlaveTransferComplete(base, handle);
+        return;
+    }
+
+    /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */
+    if ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoUnderflowFlag) && (base->RSER & SPI_RSER_TFUF_RE_MASK))
+    {
+        DSPI_ClearStatusFlags(base, kDSPI_TxFifoUnderflowFlag);
+        /* Change state to error and clear flag */
+        if (handle->txData)
+        {
+            handle->state = kDSPI_Error;
+        }
+        handle->errorCount++;
+    }
+    /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */
+    if ((DSPI_GetStatusFlags(base) & kDSPI_RxFifoOverflowFlag) && (base->RSER & SPI_RSER_RFOF_RE_MASK))
+    {
+        DSPI_ClearStatusFlags(base, kDSPI_RxFifoOverflowFlag);
+        /* Change state to error and clear flag */
+        if (handle->txData)
+        {
+            handle->state = kDSPI_Error;
+        }
+        handle->errorCount++;
+    }
+}
+
+static void DSPI_CommonIRQHandler(SPI_Type *base, void *param)
+{
+    if (DSPI_IsMaster(base))
+    {
+        s_dspiMasterIsr(base, (dspi_master_handle_t *)param);
+    }
+    else
+    {
+        s_dspiSlaveIsr(base, (dspi_slave_handle_t *)param);
+    }
+}
+
+#if (FSL_FEATURE_SOC_DSPI_COUNT > 0)
+void SPI0_DriverIRQHandler(void)
+{
+    assert(g_dspiHandle[0]);
+    DSPI_CommonIRQHandler(SPI0, g_dspiHandle[0]);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_DSPI_COUNT > 1)
+void SPI1_DriverIRQHandler(void)
+{
+    assert(g_dspiHandle[1]);
+    DSPI_CommonIRQHandler(SPI1, g_dspiHandle[1]);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_DSPI_COUNT > 2)
+void SPI2_DriverIRQHandler(void)
+{
+    assert(g_dspiHandle[2]);
+    DSPI_CommonIRQHandler(SPI2, g_dspiHandle[2]);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_DSPI_COUNT > 3)
+void SPI3_DriverIRQHandler(void)
+{
+    assert(g_dspiHandle[3]);
+    DSPI_CommonIRQHandler(SPI3, g_dspiHandle[3]);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_DSPI_COUNT > 4)
+void SPI4_DriverIRQHandler(void)
+{
+    assert(g_dspiHandle[4]);
+    DSPI_CommonIRQHandler(SPI4, g_dspiHandle[4]);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_DSPI_COUNT > 5)
+void SPI5_DriverIRQHandler(void)
+{
+    assert(g_dspiHandle[5]);
+    DSPI_CommonIRQHandler(SPI5, g_dspiHandle[5]);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_DSPI_COUNT > 6)
+#error "Should write the SPIx_DriverIRQHandler function that instance greater than 5 !"
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi.h
new file mode 100644
index 00000000000..dfbeb3e4571
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi.h
@@ -0,0 +1,1181 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_DSPI_H_
+#define _FSL_DSPI_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dspi_driver
+ * @{
+ */
+
+
+/**********************************************************************************************************************
+ * Definitions
+ *********************************************************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief DSPI driver version 2.1.1. */
+#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*@}*/
+
+/*! @brief DSPI dummy data if no Tx data.*/
+#define DSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */
+
+/*! @brief Status for the DSPI driver.*/
+enum _dspi_status
+{
+    kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0),      /*!< DSPI transfer is busy.*/
+    kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1),     /*!< DSPI driver error. */
+    kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2),      /*!< DSPI is idle.*/
+    kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out Of range. */
+};
+
+/*! @brief DSPI status flags in SPIx_SR register.*/
+enum _dspi_flags
+{
+    kDSPI_TxCompleteFlag = SPI_SR_TCF_MASK,          /*!< Transfer Complete Flag. */
+    kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK,         /*!< End of Queue Flag.*/
+    kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK,    /*!< Transmit FIFO Underflow Flag.*/
+    kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK,  /*!< Transmit FIFO Fill Flag.*/
+    kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK,     /*!< Receive FIFO Overflow Flag.*/
+    kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /*!< Receive FIFO Drain Flag.*/
+    kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK,     /*!< The module is in Stopped/Running state.*/
+    kDSPI_AllStatusFlag = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK |
+                          SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK /*!< All status above.*/
+};
+
+/*! @brief DSPI interrupt source.*/
+enum _dspi_interrupt_enable
+{
+    kDSPI_TxCompleteInterruptEnable = SPI_RSER_TCF_RE_MASK,          /*!< TCF  interrupt enable.*/
+    kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK,         /*!< EOQF interrupt enable.*/
+    kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK,    /*!< TFUF interrupt enable.*/
+    kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK,  /*!< TFFF interrupt enable, DMA disable.*/
+    kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK,     /*!< RFOF interrupt enable.*/
+    kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, /*!< RFDF interrupt enable, DMA disable.*/
+    kDSPI_AllInterruptEnable = SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK | SPI_RSER_TFUF_RE_MASK |
+                               SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK
+    /*!< All above interrupts enable.*/
+};
+
+/*! @brief DSPI DMA source.*/
+enum _dspi_dma_enable
+{
+    kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK), /*!< TFFF flag generates DMA requests.
+                                                                                No Tx interrupt request. */
+    kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK)  /*!< RFDF flag generates DMA requests.
+                                                                                No Rx interrupt request. */
+};
+
+/*! @brief DSPI master or slave mode configuration.*/
+typedef enum _dspi_master_slave_mode
+{
+    kDSPI_Master = 1U, /*!< DSPI peripheral operates in master mode.*/
+    kDSPI_Slave = 0U   /*!< DSPI peripheral operates in slave mode.*/
+} dspi_master_slave_mode_t;
+
+/*!
+ * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer Format. This field is valid
+ * only when CPHA bit in CTAR register is 0.
+ */
+typedef enum _dspi_master_sample_point
+{
+    kDSPI_SckToSin0Clock = 0U, /*!< 0 system clocks between SCK edge and SIN sample.*/
+    kDSPI_SckToSin1Clock = 1U, /*!< 1 system clock  between SCK edge and SIN sample.*/
+    kDSPI_SckToSin2Clock = 2U  /*!< 2 system clocks between SCK edge and SIN sample.*/
+} dspi_master_sample_point_t;
+
+/*! @brief DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure).*/
+typedef enum _dspi_which_pcs_config
+{
+    kDSPI_Pcs0 = 1U << 0, /*!< Pcs[0] */
+    kDSPI_Pcs1 = 1U << 1, /*!< Pcs[1] */
+    kDSPI_Pcs2 = 1U << 2, /*!< Pcs[2] */
+    kDSPI_Pcs3 = 1U << 3, /*!< Pcs[3] */
+    kDSPI_Pcs4 = 1U << 4, /*!< Pcs[4] */
+    kDSPI_Pcs5 = 1U << 5  /*!< Pcs[5] */
+} dspi_which_pcs_t;
+
+/*! @brief DSPI Peripheral Chip Select (Pcs) Polarity configuration.*/
+typedef enum _dspi_pcs_polarity_config
+{
+    kDSPI_PcsActiveHigh = 0U, /*!< Pcs Active High (idles low). */
+    kDSPI_PcsActiveLow = 1U   /*!< Pcs Active Low (idles high). */
+} dspi_pcs_polarity_config_t;
+
+/*! @brief DSPI Peripheral Chip Select (Pcs) Polarity.*/
+enum _dspi_pcs_polarity
+{
+    kDSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */
+    kDSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */
+    kDSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */
+    kDSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */
+    kDSPI_Pcs4ActiveLow = 1U << 4, /*!< Pcs4 Active Low (idles high). */
+    kDSPI_Pcs5ActiveLow = 1U << 5, /*!< Pcs5 Active Low (idles high). */
+    kDSPI_PcsAllActiveLow = 0xFFU  /*!< Pcs0 to Pcs5 Active Low (idles high). */
+};
+
+/*! @brief DSPI clock polarity configuration for a given CTAR.*/
+typedef enum _dspi_clock_polarity
+{
+    kDSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high DSPI clock (idles low).*/
+    kDSPI_ClockPolarityActiveLow = 1U   /*!< CPOL=1. Active-low DSPI clock (idles high).*/
+} dspi_clock_polarity_t;
+
+/*! @brief DSPI clock phase configuration for a given CTAR.*/
+typedef enum _dspi_clock_phase
+{
+    kDSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the
+                                         following edge.*/
+    kDSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the
+                                        following edge.*/
+} dspi_clock_phase_t;
+
+/*! @brief DSPI data shifter direction options for a given CTAR.*/
+typedef enum _dspi_shift_direction
+{
+    kDSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/
+    kDSPI_LsbFirst = 1U  /*!< Data transfers start with least significant bit.*/
+} dspi_shift_direction_t;
+
+/*! @brief DSPI delay type selection.*/
+typedef enum _dspi_delay_type
+{
+    kDSPI_PcsToSck = 1U,  /*!< Pcs-to-SCK delay. */
+    kDSPI_LastSckToPcs,   /*!< Last SCK edge to Pcs delay. */
+    kDSPI_BetweenTransfer /*!< Delay between transfers. */
+} dspi_delay_type_t;
+
+/*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection.*/
+typedef enum _dspi_ctar_selection
+{
+    kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode, note that CTAR0 and CTAR0_SLAVE are the
+                         same register address. */
+    kDSPI_Ctar1 = 1U, /*!< CTAR1 selection option for master mode only. */
+    kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only , note that some device do not support CTAR2. */
+    kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only , note that some device do not support CTAR3. */
+    kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only , note that some device do not support CTAR4. */
+    kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only , note that some device do not support CTAR5. */
+    kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only , note that some device do not support CTAR6. */
+    kDSPI_Ctar7 = 7U  /*!< CTAR7 selection option for master mode only , note that some device do not support CTAR7. */
+} dspi_ctar_selection_t;
+
+#define DSPI_MASTER_CTAR_SHIFT (0U)   /*!< DSPI master CTAR shift macro , internal used. */
+#define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro , internal used. */
+#define DSPI_MASTER_PCS_SHIFT (4U)    /*!< DSPI master PCS shift macro , internal used. */
+#define DSPI_MASTER_PCS_MASK (0xF0U)  /*!< DSPI master PCS mask macro , internal used. */
+/*! @brief Can use this enumeration for DSPI master transfer configFlags. */
+enum _dspi_transfer_config_flag_for_master
+{
+    kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */
+    kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR1 setting. */
+    kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR2 setting. */
+    kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR3 setting. */
+    kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR4 setting. */
+    kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR5 setting. */
+    kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR6 setting. */
+    kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR7 setting. */
+
+    kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS0 signal. */
+    kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS1 signal. */
+    kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS2 signal.*/
+    kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS3 signal. */
+    kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */
+    kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */
+
+    kDSPI_MasterPcsContinuous = 1U << 20,       /*!< Is PCS signal continuous. */
+    kDSPI_MasterActiveAfterTransfer = 1U << 21, /*!< Is PCS signal active after last frame transfer.*/
+};
+
+#define DSPI_SLAVE_CTAR_SHIFT (0U)   /*!< DSPI slave CTAR shift macro , internal used. */
+#define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro , internal used. */
+/*! @brief Can use this enum for DSPI slave transfer configFlags. */
+enum _dspi_transfer_config_flag_for_slave
+{
+    kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /*!< DSPI slave transfer use CTAR0 setting. */
+                                                    /*!< DSPI slave can only use PCS0. */
+};
+
+/*! @brief DSPI transfer state, which is used for DSPI transactional API state machine. */
+enum _dspi_transfer_state
+{
+    kDSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */
+    kDSPI_Busy,        /*!< Transfer queue is not finished. */
+    kDSPI_Error        /*!< Transfer error. */
+};
+
+/*! @brief DSPI master command date configuration used for SPIx_PUSHR.*/
+typedef struct _dspi_command_data_config
+{
+    bool isPcsContinuous;            /*!< Option to enable the continuous assertion of chip select between transfers.*/
+    dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
+                                          Register (CTAR) to use for CTAS.*/
+    dspi_which_pcs_t whichPcs;       /*!< The desired PCS signal to use for the data transfer.*/
+    bool isEndOfQueue;               /*!< Signals that the current transfer is the last in the queue.*/
+    bool clearTransferCount;         /*!< Clears SPI Transfer Counter (SPI_TCNT) before transmission starts.*/
+} dspi_command_data_config_t;
+
+/*! @brief DSPI master ctar configuration structure.*/
+typedef struct _dspi_master_ctar_config
+{
+    uint32_t baudRate;                /*!< Baud Rate for DSPI. */
+    uint32_t bitsPerFrame;            /*!< Bits per frame, minimum 4, maximum 16.*/
+    dspi_clock_polarity_t cpol;       /*!< Clock polarity. */
+    dspi_clock_phase_t cpha;          /*!< Clock phase. */
+    dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
+
+    uint32_t pcsToSckDelayInNanoSec;        /*!< PCS to SCK delay time with nanosecond , set to 0 sets the minimum
+                                               delay. It sets the boundary value if out of range that can be set.*/
+    uint32_t lastSckToPcsDelayInNanoSec;    /*!< Last SCK to PCS delay time with nanosecond , set to 0 sets the
+                                               minimum delay.It sets the boundary value if out of range that can be
+                                               set.*/
+    uint32_t betweenTransferDelayInNanoSec; /*!< After SCK delay time with nanosecond , set to 0 sets the minimum
+                                             delay.It sets the boundary value if out of range that can be set.*/
+} dspi_master_ctar_config_t;
+
+/*! @brief DSPI master configuration structure.*/
+typedef struct _dspi_master_config
+{
+    dspi_ctar_selection_t whichCtar;      /*!< Desired CTAR to use. */
+    dspi_master_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */
+
+    dspi_which_pcs_t whichPcs;                     /*!< Desired Peripheral Chip Select (pcs). */
+    dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low. */
+
+    bool enableContinuousSCK;   /*!< CONT_SCKE, continuous SCK enable . Note that continuous SCK is only
+                                     supported for CPHA = 1.*/
+    bool enableRxFifoOverWrite; /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming
+                                     data is ignored, the data from the transfer that generated the overflow
+                                     is either ignored. ROOE = 1, the incoming data is shifted in to the
+                                     shift to the shift register. */
+
+    bool enableModifiedTimingFormat;        /*!< Enables a modified transfer format to be used if it's true.*/
+    dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer
+                                                 Format. It's valid only when CPHA=0. */
+} dspi_master_config_t;
+
+/*! @brief DSPI slave ctar configuration structure.*/
+typedef struct _dspi_slave_ctar_config
+{
+    uint32_t bitsPerFrame;      /*!< Bits per frame, minimum 4, maximum 16.*/
+    dspi_clock_polarity_t cpol; /*!< Clock polarity. */
+    dspi_clock_phase_t cpha;    /*!< Clock phase. */
+                                /*!< Slave only supports MSB , does not support LSB.*/
+} dspi_slave_ctar_config_t;
+
+/*! @brief DSPI slave configuration structure.*/
+typedef struct _dspi_slave_config
+{
+    dspi_ctar_selection_t whichCtar;     /*!< Desired CTAR to use. */
+    dspi_slave_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */
+
+    bool enableContinuousSCK;               /*!< CONT_SCKE, continuous SCK enable. Note that continuous SCK is only
+                                                 supported for CPHA = 1.*/
+    bool enableRxFifoOverWrite;             /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming
+                                                 data is ignored, the data from the transfer that generated the overflow
+                                                 is either ignored. ROOE = 1, the incoming data is shifted in to the
+                                                 shift to the shift register. */
+    bool enableModifiedTimingFormat;        /*!< Enables a modified transfer format to be used if it's true.*/
+    dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer
+                                               Format. It's valid only when CPHA=0. */
+} dspi_slave_config_t;
+
+/*!
+* @brief Forward declaration of the _dspi_master_handle typedefs.
+*/
+typedef struct _dspi_master_handle dspi_master_handle_t;
+
+/*!
+* @brief Forward declaration of the _dspi_slave_handle typedefs.
+*/
+typedef struct _dspi_slave_handle dspi_slave_handle_t;
+
+/*!
+ * @brief Completion callback function pointer type.
+ *
+ * @param base DSPI peripheral address.
+ * @param handle Pointer to the handle for the DSPI master.
+ * @param status Success or error code describing whether the transfer completed.
+ * @param userData Arbitrary pointer-dataSized value passed from the application.
+ */
+typedef void (*dspi_master_transfer_callback_t)(SPI_Type *base,
+                                                dspi_master_handle_t *handle,
+                                                status_t status,
+                                                void *userData);
+/*!
+ * @brief Completion callback function pointer type.
+ *
+ * @param base DSPI peripheral address.
+ * @param handle Pointer to the handle for the DSPI slave.
+ * @param status Success or error code describing whether the transfer completed.
+ * @param userData Arbitrary pointer-dataSized value passed from the application.
+ */
+typedef void (*dspi_slave_transfer_callback_t)(SPI_Type *base,
+                                               dspi_slave_handle_t *handle,
+                                               status_t status,
+                                               void *userData);
+
+/*! @brief DSPI master/slave transfer structure.*/
+typedef struct _dspi_transfer
+{
+    uint8_t *txData;          /*!< Send buffer. */
+    uint8_t *rxData;          /*!< Receive buffer. */
+    volatile size_t dataSize; /*!< Transfer bytes. */
+
+    uint32_t
+        configFlags; /*!< Transfer transfer configuration flags , set from _dspi_transfer_config_flag_for_master if the
+                        transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer
+                        is used for slave.*/
+} dspi_transfer_t;
+
+/*! @brief DSPI master transfer handle structure used for transactional API. */
+struct _dspi_master_handle
+{
+    uint32_t bitsPerFrame;         /*!< Desired number of bits per frame. */
+    volatile uint32_t command;     /*!< Desired data command. */
+    volatile uint32_t lastCommand; /*!< Desired last data command. */
+
+    uint8_t fifoSize; /*!< FIFO dataSize. */
+
+    volatile bool isPcsActiveAfterTransfer; /*!< Is PCS signal keep active after the last frame transfer.*/
+    volatile bool isThereExtraByte;         /*!< Is there extra byte.*/
+
+    uint8_t *volatile txData;                  /*!< Send buffer. */
+    uint8_t *volatile rxData;                  /*!< Receive buffer. */
+    volatile size_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
+    size_t totalByteCount;                     /*!< Number of transfer bytes*/
+
+    volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/
+
+    dspi_master_transfer_callback_t callback; /*!< Completion callback. */
+    void *userData;                           /*!< Callback user data. */
+};
+
+/*! @brief DSPI slave transfer handle structure used for transactional API. */
+struct _dspi_slave_handle
+{
+    uint32_t bitsPerFrame;          /*!< Desired number of bits per frame. */
+    volatile bool isThereExtraByte; /*!< Is there extra byte.*/
+
+    uint8_t *volatile txData;                  /*!< Send buffer. */
+    uint8_t *volatile rxData;                  /*!< Receive buffer. */
+    volatile size_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
+    size_t totalByteCount;                     /*!< Number of transfer bytes*/
+
+    volatile uint8_t state; /*!< DSPI transfer state.*/
+
+    volatile uint32_t errorCount; /*!< Error count for slave transfer.*/
+
+    dspi_slave_transfer_callback_t callback; /*!< Completion callback. */
+    void *userData;                          /*!< Callback user data. */
+};
+
+/**********************************************************************************************************************
+ * API
+ *********************************************************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the DSPI master.
+ *
+ * This function initializes the DSPI master configuration. An example use case is as follows:
+ *  @code
+ *   dspi_master_config_t  masterConfig;
+ *   masterConfig.whichCtar                                = kDSPI_Ctar0;
+ *   masterConfig.ctarConfig.baudRate                      = 500000000;
+ *   masterConfig.ctarConfig.bitsPerFrame                  = 8;
+ *   masterConfig.ctarConfig.cpol                          = kDSPI_ClockPolarityActiveHigh;
+ *   masterConfig.ctarConfig.cpha                          = kDSPI_ClockPhaseFirstEdge;
+ *   masterConfig.ctarConfig.direction                     = kDSPI_MsbFirst;
+ *   masterConfig.ctarConfig.pcsToSckDelayInNanoSec        = 1000000000 / masterConfig.ctarConfig.baudRate ;
+ *   masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec    = 1000000000 / masterConfig.ctarConfig.baudRate ;
+ *   masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ;
+ *   masterConfig.whichPcs                                 = kDSPI_Pcs0;
+ *   masterConfig.pcsActiveHighOrLow                       = kDSPI_PcsActiveLow;
+ *   masterConfig.enableContinuousSCK                      = false;
+ *   masterConfig.enableRxFifoOverWrite                    = false;
+ *   masterConfig.enableModifiedTimingFormat               = false;
+ *   masterConfig.samplePoint                              = kDSPI_SckToSin0Clock;
+ *   DSPI_MasterInit(base, &masterConfig, srcClock_Hz);
+ *  @endcode
+ *
+ * @param base DSPI peripheral address.
+ * @param masterConfig Pointer to structure dspi_master_config_t.
+ * @param srcClock_Hz Module source input clock in Hertz
+ */
+void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Sets the dspi_master_config_t structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit().
+ * User may use the initialized structure unchanged in DSPI_MasterInit() or modify the structure
+ * before calling DSPI_MasterInit().
+ * Example:
+ * @code
+ *  dspi_master_config_t  masterConfig;
+ *  DSPI_MasterGetDefaultConfig(&masterConfig);
+ * @endcode
+ * @param masterConfig pointer to dspi_master_config_t structure
+ */
+void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig);
+
+/*!
+ * @brief DSPI slave configuration.
+ *
+ * This function initializes the DSPI slave configuration. An example use case is as follows:
+ *  @code
+ *   dspi_slave_config_t  slaveConfig;
+ *  slaveConfig->whichCtar                  = kDSPI_Ctar0;
+ *  slaveConfig->ctarConfig.bitsPerFrame    = 8;
+ *  slaveConfig->ctarConfig.cpol            = kDSPI_ClockPolarityActiveHigh;
+ *  slaveConfig->ctarConfig.cpha            = kDSPI_ClockPhaseFirstEdge;
+ *  slaveConfig->enableContinuousSCK        = false;
+ *  slaveConfig->enableRxFifoOverWrite      = false;
+ *  slaveConfig->enableModifiedTimingFormat = false;
+ *  slaveConfig->samplePoint                = kDSPI_SckToSin0Clock;
+ *   DSPI_SlaveInit(base, &slaveConfig);
+ *  @endcode
+ *
+ * @param base DSPI peripheral address.
+ * @param slaveConfig Pointer to structure dspi_master_config_t.
+ */
+void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig);
+
+/*!
+ * @brief Sets the dspi_slave_config_t structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit().
+ * User may use the initialized structure unchanged in DSPI_SlaveInit(), or modify the structure
+ * before calling DSPI_SlaveInit().
+ * Example:
+ * @code
+ *  dspi_slave_config_t  slaveConfig;
+ *  DSPI_SlaveGetDefaultConfig(&slaveConfig);
+ * @endcode
+ * @param slaveConfig pointer to dspi_slave_config_t structure.
+ */
+void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig);
+
+/*!
+ * @brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock.
+ * @param base DSPI peripheral address.
+ */
+void DSPI_Deinit(SPI_Type *base);
+
+/*!
+ * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0.
+ *
+ * @param base DSPI peripheral address.
+ * @param enable pass true to enable module, false to disable module.
+ */
+static inline void DSPI_Enable(SPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->MCR &= ~SPI_MCR_MDIS_MASK;
+    }
+    else
+    {
+        base->MCR |= SPI_MCR_MDIS_MASK;
+    }
+}
+
+/*!
+ *@}
+*/
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the DSPI status flag state.
+ * @param base DSPI peripheral address.
+ * @return The DSPI status(in SR register).
+ */
+static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base)
+{
+    return (base->SR);
+}
+
+/*!
+ * @brief Clears the DSPI status flag.
+ *
+ * This function  clears the desired status bit by using a write-1-to-clear. The user passes in the base and the
+ * desired status bit to clear.  The list of status bits is defined in the dspi_status_and_interrupt_request_t. The
+ * function uses these bit positions in its algorithm to clear the desired flag state.
+ * Example usage:
+ * @code
+ *  DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag|kDSPI_EndOfQueueFlag);
+ * @endcode
+ *
+ * @param base DSPI peripheral address.
+ * @param statusFlags The status flag , used from type dspi_flags.
+ */
+static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags)
+{
+    base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/
+}
+
+/*!
+ *@}
+*/
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the DSPI interrupts.
+ *
+ * This function configures the various interrupt masks of the DSPI.  The parameters are base and an interrupt mask.
+ * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request.
+ *
+ * @code
+ *  DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable );
+ * @endcode
+ *
+ * @param base DSPI peripheral address.
+ * @param mask The interrupt mask, can use the enum _dspi_interrupt_enable.
+ */
+void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the DSPI interrupts.
+ *
+ * @code
+ *  DSPI_DisableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable );
+ * @endcode
+ *
+ * @param base DSPI peripheral address.
+ * @param mask The interrupt mask, can use the enum _dspi_interrupt_enable.
+ */
+static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
+{
+    base->RSER &= ~mask;
+}
+
+/*!
+ *@}
+*/
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Enables the DSPI DMA request.
+ *
+ * This function configures the Rx and Tx DMA mask of the DSPI.  The parameters are base and a DMA mask.
+ * @code
+ *  DSPI_EnableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable);
+ * @endcode
+ *
+ * @param base DSPI peripheral address.
+ * @param mask The interrupt mask can use the enum dspi_dma_enable.
+ */
+static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask)
+{
+    base->RSER |= mask;
+}
+
+/*!
+ * @brief Disables the DSPI DMA request.
+ *
+ * This function configures the Rx and Tx DMA mask of the DSPI.  The parameters are base and a DMA mask.
+ * @code
+ *  SPI_DisableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable);
+ * @endcode
+ *
+ * @param base DSPI peripheral address.
+ * @param mask The interrupt mask can use the enum dspi_dma_enable.
+ */
+static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask)
+{
+    base->RSER &= ~mask;
+}
+
+/*!
+ * @brief Gets the DSPI master PUSHR data register address for the DMA operation.
+ *
+ * This function gets the DSPI master PUSHR data register address because this value is needed for the DMA operation.
+ *
+ * @param base DSPI peripheral address.
+ * @return The DSPI master PUSHR data register address.
+ */
+static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base)
+{
+    return (uint32_t) & (base->PUSHR);
+}
+
+/*!
+ * @brief Gets the DSPI slave PUSHR data register address for the DMA operation.
+ *
+ * This function gets the DSPI slave PUSHR data register address as this value is needed for the DMA operation.
+ *
+ * @param base DSPI peripheral address.
+ * @return The DSPI slave PUSHR data register address.
+ */
+static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base)
+{
+    return (uint32_t) & (base->PUSHR_SLAVE);
+}
+
+/*!
+ * @brief Gets the DSPI POPR data register address for the DMA operation.
+ *
+ * This function gets the DSPI POPR data register address as this value is needed for the DMA operation.
+ *
+ * @param base DSPI peripheral address.
+ * @return The DSPI POPR data register address.
+ */
+static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base)
+{
+    return (uint32_t) & (base->POPR);
+}
+
+/*!
+ *@}
+*/
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Configures the DSPI for master or slave.
+ *
+ * @param base DSPI peripheral address.
+ * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t.
+ */
+static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode)
+{
+    base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) | SPI_MCR_MSTR(mode);
+}
+
+/*!
+ * @brief Returns whether the DSPI module is in master mode.
+ *
+ * @param base DSPI peripheral address.
+ * @return Returns true if the module is in master mode or false if the module is in slave mode.
+ */
+static inline bool DSPI_IsMaster(SPI_Type *base)
+{
+    return (bool)((base->MCR) & SPI_MCR_MSTR_MASK);
+}
+/*!
+ * @brief Starts the DSPI transfers and clears HALT bit in MCR.
+ *
+ * This function sets the module to begin data transfer in either master or slave mode.
+ *
+ * @param base DSPI peripheral address.
+ */
+static inline void DSPI_StartTransfer(SPI_Type *base)
+{
+    base->MCR &= ~SPI_MCR_HALT_MASK;
+}
+/*!
+ * @brief Stops (halts) DSPI transfers and sets HALT bit in MCR.
+ *
+ * This function stops data transfers in either master or slave mode.
+ *
+ * @param base DSPI peripheral address.
+ */
+static inline void DSPI_StopTransfer(SPI_Type *base)
+{
+    base->MCR |= SPI_MCR_HALT_MASK;
+}
+
+/*!
+ * @brief Enables (or disables) the DSPI FIFOs.
+ *
+ * This function  allows the caller to disable/enable the Tx and Rx FIFOs (independently).
+ * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO configuration.  To enable,
+ * the caller must pass in a logic 1 (true).
+ *
+ * @param base DSPI peripheral address.
+ * @param enableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO
+ * @param enableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO
+ */
+static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo)
+{
+    base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK))) | SPI_MCR_DIS_TXF(!enableTxFifo) |
+                SPI_MCR_DIS_RXF(!enableRxFifo);
+}
+
+/*!
+ * @brief Flushes the DSPI FIFOs.
+ *
+ * @param base DSPI peripheral address.
+ * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO
+ * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO
+ */
+static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo)
+{
+    base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK))) | SPI_MCR_CLR_TXF(flushTxFifo) |
+                SPI_MCR_CLR_RXF(flushRxFifo);
+}
+
+/*!
+ * @brief Configures the DSPI peripheral chip select polarity simultaneously.
+ * For example, PCS0 and PCS1 set to active low and other PCS set to active high. Note that the number of
+ * PCSs is specific to the device.
+ * @code
+ *  DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow | kDSPI_Pcs1ActiveLow);
+   @endcode
+ * @param base DSPI peripheral address.
+ * @param mask The PCS polarity mask ,  can use the enum _dspi_pcs_polarity.
+ */
+static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask)
+{
+    base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) | SPI_MCR_PCSIS(mask);
+}
+
+/*!
+ * @brief Sets the DSPI baud rate in bits per second.
+ *
+ * This function  takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without
+ * exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the
+ * caller also provide the frequency of the module source clock (in Hertz).
+ *
+ * @param base DSPI peripheral address.
+ * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t
+ * @param baudRate_Bps The desired baud rate in bits per second
+ * @param srcClock_Hz Module source input clock in Hertz
+ * @return The actual calculated baud rate
+ */
+uint32_t DSPI_MasterSetBaudRate(SPI_Type *base,
+                                dspi_ctar_selection_t whichCtar,
+                                uint32_t baudRate_Bps,
+                                uint32_t srcClock_Hz);
+
+/*!
+ * @brief Manually configures the delay prescaler and scaler for a particular CTAR.
+ *
+ * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar
+ * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT)and scalar (DT).
+ *
+ * These delay names are available in type dspi_delay_type_t.
+ *
+ * The user passes the delay to configure along with the prescaler and scaler value.
+ * This allows the user to directly set the prescaler/scaler values if they have pre-calculated them or if they simply
+ * wish to manually increment either value.
+ *
+ * @param base DSPI peripheral address.
+ * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t.
+ * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3).
+ * @param scaler The scaler delay value (can be any integer between 0 to 15).
+ * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
+ */
+void DSPI_MasterSetDelayScaler(
+    SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay);
+
+/*!
+ * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds.
+ *
+ * This function calculates the values for:
+ * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
+ * After SCK delay pre-scalar (PASC) and scalar (ASC), or
+ * Delay after transfer pre-scalar (PDT)and scalar (DT).
+ *
+ * These delay names are available in type dspi_delay_type_t.
+ *
+ * The user passes which delay they want to configure along with the desired delay value in nanoseconds.  The function
+ * calculates the values needed for the prescaler and scaler and returning the actual calculated delay as an exact
+ * delay match may not be possible. In this case, the closest match is calculated without going below the desired
+ * delay value input.
+ * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum
+ * supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay
+ * input.
+ *
+ * @param base DSPI peripheral address.
+ * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t.
+ * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
+ * @param srcClock_Hz Module source input clock in Hertz
+ * @param delayTimeInNanoSec The desired delay value in nanoseconds.
+ * @return The actual calculated delay value.
+ */
+uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base,
+                                  dspi_ctar_selection_t whichCtar,
+                                  dspi_delay_type_t whichDelay,
+                                  uint32_t srcClock_Hz,
+                                  uint32_t delayTimeInNanoSec);
+
+/*!
+ * @brief Writes data into the data buffer for master mode.
+ *
+ * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
+ * provides characteristics of the data such as the optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). This is an example:
+ * @code
+ *  dspi_command_data_config_t commandConfig;
+ *  commandConfig.isPcsContinuous = true;
+ *  commandConfig.whichCtar = kDSPICtar0;
+ *  commandConfig.whichPcs = kDSPIPcs0;
+ *  commandConfig.clearTransferCount = false;
+ *  commandConfig.isEndOfQueue = false;
+ *  DSPI_MasterWriteData(base, &commandConfig, dataWord);
+   @endcode
+ *
+ * @param base DSPI peripheral address.
+ * @param command Pointer to command structure.
+ * @param data The data word to be sent.
+ */
+static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data)
+{
+    base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) |
+                  SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) |
+                  SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data);
+}
+
+/*!
+ * @brief Sets the dspi_command_data_config_t structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx().
+ * User may use the initialized structure unchanged in DSPI_MasterWrite_xx() or modify the structure
+ * before calling DSPI_MasterWrite_xx().
+ * Example:
+ * @code
+ *  dspi_command_data_config_t  command;
+ *  DSPI_GetDefaultDataCommandConfig(&command);
+ * @endcode
+ * @param command pointer to dspi_command_data_config_t structure.
+ */
+void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command);
+
+/*!
+ * @brief Writes data into the data buffer master mode and waits till complete to return.
+ *
+ * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
+ * provides characteristics of the data such as the optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). This is an example:
+ * @code
+ *  dspi_command_config_t commandConfig;
+ *  commandConfig.isPcsContinuous = true;
+ *  commandConfig.whichCtar = kDSPICtar0;
+ *  commandConfig.whichPcs = kDSPIPcs1;
+ *  commandConfig.clearTransferCount = false;
+ *  commandConfig.isEndOfQueue = false;
+ *  DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord);
+ * @endcode
+ *
+ * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
+ * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol,
+ * receive data is available when transmit completes.
+ *
+ * @param base DSPI peripheral address.
+ * @param command Pointer to command structure.
+ * @param data The data word to be sent.
+ */
+void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data);
+
+/*!
+ * @brief Returns the DSPI command word formatted to the PUSHR data register bit field.
+ *
+ * This function allows the caller to pass in the data command structure and returns the command word formatted
+ * according to the DSPI PUSHR register bit field placement. The user can then "OR" the returned command word with the
+ * desired data to send and use the function DSPI_HAL_WriteCommandDataMastermode or
+ * DSPI_HAL_WriteCommandDataMastermodeBlocking to write the entire 32-bit command data word to the PUSHR. This helps
+ * improve performance in cases where the command structure is constant. For example, the user calls this function
+ * before starting a transfer to generate the command word. When they are ready to transmit the data, they OR
+ * this formatted command word with the desired data to transmit. This process increases transmit performance when
+ * compared to calling send functions such as DSPI_HAL_WriteDataMastermode which format the command word each time a
+ * data word is to be sent.
+ *
+ * @param command Pointer to command structure.
+ * @return The command word formatted to the PUSHR data register bit field.
+ */
+static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command)
+{
+    /* Format the 16-bit command word according to the PUSHR data register bit field*/
+    return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) |
+                      SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) |
+                      SPI_PUSHR_CTCNT(command->clearTransferCount));
+}
+
+/*!
+ * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data
+ *        buffer, master mode and waits till complete to return.
+ *
+ * In this function, the user must append the 16-bit data to the 16-bit command info then provide the total 32-bit word
+ * as the data to send.
+ * The command portion provides characteristics of the data such as the optional continuous chip select operation
+* between
+ * transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS
+ * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the
+ * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for
+ * appending this command with the data to send. This is an example:
+ * @code
+ *  dataWord = <16-bit command> | <16-bit data>;
+ *  DSPI_HAL_WriteCommandDataMastermodeBlocking(base, dataWord);
+ * @endcode
+ *
+ * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
+ * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0).
+ * Because the SPI is a synchronous protocol, the receive data is available when transmit completes.
+ *
+ *  For a blocking polling transfer, see methods below.
+ *  Option 1:
+*   uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command);
+*   uint32_t data0 = command_to_send | data_need_to_send_0;
+*   uint32_t data1 = command_to_send | data_need_to_send_1;
+*   uint32_t data2 = command_to_send | data_need_to_send_2;
+*
+*   DSPI_MasterWriteCommandDataBlocking(base,data0);
+*   DSPI_MasterWriteCommandDataBlocking(base,data1);
+*   DSPI_MasterWriteCommandDataBlocking(base,data2);
+*
+*  Option 2:
+*   DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0);
+*   DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1);
+*   DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2);
+*
+ * @param base DSPI peripheral address.
+ * @param data The data word (command and data combined) to be sent
+ */
+void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data);
+
+/*!
+ * @brief Writes data into the data buffer in slave mode.
+ *
+ * In slave mode, up to 16-bit words may be written.
+ *
+ * @param base DSPI peripheral address.
+ * @param data The data to send.
+ */
+static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data)
+{
+    base->PUSHR_SLAVE = data;
+}
+
+/*!
+ * @brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns.
+ *
+ * In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data
+ * into data register, and finally waits until the data is transmitted.
+ *
+ * @param base DSPI peripheral address.
+ * @param data The data to send.
+ */
+void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data);
+
+/*!
+ * @brief Reads data from the data buffer.
+ *
+ * @param base DSPI peripheral address.
+ * @return The data from the read data buffer.
+ */
+static inline uint32_t DSPI_ReadData(SPI_Type *base)
+{
+    return (base->POPR);
+}
+
+/*!
+ *@}
+*/
+
+/*!
+ * @name Transactional
+ * @{
+ */
+/*Transactional APIs*/
+
+/*!
+ * @brief Initializes the DSPI master handle.
+ *
+ * This function initializes the DSPI handle which can be used for other DSPI transactional APIs.  Usually, for a
+ * specified DSPI instance,  call this API once to get the initialized handle.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle DSPI handle pointer to dspi_master_handle_t.
+ * @param callback dspi callback.
+ * @param userData callback function parameter.
+ */
+void DSPI_MasterTransferCreateHandle(SPI_Type *base,
+                                     dspi_master_handle_t *handle,
+                                     dspi_master_transfer_callback_t callback,
+                                     void *userData);
+
+/*!
+ * @brief DSPI master transfer data using polling.
+ *
+ * This function transfers data with polling. This is a blocking function, which does not return until all transfers
+ * have been
+ * completed.
+ *
+ * @param base DSPI peripheral base address.
+ * @param transfer pointer to dspi_transfer_t structure.
+ * @return status of status_t.
+ */
+status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer);
+
+/*!
+ * @brief DSPI master transfer data using interrupts.
+ *
+ * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all
+ data
+ * have been transferred, the callback function is called.
+
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
+ * @param transfer pointer to dspi_transfer_t structure.
+ * @return status of status_t.
+ */
+status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer);
+
+/*!
+ * @brief Gets the master transfer count.
+ *
+ * This function gets the master transfer count.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @return status of status_t.
+ */
+status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief DSPI master aborts transfer using an interrupt.
+ *
+ * This function aborts a transfer using an interrupt.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
+ */
+void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle);
+
+/*!
+ * @brief DSPI Master IRQ handler function.
+ *
+ * This function processes the DSPI transmit and receive IRQ.
+
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
+ */
+void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle);
+
+/*!
+ * @brief Initializes the DSPI slave handle.
+ *
+ * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs.  Usually, for a
+ * specified DSPI instance, call this API once to get the initialized handle.
+ *
+ * @param handle DSPI handle pointer to dspi_slave_handle_t.
+ * @param base DSPI peripheral base address.
+ * @param callback DSPI callback.
+ * @param userData callback function parameter.
+ */
+void DSPI_SlaveTransferCreateHandle(SPI_Type *base,
+                                    dspi_slave_handle_t *handle,
+                                    dspi_slave_transfer_callback_t callback,
+                                    void *userData);
+
+/*!
+ * @brief DSPI slave transfers data using an interrupt.
+ *
+ * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all
+ * data
+ * have been transferred, the callback function is called.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
+ * @param transfer pointer to dspi_transfer_t structure.
+ * @return status of status_t.
+ */
+status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer);
+
+/*!
+ * @brief Gets the slave transfer count.
+ *
+ * This function gets the slave transfer count.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @return status of status_t.
+ */
+status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count);
+
+/*!
+ * @brief DSPI slave aborts a transfer using an interrupt.
+ *
+ * This function aborts transfer using an interrupt.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
+ */
+void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle);
+
+/*!
+ * @brief DSPI Master IRQ handler function.
+ *
+ * This function processes the DSPI transmit and receive IRQ.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
+ */
+void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle);
+
+/*!
+ *@}
+*/
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+       /*!
+        *@}
+       */
+
+#endif /*_FSL_DSPI_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi_edma.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi_edma.c
new file mode 100644
index 00000000000..a1c20027b2c
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi_edma.c
@@ -0,0 +1,1263 @@
+/*
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_dspi_edma.h"
+
+/***********************************************************************************************************************
+* Definitons
+***********************************************************************************************************************/
+
+/*!
+* @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private.
+*/
+typedef struct _dspi_master_edma_private_handle
+{
+    SPI_Type *base;                    /*!< DSPI peripheral base address. */
+    dspi_master_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */
+} dspi_master_edma_private_handle_t;
+
+/*!
+* @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private.
+*/
+typedef struct _dspi_slave_edma_private_handle
+{
+    SPI_Type *base;                   /*!< DSPI peripheral base address. */
+    dspi_slave_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */
+} dspi_slave_edma_private_handle_t;
+
+/***********************************************************************************************************************
+* Prototypes
+***********************************************************************************************************************/
+/*!
+* @brief EDMA_DspiMasterCallback after the DSPI master transfer completed by using EDMA.
+* This is not a public API as it is called from other driver functions.
+*/
+static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
+                                    void *g_dspiEdmaPrivateHandle,
+                                    bool transferDone,
+                                    uint32_t tcds);
+
+/*!
+* @brief EDMA_DspiSlaveCallback after the DSPI slave transfer completed by using EDMA.
+* This is not a public API as it is called from other driver functions.
+*/
+static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle,
+                                   void *g_dspiEdmaPrivateHandle,
+                                   bool transferDone,
+                                   uint32_t tcds);
+/*!
+* @brief Get instance number for DSPI module.
+*
+* This is not a public API and it's extern from fsl_dspi.c.
+*
+* @param base DSPI peripheral base address
+*/
+extern uint32_t DSPI_GetInstance(SPI_Type *base);
+
+/***********************************************************************************************************************
+* Variables
+***********************************************************************************************************************/
+
+/*! @brief Pointers to dspi edma handles for each instance. */
+static dspi_master_edma_private_handle_t s_dspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT];
+static dspi_slave_edma_private_handle_t s_dspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT];
+
+/***********************************************************************************************************************
+* Code
+***********************************************************************************************************************/
+
+void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base,
+                                         dspi_master_edma_handle_t *handle,
+                                         dspi_master_edma_transfer_callback_t callback,
+                                         void *userData,
+                                         edma_handle_t *edmaRxRegToRxDataHandle,
+                                         edma_handle_t *edmaTxDataToIntermediaryHandle,
+                                         edma_handle_t *edmaIntermediaryToTxRegHandle)
+{
+    assert(handle);
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    uint32_t instance = DSPI_GetInstance(base);
+
+    s_dspiMasterEdmaPrivateHandle[instance].base = base;
+    s_dspiMasterEdmaPrivateHandle[instance].handle = handle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle;
+    handle->edmaTxDataToIntermediaryHandle = edmaTxDataToIntermediaryHandle;
+    handle->edmaIntermediaryToTxRegHandle = edmaIntermediaryToTxRegHandle;
+}
+
+status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer)
+{
+    assert(handle && transfer);
+
+    /* If the transfer count is zero, then return immediately.*/
+    if (transfer->dataSize == 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If both send buffer and receive buffer is null */
+    if ((!(transfer->txData)) && (!(transfer->rxData)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check that we're not busy.*/
+    if (handle->state == kDSPI_Busy)
+    {
+        return kStatus_DSPI_Busy;
+    }
+
+    uint32_t instance = DSPI_GetInstance(base);
+    uint16_t wordToSend = 0;
+    uint8_t dummyData = DSPI_DUMMY_DATA;
+    uint8_t dataAlreadyFed = 0;
+    uint8_t dataFedMax = 2;
+
+    uint32_t rxAddr = DSPI_GetRxRegisterAddress(base);
+    uint32_t txAddr = DSPI_MasterGetTxRegisterAddress(base);
+
+    edma_tcd_t *softwareTCD = (edma_tcd_t *)((uint32_t)(&handle->dspiSoftwareTCD[1]) & (~0x1FU));
+
+    edma_transfer_config_t transferConfigA;
+    edma_transfer_config_t transferConfigB;
+    edma_transfer_config_t transferConfigC;
+
+    handle->txBuffIfNull = ((uint32_t)DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA;
+
+    handle->state = kDSPI_Busy;
+
+    dspi_command_data_config_t commandStruct;
+    DSPI_StopTransfer(base);
+    DSPI_FlushFifo(base, true, true);
+    DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag);
+
+    commandStruct.whichPcs =
+        (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT));
+    commandStruct.isEndOfQueue = false;
+    commandStruct.clearTransferCount = false;
+    commandStruct.whichCtar =
+        (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT);
+    commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous);
+    handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct));
+
+    commandStruct.isEndOfQueue = true;
+    commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer);
+    handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct));
+
+    handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1;
+
+    if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK))
+    {
+        handle->fifoSize = 1;
+    }
+    else
+    {
+        handle->fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base);
+    }
+    handle->txData = transfer->txData;
+    handle->rxData = transfer->rxData;
+    handle->remainingSendByteCount = transfer->dataSize;
+    handle->remainingReceiveByteCount = transfer->dataSize;
+    handle->totalByteCount = transfer->dataSize;
+
+    /* this limits the amount of data we can transfer due to the linked channel.
+    * The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
+    */
+    if (handle->bitsPerFrame > 8)
+    {
+        if (transfer->dataSize > 1022)
+        {
+            return kStatus_DSPI_OutOfRange;
+        }
+    }
+    else
+    {
+        if (transfer->dataSize > 511)
+        {
+            return kStatus_DSPI_OutOfRange;
+        }
+    }
+
+    DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
+
+    EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiMasterCallback,
+                     &s_dspiMasterEdmaPrivateHandle[instance]);
+
+    handle->isThereExtraByte = false;
+    if (handle->bitsPerFrame > 8)
+    {
+        if (handle->remainingSendByteCount % 2 == 1)
+        {
+            handle->remainingSendByteCount++;
+            handle->remainingReceiveByteCount--;
+            handle->isThereExtraByte = true;
+        }
+    }
+
+    /*If dspi has separate dma request , prepare the first data in "intermediary" .
+    else (dspi has shared dma request) , send first 2 data if there is fifo or send first 1 data if there is no fifo*/
+    if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        /* For DSPI instances with separate RX/TX DMA requests, we'll use the TX DMA request to
+        * trigger the TX DMA channel and RX DMA request to trigger the RX DMA channel
+        */
+
+        /*Prepare the firt data*/
+        if (handle->bitsPerFrame > 8)
+        {
+            /* If it's the last word */
+            if (handle->remainingSendByteCount <= 2)
+            {
+                if (handle->txData)
+                {
+                    if (handle->isThereExtraByte)
+                    {
+                        wordToSend = *(handle->txData) | ((uint32_t)dummyData << 8);
+                    }
+                    else
+                    {
+                        wordToSend = *(handle->txData);
+                        ++handle->txData; /* increment to next data byte */
+                        wordToSend |= (unsigned)(*(handle->txData)) << 8U;
+                    }
+                }
+                else
+                {
+                    wordToSend = ((uint32_t)dummyData << 8) | dummyData;
+                }
+                handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
+            }
+            else /* For all words except the last word , frame > 8bits */
+            {
+                if (handle->txData)
+                {
+                    wordToSend = *(handle->txData);
+                    ++handle->txData; /* increment to next data byte */
+                    wordToSend |= (unsigned)(*(handle->txData)) << 8U;
+                    ++handle->txData; /* increment to next data byte */
+                }
+                else
+                {
+                    wordToSend = ((uint32_t)dummyData << 8) | dummyData;
+                }
+                handle->command = (handle->command & 0xffff0000U) | wordToSend;
+            }
+        }
+        else /* Optimized for bits/frame less than or equal to one byte. */
+        {
+            if (handle->txData)
+            {
+                wordToSend = *(handle->txData);
+                ++handle->txData; /* increment to next data word*/
+            }
+            else
+            {
+                wordToSend = dummyData;
+            }
+
+            if (handle->remainingSendByteCount == 1)
+            {
+                handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
+            }
+            else
+            {
+                handle->command = (handle->command & 0xffff0000U) | wordToSend;
+            }
+        }
+    }
+
+    else /*dspi has shared dma request*/
+
+    {
+        /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
+        * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
+        */
+
+        /* If bits/frame is greater than one byte */
+        if (handle->bitsPerFrame > 8)
+        {
+            while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)
+            {
+                if (handle->remainingSendByteCount <= 2)
+                {
+                    if (handle->txData)
+                    {
+                        if (handle->isThereExtraByte)
+                        {
+                            wordToSend = *(handle->txData) | ((uint32_t)dummyData << 8);
+                        }
+                        else
+                        {
+                            wordToSend = *(handle->txData);
+                            ++handle->txData;
+                            wordToSend |= (unsigned)(*(handle->txData)) << 8U;
+                        }
+                    }
+                    else
+                    {
+                        wordToSend = ((uint32_t)dummyData << 8) | dummyData;
+                        ;
+                    }
+                    handle->remainingSendByteCount = 0;
+                    base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend;
+                }
+                /* For all words except the last word */
+                else
+                {
+                    if (handle->txData)
+                    {
+                        wordToSend = *(handle->txData);
+                        ++handle->txData;
+                        wordToSend |= (unsigned)(*(handle->txData)) << 8U;
+                        ++handle->txData;
+                    }
+                    else
+                    {
+                        wordToSend = ((uint32_t)dummyData << 8) | dummyData;
+                        ;
+                    }
+                    handle->remainingSendByteCount -= 2;
+                    base->PUSHR = (handle->command & 0xffff0000U) | wordToSend;
+                }
+
+                /* Try to clear the TFFF; if the TX FIFO is full this will clear */
+                DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+
+                dataAlreadyFed += 2;
+
+                /* exit loop if send count is zero, else update local variables for next loop */
+                if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == (dataFedMax * 2)))
+                {
+                    break;
+                }
+            } /* End of TX FIFO fill while loop */
+        }
+        else /* Optimized for bits/frame less than or equal to one byte. */
+        {
+            while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)
+            {
+                if (handle->txData)
+                {
+                    wordToSend = *(handle->txData);
+                    ++handle->txData;
+                }
+                else
+                {
+                    wordToSend = dummyData;
+                }
+
+                if (handle->remainingSendByteCount == 1)
+                {
+                    base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend;
+                }
+                else
+                {
+                    base->PUSHR = (handle->command & 0xffff0000U) | wordToSend;
+                }
+
+                /* Try to clear the TFFF; if the TX FIFO is full this will clear */
+                DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+
+                --handle->remainingSendByteCount;
+
+                dataAlreadyFed++;
+
+                /* exit loop if send count is zero, else update local variables for next loop */
+                if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == dataFedMax))
+                {
+                    break;
+                }
+            } /* End of TX FIFO fill while loop */
+        }
+    }
+
+    /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/
+    EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
+
+    transferConfigA.srcAddr = (uint32_t)rxAddr;
+    transferConfigA.srcOffset = 0;
+
+    if (handle->rxData)
+    {
+        transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]);
+        transferConfigA.destOffset = 1;
+    }
+    else
+    {
+        transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull);
+        transferConfigA.destOffset = 0;
+    }
+
+    transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes;
+
+    if (handle->bitsPerFrame <= 8)
+    {
+        transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes;
+        transferConfigA.minorLoopBytes = 1;
+        transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount;
+    }
+    else
+    {
+        transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes;
+        transferConfigA.minorLoopBytes = 2;
+        transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2;
+    }
+    EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+                           &transferConfigA, NULL);
+    EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+                                 kEDMA_MajorInterruptEnable);
+
+    /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should
+    write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the
+    SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */
+    EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel);
+
+    if (handle->remainingSendByteCount > 0)
+    {
+        if (handle->txData)
+        {
+            transferConfigB.srcAddr = (uint32_t)(handle->txData);
+            transferConfigB.srcOffset = 1;
+        }
+        else
+        {
+            transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull);
+            transferConfigB.srcOffset = 0;
+        }
+
+        transferConfigB.destAddr = (uint32_t)(&handle->command);
+        transferConfigB.destOffset = 0;
+
+        transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes;
+
+        if (handle->bitsPerFrame <= 8)
+        {
+            transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes;
+            transferConfigB.minorLoopBytes = 1;
+
+            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+            {
+                /*already prepared the first data in "intermediary" , so minus 1 */
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 1;
+            }
+            else
+            {
+                /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
+                majorlink , the majorlink would not trigger the channel_C*/
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1;
+            }
+        }
+        else
+        {
+            transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes;
+            transferConfigB.minorLoopBytes = 2;
+            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+            {
+                /*already prepared the first data in "intermediary" , so minus 1 */
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
+            }
+            else
+            {
+                /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
+                * majorlink*/
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 + 1;
+            }
+        }
+
+        EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
+                               handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
+    }
+
+    /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to
+    handle the last data */
+    EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
+
+    if (((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
+        ((((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) ||
+          ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8))) &&
+         (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))))
+    {
+        if (handle->txData)
+        {
+            uint32_t bufferIndex = 0;
+
+            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+            {
+                if (handle->bitsPerFrame <= 8)
+                {
+                    bufferIndex = handle->remainingSendByteCount - 1;
+                }
+                else
+                {
+                    bufferIndex = handle->remainingSendByteCount - 2;
+                }
+            }
+            else
+            {
+                bufferIndex = handle->remainingSendByteCount;
+            }
+
+            if (handle->bitsPerFrame <= 8)
+            {
+                handle->lastCommand = (handle->lastCommand & 0xffff0000U) | handle->txData[bufferIndex - 1];
+            }
+            else
+            {
+                if (handle->isThereExtraByte)
+                {
+                    handle->lastCommand = (handle->lastCommand & 0xffff0000U) | handle->txData[bufferIndex - 2] |
+                                          ((uint32_t)dummyData << 8);
+                }
+                else
+                {
+                    handle->lastCommand = (handle->lastCommand & 0xffff0000U) |
+                                          ((uint32_t)handle->txData[bufferIndex - 1] << 8) |
+                                          handle->txData[bufferIndex - 2];
+                }
+            }
+        }
+        else
+        {
+            if (handle->bitsPerFrame <= 8)
+            {
+                wordToSend = dummyData;
+            }
+            else
+            {
+                wordToSend = ((uint32_t)dummyData << 8) | dummyData;
+            }
+            handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
+        }
+    }
+
+    if ((1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) ||
+        ((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0)))
+    {
+        transferConfigC.srcAddr = (uint32_t) & (handle->lastCommand);
+        transferConfigC.destAddr = (uint32_t)txAddr;
+        transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes;
+        transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes;
+        transferConfigC.srcOffset = 0;
+        transferConfigC.destOffset = 0;
+        transferConfigC.minorLoopBytes = 4;
+        transferConfigC.majorLoopCounts = 1;
+
+        EDMA_TcdReset(softwareTCD);
+        EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigC, NULL);
+    }
+
+    if (((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) ||
+        ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8)))
+    {
+        transferConfigC.srcAddr = (uint32_t)(&(handle->command));
+        transferConfigC.destAddr = (uint32_t)txAddr;
+
+        transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes;
+        transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes;
+        transferConfigC.srcOffset = 0;
+        transferConfigC.destOffset = 0;
+        transferConfigC.minorLoopBytes = 4;
+
+        if (handle->bitsPerFrame <= 8)
+        {
+            transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1;
+        }
+        else
+        {
+            transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
+        }
+
+        EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+                               handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD);
+        EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base,
+                                   handle->edmaIntermediaryToTxRegHandle->channel, false);
+    }
+    else
+    {
+        EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+                               handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, NULL);
+    }
+
+    /*Start the EDMA channel_A , channel_B , channel_C transfer*/
+    EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
+    EDMA_StartTransfer(handle->edmaTxDataToIntermediaryHandle);
+    EDMA_StartTransfer(handle->edmaIntermediaryToTxRegHandle);
+
+    /*Set channel priority*/
+    uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel;
+    uint8_t channelPriorityMid = handle->edmaTxDataToIntermediaryHandle->channel;
+    uint8_t channelPriorityHigh = handle->edmaIntermediaryToTxRegHandle->channel;
+    uint8_t t = 0;
+    if (channelPriorityLow > channelPriorityMid)
+    {
+        t = channelPriorityLow;
+        channelPriorityLow = channelPriorityMid;
+        channelPriorityMid = t;
+    }
+
+    if (channelPriorityLow > channelPriorityHigh)
+    {
+        t = channelPriorityLow;
+        channelPriorityLow = channelPriorityHigh;
+        channelPriorityHigh = t;
+    }
+
+    if (channelPriorityMid > channelPriorityHigh)
+    {
+        t = channelPriorityMid;
+        channelPriorityMid = channelPriorityHigh;
+        channelPriorityHigh = t;
+    }
+    edma_channel_Preemption_config_t preemption_config_t;
+    preemption_config_t.enableChannelPreemption = true;
+    preemption_config_t.enablePreemptAbility = true;
+    preemption_config_t.channelPriority = channelPriorityLow;
+
+    if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+                                        &preemption_config_t);
+
+        preemption_config_t.channelPriority = channelPriorityMid;
+        EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base,
+                                        handle->edmaTxDataToIntermediaryHandle->channel, &preemption_config_t);
+
+        preemption_config_t.channelPriority = channelPriorityHigh;
+        EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base,
+                                        handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t);
+    }
+    else
+    {
+        EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base,
+                                        handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t);
+
+        preemption_config_t.channelPriority = channelPriorityMid;
+        EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base,
+                                        handle->edmaTxDataToIntermediaryHandle->channel, &preemption_config_t);
+
+        preemption_config_t.channelPriority = channelPriorityHigh;
+        EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+                                        &preemption_config_t);
+    }
+
+    /*Set the channel link.
+    For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C.
+    For DSPI instances with separate RX and TX DMA requests:
+    Rx DMA request -> channel_A
+    Tx DMA request -> channel_C -> channel_B . (so need prepare the first data in "intermediary"  before the DMA
+    transfer and then channel_B is used to prepare the next data to "intermediary" ) */
+    if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        /*if there is Tx DMA request , carry the 32bits data (handle->command) to PUSHR first , then link to channelB
+        to prepare the next 32bits data (User_send_buffer to handle->command) */
+        if (handle->remainingSendByteCount > 1)
+        {
+            EDMA_SetChannelLink(handle->edmaIntermediaryToTxRegHandle->base,
+                                handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MinorLink,
+                                handle->edmaTxDataToIntermediaryHandle->channel);
+        }
+
+        DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
+    }
+    else
+    {
+        if (handle->remainingSendByteCount > 0)
+        {
+            EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+                                kEDMA_MinorLink, handle->edmaTxDataToIntermediaryHandle->channel);
+
+            if (handle->isThereExtraByte)
+            {
+                EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+                                    kEDMA_MajorLink, handle->edmaTxDataToIntermediaryHandle->channel);
+            }
+
+            EDMA_SetChannelLink(handle->edmaTxDataToIntermediaryHandle->base,
+                                handle->edmaTxDataToIntermediaryHandle->channel, kEDMA_MinorLink,
+                                handle->edmaIntermediaryToTxRegHandle->channel);
+        }
+
+        DSPI_EnableDMA(base, kDSPI_RxDmaEnable);
+    }
+
+    DSPI_StartTransfer(base);
+
+    return kStatus_Success;
+}
+
+static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
+                                    void *g_dspiEdmaPrivateHandle,
+                                    bool transferDone,
+                                    uint32_t tcds)
+{
+    dspi_master_edma_private_handle_t *dspiEdmaPrivateHandle;
+
+    dspiEdmaPrivateHandle = (dspi_master_edma_private_handle_t *)g_dspiEdmaPrivateHandle;
+
+    uint32_t dataReceived;
+
+    DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
+
+    if (dspiEdmaPrivateHandle->handle->isThereExtraByte)
+    {
+        while (!((dspiEdmaPrivateHandle->base)->SR & SPI_SR_RFDF_MASK))
+        {
+        }
+        dataReceived = (dspiEdmaPrivateHandle->base)->POPR;
+        if (dspiEdmaPrivateHandle->handle->rxData)
+        {
+            (dspiEdmaPrivateHandle->handle->rxData[dspiEdmaPrivateHandle->handle->totalByteCount - 1]) = dataReceived;
+        }
+    }
+
+    if (dspiEdmaPrivateHandle->handle->callback)
+    {
+        dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle,
+                                                kStatus_Success, dspiEdmaPrivateHandle->handle->userData);
+    }
+
+    dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
+}
+
+void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle)
+{
+    DSPI_StopTransfer(base);
+
+    DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
+
+    EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle);
+    EDMA_AbortTransfer(handle->edmaTxDataToIntermediaryHandle);
+    EDMA_AbortTransfer(handle->edmaIntermediaryToTxRegHandle);
+
+    handle->state = kDSPI_Idle;
+}
+
+status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state != kDSPI_Busy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    size_t bytes;
+
+    bytes = EDMA_GetRemainingBytes(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
+
+    *count = handle->totalByteCount - bytes;
+
+    return kStatus_Success;
+}
+
+void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base,
+                                        dspi_slave_edma_handle_t *handle,
+                                        dspi_slave_edma_transfer_callback_t callback,
+                                        void *userData,
+                                        edma_handle_t *edmaRxRegToRxDataHandle,
+                                        edma_handle_t *edmaTxDataToTxRegHandle)
+{
+    assert(handle);
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    uint32_t instance = DSPI_GetInstance(base);
+
+    s_dspiSlaveEdmaPrivateHandle[instance].base = base;
+    s_dspiSlaveEdmaPrivateHandle[instance].handle = handle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle;
+    handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle;
+}
+
+status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer)
+{
+    assert(handle && transfer);
+
+    /* If send/receive length is zero */
+    if (transfer->dataSize == 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If both send buffer and receive buffer is null */
+    if ((!(transfer->txData)) && (!(transfer->rxData)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check that we're not busy.*/
+    if (handle->state == kDSPI_Busy)
+    {
+        return kStatus_DSPI_Busy;
+    }
+
+    edma_tcd_t *softwareTCD = (edma_tcd_t *)((uint32_t)(&handle->dspiSoftwareTCD[1]) & (~0x1FU));
+
+    uint32_t instance = DSPI_GetInstance(base);
+    uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT;
+    handle->bitsPerFrame =
+        (((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1;
+
+    /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
+    * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
+    */
+    if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        if (handle->bitsPerFrame > 8)
+        {
+            if (transfer->dataSize > 1022)
+            {
+                return kStatus_DSPI_OutOfRange;
+            }
+        }
+        else
+        {
+            if (transfer->dataSize > 511)
+            {
+                return kStatus_DSPI_OutOfRange;
+            }
+        }
+    }
+
+    if ((handle->bitsPerFrame > 8) && (transfer->dataSize < 2))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiSlaveCallback, &s_dspiSlaveEdmaPrivateHandle[instance]);
+
+    handle->state = kDSPI_Busy;
+
+    /* Store transfer information */
+    handle->txData = transfer->txData;
+    handle->rxData = transfer->rxData;
+    handle->remainingSendByteCount = transfer->dataSize;
+    handle->remainingReceiveByteCount = transfer->dataSize;
+    handle->totalByteCount = transfer->dataSize;
+    handle->errorCount = 0;
+
+    handle->isThereExtraByte = false;
+    if (handle->bitsPerFrame > 8)
+    {
+        if (handle->remainingSendByteCount % 2 == 1)
+        {
+            handle->remainingSendByteCount++;
+            handle->remainingReceiveByteCount--;
+            handle->isThereExtraByte = true;
+        }
+    }
+
+    uint16_t wordToSend = 0;
+    uint8_t dummyData = DSPI_DUMMY_DATA;
+    uint8_t dataAlreadyFed = 0;
+    uint8_t dataFedMax = 2;
+
+    uint32_t rxAddr = DSPI_GetRxRegisterAddress(base);
+    uint32_t txAddr = DSPI_SlaveGetTxRegisterAddress(base);
+
+    edma_transfer_config_t transferConfigA;
+    edma_transfer_config_t transferConfigC;
+
+    DSPI_StopTransfer(base);
+
+    DSPI_FlushFifo(base, true, true);
+    DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag);
+
+    DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
+
+    DSPI_StartTransfer(base);
+
+    /*if dspi has separate dma request , need not prepare data first .
+    else (dspi has shared dma request) , send first 2 data into fifo if there is fifo or send first 1 data to
+    slaveGetTxRegister if there is no fifo*/
+    if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
+        * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
+        */
+        /* If bits/frame is greater than one byte */
+        if (handle->bitsPerFrame > 8)
+        {
+            while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)
+            {
+                if (handle->txData)
+                {
+                    wordToSend = *(handle->txData);
+                    ++handle->txData; /* Increment to next data byte */
+                    if ((handle->remainingSendByteCount == 2) && (handle->isThereExtraByte))
+                    {
+                        wordToSend |= (unsigned)(dummyData) << 8U;
+                        ++handle->txData; /* Increment to next data byte */
+                    }
+                    else
+                    {
+                        wordToSend |= (unsigned)(*(handle->txData)) << 8U;
+                        ++handle->txData; /* Increment to next data byte */
+                    }
+                }
+                else
+                {
+                    wordToSend = ((uint32_t)dummyData << 8) | dummyData;
+                }
+                handle->remainingSendByteCount -= 2; /* decrement remainingSendByteCount by 2 */
+                base->PUSHR_SLAVE = wordToSend;
+
+                /* Try to clear the TFFF; if the TX FIFO is full this will clear */
+                DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+
+                dataAlreadyFed += 2;
+
+                /* Exit loop if send count is zero, else update local variables for next loop */
+                if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == (dataFedMax * 2)))
+                {
+                    break;
+                }
+            } /* End of TX FIFO fill while loop */
+        }
+        else /* Optimized for bits/frame less than or equal to one byte. */
+        {
+            while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)
+            {
+                if (handle->txData)
+                {
+                    wordToSend = *(handle->txData);
+                    /* Increment to next data word*/
+                    ++handle->txData;
+                }
+                else
+                {
+                    wordToSend = dummyData;
+                }
+
+                base->PUSHR_SLAVE = wordToSend;
+
+                /* Try to clear the TFFF; if the TX FIFO is full this will clear */
+                DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
+                /* Decrement remainingSendByteCount*/
+                --handle->remainingSendByteCount;
+
+                dataAlreadyFed++;
+
+                /* Exit loop if send count is zero, else update local variables for next loop */
+                if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == dataFedMax))
+                {
+                    break;
+                }
+            } /* End of TX FIFO fill while loop */
+        }
+    }
+
+    /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/
+    if (handle->remainingReceiveByteCount > 0)
+    {
+        EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
+
+        transferConfigA.srcAddr = (uint32_t)rxAddr;
+        transferConfigA.srcOffset = 0;
+
+        if (handle->rxData)
+        {
+            transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]);
+            transferConfigA.destOffset = 1;
+        }
+        else
+        {
+            transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull);
+            transferConfigA.destOffset = 0;
+        }
+
+        transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes;
+
+        if (handle->bitsPerFrame <= 8)
+        {
+            transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes;
+            transferConfigA.minorLoopBytes = 1;
+            transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount;
+        }
+        else
+        {
+            transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes;
+            transferConfigA.minorLoopBytes = 2;
+            transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2;
+        }
+        EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+                               &transferConfigA, NULL);
+        EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+                                     kEDMA_MajorInterruptEnable);
+    }
+
+    if (handle->remainingSendByteCount > 0)
+    {
+        /***channel_C *** used for carry the data from User_Send_Buffer to Tx_Data_Register(PUSHR_SLAVE)*/
+        EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel);
+
+        /*If there is extra byte , it would use the */
+        if (handle->isThereExtraByte)
+        {
+            if (handle->txData)
+            {
+                handle->txLastData =
+                    handle->txData[handle->remainingSendByteCount - 2] | ((uint32_t)DSPI_DUMMY_DATA << 8);
+            }
+            else
+            {
+                handle->txLastData = DSPI_DUMMY_DATA | ((uint32_t)DSPI_DUMMY_DATA << 8);
+            }
+            transferConfigC.srcAddr = (uint32_t)(&(handle->txLastData));
+            transferConfigC.destAddr = (uint32_t)txAddr;
+            transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes;
+            transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes;
+            transferConfigC.srcOffset = 0;
+            transferConfigC.destOffset = 0;
+            transferConfigC.minorLoopBytes = 4;
+            transferConfigC.majorLoopCounts = 1;
+
+            EDMA_TcdReset(softwareTCD);
+            EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigC, NULL);
+        }
+
+        /*Set another  transferConfigC*/
+        if ((handle->isThereExtraByte) && (handle->remainingSendByteCount == 2))
+        {
+            EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
+                                   &transferConfigC, NULL);
+        }
+        else
+        {
+            transferConfigC.destAddr = (uint32_t)txAddr;
+            transferConfigC.destOffset = 0;
+
+            if (handle->txData)
+            {
+                transferConfigC.srcAddr = (uint32_t)(&(handle->txData[0]));
+                transferConfigC.srcOffset = 1;
+            }
+            else
+            {
+                transferConfigC.srcAddr = (uint32_t)(&handle->txBuffIfNull);
+                transferConfigC.srcOffset = 0;
+                if (handle->bitsPerFrame <= 8)
+                {
+                    handle->txBuffIfNull = DSPI_DUMMY_DATA;
+                }
+                else
+                {
+                    handle->txBuffIfNull = (DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA;
+                }
+            }
+
+            transferConfigC.srcTransferSize = kEDMA_TransferSize1Bytes;
+
+            if (handle->bitsPerFrame <= 8)
+            {
+                transferConfigC.destTransferSize = kEDMA_TransferSize1Bytes;
+                transferConfigC.minorLoopBytes = 1;
+                transferConfigC.majorLoopCounts = handle->remainingSendByteCount;
+            }
+            else
+            {
+                transferConfigC.destTransferSize = kEDMA_TransferSize2Bytes;
+                transferConfigC.minorLoopBytes = 2;
+                if (handle->isThereExtraByte)
+                {
+                    transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
+                }
+                else
+                {
+                    transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2;
+                }
+            }
+
+            if (handle->isThereExtraByte)
+            {
+                EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
+                                       &transferConfigC, softwareTCD);
+                EDMA_EnableAutoStopRequest(handle->edmaTxDataToTxRegHandle->base,
+                                           handle->edmaTxDataToTxRegHandle->channel, false);
+            }
+            else
+            {
+                EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
+                                       &transferConfigC, NULL);
+            }
+
+            EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle);
+        }
+    }
+
+    EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
+
+    /*Set channel priority*/
+    uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel;
+    uint8_t channelPriorityHigh = handle->edmaTxDataToTxRegHandle->channel;
+    uint8_t t = 0;
+
+    if (channelPriorityLow > channelPriorityHigh)
+    {
+        t = channelPriorityLow;
+        channelPriorityLow = channelPriorityHigh;
+        channelPriorityHigh = t;
+    }
+
+    edma_channel_Preemption_config_t preemption_config_t;
+    preemption_config_t.enableChannelPreemption = true;
+    preemption_config_t.enablePreemptAbility = true;
+    preemption_config_t.channelPriority = channelPriorityLow;
+
+    if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+                                        &preemption_config_t);
+
+        preemption_config_t.channelPriority = channelPriorityHigh;
+        EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
+                                        &preemption_config_t);
+    }
+    else
+    {
+        EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
+                                        &preemption_config_t);
+
+        preemption_config_t.channelPriority = channelPriorityHigh;
+        EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+                                        &preemption_config_t);
+    }
+
+    /*Set the channel link.
+    For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_C.
+    For DSPI instances with separate RX and TX DMA requests:
+    Rx DMA request -> channel_A
+    Tx DMA request -> channel_C */
+    if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        if (handle->remainingSendByteCount > 0)
+        {
+            EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+                                kEDMA_MinorLink, handle->edmaTxDataToTxRegHandle->channel);
+        }
+        DSPI_EnableDMA(base, kDSPI_RxDmaEnable);
+    }
+    else
+    {
+        DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
+    }
+
+    return kStatus_Success;
+}
+
+static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle,
+                                   void *g_dspiEdmaPrivateHandle,
+                                   bool transferDone,
+                                   uint32_t tcds)
+{
+    dspi_slave_edma_private_handle_t *dspiEdmaPrivateHandle;
+
+    dspiEdmaPrivateHandle = (dspi_slave_edma_private_handle_t *)g_dspiEdmaPrivateHandle;
+
+    uint32_t dataReceived;
+
+    DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
+
+    if (dspiEdmaPrivateHandle->handle->isThereExtraByte)
+    {
+        while (!((dspiEdmaPrivateHandle->base)->SR & SPI_SR_RFDF_MASK))
+        {
+        }
+        dataReceived = (dspiEdmaPrivateHandle->base)->POPR;
+        if (dspiEdmaPrivateHandle->handle->rxData)
+        {
+            (dspiEdmaPrivateHandle->handle->rxData[dspiEdmaPrivateHandle->handle->totalByteCount - 1]) = dataReceived;
+        }
+    }
+
+    if (dspiEdmaPrivateHandle->handle->callback)
+    {
+        dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle,
+                                                kStatus_Success, dspiEdmaPrivateHandle->handle->userData);
+    }
+
+    dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
+}
+
+void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle)
+{
+    DSPI_StopTransfer(base);
+
+    DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
+
+    EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle);
+    EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle);
+
+    handle->state = kDSPI_Idle;
+}
+
+status_t DSPI_SlaveTransferGetCountEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state != kDSPI_Busy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    size_t bytes;
+
+    bytes = EDMA_GetRemainingBytes(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
+
+    *count = handle->totalByteCount - bytes;
+
+    return kStatus_Success;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi_edma.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi_edma.h
new file mode 100644
index 00000000000..643efadca4c
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_dspi_edma.h
@@ -0,0 +1,282 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_DSPI_EDMA_H_
+#define _FSL_DSPI_EDMA_H_
+
+#include "fsl_dspi.h"
+#include "fsl_edma.h"
+/*!
+ * @addtogroup dspi_edma_driver
+ * @{
+ */
+
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*!
+* @brief Forward declaration of the DSPI eDMA master handle typedefs.
+*/
+typedef struct _dspi_master_edma_handle dspi_master_edma_handle_t;
+
+/*!
+* @brief Forward declaration of the DSPI eDMA slave handle typedefs.
+*/
+typedef struct _dspi_slave_edma_handle dspi_slave_edma_handle_t;
+
+/*!
+ * @brief Completion callback function pointer type.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle Pointer to the handle for the DSPI master.
+ * @param status Success or error code describing whether the transfer completed.
+ * @param userData Arbitrary pointer-dataSized value passed from the application.
+ */
+typedef void (*dspi_master_edma_transfer_callback_t)(SPI_Type *base,
+                                                     dspi_master_edma_handle_t *handle,
+                                                     status_t status,
+                                                     void *userData);
+/*!
+ * @brief Completion callback function pointer type.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle Pointer to the handle for the DSPI slave.
+ * @param status Success or error code describing whether the transfer completed.
+ * @param userData Arbitrary pointer-dataSized value passed from the application.
+ */
+typedef void (*dspi_slave_edma_transfer_callback_t)(SPI_Type *base,
+                                                    dspi_slave_edma_handle_t *handle,
+                                                    status_t status,
+                                                    void *userData);
+
+/*! @brief DSPI master eDMA transfer handle structure used for transactional API. */
+struct _dspi_master_edma_handle
+{
+    uint32_t bitsPerFrame;         /*!< Desired number of bits per frame. */
+    volatile uint32_t command;     /*!< Desired data command. */
+    volatile uint32_t lastCommand; /*!< Desired last data command. */
+
+    uint8_t fifoSize; /*!< FIFO dataSize. */
+
+    volatile bool isPcsActiveAfterTransfer; /*!< Is PCS signal keep active after the last frame transfer.*/
+    volatile bool isThereExtraByte;         /*!< Is there extra byte.*/
+
+    uint8_t *volatile txData;                  /*!< Send buffer. */
+    uint8_t *volatile rxData;                  /*!< Receive buffer. */
+    volatile size_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
+    size_t totalByteCount;                     /*!< Number of transfer bytes*/
+
+    uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/
+    uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/
+
+    volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/
+
+    dspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */
+    void *userData;                                /*!< Callback user data. */
+
+    edma_handle_t *edmaRxRegToRxDataHandle;        /*!<edma_handle_t handle point used for RxReg to RxData buff*/
+    edma_handle_t *edmaTxDataToIntermediaryHandle; /*!<edma_handle_t handle point used for TxData to Intermediary*/
+    edma_handle_t *edmaIntermediaryToTxRegHandle;  /*!<edma_handle_t handle point used for Intermediary to TxReg*/
+
+    edma_tcd_t dspiSoftwareTCD[2]; /*!<SoftwareTCD , internal used*/
+};
+
+/*! @brief DSPI slave eDMA transfer handle structure used for transactional API.*/
+struct _dspi_slave_edma_handle
+{
+    uint32_t bitsPerFrame;          /*!< Desired number of bits per frame. */
+    volatile bool isThereExtraByte; /*!< Is there extra byte.*/
+
+    uint8_t *volatile txData;                  /*!< Send buffer. */
+    uint8_t *volatile rxData;                  /*!< Receive buffer. */
+    volatile size_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
+    size_t totalByteCount;                     /*!< Number of transfer bytes*/
+
+    uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/
+    uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/
+    uint32_t txLastData;   /*!< Used if there is an extra byte when 16bits per frame for DMA purpose.*/
+
+    volatile uint8_t state; /*!< DSPI transfer state.*/
+
+    uint32_t errorCount; /*!< Error count for slave transfer.*/
+
+    dspi_slave_edma_transfer_callback_t callback; /*!< Completion callback. */
+    void *userData;                               /*!< Callback user data. */
+
+    edma_handle_t *edmaRxRegToRxDataHandle; /*!<edma_handle_t handle point used for RxReg to RxData buff*/
+    edma_handle_t *edmaTxDataToTxRegHandle; /*!<edma_handle_t handle point used for TxData to TxReg*/
+
+    edma_tcd_t dspiSoftwareTCD[2]; /*!<SoftwareTCD , internal used*/
+};
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*Transactional APIs*/
+
+/*!
+ * @brief Initializes the DSPI master eDMA handle.
+ *
+ * This function initializes the DSPI eDMA handle which can be used for other DSPI transactional APIs.  Usually, for a
+ * specified DSPI instance, user need only call this API once to get the initialized handle.
+ *
+ * Note that DSPI eDMA has separated (RX and TX as two sources) or shared (RX  and TX are the same source) DMA request source.
+ * (1)For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and
+ * TX DMAMUX source for edmaIntermediaryToTxRegHandle.
+ * (2)For the shared DMA request source, enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle DSPI handle pointer to dspi_master_edma_handle_t.
+ * @param callback DSPI callback.
+ * @param userData callback function parameter.
+ * @param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t.
+ * @param edmaTxDataToIntermediaryHandle edmaTxDataToIntermediaryHandle pointer to edma_handle_t.
+ * @param edmaIntermediaryToTxRegHandle edmaIntermediaryToTxRegHandle pointer to edma_handle_t.
+ */
+void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base,
+                                         dspi_master_edma_handle_t *handle,
+                                         dspi_master_edma_transfer_callback_t callback,
+                                         void *userData,
+                                         edma_handle_t *edmaRxRegToRxDataHandle,
+                                         edma_handle_t *edmaTxDataToIntermediaryHandle,
+                                         edma_handle_t *edmaIntermediaryToTxRegHandle);
+
+/*!
+ * @brief DSPI master transfer data using eDMA.
+ *
+ * This function transfer data using eDMA. This is non-blocking function, which returns right away. When all data
+ * have been transfer, the callback function is called.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_master_edma_handle_t structure which stores the transfer state.
+ * @param transfer pointer to dspi_transfer_t structure.
+ * @return status of status_t.
+ */
+status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer);
+
+/*!
+ * @brief DSPI master aborts a transfer which using eDMA.
+ *
+ * This function aborts a transfer which using eDMA.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_master_edma_handle_t structure which stores the transfer state.
+ */
+void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle);
+
+/*!
+ * @brief Gets the master eDMA transfer count.
+ *
+ * This function get the master eDMA transfer count.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_master_edma_handle_t structure which stores the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @return status of status_t.
+ */
+status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Initializes the DSPI slave eDMA handle.
+ *
+ * This function initializes the DSPI eDMA handle which can be used for other DSPI transactional APIs.  Usually, for a
+ * specified DSPI instance, call this API once to get the initialized handle.
+ *
+ * Note that DSPI eDMA has separated (RN and TX in 2 sources) or shared (RX  and TX are the same source) DMA request source.
+ * (1)For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and
+ * TX DMAMUX source for edmaTxDataToTxRegHandle.
+ * (2)For the shared DMA request source,  enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle DSPI handle pointer to dspi_slave_edma_handle_t.
+ * @param callback DSPI callback.
+ * @param userData callback function parameter.
+ * @param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t.
+ * @param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t.
+ */
+void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base,
+                                        dspi_slave_edma_handle_t *handle,
+                                        dspi_slave_edma_transfer_callback_t callback,
+                                        void *userData,
+                                        edma_handle_t *edmaRxRegToRxDataHandle,
+                                        edma_handle_t *edmaTxDataToTxRegHandle);
+
+/*!
+ * @brief DSPI slave transfer data using eDMA.
+ *
+ * This function transfer data using eDMA. This is non-blocking function, which returns right away. When all data
+ * have been transfer, the callback function is called.
+ * Note that slave EDMA transfer cannot support the situation that transfer_size is 1 when the bitsPerFrame is greater
+ * than 8 .
+
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_slave_edma_handle_t structure which stores the transfer state.
+ * @param transfer pointer to dspi_transfer_t structure.
+ * @return status of status_t.
+ */
+status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer);
+
+/*!
+ * @brief DSPI slave aborts a transfer which using eDMA.
+ *
+ * This function aborts a transfer which using eDMA.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_slave_edma_handle_t structure which stores the transfer state.
+ */
+void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle);
+
+/*!
+ * @brief Gets the slave eDMA transfer count.
+ *
+ * This function gets the slave eDMA transfer count.
+ *
+ * @param base DSPI peripheral base address.
+ * @param handle pointer to dspi_slave_edma_handle_t structure which stores the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @return status of status_t.
+ */
+status_t DSPI_SlaveTransferGetCountEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, size_t *count);
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+       /*!
+        *@}
+        */
+
+#endif /*_FSL_DSPI_EDMA_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_edma.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_edma.c
new file mode 100644
index 00000000000..8ad12fcf2c3
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_edma.c
@@ -0,0 +1,1313 @@
+/*
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_edma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define EDMA_TRANSFER_ENABLED_MASK 0x80U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get instance number for EDMA.
+ *
+ * @param base EDMA peripheral base address.
+ */
+static uint32_t EDMA_GetInstance(DMA_Type *base);
+
+/*!
+ * @brief Push content of TCD structure into hardware TCD register.
+ *
+ * @param base EDMA peripheral base address.
+ * @param channel EDMA channel number.
+ * @param tcd Point to TCD structure.
+ */
+static void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map EDMA instance number to base pointer. */
+static DMA_Type *const s_edmaBases[] = DMA_BASE_PTRS;
+
+/*! @brief Array to map EDMA instance number to clock name. */
+static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS;
+
+/*! @brief Array to map EDMA instance number to IRQ number. */
+static const IRQn_Type s_edmaIRQNumber[] = DMA_CHN_IRQS;
+
+/*! @brief Pointers to transfer handle for each EDMA channel. */
+static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL * FSL_FEATURE_SOC_EDMA_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t EDMA_GetInstance(DMA_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_EDMA_COUNT; instance++)
+    {
+        if (s_edmaBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_EDMA_COUNT);
+
+    return instance;
+}
+
+static void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(tcd != NULL);
+    assert(((uint32_t)tcd & 0x1FU) == 0);
+
+    /* Push tcd into hardware TCD register */
+    base->TCD[channel].SADDR = tcd->SADDR;
+    base->TCD[channel].SOFF = tcd->SOFF;
+    base->TCD[channel].ATTR = tcd->ATTR;
+    base->TCD[channel].NBYTES_MLNO = tcd->NBYTES;
+    base->TCD[channel].SLAST = tcd->SLAST;
+    base->TCD[channel].DADDR = tcd->DADDR;
+    base->TCD[channel].DOFF = tcd->DOFF;
+    base->TCD[channel].CITER_ELINKNO = tcd->CITER;
+    base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA;
+    /* Clear DONE bit first, otherwise ESG cannot be set */
+    base->TCD[channel].CSR = 0;
+    base->TCD[channel].CSR = tcd->CSR;
+    base->TCD[channel].BITER_ELINKNO = tcd->BITER;
+}
+
+void EDMA_Init(DMA_Type *base, const edma_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tmpreg;
+
+    /* Ungate EDMA periphral clock */
+    CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]);
+    /* Configure EDMA peripheral according to the configuration structure. */
+    tmpreg = base->CR;
+    tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK);
+    tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) |
+               DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true));
+    base->CR = tmpreg;
+}
+
+void EDMA_Deinit(DMA_Type *base)
+{
+    /* Gate EDMA periphral clock */
+    CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]);
+}
+
+void EDMA_GetDefaultConfig(edma_config_t *config)
+{
+    assert(config != NULL);
+
+    config->enableRoundRobinArbitration = false;
+    config->enableHaltOnError = true;
+    config->enableContinuousLinkMode = false;
+    config->enableDebugMode = false;
+}
+
+void EDMA_ResetChannel(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]);
+}
+
+void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(config != NULL);
+    assert(((uint32_t)nextTcd & 0x1FU) == 0);
+
+    EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd);
+}
+
+void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(config != NULL);
+
+    uint32_t tmpreg;
+
+    tmpreg = base->TCD[channel].NBYTES_MLOFFYES;
+    tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
+    tmpreg |=
+        (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) |
+         DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset));
+    base->TCD[channel].NBYTES_MLOFFYES = tmpreg;
+}
+
+void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel);
+}
+
+void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
+}
+
+void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    uint32_t tmpreg;
+
+    tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
+    base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
+}
+
+void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    /* Enable error interrupt */
+    if (mask & kEDMA_ErrorInterruptEnable)
+    {
+        base->EEI |= (0x1U << channel);
+    }
+
+    /* Enable Major interrupt */
+    if (mask & kEDMA_MajorInterruptEnable)
+    {
+        base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK;
+    }
+
+    /* Enable Half major interrupt */
+    if (mask & kEDMA_HalfInterruptEnable)
+    {
+        base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK;
+    }
+}
+
+void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    /* Disable error interrupt */
+    if (mask & kEDMA_ErrorInterruptEnable)
+    {
+        base->EEI &= ~(0x1U << channel);
+    }
+
+    /* Disable Major interrupt */
+    if (mask & kEDMA_MajorInterruptEnable)
+    {
+        base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK;
+    }
+
+    /* Disable Half major interrupt */
+    if (mask & kEDMA_HalfInterruptEnable)
+    {
+        base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK;
+    }
+}
+
+void EDMA_TcdReset(edma_tcd_t *tcd)
+{
+    assert(tcd != NULL);
+    assert(((uint32_t)tcd & 0x1FU) == 0);
+
+    /* Reset channel TCD */
+    tcd->SADDR = 0U;
+    tcd->SOFF = 0U;
+    tcd->ATTR = 0U;
+    tcd->NBYTES = 0U;
+    tcd->SLAST = 0U;
+    tcd->DADDR = 0U;
+    tcd->DOFF = 0U;
+    tcd->CITER = 0U;
+    tcd->DLAST_SGA = 0U;
+    /* Enable auto disable request feature */
+    tcd->CSR = DMA_CSR_DREQ(true);
+    tcd->BITER = 0U;
+}
+
+void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
+{
+    assert(tcd != NULL);
+    assert(((uint32_t)tcd & 0x1FU) == 0);
+    assert(config != NULL);
+    assert(((uint32_t)nextTcd & 0x1FU) == 0);
+
+    /* source address */
+    tcd->SADDR = config->srcAddr;
+    /* destination address */
+    tcd->DADDR = config->destAddr;
+    /* Source data and destination data transfer size */
+    tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize);
+    /* Source address signed offset */
+    tcd->SOFF = config->srcOffset;
+    /* Destination address signed offset */
+    tcd->DOFF = config->destOffset;
+    /* Minor byte transfer count */
+    tcd->NBYTES = config->minorLoopBytes;
+    /* Current major iteration count */
+    tcd->CITER = config->majorLoopCounts;
+    /* Starting major iteration count */
+    tcd->BITER = config->majorLoopCounts;
+    /* Enable scatter/gather processing */
+    if (nextTcd != NULL)
+    {
+        tcd->DLAST_SGA = (uint32_t)nextTcd;
+        /*
+            Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig,
+            user must call EDMA_TcdReset or EDMA_ResetChannel which will set
+            DREQ, so must use "|" or "&" rather than "=".
+
+            Clear the DREQ bit because scatter gather has been enabled, so the
+            previous transfer is not the last transfer, and channel request should
+            be enabled at the next transfer(the next TCD).
+        */
+        tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
+    }
+}
+
+void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)
+{
+    assert(tcd != NULL);
+    assert(((uint32_t)tcd & 0x1FU) == 0);
+
+    uint32_t tmpreg;
+
+    tmpreg = tcd->NBYTES &
+             ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
+    tmpreg |=
+        (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) |
+         DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset));
+    tcd->NBYTES = tmpreg;
+}
+
+void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
+{
+    assert(tcd != NULL);
+    assert(((uint32_t)tcd & 0x1FU) == 0);
+    assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    if (type == kEDMA_MinorLink) /* Minor link config */
+    {
+        uint32_t tmpreg;
+
+        /* Enable minor link */
+        tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK;
+        tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK;
+        /* Set likned channel */
+        tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK);
+        tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel);
+        tcd->CITER = tmpreg;
+        tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK);
+        tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel);
+        tcd->BITER = tmpreg;
+    }
+    else if (type == kEDMA_MajorLink) /* Major link config */
+    {
+        uint32_t tmpreg;
+
+        /* Enable major link */
+        tcd->CSR |= DMA_CSR_MAJORELINK_MASK;
+        /* Set major linked channel */
+        tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK);
+        tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel);
+    }
+    else /* Link none */
+    {
+        tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK;
+        tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK;
+        tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK;
+    }
+}
+
+void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)
+{
+    assert(tcd != NULL);
+    assert(((uint32_t)tcd & 0x1FU) == 0);
+
+    uint32_t tmpreg;
+
+    tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
+    tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
+}
+
+void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)
+{
+    assert(tcd != NULL);
+
+    /* Enable Major interrupt */
+    if (mask & kEDMA_MajorInterruptEnable)
+    {
+        tcd->CSR |= DMA_CSR_INTMAJOR_MASK;
+    }
+
+    /* Enable Half major interrupt */
+    if (mask & kEDMA_HalfInterruptEnable)
+    {
+        tcd->CSR |= DMA_CSR_INTHALF_MASK;
+    }
+}
+
+void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)
+{
+    assert(tcd != NULL);
+
+    /* Disable Major interrupt */
+    if (mask & kEDMA_MajorInterruptEnable)
+    {
+        tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK;
+    }
+
+    /* Disable Half major interrupt */
+    if (mask & kEDMA_HalfInterruptEnable)
+    {
+        tcd->CSR &= ~DMA_CSR_INTHALF_MASK;
+    }
+}
+
+uint32_t EDMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    uint32_t nbytes = 0;
+    uint32_t remainingBytes = 0;
+
+    if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR)
+    {
+        remainingBytes = 0;
+    }
+    else
+    {
+        /* Calculate the nbytes */
+        if (base->TCD[channel].NBYTES_MLOFFYES & (DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK))
+        {
+            nbytes = (base->TCD[channel].NBYTES_MLOFFYES & DMA_NBYTES_MLOFFYES_NBYTES_MASK) >>
+                     DMA_NBYTES_MLOFFYES_NBYTES_SHIFT;
+        }
+        else
+        {
+            nbytes =
+                (base->TCD[channel].NBYTES_MLOFFNO & DMA_NBYTES_MLOFFNO_NBYTES_MASK) >> DMA_NBYTES_MLOFFNO_NBYTES_SHIFT;
+        }
+        /* Calculate the unfinished bytes */
+        if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK)
+        {
+            remainingBytes = ((base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >>
+                              DMA_CITER_ELINKYES_CITER_SHIFT) *
+                             nbytes;
+        }
+        else
+        {
+            remainingBytes =
+                ((base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT) *
+                nbytes;
+        }
+    }
+
+    return remainingBytes;
+}
+
+uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    uint32_t retval = 0;
+
+    /* Get DONE bit flag */
+    retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT);
+    /* Get ERROR bit flag */
+    retval |= (((base->ERR >> channel) & 0x1U) << 1U);
+    /* Get INT bit flag */
+    retval |= (((base->INT >> channel) & 0x1U) << 2U);
+
+    return retval;
+}
+
+void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    /* Clear DONE bit flag */
+    if (mask & kEDMA_DoneFlag)
+    {
+        base->CDNE = channel;
+    }
+    /* Clear ERROR bit flag */
+    if (mask & kEDMA_ErrorFlag)
+    {
+        base->CERR = channel;
+    }
+    /* Clear INT bit flag */
+    if (mask & kEDMA_InterruptFlag)
+    {
+        base->CINT = channel;
+    }
+}
+
+void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel)
+{
+    assert(handle != NULL);
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+
+    uint32_t edmaInstance;
+    uint32_t channelIndex;
+    edma_tcd_t *tcdRegs;
+
+    handle->base = base;
+    handle->channel = channel;
+    /* Get the DMA instance number */
+    edmaInstance = EDMA_GetInstance(base);
+    channelIndex = (edmaInstance * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel;
+    s_EDMAHandle[channelIndex] = handle;
+    /* Enable NVIC interrupt */
+    EnableIRQ(s_edmaIRQNumber[channelIndex]);
+    /*
+       Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set),
+       CSR will be 0. Because in order to suit EDMA busy check mechanism in
+       EDMA_SubmitTransfer, CSR must be set 0.
+    */
+    tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
+    tcdRegs->SADDR = 0;
+    tcdRegs->SOFF = 0;
+    tcdRegs->ATTR = 0;
+    tcdRegs->NBYTES = 0;
+    tcdRegs->SLAST = 0;
+    tcdRegs->DADDR = 0;
+    tcdRegs->DOFF = 0;
+    tcdRegs->CITER = 0;
+    tcdRegs->DLAST_SGA = 0;
+    tcdRegs->CSR = 0;
+    tcdRegs->BITER = 0;
+}
+
+void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)
+{
+    assert(handle != NULL);
+    assert(((uint32_t)tcdPool & 0x1FU) == 0);
+
+    /* Initialize tcd queue attibute. */
+    handle->header = 0;
+    handle->tail = 0;
+    handle->tcdUsed = 0;
+    handle->tcdSize = tcdSize;
+    handle->flags = 0;
+    handle->tcdPool = tcdPool;
+}
+
+void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)
+{
+    assert(handle != NULL);
+
+    handle->callback = callback;
+    handle->userData = userData;
+}
+
+void EDMA_PrepareTransfer(edma_transfer_config_t *config,
+                          void *srcAddr,
+                          uint32_t srcWidth,
+                          void *destAddr,
+                          uint32_t destWidth,
+                          uint32_t bytesEachRequest,
+                          uint32_t transferBytes,
+                          edma_transfer_type_t type)
+{
+    assert(config != NULL);
+    assert(srcAddr != NULL);
+    assert(destAddr != NULL);
+    assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U));
+    assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U));
+    assert(transferBytes % bytesEachRequest == 0);
+
+    config->destAddr = (uint32_t)destAddr;
+    config->srcAddr = (uint32_t)srcAddr;
+    config->minorLoopBytes = bytesEachRequest;
+    config->majorLoopCounts = transferBytes / bytesEachRequest;
+    switch (srcWidth)
+    {
+        case 1U:
+            config->srcTransferSize = kEDMA_TransferSize1Bytes;
+            break;
+        case 2U:
+            config->srcTransferSize = kEDMA_TransferSize2Bytes;
+            break;
+        case 4U:
+            config->srcTransferSize = kEDMA_TransferSize4Bytes;
+            break;
+        case 16U:
+            config->srcTransferSize = kEDMA_TransferSize16Bytes;
+            break;
+        case 32U:
+            config->srcTransferSize = kEDMA_TransferSize32Bytes;
+            break;
+        default:
+            break;
+    }
+    switch (destWidth)
+    {
+        case 1U:
+            config->destTransferSize = kEDMA_TransferSize1Bytes;
+            break;
+        case 2U:
+            config->destTransferSize = kEDMA_TransferSize2Bytes;
+            break;
+        case 4U:
+            config->destTransferSize = kEDMA_TransferSize4Bytes;
+            break;
+        case 16U:
+            config->destTransferSize = kEDMA_TransferSize16Bytes;
+            break;
+        case 32U:
+            config->destTransferSize = kEDMA_TransferSize32Bytes;
+            break;
+        default:
+            break;
+    }
+    switch (type)
+    {
+        case kEDMA_MemoryToMemory:
+            config->destOffset = destWidth;
+            config->srcOffset = srcWidth;
+            break;
+        case kEDMA_MemoryToPeripheral:
+            config->destOffset = 0U;
+            config->srcOffset = srcWidth;
+            break;
+        case kEDMA_PeripheralToMemory:
+            config->destOffset = destWidth;
+            config->srcOffset = 0U;
+            break;
+        default:
+            break;
+    }
+}
+
+status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)
+{
+    assert(handle != NULL);
+    assert(config != NULL);
+
+    edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
+
+    if (handle->tcdPool == NULL)
+    {
+        /*
+            Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because
+            if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit
+            this check mechanism, EDMA_CreatHandle will clear CSR register.
+        */
+        if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0))
+        {
+            return kStatus_EDMA_Busy;
+        }
+        else
+        {
+            EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL);
+            /* Enable auto disable request feature */
+            handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK;
+            /* Enable major interrupt */
+            handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK;
+
+            return kStatus_Success;
+        }
+    }
+    else /* Use the TCD queue. */
+    {
+        uint32_t primask;
+        uint32_t csr;
+        int8_t currentTcd;
+        int8_t previousTcd;
+        int8_t nextTcd;
+
+        /* Check if tcd pool is full. */
+        primask = DisableGlobalIRQ();
+        if (handle->tcdUsed >= handle->tcdSize)
+        {
+            EnableGlobalIRQ(primask);
+
+            return kStatus_EDMA_QueueFull;
+        }
+        currentTcd = handle->tail;
+        handle->tcdUsed++;
+        /* Calculate index of next TCD */
+        nextTcd = currentTcd + 1U;
+        if (nextTcd == handle->tcdSize)
+        {
+            nextTcd = 0U;
+        }
+        /* Advance queue tail index */
+        handle->tail = nextTcd;
+        EnableGlobalIRQ(primask);
+        /* Calculate index of previous TCD */
+        previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U;
+        /* Configure current TCD block. */
+        EDMA_TcdReset(&handle->tcdPool[currentTcd]);
+        EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL);
+        /* Enable major interrupt */
+        handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK;
+        /* Link current TCD with next TCD for identification of current TCD */
+        handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd];
+        /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */
+        if (currentTcd != previousTcd)
+        {
+            /* Enable scatter/gather feature in the previous TCD block. */
+            csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
+            handle->tcdPool[previousTcd].CSR = csr;
+            /*
+                Check if the TCD blcok in the registers is the previous one (points to current TCD block). It
+                is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to
+                link the TCD register in case link the current TCD with the dead chain when TCD loading occurs
+                before link the previous TCD block.
+            */
+            if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd])
+            {
+                /* Enable scatter/gather also in the TCD registers. */
+                csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
+                /* Must write the CSR register one-time, because the transfer maybe finished anytime. */
+                tcdRegs->CSR = csr;
+                /*
+                    It is very important to check the ESG bit!
+                    Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can
+                    be used to check if the dynamic TCD link operation is successful. If ESG bit is not set
+                    and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and
+                    the current TCD block has been loaded into TCD registers), it means transfer finished
+                    and TCD link operation fail, so must install TCD content into TCD registers and enable
+                    transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic
+                    link succeed.
+                */
+                if (tcdRegs->CSR & DMA_CSR_ESG_MASK)
+                {
+                    return kStatus_Success;
+                }
+                /*
+                    Check whether the current TCD block is already loaded in the TCD registers. It is another
+                    condition when ESG bit is not set: it means the dynamic TCD link succeed and the current
+                    TCD block has been loaded into TCD registers.
+                */
+                if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd])
+                {
+                    return kStatus_Success;
+                }
+                /*
+                    If go to this, means the previous transfer finished, and the DONE bit is set.
+                    So shall configure TCD registers.
+                */
+            }
+            else if (tcdRegs->DLAST_SGA != 0)
+            {
+                /* The current TCD block has been linked successfully. */
+                return kStatus_Success;
+            }
+            else
+            {
+                /*
+                    DLAST_SGA is 0 and it means the first submit transfer, so shall configure
+                    TCD registers.
+                */
+            }
+        }
+        /* There is no live chain, TCD block need to be installed in TCD registers. */
+        EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]);
+        /* Enable channel request again. */
+        if (handle->flags & EDMA_TRANSFER_ENABLED_MASK)
+        {
+            handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
+        }
+
+        return kStatus_Success;
+    }
+}
+
+void EDMA_StartTransfer(edma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    if (handle->tcdPool == NULL)
+    {
+        handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
+    }
+    else /* Use the TCD queue. */
+    {
+        uint32_t primask;
+        edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
+
+        handle->flags |= EDMA_TRANSFER_ENABLED_MASK;
+
+        /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */
+        if (tcdRegs->DLAST_SGA != 0U)
+        {
+            primask = DisableGlobalIRQ();
+            /* Check if channel request is actually disable. */
+            if ((handle->base->ERQ & (1U << handle->channel)) == 0U)
+            {
+                /* Check if transfer is paused. */
+                if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK))
+                {
+                    /*
+                        Re-enable channel request must be as soon as possible, so must put it into
+                        critical section to avoid task switching or interrupt service routine.
+                    */
+                    handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
+                }
+            }
+            EnableGlobalIRQ(primask);
+        }
+    }
+}
+
+void EDMA_StopTransfer(edma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK);
+    handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
+}
+
+void EDMA_AbortTransfer(edma_handle_t *handle)
+{
+    handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
+    /*
+        Clear CSR to release channel. Because if the given channel started transfer,
+        CSR will be not zero. Because if it is the last transfer, DREQ will be set.
+        If not, ESG will be set.
+    */
+    handle->base->TCD[handle->channel].CSR = 0;
+    /* Cancel all next TCD transfer. */
+    handle->base->TCD[handle->channel].DLAST_SGA = 0;
+}
+
+void EDMA_HandleIRQ(edma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    /* Clear EDMA interrupt flag */
+    handle->base->CINT = handle->channel;
+    if ((handle->tcdPool == NULL) && (handle->callback != NULL))
+    {
+        (handle->callback)(handle, handle->userData, true, 0);
+    }
+    else /* Use the TCD queue. */
+    {
+        uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA;
+        uint32_t sga_index;
+        int32_t tcds_done;
+        uint8_t new_header;
+        bool transfer_done;
+
+        /* Check if transfer is already finished. */
+        transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0);
+        /* Get the offset of the current transfer TCD blcoks. */
+        sga -= (uint32_t)handle->tcdPool;
+        /* Get the index of the current transfer TCD blcoks. */
+        sga_index = sga / sizeof(edma_tcd_t);
+        /* Adjust header positions. */
+        if (transfer_done)
+        {
+            /* New header shall point to the next TCD (current one is already finished) */
+            new_header = sga_index;
+        }
+        else
+        {
+            /* New header shall point to this descriptor (not finished yet) */
+            new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U;
+        }
+        /* Calculate the number of finished TCDs */
+        if (new_header == handle->header)
+        {
+            if (handle->tcdUsed == handle->tcdSize)
+            {
+                tcds_done = handle->tcdUsed;
+            }
+            else
+            {
+                /* Internal error occurs. */
+                tcds_done = 0;
+            }
+        }
+        else
+        {
+            tcds_done = new_header - handle->header;
+            if (tcds_done < 0)
+            {
+                tcds_done += handle->tcdSize;
+            }
+        }
+        /* Advance header to the point beyond the last finished TCD block. */
+        handle->header = new_header;
+        /* Release TCD blocks. */
+        handle->tcdUsed -= tcds_done;
+        /* Invoke callback function. */
+        if (handle->callback)
+        {
+            (handle->callback)(handle, handle->userData, transfer_done, tcds_done);
+        }
+    }
+}
+
+/* 8 channels (Shared): kl28 */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U
+
+void DMA0_04_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[0]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[4]);
+    }
+}
+
+void DMA0_15_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[1]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[5]);
+    }
+}
+
+void DMA0_26_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[2]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[6]);
+    }
+}
+
+void DMA0_37_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[3]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[7]);
+    }
+}
+#endif /* 8 channels (Shared) */
+
+/* 32 channels (Shared): k80 */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
+
+void DMA0_DMA16_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[0]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[16]);
+    }
+}
+
+void DMA1_DMA17_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[1]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[17]);
+    }
+}
+
+void DMA2_DMA18_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[2]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[18]);
+    }
+}
+
+void DMA3_DMA19_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[3]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[19]);
+    }
+}
+
+void DMA4_DMA20_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[4]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[20]);
+    }
+}
+
+void DMA5_DMA21_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[5]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[21]);
+    }
+}
+
+void DMA6_DMA22_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[6]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[22]);
+    }
+}
+
+void DMA7_DMA23_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[7]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[23]);
+    }
+}
+
+void DMA8_DMA24_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[8]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[24]);
+    }
+}
+
+void DMA9_DMA25_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[9]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[25]);
+    }
+}
+
+void DMA10_DMA26_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[10]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[26]);
+    }
+}
+
+void DMA11_DMA27_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[11]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[27]);
+    }
+}
+
+void DMA12_DMA28_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[12]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[28]);
+    }
+}
+
+void DMA13_DMA29_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[13]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[29]);
+    }
+}
+
+void DMA14_DMA30_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[14]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[30]);
+    }
+}
+
+void DMA15_DMA31_IRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[15]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[31]);
+    }
+}
+#endif /* 32 channels (Shared) */
+
+/* 4 channels (No Shared): kv10  */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0
+
+void DMA0_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[0]);
+}
+
+void DMA1_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[1]);
+}
+
+void DMA2_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[2]);
+}
+
+void DMA3_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[3]);
+}
+
+/* 8 channels (No Shared) */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U
+
+void DMA4_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[4]);
+}
+
+void DMA5_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[5]);
+}
+
+void DMA6_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[6]);
+}
+
+void DMA7_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[7]);
+}
+#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */
+
+/* 16 channels (No Shared) */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U
+
+void DMA8_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[8]);
+}
+
+void DMA9_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[9]);
+}
+
+void DMA10_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[10]);
+}
+
+void DMA11_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[11]);
+}
+
+void DMA12_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[12]);
+}
+
+void DMA13_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[13]);
+}
+
+void DMA14_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[14]);
+}
+
+void DMA15_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[15]);
+}
+#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */
+
+/* 32 channels (No Shared) */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U
+
+void DMA16_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[16]);
+}
+
+void DMA17_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[17]);
+}
+
+void DMA18_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[18]);
+}
+
+void DMA19_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[19]);
+}
+
+void DMA20_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[20]);
+}
+
+void DMA21_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[21]);
+}
+
+void DMA22_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[22]);
+}
+
+void DMA23_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[23]);
+}
+
+void DMA24_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[24]);
+}
+
+void DMA25_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[25]);
+}
+
+void DMA26_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[26]);
+}
+
+void DMA27_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[27]);
+}
+
+void DMA28_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[28]);
+}
+
+void DMA29_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[29]);
+}
+
+void DMA30_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[30]);
+}
+
+void DMA31_DriverIRQHandler(void)
+{
+    EDMA_HandleIRQ(s_EDMAHandle[31]);
+}
+#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */
+
+#endif /* 4/8/16/32 channels (No Shared)  */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_edma.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_edma.h
new file mode 100644
index 00000000000..02c4fabf723
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_edma.h
@@ -0,0 +1,880 @@
+/*
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _FSL_EDMA_H_
+#define _FSL_EDMA_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup edma
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief eDMA driver version */
+#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
+/*@}*/
+
+/*! @brief Compute the offset unit from DCHPRI3 */
+#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U)))
+
+/*! @brief Get the pointer of DCHPRIn */
+#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)]
+
+/*! @brief eDMA transfer configuration */
+typedef enum _edma_transfer_size
+{
+    kEDMA_TransferSize1Bytes = 0x0U,  /*!< Source/Destination data transfer size is 1 byte every time */
+    kEDMA_TransferSize2Bytes = 0x1U,  /*!< Source/Destination data transfer size is 2 bytes every time */
+    kEDMA_TransferSize4Bytes = 0x2U,  /*!< Source/Destination data transfer size is 4 bytes every time */
+    kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */
+    kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */
+} edma_transfer_size_t;
+
+/*! @brief eDMA modulo configuration */
+typedef enum _edma_modulo
+{
+    kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */
+    kEDMA_Modulo2bytes,         /*!< Circular buffer size is 2 bytes. */
+    kEDMA_Modulo4bytes,         /*!< Circular buffer size is 4 bytes. */
+    kEDMA_Modulo8bytes,         /*!< Circular buffer size is 8 bytes. */
+    kEDMA_Modulo16bytes,        /*!< Circular buffer size is 16 bytes. */
+    kEDMA_Modulo32bytes,        /*!< Circular buffer size is 32 bytes. */
+    kEDMA_Modulo64bytes,        /*!< Circular buffer size is 64 bytes. */
+    kEDMA_Modulo128bytes,       /*!< Circular buffer size is 128 bytes. */
+    kEDMA_Modulo256bytes,       /*!< Circular buffer size is 256 bytes. */
+    kEDMA_Modulo512bytes,       /*!< Circular buffer size is 512 bytes. */
+    kEDMA_Modulo1Kbytes,        /*!< Circular buffer size is 1K bytes. */
+    kEDMA_Modulo2Kbytes,        /*!< Circular buffer size is 2K bytes. */
+    kEDMA_Modulo4Kbytes,        /*!< Circular buffer size is 4K bytes. */
+    kEDMA_Modulo8Kbytes,        /*!< Circular buffer size is 8K bytes. */
+    kEDMA_Modulo16Kbytes,       /*!< Circular buffer size is 16K bytes. */
+    kEDMA_Modulo32Kbytes,       /*!< Circular buffer size is 32K bytes. */
+    kEDMA_Modulo64Kbytes,       /*!< Circular buffer size is 64K bytes. */
+    kEDMA_Modulo128Kbytes,      /*!< Circular buffer size is 128K bytes. */
+    kEDMA_Modulo256Kbytes,      /*!< Circular buffer size is 256K bytes. */
+    kEDMA_Modulo512Kbytes,      /*!< Circular buffer size is 512K bytes. */
+    kEDMA_Modulo1Mbytes,        /*!< Circular buffer size is 1M bytes. */
+    kEDMA_Modulo2Mbytes,        /*!< Circular buffer size is 2M bytes. */
+    kEDMA_Modulo4Mbytes,        /*!< Circular buffer size is 4M bytes. */
+    kEDMA_Modulo8Mbytes,        /*!< Circular buffer size is 8M bytes. */
+    kEDMA_Modulo16Mbytes,       /*!< Circular buffer size is 16M bytes. */
+    kEDMA_Modulo32Mbytes,       /*!< Circular buffer size is 32M bytes. */
+    kEDMA_Modulo64Mbytes,       /*!< Circular buffer size is 64M bytes. */
+    kEDMA_Modulo128Mbytes,      /*!< Circular buffer size is 128M bytes. */
+    kEDMA_Modulo256Mbytes,      /*!< Circular buffer size is 256M bytes. */
+    kEDMA_Modulo512Mbytes,      /*!< Circular buffer size is 512M bytes. */
+    kEDMA_Modulo1Gbytes,        /*!< Circular buffer size is 1G bytes. */
+    kEDMA_Modulo2Gbytes,        /*!< Circular buffer size is 2G bytes. */
+} edma_modulo_t;
+
+/*! @brief Bandwidth control */
+typedef enum _edma_bandwidth
+{
+    kEDMA_BandwidthStallNone = 0x0U,   /*!< No eDMA engine stalls. */
+    kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */
+    kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */
+} edma_bandwidth_t;
+
+/*! @brief Channel link type */
+typedef enum _edma_channel_link_type
+{
+    kEDMA_LinkNone = 0x0U, /*!< No channel link  */
+    kEDMA_MinorLink,       /*!< Channel link after each minor loop */
+    kEDMA_MajorLink,       /*!< Channel link while major loop count exhausted */
+} edma_channel_link_type_t;
+
+/*!@brief eDMA channel status flags. */
+enum _edma_channel_status_flags
+{
+    kEDMA_DoneFlag = 0x1U,      /*!< DONE flag, set while transfer finished, CITER value exhausted*/
+    kEDMA_ErrorFlag = 0x2U,     /*!< eDMA error flag, an error occurred in a transfer */
+    kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */
+};
+
+/*! @brief eDMA channel error status flags. */
+enum _edma_error_status_flags
+{
+    kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK,    /*!< Bus error on destination address */
+    kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK,         /*!< Bus error on the source address */
+    kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK,     /*!< Error on the Scatter/Gather address, not 32byte aligned. */
+    kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK,            /*!< NBYTES/CITER configuration error */
+    kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */
+    kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */
+    kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK,       /*!< Source offset not aligned with source size */
+    kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK,      /*!< Source address not aligned with source size*/
+    kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK,         /*!< Error channel number of the cancelled channel number */
+    kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK,    /*!< Channel priority is not unique. */
+    kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK,        /*!< Transfer cancelled */
+#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1
+    kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */
+#endif
+    kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
+};
+
+/*! @brief eDMA interrupt source */
+typedef enum _edma_interrupt_enable
+{
+    kEDMA_ErrorInterruptEnable = 0x1U,                  /*!< Enable interrupt while channel error occurs. */
+    kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */
+    kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK,   /*!< Enable interrupt while major count to half value. */
+} edma_interrupt_enable_t;
+
+/*! @brief eDMA transfer type */
+typedef enum _edma_transfer_type
+{
+    kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */
+    kEDMA_PeripheralToMemory,    /*!< Transfer from peripheral to memory */
+    kEDMA_MemoryToPeripheral,    /*!< Transfer from memory to peripheral */
+} edma_transfer_type_t;
+
+/*! @brief eDMA transfer status */
+enum _edma_transfer_status
+{
+    kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */
+    kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1),      /*!< Channel is busy and can't handle the
+                                                                     transfer request. */
+};
+
+/*! @brief eDMA global configuration structure.*/
+typedef struct _edma_config
+{
+    bool enableContinuousLinkMode;    /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel
+                                           activates again if that channel has a minor loop channel link enabled and
+                                           the link channel is itself. */
+    bool enableHaltOnError;           /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set.
+                                           Subsequently, all service requests are ignored until the HALT bit is cleared.*/
+    bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method, or fixed priority
+                                           arbitration is used for channel selection */
+    bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of
+                               a new channel. Executing channels are allowed to complete. */
+} edma_config_t;
+
+/*!
+ * @brief eDMA transfer configuration
+ *
+ * This structure configures the source/destination transfer attribute.
+ * This figure shows the eDMA's transfer model:
+ *  _________________________________________________
+ *              | Transfer Size |                    |
+ *   Minor Loop |_______________| Major loop Count 1 |
+ *     Bytes    | Transfer Size |                    |
+ *  ____________|_______________|____________________|--> Minor loop complete
+ *               ____________________________________
+ *              |               |                    |
+ *              |_______________| Major Loop Count 2 |
+ *              |               |                    |
+ *              |_______________|____________________|--> Minor loop  Complete
+ *
+ *               ---------------------------------------------------------> Transfer complete
+ */
+typedef struct _edma_transfer_config
+{
+    uint32_t srcAddr;                      /*!< Source data address. */
+    uint32_t destAddr;                     /*!< Destination data address. */
+    edma_transfer_size_t srcTransferSize;  /*!< Source data transfer size. */
+    edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */
+    int16_t srcOffset;                     /*!< Sign-extended offset applied to the current source address to
+                                                form the next-state value as each source read is completed. */
+    int16_t destOffset;                    /*!< Sign-extended offset applied to the current destination address to
+                                                form the next-state value as each destination write is completed. */
+    uint16_t minorLoopBytes;               /*!< Bytes to transfer in a minor loop*/
+    uint32_t majorLoopCounts;              /*!< Major loop iteration count. */
+} edma_transfer_config_t;
+
+/*! @brief eDMA channel priority configuration */
+typedef struct _edma_channel_Preemption_config
+{
+    bool enableChannelPreemption; /*!< If true: channel can be suspended by other channel with higher priority */
+    bool enablePreemptAbility;    /*!< If true: channel can suspend other channel with low priority */
+    uint8_t channelPriority;      /*!< Channel priority */
+} edma_channel_Preemption_config_t;
+
+/*! @brief eDMA minor offset configuration */
+typedef struct _edma_minor_offset_config
+{
+    bool enableSrcMinorOffset;  /*!< Enable(true) or Disable(false) source minor loop offset. */
+    bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */
+    uint32_t minorOffset;       /*!< Offset for minor loop mapping. */
+} edma_minor_offset_config_t;
+
+/*!
+ * @brief eDMA TCD.
+ *
+ * This structure is same as TCD register which is described in reference manual,
+ * and is used to configure the scatter/gather feature as a next hardware TCD.
+ */
+typedef struct _edma_tcd
+{
+    __IO uint32_t SADDR;     /*!< SADDR register, used to save source address */
+    __IO uint16_t SOFF;      /*!< SOFF register, save offset bytes every transfer */
+    __IO uint16_t ATTR;      /*!< ATTR register, source/destination transfer size and modulo */
+    __IO uint32_t NBYTES;    /*!< Nbytes register, minor loop length in bytes */
+    __IO uint32_t SLAST;     /*!< SLAST register */
+    __IO uint32_t DADDR;     /*!< DADDR register, used for destination address */
+    __IO uint16_t DOFF;      /*!< DOFF register, used for destination offset */
+    __IO uint16_t CITER;     /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/
+    __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */
+    __IO uint16_t CSR;       /*!< CSR register, for TCD control status */
+    __IO uint16_t BITER;     /*!< BITER register, begin minor loop count. */
+} edma_tcd_t;
+
+/*! @brief Callback for eDMA */
+struct _edma_handle;
+
+/*! @brief Define Callback function for eDMA. */
+typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds);
+
+/*! @brief eDMA transfer handle structure */
+typedef struct _edma_handle
+{
+    edma_callback callback;  /*!< Callback function for major count exhausted. */
+    void *userData;          /*!< Callback function parameter. */
+    DMA_Type *base;          /*!< eDMA peripheral base address. */
+    edma_tcd_t *tcdPool;     /*!< Pointer to memory stored TCDs. */
+    uint8_t channel;         /*!< eDMA channel number. */
+    volatile int8_t header;  /*!< The first TCD index. */
+    volatile int8_t tail;    /*!< The last TCD index. */
+    volatile int8_t tcdUsed; /*!< The number of used TCD slots. */
+    volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */
+    uint8_t flags;           /*!< The status of the current channel. */
+} edma_handle_t;
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name eDMA initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes eDMA peripheral.
+ *
+ * This function ungates the eDMA clock and configures the eDMA peripheral according
+ * to the configuration structure.
+ *
+ * @param base eDMA peripheral base address.
+ * @param config Pointer to configuration structure, see "edma_config_t".
+ * @note This function enable the minor loop map feature.
+ */
+void EDMA_Init(DMA_Type *base, const edma_config_t *config);
+
+/*!
+ * @brief Deinitializes eDMA peripheral.
+ *
+ * This function gates the eDMA clock.
+ *
+ * @param base eDMA peripheral base address.
+ */
+void EDMA_Deinit(DMA_Type *base);
+
+/*!
+ * @brief Gets the eDMA default configuration structure.
+ *
+ * This function sets the configuration structure to a default value.
+ * The default configuration is set to the following value:
+ * @code
+ *   config.enableContinuousLinkMode = false;
+ *   config.enableHaltOnError = true;
+ *   config.enableRoundRobinArbitration = false;
+ *   config.enableDebugMode = false;
+ * @endcode
+ *
+ * @param config Pointer to eDMA configuration structure.
+ */
+void EDMA_GetDefaultConfig(edma_config_t *config);
+
+/* @} */
+/*!
+ * @name eDMA Channel Operation
+ * @{
+ */
+
+/*!
+ * @brief Sets all TCD registers to a default value.
+ *
+ * This function sets TCD registers for this channel to default value.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @note This function must not be called while the channel transfer is on-going,
+ *       or it causes unpredictable results.
+ * @note This function enables the auto stop request feature.
+ */
+void EDMA_ResetChannel(DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Configures the eDMA transfer attribute.
+ *
+ * This function configures the transfer attribute, including source address, destination address,
+ * transfer size, address offset, and so on. It also configures the scatter gather feature if the
+ * user supplies the TCD address.
+ * Example:
+ * @code
+ *  edma_transfer_t config;
+ *  edma_tcd_t tcd;
+ *  config.srcAddr = ..;
+ *  config.destAddr = ..;
+ *  ...
+ *  EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);
+ * @endcode
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param config Pointer to eDMA transfer configuration structure.
+ * @param nextTcd Point to TCD structure. It can be NULL if users
+ *                do not want to enable scatter/gather feature.
+ * @note If nextTcd is not NULL, it means scatter gather feature is enabled
+ *       and DREQ bit is cleared in the previous transfer configuration, which
+ *       is set in eDMA_ResetChannel.
+ */
+void EDMA_SetTransferConfig(DMA_Type *base,
+                            uint32_t channel,
+                            const edma_transfer_config_t *config,
+                            edma_tcd_t *nextTcd);
+
+/*!
+ * @brief Configures the eDMA minor offset feature.
+ *
+ * Minor offset means signed-extended value added to source address or destination
+ * address after each minor loop.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param config Pointer to Minor offset configuration structure.
+ */
+void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config);
+
+/*!
+ * @brief Configures the eDMA channel preemption feature.
+ *
+ * This function configures the channel preemption attribute and the priority of the channel.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number
+ * @param config Pointer to channel preemption configuration structure.
+ */
+static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base,
+                                                   uint32_t channel,
+                                                   const edma_channel_Preemption_config_t *config)
+{
+    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(config != NULL);
+
+    DMA_DCHPRIn(base, channel) =
+        (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) |
+         DMA_DCHPRI0_CHPRI(config->channelPriority));
+}
+
+/*!
+ * @brief Sets the channel link for the eDMA transfer.
+ *
+ * This function configures  minor link or major link mode. The minor link means that the channel link is
+ * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
+ * exhausted.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param type Channel link type, it can be one of:
+ *   @arg kEDMA_LinkNone
+ *   @arg kEDMA_MinorLink
+ *   @arg kEDMA_MajorLink
+ * @param linkedChannel The linked channel number.
+ * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
+ */
+void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel);
+
+/*!
+ * @brief Sets the bandwidth for the eDMA transfer.
+ *
+ * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences
+ * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
+ * each read/write access to control the bus request bandwidth seen by the crossbar switch.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param bandWidth Bandwidth setting, it can be one of:
+ *     @arg kEDMABandwidthStallNone
+ *     @arg kEDMABandwidthStall4Cycle
+ *     @arg kEDMABandwidthStall8Cycle
+ */
+void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth);
+
+/*!
+ * @brief Sets the source modulo and destination modulo for eDMA transfer.
+ *
+ * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
+ * calculation is performed or the original register value. It provides the ability to implement a circular data
+ * queue easily.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param srcModulo Source modulo value.
+ * @param destModulo Destination modulo value.
+ */
+void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo);
+
+#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT
+/*!
+ * @brief Enables an async request for the eDMA transfer.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param enable The command for enable(ture) or disable(false).
+ */
+static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel);
+}
+#endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */
+
+/*!
+ * @brief Enables an auto stop request for the eDMA transfer.
+ *
+ * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param enable The command for enable (true) or disable (false).
+ */
+static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
+}
+
+/*!
+ * @brief Enables the interrupt source for the eDMA transfer.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param mask The mask of interrupt source to be set. Users need to use
+ *             the defined edma_interrupt_enable_t type.
+ */
+void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask);
+
+/*!
+ * @brief Disables the interrupt source for the eDMA transfer.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param mask The mask of interrupt source to be set. Use
+ *             the defined edma_interrupt_enable_t type.
+ */
+void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask);
+
+/* @} */
+/*!
+ * @name eDMA TCD Operation
+ * @{
+ */
+
+/*!
+ * @brief Sets all fields to default values for the TCD structure.
+ *
+ * This function sets all fields for this TCD structure to default value.
+ *
+ * @param tcd Pointer to the TCD structure.
+ * @note This function enables the auto stop request feature.
+ */
+void EDMA_TcdReset(edma_tcd_t *tcd);
+
+/*!
+ * @brief Configures the eDMA TCD transfer attribute.
+ *
+ * TCD is a transfer control descriptor. The content of the TCD is the same as hardware TCD registers.
+ * STCD is used in scatter-gather mode.
+ * This function configures the TCD transfer attribute, including source address, destination address,
+ * transfer size, address offset, and so on. It also configures the scatter gather feature if the
+ * user supplies the next TCD address.
+ * Example:
+ * @code
+ *   edma_transfer_t config = {
+ *   ...
+ *   }
+ *   edma_tcd_t tcd __aligned(32);
+ *   edma_tcd_t nextTcd __aligned(32);
+ *   EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);
+ * @endcode
+ *
+ * @param tcd Pointer to the TCD structure.
+ * @param config Pointer to eDMA transfer configuration structure.
+ * @param nextTcd Pointer to the next TCD structure. It can be NULL if users
+ *                do not want to enable scatter/gather feature.
+ * @note TCD address should be 32 bytes aligned, or it causes an eDMA error.
+ * @note If the nextTcd is not NULL, the scatter gather feature is enabled
+ *       and DREQ bit is cleared in the previous transfer configuration, which
+ *       is set in the EDMA_TcdReset.
+ */
+void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd);
+
+/*!
+ * @brief Configures the eDMA TCD minor offset feature.
+ *
+ * Minor offset is a signed-extended value added to the source address or destination
+ * address after each minor loop.
+ *
+ * @param tcd Point to the TCD structure.
+ * @param config Pointer to Minor offset configuration structure.
+ */
+void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config);
+
+/*!
+ * @brief Sets the channel link for eDMA TCD.
+ *
+ * This function configures either a minor link or a major link. The minor link means the channel link is
+ * triggered every time CITER decreases by 1. The major link means that the channel link  is triggered when the CITER is
+ * exhausted.
+ *
+ * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
+ * @param tcd Point to the TCD structure.
+ * @param type Channel link type, it can be one of:
+ *   @arg kEDMA_LinkNone
+ *   @arg kEDMA_MinorLink
+ *   @arg kEDMA_MajorLink
+ * @param linkedChannel The linked channel number.
+ */
+void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel);
+
+/*!
+ * @brief Sets the bandwidth for the eDMA TCD.
+ *
+ * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences
+ * until the minor count is exhausted. Bandwidth forces the eDMA to stall after the completion of
+ * each read/write access to control the bus request bandwidth seen by the crossbar switch.
+ * @param tcd Point to the TCD structure.
+ * @param bandWidth Bandwidth setting, it can be one of:
+ *     @arg kEDMABandwidthStallNone
+ *     @arg kEDMABandwidthStall4Cycle
+ *     @arg kEDMABandwidthStall8Cycle
+ */
+static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)
+{
+    assert(tcd != NULL);
+    assert(((uint32_t)tcd & 0x1FU) == 0);
+
+    tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
+}
+
+/*!
+ * @brief Sets the source modulo and destination modulo for eDMA TCD.
+ *
+ * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
+ * calculation is performed or the original register value. It provides the ability to implement a circular data
+ * queue easily.
+ *
+ * @param tcd Point to the TCD structure.
+ * @param srcModulo Source modulo value.
+ * @param destModulo Destination modulo value.
+ */
+void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo);
+
+/*!
+ * @brief Sets the auto stop request for the eDMA TCD.
+ *
+ * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
+ *
+ * @param tcd Point to the TCD structure.
+ * @param enable The command for enable(ture) or disable(false).
+ */
+static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)
+{
+    assert(tcd != NULL);
+    assert(((uint32_t)tcd & 0x1FU) == 0);
+
+    tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
+}
+
+/*!
+ * @brief Enables the interrupt source for the eDMA TCD.
+ *
+ * @param tcd Point to the TCD structure.
+ * @param mask The mask of interrupt source to be set. Users need to use
+ *             the defined edma_interrupt_enable_t type.
+ */
+void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask);
+
+/*!
+ * @brief Disables the interrupt source for the eDMA TCD.
+ *
+ * @param tcd Point to the TCD structure.
+ * @param mask The mask of interrupt source to be set. Users need to use
+ *             the defined edma_interrupt_enable_t type.
+ */
+void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask);
+
+/*! @} */
+/*!
+ * @name eDMA Channel Transfer Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the eDMA hardware channel request.
+ *
+ * This function enables the hardware channel request.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ */
+static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    base->SERQ = DMA_SERQ_SERQ(channel);
+}
+
+/*!
+ * @brief Disables the eDMA hardware channel request.
+ *
+ * This function disables the hardware channel request.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ */
+static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    base->CERQ = DMA_CERQ_CERQ(channel);
+}
+
+/*!
+ * @brief Starts the eDMA transfer by software trigger.
+ *
+ * This function starts a minor loop transfer.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ */
+static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    base->SSRT = DMA_SSRT_SSRT(channel);
+}
+
+/*! @} */
+/*!
+ * @name eDMA Channel Status Operation
+ * @{
+ */
+
+/*!
+ * @brief Gets the Remaining bytes from the eDMA current channel TCD.
+ *
+ * This function checks the TCD (Task Control Descriptor) status for a specified
+ * eDMA channel and returns the the number of bytes that have not finished.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @return Bytes have not been transferred yet for the current TCD.
+ * @note This function can only be used to get unfinished bytes of transfer without
+ *       the next TCD, or it might be inaccuracy.
+ */
+uint32_t EDMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Gets the eDMA channel error status flags.
+ *
+ * @param base eDMA peripheral base address.
+ * @return The mask of error status flags. Users need to use the
+ *         _edma_error_status_flags type to decode the return variables.
+ */
+static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base)
+{
+    return base->ES;
+}
+
+/*!
+ * @brief Gets the eDMA channel status flags.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @return The mask of channel status flags. Users need to use the
+ *         _edma_channel_status_flags type to decode the return variables.
+ */
+uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Clears the eDMA channel status flags.
+ *
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ * @param mask The mask of channel status to be cleared. Users need to use
+ *             the defined _edma_channel_status_flags type.
+ */
+void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask);
+
+/*! @} */
+/*!
+ * @name eDMA Transactional Operation
+ */
+
+/*!
+ * @brief Creates the eDMA handle.
+ *
+ * This function is called if using transaction API for eDMA. This function
+ * initializes the internal state of eDMA handle.
+ *
+ * @param handle eDMA handle pointer. The eDMA handle stores callback function and
+ *               parameters.
+ * @param base eDMA peripheral base address.
+ * @param channel eDMA channel number.
+ */
+void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Installs the TCDs memory pool into eDMA handle.
+ *
+ * This function is called after the EDMA_CreateHandle to use scatter/gather feature.
+ *
+ * @param handle eDMA handle pointer.
+ * @param tcdPool Memory pool to store TCDs. It must be 32 bytes aligned.
+ * @param tcdSize The number of TCD slots.
+ */
+void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize);
+
+/*!
+ * @brief Installs a callback function for the eDMA transfer.
+ *
+ * This callback is called in eDMA IRQ handler. Use the callback to do something after
+ * the current major loop transfer completes.
+ *
+ * @param handle eDMA handle pointer.
+ * @param callback eDMA callback function pointer.
+ * @param userData Parameter for callback function.
+ */
+void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData);
+
+/*!
+ * @brief Prepares the eDMA transfer structure.
+ *
+ * This function prepares the transfer configuration structure according to the user input.
+ *
+ * @param config The user configuration structure of type edma_transfer_t.
+ * @param srcAddr eDMA transfer source address.
+ * @param srcWidth eDMA transfer source address width(bytes).
+ * @param destAddr eDMA transfer destination address.
+ * @param destWidth eDMA transfer destination address width(bytes).
+ * @param bytesEachRequest eDMA transfer bytes per channel request.
+ * @param transferBytes eDMA transfer bytes to be transferred.
+ * @param type eDMA transfer type.
+ * @note The data address and the data width must be consistent. For example, if the SRC
+ *       is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
+ *       source address error(SAE).
+ */
+void EDMA_PrepareTransfer(edma_transfer_config_t *config,
+                          void *srcAddr,
+                          uint32_t srcWidth,
+                          void *destAddr,
+                          uint32_t destWidth,
+                          uint32_t bytesEachRequest,
+                          uint32_t transferBytes,
+                          edma_transfer_type_t type);
+
+/*!
+ * @brief Submits the eDMA transfer request.
+ *
+ * This function submits the eDMA transfer request according to the transfer configuration structure.
+ * If the user submits the transfer request repeatedly, this function packs an unprocessed request as
+ * a TCD and enables scatter/gather feature to process it in the next time.
+ *
+ * @param handle eDMA handle pointer.
+ * @param config Pointer to eDMA transfer configuration structure.
+ * @retval kStatus_EDMA_Success It means submit transfer request succeed.
+ * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
+ * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later.
+ */
+status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config);
+
+/*!
+ * @brief eDMA start transfer.
+ *
+ * This function enables the channel request. Users can call this function after submitting the transfer request
+ * or before submitting the transfer request.
+ *
+ * @param handle eDMA handle pointer.
+ */
+void EDMA_StartTransfer(edma_handle_t *handle);
+
+/*!
+ * @brief eDMA stop transfer.
+ *
+ * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer()
+ * again to resume the transfer.
+ *
+ * @param handle eDMA handle pointer.
+ */
+void EDMA_StopTransfer(edma_handle_t *handle);
+
+/*!
+ * @brief eDMA abort transfer.
+ *
+ * This function disables the channel request and clear transfer status bits.
+ * Users can submit another transfer after calling this API.
+ *
+ * @param handle DMA handle pointer.
+ */
+void EDMA_AbortTransfer(edma_handle_t *handle);
+
+/*!
+ * @brief eDMA IRQ handler for current major loop transfer complete.
+ *
+ * This function clears the channel major interrupt flag and call
+ * the callback function if it is not NULL.
+ *
+ * @param handle eDMA handle pointer.
+ */
+void EDMA_HandleIRQ(edma_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/* @} */
+
+#endif /*_FSL_EDMA_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ewm.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ewm.c
new file mode 100644
index 00000000000..1a71a07e582
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ewm.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_ewm.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void EWM_Init(EWM_Type *base, const ewm_config_t *config)
+{
+    assert(config);
+
+    uint32_t value = 0U;
+
+    CLOCK_EnableClock(kCLOCK_Ewm0);
+    value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) |
+            EWM_CTRL_INEN(config->enableEwmInput) | EWM_CTRL_INTEN(config->enableInterrupt);
+#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER
+    base->CLKPRESCALER = config->prescaler;
+#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */
+
+#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT
+    base->CLKCTRL = config->clockSource;
+#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/
+
+    base->CMPL = config->compareLowValue;
+    base->CMPH = config->compareHighValue;
+    base->CTRL = value;
+}
+
+void EWM_Deinit(EWM_Type *base)
+{
+    EWM_DisableInterrupts(base, kEWM_InterruptEnable);
+    CLOCK_DisableClock(kCLOCK_Ewm0);
+}
+
+void EWM_GetDefaultConfig(ewm_config_t *config)
+{
+    assert(config);
+
+    config->enableEwm = true;
+    config->enableEwmInput = false;
+    config->setInputAssertLogic = false;
+    config->enableInterrupt = false;
+#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT
+    config->clockSource = kEWM_LpoClockSource0;
+#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/
+#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER
+    config->prescaler = 0U;
+#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */
+    config->compareLowValue = 0U;
+    config->compareHighValue = 0xFEU;
+}
+
+void EWM_Refresh(EWM_Type *base)
+{
+    uint32_t primaskValue = 0U;
+
+    /* Disable the global interrupt to protect refresh sequence */
+    primaskValue = DisableGlobalIRQ();
+    base->SERV = (uint8_t)0xB4U;
+    base->SERV = (uint8_t)0x2CU;
+    EnableGlobalIRQ(primaskValue);
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ewm.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ewm.h
new file mode 100644
index 00000000000..180575e93f0
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ewm.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_EWM_H_
+#define _FSL_EWM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup ewm
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief EWM driver version 2.0.1. */
+#define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*! @brief Describes EWM clock source. */
+#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT
+typedef enum _ewm_lpo_clock_source
+{
+    kEWM_LpoClockSource0 = 0U, /*!< EWM clock sourced from lpo_clk[0]*/
+    kEWM_LpoClockSource1 = 1U, /*!< EWM clock sourced from lpo_clk[1]*/
+    kEWM_LpoClockSource2 = 2U, /*!< EWM clock sourced from lpo_clk[2]*/
+    kEWM_LpoClockSource3 = 3U, /*!< EWM clock sourced from lpo_clk[3]*/
+} ewm_lpo_clock_source_t;
+#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */
+
+/*!
+* @brief Data structure for EWM configuration.
+*
+* This structure is used to configure the EWM.
+*/
+typedef struct _ewm_config
+{
+    bool enableEwm;           /*!< Enable EWM module */
+    bool enableEwmInput;      /*!< Enable EWM_in input */
+    bool setInputAssertLogic; /*!< EWM_in signal assertion state */
+    bool enableInterrupt;     /*!< Enable EWM interrupt */
+#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT
+    ewm_lpo_clock_source_t clockSource; /*!< Clock source select */
+#endif                                  /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */
+#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER
+    uint8_t prescaler;        /*!< Clock prescaler value */
+#endif                        /* FSL_FEATURE_EWM_HAS_PRESCALER */
+    uint8_t compareLowValue;  /*!< Compare low-register value */
+    uint8_t compareHighValue; /*!< Compare high-register value */
+} ewm_config_t;
+
+/*!
+ * @brief EWM interrupt configuration structure, default settings all disabled.
+ *
+ * This structure contains the settings for all of the EWM interrupt configurations.
+ */
+enum _ewm_interrupt_enable_t
+{
+    kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable EWM to generate an interrupt*/
+};
+
+/*!
+ * @brief EWM status flags.
+ *
+ * This structure contains the constants for the EWM status flags for use in the EWM functions.
+ */
+enum _ewm_status_flags_t
+{
+    kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when EWM is enabled*/
+};
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name EWM Initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the EWM peripheral.
+ *
+ * This function is used to initialize the EWM. After calling, the EWM
+ * runs immediately according to the configuration.
+ * Note that except for interrupt enable control bit, other control bits and registers are write once after a
+ * CPU reset. Modifying them more than once generates a bus transfer error.
+ *
+ * Example:
+ * @code
+ *   ewm_config_t config;
+ *   EWM_GetDefaultConfig(&config);
+ *   config.compareHighValue = 0xAAU;
+ *   EWM_Init(ewm_base,&config);
+ * @endcode
+ *
+ * @param base EWM peripheral base address
+ * @param config The configuration of EWM
+*/
+void EWM_Init(EWM_Type *base, const ewm_config_t *config);
+
+/*!
+ * @brief Deinitializes the EWM peripheral.
+ *
+ * This function is used to shut down the EWM.
+ *
+ * @param base EWM peripheral base address
+*/
+void EWM_Deinit(EWM_Type *base);
+
+/*!
+ * @brief Initializes the EWM configuration structure.
+ *
+ * This function initializes the EWM configuration structure to default values. The default
+ * values are:
+ * @code
+ *   ewmConfig->enableEwm = true;
+ *   ewmConfig->enableEwmInput = false;
+ *   ewmConfig->setInputAssertLogic = false;
+ *   ewmConfig->enableInterrupt = false;
+ *   ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0;
+ *   ewmConfig->prescaler = 0;
+ *   ewmConfig->compareLowValue = 0;
+ *   ewmConfig->compareHighValue = 0xFEU;
+ * @endcode
+ *
+ * @param config Pointer to EWM configuration structure.
+ * @see ewm_config_t
+ */
+void EWM_GetDefaultConfig(ewm_config_t *config);
+
+/* @} */
+
+/*!
+ * @name EWM functional Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the EWM interrupt.
+ *
+ * This function enables the EWM interrupt.
+ *
+ * @param base EWM peripheral base address
+ * @param mask The interrupts to enable
+ *        The parameter can be combination of the following source if defined:
+ *        @arg kEWM_InterruptEnable
+ */
+static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask)
+{
+    base->CTRL |= mask;
+}
+
+/*!
+ * @brief Disables the EWM interrupt.
+ *
+ * This function enables the EWM interrupt.
+ *
+ * @param base EWM peripheral base address
+ * @param mask The interrupts to disable
+ *        The parameter can be combination of the following source if defined:
+ *        @arg kEWM_InterruptEnable
+ */
+static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask)
+{
+    base->CTRL &= ~mask;
+}
+
+/*!
+ * @brief Gets EWM all status flags.
+ *
+ * This function gets all status flags.
+ *
+ * Example for getting Running Flag:
+ * @code
+ *   uint32_t status;
+ *   status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag;
+ * @endcode
+ * @param base        EWM peripheral base address
+ * @return            State of the status flag: asserted (true) or not-asserted (false).@see _ewm_status_flags_t
+ *                    - true: a related status flag has been set.
+ *                    - false: a related status flag is not set.
+ */
+static inline uint32_t EWM_GetStatusFlags(EWM_Type *base)
+{
+    return (base->CTRL & EWM_CTRL_EWMEN_MASK);
+}
+
+/*!
+ * @brief Services the EWM.
+ *
+ * This function reset EWM counter to zero.
+ *
+ * @param base EWM peripheral base address
+*/
+void EWM_Refresh(EWM_Type *base);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_EWM_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flash.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flash.c
new file mode 100644
index 00000000000..9251c49d713
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flash.c
@@ -0,0 +1,2630 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flash.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @name Misc utility defines
+ * @{
+ */
+#ifndef ALIGN_DOWN
+#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a))))
+#endif
+#ifndef ALIGN_UP
+#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a))))))
+#endif
+
+#define BYTES_JOIN_TO_WORD_1_3(x, y) ((((uint32_t)(x)&0xFFU) << 24) | ((uint32_t)(y)&0xFFFFFFU))
+#define BYTES_JOIN_TO_WORD_2_2(x, y) ((((uint32_t)(x)&0xFFFFU) << 16) | ((uint32_t)(y)&0xFFFFU))
+#define BYTES_JOIN_TO_WORD_3_1(x, y) ((((uint32_t)(x)&0xFFFFFFU) << 8) | ((uint32_t)(y)&0xFFU))
+#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) \
+    ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | ((uint32_t)(z)&0xFFFFU))
+#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) \
+    ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFFFU) << 8) | ((uint32_t)(z)&0xFFU))
+#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) \
+    ((((uint32_t)(x)&0xFFFFU) << 16) | (((uint32_t)(y)&0xFFU) << 8) | ((uint32_t)(z)&0xFFU))
+#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w)                                                      \
+    ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | (((uint32_t)(z)&0xFFU) << 8) | \
+     ((uint32_t)(w)&0xFFU))
+/*@}*/
+
+/*! @brief Data flash IFR map Field*/
+#if defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE
+#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8003F8U
+#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */
+#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8000F8U
+#endif
+
+/*!
+ * @name Reserved FlexNVM size (For a variety of purposes) defines
+ * @{
+ */
+#define FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED 0xFFFFFFFFU
+#define FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED 0xFFFFU
+/*@}*/
+
+/*!
+ * @name Flash Program Once Field defines
+ * @{
+ */
+#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA
+/* FTFA parts(eg. K80, KL80, L5K) support both 4-bytes and 8-bytes unit size */
+#define FLASH_PROGRAM_ONCE_MIN_ID_8BYTES \
+    0x10U /* Minimum Index indcating one of Progam Once Fields which is accessed in 8-byte records */
+#define FLASH_PROGRAM_ONCE_MAX_ID_8BYTES \
+    0x13U /* Maximum Index indcating one of Progam Once Fields which is accessed in 8-byte records */
+#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1
+#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1
+#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE
+/* FTFE parts(eg. K65, KE18) only support 8-bytes unit size */
+#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 0
+#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1
+#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL
+/* FTFL parts(eg. K20) only support 4-bytes unit size */
+#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1
+#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 0
+#endif
+/*@}*/
+
+/*!
+ * @name Flash security status defines
+ * @{
+ */
+#define FLASH_SECURITY_STATE_KEYEN 0x80U
+#define FLASH_SECURITY_STATE_UNSECURED 0x02U
+#define FLASH_NOT_SECURE 0x01U
+#define FLASH_SECURE_BACKDOOR_ENABLED 0x02U
+#define FLASH_SECURE_BACKDOOR_DISABLED 0x04U
+/*@}*/
+
+/*!
+ * @name Flash controller command numbers
+ * @{
+ */
+#define FTFx_VERIFY_BLOCK 0x00U                    /*!< RD1BLK*/
+#define FTFx_VERIFY_SECTION 0x01U                  /*!< RD1SEC*/
+#define FTFx_PROGRAM_CHECK 0x02U                   /*!< PGMCHK*/
+#define FTFx_READ_RESOURCE 0x03U                   /*!< RDRSRC*/
+#define FTFx_PROGRAM_LONGWORD 0x06U                /*!< PGM4*/
+#define FTFx_PROGRAM_PHRASE 0x07U                  /*!< PGM8*/
+#define FTFx_ERASE_BLOCK 0x08U                     /*!< ERSBLK*/
+#define FTFx_ERASE_SECTOR 0x09U                    /*!< ERSSCR*/
+#define FTFx_PROGRAM_SECTION 0x0BU                 /*!< PGMSEC*/
+#define FTFx_VERIFY_ALL_BLOCK 0x40U                /*!< RD1ALL*/
+#define FTFx_READ_ONCE 0x41U                       /*!< RDONCE or RDINDEX*/
+#define FTFx_PROGRAM_ONCE 0x43U                    /*!< PGMONCE or PGMINDEX*/
+#define FTFx_ERASE_ALL_BLOCK 0x44U                 /*!< ERSALL*/
+#define FTFx_SECURITY_BY_PASS 0x45U                /*!< VFYKEY*/
+#define FTFx_SWAP_CONTROL 0x46U                    /*!< SWAP*/
+#define FTFx_ERASE_ALL_BLOCK_UNSECURE 0x49U        /*!< ERSALLU*/
+#define FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4AU /*!< RD1XA*/
+#define FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT 0x4BU  /*!< ERSXA*/
+#define FTFx_PROGRAM_PARTITION 0x80U               /*!< PGMPART)*/
+#define FTFx_SET_FLEXRAM_FUNCTION 0x81U            /*!< SETRAM*/
+                                                   /*@}*/
+
+/*!
+ * @name Common flash register info defines
+ * @{
+ */
+#if defined(FTFA)
+#define FTFx FTFA
+#define FTFx_BASE FTFA_BASE
+#define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK
+#define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK
+#define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK
+#define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK
+#define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK
+#define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK
+#define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM
+#define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+#define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+#elif defined(FTFE)
+#define FTFx FTFE
+#define FTFx_BASE FTFE_BASE
+#define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK
+#define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK
+#define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK
+#define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK
+#define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK
+#define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK
+#define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM
+#define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+#define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+#elif defined(FTFL)
+#define FTFx FTFL
+#define FTFx_BASE FTFL_BASE
+#define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK
+#define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK
+#define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK
+#define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK
+#define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK
+#define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK
+#define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM
+#define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */
+#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
+#define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK
+#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
+#else
+#error "Unknown flash controller"
+#endif
+/*@}*/
+
+/*!
+ * @brief Enumeration for access segment property.
+ */
+enum _flash_access_segment_property
+{
+    kFLASH_AccessSegmentBase = 256UL,
+};
+
+/*!
+ * @brief Enumeration for flash config area.
+ */
+enum _flash_config_area_range
+{
+    kFLASH_ConfigAreaStart = 0x400U,
+    kFLASH_ConfigAreaEnd = 0x40FU
+};
+
+/*! @brief Total flash region count*/
+#define FSL_FEATURE_FTFx_REGION_COUNT (32U)
+
+/*!
+ * @name Flash register access type defines
+ * @{
+ */
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+#define FTFx_REG_ACCESS_TYPE volatile uint8_t *
+#define FTFx_REG32_ACCESS_TYPE volatile uint32_t *
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+       /*@}*/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+/*! @brief Copy flash_run_command() to RAM*/
+static void copy_flash_run_command(uint32_t *flashRunCommand);
+/*! @brief Copy flash_cache_clear_command() to RAM*/
+static void copy_flash_cache_clear_command(uint32_t *flashCacheClearCommand);
+/*! @brief Check whether flash execute-in-ram functions are ready*/
+static status_t flash_check_execute_in_ram_function_info(flash_config_t *config);
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+/*! @brief Internal function Flash command sequence. Called by driver APIs only*/
+static status_t flash_command_sequence(flash_config_t *config);
+
+/*! @brief Perform the cache clear to the flash*/
+void flash_cache_clear(flash_config_t *config);
+
+/*! @brief Validates the range and alignment of the given address range.*/
+static status_t flash_check_range(flash_config_t *config,
+                                  uint32_t startAddress,
+                                  uint32_t lengthInBytes,
+                                  uint32_t alignmentBaseline);
+/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/
+static status_t flash_get_matched_operation_info(flash_config_t *config,
+                                                 uint32_t address,
+                                                 flash_operation_config_t *info);
+/*! @brief Validates the given user key for flash erase APIs.*/
+static status_t flash_check_user_key(uint32_t key);
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/
+static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config);
+#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+/*! @brief Validates the range of the given resource address.*/
+static status_t flash_check_resource_range(uint32_t start,
+                                           uint32_t lengthInBytes,
+                                           uint32_t alignmentBaseline,
+                                           flash_read_resource_option_t option);
+#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+/*! @brief Validates the gived swap control option.*/
+static status_t flash_check_swap_control_option(flash_swap_control_option_t option);
+#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+
+#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/
+static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address);
+#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+/*! @brief Validates the gived flexram function option.*/
+static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option);
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Access to FTFx->FCCOB */
+#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA
+volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFA->FCCOB3;
+#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE
+volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFE->FCCOB3;
+#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL
+volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFL->FCCOB3;
+#else
+#error "Unknown flash controller"
+#endif
+
+/*! @brief Access to FTFx->FPROT */
+#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA
+volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFA->FPROT3;
+#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE
+volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFE->FPROT3;
+#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL
+volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFL->FPROT3;
+#else
+#error "Unknown flash controller"
+#endif
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+/*! @brief A function pointer used to point to relocated flash_run_command() */
+static void (*callFlashRunCommand)(FTFx_REG_ACCESS_TYPE ftfx_fstat);
+/*! @brief A function pointer used to point to relocated flash_cache_clear_command() */
+static void (*callFlashCacheClearCommand)(FTFx_REG32_ACCESS_TYPE ftfx_reg);
+
+/*!
+ * @brief Position independent code of flash_run_command()
+ *
+ * Note1: The prototype of C function is shown as below:
+ * @code
+ *   void flash_run_command(FTFx_REG_ACCESS_TYPE ftfx_fstat)
+ *   {
+ *       // clear CCIF bit
+ *       *ftfx_fstat = FTFx_FSTAT_CCIF_MASK;
+ *
+ *       // Check CCIF bit of the flash status register, wait till it is set.
+ *       // IP team indicates that this loop will always complete.
+ *       while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK))
+ *       {
+ *       }
+ *   }
+ * @endcode
+ * Note2: The binary code is generated by IAR 7.50.1
+ */
+const static uint16_t s_flashRunCommandFunctionCode[] = {
+    0x2180, /* MOVS  R1, #128 ; 0x80 */
+    0x7001, /* STRB  R1, [R0] */
+    /* @4: */
+    0x7802, /* LDRB  R2, [R0] */
+    0x420a, /* TST   R2, R1 */
+    0xd0fc, /* BEQ.N @4 */
+    0x4770  /* BX    LR */
+};
+
+/*!
+ * @brief Position independent code of flash_cache_clear_command()
+ *
+ * Note1: The prototype of C function is shown as below:
+ * @code
+ *   void flash_cache_clear_command(FTFx_REG32_ACCESS_TYPE ftfx_reg)
+ *   {
+ *   #if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS
+ *       *ftfx_reg |= MCM_PLACR_CFCC_MASK;
+ *   #elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS
+ *   #if defined(FMC_PFB01CR_CINV_WAY_MASK)
+ *       *ftfx_reg = (*ftfx_reg & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0);
+ *   #else
+ *       *ftfx_reg = (*ftfx_reg & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0);
+ *   #endif
+ *   #elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS
+ *       *ftfx_reg |= MSCM_OCMDR_OCMC1(2);
+ *       *ftfx_reg |= MSCM_OCMDR_OCMC1(1);
+ *   #else
+ *   #if defined(FMC_PFB0CR_S_INV_MASK)
+ *       *ftfx_reg |= FMC_PFB0CR_S_INV_MASK;
+ *   #elif defined(FMC_PFB01CR_S_INV_MASK)
+ *       *ftfx_reg |= FMC_PFB01CR_S_INV_MASK;
+ *   #endif
+ *   //    #error "Unknown flash cache controller"
+ *   #endif // FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS
+ *       // Memory barriers for good measure.
+ *       // All Cache, Branch predictor and TLB maintenance operations before this instruction complete
+ *       __ISB();
+ *       __DSB();
+ *   }
+ * @endcode
+ * Note2: The binary code is generated by IAR 7.50.1
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS
+const static uint16_t s_flashCacheClearCommandFunctionCode[] = {
+    0x6801,         /* LDR  R1, [R0] */
+    0x2280,         /* MOVS R2, #128   ; 0x80 */
+    0x00d2,         /* LSLS R2, R2, #3 */
+    0x430a,         /* ORRS R2, R2, R1 */
+    0x6002,         /* STR  R2, [R0] */
+    0xf3bf, 0x8f6f, /* ISB */
+    0xf3bf, 0x8f4f, /* DSB */
+    0x4770          /* BX   LR */
+};
+#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS
+const static uint16_t s_flashCacheClearCommandFunctionCode[] = {
+    0x6801,         /* LDR  R1, [R0] */
+    0x22f0,         /* MOVS R2, #240    ; 0xf0 */
+    0x0412,         /* LSLS R2, R2, #16 */
+    0x430a,         /* ORRS R2, R2, R1 */
+    0x6002,         /* STR  R2, [R0] */
+    0xf3bf, 0x8f6f, /* ISB */
+    0xf3bf, 0x8f4f, /* DSB */
+    0x4770          /* BX   LR */
+};
+#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS
+const static uint16_t s_flashCacheClearCommandFunctionCode[] = {
+    0x6801,         /* LDR  R1, [R0] */
+    0x2220,         /* MOVS R2, #32    ; 0x20 */
+    0x430a,         /* ORRS R2, R2, R1 */
+    0x6002,         /* STR  R2, [R0] */
+    0x6801,         /* LDR  R1, [R0] */
+    0x2210,         /* MOVS R2, #16    ; 0x10 */
+    0x430a,         /* ORRS R2, R2, R1 */
+    0x6002,         /* STR  R2, [R0] */
+    0xf3bf, 0x8f6f, /* ISB */
+    0xf3bf, 0x8f4f, /* DSB */
+    0x4770          /* BX   LR */
+};
+#else
+#if defined(FMC_PFB0CR_S_INV_MASK) || defined(FMC_PFB01CR_S_INV_MASK)
+const static uint16_t s_flashCacheClearCommandFunctionCode[] = {
+    0x6801,         /* LDR  R1, [R0]  */
+    0x2280,         /* MOVS R2, #128    ; 0x80 */
+    0x0312,         /* LSLS R2, R2, #12 */
+    0x430a,         /* ORRS R2, R2, R1 */
+    0x6002,         /* STR  R2, [R0] */
+    0xf3bf, 0x8f6f, /* ISB */
+    0xf3bf, 0x8f4f, /* DSB */
+    0x4770          /* BX   LR */
+};
+#else
+const static uint16_t s_flashCacheClearCommandFunctionCode[] = {
+    0xf3bf, 0x8f6f, /* ISB */
+    0xf3bf, 0x8f4f, /* DSB */
+    0x4770          /* BX   LR */
+};
+#endif
+#endif
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED)
+/*! @brief A static buffer used to hold flash_run_command() */
+static uint32_t s_flashRunCommand[kFLASH_ExecuteInRamFunctionMaxSizeInWords];
+/*! @brief A static buffer used to hold flash_cache_clear_command() */
+static uint32_t s_flashCacheClearCommand[kFLASH_ExecuteInRamFunctionMaxSizeInWords];
+/*! @brief Flash execute-in-ram function information */
+static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo;
+#endif
+
+/*!
+ * @brief Table of pflash sizes.
+ *
+ *  The index into this table is the value of the SIM_FCFG1.PFSIZE bitfield.
+ *
+ *  The values in this table have been right shifted 10 bits so that they will all fit within
+ *  an 16-bit integer. To get the actual flash density, you must left shift the looked up value
+ *  by 10 bits.
+ *
+ *  Elements of this table have a value of 0 in cases where the PFSIZE bitfield value is
+ *  reserved.
+ *
+ *  Code to use the table:
+ *  @code
+ *      uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT;
+ *      flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10;
+ *  @endcode
+ */
+const uint16_t kPFlashDensities[] = {
+    8,    /* 0x0 - 8192, 8KB */
+    16,   /* 0x1 - 16384, 16KB */
+    24,   /* 0x2 - 24576, 24KB */
+    32,   /* 0x3 - 32768, 32KB */
+    48,   /* 0x4 - 49152, 48KB */
+    64,   /* 0x5 - 65536, 64KB */
+    96,   /* 0x6 - 98304, 96KB */
+    128,  /* 0x7 - 131072, 128KB */
+    192,  /* 0x8 - 196608, 192KB */
+    256,  /* 0x9 - 262144, 256KB */
+    384,  /* 0xa - 393216, 384KB */
+    512,  /* 0xb - 524288, 512KB */
+    768,  /* 0xc - 786432, 768KB */
+    1024, /* 0xd - 1048576, 1MB */
+    1536, /* 0xe - 1572864, 1.5MB */
+    /* 2048,  0xf - 2097152, 2MB */
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+status_t FLASH_Init(flash_config_t *config)
+{
+    uint32_t flashDensity;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* calculate the flash density from SIM_FCFG1.PFSIZE */
+    uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT;
+    /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed.
+     * We just use the pre-defined flash size in feature file here to support pre-production parts */
+    if (pfsize == 0xf)
+    {
+        flashDensity = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE;
+    }
+    else
+    {
+        flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10;
+    }
+
+    /* fill out a few of the structure members */
+    config->PFlashBlockBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS;
+    config->PFlashTotalSize = flashDensity;
+    config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT;
+    config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE;
+
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+    config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSS;
+    config->PFlashAccessSegmentCount = FTFx->FACSN;
+#else
+    config->PFlashAccessSegmentSize = 0;
+    config->PFlashAccessSegmentCount = 0;
+#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+
+    config->PFlashCallback = NULL;
+
+/* copy required flash commands to RAM */
+#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED)
+    if (kStatus_FLASH_Success != flash_check_execute_in_ram_function_info(config))
+    {
+        s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0;
+        s_flashExecuteInRamFunctionInfo.flashRunCommand = s_flashRunCommand;
+        s_flashExecuteInRamFunctionInfo.flashCacheClearCommand = s_flashCacheClearCommand;
+        config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount;
+        FLASH_PrepareExecuteInRamFunctions(config);
+    }
+#endif
+
+    config->FlexRAMBlockBase = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS;
+    config->FlexRAMTotalSize = FSL_FEATURE_FLASH_FLEX_RAM_SIZE;
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+    {
+        status_t returnCode;
+        config->DFlashBlockBase = FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS;
+        returnCode = flash_update_flexnvm_memory_partition_status(config);
+        if (returnCode != kStatus_FLASH_Success)
+        {
+            return returnCode;
+        }
+    }
+#endif
+
+    return kStatus_FLASH_Success;
+}
+
+status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback)
+{
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    config->PFlashCallback = callback;
+
+    return kStatus_FLASH_Success;
+}
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config)
+{
+    flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo;
+
+    copy_flash_run_command(flashExecuteInRamFunctionInfo->flashRunCommand);
+    copy_flash_cache_clear_command(flashExecuteInRamFunctionInfo->flashCacheClearCommand);
+    flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_ExecuteInRamFunctionTotalNum;
+
+    return kStatus_FLASH_Success;
+}
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+status_t FLASH_EraseAll(flash_config_t *config, uint32_t key)
+{
+    status_t returnCode;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* preparing passing parameter to erase all flash blocks */
+    kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK, 0xFFFFFFU);
+
+    /* Validate the user key */
+    returnCode = flash_check_user_key(key);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
+    /* calling flash command sequence function to execute the command */
+    returnCode = flash_command_sequence(config);
+
+    flash_cache_clear(config);
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+    /* Data flash IFR will be erased by erase all command, so we need to
+     *  update FlexNVM memory partition status synchronously */
+    if (returnCode == kStatus_FLASH_Success)
+    {
+        returnCode = flash_update_flexnvm_memory_partition_status(config);
+    }
+#endif
+
+    return returnCode;
+}
+
+status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key)
+{
+    uint32_t sectorSize;
+    flash_operation_config_t flashInfo;
+    uint32_t endAddress;      /* storing end address */
+    uint32_t numberOfSectors; /* number of sectors calculated by endAddress */
+    status_t returnCode;
+
+    flash_get_matched_operation_info(config, start, &flashInfo);
+
+    /* Check the supplied address range. */
+    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectorCmdAddressAligment);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
+    start = flashInfo.convertedAddress;
+    sectorSize = flashInfo.activeSectorSize;
+
+    /* calculating Flash end address */
+    endAddress = start + lengthInBytes - 1;
+
+    /* re-calculate the endAddress and align it to the start of the next sector
+     * which will be used in the comparison below */
+    if (endAddress % sectorSize)
+    {
+        numberOfSectors = endAddress / sectorSize + 1;
+        endAddress = numberOfSectors * sectorSize - 1;
+    }
+
+    /* the start address will increment to the next sector address
+     * until it reaches the endAdddress */
+    while (start <= endAddress)
+    {
+        /* preparing passing parameter to erase a flash block */
+        kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_SECTOR, start);
+
+        /* Validate the user key */
+        returnCode = flash_check_user_key(key);
+        if (returnCode)
+        {
+            return returnCode;
+        }
+
+        /* calling flash command sequence function to execute the command */
+        returnCode = flash_command_sequence(config);
+
+        /* calling flash callback function if it is available */
+        if (config->PFlashCallback)
+        {
+            config->PFlashCallback();
+        }
+
+        /* checking the success of command execution */
+        if (kStatus_FLASH_Success != returnCode)
+        {
+            break;
+        }
+        else
+        {
+            /* Increment to the next sector */
+            start += sectorSize;
+        }
+    }
+
+    flash_cache_clear(config);
+
+    return (returnCode);
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD
+status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key)
+{
+    status_t returnCode;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* Prepare passing parameter to erase all flash blocks (unsecure). */
+    kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK_UNSECURE, 0xFFFFFFU);
+
+    /* Validate the user key */
+    returnCode = flash_check_user_key(key);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
+    /* calling flash command sequence function to execute the command */
+    returnCode = flash_command_sequence(config);
+
+    flash_cache_clear(config);
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+    /* Data flash IFR will be erased by erase all unsecure command, so we need to
+     *  update FlexNVM memory partition status synchronously */
+    if (returnCode == kStatus_FLASH_Success)
+    {
+        returnCode = flash_update_flexnvm_memory_partition_status(config);
+    }
+#endif
+
+    return returnCode;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */
+
+status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key)
+{
+    status_t returnCode;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* preparing passing parameter to erase all execute-only segments
+     * 1st element for the FCCOB register */
+    kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT, 0xFFFFFFU);
+
+    /* Validate the user key */
+    returnCode = flash_check_user_key(key);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
+    /* calling flash command sequence function to execute the command */
+    returnCode = flash_command_sequence(config);
+
+    flash_cache_clear(config);
+
+    return returnCode;
+}
+
+status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+    flash_operation_config_t flashInfo;
+
+    if (src == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    flash_get_matched_operation_info(config, start, &flashInfo);
+
+    /* Check the supplied address range. */
+    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.blockWriteUnitSize);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
+    start = flashInfo.convertedAddress;
+
+    while (lengthInBytes > 0)
+    {
+        /* preparing passing parameter to program the flash block */
+        kFCCOBx[1] = *src++;
+        if (4 == flashInfo.blockWriteUnitSize)
+        {
+            kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_LONGWORD, start);
+        }
+        else if (8 == flashInfo.blockWriteUnitSize)
+        {
+            kFCCOBx[2] = *src++;
+            kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_PHRASE, start);
+        }
+        else
+        {
+        }
+
+        /* calling flash command sequence function to execute the command */
+        returnCode = flash_command_sequence(config);
+
+        /* calling flash callback function if it is available */
+        if (config->PFlashCallback)
+        {
+            config->PFlashCallback();
+        }
+
+        /* checking for the success of command execution */
+        if (kStatus_FLASH_Success != returnCode)
+        {
+            break;
+        }
+        else
+        {
+            /* update start address for next iteration */
+            start += flashInfo.blockWriteUnitSize;
+
+            /* update lengthInBytes for next iteration */
+            lengthInBytes -= flashInfo.blockWriteUnitSize;
+        }
+    }
+
+    flash_cache_clear(config);
+
+    return (returnCode);
+}
+
+status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+
+    if ((config == NULL) || (src == NULL))
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* pass paramters to FTFx */
+    kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_PROGRAM_ONCE, index, 0xFFFFU);
+
+    kFCCOBx[1] = *src;
+
+/* Note: Have to seperate the first index from the rest if it equals 0
+ * to avoid a pointless comparison of unsigned int to 0 compiler warning */
+#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT
+#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT
+    if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) ||
+         /* Range check */
+         ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) &&
+        (lengthInBytes == 8))
+#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */
+    {
+        kFCCOBx[2] = *(src + 1);
+    }
+#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */
+
+    /* calling flash command sequence function to execute the command */
+    returnCode = flash_command_sequence(config);
+
+    flash_cache_clear(config);
+
+    return returnCode;
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD
+status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+    uint32_t sectorSize;
+    flash_operation_config_t flashInfo;
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+    bool needSwitchFlexRamMode = false;
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+    if (src == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    flash_get_matched_operation_info(config, start, &flashInfo);
+
+    /* Check the supplied address range. */
+    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
+    start = flashInfo.convertedAddress;
+    sectorSize = flashInfo.activeSectorSize;
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+    /* Switch function of FlexRAM if needed */
+    if (!(FTFx->FCNFG & FTFx_FCNFG_RAMRDY_MASK))
+    {
+        needSwitchFlexRamMode = true;
+
+        returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam);
+        if (returnCode != kStatus_FLASH_Success)
+        {
+            return kStatus_FLASH_SetFlexramAsRamError;
+        }
+    }
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+    while (lengthInBytes > 0)
+    {
+        /* Make sure the write operation doesn't span two sectors */
+        uint32_t endAddressOfCurrentSector = ALIGN_UP(start, sectorSize);
+        uint32_t lengthTobeProgrammedOfCurrentSector;
+        uint32_t currentOffset = 0;
+
+        if (endAddressOfCurrentSector == start)
+        {
+            endAddressOfCurrentSector += sectorSize;
+        }
+
+        if (lengthInBytes + start > endAddressOfCurrentSector)
+        {
+            lengthTobeProgrammedOfCurrentSector = endAddressOfCurrentSector - start;
+        }
+        else
+        {
+            lengthTobeProgrammedOfCurrentSector = lengthInBytes;
+        }
+
+        /* Program Current Sector */
+        while (lengthTobeProgrammedOfCurrentSector > 0)
+        {
+            /* Make sure the program size doesn't exceeds Acceleration RAM size */
+            uint32_t programSizeOfCurrentPass;
+            uint32_t numberOfPhases;
+
+            if (lengthTobeProgrammedOfCurrentSector > kFLASH_AccelerationRamSize)
+            {
+                programSizeOfCurrentPass = kFLASH_AccelerationRamSize;
+            }
+            else
+            {
+                programSizeOfCurrentPass = lengthTobeProgrammedOfCurrentSector;
+            }
+
+            /* Copy data to FlexRAM */
+            memcpy((void *)FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS, src + currentOffset / 4, programSizeOfCurrentPass);
+            /* Set start address of the data to be programmed */
+            kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset);
+            /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */
+            numberOfPhases = programSizeOfCurrentPass / flashInfo.sectionCmdAddressAligment;
+
+            kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_2(numberOfPhases, 0xFFFFU);
+
+            /* Peform command sequence */
+            returnCode = flash_command_sequence(config);
+
+            /* calling flash callback function if it is available */
+            if (config->PFlashCallback)
+            {
+                config->PFlashCallback();
+            }
+
+            if (returnCode != kStatus_FLASH_Success)
+            {
+                flash_cache_clear(config);
+                return returnCode;
+            }
+
+            lengthTobeProgrammedOfCurrentSector -= programSizeOfCurrentPass;
+            currentOffset += programSizeOfCurrentPass;
+        }
+
+        src += currentOffset / 4;
+        start += currentOffset;
+        lengthInBytes -= currentOffset;
+    }
+
+    flash_cache_clear(config);
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+    /* Restore function of FlexRAM if needed. */
+    if (needSwitchFlexRamMode)
+    {
+        returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom);
+        if (returnCode != kStatus_FLASH_Success)
+        {
+            return kStatus_FLASH_RecoverFlexramAsEepromError;
+        }
+    }
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+    return returnCode;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+    bool needSwitchFlexRamMode = false;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* Validates the range of the given address */
+    if ((start < config->FlexRAMBlockBase) ||
+        ((start + lengthInBytes) > (config->FlexRAMBlockBase + config->EEpromTotalSize)))
+    {
+        return kStatus_FLASH_AddressError;
+    }
+
+    returnCode = kStatus_FLASH_Success;
+
+    /* Switch function of FlexRAM if needed */
+    if (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK))
+    {
+        needSwitchFlexRamMode = true;
+
+        returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom);
+        if (returnCode != kStatus_FLASH_Success)
+        {
+            return kStatus_FLASH_SetFlexramAsEepromError;
+        }
+    }
+
+    /* Write data to FlexRAM when it is used as EEPROM emulator */
+    while (lengthInBytes > 0)
+    {
+        if ((!(start & 0x3U)) && (lengthInBytes >= 4))
+        {
+            *(uint32_t *)start = *(uint32_t *)src;
+            start += 4;
+            src += 4;
+            lengthInBytes -= 4;
+        }
+        else if ((!(start & 0x1U)) && (lengthInBytes >= 2))
+        {
+            *(uint16_t *)start = *(uint16_t *)src;
+            start += 2;
+            src += 2;
+            lengthInBytes -= 2;
+        }
+        else
+        {
+            *(uint8_t *)start = *src;
+            start += 1;
+            src += 1;
+            lengthInBytes -= 1;
+        }
+        /* Wait till EEERDY bit is set */
+        while (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK))
+        {
+        }
+
+        /* Check for protection violation error */
+        if (FTFx->FSTAT & FTFx_FSTAT_FPVIOL_MASK)
+        {
+            return kStatus_FLASH_ProtectionViolation;
+        }
+    }
+
+    /* Switch function of FlexRAM if needed */
+    if (needSwitchFlexRamMode)
+    {
+        returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam);
+        if (returnCode != kStatus_FLASH_Success)
+        {
+            return kStatus_FLASH_RecoverFlexramAsRamError;
+        }
+    }
+
+    return returnCode;
+}
+#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+status_t FLASH_ReadResource(
+    flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option)
+{
+    status_t returnCode;
+    flash_operation_config_t flashInfo;
+
+    if ((config == NULL) || (dst == NULL))
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    flash_get_matched_operation_info(config, start, &flashInfo);
+
+    /* Check the supplied address range. */
+    returnCode = flash_check_resource_range(start, lengthInBytes, flashInfo.resourceCmdAddressAligment, option);
+    if (returnCode != kStatus_FLASH_Success)
+    {
+        return returnCode;
+    }
+
+    while (lengthInBytes > 0)
+    {
+        /* preparing passing parameter */
+        kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_READ_RESOURCE, start);
+        if (flashInfo.resourceCmdAddressAligment == 4)
+        {
+            kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU);
+        }
+        else if (flashInfo.resourceCmdAddressAligment == 8)
+        {
+            kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU);
+        }
+        else
+        {
+        }
+
+        /* calling flash command sequence function to execute the command */
+        returnCode = flash_command_sequence(config);
+
+        if (kStatus_FLASH_Success != returnCode)
+        {
+            break;
+        }
+
+        /* fetch data */
+        *dst++ = kFCCOBx[1];
+        if (flashInfo.resourceCmdAddressAligment == 8)
+        {
+            *dst++ = kFCCOBx[2];
+        }
+        /* update start address for next iteration */
+        start += flashInfo.resourceCmdAddressAligment;
+        /* update lengthInBytes for next iteration */
+        lengthInBytes -= flashInfo.resourceCmdAddressAligment;
+    }
+
+    return (returnCode);
+}
+#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+
+status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes)
+{
+    status_t returnCode;
+
+    if ((config == NULL) || (dst == NULL))
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* pass paramters to FTFx */
+    kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_READ_ONCE, index, 0xFFFFU);
+
+    /* calling flash command sequence function to execute the command */
+    returnCode = flash_command_sequence(config);
+
+    if (kStatus_FLASH_Success == returnCode)
+    {
+        *dst = kFCCOBx[1];
+/* Note: Have to seperate the first index from the rest if it equals 0
+ *       to avoid a pointless comparison of unsigned int to 0 compiler warning */
+#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT
+#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT
+        if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) ||
+             /* Range check */
+             ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) &&
+            (lengthInBytes == 8))
+#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */
+        {
+            *(dst + 1) = kFCCOBx[2];
+        }
+#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */
+    }
+
+    return returnCode;
+}
+
+status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state)
+{
+    /* store data read from flash register */
+    uint8_t registerValue;
+
+    if ((config == NULL) || (state == NULL))
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* Get flash security register value */
+    registerValue = FTFx->FSEC;
+
+    /* check the status of the flash security bits in the security register */
+    if (FLASH_SECURITY_STATE_UNSECURED == (registerValue & FTFx_FSEC_SEC_MASK))
+    {
+        /* Flash in unsecured state */
+        *state = kFLASH_SecurityStateNotSecure;
+    }
+    else
+    {
+        /* Flash in secured state
+         * check for backdoor key security enable bit */
+        if (FLASH_SECURITY_STATE_KEYEN == (registerValue & FTFx_FSEC_KEYEN_MASK))
+        {
+            /* Backdoor key security enabled */
+            *state = kFLASH_SecurityStateBackdoorEnabled;
+        }
+        else
+        {
+            /* Backdoor key security disabled */
+            *state = kFLASH_SecurityStateBackdoorDisabled;
+        }
+    }
+
+    return (kStatus_FLASH_Success);
+}
+
+status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey)
+{
+    uint8_t registerValue; /* registerValue */
+    status_t returnCode;   /* return code variable */
+
+    if ((config == NULL) || (backdoorKey == NULL))
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* set the default return code as kStatus_Success */
+    returnCode = kStatus_FLASH_Success;
+
+    /* Get flash security register value */
+    registerValue = FTFx->FSEC;
+
+    /* Check to see if flash is in secure state (any state other than 0x2)
+     * If not, then skip this since flash is not secure */
+    if (0x02 != (registerValue & 0x03))
+    {
+        /* preparing passing parameter to erase a flash block */
+        kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SECURITY_BY_PASS, 0xFFFFFFU);
+        kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[0], backdoorKey[1], backdoorKey[2], backdoorKey[3]);
+        kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[4], backdoorKey[5], backdoorKey[6], backdoorKey[7]);
+
+        /* calling flash command sequence function to execute the command */
+        returnCode = flash_command_sequence(config);
+    }
+
+    return (returnCode);
+}
+
+status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin)
+{
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* preparing passing parameter to verify all block command */
+    kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_BLOCK, margin, 0xFFFFU);
+
+    /* calling flash command sequence function to execute the command */
+    return flash_command_sequence(config);
+}
+
+status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin)
+{
+    /* Check arguments. */
+    uint32_t blockSize;
+    flash_operation_config_t flashInfo;
+    uint32_t nextBlockStartAddress;
+    uint32_t remainingBytes;
+    status_t returnCode;
+
+    flash_get_matched_operation_info(config, start, &flashInfo);
+
+    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
+    flash_get_matched_operation_info(config, start, &flashInfo);
+    start = flashInfo.convertedAddress;
+    blockSize = flashInfo.activeBlockSize;
+
+    nextBlockStartAddress = ALIGN_UP(start, blockSize);
+    if (nextBlockStartAddress == start)
+    {
+        nextBlockStartAddress += blockSize;
+    }
+
+    remainingBytes = lengthInBytes;
+
+    while (remainingBytes)
+    {
+        uint32_t numberOfPhrases;
+        uint32_t verifyLength = nextBlockStartAddress - start;
+        if (verifyLength > remainingBytes)
+        {
+            verifyLength = remainingBytes;
+        }
+
+        numberOfPhrases = verifyLength / flashInfo.sectionCmdAddressAligment;
+
+        /* Fill in verify section command parameters. */
+        kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_VERIFY_SECTION, start);
+        kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_1_1(numberOfPhrases, margin, 0xFFU);
+
+        /* calling flash command sequence function to execute the command */
+        returnCode = flash_command_sequence(config);
+        if (returnCode)
+        {
+            return returnCode;
+        }
+
+        remainingBytes -= verifyLength;
+        start += verifyLength;
+        nextBlockStartAddress += blockSize;
+    }
+
+    return kStatus_FLASH_Success;
+}
+
+status_t FLASH_VerifyProgram(flash_config_t *config,
+                             uint32_t start,
+                             uint32_t lengthInBytes,
+                             const uint32_t *expectedData,
+                             flash_margin_value_t margin,
+                             uint32_t *failedAddress,
+                             uint32_t *failedData)
+{
+    status_t returnCode;
+    flash_operation_config_t flashInfo;
+
+    if (expectedData == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    flash_get_matched_operation_info(config, start, &flashInfo);
+
+    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.checkCmdAddressAligment);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
+    start = flashInfo.convertedAddress;
+
+    while (lengthInBytes)
+    {
+        /* preparing passing parameter to program check the flash block */
+        kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_CHECK, start);
+        kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(margin, 0xFFFFFFU);
+        kFCCOBx[2] = *expectedData;
+
+        /* calling flash command sequence function to execute the command */
+        returnCode = flash_command_sequence(config);
+
+        /* checking for the success of command execution */
+        if (kStatus_FLASH_Success != returnCode)
+        {
+            if (failedAddress)
+            {
+                *failedAddress = start;
+            }
+            if (failedData)
+            {
+                *failedData = 0;
+            }
+            break;
+        }
+
+        lengthInBytes -= flashInfo.checkCmdAddressAligment;
+        expectedData += flashInfo.checkCmdAddressAligment / sizeof(*expectedData);
+        start += flashInfo.checkCmdAddressAligment;
+    }
+
+    return (returnCode);
+}
+
+status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin)
+{
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* preparing passing parameter to verify erase all execute-only segments command */
+    kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT, margin, 0xFFFFU);
+
+    /* calling flash command sequence function to execute the command */
+    return flash_command_sequence(config);
+}
+
+status_t FLASH_IsProtected(flash_config_t *config,
+                           uint32_t start,
+                           uint32_t lengthInBytes,
+                           flash_protection_state_t *protection_state)
+{
+    uint32_t endAddress;           /* end address for protection check */
+    uint32_t protectionRegionSize; /* size of flash protection region */
+    uint32_t regionCheckedCounter; /* increments each time the flash address was checked for
+                                    * protection status */
+    uint32_t regionCounter;        /* incrementing variable used to increment through the flash
+                                    * protection regions */
+    uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */
+
+    uint8_t flashRegionProtectStatus[FSL_FEATURE_FTFx_REGION_COUNT]; /* array of the protection status for each
+                                                                      * protection region */
+    uint32_t flashRegionAddress[FSL_FEATURE_FTFx_REGION_COUNT + 1];  /* array of the start addresses for each flash
+                                                                      * protection region. Note this is REGION_COUNT+1
+                                                                      * due to requiring the next start address after
+                                                                      * the end of flash for loop-check purposes below */
+    status_t returnCode;
+
+    if (protection_state == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* Check the supplied address range. */
+    returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
+    /* calculating Flash end address */
+    endAddress = start + lengthInBytes;
+
+    /* Calculate the size of the flash protection region
+     * If the flash density is > 32KB, then protection region is 1/32 of total flash density
+     * Else if flash density is < 32KB, then flash protection region is set to 1KB */
+    if (config->PFlashTotalSize > 32 * 1024)
+    {
+        protectionRegionSize = (config->PFlashTotalSize) / FSL_FEATURE_FTFx_REGION_COUNT;
+    }
+    else
+    {
+        protectionRegionSize = 1024;
+    }
+
+    /* populate the flashRegionAddress array with the start address of each flash region */
+    regionCounter = 0; /* make sure regionCounter is initialized to 0 first */
+
+    /* populate up to 33rd element of array, this is the next address after end of flash array */
+    while (regionCounter <= FSL_FEATURE_FTFx_REGION_COUNT)
+    {
+        flashRegionAddress[regionCounter] = config->PFlashBlockBase + protectionRegionSize * regionCounter;
+        regionCounter++;
+    }
+
+    /* populate flashRegionProtectStatus array with status information
+     * Protection status for each region is stored in the FPROT[3:0] registers
+     * Each bit represents one region of flash
+     * 4 registers * 8-bits-per-register = 32-bits (32-regions)
+     * The convention is:
+     * FPROT3[bit 0] is the first protection region (start of flash memory)
+     * FPROT0[bit 7] is the last protection region (end of flash memory)
+     * regionCounter is used to determine which FPROT[3:0] register to check for protection status
+     * Note: FPROT=1 means NOT protected, FPROT=0 means protected */
+    regionCounter = 0; /* make sure regionCounter is initialized to 0 first */
+    while (regionCounter < FSL_FEATURE_FTFx_REGION_COUNT)
+    {
+        if (regionCounter < 8)
+        {
+            flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT3) >> regionCounter) & (0x01u);
+        }
+        else if ((regionCounter >= 8) && (regionCounter < 16))
+        {
+            flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT2) >> (regionCounter - 8)) & (0x01u);
+        }
+        else if ((regionCounter >= 16) && (regionCounter < 24))
+        {
+            flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT1) >> (regionCounter - 16)) & (0x01u);
+        }
+        else
+        {
+            flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT0) >> (regionCounter - 24)) & (0x01u);
+        }
+        regionCounter++;
+    }
+
+    /* loop through the flash regions and check
+     * desired flash address range for protection status
+     * loop stops when it is detected that start has exceeded the endAddress */
+    regionCounter = 0; /* make sure regionCounter is initialized to 0 first */
+    regionCheckedCounter = 0;
+    protectStatusCounter = 0; /* make sure protectStatusCounter is initialized to 0 first */
+    while (start < endAddress)
+    {
+        /* check to see if the address falls within this protection region
+         * Note that if the entire flash is to be checked, the last protection
+         * region checked would consist of the last protection start address and
+         * the start address following the end of flash */
+        if ((start >= flashRegionAddress[regionCounter]) && (start < flashRegionAddress[regionCounter + 1]))
+        {
+            /* increment regionCheckedCounter to indicate this region was checked */
+            regionCheckedCounter++;
+
+            /* check the protection status of this region
+             * Note: FPROT=1 means NOT protected, FPROT=0 means protected */
+            if (!flashRegionProtectStatus[regionCounter])
+            {
+                /* increment protectStatusCounter to indicate this region is protected */
+                protectStatusCounter++;
+            }
+            start += protectionRegionSize; /* increment to an address within the next region */
+        }
+        regionCounter++; /* increment regionCounter to check for the next flash protection region */
+    }
+
+    /* if protectStatusCounter == 0, then no region of the desired flash region is protected */
+    if (protectStatusCounter == 0)
+    {
+        *protection_state = kFLASH_ProtectionStateUnprotected;
+    }
+    /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */
+    else if (protectStatusCounter == regionCheckedCounter)
+    {
+        *protection_state = kFLASH_ProtectionStateProtected;
+    }
+    /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed
+     * In other words, some regions are protected while others are unprotected */
+    else
+    {
+        *protection_state = kFLASH_ProtectionStateMixed;
+    }
+
+    return (returnCode);
+}
+
+status_t FLASH_IsExecuteOnly(flash_config_t *config,
+                             uint32_t start,
+                             uint32_t lengthInBytes,
+                             flash_execute_only_access_state_t *access_state)
+{
+    status_t returnCode;
+
+    if (access_state == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* Check the supplied address range. */
+    returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+    {
+        uint32_t executeOnlySegmentCounter = 0;
+
+        /* calculating end address */
+        uint32_t endAddress = start + lengthInBytes;
+
+        /* Aligning start address and end address */
+        uint32_t alignedStartAddress = ALIGN_DOWN(start, config->PFlashAccessSegmentSize);
+        uint32_t alignedEndAddress = ALIGN_UP(endAddress, config->PFlashAccessSegmentSize);
+
+        uint32_t segmentIndex = 0;
+        uint32_t maxSupportedExecuteOnlySegmentCount =
+            (alignedEndAddress - alignedStartAddress) / config->PFlashAccessSegmentSize;
+
+        while (start < endAddress)
+        {
+            uint32_t xacc;
+
+            segmentIndex = start / config->PFlashAccessSegmentSize;
+
+            if (segmentIndex < 32)
+            {
+                xacc = *(const volatile uint32_t *)&FTFx->XACCL3;
+            }
+            else if (segmentIndex < config->PFlashAccessSegmentCount)
+            {
+                xacc = *(const volatile uint32_t *)&FTFx->XACCH3;
+                segmentIndex -= 32;
+            }
+            else
+            {
+                break;
+            }
+
+            /* Determine if this address range is in a execute-only protection flash segment. */
+            if ((~xacc) & (1u << segmentIndex))
+            {
+                executeOnlySegmentCounter++;
+            }
+
+            start += config->PFlashAccessSegmentSize;
+        }
+
+        if (executeOnlySegmentCounter < 1u)
+        {
+            *access_state = kFLASH_AccessStateUnLimited;
+        }
+        else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount)
+        {
+            *access_state = kFLASH_AccessStateMixed;
+        }
+        else
+        {
+            *access_state = kFLASH_AccessStateExecuteOnly;
+        }
+    }
+#else
+    *access_state = kFLASH_AccessStateUnLimited;
+#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+
+    return (returnCode);
+}
+
+status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value)
+{
+    if ((config == NULL) || (value == NULL))
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    switch (whichProperty)
+    {
+        case kFLASH_PropertyPflashSectorSize:
+            *value = config->PFlashSectorSize;
+            break;
+
+        case kFLASH_PropertyPflashTotalSize:
+            *value = config->PFlashTotalSize;
+            break;
+
+        case kFLASH_PropertyPflashBlockSize:
+            *value = config->PFlashTotalSize / FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT;
+            break;
+
+        case kFLASH_PropertyPflashBlockCount:
+            *value = config->PFlashBlockCount;
+            break;
+
+        case kFLASH_PropertyPflashBlockBaseAddr:
+            *value = config->PFlashBlockBase;
+            break;
+
+        case kFLASH_PropertyPflashFacSupport:
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL)
+            *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL;
+#else
+            *value = 0;
+#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+            break;
+
+        case kFLASH_PropertyPflashAccessSegmentSize:
+            *value = config->PFlashAccessSegmentSize;
+            break;
+
+        case kFLASH_PropertyPflashAccessSegmentCount:
+            *value = config->PFlashAccessSegmentCount;
+            break;
+
+        case kFLASH_PropertyFlexRamBlockBaseAddr:
+            *value = config->FlexRAMBlockBase;
+            break;
+
+        case kFLASH_PropertyFlexRamTotalSize:
+            *value = config->FlexRAMTotalSize;
+            break;
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+        case kFLASH_PropertyDflashSectorSize:
+            *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE;
+            break;
+        case kFLASH_PropertyDflashTotalSize:
+            *value = config->DFlashTotalSize;
+            break;
+        case kFLASH_PropertyDflashBlockSize:
+            *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE;
+            break;
+        case kFLASH_PropertyDflashBlockCount:
+            *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT;
+            break;
+        case kFLASH_PropertyDflashBlockBaseAddr:
+            *value = config->DFlashBlockBase;
+            break;
+        case kFLASH_PropertyEepromTotalSize:
+            *value = config->EEpromTotalSize;
+            break;
+#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+
+        default: /* catch inputs that are not recognized */
+            return kStatus_FLASH_UnknownProperty;
+    }
+
+    return kStatus_FLASH_Success;
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option)
+{
+    status_t status;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    status = flasn_check_flexram_function_option_range(option);
+    if (status != kStatus_FLASH_Success)
+    {
+        return status;
+    }
+
+    /* preparing passing parameter to verify all block command */
+    kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU);
+
+    /* calling flash command sequence function to execute the command */
+    return flash_command_sequence(config);
+}
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+status_t FLASH_SwapControl(flash_config_t *config,
+                           uint32_t address,
+                           flash_swap_control_option_t option,
+                           flash_swap_state_config_t *returnInfo)
+{
+    status_t returnCode;
+
+    if ((config == NULL) || (returnInfo == NULL))
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    if (address & (FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT - 1))
+    {
+        return kStatus_FLASH_AlignmentError;
+    }
+
+    /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */
+    if ((address >= (config->PFlashTotalSize / 2)) ||
+        ((address >= kFLASH_ConfigAreaStart) && (address <= kFLASH_ConfigAreaEnd)))
+    {
+        return kStatus_FLASH_SwapIndicatorAddressError;
+    }
+
+    /* Check the option. */
+    returnCode = flash_check_swap_control_option(option);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
+    kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SWAP_CONTROL, address);
+    kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU);
+
+    returnCode = flash_command_sequence(config);
+
+    returnInfo->flashSwapState = (flash_swap_state_t)FTFx->FCCOB5;
+    returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB6;
+    returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB7;
+
+    return returnCode;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+
+#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option)
+{
+    flash_swap_state_config_t returnInfo;
+    status_t returnCode;
+
+    memset(&returnInfo, 0xFFU, sizeof(returnInfo));
+
+    do
+    {
+        returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionReportStatus, &returnInfo);
+        if (returnCode != kStatus_FLASH_Success)
+        {
+            return returnCode;
+        }
+
+        if (kFLASH_SwapFunctionOptionDisable == option)
+        {
+            if (returnInfo.flashSwapState == kFLASH_SwapStateDisabled)
+            {
+                return kStatus_FLASH_Success;
+            }
+            else if (returnInfo.flashSwapState == kFLASH_SwapStateUninitialized)
+            {
+                /* The swap system changed to the DISABLED state with Program flash block 0
+                 * located at relative flash address 0x0_0000 */
+                returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionDisableSystem, &returnInfo);
+            }
+            else
+            {
+                /* Swap disable should be requested only when swap system is in the uninitialized state */
+                return kStatus_FLASH_SwapSystemNotInUninitialized;
+            }
+        }
+        else
+        {
+            /* When first swap: the initial swap state is Uninitialized, flash swap inidicator address is unset,
+             *    the swap procedure should be Uninitialized -> Update-Erased -> Complete.
+             * After the first swap has been completed, the flash swap inidicator address cannot be modified
+             *    unless EraseAllBlocks command is issued, the swap procedure is changed to Update -> Update-Erased ->
+             *    Complete. */
+            switch (returnInfo.flashSwapState)
+            {
+                case kFLASH_SwapStateUninitialized:
+                    /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */
+                    returnCode =
+                        FLASH_SwapControl(config, address, kFLASH_SwapControlOptionIntializeSystem, &returnInfo);
+                    break;
+                case kFLASH_SwapStateReady:
+                    /* Validate whether the address provided to the swap system is matched to
+                     * swap indicator address in the IFR */
+                    returnCode = flash_validate_swap_indicator_address(config, address);
+                    if (returnCode == kStatus_FLASH_Success)
+                    {
+                        /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */
+                        returnCode =
+                            FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInUpdateState, &returnInfo);
+                    }
+                    break;
+                case kFLASH_SwapStateUpdate:
+                    /* If current swap mode is Update, Erase indicator sector in non active block
+                     * to proceed swap system to update-erased state */
+                    returnCode = FLASH_Erase(config, address + (config->PFlashTotalSize >> 1),
+                                             FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_ApiEraseKey);
+                    break;
+                case kFLASH_SwapStateUpdateErased:
+                    /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */
+                    returnCode =
+                        FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInCompleteState, &returnInfo);
+                    break;
+                case kFLASH_SwapStateComplete:
+                    break;
+                case kFLASH_SwapStateDisabled:
+                    /* When swap system is in disabled state, We need to clear swap system back to uninitialized
+                     * by issuing EraseAllBlocks command */
+                    returnCode = kStatus_FLASH_SwapSystemNotInUninitialized;
+                    break;
+                default:
+                    returnCode = kStatus_FLASH_InvalidArgument;
+                    break;
+            }
+        }
+        if (returnCode != kStatus_FLASH_Success)
+        {
+            break;
+        }
+    } while (!((kFLASH_SwapStateComplete == returnInfo.flashSwapState) && (kFLASH_SwapFunctionOptionEnable == option)));
+
+    return returnCode;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
+
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD
+status_t FLASH_ProgramPartition(flash_config_t *config,
+                                flash_partition_flexram_load_option_t option,
+                                uint32_t eepromDataSizeCode,
+                                uint32_t flexnvmPartitionCode)
+{
+    status_t returnCode;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* eepromDataSizeCode[7:6], flexnvmPartitionCode[7:4] should be all 1'b0
+     *  or it will cause access error. */
+    /* eepromDataSizeCode &= 0x3FU;  */
+    /* flexnvmPartitionCode &= 0x0FU; */
+
+    /* preparing passing parameter to program the flash block */
+    kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option);
+    kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU);
+
+    /* calling flash command sequence function to execute the command */
+    returnCode = flash_command_sequence(config);
+
+    flash_cache_clear(config);
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+    /* Data flash IFR will be updated by program partition command during reset sequence,
+     * so we just set reserved values for partitioned FlexNVM size here */
+    config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED;
+    config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif
+
+    return (returnCode);
+}
+#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */
+
+status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus)
+{
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    *kFPROT = protectStatus;
+
+    if (protectStatus != *kFPROT)
+    {
+        return kStatus_FLASH_CommandFailure;
+    }
+
+    return kStatus_FLASH_Success;
+}
+
+status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus)
+{
+    if ((config == NULL) || (protectStatus == NULL))
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    *protectStatus = *kFPROT;
+
+    return kStatus_FLASH_Success;
+}
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus)
+{
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED))
+    {
+        return kStatus_FLASH_CommandNotSupported;
+    }
+
+    FTFx->FDPROT = protectStatus;
+
+    if (FTFx->FDPROT != protectStatus)
+    {
+        return kStatus_FLASH_CommandFailure;
+    }
+
+    return kStatus_FLASH_Success;
+}
+#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus)
+{
+    if ((config == NULL) || (protectStatus == NULL))
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED))
+    {
+        return kStatus_FLASH_CommandNotSupported;
+    }
+
+    *protectStatus = FTFx->FDPROT;
+
+    return kStatus_FLASH_Success;
+}
+#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus)
+{
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED))
+    {
+        return kStatus_FLASH_CommandNotSupported;
+    }
+
+    FTFx->FEPROT = protectStatus;
+
+    if (FTFx->FEPROT != protectStatus)
+    {
+        return kStatus_FLASH_CommandFailure;
+    }
+
+    return kStatus_FLASH_Success;
+}
+#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus)
+{
+    if ((config == NULL) || (protectStatus == NULL))
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED))
+    {
+        return kStatus_FLASH_CommandNotSupported;
+    }
+
+    *protectStatus = FTFx->FEPROT;
+
+    return kStatus_FLASH_Success;
+}
+#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+/*!
+ * @brief Copy PIC of flash_run_command() to RAM
+ */
+static void copy_flash_run_command(uint32_t *flashRunCommand)
+{
+    assert(sizeof(s_flashRunCommandFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4));
+
+    /* Since the value of ARM function pointer is always odd, but the real start address
+     * of function memory should be even, that's why +1 operation exist. */
+    memcpy((void *)flashRunCommand, (void *)s_flashRunCommandFunctionCode, sizeof(s_flashRunCommandFunctionCode));
+    callFlashRunCommand = (void (*)(FTFx_REG_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1);
+}
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+/*!
+ * @brief Flash Command Sequence
+ *
+ * This function is used to perform the command write sequence to the flash.
+ *
+ * @param driver Pointer to storage for the driver runtime state.
+ * @return An error code or kStatus_FLASH_Success
+ */
+static status_t flash_command_sequence(flash_config_t *config)
+{
+    uint8_t registerValue;
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+    /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */
+    FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK;
+
+    status_t returnCode = flash_check_execute_in_ram_function_info(config);
+    if (kStatus_FLASH_Success != returnCode)
+    {
+        return returnCode;
+    }
+
+    /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using
+     * pre-processed MICRO sentences or operating global variable in flash_run_comamnd()
+     * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */
+    callFlashRunCommand((FTFx_REG_ACCESS_TYPE)(&FTFx->FSTAT));
+#else
+    /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */
+    FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK;
+
+    /* clear CCIF bit */
+    FTFx->FSTAT = FTFx_FSTAT_CCIF_MASK;
+
+    /* Check CCIF bit of the flash status register, wait till it is set.
+     * IP team indicates that this loop will always complete. */
+    while (!(FTFx->FSTAT & FTFx_FSTAT_CCIF_MASK))
+    {
+    }
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+    /* Check error bits */
+    /* Get flash status register value */
+    registerValue = FTFx->FSTAT;
+
+    /* checking access error */
+    if (registerValue & FTFx_FSTAT_ACCERR_MASK)
+    {
+        return kStatus_FLASH_AccessError;
+    }
+    /* checking protection error */
+    else if (registerValue & FTFx_FSTAT_FPVIOL_MASK)
+    {
+        return kStatus_FLASH_ProtectionViolation;
+    }
+    /* checking MGSTAT0 non-correctable error */
+    else if (registerValue & FTFx_FSTAT_MGSTAT0_MASK)
+    {
+        return kStatus_FLASH_CommandFailure;
+    }
+    else
+    {
+        return kStatus_FLASH_Success;
+    }
+}
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+/*!
+ * @brief Copy PIC of flash_cache_clear_command() to RAM
+ *
+ */
+static void copy_flash_cache_clear_command(uint32_t *flashCacheClearCommand)
+{
+    assert(sizeof(s_flashCacheClearCommandFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4));
+
+    /* Since the value of ARM function pointer is always odd, but the real start address
+     * of function memory should be even, that's why +1 operation exist. */
+    memcpy((void *)flashCacheClearCommand, (void *)s_flashCacheClearCommandFunctionCode,
+           sizeof(s_flashCacheClearCommandFunctionCode));
+    callFlashCacheClearCommand = (void (*)(FTFx_REG32_ACCESS_TYPE ftfx_reg))((uint32_t)flashCacheClearCommand + 1);
+}
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+/*!
+ * @brief Flash Cache Clear
+ *
+ * This function is used to perform the cache clear to the flash.
+ */
+#if (defined(__GNUC__))
+/* #pragma GCC push_options */
+/* #pragma GCC optimize("O0") */
+void __attribute__((optimize("O0"))) flash_cache_clear(flash_config_t *config)
+#else
+#if (defined(__ICCARM__))
+#pragma optimize = none
+#endif
+#if (defined(__CC_ARM))
+#pragma push
+#pragma O0
+#endif
+void flash_cache_clear(flash_config_t *config)
+#endif
+{
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+    status_t returnCode = flash_check_execute_in_ram_function_info(config);
+    if (kStatus_FLASH_Success != returnCode)
+    {
+        return;
+    }
+
+/* We pass the ftfx register address as a parameter to flash_cache_clear_comamnd() instead of using
+ * pre-processed MACROs or a global variable in flash_cache_clear_comamnd()
+ * to make sure that flash_cache_clear_command() will be compiled into position-independent code (PIC). */
+#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS
+#if defined(MCM)
+    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM->PLACR);
+#endif
+#if defined(MCM0)
+    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR);
+#endif
+#if defined(MCM1)
+    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM1->PLACR);
+#endif
+#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS
+#if defined(FMC_PFB01CR_CINV_WAY_MASK)
+    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR);
+#else
+    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR);
+#endif
+#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS
+    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]);
+#else
+#if defined(FMC_PFB0CR_S_INV_MASK)
+    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR);
+#elif defined(FMC_PFB01CR_S_INV_MASK)
+    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR);
+#else
+    /* meaningless code, just a workaround to solve warning*/
+    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)0);
+#endif
+/* #error "Unknown flash cache controller" */
+#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
+
+#else
+
+#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS
+#if defined(MCM)
+    MCM->PLACR |= MCM_PLACR_CFCC_MASK;
+#endif
+#if defined(MCM0)
+    MCM0->PLACR |= MCM_PLACR_CFCC_MASK;
+#endif
+#if defined(MCM1)
+    MCM1->PLACR |= MCM_PLACR_CFCC_MASK;
+#endif
+#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS
+#if defined(FMC_PFB01CR_CINV_WAY_MASK)
+    FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0);
+#else
+    FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0);
+#endif
+#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS
+    MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(2);
+    MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(1);
+#else
+#if defined(FMC_PFB0CR_S_INV_MASK)
+    FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK;
+#elif defined(FMC_PFB01CR_S_INV_MASK)
+    FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK;
+#endif
+/*    #error "Unknown flash cache controller" */
+#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+}
+#if (defined(__CC_ARM))
+#pragma pop
+#endif
+#if (defined(__GNUC__))
+/* #pragma GCC pop_options */
+#endif
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+/*! @brief Check whether flash execute-in-ram functions are ready  */
+static status_t flash_check_execute_in_ram_function_info(flash_config_t *config)
+{
+    flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo;
+
+    if ((config->flashExecuteInRamFunctionInfo) &&
+        (kFLASH_ExecuteInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount))
+    {
+        return kStatus_FLASH_Success;
+    }
+
+    return kStatus_FLASH_ExecuteInRamFunctionNotReady;
+}
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+/*! @brief Validates the range and alignment of the given address range.*/
+static status_t flash_check_range(flash_config_t *config,
+                                  uint32_t startAddress,
+                                  uint32_t lengthInBytes,
+                                  uint32_t alignmentBaseline)
+{
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* Verify the start and length are alignmentBaseline aligned. */
+    if ((startAddress & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1)))
+    {
+        return kStatus_FLASH_AlignmentError;
+    }
+
+/* check for valid range of the target addresses */
+#if !FLASH_SSD_IS_FLEXNVM_ENABLED
+    if ((startAddress < config->PFlashBlockBase) ||
+        ((startAddress + lengthInBytes) > (config->PFlashBlockBase + config->PFlashTotalSize)))
+#else
+    if (!(((startAddress >= config->PFlashBlockBase) &&
+           ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize))) ||
+          ((startAddress >= config->DFlashBlockBase) &&
+           ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize)))))
+#endif
+    {
+        return kStatus_FLASH_AddressError;
+    }
+
+    return kStatus_FLASH_Success;
+}
+
+/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/
+static status_t flash_get_matched_operation_info(flash_config_t *config,
+                                                 uint32_t address,
+                                                 flash_operation_config_t *info)
+{
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* Clean up info Structure*/
+    memset(info, 0, sizeof(flash_operation_config_t));
+
+/* When required by the command, address bit 23 selects between program flash memory
+ * (=0) and data flash memory (=1).*/
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+    if ((address >= config->DFlashBlockBase) && (address <= (config->DFlashBlockBase + config->DFlashTotalSize)))
+    {
+        info->convertedAddress = address - config->DFlashBlockBase + 0x800000U;
+        info->activeSectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE;
+        info->activeBlockSize = config->DFlashTotalSize / FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT;
+
+        info->blockWriteUnitSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE;
+        info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT;
+        info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT;
+        info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT;
+        info->checkCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT;
+    }
+    else
+#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+    {
+        info->convertedAddress = address - config->PFlashBlockBase;
+        info->activeSectorSize = config->PFlashSectorSize;
+        info->activeBlockSize = config->PFlashTotalSize / config->PFlashBlockCount;
+
+        info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE;
+        info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT;
+        info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT;
+        info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT;
+        info->checkCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT;
+    }
+
+    return kStatus_FLASH_Success;
+}
+
+/*! @brief Validates the given user key for flash erase APIs.*/
+static status_t flash_check_user_key(uint32_t key)
+{
+    /* Validate the user key */
+    if (key != kFLASH_ApiEraseKey)
+    {
+        return kStatus_FLASH_EraseKeyError;
+    }
+
+    return kStatus_FLASH_Success;
+}
+
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/
+static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config)
+{
+    struct
+    {
+        uint32_t reserved0;
+        uint8_t FlexNVMPartitionCode;
+        uint8_t EEPROMDataSetSize;
+        uint16_t reserved1;
+    } dataIFRReadOut;
+    status_t returnCode;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* Get FlexNVM memory partition info from data flash IFR */
+    returnCode = FLASH_ReadResource(config, DFLASH_IFR_READRESOURCE_START_ADDRESS, (uint32_t *)&dataIFRReadOut,
+                                    sizeof(dataIFRReadOut), kFLASH_ResourceOptionFlashIfr);
+    if (returnCode != kStatus_FLASH_Success)
+    {
+        return kStatus_FLASH_PartitionStatusUpdateFailure;
+    }
+
+    /* Fill out partitioned EEPROM size */
+    dataIFRReadOut.EEPROMDataSetSize &= 0x0FU;
+    switch (dataIFRReadOut.EEPROMDataSetSize)
+    {
+        case 0x00U:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000;
+            break;
+        case 0x01U:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001;
+            break;
+        case 0x02U:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010;
+            break;
+        case 0x03U:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011;
+            break;
+        case 0x04U:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100;
+            break;
+        case 0x05U:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101;
+            break;
+        case 0x06U:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110;
+            break;
+        case 0x07U:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111;
+            break;
+        case 0x08U:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000;
+            break;
+        case 0x09U:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001;
+            break;
+        case 0x0AU:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010;
+            break;
+        case 0x0BU:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011;
+            break;
+        case 0x0CU:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100;
+            break;
+        case 0x0DU:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101;
+            break;
+        case 0x0EU:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110;
+            break;
+        case 0x0FU:
+            config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111;
+            break;
+        default:
+            config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED;
+            break;
+    }
+
+    /* Fill out partitioned DFlash size */
+    dataIFRReadOut.FlexNVMPartitionCode &= 0x0FU;
+    switch (dataIFRReadOut.FlexNVMPartitionCode)
+    {
+        case 0x00U:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 */
+            break;
+        case 0x01U:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 */
+            break;
+        case 0x02U:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 */
+            break;
+        case 0x03U:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 */
+            break;
+        case 0x04U:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 */
+            break;
+        case 0x05U:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 */
+            break;
+        case 0x06U:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 */
+            break;
+        case 0x07U:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 */
+            break;
+        case 0x08U:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 */
+            break;
+        case 0x09U:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 */
+            break;
+        case 0x0AU:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 */
+            break;
+        case 0x0BU:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 */
+            break;
+        case 0x0CU:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 */
+            break;
+        case 0x0DU:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 */
+            break;
+        case 0x0EU:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 */
+            break;
+        case 0x0FU:
+#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 != 0xFFFFFFFF)
+            config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111;
+#else
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 */
+            break;
+        default:
+            config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED;
+            break;
+    }
+
+    return kStatus_FLASH_Success;
+}
+#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+/*! @brief Validates the range of the given resource address.*/
+static status_t flash_check_resource_range(uint32_t start,
+                                           uint32_t lengthInBytes,
+                                           uint32_t alignmentBaseline,
+                                           flash_read_resource_option_t option)
+{
+    status_t status;
+    uint32_t maxReadbleAddress;
+
+    if ((start & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1)))
+    {
+        return kStatus_FLASH_AlignmentError;
+    }
+
+    status = kStatus_FLASH_Success;
+
+    maxReadbleAddress = start + lengthInBytes - 1;
+    if (option == kFLASH_ResourceOptionVersionId)
+    {
+        if ((start != kFLASH_ResourceRangeVersionIdStart) ||
+            ((start + lengthInBytes - 1) != kFLASH_ResourceRangeVersionIdEnd))
+        {
+            status = kStatus_FLASH_InvalidArgument;
+        }
+    }
+    else if (option == kFLASH_ResourceOptionFlashIfr)
+    {
+        if (maxReadbleAddress < kFLASH_ResourceRangePflashIfrSizeInBytes)
+        {
+        }
+#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+        else if ((start >= kFLASH_ResourceRangePflashSwapIfrStart) &&
+                 (maxReadbleAddress <= kFLASH_ResourceRangePflashSwapIfrEnd))
+        {
+        }
+#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
+        else if ((start >= kFLASH_ResourceRangeDflashIfrStart) &&
+                 (maxReadbleAddress <= kFLASH_ResourceRangeDflashIfrEnd))
+        {
+        }
+        else
+        {
+            status = kStatus_FLASH_InvalidArgument;
+        }
+    }
+    else
+    {
+        status = kStatus_FLASH_InvalidArgument;
+    }
+
+    return status;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+/*! @brief Validates the gived swap control option.*/
+static status_t flash_check_swap_control_option(flash_swap_control_option_t option)
+{
+    if ((option == kFLASH_SwapControlOptionIntializeSystem) || (option == kFLASH_SwapControlOptionSetInUpdateState) ||
+        (option == kFLASH_SwapControlOptionSetInCompleteState) || (option == kFLASH_SwapControlOptionReportStatus) ||
+        (option == kFLASH_SwapControlOptionDisableSystem))
+    {
+        return kStatus_FLASH_Success;
+    }
+
+    return kStatus_FLASH_InvalidArgument;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */
+
+#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/
+static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address)
+{
+    flash_swap_ifr_field_data_t flashSwapIfrFieldData;
+    uint32_t swapIndicatorAddress;
+
+    status_t returnCode;
+    returnCode =
+        FLASH_ReadResource(config, kFLASH_ResourceRangePflashSwapIfrStart, flashSwapIfrFieldData.flashSwapIfrData,
+                           sizeof(flashSwapIfrFieldData.flashSwapIfrData), kFLASH_ResourceOptionFlashIfr);
+
+    if (returnCode != kStatus_FLASH_Success)
+    {
+        return returnCode;
+    }
+
+    /* The high bits value of Swap Indicator Address is stored in Program Flash Swap IFR Field,
+     * the low severval bit value of Swap Indicator Address is always 1'b0 */
+    swapIndicatorAddress = (uint32_t)flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress *
+                           FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT;
+    if (address != swapIndicatorAddress)
+    {
+        return kStatus_FLASH_SwapIndicatorAddressError;
+    }
+
+    return returnCode;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
+
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+/*! @brief Validates the gived flexram function option.*/
+static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option)
+{
+    if ((option != kFLASH_FlexramFunctionOptionAvailableAsRam) &&
+        (option != kFLASH_FlexramFunctionOptionAvailableForEeprom))
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    return kStatus_FLASH_Success;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flash.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flash.h
new file mode 100644
index 00000000000..8941ad7a84f
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flash.h
@@ -0,0 +1,1209 @@
+/*
+ * Copyright (c) 2013-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_FLASH_H_
+#define _FSL_FLASH_H_
+
+#if (defined(BL_TARGET_FLASH) || defined(BL_TARGET_ROM) || defined(BL_TARGET_RAM))
+#include <assert.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+#include "bootloader_common.h"
+#else
+#include "fsl_common.h"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @addtogroup flash_driver
+ * @{
+ */
+
+/*!
+ * @name Flash version
+ * @{
+ */
+/*! @brief Construct the version number for drivers. */
+#if !defined(MAKE_VERSION)
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+#endif
+
+/*! @brief FLASH driver version for SDK*/
+#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
+
+/*! @brief FLASH driver version for ROM*/
+enum _flash_driver_version_constants
+{
+    kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/
+    kFLASH_DriverVersionMajor = 2,  /*!< Major flash driver version.*/
+    kFLASH_DriverVersionMinor = 1,  /*!< Minor flash driver version.*/
+    kFLASH_DriverVersionBugfix = 0  /*!< Bugfix for flash driver version.*/
+};
+/*@}*/
+
+/*!
+ * @name Flash configuration
+ * @{
+ */
+/*! @brief Whether to support FlexNVM in flash driver */
+#if !defined(FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT)
+#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enable FlexNVM support by default. */
+#endif
+
+/*! @brief Whether the FlexNVM is enabled in flash driver */
+#define FLASH_SSD_IS_FLEXNVM_ENABLED (FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT && FSL_FEATURE_FLASH_HAS_FLEX_NVM)
+
+/*! @brief Flash driver location. */
+#if !defined(FLASH_DRIVER_IS_FLASH_RESIDENT)
+#if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM))
+#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for flash resident application. */
+#else
+#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for non-flash resident application. */
+#endif
+#endif
+
+/*! @brief Flash Driver Export option */
+#if !defined(FLASH_DRIVER_IS_EXPORTED)
+#if (defined(BL_TARGET_ROM) || defined(BL_TARGET_FLASH))
+#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for ROM bootloader. */
+#else
+#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for SDK application. */
+#endif
+#endif
+/*@}*/
+
+/*!
+ * @name Flash status
+ * @{
+ */
+/*! @brief Flash driver status group. */
+#if defined(kStatusGroup_FlashDriver)
+#define kStatusGroupGeneric kStatusGroup_Generic
+#define kStatusGroupFlashDriver kStatusGroup_FlashDriver
+#elif defined(kStatusGroup_FLASH)
+#define kStatusGroupGeneric kStatusGroup_Generic
+#define kStatusGroupFlashDriver kStatusGroup_FLASH
+#else
+#define kStatusGroupGeneric 0
+#define kStatusGroupFlashDriver 1
+#endif
+
+/*! @brief Construct a status code value from a group and code number. */
+#if !defined(MAKE_STATUS)
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+#endif
+
+/*!
+ * @brief Flash driver status codes.
+ */
+enum _flash_status
+{
+    kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0),         /*!< API is executed successfully*/
+    kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/
+    kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0),   /*!< Error size*/
+    kStatus_FLASH_AlignmentError =
+        MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with specified baseline*/
+    kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */
+    kStatus_FLASH_AccessError =
+        MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bounds addresses */
+    kStatus_FLASH_ProtectionViolation = MAKE_STATUS(
+        kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */
+    kStatus_FLASH_CommandFailure =
+        MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */
+    kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6),   /*!< Unknown property.*/
+    kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7),     /*!< API erase key is invalid.*/
+    kStatus_FLASH_RegionExecuteOnly = MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< Current region is execute only.*/
+    kStatus_FLASH_ExecuteInRamFunctionNotReady =
+        MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/
+    kStatus_FLASH_PartitionStatusUpdateFailure =
+        MAKE_STATUS(kStatusGroupFlashDriver, 10), /*!< Failed to update partition status.*/
+    kStatus_FLASH_SetFlexramAsEepromError =
+        MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set flexram as eeprom.*/
+    kStatus_FLASH_RecoverFlexramAsRamError =
+        MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover flexram as RAM.*/
+    kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set flexram as RAM.*/
+    kStatus_FLASH_RecoverFlexramAsEepromError =
+        MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover flexram as eeprom.*/
+    kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash API is not supported.*/
+    kStatus_FLASH_SwapSystemNotInUninitialized =
+        MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in uninitialzed state.*/
+    kStatus_FLASH_SwapIndicatorAddressError =
+        MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< Swap indicator address is invalid.*/
+};
+/*@}*/
+
+/*!
+ * @name Flash API key
+ * @{
+ */
+/*! @brief Construct the four char code for flash driver API key. */
+#if !defined(FOUR_CHAR_CODE)
+#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a)))
+#endif
+
+/*!
+ * @brief Enumeration for flash driver API keys.
+ *
+ * @note The resulting value is built with a byte order such that the string
+ * being readable in expected order when viewed in a hex editor, if the value
+ * is treated as a 32-bit little endian value.
+ */
+enum _flash_driver_api_keys
+{
+    kFLASH_ApiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/
+};
+/*@}*/
+
+/*!
+ * @brief Enumeration for supported flash margin levels.
+ */
+typedef enum _flash_margin_value
+{
+    kFLASH_MarginValueNormal,  /*!< Use the 'normal' read level for 1s.*/
+    kFLASH_MarginValueUser,    /*!< Apply the 'User' margin to the normal read-1 level.*/
+    kFLASH_MarginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/
+    kFLASH_MarginValueInvalid  /*!< Not real margin level, Used to determine the range of valid margin level. */
+} flash_margin_value_t;
+
+/*!
+ * @brief Enumeration for the three possible flash security states.
+ */
+typedef enum _flash_security_state
+{
+    kFLASH_SecurityStateNotSecure,       /*!< Flash is not secure.*/
+    kFLASH_SecurityStateBackdoorEnabled, /*!< Flash backdoor is enabled.*/
+    kFLASH_SecurityStateBackdoorDisabled /*!< Flash backdoor is disabled.*/
+} flash_security_state_t;
+
+/*!
+ * @brief Enumeration for the three possible flash protection levels.
+ */
+typedef enum _flash_protection_state
+{
+    kFLASH_ProtectionStateUnprotected, /*!< Flash region is not protected.*/
+    kFLASH_ProtectionStateProtected,   /*!< Flash region is protected.*/
+    kFLASH_ProtectionStateMixed        /*!< Flash is mixed with protected and unprotected region.*/
+} flash_protection_state_t;
+
+/*!
+ * @brief Enumeration for the three possible flash execute access levels.
+ */
+typedef enum _flash_execute_only_access_state
+{
+    kFLASH_AccessStateUnLimited,   /*!< Flash region is unLimited.*/
+    kFLASH_AccessStateExecuteOnly, /*!< Flash region is execute only.*/
+    kFLASH_AccessStateMixed        /*!< Flash is mixed with unLimited and execute only region.*/
+} flash_execute_only_access_state_t;
+
+/*!
+ * @brief Enumeration for various flash properties.
+ */
+typedef enum _flash_property_tag
+{
+    kFLASH_PropertyPflashSectorSize = 0x00U,         /*!< Pflash sector size property.*/
+    kFLASH_PropertyPflashTotalSize = 0x01U,          /*!< Pflash total size property.*/
+    kFLASH_PropertyPflashBlockSize = 0x02U,          /*!< Pflash block size property.*/
+    kFLASH_PropertyPflashBlockCount = 0x03U,         /*!< Pflash block count property.*/
+    kFLASH_PropertyPflashBlockBaseAddr = 0x04U,      /*!< Pflash block base address property.*/
+    kFLASH_PropertyPflashFacSupport = 0x05U,         /*!< Pflash fac support property.*/
+    kFLASH_PropertyPflashAccessSegmentSize = 0x06U,  /*!< Pflash access segment size property.*/
+    kFLASH_PropertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/
+    kFLASH_PropertyFlexRamBlockBaseAddr = 0x08U,     /*!< FlexRam block base address property.*/
+    kFLASH_PropertyFlexRamTotalSize = 0x09U,         /*!< FlexRam total size property.*/
+    kFLASH_PropertyDflashSectorSize = 0x10U,         /*!< Dflash sector size property.*/
+    kFLASH_PropertyDflashTotalSize = 0x11U,          /*!< Dflash total size property.*/
+    kFLASH_PropertyDflashBlockSize = 0x12U,          /*!< Dflash block count property.*/
+    kFLASH_PropertyDflashBlockCount = 0x13U,         /*!< Dflash block base address property.*/
+    kFLASH_PropertyDflashBlockBaseAddr = 0x14U,      /*!< Eeprom total size property.*/
+    kFLASH_PropertyEepromTotalSize = 0x15U
+} flash_property_tag_t;
+
+/*!
+ * @brief Constants for execute-in-RAM flash function.
+ */
+enum _flash_execute_in_ram_function_constants
+{
+    kFLASH_ExecuteInRamFunctionMaxSizeInWords = 16U, /*!< Max size of execute-in-RAM function.*/
+    kFLASH_ExecuteInRamFunctionTotalNum = 2U         /*!< Total number of execute-in-RAM functions.*/
+};
+
+/*!
+ * @brief Flash execute-in-RAM function information.
+ */
+typedef struct _flash_execute_in_ram_function_config
+{
+    uint32_t activeFunctionCount;     /*!< Number of available execute-in-RAM functions.*/
+    uint32_t *flashRunCommand;        /*!< execute-in-RAM function: flash_run_command.*/
+    uint32_t *flashCacheClearCommand; /*!< execute-in-RAM function: flash_cache_clear_command.*/
+} flash_execute_in_ram_function_config_t;
+
+/*!
+ * @brief Enumeration for the two possible options of flash read resource command.
+ */
+typedef enum _flash_read_resource_option
+{
+    kFLASH_ResourceOptionFlashIfr =
+        0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */
+    kFLASH_ResourceOptionVersionId = 0x01U /*!< Select code for Version ID*/
+} flash_read_resource_option_t;
+
+/*!
+ * @brief Enumeration for the range of special-purpose flash resource
+ */
+enum _flash_read_resource_range
+{
+#if (FSL_FEATURE_FLASH_IS_FTFE == 1)
+    kFLASH_ResourceRangePflashIfrSizeInBytes = 1024U,  /*!< Pflash IFR size in byte.*/
+    kFLASH_ResourceRangeVersionIdSizeInBytes = 8U,     /*!< Version ID IFR size in byte.*/
+    kFLASH_ResourceRangeVersionIdStart = 0x08U,        /*!< Version ID IFR start address.*/
+    kFLASH_ResourceRangeVersionIdEnd = 0x0FU,          /*!< Version ID IFR end address.*/
+    kFLASH_ResourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/
+    kFLASH_ResourceRangePflashSwapIfrEnd =
+        (kFLASH_ResourceRangePflashSwapIfrStart + 0x3FFU), /*!< Pflash swap IFR end address.*/
+#else                                                      /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */
+    kFLASH_ResourceRangePflashIfrSizeInBytes = 256U,  /*!< Pflash IFR size in byte.*/
+    kFLASH_ResourceRangeVersionIdSizeInBytes = 8U,    /*!< Version ID IFR size in byte.*/
+    kFLASH_ResourceRangeVersionIdStart = 0x00U,       /*!< Version ID IFR start address.*/
+    kFLASH_ResourceRangeVersionIdEnd = 0x07U,         /*!< Version ID IFR end address.*/
+#if 0x20000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE)
+    kFLASH_ResourceRangePflashSwapIfrStart = 0x8000U, /*!< Pflash swap IFR start address.*/
+#elif 0x40000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE)
+    kFLASH_ResourceRangePflashSwapIfrStart = 0x10000U, /*!< Pflash swap IFR start address.*/
+#elif 0x80000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE)
+    kFLASH_ResourceRangePflashSwapIfrStart = 0x20000U, /*!< Pflash swap IFR start address.*/
+#else
+    kFLASH_ResourceRangePflashSwapIfrStart = 0,
+#endif
+    kFLASH_ResourceRangePflashSwapIfrEnd =
+        (kFLASH_ResourceRangePflashSwapIfrStart + 0xFFU), /*!< Pflash swap IFR end address.*/
+#endif
+    kFLASH_ResourceRangeDflashIfrStart = 0x800000U, /*!< Dflash IFR start address.*/
+    kFLASH_ResourceRangeDflashIfrEnd = 0x8003FFU,   /*!< Dflash IFR end address.*/
+};
+
+/*!
+ * @brief Enumeration for the two possilbe options of set flexram function command.
+ */
+typedef enum _flash_flexram_function_option
+{
+    kFLASH_FlexramFunctionOptionAvailableAsRam = 0xFFU,    /*!< Option used to make FlexRAM available as RAM */
+    kFLASH_FlexramFunctionOptionAvailableForEeprom = 0x00U /*!< Option used to make FlexRAM available for EEPROM */
+} flash_flexram_function_option_t;
+
+/*!
+ * @brief Enumeration for acceleration RAM property.
+ */
+enum _flash_acceleration_ram_property
+{
+    kFLASH_AccelerationRamSize = 0x400U
+};
+
+/*!
+ * @brief Enumeration for the possible options of Swap function
+ */
+typedef enum _flash_swap_function_option
+{
+    kFLASH_SwapFunctionOptionEnable = 0x00U, /*!< Option used to enable Swap function */
+    kFLASH_SwapFunctionOptionDisable = 0x01U /*!< Option used to Disable Swap function */
+} flash_swap_function_option_t;
+
+/*!
+ * @brief Enumeration for the possible options of Swap Control commands
+ */
+typedef enum _flash_swap_control_option
+{
+    kFLASH_SwapControlOptionIntializeSystem = 0x01U,    /*!< Option used to Intialize Swap System */
+    kFLASH_SwapControlOptionSetInUpdateState = 0x02U,   /*!< Option used to Set Swap in Update State */
+    kFLASH_SwapControlOptionSetInCompleteState = 0x04U, /*!< Option used to Set Swap in Complete State */
+    kFLASH_SwapControlOptionReportStatus = 0x08U,       /*!< Option used to Report Swap Status */
+    kFLASH_SwapControlOptionDisableSystem = 0x10U       /*!< Option used to Disable Swap Status */
+} flash_swap_control_option_t;
+
+/*!
+ * @brief Enumeration for the possible flash swap status.
+ */
+typedef enum _flash_swap_state
+{
+    kFLASH_SwapStateUninitialized = 0x00U, /*!< Flash swap system is in uninitialized state.*/
+    kFLASH_SwapStateReady = 0x01U,         /*!< Flash swap system is in ready state.*/
+    kFLASH_SwapStateUpdate = 0x02U,        /*!< Flash swap system is in update state.*/
+    kFLASH_SwapStateUpdateErased = 0x03U,  /*!< Flash swap system is in updateErased state.*/
+    kFLASH_SwapStateComplete = 0x04U,      /*!< Flash swap system is in complete state.*/
+    kFLASH_SwapStateDisabled = 0x05U       /*!< Flash swap system is in disabled state.*/
+} flash_swap_state_t;
+
+/*!
+ * @breif Enumeration for the possible flash swap block status
+ */
+typedef enum _flash_swap_block_status
+{
+    kFLASH_SwapBlockStatusLowerHalfProgramBlocksAtZero =
+        0x00U, /*!< Swap block status is that lower half program block at zero.*/
+    kFLASH_SwapBlockStatusUpperHalfProgramBlocksAtZero =
+        0x01U, /*!< Swap block status is that upper half program block at zero.*/
+} flash_swap_block_status_t;
+
+/*!
+ * @brief Flash Swap information.
+ */
+typedef struct _flash_swap_state_config
+{
+    flash_swap_state_t flashSwapState;                /*!< Current swap system status.*/
+    flash_swap_block_status_t currentSwapBlockStatus; /*!< Current swap block status.*/
+    flash_swap_block_status_t nextSwapBlockStatus;    /*!< Next swap block status.*/
+} flash_swap_state_config_t;
+
+/*!
+ * @brief Flash Swap IFR fields.
+ */
+typedef struct _flash_swap_ifr_field_config
+{
+    uint16_t swapIndicatorAddress; /*!< Swap indicator address field.*/
+    uint16_t swapEnableWord;       /*!< Swap enable word field.*/
+    uint8_t reserved0[4];          /*!< Reserved field.*/
+#if (FSL_FEATURE_FLASH_IS_FTFE == 1)
+    uint8_t reserved1[2];     /*!< Reserved field.*/
+    uint16_t swapDisableWord; /*!< Swap disable word field.*/
+    uint8_t reserved2[4];     /*!< Reserved field.*/
+#endif
+} flash_swap_ifr_field_config_t;
+
+/*!
+ * @brief Flash Swap IFR field data.
+ */
+typedef union _flash_swap_ifr_field_data
+{
+    uint32_t flashSwapIfrData[2];                    /*!< Flash Swap IFR field data .*/
+    flash_swap_ifr_field_config_t flashSwapIfrField; /*!< Flash Swap IFR field struct.*/
+} flash_swap_ifr_field_data_t;
+
+/*!
+ * @brief Enumeration for FlexRAM load during reset option.
+ */
+typedef enum _flash_partition_flexram_load_option
+{
+    kFLASH_PartitionFlexramLoadOptionLoadedWithValidEepromData =
+        0x00U, /*!< FlexRAM is loaded with valid EEPROM data during reset sequence.*/
+    kFLASH_PartitionFlexramLoadOptionNotLoaded = 0x01U /*!< FlexRAM is not loaded during reset sequence.*/
+} flash_partition_flexram_load_option_t;
+
+/*! @brief callback type used for pflash block*/
+typedef void (*flash_callback_t)(void);
+
+/*!
+ * @brief Active flash information for current operation.
+ */
+typedef struct _flash_operation_config
+{
+    uint32_t convertedAddress;           /*!< Converted address for current flash type.*/
+    uint32_t activeSectorSize;           /*!< Sector size of current flash type.*/
+    uint32_t activeBlockSize;            /*!< Block size of current flash type.*/
+    uint32_t blockWriteUnitSize;         /*!< write unit size.*/
+    uint32_t sectorCmdAddressAligment;   /*!< Erase sector command address alignment.*/
+    uint32_t sectionCmdAddressAligment;  /*!< Program/Verify section command address alignment.*/
+    uint32_t resourceCmdAddressAligment; /*!< Read resource command address alignment.*/
+    uint32_t checkCmdAddressAligment;    /*!< Program check command address alignment.*/
+} flash_operation_config_t;
+
+/*! @brief Flash driver state information.
+ *
+ * An instance of this structure is allocated by the user of the flash driver and
+ * passed into each of the driver APIs.
+ */
+typedef struct _flash_config
+{
+    uint32_t PFlashBlockBase;                /*!< Base address of the first PFlash block */
+    uint32_t PFlashTotalSize;                /*!< Size of all combined PFlash block. */
+    uint32_t PFlashBlockCount;               /*!< Number of PFlash blocks. */
+    uint32_t PFlashSectorSize;               /*!< Size in bytes of a sector of PFlash. */
+    flash_callback_t PFlashCallback;         /*!< Callback function for flash API. */
+    uint32_t PFlashAccessSegmentSize;        /*!< Size in bytes of a access segment of PFlash. */
+    uint32_t PFlashAccessSegmentCount;       /*!< Number of PFlash access segments. */
+    uint32_t *flashExecuteInRamFunctionInfo; /*!< Info struct of flash execute-in-RAM function. */
+    uint32_t FlexRAMBlockBase;               /*!< For FlexNVM device, this is the base address of FlexRAM
+                                                  For non-FlexNVM device, this is the base address of acceleration RAM memory */
+    uint32_t FlexRAMTotalSize;               /*!< For FlexNVM device, this is the size of FlexRAM
+                                                  For non-FlexNVM device, this is the size of acceleration RAM memory */
+    uint32_t DFlashBlockBase; /*!< For FlexNVM device, this is the base address of D-Flash memory (FlexNVM memory);
+                                   For non-FlexNVM device, this field is unused */
+    uint32_t DFlashTotalSize; /*!< For FlexNVM device, this is total size of the FlexNVM memory;
+                                   For non-FlexNVM device, this field is unused */
+    uint32_t EEpromTotalSize; /*!< For FlexNVM device, this is the size in byte of EEPROM area which was partitioned
+                                 from FlexRAM;
+                                   For non-FlexNVM device, this field is unused */
+} flash_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes global flash properties structure members
+ *
+ * This function checks and initializes Flash module for the other Flash APIs.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status.
+ */
+status_t FLASH_Init(flash_config_t *config);
+
+/*!
+ * @brief Set the desired flash callback function
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param callback callback function to be stored in driver
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ */
+status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback);
+
+/*!
+ * @brief Prepare flash execute-in-RAM functions
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ */
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config);
+#endif
+
+/*@}*/
+
+/*!
+ * @name Erasing
+ * @{
+ */
+
+/*!
+ * @brief Erases entire flash
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param key value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status
+ */
+status_t FLASH_EraseAll(flash_config_t *config, uint32_t key);
+
+/*!
+ * @brief Erases flash sectors encompassed by parameters passed into function
+ *
+ * This function erases the appropriate number of flash sectors based on the
+ * desired start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be erased.
+ *              The start address does not need to be sector aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *                      to be erased. Must be word aligned.
+ * @param key value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
+
+/*!
+ * @brief Erases entire flash, including protected sectors.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param key value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD
+status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key);
+#endif
+
+/*!
+ * @brief Erases all program flash execute-only segments defined by the FXACC registers.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param key value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key);
+
+/*@}*/
+
+/*!
+ * @name Programming
+ * @{
+ */
+
+/*!
+ * @brief Programs flash with data at locations passed in through parameters
+ *
+ * This function programs the flash memory with desired data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param src Pointer to the source buffer of data that is to be programmed
+ *            into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *                      to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes);
+
+/*!
+ * @brief Programs Program Once Field through parameters
+ *
+ * This function programs the Program Once Field with desired data for a given
+ * flash area as determined by the index and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param index The index indicating which area of Program Once Field to be programmed.
+ * @param src Pointer to the source buffer of data that is to be programmed
+ *            into the Program Once Field.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *                      to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes);
+
+/*!
+ * @brief Programs flash with data at locations passed in through parameters via Program Section command
+ *
+ * This function programs the flash memory with desired data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param src Pointer to the source buffer of data that is to be programmed
+ *            into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *                      to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_SetFlexramAsRamError Failed to set flexram as RAM
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_RecoverFlexramAsEepromError Failed to recover flexram as eeprom
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD
+status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes);
+#endif
+
+/*!
+ * @brief Programs EEPROM with data at locations passed in through parameters
+ *
+ * This function programs the Emulated EEPROM with desired data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param src Pointer to the source buffer of data that is to be programmed
+ *            into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *                      to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_SetFlexramAsEepromError Failed to set flexram as eeprom.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_RecoverFlexramAsRamError Failed to recover flexram as RAM
+ */
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
+#endif
+
+/*@}*/
+
+/*!
+ * @name Reading
+ * @{
+ */
+
+/*!
+ * @brief Read resource with data at locations passed in through parameters
+ *
+ * This function reads the flash memory with desired location for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param dst Pointer to the destination buffer of data that is used to store
+ *        data to be read.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *        to be read. Must be word-aligned.
+ * @param option The resource option which indicates which area should be read back.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+status_t FLASH_ReadResource(
+    flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option);
+#endif
+
+/*!
+ * @brief Read Program Once Field through parameters
+ *
+ * This function reads the read once feild with given index and length
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param index The index indicating the area of program once field to be read.
+ * @param dst Pointer to the destination buffer of data that is used to store
+ *        data to be read.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *        to be programmed. Must be word-aligned.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes);
+
+/*@}*/
+
+/*!
+ * @name Security
+ * @{
+ */
+
+/*!
+ * @brief Returns the security state via the pointer passed into the function
+ *
+ * This function retrieves the current Flash security status, including the
+ * security enabling state and the backdoor key enabling state.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param state Pointer to the value returned for the current security status code:
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ */
+status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state);
+
+/*!
+ * @brief Allows user to bypass security with a backdoor key
+ *
+ * If the MCU is in secured state, this function will unsecure the MCU by
+ * comparing the provided backdoor key with ones in the Flash Configuration
+ * Field.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param backdoorKey Pointer to the user buffer containing the backdoor key.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey);
+
+/*@}*/
+
+/*!
+ * @name Verification
+ * @{
+ */
+
+/*!
+ * @brief Verifies erasure of entire flash at specified margin level
+ *
+ * This function will check to see if the flash have been erased to the
+ * specified read margin level.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param margin Read margin choice
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin);
+
+/*!
+ * @brief Verifies erasure of desired flash area at specified margin level
+ *
+ * This function will check the appropriate number of flash sectors based on
+ * the desired start address and length to see if the flash have been erased
+ * to the specified read margin level.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified.
+ *        The start address does not need to be sector aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *        to be verified. Must be word-aligned.
+ * @param margin Read margin choice
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin);
+
+/*!
+ * @brief Verifies programming of desired flash area at specified margin level
+ *
+ * This function verifies the data programed in the flash memory using the
+ * Flash Program Check Command and compares it with expected data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified. Must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *        to be verified. Must be word-aligned.
+ * @param expectedData Pointer to the expected data that is to be
+ *        verified against.
+ * @param margin Read margin choice
+ * @param failedAddress Pointer to returned failing address.
+ * @param failedData Pointer to returned failing data.  Some derivitives do
+ *        not included failed data as part of the FCCOBx registers.  In this
+ *        case, zeros are returned upon failure.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_VerifyProgram(flash_config_t *config,
+                             uint32_t start,
+                             uint32_t lengthInBytes,
+                             const uint32_t *expectedData,
+                             flash_margin_value_t margin,
+                             uint32_t *failedAddress,
+                             uint32_t *failedData);
+
+/*!
+ * @brief Verifies if the program flash executeonly segments have been erased to
+ *  the specified read margin level
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param margin Read margin choice
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin);
+
+/*@}*/
+
+/*!
+ * @name Protection
+ * @{
+ */
+
+/*!
+ * @brief Returns the protection state of desired flash area via the pointer passed into the function
+ *
+ * This function retrieves the current Flash protect status for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be checked. Must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *        to be checked.  Must be word-aligned.
+ * @param protection_state Pointer to the value returned for the current
+ *        protection status code for the desired flash area.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ */
+status_t FLASH_IsProtected(flash_config_t *config,
+                           uint32_t start,
+                           uint32_t lengthInBytes,
+                           flash_protection_state_t *protection_state);
+
+/*!
+ * @brief Returns the access state of desired flash area via the pointer passed into the function
+ *
+ * This function retrieves the current Flash access status for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be checked. Must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *        to be checked.  Must be word-aligned.
+ * @param access_state Pointer to the value returned for the current
+ *        access status code for the desired flash area.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ */
+status_t FLASH_IsExecuteOnly(flash_config_t *config,
+                             uint32_t start,
+                             uint32_t lengthInBytes,
+                             flash_execute_only_access_state_t *access_state);
+
+/*@}*/
+
+/*!
+ * @name Properties
+ * @{
+ */
+
+/*!
+ * @brief Returns the desired flash property.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param whichProperty The desired property from the list of properties in
+ *        enum flash_property_tag_t
+ * @param value Pointer to the value returned for the desired flash property
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_UnknownProperty unknown property tag
+ */
+status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value);
+
+/*@}*/
+
+/*!
+ * @name FlexRAM
+ * @{
+ */
+
+/*!
+ * @brief Set FlexRAM Function command
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param option The option used to set work mode of FlexRAM
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
+status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option);
+#endif
+
+/*@}*/
+
+/*!
+ * @name Swap
+ * @{
+ */
+
+/*!
+ * @brief Configure Swap function or Check the swap state of Flash Module
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param address Address used to configure the flash swap function
+ * @param option The possible option used to configure Flash Swap function or check the flash swap status
+ * @param returnInfo Pointer to the data which is used to return the information of flash swap.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
+status_t FLASH_SwapControl(flash_config_t *config,
+                           uint32_t address,
+                           flash_swap_control_option_t option,
+                           flash_swap_state_config_t *returnInfo);
+#endif
+
+/*!
+ * @brief Swap the lower half flash with the higher half flaock
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param address Address used to configure the flash swap function
+ * @param option The possible option used to configure Flash Swap function or check the flash swap status
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_SwapSystemNotInUninitialized Swap system is not in uninitialzed state
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
+status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option);
+#endif
+
+/*!
+ * @name FlexNVM
+ * @{
+ */
+
+/*!
+ * @brief Prepares the FlexNVM block for use as data flash, EEPROM backup, or a combination of both and initializes the
+ * FlexRAM.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param option The option used to set FlexRAM load behavior during reset.
+ * @param eepromDataSizeCode Determines the amount of FlexRAM used in each of the available EEPROM subsystems.
+ * @param flexnvmPartitionCode Specifies how to split the FlexNVM block between data flash memory and EEPROM backup
+ *        memory supporting EEPROM functions.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD
+status_t FLASH_ProgramPartition(flash_config_t *config,
+                                flash_partition_flexram_load_option_t option,
+                                uint32_t eepromDataSizeCode,
+                                uint32_t flexnvmPartitionCode);
+#endif
+
+/*@}*/
+
+/*!
+* @name Flash Protection Utilities
+* @{
+*/
+
+/*!
+ * @brief Set PFLASH Protection to the intended protection status.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param protectStatus The expected protect status user wants to set to PFlash protection register. Each bit is
+ * corresponding to protection of 1/32 of the total PFlash. The least significant bit is corresponding to the lowest
+ * address area of P-Flash. The most significant bit is corresponding to the highest address area of PFlash. There are
+ * two possible cases as shown below:
+ *       0: this area is protected.
+ *       1: this area is unprotected.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus);
+
+/*!
+ * @brief Get PFLASH Protection Status.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param protectStatus  Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/32 of the
+ * total PFlash. The least significant bit is corresponding to the lowest address area of PFlash. The most significant
+ * bit is corresponding to the highest address area of PFlash. Thee are two possible cases as below:
+ *       0: this area is protected.
+ *       1: this area is unprotected.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ */
+status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus);
+
+/*!
+ * @brief Set DFLASH Protection to the intended protection status.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param protectStatus The expected protect status user wants to set to DFlash protection register. Each bit is
+ * corresponding to protection of 1/8 of the total DFlash. The least significant bit is corresponding to the lowest
+ * address area of DFlash. The most significant bit is corresponding to the highest address area of  DFlash. There are
+ * two possible cases as shown below:
+ *       0: this area is protected.
+ *       1: this area is unprotected.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus);
+#endif
+
+/*!
+ * @brief Get DFLASH Protection Status.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param protectStatus  DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of
+ * the total DFlash. The least significant bit is corresponding to the lowest address area of DFlash. The most
+ * significant bit is corresponding to the highest address area of DFlash and so on. There are two possible cases as
+ * below:
+ *       0: this area is protected.
+ *       1: this area is unprotected.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported
+ */
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus);
+#endif
+
+/*!
+ * @brief Set EEPROM Protection to the intended protection status.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param protectStatus The expected protect status user wants to set to EEPROM protection register. Each bit is
+ * corresponding to protection of 1/8 of the total EEPROM. The least significant bit is corresponding to the lowest
+ * address area of EEPROM. The most significant bit is corresponding to the highest address area of EEPROM, and so on.
+ * There are two possible cases as shown below:
+ *       0: this area is protected.
+ *       1: this area is unprotected.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ */
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus);
+#endif
+
+/*!
+ * @brief Get DFLASH Protection Status.
+ *
+ * @param config Pointer to storage for the driver runtime state.
+ * @param protectStatus  DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of
+ * the total EEPROM. The least significant bit is corresponding to the lowest address area of EEPROM. The most
+ * significant bit is corresponding to the highest address area of EEPROM. There are two possible cases as below:
+ *       0: this area is protected.
+ *       1: this area is unprotected.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
+ */
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus);
+#endif
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_FLASH_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio.c
new file mode 100644
index 00000000000..ea15f00a4e7
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*< @brief user configurable flexio handle count. */
+#define FLEXIO_HANDLE_COUNT 2
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*< @brief pointer to array of FLEXIO handle. */
+static void *s_flexioHandle[FLEXIO_HANDLE_COUNT];
+
+/*< @brief pointer to array of FLEXIO IP types. */
+static void *s_flexioType[FLEXIO_HANDLE_COUNT];
+
+/*< @brief pointer to array of FLEXIO Isr. */
+static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT];
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)
+{
+    uint32_t ctrlReg = 0;
+
+    CLOCK_EnableClock(kCLOCK_Flexio0);
+
+    FLEXIO_Reset(base);
+
+    ctrlReg = base->CTRL;
+    ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
+    ctrlReg |= (FLEXIO_CTRL_DOZEN(userConfig->enableInDoze) | FLEXIO_CTRL_DBGE(userConfig->enableInDebug) |
+                FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | FLEXIO_CTRL_FLEXEN(userConfig->enableFlexio));
+
+    base->CTRL = ctrlReg;
+}
+
+void FLEXIO_Deinit(FLEXIO_Type *base)
+{
+    FLEXIO_Enable(base, false);
+    CLOCK_DisableClock(kCLOCK_Flexio0);
+}
+
+void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig)
+{
+    assert(userConfig);
+
+    userConfig->enableFlexio = true;
+    userConfig->enableInDoze = false;
+    userConfig->enableInDebug = true;
+    userConfig->enableFastAccess = false;
+}
+
+void FLEXIO_Reset(FLEXIO_Type *base)
+{
+    /*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/
+    base->CTRL |= FLEXIO_CTRL_SWRST_MASK;
+    base->CTRL = 0;
+}
+
+uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index)
+{
+    assert(index < FLEXIO_SHIFTBUF_COUNT);
+
+    uint32_t address = 0;
+
+    switch (type)
+    {
+        case kFLEXIO_ShifterBuffer:
+            address = (uint32_t) & (base->SHIFTBUF[index]);
+            break;
+
+        case kFLEXIO_ShifterBufferBitSwapped:
+            address = (uint32_t) & (base->SHIFTBUFBIS[index]);
+            break;
+
+        case kFLEXIO_ShifterBufferByteSwapped:
+            address = (uint32_t) & (base->SHIFTBUFBYS[index]);
+            break;
+
+        case kFLEXIO_ShifterBufferBitByteSwapped:
+            address = (uint32_t) & (base->SHIFTBUFBBS[index]);
+            break;
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP
+        case kFLEXIO_ShifterBufferNibbleByteSwapped:
+            address = (uint32_t) & (base->SHIFTBUFNBS[index]);
+            break;
+
+#endif
+#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP
+        case kFLEXIO_ShifterBufferHalfWordSwapped:
+            address = (uint32_t) & (base->SHIFTBUFHWS[index]);
+            break;
+
+#endif
+#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP
+        case kFLEXIO_ShifterBufferNibbleSwapped:
+            address = (uint32_t) & (base->SHIFTBUFNIS[index]);
+            break;
+
+#endif
+        default:
+            break;
+    }
+    return address;
+}
+
+void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)
+{
+    base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource)
+#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH
+                            | FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth)
+#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */
+                            | FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) |
+                            FLEXIO_SHIFTCFG_SSTART(shifterConfig->shifterStart);
+
+    base->SHIFTCTL[index] =
+        FLEXIO_SHIFTCTL_TIMSEL(shifterConfig->timerSelect) | FLEXIO_SHIFTCTL_TIMPOL(shifterConfig->timerPolarity) |
+        FLEXIO_SHIFTCTL_PINCFG(shifterConfig->pinConfig) | FLEXIO_SHIFTCTL_PINSEL(shifterConfig->pinSelect) |
+        FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode);
+}
+
+void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig)
+{
+    base->TIMCFG[index] =
+        FLEXIO_TIMCFG_TIMOUT(timerConfig->timerOutput) | FLEXIO_TIMCFG_TIMDEC(timerConfig->timerDecrement) |
+        FLEXIO_TIMCFG_TIMRST(timerConfig->timerReset) | FLEXIO_TIMCFG_TIMDIS(timerConfig->timerDisable) |
+        FLEXIO_TIMCFG_TIMENA(timerConfig->timerEnable) | FLEXIO_TIMCFG_TSTOP(timerConfig->timerStop) |
+        FLEXIO_TIMCFG_TSTART(timerConfig->timerStart);
+
+    base->TIMCMP[index] = FLEXIO_TIMCMP_CMP(timerConfig->timerCompare);
+
+    base->TIMCTL[index] = FLEXIO_TIMCTL_TRGSEL(timerConfig->triggerSelect) |
+                          FLEXIO_TIMCTL_TRGPOL(timerConfig->triggerPolarity) |
+                          FLEXIO_TIMCTL_TRGSRC(timerConfig->triggerSource) |
+                          FLEXIO_TIMCTL_PINCFG(timerConfig->pinConfig) | FLEXIO_TIMCTL_PINSEL(timerConfig->pinSelect) |
+                          FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode);
+}
+
+status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)
+{
+    assert(base);
+    assert(handle);
+    assert(isr);
+
+    uint8_t index = 0;
+
+    /* Find the an empty handle pointer to store the handle. */
+    for (index = 0; index < FLEXIO_HANDLE_COUNT; index++)
+    {
+        if (s_flexioHandle[index] == NULL)
+        {
+            /* Register FLEXIO simulated driver base, handle and isr. */
+            s_flexioType[index] = base;
+            s_flexioHandle[index] = handle;
+            s_flexioIsr[index] = isr;
+            break;
+        }
+    }
+
+    if (index == FLEXIO_HANDLE_COUNT)
+    {
+        return kStatus_OutOfRange;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+}
+
+status_t FLEXIO_UnregisterHandleIRQ(void *base)
+{
+    assert(base);
+
+    uint8_t index = 0;
+
+    /* Find the index from base address mappings. */
+    for (index = 0; index < FLEXIO_HANDLE_COUNT; index++)
+    {
+        if (s_flexioType[index] == base)
+        {
+            /* Unregister FLEXIO simulated driver handle and isr. */
+            s_flexioType[index] = NULL;
+            s_flexioHandle[index] = NULL;
+            s_flexioIsr[index] = NULL;
+            break;
+        }
+    }
+
+    if (index == FLEXIO_HANDLE_COUNT)
+    {
+        return kStatus_OutOfRange;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+}
+
+void FLEXIO_CommonIRQHandler(void)
+{
+    uint8_t index;
+
+    for (index = 0; index < FLEXIO_HANDLE_COUNT; index++)
+    {
+        if (s_flexioHandle[index])
+        {
+            s_flexioIsr[index](s_flexioType[index], s_flexioHandle[index]);
+        }
+    }
+}
+
+void FLEXIO_DriverIRQHandler(void)
+{
+    FLEXIO_CommonIRQHandler();
+}
+
+void FLEXIO0_DriverIRQHandler(void)
+{
+    FLEXIO_CommonIRQHandler();
+}
+
+void UART2_FLEXIO_DriverIRQHandler(void)
+{
+    FLEXIO_CommonIRQHandler();
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio.h
new file mode 100644
index 00000000000..40ad91803e4
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio.h
@@ -0,0 +1,706 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_FLEXIO_H_
+#define _FSL_FLEXIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexio_driver
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexIO driver version 2.0.0. */
+#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief Calculate FlexIO timer trigger.*/
+#define FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x) ((uint32_t)(x) << 1U)
+#define FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x) (((uint32_t)(x) << 2U) | 0x1U)
+#define FLEXIO_TIMER_TRIGGER_SEL_TIMn(x) (((uint32_t)(x) << 2U) | 0x3U)
+
+/*! @brief Define time of timer trigger polarity.*/
+typedef enum _flexio_timer_trigger_polarity
+{
+    kFLEXIO_TimerTriggerPolarityActiveHigh = 0x0U, /*!< Active high. */
+    kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U,  /*!< Active low. */
+} flexio_timer_trigger_polarity_t;
+
+/*! @brief Define type of timer trigger source.*/
+typedef enum _flexio_timer_trigger_source
+{
+    kFLEXIO_TimerTriggerSourceExternal = 0x0U, /*!< External trigger selected. */
+    kFLEXIO_TimerTriggerSourceInternal = 0x1U, /*!< Internal trigger selected. */
+} flexio_timer_trigger_source_t;
+
+/*! @brief Define type of timer/shifter pin configuration.*/
+typedef enum _flexio_pin_config
+{
+    kFLEXIO_PinConfigOutputDisabled = 0x0U,         /*!< Pin output disabled. */
+    kFLEXIO_PinConfigOpenDrainOrBidirection = 0x1U, /*!< Pin open drain or bidirectional output enable. */
+    kFLEXIO_PinConfigBidirectionOutputData = 0x2U,  /*!< Pin bidirectional output data. */
+    kFLEXIO_PinConfigOutput = 0x3U,                 /*!< Pin output. */
+} flexio_pin_config_t;
+
+/*! @brief Definition of pin polarity.*/
+typedef enum _flexio_pin_polarity
+{
+    kFLEXIO_PinActiveHigh = 0x0U, /*!< Active high. */
+    kFLEXIO_PinActiveLow = 0x1U,  /*!< Active low. */
+} flexio_pin_polarity_t;
+
+/*! @brief Define type of timer work mode.*/
+typedef enum _flexio_timer_mode
+{
+    kFLEXIO_TimerModeDisabled = 0x0U,        /*!< Timer Disabled. */
+    kFLEXIO_TimerModeDual8BitBaudBit = 0x1U, /*!< Dual 8-bit counters baud/bit mode. */
+    kFLEXIO_TimerModeDual8BitPWM = 0x2U,     /*!< Dual 8-bit counters PWM mode. */
+    kFLEXIO_TimerModeSingle16Bit = 0x3U,     /*!< Single 16-bit counter mode. */
+} flexio_timer_mode_t;
+
+/*! @brief Define type of timer initial output or timer reset condition.*/
+typedef enum _flexio_timer_output
+{
+    kFLEXIO_TimerOutputOneNotAffectedByReset = 0x0U,  /*!< Logic one when enabled and is not affected by timer
+                                                       reset. */
+    kFLEXIO_TimerOutputZeroNotAffectedByReset = 0x1U, /*!< Logic zero when enabled and is not affected by timer
+                                                       reset. */
+    kFLEXIO_TimerOutputOneAffectedByReset = 0x2U,     /*!< Logic one when enabled and on timer reset. */
+    kFLEXIO_TimerOutputZeroAffectedByReset = 0x3U,    /*!< Logic zero when enabled and on timer reset. */
+} flexio_timer_output_t;
+
+/*! @brief Define type of timer decrement.*/
+typedef enum _flexio_timer_decrement_source
+{
+    kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput = 0x0U,   /*!< Decrement counter on FlexIO clock, Shift clock
+                                                                equals Timer output. */
+    kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput = 0x1U,  /*!< Decrement counter on Trigger input (both edges),
+                                                                Shift clock equals Timer output. */
+    kFLEXIO_TimerDecSrcOnPinInputShiftPinInput = 0x2U,         /*!< Decrement counter on Pin input (both edges),
+                                                                Shift clock equals Pin input. */
+    kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput = 0x3U, /*!< Decrement counter on Trigger input (both edges),
+                                                                Shift clock equals Trigger input. */
+} flexio_timer_decrement_source_t;
+
+/*! @brief Define type of timer reset condition.*/
+typedef enum _flexio_timer_reset_condition
+{
+    kFLEXIO_TimerResetNever = 0x0U,                            /*!< Timer never reset. */
+    kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U,     /*!< Timer reset on Timer Pin equal to Timer Output. */
+    kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput = 0x3U, /*!< Timer reset on Timer Trigger equal to
+                                                                Timer Output. */
+    kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U,             /*!< Timer reset on Timer Pin rising edge. */
+    kFLEXIO_TimerResetOnTimerTriggerRisingEdge = 0x6U,         /*!< Timer reset on Trigger rising edge. */
+    kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U,           /*!< Timer reset on Trigger rising or falling edge. */
+} flexio_timer_reset_condition_t;
+
+/*! @brief Define type of timer disable condition.*/
+typedef enum _flexio_timer_disable_condition
+{
+    kFLEXIO_TimerDisableNever = 0x0U,                    /*!< Timer never disabled. */
+    kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U,        /*!< Timer disabled on Timer N-1 disable. */
+    kFLEXIO_TimerDisableOnTimerCompare = 0x2U,           /*!< Timer disabled on Timer compare. */
+    kFLEXIO_TimerDisableOnTimerCompareTriggerLow = 0x3U, /*!< Timer disabled on Timer compare and Trigger Low. */
+    kFLEXIO_TimerDisableOnPinBothEdge = 0x4U,            /*!< Timer disabled on Pin rising or falling edge. */
+    kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh = 0x5U, /*!< Timer disabled on Pin rising or falling edge provided
+                                                          Trigger is high. */
+    kFLEXIO_TimerDisableOnTriggerFallingEdge = 0x6U,     /*!< Timer disabled on Trigger falling edge. */
+} flexio_timer_disable_condition_t;
+
+/*! @brief Define type of timer enable condition.*/
+typedef enum _flexio_timer_enable_condition
+{
+    kFLEXIO_TimerEnabledAlways = 0x0U,                    /*!< Timer always enabled. */
+    kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U,          /*!< Timer enabled on Timer N-1 enable. */
+    kFLEXIO_TimerEnableOnTriggerHigh = 0x2U,              /*!< Timer enabled on Trigger high. */
+    kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U,       /*!< Timer enabled on Trigger high and Pin high. */
+    kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U,            /*!< Timer enabled on Pin rising edge. */
+    kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh = 0x5U, /*!< Timer enabled on Pin rising edge and Trigger high. */
+    kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U,        /*!< Timer enabled on Trigger rising edge. */
+    kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U,          /*!< Timer enabled on Trigger rising or falling edge. */
+} flexio_timer_enable_condition_t;
+
+/*! @brief Define type of timer stop bit generate condition.*/
+typedef enum _flexio_timer_stop_bit_condition
+{
+    kFLEXIO_TimerStopBitDisabled = 0x0U,                    /*!< Stop bit disabled. */
+    kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U,        /*!< Stop bit is enabled on timer compare. */
+    kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U,        /*!< Stop bit is enabled on timer disable. */
+    kFLEXIO_TimerStopBitEnableOnTimerCompareDisable = 0x3U, /*!< Stop bit is enabled on timer compare and timer
+                                                             disable. */
+} flexio_timer_stop_bit_condition_t;
+
+/*! @brief Define type of timer start bit generate condition.*/
+typedef enum _flexio_timer_start_bit_condition
+{
+    kFLEXIO_TimerStartBitDisabled = 0x0U, /*!< Start bit disabled. */
+    kFLEXIO_TimerStartBitEnabled = 0x1U,  /*!< Start bit enabled. */
+} flexio_timer_start_bit_condition_t;
+
+/*! @brief Define type of timer polarity for shifter control. */
+typedef enum _flexio_shifter_timer_polarity
+{
+    kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /* Shift on positive edge of shift clock. */
+    kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /* Shift on negative edge of shift clock. */
+} flexio_shifter_timer_polarity_t;
+
+/*! @brief Define type of shifter working mode.*/
+typedef enum _flexio_shifter_mode
+{
+    kFLEXIO_ShifterDisabled = 0x0U,            /*!< Shifter is disabled. */
+    kFLEXIO_ShifterModeReceive = 0x1U,         /*!< Receive mode. */
+    kFLEXIO_ShifterModeTransmit = 0x2U,        /*!< Transmit mode. */
+    kFLEXIO_ShifterModeMatchStore = 0x4U,      /*!< Match store mode. */
+    kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */
+#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE
+    kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing
+                                      programmable state attributes. */
+#endif                               /* FSL_FEATURE_FLEXIO_HAS_STATE_MODE */
+#if FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE
+    kFLEXIO_ShifterModeLogic = 0x7U, /*!< SHIFTBUF contents are used for implementing
+                                     programmable logic look up table. */
+#endif                               /* FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE */
+} flexio_shifter_mode_t;
+
+/*! @brief Define type of shifter input source.*/
+typedef enum _flexio_shifter_input_source
+{
+    kFLEXIO_ShifterInputFromPin = 0x0U,               /*!< Shifter input from pin. */
+    kFLEXIO_ShifterInputFromNextShifterOutput = 0x1U, /*!< Shifter input from Shifter N+1. */
+} flexio_shifter_input_source_t;
+
+/*! @brief Define of STOP bit configuration.*/
+typedef enum _flexio_shifter_stop_bit
+{
+    kFLEXIO_ShifterStopBitDisable = 0x0U, /*!< Disable shifter stop bit. */
+    kFLEXIO_ShifterStopBitLow = 0x2U,     /*!< Set shifter stop bit to logic low level. */
+    kFLEXIO_ShifterStopBitHigh = 0x3U,    /*!< Set shifter stop bit to logic high level. */
+} flexio_shifter_stop_bit_t;
+
+/*! @brief Define type of START bit configuration.*/
+typedef enum _flexio_shifter_start_bit
+{
+    kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable = 0x0U, /*!< Disable shifter start bit, transmitter loads
+                                                             data on enable. */
+    kFLEXIO_ShifterStartBitDisabledLoadDataOnShift = 0x1U,  /*!< Disable shifter start bit, transmitter loads
+                                                             data on first shift. */
+    kFLEXIO_ShifterStartBitLow = 0x2U,                      /*!< Set shifter start bit to logic low level. */
+    kFLEXIO_ShifterStartBitHigh = 0x3U,                     /*!< Set shifter start bit to logic high level. */
+} flexio_shifter_start_bit_t;
+
+/*! @brief Define FlexIO shifter buffer type*/
+typedef enum _flexio_shifter_buffer_type
+{
+    kFLEXIO_ShifterBuffer = 0x0U,               /*!< Shifter Buffer N Register. */
+    kFLEXIO_ShifterBufferBitSwapped = 0x1U,     /*!< Shifter Buffer N Bit Byte Swapped Register. */
+    kFLEXIO_ShifterBufferByteSwapped = 0x2U,    /*!< Shifter Buffer N Byte Swapped Register. */
+    kFLEXIO_ShifterBufferBitByteSwapped = 0x3U, /*!< Shifter Buffer N Bit Swapped Register. */
+#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP
+    kFLEXIO_ShifterBufferNibbleByteSwapped = 0x4U, /*!< Shifter Buffer N Nibble Byte Swapped Register. */
+#endif                                             /*FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP*/
+#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP
+    kFLEXIO_ShifterBufferHalfWordSwapped = 0x5U, /*!< Shifter Buffer N Half Word Swapped Register. */
+#endif
+#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP
+    kFLEXIO_ShifterBufferNibbleSwapped = 0x6U, /*!< Shifter Buffer N Nibble Swapped Register. */
+#endif
+} flexio_shifter_buffer_type_t;
+
+/*! @brief Define FlexIO user configuration structure. */
+typedef struct _flexio_config_
+{
+    bool enableFlexio;     /*!< Enable/disable FlexIO module */
+    bool enableInDoze;     /*!< Enable/disable FlexIO operation in doze mode */
+    bool enableInDebug;    /*!< Enable/disable FlexIO operation in debug mode */
+    bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires
+                           the FlexIO clock to be at least twice the frequency of the bus clock. */
+} flexio_config_t;
+
+/*! @brief Define FlexIO timer configuration structure. */
+typedef struct _flexio_timer_config
+{
+    /* Trigger. */
+    uint32_t triggerSelect;                          /*!< The internal trigger selection number using MACROs. */
+    flexio_timer_trigger_polarity_t triggerPolarity; /*!< Trigger Polarity. */
+    flexio_timer_trigger_source_t triggerSource;     /*!< Trigger Source, internal (see 'trgsel') or external. */
+    /* Pin. */
+    flexio_pin_config_t pinConfig;     /*!< Timer Pin Configuration. */
+    uint32_t pinSelect;                /*!< Timer Pin number Select. */
+    flexio_pin_polarity_t pinPolarity; /*!< Timer Pin Polarity. */
+    /* Timer. */
+    flexio_timer_mode_t timerMode;                  /*!< Timer work Mode. */
+    flexio_timer_output_t timerOutput;              /*!< Configures the initial state of the Timer Output and
+                                                    whether it is affected by the Timer reset. */
+    flexio_timer_decrement_source_t timerDecrement; /*!< Configures the source of the Timer decrement and the
+                                                    source of the Shift clock. */
+    flexio_timer_reset_condition_t timerReset;      /*!< Configures the condition that causes the timer counter
+                                                    (and optionally the timer output) to be reset. */
+    flexio_timer_disable_condition_t timerDisable;  /*!< Configures the condition that causes the Timer to be
+                                                    disabled and stop decrementing. */
+    flexio_timer_enable_condition_t timerEnable;    /*!< Configures the condition that causes the Timer to be
+                                                    enabled and start decrementing. */
+    flexio_timer_stop_bit_condition_t timerStop;    /*!< Timer STOP Bit generation. */
+    flexio_timer_start_bit_condition_t timerStart;  /*!< Timer STRAT Bit generation. */
+    uint32_t timerCompare;                          /*!< Value for Timer Compare N Register. */
+} flexio_timer_config_t;
+
+/*! @brief Define FlexIO shifter configuration structure. */
+typedef struct _flexio_shifter_config
+{
+    /* Timer. */
+    uint32_t timerSelect;                          /*!< Selects which Timer is used for controlling the
+                                                    logic/shift register and generating the Shift clock. */
+    flexio_shifter_timer_polarity_t timerPolarity; /*!< Timer Polarity. */
+    /* Pin. */
+    flexio_pin_config_t pinConfig;     /*!< Shifter Pin Configuration. */
+    uint32_t pinSelect;                /*!< Shifter Pin number Select. */
+    flexio_pin_polarity_t pinPolarity; /*!< Shifter Pin Polarity. */
+    /* Shifter. */
+    flexio_shifter_mode_t shifterMode; /*!< Configures the mode of the Shifter. */
+#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH
+    uint32_t parallelWidth;                    /*!< Configures the parallel width when using parallel mode.*/
+#endif                                         /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */
+    flexio_shifter_input_source_t inputSource; /*!< Selects the input source for the shifter. */
+    flexio_shifter_stop_bit_t shifterStop;     /*!< Shifter STOP bit. */
+    flexio_shifter_start_bit_t shifterStart;   /*!< Shifter START bit. */
+} flexio_shifter_config_t;
+
+/*! @brief typedef for FlexIO simulated driver interrupt handler.*/
+typedef void (*flexio_isr_t)(void *base, void *handle);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name FlexIO Initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Gets the default configuration to configure FlexIO module. The configuration
+ * can used directly for calling FLEXIO_Configure().
+ *
+ * Example:
+   @code
+   flexio_config_t config;
+   FLEXIO_GetDefaultConfig(&config);
+   @endcode
+ *
+ * @param userConfig pointer to flexio_config_t structure
+*/
+void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig);
+
+/*!
+ * @brief Configures the FlexIO with FlexIO configuration. The configuration structure
+ * can be filled by the user, or be set with default values by FLEXIO_GetDefaultConfig().
+ *
+ * Example
+   @code
+   flexio_config_t config = {
+   .enableFlexio = true,
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false
+   };
+   FLEXIO_Configure(base, &config);
+   @endcode
+ *
+ * @param base FlexIO peripheral base address
+ * @param userConfig pointer to flexio_config_t structure
+*/
+void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig);
+
+/*!
+ * @brief Gates the FlexIO clock. Call this API to stop the FlexIO clock.
+ *
+ * @note After calling this API, call the FLEXO_Init to use the FlexIO module.
+ *
+ * @param base FlexIO peripheral base address
+*/
+void FLEXIO_Deinit(FLEXIO_Type *base);
+
+/* @} */
+
+/*!
+ * @name FlexIO Basic Operation
+ * @{
+ */
+
+/*!
+ * @brief Resets the FlexIO module.
+ *
+ * @param base FlexIO peripheral base address
+*/
+void FLEXIO_Reset(FLEXIO_Type *base);
+
+/*!
+ * @brief Enables the FlexIO module operation.
+ *
+ * @param base FlexIO peripheral base address
+ * @param enable true to enable, false to disable.
+*/
+static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS
+/*!
+ * @brief Reads the input data on each of the FlexIO pins.
+ *
+ * @param base FlexIO peripheral base address
+ * @return FlexIO pin input data
+*/
+static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base)
+{
+    return base->PIN;
+}
+#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_STATE_MODE) && FSL_FEATURE_FLEXIO_HAS_STATE_MODE
+/*!
+ * @brief Gets the current state pointer for state mode use.
+ *
+ * @param base FlexIO peripheral base address
+ * @return current state pointer
+*/
+static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base)
+{
+    return ((base->SHIFTSTATE) & FLEXIO_SHIFTSTATE_STATE_MASK);
+}
+#endif /*FSL_FEATURE_FLEXIO_HAS_STATE_MODE*/
+
+/*!
+ * @brief Configures the shifter with shifter configuration. The configuration structure
+ * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper
+ * mode, select which timer controls the shifter to shift, whether to generate start bit/stop
+ *  bit, and the polarity of start bit and stop bit.
+ *
+ * Example
+   @code
+   flexio_shifter_config_t config = {
+   .timerSelect = 0,
+   .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive,
+   .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
+   .pinPolarity = kFLEXIO_PinActiveLow,
+   .shifterMode = kFLEXIO_ShifterModeTransmit,
+   .inputSource = kFLEXIO_ShifterInputFromPin,
+   .shifterStop = kFLEXIO_ShifterStopBitHigh,
+   .shifterStart = kFLEXIO_ShifterStartBitLow
+   };
+   FLEXIO_SetShifterConfig(base, &config);
+   @endcode
+ *
+ * @param base FlexIO peripheral base address
+ * @param index shifter index
+ * @param shifterConfig pointer to flexio_shifter_config_t structure
+*/
+void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig);
+/*!
+ * @brief Configures the timer with the timer configuration. The configuration structure
+ * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper
+ * mode, select trigger source for timer and the timer pin output and the timing for timer.
+ *
+ * Example
+   @code
+   flexio_timer_config_t config = {
+   .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0),
+   .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow,
+   .triggerSource = kFLEXIO_TimerTriggerSourceInternal,
+   .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
+   .pinSelect = 0,
+   .pinPolarity = kFLEXIO_PinActiveHigh,
+   .timerMode = kFLEXIO_TimerModeDual8BitBaudBit,
+   .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset,
+   .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput,
+   .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput,
+   .timerDisable = kFLEXIO_TimerDisableOnTimerCompare,
+   .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh,
+   .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable,
+   .timerStart = kFLEXIO_TimerStartBitEnabled
+   };
+   FLEXIO_SetTimerConfig(base, &config);
+   @endcode
+ *
+ * @param base FlexIO peripheral base address
+ * @param index timer index
+ * @param timerConfig pointer to flexio_timer_config_t structure
+*/
+void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig);
+
+/* @} */
+
+/*!
+ * @name FlexIO Interrupt Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask the shifter status mask which could be calculated by (1 << shifter index)
+ * @note for multiple shifter status interrupt enable, for example, two shifter status enable, could calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+*/
+static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
+{
+    base->SHIFTSIEN |= mask;
+}
+
+/*!
+ * @brief Disables the shifter status interrupt. The interrupt won't generate when the corresponding SSF is set.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask the shifter status mask which could be calculated by (1 << shifter index)
+ * @note for multiple shifter status interrupt enable, for example, two shifter status enable, could calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+*/
+static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
+{
+    base->SHIFTSIEN &= ~mask;
+}
+
+/*!
+ * @brief Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask the shifter error mask which could be calculated by (1 << shifter index)
+ * @note for multiple shifter error interrupt enable, for example, two shifter error enable, could calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+*/
+static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)
+{
+    base->SHIFTEIEN |= mask;
+}
+
+/*!
+ * @brief Disables the shifter error interrupt. The interrupt won't generate when the corresponding SEF is set.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask the shifter error mask which could be calculated by (1 << shifter index)
+ * @note for multiple shifter error interrupt enable, for example, two shifter error enable, could calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+*/
+static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)
+{
+    base->SHIFTEIEN &= ~mask;
+}
+
+/*!
+ * @brief Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask the timer status mask which could be calculated by (1 << timer index)
+ * @note for multiple timer status interrupt enable, for example, two timer status enable, could calculate
+ * the mask by using ((1 << timer index0) | (1 << timer index1))
+*/
+static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
+{
+    base->TIMIEN |= mask;
+}
+
+/*!
+ * @brief Disables the timer status interrupt. The interrupt won't generate when the corresponding SSF is set.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask the timer status mask which could be calculated by (1 << timer index)
+ * @note for multiple timer status interrupt enable, for example, two timer status enable, could calculate
+ * the mask by using ((1 << timer index0) | (1 << timer index1))
+*/
+static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
+{
+    base->TIMIEN &= ~mask;
+}
+
+/* @} */
+
+/*!
+ * @name FlexIO Status Operation
+ * @{
+ */
+
+/*!
+ * @brief Gets the shifter status flags.
+ *
+ * @param base FlexIO peripheral base address
+ * @return shifter status flags
+*/
+static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base)
+{
+    return ((base->SHIFTSTAT) & FLEXIO_SHIFTSTAT_SSF_MASK);
+}
+
+/*!
+ * @brief Clears the shifter status flags.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask the shifter status mask which could be calculated by (1 << shifter index)
+ * @note for clearing multiple shifter status flags, for example, two shifter status flags, could calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+*/
+static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask)
+{
+    base->SHIFTSTAT = mask;
+}
+
+/*!
+ * @brief Gets the shifter error flags.
+ *
+ * @param base FlexIO peripheral base address
+ * @return shifter error flags
+*/
+static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base)
+{
+    return ((base->SHIFTERR) & FLEXIO_SHIFTERR_SEF_MASK);
+}
+
+/*!
+ * @brief Clears the shifter error flags.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask the shifter error mask which could be calculated by (1 << shifter index)
+ * @note for clearing multiple shifter error flags, for example, two shifter error flags, could calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+*/
+static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask)
+{
+    base->SHIFTERR = mask;
+}
+
+/*!
+ * @brief Gets the timer status flags.
+ *
+ * @param base FlexIO peripheral base address
+ * @return timer status flags
+*/
+static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base)
+{
+    return ((base->TIMSTAT) & FLEXIO_TIMSTAT_TSF_MASK);
+}
+
+/*!
+ * @brief Clears the timer status flags.
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask the timer status mask which could be calculated by (1 << timer index)
+ * @note for clearing multiple timer status flags, for example, two timer status flags, could calculate
+ * the mask by using ((1 << timer index0) | (1 << timer index1))
+*/
+static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask)
+{
+    base->TIMSTAT = mask;
+}
+
+/* @} */
+
+/*!
+ * @name FlexIO DMA Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the shifter status DMA. The DMA request  generates when the corresponding SSF is set.
+ *
+ * @note For multiple shifter status DMA enables, for example, calculate
+ * the mask by using ((1 << shifter index0) | (1 << shifter index1))
+ *
+ * @param base FlexIO peripheral base address
+ * @param mask the shifter status mask which could be calculated by (1 << shifter index)
+ * @param enable True to enable, false to disable.
+*/
+static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable)
+{
+    if (enable)
+    {
+        base->SHIFTSDEN |= mask;
+    }
+    else
+    {
+        base->SHIFTSDEN &= ~mask;
+    }
+}
+
+/*!
+ * @brief Gets the shifter buffer address for the DMA transfer usage.
+ *
+ * @param base FlexIO peripheral base address
+ * @param type shifter type of flexio_shifter_buffer_type_t
+ * @param index shifter index
+ * @return corresponding shifter buffer index
+*/
+uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index);
+
+/*!
+ * @brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral.
+ *
+ * @param base pointer to FlexIO simulated peripheral type.
+ * @param handle pointer to handler for FlexIO simulated peripheral.
+ * @param isr FlexIO simulated peripheral interrupt handler.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+*/
+status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr);
+
+/*!
+ * @brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral.
+ *
+ * @param base pointer to FlexIO simulated peripheral type.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+*/
+status_t FLEXIO_UnregisterHandleIRQ(void *base);
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+/*@}*/
+
+#endif /*_FSL_FLEXIO_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera.c
new file mode 100644
index 00000000000..fa7cc9bd29c
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_camera.h"
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+void FLEXIO_CAMERA_GetDefaultConfig(flexio_camera_config_t *config)
+{
+    assert(config);
+
+    config->enablecamera = false;
+    config->enableInDoze = false;
+    config->enableInDebug = false;
+    config->enableFastAccess = false;
+}
+
+void FLEXIO_CAMERA_Init(FLEXIO_CAMERA_Type *base, const flexio_camera_config_t *config)
+{
+    assert(base && config);
+
+    volatile uint32_t i = 0;
+    volatile uint32_t controlVal = 0;
+
+    /* Ungate flexio clock. */
+    CLOCK_EnableClock(kCLOCK_Flexio0);
+
+    flexio_shifter_config_t shifterConfig;
+    flexio_timer_config_t timerConfig;
+
+    /* Clear the shifterConfig & timerConfig struct. */
+    memset(&shifterConfig, 0, sizeof(shifterConfig));
+    memset(&timerConfig, 0, sizeof(timerConfig));
+
+    /* Reset flexio before configuration. */
+    FLEXIO_Reset(base->flexioBase);
+
+    /* Configure flexio camera */
+    controlVal = base->flexioBase->CTRL;
+    controlVal &=
+        ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
+    controlVal |= (FLEXIO_CTRL_DOZEN(config->enableInDoze) | FLEXIO_CTRL_DBGE(config->enableInDebug) |
+                   FLEXIO_CTRL_FASTACC(config->enableFastAccess) | FLEXIO_CTRL_FLEXEN(config->enablecamera));
+
+    base->flexioBase->CTRL = controlVal;
+
+    /* FLEXIO_CAMERA shifter config */
+    shifterConfig.timerSelect = base->timerIdx;
+    shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+    shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect = base->datPinStartIdx;
+    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
+    shifterConfig.parallelWidth = FLEXIO_CAMERA_PARALLEL_DATA_WIDTH - 1U;
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromNextShifterOutput;
+    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
+    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    /* Configure the shifters as FIFO buffer. */
+    for (i = base->shifterStartIdx; i < (base->shifterStartIdx + base->shifterCount - 1U); i++)
+    {
+        FLEXIO_SetShifterConfig(base->flexioBase, i, &shifterConfig);
+    }
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    FLEXIO_SetShifterConfig(base->flexioBase, i, &shifterConfig);
+
+    /* FLEXIO_CAMERA timer config, the PCLK's clk is source of timer to drive the shifter, the HREF is the selecting
+     * signal for available data. */
+    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->hrefPinIdx);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
+    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect = base->pclkPinIdx;
+    timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
+    timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
+    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
+    timerConfig.timerReset = kFLEXIO_TimerResetOnTimerTriggerRisingEdge;
+    timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge;
+    timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge;
+    timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
+    timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
+    timerConfig.timerCompare = 8U * base->shifterCount - 1U;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIdx, &timerConfig);
+    /* Clear flags. */
+    FLEXIO_ClearShifterErrorFlags(base->flexioBase, ((1U << (base->shifterCount)) - 1U) << (base->shifterStartIdx));
+    FLEXIO_ClearTimerStatusFlags(base->flexioBase, 1U << (base->timerIdx));
+}
+
+void FLEXIO_CAMERA_Deinit(FLEXIO_CAMERA_Type *base)
+{
+    /* Disable FLEXIO CAMERA module. */
+    FLEXIO_CAMERA_Enable(base, false);
+
+    /* Gate flexio clock. */
+    CLOCK_DisableClock(kCLOCK_Flexio0);
+}
+
+uint32_t FLEXIO_CAMERA_GetStatusFlags(FLEXIO_CAMERA_Type *base)
+{
+    uint32_t status = 0;
+    status = ((FLEXIO_GetShifterStatusFlags(base->flexioBase) >> (base->shifterStartIdx)) &
+              ((1U << (base->shifterCount)) - 1U));
+    return status;
+}
+
+void FLEXIO_CAMERA_ClearStatusFlags(FLEXIO_CAMERA_Type *base, uint32_t mask)
+{
+    if (mask & kFLEXIO_CAMERA_RxDataRegFullFlag)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, ((1U << (base->shifterCount)) - 1U)
+                                                             << (base->shifterStartIdx));
+    }
+    if (mask & kFLEXIO_CAMERA_RxErrorFlag)
+    { /* Clear error flags if they are asserted to make sure the buffer would be available. */
+        FLEXIO_ClearShifterErrorFlags(base->flexioBase, ((1U << (base->shifterCount)) - 1U) << (base->shifterStartIdx));
+    }
+}
+
+void FLEXIO_CAMERA_EnableInterrupt(FLEXIO_CAMERA_Type *base)
+{
+    FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << (base->shifterStartIdx));
+}
+
+void FLEXIO_CAMERA_DisableInterrupt(FLEXIO_CAMERA_Type *base)
+{
+    FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << (base->shifterStartIdx));
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera.h
new file mode 100644
index 00000000000..f4e851781f9
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera.h
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_FLEXIO_CAMERA_H_
+#define _FSL_FLEXIO_CAMERA_H_
+
+#include "fsl_common.h"
+#include "fsl_flexio.h"
+
+/*!
+ * @addtogroup flexio_camera
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexIO camera driver version 2.1.0. */
+#define FSL_FLEXIO_CAMERA_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*@}*/
+
+/*! @brief Define the camera CPI interface is constantly 8-bit width. */
+#define FLEXIO_CAMERA_PARALLEL_DATA_WIDTH (8U)
+
+/*! @brief Error codes for the CAMERA driver. */
+enum _flexio_camera_status
+{
+    kStatus_FLEXIO_CAMERA_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_CAMERA, 0), /*!< Receiver is busy. */
+    kStatus_FLEXIO_CAMERA_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_CAMERA, 1), /*!< CAMERA receiver is idle. */
+};
+
+/*! @brief Define FlexIO CAMERA status mask. */
+enum _flexio_camera_status_flags
+{
+    kFLEXIO_CAMERA_RxDataRegFullFlag = 0x1U, /*!< Receive buffer full flag. */
+    kFLEXIO_CAMERA_RxErrorFlag = 0x2U,       /*!< Receive buffer error flag. */
+};
+
+/*!
+ * @brief Define structure of configuring the FlexIO camera device.
+ */
+typedef struct _flexio_camera_type
+{
+    FLEXIO_Type *flexioBase; /*!< FlexIO module base address. */
+    uint32_t datPinStartIdx; /*!< First data pin (D0) index for flexio_camera.
+                                  Then the successive following FLEXIO_CAMERA_DATA_WIDTH-1 pins
+                                  would be used as D1-D7.*/
+    uint32_t pclkPinIdx;     /*!< Pixel clock pin (PCLK) index for flexio_camera. */
+    uint32_t hrefPinIdx;     /*!< Horizontal sync pin (HREF) index for flexio_camera. */
+
+    uint32_t shifterStartIdx; /*!< First shifter index used for flexio_camera data FIFO. */
+    uint32_t shifterCount;    /*!< The count of shifters that are used as flexio_camera data FIFO. */
+    uint32_t timerIdx;        /*!< Timer index used for flexio_camera in FlexIO. */
+} FLEXIO_CAMERA_Type;
+
+/*! @brief Define FlexIO camera user configuration structure. */
+typedef struct _flexio_camera_config
+{
+    bool enablecamera;     /*!< Enable/disable FlexIO camera TX & RX. */
+    bool enableInDoze;     /*!< Enable/disable FlexIO operation in doze mode*/
+    bool enableInDebug;    /*!< Enable/disable FlexIO operation in debug mode*/
+    bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers,
+                            fast access requires the FlexIO clock to be at least
+                            twice the frequency of the bus clock. */
+} flexio_camera_config_t;
+
+/*! @brief Define FlexIO CAMERA transfer structure. */
+typedef struct _flexio_camera_transfer
+{
+    uint32_t dataAddress; /*!< Transfer buffer*/
+    uint32_t dataNum;     /*!< Transfer num*/
+} flexio_camera_transfer_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name Initialize and configuration
+ * @{
+ */
+
+/*!
+ * @brief Ungates the FlexIO clock, reset the FlexIO module and do FlexIO CAMERA
+ * hardware configuration.
+ *
+ * @param base pointer to FLEXIO_CAMERA_Type structure
+ * @param config pointer to flexio_camera_config_t structure
+*/
+void FLEXIO_CAMERA_Init(FLEXIO_CAMERA_Type *base, const flexio_camera_config_t *config);
+
+/*!
+ * @brief Disables the FlexIO CAMERA and gate the FlexIO clock.
+ *
+ * @note After calling this API, user need to call FLEXO_CAMERA_Init to use the FlexIO CAMERA module.
+ *
+ * @param base pointer to FLEXIO_CAMERA_Type structure
+*/
+void FLEXIO_CAMERA_Deinit(FLEXIO_CAMERA_Type *base);
+
+/*!
+ * @brief Get the default configuration to configure FlexIO CAMERA. The configuration
+ * could be used directly for calling FLEXIO_CAMERA_Init().
+ * Example:
+   @code
+   flexio_camera_config_t config;
+   FLEXIO_CAMERA_GetDefaultConfig(&userConfig);
+   @endcode
+ * @param config pointer to flexio_camera_config_t structure
+*/
+void FLEXIO_CAMERA_GetDefaultConfig(flexio_camera_config_t *config);
+
+/*!
+ * @brief Enables/disables the FlexIO CAMERA module operation.
+ *
+ * @param base pointer to FLEXIO_CAMERA_Type
+ * @param enable True to enable, false to disable.
+*/
+static inline void FLEXIO_CAMERA_Enable(FLEXIO_CAMERA_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+    else
+    {
+        base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the FlexIO CAMERA status flags.
+ *
+ * @param base pointer to FLEXIO_CAMERA_Type structure
+ * @return FlexIO shifter status flags
+ *          @arg FLEXIO_SHIFTSTAT_SSF_MASK
+ *          @arg 0
+*/
+uint32_t FLEXIO_CAMERA_GetStatusFlags(FLEXIO_CAMERA_Type *base);
+
+/*!
+ * @brief Clears the receive buffer full flag manually.
+ *
+ * @param base pointer to the device.
+ * @param mask status flag
+ *      The parameter could be any combination of the following values:
+ *          @arg kFLEXIO_CAMERA_RxDataRegFullFlag
+ *          @arg kFLEXIO_CAMERA_RxErrorFlag
+ */
+void FLEXIO_CAMERA_ClearStatusFlags(FLEXIO_CAMERA_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Switches on the interrupt for receive buffer full event.
+ *
+ * @param base pointer to the device.
+ */
+void FLEXIO_CAMERA_EnableInterrupt(FLEXIO_CAMERA_Type *base);
+
+/*!
+ * @brief Switches off the interrupt for receive buffer full event.
+ *
+ * @param base pointer to the device.
+ *
+ */
+void FLEXIO_CAMERA_DisableInterrupt(FLEXIO_CAMERA_Type *base);
+
+/*! @} */
+
+/*!
+ * @name DMA support
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the FlexIO CAMERA receive DMA.
+ *
+ * @param base pointer to FLEXIO_CAMERA_Type structure
+ * @param enable True to enable, false to disable.
+ *
+ *    The FlexIO camera mode can't work without the DMA or EDMA support,
+ *    Usually, it needs at least two DMA or EDMA channel, one for transferring data from
+ *    camera, such as 0V7670 to FlexIO buffer, another is for transferring data from FlexIO
+ *    buffer to LCD.
+ *
+ */
+static inline void FLEXIO_CAMERA_EnableRxDMA(FLEXIO_CAMERA_Type *base, bool enable)
+{
+    FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterStartIdx, enable);
+}
+
+/*!
+ * @brief Gets the data from the receive buffer.
+ *
+ * @param base pointer to the device.
+ * @return data pointer to the buffer that would keep the data with count of base->shifterCount .
+ */
+static inline uint32_t FLEXIO_CAMERA_GetRxBufferAddress(FLEXIO_CAMERA_Type *base)
+{
+    return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterStartIdx);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+
+/*@}*/
+
+#endif /*_FSL_FLEXIO_CAMERA_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera_edma.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera_edma.c
new file mode 100644
index 00000000000..a96fa4818d3
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera_edma.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_camera_edma.h"
+#include "fsl_dmamux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! Structure definition for camera_edma_private_handle_t. The structure is private. */
+typedef struct _flexio_camera_edma_private_handle
+{
+    FLEXIO_CAMERA_Type *base;
+    flexio_camera_edma_handle_t *handle;
+} flexio_camera_edma_private_handle_t;
+
+/* CAMERA EDMA transfer handle. */
+enum _flexio_camera_edma_tansfer_states
+{
+    kFLEXIO_CAMERA_RxIdle, /* RX idle. */
+    kFLEXIO_CAMERA_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*< @brief user configurable flexio camera handle count. */
+#define FLEXIO_CAMERA_HANDLE_COUNT 1
+
+/*<! Private handle only used for internally. */
+static flexio_camera_edma_private_handle_t s_edmaPrivateHandle[FLEXIO_CAMERA_HANDLE_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO CAMERA EDMA receive finished callback function.
+ *
+ * This function is called when FLEXIO CAMERA EDMA receive finished. It disables the CAMERA
+ * RX EDMA request and sends @ref kStatus_FLEXIO_CAMERA_RxIdle to CAMERA callback.
+ *
+ * @param handle The EDMA handle.
+ * @param param Callback function parameter.
+ */
+static void FLEXIO_CAMERA_TransferReceiveEDMACallback(edma_handle_t *handle,
+                                                      void *param,
+                                                      bool transferDone,
+                                                      uint32_t tcds);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void FLEXIO_CAMERA_TransferReceiveEDMACallback(edma_handle_t *handle,
+                                                      void *param,
+                                                      bool transferDone,
+                                                      uint32_t tcds)
+{
+    flexio_camera_edma_private_handle_t *cameraPrivateHandle = (flexio_camera_edma_private_handle_t *)param;
+
+    /* Avoid the warning for unused variables. */
+    handle = handle;
+    tcds = tcds;
+
+    if (transferDone)
+    {
+        FLEXIO_CAMERA_TransferAbortReceiveEDMA(cameraPrivateHandle->base, cameraPrivateHandle->handle);
+
+        if (cameraPrivateHandle->handle->callback)
+        {
+            cameraPrivateHandle->handle->callback(cameraPrivateHandle->base, cameraPrivateHandle->handle,
+                                                  kStatus_FLEXIO_CAMERA_RxIdle, cameraPrivateHandle->handle->userData);
+        }
+    }
+}
+status_t FLEXIO_CAMERA_TransferCreateHandleEDMA(FLEXIO_CAMERA_Type *base,
+                                                flexio_camera_edma_handle_t *handle,
+                                                flexio_camera_edma_transfer_callback_t callback,
+                                                void *userData,
+                                                edma_handle_t *rxEdmaHandle)
+{
+    assert(handle);
+
+    uint8_t index = 0;
+
+    /* Find the an empty handle pointer to store the handle. */
+    for (index = 0; index < FLEXIO_CAMERA_HANDLE_COUNT; index++)
+    {
+        if (s_edmaPrivateHandle[index].base == NULL)
+        {
+            s_edmaPrivateHandle[index].base = base;
+            s_edmaPrivateHandle[index].handle = handle;
+            break;
+        }
+    }
+
+    if (index == FLEXIO_CAMERA_HANDLE_COUNT)
+    {
+        return kStatus_OutOfRange;
+    }
+
+    s_edmaPrivateHandle[index].base = base;
+    s_edmaPrivateHandle[index].handle = handle;
+
+    memset(handle, 0, sizeof(*handle));
+
+    handle->rxState = kFLEXIO_CAMERA_RxIdle;
+    handle->rxEdmaHandle = rxEdmaHandle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Configure RX. */
+    if (rxEdmaHandle)
+    {
+        EDMA_SetCallback(handle->rxEdmaHandle, FLEXIO_CAMERA_TransferReceiveEDMACallback, &s_edmaPrivateHandle);
+    }
+
+    return kStatus_Success;
+}
+
+status_t FLEXIO_CAMERA_TransferReceiveEDMA(FLEXIO_CAMERA_Type *base,
+                                           flexio_camera_edma_handle_t *handle,
+                                           flexio_camera_transfer_t *xfer)
+{
+    assert(handle->rxEdmaHandle);
+
+    edma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous RX not finished. */
+    if (kFLEXIO_CAMERA_RxBusy == handle->rxState)
+    {
+        status = kStatus_FLEXIO_CAMERA_RxBusy;
+    }
+    else
+    {
+        handle->rxState = kFLEXIO_CAMERA_RxBusy;
+
+        /* Prepare transfer. */
+        EDMA_PrepareTransfer(&xferConfig, (void *)FLEXIO_CAMERA_GetRxBufferAddress(base), 32, (void *)xfer->dataAddress,
+                             32, 32, xfer->dataNum, kEDMA_PeripheralToMemory);
+
+        /* Submit transfer. */
+        EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig);
+        EDMA_StartTransfer(handle->rxEdmaHandle);
+        /* Enable CAMERA RX EDMA. */
+        FLEXIO_CAMERA_EnableRxDMA(base, true);
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void FLEXIO_CAMERA_TransferAbortReceiveEDMA(FLEXIO_CAMERA_Type *base, flexio_camera_edma_handle_t *handle)
+{
+    assert(handle->rxEdmaHandle);
+
+    /* Disable CAMERA RX EDMA. */
+    FLEXIO_CAMERA_EnableRxDMA(base, false);
+
+    /* Stop transfer. */
+    EDMA_StopTransfer(handle->rxEdmaHandle);
+
+    handle->rxState = kFLEXIO_CAMERA_RxIdle;
+}
+
+status_t FLEXIO_CAMERA_TransferGetReceiveCountEDMA(FLEXIO_CAMERA_Type *base,
+                                                   flexio_camera_edma_handle_t *handle,
+                                                   size_t *count)
+{
+    assert(handle->rxEdmaHandle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (kFLEXIO_CAMERA_RxBusy == handle->rxState)
+    {
+        *count = (handle->rxSize - EDMA_GetRemainingBytes(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel));
+    }
+    else
+    {
+        *count = handle->rxSize;
+    }
+
+    return kStatus_Success;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera_edma.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera_edma.h
new file mode 100644
index 00000000000..68cde163672
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_camera_edma.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_FLEXIO_CAMERA_EDMA_H_
+#define _FSL_FLEXIO_CAMERA_EDMA_H_
+
+#include "fsl_flexio_camera.h"
+#include "fsl_dmamux.h"
+#include "fsl_edma.h"
+
+/*!
+ * @addtogroup flexio_edma_camera
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Forward declaration of the handle typedef. */
+typedef struct _flexio_camera_edma_handle flexio_camera_edma_handle_t;
+
+/*! @brief CAMERA transfer callback function. */
+typedef void (*flexio_camera_edma_transfer_callback_t)(FLEXIO_CAMERA_Type *base,
+                                                       flexio_camera_edma_handle_t *handle,
+                                                       status_t status,
+                                                       void *userData);
+
+/*!
+* @brief CAMERA eDMA handle
+*/
+struct _flexio_camera_edma_handle
+{
+    flexio_camera_edma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                                  /*!< CAMERA callback function parameter.*/
+    size_t rxSize;                                   /*!< Total bytes to be received. */
+    edma_handle_t *rxEdmaHandle;                     /*!< The eDMA RX channel used. */
+    volatile uint8_t rxState;                        /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the camera handle, which is used in transactional functions.
+ *
+ * @param base pointer to FLEXIO_CAMERA_Type.
+ * @param handle Pointer to flexio_camera_edma_handle_t structure.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ * @param rxEdmaHandle User requested DMA handle for RX DMA transfer.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO camera eDMA type/handle table out of range.
+ */
+status_t FLEXIO_CAMERA_TransferCreateHandleEDMA(FLEXIO_CAMERA_Type *base,
+                                                flexio_camera_edma_handle_t *handle,
+                                                flexio_camera_edma_transfer_callback_t callback,
+                                                void *userData,
+                                                edma_handle_t *rxEdmaHandle);
+
+/*!
+ * @brief Receives data using eDMA.
+ *
+ * This function receives data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base Pointer to the FLEXIO_CAMERA_Type.
+ * @param handle Pointer to the flexio_camera_edma_handle_t structure.
+ * @param xfer CAMERA eDMA transfer structure, see #flexio_camera_transfer_t.
+ * @retval kStatus_Success if succeeded, others failed.
+ * @retval kStatus_CAMERA_RxBusy Previous transfer on going.
+ */
+status_t FLEXIO_CAMERA_TransferReceiveEDMA(FLEXIO_CAMERA_Type *base,
+                                           flexio_camera_edma_handle_t *handle,
+                                           flexio_camera_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the receive data which used the eDMA.
+ *
+ * This function aborts the receive data which used the eDMA.
+ *
+ * @param base Pointer to the FLEXIO_CAMERA_Type.
+ * @param handle Pointer to the flexio_camera_edma_handle_t structure.
+ */
+void FLEXIO_CAMERA_TransferAbortReceiveEDMA(FLEXIO_CAMERA_Type *base, flexio_camera_edma_handle_t *handle);
+
+/*!
+ * @brief Gets the remaining bytes to be received.
+ *
+ * This function gets the number of bytes still not received.
+ *
+ * @param base Pointer to the FLEXIO_CAMERA_Type.
+ * @param handle Pointer to the flexio_camera_edma_handle_t structure.
+ * @param count Number of bytes sent so far by the non-blocking transaction.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_InvalidArgument The count parameter is invalid.
+ */
+status_t FLEXIO_CAMERA_TransferGetReceiveCountEDMA(FLEXIO_CAMERA_Type *base,
+                                                   flexio_camera_edma_handle_t *handle,
+                                                   size_t *count);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_CAMERA_EDMA_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2c_master.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2c_master.c
new file mode 100644
index 00000000000..f19c3a73777
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2c_master.c
@@ -0,0 +1,763 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_i2c_master.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief  FLEXIO I2C transfer state */
+enum _flexio_i2c_master_transfer_states
+{
+    kFLEXIO_I2C_Idle = 0x0U,             /*!< I2C bus idle */
+    kFLEXIO_I2C_CheckAddress = 0x1U,     /*!< 7-bit address check state */
+    kFLEXIO_I2C_SendCommand = 0x2U,      /*!< Send command byte phase */
+    kFLEXIO_I2C_SendData = 0x3U,         /*!< Send data transfer phase*/
+    kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/
+    kFLEXIO_I2C_ReceiveData = 0x5U,      /*!< Receive data transfer phase*/
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Set up master transfer, send slave address and decide the initial
+ * transfer state.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * @param transfer pointer to flexio_i2c_master_transfer_t structure
+ */
+static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base,
+                                                          flexio_i2c_master_handle_t *handle,
+                                                          flexio_i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Master run transfer state machine to perform a byte of transfer.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * @param statusFlags flexio i2c hardware status
+ * @retval kStatus_Success Successfully run state machine
+ * @retval kStatus_FLEXIO_I2C_Nak Receive Nak during transfer
+ */
+static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
+                                                         flexio_i2c_master_handle_t *handle,
+                                                         uint32_t statusFlags);
+
+/*!
+ * @brief Complete transfer, disable interrupt and call callback.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * @param status flexio transfer status
+ */
+static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
+                                              flexio_i2c_master_handle_t *handle,
+                                              status_t status);
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base,
+                                                          flexio_i2c_master_handle_t *handle,
+                                                          flexio_i2c_master_transfer_t *xfer)
+{
+    bool needRestart;
+    uint32_t byteCount;
+
+    /* Init the handle member. */
+    handle->transfer.slaveAddress = xfer->slaveAddress;
+    handle->transfer.direction = xfer->direction;
+    handle->transfer.subaddress = xfer->subaddress;
+    handle->transfer.subaddressSize = xfer->subaddressSize;
+    handle->transfer.data = xfer->data;
+    handle->transfer.dataSize = xfer->dataSize;
+    handle->transfer.flags = xfer->flags;
+    handle->transferSize = xfer->dataSize;
+
+    /* Initial state, i2c check address state. */
+    handle->state = kFLEXIO_I2C_CheckAddress;
+
+    /* Clear all status before transfer. */
+    FLEXIO_I2C_MasterClearStatusFlags(base, kFLEXIO_I2C_ReceiveNakFlag);
+
+    /* Calculate whether need to send re-start. */
+    needRestart = (handle->transfer.subaddressSize != 0) && (handle->transfer.direction == kFLEXIO_I2C_Read);
+
+    /* Calculate total byte count in a frame. */
+    byteCount = 1;
+
+    if (!needRestart)
+    {
+        byteCount += handle->transfer.dataSize;
+    }
+
+    if (handle->transfer.subaddressSize != 0)
+    {
+        byteCount += handle->transfer.subaddressSize;
+        /* Next state, send command byte. */
+        handle->state = kFLEXIO_I2C_SendCommand;
+    }
+
+    /* Configure data count. */
+    if (FLEXIO_I2C_MasterSetTransferCount(base, byteCount) != kStatus_Success)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
+    {
+    }
+
+    /* Send address byte first. */
+    if (needRestart)
+    {
+        FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Write);
+    }
+    else
+    {
+        FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, handle->transfer.direction);
+    }
+
+    return kStatus_Success;
+}
+
+static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
+                                                         flexio_i2c_master_handle_t *handle,
+                                                         uint32_t statusFlags)
+{
+    if (statusFlags & kFLEXIO_I2C_ReceiveNakFlag)
+    {
+        /* Clear receive nak flag. */
+        FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
+
+        if ((!((handle->state == kFLEXIO_I2C_SendData) && (handle->transfer.dataSize == 0U))) &&
+            (!(((handle->state == kFLEXIO_I2C_ReceiveData) || (handle->state == kFLEXIO_I2C_ReceiveDataBegin)) &&
+               (handle->transfer.dataSize == 1U))))
+        {
+            FLEXIO_I2C_MasterReadByte(base);
+
+            FLEXIO_I2C_MasterAbortStop(base);
+
+            handle->state = kFLEXIO_I2C_Idle;
+
+            return kStatus_FLEXIO_I2C_Nak;
+        }
+    }
+
+    if (handle->state == kFLEXIO_I2C_CheckAddress)
+    {
+        if (handle->transfer.direction == kFLEXIO_I2C_Write)
+        {
+            /* Next state, send data. */
+            handle->state = kFLEXIO_I2C_SendData;
+        }
+        else
+        {
+            /* Next state, receive data begin. */
+            handle->state = kFLEXIO_I2C_ReceiveDataBegin;
+        }
+    }
+
+    if ((statusFlags & kFLEXIO_I2C_RxFullFlag) && (handle->state != kFLEXIO_I2C_ReceiveData))
+    {
+        FLEXIO_I2C_MasterReadByte(base);
+    }
+
+    switch (handle->state)
+    {
+        case kFLEXIO_I2C_SendCommand:
+            if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
+            {
+                if (handle->transfer.subaddressSize > 0)
+                {
+                    handle->transfer.subaddressSize--;
+                    FLEXIO_I2C_MasterWriteByte(
+                        base, ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)));
+
+                    if (handle->transfer.subaddressSize == 0)
+                    {
+                        /* Load re-start in advance. */
+                        if (handle->transfer.direction == kFLEXIO_I2C_Read)
+                        {
+                            while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
+                            {
+                            }
+                            FLEXIO_I2C_MasterRepeatedStart(base);
+                        }
+                    }
+                }
+                else
+                {
+                    if (handle->transfer.direction == kFLEXIO_I2C_Write)
+                    {
+                        /* Next state, send data. */
+                        handle->state = kFLEXIO_I2C_SendData;
+
+                        /* Send first byte of data. */
+                        if (handle->transfer.dataSize > 0)
+                        {
+                            FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
+
+                            handle->transfer.data++;
+                            handle->transfer.dataSize--;
+                        }
+                    }
+                    else
+                    {
+                        FLEXIO_I2C_MasterSetTransferCount(base, (handle->transfer.dataSize + 1));
+                        FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Read);
+
+                        /* Next state, receive data begin. */
+                        handle->state = kFLEXIO_I2C_ReceiveDataBegin;
+                    }
+                }
+            }
+            break;
+
+        /* Send command byte. */
+        case kFLEXIO_I2C_SendData:
+            if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
+            {
+                /* Send one byte of data. */
+                if (handle->transfer.dataSize > 0)
+                {
+                    FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
+
+                    handle->transfer.data++;
+                    handle->transfer.dataSize--;
+                }
+                else
+                {
+                    FLEXIO_I2C_MasterStop(base);
+                    handle->state = kFLEXIO_I2C_Idle;
+                }
+            }
+            break;
+
+        case kFLEXIO_I2C_ReceiveDataBegin:
+            if (statusFlags & kFLEXIO_I2C_RxFullFlag)
+            {
+                handle->state = kFLEXIO_I2C_ReceiveData;
+            }
+            else if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
+            {
+                /* Read one byte of data. */
+                FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
+
+                /* Send nak at the last receive byte. */
+                if (handle->transfer.dataSize == 1)
+                {
+                    FLEXIO_I2C_MasterEnableAck(base, false);
+                    while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
+                    {
+                    }
+                    FLEXIO_I2C_MasterStop(base);
+                }
+                else
+                {
+                    FLEXIO_I2C_MasterEnableAck(base, true);
+                }
+            }
+            else
+            {
+            }
+            break;
+
+        case kFLEXIO_I2C_ReceiveData:
+            if (statusFlags & kFLEXIO_I2C_RxFullFlag)
+            {
+                *handle->transfer.data = FLEXIO_I2C_MasterReadByte(base);
+                handle->transfer.data++;
+                /* Receive one byte of data. */
+                if (handle->transfer.dataSize--)
+                {
+                    if (handle->transfer.dataSize != 0)
+                    {
+                        FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
+                    }
+                    else
+                    {
+                        FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_RxFullInterruptEnable);
+                        handle->state = kFLEXIO_I2C_Idle;
+                    }
+
+                    /* Send nak at the last receive byte. */
+                    if (handle->transfer.dataSize == 1)
+                    {
+                        FLEXIO_I2C_MasterEnableAck(base, false);
+                        while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
+                        {
+                        }
+                        FLEXIO_I2C_MasterStop(base);
+                    }
+                }
+            }
+            break;
+
+        default:
+            break;
+    }
+
+    return kStatus_Success;
+}
+
+static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
+                                              flexio_i2c_master_handle_t *handle,
+                                              status_t status)
+{
+    FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable);
+
+    if (handle->completionCallback)
+    {
+        handle->completionCallback(base, handle, status, handle->userData);
+    }
+}
+
+void FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
+{
+    assert(base && masterConfig);
+
+    flexio_shifter_config_t shifterConfig;
+    flexio_timer_config_t timerConfig;
+    uint32_t controlVal = 0;
+
+    memset(&shifterConfig, 0, sizeof(shifterConfig));
+    memset(&timerConfig, 0, sizeof(timerConfig));
+
+    /* Ungate flexio clock. */
+    CLOCK_EnableClock(kCLOCK_Flexio0);
+
+    FLEXIO_Reset(base->flexioBase);
+
+    /* Do hardware configuration. */
+    /* 1. Configure the shifter 0 for tx. */
+    shifterConfig.timerSelect = base->timerIndex[1];
+    shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+    shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
+    shifterConfig.pinSelect = base->SDAPinIndex;
+    shifterConfig.pinPolarity = kFLEXIO_PinActiveLow;
+    shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
+    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
+
+    /* 2. Configure the shifter 1 for rx. */
+    shifterConfig.timerSelect = base->timerIndex[1];
+    shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+    shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect = base->SDAPinIndex;
+    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
+    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
+
+    /*3. Configure the timer 0 for generating bit clock. */
+    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
+    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
+    timerConfig.pinSelect = base->SCLPinIndex;
+    timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
+    timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
+    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput;
+    timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
+    timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
+    timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
+    timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
+
+    /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1. */
+    timerConfig.timerCompare = (srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
+
+    /* 4. Configure the timer 1 for controlling shifters. */
+    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
+    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect = base->SCLPinIndex;
+    timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
+    timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
+    timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
+    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
+    timerConfig.timerReset = kFLEXIO_TimerResetNever;
+    timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
+    timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
+    timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare;
+    timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
+
+    /* Set TIMCMP[15:0] = (number of bits x 2) - 1. */
+    timerConfig.timerCompare = 8 * 2 - 1;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
+
+    /* Configure FLEXIO I2C Master. */
+    controlVal = base->flexioBase->CTRL;
+    controlVal &=
+        ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
+    controlVal |=
+        (FLEXIO_CTRL_DOZEN(masterConfig->enableInDoze) | FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) |
+         FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster));
+
+    base->flexioBase->CTRL = controlVal;
+}
+
+void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)
+{
+    FLEXIO_Deinit(base->flexioBase);
+}
+
+void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)
+{
+    assert(masterConfig);
+
+    masterConfig->enableMaster = true;
+    masterConfig->enableInDoze = false;
+    masterConfig->enableInDebug = true;
+    masterConfig->enableFastAccess = false;
+
+    /* Default baud rate at 100kbps. */
+    masterConfig->baudRate_Bps = 100000U;
+}
+
+uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)
+{
+    uint32_t status = 0;
+
+    status =
+        ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]);
+    status |=
+        (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1]))
+         << 1U);
+    status |=
+        (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1]))
+         << 2U);
+
+    return status;
+}
+
+void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)
+{
+    if (mask & kFLEXIO_I2C_TxEmptyFlag)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]);
+    }
+
+    if (mask & kFLEXIO_I2C_RxFullFlag)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]);
+    }
+
+    if (mask & kFLEXIO_I2C_ReceiveNakFlag)
+    {
+        FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
+    }
+}
+
+void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
+{
+    if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]);
+    }
+    if (mask & kFLEXIO_I2C_RxFullInterruptEnable)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]);
+    }
+}
+
+void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
+{
+    if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]);
+    }
+    if (mask & kFLEXIO_I2C_RxFullInterruptEnable)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]);
+    }
+}
+
+void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+    uint16_t timerDiv = 0;
+    uint16_t timerCmp = 0;
+    FLEXIO_Type *flexioBase = base->flexioBase;
+
+    /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/
+    timerDiv = srcClock_Hz / baudRate_Bps;
+    timerDiv = timerDiv / 2 - 1U;
+
+    timerCmp = flexioBase->TIMCMP[base->timerIndex[0]];
+    timerCmp &= 0xFF00;
+    timerCmp |= timerDiv;
+
+    flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
+}
+
+status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count)
+{
+    if (count > 14U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    uint16_t timerCmp = 0;
+    uint32_t timerConfig = 0;
+    FLEXIO_Type *flexioBase = base->flexioBase;
+
+    timerCmp = flexioBase->TIMCMP[base->timerIndex[0]];
+    timerCmp &= 0x00FFU;
+    timerCmp |= (count * 18 + 1U) << 8U;
+    flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
+    timerConfig = flexioBase->TIMCFG[base->timerIndex[0]];
+    timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
+    timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
+    flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig;
+
+    return kStatus_Success;
+}
+
+void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)
+{
+    uint32_t data;
+
+    data = ((uint32_t)address) << 1U | ((direction == kFLEXIO_I2C_Read) ? 1U : 0U);
+
+    FLEXIO_I2C_MasterWriteByte(base, data);
+}
+
+void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)
+{
+    /* Prepare for RESTART condition, no stop.*/
+    FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
+}
+
+void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)
+{
+    /* Prepare normal stop. */
+    FLEXIO_I2C_MasterSetTransferCount(base, 0x0U);
+    FLEXIO_I2C_MasterWriteByte(base, 0x0U);
+}
+
+void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)
+{
+    uint32_t tmpConfig;
+
+    /* Prepare abort stop. */
+    tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[0]];
+    tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
+    tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge);
+    base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig;
+}
+
+void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)
+{
+    uint32_t tmpConfig = 0;
+
+    tmpConfig = base->flexioBase->SHIFTCFG[base->shifterIndex[0]];
+    tmpConfig &= ~FLEXIO_SHIFTCFG_SSTOP_MASK;
+    if (enable)
+    {
+        tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitLow);
+    }
+    else
+    {
+        tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitHigh);
+    }
+    base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig;
+}
+
+status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)
+{
+    assert(txBuff);
+    assert(txSize);
+
+    uint32_t status;
+
+    while (txSize--)
+    {
+        FLEXIO_I2C_MasterWriteByte(base, *txBuff++);
+
+        /* Wait until data transfer complete. */
+        while (!((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & kFLEXIO_I2C_RxFullFlag))
+        {
+        }
+
+        if (status & kFLEXIO_I2C_ReceiveNakFlag)
+        {
+            FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
+            return kStatus_FLEXIO_I2C_Nak;
+        }
+    }
+    return kStatus_Success;
+}
+
+void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)
+{
+    assert(rxBuff);
+    assert(rxSize);
+
+    while (rxSize--)
+    {
+        /* Wait until data transfer complete. */
+        while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag))
+        {
+        }
+
+        *rxBuff++ = FLEXIO_I2C_MasterReadByte(base);
+    }
+}
+
+status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer)
+{
+    assert(xfer);
+
+    flexio_i2c_master_handle_t tmpHandle;
+    uint32_t statusFlags;
+    uint32_t result = kStatus_Success;
+
+    FLEXIO_I2C_MasterTransferCreateHandle(base, &tmpHandle, NULL, NULL);
+
+    /* Set up transfer machine. */
+    FLEXIO_I2C_MasterTransferInitStateMachine(base, &tmpHandle, xfer);
+
+    do
+    {
+        /* Wait either tx empty or rx full flag is asserted. */
+        while (!((statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base)) &
+                 (kFLEXIO_I2C_TxEmptyFlag | kFLEXIO_I2C_RxFullFlag)))
+        {
+        }
+
+        result = FLEXIO_I2C_MasterTransferRunStateMachine(base, &tmpHandle, statusFlags);
+
+    } while ((tmpHandle.state != kFLEXIO_I2C_Idle) && (result == kStatus_Success));
+
+    return result;
+}
+
+status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
+                                               flexio_i2c_master_handle_t *handle,
+                                               flexio_i2c_master_transfer_callback_t callback,
+                                               void *userData)
+{
+    assert(handle);
+
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Register callback and userData. */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    /* Enable interrupt in NVIC. */
+    EnableIRQ(flexio_irqs[0]);
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ);
+}
+
+status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base,
+                                              flexio_i2c_master_handle_t *handle,
+                                              flexio_i2c_master_transfer_t *xfer)
+{
+    assert(handle);
+    assert(xfer);
+
+    if (handle->state != kFLEXIO_I2C_Idle)
+    {
+        return kStatus_FLEXIO_I2C_Busy;
+    }
+    else
+    {
+        /* Set up transfer machine. */
+        FLEXIO_I2C_MasterTransferInitStateMachine(base, handle, xfer);
+
+        /* Enable both tx empty and rxfull interrupt. */
+        FLEXIO_I2C_MasterEnableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable);
+
+        return kStatus_Success;
+    }
+}
+
+void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)
+{
+    assert(handle);
+
+    /* Disable interrupts. */
+    FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable);
+
+    /* Reset to idle state. */
+    handle->state = kFLEXIO_I2C_Idle;
+}
+
+status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)
+{
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    *count = handle->transferSize - handle->transfer.dataSize;
+
+    return kStatus_Success;
+}
+
+void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)
+{
+    FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType;
+    flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle;
+    uint32_t statusFlags;
+    status_t result;
+
+    statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base);
+
+    result = FLEXIO_I2C_MasterTransferRunStateMachine(base, handle, statusFlags);
+
+    if (handle->state == kFLEXIO_I2C_Idle)
+    {
+        FLEXIO_I2C_MasterTransferComplete(base, handle, result);
+    }
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2c_master.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2c_master.h
new file mode 100644
index 00000000000..c16954ed4ea
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2c_master.h
@@ -0,0 +1,486 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_FLEXIO_I2C_MASTER_H_
+#define _FSL_FLEXIO_I2C_MASTER_H_
+
+#include "fsl_common.h"
+#include "fsl_flexio.h"
+
+/*!
+ * @addtogroup flexio_i2c_master
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexIO I2C master driver version 2.1.2. */
+#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
+/*@}*/
+
+/*! @brief  FlexIO I2C transfer status*/
+enum _flexio_i2c_status
+{
+    kStatus_FLEXIO_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 0), /*!< I2C is busy doing transfer. */
+    kStatus_FLEXIO_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 1), /*!< I2C is busy doing transfer. */
+    kStatus_FLEXIO_I2C_Nak = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2),  /*!< NAK received during transfer. */
+};
+
+/*! @brief Define FlexIO I2C master interrupt mask. */
+enum _flexio_i2c_master_interrupt
+{
+    kFLEXIO_I2C_TxEmptyInterruptEnable = 0x1U, /*!< Tx buffer empty interrupt enable. */
+    kFLEXIO_I2C_RxFullInterruptEnable = 0x2U,  /*!< Rx buffer full interrupt enable. */
+};
+
+/*! @brief Define FlexIO I2C master status mask. */
+enum _flexio_i2c_master_status_flags
+{
+    kFLEXIO_I2C_TxEmptyFlag = 0x1U,    /*!< Tx shifter empty flag. */
+    kFLEXIO_I2C_RxFullFlag = 0x2U,     /*!< Rx shifter full/Transfer complete flag. */
+    kFLEXIO_I2C_ReceiveNakFlag = 0x4U, /*!< Receive NAK flag. */
+};
+
+/*! @brief Direction of master transfer.*/
+typedef enum _flexio_i2c_direction
+{
+    kFLEXIO_I2C_Write = 0x0U, /*!< Master send to slave. */
+    kFLEXIO_I2C_Read = 0x1U,  /*!< Master receive from slave. */
+} flexio_i2c_direction_t;
+
+/*! @brief Define FlexIO I2C master access structure typedef. */
+typedef struct _flexio_i2c_type
+{
+    FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */
+    uint8_t SDAPinIndex;     /*!< Pin select for I2C SDA. */
+    uint8_t SCLPinIndex;     /*!< Pin select for I2C SCL. */
+    uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO I2C. */
+    uint8_t timerIndex[2];   /*!< Timer index used in FlexIO I2C. */
+} FLEXIO_I2C_Type;
+
+/*! @brief Define FlexIO I2C master user configuration structure. */
+typedef struct _flexio_i2c_master_config
+{
+    bool enableMaster;     /*!< Enables the FLEXIO I2C peripheral at initialization time. */
+    bool enableInDoze;     /*!< Enable/disable FlexIO operation in doze mode. */
+    bool enableInDebug;    /*!< Enable/disable FlexIO operation in debug mode. */
+    bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires
+                           the FlexIO clock to be at least twice the frequency of the bus clock. */
+    uint32_t baudRate_Bps; /*!< Baud rate in Bps. */
+} flexio_i2c_master_config_t;
+
+/*! @brief Define FlexIO I2C master transfer structure. */
+typedef struct _flexio_i2c_master_transfer
+{
+    uint32_t flags;                   /*!< Transfer flag which controls the transfer, reserved for FlexIO I2C. */
+    uint8_t slaveAddress;             /*!< 7-bit slave address. */
+    flexio_i2c_direction_t direction; /*!< Transfer direction, read or write. */
+    uint32_t subaddress;              /*!< Sub address. Transferred MSB first. */
+    uint8_t subaddressSize;           /*!< Size of command buffer. */
+    uint8_t volatile *data;           /*!< Transfer buffer. */
+    volatile size_t dataSize;         /*!< Transfer size. */
+} flexio_i2c_master_transfer_t;
+
+/*! @brief FlexIO I2C master handle typedef. */
+typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t;
+
+/*! @brief FlexIO I2C master transfer callback typedef. */
+typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base,
+                                                      flexio_i2c_master_handle_t *handle,
+                                                      status_t status,
+                                                      void *userData);
+
+/*! @brief Define FlexIO I2C master handle structure. */
+struct _flexio_i2c_master_handle
+{
+    flexio_i2c_master_transfer_t transfer;                    /*!< FlexIO I2C master transfer copy. */
+    size_t transferSize;                                      /*!< Total bytes to be transferred. */
+    uint8_t state;                                            /*!< Transfer state maintained during transfer. */
+    flexio_i2c_master_transfer_callback_t completionCallback; /*!< Callback function called at transfer event. */
+                                                              /*!< Callback function called at transfer event. */
+    void *userData;                                           /*!< Callback parameter passed to callback function. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C
+ * hardware configuration.
+ *
+ * Example
+   @code
+   FLEXIO_I2C_Type base = {
+   .flexioBase = FLEXIO,
+   .SDAPinIndex = 0,
+   .SCLPinIndex = 1,
+   .shifterIndex = {0,1},
+   .timerIndex = {0,1}
+   };
+   flexio_i2c_master_config_t config = {
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .baudRate_Bps = 100000
+   };
+   FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz);
+   @endcode
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param masterConfig pointer to flexio_i2c_master_config_t structure.
+ * @param srcClock_Hz FlexIO source clock in Hz.
+*/
+void FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz);
+
+/*!
+ * @brief De-initializes the FlexIO I2C master peripheral. Calling this API gates the FlexIO clock,
+ * so the FlexIO I2C master module can't work unless call FLEXIO_I2C_MasterInit.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ */
+void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base);
+
+/*!
+ * @brief Gets the default configuration to configure the FlexIO module. The configuration
+ * can be used directly for calling FLEXIO_I2C_MasterInit().
+ *
+ * Example:
+   @code
+   flexio_i2c_master_config_t config;
+   FLEXIO_I2C_MasterGetDefaultConfig(&config);
+   @endcode
+ * @param masterConfig pointer to flexio_i2c_master_config_t structure.
+*/
+void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig);
+
+/*!
+ * @brief Enables/disables the FlexIO module operation.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param enable pass true to enable module, false to disable module.
+*/
+static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+    else
+    {
+        base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the FlexIO I2C master status flags.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @return status flag, use status flag to AND #_flexio_i2c_master_status_flags could get the related status.
+*/
+
+uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base);
+
+/*!
+ * @brief Clears the FlexIO I2C master status flags.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param mask status flag.
+ *      The parameter could be any combination of the following values:
+ *          @arg kFLEXIO_I2C_RxFullFlag
+ *          @arg kFLEXIO_I2C_ReceiveNakFlag
+*/
+
+void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask);
+
+/*@}*/
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the FlexIO i2c master interrupt requests.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param mask interrupt source.
+ *     Currently only one interrupt request source:
+ *     @arg kFLEXIO_I2C_TransferCompleteInterruptEnable
+ */
+void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the FlexIO I2C master interrupt requests.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param mask interrupt source.
+ */
+void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask);
+
+/*@}*/
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Sets the FlexIO I2C master transfer baudrate.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param baudRate_Bps the baud rate value in HZ
+ * @param srcClock_Hz source clock in HZ
+ */
+void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Sends START + 7-bit address to the bus.
+ *
+ * @note This is API should be called when transfer configuration is ready to send a START signal
+ * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address
+ * is put into the data register but not address transfer finished on the bus. Ensure that
+ * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API.
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param address 7-bit address.
+ * @param direction transfer direction.
+ *     This parameter is one of the values in flexio_i2c_direction_t:
+ *        @arg kFLEXIO_I2C_Write: Transmit
+ *        @arg kFLEXIO_I2C_Read:  Receive
+ */
+
+void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction);
+
+/*!
+ * @brief Sends the stop signal on the bus.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ */
+void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base);
+
+/*!
+ * @brief Sends the repeated start signal on the bus.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ */
+void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base);
+
+/*!
+ * @brief Sends the stop signal when transfer is still on-going.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ */
+void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base);
+
+/*!
+ * @brief Configures the sent ACK/NAK for the following byte.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param enable true to configure send ACK, false configure to send NAK.
+ */
+void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable);
+
+/*!
+ * @brief Sets the number of bytes to be transferred from a start signal to a stop signal.
+ *
+ * @note Call this API before a transfer begins because the timer generates a number of clocks according
+ * to the number of bytes that need to be transferred.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param count number of bytes need to be transferred from a start signal to a re-start/stop signal
+ * @retval kStatus_Success Successfully configured the count.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+*/
+status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count);
+
+/*!
+ * @brief Writes one byte of data to the I2C bus.
+ *
+ * @note This is a non-blocking API, which returns directly after the data is put into the
+ * data register but not data transfer finished on the bus. Ensure that
+ * the TxEmptyFlag is asserted before calling this API.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param data a byte of data.
+ */
+static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data)
+{
+    base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data;
+}
+
+/*!
+ * @brief Reads one byte of data from the I2C bus.
+ *
+ * @note This is a non-blocking API, which returns directly after the data is read from the
+ * data register. Ensure that the data is ready in the register.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @return data byte read.
+ */
+static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base)
+{
+    return base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]];
+}
+
+/*!
+ * @brief Sends a buffer of data in bytes.
+ *
+ * @note This function blocks via polling until all bytes have been sent.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param txBuff The data bytes to send.
+ * @param txSize The number of data bytes to send.
+ * @retval kStatus_Success Successfully write data.
+ * @retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data.
+ */
+status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize);
+
+/*!
+ * @brief Receives a buffer of bytes.
+ *
+ * @note This function blocks via polling until all bytes have been received.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param rxBuff The buffer to store the received bytes.
+ * @param rxSize The number of data bytes to be received.
+ */
+void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize);
+
+/*!
+ * @brief Performs a master polling transfer on the I2C bus.
+ *
+ * @note The API does not return until the transfer succeeds or fails due
+ * to receiving NAK.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param xfer pointer to flexio_i2c_master_transfer_t structure.
+ * @return status of status_t.
+ */
+status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer);
+/*@}*/
+
+/*Transactional APIs*/
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the I2C handle which is used in transactional functions.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param handle pointer to flexio_i2c_master_handle_t structure to store the transfer state.
+ * @param callback pointer to user callback function.
+ * @param userData user param passed to the callback function.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range.
+ */
+status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
+                                               flexio_i2c_master_handle_t *handle,
+                                               flexio_i2c_master_transfer_callback_t callback,
+                                               void *userData);
+
+/*!
+ * @brief Performs a master interrupt non-blocking transfer on the I2C bus.
+ *
+ * @note The API returns immediately after the transfer initiates.
+ * Call FLEXIO_I2C_MasterGetTransferCount to poll the transfer status to check whether
+ * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer
+ * is finished.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * @param xfer pointer to flexio_i2c_master_transfer_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer.
+ */
+status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base,
+                                              flexio_i2c_master_handle_t *handle,
+                                              flexio_i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Gets the master transfer status during a interrupt non-blocking transfer.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure.
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Aborts an interrupt non-blocking transfer early.
+ *
+ * @note This API can be called at any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * @param base pointer to FLEXIO_I2C_Type structure
+ * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ */
+void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle);
+
+/*!
+ * @brief Master interrupt handler.
+ *
+ * @param i2cType pointer to FLEXIO_I2C_Type structure
+ * @param i2cHandle pointer to flexio_i2c_master_transfer_t structure
+ */
+void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+/*@}*/
+
+#endif /*_FSL_FLEXIO_I2C_MASTER_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s.c
new file mode 100644
index 00000000000..0a8697309c7
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s.c
@@ -0,0 +1,635 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_i2s.h"
+
+/*******************************************************************************
+* Definitations
+******************************************************************************/
+enum _sai_transfer_state
+{
+    kFLEXIO_I2S_Busy = 0x0U, /*!< FLEXIO_I2S is busy */
+    kFLEXIO_I2S_Idle,        /*!< Transfer is done. */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Receive a piece of data in non-blocking way.
+ *
+ * @param base FLEXIO I2S base pointer
+ * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param buffer Pointer to the data to be read.
+ * @param size Bytes to be read.
+ */
+static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size);
+
+/*!
+ * @brief sends a piece of data in non-blocking way.
+ *
+ * @param base FLEXIO I2S base pointer
+ * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param buffer Pointer to the data to be written.
+ * @param size Bytes to be written.
+ */
+static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size);
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
+{
+    uint32_t i = 0;
+    uint8_t j = 0;
+    uint8_t bytesPerWord = bitWidth / 8U;
+    uint32_t data = 0;
+    uint32_t temp = 0;
+
+    for (i = 0; i < size / bytesPerWord; i++)
+    {
+        for (j = 0; j < bytesPerWord; j++)
+        {
+            temp = (uint32_t)(*txData);
+            data |= (temp << (8U * j));
+            txData++;
+        }
+        base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth));
+        data = 0;
+    }
+}
+
+static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
+{
+    uint32_t i = 0;
+    uint8_t j = 0;
+    uint8_t bytesPerWord = bitWidth / 8U;
+    uint32_t data = 0;
+
+    for (i = 0; i < size / bytesPerWord; i++)
+    {
+        data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex] >> (32U - bitWidth));
+        for (j = 0; j < bytesPerWord; j++)
+        {
+            *rxData = (data >> (8U * j)) & 0xFF;
+            rxData++;
+        }
+    }
+}
+
+void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
+{
+    assert(base && config);
+
+    flexio_shifter_config_t shifterConfig = {0};
+    flexio_timer_config_t timerConfig = {0};
+
+    /* Ungate flexio clock. */
+    CLOCK_EnableClock(kCLOCK_Flexio0);
+
+    FLEXIO_Reset(base->flexioBase);
+
+    /* Set shifter for I2S Tx data */
+    shifterConfig.timerSelect = base->bclkTimerIndex;
+    shifterConfig.pinSelect = base->txPinIndex;
+    shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+    shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
+    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
+    if (config->masterSlave == kFLEXIO_I2S_Master)
+    {
+        shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
+    }
+    else
+    {
+        shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    }
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->txShifterIndex, &shifterConfig);
+
+    /* Set shifter for I2S Rx Data */
+    shifterConfig.timerSelect = base->bclkTimerIndex;
+    shifterConfig.pinSelect = base->rxPinIndex;
+    shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+    shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
+    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->rxShifterIndex, &shifterConfig);
+
+    /* Set Timer to I2S frame sync */
+    if (config->masterSlave == kFLEXIO_I2S_Master)
+    {
+        timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->txPinIndex);
+        timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
+        timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal;
+        timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
+        timerConfig.pinSelect = base->fsPinIndex;
+        timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
+        timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
+        timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
+        timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+        timerConfig.timerReset = kFLEXIO_TimerResetNever;
+        timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
+        timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
+        timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
+        timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
+    }
+    else
+    {
+        timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex);
+        timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
+        timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
+        timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
+        timerConfig.pinSelect = base->fsPinIndex;
+        timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
+        timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
+        timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
+        timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput;
+        timerConfig.timerReset = kFLEXIO_TimerResetNever;
+        timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
+        timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge;
+        timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
+        timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
+    }
+    FLEXIO_SetTimerConfig(base->flexioBase, base->fsTimerIndex, &timerConfig);
+
+    /* Set Timer to I2S bit clock */
+    if (config->masterSlave == kFLEXIO_I2S_Master)
+    {
+        timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex);
+        timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
+        timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
+        timerConfig.pinSelect = base->bclkPinIndex;
+        timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
+        timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+        timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
+        timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
+        timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+        timerConfig.timerReset = kFLEXIO_TimerResetNever;
+        timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
+        timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
+        timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
+        timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
+    }
+    else
+    {
+        timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex);
+        timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
+        timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
+        timerConfig.pinSelect = base->bclkPinIndex;
+        timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
+        timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+        timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
+        timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
+        timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
+        timerConfig.timerReset = kFLEXIO_TimerResetNever;
+        timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompareTriggerLow;
+        timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh;
+        timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
+        timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
+    }
+    FLEXIO_SetTimerConfig(base->flexioBase, base->bclkTimerIndex, &timerConfig);
+
+    /* If enable flexio I2S */
+    if (config->enableI2S)
+    {
+        base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+    else
+    {
+        base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)
+{
+    config->masterSlave = kFLEXIO_I2S_Master;
+    config->enableI2S = true;
+}
+
+void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)
+{
+    /* Disable FLEXIO I2S module. */
+    FLEXIO_I2S_Enable(base, false);
+
+    /* Gate flexio clock. */
+    CLOCK_DisableClock(kCLOCK_Flexio0);
+}
+
+void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
+{
+    if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex);
+    }
+    if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex);
+    }
+}
+
+uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)
+{
+    uint32_t status = 0;
+    status = ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->txShifterIndex)) >> base->txShifterIndex);
+    status |=
+        (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex)) >> (base->rxShifterIndex))
+         << 1U);
+    return status;
+}
+
+void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
+{
+    if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex);
+    }
+    if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex);
+    }
+}
+
+void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz)
+{
+    uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * 32U * 2U);
+    uint32_t bclkDiv = 0;
+
+    /* Set Frame sync timer cmp */
+    base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * timDiv - 1U);
+
+    /* Set bit clock timer cmp */
+    bclkDiv = ((timDiv / 2U - 1U) | (63U << 8U));
+    base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(bclkDiv);
+}
+
+void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format)
+{
+    /* Set Frame sync timer cmp */
+    base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 4U - 3U);
+
+    /* Set bit clock timer cmp */
+    base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 2U - 1U);
+}
+
+void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
+{
+    uint32_t i = 0;
+    uint8_t bytesPerWord = bitWidth / 8U;
+
+    for (i = 0; i < size / bytesPerWord; i++)
+    {
+        /* Wait until it can write data */
+        while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0)
+        {
+        }
+
+        FLEXIO_I2S_WriteNonBlocking(base, bitWidth, txData, bytesPerWord);
+        txData += bytesPerWord;
+    }
+
+    /* Wait until the last data is sent */
+    while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0)
+    {
+    }
+}
+
+void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
+{
+    uint32_t i = 0;
+    uint8_t bytesPerWord = bitWidth / 8U;
+
+    for (i = 0; i < size / bytesPerWord; i++)
+    {
+        /* Wait until data is received */
+        while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex)))
+        {
+        }
+
+        FLEXIO_I2S_ReadNonBlocking(base, bitWidth, rxData, bytesPerWord);
+        rxData += bytesPerWord;
+    }
+}
+
+void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
+                                       flexio_i2s_handle_t *handle,
+                                       flexio_i2s_callback_t callback,
+                                       void *userData)
+{
+    assert(handle);
+
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Store callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferTxHandleIRQ);
+
+    /* Set the TX/RX state. */
+    handle->state = kFLEXIO_I2S_Idle;
+
+    /* Enable interrupt in NVIC. */
+    EnableIRQ(flexio_irqs[0]);
+}
+
+void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base,
+                                       flexio_i2s_handle_t *handle,
+                                       flexio_i2s_callback_t callback,
+                                       void *userData)
+{
+    assert(handle);
+
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Store callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferRxHandleIRQ);
+
+    /* Set the TX/RX state. */
+    handle->state = kFLEXIO_I2S_Idle;
+
+    /* Enable interrupt in NVIC. */
+    EnableIRQ(flexio_irqs[0]);
+}
+
+void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
+                                  flexio_i2s_handle_t *handle,
+                                  flexio_i2s_format_t *format,
+                                  uint32_t srcClock_Hz)
+{
+    assert(handle && format);
+
+    /* Set the bitWidth to handle */
+    handle->bitWidth = format->bitWidth;
+
+    /* Set sample rate */
+    if (srcClock_Hz != 0)
+    {
+        /* It is master */
+        FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz);
+    }
+    else
+    {
+        FLEXIO_I2S_SlaveSetFormat(base, format);
+    }
+}
+
+status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
+                                            flexio_i2s_handle_t *handle,
+                                            flexio_i2s_transfer_t *xfer)
+{
+    assert(handle);
+
+    /* Check if the queue is full */
+    if (handle->queue[handle->queueUser].data)
+    {
+        return kStatus_FLEXIO_I2S_QueueFull;
+    }
+    if ((xfer->dataSize == 0) || (xfer->data == NULL))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Add into queue */
+    handle->queue[handle->queueUser].data = xfer->data;
+    handle->queue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->transferSize[handle->queueUser] = xfer->dataSize;
+    handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+
+    /* Set the state to busy */
+    handle->state = kFLEXIO_I2S_Busy;
+
+    FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable);
+
+    /* Enable Tx transfer */
+    FLEXIO_I2S_Enable(base, true);
+
+    return kStatus_Success;
+}
+
+status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
+                                               flexio_i2s_handle_t *handle,
+                                               flexio_i2s_transfer_t *xfer)
+{
+    assert(handle);
+
+    /* Check if the queue is full */
+    if (handle->queue[handle->queueUser].data)
+    {
+        return kStatus_FLEXIO_I2S_QueueFull;
+    }
+
+    if ((xfer->dataSize == 0) || (xfer->data == NULL))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Add into queue */
+    handle->queue[handle->queueUser].data = xfer->data;
+    handle->queue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->transferSize[handle->queueUser] = xfer->dataSize;
+    handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+
+    /* Set state to busy */
+    handle->state = kFLEXIO_I2S_Busy;
+
+    /* Enable interrupt */
+    FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable);
+
+    /* Enable Rx transfer */
+    FLEXIO_I2S_Enable(base, true);
+
+    return kStatus_Success;
+}
+
+void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
+{
+    assert(handle);
+
+    /* Stop Tx transfer and disable interrupt */
+    FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable);
+    handle->state = kFLEXIO_I2S_Idle;
+
+    /* Clear the queue */
+    memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE);
+    handle->queueDriver = 0;
+    handle->queueUser = 0;
+}
+
+void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
+{
+    assert(handle);
+
+    /* Stop rx transfer and disable interrupt */
+    FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable);
+    handle->state = kFLEXIO_I2S_Idle;
+
+    /* Clear the queue */
+    memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE);
+    handle->queueDriver = 0;
+    handle->queueUser = 0;
+}
+
+status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != kFLEXIO_I2S_Busy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize);
+    }
+
+    return status;
+}
+
+status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != kFLEXIO_I2S_Busy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize);
+    }
+
+    return status;
+}
+
+void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)
+{
+    assert(i2sHandle);
+
+    flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle;
+    FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase;
+    uint8_t *buffer = handle->queue[handle->queueDriver].data;
+    uint8_t dataSize = handle->bitWidth / 8U;
+
+    /* Handle error */
+    if (FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->txShifterIndex))
+    {
+        FLEXIO_ClearShifterErrorFlags(base->flexioBase, (1U << base->txShifterIndex));
+    }
+    /* Handle transfer */
+    if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) != 0) &&
+        (handle->queue[handle->queueDriver].data != NULL))
+    {
+        FLEXIO_I2S_WriteNonBlocking(base, handle->bitWidth, buffer, dataSize);
+
+        /* Update internal counter */
+        handle->queue[handle->queueDriver].dataSize -= dataSize;
+        handle->queue[handle->queueDriver].data += dataSize;
+    }
+
+    /* If finished a blcok, call the callback function */
+    if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL))
+    {
+        memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
+        handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+        if (handle->callback)
+        {
+            (handle->callback)(base, handle, kStatus_Success, handle->userData);
+        }
+    }
+
+    /* If all data finished, just stop the transfer */
+    if (handle->queue[handle->queueDriver].data == NULL)
+    {
+        FLEXIO_I2S_TransferAbortSend(base, handle);
+    }
+}
+
+void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)
+{
+    assert(i2sHandle);
+
+    flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle;
+    FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase;
+    uint8_t *buffer = handle->queue[handle->queueDriver].data;
+    uint8_t dataSize = handle->bitWidth / 8U;
+
+    /* Handle transfer */
+    if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_RxDataRegFullFlag) != 0) &&
+        (handle->queue[handle->queueDriver].data != NULL))
+    {
+        FLEXIO_I2S_ReadNonBlocking(base, handle->bitWidth, buffer, dataSize);
+
+        /* Update internal state */
+        handle->queue[handle->queueDriver].dataSize -= dataSize;
+        handle->queue[handle->queueDriver].data += dataSize;
+    }
+
+    /* If finished a blcok, call the callback function */
+    if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL))
+    {
+        memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
+        handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+        if (handle->callback)
+        {
+            (handle->callback)(base, handle, kStatus_Success, handle->userData);
+        }
+    }
+
+    /* If all data finished, just stop the transfer */
+    if (handle->queue[handle->queueDriver].data == NULL)
+    {
+        FLEXIO_I2S_TransferAbortReceive(base, handle);
+    }
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s.h
new file mode 100644
index 00000000000..ea3a9c07b94
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s.h
@@ -0,0 +1,569 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_FLEXIO_I2S_H_
+#define _FSL_FLEXIO_I2S_H_
+
+#include "fsl_common.h"
+#include "fsl_flexio.h"
+
+/*!
+ * @addtogroup flexio_i2s
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexIO I2S driver version 2.1.0. */
+#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*@}*/
+
+/*! @brief FlexIO I2S transfer status */
+enum _flexio_i2s_status
+{
+    kStatus_FLEXIO_I2S_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 0),      /*!< FlexIO I2S is in idle state */
+    kStatus_FLEXIO_I2S_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 1),    /*!< FlexIO I2S Tx is busy */
+    kStatus_FLEXIO_I2S_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 2),    /*!< FlexIO I2S Tx is busy */
+    kStatus_FLEXIO_I2S_Error = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 3),     /*!< FlexIO I2S error occurred */
+    kStatus_FLEXIO_I2S_QueueFull = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 4), /*!< FlexIO I2S transfer queue is full. */
+};
+
+/*! @brief Define FlexIO I2S access structure typedef */
+typedef struct _flexio_i2s_type
+{
+    FLEXIO_Type *flexioBase; /*!< FlexIO base pointer */
+    uint8_t txPinIndex;      /*!< Tx data pin index in FlexIO pins */
+    uint8_t rxPinIndex;      /*!< Rx data pin index */
+    uint8_t bclkPinIndex;    /*!< Bit clock pin index */
+    uint8_t fsPinIndex;      /*!< Frame sync pin index */
+    uint8_t txShifterIndex;  /*!< Tx data shifter index */
+    uint8_t rxShifterIndex;  /*!< Rx data shifter index */
+    uint8_t bclkTimerIndex;  /*!< Bit clock timer index */
+    uint8_t fsTimerIndex;    /*!< Frame sync timer index */
+} FLEXIO_I2S_Type;
+
+/*! @brief Master or slave mode */
+typedef enum _flexio_i2s_master_slave
+{
+    kFLEXIO_I2S_Master = 0x0U, /*!< Master mode */
+    kFLEXIO_I2S_Slave = 0x1U   /*!< Slave mode */
+} flexio_i2s_master_slave_t;
+
+/*! @brief Define FlexIO FlexIO I2S interrupt mask. */
+enum _flexio_i2s_interrupt_enable
+{
+    kFLEXIO_I2S_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
+    kFLEXIO_I2S_RxDataRegFullInterruptEnable = 0x2U,  /*!< Receive buffer full interrupt enable. */
+};
+
+/*! @brief Define FlexIO FlexIO I2S status mask. */
+enum _flexio_i2s_status_flags
+{
+    kFLEXIO_I2S_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
+    kFLEXIO_I2S_RxDataRegFullFlag = 0x2U,  /*!< Receive buffer full flag. */
+};
+
+/*! @brief FlexIO I2S configure structure */
+typedef struct _flexio_i2s_config
+{
+    bool enableI2S;                        /*!< Enable FlexIO I2S */
+    flexio_i2s_master_slave_t masterSlave; /*!< Master or slave */
+} flexio_i2s_config_t;
+
+/*! @brief FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx */
+typedef struct _flexio_i2s_format
+{
+    uint8_t bitWidth;       /*!< Bit width of audio data, always 8/16/24/32 bits */
+    uint32_t sampleRate_Hz; /*!< Sample rate of the audio data */
+} flexio_i2s_format_t;
+
+/*!@brief FlexIO I2S transfer queue size, user can refine it according to use case. */
+#define FLEXIO_I2S_XFER_QUEUE_SIZE (4)
+
+/*! @brief Audio sample rate */
+typedef enum _flexio_i2s_sample_rate
+{
+    kFLEXIO_I2S_SampleRate8KHz = 8000U,     /*!< Sample rate 8000Hz */
+    kFLEXIO_I2S_SampleRate11025Hz = 11025U, /*!< Sample rate 11025Hz */
+    kFLEXIO_I2S_SampleRate12KHz = 12000U,   /*!< Sample rate 12000Hz */
+    kFLEXIO_I2S_SampleRate16KHz = 16000U,   /*!< Sample rate 16000Hz */
+    kFLEXIO_I2S_SampleRate22050Hz = 22050U, /*!< Sample rate 22050Hz */
+    kFLEXIO_I2S_SampleRate24KHz = 24000U,   /*!< Sample rate 24000Hz */
+    kFLEXIO_I2S_SampleRate32KHz = 32000U,   /*!< Sample rate 32000Hz */
+    kFLEXIO_I2S_SampleRate44100Hz = 44100U, /*!< Sample rate 44100Hz */
+    kFLEXIO_I2S_SampleRate48KHz = 48000U,   /*!< Sample rate 48000Hz */
+    kFLEXIO_I2S_SampleRate96KHz = 96000U    /*!< Sample rate 96000Hz */
+} flexio_i2s_sample_rate_t;
+
+/*! @brief Audio word width */
+typedef enum _flexio_i2s_word_width
+{
+    kFLEXIO_I2S_WordWidth8bits = 8U,   /*!< Audio data width 8 bits */
+    kFLEXIO_I2S_WordWidth16bits = 16U, /*!< Audio data width 16 bits */
+    kFLEXIO_I2S_WordWidth24bits = 24U, /*!< Audio data width 24 bits */
+    kFLEXIO_I2S_WordWidth32bits = 32U  /*!< Audio data width 32 bits */
+} flexio_i2s_word_width_t;
+
+/*! @brief Define FlexIO I2S transfer structure. */
+typedef struct _flexio_i2s_transfer
+{
+    uint8_t *data;   /*!< Data buffer start pointer */
+    size_t dataSize; /*!< Bytes to be transferred. */
+} flexio_i2s_transfer_t;
+
+typedef struct _flexio_i2s_handle flexio_i2s_handle_t;
+
+/*! @brief FlexIO I2S xfer callback prototype */
+typedef void (*flexio_i2s_callback_t)(FLEXIO_I2S_Type *base,
+                                      flexio_i2s_handle_t *handle,
+                                      status_t status,
+                                      void *userData);
+
+/*! @brief Define FlexIO I2S handle structure. */
+struct _flexio_i2s_handle
+{
+    uint32_t state;                                          /*!< Internal state */
+    flexio_i2s_callback_t callback;                          /*!< Callback function called at transfer event*/
+    void *userData;                                          /*!< Callback parameter passed to callback function*/
+    uint8_t bitWidth;                                        /*!< Bit width for transfer, 8/16/24/32bits */
+    flexio_i2s_transfer_t queue[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */
+    size_t transferSize[FLEXIO_I2S_XFER_QUEUE_SIZE];         /*!< Data bytes need to transfer */
+    volatile uint8_t queueUser;                              /*!< Index for user to queue transfer */
+    volatile uint8_t queueDriver;                            /*!< Index for driver to get the transfer data and size */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FlexIO I2S.
+ *
+ * This API configures FlexIO pins and shifter to I2S and configure FlexIO I2S with configuration structure.
+ * The configuration structure can be filled by the user, or be set with default values by
+ * FLEXIO_I2S_GetDefaultConfig().
+ *
+ * @note  This API should be called at the beginning of the application to use
+ * the FlexIO I2S driver, or any access to the FlexIO I2S module could cause hard fault
+ * because clock is not enabled.
+ *
+ * @param base FlexIO I2S base pointer
+ * @param config FlexIO I2S configure structure.
+*/
+void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config);
+
+/*!
+ * @brief  Sets the FlexIO I2S configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init().
+ * User may use the initialized structure unchanged in FLEXIO_I2S_Init(), or modify
+ * some fields of the structure before calling FLEXIO_I2S_Init().
+ *
+ * @param config pointer to master configuration structure
+ */
+void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config);
+
+/*!
+ * @brief De-initializes the FlexIO I2S.
+ *
+ * Calling this API gates the FlexIO i2s clock. After calling this API, call the FLEXO_I2S_Init to use the
+ * FlexIO I2S module.
+ *
+ * @param base FlexIO I2S base pointer
+*/
+void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base);
+
+/*!
+ * @brief Enables/disables the FlexIO I2S module operation.
+ *
+ * @param base pointer to FLEXIO_I2S_Type
+ * @param enable True to enable, false to disable.
+*/
+static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+    else
+    {
+        base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the FlexIO I2S status flags.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure
+ * @return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.
+*/
+uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base);
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the FlexIO I2S interrupt.
+ *
+ * This function enables the FlexIO UART interrupt.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure
+ * @param mask interrupt source
+ */
+void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the FlexIO I2S interrupt.
+ *
+ * This function enables the FlexIO UART interrupt.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure
+ * @param mask interrupt source
+ */
+void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask);
+
+/*! @} */
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the FlexIO I2S Tx DMA requests.
+ *
+ * @param base FlexIO I2S base pointer
+ * @param enable True means enable DMA, false means disable DMA.
+ */
+static inline void FLEXIO_I2S_TxEnableDMA(FLEXIO_I2S_Type *base, bool enable)
+{
+    FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->txShifterIndex, enable);
+}
+
+/*!
+ * @brief Enables/disables the FlexIO I2S Rx DMA requests.
+ *
+ * @param base FlexIO I2S base pointer
+ * @param enable True means enable DMA, false means disable DMA.
+ */
+static inline void FLEXIO_I2S_RxEnableDMA(FLEXIO_I2S_Type *base, bool enable)
+{
+    FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->rxShifterIndex, enable);
+}
+
+/*!
+ * @brief Gets the FlexIO I2S send data register address.
+ *
+ * This function returns the I2S data register address, mainly used by DMA/eDMA.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure
+ * @return FlexIO i2s send data register address.
+ */
+static inline uint32_t FLEXIO_I2S_TxGetDataRegisterAddress(FLEXIO_I2S_Type *base)
+{
+    return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->txShifterIndex);
+}
+
+/*!
+ * @brief Gets the FlexIO I2S receive data register address.
+ *
+ * This function returns the I2S data register address, mainly used by DMA/eDMA.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure
+ * @return FlexIO i2s receive data register address.
+ */
+static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base)
+{
+    return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->rxShifterIndex);
+}
+
+/*! @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Configures the FlexIO I2S audio format in master mode.
+ *
+ * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure
+ * @param format Pointer to FlexIO I2S audio data format structure.
+ * @param srcClock_Hz I2S master clock source frequency in Hz.
+*/
+void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Configures the FlexIO I2S audio format in slave mode.
+ *
+ * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure
+ * @param format Pointer to FlexIO I2S audio data format structure.
+*/
+void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format);
+
+/*!
+ * @brief Sends a piece of data using a blocking method.
+ *
+ * @note This function blocks via polling until data is ready to be sent.
+ *
+ * @param base FlexIO I2S base pointer.
+ * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param txData Pointer to the data to be written.
+ * @param size Bytes to be written.
+ */
+void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size);
+
+/*!
+ * @brief Writes a data into data register.
+ *
+ * @param base FlexIO I2S base pointer.
+ * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param data Data to be written.
+ */
+static inline void FLEXIO_I2S_WriteData(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint32_t data)
+{
+    base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth));
+}
+
+/*!
+ * @brief Receives a piece of data using a blocking method.
+ *
+ * @note This function blocks via polling until data is ready to be sent.
+ *
+ * @param base FlexIO I2S base pointer
+ * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param rxData Pointer to the data to be read.
+ * @param size Bytes to be read.
+ */
+void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size);
+
+/*!
+ * @brief Reads a data from the data register.
+ *
+ * @param base FlexIO I2S base pointer
+ * @return Data read from data register.
+ */
+static inline uint32_t FLEXIO_I2S_ReadData(FLEXIO_I2S_Type *base)
+{
+    return base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex];
+}
+
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FlexIO I2S handle.
+ *
+ * This function initializes the FlexIO I2S handle which can be used for other
+ * FlexIO I2S transactional APIs. Call this API once to get the
+ * initialized handle.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure
+ * @param handle pointer to flexio_i2s_handle_t structure to store the transfer state.
+ * @param callback FlexIO I2S callback function, which is called while finished a block.
+ * @param userData User parameter for the FlexIO I2S callback.
+ */
+void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
+                                       flexio_i2s_handle_t *handle,
+                                       flexio_i2s_callback_t callback,
+                                       void *userData);
+
+/*!
+ * @brief Configures the FlexIO I2S audio format.
+ *
+ * Audio format can be changed in run-time of FlexIO i2s. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure.
+ * @param handle FlexIO I2S handle pointer.
+ * @param format Pointer to audio data format structure.
+ * @param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.
+*/
+void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
+                                  flexio_i2s_handle_t *handle,
+                                  flexio_i2s_format_t *format,
+                                  uint32_t srcClock_Hz);
+
+/*!
+ * @brief Initializes the FlexIO I2S receive handle.
+ *
+ * This function initializes the FlexIO I2S handle which can be used for other
+ * FlexIO I2S transactional APIs. Usually, user only need to call this API once to get the
+ * initialized handle.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure.
+ * @param handle pointer to flexio_i2s_handle_t structure to store the transfer state.
+ * @param callback FlexIO I2S callback function, which is called while finished a block.
+ * @param userData User parameter for the FlexIO I2S callback.
+ */
+void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base,
+                                       flexio_i2s_handle_t *handle,
+                                       flexio_i2s_callback_t callback,
+                                       void *userData);
+
+/*!
+ * @brief Performs an interrupt non-blocking send transfer on FlexIO I2S.
+ *
+ * @note Calling the API returns immediately after transfer initiates.
+ * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether
+ * the transfer is finished. If the return status is 0, the transfer is finished.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure.
+ * @param handle pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * @param xfer pointer to flexio_i2s_transfer_t structure
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_FLEXIO_I2S_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * @retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
+                                            flexio_i2s_handle_t *handle,
+                                            flexio_i2s_transfer_t *xfer);
+
+/*!
+ * @brief Performs an interrupt non-blocking receive transfer on FlexIO I2S.
+ *
+ * @note The API returns immediately after transfer initiates.
+ * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether
+ * the transfer is finished. If the return status is 0, the transfer is finished.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure.
+ * @param handle pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * @param xfer pointer to flexio_i2s_transfer_t structure
+ * @retval kStatus_Success Successfully start the data receive.
+ * @retval kStatus_FLEXIO_I2S_RxBusy Previous receive still not finished.
+ * @retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
+                                               flexio_i2s_handle_t *handle,
+                                               flexio_i2s_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the current send.
+ *
+ * @note This API can be called at any time when interrupt non-blocking transfer initiates
+ * to abort the transfer in a early time.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure.
+ * @param handle pointer to flexio_i2s_handle_t structure which stores the transfer state
+ */
+void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle);
+
+/*!
+ * @brief Aborts the current receive.
+ *
+ * @note This API can be called at any time when interrupt non-blocking transfer initiates
+ * to abort the transfer in a early time.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure.
+ * @param handle pointer to flexio_i2s_handle_t structure which stores the transfer state
+ */
+void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle);
+
+/*!
+ * @brief Gets the remaining bytes to be sent.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure.
+ * @param handle pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * @param count Bytes sent.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Gets the remaining bytes to be received.
+ *
+ * @param base pointer to FLEXIO_I2S_Type structure.
+ * @param handle pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * @return count Bytes received.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Tx interrupt handler.
+ *
+ * @param i2sBase pointer to FLEXIO_I2S_Type structure.
+ * @param i2sHandle pointer to flexio_i2s_handle_t structure
+ */
+void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle);
+
+/*!
+ * @brief Rx interrupt handler.
+ *
+ * @param i2sBase pointer to FLEXIO_I2S_Type structure.
+ * @param i2sHandle pointer to flexio_i2s_handle_t structure
+ */
+void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+
+/*! @} */
+
+#endif /* _FSL_FLEXIO_I2S_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s_edma.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s_edma.c
new file mode 100644
index 00000000000..f5a2682fe52
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s_edma.c
@@ -0,0 +1,353 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_i2s_edma.h"
+
+/*******************************************************************************
+ * Definitations
+ ******************************************************************************/
+/* Used for 32byte aligned */
+#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)address + 32) & ~0x1FU)
+
+/*<! Structure definition for flexio_i2s_edma_private_handle_t. The structure is private. */
+typedef struct _flexio_i2s_edma_private_handle
+{
+    FLEXIO_I2S_Type *base;
+    flexio_i2s_edma_handle_t *handle;
+} flexio_i2s_edma_private_handle_t;
+
+enum _flexio_i2s_edma_transfer_state
+{
+    kFLEXIO_I2S_Busy = 0x0U, /*!< FLEXIO I2S is busy */
+    kFLEXIO_I2S_Idle,        /*!< Transfer is done. */
+};
+
+/*<! Private handle only used for internally. */
+static flexio_i2s_edma_private_handle_t s_edmaPrivateHandle[2];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief FLEXIO I2S EDMA callback for send.
+ *
+ * @param handle pointer to flexio_i2s_edma_handle_t structure which stores the transfer state.
+ * @param userData Parameter for user callback.
+ * @param done If the DMA transfer finished.
+ * @param tcds The TCD index.
+ */
+static void FLEXIO_I2S_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds);
+
+/*!
+ * @brief FLEXIO I2S EDMA callback for receive.
+ *
+ * @param handle pointer to flexio_i2s_edma_handle_t structure which stores the transfer state.
+ * @param userData Parameter for user callback.
+ * @param done If the DMA transfer finished.
+ * @param tcds The TCD index.
+ */
+static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds);
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+static void FLEXIO_I2S_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
+{
+    flexio_i2s_edma_private_handle_t *privHandle = (flexio_i2s_edma_private_handle_t *)userData;
+    flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle;
+
+    /* If finished a blcok, call the callback function */
+    memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
+    flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+    if (flexio_i2sHandle->callback)
+    {
+        (flexio_i2sHandle->callback)(privHandle->base, flexio_i2sHandle, kStatus_Success, flexio_i2sHandle->userData);
+    }
+
+    /* If all data finished, just stop the transfer */
+    if (flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver].data == NULL)
+    {
+        FLEXIO_I2S_TransferAbortSendEDMA(privHandle->base, flexio_i2sHandle);
+    }
+}
+
+static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
+{
+    flexio_i2s_edma_private_handle_t *privHandle = (flexio_i2s_edma_private_handle_t *)userData;
+    flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle;
+
+    /* If finished a blcok, call the callback function */
+    memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
+    flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+    if (flexio_i2sHandle->callback)
+    {
+        (flexio_i2sHandle->callback)(privHandle->base, flexio_i2sHandle, kStatus_Success, flexio_i2sHandle->userData);
+    }
+
+    /* If all data finished, just stop the transfer */
+    if (flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver].data == NULL)
+    {
+        FLEXIO_I2S_TransferAbortReceiveEDMA(privHandle->base, flexio_i2sHandle);
+    }
+}
+
+void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base,
+                                           flexio_i2s_edma_handle_t *handle,
+                                           flexio_i2s_edma_callback_t callback,
+                                           void *userData,
+                                           edma_handle_t *dmaHandle)
+{
+    assert(handle && dmaHandle);
+
+    /* Set flexio_i2s base to handle */
+    handle->dmaHandle = dmaHandle;
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Set FLEXIO I2S state to idle */
+    handle->state = kFLEXIO_I2S_Idle;
+
+    s_edmaPrivateHandle[0].base = base;
+    s_edmaPrivateHandle[0].handle = handle;
+
+    /* Need to use scatter gather */
+    EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), FLEXIO_I2S_XFER_QUEUE_SIZE);
+
+    /* Install callback for Tx dma channel */
+    EDMA_SetCallback(dmaHandle, FLEXIO_I2S_TxEDMACallback, &s_edmaPrivateHandle[0]);
+}
+
+void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base,
+                                           flexio_i2s_edma_handle_t *handle,
+                                           flexio_i2s_edma_callback_t callback,
+                                           void *userData,
+                                           edma_handle_t *dmaHandle)
+{
+    assert(handle && dmaHandle);
+
+    /* Set flexio_i2s base to handle */
+    handle->dmaHandle = dmaHandle;
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Set FLEXIO I2S state to idle */
+    handle->state = kFLEXIO_I2S_Idle;
+
+    s_edmaPrivateHandle[1].base = base;
+    s_edmaPrivateHandle[1].handle = handle;
+
+    /* Need to use scatter gather */
+    EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), FLEXIO_I2S_XFER_QUEUE_SIZE);
+
+    /* Install callback for Tx dma channel */
+    EDMA_SetCallback(dmaHandle, FLEXIO_I2S_RxEDMACallback, &s_edmaPrivateHandle[1]);
+}
+
+void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base,
+                                      flexio_i2s_edma_handle_t *handle,
+                                      flexio_i2s_format_t *format,
+                                      uint32_t srcClock_Hz)
+{
+    assert(handle && format);
+
+    /* Configure the audio format to FLEXIO I2S registers */
+    if (srcClock_Hz != 0)
+    {
+        /* It is master */
+        FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz);
+    }
+    else
+    {
+        FLEXIO_I2S_SlaveSetFormat(base, format);
+    }
+
+    /* Get the tranfer size from format, this should be used in EDMA configuration */
+    handle->bytesPerFrame = format->bitWidth / 8U;
+}
+
+status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
+                                     flexio_i2s_edma_handle_t *handle,
+                                     flexio_i2s_transfer_t *xfer)
+{
+    assert(handle && xfer);
+
+    edma_transfer_config_t config = {0};
+    uint32_t destAddr = FLEXIO_I2S_TxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame);
+
+    /* Check if input parameter invalid */
+    if ((xfer->data == NULL) || (xfer->dataSize == 0U))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->queue[handle->queueUser].data)
+    {
+        return kStatus_FLEXIO_I2S_QueueFull;
+    }
+
+    /* Change the state of handle */
+    handle->state = kFLEXIO_I2S_Busy;
+
+    /* Update the queue state */
+    handle->queue[handle->queueUser].data = xfer->data;
+    handle->queue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->transferSize[handle->queueUser] = xfer->dataSize;
+    handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+
+    /* Prepare edma configure */
+    EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame,
+                         handle->bytesPerFrame, xfer->dataSize, kEDMA_MemoryToPeripheral);
+
+    EDMA_SubmitTransfer(handle->dmaHandle, &config);
+
+    /* Start DMA transfer */
+    EDMA_StartTransfer(handle->dmaHandle);
+
+    /* Enable DMA enable bit */
+    FLEXIO_I2S_TxEnableDMA(base, true);
+
+    /* Enable FLEXIO I2S Tx clock */
+    FLEXIO_I2S_Enable(base, true);
+
+    return kStatus_Success;
+}
+
+status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
+                                        flexio_i2s_edma_handle_t *handle,
+                                        flexio_i2s_transfer_t *xfer)
+{
+    assert(handle && xfer);
+
+    edma_transfer_config_t config = {0};
+    uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame);
+
+    /* Check if input parameter invalid */
+    if ((xfer->data == NULL) || (xfer->dataSize == 0U))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->queue[handle->queueUser].data)
+    {
+        return kStatus_FLEXIO_I2S_QueueFull;
+    }
+
+    /* Change the state of handle */
+    handle->state = kFLEXIO_I2S_Busy;
+
+    /* Update queue state  */
+    handle->queue[handle->queueUser].data = xfer->data;
+    handle->queue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->transferSize[handle->queueUser] = xfer->dataSize;
+    handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+
+    /* Prepare edma configure */
+    EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame,
+                         handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory);
+
+    EDMA_SubmitTransfer(handle->dmaHandle, &config);
+
+    /* Start DMA transfer */
+    EDMA_StartTransfer(handle->dmaHandle);
+
+    /* Enable DMA enable bit */
+    FLEXIO_I2S_RxEnableDMA(base, true);
+
+    /* Enable FLEXIO I2S Rx clock */
+    FLEXIO_I2S_Enable(base, true);
+
+    return kStatus_Success;
+}
+
+void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)
+{
+    assert(handle);
+
+    /* Disable dma */
+    EDMA_AbortTransfer(handle->dmaHandle);
+
+    /* Disable DMA enable bit */
+    FLEXIO_I2S_TxEnableDMA(base, false);
+
+    /* Set the handle state */
+    handle->state = kFLEXIO_I2S_Idle;
+}
+
+void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)
+{
+    assert(handle);
+
+    /* Disable dma */
+    EDMA_AbortTransfer(handle->dmaHandle);
+
+    /* Disable DMA enable bit */
+    FLEXIO_I2S_RxEnableDMA(base, false);
+
+    /* Set the handle state */
+    handle->state = kFLEXIO_I2S_Idle;
+}
+
+status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != kFLEXIO_I2S_Busy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->transferSize[handle->queueDriver] -
+                 EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel);
+    }
+
+    return status;
+}
+
+status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != kFLEXIO_I2S_Busy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->transferSize[handle->queueDriver] -
+                 EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel);
+    }
+
+    return status;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s_edma.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s_edma.h
new file mode 100644
index 00000000000..0624701ccfb
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_i2s_edma.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_FLEXIO_I2S_EDMA_H_
+#define _FSL_FLEXIO_I2S_EDMA_H_
+
+#include "fsl_flexio_i2s.h"
+#include "fsl_edma.h"
+
+/*!
+ * @addtogroup flexio_edma_i2s
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t;
+
+/*! @brief FlexIO I2S eDMA transfer callback function for finish and error */
+typedef void (*flexio_i2s_edma_callback_t)(FLEXIO_I2S_Type *base,
+                                           flexio_i2s_edma_handle_t *handle,
+                                           status_t status,
+                                           void *userData);
+
+/*! @brief FlexIO I2S DMA transfer handle, users should not touch the content of the handle.*/
+struct _flexio_i2s_edma_handle
+{
+    edma_handle_t *dmaHandle;                        /*!< DMA handler for FlexIO I2S send */
+    uint8_t bytesPerFrame;                           /*!< Bytes in a frame */
+    uint32_t state;                                  /*!< Internal state for FlexIO I2S eDMA transfer */
+    flexio_i2s_edma_callback_t callback;             /*!< Callback for users while transfer finish or error occurred */
+    void *userData;                                  /*!< User callback parameter */
+    edma_tcd_t tcd[FLEXIO_I2S_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */
+    flexio_i2s_transfer_t queue[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */
+    size_t transferSize[FLEXIO_I2S_XFER_QUEUE_SIZE];         /*!< Data bytes need to transfer */
+    volatile uint8_t queueUser;                              /*!< Index for user to queue transfer. */
+    volatile uint8_t queueDriver;                            /*!< Index for driver to get the transfer data and size */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FlexIO I2S eDMA handle.
+ *
+ * This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master
+ * transactional APIs.
+ * Usually, for a specified FlexIO I2S instance, user need only call this API once to get the initialized handle.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S eDMA handle pointer.
+ * @param callback FlexIO I2S eDMA callback function called while finished a block.
+ * @param userData User parameter for callback.
+ * @param dmaHandle eDMA handle for FlexIO I2S. This handle shall be a static value allocated by users.
+ */
+void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base,
+                                           flexio_i2s_edma_handle_t *handle,
+                                           flexio_i2s_edma_callback_t callback,
+                                           void *userData,
+                                           edma_handle_t *dmaHandle);
+
+/*!
+ * @brief Initializes the FlexIO I2S Rx eDMA handle.
+ *
+ * This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional
+ * APIs.
+ * Usually, for a specified FlexIO I2S instance, user need only call this API once to get the initialized handle.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S eDMA handle pointer.
+ * @param callback FlexIO I2S eDMA callback function called while finished a block.
+ * @param userData User parameter for callback.
+ * @param dmaHandle eDMA handle for FlexIO I2S. This handle shall be a static value allocated by users.
+ */
+void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base,
+                                           flexio_i2s_edma_handle_t *handle,
+                                           flexio_i2s_edma_callback_t callback,
+                                           void *userData,
+                                           edma_handle_t *dmaHandle);
+
+/*!
+ * @brief Configures the FlexIO I2S Tx audio format.
+ *
+ * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred. This function also sets eDMA parameter according to format.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S eDMA handle pointer
+ * @param format Pointer to FlexIO I2S audio data format structure.
+ * @param srcClock_Hz FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode.
+ * @retval kStatus_Success Audio format set successfully.
+ * @retval kStatus_InvalidArgument The input arguments is invalid.
+*/
+void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base,
+                                      flexio_i2s_edma_handle_t *handle,
+                                      flexio_i2s_format_t *format,
+                                      uint32_t srcClock_Hz);
+
+/*!
+ * @brief Performs a non-blocking FlexIO I2S transfer using DMA.
+ *
+ * @note This interface returned immediately after transfer initiates, users should call
+ * FLEXIO_I2S_GetTransferStatus to poll the transfer status to check whether FlexIO I2S transfer finished.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ * @param xfer Pointer to DMA transfer structure.
+ * @retval kStatus_Success Start a FlexIO I2S eDMA send successfully.
+ * @retval kStatus_InvalidArgument The input arguments is invalid.
+ * @retval kStatus_TxBusy FlexIO I2S is busy sending data.
+ */
+status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
+                                     flexio_i2s_edma_handle_t *handle,
+                                     flexio_i2s_transfer_t *xfer);
+
+/*!
+ * @brief Performs a non-blocking FlexIO I2S receive using eDMA.
+ *
+ * @note This interface returned immediately after transfer initiates, users should call
+ * FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status to check whether FlexIO I2S transfer finished.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ * @param xfer Pointer to DMA transfer structure.
+ * @retval kStatus_Success Start a FlexIO I2S eDMA receive successfully.
+ * @retval kStatus_InvalidArgument The input arguments is invalid.
+ * @retval kStatus_RxBusy FlexIO I2S is busy receiving data.
+ */
+status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
+                                        flexio_i2s_edma_handle_t *handle,
+                                        flexio_i2s_transfer_t *xfer);
+
+/*!
+ * @brief Aborts a FlexIO I2S transfer using eDMA.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ */
+void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle);
+
+/*!
+ * @brief Aborts a FlexIO I2S receive using eDMA.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ */
+void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle);
+
+/*!
+ * @brief Gets the remaining bytes to be sent.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ * @param count Bytes sent.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Get the remaining bytes to be received.
+ *
+ * @param base FlexIO I2S peripheral base address.
+ * @param handle FlexIO I2S DMA handle pointer.
+ * @param count Bytes received.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi.c
new file mode 100644
index 00000000000..65c987a6ffd
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi.c
@@ -0,0 +1,935 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_spi.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
+enum _flexio_spi_transfer_states
+{
+    kFLEXIO_SPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver's queue. */
+    kFLEXIO_SPI_Busy,        /*!< Transmiter/Receive's queue is not finished. */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Send a piece of data for SPI.
+ *
+ * This function computes the number of data to be written into D register or Tx FIFO,
+ * and write the data into it. At the same time, this function updates the values in
+ * master handle structure.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure
+ * @param handle Pointer to SPI master handle structure.
+ */
+static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
+
+/*!
+ * @brief Receive a piece of data for SPI master.
+ *
+ * This function computes the number of data to receive from D register or Rx FIFO,
+ * and write the data to destination address. At the same time, this function updates
+ * the values in master handle structure.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure
+ * @param handle Pointer to SPI master handle structure.
+ */
+static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
+{
+    uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
+
+    if (handle->txData != NULL)
+    {
+        /* Transmit data and update tx size/buff. */
+        if (handle->bytePerFrame == 1U)
+        {
+            tmpData = *(handle->txData);
+            handle->txData++;
+        }
+        else
+        {
+            tmpData = (uint32_t)(handle->txData[0]) << 8U;
+            tmpData += handle->txData[1];
+            handle->txData += 2U;
+        }
+    }
+    else
+    {
+        tmpData = FLEXIO_SPI_DUMMYDATA;
+    }
+
+    handle->txRemainingBytes -= handle->bytePerFrame;
+
+    FLEXIO_SPI_WriteData(base, handle->direction, tmpData);
+
+    if (!handle->txRemainingBytes)
+    {
+        FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable);
+    }
+}
+
+static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
+{
+    uint16_t tmpData;
+
+    tmpData = FLEXIO_SPI_ReadData(base, handle->direction);
+
+    if (handle->rxData != NULL)
+    {
+        if (handle->bytePerFrame == 1U)
+        {
+            *handle->rxData = tmpData;
+            handle->rxData++;
+        }
+        else
+        {
+            *((uint16_t *)(handle->rxData)) = tmpData;
+            handle->rxData += 2U;
+        }
+    }
+    handle->rxRemainingBytes -= handle->bytePerFrame;
+}
+
+void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)
+{
+    assert(base);
+    assert(masterConfig);
+
+    flexio_shifter_config_t shifterConfig;
+    flexio_timer_config_t timerConfig;
+    uint32_t ctrlReg = 0;
+    uint16_t timerDiv = 0;
+    uint16_t timerCmp = 0;
+
+    /* Clear the shifterConfig & timerConfig struct. */
+    memset(&shifterConfig, 0, sizeof(shifterConfig));
+    memset(&timerConfig, 0, sizeof(timerConfig));
+
+    /* Ungate flexio clock. */
+    CLOCK_EnableClock(kCLOCK_Flexio0);
+
+    /* Configure FLEXIO SPI Master */
+    ctrlReg = base->flexioBase->CTRL;
+    ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
+    ctrlReg |= (FLEXIO_CTRL_DOZEN(masterConfig->enableInDoze) | FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) |
+                FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster));
+
+    base->flexioBase->CTRL = ctrlReg;
+
+    /* Do hardware configuration. */
+    /* 1. Configure the shifter 0 for tx. */
+    shifterConfig.timerSelect = base->timerIndex[0];
+    shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
+    shifterConfig.pinSelect = base->SDOPinIndex;
+    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+        shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
+        shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    }
+    else
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+        shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
+        shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
+    }
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
+
+    /* 2. Configure the shifter 1 for rx. */
+    shifterConfig.timerSelect = base->timerIndex[0];
+    shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect = base->SDIPinIndex;
+    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
+    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+    }
+    else
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+    }
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
+
+    /*3. Configure the timer 0 for SCK. */
+    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
+    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
+    timerConfig.pinSelect = base->SCKPinIndex;
+    timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
+    timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
+    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset = kFLEXIO_TimerResetNever;
+    timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
+    timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
+    timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
+    timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
+
+    timerDiv = srcClock_Hz / masterConfig->baudRate_Bps;
+    timerDiv = timerDiv / 2 - 1;
+
+    timerCmp = ((uint32_t)(masterConfig->dataMode * 2 - 1U)) << 8U;
+    timerCmp |= timerDiv;
+
+    timerConfig.timerCompare = timerCmp;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
+
+    /* 4. Configure the timer 1 for CSn. */
+    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
+    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
+    timerConfig.pinSelect = base->CSnPinIndex;
+    timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
+    timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
+    timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
+    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset = kFLEXIO_TimerResetNever;
+    timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
+    timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
+    timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
+    timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
+
+    timerConfig.timerCompare = 0xFFFFU;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
+}
+
+void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)
+{
+    /* Disable FLEXIO SPI module. */
+    FLEXIO_SPI_Enable(base, false);
+
+    /* Gate flexio clock. */
+    CLOCK_DisableClock(kCLOCK_Flexio0);
+}
+
+void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)
+{
+    assert(masterConfig);
+
+    masterConfig->enableMaster = true;
+    masterConfig->enableInDoze = false;
+    masterConfig->enableInDebug = true;
+    masterConfig->enableFastAccess = false;
+    /* Default baud rate 500kbps. */
+    masterConfig->baudRate_Bps = 500000U;
+    /* Default CPHA = 0. */
+    masterConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge;
+    /* Default bit count at 8. */
+    masterConfig->dataMode = kFLEXIO_SPI_8BitMode;
+}
+
+void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)
+{
+    assert(base && slaveConfig);
+
+    flexio_shifter_config_t shifterConfig;
+    flexio_timer_config_t timerConfig;
+    uint32_t ctrlReg = 0;
+
+    /* Clear the shifterConfig & timerConfig struct. */
+    memset(&shifterConfig, 0, sizeof(shifterConfig));
+    memset(&timerConfig, 0, sizeof(timerConfig));
+
+    /* Ungate flexio clock. */
+    CLOCK_EnableClock(kCLOCK_Flexio0);
+
+    /* Configure FLEXIO SPI Slave */
+    ctrlReg = base->flexioBase->CTRL;
+    ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
+    ctrlReg |= (FLEXIO_CTRL_DOZEN(slaveConfig->enableInDoze) | FLEXIO_CTRL_DBGE(slaveConfig->enableInDebug) |
+                FLEXIO_CTRL_FASTACC(slaveConfig->enableFastAccess) | FLEXIO_CTRL_FLEXEN(slaveConfig->enableSlave));
+
+    base->flexioBase->CTRL = ctrlReg;
+
+    /* Do hardware configuration. */
+    /* 1. Configure the shifter 0 for tx. */
+    shifterConfig.timerSelect = base->timerIndex[0];
+    shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
+    shifterConfig.pinSelect = base->SDOPinIndex;
+    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
+    if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+        shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    }
+    else
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+        shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
+    }
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
+
+    /* 2. Configure the shifter 1 for rx. */
+    shifterConfig.timerSelect = base->timerIndex[0];
+    shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect = base->SDIPinIndex;
+    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
+    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+    }
+    else
+    {
+        shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+    }
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
+
+    /*3. Configure the timer 0 for shift clock. */
+    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
+    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect = base->SCKPinIndex;
+    timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
+    timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
+    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
+    timerConfig.timerReset = kFLEXIO_TimerResetNever;
+    timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge;
+    timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
+    if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
+    {
+        /* The configuration kFLEXIO_TimerDisableOnTimerCompare only support continuous
+        PCS access, change to kFLEXIO_TimerDisableNever to enable discontinuous PCS access. */
+        timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
+        timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
+    }
+    else
+    {
+        timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge;
+        timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
+    }
+
+    timerConfig.timerCompare = slaveConfig->dataMode * 2 - 1U;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
+}
+
+void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)
+{
+    FLEXIO_SPI_MasterDeinit(base);
+}
+
+void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)
+{
+    assert(slaveConfig);
+
+    slaveConfig->enableSlave = true;
+    slaveConfig->enableInDoze = false;
+    slaveConfig->enableInDebug = true;
+    slaveConfig->enableFastAccess = false;
+    /* Default CPHA = 0. */
+    slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge;
+    /* Default bit count at 8. */
+    slaveConfig->dataMode = kFLEXIO_SPI_8BitMode;
+}
+
+void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
+{
+    if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]);
+    }
+    if (mask & kFLEXIO_SPI_RxFullInterruptEnable)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]);
+    }
+}
+
+void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
+{
+    if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]);
+    }
+    if (mask & kFLEXIO_SPI_RxFullInterruptEnable)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]);
+    }
+}
+
+void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)
+{
+    if (mask & kFLEXIO_SPI_TxDmaEnable)
+    {
+        FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[0], enable);
+    }
+
+    if (mask & kFLEXIO_SPI_RxDmaEnable)
+    {
+        FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[1], enable);
+    }
+}
+
+uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)
+{
+    uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase);
+    uint32_t status = 0;
+
+    status = ((shifterStatus & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]);
+    status |= (((shifterStatus & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U);
+
+    return status;
+}
+
+void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)
+{
+    if (mask & kFLEXIO_SPI_TxBufferEmptyFlag)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]);
+    }
+    if (mask & kFLEXIO_SPI_RxBufferFullFlag)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]);
+    }
+}
+
+void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)
+{
+    uint16_t timerDiv = 0;
+    uint16_t timerCmp = 0;
+    FLEXIO_Type *flexioBase = base->flexioBase;
+
+    /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/
+    timerDiv = srcClockHz / baudRate_Bps;
+    timerDiv = timerDiv / 2 - 1U;
+
+    timerCmp = flexioBase->TIMCMP[base->timerIndex[0]];
+    timerCmp &= 0xFF00U;
+    timerCmp |= timerDiv;
+
+    flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
+}
+
+void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
+                              flexio_spi_shift_direction_t direction,
+                              const uint8_t *buffer,
+                              size_t size)
+{
+    assert(buffer);
+    assert(size);
+
+    while (size--)
+    {
+        /* Wait until data transfer complete. */
+        while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag))
+        {
+        }
+        FLEXIO_SPI_WriteData(base, direction, *buffer++);
+    }
+}
+
+void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
+                             flexio_spi_shift_direction_t direction,
+                             uint8_t *buffer,
+                             size_t size)
+{
+    assert(buffer);
+    assert(size);
+
+    while (size--)
+    {
+        /* Wait until data transfer complete. */
+        while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag))
+        {
+        }
+        *buffer++ = FLEXIO_SPI_ReadData(base, direction);
+    }
+}
+
+void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)
+{
+    flexio_spi_shift_direction_t direction;
+    uint8_t bytesPerFrame;
+    uint32_t dataMode = 0;
+    uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]];
+    uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
+
+    timerCmp &= 0x00FFU;
+    /* Configure the values in handle. */
+    switch (xfer->flags)
+    {
+        case kFLEXIO_SPI_8bitMsb:
+            dataMode = (8 * 2 - 1U) << 8U;
+            bytesPerFrame = 1;
+            direction = kFLEXIO_SPI_MsbFirst;
+            break;
+
+        case kFLEXIO_SPI_8bitLsb:
+            dataMode = (8 * 2 - 1U) << 8U;
+            bytesPerFrame = 1;
+            direction = kFLEXIO_SPI_LsbFirst;
+            break;
+
+        case kFLEXIO_SPI_16bitMsb:
+            dataMode = (16 * 2 - 1U) << 8U;
+            bytesPerFrame = 2;
+            direction = kFLEXIO_SPI_MsbFirst;
+            break;
+
+        case kFLEXIO_SPI_16bitLsb:
+            dataMode = (16 * 2 - 1U) << 8U;
+            bytesPerFrame = 2;
+            direction = kFLEXIO_SPI_LsbFirst;
+            break;
+
+        default:
+            dataMode = (8 * 2 - 1U) << 8U;
+            bytesPerFrame = 1;
+            direction = kFLEXIO_SPI_MsbFirst;
+            assert(true);
+            break;
+    }
+
+    dataMode |= timerCmp;
+
+    /* Configure transfer size. */
+    base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
+
+    while (xfer->dataSize)
+    {
+        /* Wait until data transfer complete. */
+        while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag))
+        {
+        }
+        if (xfer->txData != NULL)
+        {
+            /* Transmit data and update tx size/buff. */
+            if (bytesPerFrame == 1U)
+            {
+                tmpData = *(xfer->txData);
+                xfer->txData++;
+            }
+            else
+            {
+                tmpData = (uint32_t)(xfer->txData[0]) << 8U;
+                tmpData += xfer->txData[1];
+                xfer->txData += 2U;
+            }
+        }
+        else
+        {
+            tmpData = FLEXIO_SPI_DUMMYDATA;
+        }
+
+        xfer->dataSize -= bytesPerFrame;
+
+        FLEXIO_SPI_WriteData(base, direction, tmpData);
+
+        while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag))
+        {
+        }
+        tmpData = FLEXIO_SPI_ReadData(base, direction);
+
+        if (xfer->rxData != NULL)
+        {
+            if (bytesPerFrame == 1U)
+            {
+                *xfer->rxData = tmpData;
+                xfer->rxData++;
+            }
+            else
+            {
+                *((uint16_t *)(xfer->rxData)) = tmpData;
+                xfer->rxData += 2U;
+            }
+        }
+    }
+}
+
+status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
+                                               flexio_spi_master_handle_t *handle,
+                                               flexio_spi_master_transfer_callback_t callback,
+                                               void *userData)
+{
+    assert(handle);
+
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Register callback and userData. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Enable interrupt in NVIC. */
+    EnableIRQ(flexio_irqs[0]);
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ);
+}
+
+status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
+                                              flexio_spi_master_handle_t *handle,
+                                              flexio_spi_transfer_t *xfer)
+{
+    assert(handle);
+    assert(xfer);
+
+    uint32_t dataMode = 0;
+    uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]];
+    uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
+
+    timerCmp &= 0x00FFU;
+
+    /* Check if SPI is busy. */
+    if (handle->state == kFLEXIO_SPI_Busy)
+    {
+        return kStatus_FLEXIO_SPI_Busy;
+    }
+
+    /* Check if the argument is legal. */
+    if ((xfer->txData == NULL) && (xfer->rxData == NULL))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Configure the values in handle */
+    switch (xfer->flags)
+    {
+        case kFLEXIO_SPI_8bitMsb:
+            dataMode = (8 * 2 - 1U) << 8U;
+            handle->bytePerFrame = 1U;
+            handle->direction = kFLEXIO_SPI_MsbFirst;
+            break;
+        case kFLEXIO_SPI_8bitLsb:
+            dataMode = (8 * 2 - 1U) << 8U;
+            handle->bytePerFrame = 1U;
+            handle->direction = kFLEXIO_SPI_LsbFirst;
+            break;
+        case kFLEXIO_SPI_16bitMsb:
+            dataMode = (16 * 2 - 1U) << 8U;
+            handle->bytePerFrame = 2U;
+            handle->direction = kFLEXIO_SPI_MsbFirst;
+            break;
+        case kFLEXIO_SPI_16bitLsb:
+            dataMode = (16 * 2 - 1U) << 8U;
+            handle->bytePerFrame = 2U;
+            handle->direction = kFLEXIO_SPI_LsbFirst;
+            break;
+        default:
+            dataMode = (8 * 2 - 1U) << 8U;
+            handle->bytePerFrame = 1U;
+            handle->direction = kFLEXIO_SPI_MsbFirst;
+            assert(true);
+            break;
+    }
+
+    dataMode |= timerCmp;
+
+    /* Configure transfer size. */
+    base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
+
+    handle->state = kFLEXIO_SPI_Busy;
+    handle->txData = xfer->txData;
+    handle->rxData = xfer->rxData;
+    handle->rxRemainingBytes = xfer->dataSize;
+
+    /* Save total transfer size. */
+    handle->transferSize = xfer->dataSize;
+
+    /* Send first byte of data to trigger the rx interrupt. */
+    if (handle->txData != NULL)
+    {
+        /* Transmit data and update tx size/buff. */
+        if (handle->bytePerFrame == 1U)
+        {
+            tmpData = *(handle->txData);
+            handle->txData++;
+        }
+        else
+        {
+            tmpData = (uint32_t)(handle->txData[0]) << 8U;
+            tmpData += handle->txData[1];
+            handle->txData += 2U;
+        }
+    }
+    else
+    {
+        tmpData = FLEXIO_SPI_DUMMYDATA;
+    }
+
+    handle->txRemainingBytes = xfer->dataSize - handle->bytePerFrame;
+
+    FLEXIO_SPI_WriteData(base, handle->direction, tmpData);
+
+    /* Enable transmit and receive interrupt to handle rx. */
+    FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable);
+
+    return kStatus_Success;
+}
+
+status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Return remaing bytes in different cases. */
+    if (handle->rxData)
+    {
+        *count = handle->transferSize - handle->rxRemainingBytes;
+    }
+    else
+    {
+        *count = handle->transferSize - handle->txRemainingBytes;
+    }
+
+    return kStatus_Success;
+}
+
+void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
+{
+    assert(handle);
+
+    FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable);
+    FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable);
+
+    /* Transfer finished, set the state to idle. */
+    handle->state = kFLEXIO_SPI_Idle;
+
+    /* Clear the internal state. */
+    handle->rxRemainingBytes = 0;
+    handle->txRemainingBytes = 0;
+}
+
+void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
+{
+    assert(spiHandle);
+
+    flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle;
+    FLEXIO_SPI_Type *base;
+    uint32_t status;
+
+    if (handle->state == kFLEXIO_SPI_Idle)
+    {
+        return;
+    }
+
+    base = (FLEXIO_SPI_Type *)spiType;
+    status = FLEXIO_SPI_GetStatusFlags(base);
+
+    /* Handle rx. */
+    if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes))
+    {
+        FLEXIO_SPI_TransferReceiveTransaction(base, handle);
+    }
+
+    /* Handle tx. */
+    if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes))
+    {
+        FLEXIO_SPI_TransferSendTransaction(base, handle);
+    }
+
+    /* All the transfer finished. */
+    if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U))
+    {
+        FLEXIO_SPI_MasterTransferAbort(base, handle);
+        if (handle->callback)
+        {
+            (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData);
+        }
+    }
+}
+
+status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
+                                              flexio_spi_slave_handle_t *handle,
+                                              flexio_spi_slave_transfer_callback_t callback,
+                                              void *userData)
+{
+    assert(handle);
+
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Register callback and userData. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Enable interrupt in NVIC. */
+    EnableIRQ(flexio_irqs[0]);
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ);
+}
+
+status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
+                                             flexio_spi_slave_handle_t *handle,
+                                             flexio_spi_transfer_t *xfer)
+{
+    assert(handle);
+    assert(xfer);
+
+    uint32_t dataMode = 0;
+
+    /* Check if SPI is busy. */
+    if (handle->state == kFLEXIO_SPI_Busy)
+    {
+        return kStatus_FLEXIO_SPI_Busy;
+    }
+
+    /* Check if the argument is legal. */
+    if ((xfer->txData == NULL) && (xfer->rxData == NULL))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Configure the values in handle */
+    switch (xfer->flags)
+    {
+        case kFLEXIO_SPI_8bitMsb:
+            dataMode = 8 * 2 - 1U;
+            handle->bytePerFrame = 1U;
+            handle->direction = kFLEXIO_SPI_MsbFirst;
+            break;
+        case kFLEXIO_SPI_8bitLsb:
+            dataMode = 8 * 2 - 1U;
+            handle->bytePerFrame = 1U;
+            handle->direction = kFLEXIO_SPI_LsbFirst;
+            break;
+        case kFLEXIO_SPI_16bitMsb:
+            dataMode = 16 * 2 - 1U;
+            handle->bytePerFrame = 2U;
+            handle->direction = kFLEXIO_SPI_MsbFirst;
+            break;
+        case kFLEXIO_SPI_16bitLsb:
+            dataMode = 16 * 2 - 1U;
+            handle->bytePerFrame = 2U;
+            handle->direction = kFLEXIO_SPI_LsbFirst;
+            break;
+        default:
+            dataMode = 8 * 2 - 1U;
+            handle->bytePerFrame = 1U;
+            handle->direction = kFLEXIO_SPI_MsbFirst;
+            assert(true);
+            break;
+    }
+
+    /* Configure transfer size. */
+    base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
+
+    handle->state = kFLEXIO_SPI_Busy;
+    handle->txData = xfer->txData;
+    handle->rxData = xfer->rxData;
+    handle->txRemainingBytes = xfer->dataSize;
+    handle->rxRemainingBytes = xfer->dataSize;
+
+    /* Save total transfer size. */
+    handle->transferSize = xfer->dataSize;
+
+    /* Enable transmit and receive interrupt to handle tx and rx. */
+    FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable);
+    FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable);
+
+    return kStatus_Success;
+}
+
+void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)
+{
+    assert(spiHandle);
+
+    flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle;
+    FLEXIO_SPI_Type *base;
+    uint32_t status;
+
+    if (handle->state == kFLEXIO_SPI_Idle)
+    {
+        return;
+    }
+
+    base = (FLEXIO_SPI_Type *)spiType;
+    status = FLEXIO_SPI_GetStatusFlags(base);
+
+    /* Handle tx. */
+    if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes))
+    {
+        FLEXIO_SPI_TransferSendTransaction(base, handle);
+    }
+
+    /* Handle rx. */
+    if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes))
+    {
+        FLEXIO_SPI_TransferReceiveTransaction(base, handle);
+    }
+
+    /* All the transfer finished. */
+    if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U))
+    {
+        FLEXIO_SPI_SlaveTransferAbort(base, handle);
+        if (handle->callback)
+        {
+            (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData);
+        }
+    }
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi.h
new file mode 100644
index 00000000000..8bdad286e06
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi.h
@@ -0,0 +1,707 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_FLEXIO_SPI_H_
+#define _FSL_FLEXIO_SPI_H_
+
+#include "fsl_common.h"
+#include "fsl_flexio.h"
+
+/*!
+ * @addtogroup flexio_spi
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexIO SPI driver version 2.1.0. */
+#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*@}*/
+
+/*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */
+#define FLEXIO_SPI_DUMMYDATA (0xFFFFU)
+
+/*! @brief Error codes for the FlexIO SPI driver. */
+enum _flexio_spi_status
+{
+    kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1),  /*!< FlexIO SPI is busy. */
+    kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2),  /*!< SPI is idle */
+    kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */
+};
+
+/*! @brief FlexIO SPI clock phase configuration. */
+typedef enum _flexio_spi_clock_phase
+{
+    kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U,  /*!< First edge on SPSCK occurs at the middle of the first
+                                   *   cycle of a data transfer. */
+    kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the
+                                   *   first cycle of a data transfer. */
+} flexio_spi_clock_phase_t;
+
+/*! @brief FlexIO SPI data shifter direction options. */
+typedef enum _flexio_spi_shift_direction
+{
+    kFLEXIO_SPI_MsbFirst = 0, /*!< Data transfers start with most significant bit. */
+    kFLEXIO_SPI_LsbFirst = 1, /*!< Data transfers start with least significant bit. */
+} flexio_spi_shift_direction_t;
+
+/*! @brief FlexIO SPI data length mode options. */
+typedef enum _flexio_spi_data_bitcount_mode
+{
+    kFLEXIO_SPI_8BitMode = 0x08U,  /*!< 8-bit data transmission mode. */
+    kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */
+} flexio_spi_data_bitcount_mode_t;
+
+/*! @brief Define FlexIO SPI interrupt mask. */
+enum _flexio_spi_interrupt_enable
+{
+    kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
+    kFLEXIO_SPI_RxFullInterruptEnable = 0x2U,  /*!< Receive buffer full interrupt enable. */
+};
+
+/*! @brief Define FlexIO SPI status mask. */
+enum _flexio_spi_status_flags
+{
+    kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
+    kFLEXIO_SPI_RxBufferFullFlag = 0x2U,  /*!< Receive buffer full flag. */
+};
+
+/*! @brief Define FlexIO SPI DMA mask. */
+enum _flexio_spi_dma_enable
+{
+    kFLEXIO_SPI_TxDmaEnable = 0x1U,  /*!< Tx DMA request source */
+    kFLEXIO_SPI_RxDmaEnable = 0x2U,  /*!< Rx DMA request source */
+    kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/
+};
+
+/*! @brief Define FlexIO SPI transfer flags. */
+enum _flexio_spi_transfer_flags
+{
+    kFLEXIO_SPI_8bitMsb = 0x1U,  /*!< FlexIO SPI 8-bit MSB first */
+    kFLEXIO_SPI_8bitLsb = 0x2U,  /*!< FlexIO SPI 8-bit LSB first */
+    kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */
+    kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */
+};
+
+/*! @brief Define FlexIO SPI access structure typedef. */
+typedef struct _flexio_spi_type
+{
+    FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */
+    uint8_t SDOPinIndex;     /*!< Pin select for data output. */
+    uint8_t SDIPinIndex;     /*!< Pin select for data input. */
+    uint8_t SCKPinIndex;     /*!< Pin select for clock. */
+    uint8_t CSnPinIndex;     /*!< Pin select for enable. */
+    uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO SPI. */
+    uint8_t timerIndex[2];   /*!< Timer index used in FlexIO SPI. */
+} FLEXIO_SPI_Type;
+
+/*! @brief Define FlexIO SPI master configuration structure. */
+typedef struct _flexio_spi_master_config
+{
+    bool enableMaster;                        /*!< Enable/disable FlexIO SPI master after configuration. */
+    bool enableInDoze;                        /*!< Enable/disable FlexIO operation in doze mode. */
+    bool enableInDebug;                       /*!< Enable/disable FlexIO operation in debug mode. */
+    bool enableFastAccess;                    /*!< Enable/disable fast access to FlexIO registers,
+                                              fast access requires the FlexIO clock to be at least
+                                              twice the frequency of the bus clock. */
+    uint32_t baudRate_Bps;                    /*!< Baud rate in Bps. */
+    flexio_spi_clock_phase_t phase;           /*!< Clock phase. */
+    flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */
+} flexio_spi_master_config_t;
+
+/*! @brief Define FlexIO SPI slave configuration structure. */
+typedef struct _flexio_spi_slave_config
+{
+    bool enableSlave;                         /*!< Enable/disable FlexIO SPI slave after configuration. */
+    bool enableInDoze;                        /*!< Enable/disable FlexIO operation in doze mode. */
+    bool enableInDebug;                       /*!< Enable/disable FlexIO operation in debug mode. */
+    bool enableFastAccess;                    /*!< Enable/disable fast access to FlexIO registers,
+                                              fast access requires the FlexIO clock to be at least
+                                              twice the frequency of the bus clock. */
+    flexio_spi_clock_phase_t phase;           /*!< Clock phase. */
+    flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */
+} flexio_spi_slave_config_t;
+
+/*! @brief Define FlexIO SPI transfer structure. */
+typedef struct _flexio_spi_transfer
+{
+    uint8_t *txData; /*!< Send buffer. */
+    uint8_t *rxData; /*!< Receive buffer. */
+    size_t dataSize; /*!< Transfer bytes. */
+    uint8_t flags;   /*!< FlexIO SPI control flag, MSB first  or LSB first. */
+} flexio_spi_transfer_t;
+
+/*! @brief  typedef for flexio_spi_master_handle_t in advance. */
+typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t;
+
+/*! @brief  Slave handle is the same with master handle. */
+typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t;
+
+/*! @brief FlexIO SPI master callback for finished transmit */
+typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base,
+                                                      flexio_spi_master_handle_t *handle,
+                                                      status_t status,
+                                                      void *userData);
+
+/*! @brief FlexIO SPI slave callback for finished transmit */
+typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base,
+                                                     flexio_spi_slave_handle_t *handle,
+                                                     status_t status,
+                                                     void *userData);
+
+/*! @brief Define FlexIO SPI handle structure. */
+struct _flexio_spi_master_handle
+{
+    uint8_t *txData;                                /*!< Transfer buffer. */
+    uint8_t *rxData;                                /*!< Receive buffer. */
+    size_t transferSize;                            /*!< Total bytes to be transferred. */
+    volatile size_t txRemainingBytes;               /*!< Send data remaining in bytes. */
+    volatile size_t rxRemainingBytes;               /*!< Receive data remaining in bytes. */
+    volatile uint32_t state;                        /*!< FlexIO SPI internal state. */
+    uint8_t bytePerFrame;                           /*!< SPI mode, 2bytes or 1byte in a frame */
+    flexio_spi_shift_direction_t direction;         /*!< Shift direction. */
+    flexio_spi_master_transfer_callback_t callback; /*!< FlexIO SPI callback. */
+    void *userData;                                 /*!< Callback parameter. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name FlexIO SPI Configuration
+ * @{
+ */
+
+/*!
+ * @brief Ungates the FlexIO clock, resets the FlexIO module and configures the FlexIO SPI master hardware,
+ * and configures the FlexIO SPI with FlexIO SPI master configuration. The
+ * configuration structure can be filled by the user, or be set with default values
+ * by the FLEXIO_SPI_MasterGetDefaultConfig().
+ *
+ * @note FlexIO SPI master only support CPOL = 0, which means clock inactive low.
+ *
+ * Example
+   @code
+   FLEXIO_SPI_Type spiDev = {
+   .flexioBase = FLEXIO,
+   .SDOPinIndex = 0,
+   .SDIPinIndex = 1,
+   .SCKPinIndex = 2,
+   .CSnPinIndex = 3,
+   .shifterIndex = {0,1},
+   .timerIndex = {0,1}
+   };
+   flexio_spi_master_config_t config = {
+   .enableMaster = true,
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .baudRate_Bps = 500000,
+   .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
+   .direction = kFLEXIO_SPI_MsbFirst,
+   .dataMode = kFLEXIO_SPI_8BitMode
+   };
+   FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);
+   @endcode
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param masterConfig Pointer to the flexio_spi_master_config_t structure.
+ * @param srcClock_Hz FlexIO source clock in Hz.
+*/
+void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Gates the FlexIO clock.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type.
+*/
+void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base);
+
+/*!
+ * @brief Gets the default configuration to configure the FlexIO SPI master. The configuration
+ * can be used directly by calling the FLEXIO_SPI_MasterConfigure().
+ * Example:
+   @code
+   flexio_spi_master_config_t masterConfig;
+   FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);
+   @endcode
+ * @param masterConfig Pointer to the flexio_spi_master_config_t structure.
+*/
+void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig);
+
+/*!
+ * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware
+ * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The
+ * configuration structure can be filled by the user, or be set with default values
+ * by the FLEXIO_SPI_SlaveGetDefaultConfig().
+ *
+ * @note Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored.
+ * FlexIO SPI slave only support CPOL = 0, which means clock inactive low.
+ * Example
+   @code
+   FLEXIO_SPI_Type spiDev = {
+   .flexioBase = FLEXIO,
+   .SDOPinIndex = 0,
+   .SDIPinIndex = 1,
+   .SCKPinIndex = 2,
+   .CSnPinIndex = 3,
+   .shifterIndex = {0,1},
+   .timerIndex = {0}
+   };
+   flexio_spi_slave_config_t config = {
+   .enableSlave = true,
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
+   .direction = kFLEXIO_SPI_MsbFirst,
+   .dataMode = kFLEXIO_SPI_8BitMode
+   };
+   FLEXIO_SPI_SlaveInit(&spiDev, &config);
+   @endcode
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
+*/
+void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig);
+
+/*!
+ * @brief Gates the FlexIO clock.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type.
+*/
+void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base);
+
+/*!
+ * @brief Gets the default configuration to configure the FlexIO SPI slave. The configuration
+ * can be used directly for calling the FLEXIO_SPI_SlaveConfigure().
+ * Example:
+   @code
+   flexio_spi_slave_config_t slaveConfig;
+   FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);
+   @endcode
+ * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
+*/
+void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig);
+
+/*@}*/
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets FlexIO SPI status flags.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @return status flag; Use the status flag to AND the following flag mask and get the status.
+ *          @arg kFLEXIO_SPI_TxEmptyFlag
+ *          @arg kFLEXIO_SPI_RxEmptyFlag
+*/
+
+uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base);
+
+/*!
+ * @brief Clears FlexIO SPI status flags.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param mask status flag
+ *      The parameter can be any combination of the following values:
+ *          @arg kFLEXIO_SPI_TxEmptyFlag
+ *          @arg kFLEXIO_SPI_RxEmptyFlag
+*/
+
+void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask);
+
+/*@}*/
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the FlexIO SPI interrupt.
+ *
+ * This function enables the FlexIO SPI interrupt.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param mask interrupt source. The parameter can be any combination of the following values:
+ *        @arg kFLEXIO_SPI_RxFullInterruptEnable
+ *        @arg kFLEXIO_SPI_TxEmptyInterruptEnable
+ */
+void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the FlexIO SPI interrupt.
+ *
+ * This function disables the FlexIO SPI interrupt.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param mask interrupt source The parameter can be any combination of the following values:
+ *        @arg kFLEXIO_SPI_RxFullInterruptEnable
+ *        @arg kFLEXIO_SPI_TxEmptyInterruptEnable
+ */
+void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
+
+/*@}*/
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA,
+ * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param mask SPI DMA source.
+ * @param enable True means enable DMA, false means disable DMA.
+ */
+void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable);
+
+/*!
+ * @brief Gets the FlexIO SPI transmit data register address for MSB first transfer.
+ *
+ * This function returns the SPI data register address, which is mainly used by DMA/eDMA.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param direction Shift direction of MSB first or LSB first.
+ * @return FlexIO SPI transmit data register address.
+ */
+static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base,
+                                                           flexio_spi_shift_direction_t direction)
+{
+    if (direction == kFLEXIO_SPI_MsbFirst)
+    {
+        return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped,
+                                              base->shifterIndex[0]) +
+               3U;
+    }
+    else
+    {
+        return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]);
+    }
+}
+
+/*!
+ * @brief Gets the FlexIO SPI receive data register address for the MSB first transfer.
+ *
+ * This function returns the SPI data register address, which is mainly used by DMA/eDMA.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param direction Shift direction of MSB first or LSB first.
+ * @return FlexIO SPI receive data register address.
+ */
+static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base,
+                                                           flexio_spi_shift_direction_t direction)
+{
+    if (direction == kFLEXIO_SPI_MsbFirst)
+    {
+        return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->shifterIndex[1]);
+    }
+    else
+    {
+        return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferByteSwapped,
+                                              base->shifterIndex[1]);
+    }
+}
+
+/*@}*/
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the FlexIO SPI module operation.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type.
+ * @param enable True to enable, false to disable.
+*/
+static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+    else
+    {
+        base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+/*!
+ * @brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param baudRate_Bps Baud Rate needed in Hz.
+ * @param srcClockHz SPI source clock frequency in Hz.
+ */
+void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz);
+
+/*!
+ * @brief Writes one byte of data, which is sent using the MSB method.
+ *
+ * @note This is a non-blocking API, which returns directly after the data is put into the
+ * data register but the data transfer is not finished on the bus. Ensure that
+ * the TxEmptyFlag is asserted before calling this API.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param direction Shift direction of MSB first or LSB first.
+ * @param data 8 bit/16 bit data.
+ */
+static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint16_t data)
+{
+    if (direction == kFLEXIO_SPI_MsbFirst)
+    {
+        base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data;
+    }
+    else
+    {
+        base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = data;
+    }
+}
+
+/*!
+ * @brief Reads 8 bit/16 bit data.
+ *
+ * @note This is a non-blocking API, which returns directly after the data is read from the
+ * data register. Ensure that the RxFullFlag is asserted before calling this API.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param direction Shift direction of MSB first or LSB first.
+ * @return 8 bit/16 bit data received.
+ */
+static inline uint16_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
+{
+    if (direction == kFLEXIO_SPI_MsbFirst)
+    {
+        return base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]];
+    }
+    else
+    {
+        return base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]];
+    }
+}
+
+/*!
+ * @brief Sends a buffer of data bytes.
+ *
+ * @note This function blocks using the polling method until all bytes have been sent.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param direction Shift direction of MSB first or LSB first.
+ * @param buffer The data bytes to send.
+ * @param size The number of data bytes to send.
+ */
+void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
+                              flexio_spi_shift_direction_t direction,
+                              const uint8_t *buffer,
+                              size_t size);
+
+/*!
+ * @brief Receives a buffer of bytes.
+ *
+ * @note This function blocks using the polling method until all bytes have been received.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param direction Shift direction of MSB first or LSB first.
+ * @param buffer The buffer to store the received bytes.
+ * @param size The number of data bytes to be received.
+ * @param direction Shift direction of MSB first or LSB first.
+ */
+void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
+                             flexio_spi_shift_direction_t direction,
+                             uint8_t *buffer,
+                             size_t size);
+
+/*!
+ * @brief Receives a buffer of bytes.
+ *
+ * @note This function blocks via polling until all bytes have been received.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure
+ * @param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t.
+ */
+void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer);
+
+/*Transactional APIs*/
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FlexIO SPI Master handle, which is used in transactional functions.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
+                                               flexio_spi_master_handle_t *handle,
+                                               flexio_spi_master_transfer_callback_t callback,
+                                               void *userData);
+
+/*!
+ * @brief Master transfer data using IRQ.
+ *
+ * This function sends data using IRQ. This is a non-blocking function, which returns
+ * right away. When all data is sent out/received, the callback function is called.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
+                                              flexio_spi_master_handle_t *handle,
+                                              flexio_spi_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the master data transfer, which used IRQ.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ */
+void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
+
+/*!
+ * @brief Gets the data transfer status which used IRQ.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief FlexIO SPI master IRQ handler function.
+ *
+ * @param spiType Pointer to the FLEXIO_SPI_Type structure.
+ * @param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ */
+void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle);
+
+/*!
+ * @brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
+                                              flexio_spi_slave_handle_t *handle,
+                                              flexio_spi_slave_transfer_callback_t callback,
+                                              void *userData);
+
+/*!
+ * @brief Slave transfer data using IRQ.
+ *
+ * This function sends data using IRQ. This is a non-blocking function, which returns
+ * right away. When all data is sent out/received, the callback function is called.
+ * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer.
+ */
+status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
+                                             flexio_spi_slave_handle_t *handle,
+                                             flexio_spi_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the slave data transfer which used IRQ, share same API with master.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ */
+static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle)
+{
+    FLEXIO_SPI_MasterTransferAbort(base, handle);
+}
+/*!
+ * @brief Gets the data transfer status which used IRQ, share same API with master.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base,
+                                                        flexio_spi_slave_handle_t *handle,
+                                                        size_t *count)
+{
+    return FLEXIO_SPI_MasterTransferGetCount(base, handle, count);
+}
+
+/*!
+ * @brief FlexIO SPI slave IRQ handler function.
+ *
+ * @param spiType Pointer to the FLEXIO_SPI_Type structure.
+ * @param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ */
+void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+/*@}*/
+
+#endif /*_FSL_FLEXIO_SPI_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi_edma.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi_edma.c
new file mode 100644
index 00000000000..f6f69c9ed88
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi_edma.c
@@ -0,0 +1,418 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_spi_edma.h"
+
+/*******************************************************************************
+ * Definitons
+ ******************************************************************************/
+/*<! Structure definition for spi_edma_private_handle_t. The structure is private. */
+typedef struct _flexio_spi_master_edma_private_handle
+{
+    FLEXIO_SPI_Type *base;
+    flexio_spi_master_edma_handle_t *handle;
+} flexio_spi_master_edma_private_handle_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief EDMA callback function for FLEXIO SPI send transfer.
+ *
+ * @param handle EDMA handle pointer.
+ * @param param Callback function parameter.
+ */
+static void FLEXIO_SPI_TxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
+
+/*!
+ * @brief EDMA callback function for FLEXIO SPI receive transfer.
+ *
+ * @param handle EDMA handle pointer.
+ * @param param Callback function parameter.
+ */
+static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
+
+/*!
+ * @brief EDMA config for FLEXIO SPI transfer.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure.
+ * @param handle pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
+ * @param xfer Pointer to flexio spi transfer structure.
+ */
+static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
+                                  flexio_spi_master_edma_handle_t *handle,
+                                  flexio_spi_transfer_t *xfer);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Dummy data used to send */
+static const uint16_t s_dummyData = FLEXIO_SPI_DUMMYDATA;
+
+/*< @brief user configurable flexio spi handle count. */
+#define FLEXIO_SPI_HANDLE_COUNT 2
+
+/*<! Private handle only used for internally. */
+static flexio_spi_master_edma_private_handle_t s_edmaPrivateHandle[FLEXIO_SPI_HANDLE_COUNT];
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+
+static void FLEXIO_SPI_TxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
+{
+    tcds = tcds;
+    flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param;
+
+    /* Disable Tx DMA */
+    if (transferDone)
+    {
+        FLEXIO_SPI_EnableDMA(spiPrivateHandle->base, kFLEXIO_SPI_TxDmaEnable, false);
+
+        /* change the state */
+        spiPrivateHandle->handle->txInProgress = false;
+
+        /* All finished, call the callback */
+        if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false))
+        {
+            if (spiPrivateHandle->handle->callback)
+            {
+                (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success,
+                                                     spiPrivateHandle->handle->userData);
+            }
+        }
+    }
+}
+
+static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
+{
+    tcds = tcds;
+    flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param;
+
+    if (transferDone)
+    {
+        /* Disable Rx dma */
+        FLEXIO_SPI_EnableDMA(spiPrivateHandle->base, kFLEXIO_SPI_RxDmaEnable, false);
+
+        /* change the state */
+        spiPrivateHandle->handle->rxInProgress = false;
+
+        /* All finished, call the callback */
+        if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false))
+        {
+            if (spiPrivateHandle->handle->callback)
+            {
+                (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success,
+                                                     spiPrivateHandle->handle->userData);
+            }
+        }
+    }
+}
+
+static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
+                                  flexio_spi_master_edma_handle_t *handle,
+                                  flexio_spi_transfer_t *xfer)
+{
+    edma_transfer_config_t xferConfig;
+    flexio_spi_shift_direction_t direction;
+    uint8_t bytesPerFrame;
+
+    /* Configure the values in handle. */
+    switch (xfer->flags)
+    {
+        case kFLEXIO_SPI_8bitMsb:
+            bytesPerFrame = 1;
+            direction = kFLEXIO_SPI_MsbFirst;
+            break;
+        case kFLEXIO_SPI_8bitLsb:
+            bytesPerFrame = 1;
+            direction = kFLEXIO_SPI_LsbFirst;
+            break;
+        case kFLEXIO_SPI_16bitMsb:
+            bytesPerFrame = 2;
+            direction = kFLEXIO_SPI_MsbFirst;
+            break;
+        case kFLEXIO_SPI_16bitLsb:
+            bytesPerFrame = 2;
+            direction = kFLEXIO_SPI_LsbFirst;
+            break;
+        default:
+            bytesPerFrame = 1U;
+            direction = kFLEXIO_SPI_MsbFirst;
+            assert(true);
+            break;
+    }
+
+    /* Save total transfer size. */
+    handle->transferSize = xfer->dataSize;
+
+    /* Configure tx transfer EDMA. */
+    xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction);
+    xferConfig.destOffset = 0;
+    if (bytesPerFrame == 1U)
+    {
+        xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes;
+        xferConfig.destTransferSize = kEDMA_TransferSize1Bytes;
+        xferConfig.minorLoopBytes = 1;
+    }
+    else
+    {
+        if (direction == kFLEXIO_SPI_MsbFirst)
+        {
+            xferConfig.destAddr -= 1U;
+        }
+        xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes;
+        xferConfig.destTransferSize = kEDMA_TransferSize2Bytes;
+        xferConfig.minorLoopBytes = 2;
+    }
+
+    /* Configure DMA channel. */
+    if (xfer->txData)
+    {
+        xferConfig.srcOffset = 1;
+        xferConfig.srcAddr = (uint32_t)(xfer->txData);
+    }
+    else
+    {
+        /* Disable the source increasement and source set to dummyData. */
+        xferConfig.srcOffset = 0;
+        xferConfig.srcAddr = (uint32_t)(&s_dummyData);
+    }
+
+    xferConfig.majorLoopCounts = (xfer->dataSize / xferConfig.minorLoopBytes);
+
+    if (handle->txHandle)
+    {
+        EDMA_SubmitTransfer(handle->txHandle, &xferConfig);
+    }
+
+    /* Configure tx transfer EDMA. */
+    if (xfer->rxData)
+    {
+        xferConfig.srcAddr = FLEXIO_SPI_GetRxDataRegisterAddress(base, direction);
+        xferConfig.srcOffset = 0;
+        xferConfig.destAddr = (uint32_t)(xfer->rxData);
+        xferConfig.destOffset = 1;
+        EDMA_SubmitTransfer(handle->rxHandle, &xferConfig);
+        handle->rxInProgress = true;
+        FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_RxDmaEnable, true);
+        EDMA_StartTransfer(handle->rxHandle);
+    }
+
+    /* Always start Tx transfer. */
+    if (handle->txHandle)
+    {
+        handle->txInProgress = true;
+        FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_TxDmaEnable, true);
+        EDMA_StartTransfer(handle->txHandle);
+    }
+}
+
+status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base,
+                                                   flexio_spi_master_edma_handle_t *handle,
+                                                   flexio_spi_master_edma_transfer_callback_t callback,
+                                                   void *userData,
+                                                   edma_handle_t *txHandle,
+                                                   edma_handle_t *rxHandle)
+{
+    assert(handle);
+
+    uint8_t index = 0;
+
+    /* Find the an empty handle pointer to store the handle. */
+    for (index = 0; index < FLEXIO_SPI_HANDLE_COUNT; index++)
+    {
+        if (s_edmaPrivateHandle[index].base == NULL)
+        {
+            s_edmaPrivateHandle[index].base = base;
+            s_edmaPrivateHandle[index].handle = handle;
+            break;
+        }
+    }
+
+    if (index == FLEXIO_SPI_HANDLE_COUNT)
+    {
+        return kStatus_OutOfRange;
+    }
+
+    /* Set spi base to handle. */
+    handle->txHandle = txHandle;
+    handle->rxHandle = rxHandle;
+
+    /* Register callback and userData. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Set SPI state to idle. */
+    handle->txInProgress = false;
+    handle->rxInProgress = false;
+
+    /* Install callback for Tx/Rx dma channel. */
+    if (handle->txHandle)
+    {
+        EDMA_SetCallback(handle->txHandle, FLEXIO_SPI_TxEDMACallback, &s_edmaPrivateHandle[index]);
+    }
+    if (handle->rxHandle)
+    {
+        EDMA_SetCallback(handle->rxHandle, FLEXIO_SPI_RxEDMACallback, &s_edmaPrivateHandle[index]);
+    }
+
+    return kStatus_Success;
+}
+
+status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base,
+                                       flexio_spi_master_edma_handle_t *handle,
+                                       flexio_spi_transfer_t *xfer)
+{
+    assert(handle);
+    assert(xfer);
+
+    uint32_t dataMode = 0;
+    uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]];
+
+    timerCmp &= 0x00FFU;
+
+    /* Check if the device is busy. */
+    if ((handle->txInProgress) || (handle->rxInProgress))
+    {
+        return kStatus_FLEXIO_SPI_Busy;
+    }
+
+    /* Check if input parameter invalid. */
+    if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* configure data mode. */
+    if ((xfer->flags == kFLEXIO_SPI_8bitMsb) || (xfer->flags == kFLEXIO_SPI_8bitLsb))
+    {
+        dataMode = (8 * 2 - 1U) << 8U;
+    }
+    else if ((xfer->flags == kFLEXIO_SPI_16bitMsb) || (xfer->flags == kFLEXIO_SPI_16bitLsb))
+    {
+        dataMode = (16 * 2 - 1U) << 8U;
+    }
+    else
+    {
+        dataMode = 8 * 2 - 1U;
+    }
+
+    dataMode |= timerCmp;
+
+    base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
+
+    FLEXIO_SPI_EDMAConfig(base, handle, xfer);
+
+    return kStatus_Success;
+}
+
+status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base,
+                                               flexio_spi_master_edma_handle_t *handle,
+                                               size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->rxInProgress)
+    {
+        *count = (handle->transferSize - EDMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel));
+    }
+    else
+    {
+        *count = (handle->transferSize - EDMA_GetRemainingBytes(handle->txHandle->base, handle->txHandle->channel));
+    }
+
+    return kStatus_Success;
+}
+
+void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle)
+{
+    assert(handle);
+
+    /* Disable dma. */
+    EDMA_StopTransfer(handle->txHandle);
+    EDMA_StopTransfer(handle->rxHandle);
+
+    /* Disable DMA enable bit. */
+    FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_DmaAllEnable, false);
+
+    /* Set the handle state. */
+    handle->txInProgress = false;
+    handle->rxInProgress = false;
+}
+
+status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
+                                      flexio_spi_slave_edma_handle_t *handle,
+                                      flexio_spi_transfer_t *xfer)
+{
+    assert(handle);
+    assert(xfer);
+
+    uint32_t dataMode = 0;
+
+    /* Check if the device is busy. */
+    if ((handle->txInProgress) || (handle->rxInProgress))
+    {
+        return kStatus_FLEXIO_SPI_Busy;
+    }
+
+    /* Check if input parameter invalid. */
+    if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* configure data mode. */
+    if ((xfer->flags == kFLEXIO_SPI_8bitMsb) || (xfer->flags == kFLEXIO_SPI_8bitLsb))
+    {
+        dataMode = 8 * 2 - 1U;
+    }
+    else if ((xfer->flags == kFLEXIO_SPI_16bitMsb) || (xfer->flags == kFLEXIO_SPI_16bitLsb))
+    {
+        dataMode = 16 * 2 - 1U;
+    }
+    else
+    {
+        dataMode = 8 * 2 - 1U;
+    }
+
+    base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
+
+    FLEXIO_SPI_EDMAConfig(base, handle, xfer);
+
+    return kStatus_Success;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi_edma.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi_edma.h
new file mode 100644
index 00000000000..4b942e8cc82
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_spi_edma.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_FLEXIO_SPI_EDMA_H_
+#define _FSL_FLEXIO_SPI_EDMA_H_
+
+#include "fsl_flexio_spi.h"
+#include "fsl_edma.h"
+
+/*!
+ * @addtogroup flexio_edma_spi
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief  typedef for flexio_spi_master_edma_handle_t in advance. */
+typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t;
+
+/*! @brief  Slave handle is the same with master handle. */
+typedef flexio_spi_master_edma_handle_t flexio_spi_slave_edma_handle_t;
+
+/*! @brief FlexIO SPI master callback for finished transmit */
+typedef void (*flexio_spi_master_edma_transfer_callback_t)(FLEXIO_SPI_Type *base,
+                                                           flexio_spi_master_edma_handle_t *handle,
+                                                           status_t status,
+                                                           void *userData);
+
+/*! @brief FlexIO SPI slave callback for finished transmit */
+typedef void (*flexio_spi_slave_edma_transfer_callback_t)(FLEXIO_SPI_Type *base,
+                                                          flexio_spi_slave_edma_handle_t *handle,
+                                                          status_t status,
+                                                          void *userData);
+
+/*! @brief FlexIO SPI eDMA transfer handle, users should not touch the content of the handle.*/
+struct _flexio_spi_master_edma_handle
+{
+    size_t transferSize;                                 /*!< Total bytes to be transferred. */
+    bool txInProgress;                                   /*!< Send transfer in progress */
+    bool rxInProgress;                                   /*!< Receive transfer in progress */
+    edma_handle_t *txHandle;                             /*!< DMA handler for SPI send */
+    edma_handle_t *rxHandle;                             /*!< DMA handler for SPI receive */
+    flexio_spi_master_edma_transfer_callback_t callback; /*!< Callback for SPI DMA transfer */
+    void *userData;                                      /*!< User Data for SPI DMA callback */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FLEXO SPI master eDMA handle.
+ *
+ * This function initializes the FLEXO SPI master eDMA handle which can be used for other FLEXO SPI master transactional
+ * APIs.
+ * For a specified FLEXO SPI instance, call this API once to get the initialized handle.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure.
+ * @param handle pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
+ * @param callback SPI callback, NULL means no callback.
+ * @param userData callback function parameter.
+ * @param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer.
+ * @param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range.
+ */
+status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base,
+                                                   flexio_spi_master_edma_handle_t *handle,
+                                                   flexio_spi_master_edma_transfer_callback_t callback,
+                                                   void *userData,
+                                                   edma_handle_t *txHandle,
+                                                   edma_handle_t *rxHandle);
+
+/*!
+ * @brief Performs a non-blocking FlexIO SPI transfer using eDMA.
+ *
+ * @note This interface returns immediately after transfer initiates. Call
+ * FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status to check
+ * whether FlexIO SPI transfer finished.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure.
+ * @param handle pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
+ * @param xfer Pointer to FlexIO SPI transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
+ */
+status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base,
+                                       flexio_spi_master_edma_handle_t *handle,
+                                       flexio_spi_transfer_t *xfer);
+
+/*!
+ * @brief Aborts a FlexIO SPI transfer using eDMA.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure.
+ * @param handle FlexIO SPI eDMA handle pointer.
+ */
+void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle);
+
+/*!
+ * @brief Gets the remaining bytes for FlexIO SPI eDMA transfer.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure.
+ * @param handle FlexIO SPI eDMA handle pointer.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ */
+status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base,
+                                               flexio_spi_master_edma_handle_t *handle,
+                                               size_t *count);
+
+/*!
+ * @brief Initializes the FlexIO SPI slave eDMA handle.
+ *
+ * This function initializes the FlexIO SPI slave eDMA handle.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure.
+ * @param handle pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
+ * @param callback SPI callback, NULL means no callback.
+ * @param userData callback function parameter.
+ * @param txHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer.
+ * @param rxHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer.
+ */
+static inline void FLEXIO_SPI_SlaveTransferCreateHandleEDMA(FLEXIO_SPI_Type *base,
+                                                            flexio_spi_slave_edma_handle_t *handle,
+                                                            flexio_spi_slave_edma_transfer_callback_t callback,
+                                                            void *userData,
+                                                            edma_handle_t *txHandle,
+                                                            edma_handle_t *rxHandle)
+{
+    FLEXIO_SPI_MasterTransferCreateHandleEDMA(base, handle, callback, userData, txHandle, rxHandle);
+}
+
+/*!
+ * @brief Performs a non-blocking FlexIO SPI transfer using eDMA.
+ *
+ * @note This interface returns immediately after transfer initiates. Call
+ * FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status to
+ * check whether FlexIO SPI transfer finished.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure.
+ * @param handle pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
+ * @param xfer Pointer to FlexIO SPI transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
+ */
+status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
+                                      flexio_spi_slave_edma_handle_t *handle,
+                                      flexio_spi_transfer_t *xfer);
+
+/*!
+ * @brief Aborts a FlexIO SPI transfer using eDMA.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure.
+ * @param handle pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
+ */
+static inline void FLEXIO_SPI_SlaveTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle)
+{
+    FLEXIO_SPI_MasterTransferAbortEDMA(base, handle);
+}
+
+/*!
+ * @brief Gets the remaining bytes to be transferred for FlexIO SPI eDMA.
+ *
+ * @param base pointer to FLEXIO_SPI_Type structure.
+ * @param handle FlexIO SPI eDMA handle pointer.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ */
+static inline status_t FLEXIO_SPI_SlaveTransferGetCountEDMA(FLEXIO_SPI_Type *base,
+                                                            flexio_spi_slave_edma_handle_t *handle,
+                                                            size_t *count)
+{
+    return FLEXIO_SPI_MasterTransferGetCountEDMA(base, handle, count);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart.c
new file mode 100644
index 00000000000..92349ea5a5f
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart.c
@@ -0,0 +1,690 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! @brief uart transfer state. */
+enum _flexio_uart_transfer_states
+{
+    kFLEXIO_UART_TxIdle, /* TX idle. */
+    kFLEXIO_UART_TxBusy, /* TX busy. */
+    kFLEXIO_UART_RxIdle, /* RX idle. */
+    kFLEXIO_UART_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @param handle FLEXIO UART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+static size_t FLEXIO_UART_TransferGetRxRingBufferLength(flexio_uart_handle_t *handle);
+
+/*!
+ * @brief Check whether the RX ring buffer is full.
+ *
+ * @param handle FLEXIO UART handle pointer.
+ * @retval true  RX ring buffer is full.
+ * @retval false RX ring buffer is not full.
+ */
+static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle);
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+static size_t FLEXIO_UART_TransferGetRxRingBufferLength(flexio_uart_handle_t *handle)
+{
+    size_t size;
+
+    if (handle->rxRingBufferTail > handle->rxRingBufferHead)
+    {
+        size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
+    }
+    else
+    {
+        size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
+    }
+
+    return size;
+}
+
+static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle)
+{
+    bool full;
+
+    if (FLEXIO_UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
+    {
+        full = true;
+    }
+    else
+    {
+        full = false;
+    }
+
+    return full;
+}
+
+void FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz)
+{
+    assert(base && userConfig);
+
+    flexio_shifter_config_t shifterConfig;
+    flexio_timer_config_t timerConfig;
+    uint32_t ctrlReg = 0;
+    uint16_t timerDiv = 0;
+    uint16_t timerCmp = 0;
+
+    /* Clear the shifterConfig & timerConfig struct. */
+    memset(&shifterConfig, 0, sizeof(shifterConfig));
+    memset(&timerConfig, 0, sizeof(timerConfig));
+
+    /* Ungate flexio clock. */
+    CLOCK_EnableClock(kCLOCK_Flexio0);
+
+    /* Reset FLEXIO before configuration. */
+    FLEXIO_Reset(base->flexioBase);
+
+    /* Configure FLEXIO UART */
+    ctrlReg = base->flexioBase->CTRL;
+    ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
+    ctrlReg |= (FLEXIO_CTRL_DOZEN(userConfig->enableInDoze) | FLEXIO_CTRL_DBGE(userConfig->enableInDebug) |
+                FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | FLEXIO_CTRL_FLEXEN(userConfig->enableUart));
+
+    base->flexioBase->CTRL = ctrlReg;
+
+    /* Do hardware configuration. */
+    /* 1. Configure the shifter 0 for tx. */
+    shifterConfig.timerSelect = base->timerIndex[0];
+    shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+    shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
+    shifterConfig.pinSelect = base->TxPinIndex;
+    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
+    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
+
+    /*2. Configure the timer 0 for tx. */
+    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
+    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect = base->TxPinIndex;
+    timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
+    timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
+    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset = kFLEXIO_TimerResetNever;
+    timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
+    timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
+    timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
+    timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
+
+    timerDiv = srcClock_Hz / userConfig->baudRate_Bps;
+    timerDiv = timerDiv / 2 - 1;
+
+    timerCmp = ((uint32_t)(userConfig->bitCountPerChar * 2 - 1)) << 8U;
+    timerCmp |= timerDiv;
+
+    timerConfig.timerCompare = timerCmp;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
+
+    /* 3. Configure the shifter 1 for rx. */
+    shifterConfig.timerSelect = base->timerIndex[1];
+    shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
+    shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect = base->RxPinIndex;
+    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
+    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
+
+    FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
+
+    /* 4. Configure the timer 1 for rx. */
+    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
+    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal;
+    timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect = base->RxPinIndex;
+    timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
+    timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
+    timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset;
+    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge;
+    timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
+    timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge;
+    timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
+    timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
+
+    timerConfig.timerCompare = timerCmp;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
+}
+
+void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)
+{
+    /* Disable FLEXIO UART module. */
+    FLEXIO_UART_Enable(base, false);
+
+    /* Gate flexio clock. */
+    CLOCK_DisableClock(kCLOCK_Flexio0);
+}
+
+void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)
+{
+    assert(userConfig);
+
+    userConfig->enableUart = true;
+    userConfig->enableInDoze = false;
+    userConfig->enableInDebug = true;
+    userConfig->enableFastAccess = false;
+    /* Default baud rate 115200. */
+    userConfig->baudRate_Bps = 115200U;
+    /* Default bit count at 8. */
+    userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar;
+}
+
+void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
+{
+    if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]);
+    }
+    if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable)
+    {
+        FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]);
+    }
+}
+
+void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
+{
+    if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]);
+    }
+    if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable)
+    {
+        FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]);
+    }
+}
+
+uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)
+{
+    uint32_t status = 0;
+    status =
+        ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]);
+    status |=
+        (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1]))
+         << 1U);
+    status |=
+        (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1]))
+         << 2U);
+    return status;
+}
+
+void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)
+{
+    if (mask & kFLEXIO_UART_TxDataRegEmptyFlag)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]);
+    }
+    if (mask & kFLEXIO_UART_RxDataRegFullFlag)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]);
+    }
+    if (mask & kFLEXIO_UART_RxOverRunFlag)
+    {
+        FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
+    }
+}
+
+void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize)
+{
+    assert(txData);
+    assert(txSize);
+
+    while (txSize--)
+    {
+        /* Wait until data transfer complete. */
+        while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))
+        {
+        }
+
+        base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *txData++;
+    }
+}
+
+void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize)
+{
+    assert(rxData);
+    assert(rxSize);
+
+    while (rxSize--)
+    {
+        /* Wait until data transfer complete. */
+        while (!(FLEXIO_UART_GetStatusFlags(base) & kFLEXIO_UART_RxDataRegFullFlag))
+        {
+        }
+
+        *rxData++ = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]];
+    }
+}
+
+status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base,
+                                          flexio_uart_handle_t *handle,
+                                          flexio_uart_transfer_callback_t callback,
+                                          void *userData)
+{
+    assert(handle);
+
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Set the TX/RX state. */
+    handle->rxState = kFLEXIO_UART_RxIdle;
+    handle->txState = kFLEXIO_UART_TxIdle;
+
+    /* Set the callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Enable interrupt in NVIC. */
+    EnableIRQ(flexio_irqs[0]);
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ);
+}
+
+void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base,
+                                         flexio_uart_handle_t *handle,
+                                         uint8_t *ringBuffer,
+                                         size_t ringBufferSize)
+{
+    assert(handle);
+
+    /* Setup the ringbuffer address */
+    if (ringBuffer)
+    {
+        handle->rxRingBuffer = ringBuffer;
+        handle->rxRingBufferSize = ringBufferSize;
+        handle->rxRingBufferHead = 0U;
+        handle->rxRingBufferTail = 0U;
+
+        /* Enable the interrupt to accept the data when user need the ring buffer. */
+        FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
+    }
+}
+
+void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
+{
+    assert(handle);
+
+    if (handle->rxState == kFLEXIO_UART_RxIdle)
+    {
+        FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
+    }
+
+    handle->rxRingBuffer = NULL;
+    handle->rxRingBufferSize = 0U;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+}
+
+status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base,
+                                             flexio_uart_handle_t *handle,
+                                             flexio_uart_transfer_t *xfer)
+{
+    status_t status;
+
+    /* Return error if xfer invalid. */
+    if ((0U == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Return error if current TX busy. */
+    if (kFLEXIO_UART_TxBusy == handle->txState)
+    {
+        status = kStatus_FLEXIO_UART_TxBusy;
+    }
+    else
+    {
+        handle->txData = xfer->data;
+        handle->txDataSize = xfer->dataSize;
+        handle->txState = kFLEXIO_UART_TxBusy;
+
+        /* Enable transmiter interrupt. */
+        FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
+{
+    /* Disable the transmitter and disable the interrupt. */
+    FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable);
+
+    handle->txDataSize = 0;
+    handle->txState = kFLEXIO_UART_TxIdle;
+}
+
+status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_Success;
+    }
+
+    *count = handle->txSize - handle->txDataSize;
+
+    return kStatus_Success;
+}
+
+status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
+                                                flexio_uart_handle_t *handle,
+                                                flexio_uart_transfer_t *xfer,
+                                                size_t *receivedBytes)
+{
+    uint32_t i;
+    status_t status;
+    /* How many bytes to copy from ring buffer to user memory. */
+    size_t bytesToCopy = 0U;
+    /* How many bytes to receive. */
+    size_t bytesToReceive;
+    /* How many bytes currently have received. */
+    size_t bytesCurrentReceived;
+    uint32_t regPrimask = 0U;
+
+    /* Return error if xfer invalid. */
+    if ((0U == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* How to get data:
+       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+          to uart handle, enable interrupt to store received data to xfer->data. When
+          all data received, trigger callback.
+       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+          If there are enough data in ring buffer, copy them to xfer->data and return.
+          If there are not enough data in ring buffer, copy all of them to xfer->data,
+          save the xfer->data remained empty space to uart handle, receive data
+          to this empty space and trigger callback when finished. */
+
+    if (kFLEXIO_UART_RxBusy == handle->rxState)
+    {
+        status = kStatus_FLEXIO_UART_RxBusy;
+    }
+    else
+    {
+        bytesToReceive = xfer->dataSize;
+        bytesCurrentReceived = 0U;
+
+        /* If RX ring buffer is used. */
+        if (handle->rxRingBuffer)
+        {
+            /* Disable IRQ, protect ring buffer. */
+            regPrimask = __get_PRIMASK();
+            __disable_irq();
+
+            /* How many bytes in RX ring buffer currently. */
+            bytesToCopy = FLEXIO_UART_TransferGetRxRingBufferLength(handle);
+
+            if (bytesToCopy)
+            {
+                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+
+                bytesToReceive -= bytesToCopy;
+
+                /* Copy data from ring buffer to user memory. */
+                for (i = 0U; i < bytesToCopy; i++)
+                {
+                    xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+
+                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+                    if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+            }
+
+            /* If ring buffer does not have enough data, still need to read more data. */
+            if (bytesToReceive)
+            {
+                /* No data in ring buffer, save the request to UART handle. */
+                handle->rxData = xfer->data + bytesCurrentReceived;
+                handle->rxDataSize = bytesToReceive;
+                handle->rxState = kFLEXIO_UART_RxBusy;
+            }
+
+            /* Recover PRIMASK, enable IRQ if previously enabled. */
+            __set_PRIMASK(regPrimask);
+        }
+        /* Ring buffer not used. */
+        else
+        {
+            handle->rxData = xfer->data + bytesCurrentReceived;
+            handle->rxDataSize = bytesToReceive;
+            handle->rxState = kFLEXIO_UART_RxBusy;
+
+            /* Enable RX interrupt. */
+            FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
+        }
+
+        /* Return the how many bytes have read. */
+        if (receivedBytes)
+        {
+            *receivedBytes = bytesCurrentReceived;
+        }
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
+{
+    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+    if (!handle->rxRingBuffer)
+    {
+        /* Disable RX interrupt. */
+        FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
+    }
+
+    handle->rxDataSize = 0U;
+    handle->rxState = kFLEXIO_UART_RxIdle;
+}
+
+status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_Success;
+    }
+
+    *count = handle->rxSize - handle->rxDataSize;
+
+    return kStatus_Success;
+}
+
+void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)
+{
+    uint8_t count = 1;
+    FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType;
+    flexio_uart_handle_t *handle = (flexio_uart_handle_t *)uartHandle;
+
+    /* Read the status back. */
+    uint8_t status = FLEXIO_UART_GetStatusFlags(base);
+
+    /* If RX overrun. */
+    if (kFLEXIO_UART_RxOverRunFlag & status)
+    {
+        /* Clear Overrun flag. */
+        FLEXIO_UART_ClearStatusFlags(base, kFLEXIO_UART_RxOverRunFlag);
+
+        /* Trigger callback. */
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_FLEXIO_UART_RxHardwareOverrun, handle->userData);
+        }
+    }
+
+    /* Receive data register full */
+    if ((kFLEXIO_UART_RxDataRegFullFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[1])))
+    {
+        /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
+        if (handle->rxDataSize)
+        {
+            /* Using non block API to read the data from the registers. */
+            FLEXIO_UART_ReadByte(base, handle->rxData);
+            handle->rxDataSize--;
+            handle->rxData++;
+            count--;
+
+            /* If all the data required for upper layer is ready, trigger callback. */
+            if (!handle->rxDataSize)
+            {
+                handle->rxState = kFLEXIO_UART_RxIdle;
+
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData);
+                }
+            }
+        }
+
+        if (handle->rxRingBuffer)
+        {
+            if (count)
+            {
+                /* If RX ring buffer is full, trigger callback to notify over run. */
+                if (FLEXIO_UART_TransferIsRxRingBufferFull(handle))
+                {
+                    if (handle->callback)
+                    {
+                        handle->callback(base, handle, kStatus_FLEXIO_UART_RxRingBufferOverrun, handle->userData);
+                    }
+                }
+
+                /* If ring buffer is still full after callback function, the oldest data is overrided. */
+                if (FLEXIO_UART_TransferIsRxRingBufferFull(handle))
+                {
+                    /* Increase handle->rxRingBufferTail to make room for new data. */
+                    if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+
+                /* Read data. */
+                handle->rxRingBuffer[handle->rxRingBufferHead] = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]];
+
+                /* Increase handle->rxRingBufferHead. */
+                if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+                {
+                    handle->rxRingBufferHead = 0U;
+                }
+                else
+                {
+                    handle->rxRingBufferHead++;
+                }
+            }
+        }
+        /* If no receive requst pending, stop RX interrupt. */
+        else if (!handle->rxDataSize)
+        {
+            FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
+        }
+        else
+        {
+        }
+    }
+
+    /* Send data register empty and the interrupt is enabled. */
+    if ((kFLEXIO_UART_TxDataRegEmptyFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[0])))
+    {
+        if (handle->txDataSize)
+        {
+            /* Using non block API to write the data to the registers. */
+            FLEXIO_UART_WriteByte(base, handle->txData);
+            handle->txData++;
+            handle->txDataSize--;
+            count--;
+
+            /* If all the data are written to data register, TX finished. */
+            if (!handle->txDataSize)
+            {
+                handle->txState = kFLEXIO_UART_TxIdle;
+
+                /* Disable TX register empty interrupt. */
+                FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable);
+
+                /* Trigger callback. */
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_FLEXIO_UART_TxIdle, handle->userData);
+                }
+            }
+        }
+    }
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart.h
new file mode 100644
index 00000000000..53b35faeab4
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart.h
@@ -0,0 +1,585 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_FLEXIO_UART_H_
+#define _FSL_FLEXIO_UART_H_
+
+#include "fsl_common.h"
+#include "fsl_flexio.h"
+
+/*!
+ * @addtogroup flexio_uart
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexIO UART driver version 2.1.1. */
+#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*@}*/
+
+/*! @brief Error codes for the UART driver. */
+enum _flexio_uart_status
+{
+    kStatus_FLEXIO_UART_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 0), /*!< Transmitter is busy. */
+    kStatus_FLEXIO_UART_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 1), /*!< Receiver is busy. */
+    kStatus_FLEXIO_UART_TxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 2), /*!< UART transmitter is idle. */
+    kStatus_FLEXIO_UART_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 3), /*!< UART receiver is idle. */
+    kStatus_FLEXIO_UART_ERROR = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4),  /*!< ERROR happens on UART. */
+    kStatus_FLEXIO_UART_RxRingBufferOverrun =
+        MAKE_STATUS(kStatusGroup_FLEXIO_UART, 5), /*!< UART RX software ring buffer overrun. */
+    kStatus_FLEXIO_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 6) /*!< UART RX receiver overrun. */
+};
+
+/*! @brief FlexIO UART bit count per char. */
+typedef enum _flexio_uart_bit_count_per_char
+{
+    kFLEXIO_UART_7BitsPerChar = 7U, /*!< 7-bit data characters */
+    kFLEXIO_UART_8BitsPerChar = 8U, /*!< 8-bit data characters */
+    kFLEXIO_UART_9BitsPerChar = 9U, /*!< 9-bit data characters */
+} flexio_uart_bit_count_per_char_t;
+
+/*! @brief Define FlexIO UART interrupt mask. */
+enum _flexio_uart_interrupt_enable
+{
+    kFLEXIO_UART_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
+    kFLEXIO_UART_RxDataRegFullInterruptEnable = 0x2U,  /*!< Receive buffer full interrupt enable. */
+};
+
+/*! @brief Define FlexIO UART status mask. */
+enum _flexio_uart_status_flags
+{
+    kFLEXIO_UART_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
+    kFLEXIO_UART_RxDataRegFullFlag = 0x2U,  /*!< Receive buffer full flag. */
+    kFLEXIO_UART_RxOverRunFlag = 0x4U,      /*!< Receive buffer over run flag. */
+};
+
+/*! @brief Define FlexIO UART access structure typedef. */
+typedef struct _flexio_uart_type
+{
+    FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */
+    uint8_t TxPinIndex;      /*!< Pin select for UART_Tx. */
+    uint8_t RxPinIndex;      /*!< Pin select for UART_Rx. */
+    uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO UART. */
+    uint8_t timerIndex[2];   /*!< Timer index used in FlexIO UART. */
+} FLEXIO_UART_Type;
+
+/*! @brief Define FlexIO UART user configuration structure. */
+typedef struct _flexio_uart_config
+{
+    bool enableUart;                                  /*!< Enable/disable FlexIO UART TX & RX. */
+    bool enableInDoze;                                /*!< Enable/disable FlexIO operation in doze mode*/
+    bool enableInDebug;                               /*!< Enable/disable FlexIO operation in debug mode*/
+    bool enableFastAccess;                            /*!< Enable/disable fast access to FlexIO registers,
+                                                       fast access requires the FlexIO clock to be at least
+                                                       twice the frequency of the bus clock. */
+    uint32_t baudRate_Bps;                            /*!< Baud rate in Bps. */
+    flexio_uart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 7/8/9 -bit */
+} flexio_uart_config_t;
+
+/*! @brief Define FlexIO UART transfer structure. */
+typedef struct _flexio_uart_transfer
+{
+    uint8_t *data;   /*!< Transfer buffer*/
+    size_t dataSize; /*!< Transfer size*/
+} flexio_uart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _flexio_uart_handle flexio_uart_handle_t;
+
+/*! @brief FlexIO UART transfer callback function. */
+typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base,
+                                                flexio_uart_handle_t *handle,
+                                                status_t status,
+                                                void *userData);
+
+/*! @brief Define FLEXIO UART handle structure*/
+struct _flexio_uart_handle
+{
+    uint8_t *volatile txData;   /*!< Address of remaining data to send. */
+    volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+    uint8_t *volatile rxData;   /*!< Address of remaining data to receive. */
+    volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+    size_t txSize;              /*!< Total bytes to be sent. */
+    size_t rxSize;              /*!< Total bytes to be received. */
+
+    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
+    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+    flexio_uart_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                           /*!< UART callback function parameter.*/
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART
+ * hardware, and configures the FlexIO UART with FlexIO UART configuration.
+ * The configuration structure can be filled by the user, or be set with
+ * default values by FLEXIO_UART_GetDefaultConfig().
+ *
+ * Example
+   @code
+   FLEXIO_UART_Type base = {
+   .flexioBase = FLEXIO,
+   .TxPinIndex = 0,
+   .RxPinIndex = 1,
+   .shifterIndex = {0,1},
+   .timerIndex = {0,1}
+   };
+   flexio_uart_config_t config = {
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .baudRate_Bps = 115200U,
+   .bitCountPerChar = 8
+   };
+   FLEXIO_UART_Init(base, &config, srcClock_Hz);
+   @endcode
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param userConfig Pointer to the flexio_uart_config_t structure.
+ * @param srcClock_Hz FlexIO source clock in Hz.
+*/
+void FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Disables the FlexIO UART and gates the FlexIO clock.
+ *
+ * @note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.
+ *
+ * @param base pointer to FLEXIO_UART_Type structure
+*/
+void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base);
+
+/*!
+ * @brief Gets the default configuration to configure the FlexIO UART. The configuration
+ * can be used directly for calling the FLEXIO_UART_Init().
+ * Example:
+   @code
+   flexio_uart_config_t config;
+   FLEXIO_UART_GetDefaultConfig(&userConfig);
+   @endcode
+ * @param userConfig Pointer to the flexio_uart_config_t structure.
+*/
+void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig);
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the FlexIO UART status flags.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @return FlexIO UART status flags.
+*/
+
+uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base);
+
+/*!
+ * @brief Gets the FlexIO UART status flags.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param mask Status flag.
+ *      The parameter can be any combination of the following values:
+ *          @arg kFLEXIO_UART_TxDataRegEmptyFlag
+ *          @arg kFLEXIO_UART_RxEmptyFlag
+ *          @arg kFLEXIO_UART_RxOverRunFlag
+*/
+
+void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the FlexIO UART interrupt.
+ *
+ * This function enables the FlexIO UART interrupt.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param mask Interrupt source.
+ */
+void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the FlexIO UART interrupt.
+ *
+ * This function disables the FlexIO UART interrupt.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param mask Interrupt source.
+ */
+void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Gets the FlexIO UARt transmit data register address.
+ *
+ * This function returns the UART data register address, which is mainly used by DMA/eDMA.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @return FlexIO UART transmit data register address.
+ */
+static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base)
+{
+    return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]);
+}
+
+/*!
+ * @brief Gets the FlexIO UART receive data register address.
+ *
+ * This function returns the UART data register address, which is mainly used by DMA/eDMA.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @return FlexIO UART receive data register address.
+ */
+static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base)
+{
+    return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferByteSwapped, base->shifterIndex[1]);
+}
+
+/*!
+ * @brief Enables/disables the FlexIO UART transmit DMA.
+ * This function enables/disables the FlexIO UART Tx DMA,
+ * which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn't trigger the DMA request.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param enable True to enable, false to disable.
+ */
+static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable)
+{
+    FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterIndex[0], enable);
+}
+
+/*!
+ * @brief Enables/disables the FlexIO UART receive DMA.
+ * This function enables/disables the FlexIO UART Rx DMA,
+ * which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn't trigger the DMA request.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param enable True to enable, false to disable.
+ */
+static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable)
+{
+    FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterIndex[1], enable);
+}
+
+/* @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the FlexIO UART module operation.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type.
+ * @param enable True to enable, false to disable.
+*/
+static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+    else
+    {
+        base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+/*!
+ * @brief Writes one byte of data.
+ *
+ * @note This is a non-blocking API, which returns directly after the data is put into the
+ * data register. Ensure that the TxEmptyFlag is asserted before calling
+ * this API.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param buffer The data bytes to send.
+ */
+static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer)
+{
+    base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *buffer;
+}
+
+/*!
+ * @brief Reads one byte of data.
+ *
+ * @note This is a non-blocking API, which returns directly after the data is read from the
+ * data register. Ensure that the RxFullFlag is asserted before calling this API.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param buffer The buffer to store the received bytes.
+ */
+static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer)
+{
+    *buffer = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]];
+}
+
+/*!
+ * @brief Sends a buffer of data bytes.
+ *
+ * @note This function blocks using the polling method until all bytes have been sent.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param txData The data bytes to send.
+ * @param txSize The number of data bytes to send.
+ */
+void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize);
+
+/*!
+ * @brief Receives a buffer of bytes.
+ *
+ * @note This function blocks using the polling method until all bytes have been received.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param rxData The buffer to store the received bytes.
+ * @param rxSize The number of data bytes to be received.
+ */
+void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the UART handle.
+ *
+ * This function initializes the FlexIO UART handle, which can be used for other FlexIO
+ * UART transactional APIs. Call this API once to get the
+ * initialized handle.
+ *
+ * The UART driver supports the "background" receiving, which means that user can set up
+ * a RX ring buffer optionally. Data received is stored into the ring buffer even when
+ * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data
+ * received in the ring buffer, user can get the received data from the ring buffer
+ * directly. The ring buffer is disabled if passing NULL as @p ringBuffer.
+ *
+ * @param base to FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base,
+                                          flexio_uart_handle_t *handle,
+                                          flexio_uart_transfer_callback_t callback,
+                                          void *userData);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received is stored into the ring buffer even when
+ * the user doesn't call the UART_ReceiveNonBlocking() API. If there are already data received
+ * in the ring buffer, user can get the received data from the ring buffer directly.
+ *
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize Size of the ring buffer.
+ */
+void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base,
+                                         flexio_uart_handle_t *handle,
+                                         uint8_t *ringBuffer,
+                                         size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
+void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function,
+ * which returns directly without waiting for all data to be written to the TX register. When
+ * all data are written to TX register in ISR, the FlexIO UART driver calls the callback
+ * function and passes the @ref kStatus_FLEXIO_UART_TxIdle as status parameter.
+ *
+ * @note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However, it does not ensure that all data is sent out.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * @param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t.
+ * @retval kStatus_Success Successfully starts the data transmission.
+ * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register.
+ */
+status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base,
+                                             flexio_uart_handle_t *handle,
+                                             flexio_uart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt-driven data sending. Get the remainBytes to know
+ * how many bytes are still not sent out.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
+void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of remaining bytes not sent.
+ *
+ * This function gets the number of remaining bytes not sent driven by interrupt.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * @param count Number of bytes sent so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Receives a buffer of data using the interrupt method.
+ *
+ * This function receives data using the interrupt method. This is a non-blocking function,
+ * which returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in ring buffer is not enough to read, the receive
+ * request is saved by the UART driver. When new data arrives, the receive request
+ * is serviced first. When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer,
+ * the 5 bytes are copied to xfer->data. This function returns with the
+ * parameter @p receivedBytes set to 5. For the last 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * @param xfer UART transfer structure. See #flexio_uart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into the transmit queue.
+ * @retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished.
+ */
+status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
+                                                flexio_uart_handle_t *handle,
+                                                flexio_uart_transfer_t *xfer,
+                                                size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the receive data which was using IRQ.
+ *
+ * This function aborts the receive data which was using IRQ.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
+void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of remaining bytes not received.
+ *
+ * This function gets the number of remaining bytes not received driven by interrupt.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * @param count Number of bytes received so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count);
+
+/*!
+ * @brief FlexIO UART IRQ handler function.
+ *
+ * This function processes the FlexIO UART transmit and receives the IRQ request.
+ *
+ * @param uartType Pointer to the FLEXIO_UART_Type structure.
+ * @param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
+void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+/*@}*/
+
+#endif /*_FSL_FLEXIO_UART_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart_edma.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart_edma.c
new file mode 100644
index 00000000000..0c3655419c5
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart_edma.c
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flexio_uart_edma.h"
+#include "fsl_dmamux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! Structure definition for uart_edma_private_handle_t. The structure is private. */
+typedef struct _flexio_uart_edma_private_handle
+{
+    FLEXIO_UART_Type *base;
+    flexio_uart_edma_handle_t *handle;
+} flexio_uart_edma_private_handle_t;
+
+/* UART EDMA transfer handle. */
+enum _flexio_uart_edma_tansfer_states
+{
+    kFLEXIO_UART_TxIdle, /* TX idle. */
+    kFLEXIO_UART_TxBusy, /* TX busy. */
+    kFLEXIO_UART_RxIdle, /* RX idle. */
+    kFLEXIO_UART_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*< @brief user configurable flexio uart handle count. */
+#define FLEXIO_UART_HANDLE_COUNT 2
+
+/*<! Private handle only used for internally. */
+static flexio_uart_edma_private_handle_t s_edmaPrivateHandle[FLEXIO_UART_HANDLE_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO UART EDMA send finished callback function.
+ *
+ * This function is called when FLEXIO UART EDMA send finished. It disables the UART
+ * TX EDMA request and sends @ref kStatus_FLEXIO_UART_TxIdle to FLEXIO UART callback.
+ *
+ * @param handle The EDMA handle.
+ * @param param Callback function parameter.
+ */
+static void FLEXIO_UART_TransferSendEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
+
+/*!
+ * @brief FLEXIO UART EDMA receive finished callback function.
+ *
+ * This function is called when FLEXIO UART EDMA receive finished. It disables the UART
+ * RX EDMA request and sends @ref kStatus_FLEXIO_UART_RxIdle to UART callback.
+ *
+ * @param handle The EDMA handle.
+ * @param param Callback function parameter.
+ */
+static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle,
+                                                    void *param,
+                                                    bool transferDone,
+                                                    uint32_t tcds);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void FLEXIO_UART_TransferSendEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
+{
+    flexio_uart_edma_private_handle_t *uartPrivateHandle = (flexio_uart_edma_private_handle_t *)param;
+
+    assert(uartPrivateHandle->handle);
+
+    /* Avoid the warning for unused variables. */
+    handle = handle;
+    tcds = tcds;
+
+    if (transferDone)
+    {
+        FLEXIO_UART_TransferAbortSendEDMA(uartPrivateHandle->base, uartPrivateHandle->handle);
+
+        if (uartPrivateHandle->handle->callback)
+        {
+            uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle,
+                                                kStatus_FLEXIO_UART_TxIdle, uartPrivateHandle->handle->userData);
+        }
+    }
+}
+
+static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle,
+                                                    void *param,
+                                                    bool transferDone,
+                                                    uint32_t tcds)
+{
+    flexio_uart_edma_private_handle_t *uartPrivateHandle = (flexio_uart_edma_private_handle_t *)param;
+
+    assert(uartPrivateHandle->handle);
+
+    /* Avoid the warning for unused variables. */
+    handle = handle;
+    tcds = tcds;
+
+    if (transferDone)
+    {
+        /* Disable transfer. */
+        FLEXIO_UART_TransferAbortReceiveEDMA(uartPrivateHandle->base, uartPrivateHandle->handle);
+
+        if (uartPrivateHandle->handle->callback)
+        {
+            uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle,
+                                                kStatus_FLEXIO_UART_RxIdle, uartPrivateHandle->handle->userData);
+        }
+    }
+}
+
+status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base,
+                                              flexio_uart_edma_handle_t *handle,
+                                              flexio_uart_edma_transfer_callback_t callback,
+                                              void *userData,
+                                              edma_handle_t *txEdmaHandle,
+                                              edma_handle_t *rxEdmaHandle)
+{
+    assert(handle);
+
+    uint8_t index = 0;
+
+    /* Find the an empty handle pointer to store the handle. */
+    for (index = 0; index < FLEXIO_UART_HANDLE_COUNT; index++)
+    {
+        if (s_edmaPrivateHandle[index].base == NULL)
+        {
+            s_edmaPrivateHandle[index].base = base;
+            s_edmaPrivateHandle[index].handle = handle;
+            break;
+        }
+    }
+
+    if (index == FLEXIO_UART_HANDLE_COUNT)
+    {
+        return kStatus_OutOfRange;
+    }
+
+    memset(handle, 0, sizeof(*handle));
+
+    handle->rxState = kFLEXIO_UART_RxIdle;
+    handle->txState = kFLEXIO_UART_TxIdle;
+
+    handle->rxEdmaHandle = rxEdmaHandle;
+    handle->txEdmaHandle = txEdmaHandle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Configure TX. */
+    if (txEdmaHandle)
+    {
+        EDMA_SetCallback(handle->txEdmaHandle, FLEXIO_UART_TransferSendEDMACallback, &s_edmaPrivateHandle);
+    }
+
+    /* Configure RX. */
+    if (rxEdmaHandle)
+    {
+        EDMA_SetCallback(handle->rxEdmaHandle, FLEXIO_UART_TransferReceiveEDMACallback, &s_edmaPrivateHandle);
+    }
+
+    return kStatus_Success;
+}
+
+status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base,
+                                      flexio_uart_edma_handle_t *handle,
+                                      flexio_uart_transfer_t *xfer)
+{
+    assert(handle->txEdmaHandle);
+
+    edma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* Return error if xfer invalid. */
+    if ((0U == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If previous TX not finished. */
+    if (kFLEXIO_UART_TxBusy == handle->txState)
+    {
+        status = kStatus_FLEXIO_UART_TxBusy;
+    }
+    else
+    {
+        handle->txState = kFLEXIO_UART_TxBusy;
+
+        /* Prepare transfer. */
+        EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t),
+                             (void *)FLEXIO_UART_GetTxDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t),
+                             xfer->dataSize, kEDMA_MemoryToPeripheral);
+
+        /* Submit transfer. */
+        EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig);
+        EDMA_StartTransfer(handle->txEdmaHandle);
+
+        /* Enable UART TX EDMA. */
+        FLEXIO_UART_EnableTxDMA(base, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base,
+                                         flexio_uart_edma_handle_t *handle,
+                                         flexio_uart_transfer_t *xfer)
+{
+    assert(handle->rxEdmaHandle);
+
+    edma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* Return error if xfer invalid. */
+    if ((0U == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If previous RX not finished. */
+    if (kFLEXIO_UART_RxBusy == handle->rxState)
+    {
+        status = kStatus_FLEXIO_UART_RxBusy;
+    }
+    else
+    {
+        handle->rxState = kFLEXIO_UART_RxBusy;
+
+        /* Prepare transfer. */
+        EDMA_PrepareTransfer(&xferConfig, (void *)FLEXIO_UART_GetRxDataRegisterAddress(base), sizeof(uint8_t),
+                             xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory);
+
+        /* Submit transfer. */
+        EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig);
+        EDMA_StartTransfer(handle->rxEdmaHandle);
+
+        /* Enable UART RX EDMA. */
+        FLEXIO_UART_EnableRxDMA(base, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)
+{
+    assert(handle->txEdmaHandle);
+
+    /* Disable UART TX EDMA. */
+    FLEXIO_UART_EnableTxDMA(base, false);
+
+    /* Stop transfer. */
+    EDMA_StopTransfer(handle->txEdmaHandle);
+
+    handle->txState = kFLEXIO_UART_TxIdle;
+}
+
+void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)
+{
+    assert(handle->rxEdmaHandle);
+
+    /* Disable UART RX EDMA. */
+    FLEXIO_UART_EnableRxDMA(base, false);
+
+    /* Stop transfer. */
+    EDMA_StopTransfer(handle->rxEdmaHandle);
+
+    handle->rxState = kFLEXIO_UART_RxIdle;
+}
+
+status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
+                                                 flexio_uart_edma_handle_t *handle,
+                                                 size_t *count)
+{
+    assert(handle->rxEdmaHandle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (kFLEXIO_UART_RxBusy == handle->rxState)
+    {
+        *count = (handle->rxSize - EDMA_GetRemainingBytes(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel));
+    }
+    else
+    {
+        *count = handle->rxSize;
+    }
+
+    return kStatus_Success;
+}
+
+status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)
+{
+    assert(handle->txEdmaHandle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (kFLEXIO_UART_TxBusy == handle->txState)
+    {
+        *count = (handle->txSize - EDMA_GetRemainingBytes(handle->txEdmaHandle->base, handle->txEdmaHandle->channel));
+    }
+    else
+    {
+        *count = handle->txSize;
+    }
+
+    return kStatus_Success;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart_edma.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart_edma.h
new file mode 100644
index 00000000000..bcd5945c676
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_flexio_uart_edma.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_FLEXIO_UART_EDMA_H_
+#define _FSL_FLEXIO_UART_EDMA_H_
+
+#include "fsl_flexio_uart.h"
+#include "fsl_dmamux.h"
+#include "fsl_edma.h"
+
+/*!
+ * @addtogroup flexio_edma_uart
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Forward declaration of the handle typedef. */
+typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base,
+                                                     flexio_uart_edma_handle_t *handle,
+                                                     status_t status,
+                                                     void *userData);
+
+/*!
+* @brief UART eDMA handle
+*/
+struct _flexio_uart_edma_handle
+{
+    flexio_uart_edma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                                /*!< UART callback function parameter.*/
+
+    size_t txSize; /*!< Total bytes to be sent. */
+    size_t rxSize; /*!< Total bytes to be received. */
+
+    edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */
+    edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the UART handle which is used in transactional functions.
+ *
+ * @param base pointer to FLEXIO_UART_Type.
+ * @param handle Pointer to flexio_uart_edma_handle_t structure.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ * @param rxEdmaHandle User requested DMA handle for RX DMA transfer.
+ * @param txEdmaHandle User requested DMA handle for TX DMA transfer.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range.
+ */
+status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base,
+                                              flexio_uart_edma_handle_t *handle,
+                                              flexio_uart_edma_transfer_callback_t callback,
+                                              void *userData,
+                                              edma_handle_t *txEdmaHandle,
+                                              edma_handle_t *rxEdmaHandle);
+
+/*!
+ * @brief Sends data using eDMA.
+ *
+ * This function sends data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data have been sent out, the send callback function is called.
+ *
+ * @param base pointer to FLEXIO_UART_Type
+ * @param handle UART handle pointer.
+ * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going.
+ */
+status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base,
+                                      flexio_uart_edma_handle_t *handle,
+                                      flexio_uart_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using eDMA.
+ *
+ * This function receives data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data have been received, the receive callback function is called.
+ *
+ * @param base pointer to FLEXIO_UART_Type
+ * @param handle Pointer to flexio_uart_edma_handle_t structure
+ * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_UART_RxBusy Previous transfer on going.
+ */
+status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base,
+                                         flexio_uart_edma_handle_t *handle,
+                                         flexio_uart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the sent data which using eDMA.
+ *
+ * This function aborts sent data which using eDMA.
+ *
+ * @param base pointer to FLEXIO_UART_Type
+ * @param handle Pointer to flexio_uart_edma_handle_t structure
+ */
+void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle);
+
+/*!
+ * @brief Aborts the receive data which using eDMA.
+ *
+ * This function aborts the receive data which using eDMA.
+ *
+ * @param base pointer to FLEXIO_UART_Type
+ * @param handle Pointer to flexio_uart_edma_handle_t structure
+ */
+void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes still not sent out.
+ *
+ * This function gets the number of bytes still not sent out.
+ *
+ * @param base pointer to FLEXIO_UART_Type
+ * @param handle Pointer to flexio_uart_edma_handle_t structure
+ * @param count Number of bytes sent so far by the non-blocking transaction.
+ */
+status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Gets the number of bytes still not received.
+ *
+ * This function gets the number of bytes still not received.
+ *
+ * @param base pointer to FLEXIO_UART_Type
+ * @param handle Pointer to flexio_uart_edma_handle_t structure
+ * @param count Number of bytes sent so far by the non-blocking transaction.
+ */
+status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
+                                                 flexio_uart_edma_handle_t *handle,
+                                                 size_t *count);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_UART_EDMA_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_gpio.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_gpio.c
new file mode 100644
index 00000000000..8fc068f2d6a
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_gpio.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
+static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+
+/*!
+* @brief Gets the GPIO instance according to the GPIO base
+*
+* @param base    GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+* @retval GPIO instance
+*/
+static uint32_t GPIO_GetInstance(GPIO_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t GPIO_GetInstance(GPIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_GPIO_COUNT; instance++)
+    {
+        if (s_gpioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_GPIO_COUNT);
+
+    return instance;
+}
+
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
+{
+    assert(config);
+
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->PDDR &= ~(1U << pin);
+    }
+    else
+    {
+        GPIO_WritePinOutput(base, pin, config->outputLogic);
+        base->PDDR |= (1U << pin);
+    }
+}
+
+uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)
+{
+    uint8_t instance;
+    PORT_Type *portBase;
+    instance = GPIO_GetInstance(base);
+    portBase = s_portBases[instance];
+    return portBase->ISFR;
+}
+
+void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)
+{
+    uint8_t instance;
+    PORT_Type *portBase;
+    instance = GPIO_GetInstance(base);
+    portBase = s_portBases[instance];
+    portBase->ISFR = mask;
+}
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+/*!
+* @brief Gets the FGPIO instance according to the GPIO base
+*
+* @param base    FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+* @retval FGPIO instance
+*/
+static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_FGPIO_COUNT; instance++)
+    {
+        if (s_fgpioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_FGPIO_COUNT);
+
+    return instance;
+}
+
+void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
+{
+    assert(config);
+
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->PDDR &= ~(1U << pin);
+    }
+    else
+    {
+        FGPIO_WritePinOutput(base, pin, config->outputLogic);
+        base->PDDR |= (1U << pin);
+    }
+}
+
+uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base)
+{
+    uint8_t instance;
+    instance = FGPIO_GetInstance(base);
+    PORT_Type *portBase;
+    portBase = s_portBases[instance];
+    return portBase->ISFR;
+}
+
+void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask)
+{
+    uint8_t instance;
+    instance = FGPIO_GetInstance(base);
+    PORT_Type *portBase;
+    portBase = s_portBases[instance];
+    portBase->ISFR = mask;
+}
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_gpio.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_gpio.h
new file mode 100644
index 00000000000..d62545fea1e
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_gpio.h
@@ -0,0 +1,389 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_GPIO_H_
+#define _FSL_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup gpio
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief GPIO driver version 2.1.0. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*@}*/
+
+/*! @brief GPIO direction definition*/
+typedef enum _gpio_pin_direction
+{
+    kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input*/
+    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Every pin can only be configured as either output pin or input pin at a time.
+ * If configured as a input pin, then leave the outputConfig unused
+ * Note : In some use cases, the corresponding port property should be configured in advance
+ *        with the PORT_SetPinConfig()
+ */
+typedef struct _gpio_pin_config
+{
+    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+    /* Output configurations, please ignore if configured as a input one */
+    uint8_t outputLogic; /*!< Set default output logic, no use in input */
+} gpio_pin_config_t;
+
+/*! @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup gpio_driver
+ * @{
+ */
+
+/*! @name GPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * @code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin    GPIO port pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name GPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
+ *
+ * @param base    GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin     GPIO pin number
+ * @param output  GPIO pin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
+{
+    if (output == 0U)
+    {
+        base->PCOR = 1 << pin;
+    }
+    else
+    {
+        base->PSOR = 1 << pin;
+    }
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
+{
+    base->PSOR = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
+{
+    base->PCOR = mask;
+}
+
+/*!
+ * @brief Reverses current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask)
+{
+    base->PTOR = mask;
+}
+/*@}*/
+
+/*! @name GPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the whole GPIO port.
+ *
+ * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin     GPIO pin number
+ * @retval GPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
+{
+    return (((base->PDIR) >> pin) & 0x01U);
+}
+/*@}*/
+
+/*! @name GPIO Interrupt */
+/*@{*/
+
+/*!
+ * @brief Reads whole GPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @retval Current GPIO port interrupt status flag, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base);
+
+/*!
+ * @brief Clears multiple GPIO pin interrupt status flag.
+ *
+ * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
+
+/*@}*/
+/*! @} */
+
+/*!
+ * @addtogroup fgpio_driver
+ * @{
+ */
+
+/*
+ * Introduce the FGPIO feature.
+ *
+ * The FGPIO features are only support on some of Kinetis chips. The FGPIO registers are aliased to the IOPORT
+ * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore
+ * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
+ */
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+/*! @name FGPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes a FGPIO pin used by the board.
+ *
+ * To initialize the FGPIO driver, define a pin configuration, either input or output, in the user file.
+ * Then, call the FGPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * @code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin    FGPIO port pin number
+ * @param config FGPIO pin configuration pointer
+ */
+void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name FGPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
+ *
+ * @param base    FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin     FGPIO pin number
+ * @param output  FGPIOpin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output)
+{
+    if (output == 0U)
+    {
+        base->PCOR = 1 << pin;
+    }
+    else
+    {
+        base->PSOR = 1 << pin;
+    }
+}
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 1.
+ *
+ * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask)
+{
+    base->PSOR = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 0.
+ *
+ * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask)
+{
+    base->PCOR = mask;
+}
+
+/*!
+ * @brief Reverses current output logic of the multiple FGPIO pins.
+ *
+ * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask)
+{
+    base->PTOR = mask;
+}
+/*@}*/
+
+/*! @name FGPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the whole FGPIO port.
+ *
+ * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin  FGPIO pin number
+ * @retval FGPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin)
+{
+    return (((base->PDIR) >> pin) & 0x01U);
+}
+/*@}*/
+
+/*! @name FGPIO Interrupt */
+/*@{*/
+
+/*!
+ * @brief Reads the whole FGPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request,  the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @retval Current FGPIO port interrupt status flags, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base);
+
+/*!
+ * @brief Clears the multiple FGPIO pin interrupt status flag.
+ *
+ * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask);
+
+/*@}*/
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _FSL_GPIO_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c.c
new file mode 100644
index 00000000000..b51fc07a151
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c.c
@@ -0,0 +1,1633 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_i2c.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief i2c transfer state. */
+enum _i2c_transfer_states
+{
+    kIdleState = 0x0U,             /*!< I2C bus idle. */
+    kCheckAddressState = 0x1U,     /*!< 7-bit address check state. */
+    kSendCommandState = 0x2U,      /*!< Send command byte phase. */
+    kSendDataState = 0x3U,         /*!< Send data transfer phase. */
+    kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */
+    kReceiveDataState = 0x5U,      /*!< Receive data transfer phase. */
+};
+
+/*! @brief Common sets of flags used by the driver. */
+enum _i2c_flag_constants
+{
+/*! All flags which are cleared by the driver upon starting a transfer. */
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StartDetectFlag | kI2C_StopDetectFlag,
+    kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StartStopDetectInterruptEnable,
+#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StopDetectFlag,
+    kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StopDetectInterruptEnable,
+#else
+    kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag,
+    kIrqFlags = kI2C_GlobalInterruptEnable,
+#endif
+
+};
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get instance number for I2C module.
+ *
+ * @param base I2C peripheral base address.
+ */
+uint32_t I2C_GetInstance(I2C_Type *base);
+
+/*!
+ * @brief Set up master transfer, send slave address and decide the initial
+ * transfer state.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_handle_t structure which stores the transfer state.
+ * @param xfer pointer to i2c_master_transfer_t structure.
+ */
+static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Check and clear status operation.
+ *
+ * @param base I2C peripheral base address.
+ * @param status current i2c hardware status.
+ * @retval kStatus_Success No error found.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStatus_I2C_Nak Received Nak error.
+ */
+static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status);
+
+/*!
+ * @brief Master run transfer state machine to perform a byte of transfer.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_handle_t structure which stores the transfer state
+ * @param isDone input param to get whether the thing is done, true is done
+ * @retval kStatus_Success No error found.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStatus_I2C_Nak Received Nak error.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ */
+static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone);
+
+/*!
+ * @brief I2C common interrupt handler.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_handle_t structure which stores the transfer state
+ */
+static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to i2c handles for each instance. */
+static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT] = {NULL};
+
+/*! @brief SCL clock divider used to calculate baudrate. */
+static const uint16_t s_i2cDividerTable[] = {
+    20,  22,  24,  26,   28,   30,   34,   40,   28,   32,   36,   40,   44,   48,   56,   68,
+    48,  56,  64,  72,   80,   88,   104,  128,  80,   96,   112,  128,  144,  160,  192,  240,
+    160, 192, 224, 256,  288,  320,  384,  480,  320,  384,  448,  512,  576,  640,  768,  960,
+    640, 768, 896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840};
+
+/*! @brief Pointers to i2c bases for each instance. */
+static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS;
+
+/*! @brief Pointers to i2c IRQ number for each instance. */
+static const IRQn_Type s_i2cIrqs[] = I2C_IRQS;
+
+/*! @brief Pointers to i2c clocks for each instance. */
+static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS;
+
+/*! @brief Pointer to master IRQ handler for each instance. */
+static i2c_isr_t s_i2cMasterIsr;
+
+/*! @brief Pointer to slave IRQ handler for each instance. */
+static i2c_isr_t s_i2cSlaveIsr;
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+uint32_t I2C_GetInstance(I2C_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_I2C_COUNT; instance++)
+    {
+        if (s_i2cBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_I2C_COUNT);
+
+    return instance;
+}
+
+static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    status_t result = kStatus_Success;
+    i2c_direction_t direction = xfer->direction;
+    uint16_t timeout = UINT16_MAX;
+
+    /* Initialize the handle transfer information. */
+    handle->transfer = *xfer;
+
+    /* Save total transfer size. */
+    handle->transferSize = xfer->dataSize;
+
+    /* Initial transfer state. */
+    if (handle->transfer.subaddressSize > 0)
+    {
+        handle->state = kSendCommandState;
+        if (xfer->direction == kI2C_Read)
+        {
+            direction = kI2C_Write;
+        }
+    }
+    else
+    {
+        handle->state = kCheckAddressState;
+    }
+
+    /* Wait until the data register is ready for transmit. */
+    while ((!(base->S & kI2C_TransferCompleteFlag)) && (--timeout))
+    {
+    }
+
+    /* Failed to start the transfer. */
+    if (timeout == 0)
+    {
+        return kStatus_I2C_Timeout;
+    }
+
+    /* Clear all status before transfer. */
+    I2C_MasterClearStatusFlags(base, kClearFlags);
+
+    /* If repeated start is requested, send repeated start. */
+    if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag)
+    {
+        result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction);
+    }
+    else /* For normal transfer, send start. */
+    {
+        result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction);
+    }
+
+    return result;
+}
+
+static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status)
+{
+    status_t result = kStatus_Success;
+
+    /* Check arbitration lost. */
+    if (status & kI2C_ArbitrationLostFlag)
+    {
+        /* Clear arbitration lost flag. */
+        base->S = kI2C_ArbitrationLostFlag;
+        result = kStatus_I2C_ArbitrationLost;
+    }
+    /* Check NAK */
+    else if (status & kI2C_ReceiveNakFlag)
+    {
+        result = kStatus_I2C_Nak;
+    }
+    else
+    {
+    }
+
+    return result;
+}
+
+static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone)
+{
+    status_t result = kStatus_Success;
+    uint32_t statusFlags = base->S;
+    *isDone = false;
+    volatile uint8_t dummy = 0;
+    bool ignoreNak = ((handle->state == kSendDataState) && (handle->transfer.dataSize == 0U)) ||
+                     ((handle->state == kReceiveDataState) && (handle->transfer.dataSize == 1U));
+
+    /* Add this to avoid build warning. */
+    dummy++;
+
+    /* Check & clear error flags. */
+    result = I2C_CheckAndClearError(base, statusFlags);
+
+    /* Ignore Nak when it's appeared for last byte. */
+    if ((result == kStatus_I2C_Nak) && ignoreNak)
+    {
+        result = kStatus_Success;
+    }
+
+    if (result)
+    {
+        return result;
+    }
+
+    /* Handle Check address state to check the slave address is Acked in slave
+       probe application. */
+    if (handle->state == kCheckAddressState)
+    {
+        if (statusFlags & kI2C_ReceiveNakFlag)
+        {
+            return kStatus_I2C_Nak;
+        }
+        else
+        {
+            if (handle->transfer.direction == kI2C_Write)
+            {
+                /* Next state, send data. */
+                handle->state = kSendDataState;
+            }
+            else
+            {
+                /* Next state, receive data begin. */
+                handle->state = kReceiveDataBeginState;
+            }
+        }
+    }
+
+    /* Run state machine. */
+    switch (handle->state)
+    {
+        /* Send I2C command. */
+        case kSendCommandState:
+            if (handle->transfer.subaddressSize)
+            {
+                handle->transfer.subaddressSize--;
+                base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize));
+            }
+            else
+            {
+                if (handle->transfer.direction == kI2C_Write)
+                {
+                    /* Next state, send data. */
+                    handle->state = kSendDataState;
+
+                    /* Send first byte of data. */
+                    if (handle->transfer.dataSize > 0)
+                    {
+                        base->D = *handle->transfer.data;
+                        handle->transfer.data++;
+                        handle->transfer.dataSize--;
+                    }
+                }
+                else
+                {
+                    /* Send repeated start and slave address. */
+                    result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read);
+
+                    /* Next state, receive data begin. */
+                    handle->state = kReceiveDataBeginState;
+                }
+            }
+            break;
+
+        /* Send I2C data. */
+        case kSendDataState:
+            /* Send one byte of data. */
+            if (handle->transfer.dataSize > 0)
+            {
+                base->D = *handle->transfer.data;
+                handle->transfer.data++;
+                handle->transfer.dataSize--;
+            }
+            else
+            {
+                *isDone = true;
+            }
+            break;
+
+        /* Start I2C data receive. */
+        case kReceiveDataBeginState:
+            base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+            /* Send nak at the last receive byte. */
+            if (handle->transfer.dataSize == 1)
+            {
+                base->C1 |= I2C_C1_TXAK_MASK;
+            }
+
+            /* Read dummy to release the bus. */
+            dummy = base->D;
+
+            /* Next state, receive data. */
+            handle->state = kReceiveDataState;
+            break;
+
+        /* Receive I2C data. */
+        case kReceiveDataState:
+            /* Receive one byte of data. */
+            if (handle->transfer.dataSize--)
+            {
+                if (handle->transfer.dataSize == 0)
+                {
+                    *isDone = true;
+
+                    /* Send stop if kI2C_TransferNoStop is not asserted. */
+                    if (!(handle->transfer.flags & kI2C_TransferNoStopFlag))
+                    {
+                        result = I2C_MasterStop(base);
+                    }
+                }
+
+                /* Send NAK at the last receive byte. */
+                if (handle->transfer.dataSize == 1)
+                {
+                    base->C1 |= I2C_C1_TXAK_MASK;
+                }
+
+                /* Read the data byte into the transfer buffer. */
+                *handle->transfer.data = base->D;
+                handle->transfer.data++;
+            }
+            break;
+
+        default:
+            break;
+    }
+
+    return result;
+}
+
+static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle)
+{
+    /* Check if master interrupt. */
+    if ((base->S & kI2C_ArbitrationLostFlag) || (base->C1 & I2C_C1_MST_MASK))
+    {
+        s_i2cMasterIsr(base, handle);
+    }
+    else
+    {
+        s_i2cSlaveIsr(base, handle);
+    }
+}
+
+void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
+{
+    assert(masterConfig && srcClock_Hz);
+
+    /* Temporary register for filter read. */
+    uint8_t fltReg;
+#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
+    uint8_t c2Reg;
+#endif
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    uint8_t s2Reg;
+#endif
+    /* Enable I2C clock. */
+    CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]);
+
+    /* Disable I2C prior to configuring it. */
+    base->C1 &= ~(I2C_C1_IICEN_MASK);
+
+    /* Clear all flags. */
+    I2C_MasterClearStatusFlags(base, kClearFlags);
+
+    /* Configure baud rate. */
+    I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz);
+
+#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
+    /* Configure high drive feature. */
+    c2Reg = base->C2;
+    c2Reg &= ~(I2C_C2_HDRS_MASK);
+    c2Reg |= I2C_C2_HDRS(masterConfig->enableHighDrive);
+    base->C2 = c2Reg;
+#endif
+
+    /* Read out the FLT register. */
+    fltReg = base->FLT;
+
+#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
+    /* Configure the stop / hold enable. */
+    fltReg &= ~(I2C_FLT_SHEN_MASK);
+    fltReg |= I2C_FLT_SHEN(masterConfig->enableStopHold);
+#endif
+
+    /* Configure the glitch filter value. */
+    fltReg &= ~(I2C_FLT_FLT_MASK);
+    fltReg |= I2C_FLT_FLT(masterConfig->glitchFilterWidth);
+
+    /* Write the register value back to the filter register. */
+    base->FLT = fltReg;
+
+/* Enable/Disable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    s2Reg = base->S2 & (~I2C_S2_DFEN_MASK);
+    base->S2 = s2Reg | I2C_S2_DFEN(masterConfig->enableDoubleBuffering);
+#endif
+
+    /* Enable the I2C peripheral based on the configuration. */
+    base->C1 = I2C_C1_IICEN(masterConfig->enableMaster);
+}
+
+void I2C_MasterDeinit(I2C_Type *base)
+{
+    /* Disable I2C module. */
+    I2C_Enable(base, false);
+
+    /* Disable I2C clock. */
+    CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]);
+}
+
+void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)
+{
+    assert(masterConfig);
+
+    /* Default baud rate at 100kbps. */
+    masterConfig->baudRate_Bps = 100000U;
+
+/* Default pin high drive is disabled. */
+#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
+    masterConfig->enableHighDrive = false;
+#endif
+
+/* Default stop hold enable is disabled. */
+#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
+    masterConfig->enableStopHold = false;
+#endif
+
+    /* Default glitch filter value is no filter. */
+    masterConfig->glitchFilterWidth = 0U;
+
+/* Default enable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    masterConfig->enableDoubleBuffering = true;
+#endif
+
+    /* Enable the I2C peripheral. */
+    masterConfig->enableMaster = true;
+}
+
+void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask)
+{
+#ifdef I2C_HAS_STOP_DETECT
+    uint8_t fltReg;
+#endif
+
+    if (mask & kI2C_GlobalInterruptEnable)
+    {
+        base->C1 |= I2C_C1_IICIE_MASK;
+    }
+
+#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    if (mask & kI2C_StopDetectInterruptEnable)
+    {
+        fltReg = base->FLT;
+
+        /* Keep STOPF flag. */
+        fltReg &= ~I2C_FLT_STOPF_MASK;
+
+        /* Stop detect enable. */
+        fltReg |= I2C_FLT_STOPIE_MASK;
+        base->FLT = fltReg;
+    }
+#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    if (mask & kI2C_StartStopDetectInterruptEnable)
+    {
+        fltReg = base->FLT;
+
+        /* Keep STARTF and STOPF flags. */
+        fltReg &= ~(I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK);
+
+        /* Start and stop detect enable. */
+        fltReg |= I2C_FLT_SSIE_MASK;
+        base->FLT = fltReg;
+    }
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+}
+
+void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask)
+{
+    if (mask & kI2C_GlobalInterruptEnable)
+    {
+        base->C1 &= ~I2C_C1_IICIE_MASK;
+    }
+
+#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    if (mask & kI2C_StopDetectInterruptEnable)
+    {
+        base->FLT &= ~(I2C_FLT_STOPIE_MASK | I2C_FLT_STOPF_MASK);
+    }
+#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    if (mask & kI2C_StartStopDetectInterruptEnable)
+    {
+        base->FLT &= ~(I2C_FLT_SSIE_MASK | I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK);
+    }
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+}
+
+void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t multiplier;
+    uint32_t computedRate;
+    uint32_t absError;
+    uint32_t bestError = UINT32_MAX;
+    uint32_t bestMult = 0u;
+    uint32_t bestIcr = 0u;
+    uint8_t mult;
+    uint8_t i;
+
+    /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register,
+     * and ranges from 0-2. It selects the multiplier factor for the divider. */
+    for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult)
+    {
+        multiplier = 1u << mult;
+
+        /* Scan table to find best match. */
+        for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(uint16_t); ++i)
+        {
+            computedRate = srcClock_Hz / (multiplier * s_i2cDividerTable[i]);
+            absError = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps);
+
+            if (absError < bestError)
+            {
+                bestMult = mult;
+                bestIcr = i;
+                bestError = absError;
+
+                /* If the error is 0, then we can stop searching because we won't find a better match. */
+                if (absError == 0)
+                {
+                    break;
+                }
+            }
+        }
+    }
+
+    /* Set frequency register based on best settings. */
+    base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr);
+}
+
+status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
+{
+    status_t result = kStatus_Success;
+    uint32_t statusFlags = I2C_MasterGetStatusFlags(base);
+
+    /* Return an error if the bus is already in use. */
+    if (statusFlags & kI2C_BusBusyFlag)
+    {
+        result = kStatus_I2C_Busy;
+    }
+    else
+    {
+        /* Send the START signal. */
+        base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK;
+
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING
+        while (!(base->S2 & I2C_S2_EMPTY_MASK))
+        {
+        }
+#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */
+
+        base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U));
+    }
+
+    return result;
+}
+
+status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
+{
+    status_t result = kStatus_Success;
+    uint8_t savedMult;
+    uint32_t statusFlags = I2C_MasterGetStatusFlags(base);
+    uint8_t timeDelay = 6;
+
+    /* Return an error if the bus is already in use, but not by us. */
+    if ((statusFlags & kI2C_BusBusyFlag) && ((base->C1 & I2C_C1_MST_MASK) == 0))
+    {
+        result = kStatus_I2C_Busy;
+    }
+    else
+    {
+        savedMult = base->F;
+        base->F = savedMult & (~I2C_F_MULT_MASK);
+
+        /* We are already in a transfer, so send a repeated start. */
+        base->C1 |= I2C_C1_RSTA_MASK;
+
+        /* Restore the multiplier factor. */
+        base->F = savedMult;
+
+        /* Add some delay to wait the Re-Start signal. */
+        while (timeDelay--)
+        {
+            __NOP();
+        }
+
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING
+        while (!(base->S2 & I2C_S2_EMPTY_MASK))
+        {
+        }
+#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */
+
+        base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U));
+    }
+
+    return result;
+}
+
+status_t I2C_MasterStop(I2C_Type *base)
+{
+    status_t result = kStatus_Success;
+    uint16_t timeout = UINT16_MAX;
+
+    /* Issue the STOP command on the bus. */
+    base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+    /* Wait until data transfer complete. */
+    while ((base->S & kI2C_BusBusyFlag) && (--timeout))
+    {
+    }
+
+    if (timeout == 0)
+    {
+        result = kStatus_I2C_Timeout;
+    }
+
+    return result;
+}
+
+uint32_t I2C_MasterGetStatusFlags(I2C_Type *base)
+{
+    uint32_t statusFlags = base->S;
+
+#ifdef I2C_HAS_STOP_DETECT
+    /* Look up the STOPF bit from the filter register. */
+    if (base->FLT & I2C_FLT_STOPF_MASK)
+    {
+        statusFlags |= kI2C_StopDetectFlag;
+    }
+#endif
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Look up the STARTF bit from the filter register. */
+    if (base->FLT & I2C_FLT_STARTF_MASK)
+    {
+        statusFlags |= kI2C_StartDetectFlag;
+    }
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+
+    return statusFlags;
+}
+
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)
+{
+    status_t result = kStatus_Success;
+    uint8_t statusFlags = 0;
+
+    /* Wait until the data register is ready for transmit. */
+    while (!(base->S & kI2C_TransferCompleteFlag))
+    {
+    }
+
+    /* Clear the IICIF flag. */
+    base->S = kI2C_IntPendingFlag;
+
+    /* Setup the I2C peripheral to transmit data. */
+    base->C1 |= I2C_C1_TX_MASK;
+
+    while (txSize--)
+    {
+        /* Send a byte of data. */
+        base->D = *txBuff++;
+
+        /* Wait until data transfer complete. */
+        while (!(base->S & kI2C_IntPendingFlag))
+        {
+        }
+
+        statusFlags = base->S;
+
+        /* Clear the IICIF flag. */
+        base->S = kI2C_IntPendingFlag;
+
+        /* Check if arbitration lost or no acknowledgement (NAK), return failure status. */
+        if (statusFlags & kI2C_ArbitrationLostFlag)
+        {
+            base->S = kI2C_ArbitrationLostFlag;
+            result = kStatus_I2C_ArbitrationLost;
+        }
+
+        if ((statusFlags & kI2C_ReceiveNakFlag) && txSize)
+        {
+            base->S = kI2C_ReceiveNakFlag;
+            result = kStatus_I2C_Nak;
+        }
+
+        if (result != kStatus_Success)
+        {
+            /* Breaking out of the send loop. */
+            break;
+        }
+    }
+
+    return result;
+}
+
+status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
+{
+    status_t result = kStatus_Success;
+    volatile uint8_t dummy = 0;
+
+    /* Add this to avoid build warning. */
+    dummy++;
+
+    /* Wait until the data register is ready for transmit. */
+    while (!(base->S & kI2C_TransferCompleteFlag))
+    {
+    }
+
+    /* Clear the IICIF flag. */
+    base->S = kI2C_IntPendingFlag;
+
+    /* Setup the I2C peripheral to receive data. */
+    base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+    /* If rxSize equals 1, configure to send NAK. */
+    if (rxSize == 1)
+    {
+        /* Issue NACK on read. */
+        base->C1 |= I2C_C1_TXAK_MASK;
+    }
+
+    /* Do dummy read. */
+    dummy = base->D;
+
+    while ((rxSize--))
+    {
+        /* Wait until data transfer complete. */
+        while (!(base->S & kI2C_IntPendingFlag))
+        {
+        }
+
+        /* Clear the IICIF flag. */
+        base->S = kI2C_IntPendingFlag;
+
+        /* Single byte use case. */
+        if (rxSize == 0)
+        {
+            /* Read the final byte. */
+            result = I2C_MasterStop(base);
+        }
+
+        if (rxSize == 1)
+        {
+            /* Issue NACK on read. */
+            base->C1 |= I2C_C1_TXAK_MASK;
+        }
+
+        /* Read from the data register. */
+        *rxBuff++ = base->D;
+    }
+
+    return result;
+}
+
+status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer)
+{
+    assert(xfer);
+
+    i2c_direction_t direction = xfer->direction;
+    status_t result = kStatus_Success;
+
+    /* Clear all status before transfer. */
+    I2C_MasterClearStatusFlags(base, kClearFlags);
+
+    /* Wait until ready to complete. */
+    while (!(base->S & kI2C_TransferCompleteFlag))
+    {
+    }
+
+    /* Change to send write address when it's a read operation with command. */
+    if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read))
+    {
+        direction = kI2C_Write;
+    }
+
+    /* If repeated start is requested, send repeated start. */
+    if (xfer->flags & kI2C_TransferRepeatedStartFlag)
+    {
+        result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction);
+    }
+    else /* For normal transfer, send start. */
+    {
+        result = I2C_MasterStart(base, xfer->slaveAddress, direction);
+    }
+
+    /* Return if error. */
+    if (result)
+    {
+        return result;
+    }
+
+    /* Send subaddress. */
+    if (xfer->subaddressSize)
+    {
+        do
+        {
+            /* Wait until data transfer complete. */
+            while (!(base->S & kI2C_IntPendingFlag))
+            {
+            }
+
+            /* Clear interrupt pending flag. */
+            base->S = kI2C_IntPendingFlag;
+
+            /* Check if there's transfer error. */
+            result = I2C_CheckAndClearError(base, base->S);
+
+            if (result)
+            {
+                if (result == kStatus_I2C_Nak)
+                {
+                    I2C_MasterStop(base);
+                }
+
+                return result;
+            }
+
+            xfer->subaddressSize--;
+            base->D = ((xfer->subaddress) >> (8 * xfer->subaddressSize));
+
+        } while ((xfer->subaddressSize > 0) && (result == kStatus_Success));
+
+        if (xfer->direction == kI2C_Read)
+        {
+            /* Wait until data transfer complete. */
+            while (!(base->S & kI2C_IntPendingFlag))
+            {
+            }
+
+            /* Clear pending flag. */
+            base->S = kI2C_IntPendingFlag;
+
+            /* Check if there's transfer error. */
+            result = I2C_CheckAndClearError(base, base->S);
+
+            if (result)
+            {
+                if (result == kStatus_I2C_Nak)
+                {
+                    I2C_MasterStop(base);
+                }
+
+                return result;
+            }
+
+            /* Send repeated start and slave address. */
+            result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read);
+
+            /* Return if error. */
+            if (result)
+            {
+                return result;
+            }
+        }
+    }
+
+    /* Wait until address + command transfer complete. */
+    while (!(base->S & kI2C_IntPendingFlag))
+    {
+    }
+
+    /* Check if there's transfer error. */
+    result = I2C_CheckAndClearError(base, base->S);
+
+    /* Return if error. */
+    if (result)
+    {
+        if (result == kStatus_I2C_Nak)
+        {
+            I2C_MasterStop(base);
+        }
+
+        return result;
+    }
+
+    /* Transmit data. */
+    if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0))
+    {
+        /* Send Data. */
+        result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize);
+
+        if (((result == kStatus_Success) && (!(xfer->flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak))
+        {
+            /* Clear the IICIF flag. */
+            base->S = kI2C_IntPendingFlag;
+
+            /* Send stop. */
+            result = I2C_MasterStop(base);
+        }
+    }
+
+    /* Receive Data. */
+    if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0))
+    {
+        result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize);
+    }
+
+    return result;
+}
+
+void I2C_MasterTransferCreateHandle(I2C_Type *base,
+                                    i2c_master_handle_t *handle,
+                                    i2c_master_transfer_callback_t callback,
+                                    void *userData)
+{
+    assert(handle);
+
+    uint32_t instance = I2C_GetInstance(base);
+
+    /* Zero handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Set callback and userData. */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    s_i2cHandle[instance] = handle;
+
+    /* Save master interrupt handler. */
+    s_i2cMasterIsr = I2C_MasterTransferHandleIRQ;
+
+    /* Enable NVIC interrupt. */
+    EnableIRQ(s_i2cIrqs[instance]);
+}
+
+status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    assert(handle);
+    assert(xfer);
+
+    status_t result = kStatus_Success;
+
+    /* Check if the I2C bus is idle - if not return busy status. */
+    if (handle->state != kIdleState)
+    {
+        result = kStatus_I2C_Busy;
+    }
+    else
+    {
+        /* Start up the master transfer state machine. */
+        result = I2C_InitTransferStateMachine(base, handle, xfer);
+
+        if (result == kStatus_Success)
+        {
+            /* Enable the I2C interrupts. */
+            I2C_EnableInterrupts(base, kI2C_GlobalInterruptEnable);
+        }
+    }
+
+    return result;
+}
+
+void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle)
+{
+    assert(handle);
+
+    /* Disable interrupt. */
+    I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable);
+
+    /* Reset the state to idle. */
+    handle->state = kIdleState;
+}
+
+status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    *count = handle->transferSize - handle->transfer.dataSize;
+
+    return kStatus_Success;
+}
+
+void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
+{
+    assert(i2cHandle);
+
+    i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle;
+    status_t result = kStatus_Success;
+    bool isDone;
+
+    /* Clear the interrupt flag. */
+    base->S = kI2C_IntPendingFlag;
+
+    /* Check transfer complete flag. */
+    result = I2C_MasterTransferRunStateMachine(base, handle, &isDone);
+
+    if (isDone || result)
+    {
+        /* Send stop command if transfer done or received Nak. */
+        if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak))
+        {
+            /* Ensure stop command is a need. */
+            if ((base->C1 & I2C_C1_MST_MASK))
+            {
+                if (I2C_MasterStop(base) != kStatus_Success)
+                {
+                    result = kStatus_I2C_Timeout;
+                }
+            }
+        }
+
+        /* Restore handle to idle state. */
+        handle->state = kIdleState;
+
+        /* Disable interrupt. */
+        I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable);
+
+        /* Call the callback function after the function has completed. */
+        if (handle->completionCallback)
+        {
+            handle->completionCallback(base, handle, result, handle->userData);
+        }
+    }
+}
+
+void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig)
+{
+    assert(slaveConfig);
+
+    uint8_t tmpReg;
+
+    CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]);
+
+    /* Configure addressing mode. */
+    switch (slaveConfig->addressingMode)
+    {
+        case kI2C_Address7bit:
+            base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U;
+            break;
+
+        case kI2C_RangeMatch:
+            assert(slaveConfig->slaveAddress < slaveConfig->upperAddress);
+            base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U;
+            base->RA = ((uint32_t)(slaveConfig->upperAddress)) << 1U;
+            base->C2 |= I2C_C2_RMEN_MASK;
+            break;
+
+        default:
+            break;
+    }
+
+    /* Configure low power wake up feature. */
+    tmpReg = base->C1;
+    tmpReg &= ~I2C_C1_WUEN_MASK;
+    base->C1 = tmpReg | I2C_C1_WUEN(slaveConfig->enableWakeUp) | I2C_C1_IICEN(slaveConfig->enableSlave);
+
+    /* Configure general call & baud rate control & high drive feature. */
+    tmpReg = base->C2;
+    tmpReg &= ~(I2C_C2_SBRC_MASK | I2C_C2_GCAEN_MASK);
+    tmpReg |= I2C_C2_SBRC(slaveConfig->enableBaudRateCtl) | I2C_C2_GCAEN(slaveConfig->enableGeneralCall);
+#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
+    tmpReg &= ~I2C_C2_HDRS_MASK;
+    tmpReg |= I2C_C2_HDRS(slaveConfig->enableHighDrive);
+#endif
+    base->C2 = tmpReg;
+
+/* Enable/Disable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    tmpReg = base->S2 & (~I2C_S2_DFEN_MASK);
+    base->S2 = tmpReg | I2C_S2_DFEN(slaveConfig->enableDoubleBuffering);
+#endif
+}
+
+void I2C_SlaveDeinit(I2C_Type *base)
+{
+    /* Disable I2C module. */
+    I2C_Enable(base, false);
+
+    /* Disable I2C clock. */
+    CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]);
+}
+
+void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)
+{
+    assert(slaveConfig);
+
+    /* By default slave is addressed with 7-bit address. */
+    slaveConfig->addressingMode = kI2C_Address7bit;
+
+    /* General call mode is disabled by default. */
+    slaveConfig->enableGeneralCall = false;
+
+    /* Slave address match waking up MCU from low power mode is disabled. */
+    slaveConfig->enableWakeUp = false;
+
+#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
+    /* Default pin high drive is disabled. */
+    slaveConfig->enableHighDrive = false;
+#endif
+
+    /* Independent slave mode baud rate at maximum frequency is disabled. */
+    slaveConfig->enableBaudRateCtl = false;
+
+/* Default enable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    slaveConfig->enableDoubleBuffering = true;
+#endif
+
+    /* Enable the I2C peripheral. */
+    slaveConfig->enableSlave = true;
+}
+
+status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)
+{
+    status_t result = kStatus_Success;
+    volatile uint8_t dummy = 0;
+
+    /* Add this to avoid build warning. */
+    dummy++;
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Check start flag. */
+    while (!(base->FLT & I2C_FLT_STARTF_MASK))
+    {
+    }
+    /* Clear STARTF flag. */
+    base->FLT |= I2C_FLT_STARTF_MASK;
+    /* Clear the IICIF flag. */
+    base->S = kI2C_IntPendingFlag;
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+
+    /* Wait for address match flag. */
+    while (!(base->S & kI2C_AddressMatchFlag))
+    {
+    }
+
+    /* Read dummy to release bus. */
+    dummy = base->D;
+
+    result = I2C_MasterWriteBlocking(base, txBuff, txSize);
+
+    /* Switch to receive mode. */
+    base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+    /* Read dummy to release bus. */
+    dummy = base->D;
+
+    return result;
+}
+
+void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
+{
+    volatile uint8_t dummy = 0;
+
+    /* Add this to avoid build warning. */
+    dummy++;
+
+/* Wait until address match. */
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Check start flag. */
+    while (!(base->FLT & I2C_FLT_STARTF_MASK))
+    {
+    }
+    /* Clear STARTF flag. */
+    base->FLT |= I2C_FLT_STARTF_MASK;
+    /* Clear the IICIF flag. */
+    base->S = kI2C_IntPendingFlag;
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+
+    /* Wait for address match and int pending flag. */
+    while (!(base->S & kI2C_AddressMatchFlag))
+    {
+    }
+    while (!(base->S & kI2C_IntPendingFlag))
+    {
+    }
+
+    /* Read dummy to release bus. */
+    dummy = base->D;
+
+    /* Clear the IICIF flag. */
+    base->S = kI2C_IntPendingFlag;
+
+    /* Setup the I2C peripheral to receive data. */
+    base->C1 &= ~(I2C_C1_TX_MASK);
+
+    while (rxSize--)
+    {
+        /* Wait until data transfer complete. */
+        while (!(base->S & kI2C_IntPendingFlag))
+        {
+        }
+        /* Clear the IICIF flag. */
+        base->S = kI2C_IntPendingFlag;
+
+        /* Read from the data register. */
+        *rxBuff++ = base->D;
+    }
+}
+
+void I2C_SlaveTransferCreateHandle(I2C_Type *base,
+                                   i2c_slave_handle_t *handle,
+                                   i2c_slave_transfer_callback_t callback,
+                                   void *userData)
+{
+    assert(handle);
+
+    uint32_t instance = I2C_GetInstance(base);
+
+    /* Zero handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Set callback and userData. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    s_i2cHandle[instance] = handle;
+
+    /* Save slave interrupt handler. */
+    s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ;
+
+    /* Enable NVIC interrupt. */
+    EnableIRQ(s_i2cIrqs[instance]);
+}
+
+status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask)
+{
+    assert(handle);
+
+    /* Check if the I2C bus is idle - if not return busy status. */
+    if (handle->isBusy)
+    {
+        return kStatus_I2C_Busy;
+    }
+    else
+    {
+        /* Disable LPI2C IRQ sources while we configure stuff. */
+        I2C_DisableInterrupts(base, kIrqFlags);
+
+        /* Clear transfer in handle. */
+        memset(&handle->transfer, 0, sizeof(handle->transfer));
+
+        /* Record that we're busy. */
+        handle->isBusy = true;
+
+        /* Set up event mask. tx and rx are always enabled. */
+        handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent;
+
+        /* Clear all flags. */
+        I2C_SlaveClearStatusFlags(base, kClearFlags);
+
+        /* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */
+        I2C_EnableInterrupts(base, kIrqFlags);
+    }
+
+    return kStatus_Success;
+}
+
+void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle)
+{
+    assert(handle);
+
+    if (handle->isBusy)
+    {
+        /* Disable interrupts. */
+        I2C_DisableInterrupts(base, kIrqFlags);
+
+        /* Reset transfer info. */
+        memset(&handle->transfer, 0, sizeof(handle->transfer));
+
+        /* Reset the state to idle. */
+        handle->isBusy = false;
+    }
+}
+
+status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (!handle->isBusy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    /* For an active transfer, just return the count from the handle. */
+    *count = handle->transfer.transferredCount;
+
+    return kStatus_Success;
+}
+
+void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
+{
+    assert(i2cHandle);
+
+    uint16_t status;
+    bool doTransmit = false;
+    i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle;
+    i2c_slave_transfer_t *xfer;
+    volatile uint8_t dummy = 0;
+
+    /* Add this to avoid build warning. */
+    dummy++;
+
+    status = I2C_SlaveGetStatusFlags(base);
+    xfer = &(handle->transfer);
+
+#ifdef I2C_HAS_STOP_DETECT
+    /* Check stop flag. */
+    if (status & kI2C_StopDetectFlag)
+    {
+        I2C_MasterClearStatusFlags(base, kI2C_StopDetectFlag);
+
+        /* Clear the interrupt flag. */
+        base->S = kI2C_IntPendingFlag;
+
+        /* Call slave callback if this is the STOP of the transfer. */
+        if (handle->isBusy)
+        {
+            xfer->event = kI2C_SlaveCompletionEvent;
+            xfer->completionStatus = kStatus_Success;
+            handle->isBusy = false;
+
+            if ((handle->eventMask & xfer->event) && (handle->callback))
+            {
+                handle->callback(base, xfer, handle->userData);
+            }
+        }
+
+        return;
+    }
+#endif /* I2C_HAS_STOP_DETECT */
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Check start flag. */
+    if (status & kI2C_StartDetectFlag)
+    {
+        I2C_MasterClearStatusFlags(base, kI2C_StartDetectFlag);
+
+        /* Clear the interrupt flag. */
+        base->S = kI2C_IntPendingFlag;
+
+        xfer->event = kI2C_SlaveStartEvent;
+
+        if ((handle->eventMask & xfer->event) && (handle->callback))
+        {
+            handle->callback(base, xfer, handle->userData);
+        }
+
+        if (!(status & kI2C_AddressMatchFlag))
+        {
+            return;
+        }
+    }
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+
+    /* Clear the interrupt flag. */
+    base->S = kI2C_IntPendingFlag;
+
+    /* Check NAK */
+    if (status & kI2C_ReceiveNakFlag)
+    {
+        /* Set receive mode. */
+        base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+        /* Read dummy. */
+        dummy = base->D;
+
+        if (handle->transfer.dataSize != 0)
+        {
+            xfer->event = kI2C_SlaveCompletionEvent;
+            xfer->completionStatus = kStatus_I2C_Nak;
+            handle->isBusy = false;
+
+            if ((handle->eventMask & xfer->event) && (handle->callback))
+            {
+                handle->callback(base, xfer, handle->userData);
+            }
+        }
+        else
+        {
+#ifndef I2C_HAS_STOP_DETECT
+            xfer->event = kI2C_SlaveCompletionEvent;
+            xfer->completionStatus = kStatus_Success;
+            handle->isBusy = false;
+
+            if ((handle->eventMask & xfer->event) && (handle->callback))
+            {
+                handle->callback(base, xfer, handle->userData);
+            }
+#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */
+        }
+    }
+    /* Check address match. */
+    else if (status & kI2C_AddressMatchFlag)
+    {
+        handle->isBusy = true;
+        xfer->event = kI2C_SlaveAddressMatchEvent;
+
+        if ((handle->eventMask & xfer->event) && (handle->callback))
+        {
+            handle->callback(base, xfer, handle->userData);
+        }
+
+        /* Slave transmit, master reading from slave. */
+        if (status & kI2C_TransferDirectionFlag)
+        {
+            /* Change direction to send data. */
+            base->C1 |= I2C_C1_TX_MASK;
+
+            doTransmit = true;
+        }
+        else
+        {
+            /* Slave receive, master writing to slave. */
+            base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+            /* Read dummy to release the bus. */
+            dummy = base->D;
+        }
+    }
+    /* Check transfer complete flag. */
+    else if (status & kI2C_TransferCompleteFlag)
+    {
+        /* Slave transmit, master reading from slave. */
+        if (status & kI2C_TransferDirectionFlag)
+        {
+            doTransmit = true;
+        }
+        else
+        {
+            /* If we're out of data, invoke callback to get more. */
+            if ((!xfer->data) || (!xfer->dataSize))
+            {
+                xfer->event = kI2C_SlaveReceiveEvent;
+
+                if (handle->callback)
+                {
+                    handle->callback(base, xfer, handle->userData);
+                }
+
+                /* Clear the transferred count now that we have a new buffer. */
+                xfer->transferredCount = 0;
+            }
+
+            /* Slave receive, master writing to slave. */
+            uint8_t data = base->D;
+
+            if (handle->transfer.dataSize)
+            {
+                /* Receive data. */
+                *handle->transfer.data++ = data;
+                handle->transfer.dataSize--;
+                xfer->transferredCount++;
+                if (!handle->transfer.dataSize)
+                {
+#ifndef I2C_HAS_STOP_DETECT
+                    xfer->event = kI2C_SlaveCompletionEvent;
+                    xfer->completionStatus = kStatus_Success;
+                    handle->isBusy = false;
+
+                    /* Proceed receive complete event. */
+                    if ((handle->eventMask & xfer->event) && (handle->callback))
+                    {
+                        handle->callback(base, xfer, handle->userData);
+                    }
+#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */
+                }
+            }
+        }
+    }
+    else
+    {
+        /* Read dummy to release bus. */
+        dummy = base->D;
+    }
+
+    /* Send data if there is the need. */
+    if (doTransmit)
+    {
+        /* If we're out of data, invoke callback to get more. */
+        if ((!xfer->data) || (!xfer->dataSize))
+        {
+            xfer->event = kI2C_SlaveTransmitEvent;
+
+            if (handle->callback)
+            {
+                handle->callback(base, xfer, handle->userData);
+            }
+
+            /* Clear the transferred count now that we have a new buffer. */
+            xfer->transferredCount = 0;
+        }
+
+        if (handle->transfer.dataSize)
+        {
+            /* Send data. */
+            base->D = *handle->transfer.data++;
+            handle->transfer.dataSize--;
+            xfer->transferredCount++;
+        }
+        else
+        {
+            /* Switch to receive mode. */
+            base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+            /* Read dummy to release bus. */
+            dummy = base->D;
+
+#ifndef I2C_HAS_STOP_DETECT
+            xfer->event = kI2C_SlaveCompletionEvent;
+            xfer->completionStatus = kStatus_Success;
+            handle->isBusy = false;
+
+            /* Proceed txdone event. */
+            if ((handle->eventMask & xfer->event) && (handle->callback))
+            {
+                handle->callback(base, xfer, handle->userData);
+            }
+#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */
+        }
+    }
+}
+
+void I2C0_DriverIRQHandler(void)
+{
+    I2C_TransferCommonIRQHandler(I2C0, s_i2cHandle[0]);
+}
+
+#if (FSL_FEATURE_SOC_I2C_COUNT > 1)
+void I2C1_DriverIRQHandler(void)
+{
+    I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]);
+}
+#endif /* I2C COUNT > 1 */
+
+#if (FSL_FEATURE_SOC_I2C_COUNT > 2)
+void I2C2_DriverIRQHandler(void)
+{
+    I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]);
+}
+#endif /* I2C COUNT > 2 */
+#if (FSL_FEATURE_SOC_I2C_COUNT > 3)
+void I2C3_DriverIRQHandler(void)
+{
+    I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]);
+}
+#endif /* I2C COUNT > 3 */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c.h
new file mode 100644
index 00000000000..7117fd5753c
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c.h
@@ -0,0 +1,788 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2C_H_
+#define _FSL_I2C_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup i2c_driver
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2C driver version 2.0.1. */
+#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+#if (defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT || \
+     defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT)
+#define I2C_HAS_STOP_DETECT
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */
+
+/*! @brief  I2C status return codes. */
+enum _i2c_status
+{
+    kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0),            /*!< I2C is busy with current transfer. */
+    kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1),            /*!< Bus is Idle. */
+    kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2),             /*!< NAK received during transfer. */
+    kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */
+    kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4),         /*!< Wait event timeout. */
+};
+
+/*!
+ * @brief I2C peripheral flags
+ *
+ * The following status register flags can be cleared:
+ * - #kI2C_ArbitrationLostFlag
+ * - #kI2C_IntPendingFlag
+ * - #kI2C_StartDetectFlag
+ * - #kI2C_StopDetectFlag
+ *
+ * @note These enumerations are meant to be OR'd together to form a bit mask.
+ *
+ */
+enum _i2c_flags
+{
+    kI2C_ReceiveNakFlag = I2C_S_RXAK_MASK,       /*!< I2C receive NAK flag. */
+    kI2C_IntPendingFlag = I2C_S_IICIF_MASK,      /*!< I2C interrupt pending flag. */
+    kI2C_TransferDirectionFlag = I2C_S_SRW_MASK, /*!< I2C transfer direction flag. */
+    kI2C_RangeAddressMatchFlag = I2C_S_RAM_MASK, /*!< I2C range address match flag. */
+    kI2C_ArbitrationLostFlag = I2C_S_ARBL_MASK,  /*!< I2C arbitration lost flag. */
+    kI2C_BusBusyFlag = I2C_S_BUSY_MASK,          /*!< I2C bus busy flag. */
+    kI2C_AddressMatchFlag = I2C_S_IAAS_MASK,     /*!< I2C address match flag. */
+    kI2C_TransferCompleteFlag = I2C_S_TCF_MASK,  /*!< I2C transfer complete flag. */
+#ifdef I2C_HAS_STOP_DETECT
+    kI2C_StopDetectFlag = I2C_FLT_STOPF_MASK << 8, /*!< I2C stop detect flag. */
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    kI2C_StartDetectFlag = I2C_FLT_STARTF_MASK << 8, /*!< I2C start detect flag. */
+#endif                                               /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+};
+
+/*! @brief I2C feature interrupt source. */
+enum _i2c_interrupt_enable
+{
+    kI2C_GlobalInterruptEnable = I2C_C1_IICIE_MASK, /*!< I2C global interrupt. */
+
+#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    kI2C_StopDetectInterruptEnable = I2C_FLT_STOPIE_MASK, /*!< I2C stop detect interrupt. */
+#endif                                                    /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    kI2C_StartStopDetectInterruptEnable = I2C_FLT_SSIE_MASK, /*!< I2C start&stop detect interrupt. */
+#endif                                                       /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+};
+
+/*! @brief Direction of master and slave transfers. */
+typedef enum _i2c_direction
+{
+    kI2C_Write = 0x0U, /*!< Master transmit to slave. */
+    kI2C_Read = 0x1U,  /*!< Master receive from slave. */
+} i2c_direction_t;
+
+/*! @brief Addressing mode. */
+typedef enum _i2c_slave_address_mode
+{
+    kI2C_Address7bit = 0x0U, /*!< 7-bit addressing mode. */
+    kI2C_RangeMatch = 0X2U,  /*!< Range address match addressing mode. */
+} i2c_slave_address_mode_t;
+
+/*! @brief I2C transfer control flag. */
+enum _i2c_master_transfer_flags
+{
+    kI2C_TransferDefaultFlag = 0x0U,       /*!< Transfer starts with a start signal, stops with a stop signal. */
+    kI2C_TransferNoStartFlag = 0x1U,       /*!< Transfer starts without a start signal. */
+    kI2C_TransferRepeatedStartFlag = 0x2U, /*!< Transfer starts with a repeated start signal. */
+    kI2C_TransferNoStopFlag = 0x4U,        /*!< Transfer ends without a stop signal. */
+};
+
+/*!
+ * @brief Set of events sent to the callback for nonblocking slave transfers.
+ *
+ * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together
+ * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable.
+ * Then, when the slave callback is invoked, it is passed the current event through its @a transfer
+ * parameter.
+ *
+ * @note These enumerations are meant to be OR'd together to form a bit mask of events.
+ */
+typedef enum _i2c_slave_transfer_event
+{
+    kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */
+    kI2C_SlaveTransmitEvent = 0x02U,     /*!< Callback is requested to provide data to transmit
+                                                (slave-transmitter role). */
+    kI2C_SlaveReceiveEvent = 0x04U,      /*!< Callback is requested to provide a buffer in which to place received
+                                                 data (slave-receiver role). */
+    kI2C_SlaveTransmitAckEvent = 0x08U,  /*!< Callback needs to either transmit an ACK or NACK. */
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    kI2C_SlaveStartEvent = 0x10U, /*!< A start/repeated start was detected. */
+#endif
+    kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */
+
+    /*! Bit mask of all available events. */
+    kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent |
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+                          kI2C_SlaveStartEvent |
+#endif
+                          kI2C_SlaveCompletionEvent,
+} i2c_slave_transfer_event_t;
+
+/*! @brief I2C master user configuration. */
+typedef struct _i2c_master_config
+{
+    bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */
+#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
+    bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */
+#endif
+#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
+    bool enableStopHold; /*!< Controls the stop hold enable. */
+#endif
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    bool enableDoubleBuffering; /*!< Controls double buffer enable, notice that
+                                     enabling the double buffer disables the clock stretch. */
+#endif
+    uint32_t baudRate_Bps;     /*!< Baud rate configuration of I2C peripheral. */
+    uint8_t glitchFilterWidth; /*!< Controls the width of the glitch. */
+} i2c_master_config_t;
+
+/*! @brief I2C slave user configuration. */
+typedef struct _i2c_slave_config
+{
+    bool enableSlave;       /*!< Enables the I2C peripheral at initialization time. */
+    bool enableGeneralCall; /*!< Enable general call addressing mode. */
+    bool enableWakeUp;      /*!< Enables/disables waking up MCU from low-power mode. */
+#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
+    bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */
+#endif
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    bool enableDoubleBuffering; /*!< Controls double buffer enable, notice that
+                                     enabling the double buffer disables the clock stretch. */
+#endif
+    bool enableBaudRateCtl; /*!< Enables/disables independent slave baud rate on SCL in very fast I2C modes. */
+    uint16_t slaveAddress;  /*!< Slave address configuration. */
+    uint16_t upperAddress;  /*!< Maximum boundary slave address used in range matching mode. */
+    i2c_slave_address_mode_t addressingMode; /*!< Addressing mode configuration of i2c_slave_address_mode_config_t. */
+} i2c_slave_config_t;
+
+/*! @brief I2C master handle typedef. */
+typedef struct _i2c_master_handle i2c_master_handle_t;
+
+/*! @brief I2C master transfer callback typedef. */
+typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base,
+                                               i2c_master_handle_t *handle,
+                                               status_t status,
+                                               void *userData);
+
+/*! @brief I2C slave handle typedef. */
+typedef struct _i2c_slave_handle i2c_slave_handle_t;
+
+/*! @brief I2C master transfer structure. */
+typedef struct _i2c_master_transfer
+{
+    uint32_t flags;            /*!< Transfer flag which controls the transfer. */
+    uint8_t slaveAddress;      /*!< 7-bit slave address. */
+    i2c_direction_t direction; /*!< Transfer direction, read or write. */
+    uint32_t subaddress;       /*!< Sub address. Transferred MSB first. */
+    uint8_t subaddressSize;    /*!< Size of command buffer. */
+    uint8_t *volatile data;    /*!< Transfer buffer. */
+    volatile size_t dataSize;  /*!< Transfer size. */
+} i2c_master_transfer_t;
+
+/*! @brief I2C master handle structure. */
+struct _i2c_master_handle
+{
+    i2c_master_transfer_t transfer;                    /*!< I2C master transfer copy. */
+    size_t transferSize;                               /*!< Total bytes to be transferred. */
+    uint8_t state;                                     /*!< Transfer state maintained during transfer. */
+    i2c_master_transfer_callback_t completionCallback; /*!< Callback function called when transfer finished. */
+    void *userData;                                    /*!< Callback parameter passed to callback function. */
+};
+
+/*! @brief I2C slave transfer structure. */
+typedef struct _i2c_slave_transfer
+{
+    i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */
+    uint8_t *volatile data;           /*!< Transfer buffer. */
+    volatile size_t dataSize;         /*!< Transfer size. */
+    status_t completionStatus;        /*!< Success or error code describing how the transfer completed. Only applies for
+                                         #kI2C_SlaveCompletionEvent. */
+    size_t transferredCount;          /*!< Number of bytes actually transferred since start or last repeated start. */
+} i2c_slave_transfer_t;
+
+/*! @brief I2C slave transfer callback typedef. */
+typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData);
+
+/*! @brief I2C slave handle structure. */
+struct _i2c_slave_handle
+{
+    bool isBusy;                            /*!< Whether transfer is busy. */
+    i2c_slave_transfer_t transfer;          /*!< I2C slave transfer copy. */
+    uint32_t eventMask;                     /*!< Mask of enabled events. */
+    i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */
+    void *userData;                         /*!< Callback parameter passed to callback. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus. */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
+ * and configure the I2C with master configuration.
+ *
+ * @note This API should be called at the beginning of the application to use
+ * the I2C driver, or any operation to the I2C module may cause a hard fault
+ * because clock is not enabled. The configuration structure can be filled by user
+ * from scratch, or be set with default values by I2C_MasterGetDefaultConfig().
+ * After calling this API, the master is ready to transfer.
+ * Example:
+ * @code
+ * i2c_master_config_t config = {
+ * .enableMaster = true,
+ * .enableStopHold = false,
+ * .highDrive = false,
+ * .baudRate_Bps = 100000,
+ * .glitchFilterWidth = 0
+ * };
+ * I2C_MasterInit(I2C0, &config, 12000000U);
+ * @endcode
+ *
+ * @param base I2C base pointer
+ * @param masterConfig pointer to master configuration structure
+ * @param srcClock_Hz I2C peripheral clock frequency in Hz
+ */
+void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
+ * and initializes the I2C with slave configuration.
+ *
+ * @note This API should be called at the beginning of the application to use
+ * the I2C driver, or any operation to the I2C module can cause a hard fault
+ * because the clock is not enabled. The configuration structure can partly be set
+ * with default values by I2C_SlaveGetDefaultConfig(), or can be filled by the user.
+ * Example
+ * @code
+ * i2c_slave_config_t config = {
+ * .enableSlave = true,
+ * .enableGeneralCall = false,
+ * .addressingMode = kI2C_Address7bit,
+ * .slaveAddress = 0x1DU,
+ * .enableWakeUp = false,
+ * .enablehighDrive = false,
+ * .enableBaudRateCtl = false
+ * };
+ * I2C_SlaveInit(I2C0, &config);
+ * @endcode
+ *
+ * @param base I2C base pointer
+ * @param slaveConfig pointer to slave configuration structure
+ */
+void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig);
+
+/*!
+ * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock.
+ * The I2C master module can't work unless the I2C_MasterInit is called.
+ * @param base I2C base pointer
+ */
+void I2C_MasterDeinit(I2C_Type *base);
+
+/*!
+ * @brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock.
+ * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock.
+ * @param base I2C base pointer
+ */
+void I2C_SlaveDeinit(I2C_Type *base);
+
+/*!
+ * @brief  Sets the I2C master configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure().
+ * Use the initialized structure unchanged in I2C_MasterConfigure(), or modify some fields of
+ * the structure before calling I2C_MasterConfigure().
+ * Example:
+ * @code
+ * i2c_master_config_t config;
+ * I2C_MasterGetDefaultConfig(&config);
+ * @endcode
+ * @param masterConfig Pointer to the master configuration structure.
+*/
+void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig);
+
+/*!
+ * @brief  Sets the I2C slave configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in I2C_SlaveConfigure().
+ * Modify fields of the structure before calling the I2C_SlaveConfigure().
+ * Example:
+ * @code
+ * i2c_slave_config_t config;
+ * I2C_SlaveGetDefaultConfig(&config);
+ * @endcode
+ * @param slaveConfig Pointer to the slave configuration structure.
+ */
+void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig);
+
+/*!
+ * @brief Enables or disabless the I2C peripheral operation.
+ *
+ * @param base I2C base pointer
+ * @param enable pass true to enable module, false to disable module
+ */
+static inline void I2C_Enable(I2C_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->C1 |= I2C_C1_IICEN_MASK;
+    }
+    else
+    {
+        base->C1 &= ~I2C_C1_IICEN_MASK;
+    }
+}
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the I2C status flags.
+ *
+ * @param base I2C base pointer
+ * @return status flag, use status flag to AND #_i2c_flags to get the related status.
+ */
+uint32_t I2C_MasterGetStatusFlags(I2C_Type *base);
+
+/*!
+ * @brief Gets the I2C status flags.
+ *
+ * @param base I2C base pointer
+ * @return status flag, use status flag to AND #_i2c_flags to get the related status.
+ */
+static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base)
+{
+    return I2C_MasterGetStatusFlags(base);
+}
+
+/*!
+ * @brief Clears the I2C status flag state.
+ *
+ * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag
+ *
+ * @param base I2C base pointer
+ * @param statusMask The status flag mask, defined in type i2c_status_flag_t.
+ *      The parameter can be any combination of the following values:
+ *          @arg kI2C_StartDetectFlag (if available)
+ *          @arg kI2C_StopDetectFlag (if available)
+ *          @arg kI2C_ArbitrationLostFlag
+ *          @arg kI2C_IntPendingFlagFlag
+ */
+static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask)
+{
+/* Must clear the STARTF / STOPF bits prior to clearing IICIF */
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    if (statusMask & kI2C_StartDetectFlag)
+    {
+        /* Shift the odd-ball flags back into place. */
+        base->FLT |= (uint8_t)(statusMask >> 8U);
+    }
+#endif
+
+#ifdef I2C_HAS_STOP_DETECT
+    if (statusMask & kI2C_StopDetectFlag)
+    {
+        /* Shift the odd-ball flags back into place. */
+        base->FLT |= (uint8_t)(statusMask >> 8U);
+    }
+#endif
+
+    base->S = (uint8_t)statusMask;
+}
+
+/*!
+ * @brief Clears the I2C status flag state.
+ *
+ * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag
+ *
+  * @param base I2C base pointer
+  * @param statusMask The status flag mask, defined in type i2c_status_flag_t.
+ *      The parameter can be any combination of the following values:
+ *          @arg kI2C_StartDetectFlag (if available)
+ *          @arg kI2C_StopDetectFlag (if available)
+ *          @arg kI2C_ArbitrationLostFlag
+ *          @arg kI2C_IntPendingFlagFlag
+ */
+static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask)
+{
+    I2C_MasterClearStatusFlags(base, statusMask);
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables I2C interrupt requests.
+ *
+ * @param base I2C base pointer
+ * @param mask interrupt source
+ *     The parameter can be combination of the following source if defined:
+ *     @arg kI2C_GlobalInterruptEnable
+ *     @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
+ *     @arg kI2C_SdaTimeoutInterruptEnable
+ */
+void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables I2C interrupt requests.
+ *
+ * @param base I2C base pointer
+ * @param mask interrupt source
+ *     The parameter can be combination of the following source if defined:
+ *     @arg kI2C_GlobalInterruptEnable
+ *     @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
+ *     @arg kI2C_SdaTimeoutInterruptEnable
+ */
+void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask);
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+#if defined(FSL_FEATURE_I2C_HAS_DMA_SUPPORT) && FSL_FEATURE_I2C_HAS_DMA_SUPPORT
+/*!
+ * @brief Enables/disables the I2C DMA interrupt.
+ *
+ * @param base I2C base pointer
+ * @param enable true to enable, false to disable
+*/
+static inline void I2C_EnableDMA(I2C_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->C1 |= I2C_C1_DMAEN_MASK;
+    }
+    else
+    {
+        base->C1 &= ~I2C_C1_DMAEN_MASK;
+    }
+}
+
+#endif /* FSL_FEATURE_I2C_HAS_DMA_SUPPORT */
+
+/*!
+ * @brief  Gets the I2C tx/rx data register address. This API is used to provide a transfer address
+ * for I2C DMA transfer configuration.
+ *
+ * @param base I2C base pointer
+ * @return data register address
+ */
+static inline uint32_t I2C_GetDataRegAddr(I2C_Type *base)
+{
+    return (uint32_t)(&(base->D));
+}
+
+/* @} */
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Sets the I2C master transfer baud rate.
+ *
+ * @param base I2C base pointer
+ * @param baudRate_Bps the baud rate value in bps
+ * @param srcClock_Hz Source clock
+ */
+void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Sends a START on the I2C bus.
+ *
+ * This function is used to initiate a new master mode transfer by sending the START signal.
+ * The slave address is sent following the I2C START signal.
+ *
+ * @param base I2C peripheral base pointer
+ * @param address 7-bit slave device address.
+ * @param direction Master transfer directions(transmit/receive).
+ * @retval kStatus_Success Successfully send the start signal.
+ * @retval kStatus_I2C_Busy Current bus is busy.
+ */
+status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction);
+
+/*!
+ * @brief Sends a STOP signal on the I2C bus.
+ *
+ * @retval kStatus_Success Successfully send the stop signal.
+ * @retval kStatus_I2C_Timeout Send stop signal failed, timeout.
+ */
+status_t I2C_MasterStop(I2C_Type *base);
+
+/*!
+ * @brief Sends a REPEATED START on the I2C bus.
+ *
+ * @param base I2C peripheral base pointer
+ * @param address 7-bit slave device address.
+ * @param direction Master transfer directions(transmit/receive).
+ * @retval kStatus_Success Successfully send the start signal.
+ * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master.
+ */
+status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction);
+
+/*!
+ * @brief Performs a polling send transaction on the I2C bus without a STOP signal.
+ *
+ * @param base  The I2C peripheral base pointer.
+ * @param txBuff The pointer to the data to be transferred.
+ * @param txSize The length in bytes of the data to be transferred.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
+ */
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize);
+
+/*!
+ * @brief Performs a polling receive transaction on the I2C bus with a STOP signal.
+ *
+ * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte.
+ * Without stopping the bus prior for the final read, the bus issues another read, resulting
+ * in garbage data being read into the data register.
+ *
+ * @param base I2C peripheral base pointer.
+ * @param rxBuff The pointer to the data to store the received data.
+ * @param rxSize The length in bytes of the data to be received.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval kStatus_I2C_Timeout Send stop signal failed, timeout.
+ */
+status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize);
+
+/*!
+ * @brief Performs a polling send transaction on the I2C bus.
+ *
+ * @param base  The I2C peripheral base pointer.
+ * @param txBuff The pointer to the data to be transferred.
+ * @param txSize The length in bytes of the data to be transferred.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
+ */
+status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize);
+
+/*!
+ * @brief Performs a polling receive transaction on the I2C bus.
+ *
+ * @param base I2C peripheral base pointer.
+ * @param rxBuff The pointer to the data to store the received data.
+ * @param rxSize The length in bytes of the data to be received.
+ */
+void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize);
+
+/*!
+ * @brief Performs a master polling transfer on the I2C bus.
+ *
+ * @note The API does not return until the transfer succeeds or fails due
+ * to arbitration lost or receiving a NAK.
+ *
+ * @param base I2C peripheral base address.
+ * @param xfer Pointer to the transfer structure.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval kStatus_I2C_Busy Previous transmission still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
+ */
+status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the I2C handle which is used in transactional functions.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_master_handle_t structure to store the transfer state.
+ * @param callback pointer to user callback function.
+ * @param userData user parameter passed to the callback function.
+ */
+void I2C_MasterTransferCreateHandle(I2C_Type *base,
+                                    i2c_master_handle_t *handle,
+                                    i2c_master_transfer_callback_t callback,
+                                    void *userData);
+
+/*!
+ * @brief Performs a master interrupt non-blocking transfer on the I2C bus.
+ *
+ * @note Calling the API returns immediately after transfer initiates. The user needs
+ * to call I2C_MasterGetTransferCount to poll the transfer status to check whether
+ * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer
+ * is finished.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_master_handle_t structure which stores the transfer state.
+ * @param xfer pointer to i2c_master_transfer_t structure.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_I2C_Busy Previous transmission still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ */
+status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Gets the master transfer status during a interrupt non-blocking transfer.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_master_handle_t structure which stores the transfer state.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Aborts an interrupt non-blocking transfer early.
+ *
+ * @note This API can be called at any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_master_handle_t structure which stores the transfer state
+ */
+void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle);
+
+/*!
+ * @brief Master interrupt handler.
+ *
+ * @param base I2C base pointer.
+ * @param i2cHandle pointer to i2c_master_handle_t structure.
+ */
+void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle);
+
+/*!
+ * @brief Initializes the I2C handle which is used in transactional functions.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_slave_handle_t structure to store the transfer state.
+ * @param callback pointer to user callback function.
+ * @param userData user parameter passed to the callback function.
+ */
+void I2C_SlaveTransferCreateHandle(I2C_Type *base,
+                                   i2c_slave_handle_t *handle,
+                                   i2c_slave_transfer_callback_t callback,
+                                   void *userData);
+
+/*!
+ * @brief Starts accepting slave transfers.
+ *
+ * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing
+ * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the
+ * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked
+ * from the interrupt context.
+ *
+ * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
+ * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
+ * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need
+ * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and
+ * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
+ * a convenient way to enable all events.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state.
+ * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. Other accepted values are 0 to get a default set of
+ *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
+ *
+ * @retval #kStatus_Success Slave transfers were successfully started.
+ * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask);
+
+/*!
+ * @brief Aborts the slave transfer.
+ *
+ * @note This API can be called at any time to stop slave for handling the bus events.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state.
+ */
+void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle);
+
+/*!
+ * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_slave_handle_t structure.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Slave interrupt handler.
+ *
+ * @param base I2C base pointer.
+ * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state
+ */
+void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle);
+
+/* @} */
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus. */
+/*@}*/
+
+#endif /* _FSL_I2C_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c_edma.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c_edma.c
new file mode 100644
index 00000000000..c8f7c20629f
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c_edma.c
@@ -0,0 +1,526 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_i2c_edma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! @breif Structure definition for i2c_master_edma_private_handle_t. The structure is private. */
+typedef struct _i2c_master_edma_private_handle
+{
+    I2C_Type *base;
+    i2c_master_edma_handle_t *handle;
+} i2c_master_edma_private_handle_t;
+
+/*! @brief i2c master DMA transfer state. */
+enum _i2c_master_dma_transfer_states
+{
+    kIdleState = 0x0U,         /*!< I2C bus idle. */
+    kTransferDataState = 0x1U, /*!< 7-bit address check state. */
+};
+
+/*! @brief Common sets of flags used by the driver. */
+enum _i2c_flag_constants
+{
+/*! All flags which are cleared by the driver upon starting a transfer. */
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StartDetectFlag | kI2C_StopDetectFlag,
+#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StopDetectFlag,
+#else
+    kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag,
+#endif
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief EDMA callback for I2C master EDMA driver.
+ *
+ * @param handle EDMA handler for I2C master EDMA driver
+ * @param userData user param passed to the callback function
+ */
+static void I2C_MasterTransferCallbackEDMA(edma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds);
+
+/*!
+ * @brief Check and clear status operation.
+ *
+ * @param base I2C peripheral base address.
+ * @param status current i2c hardware status.
+ * @retval kStatus_Success No error found.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStatus_I2C_Nak Received Nak error.
+ */
+static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status);
+
+/*!
+ * @brief EDMA config for I2C master driver.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_edma_handle_t structure which stores the transfer state
+ */
+static void I2C_MasterTransferEDMAConfig(I2C_Type *base, i2c_master_edma_handle_t *handle);
+
+/*!
+ * @brief Set up master transfer, send slave address and sub address(if any), wait until the
+ * wait until address sent status return.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_edma_handle_t structure which stores the transfer state
+ * @param xfer pointer to i2c_master_transfer_t structure
+ */
+static status_t I2C_InitTransferStateMachineEDMA(I2C_Type *base,
+                                                 i2c_master_edma_handle_t *handle,
+                                                 i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Get the I2C instance from peripheral base address.
+ *
+ * @param base I2C peripheral base address.
+ * @return I2C instance.
+ */
+extern uint32_t I2C_GetInstance(I2C_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*<! Private handle only used for internally. */
+static i2c_master_edma_private_handle_t s_edmaPrivateHandle[FSL_FEATURE_SOC_I2C_COUNT];
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+static void I2C_MasterTransferCallbackEDMA(edma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds)
+{
+    i2c_master_edma_private_handle_t *i2cPrivateHandle = (i2c_master_edma_private_handle_t *)userData;
+    status_t result = kStatus_Success;
+
+    /* Disable DMA. */
+    I2C_EnableDMA(i2cPrivateHandle->base, false);
+
+    /* Send stop if kI2C_TransferNoStop flag is not asserted. */
+    if (!(i2cPrivateHandle->handle->transfer.flags & kI2C_TransferNoStopFlag))
+    {
+        if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read)
+        {
+            /* Change to send NAK at the last byte. */
+            i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK;
+
+            /* Wait the last data to be received. */
+            while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag))
+            {
+            }
+
+            /* Send stop signal. */
+            result = I2C_MasterStop(i2cPrivateHandle->base);
+
+            /* Read the last data byte. */
+            *(i2cPrivateHandle->handle->transfer.data + i2cPrivateHandle->handle->transfer.dataSize - 1) =
+                i2cPrivateHandle->base->D;
+        }
+        else
+        {
+            /* Wait the last data to be sent. */
+            while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag))
+            {
+            }
+
+            /* Send stop signal. */
+            result = I2C_MasterStop(i2cPrivateHandle->base);
+        }
+    }
+
+    i2cPrivateHandle->handle->state = kIdleState;
+
+    if (i2cPrivateHandle->handle->completionCallback)
+    {
+        i2cPrivateHandle->handle->completionCallback(i2cPrivateHandle->base, i2cPrivateHandle->handle, result,
+                                                     i2cPrivateHandle->handle->userData);
+    }
+}
+
+static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status)
+{
+    status_t result = kStatus_Success;
+
+    /* Check arbitration lost. */
+    if (status & kI2C_ArbitrationLostFlag)
+    {
+        /* Clear arbitration lost flag. */
+        base->S = kI2C_ArbitrationLostFlag;
+        result = kStatus_I2C_ArbitrationLost;
+    }
+    /* Check NAK */
+    else if (status & kI2C_ReceiveNakFlag)
+    {
+        result = kStatus_I2C_Nak;
+    }
+    else
+    {
+    }
+
+    return result;
+}
+
+static status_t I2C_InitTransferStateMachineEDMA(I2C_Type *base,
+                                                 i2c_master_edma_handle_t *handle,
+                                                 i2c_master_transfer_t *xfer)
+{
+    assert(handle);
+    assert(xfer);
+
+    status_t result = kStatus_Success;
+    uint16_t timeout = UINT16_MAX;
+
+    if (handle->state != kIdleState)
+    {
+        return kStatus_I2C_Busy;
+    }
+    else
+    {
+        i2c_direction_t direction = xfer->direction;
+
+        /* Init the handle member. */
+        handle->transfer = *xfer;
+
+        /* Save total transfer size. */
+        handle->transferSize = xfer->dataSize;
+
+        handle->state = kTransferDataState;
+
+        /* Wait until ready to complete. */
+        while ((!(base->S & kI2C_TransferCompleteFlag)) && (--timeout))
+        {
+        }
+
+        /* Failed to start the transfer. */
+        if (timeout == 0)
+        {
+            return kStatus_I2C_Timeout;
+        }
+        /* Clear all status before transfer. */
+        I2C_MasterClearStatusFlags(base, kClearFlags);
+
+        /* Change to send write address when it's a read operation with command. */
+        if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read))
+        {
+            direction = kI2C_Write;
+        }
+
+        /* If repeated start is requested, send repeated start. */
+        if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag)
+        {
+            result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction);
+        }
+        else /* For normal transfer, send start. */
+        {
+            result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction);
+        }
+
+        /* Send subaddress. */
+        if (handle->transfer.subaddressSize)
+        {
+            do
+            {
+                /* Wait until data transfer complete. */
+                while (!(base->S & kI2C_IntPendingFlag))
+                {
+                }
+
+                /* Clear interrupt pending flag. */
+                base->S = kI2C_IntPendingFlag;
+
+                handle->transfer.subaddressSize--;
+                base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize));
+
+                /* Check if there's transfer error. */
+                result = I2C_CheckAndClearError(base, base->S);
+
+                if (result)
+                {
+                    return result;
+                }
+
+            } while ((handle->transfer.subaddressSize > 0) && (result == kStatus_Success));
+
+            if (handle->transfer.direction == kI2C_Read)
+            {
+                /* Wait until data transfer complete. */
+                while (!(base->S & kI2C_IntPendingFlag))
+                {
+                }
+
+                /* Clear pending flag. */
+                base->S = kI2C_IntPendingFlag;
+
+                /* Send repeated start and slave address. */
+                result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read);
+            }
+        }
+
+        if (result)
+        {
+            return result;
+        }
+
+        /* Wait until data transfer complete. */
+        while (!(base->S & kI2C_IntPendingFlag))
+        {
+        }
+
+        /* Clear pending flag. */
+        base->S = kI2C_IntPendingFlag;
+
+        /* Check if there's transfer error. */
+        result = I2C_CheckAndClearError(base, base->S);
+    }
+
+    return result;
+}
+
+static void I2C_MasterTransferEDMAConfig(I2C_Type *base, i2c_master_edma_handle_t *handle)
+{
+    edma_transfer_config_t transfer_config;
+
+    if (handle->transfer.direction == kI2C_Read)
+    {
+        transfer_config.srcAddr = (uint32_t)I2C_GetDataRegAddr(base);
+        transfer_config.destAddr = (uint32_t)(handle->transfer.data);
+
+        /* Send stop if kI2C_TransferNoStop flag is not asserted. */
+        if (!(handle->transfer.flags & kI2C_TransferNoStopFlag))
+        {
+            transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1);
+        }
+        else
+        {
+            transfer_config.majorLoopCounts = handle->transfer.dataSize;
+        }
+
+        transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes;
+        transfer_config.srcOffset = 0;
+        transfer_config.destTransferSize = kEDMA_TransferSize1Bytes;
+        transfer_config.destOffset = 1;
+        transfer_config.minorLoopBytes = 1;
+    }
+    else
+    {
+        transfer_config.srcAddr = (uint32_t)(handle->transfer.data + 1);
+        transfer_config.destAddr = (uint32_t)I2C_GetDataRegAddr(base);
+        transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1);
+        transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes;
+        transfer_config.srcOffset = 1;
+        transfer_config.destTransferSize = kEDMA_TransferSize1Bytes;
+        transfer_config.destOffset = 0;
+        transfer_config.minorLoopBytes = 1;
+    }
+
+    EDMA_SubmitTransfer(handle->dmaHandle, &transfer_config);
+    EDMA_StartTransfer(handle->dmaHandle);
+}
+
+void I2C_MasterCreateEDMAHandle(I2C_Type *base,
+                                i2c_master_edma_handle_t *handle,
+                                i2c_master_edma_transfer_callback_t callback,
+                                void *userData,
+                                edma_handle_t *edmaHandle)
+{
+    assert(handle);
+    assert(edmaHandle);
+
+    uint32_t instance = I2C_GetInstance(base);
+
+    /* Zero handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Set the user callback and userData. */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    /* Set the base for the handle. */
+    base = base;
+
+    /* Set the handle for EDMA. */
+    handle->dmaHandle = edmaHandle;
+
+    s_edmaPrivateHandle[instance].base = base;
+    s_edmaPrivateHandle[instance].handle = handle;
+
+    EDMA_SetCallback(edmaHandle, (edma_callback)I2C_MasterTransferCallbackEDMA, &s_edmaPrivateHandle[instance]);
+}
+
+status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    assert(handle);
+    assert(xfer);
+
+    status_t result;
+    uint8_t tmpReg;
+    volatile uint8_t dummy = 0;
+
+    /* Add this to avoid build warning. */
+    dummy++;
+
+    /* Disable dma xfer. */
+    I2C_EnableDMA(base, false);
+
+    /* Send address and command buffer(if there is), until senddata phase or receive data phase. */
+    result = I2C_InitTransferStateMachineEDMA(base, handle, xfer);
+
+    if (result)
+    {
+        /* Send stop if received Nak. */
+        if (result == kStatus_I2C_Nak)
+        {
+            if (I2C_MasterStop(base) != kStatus_Success)
+            {
+                result = kStatus_I2C_Timeout;
+            }
+        }
+
+        /* Reset the state to idle state. */
+        handle->state = kIdleState;
+
+        return result;
+    }
+
+    /* Configure dma transfer. */
+    /* For i2c send, need to send 1 byte first to trigger the dma, for i2c read,
+    need to send stop before reading the last byte, so the dma transfer size should
+    be (xSize - 1). */
+    if (handle->transfer.dataSize > 1)
+    {
+        I2C_MasterTransferEDMAConfig(base, handle);
+        if (handle->transfer.direction == kI2C_Read)
+        {
+            /* Change direction for receive. */
+            base->C1 &= ~I2C_C1_TX_MASK;
+
+            /* Read dummy to release the bus. */
+            dummy = base->D;
+
+            /* Enabe dma transfer. */
+            I2C_EnableDMA(base, true);
+        }
+        else
+        {
+            /* Enabe dma transfer. */
+            I2C_EnableDMA(base, true);
+
+            /* Send the first data. */
+            base->D = *handle->transfer.data;
+        }
+    }
+    else /* If transfer size is 1, use polling method. */
+    {
+        if (handle->transfer.direction == kI2C_Read)
+        {
+            tmpReg = base->C1;
+
+            /* Change direction to Rx. */
+            tmpReg &= ~I2C_C1_TX_MASK;
+
+            /* Configure send NAK */
+            tmpReg |= I2C_C1_TXAK_MASK;
+
+            base->C1 = tmpReg;
+
+            /* Read dummy to release the bus. */
+            dummy = base->D;
+        }
+        else
+        {
+            base->D = *handle->transfer.data;
+        }
+
+        /* Wait until data transfer complete. */
+        while (!(base->S & kI2C_IntPendingFlag))
+        {
+        }
+
+        /* Clear pending flag. */
+        base->S = kI2C_IntPendingFlag;
+
+        /* Send stop if kI2C_TransferNoStop flag is not asserted. */
+        if (!(handle->transfer.flags & kI2C_TransferNoStopFlag))
+        {
+            result = I2C_MasterStop(base);
+        }
+
+        /* Read the last byte of data. */
+        if (handle->transfer.direction == kI2C_Read)
+        {
+            *handle->transfer.data = base->D;
+        }
+
+        /* Reset the state to idle. */
+        handle->state = kIdleState;
+    }
+
+    return result;
+}
+
+status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count)
+{
+    assert(handle->dmaHandle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (kIdleState != handle->state)
+    {
+        *count = (handle->transferSize - EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel));
+    }
+    else
+    {
+        *count = handle->transferSize;
+    }
+
+    return kStatus_Success;
+}
+
+void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle)
+{
+    EDMA_AbortTransfer(handle->dmaHandle);
+
+    /* Disable dma transfer. */
+    I2C_EnableDMA(base, false);
+
+    /* Reset the state to idle. */
+    handle->state = kIdleState;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c_edma.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c_edma.h
new file mode 100644
index 00000000000..c95d6adeeed
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_i2c_edma.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2C_DMA_H_
+#define _FSL_I2C_DMA_H_
+
+#include "fsl_i2c.h"
+#include "fsl_dmamux.h"
+#include "fsl_edma.h"
+
+/*!
+ * @addtogroup i2c_edma_driver
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief I2C master eDMA handle typedef. */
+typedef struct _i2c_master_edma_handle i2c_master_edma_handle_t;
+
+/*! @brief I2C master eDMA transfer callback typedef. */
+typedef void (*i2c_master_edma_transfer_callback_t)(I2C_Type *base,
+                                                    i2c_master_edma_handle_t *handle,
+                                                    status_t status,
+                                                    void *userData);
+
+/*! @brief I2C master eDMA transfer structure. */
+struct _i2c_master_edma_handle
+{
+    i2c_master_transfer_t transfer; /*!< I2C master transfer struct. */
+    size_t transferSize;            /*!< Total bytes to be transferred. */
+    uint8_t state;                  /*!< I2C master transfer status. */
+    edma_handle_t *dmaHandle;       /*!< The eDMA handler used. */
+    i2c_master_edma_transfer_callback_t
+        completionCallback; /*!< Callback function called after eDMA transfer finished. */
+    void *userData;         /*!< Callback parameter passed to callback function. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus. */
+
+/*!
+ * @name I2C Block eDMA Transfer Operation
+ * @{
+ */
+
+/*!
+ * @brief Init the I2C handle which is used in transcational functions.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_edma_handle_t structure.
+ * @param callback pointer to user callback function.
+ * @param userData user param passed to the callback function.
+ * @param edmaHandle eDMA handle pointer.
+ */
+void I2C_MasterCreateEDMAHandle(I2C_Type *base,
+                                i2c_master_edma_handle_t *handle,
+                                i2c_master_edma_transfer_callback_t callback,
+                                void *userData,
+                                edma_handle_t *edmaHandle);
+
+/*!
+ * @brief Performs a master eDMA non-blocking transfer on the I2C bus.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_edma_handle_t structure.
+ * @param xfer pointer to transfer structure of i2c_master_transfer_t.
+ * @retval kStatus_Success Sucessully complete the data transmission.
+ * @retval kStatus_I2C_Busy Previous transmission still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer.
+ */
+status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Get master transfer status during a eDMA non-blocking transfer.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_edma_handle_t structure.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ */
+status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Abort a master eDMA non-blocking transfer in a early time.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_edma_handle_t structure.
+ */
+void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle);
+
+/* @} */
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus. */
+/*@}*/
+#endif /*_FSL_I2C_DMA_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_intmux.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_intmux.c
new file mode 100644
index 00000000000..c6a55a153b9
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_intmux.c
@@ -0,0 +1,177 @@
+/*
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_intmux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get instance number for INTMUX.
+ *
+ * @param base INTMUX peripheral base address.
+ */
+static uint32_t INTMUX_GetInstance(INTMUX_Type *base);
+
+/*!
+ * @brief Handle INTMUX all channels IRQ.
+ *
+ * The handler reads the INTMUX channel's active vector register. This returns the offset
+ * from the start of the vector table to the vector for the INTMUX channel's highest priority
+ * pending source interrupt. After a check for spurious interrupts (an offset of 0), the
+ * function address at the vector offset is read and jumped to.
+ *
+ * @param instance INTMUX instance number.
+ * @param channel INTMUX channel number.
+ */
+static void INTMUX_CommonIRQHandler(uint32_t instance, uint32_t channel);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map INTMUX instance number to base pointer. */
+static INTMUX_Type *const s_intmuxBases[] = INTMUX_BASE_PTRS;
+
+/*! @brief Array to map INTMUX instance number to clock name. */
+static const clock_ip_name_t s_intmuxClockName[] = INTMUX_CLOCKS;
+
+/*! @brief Array to map INTMUX instance number to IRQ number. */
+static const IRQn_Type s_intmuxIRQNumber[] = INTMUX_IRQS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t INTMUX_GetInstance(INTMUX_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_INTMUX_COUNT; instance++)
+    {
+        if (s_intmuxBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_INTMUX_COUNT);
+
+    return instance;
+}
+
+static void INTMUX_CommonIRQHandler(uint32_t instance, uint32_t channel)
+{
+    INTMUX_Type *intmuxBase;
+    uint32_t pendingIrqOffset;
+
+    intmuxBase = s_intmuxBases[instance];
+    pendingIrqOffset = intmuxBase->CHANNEL[channel].CHn_VEC;
+    if (pendingIrqOffset)
+    {
+        uint32_t isr = *(uint32_t *)(SCB->VTOR + pendingIrqOffset);
+        ((void (*)(void))isr)();
+    }
+}
+
+void INTMUX_Init(INTMUX_Type *base)
+{
+    uint32_t channel;
+
+    /* Enable clock gate. */
+    CLOCK_EnableClock(s_intmuxClockName[INTMUX_GetInstance(base)]);
+    /* Reset all channels and enable NVIC vectors for all INTMUX channels. */
+    for (channel = 0; channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT; channel++)
+    {
+        INTMUX_ResetChannel(base, channel);
+        NVIC_EnableIRQ(s_intmuxIRQNumber[channel]);
+    }
+}
+
+void INTMUX_Deinit(INTMUX_Type *base)
+{
+    uint32_t channel;
+
+    /* Disable clock gate. */
+    CLOCK_DisableClock(s_intmuxClockName[INTMUX_GetInstance(base)]);
+    /* Disable NVIC vectors for all of the INTMUX channels. */
+    for (channel = 0; channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT; channel++)
+    {
+        NVIC_DisableIRQ(s_intmuxIRQNumber[channel]);
+    }
+}
+
+void INTMUX0_0_DriverIRQHandler(void)
+{
+    INTMUX_CommonIRQHandler(0, 0);
+}
+
+void INTMUX0_1_DriverIRQHandler(void)
+{
+    INTMUX_CommonIRQHandler(0, 1);
+}
+
+void INTMUX0_2_DriverIRQHandler(void)
+{
+    INTMUX_CommonIRQHandler(0, 2);
+}
+
+void INTMUX0_3_DriverIRQHandler(void)
+{
+    INTMUX_CommonIRQHandler(0, 3);
+}
+
+#if defined(INTMUX1)
+void INTMUX1_0_DriverIRQHandler(void)
+{
+    INTMUX_CommonIRQHandler(0, 0);
+}
+
+void INTMUX1_1_DriverIRQHandler(void)
+{
+    INTMUX_CommonIRQHandler(0, 1);
+}
+
+void INTMUX1_2_DriverIRQHandler(void)
+{
+    INTMUX_CommonIRQHandler(0, 2);
+}
+
+void INTMUX1_3_DriverIRQHandler(void)
+{
+    INTMUX_CommonIRQHandler(0, 3);
+}
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_intmux.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_intmux.h
new file mode 100644
index 00000000000..a272360de1a
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_intmux.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_INTMUX_H_
+#define _FSL_INTMUX_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup intmux
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*!< Version 2.0.0. */
+#define FSL_INTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief INTMUX channel logic mode. */
+typedef enum _intmux_channel_logic_mode
+{
+    kINTMUX_ChannelLogicOR = 0x0U, /*!< Logic OR all enabled interrupt inputs */
+    kINTMUX_ChannelLogicAND,       /*!< Logic AND all enabled interrupt inputs */
+} intmux_channel_logic_mode_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name Initialization and deinitialization */
+/*@{*/
+
+/*!
+ * @brief Initializes the INTMUX module.
+ *
+ * This function enables the clock gate for the specified INTMUX. It then resets all channels, so that no
+ * interrupt sources are routed and the logic mode is set to default of #kINTMUX_ChannelLogicOR.
+ * Finally, the NVIC vectors for all the INTMUX output channels are enabled.
+ *
+ * @param base INTMUX peripheral base address.
+ */
+void INTMUX_Init(INTMUX_Type *base);
+
+/*!
+ * @brief Deinitializes an INTMUX instance for operation.
+ *
+ * The clock gate for the specified INTMUX is disabled and the NVIC vectors for all channels are disabled.
+ *
+ * @param base INTMUX peripheral base address.
+ */
+void INTMUX_Deinit(INTMUX_Type *base);
+
+/*!
+ * @brief Resets an INTMUX channel.
+ *
+ * Sets all register values in the specified channel to their reset value. This function disables all interrupt
+ * sources for the channel.
+ *
+ * @param base INTMUX peripheral base address.
+ * @param channel The INTMUX channel number.
+ */
+static inline void INTMUX_ResetChannel(INTMUX_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
+
+    base->CHANNEL[channel].CHn_CSR |= INTMUX_CHn_CSR_RST_MASK;
+}
+
+/*!
+ * @brief Sets the logic mode for an INTMUX channel.
+ *
+ * INTMUX channels can be configured to use one of the two logic modes that control how pending interrupt sources
+ * on the channel trigger the output interrupt.
+ * - #kINTMUX_ChannelLogicOR means any source pending triggers the output interrupt.
+ * - #kINTMUX_ChannelLogicAND means all selected sources on the channel must be pending before the channel
+ *          output interrupt triggers.
+ *
+ * @param base INTMUX peripheral base address.
+ * @param channel The INTMUX channel number.
+ * @param logic The INTMUX channel logic mode.
+ */
+static inline void INTMUX_SetChannelMode(INTMUX_Type *base, uint32_t channel, intmux_channel_logic_mode_t logic)
+{
+    assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
+
+    base->CHANNEL[channel].CHn_CSR = INTMUX_CHn_CSR_AND(logic);
+}
+
+/*@}*/
+/*! @name Sources */
+/*@{*/
+
+/*!
+ * @brief Enables an interrupt source on an INTMUX channel.
+ *
+ * @param base INTMUX peripheral base address.
+ * @param channel Index of the INTMUX channel on which the specified interrupt is enabled.
+ * @param irq Interrupt to route to the specified INTMUX channel. The interrupt must be an INTMUX source.
+ */
+static inline void INTMUX_EnableInterrupt(INTMUX_Type *base, uint32_t channel, IRQn_Type irq)
+{
+    assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
+    assert(irq >= FSL_FEATURE_INTMUX_IRQ_START_INDEX);
+
+    base->CHANNEL[channel].CHn_IER_31_0 |= (1U << ((uint32_t)irq - FSL_FEATURE_INTMUX_IRQ_START_INDEX));
+}
+
+/*!
+ * @brief Disables an interrupt source on an INTMUX channel.
+ *
+ * @param base INTMUX peripheral base address.
+ * @param channel Index of the INTMUX channel on which the specified interrupt is disabled.
+ * @param irq Interrupt number. The interrupt must be an INTMUX source.
+ */
+static inline void INTMUX_DisableInterrupt(INTMUX_Type *base, uint32_t channel, IRQn_Type irq)
+{
+    assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
+    assert(irq >= FSL_FEATURE_INTMUX_IRQ_START_INDEX);
+
+    base->CHANNEL[channel].CHn_IER_31_0 &= ~(1U << ((uint32_t)irq - FSL_FEATURE_INTMUX_IRQ_START_INDEX));
+}
+
+/*@}*/
+/*! @name Status */
+/*@{*/
+
+/*!
+ * @brief Gets INTMUX pending interrupt sources for a specific channel.
+ *
+ * @param base INTMUX peripheral base address.
+ * @param channel The INTMUX channel number.
+ * @return The mask of pending interrupt bits. Bit[n] set means INTMUX source n is pending.
+ */
+static inline uint32_t INTMUX_GetChannelPendingSources(INTMUX_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
+
+    return base->CHANNEL[channel].CHn_IPR_31_0;
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_INTMUX_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_llwu.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_llwu.c
new file mode 100644
index 00000000000..c27b91e9f04
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_llwu.c
@@ -0,0 +1,404 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_llwu.h"
+
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN)
+void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode)
+{
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+    volatile uint32_t *regBase;
+    uint32_t regOffset;
+    uint32_t reg;
+
+    switch (pinIndex >> 4U)
+    {
+        case 0U:
+            regBase = &base->PE1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
+        case 1U:
+            regBase = &base->PE2;
+            break;
+#endif
+        default:
+            regBase = NULL;
+            break;
+    }
+#else
+    volatile uint8_t *regBase;
+    uint8_t regOffset;
+    uint8_t reg;
+    switch (pinIndex >> 2U)
+    {
+        case 0U:
+            regBase = &base->PE1;
+            break;
+        case 1U:
+            regBase = &base->PE2;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
+        case 2U:
+            regBase = &base->PE3;
+            break;
+#endif
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 12))
+        case 3U:
+            regBase = &base->PE4;
+            break;
+#endif
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
+        case 4U:
+            regBase = &base->PE5;
+            break;
+#endif
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 20))
+        case 5U:
+            regBase = &base->PE6;
+            break;
+#endif
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
+        case 6U:
+            regBase = &base->PE7;
+            break;
+#endif
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 28))
+        case 7U:
+            regBase = &base->PE8;
+            break;
+#endif
+        default:
+            regBase = NULL;
+            break;
+    }
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH == 32 */
+
+    if (regBase)
+    {
+        reg = *regBase;
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+        regOffset = ((pinIndex & 0x0FU) << 1U);
+#else
+        regOffset = ((pinIndex & 0x03U) << 1U);
+#endif
+        reg &= ~(0x3U << regOffset);
+        reg |= ((uint32_t)pinMode << regOffset);
+        *regBase = reg;
+    }
+}
+
+bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex)
+{
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+    return (bool)(base->PF & (1U << pinIndex));
+#else
+    volatile uint8_t *regBase;
+
+    switch (pinIndex >> 3U)
+    {
+#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF)
+        case 0U:
+            regBase = &base->PF1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
+        case 1U:
+            regBase = &base->PF2;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
+        case 2U:
+            regBase = &base->PF3;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
+        case 3U:
+            regBase = &base->PF4;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#else
+        case 0U:
+            regBase = &base->F1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
+        case 1U:
+            regBase = &base->F2;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
+        case 2U:
+            regBase = &base->F3;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
+        case 3U:
+            regBase = &base->F4;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#endif /* FSL_FEATURE_LLWU_HAS_PF */
+        default:
+            regBase = NULL;
+            break;
+    }
+
+    if (regBase)
+    {
+        return (bool)(*regBase & (1U << pinIndex % 8));
+    }
+    else
+    {
+        return false;
+    }
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+}
+
+void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex)
+{
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+    base->PF = (1U << pinIndex);
+#else
+    volatile uint8_t *regBase;
+    switch (pinIndex >> 3U)
+    {
+#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF)
+        case 0U:
+            regBase = &base->PF1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
+        case 1U:
+            regBase = &base->PF2;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
+        case 2U:
+            regBase = &base->PF3;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
+        case 3U:
+            regBase = &base->PF4;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#else
+        case 0U:
+            regBase = &base->F1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
+        case 1U:
+            regBase = &base->F2;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
+        case 2U:
+            regBase = &base->F3;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
+        case 3U:
+            regBase = &base->F4;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#endif /* FSL_FEATURE_LLWU_HAS_PF */
+        default:
+            regBase = NULL;
+            break;
+    }
+    if (regBase)
+    {
+        *regBase = (1U << pinIndex % 8U);
+    }
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+}
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER)
+void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode)
+{
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+    uint32_t reg;
+
+    reg = base->FILT;
+    reg &= ~((LLWU_FILT_FILTSEL1_MASK | LLWU_FILT_FILTE1_MASK) << (filterIndex * 8U - 1U));
+    reg |= (((filterMode.pinIndex << LLWU_FILT_FILTSEL1_SHIFT) | (filterMode.filterMode << LLWU_FILT_FILTE1_SHIFT)
+             /* Clear the Filter Detect Flag */
+             | LLWU_FILT_FILTF1_MASK)
+            << (filterIndex * 8U - 1U));
+    base->FILT = reg;
+#else
+    volatile uint8_t *regBase;
+    uint8_t reg;
+
+    switch (filterIndex)
+    {
+        case 1:
+            regBase = &base->FILT1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1))
+        case 2:
+            regBase = &base->FILT2;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2))
+        case 3:
+            regBase = &base->FILT3;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3))
+        case 4:
+            regBase = &base->FILT4;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+        default:
+            regBase = NULL;
+            break;
+    }
+
+    if (regBase)
+    {
+        reg = *regBase;
+        reg &= ~(LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTE_MASK);
+        reg |= ((uint32_t)filterMode.pinIndex << LLWU_FILT1_FILTSEL_SHIFT);
+        reg |= ((uint32_t)filterMode.filterMode << LLWU_FILT1_FILTE_SHIFT);
+        /* Clear the Filter Detect Flag */
+        reg |= LLWU_FILT1_FILTF_MASK;
+        *regBase = reg;
+    }
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+}
+
+bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex)
+{
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+    return (bool)(base->FILT & (1U << (filterIndex * 8U - 1)));
+#else
+    bool status = false;
+
+    switch (filterIndex)
+    {
+        case 1:
+            status = (base->FILT1 & LLWU_FILT1_FILTF_MASK);
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1))
+        case 2:
+            status = (base->FILT2 & LLWU_FILT2_FILTF_MASK);
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2))
+        case 3:
+            status = (base->FILT3 & LLWU_FILT3_FILTF_MASK);
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3))
+        case 4:
+            status = (base->FILT4 & LLWU_FILT4_FILTF_MASK);
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+        default:
+            break;
+    }
+
+    return status;
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+}
+
+void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex)
+{
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+    uint32_t reg;
+
+    reg = base->FILT;
+    switch (filterIndex)
+    {
+        case 1:
+            reg |= LLWU_FILT_FILTF1_MASK;
+            break;
+        case 2:
+            reg |= LLWU_FILT_FILTF2_MASK;
+            break;
+        case 3:
+            reg |= LLWU_FILT_FILTF3_MASK;
+            break;
+        case 4:
+            reg |= LLWU_FILT_FILTF4_MASK;
+            break;
+        default:
+            break;
+    }
+    base->FILT = reg;
+#else
+    volatile uint8_t *regBase;
+    uint8_t reg;
+
+    switch (filterIndex)
+    {
+        case 1:
+            regBase = &base->FILT1;
+            break;
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1))
+        case 2:
+            regBase = &base->FILT2;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2))
+        case 3:
+            regBase = &base->FILT3;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3))
+        case 4:
+            regBase = &base->FILT4;
+            break;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+        default:
+            regBase = NULL;
+            break;
+    }
+
+    if (regBase)
+    {
+        reg = *regBase;
+        reg |= LLWU_FILT1_FILTF_MASK;
+        *regBase = reg;
+    }
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+}
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE)
+void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode)
+{
+    uint8_t reg;
+
+    reg = base->RST;
+    reg &= ~(LLWU_RST_LLRSTE_MASK | LLWU_RST_RSTFILT_MASK);
+    reg |=
+        (((uint32_t)pinEnable << LLWU_RST_LLRSTE_SHIFT) | ((uint32_t)enableInLowLeakageMode << LLWU_RST_RSTFILT_SHIFT));
+    base->RST = reg;
+}
+#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_llwu.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_llwu.h
new file mode 100644
index 00000000000..1384d51cc57
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_llwu.h
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_LLWU_H_
+#define _FSL_LLWU_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup llwu */
+/*! @{ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LLWU driver version 2.0.1. */
+#define FSL_LLWU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*!
+ * @brief External input pin control modes
+ */
+typedef enum _llwu_external_pin_mode
+{
+    kLLWU_ExternalPinDisable = 0U,     /*!< Pin disabled as wakeup input.           */
+    kLLWU_ExternalPinRisingEdge = 1U,  /*!< Pin enabled with rising edge detection. */
+    kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with falling edge detection.*/
+    kLLWU_ExternalPinAnyEdge = 3U      /*!< Pin enabled with any change detection.  */
+} llwu_external_pin_mode_t;
+
+/*!
+ * @brief Digital filter control modes
+ */
+typedef enum _llwu_pin_filter_mode
+{
+    kLLWU_PinFilterDisable = 0U,     /*!< Filter disabled.               */
+    kLLWU_PinFilterRisingEdge = 1U,  /*!< Filter positive edge detection.*/
+    kLLWU_PinFilterFallingEdge = 2U, /*!< Filter negative edge detection.*/
+    kLLWU_PinFilterAnyEdge = 3U      /*!< Filter any edge detection.     */
+} llwu_pin_filter_mode_t;
+
+#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID)
+/*!
+ * @brief IP version ID definition.
+ */
+typedef struct _llwu_version_id
+{
+    uint16_t feature; /*!< Feature Specification Number. */
+    uint8_t minor;    /*!< Minor version number.         */
+    uint8_t major;    /*!< Major version number.         */
+} llwu_version_id_t;
+#endif /* FSL_FEATURE_LLWU_HAS_VERID */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM)
+/*!
+ * @brief IP parameter definition.
+ */
+typedef struct _llwu_param
+{
+    uint8_t filters; /*!< Number of pin filter.      */
+    uint8_t dmas;    /*!< Number of wakeup DMA.      */
+    uint8_t modules; /*!< Number of wakeup module.   */
+    uint8_t pins;    /*!< Number of wake up pin.     */
+} llwu_param_t;
+#endif /* FSL_FEATURE_LLWU_HAS_PARAM */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER)
+/*!
+ * @brief External input pin filter control structure
+ */
+typedef struct _llwu_external_pin_filter_mode
+{
+    uint32_t pinIndex;                 /*!< Pin number  */
+    llwu_pin_filter_mode_t filterMode; /*!< Filter mode */
+} llwu_external_pin_filter_mode_t;
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Low-Leakage Wakeup Unit Control APIs
+ * @{
+ */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID)
+/*!
+ * @brief Gets the LLWU version ID.
+ *
+ * This function gets the LLWU version ID, including major version number,
+ * minor version number, and feature specification number.
+ *
+ * @param base LLWU peripheral base address.
+ * @param versionId     Pointer to version ID structure.
+ */
+static inline void LLWU_GetVersionId(LLWU_Type *base, llwu_version_id_t *versionId)
+{
+    *((uint32_t *)versionId) = base->VERID;
+}
+#endif /* FSL_FEATURE_LLWU_HAS_VERID */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM)
+/*!
+ * @brief Gets the LLWU parameter.
+ *
+ * This function gets the LLWU parameter, including wakeup pin number, module
+ * number, DMA number, and pin filter number.
+ *
+ * @param base LLWU peripheral base address.
+ * @param param         Pointer to LLWU param structure.
+ */
+static inline void LLWU_GetParam(LLWU_Type *base, llwu_param_t *param)
+{
+    *((uint32_t *)param) = base->PARAM;
+}
+#endif /* FSL_FEATURE_LLWU_HAS_PARAM */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN)
+/*!
+ * @brief Sets the external input pin source mode.
+ *
+ * This function sets the external input pin source mode that is used
+ * as a wake up source.
+ *
+ * @param base LLWU peripheral base address.
+ * @param pinIndex pin index which to be enabled as external wakeup source, start from 1.
+ * @param pinMode pin configuration mode defined in llwu_external_pin_modes_t
+ */
+void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode);
+
+/*!
+ * @brief Gets the external wakeup source flag.
+ *
+ * This function checks the external pin flag to detect whether the MCU is
+ * woke up by the specific pin.
+ *
+ * @param base LLWU peripheral base address.
+ * @param pinIndex     pin index, start from 1.
+ * @return true if the specific pin is wake up source.
+ */
+bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex);
+
+/*!
+ * @brief Clears the external wakeup source flag.
+ *
+ * This function clears the external wakeup source flag for a specific pin.
+ *
+ * @param base LLWU peripheral base address.
+ * @param pinIndex pin index, start from 1.
+ */
+void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex);
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) && FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE)
+/*!
+ * @brief Enables/disables the internal module source.
+ *
+ * This function enables/disables the internal module source mode that is used
+ * as a wake up source.
+ *
+ * @param base LLWU peripheral base address.
+ * @param moduleIndex   module index which to be enabled as internal wakeup source, start from 1.
+ * @param enable        enable or disable setting
+ */
+static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable)
+{
+    if (enable)
+    {
+        base->ME |= 1U << moduleIndex;
+    }
+    else
+    {
+        base->ME &= ~(1U << moduleIndex);
+    }
+}
+
+/*!
+ * @brief Gets the external wakeup source flag.
+ *
+ * This function checks the external pin flag to detect whether the system is
+ * woke up by the specific pin.
+ *
+ * @param base LLWU peripheral base address.
+ * @param moduleIndex  module index, start from 1.
+ * @return true if the specific pin is wake up source.
+ */
+static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t moduleIndex)
+{
+#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF)
+#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
+    return (bool)(base->MF & (1U << moduleIndex));
+#else
+    return (bool)(base->MF5 & (1U << moduleIndex));
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+#else
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
+    return (bool)(base->F5 & (1U << moduleIndex));
+#else
+#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF)
+    return (bool)(base->PF3 & (1U << moduleIndex));
+#else
+    return (bool)(base->F3 & (1U << moduleIndex));
+#endif /* FSL_FEATURE_LLWU_HAS_PF */
+#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
+#endif /* FSL_FEATURE_LLWU_HAS_MF */
+}
+#endif /* FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) && FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG)
+/*!
+ * @brief Enables/disables the internal module DMA wakeup source.
+ *
+ * This function enables/disables the internal DMA that is used as a wake up source.
+ *
+ * @param base LLWU peripheral base address.
+ * @param moduleIndex   Internal module index which used as DMA request source, start from 1.
+ * @param enable        Enable or disable DMA request source
+ */
+static inline void LLWU_EnableInternalModuleDmaRequestWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable)
+{
+    if (enable)
+    {
+        base->DE |= 1U << moduleIndex;
+    }
+    else
+    {
+        base->DE &= ~(1U << moduleIndex);
+    }
+}
+#endif /* FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER)
+/*!
+ * @brief Sets the pin filter configuration.
+ *
+ * This function sets the pin filter configuration.
+ *
+ * @param base LLWU peripheral base address.
+ * @param filterIndex pin filter index which used to enable/disable the digital filter, start from 1.
+ * @param filterMode filter mode configuration
+ */
+void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode);
+
+/*!
+ * @brief Gets the pin filter configuration.
+ *
+ * This function gets the pin filter flag.
+ *
+ * @param base LLWU peripheral base address.
+ * @param filterIndex pin filter index, start from 1.
+ * @return true if the flag is a source of existing a low-leakage power mode.
+ */
+bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex);
+
+/*!
+ * @brief Clear the pin filter configuration.
+ *
+ * This function clear the pin filter flag.
+ *
+ * @param base LLWU peripheral base address.
+ * @param filterIndex pin filter index which to be clear the flag, start from 1.
+ */
+void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex);
+
+#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
+
+#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE)
+/*!
+ * @brief Sets the reset pin mode.
+ *
+ * This function sets how the reset pin is used as a low leakage mode exit source.
+ *
+ * @param pinEnable       Enable reset pin filter
+ * @param pinFilterEnable Specify whether pin filter is enabled in Low-Leakage power mode.
+ */
+void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode);
+#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+#endif /* _FSL_LLWU_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lptmr.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lptmr.c
new file mode 100644
index 00000000000..b3dcc89d55d
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lptmr.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_lptmr.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address to be used to gate or ungate the module clock
+ *
+ * @param base LPTMR peripheral base address
+ *
+ * @return The LPTMR instance
+ */
+static uint32_t LPTMR_GetInstance(LPTMR_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to LPTMR bases for each instance. */
+static LPTMR_Type *const s_lptmrBases[] = LPTMR_BASE_PTRS;
+
+/*! @brief Pointers to LPTMR clocks for each instance. */
+static const clock_ip_name_t s_lptmrClocks[] = LPTMR_CLOCKS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t LPTMR_GetInstance(LPTMR_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_LPTMR_COUNT; instance++)
+    {
+        if (s_lptmrBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_LPTMR_COUNT);
+
+    return instance;
+}
+
+void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config)
+{
+    assert(config);
+
+    /* Ungate the LPTMR clock*/
+    CLOCK_EnableClock(s_lptmrClocks[LPTMR_GetInstance(base)]);
+
+    /* Configure the timers operation mode and input pin setup */
+    base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) |
+                 LPTMR_CSR_TPP(config->pinPolarity) | LPTMR_CSR_TPS(config->pinSelect));
+
+    /* Configure the prescale value and clock source */
+    base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) |
+                 LPTMR_PSR_PCS(config->prescalerClockSource));
+}
+
+void LPTMR_Deinit(LPTMR_Type *base)
+{
+    /* Disable the LPTMR and reset the internal logic */
+    base->CSR &= ~LPTMR_CSR_TEN_MASK;
+    /* Gate the LPTMR clock*/
+    CLOCK_DisableClock(s_lptmrClocks[LPTMR_GetInstance(base)]);
+}
+
+void LPTMR_GetDefaultConfig(lptmr_config_t *config)
+{
+    assert(config);
+
+    /* Use time counter mode */
+    config->timerMode = kLPTMR_TimerModeTimeCounter;
+    /* Use input 0 as source in pulse counter mode */
+    config->pinSelect = kLPTMR_PinSelectInput_0;
+    /* Pulse input pin polarity is active-high */
+    config->pinPolarity = kLPTMR_PinPolarityActiveHigh;
+    /* Counter resets whenever TCF flag is set */
+    config->enableFreeRunning = false;
+    /* Bypass the prescaler */
+    config->bypassPrescaler = true;
+    /* LPTMR clock source */
+    config->prescalerClockSource = kLPTMR_PrescalerClock_1;
+    /* Divide the prescaler clock by 2 */
+    config->value = kLPTMR_Prescale_Glitch_0;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lptmr.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lptmr.h
new file mode 100644
index 00000000000..d022cbba6a8
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lptmr.h
@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_LPTMR_H_
+#define _FSL_LPTMR_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lptmr
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief LPTMR pin selection, used in pulse counter mode.*/
+typedef enum _lptmr_pin_select
+{
+    kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */
+    kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */
+    kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */
+    kLPTMR_PinSelectInput_3 = 0x3U  /*!< Pulse counter input 3 is selected */
+} lptmr_pin_select_t;
+
+/*! @brief LPTMR pin polarity, used in pulse counter mode.*/
+typedef enum _lptmr_pin_polarity
+{
+    kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */
+    kLPTMR_PinPolarityActiveLow = 0x1U   /*!< Pulse Counter input source is active-low */
+} lptmr_pin_polarity_t;
+
+/*! @brief LPTMR timer mode selection.*/
+typedef enum _lptmr_timer_mode
+{
+    kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */
+    kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */
+} lptmr_timer_mode_t;
+
+/*! @brief LPTMR prescaler/glitch filter values*/
+typedef enum _lptmr_prescaler_glitch_value
+{
+    kLPTMR_Prescale_Glitch_0 = 0x0U,  /*!< Prescaler divide 2, glitch filter does not support this setting */
+    kLPTMR_Prescale_Glitch_1 = 0x1U,  /*!< Prescaler divide 4, glitch filter 2 */
+    kLPTMR_Prescale_Glitch_2 = 0x2U,  /*!< Prescaler divide 8, glitch filter 4 */
+    kLPTMR_Prescale_Glitch_3 = 0x3U,  /*!< Prescaler divide 16, glitch filter 8 */
+    kLPTMR_Prescale_Glitch_4 = 0x4U,  /*!< Prescaler divide 32, glitch filter 16 */
+    kLPTMR_Prescale_Glitch_5 = 0x5U,  /*!< Prescaler divide 64, glitch filter 32 */
+    kLPTMR_Prescale_Glitch_6 = 0x6U,  /*!< Prescaler divide 128, glitch filter 64 */
+    kLPTMR_Prescale_Glitch_7 = 0x7U,  /*!< Prescaler divide 256, glitch filter 128 */
+    kLPTMR_Prescale_Glitch_8 = 0x8U,  /*!< Prescaler divide 512, glitch filter 256 */
+    kLPTMR_Prescale_Glitch_9 = 0x9U,  /*!< Prescaler divide 1024, glitch filter 512*/
+    kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */
+    kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */
+    kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */
+    kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */
+    kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */
+    kLPTMR_Prescale_Glitch_15 = 0xFU  /*!< Prescaler divide 65536, glitch filter 32768 */
+} lptmr_prescaler_glitch_value_t;
+
+/*!
+ * @brief LPTMR prescaler/glitch filter clock select.
+ * @note Clock connections are SoC-specific
+ */
+typedef enum _lptmr_prescaler_clock_select
+{
+    kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */
+    kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */
+    kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */
+    kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */
+} lptmr_prescaler_clock_select_t;
+
+/*! @brief List of LPTMR interrupts */
+typedef enum _lptmr_interrupt_enable
+{
+    kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */
+} lptmr_interrupt_enable_t;
+
+/*! @brief List of LPTMR status flags */
+typedef enum _lptmr_status_flags
+{
+    kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */
+} lptmr_status_flags_t;
+
+/*!
+ * @brief LPTMR config structure
+ *
+ * This structure holds the configuration settings for the LPTMR peripheral. To initialize this
+ * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The config struct can be made const so it resides in flash
+ */
+typedef struct _lptmr_config
+{
+    lptmr_timer_mode_t timerMode;     /*!< Time counter mode or pulse counter mode */
+    lptmr_pin_select_t pinSelect;     /*!< LPTMR pulse input pin select; used only in pulse counter mode */
+    lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */
+    bool enableFreeRunning;           /*!< true: enable free running, counter is reset on overflow
+                                           false: counter is reset when the compare flag is set */
+    bool bypassPrescaler;             /*!< true: bypass prescaler; false: use clock from prescaler */
+    lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */
+    lptmr_prescaler_glitch_value_t value;                /*!< Prescaler or glitch filter value */
+} lptmr_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungate the LPTMR clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application using the LPTMR driver.
+ *
+ * @param base   LPTMR peripheral base address
+ * @param config Pointer to user's LPTMR config structure.
+ */
+void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config);
+
+/*!
+ * @brief Gate the LPTMR clock
+ *
+ * @param base LPTMR peripheral base address
+ */
+void LPTMR_Deinit(LPTMR_Type *base);
+
+/*!
+ * @brief Fill in the LPTMR config struct with the default settings
+ *
+ * The default values are:
+ * @code
+ *    config->timerMode = kLPTMR_TimerModeTimeCounter;
+ *    config->pinSelect = kLPTMR_PinSelectInput_0;
+ *    config->pinPolarity = kLPTMR_PinPolarityActiveHigh;
+ *    config->enableFreeRunning = false;
+ *    config->bypassPrescaler = true;
+ *    config->prescalerClockSource = kLPTMR_PrescalerClock_1;
+ *    config->value = kLPTMR_Prescale_Glitch_0;
+ * @endcode
+ * @param config Pointer to user's LPTMR config structure.
+ */
+void LPTMR_GetDefaultConfig(lptmr_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected LPTMR interrupts.
+ *
+ * @param base LPTMR peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::lptmr_interrupt_enable_t
+ */
+static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg |= mask;
+    base->CSR = reg;
+}
+
+/*!
+ * @brief Disables the selected LPTMR interrupts.
+ *
+ * @param base LPTMR peripheral base address
+ * @param mask The interrupts to disable. This is a logical OR of members of the
+ *             enumeration ::lptmr_interrupt_enable_t
+ */
+static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg &= ~mask;
+    base->CSR = reg;
+}
+
+/*!
+ * @brief Gets the enabled LPTMR interrupts.
+ *
+ * @param base LPTMR peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::lptmr_interrupt_enable_t
+ */
+static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base)
+{
+    return (base->CSR & LPTMR_CSR_TIE_MASK);
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the LPTMR status flags
+ *
+ * @param base LPTMR peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::lptmr_status_flags_t
+ */
+static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base)
+{
+    return (base->CSR & LPTMR_CSR_TCF_MASK);
+}
+
+/*!
+ * @brief  Clears the LPTMR status flags
+ *
+ * @param base LPTMR peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::lptmr_status_flags_t
+ */
+static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)
+{
+    base->CSR |= mask;
+}
+
+/*! @}*/
+
+/*!
+ * @name Read and Write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of count.
+ *
+ * Timers counts from 0 till it equals the count value set here. The count value is written to
+ * the CMR register.
+ *
+ * @note
+ * 1. The TCF flag is set with the CNR equals the count provided here and then increments.
+ * 2. User can call the utility macros provided in fsl_common.h to convert to ticks
+ *
+ * @param base  LPTMR peripheral base address
+ * @param ticks Timer period in units of ticks
+ */
+static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint16_t ticks)
+{
+    base->CMR = ticks;
+}
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ *
+ * @param base LPTMR peripheral base address
+ *
+ * @return Current counter value in ticks
+ */
+static inline uint16_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)
+{
+    /* Must first write any value to the CNR. This synchronizes and registers the current value
+     * of the CNR into a temporary register which can then be read
+     */
+    base->CNR = 0U;
+    return (uint16_t)base->CNR;
+}
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the timer counting.
+ *
+ * After calling this function, the timer counts up to the CMR register value.
+ * Each time the timer reaches CMR value and then increments, it generates a
+ * trigger pulse and sets the timeout interrupt flag. An interrupt is also
+ * triggered if the timer interrupt is enabled.
+ *
+ * @param base LPTMR peripheral base address
+ */
+static inline void LPTMR_StartTimer(LPTMR_Type *base)
+{
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg |= LPTMR_CSR_TEN_MASK;
+    base->CSR = reg;
+}
+
+/*!
+ * @brief Stops the timer counting.
+ *
+ * This function stops the timer counting and resets the timer's counter register
+ *
+ * @param base LPTMR peripheral base address
+ */
+static inline void LPTMR_StopTimer(LPTMR_Type *base)
+{
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg &= ~LPTMR_CSR_TEN_MASK;
+    base->CSR = reg;
+}
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_LPTMR_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart.c
new file mode 100644
index 00000000000..9a7fd9cb3f5
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart.c
@@ -0,0 +1,1266 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_lpuart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* LPUART transfer state. */
+enum _lpuart_transfer_states
+{
+    kLPUART_TxIdle, /*!< TX idle. */
+    kLPUART_TxBusy, /*!< TX busy. */
+    kLPUART_RxIdle, /*!< RX idle. */
+    kLPUART_RxBusy  /*!< RX busy. */
+};
+
+/* Typedef for interrupt handler. */
+typedef void (*lpuart_isr_t)(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get the LPUART instance from peripheral base address.
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART instance.
+ */
+uint32_t LPUART_GetInstance(LPUART_Type *base);
+
+/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @userData handle LPUART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Check whether the RX ring buffer is full.
+ *
+ * @userData handle LPUART handle pointer.
+ * @retval true  RX ring buffer is full.
+ * @retval false RX ring buffer is not full.
+ */
+static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Write to TX register using non-blocking method.
+ *
+ * This function writes data to the TX register directly, upper layer must make
+ * sure the TX register is empty or TX FIFO has empty room before calling this function.
+ *
+ * @note This function does not check whether all the data has been sent out to bus,
+ * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is
+ * finished.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start addresss of the data to write.
+ * @param length Size of the buffer to be sent.
+ */
+static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Read RX register using non-blocking method.
+ *
+ * This function reads data from the TX register directly, upper layer must make
+ * sure the RX register is full or TX FIFO has data before calling this function.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start addresss of the buffer to store the received data.
+ * @param length Size of the buffer.
+ */
+static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of LPUART handle. */
+static lpuart_handle_t *s_lpuartHandle[FSL_FEATURE_SOC_LPUART_COUNT];
+/* Array of LPUART peripheral base address. */
+static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS;
+/* Array of LPUART IRQ number. */
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS;
+static const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS;
+#else
+static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS;
+#endif
+/* Array of LPUART clock name. */
+static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS;
+/* LPUART ISR for transactional APIs. */
+static lpuart_isr_t s_lpuartIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+uint32_t LPUART_GetInstance(LPUART_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_LPUART_COUNT; instance++)
+    {
+        if (s_lpuartBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_LPUART_COUNT);
+
+    return instance;
+}
+
+static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(handle);
+
+    size_t size;
+
+    if (handle->rxRingBufferTail > handle->rxRingBufferHead)
+    {
+        size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
+    }
+    else
+    {
+        size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
+    }
+
+    return size;
+}
+
+static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(handle);
+
+    bool full;
+
+    if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U))
+    {
+        full = true;
+    }
+    else
+    {
+        full = false;
+    }
+    return full;
+}
+
+static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
+{
+    assert(data);
+
+    size_t i;
+
+    /* The Non Blocking write data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+        base->DATA = data[i];
+    }
+}
+
+static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
+{
+    assert(data);
+
+    size_t i;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+#endif
+
+    /* The Non Blocking read data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        if (isSevenDataBits)
+        {
+            data[i] = (base->DATA & 0x7F);
+        }
+        else
+        {
+            data[i] = base->DATA;
+        }
+#else
+        data[i] = base->DATA;
+#endif
+    }
+}
+
+status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
+{
+    assert(config);
+    assert(config->baudRate_Bps);
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark);
+    assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
+#endif
+
+    uint32_t temp;
+    uint16_t sbr, sbrTemp;
+    uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
+
+    /* This LPUART instantiation uses a slightly different baud rate calculation
+     * The idea is to use the best OSR (over-sampling rate) possible
+     * Note, OSR is typically hard-set to 16 in other LPUART instantiations
+     * loop to find the best OSR value possible, one that generates minimum baudDiff
+     * iterate through the rest of the supported values of OSR */
+
+    baudDiff = config->baudRate_Bps;
+    osr = 0;
+    sbr = 0;
+    for (osrTemp = 4; osrTemp <= 32; osrTemp++)
+    {
+        /* calculate the temporary sbr value   */
+        sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp));
+        /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
+        if (sbrTemp == 0)
+        {
+            sbrTemp = 1;
+        }
+        /* Calculate the baud rate based on the temporary OSR and SBR values */
+        calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
+
+        tempDiff = calculatedBaud - config->baudRate_Bps;
+
+        /* Select the better value between srb and (sbr + 1) */
+        if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
+        {
+            tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
+            sbrTemp++;
+        }
+
+        if (tempDiff <= baudDiff)
+        {
+            baudDiff = tempDiff;
+            osr = osrTemp; /* update and store the best OSR value calculated */
+            sbr = sbrTemp; /* update store the best SBR value calculated */
+        }
+    }
+
+    /* Check to see if actual baud rate is within 3% of desired baud rate
+     * based on the best calculate OSR value */
+    if (baudDiff > ((config->baudRate_Bps / 100) * 3))
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_LPUART_BaudrateNotSupport;
+    }
+
+    /* Enable lpuart clock */
+    CLOCK_EnableClock(s_lpuartClock[LPUART_GetInstance(base)]);
+
+    /* Disable LPUART TX RX before setting. */
+    base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
+
+    temp = base->BAUD;
+
+    /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
+     * If so, then "BOTHEDGE" sampling must be turned on */
+    if ((osr > 3) && (osr < 8))
+    {
+        temp |= LPUART_BAUD_BOTHEDGE_MASK;
+    }
+
+    /* program the osr value (bit value is one less than actual value) */
+    temp &= ~LPUART_BAUD_OSR_MASK;
+    temp |= LPUART_BAUD_OSR(osr - 1);
+
+    /* write the sbr value to the BAUD registers */
+    temp &= ~LPUART_BAUD_SBR_MASK;
+    base->BAUD = temp | LPUART_BAUD_SBR(sbr);
+
+    /* Set bit count and parity mode. */
+    base->BAUD &= ~LPUART_BAUD_M10_MASK;
+
+    temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK);
+
+    temp |= (uint8_t)config->parityMode;
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    if (kLPUART_SevenDataBits == config->dataBitsCount)
+    {
+        if (kLPUART_ParityDisabled != config->parityMode)
+        {
+            temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */
+        }
+        else
+        {
+            temp |= LPUART_CTRL_M7_MASK;
+        }
+    }
+    else
+#endif
+    {
+        if (kLPUART_ParityDisabled != config->parityMode)
+        {
+            temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */
+        }
+    }
+
+    base->CTRL = temp;
+
+#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
+    /* set stop bit per char */
+    temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK;
+    base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount);
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    /* Set tx/rx WATER watermark */
+    base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark);
+
+    /* Enable tx/rx FIFO */
+    base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK);
+
+    /* Flush FIFO */
+    base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK);
+#endif
+
+    /* Clear all status flags */
+    temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+            LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
+
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    temp |= LPUART_STAT_LBKDIF_MASK;
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
+#endif
+
+    /* Set data bits order. */
+    if (config->isMsb)
+    {
+        temp |= LPUART_STAT_MSBF_MASK;
+    }
+    else
+    {
+        temp &= ~LPUART_STAT_MSBF_MASK;
+    }
+
+    base->STAT |= temp;
+
+    /* Enable TX/RX base on configure structure. */
+    temp = base->CTRL;
+    if (config->enableTx)
+    {
+        temp |= LPUART_CTRL_TE_MASK;
+    }
+
+    if (config->enableRx)
+    {
+        temp |= LPUART_CTRL_RE_MASK;
+    }
+
+    base->CTRL = temp;
+
+    return kStatus_Success;
+}
+void LPUART_Deinit(LPUART_Type *base)
+{
+    uint32_t temp;
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    /* Wait tx FIFO send out*/
+    while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT))
+    {
+    }
+#endif
+    /* Wait last char shoft out */
+    while (0 == (base->STAT & LPUART_STAT_TC_MASK))
+    {
+    }
+
+    /* Clear all status flags */
+    temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+            LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
+
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    temp |= LPUART_STAT_LBKDIF_MASK;
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
+#endif
+
+    base->STAT |= temp;
+
+    /* Disable the module. */
+    base->CTRL = 0;
+
+    /* Disable lpuart clock */
+    CLOCK_DisableClock(s_lpuartClock[LPUART_GetInstance(base)]);
+}
+
+void LPUART_GetDefaultConfig(lpuart_config_t *config)
+{
+    assert(config);
+
+    config->baudRate_Bps = 115200U;
+    config->parityMode = kLPUART_ParityDisabled;
+    config->dataBitsCount = kLPUART_EightDataBits;
+    config->isMsb = false;
+#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
+    config->stopBitCount = kLPUART_OneStopBit;
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    config->txFifoWatermark = 0;
+    config->rxFifoWatermark = 0;
+#endif
+    config->enableTx = false;
+    config->enableRx = false;
+}
+
+status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+    assert(baudRate_Bps);
+
+    uint32_t temp, oldCtrl;
+    uint16_t sbr, sbrTemp;
+    uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
+
+    /* This LPUART instantiation uses a slightly different baud rate calculation
+     * The idea is to use the best OSR (over-sampling rate) possible
+     * Note, OSR is typically hard-set to 16 in other LPUART instantiations
+     * loop to find the best OSR value possible, one that generates minimum baudDiff
+     * iterate through the rest of the supported values of OSR */
+
+    baudDiff = baudRate_Bps;
+    osr = 0;
+    sbr = 0;
+    for (osrTemp = 4; osrTemp <= 32; osrTemp++)
+    {
+        /* calculate the temporary sbr value   */
+        sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp));
+        /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
+        if (sbrTemp == 0)
+        {
+            sbrTemp = 1;
+        }
+        /* Calculate the baud rate based on the temporary OSR and SBR values */
+        calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
+
+        tempDiff = calculatedBaud - baudRate_Bps;
+
+        /* Select the better value between srb and (sbr + 1) */
+        if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
+        {
+            tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
+            sbrTemp++;
+        }
+
+        if (tempDiff <= baudDiff)
+        {
+            baudDiff = tempDiff;
+            osr = osrTemp; /* update and store the best OSR value calculated */
+            sbr = sbrTemp; /* update store the best SBR value calculated */
+        }
+    }
+
+    /* Check to see if actual baud rate is within 3% of desired baud rate
+     * based on the best calculate OSR value */
+    if (baudDiff < ((baudRate_Bps / 100) * 3))
+    {
+        /* Store CTRL before disable Tx and Rx */
+        oldCtrl = base->CTRL;
+
+        /* Disable LPUART TX RX before setting. */
+        base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
+
+        temp = base->BAUD;
+
+        /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
+         * If so, then "BOTHEDGE" sampling must be turned on */
+        if ((osr > 3) && (osr < 8))
+        {
+            temp |= LPUART_BAUD_BOTHEDGE_MASK;
+        }
+
+        /* program the osr value (bit value is one less than actual value) */
+        temp &= ~LPUART_BAUD_OSR_MASK;
+        temp |= LPUART_BAUD_OSR(osr - 1);
+
+        /* write the sbr value to the BAUD registers */
+        temp &= ~LPUART_BAUD_SBR_MASK;
+        base->BAUD = temp | LPUART_BAUD_SBR(sbr);
+
+        /* Restore CTRL. */
+        base->CTRL = oldCtrl;
+
+        return kStatus_Success;
+    }
+    else
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_LPUART_BaudrateNotSupport;
+    }
+}
+
+void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
+{
+    base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
+                 ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+#endif
+    mask &= 0xFFFFFF00U;
+    base->CTRL |= mask;
+}
+
+void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
+{
+    base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
+                 ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+#endif
+    mask &= 0xFFFFFF00U;
+    base->CTRL &= ~mask;
+}
+
+uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)
+{
+    uint32_t temp;
+    temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8;
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8;
+#endif
+    temp |= (base->CTRL & 0xFF0C000);
+
+    return temp;
+}
+
+uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
+{
+    uint32_t temp;
+    temp = base->STAT;
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    temp |= (base->FIFO &
+             (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >>
+            16;
+#endif
+    return temp;
+}
+
+status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
+{
+    uint32_t temp;
+    status_t status;
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    temp = (uint32_t)base->FIFO;
+    temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK));
+    temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
+    base->FIFO = temp;
+#endif
+    temp = (uint32_t)base->STAT;
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK));
+    temp |= mask & LPUART_STAT_LBKDIF_MASK;
+#endif
+    temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+                         LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK));
+    temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+                    LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK));
+    temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK);
+#endif
+    base->STAT = temp;
+    /* If some flags still pending. */
+    if (mask & LPUART_GetStatusFlags(base))
+    {
+        /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag,
+        kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag,
+        kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
+        kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */
+        status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */
+    }
+    else
+    {
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
+{
+    assert(data);
+
+    /* This API can only ensure that the data is written into the data buffer but can't
+    ensure all data in the data buffer are sent into the transmit shift buffer. */
+    while (length--)
+    {
+        while (!(base->STAT & LPUART_STAT_TDRE_MASK))
+        {
+        }
+        base->DATA = *(data++);
+    }
+}
+
+status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
+{
+    assert(data);
+
+    uint32_t statusFlag;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+#endif
+
+    while (length--)
+    {
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
+#else
+        while (!(base->STAT & LPUART_STAT_RDRF_MASK))
+#endif
+        {
+            statusFlag = LPUART_GetStatusFlags(base);
+
+            if (statusFlag & kLPUART_RxOverrunFlag)
+            {
+                LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag);
+                return kStatus_LPUART_RxHardwareOverrun;
+            }
+
+            if (statusFlag & kLPUART_NoiseErrorFlag)
+            {
+                LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag);
+                return kStatus_LPUART_NoiseError;
+            }
+
+            if (statusFlag & kLPUART_FramingErrorFlag)
+            {
+                LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag);
+                return kStatus_LPUART_FramingError;
+            }
+
+            if (statusFlag & kLPUART_ParityErrorFlag)
+            {
+                LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag);
+                return kStatus_LPUART_ParityError;
+            }
+        }
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        if (isSevenDataBits)
+        {
+            *(data++) = (base->DATA & 0x7F);
+        }
+        else
+        {
+            *(data++) = base->DATA;
+        }
+#else
+        *(data++) = base->DATA;
+#endif
+    }
+
+    return kStatus_Success;
+}
+
+void LPUART_TransferCreateHandle(LPUART_Type *base,
+                                 lpuart_handle_t *handle,
+                                 lpuart_transfer_callback_t callback,
+                                 void *userData)
+{
+    assert(handle);
+
+    uint32_t instance;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+#endif
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(lpuart_handle_t));
+
+    /* Set the TX/RX state. */
+    handle->rxState = kLPUART_RxIdle;
+    handle->txState = kLPUART_TxIdle;
+
+    /* Set the callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    /* Initial seven data bits flag */
+    handle->isSevenDataBits = isSevenDataBits;
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    /* Note:
+       Take care of the RX FIFO, RX interrupt request only assert when received bytes
+       equal or more than RX water mark, there is potential issue if RX water
+       mark larger than 1.
+       For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
+       5 bytes are received. the last byte will be saved in FIFO but not trigger
+       RX interrupt because the water mark is 2.
+     */
+    base->WATER &= (~LPUART_WATER_RXWATER_MASK);
+#endif
+
+    /* Get instance from peripheral base address. */
+    instance = LPUART_GetInstance(base);
+
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_lpuartHandle[instance] = handle;
+
+    s_lpuartIsr = LPUART_TransferHandleIRQ;
+
+/* Enable interrupt in NVIC. */
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+    EnableIRQ(s_lpuartRxIRQ[instance]);
+    EnableIRQ(s_lpuartTxIRQ[instance]);
+#else
+    EnableIRQ(s_lpuartIRQ[instance]);
+#endif
+}
+
+void LPUART_TransferStartRingBuffer(LPUART_Type *base,
+                                    lpuart_handle_t *handle,
+                                    uint8_t *ringBuffer,
+                                    size_t ringBufferSize)
+{
+    assert(handle);
+    assert(ringBuffer);
+
+    /* Setup the ring buffer address */
+    handle->rxRingBuffer = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+
+    /* Enable the interrupt to accept the data when user need the ring buffer. */
+    LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
+}
+
+void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(handle);
+
+    if (handle->rxState == kLPUART_RxIdle)
+    {
+        LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
+    }
+
+    handle->rxRingBuffer = NULL;
+    handle->rxRingBufferSize = 0U;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+}
+
+status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)
+{
+    assert(handle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    status_t status;
+
+    /* Return error if current TX busy. */
+    if (kLPUART_TxBusy == handle->txState)
+    {
+        status = kStatus_LPUART_TxBusy;
+    }
+    else
+    {
+        handle->txData = xfer->data;
+        handle->txDataSize = xfer->dataSize;
+        handle->txDataSizeAll = xfer->dataSize;
+        handle->txState = kLPUART_TxBusy;
+
+        /* Enable transmiter interrupt. */
+        LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(handle);
+
+    LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable);
+
+    handle->txDataSize = 0;
+    handle->txState = kLPUART_TxIdle;
+}
+
+status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
+{
+    assert(handle);
+    assert(count);
+
+    if (kLPUART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - handle->txDataSize;
+
+    return kStatus_Success;
+}
+
+status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
+                                           lpuart_handle_t *handle,
+                                           lpuart_transfer_t *xfer,
+                                           size_t *receivedBytes)
+{
+    assert(handle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    uint32_t i;
+    status_t status;
+    /* How many bytes to copy from ring buffer to user memory. */
+    size_t bytesToCopy = 0U;
+    /* How many bytes to receive. */
+    size_t bytesToReceive;
+    /* How many bytes currently have received. */
+    size_t bytesCurrentReceived;
+    uint32_t regPrimask = 0U;
+
+    /* How to get data:
+       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+          to lpuart handle, enable interrupt to store received data to xfer->data. When
+          all data received, trigger callback.
+       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+          If there are enough data in ring buffer, copy them to xfer->data and return.
+          If there are not enough data in ring buffer, copy all of them to xfer->data,
+          save the xfer->data remained empty space to lpuart handle, receive data
+          to this empty space and trigger callback when finished. */
+
+    if (kLPUART_RxBusy == handle->rxState)
+    {
+        status = kStatus_LPUART_RxBusy;
+    }
+    else
+    {
+        bytesToReceive = xfer->dataSize;
+        bytesCurrentReceived = 0;
+
+        /* If RX ring buffer is used. */
+        if (handle->rxRingBuffer)
+        {
+            /* Disable IRQ, protect ring buffer. */
+            regPrimask = DisableGlobalIRQ();
+
+            /* How many bytes in RX ring buffer currently. */
+            bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle);
+
+            if (bytesToCopy)
+            {
+                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+
+                bytesToReceive -= bytesToCopy;
+
+                /* Copy data from ring buffer to user memory. */
+                for (i = 0U; i < bytesToCopy; i++)
+                {
+                    xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+
+                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+                    if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+            }
+
+            /* If ring buffer does not have enough data, still need to read more data. */
+            if (bytesToReceive)
+            {
+                /* No data in ring buffer, save the request to LPUART handle. */
+                handle->rxData = xfer->data + bytesCurrentReceived;
+                handle->rxDataSize = bytesToReceive;
+                handle->rxDataSizeAll = bytesToReceive;
+                handle->rxState = kLPUART_RxBusy;
+            }
+            /* Enable IRQ if previously enabled. */
+            EnableGlobalIRQ(regPrimask);
+
+            /* Call user callback since all data are received. */
+            if (0 == bytesToReceive)
+            {
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
+                }
+            }
+        }
+        /* Ring buffer not used. */
+        else
+        {
+            handle->rxData = xfer->data + bytesCurrentReceived;
+            handle->rxDataSize = bytesToReceive;
+            handle->rxDataSizeAll = bytesToReceive;
+            handle->rxState = kLPUART_RxBusy;
+
+            /* Enable RX interrupt. */
+            LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
+        }
+
+        /* Return the how many bytes have read. */
+        if (receivedBytes)
+        {
+            *receivedBytes = bytesCurrentReceived;
+        }
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(handle);
+
+    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+    if (!handle->rxRingBuffer)
+    {
+        /* Disable RX interrupt. */
+        LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
+    }
+
+    handle->rxDataSize = 0U;
+    handle->rxState = kLPUART_RxIdle;
+}
+
+status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
+{
+    assert(handle);
+    assert(count);
+
+    if (kLPUART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+    return kStatus_Success;
+}
+
+void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(handle);
+
+    uint8_t count;
+    uint8_t tempCount;
+
+    /* If RX overrun. */
+    if (LPUART_STAT_OR_MASK & base->STAT)
+    {
+        /* Clear overrun flag, otherwise the RX does not work. */
+        base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
+
+        /* Trigger callback. */
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData);
+        }
+    }
+
+    /* Receive data register full */
+    if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL))
+    {
+/* Get the size that can be stored into buffer for this interrupt. */
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
+#else
+        count = 1;
+#endif
+
+        /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
+        while ((count) && (handle->rxDataSize))
+        {
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+            tempCount = MIN(handle->rxDataSize, count);
+#else
+            tempCount = 1;
+#endif
+
+            /* Using non block API to read the data from the registers. */
+            LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
+            handle->rxData += tempCount;
+            handle->rxDataSize -= tempCount;
+            count -= tempCount;
+
+            /* If all the data required for upper layer is ready, trigger callback. */
+            if (!handle->rxDataSize)
+            {
+                handle->rxState = kLPUART_RxIdle;
+
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
+                }
+            }
+        }
+
+        /* If use RX ring buffer, receive data to ring buffer. */
+        if (handle->rxRingBuffer)
+        {
+            while (count--)
+            {
+                /* If RX ring buffer is full, trigger callback to notify over run. */
+                if (LPUART_TransferIsRxRingBufferFull(base, handle))
+                {
+                    if (handle->callback)
+                    {
+                        handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData);
+                    }
+                }
+
+                /* If ring buffer is still full after callback function, the oldest data is overrided. */
+                if (LPUART_TransferIsRxRingBufferFull(base, handle))
+                {
+                    /* Increase handle->rxRingBufferTail to make room for new data. */
+                    if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+
+/* Read data. */
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+                if (handle->isSevenDataBits)
+                {
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = (base->DATA & 0x7F);
+                }
+                else
+                {
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
+                }
+#else
+                handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
+#endif
+
+                /* Increase handle->rxRingBufferHead. */
+                if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+                {
+                    handle->rxRingBufferHead = 0U;
+                }
+                else
+                {
+                    handle->rxRingBufferHead++;
+                }
+            }
+        }
+        /* If no receive requst pending, stop RX interrupt. */
+        else if (!handle->rxDataSize)
+        {
+            LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
+        }
+        else
+        {
+        }
+    }
+
+    /* Send data register empty and the interrupt is enabled. */
+    if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK))
+    {
+/* Get the bytes that available at this moment. */
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) -
+                ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
+#else
+        count = 1;
+#endif
+
+        while ((count) && (handle->txDataSize))
+        {
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+            tempCount = MIN(handle->txDataSize, count);
+#else
+            tempCount = 1;
+#endif
+
+            /* Using non block API to write the data to the registers. */
+            LPUART_WriteNonBlocking(base, handle->txData, tempCount);
+            handle->txData += tempCount;
+            handle->txDataSize -= tempCount;
+            count -= tempCount;
+
+            /* If all the data are written to data register, notify user with the callback, then TX finished. */
+            if (!handle->txDataSize)
+            {
+                handle->txState = kLPUART_TxIdle;
+
+                /* Disable TX register empty interrupt. */
+                base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK);
+
+                /* Trigger callback. */
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData);
+                }
+            }
+        }
+    }
+}
+
+void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    /* To be implemented by User. */
+}
+
+#if defined(LPUART0)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART0_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
+}
+void LPUART0_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
+}
+#else
+void LPUART0_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
+}
+#endif
+#endif
+
+#if defined(LPUART1)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART1_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
+}
+void LPUART1_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
+}
+#else
+void LPUART1_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
+}
+#endif
+#endif
+
+#if defined(LPUART2)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART2_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
+}
+void LPUART2_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
+}
+#else
+void LPUART2_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
+}
+#endif
+#endif
+
+#if defined(LPUART3)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART3_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
+}
+void LPUART3_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
+}
+#else
+void LPUART3_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
+}
+#endif
+#endif
+
+#if defined(LPUART4)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART4_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
+}
+void LPUART4_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
+}
+#else
+void LPUART4_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
+}
+#endif
+#endif
+
+#if defined(LPUART5)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART5_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
+}
+void LPUART5_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
+}
+#else
+void LPUART5_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
+}
+#endif
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart.h
new file mode 100644
index 00000000000..c538d723d38
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart.h
@@ -0,0 +1,792 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_LPUART_H_
+#define _FSL_LPUART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpuart_driver
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPUART driver version 2.2.1. */
+#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
+/*@}*/
+
+/*! @brief Error codes for the LPUART driver. */
+enum _lpuart_status
+{
+    kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0),              /*!< TX busy */
+    kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1),              /*!< RX busy */
+    kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2),              /*!< LPUART transmitter is idle. */
+    kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3),              /*!< LPUART receiver is idle. */
+    kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large  */
+    kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large  */
+    kStatus_LPUART_FlagCannotClearManually =
+        MAKE_STATUS(kStatusGroup_LPUART, 6),                    /*!< Some flag can't manually clear */
+    kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */
+    kStatus_LPUART_RxRingBufferOverrun =
+        MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */
+    kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */
+    kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10),       /*!< LPUART noise error. */
+    kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11),     /*!< LPUART framing error. */
+    kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12),      /*!< LPUART parity error. */
+    kStatus_LPUART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPUART, 13),                               /*!< Baudrate is not support in current clock source */
+};
+
+/*! @brief LPUART parity mode. */
+typedef enum _lpuart_parity_mode
+{
+    kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */
+    kLPUART_ParityEven = 0x2U,     /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+    kLPUART_ParityOdd = 0x3U,      /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
+} lpuart_parity_mode_t;
+
+/*! @brief LPUART data bits count. */
+typedef enum _lpuart_data_bits
+{
+    kLPUART_EightDataBits = 0x0U,     /*!< Eight data bit */
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    kLPUART_SevenDataBits = 0x1U,     /*!< Seven data bit */
+#endif
+} lpuart_data_bits_t;
+
+/*! @brief LPUART stop bit count. */
+typedef enum _lpuart_stop_bit_count
+{
+    kLPUART_OneStopBit = 0U, /*!< One stop bit */
+    kLPUART_TwoStopBit = 1U, /*!< Two stop bits */
+} lpuart_stop_bit_count_t;
+
+/*!
+ * @brief LPUART interrupt configuration structure, default settings all disabled.
+ *
+ * This structure contains the settings for all LPUART interrupt configurations.
+ */
+enum _lpuart_interrupt_enable
+{
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */
+#endif
+    kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */
+    kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK),        /*!< Transmit data register empty. */
+    kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */
+    kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK),         /*!< Receiver data register full. */
+    kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK),             /*!< Idle line. */
+    kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK),            /*!< Receiver Overrun. */
+    kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK),           /*!< Noise error flag. */
+    kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK),         /*!< Framing error flag. */
+    kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK),          /*!< Parity error flag. */
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8),  /*!< Transmit FIFO Overflow. */
+    kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */
+#endif
+};
+
+/*!
+ * @brief LPUART status flags.
+ *
+ * This provides constants for the LPUART status flags for use in the LPUART functions.
+ */
+enum _lpuart_flags
+{
+    kLPUART_TxDataRegEmptyFlag =
+        (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */
+    kLPUART_TransmissionCompleteFlag =
+        (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */
+    kLPUART_RxDataRegFullFlag =
+        (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */
+    kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */
+    kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK),  /*!< Receive Overrun, sets when new data is received before data is
+                                                       read from receive register */
+    kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit.  If any of these
+                                                       samples differ, noise flag sets */
+    kLPUART_FramingErrorFlag =
+        (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
+    kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char
+                                                         detected and LIN circuit enabled */
+#endif
+    kLPUART_RxActiveEdgeFlag =
+        (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */
+    kLPUART_RxActiveFlag =
+        (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/
+    kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+    kLPUART_NoiseErrorInRxDataRegFlag =
+        (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */
+    kLPUART_ParityErrorInRxDataRegFlag =
+        (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */
+    kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */
+    kLPUART_TxFifoOverflowFlag =
+        (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */
+    kLPUART_RxFifoUnderflowFlag =
+        (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */
+#endif
+};
+
+/*! @brief LPUART configure structure. */
+typedef struct _lpuart_config
+{
+    uint32_t baudRate_Bps;           /*!< LPUART baud rate  */
+    lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+    lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */
+    bool isMsb; /*!< Data bits order, LSB (default), MSB */
+#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
+    lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    uint8_t txFifoWatermark; /*!< TX FIFO watermark */
+    uint8_t rxFifoWatermark; /*!< RX FIFO watermark */
+#endif
+    bool enableTx; /*!< Enable TX */
+    bool enableRx; /*!< Enable RX */
+} lpuart_config_t;
+
+/*! @brief LPUART transfer structure. */
+typedef struct _lpuart_transfer
+{
+    uint8_t *data;   /*!< The buffer of data to be transfer.*/
+    size_t dataSize; /*!< The byte count to be transfer. */
+} lpuart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _lpuart_handle lpuart_handle_t;
+
+/*! @brief LPUART transfer callback function. */
+typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief LPUART handle structure. */
+struct _lpuart_handle
+{
+    uint8_t *volatile txData;   /*!< Address of remaining data to send. */
+    volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+    size_t txDataSizeAll;       /*!< Size of the data to send out. */
+    uint8_t *volatile rxData;   /*!< Address of remaining data to receive. */
+    volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+    size_t rxDataSizeAll;       /*!< Size of the data to receive. */
+
+    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
+    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+    lpuart_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                      /*!< LPUART callback function parameter.*/
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state. */
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    bool isSevenDataBits; /*!< Seven data bits flag. */
+#endif
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+* @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
+*
+* This function configures the LPUART module with  user-defined settings. Call the LPUART_GetDefaultConfig() function
+* to configure the configuration structure and get the default configuration.
+* The example below shows how to use this API to configure the LPUART.
+* @code
+*  lpuart_config_t lpuartConfig;
+*  lpuartConfig.baudRate_Bps = 115200U;
+*  lpuartConfig.parityMode = kLPUART_ParityDisabled;
+*  lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
+*  lpuartConfig.isMsb = false;
+*  lpuartConfig.stopBitCount = kLPUART_OneStopBit;
+*  lpuartConfig.txFifoWatermark = 0;
+*  lpuartConfig.rxFifoWatermark = 1;
+*  LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
+* @endcode
+*
+* @param base LPUART peripheral base address.
+* @param config Pointer to a user-defined configuration structure.
+* @param srcClock_Hz LPUART clock source frequency in HZ.
+* @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source.
+* @retval kStatus_Success LPUART initialize succeed
+*/
+status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a LPUART instance.
+ *
+ * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.
+ *
+ * @param base LPUART peripheral base address.
+ */
+void LPUART_Deinit(LPUART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the LPUART configuration structure to a default value. The default
+ * values are:
+ *   lpuartConfig->baudRate_Bps = 115200U;
+ *   lpuartConfig->parityMode = kLPUART_ParityDisabled;
+ *   lpuartConfig->dataBitsCount = kLPUART_EightDataBits;
+ *   lpuartConfig->isMsb = false;
+ *   lpuartConfig->stopBitCount = kLPUART_OneStopBit;
+ *   lpuartConfig->txFifoWatermark = 0;
+ *   lpuartConfig->rxFifoWatermark = 1;
+ *   lpuartConfig->enableTx = false;
+ *   lpuartConfig->enableRx = false;
+ *
+ * @param config Pointer to a configuration structure.
+ */
+void LPUART_GetDefaultConfig(lpuart_config_t *config);
+
+/*!
+ * @brief Sets the LPUART instance baudrate.
+ *
+ * This function configures the LPUART module baudrate. This function is used to update
+ * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.
+ * @code
+ *  LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param baudRate_Bps LPUART baudrate to be set.
+ * @param srcClock_Hz LPUART clock source frequency in HZ.
+ * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source.
+ * @retval kStatus_Success Set baudrate succeeded.
+ */
+status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets LPUART status flags.
+ *
+ * This function gets all LPUART status flags. The flags are returned as the logical
+ * OR value of the enumerators @ref _lpuart_flags. To check for a specific status,
+ * compare the return value with enumerators in the @ref _lpuart_flags.
+ * For example, to check whether the TX is empty:
+ * @code
+ *     if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags.
+ */
+uint32_t LPUART_GetStatusFlags(LPUART_Type *base);
+
+/*!
+ * @brief Clears status flags with a provided mask.
+ *
+ * This function clears LPUART status flags with a provided mask. Automatically cleared flags
+ * can't be cleared by this function.
+ * Flags that can only cleared or set by hardware are:
+ *    kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
+ *    kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
+ *    kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
+ * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
+ *
+ * @param base LPUART peripheral base address.
+ * @param mask the status flags to be cleared. The user can use the enumerators in the
+ *  _lpuart_status_flag_t to do the OR operation and get the mask.
+ * @return 0 succeed, others failed.
+ * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but
+ *         it is cleared automatically by hardware.
+ * @retval kStatus_Success Status in the mask are cleared.
+ */
+status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables LPUART interrupts according to a provided mask.
+ *
+ * This function enables the LPUART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable.
+ * This examples shows how to enable TX empty interrupt and RX full interrupt:
+ * @code
+ *     LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable.
+ */
+void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables  LPUART interrupts according to a provided mask.
+ *
+ * This function disables the LPUART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * @code
+ *     LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable.
+ */
+void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets enabled LPUART interrupts.
+ *
+ * This function gets the enabled LPUART interrupts. The enabled interrupts are returned
+ * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check
+ * a specific interrupt enable status, compare the return value with enumerators
+ * in @ref _lpuart_interrupt_enable.
+ * For example, to check whether the TX empty interrupt is enabled:
+ * @code
+ *     uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);
+ *
+ *     if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable.
+ */
+uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base);
+
+#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE
+/*!
+ * @brief Gets the LPUART data register address.
+ *
+ * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART data register addresses which are used both by the transmitter and receiver.
+ */
+static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base)
+{
+    return (uint32_t) & (base->DATA);
+}
+
+/*!
+ * @brief Enables or disables the LPUART transmitter DMA request.
+ *
+ * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->BAUD |= LPUART_BAUD_TDMAE_MASK;
+        base->CTRL |= LPUART_CTRL_TIE_MASK;
+    }
+    else
+    {
+        base->BAUD &= ~LPUART_BAUD_TDMAE_MASK;
+        base->CTRL &= ~LPUART_CTRL_TIE_MASK;
+    }
+}
+
+/*!
+ * @brief Enables or disables the LPUART receiver DMA.
+ *
+ * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->BAUD |= LPUART_BAUD_RDMAE_MASK;
+        base->CTRL |= LPUART_CTRL_RIE_MASK;
+    }
+    else
+    {
+        base->BAUD &= ~LPUART_BAUD_RDMAE_MASK;
+        base->CTRL &= ~LPUART_CTRL_RIE_MASK;
+    }
+}
+
+/* @} */
+#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Enables or disables the LPUART transmitter.
+ *
+ * This function enables or disables the LPUART transmitter.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= LPUART_CTRL_TE_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~LPUART_CTRL_TE_MASK;
+    }
+}
+
+/*!
+ * @brief Enables or disables the LPUART receiver.
+ *
+ * This function enables or disables the LPUART receiver.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= LPUART_CTRL_RE_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~LPUART_CTRL_RE_MASK;
+    }
+}
+
+/*!
+ * @brief Writes to the transmitter register.
+ *
+ * This function writes data to the transmitter register directly. The upper layer must
+ * ensure that the TX register is empty or that the TX FIFO has room before calling this function.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Data write to the TX register.
+ */
+static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)
+{
+    base->DATA = data;
+}
+
+/*!
+ * @brief Reads the RX register.
+ *
+ * This function reads data from the receiver register directly. The upper layer must
+ * ensure that the RX register is full or that the RX FIFO has data before calling this function.
+ *
+ * @param base LPUART peripheral base address.
+ * @return Data read from data register.
+ */
+static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
+{
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits = ((ctrl & LPUART_CTRL_M7_MASK) ||
+            ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+
+    if (isSevenDataBits)
+    {
+        return (base->DATA & 0x7F);
+    }
+    else
+    {
+        return base->DATA;
+    }
+#else
+    return base->DATA;
+#endif
+}
+
+/*!
+ * @brief Writes to transmitter register using a blocking method.
+ *
+ * This function polls the transmitter register, waits for the register to be empty or  for TX FIFO to have
+ * room and then writes data to the transmitter buffer.
+ *
+ * @note This function does not check whether all data has been sent out to the bus.
+ * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is
+ * finished.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ */
+void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+* @brief Reads the RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register full or RX FIFO
+ * has data then reads data from the TX register.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
+ * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
+ * @retval kStatus_LPUART_FramingError Framing error happened while receiving data.
+ * @retval kStatus_LPUART_ParityError Parity error happened while receiving data.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the LPUART handle.
+ *
+ * This function initializes the LPUART handle, which can be used for other LPUART
+ * transactional APIs. Usually, for a specified LPUART instance,
+ * call this API once to get the initialized handle.
+ *
+ * The LPUART driver supports the "background" receiving, which means that user can set up
+ * an RX ring buffer optionally. Data received is stored into the ring buffer even when the
+ * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ * The ring buffer is disabled if passing NULL as @p ringBuffer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param callback Callback function.
+ * @param userData User data.
+ */
+void LPUART_TransferCreateHandle(LPUART_Type *base,
+                                 lpuart_handle_t *handle,
+                                 lpuart_transfer_callback_t callback,
+                                 void *userData);
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function send data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data written to the transmitter register. When
+ * all data is written to the TX register in the ISR, the LPUART driver calls the callback
+ * function and passes the @ref kStatus_LPUART_TxIdle as status parameter.
+ *
+ * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written
+ * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
+ * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param xfer LPUART transfer structure, see #lpuart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received is stored into the ring buffer even when
+ * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize size of the ring buffer.
+ */
+void LPUART_TransferStartRingBuffer(LPUART_Type *base,
+                                    lpuart_handle_t *handle,
+                                    uint8_t *ringBuffer,
+                                    size_t ringBufferSize);
+
+/*!
+ * @brief Abort the background transfer and uninstall the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been written to LPUART TX register.
+ *
+ * This function gets the number of bytes that have been written to LPUART TX
+ * register by interrupt method.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using the interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function
+ * which returns without waiting to ensure that all data are received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough for read, the receive
+ * request is saved by the LPUART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the LPUART driver notifies the upper layer
+ * through a callback function and passes a status parameter @ref kStatus_UART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
+ * The 5 bytes are copied to xfer->data, which returns with the
+ * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
+ * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param xfer LPUART transfer structure, see #uart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into the transmit queue.
+ * @retval kStatus_LPUART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
+                                           lpuart_handle_t *handle,
+                                           lpuart_transfer_t *xfer,
+                                           size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief LPUART IRQ handle function.
+ *
+ * This function handles the LPUART transmit and receive IRQ request.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief LPUART Error IRQ handle function.
+ *
+ * This function handles the LPUART error IRQ request.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_LPUART_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart_edma.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart_edma.c
new file mode 100644
index 00000000000..0ba8df3335b
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart_edma.c
@@ -0,0 +1,331 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_lpuart_edma.h"
+#include "fsl_dmamux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! Structure definition for lpuart_edma_private_handle_t. The structure is private. */
+typedef struct _lpuart_edma_private_handle
+{
+    LPUART_Type *base;
+    lpuart_edma_handle_t *handle;
+} lpuart_edma_private_handle_t;
+
+/* LPUART EDMA transfer handle. */
+enum _lpuart_edma_tansfer_states
+{
+    kLPUART_TxIdle, /* TX idle. */
+    kLPUART_TxBusy, /* TX busy. */
+    kLPUART_RxIdle, /* RX idle. */
+    kLPUART_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! Private handle only used for internally. */
+static lpuart_edma_private_handle_t s_edmaPrivateHandle[FSL_FEATURE_SOC_LPUART_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief LPUART EDMA send finished callback function.
+ *
+ * This function is called when LPUART EDMA send finished. It disables the LPUART
+ * TX EDMA request and sends @ref kStatus_LPUART_TxIdle to LPUART callback.
+ *
+ * @param handle The EDMA handle.
+ * @param param Callback function parameter.
+ */
+static void LPUART_SendEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
+
+/*!
+ * @brief LPUART EDMA receive finished callback function.
+ *
+ * This function is called when LPUART EDMA receive finished. It disables the LPUART
+ * RX EDMA request and sends @ref kStatus_LPUART_RxIdle to LPUART callback.
+ *
+ * @param handle The EDMA handle.
+ * @param param Callback function parameter.
+ */
+static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
+
+/*!
+ * @brief Get the LPUART instance from peripheral base address.
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART instance.
+ */
+extern uint32_t LPUART_GetInstance(LPUART_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void LPUART_SendEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
+{
+    assert(param);
+
+    lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param;
+
+    /* Avoid the warning for unused variables. */
+    handle = handle;
+    tcds = tcds;
+
+    if (transferDone)
+    {
+        LPUART_TransferAbortSendEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle);
+
+        if (lpuartPrivateHandle->handle->callback)
+        {
+            lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle,
+                                                  kStatus_LPUART_TxIdle, lpuartPrivateHandle->handle->userData);
+        }
+    }
+}
+
+static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
+{
+    assert(param);
+
+    lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param;
+
+    /* Avoid warning for unused parameters. */
+    handle = handle;
+    tcds = tcds;
+
+    if (transferDone)
+    {
+        /* Disable transfer. */
+        LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle);
+
+        if (lpuartPrivateHandle->handle->callback)
+        {
+            lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle,
+                                                  kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData);
+        }
+    }
+}
+
+void LPUART_TransferCreateHandleEDMA(LPUART_Type *base,
+                                     lpuart_edma_handle_t *handle,
+                                     lpuart_edma_transfer_callback_t callback,
+                                     void *userData,
+                                     edma_handle_t *txEdmaHandle,
+                                     edma_handle_t *rxEdmaHandle)
+{
+    assert(handle);
+
+    uint32_t instance = LPUART_GetInstance(base);
+
+    s_edmaPrivateHandle[instance].base = base;
+    s_edmaPrivateHandle[instance].handle = handle;
+
+    memset(handle, 0, sizeof(*handle));
+
+    handle->rxState = kLPUART_RxIdle;
+    handle->txState = kLPUART_TxIdle;
+
+    handle->rxEdmaHandle = rxEdmaHandle;
+    handle->txEdmaHandle = txEdmaHandle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    /* Note:
+       Take care of the RX FIFO, EDMA request only assert when received bytes
+       equal or more than RX water mark, there is potential issue if RX water
+       mark larger than 1.
+       For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
+       5 bytes are received. the last byte will be saved in FIFO but not trigger
+       EDMA transfer because the water mark is 2.
+     */
+    if (rxEdmaHandle)
+    {
+        base->WATER &= (~LPUART_WATER_RXWATER_MASK);
+    }
+#endif
+
+    /* Configure TX. */
+    if (txEdmaHandle)
+    {
+        EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_edmaPrivateHandle[instance]);
+    }
+
+    /* Configure RX. */
+    if (rxEdmaHandle)
+    {
+        EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]);
+    }
+}
+
+status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)
+{
+    assert(handle);
+    assert(handle->txEdmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    edma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous TX not finished. */
+    if (kLPUART_TxBusy == handle->txState)
+    {
+        status = kStatus_LPUART_TxBusy;
+    }
+    else
+    {
+        handle->txState = kLPUART_TxBusy;
+        handle->txDataSizeAll = xfer->dataSize;
+
+        /* Prepare transfer. */
+        EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)LPUART_GetDataRegisterAddress(base),
+                             sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral);
+
+        /* Submit transfer. */
+        EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig);
+        EDMA_StartTransfer(handle->txEdmaHandle);
+
+        /* Enable LPUART TX EDMA. */
+        LPUART_EnableTxDMA(base, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)
+{
+    assert(handle);
+    assert(handle->rxEdmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    edma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous RX not finished. */
+    if (kLPUART_RxBusy == handle->rxState)
+    {
+        status = kStatus_LPUART_RxBusy;
+    }
+    else
+    {
+        handle->rxState = kLPUART_RxBusy;
+        handle->rxDataSizeAll = xfer->dataSize;
+
+        /* Prepare transfer. */
+        EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data,
+                             sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory);
+
+        /* Submit transfer. */
+        EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig);
+        EDMA_StartTransfer(handle->rxEdmaHandle);
+
+        /* Enable LPUART RX EDMA. */
+        LPUART_EnableRxDMA(base, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)
+{
+    assert(handle);
+    assert(handle->txEdmaHandle);
+
+    /* Disable LPUART TX EDMA. */
+    LPUART_EnableTxDMA(base, false);
+
+    /* Stop transfer. */
+    EDMA_AbortTransfer(handle->txEdmaHandle);
+
+    handle->txState = kLPUART_TxIdle;
+}
+
+void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)
+{
+    assert(handle);
+    assert(handle->rxEdmaHandle);
+
+    /* Disable LPUART RX EDMA. */
+    LPUART_EnableRxDMA(base, false);
+
+    /* Stop transfer. */
+    EDMA_AbortTransfer(handle->rxEdmaHandle);
+
+    handle->rxState = kLPUART_RxIdle;
+}
+
+status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)
+{
+    assert(handle);
+    assert(handle->rxEdmaHandle);
+    assert(count);
+
+    if (kLPUART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - EDMA_GetRemainingBytes(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel);
+
+    return kStatus_Success;
+}
+
+status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)
+{
+    assert(handle);
+    assert(handle->txEdmaHandle);
+    assert(count);
+
+    if (kLPUART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - EDMA_GetRemainingBytes(handle->txEdmaHandle->base, handle->txEdmaHandle->channel);
+
+    return kStatus_Success;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart_edma.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart_edma.h
new file mode 100644
index 00000000000..99baf90e146
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_lpuart_edma.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_LPUART_EDMA_H_
+#define _FSL_LPUART_EDMA_H_
+
+#include "fsl_lpuart.h"
+#include "fsl_dmamux.h"
+#include "fsl_edma.h"
+
+/*!
+ * @addtogroup lpuart_edma_driver
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Forward declaration of the handle typedef. */
+typedef struct _lpuart_edma_handle lpuart_edma_handle_t;
+
+/*! @brief LPUART transfer callback function. */
+typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base,
+                                                lpuart_edma_handle_t *handle,
+                                                status_t status,
+                                                void *userData);
+
+/*!
+* @brief LPUART eDMA handle
+*/
+struct _lpuart_edma_handle
+{
+    lpuart_edma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                           /*!< LPUART callback function parameter.*/
+    size_t rxDataSizeAll;                     /*!< Size of the data to receive. */
+    size_t txDataSizeAll;                     /*!< Size of the data to send out. */
+
+    edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */
+    edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the LPUART handle which is used in transactional functions.
+ * @param base LPUART peripheral base address.
+ * @param handle Pointer to lpuart_edma_handle_t structure.
+ * @param callback Callback function.
+ * @param userData User data.
+ * @param txEdmaHandle User requested DMA handle for TX DMA transfer.
+ * @param rxEdmaHandle User requested DMA handle for RX DMA transfer.
+ */
+void LPUART_TransferCreateHandleEDMA(LPUART_Type *base,
+                             lpuart_edma_handle_t *handle,
+                             lpuart_edma_transfer_callback_t callback,
+                             void *userData,
+                             edma_handle_t *txEdmaHandle,
+                             edma_handle_t *rxEdmaHandle);
+
+/*!
+ * @brief Sends data using eDMA.
+ *
+ * This function sends data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data is sent, the send callback function is called.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_LPUART_TxBusy Previous transfer on going.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using eDMA.
+ *
+ * This function receives data using eDMA. This is non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle Pointer to lpuart_edma_handle_t structure.
+ * @param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t.
+ * @retval kStatus_Success if succeed, others fail.
+ * @retval kStatus_LPUART_RxBusy Previous transfer ongoing.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the sent data using eDMA.
+ *
+ * This function aborts the sent data using eDMA.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle Pointer to lpuart_edma_handle_t structure.
+ */
+void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle);
+
+/*!
+ * @brief Aborts the received data using eDMA.
+ *
+ * This function aborts the received data using eDMA.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle Pointer to lpuart_edma_handle_t structure.
+ */
+void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been written to LPUART TX register.
+ *
+ * This function gets the number of bytes that have been written to LPUART TX
+ * register by DMA.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_LPUART_EDMA_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc.c
new file mode 100644
index 00000000000..37bd746f750
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc.c
@@ -0,0 +1,4292 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_ltc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! Full word representing the actual bit values for the LTC mode register. */
+typedef uint32_t ltc_mode_t;
+
+#define LTC_FIFO_SZ_MAX_DOWN_ALGN (0xff0u)
+#define LTC_MD_ALG_AES (0x10U)        /*!< Bit field value for LTC_MD_ALG: AES */
+#define LTC_MD_ALG_DES (0x20U)        /*!< Bit field value for LTC_MD_ALG: DES */
+#define LTC_MD_ALG_TRIPLE_DES (0x21U) /*!< Bit field value for LTC_MD_ALG: 3DES */
+#define LTC_MD_ALG_SHA1 (0x41U)       /*!< Bit field value for LTC_MD_ALG: SHA-1 */
+#define LTC_MD_ALG_SHA224 (0x42U)     /*!< Bit field value for LTC_MD_ALG: SHA-224 */
+#define LTC_MD_ALG_SHA256 (0x43U)     /*!< Bit field value for LTC_MD_ALG: SHA-256 */
+#define LTC_MDPK_ALG_PKHA (0x80U)     /*!< Bit field value for LTC_MDPK_ALG: PKHA */
+#define LTC_MD_ENC_DECRYPT (0U)       /*!< Bit field value for LTC_MD_ENC: Decrypt. */
+#define LTC_MD_ENC_ENCRYPT (0x1U)     /*!< Bit field value for LTC_MD_ENC: Encrypt. */
+#define LTC_MD_AS_UPDATE (0U)         /*!< Bit field value for LTC_MD_AS: Update */
+#define LTC_MD_AS_INITIALIZE (0x1U)   /*!< Bit field value for LTC_MD_AS: Initialize */
+#define LTC_MD_AS_FINALIZE (0x2U)     /*!< Bit field value for LTC_MD_AS: Finalize */
+#define LTC_MD_AS_INIT_FINAL (0x3U)   /*!< Bit field value for LTC_MD_AS: Initialize/Finalize */
+
+#define LTC_AES_GCM_TYPE_AAD 55
+#define LTC_AES_GCM_TYPE_IV 0
+
+#define LTC_CCM_TAG_IDX 8 /*! For CCM encryption, the encrypted final MAC is written to the context word 8-11 */
+#define LTC_GCM_TAG_IDX 0 /*! For GCM encryption, the encrypted final MAC is written to the context word 0-3 */
+
+enum _ltc_md_dk_bit_shift
+{
+    kLTC_ModeRegBitShiftDK = 12U,
+};
+
+typedef enum _ltc_algorithm
+{
+#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA
+    kLTC_AlgorithmPKHA = LTC_MDPK_ALG_PKHA << LTC_MD_ALG_SHIFT,
+#endif /* FSL_FEATURE_LTC_HAS_PKHA */
+    kLTC_AlgorithmAES = LTC_MD_ALG_AES << LTC_MD_ALG_SHIFT,
+#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES
+    kLTC_AlgorithmDES = LTC_MD_ALG_DES << LTC_MD_ALG_SHIFT,
+    kLTC_Algorithm3DES = LTC_MD_ALG_TRIPLE_DES << LTC_MD_ALG_SHIFT,
+#endif /* FSL_FEATURE_LTC_HAS_DES */
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+    kLTC_AlgorithmSHA1 = LTC_MD_ALG_SHA1 << LTC_MD_ALG_SHIFT,
+    kLTC_AlgorithmSHA224 = LTC_MD_ALG_SHA224 << LTC_MD_ALG_SHIFT,
+    kLTC_AlgorithmSHA256 = LTC_MD_ALG_SHA256 << LTC_MD_ALG_SHIFT,
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+} ltc_algorithm_t;
+
+typedef enum _ltc_mode_symmetric_alg
+{
+    kLTC_ModeCTR = 0x00U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeCBC = 0x10U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeECB = 0x20U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeCFB = 0x30U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeOFB = 0x40U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeCMAC = 0x60U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeXCBCMAC = 0x70U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeCCM = 0x80U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeGCM = 0x90U << LTC_MD_AAI_SHIFT,
+} ltc_mode_symmetric_alg_t;
+
+typedef enum _ltc_mode_encrypt
+{
+    kLTC_ModeDecrypt = LTC_MD_ENC_DECRYPT << LTC_MD_ENC_SHIFT,
+    kLTC_ModeEncrypt = LTC_MD_ENC_ENCRYPT << LTC_MD_ENC_SHIFT,
+} ltc_mode_encrypt_t;
+
+typedef enum _ltc_mode_algorithm_state
+{
+    kLTC_ModeUpdate = LTC_MD_AS_UPDATE << LTC_MD_AS_SHIFT,
+    kLTC_ModeInit = LTC_MD_AS_INITIALIZE << LTC_MD_AS_SHIFT,
+    kLTC_ModeFinalize = LTC_MD_AS_FINALIZE << LTC_MD_AS_SHIFT,
+    kLTC_ModeInitFinal = LTC_MD_AS_INIT_FINAL << LTC_MD_AS_SHIFT
+} ltc_mode_algorithm_state_t;
+
+/*! @brief LTC status flags */
+enum _ltc_status_flag
+{
+    kLTC_StatusAesBusy = 1U << LTC_STA_AB_SHIFT,
+#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES
+    kLTC_StatusDesBusy = 1U << LTC_STA_DB_SHIFT,
+#endif /* FSL_FEATURE_LTC_HAS_DES */
+#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA
+    kLTC_StatusPkhaBusy = 1U << LTC_STA_PB_SHIFT,
+#endif /* FSL_FEATURE_LTC_HAS_PKHA */
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+    kLTC_StatusMdhaBusy = 1U << LTC_STA_MB_SHIFT,
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+    kLTC_StatusDoneIsr = 1U << LTC_STA_DI_SHIFT,
+    kLTC_StatusErrorIsr = 1U << LTC_STA_EI_SHIFT,
+#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA
+    kLTC_StatusPublicKeyPrime = 1U << LTC_STA_PKP_SHIFT,
+    kLTC_StatusPublicKeyOpOne = 1U << LTC_STA_PKO_SHIFT,
+    kLTC_StatusPublicKeyOpZero = 1U << LTC_STA_PKZ_SHIFT,
+#endif /* FSL_FEATURE_LTC_HAS_PKHA */
+    kLTC_StatusAll = LTC_STA_AB_MASK |
+#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES
+                     LTC_STA_DB_MASK |
+#endif /* FSL_FEATURE_LTC_HAS_DES */
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+                     LTC_STA_MB_MASK |
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+                     LTC_STA_DI_MASK | LTC_STA_EI_MASK
+#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA
+                     |
+                     LTC_STA_PB_MASK | LTC_STA_PKP_MASK | LTC_STA_PKO_MASK | LTC_STA_PKZ_MASK
+#endif /* FSL_FEATURE_LTC_HAS_PKHA */
+};
+
+/*! @brief LTC clear register */
+typedef enum _ltc_clear_written
+{
+    kLTC_ClearMode = 1U << LTC_CW_CM_SHIFT,
+    kLTC_ClearDataSize = 1U << LTC_CW_CDS_SHIFT,
+    kLTC_ClearIcvSize = 1U << LTC_CW_CICV_SHIFT,
+    kLTC_ClearContext = 1U << LTC_CW_CCR_SHIFT,
+    kLTC_ClearKey = 1U << LTC_CW_CKR_SHIFT,
+#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA
+    kLTC_ClearPkhaSizeA = 1U << LTC_CW_CPKA_SHIFT,
+    kLTC_ClearPkhaSizeB = 1U << LTC_CW_CPKB_SHIFT,
+    kLTC_ClearPkhaSizeN = 1U << LTC_CW_CPKN_SHIFT,
+    kLTC_ClearPkhaSizeE = 1U << LTC_CW_CPKE_SHIFT,
+    kLTC_ClearAllSize = (int)kLTC_ClearPkhaSizeA | kLTC_ClearPkhaSizeB | kLTC_ClearPkhaSizeN | kLTC_ClearPkhaSizeE,
+#endif /* FSL_FEATURE_LTC_HAS_PKHA */
+    kLTC_ClearOutputFifo = 1U << LTC_CW_COF_SHIFT,
+    kLTC_ClearInputFifo = (int)(1U << LTC_CW_CIF_SHIFT),
+    kLTC_ClearAll = (int)(LTC_CW_CM_MASK | LTC_CW_CDS_MASK | LTC_CW_CICV_MASK | LTC_CW_CCR_MASK | LTC_CW_CKR_MASK |
+#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA
+                          LTC_CW_CPKA_MASK | LTC_CW_CPKB_MASK | LTC_CW_CPKN_MASK | LTC_CW_CPKE_MASK |
+#endif /* FSL_FEATURE_LTC_HAS_PKHA */
+                          LTC_CW_COF_MASK | LTC_CW_CIF_MASK)
+} ltc_clear_written_t;
+
+enum _ltc_ctrl_swap
+{
+    kLTC_CtrlSwapAll =
+        LTC_CTL_IFS_MASK | LTC_CTL_OFS_MASK | LTC_CTL_KIS_MASK | LTC_CTL_KOS_MASK | LTC_CTL_CIS_MASK | LTC_CTL_COS_MASK,
+};
+
+/*! @brief Type used in GCM and CCM modes.
+
+    Content of a block is established via individual bytes and moved to LTC
+   IFIFO by moving 32-bit words.
+*/
+typedef union _ltc_xcm_block_t
+{
+    uint32_t w[4]; /*!< LTC context register is 16 bytes written as four 32-bit words */
+    uint8_t b[16]; /*!< 16 octets block for CCM B0 and CTR0 and for GCM */
+} ltc_xcm_block_t;
+
+#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA
+
+/*! @brief PKHA functions - arithmetic, copy/clear memory. */
+typedef enum _ltc_pkha_func_t
+{
+    kLTC_PKHA_ClearMem = 1U,
+    kLTC_PKHA_ArithModAdd = 2U,         /*!< (A + B) mod N */
+    kLTC_PKHA_ArithModSub1 = 3U,        /*!< (A - B) mod N */
+    kLTC_PKHA_ArithModSub2 = 4U,        /*!< (B - A) mod N */
+    kLTC_PKHA_ArithModMul = 5U,         /*!< (A x B) mod N */
+    kLTC_PKHA_ArithModExp = 6U,         /*!< (A^E) mod N */
+    kLTC_PKHA_ArithModRed = 7U,         /*!< (A) mod N */
+    kLTC_PKHA_ArithModInv = 8U,         /*!< (A^-1) mod N */
+    kLTC_PKHA_ArithEccAdd = 9U,         /*!< (P1 + P2) */
+    kLTC_PKHA_ArithEccDouble = 10U,     /*!< (P2 + P2) */
+    kLTC_PKHA_ArithEccMul = 11U,        /*!< (E x P1) */
+    kLTC_PKHA_ArithModR2 = 12U,         /*!< (R^2 mod N) */
+    kLTC_PKHA_ArithGcd = 14U,           /*!< GCD (A, N) */
+    kLTC_PKHA_ArithPrimalityTest = 15U, /*!< Miller-Rabin */
+    kLTC_PKHA_CopyMemSizeN = 16U,
+    kLTC_PKHA_CopyMemSizeSrc = 17U,
+} ltc_pkha_func_t;
+
+/*! @brief Register areas for PKHA clear memory operations. */
+typedef enum _ltc_pkha_reg_area
+{
+    kLTC_PKHA_RegA = 8U,
+    kLTC_PKHA_RegB = 4U,
+    kLTC_PKHA_RegE = 2U,
+    kLTC_PKHA_RegN = 1U,
+    kLTC_PKHA_RegAll = kLTC_PKHA_RegA | kLTC_PKHA_RegB | kLTC_PKHA_RegE | kLTC_PKHA_RegN,
+} ltc_pkha_reg_area_t;
+
+/*! @brief Quadrant areas for 2048-bit registers for PKHA copy memory
+ * operations. */
+typedef enum _ltc_pkha_quad_area_t
+{
+    kLTC_PKHA_Quad0 = 0U,
+    kLTC_PKHA_Quad1 = 1U,
+    kLTC_PKHA_Quad2 = 2U,
+    kLTC_PKHA_Quad3 = 3U,
+} ltc_pkha_quad_area_t;
+
+/*! @brief User-supplied (R^2 mod N) input or LTC should calculate. */
+typedef enum _ltc_pkha_r2_t
+{
+    kLTC_PKHA_CalcR2 = 0U, /*!< Calculate (R^2 mod N) */
+    kLTC_PKHA_InputR2 = 1U /*!< (R^2 mod N) supplied as input */
+} ltc_pkha_r2_t;
+
+/*! @brief LTC PKHA parameters */
+typedef struct _ltc_pkha_mode_params_t
+{
+    ltc_pkha_func_t func;
+    ltc_pkha_f2m_t arithType;
+    ltc_pkha_montgomery_form_t montFormIn;
+    ltc_pkha_montgomery_form_t montFormOut;
+    ltc_pkha_reg_area_t srcReg;
+    ltc_pkha_quad_area_t srcQuad;
+    ltc_pkha_reg_area_t dstReg;
+    ltc_pkha_quad_area_t dstQuad;
+    ltc_pkha_timing_t equalTime;
+    ltc_pkha_r2_t r2modn;
+} ltc_pkha_mode_params_t;
+
+#endif /* FSL_FEATURE_LTC_HAS_PKHA */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA
+static status_t ltc_pkha_clear_regabne(LTC_Type *base, bool A, bool B, bool N, bool E);
+#endif /* FSL_FEATURE_LTC_HAS_PKHA */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*******************************************************************************
+ * LTC Common code static
+ ******************************************************************************/
+/*!
+ * @brief Tests the correct key size.
+ *
+ * This function tests the correct key size.
+ * @param keySize Input key length in bytes.
+ * @return True if the key length is supported, false if not.
+ */
+bool ltc_check_key_size(const uint32_t keySize)
+{
+    return ((keySize == 16u)
+#if defined(FSL_FEATURE_LTC_HAS_AES192) && FSL_FEATURE_LTC_HAS_AES192
+            || ((keySize == 24u))
+#endif /* FSL_FEATURE_LTC_HAS_AES192 */
+#if defined(FSL_FEATURE_LTC_HAS_AES256) && FSL_FEATURE_LTC_HAS_AES256
+            || ((keySize == 32u))
+#endif /* FSL_FEATURE_LTC_HAS_AES256 */
+                );
+}
+
+/*! @brief LTC driver wait mechanism. */
+status_t ltc_wait(LTC_Type *base)
+{
+    status_t status;
+
+    bool error = false;
+    bool done = false;
+
+    /* Wait for 'done' or 'error' flag. */
+    while ((!error) && (!done))
+    {
+        uint32_t temp32 = base->STA;
+        error = temp32 & LTC_STA_EI_MASK;
+        done = temp32 & LTC_STA_DI_MASK;
+    }
+
+    if (error)
+    {
+        base->COM = LTC_COM_ALL_MASK; /* Reset all engine to clear the error flag */
+        status = kStatus_Fail;
+    }
+    else /* 'done' */
+    {
+        status = kStatus_Success;
+
+        base->CW = kLTC_ClearDataSize;
+        /* Clear 'done' interrupt status.  This also clears the mode register. */
+        base->STA = kLTC_StatusDoneIsr;
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Clears the LTC module.
+ * This function can be used to clear all sensitive data from theLTC module, such as private keys. It is called
+ * internally by the LTC driver in case of an error or operation complete.
+ * @param base LTC peripheral base address
+ * @param pkha Include LTC PKHA register clear. If there is no PKHA, the argument is ignored.
+ */
+void ltc_clear_all(LTC_Type *base, bool addPKHA)
+{
+    base->CW = (uint32_t)kLTC_ClearAll;
+#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA
+    if (addPKHA)
+    {
+        ltc_pkha_clear_regabne(base, true, true, true, true);
+    }
+#endif /* FSL_FEATURE_LTC_HAS_PKHA */
+}
+
+void ltc_memcpy(void *dst, const void *src, size_t size)
+{
+#if defined(__cplusplus)
+    register uint8_t *to = (uint8_t *)dst;
+    register const uint8_t *from = (const uint8_t *)src;
+#else
+    register uint8_t *to = dst;
+    register const uint8_t *from = src;
+#endif
+    while (size)
+    {
+        *to = *from;
+        size--;
+        to++;
+        from++;
+    }
+}
+
+/*!
+ * @brief Reads an unaligned word.
+ *
+ * This function creates a 32-bit word from an input array of four bytes.
+ *
+ * @param src Input array of four bytes. The array can start at any address in memory.
+ * @return 32-bit unsigned int created from the input byte array.
+ */
+static inline uint32_t ltc_get_word_from_unaligned(const uint8_t *srcAddr)
+{
+#if (!(defined(__CORTEX_M)) || (defined(__CORTEX_M) && (__CORTEX_M == 0)))
+    register const uint8_t *src = srcAddr;
+    /* Cortex M0 does not support misaligned loads */
+    if ((uint32_t)src & 0x3u)
+    {
+        union _align_bytes_t
+        {
+            uint32_t word;
+            uint8_t byte[sizeof(uint32_t)];
+        } my_bytes;
+
+        my_bytes.byte[0] = *src;
+        my_bytes.byte[1] = *(src + 1);
+        my_bytes.byte[2] = *(src + 2);
+        my_bytes.byte[3] = *(src + 3);
+        return my_bytes.word;
+    }
+    else
+    {
+        /* addr aligned to 0-modulo-4 so it is safe to type cast */
+        return *((const uint32_t *)src);
+    }
+#elif defined(__CC_ARM)
+    /* -O3 optimization in Keil 5.15 and 5.16a uses LDM instruction here (LDM r4!, {r0})
+     *    which is wrong, because srcAddr might be unaligned.
+     *    LDM on unaligned address causes hard-fault. in contrary,
+     *    LDR supports unaligned address on Cortex M4 */
+    register uint32_t retVal;
+    __asm
+    {
+        LDR retVal, [srcAddr]
+    }
+    return retVal;
+#else
+    return *((const uint32_t *)srcAddr);
+#endif
+}
+
+/*!
+ * @brief Converts a 32-bit word into a byte array.
+ *
+ * This function creates an output array of four bytes from an input 32-bit word.
+ *
+ * @param srcWord Input 32-bit unsigned integer.
+ * @param dst Output array of four bytes. The array can start at any address in memory.
+ */
+static inline void ltc_set_unaligned_from_word(uint32_t srcWord, uint8_t *dstAddr)
+{
+#if (!(defined(__CORTEX_M)) || (defined(__CORTEX_M) && (__CORTEX_M == 0)))
+    register uint8_t *dst = dstAddr;
+    /* Cortex M0 does not support misaligned stores */
+    if ((uint32_t)dst & 0x3u)
+    {
+        *dst++ = (srcWord & 0x000000FFU);
+        *dst++ = (srcWord & 0x0000FF00U) >> 8;
+        *dst++ = (srcWord & 0x00FF0000U) >> 16;
+        *dst++ = (srcWord & 0xFF000000U) >> 24;
+    }
+    else
+    {
+        *((uint32_t *)dstAddr) = srcWord; /* addr aligned to 0-modulo-4 so it is safe to type cast */
+    }
+#elif defined(__CC_ARM)
+    __asm
+    {
+        STR srcWord, [dstAddr]
+    }
+    return;
+#else
+    *((uint32_t *)dstAddr) = srcWord;
+#endif
+}
+
+/*!
+ * @brief Sets the LTC keys.
+ *
+ * This function writes the LTC keys into the key register.  The keys should
+ * be written before the key size.
+ *
+ * @param base LTC peripheral base address
+ * @param key Key
+ * @param keySize Number of bytes for all keys to be loaded (maximum 32, must be a
+ *                multiple of 4).
+ * @returns Key set status
+ */
+static status_t ltc_set_key(LTC_Type *base, const uint8_t *key, uint8_t keySize)
+{
+    int32_t i;
+
+    for (i = 0; i < (keySize / 4); i++)
+    {
+        base->KEY[i] = ltc_get_word_from_unaligned(key + i * sizeof(uint32_t));
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Gets the LTC keys.
+ *
+ * This function retrieves the LTC keys from the key register.
+ *
+ * @param base LTC peripheral base address
+ * @param key Array of data to store keys
+ * @param keySize Number of bytes of keys to retrieve
+ * @returns Key set status
+ */
+static status_t ltc_get_key(LTC_Type *base, uint8_t *key, uint8_t keySize)
+{
+    int32_t i;
+
+    for (i = 0; i < (keySize / 4); i++)
+    {
+        ltc_set_unaligned_from_word(base->KEY[i], key + i * sizeof(uint32_t));
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Writes the LTC context register;
+ *
+ * The LTC context register is a 512 bit (64 byte) register that holds
+ * internal context for the crypto engine.  The meaning varies based on the
+ * algorithm and operating state being used.  This register is written by the
+ * driver/application to load state such as IV, counter, and so on. Then, it is
+ * updated by the internal crypto engine as needed.
+ *
+ * @param base LTC peripheral base address
+ * @param data Data to write
+ * @param dataSize Size of data to write in bytes
+ * @param startIndex Starting word (4-byte) index into the 16-word register.
+ * @return Status of write
+ */
+status_t ltc_set_context(LTC_Type *base, const uint8_t *data, uint8_t dataSize, uint8_t startIndex)
+{
+    int32_t i;
+    int32_t j;
+    int32_t szLeft;
+
+    /* Context register is 16 words in size (64 bytes).  Ensure we are only
+     * writing a valid amount of data. */
+    if (startIndex + (dataSize / 4) >= 16)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    j = 0;
+    szLeft = dataSize % 4;
+    for (i = startIndex; i < (startIndex + dataSize / 4); i++)
+    {
+        base->CTX[i] = ltc_get_word_from_unaligned(data + j);
+        j += sizeof(uint32_t);
+    }
+
+    if (szLeft)
+    {
+        uint32_t context_data = {0};
+        ltc_memcpy(&context_data, data + j, szLeft);
+        base->CTX[i] = context_data;
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Reads the LTC context register.
+ *
+ * The LTC context register is a 512 bit (64 byte) register that holds
+ * internal context for the crypto engine.  The meaning varies based on the
+ * algorithm and operating state being used.  This register is written by the
+ * driver/application to load state such as IV, counter, and so on. Then, it is
+ * updated by the internal crypto engine as needed.
+ *
+ * @param base LTC peripheral base address
+ * @param data Destination of read data
+ * @param dataSize Size of data to read in bytes
+ * @param startIndex Starting word (4-byte) index into the 16-word register.
+ * @return Status of read
+ */
+status_t ltc_get_context(LTC_Type *base, uint8_t *dest, uint8_t dataSize, uint8_t startIndex)
+{
+    int32_t i;
+    int32_t j;
+    int32_t szLeft;
+    uint32_t rdCtx;
+
+    /* Context register is 16 words in size (64 bytes).  Ensure we are only
+     * writing a valid amount of data. */
+    if (startIndex + (dataSize / 4) >= 16)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    j = 0;
+    szLeft = dataSize % 4;
+    for (i = startIndex; i < (startIndex + dataSize / 4); i++)
+    {
+        ltc_set_unaligned_from_word(base->CTX[i], dest + j);
+        j += sizeof(uint32_t);
+    }
+
+    if (szLeft)
+    {
+        rdCtx = 0;
+        rdCtx = base->CTX[i];
+        ltc_memcpy(dest + j, &rdCtx, szLeft);
+    }
+    return kStatus_Success;
+}
+
+static status_t ltc_symmetric_alg_state(LTC_Type *base,
+                                        const uint8_t *key,
+                                        uint8_t keySize,
+                                        ltc_algorithm_t alg,
+                                        ltc_mode_symmetric_alg_t mode,
+                                        ltc_mode_encrypt_t enc,
+                                        ltc_mode_algorithm_state_t as)
+{
+    ltc_mode_t modeReg;
+
+    /* Clear internal register states. */
+    base->CW = (uint32_t)kLTC_ClearAll;
+
+    /* Set byte swap on for several registers we will be reading and writing
+     * user data to/from. */
+    base->CTL |= kLTC_CtrlSwapAll;
+
+    /* Write the key in place. */
+    ltc_set_key(base, key, keySize);
+
+    /* Write the key size.  This must be done after writing the key, and this
+     * action locks the ability to modify the key registers. */
+    base->KS = keySize;
+
+    /* Clear the 'done' interrupt. */
+    base->STA = kLTC_StatusDoneIsr;
+
+    /* Set the proper block and algorithm mode. */
+    modeReg = (uint32_t)alg | (uint32_t)enc | (uint32_t)as | (uint32_t)mode;
+
+    /* Write the mode register to the hardware. */
+    base->MD = modeReg;
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Initializes the LTC for symmetric encrypt/decrypt operation. Mode is set to UPDATE.
+ *
+ * @param base LTC peripheral base address
+ * @param key Input key to use for encryption
+ * @param keySize Size of the input key, in bytes. Must be 8, 16, 24, or 32.
+ * @param alg Symmetric algorithm
+ * @param mode Symmetric block mode
+ * @param enc Encrypt/decrypt control
+ * @return Status
+ */
+status_t ltc_symmetric_update(LTC_Type *base,
+                              const uint8_t *key,
+                              uint8_t keySize,
+                              ltc_algorithm_t alg,
+                              ltc_mode_symmetric_alg_t mode,
+                              ltc_mode_encrypt_t enc)
+{
+    return ltc_symmetric_alg_state(base, key, keySize, alg, mode, enc, kLTC_ModeUpdate);
+}
+
+#if defined(FSL_FEATURE_LTC_HAS_GCM) && FSL_FEATURE_LTC_HAS_GCM
+/*!
+ * @brief Initializes the LTC for symmetric encrypt/decrypt operation. Mode is set to FINALIZE.
+ *
+ * @param base LTC peripheral base address
+ * @param key Input key to use for encryption
+ * @param keySize Size of the input key, in bytes. Must be 8, 16, 24, or 32.
+ * @param alg Symmetric algorithm
+ * @param mode Symmetric block mode
+ * @param enc Encrypt/decrypt control
+ * @return Status
+ */
+static status_t ltc_symmetric_final(LTC_Type *base,
+                                    const uint8_t *key,
+                                    uint8_t keySize,
+                                    ltc_algorithm_t alg,
+                                    ltc_mode_symmetric_alg_t mode,
+                                    ltc_mode_encrypt_t enc)
+{
+    return ltc_symmetric_alg_state(base, key, keySize, alg, mode, enc, kLTC_ModeFinalize);
+}
+#endif /* FSL_FEATURE_LTC_HAS_GCM */
+
+/*!
+ * @brief Initializes the LTC for symmetric encrypt/decrypt operation. Mode is set to INITIALIZE.
+ *
+ * @param base LTC peripheral base address
+ * @param key Input key to use for encryption
+ * @param keySize Size of the input key, in bytes. Must be 8, 16, 24, or 32.
+ * @param alg Symmetric algorithm
+ * @param mode Symmetric block mode
+ * @param enc Encrypt/decrypt control
+ * @return Status
+ */
+static status_t ltc_symmetric_init(LTC_Type *base,
+                                   const uint8_t *key,
+                                   uint8_t keySize,
+                                   ltc_algorithm_t alg,
+                                   ltc_mode_symmetric_alg_t mode,
+                                   ltc_mode_encrypt_t enc)
+{
+    return ltc_symmetric_alg_state(base, key, keySize, alg, mode, enc, kLTC_ModeInit);
+}
+
+/*!
+ * @brief Initializes the LTC for symmetric encrypt/decrypt operation. Mode is set to INITIALIZE/FINALIZE.
+ *
+ * @param base LTC peripheral base address
+ * @param key Input key to use for encryption
+ * @param keySize Size of the input key, in bytes. Must be 8, 16, 24, or 32.
+ * @param alg Symmetric algorithm
+ * @param mode Symmetric block mode
+ * @param enc Encrypt/decrypt control
+ * @return Status
+ */
+static status_t ltc_symmetric_init_final(LTC_Type *base,
+                                         const uint8_t *key,
+                                         uint8_t keySize,
+                                         ltc_algorithm_t alg,
+                                         ltc_mode_symmetric_alg_t mode,
+                                         ltc_mode_encrypt_t enc)
+{
+    return ltc_symmetric_alg_state(base, key, keySize, alg, mode, enc, kLTC_ModeInitFinal);
+}
+
+void ltc_symmetric_process(LTC_Type *base, uint32_t inSize, const uint8_t **inData, uint8_t **outData)
+{
+    uint32_t outSize;
+    uint32_t fifoData;
+    uint32_t fifoStatus;
+
+    register const uint8_t *in = *inData;
+    register uint8_t *out = *outData;
+
+    outSize = inSize;
+    while ((outSize > 0) || (inSize > 0))
+    {
+        fifoStatus = base->FIFOSTA;
+
+        /* Check output FIFO level to make sure there is at least an entry
+         * ready to be read. */
+        if (fifoStatus & LTC_FIFOSTA_OFL_MASK)
+        {
+            /* Read data from the output FIFO. */
+            if (outSize > 0)
+            {
+                if (outSize >= sizeof(uint32_t))
+                {
+                    ltc_set_unaligned_from_word(base->OFIFO, out);
+                    out += sizeof(uint32_t);
+                    outSize -= sizeof(uint32_t);
+                }
+                else /* (outSize > 0) && (outSize < 4) */
+                {
+                    fifoData = base->OFIFO;
+                    ltc_memcpy(out, &fifoData, outSize);
+                    out += outSize;
+                    outSize = 0;
+                }
+            }
+        }
+
+        /* Check input FIFO status to see if it is full.  We can
+         * only write more data when both input and output FIFOs are not at a full state.
+         * At the same time we are sure Output FIFO is not full because we have poped at least one entry
+         * by the while loop above.
+         */
+        if (!(fifoStatus & LTC_FIFOSTA_IFF_MASK))
+        {
+            /* Copy data to the input FIFO.
+             * Data can only be copied one word at a time, so pad the data
+             * appropriately if it is less than this size. */
+            if (inSize > 0)
+            {
+                if (inSize >= sizeof(uint32_t))
+                {
+                    base->IFIFO = ltc_get_word_from_unaligned(in);
+                    inSize -= sizeof(uint32_t);
+                    in += sizeof(uint32_t);
+                }
+                else /* (inSize > 0) && (inSize < 4) */
+                {
+                    fifoData = 0;
+                    ltc_memcpy(&fifoData, in, inSize);
+                    base->IFIFO = fifoData;
+                    in += inSize;
+                    inSize = 0;
+                }
+            }
+        }
+    }
+    *inData = in;
+    *outData = out;
+}
+
+/*!
+ * @brief Processes symmetric data through LTC AES and DES engines.
+ *
+ * @param base LTC peripheral base address
+ * @param inData Input data
+ * @param inSize Size of input data, in bytes
+ * @param outData Output data
+ * @return Status from encrypt/decrypt operation
+ */
+status_t ltc_symmetric_process_data(LTC_Type *base, const uint8_t *inData, uint32_t inSize, uint8_t *outData)
+{
+    uint32_t lastSize;
+
+    if ((!inData) || (!outData))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Write the data size. */
+    base->DS = inSize;
+
+    /* Split the inSize into full 16-byte chunks and last incomplete block due to LTC AES OFIFO errata */
+    if (inSize <= 16u)
+    {
+        lastSize = inSize;
+        inSize = 0;
+    }
+    else
+    {
+        /* Process all 16-byte data chunks. */
+        lastSize = inSize % 16u;
+        if (lastSize == 0)
+        {
+            lastSize = 16;
+            inSize -= 16;
+        }
+        else
+        {
+            inSize -= lastSize; /* inSize will be rounded down to 16 byte boundary. remaining bytes in lastSize */
+        }
+    }
+
+    ltc_symmetric_process(base, inSize, &inData, &outData);
+    ltc_symmetric_process(base, lastSize, &inData, &outData);
+    return ltc_wait(base);
+}
+
+/*!
+ * @brief Splits the LTC job into sessions. Used for CBC, CTR, CFB, OFB cipher block modes.
+ *
+ * @param base LTC peripheral base address
+ * @param inData Input data to process.
+ * @param inSize Input size of the input buffer.
+ * @param outData Output data buffer.
+ */
+static status_t ltc_process_message_in_sessions(LTC_Type *base,
+                                                const uint8_t *inData,
+                                                uint32_t inSize,
+                                                uint8_t *outData)
+{
+    uint32_t sz;
+    status_t retval;
+    ltc_mode_t modeReg; /* read and write LTC mode register */
+
+    sz = LTC_FIFO_SZ_MAX_DOWN_ALGN;
+    modeReg = base->MD;
+    retval = kStatus_Success;
+
+    while (inSize)
+    {
+        if (inSize <= sz)
+        {
+            retval = ltc_symmetric_process_data(base, inData, inSize, outData);
+            if (kStatus_Success != retval)
+            {
+                return retval;
+            }
+            inSize = 0;
+        }
+        else
+        {
+            retval = ltc_symmetric_process_data(base, inData, sz, outData);
+            if (kStatus_Success != retval)
+            {
+                return retval;
+            }
+            inData += sz;
+            inSize -= sz;
+            outData += sz;
+            base->MD = modeReg;
+        }
+    }
+    return retval;
+}
+
+static void ltc_move_block_to_ififo(LTC_Type *base, const ltc_xcm_block_t *blk, uint32_t num_bytes)
+{
+    uint32_t i = 0;
+    uint32_t words;
+
+    words = num_bytes / 4u;
+    if (num_bytes % 4u)
+    {
+        words++;
+    }
+
+    if (words > 4)
+    {
+        words = 4;
+    }
+
+    while (i < words)
+    {
+        if (0U == (base->FIFOSTA & LTC_FIFOSTA_IFF_MASK))
+        {
+            /* Copy data to the input FIFO. */
+            base->IFIFO = blk->w[i++];
+        }
+    }
+}
+
+static void ltc_move_to_ififo(LTC_Type *base, const uint8_t *data, uint32_t dataSize)
+{
+    ltc_xcm_block_t blk;
+    ltc_xcm_block_t blkZero = {{0x0u, 0x0u, 0x0u, 0x0u}};
+
+    while (dataSize)
+    {
+        if (dataSize > 16u)
+        {
+            ltc_memcpy(&blk, data, 16u);
+            dataSize -= 16u;
+            data += 16u;
+        }
+        else
+        {
+            ltc_memcpy(&blk, &blkZero, sizeof(ltc_xcm_block_t)); /* memset blk to zeroes */
+            ltc_memcpy(&blk, data, dataSize);
+            dataSize = 0;
+        }
+        ltc_move_block_to_ififo(base, &blk, sizeof(ltc_xcm_block_t));
+    }
+}
+
+/*!
+ * @brief Processes symmetric data through LTC AES in multiple sessions.
+ *
+ * Specific for AES CCM and GCM modes as they need to update mode register.
+ *
+ * @param base LTC peripheral base address
+ * @param inData Input data
+ * @param inSize Size of input data, in bytes
+ * @param outData Output data
+ * @param lastAs The LTC Algorithm state to be set sup for last block during message processing in multiple sessions.
+ *               For CCM it is kLTC_ModeFinalize. For GCM it is kLTC_ModeInitFinal.
+ * @return Status from encrypt/decrypt operation
+ */
+static status_t ltc_symmetric_process_data_multiple(LTC_Type *base,
+                                                    const uint8_t *inData,
+                                                    uint32_t inSize,
+                                                    uint8_t *outData,
+                                                    ltc_mode_t modeReg,
+                                                    ltc_mode_algorithm_state_t lastAs)
+{
+    uint32_t fifoConsumed;
+    uint32_t lastSize;
+    uint32_t sz;
+    uint32_t max_ltc_fifo_size;
+    ltc_mode_algorithm_state_t fsm;
+    status_t status;
+
+    if ((!inData) || (!outData))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (!((kLTC_ModeFinalize == lastAs) || (kLTC_ModeInitFinal == lastAs)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (0 == inSize)
+    {
+        return kStatus_Success;
+    }
+
+    if (inSize <= 16u)
+    {
+        fsm = lastAs;
+        lastSize = inSize;
+    }
+    else
+    {
+        fsm = (ltc_mode_algorithm_state_t)(
+            modeReg &
+            LTC_MD_AS_MASK); /* this will be either kLTC_ModeInit or kLTC_ModeUpdate, based on prior processing */
+
+        /* Process all 16-byte data chunks. */
+        lastSize = inSize % 16u;
+        if (lastSize == 0u)
+        {
+            lastSize = 16u;
+            inSize -= 16u;
+        }
+        else
+        {
+            inSize -= lastSize; /* inSize will be rounded down to 16 byte boundary. remaining bytes in lastSize */
+        }
+    }
+
+    max_ltc_fifo_size = LTC_FIFO_SZ_MAX_DOWN_ALGN;
+    fifoConsumed = base->DS;
+
+    while (lastSize)
+    {
+        switch (fsm)
+        {
+            case kLTC_ModeUpdate:
+            case kLTC_ModeInit:
+                while (inSize)
+                {
+                    if (inSize > (max_ltc_fifo_size - fifoConsumed))
+                    {
+                        sz = (max_ltc_fifo_size - fifoConsumed);
+                    }
+                    else
+                    {
+                        sz = inSize;
+                    }
+                    base->DS = sz;
+                    ltc_symmetric_process(base, sz, &inData, &outData);
+                    inSize -= sz;
+                    fifoConsumed = 0;
+
+                    /* after we completed INITIALIZE job, are there still any data left? */
+                    if (inSize)
+                    {
+                        fsm = kLTC_ModeUpdate;
+                        status = ltc_wait(base);
+                        if (kStatus_Success != status)
+                        {
+                            return status;
+                        }
+                        modeReg &= ~LTC_MD_AS_MASK;
+                        modeReg |= (uint32_t)fsm;
+                        base->MD = modeReg;
+                    }
+                    else
+                    {
+                        fsm = lastAs;
+                    }
+                }
+                break;
+
+            case kLTC_ModeFinalize:
+            case kLTC_ModeInitFinal:
+                /* process last block in FINALIZE */
+
+                status = ltc_wait(base);
+                if (kStatus_Success != status)
+                {
+                    return status;
+                }
+
+                modeReg &= ~LTC_MD_AS_MASK;
+                modeReg |= (uint32_t)lastAs;
+                base->MD = modeReg;
+
+                base->DS = lastSize;
+                ltc_symmetric_process(base, lastSize, &inData, &outData);
+                lastSize = 0;
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    status = ltc_wait(base);
+    return status;
+}
+
+/*!
+ * @brief Receives MAC compare.
+ *
+ * This function is a sub-process of CCM and GCM decryption.
+ * It compares received MAC with the MAC computed during decryption.
+ *
+ * @param base LTC peripheral base address
+ * @param tag Received MAC.
+ * @param tagSize Number of bytes in the received MAC.
+ * @param modeReg LTC Mode Register current value. It is modified and written to LTC Mode Register.
+ */
+static status_t ltc_aes_received_mac_compare(LTC_Type *base, const uint8_t *tag, uint32_t tagSize, ltc_mode_t modeReg)
+{
+    ltc_xcm_block_t blk = {{0x0u, 0x0u, 0x0u, 0x0u}};
+
+    base->CW = kLTC_ClearDataSize;
+    base->STA = kLTC_StatusDoneIsr;
+
+    modeReg &= ~LTC_MD_AS_MASK;
+    modeReg |= (uint32_t)kLTC_ModeUpdate | LTC_MD_ICV_TEST_MASK;
+    base->MD = modeReg;
+
+    base->DS = 0u;
+    base->ICVS = tagSize;
+    ltc_memcpy(&blk.b[0], &tag[0], tagSize);
+
+    ltc_move_block_to_ififo(base, &blk, tagSize);
+    return ltc_wait(base);
+}
+
+/*!
+ * @brief Processes tag during AES GCM and CCM.
+ *
+ * This function is a sub-process of CCM and GCM encryption and decryption.
+ * For encryption, it writes computed MAC to the output tag.
+ * For decryption, it compares the received MAC with the computed MAC.
+ *
+ * @param base LTC peripheral base address
+ * @param[in,out] tag Output computed MAC during encryption or Input received MAC during decryption.
+ * @param tagSize Size of MAC buffer in bytes.
+ * @param modeReg LTC Mode Register current value. It is checked to read Enc/Dec bit.
+ *                 It is modified and written to LTC Mode Register during decryption.
+ * @param ctx Index to LTC context registers with computed MAC for encryption process.
+ */
+static status_t ltc_aes_process_tag(LTC_Type *base, uint8_t *tag, uint32_t tagSize, ltc_mode_t modeReg, uint32_t ctx)
+{
+    status_t status = kStatus_Success;
+    if (tag)
+    {
+        /* For decrypt, compare received MAC with the computed MAC. */
+        if (kLTC_ModeDecrypt == (modeReg & LTC_MD_ENC_MASK))
+        {
+            status = ltc_aes_received_mac_compare(base, tag, tagSize, modeReg);
+        }
+        else /* FSL_AES_GCM_TYPE_ENCRYPT */
+        {
+            /* For encryption, write the computed and encrypted MAC to user buffer */
+            ltc_get_context(base, &tag[0], tagSize, ctx);
+        }
+    }
+    return status;
+}
+
+/*******************************************************************************
+ * LTC Common code public
+ ******************************************************************************/
+void LTC_Init(LTC_Type *base)
+{
+    /* ungate clock */
+    CLOCK_EnableClock(kCLOCK_Ltc0);
+}
+
+void LTC_Deinit(LTC_Type *base)
+{
+    /* gate clock */
+    CLOCK_DisableClock(kCLOCK_Ltc0);
+}
+
+#if defined(FSL_FEATURE_LTC_HAS_DPAMS) && FSL_FEATURE_LTC_HAS_DPAMS
+void LTC_SetDpaMaskSeed(LTC_Type *base, uint32_t mask)
+{
+    base->DPAMS = mask;
+    /* second write as workaround for DPA mask re-seed errata */
+    base->DPAMS = mask;
+}
+#endif /* FSL_FEATURE_LTC_HAS_DPAMS */
+
+/*******************************************************************************
+ * AES Code static
+ ******************************************************************************/
+static status_t ltc_aes_decrypt_ecb(LTC_Type *base,
+                                    const uint8_t *ciphertext,
+                                    uint8_t *plaintext,
+                                    uint32_t size,
+                                    const uint8_t *key,
+                                    uint32_t keySize,
+                                    ltc_aes_key_t keyType)
+{
+    status_t retval;
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeECB, kLTC_ModeDecrypt);
+
+    /* set DK bit in the LTC Mode Register AAI field for directly loaded decrypt keys */
+    if (keyType == kLTC_DecryptKey)
+    {
+        base->MD |= (1U << kLTC_ModeRegBitShiftDK);
+    }
+
+    /* Process data and return status. */
+    retval = ltc_process_message_in_sessions(base, &ciphertext[0], size, &plaintext[0]);
+    return retval;
+}
+
+/*******************************************************************************
+ * AES Code public
+ ******************************************************************************/
+status_t LTC_AES_GenerateDecryptKey(LTC_Type *base, const uint8_t *encryptKey, uint8_t *decryptKey, uint32_t keySize)
+{
+    uint8_t plaintext[LTC_AES_BLOCK_SIZE];
+    uint8_t ciphertext[LTC_AES_BLOCK_SIZE];
+    status_t status;
+
+    if (!ltc_check_key_size(keySize))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* ECB decrypt with encrypt key will convert the key in LTC context into decrypt form of the key */
+    status = ltc_aes_decrypt_ecb(base, ciphertext, plaintext, LTC_AES_BLOCK_SIZE, encryptKey, keySize, kLTC_EncryptKey);
+    /* now there is decrypt form of the key in the LTC context, so take it */
+    ltc_get_key(base, decryptKey, keySize);
+
+    ltc_clear_all(base, false);
+
+    return status;
+}
+
+status_t LTC_AES_EncryptEcb(
+    LTC_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, uint32_t size, const uint8_t *key, uint32_t keySize)
+{
+    status_t retval;
+
+    if (!ltc_check_key_size(keySize))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* ECB mode, size must be 16-byte multiple */
+    if ((size < 16u) || (size % 16u))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeECB, kLTC_ModeEncrypt);
+
+    /* Process data and return status. */
+    retval = ltc_process_message_in_sessions(base, &plaintext[0], size, &ciphertext[0]);
+    ltc_clear_all(base, false);
+    return retval;
+}
+
+status_t LTC_AES_DecryptEcb(LTC_Type *base,
+                            const uint8_t *ciphertext,
+                            uint8_t *plaintext,
+                            uint32_t size,
+                            const uint8_t *key,
+                            uint32_t keySize,
+                            ltc_aes_key_t keyType)
+{
+    status_t status;
+
+    if (!ltc_check_key_size(keySize))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* ECB mode, size must be 16-byte multiple */
+    if ((size < 16u) || (size % 16u))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    status = ltc_aes_decrypt_ecb(base, ciphertext, plaintext, size, key, keySize, keyType);
+    ltc_clear_all(base, false);
+    return status;
+}
+
+status_t LTC_AES_EncryptCbc(LTC_Type *base,
+                            const uint8_t *plaintext,
+                            uint8_t *ciphertext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_AES_IV_SIZE],
+                            const uint8_t *key,
+                            uint32_t keySize)
+{
+    status_t retval;
+
+    if (!ltc_check_key_size(keySize))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* CBC mode, size must be 16-byte multiple */
+    if ((size < 16u) || (size % 16u))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCBC, kLTC_ModeEncrypt);
+
+    /* Write IV data to the context register. */
+    ltc_set_context(base, &iv[0], LTC_AES_IV_SIZE, 0);
+
+    /* Process data and return status. */
+    retval = ltc_process_message_in_sessions(base, &plaintext[0], size, &ciphertext[0]);
+    ltc_clear_all(base, false);
+    return retval;
+}
+
+status_t LTC_AES_DecryptCbc(LTC_Type *base,
+                            const uint8_t *ciphertext,
+                            uint8_t *plaintext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_AES_IV_SIZE],
+                            const uint8_t *key,
+                            uint32_t keySize,
+                            ltc_aes_key_t keyType)
+{
+    status_t retval;
+
+    if (!ltc_check_key_size(keySize))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* CBC mode, size must be 16-byte multiple */
+    if ((size < 16u) || (size % 16u))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* set DK bit in the LTC Mode Register AAI field for directly loaded decrypt keys */
+    if (keyType == kLTC_DecryptKey)
+    {
+        base->MD |= (1U << kLTC_ModeRegBitShiftDK);
+    }
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCBC, kLTC_ModeDecrypt);
+
+    /* Write IV data to the context register. */
+    ltc_set_context(base, &iv[0], LTC_AES_IV_SIZE, 0);
+
+    /* Process data and return status. */
+    retval = ltc_process_message_in_sessions(base, &ciphertext[0], size, &plaintext[0]);
+    ltc_clear_all(base, false);
+    return retval;
+}
+
+status_t LTC_AES_CryptCtr(LTC_Type *base,
+                          const uint8_t *input,
+                          uint8_t *output,
+                          uint32_t size,
+                          uint8_t counter[LTC_AES_BLOCK_SIZE],
+                          const uint8_t *key,
+                          uint32_t keySize,
+                          uint8_t counterlast[LTC_AES_BLOCK_SIZE],
+                          uint32_t *szLeft)
+{
+    status_t retval;
+    uint32_t lastSize;
+
+    if (!ltc_check_key_size(keySize))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    lastSize = 0U;
+    if (counterlast != NULL)
+    {
+        /* Split the size into full 16-byte chunks and last incomplete block due to LTC AES OFIFO errata */
+        if (size <= 16U)
+        {
+            lastSize = size;
+            size = 0U;
+        }
+        else
+        {
+            /* Process all 16-byte data chunks. */
+            lastSize = size % 16U;
+            if (lastSize == 0U)
+            {
+                lastSize = 16U;
+                size -= 16U;
+            }
+            else
+            {
+                size -= lastSize; /* size will be rounded down to 16 byte boundary. remaining bytes in lastSize */
+            }
+        }
+    }
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCTR, kLTC_ModeEncrypt);
+
+    /* Write initial counter data to the context register.
+     * NOTE the counter values start at 4-bytes offset into the context. */
+    ltc_set_context(base, &counter[0], 16U, 4U);
+
+    /* Process data and return status. */
+    retval = ltc_process_message_in_sessions(base, input, size, output);
+    if (kStatus_Success != retval)
+    {
+        return retval;
+    }
+
+    input += size;
+    output += size;
+
+    if ((counterlast != NULL) && lastSize)
+    {
+        uint8_t zeroes[16] = {0};
+        ltc_mode_t modeReg;
+
+        modeReg = (uint32_t)kLTC_AlgorithmAES | (uint32_t)kLTC_ModeCTR | (uint32_t)kLTC_ModeEncrypt;
+        /* Write the mode register to the hardware. */
+        base->MD = modeReg | (uint32_t)kLTC_ModeFinalize;
+
+        /* context is re-used (CTRi) */
+
+        /* Process data and return status. */
+        retval = ltc_symmetric_process_data(base, input, lastSize, output);
+        if (kStatus_Success != retval)
+        {
+            return retval;
+        }
+        if (szLeft)
+        {
+            *szLeft = 16U - lastSize;
+        }
+
+        /* Initialize algorithm state. */
+        base->MD = modeReg | (uint32_t)kLTC_ModeUpdate;
+
+        /* context is re-used (CTRi) */
+
+        /* Process data and return status. */
+        retval = ltc_symmetric_process_data(base, zeroes, 16U, counterlast);
+    }
+    ltc_get_context(base, &counter[0], 16U, 4U);
+    ltc_clear_all(base, false);
+    return retval;
+}
+
+#if defined(FSL_FEATURE_LTC_HAS_GCM) && FSL_FEATURE_LTC_HAS_GCM
+/*******************************************************************************
+ * GCM Code static
+ ******************************************************************************/
+static status_t ltc_aes_gcm_check_input_args(LTC_Type *base,
+                                             const uint8_t *src,
+                                             const uint8_t *iv,
+                                             const uint8_t *aad,
+                                             const uint8_t *key,
+                                             uint8_t *dst,
+                                             uint32_t inputSize,
+                                             uint32_t ivSize,
+                                             uint32_t aadSize,
+                                             uint32_t keySize,
+                                             uint32_t tagSize)
+{
+    if (!base)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* tag can be NULL to skip tag processing */
+    if ((!key) || (ivSize && (!iv)) || (aadSize && (!aad)) || (inputSize && ((!src) || (!dst))))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* octet length of tag (tagSize) must be element of 4,8,12,13,14,15,16 */
+    if (((tagSize > 16u) || (tagSize < 12u)) && (tagSize != 4u) && (tagSize != 8u))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* check if keySize is supported */
+    if (!ltc_check_key_size(keySize))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* no IV AAD DATA makes no sense */
+    if (0 == (inputSize + ivSize + aadSize))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Process Wrapper for void (*pfunc)(LTC_Type*, uint32_t, bool). Sets IV Size register.
+ */
+static void ivsize_next(LTC_Type *base, uint32_t ivSize, bool iv_only)
+{
+    base->IVSZ = LTC_IVSZ_IL(iv_only) | ((ivSize)&LTC_DS_DS_MASK);
+}
+
+/*!
+ * @brief Process Wrapper for void (*pfunc)(LTC_Type*, uint32_t, bool). Sets AAD Size register.
+ */
+static void aadsize_next(LTC_Type *base, uint32_t aadSize, bool aad_only)
+{
+    base->AADSZ = LTC_AADSZ_AL(aad_only) | ((aadSize)&LTC_DS_DS_MASK);
+}
+
+/*!
+ * @brief Process IV or AAD string in multi-session.
+ *
+ * @param base LTC peripheral base address
+ * @param iv IV or AAD data
+ * @param ivSize Size in bytes of IV or AAD data
+ * @param modeReg LTC peripheral Mode register value
+ * @param iv_only IV only or AAD only flag
+ * @param type selects between IV or AAD
+ */
+static status_t ltc_aes_gcm_process_iv_aad(
+    LTC_Type *base, const uint8_t *iv, uint32_t ivSize, ltc_mode_t modeReg, bool iv_only, int type, ltc_mode_t modeLast)
+{
+    uint32_t sz;
+    status_t retval;
+    void (*next_size_func)(LTC_Type *ltcBase, uint32_t nextSize, bool authOnly);
+
+    if ((NULL == iv) || (ivSize == 0))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    sz = LTC_FIFO_SZ_MAX_DOWN_ALGN;
+    next_size_func = type == LTC_AES_GCM_TYPE_AAD ? aadsize_next : ivsize_next;
+
+    while (ivSize)
+    {
+        if (ivSize < sz)
+        {
+            modeReg &= ~LTC_MD_AS_MASK;
+            modeReg |= modeLast;
+            base->MD = modeReg;
+            next_size_func(base, ivSize, iv_only);
+            ltc_move_to_ififo(base, iv, ivSize);
+            ivSize = 0;
+        }
+        else
+        {
+            /* set algorithm state to UPDATE */
+            modeReg &= ~LTC_MD_AS_MASK;
+            modeReg |= kLTC_ModeUpdate;
+            base->MD = modeReg;
+
+            next_size_func(base, (uint16_t)sz, true);
+            ltc_move_to_ififo(base, iv, sz);
+            ivSize -= sz;
+            iv += sz;
+        }
+
+        retval = ltc_wait(base);
+        if (kStatus_Success != retval)
+        {
+            return retval;
+        }
+    } /* end while */
+    return kStatus_Success;
+}
+
+static status_t ltc_aes_gcm_process(LTC_Type *base,
+                                    ltc_mode_encrypt_t encryptMode,
+                                    const uint8_t *src,
+                                    uint32_t inputSize,
+                                    const uint8_t *iv,
+                                    uint32_t ivSize,
+                                    const uint8_t *aad,
+                                    uint32_t aadSize,
+                                    const uint8_t *key,
+                                    uint32_t keySize,
+                                    uint8_t *dst,
+                                    uint8_t *tag,
+                                    uint32_t tagSize)
+{
+    status_t retval;          /* return value */
+    uint32_t max_ltc_fifo_sz; /* maximum data size that we can put to LTC FIFO in one session. 12-bit limit. */
+    ltc_mode_t modeReg;       /* read and write LTC mode register */
+
+    bool single_ses_proc_all; /* iv, aad and src data can be processed in one session */
+    bool iv_only;
+    bool aad_only;
+
+    retval = ltc_aes_gcm_check_input_args(base, src, iv, aad, key, dst, inputSize, ivSize, aadSize, keySize, tagSize);
+
+    /* API input validation */
+    if (kStatus_Success != retval)
+    {
+        return retval;
+    }
+
+    max_ltc_fifo_sz = LTC_DS_DS_MASK; /* 12-bit field limit */
+
+    /*
+     * Write value to LTC AADSIZE (rounded up to next 16 byte boundary)
+     * plus the write value to LTC IV (rounded up to next 16 byte boundary)
+     * plus the inputSize. If the result is less than max_ltc_fifo_sz
+     * then all can be processed in one session FINALIZE.
+     * Otherwise, we have to split into multiple session, going through UPDATE(s), INITIALIZE, UPDATE(s) and FINALIZE.
+     */
+    single_ses_proc_all =
+        (((aadSize + 15u) & 0xfffffff0u) + ((ivSize + 15u) & 0xfffffff0u) + inputSize) <= max_ltc_fifo_sz;
+
+    /* setup key, algorithm and set the alg.state */
+    if (single_ses_proc_all)
+    {
+        ltc_symmetric_final(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeGCM, encryptMode);
+        modeReg = base->MD;
+
+        iv_only = (aadSize == 0) && (inputSize == 0);
+        aad_only = (inputSize == 0);
+
+        /* DS_MASK here is not a bug. IV size field can be written with more than 4-bits,
+         * as the IVSZ write value, aligned to next 16 bytes boundary, is written also to the Data Size.
+         * For example, I can write 22 to IVSZ, 32 will be written to Data Size and IVSZ will have value 6, which is 22
+         * mod 16.
+         */
+        base->IVSZ = LTC_IVSZ_IL(iv_only) | ((ivSize)&LTC_DS_DS_MASK);
+        ltc_move_to_ififo(base, iv, ivSize);
+        if (iv_only && ivSize)
+        {
+            retval = ltc_wait(base);
+            if (kStatus_Success != retval)
+            {
+                return retval;
+            }
+        }
+        base->AADSZ = LTC_AADSZ_AL(aad_only) | ((aadSize)&LTC_DS_DS_MASK);
+        ltc_move_to_ififo(base, aad, aadSize);
+        if (aad_only && aadSize)
+        {
+            retval = ltc_wait(base);
+            if (kStatus_Success != retval)
+            {
+                return retval;
+            }
+        }
+
+        if (inputSize)
+        {
+            /* Workaround for the LTC Data Size register update errata TKT261180 */
+            while (16U < base->DS)
+            {
+            }
+
+            ltc_symmetric_process_data(base, &src[0], inputSize, &dst[0]);
+        }
+    }
+    else
+    {
+        ltc_symmetric_init(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeGCM, encryptMode);
+        modeReg = base->MD;
+
+        /* process IV */
+        if (ivSize)
+        {
+            /* last chunk of IV is always INITIALIZE (for GHASH to occur) */
+            retval = ltc_aes_gcm_process_iv_aad(base, iv, ivSize, modeReg, true, LTC_AES_GCM_TYPE_IV, kLTC_ModeInit);
+            if (kStatus_Success != retval)
+            {
+                return retval;
+            }
+        }
+
+        /* process AAD */
+        if (aadSize)
+        {
+            /* AS mode to process last chunk of AAD. it differs if we are in GMAC or GCM */
+            ltc_mode_t lastModeReg;
+            if (0 == inputSize)
+            {
+                /* if there is no DATA, set mode to compute final MAC. this is GMAC mode */
+                lastModeReg = kLTC_ModeInitFinal;
+            }
+            else
+            {
+                /* there are confidential DATA. so process last chunk of AAD in UPDATE mode */
+                lastModeReg = kLTC_ModeUpdate;
+            }
+            retval = ltc_aes_gcm_process_iv_aad(base, aad, aadSize, modeReg, true, LTC_AES_GCM_TYPE_AAD, lastModeReg);
+            if (kStatus_Success != retval)
+            {
+                return retval;
+            }
+        }
+
+        /* there are DATA. */
+        if (inputSize)
+        {
+            /* set algorithm state to UPDATE */
+            modeReg &= ~LTC_MD_AS_MASK;
+            modeReg |= kLTC_ModeUpdate;
+            base->MD = modeReg;
+            retval =
+                ltc_symmetric_process_data_multiple(base, &src[0], inputSize, &dst[0], modeReg, kLTC_ModeInitFinal);
+        }
+    }
+    if (kStatus_Success != retval)
+    {
+        return retval;
+    }
+    retval = ltc_aes_process_tag(base, tag, tagSize, modeReg, LTC_GCM_TAG_IDX);
+    return retval;
+}
+
+/*******************************************************************************
+ * GCM Code public
+ ******************************************************************************/
+status_t LTC_AES_EncryptTagGcm(LTC_Type *base,
+                               const uint8_t *plaintext,
+                               uint8_t *ciphertext,
+                               uint32_t size,
+                               const uint8_t *iv,
+                               uint32_t ivSize,
+                               const uint8_t *aad,
+                               uint32_t aadSize,
+                               const uint8_t *key,
+                               uint32_t keySize,
+                               uint8_t *tag,
+                               uint32_t tagSize)
+{
+    status_t status;
+
+    status = ltc_aes_gcm_process(base, kLTC_ModeEncrypt, plaintext, size, iv, ivSize, aad, aadSize, key, keySize,
+                                 ciphertext, tag, tagSize);
+
+    ltc_clear_all(base, false);
+    return status;
+}
+
+status_t LTC_AES_DecryptTagGcm(LTC_Type *base,
+                               const uint8_t *ciphertext,
+                               uint8_t *plaintext,
+                               uint32_t size,
+                               const uint8_t *iv,
+                               uint32_t ivSize,
+                               const uint8_t *aad,
+                               uint32_t aadSize,
+                               const uint8_t *key,
+                               uint32_t keySize,
+                               const uint8_t *tag,
+                               uint32_t tagSize)
+{
+    uint8_t temp_tag[16] = {0}; /* max. octet length of Integrity Check Value ICV (tag) is 16 */
+    uint8_t *tag_ptr;
+    status_t status;
+
+    tag_ptr = NULL;
+    if (tag)
+    {
+        ltc_memcpy(temp_tag, tag, tagSize);
+        tag_ptr = &temp_tag[0];
+    }
+    status = ltc_aes_gcm_process(base, kLTC_ModeDecrypt, ciphertext, size, iv, ivSize, aad, aadSize, key, keySize,
+                                 plaintext, tag_ptr, tagSize);
+
+    ltc_clear_all(base, false);
+    return status;
+}
+#endif /* FSL_FEATURE_LTC_HAS_GCM */
+
+/*******************************************************************************
+ * CCM Code static
+ ******************************************************************************/
+static status_t ltc_aes_ccm_check_input_args(LTC_Type *base,
+                                             const uint8_t *src,
+                                             const uint8_t *iv,
+                                             const uint8_t *key,
+                                             uint8_t *dst,
+                                             uint32_t ivSize,
+                                             uint32_t aadSize,
+                                             uint32_t keySize,
+                                             uint32_t tagSize)
+{
+    if (!base)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* tag can be NULL to skip tag processing */
+    if ((!src) || (!iv) || (!key) || (!dst))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* size of Nonce (ivSize) must be element of 7,8,9,10,11,12,13 */
+    if ((ivSize < 7u) || (ivSize > 13u))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* octet length of MAC (tagSize) must be element of 4,6,8,10,12,14,16 for tag processing or zero to skip tag
+     * processing */
+    if (((tagSize > 0) && (tagSize < 4u)) || (tagSize > 16u) || (tagSize & 1u))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* check if keySize is supported */
+    if (!ltc_check_key_size(keySize))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* LTC does not support more AAD than this */
+    if (aadSize >= 65280u)
+    {
+        return kStatus_InvalidArgument;
+    }
+    return kStatus_Success;
+}
+
+static uint32_t swap_bytes(uint32_t in)
+{
+    return (((in & 0x000000ffu) << 24) | ((in & 0x0000ff00u) << 8) | ((in & 0x00ff0000u) >> 8) |
+            ((in & 0xff000000u) >> 24));
+}
+
+static void ltc_aes_ccm_context_init(
+    LTC_Type *base, uint32_t inputSize, const uint8_t *iv, uint32_t ivSize, uint32_t aadSize, uint32_t tagSize)
+{
+    ltc_xcm_block_t blk;
+    ltc_xcm_block_t blkZero = {{0x0u, 0x0u, 0x0u, 0x0u}};
+
+    int q; /* octet length of binary representation of the octet length of the payload. computed as (15 - n), where n is
+              length of nonce(=ivSize) */
+    uint8_t flags; /* flags field in B0 and CTR0 */
+
+    /* compute B0 */
+    ltc_memcpy(&blk, &blkZero, sizeof(blk));
+    /* tagSize - size of output MAC */
+    q = 15 - ivSize;
+    flags = (uint8_t)(8 * ((tagSize - 2) / 2) + q - 1); /* 8*M' + L' */
+    if (aadSize)
+    {
+        flags |= 0x40; /* Adata */
+    }
+    blk.b[0] = flags;                  /* flags field */
+    blk.w[3] = swap_bytes(inputSize);  /* message size, most significant byte first */
+    ltc_memcpy(&blk.b[1], iv, ivSize); /* nonce field */
+
+    /* Write B0 data to the context register.
+     */
+    ltc_set_context(base, &blk.b[0], 16, 0);
+
+    /* Write CTR0 to the context register.
+     */
+    ltc_memcpy(&blk, &blkZero, sizeof(blk)); /* ctr(0) field = zero */
+    blk.b[0] = q - 1;                        /* flags field */
+    ltc_memcpy(&blk.b[1], iv, ivSize);       /* nonce field */
+    ltc_set_context(base, &blk.b[0], 16, 4);
+}
+
+static status_t ltc_aes_ccm_process_aad(
+    LTC_Type *base, uint32_t inputSize, const uint8_t *aad, uint32_t aadSize, ltc_mode_t *modeReg)
+{
+    ltc_xcm_block_t blk = {{0x0u, 0x0u, 0x0u, 0x0u}};
+    uint32_t swapped; /* holds byte swap of uint32_t */
+    status_t retval;
+
+    if (aadSize)
+    {
+        bool aad_only;
+        bool aad_single_session;
+
+        uint32_t sz = 0;
+
+        aad_only = inputSize == 0u;
+        aad_single_session = (((aadSize + 2u) + 15u) & 0xfffffff0u) <= LTC_FIFO_SZ_MAX_DOWN_ALGN;
+
+        /* limit by CCM spec: 2^16 - 2^8 = 65280 */
+
+        /* encoding is two octets, msbyte first */
+        swapped = swap_bytes(aadSize);
+        ltc_memcpy(&blk.b[0], ((uint8_t *)&swapped) + sizeof(uint16_t), sizeof(uint16_t));
+
+        sz = aadSize > 14u ? 14u : aadSize; /* limit aad to the end of 16 bytes blk */
+        ltc_memcpy(&blk.b[2], aad, sz);     /* fill B1 with aad */
+
+        if (aad_single_session)
+        {
+            base->AADSZ = LTC_AADSZ_AL(aad_only) | ((aadSize + 2U) & LTC_DS_DS_MASK);
+            /* move first AAD block (16 bytes block B1) to FIFO */
+            ltc_move_block_to_ififo(base, &blk, sizeof(blk));
+        }
+        else
+        {
+            base->AADSZ = LTC_AADSZ_AL(true) | (16U);
+            /* move first AAD block (16 bytes block B1) to FIFO */
+            ltc_move_block_to_ififo(base, &blk, sizeof(blk));
+        }
+
+        /* track consumed AAD. sz bytes have been moved to fifo. */
+        aadSize -= sz;
+        aad += sz;
+
+        if (aad_single_session)
+        {
+            /* move remaining AAD to FIFO, then return, to continue with MDATA */
+            ltc_move_to_ififo(base, aad, aadSize);
+        }
+        else if (aadSize == 0u)
+        {
+            retval = ltc_wait(base);
+            if (kStatus_Success != retval)
+            {
+                return retval;
+            }
+        }
+        else
+        {
+            while (aadSize)
+            {
+                retval = ltc_wait(base);
+                if (kStatus_Success != retval)
+                {
+                    return retval;
+                }
+
+                *modeReg &= ~LTC_MD_AS_MASK;
+                *modeReg |= (uint32_t)kLTC_ModeUpdate;
+                base->MD = *modeReg;
+
+                sz = LTC_FIFO_SZ_MAX_DOWN_ALGN;
+                if (aadSize < sz)
+                {
+                    base->AADSZ = LTC_AADSZ_AL(aad_only) | (aadSize & LTC_DS_DS_MASK);
+                    ltc_move_to_ififo(base, aad, aadSize);
+                    aadSize = 0;
+                }
+                else
+                {
+                    base->AADSZ = LTC_AADSZ_AL(true) | (sz & LTC_DS_DS_MASK);
+                    ltc_move_to_ififo(base, aad, sz);
+                    aadSize -= sz;
+                    aad += sz;
+                }
+            } /* end while */
+        }     /* end else */
+    }         /* end if */
+    return kStatus_Success;
+}
+
+static status_t ltc_aes_ccm_process(LTC_Type *base,
+                                    ltc_mode_encrypt_t encryptMode,
+                                    const uint8_t *src,
+                                    uint32_t inputSize,
+                                    const uint8_t *iv,
+                                    uint32_t ivSize,
+                                    const uint8_t *aad,
+                                    uint32_t aadSize,
+                                    const uint8_t *key,
+                                    uint32_t keySize,
+                                    uint8_t *dst,
+                                    uint8_t *tag,
+                                    uint32_t tagSize)
+{
+    status_t retval;          /* return value */
+    uint32_t max_ltc_fifo_sz; /* maximum data size that we can put to LTC FIFO in one session. 12-bit limit. */
+    ltc_mode_t modeReg;       /* read and write LTC mode register */
+
+    bool single_ses_proc_all; /* aad and src data can be processed in one session */
+
+    retval = ltc_aes_ccm_check_input_args(base, src, iv, key, dst, ivSize, aadSize, keySize, tagSize);
+
+    /* API input validation */
+    if (kStatus_Success != retval)
+    {
+        return retval;
+    }
+
+    max_ltc_fifo_sz = LTC_DS_DS_MASK; /* 12-bit field limit */
+
+    /* Write value to LTC AADSIZE will be (aadSize+2) value.
+     * The value will be rounded up to next 16 byte boundary and added to Data Size register.
+     * We then add inputSize to Data Size register. If the resulting Data Size is less than max_ltc_fifo_sz
+     * then all can be processed in one session INITIALIZE/FINALIZE.
+     * Otherwise, we have to split into multiple session, going through INITIALIZE, UPDATE (if required) and FINALIZE.
+     */
+    single_ses_proc_all = ((((aadSize + 2) + 15u) & 0xfffffff0u) + inputSize) <= max_ltc_fifo_sz;
+
+    /* setup key, algorithm and set the alg.state to INITIALIZE */
+    if (single_ses_proc_all)
+    {
+        ltc_symmetric_init_final(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCCM, encryptMode);
+    }
+    else
+    {
+        ltc_symmetric_init(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCCM, encryptMode);
+    }
+    modeReg = base->MD;
+
+    /* Initialize LTC context for AES CCM: block B0 and initial counter CTR0 */
+    ltc_aes_ccm_context_init(base, inputSize, iv, ivSize, aadSize, tagSize);
+
+    /* Process additional authentication data, if there are any.
+     * Need to split the job into individual sessions of up to 4096 bytes, due to LTC IFIFO data size limit.
+     */
+    retval = ltc_aes_ccm_process_aad(base, inputSize, aad, aadSize, &modeReg);
+    if (kStatus_Success != retval)
+    {
+        return retval;
+    }
+
+    /* Workaround for the LTC Data Size register update errata TKT261180 */
+    if (inputSize)
+    {
+        while (16u < base->DS)
+        {
+        }
+    }
+
+    /* Process message */
+    if (single_ses_proc_all)
+    {
+        retval = ltc_symmetric_process_data(base, &src[0], inputSize, &dst[0]);
+    }
+    else
+    {
+        retval = ltc_symmetric_process_data_multiple(base, &src[0], inputSize, &dst[0], modeReg, kLTC_ModeFinalize);
+    }
+    if (kStatus_Success != retval)
+    {
+        return retval;
+    }
+    retval = ltc_aes_process_tag(base, tag, tagSize, modeReg, LTC_CCM_TAG_IDX);
+    return retval;
+}
+
+/*******************************************************************************
+ * CCM Code public
+ ******************************************************************************/
+status_t LTC_AES_EncryptTagCcm(LTC_Type *base,
+                               const uint8_t *plaintext,
+                               uint8_t *ciphertext,
+                               uint32_t size,
+                               const uint8_t *iv,
+                               uint32_t ivSize,
+                               const uint8_t *aad,
+                               uint32_t aadSize,
+                               const uint8_t *key,
+                               uint32_t keySize,
+                               uint8_t *tag,
+                               uint32_t tagSize)
+{
+    status_t status;
+    status = ltc_aes_ccm_process(base, kLTC_ModeEncrypt, plaintext, size, iv, ivSize, aad, aadSize, key, keySize,
+                                 ciphertext, tag, tagSize);
+
+    ltc_clear_all(base, false);
+    return status;
+}
+
+status_t LTC_AES_DecryptTagCcm(LTC_Type *base,
+                               const uint8_t *ciphertext,
+                               uint8_t *plaintext,
+                               uint32_t size,
+                               const uint8_t *iv,
+                               uint32_t ivSize,
+                               const uint8_t *aad,
+                               uint32_t aadSize,
+                               const uint8_t *key,
+                               uint32_t keySize,
+                               const uint8_t *tag,
+                               uint32_t tagSize)
+{
+    uint8_t temp_tag[16] = {0}; /* max. octet length of MAC (tag) is 16 */
+    uint8_t *tag_ptr;
+    status_t status;
+
+    tag_ptr = NULL;
+    if (tag)
+    {
+        ltc_memcpy(temp_tag, tag, tagSize);
+        tag_ptr = &temp_tag[0];
+    }
+
+    status = ltc_aes_ccm_process(base, kLTC_ModeDecrypt, ciphertext, size, iv, ivSize, aad, aadSize, key, keySize,
+                                 plaintext, tag_ptr, tagSize);
+
+    ltc_clear_all(base, false);
+    return status;
+}
+
+#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES
+/*******************************************************************************
+ * DES / 3DES Code static
+ ******************************************************************************/
+static status_t ltc_des_process(LTC_Type *base,
+                                const uint8_t *input,
+                                uint8_t *output,
+                                uint32_t size,
+                                const uint8_t iv[LTC_DES_IV_SIZE],
+                                const uint8_t key[LTC_DES_KEY_SIZE],
+                                ltc_mode_symmetric_alg_t modeAs,
+                                ltc_mode_encrypt_t modeEnc)
+{
+    status_t retval;
+
+    /* all but OFB, size must be 8-byte multiple */
+    if ((modeAs != kLTC_ModeOFB) && ((size < 8u) || (size % 8u)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, &key[0], LTC_DES_KEY_SIZE, kLTC_AlgorithmDES, modeAs, modeEnc);
+
+    if ((modeAs != kLTC_ModeECB))
+    {
+        ltc_set_context(base, iv, LTC_DES_IV_SIZE, 0);
+    }
+
+    /* Process data and return status. */
+    retval = ltc_process_message_in_sessions(base, input, size, output);
+    ltc_clear_all(base, false);
+    return retval;
+}
+
+status_t ltc_3des_check_input_args(ltc_mode_symmetric_alg_t modeAs,
+                                   uint32_t size,
+                                   const uint8_t *key1,
+                                   const uint8_t *key2)
+{
+    /* all but OFB, size must be 8-byte multiple */
+    if ((modeAs != kLTC_ModeOFB) && ((size < 8u) || (size % 8u)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if ((key1 == NULL) || (key2 == NULL))
+    {
+        return kStatus_InvalidArgument;
+    }
+    return kStatus_Success;
+}
+
+static status_t ltc_3des_process(LTC_Type *base,
+                                 const uint8_t *input,
+                                 uint8_t *output,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE],
+                                 ltc_mode_symmetric_alg_t modeAs,
+                                 ltc_mode_encrypt_t modeEnc)
+{
+    status_t retval;
+    uint8_t key[LTC_DES_KEY_SIZE * 3];
+    uint8_t keySize = LTC_DES_KEY_SIZE * 2;
+
+    retval = ltc_3des_check_input_args(modeAs, size, key1, key2);
+    if (kStatus_Success != retval)
+    {
+        return retval;
+    }
+
+    ltc_memcpy(&key[0], &key1[0], LTC_DES_KEY_SIZE);
+    ltc_memcpy(&key[LTC_DES_KEY_SIZE], &key2[0], LTC_DES_KEY_SIZE);
+    if (key3)
+    {
+        ltc_memcpy(&key[LTC_DES_KEY_SIZE * 2], &key3[0], LTC_DES_KEY_SIZE);
+        keySize = sizeof(key);
+    }
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, &key[0], keySize, kLTC_Algorithm3DES, modeAs, modeEnc);
+
+    if ((modeAs != kLTC_ModeECB))
+    {
+        ltc_set_context(base, iv, LTC_DES_IV_SIZE, 0);
+    }
+
+    /* Process data and return status. */
+    retval = ltc_process_message_in_sessions(base, input, size, output);
+    ltc_clear_all(base, false);
+    return retval;
+}
+/*******************************************************************************
+ * DES / 3DES Code public
+ ******************************************************************************/
+status_t LTC_DES_EncryptEcb(
+    LTC_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, uint32_t size, const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process(base, plaintext, ciphertext, size, NULL, key, kLTC_ModeECB, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES_DecryptEcb(
+    LTC_Type *base, const uint8_t *ciphertext, uint8_t *plaintext, uint32_t size, const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process(base, ciphertext, plaintext, size, NULL, key, kLTC_ModeECB, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES_EncryptCbc(LTC_Type *base,
+                            const uint8_t *plaintext,
+                            uint8_t *ciphertext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_DES_IV_SIZE],
+                            const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process(base, plaintext, ciphertext, size, iv, key, kLTC_ModeCBC, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES_DecryptCbc(LTC_Type *base,
+                            const uint8_t *ciphertext,
+                            uint8_t *plaintext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_DES_IV_SIZE],
+                            const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process(base, ciphertext, plaintext, size, iv, key, kLTC_ModeCBC, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES_EncryptCfb(LTC_Type *base,
+                            const uint8_t *plaintext,
+                            uint8_t *ciphertext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_DES_IV_SIZE],
+                            const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process(base, plaintext, ciphertext, size, iv, key, kLTC_ModeCFB, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES_DecryptCfb(LTC_Type *base,
+                            const uint8_t *ciphertext,
+                            uint8_t *plaintext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_DES_IV_SIZE],
+                            const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process(base, ciphertext, plaintext, size, iv, key, kLTC_ModeCFB, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES_EncryptOfb(LTC_Type *base,
+                            const uint8_t *plaintext,
+                            uint8_t *ciphertext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_DES_IV_SIZE],
+                            const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process(base, plaintext, ciphertext, size, iv, key, kLTC_ModeOFB, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES_DecryptOfb(LTC_Type *base,
+                            const uint8_t *ciphertext,
+                            uint8_t *plaintext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_DES_IV_SIZE],
+                            const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process(base, ciphertext, plaintext, size, iv, key, kLTC_ModeOFB, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES2_EncryptEcb(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, plaintext, ciphertext, size, NULL, key1, key2, NULL, kLTC_ModeECB, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES3_EncryptEcb(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, plaintext, ciphertext, size, NULL, key1, key2, key3, kLTC_ModeECB, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES2_DecryptEcb(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, ciphertext, plaintext, size, NULL, key1, key2, NULL, kLTC_ModeECB, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES3_DecryptEcb(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, ciphertext, plaintext, size, NULL, key1, key2, key3, kLTC_ModeECB, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES2_EncryptCbc(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, plaintext, ciphertext, size, iv, key1, key2, NULL, kLTC_ModeCBC, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES3_EncryptCbc(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, plaintext, ciphertext, size, iv, key1, key2, key3, kLTC_ModeCBC, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES2_DecryptCbc(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, ciphertext, plaintext, size, iv, key1, key2, NULL, kLTC_ModeCBC, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES3_DecryptCbc(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, ciphertext, plaintext, size, iv, key1, key2, key3, kLTC_ModeCBC, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES2_EncryptCfb(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, plaintext, ciphertext, size, iv, key1, key2, NULL, kLTC_ModeCFB, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES3_EncryptCfb(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, plaintext, ciphertext, size, iv, key1, key2, key3, kLTC_ModeCFB, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES2_DecryptCfb(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, ciphertext, plaintext, size, iv, key1, key2, NULL, kLTC_ModeCFB, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES3_DecryptCfb(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, ciphertext, plaintext, size, iv, key1, key2, key3, kLTC_ModeCFB, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES2_EncryptOfb(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, plaintext, ciphertext, size, iv, key1, key2, NULL, kLTC_ModeOFB, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES3_EncryptOfb(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, plaintext, ciphertext, size, iv, key1, key2, key3, kLTC_ModeOFB, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES2_DecryptOfb(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, ciphertext, plaintext, size, iv, key1, key2, NULL, kLTC_ModeOFB, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES3_DecryptOfb(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process(base, ciphertext, plaintext, size, iv, key1, key2, key3, kLTC_ModeOFB, kLTC_ModeDecrypt);
+}
+#endif /* FSL_FEATURE_LTC_HAS_DES */
+
+/*******************************************************************************
+ * HASH Definitions
+ ******************************************************************************/
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+#define LTC_SHA_BLOCK_SIZE 64                  /*!< SHA-1, SHA-224 & SHA-256 block size  */
+#define LTC_HASH_BLOCK_SIZE LTC_SHA_BLOCK_SIZE /*!< LTC hash block size  */
+
+enum _ltc_sha_digest_len
+{
+    kLTC_RunLenSha1 = 28u,
+    kLTC_OutLenSha1 = 20u,
+    kLTC_RunLenSha224 = 40u,
+    kLTC_OutLenSha224 = 28u,
+    kLTC_RunLenSha256 = 40u,
+    kLTC_OutLenSha256 = 32u,
+};
+#else
+#define LTC_HASH_BLOCK_SIZE LTC_AES_BLOCK_SIZE /*!< LTC hash block size  */
+#endif                                         /* FSL_FEATURE_LTC_HAS_SHA */
+
+/*! Internal states of the HASH creation process */
+typedef enum _ltc_hash_algo_state
+{
+    kLTC_HashInit = 1u, /*!< Key in the HASH context is the input key. */
+    kLTC_HashUpdate,    /*!< HASH context has algorithm specific context: MAC, K2 and K3 (XCBC-MAC), MAC and L (CMAC),
+                           running digest (MDHA). Key in the HASH context is the derived key. */
+} ltc_hash_algo_state_t;
+
+/*! 16/64-byte block represented as byte array or 4/16 32-bit words */
+typedef union _ltc_hash_block
+{
+    uint32_t w[LTC_HASH_BLOCK_SIZE / 4]; /*!< array of 32-bit words */
+    uint8_t b[LTC_HASH_BLOCK_SIZE];      /*!< byte array */
+} ltc_hash_block_t;
+
+/*! Definitions of indexes into hash context array */
+typedef enum _ltc_hash_ctx_indexes
+{
+    kLTC_HashCtxKeyStartIdx = 12, /*!< context word array index where key is stored */
+    kLTC_HashCtxKeySize = 20,     /*!< context word array index where key size is stored */
+    kLTC_HashCtxNumWords = 21,    /*!< number of context array 32-bit words  */
+} ltc_hash_ctx_indexes;
+
+typedef struct _ltc_hash_ctx_internal
+{
+    ltc_hash_block_t blk; /*!< memory buffer. only full 64/16-byte blocks are written to LTC during hash updates */
+    uint32_t blksz;       /*!< number of valid bytes in memory buffer */
+    LTC_Type *base;       /*!< LTC peripheral base address */
+    ltc_hash_algo_t algo; /*!< selected algorithm from the set of supported algorithms in ltc_drv_hash_algo */
+    ltc_hash_algo_state_t state;         /*!< finite machine state of the hash software process */
+    uint32_t word[kLTC_HashCtxNumWords]; /*!< LTC module context that needs to be saved/restored between LTC jobs */
+} ltc_hash_ctx_internal_t;
+
+/*******************************************************************************
+ * HASH Code static
+ ******************************************************************************/
+static status_t ltc_hash_check_input_alg(ltc_hash_algo_t algo)
+{
+    if ((algo != kLTC_XcbcMac) && (algo != kLTC_Cmac)
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+        && (algo != kLTC_Sha1) && (algo != kLTC_Sha224) && (algo != kLTC_Sha256)
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+            )
+    {
+        return kStatus_InvalidArgument;
+    }
+    return kStatus_Success;
+}
+
+static inline bool ltc_hash_alg_is_cmac(ltc_hash_algo_t algo)
+{
+    return ((algo == kLTC_XcbcMac) || (algo == kLTC_Cmac));
+}
+
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+static inline bool ltc_hash_alg_is_sha(ltc_hash_algo_t algo)
+{
+    return ((algo == kLTC_Sha1) || (algo == kLTC_Sha224) || (algo == kLTC_Sha256));
+}
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+
+static status_t ltc_hash_check_input_args(
+    LTC_Type *base, ltc_hash_ctx_t *ctx, ltc_hash_algo_t algo, const uint8_t *key, uint32_t keySize)
+{
+    /* Check validity of input algorithm */
+    if (kStatus_Success != ltc_hash_check_input_alg(algo))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if ((NULL == ctx) || (NULL == base))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (ltc_hash_alg_is_cmac(algo))
+    {
+        if ((NULL == key) || (!ltc_check_key_size(keySize)))
+        {
+            return kStatus_InvalidArgument;
+        }
+    }
+
+    return kStatus_Success;
+}
+
+static status_t ltc_hash_check_context(ltc_hash_ctx_internal_t *ctxInternal, const uint8_t *data)
+{
+    if ((NULL == data) || (NULL == ctxInternal) || (NULL == ctxInternal->base) ||
+        (kStatus_Success != ltc_hash_check_input_alg(ctxInternal->algo)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    return kStatus_Success;
+}
+
+static uint32_t ltc_hash_algo2mode(ltc_hash_algo_t algo, ltc_mode_algorithm_state_t asMode, uint32_t *algOutSize)
+{
+    uint32_t modeReg = 0u;
+    uint32_t outSize = 0u;
+
+    /* Set LTC algorithm */
+    switch (algo)
+    {
+        case kLTC_XcbcMac:
+            modeReg = (uint32_t)kLTC_AlgorithmAES | (uint32_t)kLTC_ModeXCBCMAC;
+            outSize = 16u;
+            break;
+        case kLTC_Cmac:
+            modeReg = (uint32_t)kLTC_AlgorithmAES | (uint32_t)kLTC_ModeCMAC;
+            outSize = 16u;
+            break;
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+        case kLTC_Sha1:
+            modeReg = (uint32_t)kLTC_AlgorithmSHA1;
+            outSize = kLTC_OutLenSha1;
+            break;
+        case kLTC_Sha224:
+            modeReg = (uint32_t)kLTC_AlgorithmSHA224;
+            outSize = kLTC_OutLenSha224;
+            break;
+        case kLTC_Sha256:
+            modeReg = (uint32_t)kLTC_AlgorithmSHA256;
+            outSize = kLTC_OutLenSha256;
+            break;
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+        default:
+            break;
+    }
+
+    modeReg |= (uint32_t)asMode;
+    if (algOutSize)
+    {
+        *algOutSize = outSize;
+    }
+
+    return modeReg;
+}
+
+static void ltc_hash_engine_init(ltc_hash_ctx_internal_t *ctx)
+{
+    uint8_t *key;
+    uint32_t keySize;
+    LTC_Type *base;
+    ltc_mode_symmetric_alg_t algo;
+
+    base = ctx->base;
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+    if (ltc_hash_alg_is_cmac(ctx->algo))
+    {
+#endif  /* FSL_FEATURE_LTC_HAS_SHA */
+        /*
+         *  word[kLtcCmacCtxKeySize] = key_length
+         *  word[1-8] = key
+         */
+        keySize = ctx->word[kLTC_HashCtxKeySize];
+        key = (uint8_t *)&ctx->word[kLTC_HashCtxKeyStartIdx];
+
+        /* set LTC mode register to INITIALIZE */
+        algo = (ctx->algo == kLTC_XcbcMac) ? kLTC_ModeXCBCMAC : kLTC_ModeCMAC;
+        ltc_symmetric_init(base, key, keySize, kLTC_AlgorithmAES, algo, kLTC_ModeEncrypt);
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+    }
+    else if (ltc_hash_alg_is_sha(ctx->algo))
+    {
+        /* Clear internal register states. */
+        base->CW = (uint32_t)kLTC_ClearAll;
+
+        /* Set byte swap on for several registers we will be reading and writing
+         * user data to/from. */
+        base->CTL |= kLTC_CtrlSwapAll;
+    }
+    else
+    {
+        /* do nothing in this case */
+    }
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+}
+
+static void ltc_hash_save_context(ltc_hash_ctx_internal_t *ctx)
+{
+    uint32_t sz;
+    LTC_Type *base;
+
+    base = ctx->base;
+    /* Get context size */
+    switch (ctx->algo)
+    {
+        case kLTC_XcbcMac:
+            /*
+            *  word[0-3] = mac
+            *  word[3-7] = k3
+            *  word[8-11] = k2
+            *  word[kLtcCmacCtxKeySize] = keySize
+            */
+            sz = 12 * sizeof(uint32_t);
+            break;
+        case kLTC_Cmac:
+            /*
+            *  word[0-3] = mac
+            *  word[3-7] = L */
+            sz = 8 * sizeof(uint32_t);
+            break;
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+        case kLTC_Sha1:
+            sz = (kLTC_RunLenSha1);
+            break;
+        case kLTC_Sha224:
+            sz = (kLTC_RunLenSha224);
+            break;
+        case kLTC_Sha256:
+            sz = (kLTC_RunLenSha256);
+            break;
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+        default:
+            sz = 0;
+            break;
+    }
+
+    ltc_get_context(base, (uint8_t *)&ctx->word[0], sz, 0);
+
+    if (true == ltc_hash_alg_is_cmac(ctx->algo))
+    {
+        /* word[12-19] = key */
+        ltc_get_key(base, (uint8_t *)&ctx->word[kLTC_HashCtxKeyStartIdx], ctx->word[kLTC_HashCtxKeySize]);
+    }
+}
+
+static void ltc_hash_restore_context(ltc_hash_ctx_internal_t *ctx)
+{
+    uint32_t sz;
+    uint32_t keySize;
+    LTC_Type *base;
+
+    base = ctx->base;
+    /* Get context size */
+    switch (ctx->algo)
+    {
+        case kLTC_XcbcMac:
+            /*
+            *  word[0-3] = mac
+            *  word[3-7] = k3
+            *  word[8-11] = k2
+            *  word[kLtcCmacCtxKeySize] = keySize
+            */
+            sz = 12 * sizeof(uint32_t);
+            break;
+        case kLTC_Cmac:
+            /*
+            *  word[0-3] = mac
+            *  word[3-7] = L */
+            sz = 8 * sizeof(uint32_t);
+            break;
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+        case kLTC_Sha1:
+            sz = (kLTC_RunLenSha1);
+            break;
+        case kLTC_Sha224:
+            sz = (kLTC_RunLenSha224);
+            break;
+        case kLTC_Sha256:
+            sz = (kLTC_RunLenSha256);
+            break;
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+        default:
+            sz = 0;
+            break;
+    }
+
+    ltc_set_context(base, (const uint8_t *)&ctx->word[0], sz, 0);
+
+    if (ltc_hash_alg_is_cmac(ctx->algo))
+    {
+        /*
+         *  word[12-19] = key
+         *  word[kLtcCmacCtxKeySize] = keySize
+         */
+        base->CW = kLTC_ClearKey; /* clear Key and Key Size registers */
+
+        keySize = ctx->word[kLTC_HashCtxKeySize];
+        /* Write the key in place. */
+        ltc_set_key(base, (const uint8_t *)&ctx->word[kLTC_HashCtxKeyStartIdx], keySize);
+
+        /* Write the key size.  This must be done after writing the key, and this
+         * action locks the ability to modify the key registers. */
+        base->KS = keySize;
+    }
+}
+
+static void ltc_hash_prepare_context_switch(LTC_Type *base)
+{
+    base->CW = (uint32_t)kLTC_ClearDataSize | (uint32_t)kLTC_ClearMode;
+    base->STA = kLTC_StatusDoneIsr;
+}
+
+static uint32_t ltc_hash_get_block_size(ltc_hash_algo_t algo)
+{
+    if ((algo == kLTC_XcbcMac) || (algo == kLTC_Cmac))
+    {
+        return (uint32_t)LTC_AES_BLOCK_SIZE;
+    }
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+    else if ((algo == kLTC_Sha1) || (algo == kLTC_Sha224) || (algo == kLTC_Sha256))
+    {
+        return (uint32_t)LTC_SHA_BLOCK_SIZE;
+    }
+    else
+    {
+        return 0;
+    }
+#else
+    return 0;
+#endif
+}
+
+static void ltc_hash_block_to_ififo(LTC_Type *base, const ltc_hash_block_t *blk, uint32_t numBytes, uint32_t blockSize)
+{
+    uint32_t i = 0;
+    uint32_t words;
+
+    words = numBytes / 4u;
+    if (numBytes % 4u)
+    {
+        words++;
+    }
+
+    if (words > blockSize / 4u)
+    {
+        words = blockSize / 4u;
+    }
+
+    while (i < words)
+    {
+        if (0U == (base->FIFOSTA & LTC_FIFOSTA_IFF_MASK))
+        {
+            /* Copy data to the input FIFO. */
+            base->IFIFO = blk->w[i++];
+        }
+    }
+}
+
+static void ltc_hash_move_to_ififo(ltc_hash_ctx_internal_t *ctx,
+                                   const uint8_t *data,
+                                   uint32_t dataSize,
+                                   uint32_t blockSize)
+{
+    ltc_hash_block_t blkZero;
+    uint32_t i;
+
+    for (i = 0; i < ARRAY_SIZE(blkZero.w); i++)
+    {
+        blkZero.w[i] = 0;
+    }
+
+    while (dataSize)
+    {
+        if (dataSize >= blockSize)
+        {
+            ltc_memcpy(&ctx->blk, data, blockSize);
+            ltc_hash_block_to_ififo(ctx->base, &ctx->blk, blockSize, blockSize);
+            dataSize -= blockSize;
+            data += blockSize;
+        }
+        else
+        {
+            /* last incomplete 16/64-bytes block of this message chunk */
+            ltc_memcpy(&ctx->blk, &blkZero, sizeof(ctx->blk));
+            ltc_memcpy(&ctx->blk, data, dataSize);
+            ctx->blksz = dataSize;
+            dataSize = 0;
+        }
+    }
+}
+
+static status_t ltc_hash_merge_and_flush_buf(ltc_hash_ctx_internal_t *ctx,
+                                             const uint8_t *input,
+                                             uint32_t inputSize,
+                                             ltc_mode_t modeReg,
+                                             uint32_t blockSize,
+                                             uint32_t *consumedSize)
+{
+    uint32_t sz;
+    LTC_Type *base;
+    status_t status = kStatus_Success;
+
+    base = ctx->base;
+    sz = 0;
+    if (ctx->blksz)
+    {
+        sz = blockSize - ctx->blksz;
+        if (sz > inputSize)
+        {
+            sz = inputSize;
+        }
+        ltc_memcpy(ctx->blk.b + ctx->blksz, input, sz);
+        input += sz;
+        inputSize -= sz;
+        ctx->blksz += sz;
+
+        if (ctx->blksz == blockSize)
+        {
+            base->DS = blockSize;
+            ltc_hash_block_to_ififo(base, &ctx->blk, blockSize, blockSize);
+            ctx->blksz = 0;
+
+            status = ltc_wait(base);
+            if (kStatus_Success != status)
+            {
+                return status;
+            }
+
+            /* if there is still inputSize left, make sure LTC alg.state is set to UPDATE and continue */
+            if (inputSize)
+            {
+                /* set algorithm state to UPDATE */
+                modeReg &= ~LTC_MD_AS_MASK;
+                modeReg |= kLTC_ModeUpdate;
+                base->MD = modeReg;
+            }
+        }
+    }
+    if (consumedSize)
+    {
+        *consumedSize = sz;
+    }
+    return status;
+}
+
+static status_t ltc_hash_move_rest_to_context(
+    ltc_hash_ctx_internal_t *ctx, const uint8_t *data, uint32_t dataSize, ltc_mode_t modeReg, uint32_t blockSize)
+{
+    status_t status = kStatus_Success;
+    ltc_hash_block_t blkZero;
+    uint32_t i;
+
+    /* make blkZero clear */
+    for (i = 0; i < ARRAY_SIZE(blkZero.w); i++)
+    {
+        blkZero.w[i] = 0;
+    }
+
+    while (dataSize)
+    {
+        if (dataSize > blockSize)
+        {
+            dataSize -= blockSize;
+            data += blockSize;
+        }
+        else
+        {
+            if (dataSize + ctx->blksz > blockSize)
+            {
+                uint32_t sz;
+                status = ltc_hash_merge_and_flush_buf(ctx, data, dataSize, modeReg, blockSize, &sz);
+                if (kStatus_Success != status)
+                {
+                    return status;
+                }
+                data += sz;
+                dataSize -= sz;
+            }
+            /* last incomplete 16/64-bytes block of this message chunk */
+            ltc_memcpy(&ctx->blk, &blkZero, blockSize);
+            ltc_memcpy(&ctx->blk, data, dataSize);
+            ctx->blksz = dataSize;
+            dataSize = 0;
+        }
+    }
+    return status;
+}
+
+static status_t ltc_hash_process_input_data(ltc_hash_ctx_internal_t *ctx,
+                                            const uint8_t *input,
+                                            uint32_t inputSize,
+                                            ltc_mode_t modeReg)
+{
+    uint32_t sz = 0;
+    LTC_Type *base;
+    uint32_t blockSize = 0;
+    status_t status = kStatus_Success;
+
+    blockSize = ltc_hash_get_block_size(ctx->algo);
+    base = ctx->base;
+
+    /* fill context struct blk and flush to LTC ififo in case it is full block */
+    status = ltc_hash_merge_and_flush_buf(ctx, input, inputSize, modeReg, blockSize, &sz);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+    input += sz;
+    inputSize -= sz;
+
+    /* if there is still more than or equal to 16 bytes, move each 16 bytes through LTC */
+    sz = LTC_FIFO_SZ_MAX_DOWN_ALGN;
+    while (inputSize)
+    {
+        if (inputSize < sz)
+        {
+            uint32_t lastSize;
+
+            lastSize = inputSize % blockSize;
+            if (lastSize == 0)
+            {
+                lastSize = blockSize;
+            }
+            inputSize -= lastSize;
+            if (inputSize)
+            {
+                /* move all complete blocks to ififo. */
+                base->DS = inputSize;
+                ltc_hash_move_to_ififo(ctx, input, inputSize, blockSize);
+
+                status = ltc_wait(base);
+                if (kStatus_Success != status)
+                {
+                    return status;
+                }
+
+                input += inputSize;
+            }
+            /* keep last (in)complete 16-bytes block in context struct. */
+            /* when 3rd argument of cmac_move_to_ififo() is <= 16 bytes, it only stores the data to context struct */
+            status = ltc_hash_move_rest_to_context(ctx, input, lastSize, modeReg, blockSize);
+            if (kStatus_Success != status)
+            {
+                return status;
+            }
+            inputSize = 0;
+        }
+        else
+        {
+            base->DS = sz;
+            ltc_hash_move_to_ififo(ctx, input, sz, blockSize);
+            inputSize -= sz;
+            input += sz;
+
+            status = ltc_wait(base);
+            if (kStatus_Success != status)
+            {
+                return status;
+            }
+
+            /* set algorithm state to UPDATE */
+            modeReg &= ~LTC_MD_AS_MASK;
+            modeReg |= kLTC_ModeUpdate;
+            base->MD = modeReg;
+        }
+    } /* end while */
+
+    return status;
+}
+
+/*******************************************************************************
+ * HASH Code public
+ ******************************************************************************/
+status_t LTC_HASH_Init(LTC_Type *base, ltc_hash_ctx_t *ctx, ltc_hash_algo_t algo, const uint8_t *key, uint32_t keySize)
+{
+    status_t ret;
+    ltc_hash_ctx_internal_t *ctxInternal;
+    uint32_t i;
+
+    ret = ltc_hash_check_input_args(base, ctx, algo, key, keySize);
+    if (ret != kStatus_Success)
+    {
+        return ret;
+    }
+
+    /* set algorithm in context struct for later use */
+    ctxInternal = (ltc_hash_ctx_internal_t *)ctx;
+    ctxInternal->algo = algo;
+    for (i = 0; i < kLTC_HashCtxNumWords; i++)
+    {
+        ctxInternal->word[i] = 0u;
+    }
+
+    /* Steps required only using AES engine */
+    if (ltc_hash_alg_is_cmac(algo))
+    {
+        /* store input key and key length in context struct for later use */
+        ctxInternal->word[kLTC_HashCtxKeySize] = keySize;
+        ltc_memcpy(&ctxInternal->word[kLTC_HashCtxKeyStartIdx], key, keySize);
+    }
+    ctxInternal->blksz = 0u;
+    for (i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++)
+    {
+        ctxInternal->blk.w[0] = 0u;
+    }
+    ctxInternal->state = kLTC_HashInit;
+    ctxInternal->base = base;
+
+    return kStatus_Success;
+}
+
+status_t LTC_HASH_Update(ltc_hash_ctx_t *ctx, const uint8_t *input, uint32_t inputSize)
+{
+    bool isUpdateState;
+    ltc_mode_t modeReg = 0; /* read and write LTC mode register */
+    LTC_Type *base;
+    status_t status;
+    ltc_hash_ctx_internal_t *ctxInternal;
+    uint32_t blockSize;
+
+    ctxInternal = (ltc_hash_ctx_internal_t *)ctx;
+    status = ltc_hash_check_context(ctxInternal, input);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    base = ctxInternal->base;
+    blockSize = ltc_hash_get_block_size(ctxInternal->algo);
+    /* if we are still less than 64 bytes, keep only in context */
+    if ((ctxInternal->blksz + inputSize) <= blockSize)
+    {
+        ltc_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize);
+        ctxInternal->blksz += inputSize;
+        return status;
+    }
+    else
+    {
+        isUpdateState = ctxInternal->state == kLTC_HashUpdate;
+        if (ctxInternal->state == kLTC_HashInit)
+        {
+            /* set LTC mode register to INITIALIZE job */
+            ltc_hash_engine_init(ctxInternal);
+
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+            if (ltc_hash_alg_is_cmac(ctxInternal->algo))
+            {
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+                ctxInternal->state = kLTC_HashUpdate;
+                isUpdateState = true;
+                base->DS = 0u;
+                status = ltc_wait(base);
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+            }
+            else
+            {
+                /* Set the proper block and algorithm mode. */
+                modeReg = ltc_hash_algo2mode(ctxInternal->algo, kLTC_ModeInit, NULL);
+                base->MD = modeReg;
+
+                ctxInternal->state = kLTC_HashUpdate;
+                status = ltc_hash_process_input_data(ctxInternal, input, inputSize, modeReg);
+                ltc_hash_save_context(ctxInternal);
+            }
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+        }
+        else if (isUpdateState)
+        {
+            /* restore LTC context from context struct */
+            ltc_hash_restore_context(ctxInternal);
+        }
+        else
+        {
+            /* nothing special at this place */
+        }
+    }
+
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    if (isUpdateState)
+    {
+        /* set LTC mode register to UPDATE job */
+        ltc_hash_prepare_context_switch(base);
+        base->CW = kLTC_ClearDataSize;
+        modeReg = ltc_hash_algo2mode(ctxInternal->algo, kLTC_ModeUpdate, NULL);
+        base->MD = modeReg;
+
+        /* process input data and save LTC context to context structure */
+        status = ltc_hash_process_input_data(ctxInternal, input, inputSize, modeReg);
+        ltc_hash_save_context(ctxInternal);
+    }
+    ltc_clear_all(base, false);
+    return status;
+}
+
+status_t LTC_HASH_Finish(ltc_hash_ctx_t *ctx, uint8_t *output, uint32_t *outputSize)
+{
+    ltc_mode_t modeReg; /* read and write LTC mode register */
+    LTC_Type *base;
+    uint32_t algOutSize = 0;
+    status_t status;
+    ltc_hash_ctx_internal_t *ctxInternal;
+    uint32_t *ctxW;
+    uint32_t i;
+
+    ctxInternal = (ltc_hash_ctx_internal_t *)ctx;
+    status = ltc_hash_check_context(ctxInternal, output);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    base = ctxInternal->base;
+    ltc_hash_prepare_context_switch(base);
+
+    base->CW = kLTC_ClearDataSize;
+    if (ctxInternal->state == kLTC_HashInit)
+    {
+        ltc_hash_engine_init(ctxInternal);
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+        if (ltc_hash_alg_is_cmac(ctxInternal->algo))
+        {
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+            base->DS = 0u;
+            status = ltc_wait(base);
+            if (kStatus_Success != status)
+            {
+                return status;
+            }
+            modeReg = ltc_hash_algo2mode(ctxInternal->algo, kLTC_ModeFinalize, &algOutSize);
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+        }
+        else
+        {
+            modeReg = ltc_hash_algo2mode(ctxInternal->algo, kLTC_ModeInitFinal, &algOutSize);
+        }
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+        base->MD = modeReg;
+    }
+    else
+    {
+        modeReg = ltc_hash_algo2mode(ctxInternal->algo, kLTC_ModeFinalize, &algOutSize);
+        base->MD = modeReg;
+
+        /* restore LTC context from context struct */
+        ltc_hash_restore_context(ctxInternal);
+    }
+
+    /* flush message last incomplete block, if there is any, or write zero to data size register. */
+    base->DS = ctxInternal->blksz;
+    ltc_hash_block_to_ififo(base, &ctxInternal->blk, ctxInternal->blksz, ltc_hash_get_block_size(ctxInternal->algo));
+    /* Wait for finish of the encryption */
+    status = ltc_wait(base);
+
+    if (outputSize)
+    {
+        if (algOutSize < *outputSize)
+        {
+            *outputSize = algOutSize;
+        }
+        else
+        {
+            algOutSize = *outputSize;
+        }
+    }
+
+    ltc_get_context(base, &output[0], algOutSize, 0u);
+
+    ctxW = (uint32_t *)ctx;
+    for (i = 0; i < LTC_HASH_CTX_SIZE; i++)
+    {
+        ctxW[i] = 0u;
+    }
+
+    ltc_clear_all(base, false);
+    return status;
+}
+
+status_t LTC_HASH(LTC_Type *base,
+                  ltc_hash_algo_t algo,
+                  const uint8_t *input,
+                  uint32_t inputSize,
+                  const uint8_t *key,
+                  uint32_t keySize,
+                  uint8_t *output,
+                  uint32_t *outputSize)
+{
+    status_t status;
+    ltc_hash_ctx_t ctx;
+
+    status = LTC_HASH_Init(base, &ctx, algo, key, keySize);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    status = LTC_HASH_Update(&ctx, input, inputSize);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    status = LTC_HASH_Finish(&ctx, output, outputSize);
+    return status;
+}
+
+/*******************************************************************************
+ * PKHA Code static
+ ******************************************************************************/
+#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA
+static status_t ltc_pkha_clear_regabne(LTC_Type *base, bool A, bool B, bool N, bool E)
+{
+    ltc_mode_t mode;
+
+    /* Set the PKHA algorithm and the appropriate function. */
+    mode = (uint32_t)kLTC_AlgorithmPKHA | 1U;
+
+    /* Set ram area to clear. Clear all. */
+    if (A)
+    {
+        mode |= 1U << 19U;
+    }
+    if (B)
+    {
+        mode |= 1U << 18U;
+    }
+    if (N)
+    {
+        mode |= 1U << 16U;
+    }
+    if (E)
+    {
+        mode |= 1U << 17U;
+    }
+
+    /* Write the mode register to the hardware.
+     * NOTE: This will begin the operation. */
+    base->MDPK = mode;
+
+    /* Wait for 'done' */
+    return ltc_wait(base);
+}
+
+static void ltc_pkha_default_parms(ltc_pkha_mode_params_t *params)
+{
+    params->func = (ltc_pkha_func_t)0;
+    params->arithType = kLTC_PKHA_IntegerArith;
+    params->montFormIn = kLTC_PKHA_NormalValue;
+    params->montFormOut = kLTC_PKHA_NormalValue;
+    params->srcReg = kLTC_PKHA_RegAll;
+    params->srcQuad = kLTC_PKHA_Quad0;
+    params->dstReg = kLTC_PKHA_RegAll;
+    params->dstQuad = kLTC_PKHA_Quad0;
+    params->equalTime = kLTC_PKHA_NoTimingEqualized;
+    params->r2modn = kLTC_PKHA_CalcR2;
+}
+
+static void ltc_pkha_write_word(LTC_Type *base, ltc_pkha_reg_area_t reg, uint8_t index, uint32_t data)
+{
+    switch (reg)
+    {
+        case kLTC_PKHA_RegA:
+            base->PKA[index] = data;
+            break;
+
+        case kLTC_PKHA_RegB:
+            base->PKB[index] = data;
+            break;
+
+        case kLTC_PKHA_RegN:
+            base->PKN[index] = data;
+            break;
+
+        case kLTC_PKHA_RegE:
+            base->PKE[index] = data;
+            break;
+
+        default:
+            break;
+    }
+}
+
+static uint32_t ltc_pkha_read_word(LTC_Type *base, ltc_pkha_reg_area_t reg, uint8_t index)
+{
+    uint32_t retval;
+
+    switch (reg)
+    {
+        case kLTC_PKHA_RegA:
+            retval = base->PKA[index];
+            break;
+
+        case kLTC_PKHA_RegB:
+            retval = base->PKB[index];
+            break;
+
+        case kLTC_PKHA_RegN:
+            retval = base->PKN[index];
+            break;
+
+        case kLTC_PKHA_RegE:
+            retval = base->PKE[index];
+            break;
+
+        default:
+            retval = 0;
+            break;
+    }
+    return retval;
+}
+
+static status_t ltc_pkha_write_reg(
+    LTC_Type *base, ltc_pkha_reg_area_t reg, uint8_t quad, const uint8_t *data, uint16_t dataSize)
+{
+    /* Select the word-based start index for each quadrant of 64 bytes. */
+    uint8_t startIndex = (quad * 16u);
+    uint32_t outWord;
+
+    while (dataSize > 0)
+    {
+        if (dataSize >= sizeof(uint32_t))
+        {
+            ltc_pkha_write_word(base, reg, startIndex++, ltc_get_word_from_unaligned(data));
+            dataSize -= sizeof(uint32_t);
+            data += sizeof(uint32_t);
+        }
+        else /* (dataSize > 0) && (dataSize < 4) */
+        {
+            outWord = 0;
+            ltc_memcpy(&outWord, data, dataSize);
+            ltc_pkha_write_word(base, reg, startIndex, outWord);
+            dataSize = 0;
+        }
+    }
+
+    return kStatus_Success;
+}
+
+static void ltc_pkha_read_reg(LTC_Type *base, ltc_pkha_reg_area_t reg, uint8_t quad, uint8_t *data, uint16_t dataSize)
+{
+    /* Select the word-based start index for each quadrant of 64 bytes. */
+    uint8_t startIndex = (quad * 16u);
+    uint16_t calcSize;
+    uint32_t word;
+
+    while (dataSize > 0)
+    {
+        word = ltc_pkha_read_word(base, reg, startIndex++);
+
+        calcSize = (dataSize >= sizeof(uint32_t)) ? sizeof(uint32_t) : dataSize;
+        ltc_memcpy(data, &word, calcSize);
+
+        data += calcSize;
+        dataSize -= calcSize;
+    }
+}
+
+static void ltc_pkha_init_data(LTC_Type *base,
+                               const uint8_t *A,
+                               uint16_t sizeA,
+                               const uint8_t *B,
+                               uint16_t sizeB,
+                               const uint8_t *N,
+                               uint16_t sizeN,
+                               const uint8_t *E,
+                               uint16_t sizeE)
+{
+    uint32_t clearMask = kLTC_ClearMode; /* clear Mode Register */
+
+    /* Clear internal register states. */
+    if (sizeA)
+    {
+        clearMask |= kLTC_ClearPkhaSizeA;
+    }
+    if (sizeB)
+    {
+        clearMask |= kLTC_ClearPkhaSizeB;
+    }
+    if (sizeN)
+    {
+        clearMask |= kLTC_ClearPkhaSizeN;
+    }
+    if (sizeE)
+    {
+        clearMask |= kLTC_ClearPkhaSizeE;
+    }
+
+    base->CW = clearMask;
+    base->STA = kLTC_StatusDoneIsr;
+    ltc_pkha_clear_regabne(base, A, B, N, E);
+
+    /* Write register sizes. */
+    /* Write modulus (N) and A and B register arguments. */
+    if (sizeN)
+    {
+        base->PKNSZ = sizeN;
+        if (N)
+        {
+            ltc_pkha_write_reg(base, kLTC_PKHA_RegN, 0, N, sizeN);
+        }
+    }
+
+    if (sizeA)
+    {
+        base->PKASZ = sizeA;
+        if (A)
+        {
+            ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 0, A, sizeA);
+        }
+    }
+
+    if (sizeB)
+    {
+        base->PKBSZ = sizeB;
+        if (B)
+        {
+            ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 0, B, sizeB);
+        }
+    }
+
+    if (sizeE)
+    {
+        base->PKESZ = sizeE;
+        if (E)
+        {
+            ltc_pkha_write_reg(base, kLTC_PKHA_RegE, 0, E, sizeE);
+        }
+    }
+}
+
+static void ltc_pkha_mode_set_src_reg_copy(ltc_mode_t *outMode, ltc_pkha_reg_area_t reg)
+{
+    int i = 0;
+
+    do
+    {
+        reg = (ltc_pkha_reg_area_t)(((uint32_t)reg) >> 1u);
+        i++;
+    } while (reg);
+
+    i = 4 - i;
+    /* Source register must not be E. */
+    if (i != 2)
+    {
+        *outMode |= ((uint32_t)i << 17u);
+    }
+}
+
+static void ltc_pkha_mode_set_dst_reg_copy(ltc_mode_t *outMode, ltc_pkha_reg_area_t reg)
+{
+    int i = 0;
+
+    do
+    {
+        reg = (ltc_pkha_reg_area_t)(((uint32_t)reg) >> 1u);
+        i++;
+    } while (reg);
+
+    i = 4 - i;
+    *outMode |= ((uint32_t)i << 10u);
+}
+
+static void ltc_pkha_mode_set_src_seg_copy(ltc_mode_t *outMode, const ltc_pkha_quad_area_t quad)
+{
+    *outMode |= ((uint32_t)quad << 8u);
+}
+
+static void ltc_pkha_mode_set_dst_seg_copy(ltc_mode_t *outMode, const ltc_pkha_quad_area_t quad)
+{
+    *outMode |= ((uint32_t)quad << 6u);
+}
+
+/*!
+ * @brief Starts the PKHA operation.
+ *
+ * This function starts an operation configured by the params parameter.
+ *
+ * @param base LTC peripheral base address
+ * @param params Configuration structure containing all settings required for PKHA operation.
+ */
+static status_t ltc_pkha_init_mode(LTC_Type *base, const ltc_pkha_mode_params_t *params)
+{
+    ltc_mode_t modeReg;
+    status_t retval;
+
+    /* Set the PKHA algorithm and the appropriate function. */
+    modeReg = kLTC_AlgorithmPKHA;
+    modeReg |= (uint32_t)params->func;
+
+    if ((params->func == kLTC_PKHA_CopyMemSizeN) || (params->func == kLTC_PKHA_CopyMemSizeSrc))
+    {
+        /* Set source and destination registers and quads. */
+        ltc_pkha_mode_set_src_reg_copy(&modeReg, params->srcReg);
+        ltc_pkha_mode_set_dst_reg_copy(&modeReg, params->dstReg);
+        ltc_pkha_mode_set_src_seg_copy(&modeReg, params->srcQuad);
+        ltc_pkha_mode_set_dst_seg_copy(&modeReg, params->dstQuad);
+    }
+    else
+    {
+        /* Set the arithmetic type - integer or binary polynomial (F2m). */
+        modeReg |= ((uint32_t)params->arithType << 17u);
+
+        /* Set to use Montgomery form of inputs and/or outputs. */
+        modeReg |= ((uint32_t)params->montFormIn << 19u);
+        modeReg |= ((uint32_t)params->montFormOut << 18u);
+
+        /* Set to use pre-computed R2modN */
+        modeReg |= ((uint32_t)params->r2modn << 16u);
+    }
+
+    modeReg |= ((uint32_t)params->equalTime << 10u);
+
+    /* Write the mode register to the hardware.
+     * NOTE: This will begin the operation. */
+    base->MDPK = modeReg;
+
+    retval = ltc_wait(base);
+    return (retval);
+}
+
+static status_t ltc_pkha_modR2(
+    LTC_Type *base, const uint8_t *N, uint16_t sizeN, uint8_t *result, uint16_t *resultSize, ltc_pkha_f2m_t arithType)
+{
+    status_t status;
+    ltc_pkha_mode_params_t params;
+
+    ltc_pkha_default_parms(&params);
+    params.func = kLTC_PKHA_ArithModR2;
+    params.arithType = arithType;
+
+    ltc_pkha_init_data(base, NULL, 0, NULL, 0, N, sizeN, NULL, 0);
+    status = ltc_pkha_init_mode(base, &params);
+
+    if (status == kStatus_Success)
+    {
+        /* Read the result and size from register B0. */
+        if (resultSize && result)
+        {
+            *resultSize = base->PKBSZ;
+            /* Read the data from the result register into place. */
+            ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize);
+        }
+    }
+
+    return status;
+}
+
+static status_t ltc_pkha_modmul(LTC_Type *base,
+                                const uint8_t *A,
+                                uint16_t sizeA,
+                                const uint8_t *B,
+                                uint16_t sizeB,
+                                const uint8_t *N,
+                                uint16_t sizeN,
+                                uint8_t *result,
+                                uint16_t *resultSize,
+                                ltc_pkha_f2m_t arithType,
+                                ltc_pkha_montgomery_form_t montIn,
+                                ltc_pkha_montgomery_form_t montOut,
+                                ltc_pkha_timing_t equalTime)
+{
+    ltc_pkha_mode_params_t params;
+    status_t status;
+
+    if (arithType == kLTC_PKHA_IntegerArith)
+    {
+        if (LTC_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0)
+        {
+            return (kStatus_InvalidArgument);
+        }
+
+        if (LTC_PKHA_CompareBigNum(B, sizeB, N, sizeN) >= 0)
+        {
+            return (kStatus_InvalidArgument);
+        }
+    }
+
+    ltc_pkha_default_parms(&params);
+    params.func = kLTC_PKHA_ArithModMul;
+    params.arithType = arithType;
+    params.montFormIn = montIn;
+    params.montFormOut = montOut;
+    params.equalTime = equalTime;
+
+    ltc_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0);
+    status = ltc_pkha_init_mode(base, &params);
+
+    if (status == kStatus_Success)
+    {
+        /* Read the result and size from register B0. */
+        if (resultSize && result)
+        {
+            *resultSize = base->PKBSZ;
+            /* Read the data from the result register into place. */
+            ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize);
+        }
+    }
+
+    return status;
+}
+
+/*******************************************************************************
+ * PKHA Code public
+ ******************************************************************************/
+int LTC_PKHA_CompareBigNum(const uint8_t *a, size_t sizeA, const uint8_t *b, size_t sizeB)
+{
+    int retval;
+
+    /* skip zero msbytes - integer a */
+    if (sizeA)
+    {
+        while (0u == a[sizeA - 1])
+        {
+            sizeA--;
+        }
+    }
+
+    /* skip zero msbytes - integer b */
+    if (sizeB)
+    {
+        while (0u == b[sizeB - 1])
+        {
+            sizeB--;
+        }
+    }
+
+    if (sizeA > sizeB)
+    {
+        retval = 1;
+    } /* int a has more non-zero bytes, thus it is bigger than b */
+    else if (sizeA < sizeB)
+    {
+        retval = -1;
+    } /* int b has more non-zero bytes, thus it is bigger than a */
+    else if (sizeA == 0)
+    {
+        retval = 0;
+    } /* sizeA = sizeB = 0 */
+    else
+    {
+        int n;
+
+        n = sizeA - 1;
+        /* skip all equal bytes */
+        while ((n >= 0) && (a[n] == b[n]))
+        {
+            n--;
+        }
+        if (n < 0)
+        {
+            retval = 0;
+        }
+        else
+        {
+            retval = (a[n] > b[n]) ? 1 : -1;
+        }
+    }
+    return (retval);
+}
+
+status_t LTC_PKHA_NormalToMontgomery(LTC_Type *base,
+                                     const uint8_t *N,
+                                     uint16_t sizeN,
+                                     uint8_t *A,
+                                     uint16_t *sizeA,
+                                     uint8_t *B,
+                                     uint16_t *sizeB,
+                                     uint8_t *R2,
+                                     uint16_t *sizeR2,
+                                     ltc_pkha_timing_t equalTime,
+                                     ltc_pkha_f2m_t arithType)
+{
+    status_t status;
+
+    /* need to convert our Integer inputs into Montgomery format */
+    if (N && sizeN && R2 && sizeR2)
+    {
+        /* 1. R2 = MOD_R2(N) */
+        status = ltc_pkha_modR2(base, N, sizeN, R2, sizeR2, arithType);
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+
+        /* 2. A(Montgomery) = MOD_MUL_IM_OM(A, R2, N) */
+        if (A && sizeA)
+        {
+            status = ltc_pkha_modmul(base, A, *sizeA, R2, *sizeR2, N, sizeN, A, sizeA, arithType,
+                                     kLTC_PKHA_MontgomeryFormat, kLTC_PKHA_MontgomeryFormat, equalTime);
+            if (status != kStatus_Success)
+            {
+                return status;
+            }
+        }
+
+        /* 2. B(Montgomery) = MOD_MUL_IM_OM(B, R2, N) */
+        if (B && sizeB)
+        {
+            status = ltc_pkha_modmul(base, B, *sizeB, R2, *sizeR2, N, sizeN, B, sizeB, arithType,
+                                     kLTC_PKHA_MontgomeryFormat, kLTC_PKHA_MontgomeryFormat, equalTime);
+            if (status != kStatus_Success)
+            {
+                return status;
+            }
+        }
+
+        ltc_clear_all(base, true);
+    }
+    else
+    {
+        status = kStatus_InvalidArgument;
+    }
+
+    return status;
+}
+
+status_t LTC_PKHA_MontgomeryToNormal(LTC_Type *base,
+                                     const uint8_t *N,
+                                     uint16_t sizeN,
+                                     uint8_t *A,
+                                     uint16_t *sizeA,
+                                     uint8_t *B,
+                                     uint16_t *sizeB,
+                                     ltc_pkha_timing_t equalTime,
+                                     ltc_pkha_f2m_t arithType)
+{
+    uint8_t one = 1;
+    status_t status = kStatus_InvalidArgument;
+
+    /* A = MOD_MUL_IM_OM(A(Montgomery), 1, N) */
+    if (A && sizeA)
+    {
+        status = ltc_pkha_modmul(base, A, *sizeA, &one, sizeof(one), N, sizeN, A, sizeA, arithType,
+                                 kLTC_PKHA_MontgomeryFormat, kLTC_PKHA_MontgomeryFormat, equalTime);
+        if (kStatus_Success != status)
+        {
+            return status;
+        }
+    }
+
+    /* B = MOD_MUL_IM_OM(B(Montgomery), 1, N) */
+    if (B && sizeB)
+    {
+        status = ltc_pkha_modmul(base, B, *sizeB, &one, sizeof(one), N, sizeN, B, sizeB, arithType,
+                                 kLTC_PKHA_MontgomeryFormat, kLTC_PKHA_MontgomeryFormat, equalTime);
+        if (kStatus_Success != status)
+        {
+            return status;
+        }
+    }
+
+    ltc_clear_all(base, true);
+    return status;
+}
+
+status_t LTC_PKHA_ModAdd(LTC_Type *base,
+                         const uint8_t *A,
+                         uint16_t sizeA,
+                         const uint8_t *B,
+                         uint16_t sizeB,
+                         const uint8_t *N,
+                         uint16_t sizeN,
+                         uint8_t *result,
+                         uint16_t *resultSize,
+                         ltc_pkha_f2m_t arithType)
+{
+    ltc_pkha_mode_params_t params;
+    status_t status;
+
+    if (arithType == kLTC_PKHA_IntegerArith)
+    {
+        if (LTC_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0)
+        {
+            return (kStatus_InvalidArgument);
+        }
+
+        if (LTC_PKHA_CompareBigNum(B, sizeB, N, sizeN) >= 0)
+        {
+            return (kStatus_InvalidArgument);
+        }
+    }
+
+    ltc_pkha_default_parms(&params);
+    params.func = kLTC_PKHA_ArithModAdd;
+    params.arithType = arithType;
+
+    ltc_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0);
+    status = ltc_pkha_init_mode(base, &params);
+
+    if (status == kStatus_Success)
+    {
+        /* Read the result and size from register B0. */
+        if (resultSize && result)
+        {
+            *resultSize = base->PKBSZ;
+            /* Read the data from the result register into place. */
+            ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize);
+        }
+    }
+
+    ltc_clear_all(base, true);
+    return status;
+}
+
+status_t LTC_PKHA_ModSub1(LTC_Type *base,
+                          const uint8_t *A,
+                          uint16_t sizeA,
+                          const uint8_t *B,
+                          uint16_t sizeB,
+                          const uint8_t *N,
+                          uint16_t sizeN,
+                          uint8_t *result,
+                          uint16_t *resultSize)
+{
+    ltc_pkha_mode_params_t params;
+    status_t status;
+
+    if (LTC_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0)
+    {
+        return (kStatus_InvalidArgument);
+    }
+
+    if (LTC_PKHA_CompareBigNum(B, sizeB, N, sizeN) >= 0)
+    {
+        return (kStatus_InvalidArgument);
+    }
+
+    ltc_pkha_default_parms(&params);
+    params.func = kLTC_PKHA_ArithModSub1;
+    ltc_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0);
+
+    status = ltc_pkha_init_mode(base, &params);
+
+    if (status == kStatus_Success)
+    {
+        /* Read the result and size from register B0. */
+        if (resultSize && result)
+        {
+            *resultSize = base->PKBSZ;
+            /* Read the data from the result register into place. */
+            ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize);
+        }
+    }
+
+    ltc_clear_all(base, true);
+    return status;
+}
+
+status_t LTC_PKHA_ModSub2(LTC_Type *base,
+                          const uint8_t *A,
+                          uint16_t sizeA,
+                          const uint8_t *B,
+                          uint16_t sizeB,
+                          const uint8_t *N,
+                          uint16_t sizeN,
+                          uint8_t *result,
+                          uint16_t *resultSize)
+{
+    ltc_pkha_mode_params_t params;
+    status_t status;
+
+    ltc_pkha_default_parms(&params);
+    params.func = kLTC_PKHA_ArithModSub2;
+
+    ltc_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0);
+    status = ltc_pkha_init_mode(base, &params);
+
+    if (status == kStatus_Success)
+    {
+        /* Read the result and size from register B0. */
+        if (resultSize && result)
+        {
+            *resultSize = base->PKBSZ;
+            /* Read the data from the result register into place. */
+            ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize);
+        }
+    }
+
+    ltc_clear_all(base, true);
+    return status;
+}
+
+status_t LTC_PKHA_ModMul(LTC_Type *base,
+                         const uint8_t *A,
+                         uint16_t sizeA,
+                         const uint8_t *B,
+                         uint16_t sizeB,
+                         const uint8_t *N,
+                         uint16_t sizeN,
+                         uint8_t *result,
+                         uint16_t *resultSize,
+                         ltc_pkha_f2m_t arithType,
+                         ltc_pkha_montgomery_form_t montIn,
+                         ltc_pkha_montgomery_form_t montOut,
+                         ltc_pkha_timing_t equalTime)
+{
+    status_t status;
+
+    status =
+        ltc_pkha_modmul(base, A, sizeA, B, sizeB, N, sizeN, result, resultSize, arithType, montIn, montOut, equalTime);
+
+    ltc_clear_all(base, true);
+    return status;
+}
+
+status_t LTC_PKHA_ModExp(LTC_Type *base,
+                         const uint8_t *A,
+                         uint16_t sizeA,
+                         const uint8_t *N,
+                         uint16_t sizeN,
+                         const uint8_t *E,
+                         uint16_t sizeE,
+                         uint8_t *result,
+                         uint16_t *resultSize,
+                         ltc_pkha_f2m_t arithType,
+                         ltc_pkha_montgomery_form_t montIn,
+                         ltc_pkha_timing_t equalTime)
+{
+    ltc_pkha_mode_params_t params;
+    status_t status;
+
+    if (arithType == kLTC_PKHA_IntegerArith)
+    {
+        if (LTC_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0)
+        {
+            return (kStatus_InvalidArgument);
+        }
+    }
+
+    ltc_pkha_default_parms(&params);
+    params.func = kLTC_PKHA_ArithModExp;
+    params.arithType = arithType;
+    params.montFormIn = montIn;
+    params.equalTime = equalTime;
+
+    ltc_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, E, sizeE);
+    status = ltc_pkha_init_mode(base, &params);
+
+    if (status == kStatus_Success)
+    {
+        /* Read the result and size from register B0. */
+        if (resultSize && result)
+        {
+            *resultSize = base->PKBSZ;
+            /* Read the data from the result register into place. */
+            ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize);
+        }
+    }
+
+    ltc_clear_all(base, true);
+    return status;
+}
+
+status_t LTC_PKHA_ModRed(LTC_Type *base,
+                         const uint8_t *A,
+                         uint16_t sizeA,
+                         const uint8_t *N,
+                         uint16_t sizeN,
+                         uint8_t *result,
+                         uint16_t *resultSize,
+                         ltc_pkha_f2m_t arithType)
+{
+    ltc_pkha_mode_params_t params;
+    status_t status;
+
+    ltc_pkha_default_parms(&params);
+    params.func = kLTC_PKHA_ArithModRed;
+    params.arithType = arithType;
+
+    ltc_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, NULL, 0);
+    status = ltc_pkha_init_mode(base, &params);
+
+    if (status == kStatus_Success)
+    {
+        /* Read the result and size from register B0. */
+        if (resultSize && result)
+        {
+            *resultSize = base->PKBSZ;
+            /* Read the data from the result register into place. */
+            ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize);
+        }
+    }
+
+    ltc_clear_all(base, true);
+    return status;
+}
+
+status_t LTC_PKHA_ModInv(LTC_Type *base,
+                         const uint8_t *A,
+                         uint16_t sizeA,
+                         const uint8_t *N,
+                         uint16_t sizeN,
+                         uint8_t *result,
+                         uint16_t *resultSize,
+                         ltc_pkha_f2m_t arithType)
+{
+    ltc_pkha_mode_params_t params;
+    status_t status;
+
+    /* A must be less than N -> LTC_PKHA_CompareBigNum() must return -1 */
+    if (arithType == kLTC_PKHA_IntegerArith)
+    {
+        if (LTC_PKHA_CompareBigNum(A, sizeA, N, sizeN) >= 0)
+        {
+            return (kStatus_InvalidArgument);
+        }
+    }
+
+    ltc_pkha_default_parms(&params);
+    params.func = kLTC_PKHA_ArithModInv;
+    params.arithType = arithType;
+
+    ltc_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, NULL, 0);
+    status = ltc_pkha_init_mode(base, &params);
+
+    if (status == kStatus_Success)
+    {
+        /* Read the result and size from register B0. */
+        if (resultSize && result)
+        {
+            *resultSize = base->PKBSZ;
+            /* Read the data from the result register into place. */
+            ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize);
+        }
+    }
+
+    ltc_clear_all(base, true);
+    return status;
+}
+
+status_t LTC_PKHA_ModR2(
+    LTC_Type *base, const uint8_t *N, uint16_t sizeN, uint8_t *result, uint16_t *resultSize, ltc_pkha_f2m_t arithType)
+{
+    status_t status;
+    status = ltc_pkha_modR2(base, N, sizeN, result, resultSize, arithType);
+    ltc_clear_all(base, true);
+    return status;
+}
+
+status_t LTC_PKHA_GCD(LTC_Type *base,
+                      const uint8_t *A,
+                      uint16_t sizeA,
+                      const uint8_t *N,
+                      uint16_t sizeN,
+                      uint8_t *result,
+                      uint16_t *resultSize,
+                      ltc_pkha_f2m_t arithType)
+{
+    ltc_pkha_mode_params_t params;
+    status_t status;
+
+    ltc_pkha_default_parms(&params);
+    params.func = kLTC_PKHA_ArithGcd;
+    params.arithType = arithType;
+
+    ltc_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, NULL, 0);
+    status = ltc_pkha_init_mode(base, &params);
+
+    if (status == kStatus_Success)
+    {
+        /* Read the result and size from register B0. */
+        if (resultSize && result)
+        {
+            *resultSize = base->PKBSZ;
+            /* Read the data from the result register into place. */
+            ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, result, *resultSize);
+        }
+    }
+
+    ltc_clear_all(base, true);
+    return status;
+}
+
+status_t LTC_PKHA_PrimalityTest(LTC_Type *base,
+                                const uint8_t *A,
+                                uint16_t sizeA,
+                                const uint8_t *B,
+                                uint16_t sizeB,
+                                const uint8_t *N,
+                                uint16_t sizeN,
+                                bool *res)
+{
+    uint8_t result;
+    ltc_pkha_mode_params_t params;
+    status_t status;
+
+    ltc_pkha_default_parms(&params);
+    params.func = kLTC_PKHA_ArithPrimalityTest;
+    ltc_pkha_init_data(base, A, sizeA, B, sizeB, N, sizeN, NULL, 0);
+    status = ltc_pkha_init_mode(base, &params);
+
+    if (status == kStatus_Success)
+    {
+        /* Read the data from the result register into place. */
+        ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 0, &result, 1);
+
+        *res = (bool)result;
+    }
+
+    ltc_clear_all(base, true);
+    return status;
+}
+
+status_t LTC_PKHA_ECC_PointAdd(LTC_Type *base,
+                               const ltc_pkha_ecc_point_t *A,
+                               const ltc_pkha_ecc_point_t *B,
+                               const uint8_t *N,
+                               const uint8_t *R2modN,
+                               const uint8_t *aCurveParam,
+                               const uint8_t *bCurveParam,
+                               uint8_t size,
+                               ltc_pkha_f2m_t arithType,
+                               ltc_pkha_ecc_point_t *result)
+{
+    ltc_pkha_mode_params_t params;
+    uint32_t clearMask;
+    status_t status;
+
+    ltc_pkha_default_parms(&params);
+    params.func = kLTC_PKHA_ArithEccAdd;
+    params.arithType = arithType;
+    params.r2modn = R2modN ? kLTC_PKHA_InputR2 : kLTC_PKHA_CalcR2;
+
+    clearMask = kLTC_ClearMode;
+
+    /* Clear internal register states. */
+    clearMask |= kLTC_ClearPkhaSizeA;
+    clearMask |= kLTC_ClearPkhaSizeB;
+    clearMask |= kLTC_ClearPkhaSizeN;
+    clearMask |= kLTC_ClearPkhaSizeE;
+
+    base->CW = clearMask;
+    base->STA = kLTC_StatusDoneIsr;
+    ltc_pkha_clear_regabne(base, true, true, true, false);
+
+    /* sizeN should be less than 64 bytes. */
+    base->PKNSZ = size;
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegN, 0, N, size);
+
+    base->PKASZ = size;
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 0, A->X, size);
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 1, A->Y, size);
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 3, aCurveParam, size);
+
+    base->PKBSZ = size;
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 0, bCurveParam, size);
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 1, B->X, size);
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 2, B->Y, size);
+    if (R2modN)
+    {
+        ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 3, R2modN, size);
+    }
+
+    status = ltc_pkha_init_mode(base, &params);
+
+    if (status == kStatus_Success)
+    {
+        /* Read the data from the result register into place. */
+        ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 1, result->X, size);
+        ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 2, result->Y, size);
+    }
+
+    ltc_clear_all(base, true);
+    return status;
+}
+
+status_t LTC_PKHA_ECC_PointDouble(LTC_Type *base,
+                                  const ltc_pkha_ecc_point_t *B,
+                                  const uint8_t *N,
+                                  const uint8_t *aCurveParam,
+                                  const uint8_t *bCurveParam,
+                                  uint8_t size,
+                                  ltc_pkha_f2m_t arithType,
+                                  ltc_pkha_ecc_point_t *result)
+{
+    ltc_pkha_mode_params_t params;
+    uint32_t clearMask;
+    status_t status;
+
+    ltc_pkha_default_parms(&params);
+    params.func = kLTC_PKHA_ArithEccDouble;
+    params.arithType = arithType;
+
+    clearMask = kLTC_ClearMode;
+
+    /* Clear internal register states. */
+    clearMask |= kLTC_ClearPkhaSizeA;
+    clearMask |= kLTC_ClearPkhaSizeB;
+    clearMask |= kLTC_ClearPkhaSizeN;
+    clearMask |= kLTC_ClearPkhaSizeE;
+
+    base->CW = clearMask;
+    base->STA = kLTC_StatusDoneIsr;
+    ltc_pkha_clear_regabne(base, true, true, true, false);
+
+    /* sizeN should be less than 64 bytes. */
+    base->PKNSZ = size;
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegN, 0, N, size);
+
+    base->PKASZ = size;
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 3, aCurveParam, size);
+
+    base->PKBSZ = size;
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 0, bCurveParam, size);
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 1, B->X, size);
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 2, B->Y, size);
+    status = ltc_pkha_init_mode(base, &params);
+
+    if (status == kStatus_Success)
+    {
+        /* Read the data from the result register into place. */
+        ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 1, result->X, size);
+        ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 2, result->Y, size);
+    }
+
+    ltc_clear_all(base, true);
+    return status;
+}
+
+status_t LTC_PKHA_ECC_PointMul(LTC_Type *base,
+                               const ltc_pkha_ecc_point_t *A,
+                               const uint8_t *E,
+                               uint8_t sizeE,
+                               const uint8_t *N,
+                               const uint8_t *R2modN,
+                               const uint8_t *aCurveParam,
+                               const uint8_t *bCurveParam,
+                               uint8_t size,
+                               ltc_pkha_timing_t equalTime,
+                               ltc_pkha_f2m_t arithType,
+                               ltc_pkha_ecc_point_t *result,
+                               bool *infinity)
+{
+    ltc_pkha_mode_params_t params;
+    uint32_t clearMask;
+    status_t status;
+
+    ltc_pkha_default_parms(&params);
+    params.func = kLTC_PKHA_ArithEccMul;
+    params.equalTime = equalTime;
+    params.arithType = arithType;
+    params.r2modn = R2modN ? kLTC_PKHA_InputR2 : kLTC_PKHA_CalcR2;
+
+    clearMask = kLTC_ClearMode;
+
+    /* Clear internal register states. */
+    clearMask |= kLTC_ClearPkhaSizeA;
+    clearMask |= kLTC_ClearPkhaSizeB;
+    clearMask |= kLTC_ClearPkhaSizeN;
+    clearMask |= kLTC_ClearPkhaSizeE;
+
+    base->CW = clearMask;
+    base->STA = kLTC_StatusDoneIsr;
+    ltc_pkha_clear_regabne(base, true, true, true, true);
+
+    /* sizeN should be less than 64 bytes. */
+    base->PKNSZ = size;
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegN, 0, N, size);
+
+    base->PKESZ = sizeE;
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegE, 0, E, sizeE);
+
+    base->PKASZ = size;
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 0, A->X, size);
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 1, A->Y, size);
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegA, 3, aCurveParam, size);
+
+    base->PKBSZ = size;
+    ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 0, bCurveParam, size);
+    if (R2modN)
+    {
+        ltc_pkha_write_reg(base, kLTC_PKHA_RegB, 1, R2modN, size);
+    }
+
+    status = ltc_pkha_init_mode(base, &params);
+
+    if (status == kStatus_Success)
+    {
+        /* Read the data from the result register into place. */
+        ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 1, result->X, size);
+        ltc_pkha_read_reg(base, kLTC_PKHA_RegB, 2, result->Y, size);
+
+        if (infinity)
+        {
+            *infinity = (bool)(base->STA & kLTC_StatusPublicKeyOpZero);
+        }
+    }
+
+    ltc_clear_all(base, true);
+    return status;
+}
+
+#endif /* FSL_FEATURE_LTC_HAS_PKHA */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc.h
new file mode 100644
index 00000000000..910ad7790f3
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc.h
@@ -0,0 +1,1575 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_LTC_H_
+#define _FSL_LTC_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*!
+ * @addtogroup ltc
+ * @{
+ */
+/*! @name Driver version */
+/*@{*/
+/*! @brief LTC driver version. Version 2.0.1.
+ *
+ * Current version: 2.0.1
+ *
+ * Change log:
+ * - Version 2.0.1
+ *   - fixed warning during g++ compilation
+ */
+#define FSL_LTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+/*! @} */
+
+/*******************************************************************************
+ * AES Definitions
+ *******************************************************************************/
+/*!
+ * @addtogroup ltc_driver_aes
+ * @{
+ */
+/*! AES block size in bytes */
+#define LTC_AES_BLOCK_SIZE 16
+/*! AES Input Vector size in bytes */
+#define LTC_AES_IV_SIZE 16
+
+/*! @brief Type of AES key for ECB and CBC decrypt operations. */
+typedef enum _ltc_aes_key_t
+{
+    kLTC_EncryptKey = 0U, /*!< Input key is an encrypt key */
+    kLTC_DecryptKey = 1U, /*!< Input key is a decrypt key */
+} ltc_aes_key_t;
+
+/*!
+ *@}
+ */
+
+/*******************************************************************************
+ * DES Definitions
+ *******************************************************************************/
+/*!
+ * @addtogroup ltc_driver_des
+ * @{
+ */
+
+/*! @brief LTC DES key size - 64 bits. */
+#define LTC_DES_KEY_SIZE 8
+
+/*! @brief LTC DES IV size - 8 bytes */
+#define LTC_DES_IV_SIZE 8
+
+/*!
+ *@}
+ */
+
+/*******************************************************************************
+ * HASH Definitions
+ ******************************************************************************/
+/*!
+ * @addtogroup ltc_driver_hash
+ * @{
+ */
+/*! Supported cryptographic block cipher functions for HASH creation */
+typedef enum _ltc_hash_algo_t
+{
+    kLTC_XcbcMac = 0, /*!< XCBC-MAC (AES engine) */
+    kLTC_Cmac,        /*!< CMAC (AES engine) */
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+    kLTC_Sha1,   /*!< SHA_1   (MDHA engine)  */
+    kLTC_Sha224, /*!< SHA_224 (MDHA engine)  */
+    kLTC_Sha256, /*!< SHA_256 (MDHA engine)  */
+#endif           /* FSL_FEATURE_LTC_HAS_SHA */
+} ltc_hash_algo_t;
+
+/*! @brief LTC HASH Context size. */
+#if defined(FSL_FEATURE_LTC_HAS_SHA) && FSL_FEATURE_LTC_HAS_SHA
+#define LTC_HASH_CTX_SIZE 41
+#else
+#define LTC_HASH_CTX_SIZE 29
+#endif /* FSL_FEATURE_LTC_HAS_SHA */
+
+/*! @brief Storage type used to save hash context. */
+typedef uint32_t ltc_hash_ctx_t[LTC_HASH_CTX_SIZE];
+
+/*!
+ *@}
+ */
+/*******************************************************************************
+ * PKHA Definitions
+ ******************************************************************************/
+/*!
+ * @addtogroup ltc_driver_pkha
+ * @{
+ */
+/*! PKHA ECC point structure */
+typedef struct _ltc_pkha_ecc_point_t
+{
+    uint8_t *X; /*!< X coordinate (affine) */
+    uint8_t *Y; /*!< Y coordinate (affine) */
+} ltc_pkha_ecc_point_t;
+
+/*! @brief Use of timing equalized version of a PKHA function. */
+typedef enum _ltc_pkha_timing_t
+{
+    kLTC_PKHA_NoTimingEqualized = 0U, /*!< Normal version of a PKHA operation */
+    kLTC_PKHA_TimingEqualized = 1U    /*!< Timing-equalized version of a PKHA operation  */
+} ltc_pkha_timing_t;
+
+/*! @brief Integer vs binary polynomial arithmetic selection. */
+typedef enum _ltc_pkha_f2m_t
+{
+    kLTC_PKHA_IntegerArith = 0U, /*!< Use integer arithmetic */
+    kLTC_PKHA_F2mArith = 1U      /*!< Use binary polynomial arithmetic */
+} ltc_pkha_f2m_t;
+
+/*! @brief Montgomery or normal PKHA input format. */
+typedef enum _ltc_pkha_montgomery_form_t
+{
+    kLTC_PKHA_NormalValue = 0U,     /*!< PKHA number is normal integer */
+    kLTC_PKHA_MontgomeryFormat = 1U /*!< PKHA number is in montgomery format */
+} ltc_pkha_montgomery_form_t;
+
+/*!
+ *@}
+ */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup ltc
+ * @{
+ */
+
+/*!
+ * @brief Initializes the LTC driver.
+ * This function initializes the LTC driver.
+ * @param base LTC peripheral base address
+ */
+void LTC_Init(LTC_Type *base);
+
+/*!
+ * @brief Deinitializes the LTC driver.
+ * This function deinitializes the LTC driver.
+ * @param base LTC peripheral base address
+ */
+void LTC_Deinit(LTC_Type *base);
+
+#if defined(FSL_FEATURE_LTC_HAS_DPAMS) && FSL_FEATURE_LTC_HAS_DPAMS
+/*!
+ * @brief Sets the DPA Mask Seed register.
+ *
+ * The DPA Mask Seed register reseeds the mask that provides resistance against DPA (differential power analysis)
+ * attacks on AES or DES keys.
+ *
+ * Differential Power Analysis Mask (DPA) resistance uses a randomly changing mask that introduces
+ * "noise" into the power consumed by the AES or DES. This reduces the signal-to-noise ratio that differential
+ * power analysis attacks use to "guess" bits of the key. This randomly changing mask should be
+ * seeded at POR, and continues to provide DPA resistance from that point on. However, to provide even more
+ * DPA protection it is recommended that the DPA mask be reseeded after every 50,000 blocks have
+ * been processed. At that time, software can opt to write a new seed (preferably obtained from an RNG)
+ * into the DPA Mask Seed register (DPAMS), or software can opt to provide the new seed earlier or
+ * later, or not at all. DPA resistance continues even if the DPA mask is never reseeded.
+ *
+ * @param base LTC peripheral base address
+ * @param mask The DPA mask seed.
+ */
+void LTC_SetDpaMaskSeed(LTC_Type *base, uint32_t mask);
+#endif /* FSL_FEATURE_LTC_HAS_DPAMS */
+
+/*!
+ *@}
+ */
+
+/*******************************************************************************
+ * AES API
+ ******************************************************************************/
+
+/*!
+ * @addtogroup ltc_driver_aes
+ * @{
+ */
+
+/*!
+ * @brief Transforms an AES encrypt key (forward AES) into the decrypt key (inverse AES).
+ *
+ * Transforms the AES encrypt key (forward AES) into the decrypt key (inverse AES).
+ * The key derived by this function can be used as a direct load decrypt key
+ * for AES ECB and CBC decryption operations (keyType argument).
+ *
+ * @param base LTC peripheral base address
+ * @param encryptKey Input key for decrypt key transformation
+ * @param[out] decryptKey Output key, the decrypt form of the AES key.
+ * @param keySize Size of the input key and output key in bytes. Must be 16, 24, or 32.
+ * @return Status from key generation operation
+ */
+status_t LTC_AES_GenerateDecryptKey(LTC_Type *base, const uint8_t *encryptKey, uint8_t *decryptKey, uint32_t keySize);
+
+/*!
+ * @brief Encrypts AES using the ECB block mode.
+ *
+ * Encrypts AES using the ECB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param key Input key to use for encryption
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @return Status from encrypt operation
+ */
+status_t LTC_AES_EncryptEcb(
+    LTC_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, uint32_t size, const uint8_t *key, uint32_t keySize);
+
+/*!
+ * @brief Decrypts AES using ECB block mode.
+ *
+ * Decrypts AES using ECB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param key Input key.
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @param keyType Input type of the key (allows to directly load decrypt key for AES ECB decrypt operation.)
+ * @return Status from decrypt operation
+ */
+status_t LTC_AES_DecryptEcb(LTC_Type *base,
+                            const uint8_t *ciphertext,
+                            uint8_t *plaintext,
+                            uint32_t size,
+                            const uint8_t *key,
+                            uint32_t keySize,
+                            ltc_aes_key_t keyType);
+
+/*!
+ * @brief Encrypts AES using CBC block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @param key Input key to use for encryption
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @return Status from encrypt operation
+ */
+status_t LTC_AES_EncryptCbc(LTC_Type *base,
+                            const uint8_t *plaintext,
+                            uint8_t *ciphertext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_AES_IV_SIZE],
+                            const uint8_t *key,
+                            uint32_t keySize);
+
+/*!
+ * @brief Decrypts AES using CBC block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @param key Input key to use for decryption
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @param keyType Input type of the key (allows to directly load decrypt key for AES CBC decrypt operation.)
+ * @return Status from decrypt operation
+ */
+status_t LTC_AES_DecryptCbc(LTC_Type *base,
+                            const uint8_t *ciphertext,
+                            uint8_t *plaintext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_AES_IV_SIZE],
+                            const uint8_t *key,
+                            uint32_t keySize,
+                            ltc_aes_key_t keyType);
+
+/*!
+ * @brief Encrypts or decrypts AES using CTR block mode.
+ *
+ * Encrypts or decrypts AES using CTR block mode.
+ * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption.
+ * The only difference between encryption and decryption is that, for encryption, the input argument
+ * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text
+ * and the output argument is plain text.
+ *
+ * @param base LTC peripheral base address
+ * @param input Input data for CTR block mode
+ * @param[out] output Output data for CTR block mode
+ * @param size Size of input and output data in bytes
+ * @param[in,out] counter Input counter (updates on return)
+ * @param key Input key to use for forward AES cipher
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @param[out] counterlast Output cipher of last counter, for chained CTR calls. NULL can be passed if chained calls are
+ * not used.
+ * @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls
+ * are not used.
+ * @return Status from encrypt operation
+ */
+status_t LTC_AES_CryptCtr(LTC_Type *base,
+                          const uint8_t *input,
+                          uint8_t *output,
+                          uint32_t size,
+                          uint8_t counter[LTC_AES_BLOCK_SIZE],
+                          const uint8_t *key,
+                          uint32_t keySize,
+                          uint8_t counterlast[LTC_AES_BLOCK_SIZE],
+                          uint32_t *szLeft);
+
+/*! AES CTR decrypt is mapped to the AES CTR generic operation */
+#define LTC_AES_DecryptCtr(base, input, output, size, counter, key, keySize, counterlast, szLeft) \
+    LTC_AES_CryptCtr(base, input, output, size, counter, key, keySize, counterlast, szLeft)
+
+/*! AES CTR encrypt is mapped to the AES CTR generic operation */
+#define LTC_AES_EncryptCtr(base, input, output, size, counter, key, keySize, counterlast, szLeft) \
+    LTC_AES_CryptCtr(base, input, output, size, counter, key, keySize, counterlast, szLeft)
+
+#if defined(FSL_FEATURE_LTC_HAS_GCM) && FSL_FEATURE_LTC_HAS_GCM
+/*!
+ * @brief Encrypts AES and tags using GCM block mode.
+ *
+ * Encrypts AES and optionally tags using GCM block mode. If plaintext is NULL, only the GHASH is calculated and output
+ * in the 'tag' field.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text.
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector
+ * @param ivSize Size of the IV
+ * @param aad Input additional authentication data
+ * @param aadSize Input size in bytes of AAD
+ * @param key Input key to use for encryption
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @param[out] tag Output hash tag. Set to NULL to skip tag processing.
+ * @param tagSize Input size of the tag to generate, in bytes. Must be 4,8,12,13,14,15 or 16.
+ * @return Status from encrypt operation
+ */
+status_t LTC_AES_EncryptTagGcm(LTC_Type *base,
+                               const uint8_t *plaintext,
+                               uint8_t *ciphertext,
+                               uint32_t size,
+                               const uint8_t *iv,
+                               uint32_t ivSize,
+                               const uint8_t *aad,
+                               uint32_t aadSize,
+                               const uint8_t *key,
+                               uint32_t keySize,
+                               uint8_t *tag,
+                               uint32_t tagSize);
+
+/*!
+ * @brief Decrypts AES and authenticates using GCM block mode.
+ *
+ * Decrypts AES and optionally authenticates using GCM block mode. If ciphertext is NULL, only the GHASH is calculated
+ * and compared with the received GHASH in 'tag' field.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text.
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector
+ * @param ivSize Size of the IV
+ * @param aad Input additional authentication data
+ * @param aadSize Input size in bytes of AAD
+ * @param key Input key to use for encryption
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @param tag Input hash tag to compare. Set to NULL to skip tag processing.
+ * @param tagSize Input size of the tag, in bytes. Must be 4, 8, 12, 13, 14, 15, or 16.
+ * @return Status from decrypt operation
+ */
+status_t LTC_AES_DecryptTagGcm(LTC_Type *base,
+                               const uint8_t *ciphertext,
+                               uint8_t *plaintext,
+                               uint32_t size,
+                               const uint8_t *iv,
+                               uint32_t ivSize,
+                               const uint8_t *aad,
+                               uint32_t aadSize,
+                               const uint8_t *key,
+                               uint32_t keySize,
+                               const uint8_t *tag,
+                               uint32_t tagSize);
+#endif /* FSL_FEATURE_LTC_HAS_GCM */
+
+/*!
+ * @brief Encrypts AES and tags using CCM block mode.
+ *
+ * Encrypts AES and optionally tags using CCM block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text.
+ * @param size Size of input and output data in bytes. Zero means authentication only.
+ * @param iv Nonce
+ * @param ivSize Length of the Nonce in bytes. Must be 7, 8, 9, 10, 11, 12, or 13.
+ * @param aad Input additional authentication data. Can be NULL if aadSize is zero.
+ * @param aadSize Input size in bytes of AAD. Zero means data mode only (authentication skipped).
+ * @param key Input key to use for encryption
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @param[out] tag Generated output tag. Set to NULL to skip tag processing.
+ * @param tagSize Input size of the tag to generate, in bytes. Must be 4, 6, 8, 10, 12, 14, or 16.
+ * @return Status from encrypt operation
+ */
+status_t LTC_AES_EncryptTagCcm(LTC_Type *base,
+                               const uint8_t *plaintext,
+                               uint8_t *ciphertext,
+                               uint32_t size,
+                               const uint8_t *iv,
+                               uint32_t ivSize,
+                               const uint8_t *aad,
+                               uint32_t aadSize,
+                               const uint8_t *key,
+                               uint32_t keySize,
+                               uint8_t *tag,
+                               uint32_t tagSize);
+
+/*!
+ * @brief Decrypts AES and authenticates using CCM block mode.
+ *
+ * Decrypts AES and optionally authenticates using CCM block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text.
+ * @param size Size of input and output data in bytes. Zero means authentication only.
+ * @param iv Nonce
+ * @param ivSize Length of the Nonce in bytes. Must be 7, 8, 9, 10, 11, 12, or 13.
+ * @param aad Input additional authentication data. Can be NULL if aadSize is zero.
+ * @param aadSize Input size in bytes of AAD. Zero means data mode only (authentication skipped).
+ * @param key Input key to use for decryption
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @param tag Received tag. Set to NULL to skip tag processing.
+ * @param tagSize Input size of the received tag to compare with the computed tag, in bytes. Must be 4, 6, 8, 10, 12,
+ * 14, or 16.
+ * @return Status from decrypt operation
+ */
+status_t LTC_AES_DecryptTagCcm(LTC_Type *base,
+                               const uint8_t *ciphertext,
+                               uint8_t *plaintext,
+                               uint32_t size,
+                               const uint8_t *iv,
+                               uint32_t ivSize,
+                               const uint8_t *aad,
+                               uint32_t aadSize,
+                               const uint8_t *key,
+                               uint32_t keySize,
+                               const uint8_t *tag,
+                               uint32_t tagSize);
+
+/*!
+ *@}
+ */
+
+/*******************************************************************************
+ * DES API
+ ******************************************************************************/
+/*!
+ * @addtogroup ltc_driver_des
+ * @{
+ */
+/*!
+ * @brief Encrypts DES using ECB block mode.
+ *
+ * Encrypts DES using ECB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param key Input key to use for encryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_EncryptEcb(
+    LTC_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, uint32_t size, const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts DES using ECB block mode.
+ *
+ * Decrypts DES using ECB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param key Input key to use for decryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_DecryptEcb(
+    LTC_Type *base, const uint8_t *ciphertext, uint8_t *plaintext, uint32_t size, const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts DES using CBC block mode.
+ *
+ * Encrypts DES using CBC block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Ouput ciphertext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector to combine with the first plaintext block.
+ *           The iv does not need to be secret, but it must be unpredictable.
+ * @param key Input key to use for encryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_EncryptCbc(LTC_Type *base,
+                            const uint8_t *plaintext,
+                            uint8_t *ciphertext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_DES_IV_SIZE],
+                            const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts DES using CBC block mode.
+ *
+ * Decrypts DES using CBC block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input data in bytes
+ * @param iv Input initial vector to combine with the first plaintext block.
+ *           The iv does not need to be secret, but it must be unpredictable.
+ * @param key Input key to use for decryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_DecryptCbc(LTC_Type *base,
+                            const uint8_t *ciphertext,
+                            uint8_t *plaintext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_DES_IV_SIZE],
+                            const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts DES using CFB block mode.
+ *
+ * Encrypts DES using CFB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plaintext to encrypt
+ * @param size Size of input data in bytes
+ * @param iv Input initial block.
+ * @param key Input key to use for encryption
+ * @param[out] ciphertext Output ciphertext
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_EncryptCfb(LTC_Type *base,
+                            const uint8_t *plaintext,
+                            uint8_t *ciphertext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_DES_IV_SIZE],
+                            const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts DES using CFB block mode.
+ *
+ * Decrypts DES using CFB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial block.
+ * @param key Input key to use for decryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_DecryptCfb(LTC_Type *base,
+                            const uint8_t *ciphertext,
+                            uint8_t *plaintext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_DES_IV_SIZE],
+                            const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts DES using OFB block mode.
+ *
+ * Encrypts DES using OFB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes
+ * @param iv Input unique input vector. The OFB mode requires that the IV be unique
+ *           for each execution of the mode under the given key.
+ * @param key Input key to use for encryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_EncryptOfb(LTC_Type *base,
+                            const uint8_t *plaintext,
+                            uint8_t *ciphertext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_DES_IV_SIZE],
+                            const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts DES using OFB block mode.
+ *
+ * Decrypts DES using OFB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param iv Input unique input vector. The OFB mode requires that the IV be unique
+ *           for each execution of the mode under the given key.
+ * @param key Input key to use for decryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_DecryptOfb(LTC_Type *base,
+                            const uint8_t *ciphertext,
+                            uint8_t *plaintext,
+                            uint32_t size,
+                            const uint8_t iv[LTC_DES_IV_SIZE],
+                            const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using ECB block mode with two keys.
+ *
+ * Encrypts triple DES using ECB block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_EncryptEcb(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using ECB block mode with two keys.
+ *
+ * Decrypts triple DES using ECB block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_DecryptEcb(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using CBC block mode with two keys.
+ *
+ * Encrypts triple DES using CBC block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector to combine with the first plaintext block.
+ *           The iv does not need to be secret, but it must be unpredictable.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_EncryptCbc(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using CBC block mode with two keys.
+ *
+ * Decrypts triple DES using CBC block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector to combine with the first plaintext block.
+ *           The iv does not need to be secret, but it must be unpredictable.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_DecryptCbc(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using CFB block mode with two keys.
+ *
+ * Encrypts triple DES using CFB block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial block.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_EncryptCfb(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using CFB block mode with two keys.
+ *
+ * Decrypts triple DES using CFB block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial block.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_DecryptCfb(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using OFB block mode with two keys.
+ *
+ * Encrypts triple DES using OFB block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes
+ * @param iv Input unique input vector. The OFB mode requires that the IV be unique
+ *           for each execution of the mode under the given key.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_EncryptOfb(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using OFB block mode with two keys.
+ *
+ * Decrypts triple DES using OFB block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes
+ * @param iv Input unique input vector. The OFB mode requires that the IV be unique
+ *           for each execution of the mode under the given key.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_DecryptOfb(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using ECB block mode with three keys.
+ *
+ * Encrypts triple DES using ECB block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_EncryptEcb(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using ECB block mode with three keys.
+ *
+ * Decrypts triple DES using ECB block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_DecryptEcb(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using CBC block mode with three keys.
+ *
+ * Encrypts triple DES using CBC block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input data in bytes
+ * @param iv Input initial vector to combine with the first plaintext block.
+ *           The iv does not need to be secret, but it must be unpredictable.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_EncryptCbc(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using CBC block mode with three keys.
+ *
+ * Decrypts triple DES using CBC block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector to combine with the first plaintext block.
+ *           The iv does not need to be secret, but it must be unpredictable.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_DecryptCbc(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using CFB block mode with three keys.
+ *
+ * Encrypts triple DES using CFB block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and ouput data in bytes
+ * @param iv Input initial block.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_EncryptCfb(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using CFB block mode with three keys.
+ *
+ * Decrypts triple DES using CFB block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input data in bytes
+ * @param iv Input initial block.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_DecryptCfb(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using OFB block mode with three keys.
+ *
+ * Encrypts triple DES using OFB block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes
+ * @param iv Input unique input vector. The OFB mode requires that the IV be unique
+ *           for each execution of the mode under the given key.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_EncryptOfb(LTC_Type *base,
+                             const uint8_t *plaintext,
+                             uint8_t *ciphertext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using OFB block mode with three keys.
+ *
+ * Decrypts triple DES using OFB block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes
+ * @param iv Input unique input vector. The OFB mode requires that the IV be unique
+ *           for each execution of the mode under the given key.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_DecryptOfb(LTC_Type *base,
+                             const uint8_t *ciphertext,
+                             uint8_t *plaintext,
+                             uint32_t size,
+                             const uint8_t iv[LTC_DES_IV_SIZE],
+                             const uint8_t key1[LTC_DES_KEY_SIZE],
+                             const uint8_t key2[LTC_DES_KEY_SIZE],
+                             const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ *@}
+ */
+
+/*******************************************************************************
+ * HASH API
+ ******************************************************************************/
+
+/*!
+ * @addtogroup ltc_driver_hash
+ * @{
+ */
+/*!
+ * @brief Initialize HASH context
+ *
+ * This function initialize the HASH.
+ * Key shall be supplied if the underlaying algoritm is AES XCBC-MAC or CMAC.
+ * Key shall be NULL if the underlaying algoritm is SHA.
+ *
+ * For XCBC-MAC, the key length must be 16. For CMAC, the key length can be
+ * the AES key lengths supported by AES engine. For MDHA the key length argument
+ * is ignored.
+ *
+ * @param base LTC peripheral base address
+ * @param[out] ctx Output hash context
+ * @param algo Underlaying algorithm to use for hash computation.
+ * @param key Input key (NULL if underlaying algorithm is SHA)
+ * @param keySize Size of input key in bytes
+ * @return Status of initialization
+ */
+status_t LTC_HASH_Init(LTC_Type *base, ltc_hash_ctx_t *ctx, ltc_hash_algo_t algo, const uint8_t *key, uint32_t keySize);
+
+/*!
+ * @brief Add data to current HASH
+ *
+ * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be
+ * hashed.
+ *
+ * @param[in,out] ctx HASH context
+ * @param input Input data
+ * @param inputSize Size of input data in bytes
+ * @return Status of the hash update operation
+ */
+status_t LTC_HASH_Update(ltc_hash_ctx_t *ctx, const uint8_t *input, uint32_t inputSize);
+
+/*!
+ * @brief Finalize hashing
+ *
+ * Outputs the final hash and erases the context.
+ *
+ * @param[in,out] ctx Input hash context
+ * @param[out] output Output hash data
+ * @param[out] outputSize Output parameter storing the size of the output hash in bytes
+ * @return Status of the hash finish operation
+ */
+status_t LTC_HASH_Finish(ltc_hash_ctx_t *ctx, uint8_t *output, uint32_t *outputSize);
+
+/*!
+ * @brief Create HASH on given data
+ *
+ * Perform the full keyed HASH in one function call.
+ *
+ * @param base LTC peripheral base address
+ * @param algo Block cipher algorithm to use for CMAC creation
+ * @param input Input data
+ * @param inputSize Size of input data in bytes
+ * @param key Input key
+ * @param keySize Size of input key in bytes
+ * @param[out] output Output hash data
+ * @param[out] outputSize Output parameter storing the size of the output hash in bytes
+ * @return Status of the one call hash operation.
+ */
+status_t LTC_HASH(LTC_Type *base,
+                  ltc_hash_algo_t algo,
+                  const uint8_t *input,
+                  uint32_t inputSize,
+                  const uint8_t *key,
+                  uint32_t keySize,
+                  uint8_t *output,
+                  uint32_t *outputSize);
+/*!
+ *@}
+ */
+
+/*******************************************************************************
+ * PKHA API
+ ******************************************************************************/
+/*!
+ * @addtogroup ltc_driver_pkha
+ * @{
+ */
+
+/*!
+ * @brief Compare two PKHA big numbers.
+ *
+ * Compare two PKHA big numbers. Return 1 for a > b, -1 for a < b and 0 if they are same.
+ * PKHA big number is lsbyte first. Thus the comparison starts at msbyte which is the last member of tested arrays.
+ *
+ * @param a First integer represented as an array of bytes, lsbyte first.
+ * @param sizeA Size in bytes of the first integer.
+ * @param b Second integer represented as an array of bytes, lsbyte first.
+ * @param sizeB Size in bytes of the second integer.
+ * @return 1 if a > b.
+ * @return -1 if a < b.
+ * @return 0 if a = b.
+ */
+int LTC_PKHA_CompareBigNum(const uint8_t *a, size_t sizeA, const uint8_t *b, size_t sizeB);
+
+/*!
+ * @brief Converts from integer to Montgomery format.
+ *
+ * This function computes R2 mod N and optionally converts A or B into Montgomery format of A or B.
+ *
+ * @param base LTC peripheral base address
+ * @param N modulus
+ * @param sizeN size of N in bytes
+ * @param[in,out] A The first input in non-Montgomery format. Output Montgomery format of the first input.
+ * @param[in,out] sizeA pointer to size variable. On input it holds size of input A in bytes. On output it holds size of
+ *                Montgomery format of A in bytes.
+ * @param[in,out] B Second input in non-Montgomery format. Output Montgomery format of the second input.
+ * @param[in,out] sizeB pointer to size variable. On input it holds size of input B in bytes. On output it holds size of
+ *                Montgomery format of B in bytes.
+ * @param[out] R2 Output Montgomery factor R2 mod N.
+ * @param[out] sizeR2 pointer to size variable. On output it holds size of Montgomery factor R2 mod N in bytes.
+ * @param equalTime Run the function time equalized or no timing equalization.
+ * @param arithType Type of arithmetic to perform (integer or F2m)
+ * @return Operation status.
+ */
+status_t LTC_PKHA_NormalToMontgomery(LTC_Type *base,
+                                     const uint8_t *N,
+                                     uint16_t sizeN,
+                                     uint8_t *A,
+                                     uint16_t *sizeA,
+                                     uint8_t *B,
+                                     uint16_t *sizeB,
+                                     uint8_t *R2,
+                                     uint16_t *sizeR2,
+                                     ltc_pkha_timing_t equalTime,
+                                     ltc_pkha_f2m_t arithType);
+
+/*!
+ * @brief Converts from Montgomery format to int.
+ *
+ * This function converts Montgomery format of A or B into int A or B.
+ *
+ * @param base LTC peripheral base address
+ * @param N modulus.
+ * @param sizeN size of N modulus in bytes.
+ * @param[in,out] A Input first number in Montgomery format. Output is non-Montgomery format.
+ * @param[in,out] sizeA pointer to size variable. On input it holds size of the input A in bytes. On output it holds
+ * size of non-Montgomery A in bytes.
+ * @param[in,out] B Input first number in Montgomery format. Output is non-Montgomery format.
+ * @param[in,out] sizeB pointer to size variable. On input it holds size of the input B in bytes. On output it holds
+ * size of non-Montgomery B in bytes.
+ * @param equalTime Run the function time equalized or no timing equalization.
+ * @param arithType Type of arithmetic to perform (integer or F2m)
+ * @return Operation status.
+ */
+status_t LTC_PKHA_MontgomeryToNormal(LTC_Type *base,
+                                     const uint8_t *N,
+                                     uint16_t sizeN,
+                                     uint8_t *A,
+                                     uint16_t *sizeA,
+                                     uint8_t *B,
+                                     uint16_t *sizeB,
+                                     ltc_pkha_timing_t equalTime,
+                                     ltc_pkha_f2m_t arithType);
+
+/*!
+ * @brief Performs modular addition - (A + B) mod N.
+ *
+ * This function performs modular addition of (A + B) mod N, with either
+ * integer or binary polynomial (F2m) inputs.  In the F2m form, this function is
+ * equivalent to a bitwise XOR and it is functionally the same as subtraction.
+ *
+ * @param base LTC peripheral base address
+ * @param A first addend (integer or binary polynomial)
+ * @param sizeA Size of A in bytes
+ * @param B second addend (integer or binary polynomial)
+ * @param sizeB Size of B in bytes
+ * @param N modulus. For F2m operation this can be NULL, as N is ignored during F2m polynomial addition.
+ * @param sizeN Size of N in bytes. This must be given for both integer and F2m polynomial additions.
+ * @param[out] result Output array to store result of operation
+ * @param[out] resultSize Output size of operation in bytes
+ * @param arithType Type of arithmetic to perform (integer or F2m)
+ * @return Operation status.
+ */
+status_t LTC_PKHA_ModAdd(LTC_Type *base,
+                         const uint8_t *A,
+                         uint16_t sizeA,
+                         const uint8_t *B,
+                         uint16_t sizeB,
+                         const uint8_t *N,
+                         uint16_t sizeN,
+                         uint8_t *result,
+                         uint16_t *resultSize,
+                         ltc_pkha_f2m_t arithType);
+
+/*!
+ * @brief Performs modular subtraction - (A - B) mod N.
+ *
+ * This function performs modular subtraction of (A - B) mod N with
+ * integer inputs.
+ *
+ * @param base LTC peripheral base address
+ * @param A first addend (integer or binary polynomial)
+ * @param sizeA Size of A in bytes
+ * @param B second addend (integer or binary polynomial)
+ * @param sizeB Size of B in bytes
+ * @param N modulus
+ * @param sizeN Size of N in bytes
+ * @param[out] result Output array to store result of operation
+ * @param[out] resultSize Output size of operation in bytes
+ * @return Operation status.
+ */
+status_t LTC_PKHA_ModSub1(LTC_Type *base,
+                          const uint8_t *A,
+                          uint16_t sizeA,
+                          const uint8_t *B,
+                          uint16_t sizeB,
+                          const uint8_t *N,
+                          uint16_t sizeN,
+                          uint8_t *result,
+                          uint16_t *resultSize);
+
+/*!
+ * @brief Performs modular subtraction - (B - A) mod N.
+ *
+ * This function performs modular subtraction of (B - A) mod N,
+ * with integer inputs.
+ *
+ * @param base LTC peripheral base address
+ * @param A first addend (integer or binary polynomial)
+ * @param sizeA Size of A in bytes
+ * @param B second addend (integer or binary polynomial)
+ * @param sizeB Size of B in bytes
+ * @param N modulus
+ * @param sizeN Size of N in bytes
+ * @param[out] result Output array to store result of operation
+ * @param[out] resultSize Output size of operation in bytes
+ * @return Operation status.
+ */
+status_t LTC_PKHA_ModSub2(LTC_Type *base,
+                          const uint8_t *A,
+                          uint16_t sizeA,
+                          const uint8_t *B,
+                          uint16_t sizeB,
+                          const uint8_t *N,
+                          uint16_t sizeN,
+                          uint8_t *result,
+                          uint16_t *resultSize);
+
+/*!
+ * @brief Performs modular multiplication - (A x B) mod N.
+ *
+ * This function performs modular multiplication with either integer or
+ * binary polynomial (F2m) inputs.  It can optionally specify whether inputs
+ * and/or outputs will be in Montgomery form or not.
+ *
+ * @param base LTC peripheral base address
+ * @param A first addend (integer or binary polynomial)
+ * @param sizeA Size of A in bytes
+ * @param B second addend (integer or binary polynomial)
+ * @param sizeB Size of B in bytes
+ * @param N modulus.
+ * @param sizeN Size of N in bytes
+ * @param[out] result Output array to store result of operation
+ * @param[out] resultSize Output size of operation in bytes
+ * @param arithType Type of arithmetic to perform (integer or F2m)
+ * @param montIn Format of inputs
+ * @param montOut Format of output
+ * @param equalTime Run the function time equalized or no timing equalization. This argument is ignored for F2m modular
+ * multiplication.
+ * @return Operation status.
+ */
+status_t LTC_PKHA_ModMul(LTC_Type *base,
+                         const uint8_t *A,
+                         uint16_t sizeA,
+                         const uint8_t *B,
+                         uint16_t sizeB,
+                         const uint8_t *N,
+                         uint16_t sizeN,
+                         uint8_t *result,
+                         uint16_t *resultSize,
+                         ltc_pkha_f2m_t arithType,
+                         ltc_pkha_montgomery_form_t montIn,
+                         ltc_pkha_montgomery_form_t montOut,
+                         ltc_pkha_timing_t equalTime);
+
+/*!
+ * @brief Performs modular exponentiation - (A^E) mod N.
+ *
+ * This function performs modular exponentiation with either integer or
+ * binary polynomial (F2m) inputs.
+ *
+ * @param base LTC peripheral base address
+ * @param A first addend (integer or binary polynomial)
+ * @param sizeA Size of A in bytes
+ * @param N modulus
+ * @param sizeN Size of N in bytes
+ * @param E exponent
+ * @param sizeE Size of E in bytes
+ * @param[out] result Output array to store result of operation
+ * @param[out] resultSize Output size of operation in bytes
+ * @param montIn Format of A input (normal or Montgomery)
+ * @param arithType Type of arithmetic to perform (integer or F2m)
+ * @param equalTime Run the function time equalized or no timing equalization.
+ * @return Operation status.
+ */
+status_t LTC_PKHA_ModExp(LTC_Type *base,
+                         const uint8_t *A,
+                         uint16_t sizeA,
+                         const uint8_t *N,
+                         uint16_t sizeN,
+                         const uint8_t *E,
+                         uint16_t sizeE,
+                         uint8_t *result,
+                         uint16_t *resultSize,
+                         ltc_pkha_f2m_t arithType,
+                         ltc_pkha_montgomery_form_t montIn,
+                         ltc_pkha_timing_t equalTime);
+
+/*!
+ * @brief Performs modular reduction - (A) mod N.
+ *
+ * This function performs modular reduction with either integer or
+ * binary polynomial (F2m) inputs.
+ *
+ * @param base LTC peripheral base address
+ * @param A first addend (integer or binary polynomial)
+ * @param sizeA Size of A in bytes
+ * @param N modulus
+ * @param sizeN Size of N in bytes
+ * @param[out] result Output array to store result of operation
+ * @param[out] resultSize Output size of operation in bytes
+ * @param arithType Type of arithmetic to perform (integer or F2m)
+ * @return Operation status.
+ */
+status_t LTC_PKHA_ModRed(LTC_Type *base,
+                         const uint8_t *A,
+                         uint16_t sizeA,
+                         const uint8_t *N,
+                         uint16_t sizeN,
+                         uint8_t *result,
+                         uint16_t *resultSize,
+                         ltc_pkha_f2m_t arithType);
+
+/*!
+ * @brief Performs modular inversion - (A^-1) mod N.
+ *
+ * This function performs modular inversion with either integer or
+ * binary polynomial (F2m) inputs.
+ *
+ * @param base LTC peripheral base address
+ * @param A first addend (integer or binary polynomial)
+ * @param sizeA Size of A in bytes
+ * @param N modulus
+ * @param sizeN Size of N in bytes
+ * @param[out] result Output array to store result of operation
+ * @param[out] resultSize Output size of operation in bytes
+ * @param arithType Type of arithmetic to perform (integer or F2m)
+ * @return Operation status.
+ */
+status_t LTC_PKHA_ModInv(LTC_Type *base,
+                         const uint8_t *A,
+                         uint16_t sizeA,
+                         const uint8_t *N,
+                         uint16_t sizeN,
+                         uint8_t *result,
+                         uint16_t *resultSize,
+                         ltc_pkha_f2m_t arithType);
+
+/*!
+ * @brief Computes integer Montgomery factor R^2 mod N.
+ *
+ * This function computes a constant to assist in converting operands
+ * into the Montgomery residue system representation.
+ *
+ * @param base LTC peripheral base address
+ * @param N modulus
+ * @param sizeN Size of N in bytes
+ * @param[out] result Output array to store result of operation
+ * @param[out] resultSize Output size of operation in bytes
+ * @param arithType Type of arithmetic to perform (integer or F2m)
+ * @return Operation status.
+ */
+status_t LTC_PKHA_ModR2(
+    LTC_Type *base, const uint8_t *N, uint16_t sizeN, uint8_t *result, uint16_t *resultSize, ltc_pkha_f2m_t arithType);
+
+/*!
+ * @brief Calculates the greatest common divisor - GCD (A, N).
+ *
+ * This function calculates the greatest common divisor of two inputs with
+ * either integer or binary polynomial (F2m) inputs.
+ *
+ * @param base LTC peripheral base address
+ * @param A first value (must be smaller than or equal to N)
+ * @param sizeA Size of A in bytes
+ * @param N second value (must be non-zero)
+ * @param sizeN Size of N in bytes
+ * @param[out] result Output array to store result of operation
+ * @param[out] resultSize Output size of operation in bytes
+ * @param arithType Type of arithmetic to perform (integer or F2m)
+ * @return Operation status.
+ */
+status_t LTC_PKHA_GCD(LTC_Type *base,
+                      const uint8_t *A,
+                      uint16_t sizeA,
+                      const uint8_t *N,
+                      uint16_t sizeN,
+                      uint8_t *result,
+                      uint16_t *resultSize,
+                      ltc_pkha_f2m_t arithType);
+
+/*!
+ * @brief Executes Miller-Rabin primality test.
+ *
+ * This function calculates whether or not a candidate prime number is likely
+ * to be a prime.
+ *
+ * @param base LTC peripheral base address
+ * @param A initial random seed
+ * @param sizeA Size of A in bytes
+ * @param B number of trial runs
+ * @param sizeB Size of B in bytes
+ * @param N candidate prime integer
+ * @param sizeN Size of N in bytes
+ * @param[out] res True if the value is likely prime or false otherwise
+ * @return Operation status.
+ */
+status_t LTC_PKHA_PrimalityTest(LTC_Type *base,
+                                const uint8_t *A,
+                                uint16_t sizeA,
+                                const uint8_t *B,
+                                uint16_t sizeB,
+                                const uint8_t *N,
+                                uint16_t sizeN,
+                                bool *res);
+
+/*!
+ * @brief Adds elliptic curve points - A + B.
+ *
+ * This function performs ECC point addition over a prime field (Fp) or binary field (F2m) using
+ * affine coordinates.
+ *
+ * @param base LTC peripheral base address
+ * @param A Left-hand point
+ * @param B Right-hand point
+ * @param N Prime modulus of the field
+ * @param R2modN NULL (the function computes R2modN internally) or pointer to pre-computed R2modN (obtained from
+ *               LTC_PKHA_ModR2() function).
+ * @param aCurveParam A parameter from curve equation
+ * @param bCurveParam B parameter from curve equation (constant)
+ * @param size Size in bytes of curve points and parameters
+ * @param arithType Type of arithmetic to perform (integer or F2m)
+ * @param[out] result Result point
+ * @return Operation status.
+ */
+status_t LTC_PKHA_ECC_PointAdd(LTC_Type *base,
+                               const ltc_pkha_ecc_point_t *A,
+                               const ltc_pkha_ecc_point_t *B,
+                               const uint8_t *N,
+                               const uint8_t *R2modN,
+                               const uint8_t *aCurveParam,
+                               const uint8_t *bCurveParam,
+                               uint8_t size,
+                               ltc_pkha_f2m_t arithType,
+                               ltc_pkha_ecc_point_t *result);
+
+/*!
+ * @brief Doubles elliptic curve points - B + B.
+ *
+ * This function performs ECC point doubling over a prime field (Fp) or binary field (F2m) using
+ * affine coordinates.
+ *
+ * @param base LTC peripheral base address
+ * @param B Point to double
+ * @param N Prime modulus of the field
+ * @param aCurveParam A parameter from curve equation
+ * @param bCurveParam B parameter from curve equation (constant)
+ * @param size Size in bytes of curve points and parameters
+ * @param arithType Type of arithmetic to perform (integer or F2m)
+ * @param[out] result Result point
+ * @return Operation status.
+ */
+status_t LTC_PKHA_ECC_PointDouble(LTC_Type *base,
+                                  const ltc_pkha_ecc_point_t *B,
+                                  const uint8_t *N,
+                                  const uint8_t *aCurveParam,
+                                  const uint8_t *bCurveParam,
+                                  uint8_t size,
+                                  ltc_pkha_f2m_t arithType,
+                                  ltc_pkha_ecc_point_t *result);
+
+/*!
+ * @brief Multiplies an elliptic curve point by a scalar - E x (A0, A1).
+ *
+ * This function performs ECC point multiplication to multiply an ECC point by
+ * a scalar integer multiplier over a prime field (Fp) or a binary field (F2m).
+ *
+ * @param base LTC peripheral base address
+ * @param A Point as multiplicand
+ * @param E Scalar multiple
+ * @param sizeE The size of E, in bytes
+ * @param N Modulus, a prime number for the Fp field or Irreducible polynomial for F2m field.
+ * @param R2modN NULL (the function computes R2modN internally) or pointer to pre-computed R2modN (obtained from
+ *        LTC_PKHA_ModR2() function).
+ * @param aCurveParam A parameter from curve equation
+ * @param bCurveParam B parameter from curve equation (C parameter for operation over F2m).
+ * @param size Size in bytes of curve points and parameters
+ * @param equalTime Run the function time equalized or no timing equalization.
+ * @param arithType Type of arithmetic to perform (integer or F2m)
+ * @param[out] result Result point
+ * @param[out] infinity Output true if the result is point of infinity, and false otherwise. Writing of this output will
+ * be ignored if the argument is NULL.
+ * @return Operation status.
+ */
+status_t LTC_PKHA_ECC_PointMul(LTC_Type *base,
+                               const ltc_pkha_ecc_point_t *A,
+                               const uint8_t *E,
+                               uint8_t sizeE,
+                               const uint8_t *N,
+                               const uint8_t *R2modN,
+                               const uint8_t *aCurveParam,
+                               const uint8_t *bCurveParam,
+                               uint8_t size,
+                               ltc_pkha_timing_t equalTime,
+                               ltc_pkha_f2m_t arithType,
+                               ltc_pkha_ecc_point_t *result,
+                               bool *infinity);
+
+/*!
+ *@}
+ */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* _FSL_LTC_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc_edma.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc_edma.c
new file mode 100644
index 00000000000..93e969b6a2e
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc_edma.c
@@ -0,0 +1,1247 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_ltc_edma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! Structure definition for ltc_edma_private_handle_t. The structure is private. */
+typedef struct _ltc_edma_private_handle
+{
+    LTC_Type *base;
+    ltc_edma_handle_t *handle;
+} ltc_edma_private_handle_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*<! Private handle only used for internally. */
+static ltc_edma_private_handle_t s_edmaPrivateHandle[FSL_FEATURE_SOC_LTC_COUNT];
+
+/* Array of LTC peripheral base address. */
+static LTC_Type *const s_ltcBase[] = LTC_BASE_PTRS;
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* State machine state.*/
+#define LTC_SM_STATE_START 0x0000u
+#define LTC_SM_STATE_FINISH 0xFFFFu
+
+/*! Full word representing the actual bit values for the LTC mode register. */
+typedef uint32_t ltc_mode_t;
+
+#define LTC_FIFO_SZ_MAX_DOWN_ALGN (0xff0u)
+#define LTC_MD_ALG_AES (0x10U)        /*!< Bit field value for LTC_MD_ALG: AES */
+#define LTC_MD_ALG_DES (0x20U)        /*!< Bit field value for LTC_MD_ALG: DES */
+#define LTC_MD_ALG_TRIPLE_DES (0x21U) /*!< Bit field value for LTC_MD_ALG: 3DES */
+#define LTC_MDPK_ALG_PKHA (0x80U)     /*!< Bit field value for LTC_MDPK_ALG: PKHA */
+#define LTC_MD_ENC_DECRYPT (0U)       /*!< Bit field value for LTC_MD_ENC: Decrypt. */
+#define LTC_MD_ENC_ENCRYPT (0x1U)     /*!< Bit field value for LTC_MD_ENC: Encrypt. */
+#define LTC_MD_AS_UPDATE (0U)         /*!< Bit field value for LTC_MD_AS: Update */
+#define LTC_MD_AS_INITIALIZE (0x1U)   /*!< Bit field value for LTC_MD_AS: Initialize */
+#define LTC_MD_AS_FINALIZE (0x2U)     /*!< Bit field value for LTC_MD_AS: Finalize */
+#define LTC_MD_AS_INIT_FINAL (0x3U)   /*!< Bit field value for LTC_MD_AS: Initialize/Finalize */
+
+enum _ltc_md_dk_bit_shift
+{
+    kLTC_ModeRegBitShiftDK = 12U,
+};
+
+typedef enum _ltc_algorithm
+{
+    kLTC_AlgorithmAES = LTC_MD_ALG_AES << LTC_MD_ALG_SHIFT,
+#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES
+    kLTC_AlgorithmDES = LTC_MD_ALG_DES << LTC_MD_ALG_SHIFT,
+    kLTC_Algorithm3DES = LTC_MD_ALG_TRIPLE_DES << LTC_MD_ALG_SHIFT,
+#endif /* FSL_FEATURE_LTC_HAS_DES */
+} ltc_algorithm_t;
+
+typedef enum _ltc_mode_symmetric_alg
+{
+    kLTC_ModeCTR = 0x00U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeCBC = 0x10U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeECB = 0x20U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeCFB = 0x30U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeOFB = 0x40U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeCMAC = 0x60U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeXCBCMAC = 0x70U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeCCM = 0x80U << LTC_MD_AAI_SHIFT,
+    kLTC_ModeGCM = 0x90U << LTC_MD_AAI_SHIFT,
+} ltc_mode_symmetric_alg_t;
+
+typedef enum _ltc_mode_encrypt
+{
+    kLTC_ModeDecrypt = LTC_MD_ENC_DECRYPT << LTC_MD_ENC_SHIFT,
+    kLTC_ModeEncrypt = LTC_MD_ENC_ENCRYPT << LTC_MD_ENC_SHIFT,
+} ltc_mode_encrypt_t;
+
+typedef enum _ltc_mode_algorithm_state
+{
+    kLTC_ModeUpdate = LTC_MD_AS_UPDATE << LTC_MD_AS_SHIFT,
+    kLTC_ModeInit = LTC_MD_AS_INITIALIZE << LTC_MD_AS_SHIFT,
+    kLTC_ModeFinalize = LTC_MD_AS_FINALIZE << LTC_MD_AS_SHIFT,
+    kLTC_ModeInitFinal = LTC_MD_AS_INIT_FINAL << LTC_MD_AS_SHIFT
+} ltc_mode_algorithm_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+extern status_t ltc_get_context(LTC_Type *base, uint8_t *dest, uint8_t dataSize, uint8_t startIndex);
+extern status_t ltc_set_context(LTC_Type *base, const uint8_t *data, uint8_t dataSize, uint8_t startIndex);
+extern status_t ltc_symmetric_update(LTC_Type *base,
+                                     const uint8_t *key,
+                                     uint8_t keySize,
+                                     ltc_algorithm_t alg,
+                                     ltc_mode_symmetric_alg_t mode,
+                                     ltc_mode_encrypt_t enc);
+extern void ltc_memcpy(void *dst, const void *src, size_t size);
+extern bool ltc_check_key_size(const uint32_t keySize);
+extern status_t ltc_wait(LTC_Type *base);
+extern void ltc_clear_all(LTC_Type *base, bool addPKHA);
+extern status_t ltc_3des_check_input_args(ltc_mode_symmetric_alg_t modeAs,
+                                          uint32_t size,
+                                          const uint8_t *key1,
+                                          const uint8_t *key2);
+extern void ltc_symmetric_process(LTC_Type *base, uint32_t inSize, const uint8_t **inData, uint8_t **outData);
+extern status_t ltc_symmetric_process_data(LTC_Type *base, const uint8_t *inData, uint32_t inSize, uint8_t *outData);
+
+static uint32_t LTC_GetInstance(LTC_Type *base);
+static void ltc_symmetric_process_EDMA(LTC_Type *base, uint32_t inSize, const uint8_t **inData, uint8_t **outData);
+static status_t ltc_process_message_in_sessions_EDMA(LTC_Type *base, ltc_edma_handle_t *handle);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*******************************************************************************
+ * LTC Common code static
+ ******************************************************************************/
+
+/*!
+ * @brief Splits the LTC job into sessions. Used for CBC, CTR, CFB, OFB cipher block modes.
+ *
+ * @param base LTC peripheral base address
+ * @param inData Input data to process.
+ * @param inSize Input size of the input buffer.
+ * @param outData Output data buffer.
+ */
+static status_t ltc_process_message_in_sessions_EDMA(LTC_Type *base, ltc_edma_handle_t *handle)
+{
+    status_t retval;
+    bool exit_sm = false;
+
+    handle->modeReg = base->MD;
+    retval = kStatus_Success;
+
+    if ((!handle->inData) || (!handle->outData))
+    {
+        handle->state = LTC_SM_STATE_FINISH; /* END */
+        retval = kStatus_InvalidArgument;
+    }
+
+    while (exit_sm == false)
+    {
+        switch (handle->state)
+        {
+            case LTC_SM_STATE_START:
+                if (handle->size)
+                {
+                    uint32_t sz;
+
+                    if (handle->size <= LTC_FIFO_SZ_MAX_DOWN_ALGN)
+                    {
+                        sz = handle->size;
+                    }
+                    else
+                    {
+                        sz = LTC_FIFO_SZ_MAX_DOWN_ALGN;
+                    }
+
+                    /* retval = ltc_symmetric_process_data_EDMA(base, handle->inData, sz, handle->outData); */
+                    {
+                        uint32_t lastSize;
+                        uint32_t inSize = sz;
+
+                        /* Write the data size. */
+                        base->DS = inSize;
+
+                        /* Split the inSize into full 16-byte chunks and last incomplete block due to LTC AES OFIFO
+                         * errata */
+                        if (inSize <= 16u)
+                        {
+                            lastSize = inSize;
+                            inSize = 0;
+                        }
+                        else
+                        {
+                            /* Process all 16-byte data chunks. */
+                            lastSize = inSize % 16u;
+                            if (lastSize == 0)
+                            {
+                                lastSize = 16;
+                                inSize -= 16;
+                            }
+                            else
+                            {
+                                inSize -=
+                                    lastSize; /* inSize will be rounded down to 16 byte boundary. remaining bytes in
+                                                 lastSize */
+                            }
+                        }
+
+                        if (inSize)
+                        {
+                            handle->size -= inSize;
+                            ltc_symmetric_process_EDMA(base, inSize, &handle->inData, &handle->outData);
+                            exit_sm = true;
+                        }
+                        else if (lastSize)
+                        {
+                            ltc_symmetric_process(base, lastSize, &handle->inData, &handle->outData);
+                            retval = ltc_wait(base);
+                            handle->size -= lastSize;
+                        }
+                        else
+                        {
+                        }
+                    }
+                }
+                else
+                {
+                    handle->state = LTC_SM_STATE_FINISH;
+                }
+                break;
+            case LTC_SM_STATE_FINISH:
+            default:
+                base->MD = handle->modeReg;
+
+                ltc_clear_all(base, false);
+
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, retval, handle->userData);
+                }
+                exit_sm = true;
+                break;
+        }
+    }
+
+    return retval;
+}
+
+/*!
+ * @brief Splits the LTC job into sessions. Used for CBC, CTR, CFB, OFB cipher block modes.
+ *
+ * @param base LTC peripheral base address
+ * @param inData Input data to process.
+ * @param inSize Input size of the input buffer.
+ * @param outData Output data buffer.
+ */
+static status_t ltc_process_message_in_sessions_ctr_EDMA(LTC_Type *base, ltc_edma_handle_t *handle)
+{
+    status_t retval;
+    bool exit_sm = false;
+
+    handle->modeReg = base->MD;
+    retval = kStatus_Success;
+
+    if ((!handle->inData) || (!handle->outData))
+    {
+        handle->state = LTC_SM_STATE_FINISH;
+        retval = kStatus_InvalidArgument;
+    }
+
+    while (exit_sm == false)
+    {
+        switch (handle->state)
+        {
+            case LTC_SM_STATE_START:
+                if (handle->size)
+                {
+                    uint32_t sz;
+
+                    if (handle->size <= LTC_FIFO_SZ_MAX_DOWN_ALGN)
+                    {
+                        sz = handle->size;
+                    }
+                    else
+                    {
+                        sz = LTC_FIFO_SZ_MAX_DOWN_ALGN;
+                    }
+
+                    /* retval = ltc_symmetric_process_data_EDMA(base, handle->inData, sz, handle->outData); */
+                    {
+                        uint32_t lastSize;
+                        uint32_t inSize = sz;
+
+                        /* Write the data size. */
+                        base->DS = inSize;
+
+                        /* Split the inSize into full 16-byte chunks and last incomplete block due to LTC AES OFIFO
+                         * errata */
+                        if (inSize <= 16u)
+                        {
+                            lastSize = inSize;
+                            inSize = 0;
+                        }
+                        else
+                        {
+                            /* Process all 16-byte data chunks. */
+                            lastSize = inSize % 16u;
+                            if (lastSize == 0)
+                            {
+                                lastSize = 16;
+                                inSize -= 16;
+                            }
+                            else
+                            {
+                                inSize -=
+                                    lastSize; /* inSize will be rounded down to 16 byte boundary. remaining bytes in
+                                                 lastSize */
+                            }
+                        }
+
+                        if (inSize)
+                        {
+                            handle->size -= inSize;
+                            ltc_symmetric_process_EDMA(base, inSize, &handle->inData, &handle->outData);
+                            exit_sm = true;
+                        }
+                        else if (lastSize)
+                        {
+                            ltc_symmetric_process(base, lastSize, &handle->inData, &handle->outData);
+                            retval = ltc_wait(base);
+                            handle->size -= lastSize;
+                        }
+                        else
+                        {
+                        }
+                    }
+                }
+                else
+                {
+                    handle->state = LTC_SM_STATE_FINISH;
+                }
+                break;
+            case LTC_SM_STATE_FINISH:
+            default:
+                base->MD = handle->modeReg;
+
+                /* CTR final phase.*/
+                if (kStatus_Success == retval)
+                {
+                    const uint8_t *input = handle->inData;
+                    uint8_t *output = handle->outData;
+
+                    if ((handle->counterlast != NULL) && (handle->lastSize))
+                    {
+                        uint8_t zeroes[16] = {0};
+                        ltc_mode_t modeReg;
+
+                        modeReg = (uint32_t)kLTC_AlgorithmAES | (uint32_t)kLTC_ModeCTR | (uint32_t)kLTC_ModeEncrypt;
+                        /* Write the mode register to the hardware. */
+                        base->MD = modeReg | (uint32_t)kLTC_ModeFinalize;
+
+                        /* context is re-used (CTRi) */
+
+                        /* Process data and return status. */
+                        retval = ltc_symmetric_process_data(base, input, handle->lastSize, output);
+                        if (kStatus_Success == retval)
+                        {
+                            if (handle->szLeft)
+                            {
+                                *handle->szLeft = 16U - handle->lastSize;
+                            }
+
+                            /* Initialize algorithm state. */
+                            base->MD = modeReg | (uint32_t)kLTC_ModeUpdate;
+
+                            /* context is re-used (CTRi) */
+
+                            /* Process data and return status. */
+                            retval = ltc_symmetric_process_data(base, zeroes, 16U, handle->counterlast);
+                        }
+                    }
+                    if (kStatus_Success == retval)
+                    {
+                        ltc_get_context(base, &handle->counter[0], 16U, 4U);
+
+                        ltc_clear_all(base, false);
+                    }
+                }
+
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, retval, handle->userData);
+                }
+
+                exit_sm = true;
+                break;
+        }
+    }
+
+    return retval;
+}
+
+/*******************************************************************************
+ * AES Code public
+ ******************************************************************************/
+
+status_t LTC_AES_EncryptEcbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *plaintext,
+                                uint8_t *ciphertext,
+                                uint32_t size,
+                                const uint8_t *key,
+                                uint32_t keySize)
+{
+    status_t retval;
+
+    if ((ltc_check_key_size(keySize) == 0) || (size < 16u) ||
+        (size % 16u)) /* ECB mode, size must be 16-byte multiple */
+    {
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_InvalidArgument, handle->userData);
+        }
+
+        return kStatus_InvalidArgument;
+    }
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeECB, kLTC_ModeEncrypt);
+
+    /* Process data and return status. */
+    handle->inData = &plaintext[0];
+    handle->outData = &ciphertext[0];
+    handle->size = size;
+    handle->state = LTC_SM_STATE_START;
+    handle->state_machine = ltc_process_message_in_sessions_EDMA;
+    retval = handle->state_machine(base, handle);
+    return retval;
+}
+
+status_t LTC_AES_DecryptEcbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *ciphertext,
+                                uint8_t *plaintext,
+                                uint32_t size,
+                                const uint8_t *key,
+                                uint32_t keySize,
+                                ltc_aes_key_t keyType)
+{
+    status_t status;
+
+    if ((ltc_check_key_size(keySize) == 0) || (size < 16u) ||
+        (size % 16u)) /* ECB mode, size must be 16-byte multiple */
+    {
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_InvalidArgument, handle->userData);
+        }
+
+        return kStatus_InvalidArgument;
+    }
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeECB, kLTC_ModeDecrypt);
+
+    /* set DK bit in the LTC Mode Register AAI field for directly loaded decrypt keys */
+    if (keyType == kLTC_DecryptKey)
+    {
+        base->MD |= (1U << kLTC_ModeRegBitShiftDK);
+    }
+
+    /* Process data and return status. */
+    handle->inData = &ciphertext[0];
+    handle->outData = &plaintext[0];
+    handle->size = size;
+    handle->state = LTC_SM_STATE_START;
+    handle->state_machine = ltc_process_message_in_sessions_EDMA;
+    status = handle->state_machine(base, handle);
+
+    return status;
+}
+
+status_t LTC_AES_EncryptCbcEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *plaintext,
+                                uint8_t *ciphertext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_AES_IV_SIZE],
+                                const uint8_t *key,
+                                uint32_t keySize)
+{
+    status_t retval;
+
+    if ((ltc_check_key_size(keySize) == 0) || (size < 16u) ||
+        (size % 16u)) /* CBC mode, size must be 16-byte multiple */
+    {
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_InvalidArgument, handle->userData);
+        }
+
+        return kStatus_InvalidArgument;
+    }
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCBC, kLTC_ModeEncrypt);
+
+    /* Write IV data to the context register. */
+    ltc_set_context(base, &iv[0], LTC_AES_IV_SIZE, 0);
+
+    /* Process data and return status. */
+    handle->inData = &plaintext[0];
+    handle->outData = &ciphertext[0];
+    handle->size = size;
+    handle->state = LTC_SM_STATE_START;
+    handle->state_machine = ltc_process_message_in_sessions_EDMA;
+    retval = handle->state_machine(base, handle);
+    return retval;
+}
+
+status_t LTC_AES_DecryptCbcEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *ciphertext,
+                                uint8_t *plaintext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_AES_IV_SIZE],
+                                const uint8_t *key,
+                                uint32_t keySize,
+                                ltc_aes_key_t keyType)
+{
+    status_t retval;
+
+    if ((ltc_check_key_size(keySize) == 0) || (size < 16u) ||
+        (size % 16u)) /* CBC mode, size must be 16-byte multiple */
+    {
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_InvalidArgument, handle->userData);
+        }
+
+        return kStatus_InvalidArgument;
+    }
+
+    /* set DK bit in the LTC Mode Register AAI field for directly loaded decrypt keys */
+    if (keyType == kLTC_DecryptKey)
+    {
+        base->MD |= (1U << kLTC_ModeRegBitShiftDK);
+    }
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCBC, kLTC_ModeDecrypt);
+
+    /* Write IV data to the context register. */
+    ltc_set_context(base, &iv[0], LTC_AES_IV_SIZE, 0);
+
+    /* Process data and return status. */
+    handle->inData = &ciphertext[0];
+    handle->outData = &plaintext[0];
+    handle->size = size;
+    handle->state = LTC_SM_STATE_START;
+    handle->state_machine = ltc_process_message_in_sessions_EDMA;
+    retval = handle->state_machine(base, handle);
+    return retval;
+}
+
+status_t LTC_AES_CryptCtrEDMA(LTC_Type *base,
+                              ltc_edma_handle_t *handle,
+                              const uint8_t *input,
+                              uint8_t *output,
+                              uint32_t size,
+                              uint8_t counter[LTC_AES_BLOCK_SIZE],
+                              const uint8_t *key,
+                              uint32_t keySize,
+                              uint8_t counterlast[LTC_AES_BLOCK_SIZE],
+                              uint32_t *szLeft)
+{
+    status_t retval;
+    uint32_t lastSize;
+
+    if (!ltc_check_key_size(keySize))
+    {
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_InvalidArgument, handle->userData);
+        }
+        return kStatus_InvalidArgument;
+    }
+
+    lastSize = 0U;
+    if (counterlast != NULL)
+    {
+        /* Split the size into full 16-byte chunks and last incomplete block due to LTC AES OFIFO errata */
+        if (size <= 16U)
+        {
+            lastSize = size;
+            size = 0U;
+        }
+        else
+        {
+            /* Process all 16-byte data chunks. */
+            lastSize = size % 16U;
+            if (lastSize == 0U)
+            {
+                lastSize = 16U;
+                size -= 16U;
+            }
+            else
+            {
+                size -= lastSize; /* size will be rounded down to 16 byte boundary. remaining bytes in lastSize */
+            }
+        }
+    }
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, key, keySize, kLTC_AlgorithmAES, kLTC_ModeCTR, kLTC_ModeEncrypt);
+
+    /* Write initial counter data to the context register.
+     * NOTE the counter values start at 4-bytes offset into the context. */
+    ltc_set_context(base, &counter[0], 16U, 4U);
+
+    /* Process data and return status. */
+    handle->inData = &input[0];
+    handle->outData = &output[0];
+    handle->size = size;
+    handle->state = LTC_SM_STATE_START;
+    handle->state_machine = ltc_process_message_in_sessions_ctr_EDMA;
+
+    handle->counter = counter;
+    handle->key = key;
+    handle->keySize = keySize;
+    handle->counterlast = counterlast;
+    handle->szLeft = szLeft;
+    handle->lastSize = lastSize;
+    retval = handle->state_machine(base, handle);
+
+    return retval;
+}
+
+#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES
+/*******************************************************************************
+ * DES / 3DES Code static
+ ******************************************************************************/
+static status_t ltc_des_process_EDMA(LTC_Type *base,
+                                     ltc_edma_handle_t *handle,
+                                     const uint8_t *input,
+                                     uint8_t *output,
+                                     uint32_t size,
+                                     const uint8_t iv[LTC_DES_IV_SIZE],
+                                     const uint8_t key[LTC_DES_KEY_SIZE],
+                                     ltc_mode_symmetric_alg_t modeAs,
+                                     ltc_mode_encrypt_t modeEnc)
+{
+    status_t retval;
+
+    /* all but OFB, size must be 8-byte multiple */
+    if ((modeAs != kLTC_ModeOFB) && ((size < 8u) || (size % 8u)))
+    {
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_InvalidArgument, handle->userData);
+        }
+        return kStatus_InvalidArgument;
+    }
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, &key[0], LTC_DES_KEY_SIZE, kLTC_AlgorithmDES, modeAs, modeEnc);
+
+    if ((modeAs != kLTC_ModeECB))
+    {
+        ltc_set_context(base, iv, LTC_DES_IV_SIZE, 0);
+    }
+
+    /* Process data and return status. */
+    handle->inData = input;
+    handle->outData = output;
+    handle->size = size;
+    handle->state = LTC_SM_STATE_START;
+    handle->state_machine = ltc_process_message_in_sessions_EDMA;
+    retval = handle->state_machine(base, handle);
+
+    return retval;
+}
+
+static status_t ltc_3des_process_EDMA(LTC_Type *base,
+                                      ltc_edma_handle_t *handle,
+                                      const uint8_t *input,
+                                      uint8_t *output,
+                                      uint32_t size,
+                                      const uint8_t iv[LTC_DES_IV_SIZE],
+                                      const uint8_t key1[LTC_DES_KEY_SIZE],
+                                      const uint8_t key2[LTC_DES_KEY_SIZE],
+                                      const uint8_t key3[LTC_DES_KEY_SIZE],
+                                      ltc_mode_symmetric_alg_t modeAs,
+                                      ltc_mode_encrypt_t modeEnc)
+{
+    status_t retval;
+    uint8_t key[LTC_DES_KEY_SIZE * 3];
+    uint8_t keySize = LTC_DES_KEY_SIZE * 2;
+
+    retval = ltc_3des_check_input_args(modeAs, size, key1, key2);
+    if (kStatus_Success != retval)
+    {
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_InvalidArgument, handle->userData);
+        }
+        return retval;
+    }
+
+    ltc_memcpy(&key[0], &key1[0], LTC_DES_KEY_SIZE);
+    ltc_memcpy(&key[LTC_DES_KEY_SIZE], &key2[0], LTC_DES_KEY_SIZE);
+    if (key3)
+    {
+        ltc_memcpy(&key[LTC_DES_KEY_SIZE * 2], &key3[0], LTC_DES_KEY_SIZE);
+        keySize = sizeof(key);
+    }
+
+    /* Initialize algorithm state. */
+    ltc_symmetric_update(base, &key[0], keySize, kLTC_Algorithm3DES, modeAs, modeEnc);
+
+    if ((modeAs != kLTC_ModeECB))
+    {
+        ltc_set_context(base, iv, LTC_DES_IV_SIZE, 0);
+    }
+
+    /* Process data and return status. */
+    handle->inData = input;
+    handle->outData = output;
+    handle->size = size;
+    handle->state = LTC_SM_STATE_START;
+    handle->state_machine = ltc_process_message_in_sessions_EDMA;
+    retval = handle->state_machine(base, handle);
+
+    return retval;
+}
+/*******************************************************************************
+ * DES / 3DES Code public
+ ******************************************************************************/
+status_t LTC_DES_EncryptEcbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *plaintext,
+                                uint8_t *ciphertext,
+                                uint32_t size,
+                                const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process_EDMA(base, handle, plaintext, ciphertext, size, NULL, key, kLTC_ModeECB, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES_DecryptEcbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *ciphertext,
+                                uint8_t *plaintext,
+                                uint32_t size,
+                                const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process_EDMA(base, handle, ciphertext, plaintext, size, NULL, key, kLTC_ModeECB, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES_EncryptCbcEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *plaintext,
+                                uint8_t *ciphertext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_DES_IV_SIZE],
+                                const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key, kLTC_ModeCBC, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES_DecryptCbcEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *ciphertext,
+                                uint8_t *plaintext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_DES_IV_SIZE],
+                                const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key, kLTC_ModeCBC, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES_EncryptCfbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *plaintext,
+                                uint8_t *ciphertext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_DES_IV_SIZE],
+                                const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key, kLTC_ModeCFB, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES_DecryptCfbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *ciphertext,
+                                uint8_t *plaintext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_DES_IV_SIZE],
+                                const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key, kLTC_ModeCFB, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES_EncryptOfbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *plaintext,
+                                uint8_t *ciphertext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_DES_IV_SIZE],
+                                const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key, kLTC_ModeOFB, kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES_DecryptOfbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *ciphertext,
+                                uint8_t *plaintext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_DES_IV_SIZE],
+                                const uint8_t key[LTC_DES_KEY_SIZE])
+{
+    return ltc_des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key, kLTC_ModeOFB, kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES2_EncryptEcbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, NULL, key1, key2, NULL, kLTC_ModeECB,
+                                 kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES3_EncryptEcbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, NULL, key1, key2, key3, kLTC_ModeECB,
+                                 kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES2_DecryptEcbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, NULL, key1, key2, NULL, kLTC_ModeECB,
+                                 kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES3_DecryptEcbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, NULL, key1, key2, key3, kLTC_ModeECB,
+                                 kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES2_EncryptCbcEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key1, key2, NULL, kLTC_ModeCBC,
+                                 kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES3_EncryptCbcEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key1, key2, key3, kLTC_ModeCBC,
+                                 kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES2_DecryptCbcEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key1, key2, NULL, kLTC_ModeCBC,
+                                 kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES3_DecryptCbcEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key1, key2, key3, kLTC_ModeCBC,
+                                 kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES2_EncryptCfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key1, key2, NULL, kLTC_ModeCFB,
+                                 kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES3_EncryptCfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key1, key2, key3, kLTC_ModeCFB,
+                                 kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES2_DecryptCfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key1, key2, NULL, kLTC_ModeCFB,
+                                 kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES3_DecryptCfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key1, key2, key3, kLTC_ModeCFB,
+                                 kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES2_EncryptOfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key1, key2, NULL, kLTC_ModeOFB,
+                                 kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES3_EncryptOfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, plaintext, ciphertext, size, iv, key1, key2, key3, kLTC_ModeOFB,
+                                 kLTC_ModeEncrypt);
+}
+
+status_t LTC_DES2_DecryptOfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key1, key2, NULL, kLTC_ModeOFB,
+                                 kLTC_ModeDecrypt);
+}
+
+status_t LTC_DES3_DecryptOfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE])
+{
+    return ltc_3des_process_EDMA(base, handle, ciphertext, plaintext, size, iv, key1, key2, key3, kLTC_ModeOFB,
+                                 kLTC_ModeDecrypt);
+}
+#endif /* FSL_FEATURE_LTC_HAS_DES */
+
+/*********************** LTC EDMA tools ***************************************/
+
+static uint32_t LTC_GetInstance(LTC_Type *base)
+{
+    uint32_t instance = 0;
+    uint32_t i;
+
+    for (i = 0; i < FSL_FEATURE_SOC_LTC_COUNT; i++)
+    {
+        if (s_ltcBase[instance] == base)
+        {
+            instance = i;
+            break;
+        }
+    }
+    return instance;
+}
+
+/*!
+ * @brief Enable or disable LTC Input FIFO DMA request.
+ *
+ * This function enables or disables DMA request and done signals for Input FIFO.
+ *
+ * @param base LTC peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LTC_EnableInputFifoDMA(LTC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTL |= LTC_CTL_IFE_MASK;
+    }
+    else
+    {
+        base->CTL &= ~LTC_CTL_IFE_MASK;
+    }
+}
+
+/*!
+ * @brief Enable or disable LTC Output FIFO DMA request.
+ *
+ * This function enables or disables DMA request and done signals for Output FIFO.
+ *
+ * @param base LTC peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LTC_EnableOutputFifoDMA(LTC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTL |= LTC_CTL_OFE_MASK;
+    }
+    else
+    {
+        base->CTL &= ~LTC_CTL_OFE_MASK;
+    }
+}
+
+static void LTC_InputFifoEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
+{
+    ltc_edma_private_handle_t *ltcPrivateHandle = (ltc_edma_private_handle_t *)param;
+
+    /* Avoid the warning for unused variables. */
+    handle = handle;
+    tcds = tcds;
+
+    if (transferDone)
+    {
+        /* Stop DMA channel. */
+        EDMA_StopTransfer(ltcPrivateHandle->handle->inputFifoEdmaHandle);
+
+        /* Disable Input Fifo DMA */
+        LTC_EnableInputFifoDMA(ltcPrivateHandle->base, false);
+    }
+}
+
+static void LTC_OutputFifoEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
+{
+    ltc_edma_private_handle_t *ltcPrivateHandle = (ltc_edma_private_handle_t *)param;
+
+    /* Avoid the warning for unused variables. */
+    handle = handle;
+    tcds = tcds;
+
+    if (transferDone)
+    {
+        /* Stop DMA channel. */
+        EDMA_StopTransfer(ltcPrivateHandle->handle->outputFifoEdmaHandle);
+
+        /* Disable Output Fifo DMA */
+        LTC_EnableOutputFifoDMA(ltcPrivateHandle->base, false);
+
+        if (ltcPrivateHandle->handle->state_machine)
+        {
+            ltcPrivateHandle->handle->state_machine(ltcPrivateHandle->base, ltcPrivateHandle->handle);
+        }
+    }
+}
+
+/* @brief Copy data to Input FIFO and reading from Ouput FIFO using eDMA. */
+static void ltc_symmetric_process_EDMA(LTC_Type *base, uint32_t inSize, const uint8_t **inData, uint8_t **outData)
+{
+    const uint8_t *in = *inData;
+    uint8_t *out = *outData;
+    uint32_t instance = LTC_GetInstance(base);
+    uint32_t entry_number = inSize / sizeof(uint32_t);
+    const uint8_t *inputBuffer = *inData;
+    uint8_t *outputBuffer = *outData;
+    edma_transfer_config_t config;
+
+    if (entry_number)
+    {
+        /* =========== Init Input FIFO DMA ======================*/
+        memset(&config, 0, sizeof(config));
+
+        /* Prepare transfer. */
+        EDMA_PrepareTransfer(&config, (void *)inputBuffer, 1, (void *)(&((base)->IFIFO)), 4U, 4U, entry_number * 4,
+                             kEDMA_MemoryToPeripheral);
+        /* Submit transfer. */
+        EDMA_SubmitTransfer(s_edmaPrivateHandle[instance].handle->inputFifoEdmaHandle, &config);
+
+        /* Set request size.*/
+        base->CTL &= ~LTC_CTL_IFR_MASK; /* 1 entry */
+        /* Enable Input Fifo DMA */
+        LTC_EnableInputFifoDMA(base, true);
+
+        /* Start the DMA channel */
+        EDMA_StartTransfer(s_edmaPrivateHandle[instance].handle->inputFifoEdmaHandle);
+
+        /* =========== Init Output FIFO DMA ======================*/
+        memset(&config, 0, sizeof(config));
+
+        /* Prepare transfer. */
+        EDMA_PrepareTransfer(&config, (void *)(&((base)->OFIFO)), 4U, (void *)outputBuffer, 1U, 4U, entry_number * 4,
+                             kEDMA_PeripheralToMemory);
+        /* Submit transfer. */
+        EDMA_SubmitTransfer(s_edmaPrivateHandle[instance].handle->outputFifoEdmaHandle, &config);
+
+        /* Set request size.*/
+        base->CTL &= ~LTC_CTL_OFR_MASK; /* 1 entry */
+
+        /* Enable Output Fifo DMA */
+        LTC_EnableOutputFifoDMA(base, true);
+
+        /* Start the DMA channel */
+        EDMA_StartTransfer(s_edmaPrivateHandle[instance].handle->outputFifoEdmaHandle);
+
+        { /* Dummy read of LTC register. Do not delete.*/
+            volatile uint32_t status_reg;
+
+            status_reg = (base)->STA;
+
+            (void)status_reg;
+        }
+
+        out += entry_number * sizeof(uint32_t);
+        in += entry_number * sizeof(uint32_t);
+
+        *inData = in;
+        *outData = out;
+    }
+}
+
+void LTC_CreateHandleEDMA(LTC_Type *base,
+                          ltc_edma_handle_t *handle,
+                          ltc_edma_callback_t callback,
+                          void *userData,
+                          edma_handle_t *inputFifoEdmaHandle,
+                          edma_handle_t *outputFifoEdmaHandle)
+{
+    assert(handle);
+    assert(inputFifoEdmaHandle);
+    assert(outputFifoEdmaHandle);
+
+    uint32_t instance = LTC_GetInstance(base);
+
+    s_edmaPrivateHandle[instance].base = base;
+    s_edmaPrivateHandle[instance].handle = handle;
+
+    memset(handle, 0, sizeof(*handle));
+
+    handle->inputFifoEdmaHandle = inputFifoEdmaHandle;
+    handle->outputFifoEdmaHandle = outputFifoEdmaHandle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Register DMA callback functions */
+    EDMA_SetCallback(handle->inputFifoEdmaHandle, LTC_InputFifoEDMACallback, &s_edmaPrivateHandle[instance]);
+    EDMA_SetCallback(handle->outputFifoEdmaHandle, LTC_OutputFifoEDMACallback, &s_edmaPrivateHandle[instance]);
+
+    /* Set request size. DMA request size is 1 entry.*/
+    base->CTL &= ~LTC_CTL_IFR_MASK;
+    base->CTL &= ~LTC_CTL_OFR_MASK;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc_edma.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc_edma.h
new file mode 100644
index 00000000000..5456fb443b6
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_ltc_edma.h
@@ -0,0 +1,850 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_LTC_EDMA_H_
+#define _FSL_LTC_EDMA_H_
+
+#include "fsl_common.h"
+
+#include "fsl_ltc.h"
+#include "fsl_dmamux.h"
+#include "fsl_edma.h"
+
+/*!
+ * @addtogroup ltc_edma_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* @brief The LTC eDMA handle type. */
+typedef struct _ltc_edma_handle ltc_edma_handle_t;
+
+/*! @brief LTC eDMA callback function. */
+typedef void (*ltc_edma_callback_t)(LTC_Type *base, ltc_edma_handle_t *handle, status_t status, void *userData);
+
+/*! @brief LTC eDMA state machine function. It is defined only for private usage inside LTC eDMA driver. */
+typedef status_t (*ltc_edma_state_machine_t)(LTC_Type *base, ltc_edma_handle_t *handle);
+
+/*!
+* @brief LTC eDMA handle. It is defined only for private usage inside LTC eDMA driver.
+*/
+struct _ltc_edma_handle
+{
+    ltc_edma_callback_t callback; /*!< Callback function. */
+    void *userData;               /*!< LTC callback function parameter.*/
+
+    edma_handle_t *inputFifoEdmaHandle;  /*!< The eDMA TX channel used. */
+    edma_handle_t *outputFifoEdmaHandle; /*!< The eDMA RX channel used. */
+
+    ltc_edma_state_machine_t state_machine; /*!< State machine. */
+    uint32_t state;                         /*!< Internal state. */
+    const uint8_t *inData;                  /*!< Input data. */
+    uint8_t *outData;                       /*!< Output data. */
+    uint32_t size;                          /*!< Size of input and output data in bytes.*/
+    uint32_t modeReg;                       /*!< LTC mode register.*/
+    /* Used by AES CTR*/
+    uint8_t *counter;   /*!< Input counter (updates on return)*/
+    const uint8_t *key; /*!< Input key to use for forward AES cipher*/
+    uint32_t keySize;   /*!< Size of the input key, in bytes. Must be 16, 24, or 32.*/
+    uint8_t
+        *counterlast; /*!< Output cipher of last counter, for chained CTR calls. NULL can be passed if chained calls are
+                         not used.*/
+    uint32_t *szLeft; /*!< Output number of bytes in left unused in counterlast block. NULL can be passed if chained
+                         calls are not used.*/
+    uint32_t lastSize; /*!< Last size.*/
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Init the LTC eDMA handle which is used in transcational functions
+ * @param base      LTC module base address
+ * @param handle    Pointer to ltc_edma_handle_t structure
+ * @param callback  Callback function, NULL means no callback.
+ * @param userData  Callback function parameter.
+ * @param inputFifoEdmaHandle User requested eDMA handle for Input FIFO eDMA.
+ * @param outputFifoEdmaHandle User requested eDMA handle for Output FIFO eDMA.
+ */
+void LTC_CreateHandleEDMA(LTC_Type *base,
+                          ltc_edma_handle_t *handle,
+                          ltc_edma_callback_t callback,
+                          void *userData,
+                          edma_handle_t *inputFifoEdmaHandle,
+                          edma_handle_t *outputFifoEdmaHandle);
+
+/*! @}*/
+
+/*******************************************************************************
+ * AES API
+ ******************************************************************************/
+
+/*!
+ * @addtogroup ltc_edma_driver_aes
+ * @{
+ */
+
+/*!
+ * @brief Encrypts AES using the ECB block mode.
+ *
+ * Encrypts AES using the ECB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param key Input key to use for encryption
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @return Status from encrypt operation
+ */
+status_t LTC_AES_EncryptEcbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *plaintext,
+                                uint8_t *ciphertext,
+                                uint32_t size,
+                                const uint8_t *key,
+                                uint32_t keySize);
+
+/*!
+ * @brief Decrypts AES using ECB block mode.
+ *
+ * Decrypts AES using ECB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param key Input key.
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @param keyType Input type of the key (allows to directly load decrypt key for AES ECB decrypt operation.)
+ * @return Status from decrypt operation
+ */
+status_t LTC_AES_DecryptEcbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *ciphertext,
+                                uint8_t *plaintext,
+                                uint32_t size,
+                                const uint8_t *key,
+                                uint32_t keySize,
+                                ltc_aes_key_t keyType);
+
+/*!
+ * @brief Encrypts AES using CBC block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @param key Input key to use for encryption
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @return Status from encrypt operation
+ */
+status_t LTC_AES_EncryptCbcEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *plaintext,
+                                uint8_t *ciphertext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_AES_IV_SIZE],
+                                const uint8_t *key,
+                                uint32_t keySize);
+
+/*!
+ * @brief Decrypts AES using CBC block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @param key Input key to use for decryption
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @param keyType Input type of the key (allows to directly load decrypt key for AES CBC decrypt operation.)
+ * @return Status from decrypt operation
+ */
+status_t LTC_AES_DecryptCbcEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *ciphertext,
+                                uint8_t *plaintext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_AES_IV_SIZE],
+                                const uint8_t *key,
+                                uint32_t keySize,
+                                ltc_aes_key_t keyType);
+
+/*!
+ * @brief Encrypts or decrypts AES using CTR block mode.
+ *
+ * Encrypts or decrypts AES using CTR block mode.
+ * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption.
+ * The only difference between encryption and decryption is that, for encryption, the input argument
+ * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text
+ * and the output argument is plain text.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param input Input data for CTR block mode
+ * @param[out] output Output data for CTR block mode
+ * @param size Size of input and output data in bytes
+ * @param[in,out] counter Input counter (updates on return)
+ * @param key Input key to use for forward AES cipher
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @param[out] counterlast Output cipher of last counter, for chained CTR calls. NULL can be passed if chained calls are
+ * not used.
+ * @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls
+ * are not used.
+ * @return Status from encrypt operation
+ */
+status_t LTC_AES_CryptCtrEDMA(LTC_Type *base,
+                              ltc_edma_handle_t *handle,
+                              const uint8_t *input,
+                              uint8_t *output,
+                              uint32_t size,
+                              uint8_t counter[LTC_AES_BLOCK_SIZE],
+                              const uint8_t *key,
+                              uint32_t keySize,
+                              uint8_t counterlast[LTC_AES_BLOCK_SIZE],
+                              uint32_t *szLeft);
+
+/*! AES CTR decrypt is mapped to the AES CTR generic operation */
+#define LTC_AES_DecryptCtrEDMA(base, handle, input, output, size, counter, key, keySize, counterlast, szLeft) \
+    LTC_AES_CryptCtrEDMA(base, handle, input, output, size, counter, key, keySize, counterlast, szLeft)
+
+/*! AES CTR encrypt is mapped to the AES CTR generic operation */
+#define LTC_AES_EncryptCtrEDMA(base, handle, input, output, size, counter, key, keySize, counterlast, szLeft) \
+    LTC_AES_CryptCtrEDMA(base, handle, input, output, size, counter, key, keySize, counterlast, szLeft)
+
+/*!
+ *@}
+ */
+
+/*******************************************************************************
+ * DES API
+ ******************************************************************************/
+/*!
+ * @addtogroup ltc_edma_driver_des
+ * @{
+ */
+/*!
+ * @brief Encrypts DES using ECB block mode.
+ *
+ * Encrypts DES using ECB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param key Input key to use for encryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_EncryptEcbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *plaintext,
+                                uint8_t *ciphertext,
+                                uint32_t size,
+                                const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts DES using ECB block mode.
+ *
+ * Decrypts DES using ECB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param key Input key to use for decryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_DecryptEcbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *ciphertext,
+                                uint8_t *plaintext,
+                                uint32_t size,
+                                const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts DES using CBC block mode.
+ *
+ * Encrypts DES using CBC block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Ouput ciphertext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector to combine with the first plaintext block.
+ *           The iv does not need to be secret, but it must be unpredictable.
+ * @param key Input key to use for encryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_EncryptCbcEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *plaintext,
+                                uint8_t *ciphertext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_DES_IV_SIZE],
+                                const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts DES using CBC block mode.
+ *
+ * Decrypts DES using CBC block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input data in bytes
+ * @param iv Input initial vector to combine with the first plaintext block.
+ *           The iv does not need to be secret, but it must be unpredictable.
+ * @param key Input key to use for decryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_DecryptCbcEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *ciphertext,
+                                uint8_t *plaintext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_DES_IV_SIZE],
+                                const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts DES using CFB block mode.
+ *
+ * Encrypts DES using CFB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plaintext to encrypt
+ * @param size Size of input data in bytes
+ * @param iv Input initial block.
+ * @param key Input key to use for encryption
+ * @param[out] ciphertext Output ciphertext
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_EncryptCfbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *plaintext,
+                                uint8_t *ciphertext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_DES_IV_SIZE],
+                                const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts DES using CFB block mode.
+ *
+ * Decrypts DES using CFB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial block.
+ * @param key Input key to use for decryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_DecryptCfbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *ciphertext,
+                                uint8_t *plaintext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_DES_IV_SIZE],
+                                const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts DES using OFB block mode.
+ *
+ * Encrypts DES using OFB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes
+ * @param iv Input unique input vector. The OFB mode requires that the IV be unique
+ *           for each execution of the mode under the given key.
+ * @param key Input key to use for encryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_EncryptOfbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *plaintext,
+                                uint8_t *ciphertext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_DES_IV_SIZE],
+                                const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts DES using OFB block mode.
+ *
+ * Decrypts DES using OFB block mode.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param iv Input unique input vector. The OFB mode requires that the IV be unique
+ *           for each execution of the mode under the given key.
+ * @param key Input key to use for decryption
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES_DecryptOfbEDMA(LTC_Type *base,
+                                ltc_edma_handle_t *handle,
+                                const uint8_t *ciphertext,
+                                uint8_t *plaintext,
+                                uint32_t size,
+                                const uint8_t iv[LTC_DES_IV_SIZE],
+                                const uint8_t key[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using ECB block mode with two keys.
+ *
+ * Encrypts triple DES using ECB block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_EncryptEcbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using ECB block mode with two keys.
+ *
+ * Decrypts triple DES using ECB block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_DecryptEcbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using CBC block mode with two keys.
+ *
+ * Encrypts triple DES using CBC block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector to combine with the first plaintext block.
+ *           The iv does not need to be secret, but it must be unpredictable.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_EncryptCbcEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using CBC block mode with two keys.
+ *
+ * Decrypts triple DES using CBC block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector to combine with the first plaintext block.
+ *           The iv does not need to be secret, but it must be unpredictable.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_DecryptCbcEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using CFB block mode with two keys.
+ *
+ * Encrypts triple DES using CFB block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial block.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_EncryptCfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using CFB block mode with two keys.
+ *
+ * Decrypts triple DES using CFB block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial block.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_DecryptCfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using OFB block mode with two keys.
+ *
+ * Encrypts triple DES using OFB block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes
+ * @param iv Input unique input vector. The OFB mode requires that the IV be unique
+ *           for each execution of the mode under the given key.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_EncryptOfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using OFB block mode with two keys.
+ *
+ * Decrypts triple DES using OFB block mode with two keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes
+ * @param iv Input unique input vector. The OFB mode requires that the IV be unique
+ *           for each execution of the mode under the given key.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES2_DecryptOfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using ECB block mode with three keys.
+ *
+ * Encrypts triple DES using ECB block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_EncryptEcbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using ECB block mode with three keys.
+ *
+ * Decrypts triple DES using ECB block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes. Must be multiple of 8 bytes.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_DecryptEcbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using CBC block mode with three keys.
+ *
+ * Encrypts triple DES using CBC block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input data in bytes
+ * @param iv Input initial vector to combine with the first plaintext block.
+ *           The iv does not need to be secret, but it must be unpredictable.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_EncryptCbcEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using CBC block mode with three keys.
+ *
+ * Decrypts triple DES using CBC block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector to combine with the first plaintext block.
+ *           The iv does not need to be secret, but it must be unpredictable.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_DecryptCbcEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using CFB block mode with three keys.
+ *
+ * Encrypts triple DES using CFB block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and ouput data in bytes
+ * @param iv Input initial block.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_EncryptCfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using CFB block mode with three keys.
+ *
+ * Decrypts triple DES using CFB block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input data in bytes
+ * @param iv Input initial block.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_DecryptCfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Encrypts triple DES using OFB block mode with three keys.
+ *
+ * Encrypts triple DES using OFB block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param plaintext Input plaintext to encrypt
+ * @param[out] ciphertext Output ciphertext
+ * @param size Size of input and output data in bytes
+ * @param iv Input unique input vector. The OFB mode requires that the IV be unique
+ *           for each execution of the mode under the given key.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_EncryptOfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *plaintext,
+                                 uint8_t *ciphertext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ * @brief Decrypts triple DES using OFB block mode with three keys.
+ *
+ * Decrypts triple DES using OFB block mode with three keys.
+ *
+ * @param base LTC peripheral base address
+ * @param handle pointer to ltc_edma_handle_t structure which stores the transaction state.
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plaintext
+ * @param size Size of input and output data in bytes
+ * @param iv Input unique input vector. The OFB mode requires that the IV be unique
+ *           for each execution of the mode under the given key.
+ * @param key1 First input key for key bundle
+ * @param key2 Second input key for key bundle
+ * @param key3 Third input key for key bundle
+ * @return Status from encrypt/decrypt operation
+ */
+status_t LTC_DES3_DecryptOfbEDMA(LTC_Type *base,
+                                 ltc_edma_handle_t *handle,
+                                 const uint8_t *ciphertext,
+                                 uint8_t *plaintext,
+                                 uint32_t size,
+                                 const uint8_t iv[LTC_DES_IV_SIZE],
+                                 const uint8_t key1[LTC_DES_KEY_SIZE],
+                                 const uint8_t key2[LTC_DES_KEY_SIZE],
+                                 const uint8_t key3[LTC_DES_KEY_SIZE]);
+
+/*!
+ *@}
+ */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_LTC_EDMA_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_mpu.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_mpu.c
new file mode 100644
index 00000000000..8e0e77df570
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_mpu.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_mpu.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+const clock_ip_name_t g_mpuClock[FSL_FEATURE_SOC_MPU_COUNT] = MPU_CLOCKS;
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+void MPU_Init(MPU_Type *base, const mpu_config_t *config)
+{
+    assert(config);
+    uint8_t count;
+
+    /* Un-gate MPU clock */
+    CLOCK_EnableClock(g_mpuClock[0]);
+
+    /* Initializes the regions. */
+    for (count = 1; count < FSL_FEATURE_MPU_DESCRIPTOR_COUNT; count++)
+    {
+        base->WORD[count][3] = 0; /* VLD/VID+PID. */
+        base->WORD[count][0] = 0; /* Start address. */
+        base->WORD[count][1] = 0; /* End address. */
+        base->WORD[count][2] = 0; /* Access rights. */
+        base->RGDAAC[count] = 0;  /* Alternate access rights. */
+    }
+
+    /* MPU configure. */
+    while (config)
+    {
+        MPU_SetRegionConfig(base, &(config->regionConfig));
+        config = config->next;
+    }
+    /* Enable MPU. */
+    MPU_Enable(base, true);
+}
+
+void MPU_Deinit(MPU_Type *base)
+{
+    /* Disable MPU. */
+    MPU_Enable(base, false);
+
+    /* Gate the clock. */
+    CLOCK_DisableClock(g_mpuClock[0]);
+}
+
+void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform)
+{
+    assert(hardwareInform);
+
+    uint32_t cesReg = base->CESR;
+
+    hardwareInform->hardwareRevisionLevel = (cesReg & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT;
+    hardwareInform->slavePortsNumbers = (cesReg & MPU_CESR_NSP_MASK) >> MPU_CESR_NSP_SHIFT;
+    hardwareInform->regionsNumbers = (mpu_region_total_num_t)((cesReg & MPU_CESR_NRGD_MASK) >> MPU_CESR_NRGD_SHIFT);
+}
+
+void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig)
+{
+    assert(regionConfig);
+    assert(regionConfig->regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT);
+
+    uint32_t wordReg = 0;
+    uint8_t msPortNum;
+    uint8_t regNumber = regionConfig->regionNum;
+
+    /* The start and end address of the region descriptor. */
+    base->WORD[regNumber][0] = regionConfig->startAddress;
+    base->WORD[regNumber][1] = regionConfig->endAddress;
+
+    /* Set the privilege rights for master 0 ~ master 3. */
+    for (msPortNum = 0; msPortNum <= FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX; msPortNum++)
+    {
+        wordReg |= MPU_REGION_RWXRIGHTS_MASTER(
+            msPortNum, (((uint32_t)regionConfig->accessRights1[msPortNum].superAccessRights << 3U) |
+                        (uint32_t)regionConfig->accessRights1[msPortNum].userAccessRights));
+
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+        wordReg |=
+            MPU_REGION_RWXRIGHTS_MASTER_PE(msPortNum, regionConfig->accessRights1[msPortNum].processIdentifierEnable);
+#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
+    }
+
+    /* Set the normal read write rights for master 4 ~ master 7. */
+    for (msPortNum = FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT; msPortNum < FSL_FEATURE_MPU_MASTER_COUNT;
+         msPortNum++)
+    {
+        wordReg |= MPU_REGION_RWRIGHTS_MASTER(msPortNum,
+            ((uint32_t)regionConfig->accessRights2[msPortNum - FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT].readEnable << 1U |
+            (uint32_t)regionConfig->accessRights2[msPortNum - FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT].writeEnable));
+    }
+
+    /* Set region descriptor access rights. */
+    base->WORD[regNumber][2] = wordReg;
+
+    wordReg = MPU_WORD_VLD(1);
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+    wordReg |= MPU_WORD_PID(regionConfig->processIdentifier) | MPU_WORD_PIDMASK(regionConfig->processIdMask);
+#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
+
+    base->WORD[regNumber][3] = wordReg;
+}
+
+void MPU_SetRegionAddr(MPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr)
+{
+    assert(regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT);
+
+    base->WORD[regionNum][0] = startAddr;
+    base->WORD[regionNum][1] = endAddr;
+}
+
+void MPU_SetRegionRwxMasterAccessRights(MPU_Type *base,
+                                        uint32_t regionNum,
+                                        uint32_t masterNum,
+                                        const mpu_rwxrights_master_access_control_t *accessRights)
+{
+    assert(accessRights);
+    assert(regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT);
+    assert(masterNum <= FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX);
+
+    uint32_t mask = MPU_REGION_RWXRIGHTS_MASTER_MASK(masterNum);
+    uint32_t right = base->RGDAAC[regionNum];
+
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+    mask |= MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(masterNum);
+#endif
+
+    /* Build rights control value. */
+    right &= ~mask;
+    right |= MPU_REGION_RWXRIGHTS_MASTER(
+        masterNum, ((uint32_t)(accessRights->superAccessRights << 3U) | accessRights->userAccessRights));
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+    right |= MPU_REGION_RWXRIGHTS_MASTER_PE(masterNum, accessRights->processIdentifierEnable);
+#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
+
+    /* Set low master region access rights. */
+    base->RGDAAC[regionNum] = right;
+}
+
+void MPU_SetRegionRwMasterAccessRights(MPU_Type *base,
+                                       uint32_t regionNum,
+                                       uint32_t masterNum,
+                                       const mpu_rwrights_master_access_control_t *accessRights)
+{
+    assert(accessRights);
+    assert(regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT);
+    assert(masterNum > FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX);
+    assert(masterNum <= FSL_FEATURE_MPU_MASTER_MAX_INDEX);
+
+    uint32_t mask = MPU_REGION_RWRIGHTS_MASTER_MASK(masterNum);
+    uint32_t right = base->RGDAAC[regionNum];
+
+    /* Build rights control value. */
+    right &= ~mask;
+    right |=
+        MPU_REGION_RWRIGHTS_MASTER(masterNum, (((uint32_t)accessRights->readEnable << 1U) | accessRights->writeEnable));
+    /* Set low master region access rights. */
+    base->RGDAAC[regionNum] = right;
+}
+
+bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum)
+{
+    uint8_t sperr;
+
+    sperr = ((base->CESR & MPU_CESR_SPERR_MASK) >> MPU_CESR_SPERR_SHIFT) & (0x1U << slaveNum);
+
+    return (sperr != 0) ? true : false;
+}
+
+void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform)
+{
+    assert(errInform);
+
+    uint16_t value;
+    uint32_t cesReg;
+
+    /* Error address. */
+    errInform->address = base->SP[slaveNum].EAR;
+
+    /* Error detail information. */
+    value = (base->SP[slaveNum].EDR & MPU_EDR_EACD_MASK) >> MPU_EDR_EACD_SHIFT;
+    if (!value)
+    {
+        errInform->accessControl = kMPU_NoRegionHit;
+    }
+    else if (!(value & (uint16_t)(value - 1)))
+    {
+        errInform->accessControl = kMPU_NoneOverlappRegion;
+    }
+    else
+    {
+        errInform->accessControl = kMPU_OverlappRegion;
+    }
+
+    value = base->SP[slaveNum].EDR;
+    errInform->master = (uint32_t)((value & MPU_EDR_EMN_MASK) >> MPU_EDR_EMN_SHIFT);
+    errInform->attributes = (mpu_err_attributes_t)((value & MPU_EDR_EATTR_MASK) >> MPU_EDR_EATTR_SHIFT);
+    errInform->accessType = (mpu_err_access_type_t)((value & MPU_EDR_ERW_MASK) >> MPU_EDR_ERW_SHIFT);
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+    errInform->processorIdentification = (uint8_t)((value & MPU_EDR_EPID_MASK) >> MPU_EDR_EPID_SHIFT);
+#endif
+
+    /* Clears error slave port bit. */
+    cesReg = (base->CESR & ~MPU_CESR_SPERR_MASK) | ((0x1U << slaveNum) << MPU_CESR_SPERR_SHIFT);
+    base->CESR = cesReg;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_mpu.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_mpu.h
new file mode 100644
index 00000000000..d39d78ae48f
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_mpu.h
@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_MPU_H_
+#define _FSL_MPU_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup mpu
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief MPU driver version 2.1.0. */
+#define FSL_MPU_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*@}*/
+
+/*! @brief MPU the bit shift for masters with privilege rights: read write and execute. */
+#define MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n) (n * 6)
+
+/*! @brief MPU masters with read, write and execute rights bit mask. */
+#define MPU_REGION_RWXRIGHTS_MASTER_MASK(n) (0x1Fu << MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))
+
+/*! @brief MPU masters with read, write and execute rights bit width. */
+#define MPU_REGION_RWXRIGHTS_MASTER_WIDTH 5
+
+/*! @brief MPU masters with read, write and execute rights priority setting. */
+#define MPU_REGION_RWXRIGHTS_MASTER(n, x) \
+    (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))) & MPU_REGION_RWXRIGHTS_MASTER_MASK(n))
+
+/*! @brief MPU masters with read, write and execute rights process enable bit shift. */
+#define MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n) (n * 6 + MPU_REGION_RWXRIGHTS_MASTER_WIDTH)
+
+/*! @brief MPU masters with read, write and execute rights process enable bit mask. */
+#define MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n) (0x1u << MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))
+
+/*! @brief MPU masters with read, write and execute rights process enable setting. */
+#define MPU_REGION_RWXRIGHTS_MASTER_PE(n, x) \
+    (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))) & MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n))
+
+/*! @brief MPU masters with normal read write permission bit shift. */
+#define MPU_REGION_RWRIGHTS_MASTER_SHIFT(n) ((n - FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT) * 2 + 24)
+
+/*! @brief MPU masters with normal read write rights bit mask. */
+#define MPU_REGION_RWRIGHTS_MASTER_MASK(n) (0x3u << MPU_REGION_RWRIGHTS_MASTER_SHIFT(n))
+
+/*! @brief MPU masters with normal read write rights priority setting. */
+#define MPU_REGION_RWRIGHTS_MASTER(n, x) \
+    (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWRIGHTS_MASTER_SHIFT(n))) & MPU_REGION_RWRIGHTS_MASTER_MASK(n))
+
+/*! @brief Describes the number of MPU regions. */
+typedef enum _mpu_region_total_num
+{
+    kMPU_8Regions = 0x0U,  /*!< MPU supports 8 regions.  */
+    kMPU_12Regions = 0x1U, /*!< MPU supports 12 regions. */
+    kMPU_16Regions = 0x2U  /*!< MPU supports 16 regions. */
+} mpu_region_total_num_t;
+
+/*! @brief MPU slave port number. */
+typedef enum _mpu_slave
+{
+    kMPU_Slave0 = 4U, /*!< MPU slave port 0. */
+    kMPU_Slave1 = 3U, /*!< MPU slave port 1. */
+    kMPU_Slave2 = 2U, /*!< MPU slave port 2. */
+    kMPU_Slave3 = 1U, /*!< MPU slave port 3. */
+    kMPU_Slave4 = 0U  /*!< MPU slave port 4. */
+} mpu_slave_t;
+
+/*! @brief MPU error access control detail. */
+typedef enum _mpu_err_access_control
+{
+    kMPU_NoRegionHit = 0U,        /*!< No region hit error. */
+    kMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */
+    kMPU_OverlappRegion = 2U      /*!< Access overlapping region error. */
+} mpu_err_access_control_t;
+
+/*! @brief MPU error access type. */
+typedef enum _mpu_err_access_type
+{
+    kMPU_ErrTypeRead = 0U, /*!< MPU error access type --- read.  */
+    kMPU_ErrTypeWrite = 1U /*!< MPU error access type --- write. */
+} mpu_err_access_type_t;
+
+/*! @brief MPU access error attributes.*/
+typedef enum _mpu_err_attributes
+{
+    kMPU_InstructionAccessInUserMode = 0U,       /*!< Access instruction error in user mode. */
+    kMPU_DataAccessInUserMode = 1U,              /*!< Access data error in user mode. */
+    kMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */
+    kMPU_DataAccessInSupervisorMode = 3U         /*!< Access data error in supervisor mode. */
+} mpu_err_attributes_t;
+
+/*! @brief MPU access rights in supervisor mode for bus master 0 ~ 3. */
+typedef enum _mpu_supervisor_access_rights
+{
+    kMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */
+    kMPU_SupervisorReadExecute = 1U,      /*!< Read and execute operations are allowed in supervisor mode. */
+    kMPU_SupervisorReadWrite = 2U,        /*!< Read write operations are allowed in supervisor mode. */
+    kMPU_SupervisorEqualToUsermode = 3U   /*!< Access permission equal to user mode. */
+} mpu_supervisor_access_rights_t;
+
+/*! @brief MPU access rights in user mode for bus master 0 ~ 3. */
+typedef enum _mpu_user_access_rights
+{
+    kMPU_UserNoAccessRights = 0U,  /*!< No access allowed in user mode.  */
+    kMPU_UserExecute = 1U,         /*!< Execute operation is allowed in user mode. */
+    kMPU_UserWrite = 2U,           /*!< Write operation is allowed in user mode. */
+    kMPU_UserWriteExecute = 3U,    /*!< Write and execute operations are allowed in user mode. */
+    kMPU_UserRead = 4U,            /*!< Read is allowed in user mode. */
+    kMPU_UserReadExecute = 5U,     /*!< Read and execute operations are allowed in user mode. */
+    kMPU_UserReadWrite = 6U,       /*!< Read and write operations are allowed in user mode. */
+    kMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */
+} mpu_user_access_rights_t;
+
+/*! @brief MPU hardware basic information. */
+typedef struct _mpu_hardware_info
+{
+    uint8_t hardwareRevisionLevel;         /*!< Specifies the MPU's hardware and definition reversion level. */
+    uint8_t slavePortsNumbers;             /*!< Specifies the number of slave ports connected to MPU. */
+    mpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */
+} mpu_hardware_info_t;
+
+/*! @brief MPU detail error access information. */
+typedef struct _mpu_access_err_info
+{
+    uint32_t master;                        /*!< Access error master. */
+    mpu_err_attributes_t attributes;        /*!< Access error attributes. */
+    mpu_err_access_type_t accessType;       /*!< Access error type. */
+    mpu_err_access_control_t accessControl; /*!< Access error control. */
+    uint32_t address;                       /*!< Access error address. */
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+    uint8_t processorIdentification; /*!< Access error processor identification. */
+#endif                               /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
+} mpu_access_err_info_t;
+
+/*! @brief MPU read/write/execute rights control for bus master 0 ~ 3. */
+typedef struct _mpu_rwxrights_master_access_control
+{
+    mpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */
+    mpu_user_access_rights_t userAccessRights;        /*!< Master access rights in user mode. */
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+    bool processIdentifierEnable; /*!< Enables or disables process identifier. */
+#endif                            /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
+} mpu_rwxrights_master_access_control_t;
+
+/*! @brief MPU read/write access control for bus master 4 ~ 7. */
+typedef struct _mpu_rwrights_master_access_control
+{
+    bool writeEnable; /*!< Enables or disables write permission. */
+    bool readEnable;  /*!< Enables or disables read permission.  */
+} mpu_rwrights_master_access_control_t;
+
+/*!
+ * @brief MPU region configuration structure.
+ *
+ * This structure is used to configure the regionNum region.
+ * The accessRights1[0] ~ accessRights1[3] are used to configure the bus master
+ * 0 ~ 3 with the privilege rights setting. The accessRights2[0] ~ accessRights2[3]
+ * are used to configure the high master 4 ~ 7 with the normal read write permission.
+ * The master port assignment is the chip configuration. Normally, the core is the
+ * master 0, debugger is the master 1.
+ * Note: MPU assigns a priority scheme where the debugger is treated as the highest
+ * priority master followed by the core and then all the remaining masters.
+ * MPU protection does not allow writes from the core to affect the "regionNum 0" start
+ * and end address nor the permissions associated with the debugger. It can only write
+ * the permission fields associated with the other masters. This protection guarantee
+ * the debugger always has access to the entire address space and those rights can't
+ * be changed by the core or any other bus master. Prepare
+ * the region configuration when regionNum is 0.
+ */
+typedef struct _mpu_region_config
+{
+    uint32_t regionNum;    /*!< MPU region number, range form 0 ~ FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1. */
+    uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by MPU. The actual
+                              start address is 0-modulo-32 byte address.  */
+    uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. The actual end
+                          address is 31-modulo-32 byte address. */
+    mpu_rwxrights_master_access_control_t accessRights1[4]; /*!< Masters with read, write and execute rights setting. */
+    mpu_rwrights_master_access_control_t accessRights2[4];  /*!< Masters with normal read write rights setting. */
+#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
+    uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */
+    uint8_t
+        processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */
+#endif                 /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
+} mpu_region_config_t;
+
+/*!
+ * @brief The configuration structure for the MPU initialization.
+ *
+ * This structure is used when calling the MPU_Init function.
+ */
+typedef struct _mpu_config
+{
+    mpu_region_config_t regionConfig; /*!< region access permission. */
+    struct _mpu_config *next;         /*!< pointer to the next structure. */
+} mpu_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the MPU with the user configuration structure.
+ *
+ * This function configures the MPU module with the user-defined configuration.
+ *
+ * @param base     MPU peripheral base address.
+ * @param config   The pointer to the configuration structure.
+ */
+void MPU_Init(MPU_Type *base, const mpu_config_t *config);
+
+/*!
+ * @brief Deinitializes the MPU regions.
+ *
+ * @param base     MPU peripheral base address.
+ */
+void MPU_Deinit(MPU_Type *base);
+
+/* @}*/
+
+/*!
+ * @name Basic Control Operations
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the MPU globally.
+ *
+ * Call this API to enable or disable the MPU module.
+ *
+ * @param base     MPU peripheral base address.
+ * @param enable   True enable MPU, false disable MPU.
+ */
+static inline void MPU_Enable(MPU_Type *base, bool enable)
+{
+    if (enable)
+    {
+        /* Enable the MPU globally. */
+        base->CESR |= MPU_CESR_VLD_MASK;
+    }
+    else
+    { /* Disable the MPU globally. */
+        base->CESR &= ~MPU_CESR_VLD_MASK;
+    }
+}
+
+/*!
+ * @brief Enables/disables the MPU for a special region.
+ *
+ * When MPU is enabled, call this API to disable an unused region
+ * of an enabled MPU. Call this API to minimize the power dissipation.
+ *
+ * @param base     MPU peripheral base address.
+ * @param number   MPU region number.
+ * @param enable   True enable the special region MPU, false disable the special region MPU.
+ */
+static inline void MPU_RegionEnable(MPU_Type *base, uint32_t number, bool enable)
+{
+    if (enable)
+    {
+        /* Enable the #number region MPU. */
+        base->WORD[number][3] |= MPU_WORD_VLD_MASK;
+    }
+    else
+    { /* Disable the #number region MPU. */
+        base->WORD[number][3] &= ~MPU_WORD_VLD_MASK;
+    }
+}
+
+/*!
+ * @brief Gets the MPU basic hardware information.
+ *
+ * @param base           MPU peripheral base address.
+ * @param hardwareInform The pointer to the MPU hardware information structure. See "mpu_hardware_info_t".
+ */
+void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform);
+
+/*!
+ * @brief Sets the MPU region.
+ *
+ * Note: Due to the MPU protection, the Region number 0 does not allow writes from
+ * core to affect the start and end address nor the permissions associated with
+ * the debugger. It can only write the permission fields associated
+ * with the other masters.
+ *
+ * @param base          MPU peripheral base address.
+ * @param regionConfig  The pointer to the MPU user configuration structure. See "mpu_region_config_t".
+ */
+void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig);
+
+/*!
+ * @brief Sets the region start and end address.
+ *
+ * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by MPU.
+ * The actual start address by MPU is 0-modulo-32 byte address.
+ * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU.
+ * The actual end address used by MPU is 31-modulo-32 byte address.
+ * Note: Due to the MPU protection, the startAddr and endAddr can't be
+ * changed by the core when regionNum is 0.
+ *
+ * @param base          MPU peripheral base address.
+ * @param regionNum     MPU region number. The range is from 0 to
+ * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1.
+ * @param startAddr     Region start address.
+ * @param endAddr       Region end address.
+ */
+void MPU_SetRegionAddr(MPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr);
+
+/*!
+ * @brief Sets the MPU region access rights for masters with read, write and execute rights.
+ * The MPU access rights depend on two board classifications of bus masters.
+ * The privilege rights masters and the normal rights masters.
+ * The privilege rights masters have the read, write and execute access rights.
+ * So except the normal read and write rights, the execute rights is also
+ * allowed for these masters. The privilege rights masters are normally range from
+ * bus masters 0 - 3. However, the maximum master number is device-specific.
+ * See the "FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX".
+ * The normal rights masters access rights control see
+ * "MPU_SetRegionRwMasterAccessRights()".
+ *
+ * @param base          MPU peripheral base address.
+ * @param regionNum     MPU region number. Should range from 0 to
+ * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1.
+ * @param masterNum     MPU bus master number. Should range from 0 to
+ * FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX.
+ * @param accessRights  The pointer to the MPU access rights configuration. See "mpu_rwxrights_master_access_control_t".
+ */
+void MPU_SetRegionRwxMasterAccessRights(MPU_Type *base,
+                                        uint32_t regionNum,
+                                        uint32_t masterNum,
+                                        const mpu_rwxrights_master_access_control_t *accessRights);
+
+/*!
+ * @brief Sets the MPU region access rights for masters with read and write rights.
+ * The MPU access rights depend on two board classifications of bus masters.
+ * The privilege rights masters and the normal rights masters.
+ * The normal rights masters only have the read and write access permissions.
+ * The privilege rights access control see "MPU_SetRegionRwxMasterAccessRights".
+ *
+ * @param base          MPU peripheral base address.
+ * @param regionNum     MPU region number. The range is from 0 to
+ * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1.
+ * @param masterNum     MPU bus master number. Should range from FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT
+ * to ~ FSL_FEATURE_MPU_MASTER_MAX_INDEX.
+ * @param accessRights  The pointer to the MPU access rights configuration. See "mpu_rwrights_master_access_control_t".
+ */
+void MPU_SetRegionRwMasterAccessRights(MPU_Type *base,
+                                       uint32_t regionNum,
+                                       uint32_t masterNum,
+                                       const mpu_rwrights_master_access_control_t *accessRights);
+
+/*!
+ * @brief Gets the numbers of slave ports where errors occur.
+ *
+ * @param base       MPU peripheral base address.
+ * @param slaveNum   MPU slave port number.
+ * @return The slave ports error status.
+ *         true  - error happens in this slave port.
+ *         false - error didn't happen in this slave port.
+ */
+bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum);
+
+/*!
+ * @brief Gets the MPU detailed error access information.
+ *
+ * @param base       MPU peripheral base address.
+ * @param slaveNum   MPU slave port number.
+ * @param errInform  The pointer to the MPU access error information. See "mpu_access_err_info_t".
+ */
+void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_MPU_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pit.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pit.c
new file mode 100644
index 00000000000..1f2fdfe8b45
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pit.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_pit.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address to be used to gate or ungate the module clock
+ *
+ * @param base PIT peripheral base address
+ *
+ * @return The PIT instance
+ */
+static uint32_t PIT_GetInstance(PIT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to PIT bases for each instance. */
+static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS;
+
+/*! @brief Pointers to PIT clocks for each instance. */
+static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t PIT_GetInstance(PIT_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_PIT_COUNT; instance++)
+    {
+        if (s_pitBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_PIT_COUNT);
+
+    return instance;
+}
+
+void PIT_Init(PIT_Type *base, const pit_config_t *config)
+{
+    assert(config);
+
+    /* Ungate the PIT clock*/
+    CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]);
+
+    /* Enable PIT timers */
+    base->MCR &= ~PIT_MCR_MDIS_MASK;
+
+    /* Config timer operation when in debug mode */
+    if (config->enableRunInDebug)
+    {
+        base->MCR &= ~PIT_MCR_FRZ_MASK;
+    }
+    else
+    {
+        base->MCR |= PIT_MCR_FRZ_MASK;
+    }
+}
+
+void PIT_Deinit(PIT_Type *base)
+{
+    /* Disable PIT timers */
+    base->MCR |= PIT_MCR_MDIS_MASK;
+
+    /* Gate the PIT clock*/
+    CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]);
+}
+
+#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
+
+uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base)
+{
+    uint32_t valueH = 0U;
+    uint32_t valueL = 0U;
+
+    /* LTMR64H should be read before LTMR64L */
+    valueH = base->LTMR64H;
+    valueL = base->LTMR64L;
+
+    return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
+}
+
+#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pit.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pit.h
new file mode 100644
index 00000000000..f94c14af4f7
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pit.h
@@ -0,0 +1,354 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_PIT_H_
+#define _FSL_PIT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup pit
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*!
+ * @brief List of PIT channels
+ * @note Actual number of available channels is SoC dependent
+ */
+typedef enum _pit_chnl
+{
+    kPIT_Chnl_0 = 0U, /*!< PIT channel number 0*/
+    kPIT_Chnl_1,      /*!< PIT channel number 1 */
+    kPIT_Chnl_2,      /*!< PIT channel number 2 */
+    kPIT_Chnl_3,      /*!< PIT channel number 3 */
+} pit_chnl_t;
+
+/*! @brief List of PIT interrupts */
+typedef enum _pit_interrupt_enable
+{
+    kPIT_TimerInterruptEnable = PIT_TCTRL_TIE_MASK, /*!< Timer interrupt enable*/
+} pit_interrupt_enable_t;
+
+/*! @brief List of PIT status flags */
+typedef enum _pit_status_flags
+{
+    kPIT_TimerFlag = PIT_TFLG_TIF_MASK, /*!< Timer flag */
+} pit_status_flags_t;
+
+/*!
+ * @brief PIT config structure
+ *
+ * This structure holds the configuration settings for the PIT peripheral. To initialize this
+ * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The config struct can be made const so it resides in flash
+ */
+typedef struct _pit_config
+{
+    bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */
+} pit_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the PIT clock, enables the PIT module and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application using the PIT driver.
+ *
+ * @param base   PIT peripheral base address
+ * @param config Pointer to user's PIT config structure
+ */
+void PIT_Init(PIT_Type *base, const pit_config_t *config);
+
+/*!
+ * @brief Gate the PIT clock and disable the PIT module
+ *
+ * @param base PIT peripheral base address
+ */
+void PIT_Deinit(PIT_Type *base);
+
+/*!
+ * @brief Fill in the PIT config struct with the default settings
+ *
+ * The default values are:
+ * @code
+ *     config->enableRunInDebug = false;
+ * @endcode
+ * @param config Pointer to user's PIT config structure.
+ */
+static inline void PIT_GetDefaultConfig(pit_config_t *config)
+{
+    assert(config);
+
+    /* Timers are stopped in Debug mode */
+    config->enableRunInDebug = false;
+}
+
+#if defined(FSL_FEATURE_PIT_HAS_CHAIN_MODE) && FSL_FEATURE_PIT_HAS_CHAIN_MODE
+
+/*!
+ * @brief Enables or disables chaining a timer with the previous timer.
+ *
+ * When a timer has a chain mode enabled, it only counts after the previous
+ * timer has expired. If the timer n-1 has counted down to 0, counter n
+ * decrements the value by one. Each timer is 32-bits, this allows the developers
+ * to chain timers together and form a longer timer (64-bits and larger). The first timer
+ * (timer 0) cannot be chained to any other timer.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number which is chained with the previous timer
+ * @param enable  Enable or disable chain.
+ *                true:  Current timer is chained with the previous timer.
+ *                false: Timer doesn't chain with other timers.
+ */
+static inline void PIT_SetTimerChainMode(PIT_Type *base, pit_chnl_t channel, bool enable)
+{
+    if (enable)
+    {
+        base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK;
+    }
+    else
+    {
+        base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK;
+    }
+}
+
+#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */
+
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected PIT interrupts.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The interrupts to enable. This is a logical OR of members of the
+ *                enumeration ::pit_interrupt_enable_t
+ */
+static inline void PIT_EnableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].TCTRL |= mask;
+}
+
+/*!
+ * @brief Disables the selected PIT interrupts.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The interrupts to disable. This is a logical OR of members of the
+ *                enumeration ::pit_interrupt_enable_t
+ */
+static inline void PIT_DisableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].TCTRL &= ~mask;
+}
+
+/*!
+ * @brief Gets the enabled PIT interrupts.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::pit_interrupt_enable_t
+ */
+static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t channel)
+{
+    return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK);
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the PIT status flags
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::pit_status_flags_t
+ */
+static inline uint32_t PIT_GetStatusFlags(PIT_Type *base, pit_chnl_t channel)
+{
+    return (base->CHANNEL[channel].TFLG & PIT_TFLG_TIF_MASK);
+}
+
+/*!
+ * @brief  Clears the PIT status flags.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The status flags to clear. This is a logical OR of members of the
+ *                enumeration ::pit_status_flags_t
+ */
+static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].TFLG = mask;
+}
+
+/*! @}*/
+
+/*!
+ * @name Read and Write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of count.
+ *
+ * Timers begin counting from the value set by this function until it reaches 0,
+ * then it generates an interrupt and load this register value again.
+ * Writing a new value to this register does not restart the timer. Instead, the value
+ * is loaded after the timer expires.
+ *
+ * @note User can call the utility macros provided in fsl_common.h to convert to ticks
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ * @param count   Timer period in units of ticks
+ */
+static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count)
+{
+    base->CHANNEL[channel].LDVAL = count;
+}
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return Current timer counting value in ticks
+ */
+static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base, pit_chnl_t channel)
+{
+    return base->CHANNEL[channel].CVAL;
+}
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the timer counting.
+ *
+ * After calling this function, timers load period value, count down to 0 and
+ * then load the respective start value again. Each time a timer reaches 0,
+ * it generates a trigger pulse and sets the timeout interrupt flag.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number.
+ */
+static inline void PIT_StartTimer(PIT_Type *base, pit_chnl_t channel)
+{
+    base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK;
+}
+
+/*!
+ * @brief Stops the timer counting.
+ *
+ * This function stops every timer counting. Timers reload their periods
+ * respectively after the next time they call the PIT_DRV_StartTimer.
+ *
+ * @param base    PIT peripheral base address
+ * @param channel Timer channel number.
+ */
+static inline void PIT_StopTimer(PIT_Type *base, pit_chnl_t channel)
+{
+    base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK;
+}
+
+/*! @}*/
+
+#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
+
+/*!
+ * @brief Reads the current lifetime counter value.
+ *
+ * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together.
+ * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer.
+ * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1".
+ * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit
+ * has the value of timer 0.
+ *
+ * @param base PIT peripheral base address
+ *
+ * @return Current lifetime timer value
+ */
+uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base);
+
+#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_PIT_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pmc.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pmc.c
new file mode 100644
index 00000000000..82d7b7ace13
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pmc.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_pmc.h"
+
+#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM)
+void PMC_GetParam(PMC_Type *base, pmc_param_t *param)
+{
+    uint32_t reg = base->PARAM;
+    ;
+    param->vlpoEnable = (bool)(reg & PMC_PARAM_VLPOE_MASK);
+    param->hvdEnable = (bool)(reg & PMC_PARAM_HVDE_MASK);
+}
+#endif /* FSL_FEATURE_PMC_HAS_PARAM */
+
+void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config)
+{
+    base->LVDSC1 = (0U |
+#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV)
+                    ((uint32_t)config->voltSelect << PMC_LVDSC1_LVDV_SHIFT) |
+#endif
+                    ((uint32_t)config->enableInt << PMC_LVDSC1_LVDIE_SHIFT) |
+                    ((uint32_t)config->enableReset << PMC_LVDSC1_LVDRE_SHIFT)
+                    /* Clear the Low Voltage Detect Flag with previouse power detect setting */
+                    | PMC_LVDSC1_LVDACK_MASK);
+}
+
+void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config)
+{
+    base->LVDSC2 = (0U |
+#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV)
+                    ((uint32_t)config->voltSelect << PMC_LVDSC2_LVWV_SHIFT) |
+#endif
+                    ((uint32_t)config->enableInt << PMC_LVDSC2_LVWIE_SHIFT)
+                    /* Clear the Low Voltage Warning Flag with previouse power detect setting */
+                    | PMC_LVDSC2_LVWACK_MASK);
+}
+
+#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
+void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config)
+{
+    base->HVDSC1 = (((uint32_t)config->voltSelect << PMC_HVDSC1_HVDV_SHIFT) |
+                    ((uint32_t)config->enableInt << PMC_HVDSC1_HVDIE_SHIFT) |
+                    ((uint32_t)config->enableReset << PMC_HVDSC1_HVDRE_SHIFT)
+                    /* Clear the High Voltage Detect Flag with previouse power detect setting */
+                    | PMC_HVDSC1_HVDACK_MASK);
+}
+#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */
+
+#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \
+     (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \
+     (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS))
+void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config)
+{
+    base->REGSC = (0U
+#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE)
+                   | ((uint32_t)config->enable << PMC_REGSC_BGBE_SHIFT)
+#endif /* FSL_FEATURE_PMC_HAS_BGBE */
+#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN)
+                   | (((uint32_t)config->enableInLowPowerMode << PMC_REGSC_BGEN_SHIFT))
+#endif /* FSL_FEATURE_PMC_HAS_BGEN */
+#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)
+                   | ((uint32_t)config->drive << PMC_REGSC_BGBDS_SHIFT)
+#endif /* FSL_FEATURE_PMC_HAS_BGBDS */
+                       );
+}
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pmc.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pmc.h
new file mode 100644
index 00000000000..f39a22fc6c2
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_pmc.h
@@ -0,0 +1,421 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_PMC_H_
+#define _FSL_PMC_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup pmc */
+/*! @{ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief PMC driver version */
+#define FSL_PMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+/*@}*/
+
+#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV)
+/*!
+ * @brief Low-Voltage Detect Voltage Select
+ */
+typedef enum _pmc_low_volt_detect_volt_select
+{
+    kPMC_LowVoltDetectLowTrip = 0U, /*!< Low trip point selected (VLVD = VLVDL )*/
+    kPMC_LowVoltDetectHighTrip = 1U /*!< High trip point selected (VLVD = VLVDH )*/
+} pmc_low_volt_detect_volt_select_t;
+#endif
+
+#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV)
+/*!
+ * @brief Low-Voltage Warning Voltage Select
+ */
+typedef enum _pmc_low_volt_warning_volt_select
+{
+    kPMC_LowVoltWarningLowTrip = 0U,  /*!< Low trip point selected (VLVW = VLVW1)*/
+    kPMC_LowVoltWarningMid1Trip = 1U, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/
+    kPMC_LowVoltWarningMid2Trip = 2U, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/
+    kPMC_LowVoltWarningHighTrip = 3U  /*!< High trip point selected (VLVW = VLVW4)*/
+} pmc_low_volt_warning_volt_select_t;
+#endif
+
+#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
+/*!
+ * @brief High-Voltage Detect Voltage Select
+ */
+typedef enum _pmc_high_volt_detect_volt_select
+{
+    kPMC_HighVoltDetectLowTrip = 0U, /*!< Low trip point selected (VHVD = VHVDL )*/
+    kPMC_HighVoltDetectHighTrip = 1U /*!< High trip point selected (VHVD = VHVDH )*/
+} pmc_high_volt_detect_volt_select_t;
+#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */
+
+#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)
+/*!
+ * @brief Bandgap Buffer Drive Select.
+ */
+typedef enum _pmc_bandgap_buffer_drive_select
+{
+    kPMC_BandgapBufferDriveLow = 0U, /*!< Low drive.  */
+    kPMC_BandgapBufferDriveHigh = 1U /*!< High drive. */
+} pmc_bandgap_buffer_drive_select_t;
+#endif /* FSL_FEATURE_PMC_HAS_BGBDS */
+
+#if (defined(FSL_FEATURE_PMC_HAS_VLPO) && FSL_FEATURE_PMC_HAS_VLPO)
+/*!
+ * @brief VLPx Option
+ */
+typedef enum _pmc_vlp_freq_option
+{
+    kPMC_FreqRestrict = 0U,  /*!< Frequency is restricted in VLPx mode. */
+    kPMC_FreqUnrestrict = 1U /*!< Frequency is unrestricted in VLPx mode. */
+} pmc_vlp_freq_mode_t;
+#endif /* FSL_FEATURE_PMC_HAS_VLPO */
+
+#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID)
+/*!
+ @brief IP version ID definition.
+ */
+typedef struct _pmc_version_id
+{
+    uint16_t feature; /*!< Feature Specification Number. */
+    uint8_t minor;    /*!< Minor version number.         */
+    uint8_t major;    /*!< Major version number.         */
+} pmc_version_id_t;
+#endif /* FSL_FEATURE_PMC_HAS_VERID */
+
+#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM)
+/*! @brief IP parameter definition. */
+typedef struct _pmc_param
+{
+    bool vlpoEnable; /*!< VLPO enable. */
+    bool hvdEnable;  /*!< HVD enable.  */
+} pmc_param_t;
+#endif /* FSL_FEATURE_PMC_HAS_PARAM */
+
+/*!
+ * @brief Low-Voltage Detect Configuration Structure
+ */
+typedef struct _pmc_low_volt_detect_config
+{
+    bool enableInt;   /*!< Enable interrupt when low-voltage detect*/
+    bool enableReset; /*!< Enable system reset when low-voltage detect*/
+#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV)
+    pmc_low_volt_detect_volt_select_t voltSelect; /*!< Low-voltage detect trip point voltage selection*/
+#endif
+} pmc_low_volt_detect_config_t;
+
+/*!
+ * @brief Low-Voltage Warning Configuration Structure
+ */
+typedef struct _pmc_low_volt_warning_config
+{
+    bool enableInt; /*!< Enable interrupt when low-voltage warning*/
+#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV)
+    pmc_low_volt_warning_volt_select_t voltSelect; /*!< Low-voltage warning trip point voltage selection*/
+#endif
+} pmc_low_volt_warning_config_t;
+
+#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
+/*!
+ * @brief High-Voltage Detect Configuration Structure
+ */
+typedef struct _pmc_high_volt_detect_config
+{
+    bool enableInt;                                /*!< Enable interrupt when high-voltage detect*/
+    bool enableReset;                              /*!< Enable system reset when high-voltage detect*/
+    pmc_high_volt_detect_volt_select_t voltSelect; /*!< High-voltage detect trip point voltage selection*/
+} pmc_high_volt_detect_config_t;
+#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */
+
+#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \
+     (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \
+     (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS))
+/*!
+ * @brief Bandgap Buffer configuration.
+ */
+typedef struct _pmc_bandgap_buffer_config
+{
+#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE)
+    bool enable; /*!< Enable bandgap buffer.                   */
+#endif
+#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN)
+    bool enableInLowPowerMode; /*!< Enable bandgap buffer in low-power mode. */
+#endif                         /* FSL_FEATURE_PMC_HAS_BGEN */
+#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)
+    pmc_bandgap_buffer_drive_select_t drive; /*!< Bandgap buffer drive select.             */
+#endif                                       /* FSL_FEATURE_PMC_HAS_BGBDS */
+} pmc_bandgap_buffer_config_t;
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name Power Management Controller Control APIs*/
+/*@{*/
+
+#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID)
+/*!
+ * @brief Gets the PMC version ID.
+ *
+ * This function gets the PMC version ID, including major version number,
+ * minor version number and feature specification number.
+ *
+ * @param base PMC peripheral base address.
+ * @param versionId     Pointer to version ID structure.
+ */
+static inline void PMC_GetVersionId(PMC_Type *base, pmc_version_id_t *versionId)
+{
+    *((uint32_t *)versionId) = base->VERID;
+}
+#endif /* FSL_FEATURE_PMC_HAS_VERID */
+
+#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM)
+/*!
+ * @brief Gets the PMC parameter.
+ *
+ * This function gets the PMC parameter, including VLPO enable and HVD enable.
+ *
+ * @param base PMC peripheral base address.
+ * @param param         Pointer to PMC param structure.
+ */
+void PMC_GetParam(PMC_Type *base, pmc_param_t *param);
+#endif
+
+/*!
+ * @brief Configure the low-voltage detect setting.
+ *
+ * This function configures the low-voltage detect setting, including the trip
+ * point voltage setting, enable interrupt or not, enable system reset or not.
+ *
+ * @param base PMC peripheral base address.
+ * @param config  Low-Voltage detect configuration structure.
+ */
+void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config);
+
+/*!
+ * @brief Get Low-Voltage Detect Flag status
+ *
+ * This function  reads the current LVDF status. If it returns 1, a low-voltage event is detected.
+ *
+ * @param base PMC peripheral base address.
+ * @return Current low-voltage detect flag
+ *                - true: Low-voltage detected
+ *                - false: Low-voltage not detected
+ */
+static inline bool PMC_GetLowVoltDetectFlag(PMC_Type *base)
+{
+    return (bool)(base->LVDSC1 & PMC_LVDSC1_LVDF_MASK);
+}
+
+/*!
+ * @brief Acknowledge to clear the Low-voltage Detect flag
+ *
+ * This function acknowledges the low-voltage detection errors (write 1 to
+ * clear LVDF).
+ *
+ * @param base PMC peripheral base address.
+ */
+static inline void PMC_ClearLowVoltDetectFlag(PMC_Type *base)
+{
+    base->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK;
+}
+
+/*!
+ * @brief Configure the low-voltage warning setting.
+ *
+ * This function configures the low-voltage warning setting, including the trip
+ * point voltage setting and enable interrupt or not.
+ *
+ * @param base PMC peripheral base address.
+ * @param config  Low-Voltage warning configuration structure.
+ */
+void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config);
+
+/*!
+ * @brief Get Low-Voltage Warning Flag status
+ *
+ * This function polls the current LVWF status. When 1 is returned, it
+ * indicates a low-voltage warning event. LVWF is set when V Supply transitions
+ * below the trip point or after reset and V Supply is already below the V LVW.
+ *
+ * @param base PMC peripheral base address.
+ * @return Current LVWF status
+ *                  - true: Low-Voltage Warning Flag is set.
+ *                  - false: the  Low-Voltage Warning does not happen.
+ */
+static inline bool PMC_GetLowVoltWarningFlag(PMC_Type *base)
+{
+    return (bool)(base->LVDSC2 & PMC_LVDSC2_LVWF_MASK);
+}
+
+/*!
+ * @brief Acknowledge to Low-Voltage Warning flag
+ *
+ * This function acknowledges the low voltage warning errors (write 1 to
+ * clear LVWF).
+ *
+ * @param base PMC peripheral base address.
+ */
+static inline void PMC_ClearLowVoltWarningFlag(PMC_Type *base)
+{
+    base->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK;
+}
+
+#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
+/*!
+ * @brief Configure the high-voltage detect setting.
+ *
+ * This function configures the high-voltage detect setting, including the trip
+ * point voltage setting, enable interrupt or not, enable system reset or not.
+ *
+ * @param base PMC peripheral base address.
+ * @param config  High-voltage detect configuration structure.
+ */
+void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config);
+
+/*!
+ * @brief Get High-Voltage Detect Flag status
+ *
+ * This function  reads the current HVDF status. If it returns 1, a low
+ * voltage event is detected.
+ *
+ * @param base PMC peripheral base address.
+ * @return Current high-voltage detect flag
+ *                - true: High-Voltage detected
+ *                - false: High-Voltage not detected
+ */
+static inline bool PMC_GetHighVoltDetectFlag(PMC_Type *base)
+{
+    return (bool)(base->HVDSC1 & PMC_HVDSC1_HVDF_MASK);
+}
+
+/*!
+ * @brief Acknowledge to clear the High-Voltage Detect flag
+ *
+ * This function acknowledges the high-voltage detection errors (write 1 to
+ * clear HVDF).
+ *
+ * @param base PMC peripheral base address.
+ */
+static inline void PMC_ClearHighVoltDetectFlag(PMC_Type *base)
+{
+    base->HVDSC1 |= PMC_HVDSC1_HVDACK_MASK;
+}
+#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */
+
+#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \
+     (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \
+     (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS))
+/*!
+ * @brief Configure the PMC bandgap
+ *
+ * This function configures the PMC bandgap, including the drive select and
+ * behavior in low-power mode.
+ *
+ * @param base PMC peripheral base address.
+ * @param config Pointer to the configuration structure
+ */
+void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config);
+#endif
+
+#if (defined(FSL_FEATURE_PMC_HAS_ACKISO) && FSL_FEATURE_PMC_HAS_ACKISO)
+/*!
+ * @brief Gets the acknowledge Peripherals and I/O pads isolation flag.
+ *
+ * This function  reads the Acknowledge Isolation setting that indicates
+ * whether certain peripherals and the I/O pads are in a latched state as
+ * a result of having been in the VLLS mode.
+ *
+ * @param base PMC peripheral base address.
+ * @param base  Base address for current PMC instance.
+ * @return ACK isolation
+ *               0 - Peripherals and I/O pads are in a normal run state.
+ *               1 - Certain peripherals and I/O pads are in an isolated and
+ *                   latched state.
+ */
+static inline bool PMC_GetPeriphIOIsolationFlag(PMC_Type *base)
+{
+    return (bool)(base->REGSC & PMC_REGSC_ACKISO_MASK);
+}
+
+/*!
+ * @brief Acknowledge to Peripherals and I/O pads isolation flag.
+ *
+ * This function  clears the ACK Isolation flag. Writing one to this setting
+ * when it is set releases the I/O pads and certain peripherals to their normal
+ * run mode state.
+ *
+ * @param base PMC peripheral base address.
+ */
+static inline void PMC_ClearPeriphIOIsolationFlag(PMC_Type *base)
+{
+    base->REGSC |= PMC_REGSC_ACKISO_MASK;
+}
+#endif /* FSL_FEATURE_PMC_HAS_ACKISO */
+
+#if (defined(FSL_FEATURE_PMC_HAS_REGONS) && FSL_FEATURE_PMC_HAS_REGONS)
+/*!
+ * @brief Gets the Regulator regulation status.
+ *
+ * This function  returns the regulator to a run regulation status. It provides
+ * the current status of the internal voltage regulator.
+ *
+ * @param base PMC peripheral base address.
+ * @param base  Base address for current PMC instance.
+ * @return Regulation status
+ *               0 - Regulator is in a stop regulation or in transition to/from the regulation.
+ *               1 - Regulator is in a run regulation.
+ *
+ */
+static inline bool PMC_IsRegulatorInRunRegulation(PMC_Type *base)
+{
+    return (bool)(base->REGSC & PMC_REGSC_REGONS_MASK);
+}
+#endif /* FSL_FEATURE_PMC_HAS_REGONS */
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* _FSL_PMC_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_port.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_port.h
new file mode 100644
index 00000000000..935b032b223
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_port.h
@@ -0,0 +1,381 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_PORT_H_
+#define _FSL_PORT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup port
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! Version 2.0.1. */
+#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*! @brief Internal resistor pull feature selection */
+enum _port_pull
+{
+    kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
+    kPORT_PullDown = 2U,    /*!< Internal pull-down resistor is enabled. */
+    kPORT_PullUp = 3U,      /*!< Internal pull-up resistor is enabled. */
+};
+
+/*! @brief Slew rate selection */
+enum _port_slew_rate
+{
+    kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
+    kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
+};
+
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+/*! @brief Internal resistor pull feature enable/disable */
+enum _port_open_drain_enable
+{
+    kPORT_OpenDrainDisable = 0U, /*!< Internal pull-down resistor is disabled. */
+    kPORT_OpenDrainEnable = 1U,  /*!< Internal pull-up resistor is enabled. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+
+/*! @brief Passive filter feature enable/disable */
+enum _port_passive_filter_enable
+{
+    kPORT_PassiveFilterDisable = 0U, /*!< Fast slew rate is configured. */
+    kPORT_PassiveFilterEnable = 1U,  /*!< Slow slew rate is configured. */
+};
+
+/*! @brief Configures the drive strength. */
+enum _port_drive_strength
+{
+    kPORT_LowDriveStrength = 0U,  /*!< Low-drive strength is configured. */
+    kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
+};
+
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+/*! @brief Unlock/lock the pin control register field[15:0] */
+enum _port_lock_register
+{
+    kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
+    kPORT_LockRegister = 1U,   /*!< Pin Control Register fields [15:0] are locked. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
+
+/*! @brief Pin mux selection */
+typedef enum _port_mux
+{
+    kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
+    kPORT_MuxAsGpio = 1U,           /*!< Corresponding pin is configured as GPIO. */
+    kPORT_MuxAlt2 = 2U,             /*!< Chip-specific */
+    kPORT_MuxAlt3 = 3U,             /*!< Chip-specific */
+    kPORT_MuxAlt4 = 4U,             /*!< Chip-specific */
+    kPORT_MuxAlt5 = 5U,             /*!< Chip-specific */
+    kPORT_MuxAlt6 = 6U,             /*!< Chip-specific */
+    kPORT_MuxAlt7 = 7U,             /*!< Chip-specific */
+} port_mux_t;
+
+/*! @brief Configures the interrupt generation condition. */
+typedef enum _port_interrupt
+{
+    kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
+#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
+    kPORT_DMARisingEdge = 0x1U,  /*!< DMA request on rising edge. */
+    kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
+    kPORT_DMAEitherEdge = 0x3U,  /*!< DMA request on either edge. */
+#endif
+#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG
+    kPORT_FlagRisingEdge = 0x05U,  /*!< Flag sets on rising edge. */
+    kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
+    kPORT_FlagEitherEdge = 0x07U,  /*!< Flag sets on either edge. */
+#endif
+    kPORT_InterruptLogicZero = 0x8U,   /*!< Interrupt when logic zero. */
+    kPORT_InterruptRisingEdge = 0x9U,  /*!< Interrupt on rising edge. */
+    kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
+    kPORT_InterruptEitherEdge = 0xBU,  /*!< Interrupt on either edge. */
+    kPORT_InterruptLogicOne = 0xCU,    /*!< Interrupt when logic one. */
+#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
+    kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
+    kPORT_ActiveLowTriggerOutputEnable = 0xEU,  /*!< Enable active low-trigger output. */
+#endif
+} port_interrupt_t;
+
+#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+/*! @brief Digital filter clock source selection */
+typedef enum _port_digital_filter_clock_source
+{
+    kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
+    kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
+} port_digital_filter_clock_source_t;
+
+/*! @brief PORT digital filter feature configuration definition */
+typedef struct _port_digital_filter_config
+{
+    uint32_t digitalFilterWidth;                    /*!< Set digital filter width */
+    port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
+} port_digital_filter_config_t;
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
+
+/*! @brief PORT pin configuration structure */
+typedef struct _port_pin_config
+{
+    uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
+    uint16_t slewRate : 1;   /*!< Fast/slow slew rate Configure */
+    uint16_t : 1;
+    uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+    uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
+#else
+    uint16_t : 1;
+#endif                          /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+    uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
+    uint16_t : 1;
+    uint16_t mux : 3; /*!< Pin mux Configure */
+    uint16_t : 4;
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+    uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
+} port_pin_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the port PCR register.
+ *
+ * This is an example to define an input pin or output pin PCR configuration:
+ * @code
+ * // Define a digital input pin PCR configuration
+ * port_pin_config_t config = {
+ *      kPORT_PullUp,
+ *      kPORT_FastSlewRate,
+ *      kPORT_PassiveFilterDisable,
+ *      kPORT_OpenDrainDisable,
+ *      kPORT_LowDriveStrength,
+ *      kPORT_MuxAsGpio,
+ *      kPORT_UnLockRegister,
+ * };
+ * @endcode
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param pin    PORT pin number.
+ * @param config PORT PCR register configuration structure.
+ */
+static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
+{
+    assert(config);
+    uint32_t addr = (uint32_t)&base->PCR[pin];
+    *(volatile uint16_t *)(addr) = *((const uint16_t *)config);
+}
+
+/*!
+ * @brief Sets the port PCR register for multiple pins.
+ *
+ * This is an example to define input pins or output pins PCR configuration:
+ * @code
+ * // Define a digital input pin PCR configuration
+ * port_pin_config_t config = {
+ *      kPORT_PullUp ,
+ *      kPORT_PullEnable,
+ *      kPORT_FastSlewRate,
+ *      kPORT_PassiveFilterDisable,
+ *      kPORT_OpenDrainDisable,
+ *      kPORT_LowDriveStrength,
+ *      kPORT_MuxAsGpio,
+ *      kPORT_UnlockRegister,
+ * };
+ * @endcode
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param mask   PORT pin number macro.
+ * @param config PORT PCR register configuration structure.
+ */
+static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
+{
+    assert(config);
+
+    uint16_t pcrl = *((const uint16_t *)config);
+
+    if (mask & 0xffffU)
+    {
+        base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
+    }
+    if (mask >> 16)
+    {
+        base->GPCHR = (mask & 0xffff0000U) | pcrl;
+    }
+}
+
+/*!
+ * @brief Configures the pin muxing.
+ *
+ * @param base  PORT peripheral base pointer.
+ * @param pin   PORT pin number.
+ * @param mux   pin muxing slot selection.
+ *        - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
+ *        - #kPORT_MuxAsGpio          : Set as GPIO.
+ *        - #kPORT_MuxAlt2            : chip-specific.
+ *        - #kPORT_MuxAlt3            : chip-specific.
+ *        - #kPORT_MuxAlt4            : chip-specific.
+ *        - #kPORT_MuxAlt5            : chip-specific.
+ *        - #kPORT_MuxAlt6            : chip-specific.
+ *        - #kPORT_MuxAlt7            : chip-specific.
+ * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
+ *         the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
+ *         reset to zero : kPORT_PinDisabledOrAnalog).
+ *        This function is recommended to use to reset the pin mux
+ *
+ */
+static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
+}
+
+#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+
+/*!
+ * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
+ *
+ * @param base  PORT peripheral base pointer.
+ * @param mask  PORT pin number macro.
+ */
+static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
+{
+    if (enable == true)
+    {
+        base->DFER |= mask;
+    }
+    else
+    {
+        base->DFER &= ~mask;
+    }
+}
+
+/*!
+ * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param config PORT digital filter configuration structure.
+ */
+static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
+{
+    assert(config);
+
+    base->DFCR = PORT_DFCR_CS(config->clockSource);
+    base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
+}
+
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
+
+/*@}*/
+
+/*! @name Interrupt */
+/*@{*/
+
+/*!
+ * @brief Configures the port pin interrupt/DMA request.
+ *
+ * @param base    PORT peripheral base pointer.
+ * @param pin     PORT pin number.
+ * @param config  PORT pin interrupt configuration.
+ *        - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
+ *        - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
+ *        - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
+ *        - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
+ *        - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
+ *        - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
+ *        - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
+ *        - #kPORT_InterruptLogicZero  : Interrupt when logic zero.
+ *        - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
+ *        - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
+ *        - #kPORT_InterruptEitherEdge : Interrupt on either edge.
+ *        - #kPORT_InterruptLogicOne   : Interrupt when logic one.
+ *        - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
+ *        - #kPORT_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit).
+ */
+static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
+}
+
+/*!
+ * @brief Reads the whole port status flag.
+ *
+ * If a pin is configured to generate the DMA request,  the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base PORT peripheral base pointer.
+ * @return Current port interrupt status flags, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
+{
+    return base->ISFR;
+}
+
+/*!
+ * @brief Clears the multiple pin interrupt status flag.
+ *
+ * @param base PORT peripheral base pointer.
+ * @param mask PORT pin number macro.
+ */
+static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
+{
+    base->ISFR = mask;
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_PORT_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c
new file mode 100644
index 00000000000..00f511cd73c
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c
@@ -0,0 +1,345 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_qspi.h"
+
+/*******************************************************************************
+ * Definitations
+ ******************************************************************************/
+enum _qspi_transfer_state
+{
+    kQSPI_TxBusy = 0x0U, /*!< QSPI is busy */
+    kQSPI_TxIdle,        /*!< Transfer is done. */
+    kQSPI_TxError        /*!< Transfer error occured. */
+};
+
+#define QSPI_AHB_BUFFER_REG(base, index) (*((uint32_t *)&(base->BUF0CR) + index))
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+* @brief Get the instance number for QSPI.
+*
+* @param base QSPI base pointer.
+*/
+uint32_t QSPI_GetInstance(QuadSPI_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Base pointer array */
+static QuadSPI_Type *const s_qspiBases[] = QuadSPI_BASE_PTRS;
+/* Clock name array */
+static const clock_ip_name_t s_qspiClock[] = QSPI_CLOCKS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+uint32_t QSPI_GetInstance(QuadSPI_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_QuadSPI_COUNT; instance++)
+    {
+        if (s_qspiBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_QuadSPI_COUNT);
+
+    return instance;
+}
+
+void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz)
+{
+    uint32_t i = 0;
+    uint32_t val = 0;
+
+    /* Enable QSPI clock */
+    CLOCK_EnableClock(s_qspiClock[QSPI_GetInstance(base)]);
+
+    /* Do software reset to QSPI module */
+    QSPI_SoftwareReset(base);
+
+    /* Clear the FIFO region */
+    QSPI_ClearFifo(base, kQSPI_AllFifo);
+
+    /* Configure QSPI */
+    QSPI_Enable(base, false);
+
+    /* Set qspi clock source */
+    base->SOCCR = config->clockSource;
+
+    /* Set the divider of QSPI clock */
+    base->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK;
+    base->MCR |= QuadSPI_MCR_SCLKCFG(srcClock_Hz / config->baudRate - 1U);
+
+    /* Set AHB buffer size and buffer master */
+    for (i = 0; i < FSL_FEATURE_QSPI_AHB_BUFFER_COUNT; i++)
+    {
+        val = QuadSPI_BUF0CR_MSTRID(config->AHBbufferMaster[i]) | QuadSPI_BUF0CR_ADATSZ(config->AHBbufferSize[i] / 8U);
+        QSPI_AHB_BUFFER_REG(base, i) = val;
+    }
+    if (config->enableAHBbuffer3AllMaster)
+    {
+        base->BUF3CR |= QuadSPI_BUF3CR_ALLMST_MASK;
+    }
+    else
+    {
+        base->BUF3CR &= ~QuadSPI_BUF3CR_ALLMST_MASK;
+    }
+
+    /* Set watermark */
+    base->RBCT &= ~QuadSPI_RBCT_WMRK_MASK;
+    base->RBCT |= QuadSPI_RBCT_WMRK(config->rxWatermark - 1);
+    base->TBCT &= ~QuadSPI_TBCT_WMRK_MASK;
+    base->TBCT |= QuadSPI_TBCT_WMRK(config->txWatermark - 1);
+
+    /* Enable QSPI module */
+    if (config->enableQspi)
+    {
+        QSPI_Enable(base, true);
+    }
+}
+
+void QSPI_GetDefaultQspiConfig(qspi_config_t *config)
+{
+    config->clockSource = 2U;
+    config->baudRate = 24000000U;
+    config->AHBbufferMaster[0] = 0xE;
+    config->AHBbufferMaster[1] = 0xE;
+    config->AHBbufferMaster[2] = 0xE;
+    config->enableAHBbuffer3AllMaster = true;
+    config->txWatermark = 8;
+    config->rxWatermark = 8;
+    config->enableQspi = true;
+}
+
+void QSPI_Deinit(QuadSPI_Type *base)
+{
+    QSPI_Enable(base, false);
+    CLOCK_DisableClock(s_qspiClock[QSPI_GetInstance(base)]);
+}
+
+void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config)
+{
+    uint32_t address = FSL_FEATURE_QSPI_AMBA_BASE + config->flashA1Size;
+    uint32_t val = 0;
+    uint32_t i = 0;
+
+    /* Disable module */
+    QSPI_Enable(base, false);
+
+    /* Config the serial flash size */
+    base->SFA1AD = address;
+    address += config->flashA2Size;
+    base->SFA2AD = address;
+    address += config->flashB1Size;
+    base->SFB1AD = address;
+    address += config->flashB2Size;
+    base->SFB2AD = address;
+
+    /* Set Word Addressable feature */
+    val = QuadSPI_SFACR_WA(config->enableWordAddress) | QuadSPI_SFACR_CAS(config->cloumnspace);
+    base->SFACR = val;
+
+    /* Config look up table */
+    base->LUTKEY = 0x5AF05AF0U;
+    base->LCKCR = 0x2U;
+    for (i = 0; i < FSL_FEATURE_QSPI_LUT_DEPTH; i++)
+    {
+        base->LUT[i] = config->lookuptable[i];
+    }
+    base->LUTKEY = 0x5AF05AF0U;
+    base->LCKCR = 0x1U;
+
+    /* Config flash timing */
+    val = QuadSPI_FLSHCR_TCSS(config->CSHoldTime) | QuadSPI_FLSHCR_TDH(config->dataHoldTime) |
+          QuadSPI_FLSHCR_TCSH(config->CSSetupTime);
+    base->FLSHCR = val;
+
+    /* Set flash endianness */
+    base->MCR &= ~QuadSPI_MCR_END_CFG_MASK;
+    base->MCR |= QuadSPI_MCR_END_CFG(config->endian);
+
+    /* Enable QSPI again */
+    QSPI_Enable(base, true);
+}
+
+void QSPI_SoftwareReset(QuadSPI_Type *base)
+{
+    volatile uint32_t i = 0;
+
+    /* Reset AHB domain and buffer domian */
+    base->MCR |= (QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK);
+
+    /* Wait several time for the reset to finish, this method came from IC team */
+    for (i = 0; i < 100; i++)
+    {
+        __ASM("nop");
+    }
+
+    /* Disable QSPI module */
+    QSPI_Enable(base, false);
+
+    /* Clear the reset flags */
+    base->MCR &= ~(QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK);
+
+    /* Enable QSPI module */
+    QSPI_Enable(base, true);
+}
+
+uint32_t QSPI_GetRxDataRegisterAddress(QuadSPI_Type *base)
+{
+    /* From RDBR */
+    if (base->RBCT & QuadSPI_RBCT_RXBRD_MASK)
+    {
+        return (uint32_t)(&(base->RBDR[0]));
+    }
+    else
+    {
+        /* From ARDB */
+        return FSL_FEATURE_QSPI_ARDB_BASE;
+    }
+}
+
+void QSPI_ExecuteIPCommand(QuadSPI_Type *base, uint32_t index)
+{
+    while (QSPI_GetStatusFlags(base) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+    QSPI_ClearCommandSequence(base, kQSPI_IPSeq);
+
+    /* Write the seqid bit */
+    base->IPCR = ((base->IPCR & (~QuadSPI_IPCR_SEQID_MASK)) | QuadSPI_IPCR_SEQID(index / 4U));
+}
+
+void QSPI_ExecuteAHBCommand(QuadSPI_Type *base, uint32_t index)
+{
+    while (QSPI_GetStatusFlags(base) & (kQSPI_Busy | kQSPI_AHBAccess))
+    {
+    }
+    QSPI_ClearCommandSequence(base, kQSPI_BufferSeq);
+    base->BFGENCR = ((base->BFGENCR & (~QuadSPI_BFGENCR_SEQID_MASK)) | QuadSPI_BFGENCR_SEQID(index / 4U));
+}
+
+void QSPI_UpdateLUT(QuadSPI_Type *base, uint32_t index, uint32_t *cmd)
+{
+    uint8_t i = 0;
+
+    /* Unlock the LUT */
+    base->LUTKEY = 0x5AF05AF0U;
+    base->LCKCR = 0x2U;
+
+    /* Write data into LUT */
+    for (i = 0; i < 4; i++)
+    {
+        base->LUT[index + i] = *cmd;
+        cmd++;
+    }
+
+    /* Lcok LUT again */
+    base->LUTKEY = 0x5AF05AF0U;
+    base->LCKCR = 0x1U;
+}
+
+void QSPI_SetReadDataArea(QuadSPI_Type *base, qspi_read_area_t area)
+{
+    base->RBCT &= ~QuadSPI_RBCT_RXBRD_MASK;
+    base->RBCT |= QuadSPI_RBCT_RXBRD(area);
+}
+
+uint32_t QSPI_ReadData(QuadSPI_Type *base)
+{
+    if (base->RBCT & QuadSPI_RBCT_RXBRD_MASK)
+    {
+        return base->RBDR[0];
+    }
+    else
+    {
+        /* Data from ARDB. */
+        return *((uint32_t *)FSL_FEATURE_QSPI_ARDB_BASE);
+    }
+}
+
+void QSPI_WriteBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size)
+{
+    assert(size >= 16U);
+
+    uint32_t i = 0;
+
+    for (i = 0; i < size / 4U; i++)
+    {
+        /* Check if the buffer is full */
+        while (QSPI_GetStatusFlags(base) & kQSPI_TxBufferFull)
+        {
+        }
+        QSPI_WriteData(base, *buffer);
+        buffer++;
+    }
+}
+
+void QSPI_ReadBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size)
+{
+    uint32_t i = 0;
+    uint32_t j = 0;
+    uint32_t level = 0;
+
+    while (i < size / 4)
+    {
+        /* Check if there is data */
+        do
+        {
+            level = (base->RBSR & QuadSPI_RBSR_RDBFL_MASK) >> QuadSPI_RBSR_RDBFL_SHIFT;
+        } while (!level);
+
+        /* Data from RBDR */
+        if (base->RBCT & QuadSPI_RBCT_RXBRD_MASK)
+        {
+            for (j = 0; j < level; j++)
+            {
+                buffer[i + j] = base->RBDR[j];
+            }
+        }
+        else
+        {
+            /* Data from ARDB. */
+            for (j = 0; j < level; j++)
+            {
+                buffer[i + j] = ((uint32_t *)FSL_FEATURE_QSPI_ARDB_BASE)[j];
+            }
+        }
+        i += level;
+    }
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi.h
new file mode 100644
index 00000000000..aff961228d9
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi.h
@@ -0,0 +1,629 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_QSPI_H_
+#define _FSL_QSPI_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup qspi
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2C driver version 2.0.1. */
+#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*! @brief Status structure of QSPI.*/
+enum _status_t
+{
+    kStatus_QSPI_Idle = MAKE_STATUS(kStatusGroup_QSPI, 0),  /*!< QSPI is in idle state  */
+    kStatus_QSPI_Busy = MAKE_STATUS(kStatusGroup_QSPI, 1),  /*!< QSPI is busy */
+    kStatus_QSPI_Error = MAKE_STATUS(kStatusGroup_QSPI, 2), /*!< Error occurred during QSPI transfer */
+};
+
+/*! @brief QSPI read data area, from IP FIFO or AHB buffer.*/
+typedef enum _qspi_read_area
+{
+    kQSPI_ReadAHB = 0x0U, /*!< QSPI read from AHB buffer. */
+    kQSPI_ReadIP          /*!< QSPI read from IP FIFO. */
+} qspi_read_area_t;
+
+/*! @brief QSPI command sequence type */
+typedef enum _qspi_command_seq
+{
+    kQSPI_IPSeq = QuadSPI_SPTRCLR_IPPTRC_MASK,                               /*!< IP command sequence */
+    kQSPI_BufferSeq = QuadSPI_SPTRCLR_BFPTRC_MASK,                           /*!< Buffer command sequence */
+    kQSPI_AllSeq = QuadSPI_SPTRCLR_IPPTRC_MASK | QuadSPI_SPTRCLR_BFPTRC_MASK /* All command sequence */
+} qspi_command_seq_t;
+
+/*! @brief QSPI buffer type */
+typedef enum _qspi_fifo
+{
+    kQSPI_TxFifo = QuadSPI_MCR_CLR_TXF_MASK,                            /*!< QSPI Tx FIFO */
+    kQSPI_RxFifo = QuadSPI_MCR_CLR_RXF_MASK,                            /*!< QSPI Rx FIFO */
+    kQSPI_AllFifo = QuadSPI_MCR_CLR_TXF_MASK | QuadSPI_MCR_CLR_RXF_MASK /*!< QSPI all FIFO, including Tx and Rx */
+} qspi_fifo_t;
+
+/*! @brief QSPI transfer endianess*/
+typedef enum _qspi_endianness
+{
+    kQSPI_64BigEndian = 0x0U, /*!< 64 bits big endian */
+    kQSPI_32LittleEndian,     /*!< 32 bit little endian */
+    kQSPI_32BigEndian,        /*!< 32 bit big endian */
+    kQSPI_64LittleEndian      /*!< 64 bit little endian */
+} qspi_endianness_t;
+
+/*! @brief QSPI error flags */
+enum _qspi_error_flags
+{
+    kQSPI_DataLearningFail = QuadSPI_FR_DLPFF_MASK,                /*!< Data learning pattern failure flag */
+    kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK,                     /*!< Tx buffer fill flag */
+    kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK,                 /*!< Tx buffer underrun flag */
+    kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK,             /*!< Illegal instruction error flag */
+    kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK,                 /*!< Rx buffer overflow flag */
+    kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK,                    /*!< Rx buffer drain flag */
+    kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK,                /*!< AHB sequence error flag */
+    kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK,           /*!< AHB illegal transaction error flag */
+    kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK,            /*!< AHB illegal burst error flag */
+    kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK,                /*!< AHB buffer overflow flag */
+    kQSPI_IPCommandUsageError = QuadSPI_FR_IUEF_MASK,              /*!< IP command usage error flag */
+    kQSPI_IPCommandTriggerDuringAHBAccess = QuadSPI_FR_IPAEF_MASK, /*!< IP command trigger during AHB access error */
+    kQSPI_IPCommandTriggerDuringIPAccess = QuadSPI_FR_IPIEF_MASK,  /*!< IP command trigger cannot be executed */
+    kQSPI_IPCommandTriggerDuringAHBGrant = QuadSPI_FR_IPGEF_MASK,  /*!< IP command trigger during AHB grant error */
+    kQSPI_IPCommandTransactionFinished = QuadSPI_FR_TFF_MASK,      /*!< IP command transaction finished flag */
+    kQSPI_FlagAll = 0x8C83F8D1U                                    /*!< All error flag */
+};
+
+/*! @brief QSPI state bit */
+enum _qspi_flags
+{
+    kQSPI_DataLearningSamplePoint = QuadSPI_SR_DLPSMP_MASK,   /*!< Data learning sample point */
+    kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK,              /*!< Tx buffer full flag */
+    kQSPI_TxDMA = QuadSPI_SR_TXDMA_MASK,                      /*!< Tx DMA is requested or running */
+    kQSPI_TxWatermark = QuadSPI_SR_TXWA_MASK,                 /*!< Tx buffer watermark available */
+    kQSPI_TxBufferEnoughData = QuadSPI_SR_TXEDA_MASK,         /*!< Tx buffer enough data available */
+    kQSPI_RxDMA = QuadSPI_SR_RXDMA_MASK,                      /*!< Rx DMA is requesting or running */
+    kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK,              /*!< Rx buffer full */
+    kQSPI_RxWatermark = QuadSPI_SR_RXWE_MASK,                 /*!< Rx buffer watermark exceeded */
+    kQSPI_AHB3BufferFull = QuadSPI_SR_AHB3FUL_MASK,           /*!< AHB buffer 3 full*/
+    kQSPI_AHB2BufferFull = QuadSPI_SR_AHB2FUL_MASK,           /*!< AHB buffer 2 full */
+    kQSPI_AHB1BufferFull = QuadSPI_SR_AHB1FUL_MASK,           /*!< AHB buffer 1 full */
+    kQSPI_AHB0BufferFull = QuadSPI_SR_AHB0FUL_MASK,           /*!< AHB buffer 0 full */
+    kQSPI_AHB3BufferNotEmpty = QuadSPI_SR_AHB3NE_MASK,        /*!< AHB buffer 3 not empty */
+    kQSPI_AHB2BufferNotEmpty = QuadSPI_SR_AHB2NE_MASK,        /*!< AHB buffer 2 not empty */
+    kQSPI_AHB1BufferNotEmpty = QuadSPI_SR_AHB1NE_MASK,        /*!< AHB buffer 1 not empty */
+    kQSPI_AHB0BufferNotEmpty = QuadSPI_SR_AHB0NE_MASK,        /*!< AHB buffer 0 not empty */
+    kQSPI_AHBTransactionPending = QuadSPI_SR_AHBTRN_MASK,     /*!< AHB access transaction pending */
+    kQSPI_AHBCommandPriorityGranted = QuadSPI_SR_AHBGNT_MASK, /*!< AHB command priority granted */
+    kQSPI_AHBAccess = QuadSPI_SR_AHB_ACC_MASK,                /*!< AHB access */
+    kQSPI_IPAccess = QuadSPI_SR_IP_ACC_MASK,                  /*!< IP access */
+    kQSPI_Busy = QuadSPI_SR_BUSY_MASK,                        /*!< Module busy */
+    kQSPI_StateAll = 0xEF897FE7U                              /*!< All flags */
+};
+
+/*! @brief QSPI interrupt enable */
+enum _qspi_interrupt_enable
+{
+    kQSPI_DataLearningFailInterruptEnable =
+        QuadSPI_RSER_DLPFIE_MASK,                                /*!< Data learning pattern failure interrupt enable */
+    kQSPI_TxBufferFillInterruptEnable = QuadSPI_RSER_TBFIE_MASK, /*!< Tx buffer fill interrupt enable */
+    kQSPI_TxBufferUnderrunInterruptEnable = QuadSPI_RSER_TBUIE_MASK, /*!< Tx buffer underrun interrupt enable */
+    kQSPI_IllegalInstructionInterruptEnable =
+        QuadSPI_RSER_ILLINIE_MASK,                                    /*!< Illegal instruction error interrupt enable */
+    kQSPI_RxBufferOverflowInterruptEnable = QuadSPI_RSER_RBOIE_MASK,  /*!< Rx buffer overflow interrupt enable */
+    kQSPI_RxBufferDrainInterruptEnable = QuadSPI_RSER_RBDIE_MASK,     /*!< Rx buffer drain interrupt enable */
+    kQSPI_AHBSequenceErrorInterruptEnable = QuadSPI_RSER_ABSEIE_MASK, /*!< AHB sequence error interrupt enable */
+    kQSPI_AHBIllegalTransactionInterruptEnable =
+        QuadSPI_RSER_AITIE_MASK, /*!< AHB illegal transaction error interrupt enable */
+    kQSPI_AHBIllegalBurstSizeInterruptEnable =
+        QuadSPI_RSER_AIBSIE_MASK,                                       /*!< AHB illegal burst error interrupt enable */
+    kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK,   /*!< AHB buffer overflow interrupt enable */
+    kQSPI_IPCommandUsageErrorInterruptEnable = QuadSPI_RSER_IUEIE_MASK, /*!< IP command usage error interrupt enable */
+    kQSPI_IPCommandTriggerDuringAHBAccessInterruptEnable =
+        QuadSPI_RSER_IPAEIE_MASK, /*!< IP command trigger during AHB access error */
+    kQSPI_IPCommandTriggerDuringIPAccessInterruptEnable =
+        QuadSPI_RSER_IPIEIE_MASK, /*!< IP command trigger cannot be executed */
+    kQSPI_IPCommandTriggerDuringAHBGrantInterruptEnable =
+        QuadSPI_RSER_IPGEIE_MASK, /*!< IP command trigger during AHB grant error */
+    kQSPI_IPCommandTransactionFinishedInterruptEnable =
+        QuadSPI_RSER_TFIE_MASK,            /*!< IP command transaction finished interrupt enable */
+    kQSPI_AllInterruptEnable = 0x8C83F8D1U /*!< All error interrupt enable */
+};
+
+/*! @brief QSPI DMA request flag */
+enum _qspi_dma_enable
+{
+    kQSPI_TxBufferFillDMAEnable = QuadSPI_RSER_TBFDE_MASK,                  /*!< Tx buffer fill DMA */
+    kQSPI_RxBufferDrainDMAEnable = QuadSPI_RSER_RBDDE_MASK,                 /*!< Rx buffer drain DMA */
+    kQSPI_AllDDMAEnable = QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK /*!< All DMA source */
+};
+
+/*! @brief Phrase shift number for DQS mode. */
+typedef enum _qspi_dqs_phrase_shift
+{
+    kQSPI_DQSNoPhraseShift = 0x0U, /*!< No phase shift */
+    kQSPI_DQSPhraseShift45Degree,  /*!< Select 45 degree phase shift*/
+    kQSPI_DQSPhraseShift90Degree,  /*!< Select 90 degree phase shift */
+    kQSPI_DQSPhraseShift135Degree  /*!< Select 135 degree phase shift */
+} qspi_dqs_phrase_shift_t;
+
+/*! @brief DQS configure features*/
+typedef struct QspiDQSConfig
+{
+    uint32_t portADelayTapNum;     /*!< Delay chain tap number selection for QSPI port A DQS */
+    uint32_t portBDelayTapNum;     /*!< Delay chain tap number selection for QSPI port B DQS*/
+    qspi_dqs_phrase_shift_t shift; /*!< Phase shift for internal DQS generation */
+    bool enableDQSClkInverse;      /*!< Enable inverse clock for internal DQS generation */
+    bool enableDQSPadLoopback;     /*!< Enable DQS loop back from DQS pad */
+    bool enableDQSLoopback;        /*!< Enable DQS loop back */
+} qspi_dqs_config_t;
+
+/*! @brief Flash timing configuration. */
+typedef struct QspiFlashTiming
+{
+    uint32_t dataHoldTime; /*!< Serial flash data in hold time */
+    uint32_t CSHoldTime;   /*!< Serial flash CS hold time in terms of serial flash clock cycles */
+    uint32_t CSSetupTime;  /*!< Serial flash CS setup time in terms of serial flash clock cycles */
+} qspi_flash_timing_t;
+
+/*! @brief QSPI configuration structure*/
+typedef struct QspiConfig
+{
+    uint32_t clockSource;                                       /*!< Clock source for QSPI module */
+    uint32_t baudRate;                                          /*!< Serial flash clock baud rate */
+    uint8_t txWatermark;                                        /*!< QSPI transmit watermark value */
+    uint8_t rxWatermark;                                        /*!< QSPI receive watermark value. */
+    uint32_t AHBbufferSize[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT];  /*!< AHB buffer size. */
+    uint8_t AHBbufferMaster[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer master.  */
+    bool enableAHBbuffer3AllMaster;                             /*!< Is AHB buffer3 for all master.*/
+    qspi_read_area_t area;                                      /*!< Which area Rx data readout */
+    bool enableQspi;                                            /*!< Enable QSPI after initialization */
+} qspi_config_t;
+
+/*! @brief External flash configuration items*/
+typedef struct _qspi_flash_config
+{
+    uint32_t flashA1Size;                             /*!< Flash A1 size */
+    uint32_t flashA2Size;                             /*!< Flash A2 size */
+    uint32_t flashB1Size;                             /*!< Flash B1 size */
+    uint32_t flashB2Size;                             /*!< Flash B2 size */
+    uint32_t lookuptable[FSL_FEATURE_QSPI_LUT_DEPTH]; /*!< Flash command in LUT */
+    uint32_t dataHoldTime;                            /*!< Data line hold time. */
+    uint32_t CSHoldTime;                              /*!< CS line hold time */
+    uint32_t CSSetupTime;                             /*!< CS line setup time*/
+    uint32_t cloumnspace;                             /*!< Column space size */
+    uint32_t dataLearnValue;                          /*!< Data Learn value if enable data learn */
+    qspi_endianness_t endian;                         /*!< Flash data endianess. */
+    bool enableWordAddress;                           /*!< If enable word address.*/
+} qspi_flash_config_t;
+
+/*! @brief Transfer structure for QSPI */
+typedef struct _qspi_transfer
+{
+    uint32_t *data;  /*!< Pointer to data to transmit */
+    size_t dataSize; /*!< Bytes to be transmit */
+} qspi_transfer_t;
+
+/******************************************************************************
+ * API
+ *****************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the QSPI module and internal state.
+ *
+ * This function enables the clock for QSPI and also configures the QSPI with the
+ * input configure parameters. Users should call this function before any QSPI operations.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param config QSPI configure structure.
+ * @param srcClock_Hz QSPI source clock frequency in Hz.
+ */
+void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Gets default settings for QSPI.
+ *
+ * @param config QSPI configuration structure.
+ */
+void QSPI_GetDefaultQspiConfig(qspi_config_t *config);
+
+/*!
+ * @brief Deinitializes the QSPI module.
+ *
+ * Clears the QSPI state and  QSPI module registers.
+ * @param base Pointer to QuadSPI Type.
+ */
+void QSPI_Deinit(QuadSPI_Type *base);
+
+/*!
+ * @brief Configures the serial flash parameter.
+ *
+ * This function configures the serial flash relevant parameters, such as the size, command, and so on.
+ * The flash configuration value cannot have a default value. The user needs to configure it according to the
+ * QSPI features.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param config Flash configuration parameters.
+ */
+void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config);
+
+/*!
+ * @brief Software reset for the QSPI logic.
+ *
+ * This function sets the software reset flags for both AHB and buffer domain and
+ * resets both AHB buffer and also IP FIFOs.
+ *
+ * @param base Pointer to QuadSPI Type.
+ */
+void QSPI_SoftwareReset(QuadSPI_Type *base);
+
+/*!
+ * @brief Enables or disables the QSPI module.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param enable True means enable QSPI, false means disable.
+ */
+static inline void QSPI_Enable(QuadSPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->MCR &= ~QuadSPI_MCR_MDIS_MASK;
+    }
+    else
+    {
+        base->MCR |= QuadSPI_MCR_MDIS_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the state value of QSPI.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @return status flag, use status flag to AND #_qspi_flags could get the related status.
+ */
+static inline uint32_t QSPI_GetStatusFlags(QuadSPI_Type *base)
+{
+    return base->SR;
+}
+
+/*!
+ * @brief Gets QSPI error status flags.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @return status flag, use status flag to AND #_qspi_error_flags could get the related status.
+ */
+static inline uint32_t QSPI_GetErrorStatusFlags(QuadSPI_Type *base)
+{
+    return base->FR;
+}
+
+/*! @brief Clears the QSPI error flags.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param mask Which kind of QSPI flags to be cleared, a combination of _qspi_error_flags.
+ */
+static inline void QSPI_ClearErrorFlag(QuadSPI_Type *base, uint32_t mask)
+{
+    base->FR = mask;
+}
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the QSPI interrupts.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param mask QSPI interrupt source.
+ */
+static inline void QSPI_EnableInterrupts(QuadSPI_Type *base, uint32_t mask)
+{
+    base->RSER |= mask;
+}
+
+/*!
+ * @brief Disables the QSPI interrupts.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param mask QSPI interrupt source.
+ */
+static inline void QSPI_DisableInterrupts(QuadSPI_Type *base, uint32_t mask)
+{
+    base->RSER &= ~mask;
+}
+
+/*! @} */
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Enables the QSPI DMA source.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param mask QSPI DMA source.
+ * @param enable True means enable DMA, false means disable.
+ */
+static inline void QSPI_EnableDMA(QuadSPI_Type *base, uint32_t mask, bool enable)
+{
+    if (enable)
+    {
+        base->RSER |= mask;
+    }
+    else
+    {
+        base->RSER &= ~mask;
+    }
+}
+
+/*!
+ * @brief Gets the Tx data register address. It is used for DMA operation.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @return QSPI Tx data register address.
+ */
+static inline uint32_t QSPI_GetTxDataRegisterAddress(QuadSPI_Type *base)
+{
+    return (uint32_t)(&base->TBDR);
+}
+
+/*!
+ * @brief Gets the Rx data register address used for DMA operation.
+ *
+ * This function returns the Rx data register address or Rx buffer address
+ * according to the Rx read area settings.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @return QSPI Rx data register address.
+ */
+uint32_t QSPI_GetRxDataRegisterAddress(QuadSPI_Type *base);
+
+/* @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*! @brief Sets the IP command address.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param addr IP command address.
+ */
+static inline void QSPI_SetIPCommandAddress(QuadSPI_Type *base, uint32_t addr)
+{
+    base->SFAR = addr;
+}
+
+/*! @brief Sets the IP command size.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param size IP command size.
+ */
+static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint32_t size)
+{
+    base->IPCR = ((base->IPCR & (~QuadSPI_IPCR_IDATSZ_MASK)) | QuadSPI_IPCR_IDATSZ(size));
+}
+
+/*! @brief Executes IP commands located in LUT table.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param index IP command located in which LUT table index.
+ */
+void QSPI_ExecuteIPCommand(QuadSPI_Type *base, uint32_t index);
+
+/*! @brief Executes AHB commands located in LUT table.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param index AHB command located in which LUT table index.
+ */
+void QSPI_ExecuteAHBCommand(QuadSPI_Type *base, uint32_t index);
+
+/*! @brief Enables/disables the QSPI IP command parallel mode.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param enable True means enable parallel mode, false means disable parallel mode.
+ */
+static inline void QSPI_EnableIPParallelMode(QuadSPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->IPCR |= QuadSPI_IPCR_PAR_EN_MASK;
+    }
+    else
+    {
+        base->IPCR &= ~QuadSPI_IPCR_PAR_EN_MASK;
+    }
+}
+
+/*! @brief Enables/disables the QSPI AHB command parallel mode.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param enable True means enable parallel mode, false means disable parallel mode.
+ */
+static inline void QSPI_EnableAHBParallelMode(QuadSPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->BFGENCR |= QuadSPI_BFGENCR_PAR_EN_MASK;
+    }
+    else
+    {
+        base->BFGENCR &= ~QuadSPI_BFGENCR_PAR_EN_MASK;
+    }
+}
+
+/*! @brief Updates the LUT table.
+*
+* @param base Pointer to QuadSPI Type.
+* @param index Which LUT index needs to be located. It should be an integer divided by 4.
+* @param cmd Command sequence array.
+*/
+void QSPI_UpdateLUT(QuadSPI_Type *base, uint32_t index, uint32_t *cmd);
+
+/*! @brief Clears the QSPI FIFO logic.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param mask Which kind of QSPI FIFO to be cleared.
+ */
+static inline void QSPI_ClearFifo(QuadSPI_Type *base, uint32_t mask)
+{
+    base->MCR |= mask;
+}
+
+/*!@ brief Clears the command sequence for the IP/buffer command.
+ *
+ * This function can reset the command sequence.
+ * @param base QSPI base address.
+ * @param seq Which command sequence need to reset, IP command, buffer command or both.
+ */
+static inline void QSPI_ClearCommandSequence(QuadSPI_Type *base, qspi_command_seq_t seq)
+{
+    base->SPTRCLR = seq;
+}
+
+/*!@ brief Set the RX buffer readout area.
+ *
+ * This function can set the RX buffer readout, from AHB bus or IP Bus.
+ * @param base QSPI base address.
+ * @param area QSPI Rx buffer readout area. AHB bus buffer or IP bus buffer.
+ */
+void QSPI_SetReadDataArea(QuadSPI_Type *base, qspi_read_area_t area);
+
+/*!
+ * @brief Sends a buffer of data bytes using a  blocking method.
+ * @note This function blocks via polling until all bytes have been sent.
+ * @param base QSPI base pointer
+ * @param buffer The data bytes to send
+ * @param size The number of data bytes to send
+ */
+void QSPI_WriteBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size);
+
+/*!
+ * @brief Writes data into FIFO.
+ *
+ * @param base QSPI base pointer
+ * @param data The data bytes to send
+ */
+static inline void QSPI_WriteData(QuadSPI_Type *base, uint32_t data)
+{
+    base->TBDR = data;
+}
+
+/*!
+ * @brief Receives a buffer of data bytes using a blocking method.
+ * @note This function blocks via polling until all bytes have been sent.
+ * @param base QSPI base pointer
+ * @param buffer The data bytes to send
+ * @param size The number of data bytes to receive
+ */
+void QSPI_ReadBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size);
+
+/*!
+ * @brief Receives data from data FIFO.
+ *
+ * @param base QSPI base pointer
+ * @return The data in the FIFO.
+ */
+uint32_t QSPI_ReadData(QuadSPI_Type *base);
+
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Writes data to the QSPI transmit buffer.
+ *
+ * This function writes a continuous data to the QSPI transmit FIFO. This function is a block function
+ * and can return only when finished. This function uses polling methods.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param xfer QSPI transfer structure.
+ */
+static inline void QSPI_TransferSendBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer)
+{
+    QSPI_WriteBlocking(base, xfer->data, xfer->dataSize);
+}
+
+/*!
+ * @brief Reads data from the QSPI receive buffer in polling way.
+ *
+ * This function reads continuous data from the QSPI receive buffer/FIFO. This function is a blocking
+ * function and can return only when finished. This function uses polling methods.
+ * @param base Pointer to QuadSPI Type.
+ * @param xfer QSPI transfer structure.
+ */
+static inline void QSPI_TransferReceiveBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer)
+{
+    QSPI_ReadBlocking(base, xfer->data, xfer->dataSize);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* @}*/
+
+#endif /* _FSL_QSPI_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi_edma.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi_edma.c
new file mode 100644
index 00000000000..290ee3af3d3
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi_edma.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_qspi_edma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! Structure definition for qspi_edma_private_handle_t. The structure is private. */
+typedef struct _qspi_edma_private_handle
+{
+    QuadSPI_Type *base;
+    qspi_edma_handle_t *handle;
+} qspi_edma_private_handle_t;
+
+/* QSPI EDMA transfer handle. */
+enum _qspi_edma_tansfer_states
+{
+    kQSPI_Idle,   /* TX idle. */
+    kQSPI_BusBusy /* RX busy. */
+};
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! Private handle only used for internally. */
+static qspi_edma_private_handle_t s_edmaPrivateHandle[FSL_FEATURE_SOC_QuadSPI_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief QSPI EDMA send finished callback function.
+ *
+ * This function is called when QSPI EDMA send finished. It disables the QSPI
+ * TX EDMA request and sends @ref kStatus_QSPI_TxIdle to QSPI callback.
+ *
+ * @param handle The EDMA handle.
+ * @param param Callback function parameter.
+ */
+static void QSPI_SendEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
+
+/*!
+ * @brief QSPI EDMA receive finished callback function.
+ *
+ * This function is called when QSPI EDMA receive finished. It disables the QSPI
+ * RX EDMA request and sends @ref kStatus_QSPI_RxIdle to QSPI callback.
+ *
+ * @param handle The EDMA handle.
+ * @param param Callback function parameter.
+ */
+static void QSPI_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
+
+/*!
+ * @brief Get the QSPI instance from peripheral base address.
+ *
+ * @param base QSPI peripheral base address.
+ * @return QSPI instance.
+ */
+extern uint32_t QSPI_GetInstance(QuadSPI_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void QSPI_SendEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
+{
+    qspi_edma_private_handle_t *qspiPrivateHandle = (qspi_edma_private_handle_t *)param;
+
+    /* Avoid the warning for unused variables. */
+    handle = handle;
+    tcds = tcds;
+
+    if (transferDone)
+    {
+        QSPI_TransferAbortSendEDMA(qspiPrivateHandle->base, qspiPrivateHandle->handle);
+
+        if (qspiPrivateHandle->handle->callback)
+        {
+            qspiPrivateHandle->handle->callback(qspiPrivateHandle->base, qspiPrivateHandle->handle, kStatus_QSPI_Idle,
+                                                qspiPrivateHandle->handle->userData);
+        }
+    }
+}
+
+static void QSPI_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
+{
+    qspi_edma_private_handle_t *qspiPrivateHandle = (qspi_edma_private_handle_t *)param;
+
+    /* Avoid warning for unused parameters. */
+    handle = handle;
+    tcds = tcds;
+
+    if (transferDone)
+    {
+        /* Disable transfer. */
+        QSPI_TransferAbortReceiveEDMA(qspiPrivateHandle->base, qspiPrivateHandle->handle);
+
+        if (qspiPrivateHandle->handle->callback)
+        {
+            qspiPrivateHandle->handle->callback(qspiPrivateHandle->base, qspiPrivateHandle->handle, kStatus_QSPI_Idle,
+                                                qspiPrivateHandle->handle->userData);
+        }
+    }
+}
+
+void QSPI_TransferTxCreateHandleEDMA(QuadSPI_Type *base,
+                                     qspi_edma_handle_t *handle,
+                                     qspi_edma_callback_t callback,
+                                     void *userData,
+                                     edma_handle_t *dmaHandle)
+{
+    assert(handle);
+
+    uint32_t instance = QSPI_GetInstance(base);
+
+    s_edmaPrivateHandle[instance].base = base;
+    s_edmaPrivateHandle[instance].handle = handle;
+
+    memset(handle, 0, sizeof(*handle));
+
+    handle->state = kQSPI_Idle;
+    handle->dmaHandle = dmaHandle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Get the watermark value */
+    handle->count = base->TBCT + 1;
+
+    /* Configure TX edma callback */
+    EDMA_SetCallback(handle->dmaHandle, QSPI_SendEDMACallback, &s_edmaPrivateHandle[instance]);
+}
+
+void QSPI_TransferRxCreateHandleEDMA(QuadSPI_Type *base,
+                                     qspi_edma_handle_t *handle,
+                                     qspi_edma_callback_t callback,
+                                     void *userData,
+                                     edma_handle_t *dmaHandle)
+{
+    assert(handle);
+
+    uint32_t instance = QSPI_GetInstance(base);
+
+    s_edmaPrivateHandle[instance].base = base;
+    s_edmaPrivateHandle[instance].handle = handle;
+
+    memset(handle, 0, sizeof(*handle));
+
+    handle->state = kQSPI_Idle;
+    handle->dmaHandle = dmaHandle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Get the watermark value */
+    handle->count = (base->RBCT & QuadSPI_RBCT_WMRK_MASK) + 1;
+
+    /* Configure RX edma callback */
+    EDMA_SetCallback(handle->dmaHandle, QSPI_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]);
+}
+
+status_t QSPI_TransferSendEDMA(QuadSPI_Type *base, qspi_edma_handle_t *handle, qspi_transfer_t *xfer)
+{
+    assert(handle && (handle->dmaHandle));
+
+    edma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous TX not finished. */
+    if (kQSPI_BusBusy == handle->state)
+    {
+        status = kStatus_QSPI_Busy;
+    }
+    else
+    {
+        handle->state = kQSPI_BusBusy;
+
+        /* Prepare transfer. */
+        EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint32_t), (void *)QSPI_GetTxDataRegisterAddress(base),
+                             sizeof(uint32_t), (sizeof(uint32_t) * handle->count), xfer->dataSize,
+                             kEDMA_MemoryToPeripheral);
+
+        /* Submit transfer. */
+        EDMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+        EDMA_StartTransfer(handle->dmaHandle);
+
+        /* Enable QSPI TX EDMA. */
+        QSPI_EnableDMA(base, kQSPI_TxBufferFillDMAEnable, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+status_t QSPI_TransferReceiveEDMA(QuadSPI_Type *base, qspi_edma_handle_t *handle, qspi_transfer_t *xfer)
+{
+    assert(handle && (handle->dmaHandle));
+
+    edma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous TX not finished. */
+    if (kQSPI_BusBusy == handle->state)
+    {
+        status = kStatus_QSPI_Busy;
+    }
+    else
+    {
+        handle->state = kQSPI_BusBusy;
+
+        /* Prepare transfer. */
+        EDMA_PrepareTransfer(&xferConfig, (void *)QSPI_GetRxDataRegisterAddress(base), sizeof(uint32_t), xfer->data,
+                             sizeof(uint32_t), (sizeof(uint32_t) * handle->count), xfer->dataSize,
+                             kEDMA_PeripheralToMemory);
+
+        /* Submit transfer. */
+        EDMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+        EDMA_StartTransfer(handle->dmaHandle);
+
+        /* Enable QSPI TX EDMA. */
+        QSPI_EnableDMA(base, kQSPI_RxBufferDrainDMAEnable, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void QSPI_TransferAbortSendEDMA(QuadSPI_Type *base, qspi_edma_handle_t *handle)
+{
+    assert(handle && (handle->dmaHandle));
+
+    /* Disable QSPI TX EDMA. */
+    QSPI_EnableDMA(base, kQSPI_TxBufferFillDMAEnable, false);
+
+    /* Stop transfer. */
+    EDMA_AbortTransfer(handle->dmaHandle);
+
+    handle->state = kQSPI_Idle;
+}
+
+void QSPI_TransferAbortReceiveEDMA(QuadSPI_Type *base, qspi_edma_handle_t *handle)
+{
+    assert(handle && (handle->dmaHandle));
+
+    /* Disable QSPI RX EDMA. */
+    QSPI_EnableDMA(base, kQSPI_RxBufferDrainDMAEnable, false);
+
+    /* Stop transfer. */
+    EDMA_AbortTransfer(handle->dmaHandle);
+
+    handle->state = kQSPI_Idle;
+}
+
+status_t QSPI_TransferGetSendCountEDMA(QuadSPI_Type *base, qspi_edma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != kQSPI_BusBusy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = (handle->transferSize - EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel));
+    }
+
+    return status;
+}
+
+status_t QSPI_TransferGetReceiveCountEDMA(QuadSPI_Type *base, qspi_edma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != kQSPI_BusBusy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = (handle->transferSize - EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel));
+    }
+
+    return status;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi_edma.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi_edma.h
new file mode 100644
index 00000000000..b3d6081145a
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_qspi_edma.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_QSPI_EDMA_H_
+#define _FSL_QSPI_EDMA_H_
+
+#include "fsl_qspi.h"
+#include "fsl_edma.h"
+
+/*!
+ * @addtogroup qspi_edma
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+typedef struct _qspi_edma_handle qspi_edma_handle_t;
+
+/*! @brief QSPI eDMA transfer callback function for finish and error */
+typedef void (*qspi_edma_callback_t)(QuadSPI_Type *base, qspi_edma_handle_t *handle, status_t status, void *userData);
+
+/*! @brief QSPI DMA transfer handle, users should not touch the content of the handle.*/
+struct _qspi_edma_handle
+{
+    edma_handle_t *dmaHandle;      /*!< eDMA handler for QSPI send */
+    size_t transferSize;           /*!< Bytes need to transfer. */
+    uint8_t count;                 /*!< The transfer data count in a DMA request */
+    uint32_t state;                /*!< Internal state for QSPI eDMA transfer */
+    qspi_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurred */
+    void *userData;                /*!< User callback parameter */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the QSPI handle for send which is used in transactional functions and set the callback.
+ *
+ * @param base QSPI peripheral base address
+ * @param handle Pointer to qspi_edma_handle_t structure
+ * @param callback QSPI callback, NULL means no callback.
+ * @param userData User callback function data.
+ * @param rxDmaHandle User requested eDMA handle for eDMA transfer
+ */
+void QSPI_TransferTxCreateHandleEDMA(QuadSPI_Type *base,
+                                     qspi_edma_handle_t *handle,
+                                     qspi_edma_callback_t callback,
+                                     void *userData,
+                                     edma_handle_t *dmaHandle);
+
+/*!
+ * @brief Initializes the QSPI handle for receive which is used in transactional functions and set the callback.
+ *
+ * @param base QSPI peripheral base address
+ * @param handle Pointer to qspi_edma_handle_t structure
+ * @param callback QSPI callback, NULL means no callback.
+ * @param userData User callback function data.
+ * @param rxDmaHandle User requested eDMA handle for eDMA transfer
+ */
+void QSPI_TransferRxCreateHandleEDMA(QuadSPI_Type *base,
+                                     qspi_edma_handle_t *handle,
+                                     qspi_edma_callback_t callback,
+                                     void *userData,
+                                     edma_handle_t *dmaHandle);
+
+/*!
+ * @brief Transfers QSPI data using an eDMA non-blocking method.
+ *
+ * This function writes data to the QSPI transmit FIFO. This function is non-blocking.
+ * @param base Pointer to QuadSPI Type.
+ * @param handle Pointer to qspi_edma_handle_t structure
+ * @param xfer QSPI transfer structure.
+ */
+status_t QSPI_TransferSendEDMA(QuadSPI_Type *base, qspi_edma_handle_t *handle, qspi_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using an eDMA non-blocking method.
+ *
+ * This function receive data from the QSPI receive buffer/FIFO. This function is non-blocking.
+ * @param base Pointer to QuadSPI Type.
+ * @param handle Pointer to qspi_edma_handle_t structure
+ * @param xfer QSPI transfer structure.
+ */
+status_t QSPI_TransferReceiveEDMA(QuadSPI_Type *base, qspi_edma_handle_t *handle, qspi_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the sent data using eDMA.
+ *
+ * This function aborts the sent data using eDMA.
+ *
+ * @param base QSPI peripheral base address.
+ * @param handle Pointer to qspi_edma_handle_t structure
+ */
+void QSPI_TransferAbortSendEDMA(QuadSPI_Type *base, qspi_edma_handle_t *handle);
+
+/*!
+ * @brief Aborts the receive data using eDMA.
+ *
+ * This function abort receive data which using eDMA.
+ *
+ * @param base QSPI peripheral base address.
+ * @param handle Pointer to qspi_edma_handle_t structure
+ */
+void QSPI_TransferAbortReceiveEDMA(QuadSPI_Type *base, qspi_edma_handle_t *handle);
+
+/*!
+ * @brief Gets the transferred counts of send.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param handle Pointer to qspi_edma_handle_t structure.
+ * @param count Bytes sent.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t QSPI_TransferGetSendCountEDMA(QuadSPI_Type *base, qspi_edma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Gets the status of the receive transfer.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param handle Pointer to qspi_edma_handle_t structure
+ * @param count Bytes received.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t QSPI_TransferGetReceiveCountEDMA(QuadSPI_Type *base, qspi_edma_handle_t *handle, size_t *count);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* @} */
+
+#endif /* _FSL_QSPI_EDMA_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rcm.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rcm.c
new file mode 100644
index 00000000000..9cf7479d337
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rcm.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rcm.h"
+
+void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config)
+{
+    assert(config);
+
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+    uint32_t reg;
+
+    reg = (((uint32_t)config->enableFilterInStop << RCM_RPC_RSTFLTSS_SHIFT) | (uint32_t)config->filterInRunWait);
+    if (config->filterInRunWait == kRCM_FilterBusClock)
+    {
+        reg |= ((uint32_t)config->busClockFilterCount << RCM_RPC_RSTFLTSEL_SHIFT);
+    }
+    base->RPC = reg;
+#else
+    base->RPFC = ((uint8_t)(config->enableFilterInStop << RCM_RPFC_RSTFLTSS_SHIFT) | (uint8_t)config->filterInRunWait);
+    if (config->filterInRunWait == kRCM_FilterBusClock)
+    {
+        base->RPFW = config->busClockFilterCount;
+    }
+#endif /* FSL_FEATURE_RCM_REG_WIDTH */
+}
+
+#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM)
+void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config)
+{
+    uint32_t reg;
+
+    reg = base->FM;
+    reg &= ~RCM_FM_FORCEROM_MASK;
+    reg |= ((uint32_t)config << RCM_FM_FORCEROM_SHIFT);
+    base->FM = reg;
+}
+#endif /* #if FSL_FEATURE_RCM_HAS_BOOTROM */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rcm.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rcm.h
new file mode 100644
index 00000000000..fbc51691976
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rcm.h
@@ -0,0 +1,431 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_RCM_H_
+#define _FSL_RCM_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup rcm */
+/*! @{*/
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief RCM driver version 2.0.1. */
+#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*!
+ * @brief System Reset Source Name definitions
+ */
+typedef enum _rcm_reset_source
+{
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+/* RCM register bit width is 32. */
+#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP)
+    kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */
+#endif
+    kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< Low-voltage detect reset */
+#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC)
+    kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */
+#endif                                 /* FSL_FEATURE_RCM_HAS_LOC */
+#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL)
+    kRCM_SourceLol = RCM_SRS_LOL_MASK,   /*!< Loss of lock reset */
+#endif                                   /* FSL_FEATURE_RCM_HAS_LOL */
+    kRCM_SourceWdog = RCM_SRS_WDOG_MASK, /*!< Watchdog reset */
+    kRCM_SourcePin = RCM_SRS_PIN_MASK,   /*!< External pin reset */
+    kRCM_SourcePor = RCM_SRS_POR_MASK,   /*!< Power on reset */
+#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG)
+    kRCM_SourceJtag = RCM_SRS_JTAG_MASK,     /*!< JTAG generated reset */
+#endif                                       /* FSL_FEATURE_RCM_HAS_JTAG */
+    kRCM_SourceLockup = RCM_SRS_LOCKUP_MASK, /*!< Core lock up reset */
+    kRCM_SourceSw = RCM_SRS_SW_MASK,         /*!< Software reset */
+#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP)
+    kRCM_SourceMdmap = RCM_SRS_MDM_AP_MASK, /*!< MDM-AP system reset */
+#endif                                      /* FSL_FEATURE_RCM_HAS_MDM_AP */
+#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT)
+    kRCM_SourceEzpt = RCM_SRS_EZPT_MASK,       /*!< EzPort reset */
+#endif                                         /* FSL_FEATURE_RCM_HAS_EZPORT */
+    kRCM_SourceSackerr = RCM_SRS_SACKERR_MASK, /*!< Parameter could get all reset flags */
+
+#else /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+/* RCM register bit width is 8. */
+#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP)
+    kRCM_SourceWakeup = RCM_SRS0_WAKEUP_MASK, /*!< Low-leakage wakeup reset */
+#endif
+    kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< Low-voltage detect reset */
+#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC)
+    kRCM_SourceLoc = RCM_SRS0_LOC_MASK,   /*!< Loss of clock reset */
+#endif /* FSL_FEATURE_RCM_HAS_LOC */
+#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL)
+    kRCM_SourceLol = RCM_SRS0_LOL_MASK,   /*!< Loss of lock reset */
+#endif /* FSL_FEATURE_RCM_HAS_LOL */
+    kRCM_SourceWdog = RCM_SRS0_WDOG_MASK, /*!< Watchdog reset */
+    kRCM_SourcePin = RCM_SRS0_PIN_MASK,   /*!< External pin reset */
+    kRCM_SourcePor = RCM_SRS0_POR_MASK, /*!< Power on reset */
+#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG)
+    kRCM_SourceJtag = RCM_SRS1_JTAG_MASK << 8U,     /*!< JTAG generated reset */
+#endif /* FSL_FEATURE_RCM_HAS_JTAG */
+    kRCM_SourceLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< Core lock up reset */
+    kRCM_SourceSw = RCM_SRS1_SW_MASK << 8U, /*!< Software reset */
+#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP)
+    kRCM_SourceMdmap = RCM_SRS1_MDM_AP_MASK << 8U,    /*!< MDM-AP system reset */
+#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */
+#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT)
+    kRCM_SourceEzpt = RCM_SRS1_EZPT_MASK << 8U,       /*!< EzPort reset */
+#endif /* FSL_FEATURE_RCM_HAS_EZPORT */
+    kRCM_SourceSackerr = RCM_SRS1_SACKERR_MASK << 8U, /*!< Parameter could get all reset flags */
+#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+    kRCM_SourceAll = 0xffffffffU,
+} rcm_reset_source_t;
+
+/*!
+ * @brief Reset pin filter select in Run and Wait modes
+ */
+typedef enum _rcm_run_wait_filter_mode
+{
+    kRCM_FilterDisable = 0U,  /*!< All filtering disabled */
+    kRCM_FilterBusClock = 1U, /*!< Bus clock filter enabled */
+    kRCM_FilterLpoClock = 2U  /*!< LPO clock filter enabled */
+} rcm_run_wait_filter_mode_t;
+
+#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM)
+/*!
+ * @brief Boot from ROM configuration.
+ */
+typedef enum _rcm_boot_rom_config
+{
+    kRCM_BootFlash = 0U,   /*!< Boot from flash */
+    kRCM_BootRomCfg0 = 1U, /*!< Boot from boot ROM due to BOOTCFG0 */
+    kRCM_BootRomFopt = 2U, /*!< Boot from boot ROM due to FOPT[7] */
+    kRCM_BootRomBoth = 3U  /*!< Boot from boot ROM due to both BOOTCFG0 and FOPT[7] */
+} rcm_boot_rom_config_t;
+#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */
+
+#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE)
+/*!
+ * @brief Max delay time from interrupt asserts to system reset.
+ */
+typedef enum _rcm_reset_delay
+{
+    kRCM_ResetDelay8Lpo = 0U,   /*!< Delay 8 LPO cycles.   */
+    kRCM_ResetDelay32Lpo = 1U,  /*!< Delay 32 LPO cycles.  */
+    kRCM_ResetDelay128Lpo = 2U, /*!< Delay 128 LPO cycles. */
+    kRCM_ResetDelay512Lpo = 3U  /*!< Delay 512 LPO cycles. */
+} rcm_reset_delay_t;
+
+/*!
+ * @brief System reset interrupt enable bit definitions.
+ */
+typedef enum _rcm_interrupt_enable
+{
+    kRCM_IntNone = 0U,                              /*!< No interrupt enabled.           */
+    kRCM_IntLossOfClk = RCM_SRIE_LOC_MASK,          /*!< Loss of clock interrupt.        */
+    kRCM_IntLossOfLock = RCM_SRIE_LOL_MASK,         /*!< Loss of lock interrupt.         */
+    kRCM_IntWatchDog = RCM_SRIE_WDOG_MASK,          /*!< Watch dog interrupt.            */
+    kRCM_IntExternalPin = RCM_SRIE_PIN_MASK,        /*!< External pin interrupt.         */
+    kRCM_IntGlobal = RCM_SRIE_GIE_MASK,             /*!< Global interrupts.              */
+    kRCM_IntCoreLockup = RCM_SRIE_LOCKUP_MASK,      /*!< Core lock up interrupt           */
+    kRCM_IntSoftware = RCM_SRIE_SW_MASK,            /*!< software interrupt              */
+    kRCM_IntStopModeAckErr = RCM_SRIE_SACKERR_MASK, /*!< Stop mode ACK error interrupt.  */
+#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1)
+    kRCM_IntCore1 = RCM_SRIE_CORE1_MASK, /*!< Core 1 interrupt.               */
+#endif
+    kRCM_IntAll = RCM_SRIE_LOC_MASK /*!< Enable all interrupts.          */
+                  |
+                  RCM_SRIE_LOL_MASK | RCM_SRIE_WDOG_MASK | RCM_SRIE_PIN_MASK | RCM_SRIE_GIE_MASK |
+                  RCM_SRIE_LOCKUP_MASK | RCM_SRIE_SW_MASK | RCM_SRIE_SACKERR_MASK
+#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1)
+                  |
+                  RCM_SRIE_CORE1_MASK
+#endif
+} rcm_interrupt_enable_t;
+#endif /* FSL_FEATURE_RCM_HAS_SRIE */
+
+#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID)
+/*!
+ * @brief IP version ID definition.
+ */
+typedef struct _rcm_version_id
+{
+    uint16_t feature; /*!< Feature Specification Number. */
+    uint8_t minor;    /*!< Minor version number.         */
+    uint8_t major;    /*!< Major version number.         */
+} rcm_version_id_t;
+#endif
+
+/*!
+ * @brief Reset pin filter configuration
+ */
+typedef struct _rcm_reset_pin_filter_config
+{
+    bool enableFilterInStop;                    /*!< Reset pin filter select in stop mode. */
+    rcm_run_wait_filter_mode_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */
+    uint8_t busClockFilterCount;                /*!< Reset pin bus clock filter width.  */
+} rcm_reset_pin_filter_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name Reset Control Module APIs*/
+/*@{*/
+
+#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID)
+/*!
+ * @brief Gets the RCM version ID.
+ *
+ * This function gets the RCM version ID including the major version number,
+ * the minor version number, and the feature specification number.
+ *
+ * @param base RCM peripheral base address.
+ * @param versionId     Pointer to version ID structure.
+ */
+static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId)
+{
+    *((uint32_t *)versionId) = base->VERID;
+}
+#endif
+
+#if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM)
+/*!
+ * @brief Gets the reset source implemented status.
+ *
+ * This function gets the RCM parameter that indicates whether the corresponding reset source is implemented.
+ * Use source masks defined in the rcm_reset_source_t to get the desired source status.
+ *
+ * Example:
+   @code
+   uint32_t status;
+
+   // To test whether the MCU is reset using Watchdog.
+   status = RCM_GetResetSourceImplementedStatus(RCM) & (kRCM_SourceWdog | kRCM_SourcePin);
+   @endcode
+ *
+ * @param base RCM peripheral base address.
+ * @return All reset source implemented status bit map.
+ */
+static inline uint32_t RCM_GetResetSourceImplementedStatus(RCM_Type *base)
+{
+    return base->PARAM;
+}
+#endif /* FSL_FEATURE_RCM_HAS_PARAM */
+
+/*!
+ * @brief Gets the reset source status which caused a previous reset.
+ *
+ * This function gets the current reset source status. Use source masks
+ * defined in the rcm_reset_source_t to get the desired source status.
+ *
+ * Example:
+   @code
+   uint32_t resetStatus;
+
+   // To get all reset source statuses.
+   resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceAll;
+
+   // To test whether the MCU is reset using Watchdog.
+   resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceWdog;
+
+   // To test multiple reset sources.
+   resetStatus = RCM_GetPreviousResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin);
+   @endcode
+ *
+ * @param base RCM peripheral base address.
+ * @return All reset source status bit map.
+ */
+static inline uint32_t RCM_GetPreviousResetSources(RCM_Type *base)
+{
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+    return base->SRS;
+#else
+    return (uint32_t)((uint32_t)base->SRS0 | ((uint32_t)base->SRS1 << 8U));
+#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+}
+
+#if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS)
+/*!
+ * @brief Gets the sticky reset source status.
+ *
+ * This function gets the current reset source status that has not been cleared
+ * by software for some specific source.
+ *
+ * Example:
+   @code
+   uint32_t resetStatus;
+
+   // To get all reset source statuses.
+   resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll;
+
+   // To test whether the MCU is reset using Watchdog.
+   resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceWdog;
+
+   // To test multiple reset sources.
+   resetStatus = RCM_GetStickyResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin);
+   @endcode
+ *
+ * @param base RCM peripheral base address.
+ * @return All reset source status bit map.
+ */
+static inline uint32_t RCM_GetStickyResetSources(RCM_Type *base)
+{
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+    return base->SSRS;
+#else
+    return (base->SSRS0 | ((uint32_t)base->SSRS1 << 8U));
+#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+}
+
+/*!
+ * @brief Clears the sticky reset source status.
+ *
+ * This function clears the sticky system reset flags indicated by source masks.
+ *
+ * Example:
+   @code
+   // Clears multiple reset sources.
+   RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin);
+   @endcode
+ *
+ * @param base RCM peripheral base address.
+ * @param sourceMasks reset source status bit map
+ */
+static inline void RCM_ClearStickyResetSources(RCM_Type *base, uint32_t sourceMasks)
+{
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+    base->SSRS = sourceMasks;
+#else
+    base->SSRS0 = (sourceMasks & 0xffU);
+    base->SSRS1 = ((sourceMasks >> 8U) & 0xffU);
+#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+}
+#endif /* FSL_FEATURE_RCM_HAS_SSRS */
+
+/*!
+ * @brief Configures the reset pin filter.
+ *
+ * This function sets the reset pin filter including the filter source, filter
+ * width, and so on.
+ *
+ * @param base RCM peripheral base address.
+ * @param config Pointer to the configuration structure.
+ */
+void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config);
+
+#if (defined(FSL_FEATURE_RCM_HAS_EZPMS) && FSL_FEATURE_RCM_HAS_EZPMS)
+/*!
+ * @brief Gets the EZP_MS_B pin assert status.
+ *
+ * This function gets the easy port mode status (EZP_MS_B) pin assert status.
+ *
+ * @param base RCM peripheral base address.
+ * @return status  true - asserted, false - reasserted
+ */
+static inline bool RCM_GetEasyPortModePinStatus(RCM_Type *base)
+{
+    return (bool)(base->MR & RCM_MR_EZP_MS_MASK);
+}
+#endif /* FSL_FEATURE_RCM_HAS_EZPMS */
+
+#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM)
+/*!
+ * @brief Gets the ROM boot source.
+ *
+ * This function gets the ROM boot source during the last chip reset.
+ *
+ * @param base RCM peripheral base address.
+ * @return The ROM boot source.
+ */
+static inline rcm_boot_rom_config_t RCM_GetBootRomSource(RCM_Type *base)
+{
+    return (rcm_boot_rom_config_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT);
+}
+
+/*!
+ * @brief Clears the ROM boot source flag.
+ *
+ * This function clears the ROM boot source flag.
+ *
+ * @param base     Register base address of RCM
+ */
+static inline void RCM_ClearBootRomSource(RCM_Type *base)
+{
+    base->MR |= RCM_MR_BOOTROM_MASK;
+}
+
+/*!
+ * @brief Forces the boot from ROM.
+ *
+ * This function forces booting from ROM during all subsequent system resets.
+ *
+ * @param base RCM peripheral base address.
+ * @param config   Boot configuration.
+ */
+void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config);
+#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */
+
+#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE)
+/*!
+ * @brief Sets the system reset interrupt configuration.
+ *
+ * For a graceful shut down, the RCM supports delaying the assertion of the system
+ * reset for a period of time when the reset interrupt is generated. This function
+ * can be used to enable the interrupt and the delay period. The interrupts
+ * are passed in as bit mask. See rcm_int_t for details. For example, to
+ * delay a reset for 512 LPO cycles after the WDOG timeout or loss-of-clock occurs,
+ * configure as follows:
+ * RCM_SetSystemResetInterruptConfig(kRCM_IntWatchDog | kRCM_IntLossOfClk, kRCM_ResetDelay512Lpo);
+ *
+ * @param base RCM peripheral base address.
+ * @param intMask   Bit mask of the system reset interrupts to enable. See
+ *                  rcm_interrupt_enable_t for details.
+ * @param Delay     Bit mask of the system reset interrupts to enable.
+ */
+static inline void RCM_SetSystemResetInterruptConfig(RCM_Type *base, uint32_t intMask, rcm_reset_delay_t delay)
+{
+    base->SRIE = (intMask | delay);
+}
+#endif /* FSL_FEATURE_RCM_HAS_SRIE */
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* _FSL_RCM_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rtc.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rtc.c
new file mode 100644
index 00000000000..db6a2fadbb3
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rtc.c
@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rtc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define SECONDS_IN_A_DAY (86400U)
+#define SECONDS_IN_A_HOUR (3600U)
+#define SECONDS_IN_A_MINUTE (60U)
+#define DAYS_IN_A_YEAR (365U)
+#define YEAR_RANGE_START (1970U)
+#define YEAR_RANGE_END (2099U)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Checks whether the date and time passed in is valid
+ *
+ * @param datetime Pointer to structure where the date and time details are stored
+ *
+ * @return Returns false if the date & time details are out of range; true if in range
+ */
+static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Converts time data from datetime to seconds
+ *
+ * @param datetime Pointer to datetime structure where the date and time details are stored
+ *
+ * @return The result of the conversion in seconds
+ */
+static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Converts time data from seconds to a datetime structure
+ *
+ * @param seconds  Seconds value that needs to be converted to datetime format
+ * @param datetime Pointer to the datetime structure where the result of the conversion is stored
+ */
+static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    /* Table of days in a month for a non leap year. First entry in the table is not used,
+     * valid months start from 1
+     */
+    uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
+
+    /* Check year, month, hour, minute, seconds */
+    if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) ||
+        (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U))
+    {
+        /* If not correct then error*/
+        return false;
+    }
+
+    /* Adjust the days in February for a leap year */
+    if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0))
+    {
+        daysPerMonth[2] = 29U;
+    }
+
+    /* Check the validity of the day */
+    if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U))
+    {
+        return false;
+    }
+
+    return true;
+}
+
+static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    /* Number of days from begin of the non Leap-year*/
+    /* Number of days from begin of the non Leap-year*/
+    uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U};
+    uint32_t seconds;
+
+    /* Compute number of days from 1970 till given year*/
+    seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR;
+    /* Add leap year days */
+    seconds += ((datetime->year / 4) - (1970U / 4));
+    /* Add number of days till given month*/
+    seconds += monthDays[datetime->month];
+    /* Add days in given month. We subtract the current day as it is
+     * represented in the hours, minutes and seconds field*/
+    seconds += (datetime->day - 1);
+    /* For leap year if month less than or equal to Febraury, decrement day counter*/
+    if ((!(datetime->year & 3U)) && (datetime->month <= 2U))
+    {
+        seconds--;
+    }
+
+    seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) +
+              (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second;
+
+    return seconds;
+}
+
+static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    uint32_t x;
+    uint32_t secondsRemaining, days;
+    uint16_t daysInYear;
+    /* Table of days in a month for a non leap year. First entry in the table is not used,
+     * valid months start from 1
+     */
+    uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
+
+    /* Start with the seconds value that is passed in to be converted to date time format */
+    secondsRemaining = seconds;
+
+    /* Calcuate the number of days, we add 1 for the current day which is represented in the
+     * hours and seconds field
+     */
+    days = secondsRemaining / SECONDS_IN_A_DAY + 1;
+
+    /* Update seconds left*/
+    secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY;
+
+    /* Calculate the datetime hour, minute and second fields */
+    datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR;
+    secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR;
+    datetime->minute = secondsRemaining / 60U;
+    datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE;
+
+    /* Calculate year */
+    daysInYear = DAYS_IN_A_YEAR;
+    datetime->year = YEAR_RANGE_START;
+    while (days > daysInYear)
+    {
+        /* Decrease day count by a year and increment year by 1 */
+        days -= daysInYear;
+        datetime->year++;
+
+        /* Adjust the number of days for a leap year */
+        if (datetime->year & 3U)
+        {
+            daysInYear = DAYS_IN_A_YEAR;
+        }
+        else
+        {
+            daysInYear = DAYS_IN_A_YEAR + 1;
+        }
+    }
+
+    /* Adjust the days in February for a leap year */
+    if (!(datetime->year & 3U))
+    {
+        daysPerMonth[2] = 29U;
+    }
+
+    for (x = 1U; x <= 12U; x++)
+    {
+        if (days <= daysPerMonth[x])
+        {
+            datetime->month = x;
+            break;
+        }
+        else
+        {
+            days -= daysPerMonth[x];
+        }
+    }
+
+    datetime->day = days;
+}
+
+void RTC_Init(RTC_Type *base, const rtc_config_t *config)
+{
+    assert(config);
+
+    uint32_t reg;
+
+    CLOCK_EnableClock(kCLOCK_Rtc0);
+
+    /* Issue a software reset if timer is invalid */
+    if (RTC_GetStatusFlags(RTC) & kRTC_TimeInvalidFlag)
+    {
+        RTC_Reset(RTC);
+    }
+
+    reg = base->CR;
+    /* Setup the update mode and supervisor access mode */
+    reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK);
+    reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess);
+#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION
+    /* Setup the wakeup pin select */
+    reg &= ~(RTC_CR_WPS_MASK);
+    reg |= RTC_CR_WPS(config->wakeupSelect);
+#endif /* FSL_FEATURE_RTC_HAS_WAKEUP_PIN */
+    base->CR = reg;
+
+    /* Configure the RTC time compensation register */
+    base->TCR = (RTC_TCR_CIR(config->compensationInterval) | RTC_TCR_TCR(config->compensationTime));
+}
+
+void RTC_GetDefaultConfig(rtc_config_t *config)
+{
+    assert(config);
+
+    /* Wakeup pin will assert if the RTC interrupt asserts or if the wakeup pin is turned on */
+    config->wakeupSelect = false;
+    /* Registers cannot be written when locked */
+    config->updateMode = false;
+    /* Non-supervisor mode write accesses are not supported and will generate a bus error */
+    config->supervisorAccess = false;
+    /* Compensation interval used by the crystal compensation logic */
+    config->compensationInterval = 0;
+    /* Compensation time used by the crystal compensation logic */
+    config->compensationTime = 0;
+}
+
+status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    /* Return error if the time provided is not valid */
+    if (!(RTC_CheckDatetimeFormat(datetime)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Set time in seconds */
+    base->TSR = RTC_ConvertDatetimeToSeconds(datetime);
+
+    return kStatus_Success;
+}
+
+void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    uint32_t seconds = 0;
+
+    seconds = base->TSR;
+    RTC_ConvertSecondsToDatetime(seconds, datetime);
+}
+
+status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime)
+{
+    assert(alarmTime);
+
+    uint32_t alarmSeconds = 0;
+    uint32_t currSeconds = 0;
+
+    /* Return error if the alarm time provided is not valid */
+    if (!(RTC_CheckDatetimeFormat(alarmTime)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime);
+
+    /* Get the current time */
+    currSeconds = base->TSR;
+
+    /* Return error if the alarm time has passed */
+    if (alarmSeconds < currSeconds)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Set alarm in seconds*/
+    base->TAR = alarmSeconds;
+
+    return kStatus_Success;
+}
+
+void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    uint32_t alarmSeconds = 0;
+
+    /* Get alarm in seconds  */
+    alarmSeconds = base->TAR;
+
+    RTC_ConvertSecondsToDatetime(alarmSeconds, datetime);
+}
+
+void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask)
+{
+    /* The alarm flag is cleared by writing to the TAR register */
+    if (mask & kRTC_AlarmFlag)
+    {
+        base->TAR = 0U;
+    }
+
+    /* The timer overflow flag is cleared by initializing the TSR register.
+     * The time counter should be disabled for this write to be successful
+     */
+    if (mask & kRTC_TimeOverflowFlag)
+    {
+        base->TSR = 1U;
+    }
+
+    /* The timer overflow flag is cleared by initializing the TSR register.
+     * The time counter should be disabled for this write to be successful
+     */
+    if (mask & kRTC_TimeInvalidFlag)
+    {
+        base->TSR = 1U;
+    }
+}
+
+#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC)
+
+void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter)
+{
+    assert(counter);
+
+    *counter = (((uint64_t)base->MCHR << 32) | ((uint64_t)base->MCLR));
+}
+
+void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter)
+{
+    /* Prepare to initialize the register with the new value written */
+    base->MER &= ~RTC_MER_MCE_MASK;
+
+    base->MCHR = (uint32_t)((counter) >> 32);
+    base->MCLR = (uint32_t)(counter);
+}
+
+status_t RTC_IncrementMonotonicCounter(RTC_Type *base)
+{
+    if (base->SR & (RTC_SR_MOF_MASK | RTC_SR_TIF_MASK))
+    {
+        return kStatus_Fail;
+    }
+
+    /* Prepare to switch to increment mode */
+    base->MER |= RTC_MER_MCE_MASK;
+    /* Write anything so the counter increments*/
+    base->MCLR = 1U;
+
+    return kStatus_Success;
+}
+
+#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rtc.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rtc.h
new file mode 100644
index 00000000000..4357c2e9f9d
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_rtc.h
@@ -0,0 +1,412 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_RTC_H_
+#define _FSL_RTC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup rtc
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of RTC interrupts */
+typedef enum _rtc_interrupt_enable
+{
+    kRTC_TimeInvalidInterruptEnable = RTC_IER_TIIE_MASK,  /*!< Time invalid interrupt.*/
+    kRTC_TimeOverflowInterruptEnable = RTC_IER_TOIE_MASK, /*!< Time overflow interrupt.*/
+    kRTC_AlarmInterruptEnable = RTC_IER_TAIE_MASK,        /*!< Alarm interrupt.*/
+    kRTC_SecondsInterruptEnable = RTC_IER_TSIE_MASK       /*!< Seconds interrupt.*/
+} rtc_interrupt_enable_t;
+
+/*! @brief List of RTC flags */
+typedef enum _rtc_status_flags
+{
+    kRTC_TimeInvalidFlag = RTC_SR_TIF_MASK,  /*!< Time invalid flag */
+    kRTC_TimeOverflowFlag = RTC_SR_TOF_MASK, /*!< Time overflow flag */
+    kRTC_AlarmFlag = RTC_SR_TAF_MASK         /*!< Alarm flag*/
+} rtc_status_flags_t;
+
+#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP)
+
+/*! @brief List of RTC Oscillator capacitor load settings */
+typedef enum _rtc_osc_cap_load
+{
+    kRTC_Capacitor_2p = RTC_CR_SC2P_MASK,  /*!< 2pF capacitor load */
+    kRTC_Capacitor_4p = RTC_CR_SC4P_MASK,  /*!< 4pF capacitor load */
+    kRTC_Capacitor_8p = RTC_CR_SC8P_MASK,  /*!< 8pF capacitor load */
+    kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16pF capacitor load */
+} rtc_osc_cap_load_t;
+
+#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */
+
+/*! @brief Structure is used to hold the date and time */
+typedef struct _rtc_datetime
+{
+    uint16_t year;  /*!< Range from 1970 to 2099.*/
+    uint8_t month;  /*!< Range from 1 to 12.*/
+    uint8_t day;    /*!< Range from 1 to 31 (depending on month).*/
+    uint8_t hour;   /*!< Range from 0 to 23.*/
+    uint8_t minute; /*!< Range from 0 to 59.*/
+    uint8_t second; /*!< Range from 0 to 59.*/
+} rtc_datetime_t;
+
+/*!
+ * @brief RTC config structure
+ *
+ * This structure holds the configuration settings for the RTC peripheral. To initialize this
+ * structure to reasonable defaults, call the RTC_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The config struct can be made const so it resides in flash
+ */
+typedef struct _rtc_config
+{
+    bool wakeupSelect;             /*!< true: Wakeup pin outputs the 32 KHz clock;
+                                        false:Wakeup pin used to wakeup the chip  */
+    bool updateMode;               /*!< true: Registers can be written even when locked under certain
+                                        conditions, false: No writes allowed when registers are locked */
+    bool supervisorAccess;         /*!< true: Non-supervisor accesses are allowed;
+                                        false: Non-supervisor accesses are not supported */
+    uint32_t compensationInterval; /*!< Compensation interval that is written to the CIR field in RTC TCR Register */
+    uint32_t compensationTime;     /*!< Compensation time that is written to the TCR field in RTC TCR Register */
+} rtc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the RTC clock and configures the peripheral for basic operation.
+ *
+ * This function will issue a software reset if the timer invalid flag is set.
+ *
+ * @note This API should be called at the beginning of the application using the RTC driver.
+ *
+ * @param base   RTC peripheral base address
+ * @param config Pointer to user's RTC config structure.
+ */
+void RTC_Init(RTC_Type *base, const rtc_config_t *config);
+
+/*!
+ * @brief Stop the timer and gate the RTC clock
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_Deinit(RTC_Type *base)
+{
+    /* Stop the RTC timer */
+    base->SR &= ~RTC_SR_TCE_MASK;
+
+    /* Gate the module clock */
+    CLOCK_DisableClock(kCLOCK_Rtc0);
+}
+
+/*!
+ * @brief Fill in the RTC config struct with the default settings
+ *
+ * The default values are:
+ * @code
+ *    config->wakeupSelect = false;
+ *    config->updateMode = false;
+ *    config->supervisorAccess = false;
+ *    config->compensationInterval = 0;
+ *    config->compensationTime = 0;
+ * @endcode
+ * @param config Pointer to user's RTC config structure.
+ */
+void RTC_GetDefaultConfig(rtc_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name Current Time & Alarm
+ * @{
+ */
+
+/*!
+ * @brief Sets the RTC date and time according to the given time structure.
+ *
+ * The RTC counter must be stopped prior to calling this function as writes to the RTC
+ * seconds register will fail if the RTC counter is running.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to structure where the date and time details to set are stored
+ *
+ * @return kStatus_Success: Success in setting the time and starting the RTC
+ *         kStatus_InvalidArgument: Error because the datetime format is incorrect
+ */
+status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Gets the RTC time and stores it in the given time structure.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to structure where the date and time details are stored.
+ */
+void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime);
+
+/*!
+ * @brief Sets the RTC alarm time
+ *
+ * The function checks whether the specified alarm time is greater than the present
+ * time. If not, the function does not set the alarm and returns an error.
+ *
+ * @param base      RTC peripheral base address
+ * @param alarmTime Pointer to structure where the alarm time is stored.
+ *
+ * @return kStatus_Success: success in setting the RTC alarm
+ *         kStatus_InvalidArgument: Error because the alarm datetime format is incorrect
+ *         kStatus_Fail: Error because the alarm time has already passed
+ */
+status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime);
+
+/*!
+ * @brief Returns the RTC alarm time.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to structure where the alarm date and time details are stored.
+ */
+void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime);
+
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::rtc_interrupt_enable_t
+ */
+static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask)
+{
+    base->IER |= mask;
+}
+
+/*!
+ * @brief Disables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::rtc_interrupt_enable_t
+ */
+static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask)
+{
+    base->IER &= ~mask;
+}
+
+/*!
+ * @brief Gets the enabled RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::rtc_interrupt_enable_t
+ */
+static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base)
+{
+    return (base->IER & (RTC_IER_TIIE_MASK | RTC_IER_TOIE_MASK | RTC_IER_TAIE_MASK | RTC_IER_TSIE_MASK));
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the RTC status flags
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::rtc_status_flags_t
+ */
+static inline uint32_t RTC_GetStatusFlags(RTC_Type *base)
+{
+    return (base->SR & (RTC_SR_TIF_MASK | RTC_SR_TOF_MASK | RTC_SR_TAF_MASK));
+}
+
+/*!
+ * @brief  Clears the RTC status flags.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::rtc_status_flags_t
+ */
+void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask);
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the RTC time counter.
+ *
+ * After calling this function, the timer counter increments once a second provided SR[TOF] or
+ * SR[TIF] are not set.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_StartTimer(RTC_Type *base)
+{
+    base->SR |= RTC_SR_TCE_MASK;
+}
+
+/*!
+ * @brief Stops the RTC time counter.
+ *
+ * RTC's seconds register can be written to only when the timer is stopped.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_StopTimer(RTC_Type *base)
+{
+    base->SR &= ~RTC_SR_TCE_MASK;
+}
+
+/*! @}*/
+
+#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP)
+
+/*!
+ * @brief This function sets the specified capacitor configuration for the RTC oscillator.
+ *
+ * @param base    RTC peripheral base address
+ * @param capLoad Oscillator loads to enable. This is a logical OR of members of the
+ *                enumeration ::rtc_osc_cap_load_t
+ */
+static inline void RTC_SetOscCapLoad(RTC_Type *base, uint32_t capLoad)
+{
+    uint32_t reg = base->CR;
+
+    reg &= ~(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK);
+    reg |= capLoad;
+
+    base->CR = reg;
+}
+
+#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */
+
+/*!
+ * @brief Performs a software reset on the RTC module.
+ *
+ * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR
+ * registers. The SWR bit is cleared by software explicitly clearing it.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_Reset(RTC_Type *base)
+{
+    base->CR |= RTC_CR_SWR_MASK;
+    base->CR &= ~RTC_CR_SWR_MASK;
+
+    /* Set TSR register to 0x1 to avoid the timer invalid (TIF) bit being set in the SR register */
+    base->TSR = 1U;
+}
+
+#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC)
+
+/*!
+ * @name Monotonic counter functions
+ * @{
+ */
+
+/*!
+ * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns
+ *        them as a single value.
+ *
+ * @param base    RTC peripheral base address
+ * @param counter Pointer to variable where the value is stored.
+ */
+void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter);
+
+/*!
+ * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing
+ *        the given single value.
+ *
+ * @param base    RTC peripheral base address
+ * @param counter Counter value
+ */
+void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter);
+
+/*!
+ * @brief Increments the Monotonic Counter by one.
+ *
+ * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting
+ * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the
+ * monotonic counter low that causes it to overflow also increments the monotonic counter high.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return kStatus_Success: success
+ *         kStatus_Fail: error occurred, either time invalid or monotonic overflow flag was found
+ */
+status_t RTC_IncrementMonotonicCounter(RTC_Type *base);
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_RTC_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_sim.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_sim.c
new file mode 100644
index 00000000000..3a4b801b7b3
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_sim.c
@@ -0,0 +1,53 @@
+/*
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_sim.h"
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR)
+void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask)
+{
+    SIM->SOPT1CFG |= (SIM_SOPT1CFG_URWE_MASK | SIM_SOPT1CFG_UVSWE_MASK | SIM_SOPT1CFG_USSWE_MASK);
+
+    SIM->SOPT1 = (SIM->SOPT1 & ~kSIM_UsbVoltRegEnableInAllModes) | mask;
+}
+#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */
+
+void SIM_GetUniqueId(sim_uid_t *uid)
+{
+#if defined(SIM_UIDH)
+    uid->H = SIM->UIDH;
+#endif
+    uid->MH = SIM->UIDMH;
+    uid->ML = SIM->UIDML;
+    uid->L = SIM->UIDL;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_sim.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_sim.h
new file mode 100644
index 00000000000..77958f86fd3
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_sim.h
@@ -0,0 +1,127 @@
+/*
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _FSL_SIM_H_
+#define _FSL_SIM_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup sim */
+/*! @{*/
+
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_SIM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Driver version 2.0.0 */
+/*@}*/
+
+#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR)
+/*!@brief USB voltage regulator enable setting. */
+enum _sim_usb_volt_reg_enable_mode
+{
+    kSIM_UsbVoltRegEnable = SIM_SOPT1_USBREGEN_MASK,           /*!< Enable voltage regulator. */
+    kSIM_UsbVoltRegEnableInLowPower = SIM_SOPT1_USBVSTBY_MASK, /*!< Enable voltage regulator in VLPR/VLPW modes. */
+    kSIM_UsbVoltRegEnableInStop = SIM_SOPT1_USBSSTBY_MASK, /*!< Enable voltage regulator in STOP/VLPS/LLS/VLLS modes. */
+    kSIM_UsbVoltRegEnableInAllModes = SIM_SOPT1_USBREGEN_MASK | SIM_SOPT1_USBSSTBY_MASK |
+                                      SIM_SOPT1_USBVSTBY_MASK /*!< Enable voltage regulator in all power modes. */
+};
+#endif /* (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) */
+
+/*!@brief Unique ID. */
+typedef struct _sim_uid
+{
+#if defined(SIM_UIDH)
+    uint32_t H; /*!< UIDH.  */
+#endif
+    uint32_t MH; /*!< UIDMH. */
+    uint32_t ML; /*!< UIDML. */
+    uint32_t L;  /*!< UIDL.  */
+} sim_uid_t;
+
+/*!@brief Flash enable mode. */
+enum _sim_flash_mode
+{
+    kSIM_FlashDisableInWait = SIM_FCFG1_FLASHDOZE_MASK, /*!< Disable flash in wait mode.   */
+    kSIM_FlashDisable = SIM_FCFG1_FLASHDIS_MASK         /*!< Disable flash in normal mode. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR)
+/*!
+ * @brief Sets the USB voltage regulator setting.
+ *
+ * This function configures whether the USB voltage regulator is enabled in
+ * normal RUN mode, STOP/VLPS/LLS/VLLS modes and VLPR/VLPW modes. The configurations
+ * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, enable
+ * USB voltage regulator in RUN/VLPR/VLPW modes and disable in STOP/VLPS/LLS/VLLS mode,
+ * please use:
+ *
+ * SIM_SetUsbVoltRegulatorEnableMode(kSIM_UsbVoltRegEnable | kSIM_UsbVoltRegEnableInLowPower);
+ *
+ * @param mask  USB voltage regulator enable setting.
+ */
+void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask);
+#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */
+
+/*!
+ * @brief Get the unique identification register value.
+ *
+ * @param uid Pointer to the structure to save the UID value.
+ */
+void SIM_GetUniqueId(sim_uid_t *uid);
+
+/*!
+ * @brief Set the flash enable mode.
+ *
+ * @param mode The mode to set, see \ref _sim_flash_mode for mode details.
+ */
+static inline void SIM_SetFlashMode(uint8_t mode)
+{
+    SIM->FCFG1 = mode;
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* _FSL_SIM_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard.h
new file mode 100644
index 00000000000..98baf325e9b
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard.h
@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_SMARTCARD_H_
+#define _FSL_SMARTCARD_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup smartcard
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Smart card driver version 2.1.1.
+ */
+#define FSL_SMARTCARD_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*@}*/
+
+/*! @brief Smart card global define which specify number of clock cycles until initial 'TS' character has to be received
+ */
+#define SMARTCARD_INIT_DELAY_CLOCK_CYCLES (42000u)
+
+/*! @brief Smart card global define which specify number of clock cycles during which ATR string has to be received */
+#define SMARTCARD_EMV_ATR_DURATION_ETU (20150u)
+
+/*! @brief Smart card specification initial TS character definition of direct convention */
+#define SMARTCARD_TS_DIRECT_CONVENTION (0x3Bu)
+
+/*! @brief Smart card specification initial TS character definition of inverse convention */
+#define SMARTCARD_TS_INVERSE_CONVENTION (0x3Fu)
+
+/*! @brief Smart card Error codes. */
+typedef enum _smartcard_status
+{
+    kStatus_SMARTCARD_Success = MAKE_STATUS(kStatusGroup_SMARTCARD, 0),              /*!< Transfer ends successfully */
+    kStatus_SMARTCARD_TxBusy = MAKE_STATUS(kStatusGroup_SMARTCARD, 1),               /*!< Transmit in progress */
+    kStatus_SMARTCARD_RxBusy = MAKE_STATUS(kStatusGroup_SMARTCARD, 2),               /*!< Receiving in progress */
+    kStatus_SMARTCARD_NoTransferInProgress = MAKE_STATUS(kStatusGroup_SMARTCARD, 3), /*!< No transfer in progress */
+    kStatus_SMARTCARD_Timeout = MAKE_STATUS(kStatusGroup_SMARTCARD, 4),              /*!< Transfer ends with time-out */
+    kStatus_SMARTCARD_Initialized =
+        MAKE_STATUS(kStatusGroup_SMARTCARD, 5), /*!< Smart card driver is already initialized */
+    kStatus_SMARTCARD_PhyInitialized =
+        MAKE_STATUS(kStatusGroup_SMARTCARD, 6), /*!< Smart card PHY drive is already  initialized */
+    kStatus_SMARTCARD_CardNotActivated = MAKE_STATUS(kStatusGroup_SMARTCARD, 7), /*!< Smart card is not activated */
+    kStatus_SMARTCARD_InvalidInput =
+        MAKE_STATUS(kStatusGroup_SMARTCARD, 8), /*!< Function called with invalid input arguments */
+    kStatus_SMARTCARD_OtherError = MAKE_STATUS(kStatusGroup_SMARTCARD, 9) /*!< Some other error occur */
+} smartcard_status_t;
+
+/*! @brief Control codes for the Smart card protocol timers and misc. */
+typedef enum _smartcard_control
+{
+    kSMARTCARD_EnableADT = 0x0u,
+    kSMARTCARD_DisableADT = 0x1u,
+    kSMARTCARD_EnableGTV = 0x2u,
+    kSMARTCARD_DisableGTV = 0x3u,
+    kSMARTCARD_ResetWWT = 0x4u,
+    kSMARTCARD_EnableWWT = 0x5u,
+    kSMARTCARD_DisableWWT = 0x6u,
+    kSMARTCARD_ResetCWT = 0x7u,
+    kSMARTCARD_EnableCWT = 0x8u,
+    kSMARTCARD_DisableCWT = 0x9u,
+    kSMARTCARD_ResetBWT = 0xAu,
+    kSMARTCARD_EnableBWT = 0xBu,
+    kSMARTCARD_DisableBWT = 0xCu,
+    kSMARTCARD_EnableInitDetect = 0xDu,
+    kSMARTCARD_EnableAnack = 0xEu,
+    kSMARTCARD_DisableAnack = 0xFu,
+    kSMARTCARD_ConfigureBaudrate = 0x10u,
+    kSMARTCARD_SetupATRMode = 0x11u,
+    kSMARTCARD_SetupT0Mode = 0x12u,
+    kSMARTCARD_SetupT1Mode = 0x13u,
+    kSMARTCARD_EnableReceiverMode = 0x14u,
+    kSMARTCARD_DisableReceiverMode = 0x15u,
+    kSMARTCARD_EnableTransmitterMode = 0x16u,
+    kSMARTCARD_DisableTransmitterMode = 0x17u,
+    kSMARTCARD_ResetWaitTimeMultiplier = 0x18u,
+} smartcard_control_t;
+
+/*! @brief Defines Smart card interface voltage class values */
+typedef enum _smartcard_card_voltage_class
+{
+    kSMARTCARD_VoltageClassUnknown = 0x0u,
+    kSMARTCARD_VoltageClassA5_0V = 0x1u,
+    kSMARTCARD_VoltageClassB3_3V = 0x2u,
+    kSMARTCARD_VoltageClassC1_8V = 0x3u
+} smartcard_card_voltage_class_t;
+
+/*! @brief Defines Smart card I/O transfer states */
+typedef enum _smartcard_transfer_state
+{
+    kSMARTCARD_IdleState = 0x0u,
+    kSMARTCARD_WaitingForTSState = 0x1u,
+    kSMARTCARD_InvalidTSDetecetedState = 0x2u,
+    kSMARTCARD_ReceivingState = 0x3u,
+    kSMARTCARD_TransmittingState = 0x4u,
+} smartcard_transfer_state_t;
+
+/*! @brief Defines Smart card reset types */
+typedef enum _smartcard_reset_type
+{
+    kSMARTCARD_ColdReset = 0x0u,
+    kSMARTCARD_WarmReset = 0x1u,
+    kSMARTCARD_NoColdReset = 0x2u,
+    kSMARTCARD_NoWarmReset = 0x3u,
+} smartcard_reset_type_t;
+
+/*! @brief Defines Smart card transport protocol types */
+typedef enum _smartcard_transport_type
+{
+    kSMARTCARD_T0Transport = 0x0u,
+    kSMARTCARD_T1Transport = 0x1u
+} smartcard_transport_type_t;
+
+/*! @brief Defines Smart card data parity types */
+typedef enum _smartcard_parity_type
+{
+    kSMARTCARD_EvenParity = 0x0u,
+    kSMARTCARD_OddParity = 0x1u
+} smartcard_parity_type_t;
+
+/*! @brief Defines data Convention format */
+typedef enum _smartcard_card_convention
+{
+    kSMARTCARD_DirectConvention = 0x0u,
+    kSMARTCARD_InverseConvention = 0x1u
+} smartcard_card_convention_t;
+
+/*! @brief Defines Smart card interface IC control types */
+typedef enum _smartcard_interface_control
+{
+    kSMARTCARD_InterfaceSetVcc = 0x00u,
+    kSMARTCARD_InterfaceSetClockToResetDelay = 0x01u,
+    kSMARTCARD_InterfaceReadStatus = 0x02u
+} smartcard_interface_control_t;
+
+/*! @brief Defines transfer direction.*/
+typedef enum _smartcard_direction
+{
+    kSMARTCARD_Receive = 0u,
+    kSMARTCARD_Transmit = 1u
+} smartcard_direction_t;
+
+/*! @brief Smart card interface interrupt callback function type */
+typedef void (*smartcard_interface_callback_t)(void *smartcardContext, void *param);
+/*! @brief Smart card transfer interrupt callback function type */
+typedef void (*smartcard_transfer_callback_t)(void *smartcardContext, void *param);
+
+/*! @brief Time Delay function used to passive waiting using RTOS [ms] */
+typedef void (*smartcard_time_delay_t)(uint32_t miliseconds);
+
+/*! @brief Defines card-specific parameters for Smart card driver */
+typedef struct _smartcard_card_params
+{
+    /* ISO7816/EMV4.3 specification variables */
+    uint16_t Fi;            /*!< 4 bits Fi - clock rate conversion integer */
+    uint8_t fMax;           /*!< Maximum Smart card frequency in MHz */
+    uint8_t WI;             /*!< 8 bits WI - work wait time integer */
+    uint8_t Di;             /*!< 4 bits DI - baud rate divisor */
+    uint8_t BWI;            /*!< 4 bits BWI - block wait time integer */
+    uint8_t CWI;            /*!< 4 bits CWI - character wait time integer */
+    uint8_t BGI;            /*!< 4 bits BGI - block guard time integer */
+    uint8_t GTN;            /*!< 8 bits GTN - extended guard time integer */
+    uint8_t IFSC;           /*!< Indicates IFSC value of the card */
+    uint8_t modeNegotiable; /*!< Indicates if the card acts in negotiable or a specific mode. */
+    uint8_t currentD;       /*!< 4 bits DI - current baud rate divisor*/
+    /* Driver-specific variables */
+    uint8_t status;                         /*!< Indicates smart card status */
+    bool t0Indicated;                       /*!< Indicates ff T=0 indicated in TD1 byte */
+    bool t1Indicated;                       /*!< Indicates if T=1 indicated in TD2 byte */
+    bool atrComplete;                       /*!< Indicates whether the ATR received from the card was complete or not */
+    bool atrValid;                          /*!< Indicates whether the ATR received from the card was valid or not */
+    bool present;                           /*!< Indicates if a smart card is present */
+    bool active;                            /*!< Indicates if the smart card is activated */
+    bool faulty;                            /*!< Indicates whether smart card/interface is faulty */
+    smartcard_card_convention_t convention; /*!< Card convention, kSMARTCARD_DirectConvention for direct convention,
+                                                 kSMARTCARD_InverseConvention for inverse convention */
+} smartcard_card_params_t;
+
+/*! @brief Smart card Defines the state of the EMV timers in the Smart card driver */
+typedef struct _smartcard_timers_state
+{
+    volatile bool adtExpired;           /*!< Indicates whether ADT timer expired */
+    volatile bool wwtExpired;           /*!< Indicates whether WWT timer expired */
+    volatile bool cwtExpired;           /*!< Indicates whether CWT timer expired */
+    volatile bool bwtExpired;           /*!< Indicates whether BWT timer expired */
+    volatile bool initCharTimerExpired; /*!< Indicates whether reception timer
+                for initialization character (TS) after the RST has expired */
+} smartcard_timers_state_t;
+
+/*! @brief Defines user specified configuration of Smart card interface */
+typedef struct _smartcard_interface_config
+{
+    uint32_t smartCardClock;            /*!< Smart card interface clock [Hz] */
+    uint32_t clockToResetDelay;         /*!< Indicates clock to RST apply delay [smart card clock cycles] */
+    uint8_t clockModule;                /*!< Smart card clock module number */
+    uint8_t clockModuleChannel;         /*!< Smart card clock module channel number */
+    uint8_t clockModuleSourceClock;     /*!< Smart card clock module source clock [e.g., BusClk] */
+    smartcard_card_voltage_class_t vcc; /*!< Smart card voltage class */
+    uint8_t controlPort;                /*!< Smart card PHY control port instance */
+    uint8_t controlPin;                 /*!< Smart card PHY control pin instance */
+    uint8_t irqPort;                    /*!< Smart card PHY Interrupt port instance */
+    uint8_t irqPin;                     /*!< Smart card PHY Interrupt pin instance */
+    uint8_t resetPort;                  /*!< Smart card reset port instance */
+    uint8_t resetPin;                   /*!< Smart card reset pin instance */
+    uint8_t vsel0Port;                  /*!< Smart card PHY Vsel0 control port instance */
+    uint8_t vsel0Pin;                   /*!< Smart card PHY Vsel0 control pin instance */
+    uint8_t vsel1Port;                  /*!< Smart card PHY Vsel1 control port instance */
+    uint8_t vsel1Pin;                   /*!< Smart card PHY Vsel1 control pin instance */
+    uint8_t dataPort;                   /*!< Smart card PHY data port instance */
+    uint8_t dataPin;                    /*!< Smart card PHY data pin instance */
+    uint8_t dataPinMux;                 /*!< Smart card PHY data pin mux option */
+    uint8_t tsTimerId; /*!< Numerical identifier of the External HW timer for Initial character detection */
+} smartcard_interface_config_t;
+
+/*! @brief Defines user transfer structure used to initialize transfer */
+typedef struct _smartcard_xfer
+{
+    smartcard_direction_t direction; /*!< Direction of communication. (RX/TX) */
+    uint8_t *buff;                   /*!< The buffer of data. */
+    size_t size;                     /*!< The number of transferred units. */
+} smartcard_xfer_t;
+
+/*!
+ * @brief Runtime state of the Smart card driver.
+ */
+typedef struct _smartcard_context
+{
+    /* Xfer part */
+    void *base;                      /*!< Smart card module base address */
+    smartcard_direction_t direction; /*!< Direction of communication. (RX/TX) */
+    uint8_t *xBuff;                  /*!< The buffer of data being transferred.*/
+    volatile size_t xSize;           /*!< The number of bytes to be transferred. */
+    volatile bool xIsBusy;           /*!< True if there is an active transfer. */
+    uint8_t txFifoEntryCount;        /*!< Number of data word entries in transmit FIFO. */
+    /* Smart card Interface part */
+    smartcard_interface_callback_t interfaceCallback; /*!< Callback to invoke after interface IC raised interrupt.*/
+    smartcard_transfer_callback_t transferCallback;   /*!< Callback to invoke after transfer event occur.*/
+    void *interfaceCallbackParam;                     /*!< Interface callback parameter pointer.*/
+    void *transferCallbackParam;                      /*!< Transfer callback parameter pointer.*/
+    smartcard_time_delay_t timeDelay;                 /*!< Function which handles time delay defined by user or RTOS. */
+    smartcard_reset_type_t resetType; /*!< Indicates whether a Cold reset or Warm reset was requested. */
+    smartcard_transport_type_t tType; /*!< Indicates current transfer protocol (T0 or T1) */
+    /* Smart card State part */
+    volatile smartcard_transfer_state_t transferState; /*!< Indicates the current transfer state */
+    smartcard_timers_state_t timersState; /*!< Indicates the state of different protocol timers used in driver */
+    smartcard_card_params_t
+        cardParams; /*!< Smart card parameters(ATR and current) and interface slots states(ATR and current) */
+    uint8_t IFSD;   /*!< Indicates the terminal IFSD */
+    smartcard_parity_type_t parity; /*!< Indicates current parity even/odd */
+    volatile bool rxtCrossed;       /*!< Indicates whether RXT thresholds has been crossed */
+    volatile bool txtCrossed;       /*!< Indicates whether TXT thresholds has been crossed */
+    volatile bool wtxRequested;     /*!< Indicates whether WTX has been requested or not*/
+    volatile bool parityError;      /*!< Indicates whether a parity error has been detected */
+    uint8_t statusBytes[2]; /*!< Used to store Status bytes SW1, SW2 of the last executed card command response */
+    /* Configuration part */
+    smartcard_interface_config_t interfaceConfig; /*!< Smart card interface configuration structure */
+
+} smartcard_context_t;
+
+/*! @}*/
+#endif /* _FSL_SMARTCARD_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_emvsim.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_emvsim.c
new file mode 100644
index 00000000000..5482771783c
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_emvsim.c
@@ -0,0 +1,955 @@
+/*
+* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_smartcard_emvsim.h"
+
+/*******************************************************************************
+* Variables
+******************************************************************************/
+/*! @brief Pointers to emvsim bases for each instance. */
+static EMVSIM_Type *const s_emvsimBases[] = EMVSIM_BASE_PTRS;
+
+/*! @brief Pointers to emvsim IRQ number for each instance. */
+static const IRQn_Type s_emvsimIRQ[] = EMVSIM_IRQS;
+
+/*! @brief Pointers to emvsim clocks for each instance. */
+static const clock_ip_name_t s_emvsimClock[] = EMVSIM_CLOCKS;
+
+/*******************************************************************************
+* Private Functions
+******************************************************************************/
+static void smartcard_emvsim_CompleteSendData(EMVSIM_Type *base, smartcard_context_t *context);
+static void smartcard_emvsim_StartSendData(EMVSIM_Type *base, smartcard_context_t *context);
+static void smartcard_emvsim_CompleteReceiveData(EMVSIM_Type *base, smartcard_context_t *context);
+static void smartcard_emvsim_StartReceiveData(EMVSIM_Type *base, smartcard_context_t *context);
+static void smartcard_emvsim_SetTransferType(EMVSIM_Type *base,
+                                             smartcard_context_t *context,
+                                             smartcard_control_t control);
+static uint32_t smartcard_emvsim_GetInstance(EMVSIM_Type *base);
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+/*!
+ * @brief Get the UART instance from peripheral base address.
+ *
+ * @param base UART peripheral base address.
+ * @return UART instance.
+ */
+static uint32_t smartcard_emvsim_GetInstance(EMVSIM_Type *base)
+{
+    uint8_t instance = 0;
+    uint32_t emvsimArrayCount = (sizeof(s_emvsimBases) / sizeof(s_emvsimBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < emvsimArrayCount; instance++)
+    {
+        if (s_emvsimBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < emvsimArrayCount);
+
+    return instance;
+}
+/*!
+ * @brief Finish up a transmit by completing the process of sending data and disabling the interrupt.
+ *
+ * @param base The EMVSIM peripheral base address.
+ * @param context A pointer to a SMARTCARD driver context structure.
+ */
+static void smartcard_emvsim_CompleteSendData(EMVSIM_Type *base, smartcard_context_t *context)
+{
+    assert((NULL != context));
+
+    /* Reset additional GETU */
+    base->TX_GETU = 0x00u;
+    /* Disable the transmission complete interrupt */
+    base->INT_MASK |= EMVSIM_INT_MASK_TC_IM_MASK;
+    /* Wait for TC bit to set - last byte transmission has finished */
+    while ((!(base->TX_STATUS & EMVSIM_TX_STATUS_TCF_MASK)))
+    {
+    }
+    /* Restore previous TX_GETU value */
+    base->TX_GETU = context->cardParams.GTN;
+    /* disable after transmit */
+    base->CTRL &= ~EMVSIM_CTRL_XMT_EN_MASK;
+    /* Clear receive status flag */
+    base->RX_STATUS = EMVSIM_RX_STATUS_RX_DATA_MASK;
+    /* Enable Receiver */
+    base->CTRL |= EMVSIM_CTRL_RCV_EN_MASK;
+    /* Update the information of the module driver context */
+    context->xIsBusy = false;
+    context->transferState = kSMARTCARD_IdleState;
+    /* Clear txSize to avoid any spurious transmit from ISR */
+    context->xSize = 0u;
+    /* Invoke user call-back */
+    if (NULL != context->transferCallback)
+    {
+        context->transferCallback(context, context->transferCallbackParam);
+    }
+}
+
+/*!
+ * @brief Finish up a receive by completing the process of receiving data and disabling the interrupt.
+ *
+ * @param base The EMVSIM peripheral base address.
+ * @param context A pointer to a SMARTCARD driver context structure.
+ */
+static void smartcard_emvsim_CompleteReceiveData(EMVSIM_Type *base, smartcard_context_t *context)
+{
+    assert((NULL != context));
+
+    /* Clear receive status flag */
+    base->RX_STATUS = EMVSIM_RX_STATUS_RX_DATA_MASK;
+    /* Disable receive data full interrupt */
+    base->INT_MASK |= EMVSIM_INT_MASK_RX_DATA_IM_MASK;
+    /* Update the information of the module driver context */
+    context->xIsBusy = false;
+    /* Invoke user call-back */
+    if (NULL != context->transferCallback)
+    {
+        context->transferCallback(context, context->transferCallbackParam);
+    }
+}
+
+/*!
+ * @brief Initiate (start) a transmit by beginning the process of sending data and enabling the interrupt.
+ *
+ * @param base The EMVSIM peripheral base address.
+ * @param context A pointer to a SMARTCARD driver context structure.
+ */
+static void smartcard_emvsim_StartSendData(EMVSIM_Type *base, smartcard_context_t *context)
+{
+    assert((NULL != context));
+
+    uint32_t delay = 0u;
+    uint32_t control = 0u;
+
+    /* Block guard time */
+    /* 22 etus (16 Receiver Clocks == 1 etu) */
+    delay = 22u * 16u;
+    /* Disable all functionality like protocol timers, NACK generation */
+    control = base->CTRL;
+    base->CTRL = 0u;
+    /* Clear Global counter time-out flag */
+    base->TX_STATUS = EMVSIM_TX_STATUS_GPCNT1_TO_MASK;
+    /* Disable counter interrupt */
+    base->INT_MASK |= EMVSIM_INT_MASK_GPCNT1_IM_MASK;
+    /* Set counter value */
+    base->GPCNT1_VAL = delay;
+    /* Select the clock for GPCNT */
+    base->CLKCFG =
+        (base->CLKCFG & ~EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK) | EMVSIM_CLKCFG_GPCNT1_CLK_SEL(kEMVSIM_GPCRxClock);
+    /* Trigger the counter */
+    base->CTRL |= EMVSIM_CTRL_RCV_EN_MASK;
+    /* Wait until counter overflow event occur */
+    while ((!(base->TX_STATUS & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)))
+    {
+    }
+    /* Clear status flag and disable GPCNT1 clock */
+    base->TX_STATUS = EMVSIM_TX_STATUS_GPCNT1_TO_MASK;
+    base->CLKCFG &= ~EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK;
+    /* Restore Control register */
+    base->CTRL = control & ~(EMVSIM_CTRL_XMT_EN_MASK | EMVSIM_CTRL_RCV_EN_MASK);
+    /* Update transferState */
+    context->transferState = kSMARTCARD_TransmittingState;
+    context->xIsBusy = true;
+    /* Enable transmitter */
+    base->CTRL |= EMVSIM_CTRL_XMT_EN_MASK;
+    /* Enable the transmission complete interrupt. The TC bit will
+     * set whenever the transmit data is shifted out */
+    base->INT_MASK &= ~EMVSIM_INT_MASK_TC_IM_MASK;
+}
+
+/*!
+ * @brief Initiate (start) a receive by beginning the process of receiving data and enabling the interrupt.
+ *
+ * @param base The EMVSIM peripheral base address.
+ * @param context A pointer to a SMARTCARD driver context structure.
+ */
+static void smartcard_emvsim_StartReceiveData(EMVSIM_Type *base, smartcard_context_t *context)
+{
+    assert((NULL != context));
+
+    /* Initialize the module driver context structure to indicate transfer in progress */
+    context->xIsBusy = true;
+    /* Enable BWT Timer interrupt to occur */
+    base->INT_MASK &= ~EMVSIM_INT_MASK_BWT_ERR_IM_MASK;
+    /* Clear receive status flag */
+    base->RX_STATUS = EMVSIM_RX_STATUS_RX_DATA_MASK;
+    /* Disable transmitter */
+    base->CTRL &= ~EMVSIM_CTRL_XMT_EN_MASK;
+    /* Enable receiver and switch to receive direction */
+    base->CTRL |= EMVSIM_CTRL_RCV_EN_MASK;
+    /* Enable the receive data full interrupt */
+    base->INT_MASK &= ~EMVSIM_INT_MASK_RX_DATA_IM_MASK;
+}
+
+/*!
+ * @brief Sets up the EMVSIM hardware for T=0 or T=1 protocol data exchange and initialize timer values.
+ *
+ * @param base The EMVSIM peripheral base address.
+ * @param context A pointer to a SMARTCARD driver context structure.
+ */
+static void smartcard_emvsim_SetTransferType(EMVSIM_Type *base,
+                                             smartcard_context_t *context,
+                                             smartcard_control_t control)
+{
+    assert((NULL != context));
+    assert((control == kSMARTCARD_SetupATRMode) || (control == kSMARTCARD_SetupT0Mode) ||
+           (control == kSMARTCARD_SetupT1Mode));
+
+    uint16_t temp16 = 0u;
+    uint32_t bwiVal = 0u;
+    uint8_t tdt = 0u;
+
+    if (control == kSMARTCARD_SetupATRMode)
+    {
+        /* Disable all functionality at first */
+        base->CTRL &= ~(EMVSIM_CTRL_RCVR_11_MASK | EMVSIM_CTRL_XMT_CRC_LRC_MASK | EMVSIM_CTRL_LRC_EN_MASK |
+                        EMVSIM_CTRL_ANACK_MASK | EMVSIM_CTRL_ONACK_MASK | EMVSIM_CTRL_RCV_EN_MASK);
+        /* Set default values as per EMV specification */
+        context->cardParams.Fi = 372u;
+        context->cardParams.Di = 1u;
+        context->cardParams.currentD = 1u;
+        context->cardParams.WI = 0x0Au;
+        context->cardParams.GTN = 0x00u;
+        /* Set default baudrate/ETU time based on EMV parameters and card clock */
+        base->DIVISOR = ((context->cardParams.Fi / context->cardParams.currentD) & 0x1FFu);
+        /* EMV expectation: WWT = (960 x D x WI) + (D x 480)
+         * EMVSIM formula: BWT_VAL[15:0] = CWT_VAL[15:0] */
+        temp16 = (960u * context->cardParams.currentD * context->cardParams.WI) +
+                 (context->cardParams.currentD * 480u) + SMARTCARD_WWT_ADJUSTMENT;
+        base->CWT_VAL = temp16;
+        base->BWT_VAL = temp16;
+        /* Set Extended Guard Timer value
+         * EMV expectation: GT = GTN not equal to 255 -> 12 + GTN = GTN equal to 255 -> 12
+         * EMVSIM formula: same as above */
+        base->TX_GETU = context->cardParams.GTN;
+        /* Setting Rx threshold so that an interrupt is generated when a NACK is
+           sent either due to parity error or wrong INIT char*/
+        base->RX_THD = EMVSIM_RX_THD_RDT(1);
+        /* Setting up Tx NACK threshold */
+        tdt = ((base->PARAM & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK) >> EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT) - 1;
+        base->TX_THD = (EMVSIM_TX_THD_TNCK_THD(SMARTCARD_EMV_TX_NACK_THRESHOLD) | EMVSIM_TX_THD_TDT(tdt));
+        /* Clear all pending interrupts */
+        base->RX_STATUS = 0xFFFFFFFFu;
+        /* Enable Tx NACK threshold interrupt to occur */
+        base->INT_MASK &= ~EMVSIM_INT_MASK_TNACK_IM_MASK;
+        /* Set transport type to T=0 in SMARTCARD context structure */
+        context->tType = kSMARTCARD_T0Transport;
+    }
+    else if (control == kSMARTCARD_SetupT0Mode)
+    {
+        /* Disable receiver at first if it's not, Disable T=0 mode counters 1st,
+         * Setup for single wire ISO7816 mode (setup 12 etu mode).
+         * Set transport protocol type to T=0, Disable initial character detection.*/
+        base->CTRL &=
+            ~(EMVSIM_CTRL_RCV_EN_MASK | EMVSIM_CTRL_CWT_EN_MASK | EMVSIM_CTRL_BWT_EN_MASK | EMVSIM_CTRL_RCVR_11_MASK |
+              EMVSIM_CTRL_XMT_CRC_LRC_MASK | EMVSIM_CTRL_LRC_EN_MASK | EMVSIM_CTRL_ICM_MASK);
+        /* EMV expectation: WWT = (960 x D x WI) + (D x 480)
+         * EMVSIM formula: BWT_VAL[15:0] = CWT_VAL[15:0]  */
+        temp16 = (960u * context->cardParams.currentD * context->cardParams.WI) +
+                 (context->cardParams.currentD * 480u) + SMARTCARD_WWT_ADJUSTMENT;
+        base->CWT_VAL = temp16;
+        base->BWT_VAL = temp16;
+        /* Set Extended Guard Timer value
+         * EMV expectation: GT = GTN not equal to 255 -> 12 + GTN = GTN equal to 255 -> 12
+         * EMVSIM formula: same as above for range [0:254]
+         * Fix for EMV. If TX_GETU == 0 in T0 mode, 3 stop bits are inserted. */
+        context->cardParams.GTN = (context->cardParams.GTN == 0xFFu) ? 0x00u : context->cardParams.GTN;
+        base->TX_GETU = context->cardParams.GTN;
+        /* Setting Rx threshold so that an interrupt is generated when a NACK is
+        sent either due to parity error or wrong INIT char */
+        base->RX_THD = (EMVSIM_RX_THD_RNCK_THD(SMARTCARD_EMV_RX_NACK_THRESHOLD) | EMVSIM_RX_THD_RDT(1));
+        /* Setting up Tx NACK threshold */
+        tdt = ((base->PARAM & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK) >> EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT) - 1;
+        base->TX_THD = (EMVSIM_TX_THD_TNCK_THD(SMARTCARD_EMV_TX_NACK_THRESHOLD) | EMVSIM_TX_THD_TDT(tdt));
+        /* Enable Tx NACK threshold interrupt to occur */
+        base->INT_MASK &= ~EMVSIM_INT_MASK_TNACK_IM_MASK;
+        /* Enable T=0 mode counters, Enable NACK on error interrupt and NACK on overflow interrupt */
+        base->CTRL |=
+            (EMVSIM_CTRL_CWT_EN_MASK | EMVSIM_CTRL_BWT_EN_MASK | EMVSIM_CTRL_ANACK_MASK | EMVSIM_CTRL_ONACK_MASK);
+        /* Set transport type to T=0 in SMARTCARD context structure */
+        context->tType = kSMARTCARD_T0Transport;
+    }
+    else
+    { /* Disable T=1 mode counters 1st, Disable NACK on error interrupt, Disable NACK on overflow interrupt */
+        base->CTRL &= ~(EMVSIM_CTRL_CWT_EN_MASK | EMVSIM_CTRL_BWT_EN_MASK | EMVSIM_CTRL_ANACK_MASK |
+                       EMVSIM_CTRL_ONACK_MASK | EMVSIM_CTRL_XMT_CRC_LRC_MASK | EMVSIM_CTRL_LRC_EN_MASK);
+        /* Calculate and set Block Wait Timer (BWT) value
+         * EMV expectation: BWT = 11 + (2^BWI x 960 x D) + (D x 960) = 11 + (2^BWI + 1) x 960 x D
+         * EMVSIM formula: BWT = Same */
+        bwiVal = 11 + (((1 << context->cardParams.BWI) + 1u) * 960u * context->cardParams.currentD);
+        base->BWT_VAL = bwiVal;
+        /* Calculate and set Character Wait Timer (CWT) value
+         * EMV expectation: CWT = ((2^CWI + 11) + 4)
+         * EMVSIM formula: CWT = Same */
+        if (context->cardParams.currentD == 1u)
+        {
+            temp16 = (1u << context->cardParams.CWI) + 15u;
+        }
+        else
+        {
+            temp16 = (1u << context->cardParams.CWI) + 15u + SMARTCARD_CWT_ADJUSTMENT;
+        }
+        /* EMV = 15, ISO = 11,
+         * EMV expectation: BGT = 22
+         * EMVSIM formula: BGT = Same */
+        base->CWT_VAL = temp16;
+        context->cardParams.BGI = 22u;
+        base->BGT_VAL = context->cardParams.BGI;
+        /* Set Extended Guard Timer value
+         * EMV expectation: GT = GTN not equal to 255 -> 12 + GTN = GTN equal to 255 -> 11
+         * EMVSIM formula: same as above */
+        base->TX_GETU = context->cardParams.GTN;
+        /* Setup for single wire ISO7816 mode,
+         * Set transport protocol type to T=1, Enable T=0 mode counters */
+        base->CTRL |= (EMVSIM_CTRL_RCVR_11_MASK | EMVSIM_CTRL_CWT_EN_MASK | EMVSIM_CTRL_BWT_EN_MASK);
+        /* Setting Rx threshold */
+        base->RX_THD = (EMVSIM_RX_THD_RNCK_THD(SMARTCARD_EMV_RX_NACK_THRESHOLD) | EMVSIM_RX_THD_RDT(1));
+        /* Setting up Tx threshold */
+        tdt = ((base->PARAM & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK) >> EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT) - 1;
+        base->TX_THD = (EMVSIM_TX_THD_TDT(tdt) | EMVSIM_TX_THD_TNCK_THD(SMARTCARD_EMV_TX_NACK_THRESHOLD));
+        /* Set transport type to T=1 in SMARTCARD context structure */
+        context->tType = kSMARTCARD_T1Transport;
+    }
+}
+
+void SMARTCARD_EMVSIM_GetDefaultConfig(smartcard_card_params_t *cardParams)
+{
+    /* EMV default values */
+    cardParams->Fi = 372u;
+    cardParams->Di = 1u;
+    cardParams->currentD = 1u;
+    cardParams->WI = 0x0Au;
+    cardParams->GTN = 0x00u;
+}
+
+status_t SMARTCARD_EMVSIM_Init(EMVSIM_Type *base, smartcard_context_t *context, uint32_t srcClock_Hz)
+{
+    assert((NULL != base));
+
+    if ((NULL == context) || (srcClock_Hz == 0u))
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+
+    uint32_t instance = smartcard_emvsim_GetInstance(base);
+/* Set source clock for EMVSIM MCGPLLCLK */
+#if !(defined(FSL_FEATURE_SOC_SCG_COUNT) && FSL_FEATURE_SOC_SCG_COUNT)
+    CLOCK_SetEmvsimClock(1u);
+#endif
+    /* Enable emvsim clock */
+    CLOCK_EnableClock(s_emvsimClock[instance]);
+    context->base = base;
+    /* Initialize EMVSIM to a known context. */
+    base->CLKCFG = 0u;
+    base->DIVISOR = 372u;
+    base->CTRL = 0x300u;
+    base->INT_MASK = 0x7FFFu;
+    base->RX_THD = 1u;
+    base->TX_THD = 0u;
+    base->PCSR = 0x1000000u;
+    base->TX_GETU = 0u;
+    base->CWT_VAL = 0xFFFFu;
+    base->BWT_VAL = 0xFFFFFFFFu;
+    base->BGT_VAL = 0u;
+    base->GPCNT0_VAL = 0xFFFFu;
+    base->GPCNT1_VAL = 0xFFFFu;
+    /* Initialize EMVSIM module for SMARTCARD mode of default operation */
+    smartcard_emvsim_SetTransferType(base, context, kSMARTCARD_SetupATRMode);
+    /* For modules that do not support a FIFO, they have a data buffer that
+     * essentially acts likes a one-entry FIFO, thus to make the code cleaner,
+     * we'll equate txFifoEntryCount to 1. Also note that TDRE flag will set
+     * only when the tx buffer is empty. */
+    context->txFifoEntryCount = 1u;
+/* Enable EMVSIM interrupt on NVIC level. */
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && FSL_FEATURE_SOC_INTMUX_COUNT
+    if (s_emvsimIRQ[instance] >= FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+    {
+        INTMUX0->CHANNEL[0].CHn_IER_31_0 |= 1U << (s_emvsimIRQ[instance] - FSL_FEATURE_INTERRUPT_IRQ_MAX - 1U);
+        NVIC_EnableIRQ(INTMUX0_0_IRQn);
+    }
+    else
+    {
+        NVIC_EnableIRQ(s_emvsimIRQ[instance]);
+    }
+#else
+    NVIC_EnableIRQ(s_emvsimIRQ[instance]);
+#endif
+    /* Finally, disable the EMVSIM receiver and transmitter */
+    base->CTRL &= ~EMVSIM_CTRL_XMT_EN_MASK & ~EMVSIM_CTRL_RCV_EN_MASK;
+
+    return kStatus_SMARTCARD_Success;
+}
+
+void SMARTCARD_EMVSIM_Deinit(EMVSIM_Type *base)
+{
+    uint32_t instance = 0u;
+    /* In case there is still data in the TX FIFO or shift register that is
+     * being transmitted wait till transmit is complete.
+     * Wait until the data is completely shifted out of shift register */
+    while ((!(base->TX_STATUS & EMVSIM_TX_STATUS_TCF_MASK)))
+    {
+    }
+    instance = smartcard_emvsim_GetInstance(base);
+    /* Disable TX and RX */
+    base->CTRL &= ~EMVSIM_CTRL_XMT_EN_MASK & ~EMVSIM_CTRL_RCV_EN_MASK;
+    /* Gate EMVSIM module clock */
+    CLOCK_DisableClock(s_emvsimClock[instance]);
+/* Disable emvsim interrupt in NVIC */
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && FSL_FEATURE_SOC_INTMUX_COUNT
+    if (s_emvsimIRQ[instance] >= FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+    {
+        INTMUX0->CHANNEL[0].CHn_IER_31_0 &= ~(1U << (s_emvsimIRQ[instance] - FSL_FEATURE_INTERRUPT_IRQ_MAX - 1U));
+        NVIC_DisableIRQ(INTMUX0_0_IRQn);
+    }
+    else
+    {
+        NVIC_DisableIRQ(s_emvsimIRQ[instance]);
+    }
+#else
+    NVIC_DisableIRQ(s_emvsimIRQ[instance]);
+#endif
+}
+
+status_t SMARTCARD_EMVSIM_TransferNonBlocking(EMVSIM_Type *base, smartcard_context_t *context, smartcard_xfer_t *xfer)
+{
+    if ((NULL == context) || (NULL == xfer) || (xfer->buff == NULL))
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+
+    /* Check input parameters */
+    if ((0u == xfer->size))
+    {
+        return kStatus_SMARTCARD_Success;
+    }
+    /* Check if some transfer is in progress */
+    if (0u != SMARTCARD_EMVSIM_GetTransferRemainingBytes(base, context))
+    {
+        if (kSMARTCARD_Receive == context->direction)
+        {
+            return kStatus_SMARTCARD_RxBusy;
+        }
+        else
+        {
+            return kStatus_SMARTCARD_TxBusy;
+        }
+    }
+    /* Initialize error check flags */
+    context->rxtCrossed = false;
+    context->txtCrossed = false;
+    context->parityError = false;
+    /* Initialize SMARTCARD context structure to start transfer */
+    context->xBuff = xfer->buff;
+    context->xSize = xfer->size;
+
+    if (kSMARTCARD_Receive == xfer->direction)
+    {
+        context->direction = xfer->direction;
+        context->transferState = kSMARTCARD_ReceivingState;
+        /* Start transfer */
+        smartcard_emvsim_StartReceiveData(base, context);
+    }
+    else if (kSMARTCARD_Transmit == xfer->direction)
+    {
+        context->direction = xfer->direction;
+        context->transferState = kSMARTCARD_TransmittingState;
+        /* Start transfer */
+        smartcard_emvsim_StartSendData(base, context);
+    }
+    else
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+
+    return kStatus_SMARTCARD_Success;
+}
+
+int32_t SMARTCARD_EMVSIM_GetTransferRemainingBytes(EMVSIM_Type *base, smartcard_context_t *context)
+{
+    if ((NULL == context))
+    {
+        return -1;
+    }
+
+    /* Return kStatus_SMARTCARD_(Tx/Rx)Busy or kStatus_SMARTCARD_Success depending on whether
+    * or not the EMVSIM has a FIFO. If TX transfer and it does have a FIFO, we'll need to wait
+    * until the FIFO is completely drained before indicating success in addition to xIsBusy = 0.
+    * If there is no FIFO, then we need to only worry about xIsBusy. */
+    if (context->xIsBusy)
+    {
+        return context->xSize;
+    }
+
+    return 0;
+}
+
+status_t SMARTCARD_EMVSIM_AbortTransfer(EMVSIM_Type *base, smartcard_context_t *context)
+{
+    if ((NULL == context))
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+
+    /* Check if a transfer is running. */
+    if ((!context->xIsBusy))
+    {
+        return kStatus_SMARTCARD_NoTransferInProgress;
+    }
+    /* Call transfer complete to abort transfer */
+    if (kSMARTCARD_Receive == context->direction)
+    { /* Stop the running transfer. */
+        smartcard_emvsim_CompleteReceiveData(base, context);
+    }
+    else if (kSMARTCARD_Transmit == context->direction)
+    { /* Stop the running transfer. */
+        smartcard_emvsim_CompleteSendData(base, context);
+    }
+    else
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+
+    return kStatus_SMARTCARD_Success;
+}
+
+void SMARTCARD_EMVSIM_IRQHandler(EMVSIM_Type *base, smartcard_context_t *context)
+{
+    uint8_t temp8 = 0u;
+
+    if (NULL == context)
+    {
+        return;
+    }
+
+    /* Check card insertion/removal interrupt occurs, only EMVSIM DIRECT interface driver using enables this interrupt
+     * to occur */
+    if ((!(base->PCSR & EMVSIM_PCSR_SPDIM_MASK)) && (base->PCSR & EMVSIM_PCSR_SPDIF_MASK))
+    {
+        /* Clear card presence interrupt status */
+        base->PCSR |= EMVSIM_PCSR_SPDIF_MASK;
+        /* Set PD signal edge behaviour */
+        if (((emvsim_presence_detect_edge_t)((base->PCSR & EMVSIM_PCSR_SPDES_MASK) >> EMVSIM_PCSR_SPDES_SHIFT) ==
+             kEMVSIM_DetectOnFallingEdge) &&
+            ((emvsim_presence_detect_status_t)((base->PCSR & EMVSIM_PCSR_SPDP_MASK) >> EMVSIM_PCSR_SPDP_SHIFT) ==
+             kEMVSIM_DetectPinIsLow))
+        { /* Set rising edge interrupt */
+            base->PCSR |= EMVSIM_PCSR_SPDES_MASK;
+        }
+        if (((emvsim_presence_detect_edge_t)((base->PCSR & EMVSIM_PCSR_SPDES_MASK) >> EMVSIM_PCSR_SPDES_SHIFT) ==
+             kEMVSIM_DetectOnRisingEdge) &&
+            ((emvsim_presence_detect_status_t)((base->PCSR & EMVSIM_PCSR_SPDP_MASK) >> EMVSIM_PCSR_SPDP_SHIFT) ==
+             kEMVSIM_DetectPinIsHigh))
+        { /* Set falling edge interrupt */
+            base->PCSR &= ~EMVSIM_PCSR_SPDES_MASK;
+        }
+        /* Card presence(insertion)/removal detected */
+        /* Invoke callback if there is one */
+        if (NULL != context->interfaceCallback)
+        {
+            context->interfaceCallback(context, context->interfaceCallbackParam);
+        }
+        return;
+    }
+    /* Check if timer for initial character (TS) detection has expired */
+    if (((base->INT_MASK & EMVSIM_INT_MASK_GPCNT0_IM_MASK) >> EMVSIM_INT_MASK_GPCNT0_IM_SHIFT == 0) &&
+        (base->TX_STATUS & EMVSIM_TX_STATUS_GPCNT0_TO_MASK))
+    {
+        /* Disable TS and ADT timers by clearing source clock to 0 */
+        base->CLKCFG &= ~(EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK | EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK);
+        context->timersState.initCharTimerExpired = true;
+        /* Disable and clear GPCNT interrupt */
+        base->INT_MASK |= EMVSIM_INT_MASK_GPCNT0_IM_MASK;
+        base->TX_STATUS = EMVSIM_TX_STATUS_GPCNT0_TO_MASK;
+        /* Down counter trigger, and clear any pending counter status flag */
+        base->CTRL &= ~EMVSIM_CTRL_RCV_EN_MASK;
+        base->CTRL |= EMVSIM_CTRL_RCV_EN_MASK;
+        context->transferState = kSMARTCARD_IdleState;
+        /* Unblock the caller */
+        smartcard_emvsim_CompleteReceiveData(base, context);
+        return;
+    }
+    /* Check if timer for ATR duration timer has expired */
+    if ((!(base->INT_MASK & EMVSIM_INT_MASK_GPCNT1_IM_MASK)) && (base->TX_STATUS & EMVSIM_TX_STATUS_GPCNT1_TO_MASK))
+    { /* Disable clock counter by clearing source clock to 0 */
+        base->CLKCFG &= ~EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK;
+        /* Disable and clear GPCNT interrupt */
+        base->INT_MASK |= EMVSIM_INT_MASK_GPCNT1_IM_MASK;
+        base->TX_STATUS = EMVSIM_TX_STATUS_GPCNT1_TO_MASK;
+        context->timersState.adtExpired = true;
+        /* Unblock the caller */
+        smartcard_emvsim_CompleteReceiveData(base, context);
+        return;
+    }
+    /*
+    * Check if a parity error was indicated.
+    * A parity error will cause transmission of NACK if ANACK bit is set in
+    * CTRL register and PEF bit will not be asserted. When ANACK is not set,
+    * PEF will be asserted.
+    */
+    if (base->RX_STATUS & EMVSIM_RX_STATUS_PEF_MASK)
+    {
+        context->parityError = true;
+        /* Clear parity error indication */
+        base->RX_STATUS = EMVSIM_RX_STATUS_PEF_MASK;
+    }
+    /* Check if transmit NACK generation threshold was reached */
+    if ((base->TX_STATUS & EMVSIM_TX_STATUS_TNTE_MASK))
+    {
+        context->txtCrossed = true;
+    }
+    /* Check if receive NACK generation threshold was reached */
+    if (base->RX_STATUS & EMVSIM_RX_STATUS_RTE_MASK)
+    {
+        context->rxtCrossed = true;
+        /* Clear receiver NACK threshold interrupt status */
+        base->RX_STATUS = EMVSIM_RX_STATUS_RTE_MASK;
+        if (context->xIsBusy)
+        { /* Unblock the caller */
+            smartcard_emvsim_CompleteReceiveData(base, context);
+        }
+    }
+    /* Check if a Character Wait Timer expired */
+    if ((!(base->INT_MASK & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)) && (base->RX_STATUS & EMVSIM_RX_STATUS_CWT_ERR_MASK))
+    { /* Disable Character Wait Timer interrupt */
+        base->INT_MASK |= EMVSIM_INT_MASK_CWT_ERR_IM_MASK;
+        /* Reset the counter */
+        base->CTRL &= ~EMVSIM_CTRL_CWT_EN_MASK;
+        /* Clear interrupt status */
+        base->RX_STATUS = EMVSIM_RX_STATUS_CWT_ERR_MASK;
+        /* Enable CWT timer */
+        base->CTRL |= EMVSIM_CTRL_CWT_EN_MASK;
+        context->transferState = kSMARTCARD_IdleState;
+
+        if (kSMARTCARD_T0Transport == context->tType)
+        { /* Indicate WWT expired */
+            context->timersState.wwtExpired = true;
+        }
+        else
+        { /* Indicate CWT expired */
+            context->timersState.cwtExpired = true;
+        }
+        if (context->xIsBusy)
+        { /* Terminate and unblock any caller */
+            smartcard_emvsim_CompleteReceiveData(base, context);
+        }
+    }
+    /* Check if a Block Wait Timer expired */
+    if ((!(base->INT_MASK & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)) && (base->RX_STATUS & EMVSIM_RX_STATUS_BWT_ERR_MASK))
+    { /* Disable Block Wait Timer interrupt */
+        base->INT_MASK |= EMVSIM_INT_MASK_BWT_ERR_IM_MASK;
+        /* Clear interrupt status flag */
+        base->CTRL &= ~EMVSIM_CTRL_BWT_EN_MASK;
+        /* Clear error */
+        base->RX_STATUS = EMVSIM_RX_STATUS_BWT_ERR_MASK;
+        /* Enable BWT timer */
+        base->CTRL |= EMVSIM_CTRL_BWT_EN_MASK;
+
+        if (kSMARTCARD_T0Transport == context->tType)
+        { /* Indicate WWT expired */
+            context->timersState.wwtExpired = true;
+        }
+        else
+        { /* Indicate BWT expired */
+            context->timersState.bwtExpired = true;
+        }
+        /* Check if Wait Time Extension(WTX) was requested */
+        if (context->wtxRequested)
+        { /* Reset WTX to default */
+            SMARTCARD_EMVSIM_Control(base, context, kSMARTCARD_ResetWaitTimeMultiplier, 1);
+        }
+        if (context->xIsBusy)
+        { /* Terminate and unblock any caller */
+            smartcard_emvsim_CompleteReceiveData(base, context);
+        }
+    }
+    /* Handle receive data register full interrupt, if rx data register full
+    * interrupt is enabled AND there is data available. */
+    if ((!(base->INT_MASK & EMVSIM_INT_MASK_RX_DATA_IM_MASK)) && (base->RX_STATUS & EMVSIM_RX_STATUS_RX_DATA_MASK))
+    {
+        if (kSMARTCARD_WaitingForTSState == context->transferState)
+        {
+            temp8 = (uint8_t)(base->RX_BUF);
+
+            if (base->CTRL & EMVSIM_CTRL_ICM_MASK)
+            { /* ICM mode still enabled, this is due to parity error */
+                context->transferState = kSMARTCARD_InvalidTSDetecetedState;
+            }
+            else
+            { /* Received valid TS */
+                context->transferState = kSMARTCARD_ReceivingState;
+                /* Get Data Convention form by reading IC bit of EMVSIM_CTRL register */
+                context->cardParams.convention =
+                    (smartcard_card_convention_t)((base->CTRL & EMVSIM_CTRL_IC_MASK) >> EMVSIM_CTRL_IC_SHIFT);
+            }
+            if (kSMARTCARD_InvalidTSDetecetedState == context->transferState)
+            { /* Stop initial character (TS) detection timer, ADT timer and it's interrupt to occur */
+                base->CLKCFG &= ~(EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK | EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK);
+                base->INT_MASK |= EMVSIM_INT_MASK_GPCNT0_IM_MASK;
+                smartcard_emvsim_CompleteReceiveData(base, context);
+            }
+            if (kSMARTCARD_ReceivingState == context->transferState)
+            { /* Stop initial character (TS) detection timer and disable ATR duration timer to reset it */
+                base->CLKCFG &= ~(EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK | EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK);
+                /* Start ATR duration counter (restart GPCNT) */
+                base->CLKCFG |= EMVSIM_CLKCFG_GPCNT1_CLK_SEL(kEMVSIM_GPCTxClock);
+                /* Start ATR duration counter, Disable counter 0 interrupt and Enable counter 1 interrupt */
+                base->INT_MASK = (base->INT_MASK & ~EMVSIM_INT_MASK_GPCNT1_IM_MASK) | EMVSIM_INT_MASK_GPCNT0_IM_MASK;
+                /* Complete receive transfer */
+                smartcard_emvsim_CompleteReceiveData(base, context);
+            }
+            /* Return anyway */
+            return;
+        }
+        /* Get data and put into receive buffer */
+        *context->xBuff = (uint8_t)(base->RX_BUF);
+        /* Clear received data interrupt status */
+        base->RX_STATUS = EMVSIM_RX_STATUS_RX_DATA_MASK;
+
+        ++context->xBuff;
+        --context->xSize;
+
+        if ((context->tType == kSMARTCARD_T1Transport) && (context->xSize > 0u) &&
+            (!(base->INT_MASK & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)))
+        {
+            /* And, enable CWT interrupt */
+            context->timersState.cwtExpired = false;
+            /* Clear interrupt status */
+            base->RX_STATUS = EMVSIM_RX_STATUS_CWT_ERR_MASK;
+            base->CTRL |= EMVSIM_CTRL_CWT_EN_MASK;
+            /* Only the 1st byte has been received, now time to disable BWT interrupt */
+            base->INT_MASK = (base->INT_MASK & ~EMVSIM_INT_MASK_CWT_ERR_IM_MASK) | EMVSIM_INT_MASK_BWT_ERR_IM_MASK;
+        }
+        /* Check and see if this was the last byte received */
+        if (0u == context->xSize)
+        {
+            smartcard_emvsim_CompleteReceiveData(base, context);
+        }
+    }
+    /* Handle transmit data register empty interrupt and
+     * last data was shifted out of IO line */
+    if ((!(base->INT_MASK & EMVSIM_INT_MASK_TC_IM_MASK)) &&
+        (base->TX_STATUS & (EMVSIM_TX_STATUS_TFE_MASK | EMVSIM_TX_STATUS_TCF_MASK)))
+    {
+        if (context->txtCrossed)
+        { /* Disable and Clear TNTE interrupt */
+            base->INT_MASK |= EMVSIM_INT_MASK_TNACK_IM_MASK;
+            base->TX_STATUS = EMVSIM_TX_STATUS_TNTE_MASK;
+            /* Unblock the caller */
+            smartcard_emvsim_CompleteSendData(base, context);
+            return;
+        }
+        /* Check to see if there are any more bytes to send */
+        if (context->xSize > 0u)
+        {
+            temp8 = context->txFifoEntryCount;
+
+            while (temp8--)
+            {
+                /* Transmit data and update TX size/buff */
+                base->TX_BUF = *(context->xBuff);
+                /* Clear TCF interrupt */
+                base->TX_STATUS = EMVSIM_TX_STATUS_TCF_MASK;
+                /* Move buffer pointer and transfer data size */
+                ++context->xBuff;
+                --context->xSize;
+
+                if (!context->xSize)
+                {
+                    smartcard_emvsim_CompleteSendData(base, context);
+                    break;
+                }
+            }
+        }
+    }
+}
+
+status_t SMARTCARD_EMVSIM_Control(EMVSIM_Type *base,
+                                  smartcard_context_t *context,
+                                  smartcard_control_t control,
+                                  uint32_t param)
+{
+    if ((NULL == context))
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+
+    uint32_t temp32 = 0u;
+
+    switch (control)
+    {
+        case kSMARTCARD_EnableADT:
+            /* Do nothing, ADT counter has been loaded and started after reset
+             * and during starting TS delay counter only. This is because, once
+             * TS counter has been triggered with RCV_EN down-up, we should not
+             * trigger again after TS is received(to avoid missing next character to
+             * TS. Rather, after TS is received, the ATR duration counter should just
+             * be restarted w/o re-triggering the counter. */
+            break;
+        case kSMARTCARD_DisableADT:
+            base->CTRL &= ~EMVSIM_CTRL_RCV_EN_MASK;
+            /* Stop ADT specific counter and it's interrupt to occur */
+            base->CLKCFG &= ~EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK;
+            base->TX_STATUS = EMVSIM_TX_STATUS_GPCNT1_TO_MASK;
+            base->INT_MASK |= EMVSIM_INT_MASK_GPCNT1_IM_MASK;
+            break;
+        case kSMARTCARD_EnableGTV:
+            /* Enable GTV specific interrupt */
+            base->INT_MASK &= ~EMVSIM_INT_MASK_BGT_ERR_IM_MASK;
+            break;
+        case kSMARTCARD_DisableGTV:
+            /* Disable GTV specific interrupt */
+            base->INT_MASK |= EMVSIM_INT_MASK_BGT_ERR_IM_MASK;
+            break;
+        case kSMARTCARD_ResetWWT:
+            /* Reset WWT Timer */
+            base->CTRL &= ~(EMVSIM_CTRL_CWT_EN_MASK | EMVSIM_CTRL_BWT_EN_MASK);
+            base->CTRL |= (EMVSIM_CTRL_CWT_EN_MASK | EMVSIM_CTRL_BWT_EN_MASK);
+            break;
+        case kSMARTCARD_EnableWWT:
+            /* BGT must be masked */
+            base->INT_MASK |= EMVSIM_INT_MASK_BGT_ERR_IM_MASK;
+            /* Enable WWT Timer interrupt to occur */
+            base->INT_MASK &= (~EMVSIM_INT_MASK_CWT_ERR_IM_MASK & ~EMVSIM_INT_MASK_BWT_ERR_IM_MASK);
+            break;
+        case kSMARTCARD_DisableWWT:
+            /* Disable WWT Timer interrupt to occur */
+            base->INT_MASK |= (EMVSIM_INT_MASK_CWT_ERR_IM_MASK | EMVSIM_INT_MASK_BWT_ERR_IM_MASK);
+            break;
+        case kSMARTCARD_ResetCWT:
+            /* Reset CWT Timer */
+            base->CTRL &= ~EMVSIM_CTRL_CWT_EN_MASK;
+            base->CTRL |= EMVSIM_CTRL_CWT_EN_MASK;
+            break;
+        case kSMARTCARD_EnableCWT:
+            base->CTRL |= EMVSIM_CTRL_CWT_EN_MASK;
+            /* Enable CWT Timer interrupt to occur */
+            base->INT_MASK &= ~EMVSIM_INT_MASK_CWT_ERR_IM_MASK;
+            break;
+        case kSMARTCARD_DisableCWT:
+            /* CWT counter is for receive mode only */
+            base->CTRL &= ~EMVSIM_CTRL_CWT_EN_MASK;
+            /* Disable CWT Timer interrupt to occur */
+            base->INT_MASK |= EMVSIM_INT_MASK_CWT_ERR_IM_MASK;
+            break;
+        case kSMARTCARD_ResetBWT:
+            /* Reset BWT Timer */
+            base->CTRL &= ~EMVSIM_CTRL_BWT_EN_MASK;
+            base->CTRL |= EMVSIM_CTRL_BWT_EN_MASK;
+            break;
+        case kSMARTCARD_EnableBWT:
+            base->CTRL |= EMVSIM_CTRL_BWT_EN_MASK;
+            /* Enable BWT Timer interrupt to occur */
+            base->INT_MASK &= ~EMVSIM_INT_MASK_BWT_ERR_IM_MASK;
+            break;
+        case kSMARTCARD_DisableBWT:
+            /* Disable BWT Timer interrupt to occur */
+            base->INT_MASK |= EMVSIM_INT_MASK_BWT_ERR_IM_MASK;
+            break;
+        case kSMARTCARD_EnableInitDetect:
+            /* Clear all ISO7816 interrupt flags */
+            base->RX_STATUS = 0xFFFFFFFFu;
+            /* Enable initial character detection : hardware method */
+            context->transferState = kSMARTCARD_WaitingForTSState;
+            /* Enable initial character detection */
+            base->CTRL |= EMVSIM_CTRL_ICM_MASK;
+            base->CTRL |= EMVSIM_CTRL_RCV_EN_MASK;
+            break;
+        case kSMARTCARD_EnableAnack:
+            /* Enable NACK-on-error interrupt to occur */
+            base->CTRL |= EMVSIM_CTRL_ANACK_MASK;
+            break;
+        case kSMARTCARD_DisableAnack:
+            /* Disable NACK-on-error interrupt to occur */
+            base->CTRL &= ~EMVSIM_CTRL_ANACK_MASK;
+            break;
+        case kSMARTCARD_ConfigureBaudrate:
+            /* Set default baudrate/ETU time based on EMV parameters and card clock */
+            base->DIVISOR = ((context->cardParams.Fi / context->cardParams.currentD) & 0x1FFu);
+            break;
+        case kSMARTCARD_SetupATRMode:
+            /* Set in default ATR mode */
+            smartcard_emvsim_SetTransferType(base, context, kSMARTCARD_SetupATRMode);
+            break;
+        case kSMARTCARD_SetupT0Mode:
+            /* Set transport protocol type to T=0 */
+            smartcard_emvsim_SetTransferType(base, context, kSMARTCARD_SetupT0Mode);
+            break;
+        case kSMARTCARD_SetupT1Mode:
+            /* Set transport protocol type to T=1 */
+            smartcard_emvsim_SetTransferType(base, context, kSMARTCARD_SetupT1Mode);
+            break;
+        case kSMARTCARD_EnableReceiverMode:
+            /* Enable receiver mode and switch to receive direction */
+            base->CTRL |= EMVSIM_CTRL_RCV_EN_MASK;
+            /* Enable RX_DATA interrupt */
+            base->INT_MASK &= ~EMVSIM_INT_MASK_RX_DATA_IM_MASK;
+            break;
+        case kSMARTCARD_DisableReceiverMode:
+            /* Disable receiver */
+            base->CTRL &= ~EMVSIM_CTRL_RCV_EN_MASK;
+            break;
+        case kSMARTCARD_EnableTransmitterMode:
+            /* Enable transmitter mode and switch to transmit direction */
+            base->CTRL |= EMVSIM_CTRL_XMT_EN_MASK;
+            break;
+        case kSMARTCARD_DisableTransmitterMode:
+            /* Disable transmitter */
+            base->CTRL &= ~EMVSIM_CTRL_XMT_EN_MASK;
+            break;
+        case kSMARTCARD_ResetWaitTimeMultiplier:
+            base->CTRL &= ~EMVSIM_CTRL_BWT_EN_MASK;
+            /* Reset Wait Timer Multiplier
+            * EMV Formula : WTX x (11 + ((2^BWI + 1) x 960 x D)) */
+            temp32 = ((uint8_t)param) *
+                     (11u + (((1 << context->cardParams.BWI) + 1u) * 960u * context->cardParams.currentD));
+            base->BWT_VAL = temp32;
+            /* Set flag to SMARTCARD context accordingly */
+            if (param > 1u)
+            {
+                context->wtxRequested = true;
+            }
+            else
+            {
+                context->wtxRequested = false;
+            }
+            base->CTRL |= EMVSIM_CTRL_BWT_EN_MASK;
+            break;
+        default:
+            return kStatus_SMARTCARD_InvalidInput;
+    }
+    return kStatus_SMARTCARD_Success;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_emvsim.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_emvsim.h
new file mode 100644
index 00000000000..92878e37d73
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_emvsim.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_SMARTCARD_EMVSIM_H_
+#define _FSL_SMARTCARD_EMVSIM_H_
+
+#include "fsl_smartcard.h"
+
+/*!
+ * @addtogroup smartcard_emvsim_driver
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief EMV RX NACK interrupt generation threshold */
+#define SMARTCARD_EMV_RX_NACK_THRESHOLD (5u)
+
+/*! @brief EMV TX NACK interrupt generation threshold */
+#define SMARTCARD_EMV_TX_NACK_THRESHOLD (5u)
+
+/*! @brief Smart card Word Wait Timer adjustment value */
+#define SMARTCARD_WWT_ADJUSTMENT (160u)
+
+/*! @brief Smart card Character Wait Timer adjustment value */
+#define SMARTCARD_CWT_ADJUSTMENT (3u)
+
+/*! @brief General Purpose Counter clock selections */
+typedef enum _emvsim_gpc_clock_select
+{
+    kEMVSIM_GPCClockDisable = 0u, /*!< disabled */
+    kEMVSIM_GPCCardClock = 1u,    /*!< card clock */
+    kEMVSIM_GPCRxClock = 2u,      /*!< receive clock */
+    kEMVSIM_GPCTxClock = 3u,      /*!< transmit ETU clock */
+} emvsim_gpc_clock_select_t;
+
+/*! @brief EMVSIM card presence detection edge control */
+typedef enum _presence_detect_edge
+{
+    kEMVSIM_DetectOnFallingEdge = 0u, /*!< presence detect on falling edge */
+    kEMVSIM_DetectOnRisingEdge = 1u,  /*!< presence detect on rising edge */
+} emvsim_presence_detect_edge_t;
+
+/*! @brief EMVSIM card presence detection status */
+typedef enum _presence_detect_status
+{
+    kEMVSIM_DetectPinIsLow = 0u,  /*!< presence detect pin is logic low */
+    kEMVSIM_DetectPinIsHigh = 1u, /*!< presence detect pin is logic high */
+} emvsim_presence_detect_status_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Smart card EMVSIM Driver
+ * @{
+ */
+
+/*!
+ * @brief Fill in smartcard_card_params structure with default values according EMV 4.3 specification.
+ *
+ * @param cardParams The configuration structure of type smartcard_interface_config_t.
+ * Function fill in members:
+ *        Fi = 372;
+ *        Di = 1;
+ *        currentD = 1;
+ *        WI = 0x0A;
+ *        GTN = 0x00;
+ * with default values.
+ */
+void SMARTCARD_EMVSIM_GetDefaultConfig(smartcard_card_params_t *cardParams);
+
+/*!
+ * @brief Initializes an EMVSIM peripheral for smart card/ISO-7816 operation.
+ *
+ * This function Un-gate EMVSIM clock, initializes the module to EMV default settings,
+ * configures the IRQ, enables the module-level interrupt to the core and initialize driver context.
+ *
+ * @param base The EMVSIM peripheral base address.
+ * @param context A pointer to a smart card driver context structure.
+ * @param srcClock_Hz Smart card clock generation module source clock.
+ *
+ * @return An error code or kStatus_SMARTCARD_Success.
+ */
+status_t SMARTCARD_EMVSIM_Init(EMVSIM_Type *base, smartcard_context_t *context, uint32_t srcClock_Hz);
+
+/*!
+ * @brief This function disables the EMVSIM interrupts, disables the transmitter and receiver,
+ * flushes the FIFOs and gates EMVSIM clock in SIM.
+ *
+ * @param base The EMVSIM module base address.
+ */
+void SMARTCARD_EMVSIM_Deinit(EMVSIM_Type *base);
+
+/*!
+ * @brief Returns whether the previous EMVSIM transfer has finished.
+ *
+ * When performing an async transfer, call this function to ascertain the context of the
+ * current transfer: in progress (or busy) or complete (success). If the
+ * transfer is still in progress, the user can obtain the number of words that have not been
+ * transferred.
+ *
+ * @param base The EMVSIM module base address.
+ * @param context A pointer to a smart card driver context structure.
+ *
+ * @return The number of bytes not transferred.
+ */
+int32_t SMARTCARD_EMVSIM_GetTransferRemainingBytes(EMVSIM_Type *base, smartcard_context_t *context);
+
+/*!
+ * @brief Terminates an asynchronous EMVSIM transfer early.
+ *
+ * During an async EMVSIM transfer, the user can terminate the transfer early
+ * if the transfer is still in progress.
+ *
+ * @param base The EMVSIM peripheral address.
+ * @param context A pointer to a smart card driver context structure.
+ * @retval kStatus_SMARTCARD_Success The transmit abort was successful.
+ * @retval kStatus_SMARTCARD_NoTransmitInProgress No transmission is currently in progress.
+ */
+status_t SMARTCARD_EMVSIM_AbortTransfer(EMVSIM_Type *base, smartcard_context_t *context);
+
+/*!
+ * @brief Transfer data using interrupts.
+ *
+ * A non-blocking (also known as asynchronous) function means that the function returns
+ * immediately after initiating the transfer function. The application has to get the
+ * transfer status to see when the transfer is complete. In other words, after calling non-blocking
+ * (asynchronous) transfer function, the application must get the transfer status to check if transmit
+ * is completed or not.
+ *
+ * @param base The EMVSIM peripheral base address.
+ * @param context A pointer to a smart card driver context structure.
+ * @param xfer A pointer to smart card transfer structure where are linked buffers and sizes.
+ *
+ * @return An error code or kStatus_SMARTCARD_Success.
+ */
+status_t SMARTCARD_EMVSIM_TransferNonBlocking(EMVSIM_Type *base, smartcard_context_t *context, smartcard_xfer_t *xfer);
+
+/*!
+ * @brief Controls EMVSIM module as per different user request.
+ *
+ * @param base The EMVSIM peripheral base address.
+ * @param context A pointer to a smart card driver context structure.
+ * @param control Control type
+ * @param param Integer value of specific to control command.
+ *
+ * return kStatus_SMARTCARD_Success in success.
+ * return kStatus_SMARTCARD_OtherError in case of error.
+ */
+status_t SMARTCARD_EMVSIM_Control(EMVSIM_Type *base,
+                                  smartcard_context_t *context,
+                                  smartcard_control_t control,
+                                  uint32_t param);
+
+/*!
+ * @brief Handles EMVSIM module interrupts.
+ *
+ * @param base The EMVSIM peripheral base address.
+ * @param context A pointer to a smart card driver context structure.
+ */
+void SMARTCARD_EMVSIM_IRQHandler(EMVSIM_Type *base, smartcard_context_t *context);
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_SMARTCARD_EMVSIM_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_emvsim.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_emvsim.c
new file mode 100644
index 00000000000..55ac6483ee5
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_emvsim.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_smartcard_emvsim.h"
+#include "fsl_smartcard_phy_emvsim.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+static uint32_t smartcard_phy_emvsim_InterfaceClockInit(EMVSIM_Type *base,
+                                                        const smartcard_interface_config_t *config,
+                                                        uint32_t srcClock_Hz);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief This function initializes clock module used for card clock generation
+ */
+static uint32_t smartcard_phy_emvsim_InterfaceClockInit(EMVSIM_Type *base,
+                                                        const smartcard_interface_config_t *config,
+                                                        uint32_t srcClock_Hz)
+{
+    assert((NULL != config) && (0u != srcClock_Hz));
+
+    uint32_t emvsimClkMhz = 0u;
+    uint8_t emvsimPRSCValue;
+
+    /* Retrieve EMV SIM clock */
+    emvsimClkMhz = srcClock_Hz / 1000000u;
+    /* Calculate MOD value */
+    emvsimPRSCValue = (emvsimClkMhz * 1000u) / (config->smartCardClock / 1000u);
+    /* Set clock prescaler */
+    base->CLKCFG = (base->CLKCFG & ~EMVSIM_CLKCFG_CLK_PRSC_MASK) | EMVSIM_CLKCFG_CLK_PRSC(emvsimPRSCValue);
+
+    return config->smartCardClock;
+}
+
+void SMARTCARD_PHY_EMVSIM_GetDefaultConfig(smartcard_interface_config_t *config)
+{
+    assert((NULL != config));
+
+    config->clockToResetDelay = SMARTCARD_INIT_DELAY_CLOCK_CYCLES;
+    config->vcc = kSMARTCARD_VoltageClassB3_3V;
+}
+
+status_t SMARTCARD_PHY_EMVSIM_Init(EMVSIM_Type *base, smartcard_interface_config_t const *config, uint32_t srcClock_Hz)
+{
+    if ((NULL == config) || (0u == srcClock_Hz))
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+
+    /* SMARTCARD clock initialization. Clock is still not active after this call */
+    if (config->smartCardClock != smartcard_phy_emvsim_InterfaceClockInit(base, config, srcClock_Hz))
+    {
+        return kStatus_SMARTCARD_OtherError;
+    }
+    /* Configure EMVSIM direct interface driver interrupt occur according card presence */
+    if (base->PCSR & EMVSIM_PCSR_SPDP_MASK)
+    {
+        base->PCSR &= ~EMVSIM_PCSR_SPDES_MASK;
+    }
+    else
+    {
+        base->PCSR |= EMVSIM_PCSR_SPDES_MASK;
+    }
+    /* Un-mask presence detect interrupt flag */
+    base->PCSR &= ~EMVSIM_PCSR_SPDIM_MASK;
+
+    return kStatus_SMARTCARD_Success;
+}
+
+void SMARTCARD_PHY_EMVSIM_Deinit(EMVSIM_Type *base, const smartcard_interface_config_t *config)
+{
+    assert((NULL != config));
+    /* Deactivate VCC, CLOCK */
+    base->PCSR &= ~(EMVSIM_PCSR_SCEN_MASK | EMVSIM_PCSR_SVCC_EN_MASK);
+}
+
+status_t SMARTCARD_PHY_EMVSIM_Activate(EMVSIM_Type *base,
+                                       smartcard_context_t *context,
+                                       smartcard_reset_type_t resetType)
+{
+    if ((NULL == context) || (NULL == context->timeDelay))
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+    assert(context->interfaceConfig.vcc == kSMARTCARD_VoltageClassB3_3V);
+
+    context->timersState.initCharTimerExpired = false;
+    context->resetType = resetType;
+
+    /* Disable receiver to deactivate GPC timers trigger */
+    base->CTRL &= ~EMVSIM_CTRL_RCV_EN_MASK;
+    if (resetType == kSMARTCARD_ColdReset)
+    { /* Set polarity of VCC to active high, Enable VCC for SMARTCARD, Enable smart card clock */
+        base->PCSR = (base->PCSR & ~EMVSIM_PCSR_VCCENP_MASK) | (EMVSIM_PCSR_SVCC_EN_MASK | EMVSIM_PCSR_SCEN_MASK);
+        /* Set transfer inversion to default(direct) value */
+        base->CTRL &= ~EMVSIM_CTRL_IC_MASK;
+    }
+    else if (resetType == kSMARTCARD_WarmReset)
+    { /* Ensure that card is already active */
+        if (!context->cardParams.active)
+        { /* Card is not active;hence return */
+            return kStatus_SMARTCARD_CardNotActivated;
+        }
+    }
+    else
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+    /* Set Reset low */
+    base->PCSR &= ~EMVSIM_PCSR_SRST_MASK;
+    /* Calculate time delay needed for reset */
+    uint32_t temp = (uint32_t)((float)(1 + (float)(((float)(1000u * context->interfaceConfig.clockToResetDelay)) /
+                                                   ((float)context->interfaceConfig.smartCardClock))));
+    context->timeDelay(temp);
+    /* Pull reset HIGH Now to mark the end of Activation sequence */
+    base->PCSR |= EMVSIM_PCSR_SRST_MASK;
+    /* Disable GPC timers input clock */
+    base->CLKCFG &= ~(EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK | EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK);
+    /* Down counter trigger, and clear any pending counter status flag */
+    base->TX_STATUS = EMVSIM_TX_STATUS_GPCNT1_TO_MASK | EMVSIM_TX_STATUS_GPCNT0_TO_MASK;
+    /* Set counter value for TS detection delay */
+    base->GPCNT0_VAL = (SMARTCARD_INIT_DELAY_CLOCK_CYCLES + SMARTCARD_INIT_DELAY_CLOCK_CYCLES_ADJUSTMENT);
+    /* Pre-load counter value for ATR duration delay */
+    base->GPCNT1_VAL = (SMARTCARD_EMV_ATR_DURATION_ETU + SMARTCARD_ATR_DURATION_ADJUSTMENT);
+    /* Select the clock for GPCNT for both TS detection and early start of ATR duration counter */
+    base->CLKCFG |=
+        (EMVSIM_CLKCFG_GPCNT0_CLK_SEL(kEMVSIM_GPCCardClock) | EMVSIM_CLKCFG_GPCNT1_CLK_SEL(kEMVSIM_GPCTxClock));
+    /* Set receiver to ICM mode, Flush RX FIFO  */
+    base->CTRL |= (EMVSIM_CTRL_ICM_MASK | EMVSIM_CTRL_FLSH_RX_MASK);
+    /* Enable counter interrupt for TS detection */
+    base->INT_MASK &= ~EMVSIM_INT_MASK_GPCNT0_IM_MASK;
+    /* Clear any pending status flags */
+    base->RX_STATUS = 0xFFFFFFFFu;
+    /* Enable receiver */
+    base->CTRL |= EMVSIM_CTRL_RCV_EN_MASK;
+    /* Here the card was activated */
+    context->cardParams.active = true;
+
+    return kStatus_SMARTCARD_Success;
+}
+
+status_t SMARTCARD_PHY_EMVSIM_Deactivate(EMVSIM_Type *base, smartcard_context_t *context)
+{
+    if ((NULL == context))
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+
+    /* Assert Reset */
+    base->PCSR &= ~EMVSIM_PCSR_SRST_MASK;
+    /* Stop SMARTCARD clock generation */
+    base->PCSR &= ~EMVSIM_PCSR_SCEN_MASK;
+    /* Deactivate card by disabling VCC */
+    base->PCSR &= ~EMVSIM_PCSR_SVCC_EN_MASK;
+    /* According EMV 4.3 specification deactivation sequence should be done within 100ms.
+     * The period is measured from the time that RST is set to state L to the time that Vcc
+     * reaches 0.4 V or less.
+     */
+    context->timeDelay(100);
+    /* Here the card was deactivated */
+    context->cardParams.active = false;
+
+    return kStatus_SMARTCARD_Success;
+}
+
+status_t SMARTCARD_PHY_EMVSIM_Control(EMVSIM_Type *base,
+                                      smartcard_context_t *context,
+                                      smartcard_interface_control_t control,
+                                      uint32_t param)
+{
+    if ((NULL == context))
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+
+    switch (control)
+    {
+        case kSMARTCARD_InterfaceSetVcc:
+            /* Only 3.3V interface supported by the direct interface */
+            assert((smartcard_card_voltage_class_t)param == kSMARTCARD_VoltageClassB3_3V);
+            context->interfaceConfig.vcc = (smartcard_card_voltage_class_t)param;
+            break;
+        case kSMARTCARD_InterfaceSetClockToResetDelay:
+            /* Set interface clock to Reset delay set by caller */
+            context->interfaceConfig.clockToResetDelay = param;
+            break;
+        case kSMARTCARD_InterfaceReadStatus:
+            /* Expecting active low present detect */
+            context->cardParams.present =
+                (emvsim_presence_detect_status_t)((base->PCSR & EMVSIM_PCSR_SPDP_MASK) >> EMVSIM_PCSR_SPDP_SHIFT) ==
+                kEMVSIM_DetectPinIsLow;
+            break;
+        default:
+            return kStatus_SMARTCARD_InvalidInput;
+    }
+
+    return kStatus_SMARTCARD_Success;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_emvsim.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_emvsim.h
new file mode 100644
index 00000000000..e69bb4bae66
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_emvsim.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_SMARTCARD_PHY_EMVSIM_H_
+#define _FSL_SMARTCARD_PHY_EMVSIM_H_
+
+#include "fsl_smartcard.h"
+
+/*!
+ * @addtogroup smartcard_phy_emvsim_driver
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Smart card define which specify adjustment number of clock cycles during which ATR string has to be received
+ */
+#define SMARTCARD_ATR_DURATION_ADJUSTMENT (360u)
+
+/*! @brief Smart card define which specify adjustment number of clock cycles until initial 'TS' character has to be
+ * received */
+#define SMARTCARD_INIT_DELAY_CLOCK_CYCLES_ADJUSTMENT (4200u)
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Fill in smartcardInterfaceConfig structure with default values.
+ *
+ * @param config The user configuration structure of type smartcard_interface_config_t.
+ * Function fill in members:
+ *      clockToResetDelay = 42000,
+ *      vcc = kSmartcardVoltageClassB3_3V,
+ * with default values.
+ */
+void SMARTCARD_PHY_EMVSIM_GetDefaultConfig(smartcard_interface_config_t *config);
+
+/*!
+ * @brief Configures a Smart card interface for operation.
+ *
+ * @param base The Smart card peripheral module base address.
+ * @param config The user configuration structure of type smartcard_interface_config_t. The user
+ *  is responsible to fill out the members of this structure and to pass the pointer of this structure
+ *  into this function or call SMARTCARD_PHY_EMVSIMInitUserConfigDefault to fill out structure with default values.
+ * @param srcClock_Hz Smart card clock generation module source clock.
+ *
+ * @retval kStatus_SMARTCARD_Success or kStatus_SMARTCARD_OtherError in case of error.
+ */
+status_t SMARTCARD_PHY_EMVSIM_Init(EMVSIM_Type *base, const smartcard_interface_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief De-initializes a Smart card interface. Stops Smart card clock and disable VCC.
+ *
+ * @param base Smart card peripheral module base address.
+ * @param config Smart card configuration structure.
+ */
+void SMARTCARD_PHY_EMVSIM_Deinit(EMVSIM_Type *base, const smartcard_interface_config_t *config);
+
+/*!
+ * @brief Activates the smart card IC.
+ *
+ * @param base The EMVSIM peripheral base address.
+ * @param context A pointer to a Smart card driver context structure.
+ * @param resetType type of reset to be performed, possible values
+ *                       = kSmartcardColdReset, kSmartcardWarmReset
+ *
+ * @retval kStatus_SMARTCARD_Success or kStatus_SMARTCARD_OtherError in case of error.
+ */
+status_t SMARTCARD_PHY_EMVSIM_Activate(EMVSIM_Type *base,
+                                       smartcard_context_t *context,
+                                       smartcard_reset_type_t resetType);
+
+/*!
+ * @brief De-activates the smart card IC.
+ *
+ * @param base The EMVSIM peripheral base address.
+ * @param context A pointer to a Smart card driver context structure.
+ *
+ * @retval kStatus_SMARTCARD_Success or kStatus_SMARTCARD_OtherError in case of error.
+ */
+status_t SMARTCARD_PHY_EMVSIM_Deactivate(EMVSIM_Type *base, smartcard_context_t *context);
+
+/*!
+ * @brief Controls Smart card interface IC.
+ *
+ * @param base The EMVSIM peripheral base address.
+ * @param context A pointer to a Smart card driver context structure.
+ * @param control A interface command type.
+ * @param param Integer value specific to control type
+ *
+ * @retval kStatus_SMARTCARD_Success or kStatus_SMARTCARD_OtherError in case of error.
+ */
+status_t SMARTCARD_PHY_EMVSIM_Control(EMVSIM_Type *base,
+                                      smartcard_context_t *context,
+                                      smartcard_interface_control_t control,
+                                      uint32_t param);
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_SMARTCARD_PHY_EMVSIM_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_tda8035.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_tda8035.c
new file mode 100644
index 00000000000..e191f207cab
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_tda8035.c
@@ -0,0 +1,543 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_smartcard_phy_tda8035.h"
+#if (defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT))
+#include "fsl_smartcard_emvsim.h"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+static uint32_t smartcard_phy_tda8035_InterfaceClockInit(void *base,
+                                                         smartcard_interface_config_t const *config,
+                                                         uint32_t srcClock_Hz);
+static void smartcard_phy_tda8035_InterfaceClockDeinit(void *base, smartcard_interface_config_t const *config);
+static void smartcard_phy_tda8035_InterfaceClockEnable(void *base, smartcard_interface_config_t const *config);
+#if !(defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT))
+extern void smartcard_uart_TimerStart(uint8_t channel, uint32_t time);
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+
+/*!
+ * @brief This function initializes clock module used for card clock generation
+ */
+static uint32_t smartcard_phy_tda8035_InterfaceClockInit(void *base,
+                                                         smartcard_interface_config_t const *config,
+                                                         uint32_t srcClock_Hz)
+{
+    assert((NULL != config));
+#if defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT)
+    assert(config->clockModule < FSL_FEATURE_SOC_EMVSIM_COUNT);
+
+    uint32_t emvsimClkMhz = 0u;
+    uint8_t emvsimPRSCValue;
+
+    /* Retrieve EMV SIM clock */
+    emvsimClkMhz = srcClock_Hz / 1000000u;
+    /* Calculate MOD value */
+    emvsimPRSCValue = (emvsimClkMhz * 1000u) / (config->smartCardClock / 1000u);
+    /* Set clock prescaler */
+    ((EMVSIM_Type *)base)->CLKCFG =
+        (((EMVSIM_Type *)base)->CLKCFG & ~EMVSIM_CLKCFG_CLK_PRSC_MASK) | EMVSIM_CLKCFG_CLK_PRSC(emvsimPRSCValue);
+
+    return config->smartCardClock;
+#elif defined(FSL_FEATURE_SOC_FTM_COUNT) && (FSL_FEATURE_SOC_FTM_COUNT)
+    assert(config->clockModule < FSL_FEATURE_SOC_FTM_COUNT);
+
+    uint32_t periph_clk_mhz = 0u;
+    uint16_t ftmModValue;
+    uint32_t ftm_base[] = FTM_BASE_ADDRS;
+    FTM_Type *ftmBase = (FTM_Type *)ftm_base[config->clockModule];
+
+    /* Retrieve FTM system clock */
+    periph_clk_mhz = srcClock_Hz / 1000000u;
+    /* Calculate MOD value */
+    ftmModValue = ((periph_clk_mhz * 1000u / 2u) / (config->smartCardClock / 1000u)) - 1u;
+    /* un-gate FTM peripheral clock */
+    switch (config->clockModule)
+    {
+        case 0u:
+            CLOCK_EnableClock(kCLOCK_Ftm0);
+            break;
+#if FSL_FEATURE_SOC_FTM_COUNT > 1
+        case 1u:
+            CLOCK_EnableClock(kCLOCK_Ftm1);
+            break;
+#endif
+#if FSL_FEATURE_SOC_FTM_COUNT > 2
+        case 2u:
+            CLOCK_EnableClock(kCLOCK_Ftm2);
+            break;
+#endif
+#if FSL_FEATURE_SOC_FTM_COUNT > 3
+        case 3u:
+            CLOCK_EnableClock(kCLOCK_Ftm3);
+            break;
+#endif
+        default:
+            return 0u;
+    }
+    /* Initialize FTM driver */
+    /* Reset FTM prescaler to 'Divide by 1', i.e., to be same clock as peripheral clock
+     * Disable FTM counter, Set counter to operates in Up-counting mode */
+    ftmBase->SC &= ~(FTM_SC_PS_MASK | FTM_SC_CLKS_MASK | FTM_SC_CPWMS_MASK);
+    /* Set initial counter value */
+    ftmBase->CNTIN = 0u;
+    /* Set MOD value */
+    ftmBase->MOD = ftmModValue;
+    /* Configure mode to output compare, toggle output on match */
+    ftmBase->CONTROLS[config->clockModuleChannel].CnSC = (FTM_CnSC_ELSA_MASK | FTM_CnSC_MSA_MASK);
+    /* Configure a match value to toggle output at */
+    ftmBase->CONTROLS[config->clockModuleChannel].CnV = 1;
+    /* Re-calculate the actually configured smartcard clock and return to caller */
+    return (uint32_t)(((periph_clk_mhz * 1000u / 2u) / (ftmBase->MOD + 1u)) * 1000u);
+#else
+    return 0u;
+#endif
+}
+
+/*!
+ * @brief This function de-initialize clock module used for card clock generation
+ */
+static void smartcard_phy_tda8035_InterfaceClockDeinit(void *base, smartcard_interface_config_t const *config)
+{
+#if defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT)
+    assert((config->clockModule < FSL_FEATURE_SOC_EMVSIM_COUNT) && (NULL != base));
+
+    /* Disable smart card clock */
+    ((EMVSIM_Type *)base)->PCSR &= ~EMVSIM_PCSR_SCEN_MASK;
+#elif defined(FSL_FEATURE_SOC_FTM_COUNT) && (FSL_FEATURE_SOC_FTM_COUNT)
+    assert(config->clockModule < FSL_FEATURE_SOC_FTM_COUNT);
+    /* gate FTM peripheral clock */
+    switch (config->clockModule)
+    {
+        case 0u:
+            CLOCK_DisableClock(kCLOCK_Ftm0);
+            break;
+#if FSL_FEATURE_SOC_FTM_COUNT > 1
+        case 1u:
+            CLOCK_DisableClock(kCLOCK_Ftm1);
+            break;
+#endif
+#if FSL_FEATURE_SOC_FTM_COUNT > 2
+        case 2u:
+            CLOCK_DisableClock(kCLOCK_Ftm2);
+            break;
+#endif
+#if FSL_FEATURE_SOC_FTM_COUNT > 3
+        case 3u:
+            CLOCK_DisableClock(kCLOCK_Ftm3);
+            break;
+#endif
+        default:
+            break;
+    }
+#endif
+}
+
+/*!
+ * @brief This function activate smart card clock
+ */
+static void smartcard_phy_tda8035_InterfaceClockEnable(void *base, smartcard_interface_config_t const *config)
+{
+/* Enable smart card clock */
+#if defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT)
+    ((EMVSIM_Type *)base)->PCSR |= EMVSIM_PCSR_SCEN_MASK;
+#elif defined(FSL_FEATURE_SOC_FTM_COUNT) && (FSL_FEATURE_SOC_FTM_COUNT)
+    uint32_t ftm_base[] = FTM_BASE_ADDRS;
+    FTM_Type *ftmBase = (FTM_Type *)ftm_base[config->clockModule];
+    /* Set clock source to start the counter : System clock */
+    ftmBase->SC = FTM_SC_CLKS(1);
+#endif
+}
+
+/*!
+ * @brief This function deactivate smart card clock
+ */
+static void smartcard_phy_tda8035_InterfaceClockDisable(void *base, smartcard_interface_config_t const *config)
+{
+/* Enable smart card clock */
+#if defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT)
+    ((EMVSIM_Type *)base)->PCSR &= ~EMVSIM_PCSR_SCEN_MASK;
+#elif defined(FSL_FEATURE_SOC_FTM_COUNT) && (FSL_FEATURE_SOC_FTM_COUNT)
+    uint32_t ftm_base[] = FTM_BASE_ADDRS;
+    FTM_Type *ftmBase = (FTM_Type *)ftm_base[config->clockModule];
+    /* Set clock source to start the counter : System clock */
+    ftmBase->SC &= ~FTM_SC_CLKS_MASK;
+#endif
+}
+
+void SMARTCARD_PHY_TDA8035_GetDefaultConfig(smartcard_interface_config_t *config)
+{
+    assert((NULL != config));
+
+    config->clockToResetDelay = SMARTCARD_INIT_DELAY_CLOCK_CYCLES;
+    config->vcc = kSMARTCARD_VoltageClassB3_3V;
+}
+
+status_t SMARTCARD_PHY_TDA8035_Init(void *base, smartcard_interface_config_t const *config, uint32_t srcClock_Hz)
+{
+    if ((NULL == config) || (0u == srcClock_Hz))
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+
+    /* Configure GPIO(CMDVCC, RST, INT, VSEL0, VSEL1) pins */
+    uint32_t gpio_base[] = GPIO_BASE_ADDRS;
+    IRQn_Type port_irq[] = PORT_IRQS;
+    /* Set VSEL pins to low level context */
+    ((GPIO_Type *)gpio_base[config->vsel0Port])->PCOR |= (1u << config->vsel0Pin);
+    ((GPIO_Type *)gpio_base[config->vsel1Port])->PCOR |= (1u << config->vsel1Pin);
+    /* Set VSEL pins to output pins */
+    ((GPIO_Type *)gpio_base[config->vsel0Port])->PDDR |= (1u << config->vsel0Pin);
+    ((GPIO_Type *)gpio_base[config->vsel1Port])->PDDR |= (1u << config->vsel1Pin);
+#if defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT)
+    /* Set CMD_VCC pin to logic level '1', to allow card detection interrupt from TDA8035 */
+    ((EMVSIM_Type *)base)->PCSR |= EMVSIM_PCSR_SVCC_EN_MASK;
+    ((EMVSIM_Type *)base)->PCSR &= ~EMVSIM_PCSR_VCCENP_MASK;
+#else
+    /* Set RST pin to zero context and CMDVCC to high context */
+    ((GPIO_Type *)gpio_base[config->resetPort])->PCOR |= (1u << config->resetPin);
+    ((GPIO_Type *)gpio_base[config->controlPort])->PSOR |= (1u << config->controlPin);
+    /* Set CMDVCC, RESET pins as output pins */
+    ((GPIO_Type *)gpio_base[config->resetPort])->PDDR |= (1u << config->resetPin);
+    ((GPIO_Type *)gpio_base[config->controlPort])->PDDR |= (1u << config->controlPin);
+
+#endif
+    /* Initialize INT pin */
+    ((GPIO_Type *)gpio_base[config->irqPort])->PDDR &= ~(1u << config->irqPin);
+    /* Enable Port IRQ for smartcard presence detection */
+    NVIC_EnableIRQ(port_irq[config->irqPort]);
+    /* Smartcard clock initialization */
+    if (config->smartCardClock != smartcard_phy_tda8035_InterfaceClockInit(base, config, srcClock_Hz))
+    {
+        return kStatus_SMARTCARD_OtherError;
+    }
+
+    return kStatus_SMARTCARD_Success;
+}
+
+void SMARTCARD_PHY_TDA8035_Deinit(void *base, smartcard_interface_config_t *config)
+{
+    assert((NULL != config));
+
+    IRQn_Type port_irq[] = PORT_IRQS;
+    NVIC_DisableIRQ(port_irq[config->irqPort]);
+    /* Stop smartcard clock */
+    smartcard_phy_tda8035_InterfaceClockDeinit(base, config);
+}
+
+status_t SMARTCARD_PHY_TDA8035_Activate(void *base, smartcard_context_t *context, smartcard_reset_type_t resetType)
+{
+    if ((NULL == context) || (NULL == context->timeDelay))
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+
+    context->timersState.initCharTimerExpired = false;
+    context->resetType = resetType;
+    uint32_t gpio_base[] = GPIO_BASE_ADDRS;
+#if defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT)
+    EMVSIM_Type *emvsimBase = (EMVSIM_Type *)base;
+    /* Disable receiver to deactivate GPC timers trigger */
+    emvsimBase->CTRL &= ~EMVSIM_CTRL_RCV_EN_MASK;
+#endif
+
+    if (resetType == kSMARTCARD_ColdReset)
+    { /* Ensure that RST is HIGH and CMD is high here so that PHY goes in normal mode */
+#if defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT)
+        emvsimBase->PCSR =
+            (emvsimBase->PCSR & ~(EMVSIM_PCSR_VCCENP_MASK | EMVSIM_PCSR_SRST_MASK)) | EMVSIM_PCSR_SVCC_EN_MASK;
+        emvsimBase->PCSR &= ~EMVSIM_PCSR_SRST_MASK;
+#else
+        ((GPIO_Type *)gpio_base[context->interfaceConfig.resetPort])->PCOR |= (1u << context->interfaceConfig.resetPin);
+        ((GPIO_Type *)gpio_base[context->interfaceConfig.controlPort])->PSOR |=
+            (1u << context->interfaceConfig.controlPin);
+#endif
+        /* vcc = 5v: vsel0=1,vsel1=1
+         * vcc = 3.3v: vsel0=0,vsel1=1
+         * vcc = 1.8v: vsel0=x,vsel1=0 */
+        /* Setting of VSEL1 pin */
+        if ((kSMARTCARD_VoltageClassA5_0V == context->interfaceConfig.vcc) ||
+            (kSMARTCARD_VoltageClassB3_3V == context->interfaceConfig.vcc))
+        {
+            ((GPIO_Type *)gpio_base[context->interfaceConfig.vsel1Port])->PSOR |=
+                (1u << context->interfaceConfig.vsel1Pin);
+        }
+        else
+        {
+            ((GPIO_Type *)gpio_base[context->interfaceConfig.vsel1Port])->PCOR |=
+                (1u << context->interfaceConfig.vsel1Pin);
+        }
+        /* Setting of VSEL0 pin */
+        if (kSMARTCARD_VoltageClassA5_0V == context->interfaceConfig.vcc)
+        {
+            ((GPIO_Type *)gpio_base[context->interfaceConfig.vsel0Port])->PSOR |=
+                (1u << context->interfaceConfig.vsel0Pin);
+        }
+        else
+        {
+            ((GPIO_Type *)gpio_base[context->interfaceConfig.vsel0Port])->PCOR |=
+                (1u << context->interfaceConfig.vsel0Pin);
+        }
+/* Set PHY to start Activation sequence by pulling CMDVCC low */
+#if defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT)
+        emvsimBase->PCSR |= EMVSIM_PCSR_VCCENP_MASK;
+#else
+        ((GPIO_Type *)gpio_base[context->interfaceConfig.controlPort])->PCOR |=
+            (1u << context->interfaceConfig.controlPin);
+#endif
+        /* wait 3.42ms then enable clock  an10997 P29
+        During t0, the TDA8035 checks for the XTAL1 pin to detect if a crystal is present or if the clock is supplied
+        from the micro-controller, and then waits for the crystal to start.
+        This time is fixed, even if there is no crystal, and its maximum value is 3.1 ms.
+        t1 is the time between the beginning of the activation and the start of the clock on the smart card side. This
+        time depends on the internal oscillator frequency and
+        lasts at maximum 320 us. */
+
+        /* Set counter value , no card clock ,so use OS delay */
+        context->timeDelay(4u);
+        smartcard_phy_tda8035_InterfaceClockEnable(base, &context->interfaceConfig);
+    }
+    else if (resetType == kSMARTCARD_WarmReset)
+    { /* Ensure that card is already active */
+        if (!context->cardParams.active)
+        { /* Card is not active;hence return */
+            return kStatus_SMARTCARD_CardNotActivated;
+        }
+/* Pull RESET low to start warm Activation sequence */
+#if defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT)
+        emvsimBase->PCSR &= ~EMVSIM_PCSR_SRST_MASK;
+#else
+        ((GPIO_Type *)gpio_base[context->interfaceConfig.resetPort])->PCOR |= (1u << context->interfaceConfig.resetPin);
+#endif
+    }
+    else
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+    /* Wait for sometime as specified by EMV before pulling RST High
+     * As per EMV delay <= 42000 Clock cycles
+     * as per PHY delay >= 1us */
+    uint32_t temp = (uint32_t)((float)(1 + (float)(((float)(1000u * context->interfaceConfig.clockToResetDelay)) /
+                                                   ((float)context->interfaceConfig.smartCardClock))));
+    context->timeDelay(temp);
+/* Pull reset HIGH Now to mark the end of Activation sequence */
+#if defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT)
+    emvsimBase->PCSR |= EMVSIM_PCSR_SRST_MASK;
+#else
+    ((GPIO_Type *)gpio_base[context->interfaceConfig.resetPort])->PSOR |= (1u << context->interfaceConfig.resetPin);
+#endif
+/* Configure TS character and ATR duration timers and enable receiver */
+#if defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT)
+    emvsimBase->CLKCFG &= ~(EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK | EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK);
+    /* Down counter trigger, and clear any pending counter status flag */
+    emvsimBase->TX_STATUS = EMVSIM_TX_STATUS_GPCNT1_TO_MASK | EMVSIM_TX_STATUS_GPCNT0_TO_MASK;
+    /* Set counter value for TS detection delay */
+    emvsimBase->GPCNT0_VAL = (SMARTCARD_INIT_DELAY_CLOCK_CYCLES + SMARTCARD_INIT_DELAY_CLOCK_CYCLES_ADJUSTMENT);
+    /* Pre-load counter value for ATR duration delay */
+    emvsimBase->GPCNT1_VAL = (SMARTCARD_EMV_ATR_DURATION_ETU + SMARTCARD_ATR_DURATION_ADJUSTMENT);
+    /* Select the clock for GPCNT for both TS detection and early start of ATR duration counter */
+    emvsimBase->CLKCFG |=
+        (EMVSIM_CLKCFG_GPCNT0_CLK_SEL(kEMVSIM_GPCCardClock) | EMVSIM_CLKCFG_GPCNT1_CLK_SEL(kEMVSIM_GPCTxClock));
+    /* Set receiver to ICM mode, Flush RX FIFO  */
+    emvsimBase->CTRL |= (EMVSIM_CTRL_ICM_MASK | EMVSIM_CTRL_FLSH_RX_MASK);
+    /* Enable counter interrupt for TS detection */
+    emvsimBase->INT_MASK &= ~EMVSIM_INT_MASK_GPCNT0_IM_MASK;
+    /* Clear any pending status flags */
+    emvsimBase->RX_STATUS = 0xFFFFFFFFu;
+    /* Enable receiver */
+    emvsimBase->CTRL |= EMVSIM_CTRL_RCV_EN_MASK;
+#else
+    /* Enable external timer for TS detection time-out */
+    smartcard_uart_TimerStart(context->interfaceConfig.tsTimerId,
+                              (SMARTCARD_INIT_DELAY_CLOCK_CYCLES + SMARTCARD_INIT_DELAY_CLOCK_CYCLES_ADJUSTMENT) *
+                                  (CLOCK_GetFreq(kCLOCK_BusClk) / context->interfaceConfig.smartCardClock));
+#endif
+    /* Here the card was activated */
+    context->cardParams.active = true;
+
+    return kStatus_SMARTCARD_Success;
+}
+
+status_t SMARTCARD_PHY_TDA8035_Deactivate(void *base, smartcard_context_t *context)
+{
+    if ((NULL == context))
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+
+#if !(defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT))
+    uint32_t gpio_base[] = GPIO_BASE_ADDRS;
+#endif
+/* Tell PHY to start Deactivation sequence by pulling CMD high and reset low */
+#if defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT)
+    ((EMVSIM_Type *)base)->PCSR |= EMVSIM_PCSR_SVCC_EN_MASK;
+    ((EMVSIM_Type *)base)->PCSR &= ~EMVSIM_PCSR_VCCENP_MASK;
+    ((EMVSIM_Type *)base)->PCSR &= ~EMVSIM_PCSR_SRST_MASK;
+#else
+    ((GPIO_Type *)gpio_base[context->interfaceConfig.controlPort])->PSOR |= (1u << context->interfaceConfig.controlPin);
+    ((GPIO_Type *)gpio_base[context->interfaceConfig.resetPort])->PCOR |= (1u << context->interfaceConfig.resetPin);
+#endif
+    smartcard_phy_tda8035_InterfaceClockDisable(base, &context->interfaceConfig);
+    /* According EMV 4.3 specification deactivation sequence should be done within 100ms.
+     * The period is measured from the time that RST is set to state L to the time that Vcc
+     * reaches 0.4 V or less. */
+    context->timeDelay(100);
+    /* Here the card was deactivated */
+    context->cardParams.active = false;
+
+    return kStatus_SMARTCARD_Success;
+}
+
+status_t SMARTCARD_PHY_TDA8035_Control(void *base,
+                                       smartcard_context_t *context,
+                                       smartcard_interface_control_t control,
+                                       uint32_t param)
+{
+    if ((NULL == context))
+    {
+        return kStatus_SMARTCARD_InvalidInput;
+    }
+#if !(defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT))
+    uint32_t gpio_base[] = GPIO_BASE_ADDRS;
+#endif
+
+    switch (control)
+    {
+        case kSMARTCARD_InterfaceSetVcc:
+            /* Set card parameter to VCC level set by caller */
+            context->interfaceConfig.vcc = (smartcard_card_voltage_class_t)param;
+            break;
+        case kSMARTCARD_InterfaceSetClockToResetDelay:
+            /* Set interface clock to Reset delay set by caller */
+            context->interfaceConfig.clockToResetDelay = param;
+            break;
+        case kSMARTCARD_InterfaceReadStatus:
+#if defined(FSL_FEATURE_SOC_EMVSIM_COUNT) && (FSL_FEATURE_SOC_EMVSIM_COUNT)
+            /* Expecting active low present detect */
+            context->cardParams.present =
+                ((emvsim_presence_detect_status_t)((((EMVSIM_Type *)base)->PCSR & EMVSIM_PCSR_SPDP_MASK) >>
+                                                   EMVSIM_PCSR_SPDP_SHIFT) == kEMVSIM_DetectPinIsLow);
+#else
+            if (((GPIO_Type *)gpio_base[context->interfaceConfig.controlPort])->PDIR &
+                (1u << context->interfaceConfig.controlPin))
+            {
+                if (((GPIO_Type *)gpio_base[context->interfaceConfig.irqPort])->PDIR &
+                    (1u << context->interfaceConfig.irqPin))
+                { /* CMDVCC is high => session is inactive and INT is high => card is present */
+                    context->cardParams.present = true;
+                    context->cardParams.active = false;
+                    context->cardParams.faulty = false;
+                    context->cardParams.status = SMARTCARD_TDA8035_STATUS_PRES;
+                }
+                else
+                { /* CMDVCC is high => session is inactive and INT is low => card is absent */
+                    context->cardParams.present = false;
+                    context->cardParams.active = false;
+                    context->cardParams.faulty = false;
+                    context->cardParams.status = 0u;
+                }
+            }
+            else
+            {
+                if (((GPIO_Type *)gpio_base[context->interfaceConfig.irqPort])->PDIR &
+                    (1u << context->interfaceConfig.irqPin))
+                { /* CMDVCC is low => session is active and INT is high => card is present */
+                    context->cardParams.present = true;
+                    context->cardParams.active = true;
+                    context->cardParams.faulty = false;
+                    context->cardParams.status = SMARTCARD_TDA8035_STATUS_PRES | SMARTCARD_TDA8035_STATUS_ACTIVE;
+                }
+                else
+                {
+                    /* CMDVCC is low => session is active and INT is high => card is absent/deactivated due to some
+                     * fault
+                     * A fault has been detected (card has been deactivated) but The cause of the deactivation is not
+                     * yet known.
+                     * Lets determine the cause of fault by pulling CMD high */
+                    if (((GPIO_Type *)gpio_base[context->interfaceConfig.irqPort])->PDIR &
+                        (1u << context->interfaceConfig.irqPin))
+                    {   /* The fault detected was not a card removal (card is still present) */
+                        /* If INT follows CMDVCCN, the fault is due to a supply voltage drop, a VCC over-current
+                         * detection or overheating. */
+                        context->cardParams.present = true;
+                        context->cardParams.active = false;
+                        context->cardParams.faulty = true;
+                        context->cardParams.status = SMARTCARD_TDA8035_STATUS_PRES | SMARTCARD_TDA8035_STATUS_FAULTY |
+                                                     SMARTCARD_TDA8035_STATUS_CARD_DEACTIVATED;
+                    }
+                    else
+                    { /* The fault detected was the card removal
+                       * Setting CMDVCCN allows checking if the deactivation is due to card removal.
+                       * In this case the INT pin will stay low after CMDVCCN is high. */
+                        context->cardParams.present = false;
+                        context->cardParams.active = false;
+                        context->cardParams.faulty = false;
+                        context->cardParams.status =
+                            SMARTCARD_TDA8035_STATUS_CARD_REMOVED | SMARTCARD_TDA8035_STATUS_CARD_DEACTIVATED;
+                    }
+                }
+            }
+#endif
+            break;
+        default:
+            return kStatus_SMARTCARD_InvalidInput;
+    }
+
+    return kStatus_SMARTCARD_Success;
+}
+
+void SMARTCARD_PHY_TDA8035_IRQHandler(void *base, smartcard_context_t *context)
+{
+    if ((NULL == context))
+    {
+        return;
+    }
+    /* Read interface/card status */
+    SMARTCARD_PHY_TDA8035_Control(base, context, kSMARTCARD_InterfaceReadStatus, 0u);
+    /* Invoke callback if there is one */
+    if (NULL != context->interfaceCallback)
+    {
+        context->interfaceCallback(context, context->interfaceCallbackParam);
+    }
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_tda8035.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_tda8035.h
new file mode 100644
index 00000000000..803e2f1c131
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smartcard_phy_tda8035.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_SMARTCARD_PHY_TDA8035_H_
+#define _FSL_SMARTCARD_PHY_TDA8035_H_
+
+#include "fsl_smartcard.h"
+
+/*!
+ * @addtogroup smartcard_phy_tda8035_driver
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Smart card definition which specifies adjustment number of clock cycles during which ATR string has to be received
+ */
+#define SMARTCARD_ATR_DURATION_ADJUSTMENT (360u)
+
+/*! @brief Smart card definition which specifies adjustment number of clock cycles until initial 'TS' character has to be
+ * received */
+#define SMARTCARD_INIT_DELAY_CLOCK_CYCLES_ADJUSTMENT (4200u)
+
+/*! @brief Masks for TDA8035 status register */
+#define SMARTCARD_TDA8035_STATUS_PRES (0x01u)             /*!< Smart card phy TDA8035 Smart card present status */
+#define SMARTCARD_TDA8035_STATUS_ACTIVE (0x02u)           /*!< Smart card phy TDA8035 Smart card active status */
+#define SMARTCARD_TDA8035_STATUS_FAULTY (0x04u)           /*!< Smart card phy TDA8035 Smart card faulty status */
+#define SMARTCARD_TDA8035_STATUS_CARD_REMOVED (0x08u)     /*!< Smart card phy TDA8035 Smart card removed status */
+#define SMARTCARD_TDA8035_STATUS_CARD_DEACTIVATED (0x10u) /*!< Smart card phy TDA8035 Smart card deactivated status */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Fills in config structure with default values.
+ *
+ * @param config The Smart card user configuration structure which contains configuration structure of type
+ * smartcard_interface_config_t.
+ * Function fill in members:
+ *      clockToResetDelay = 42000,
+ *      vcc = kSmartcardVoltageClassB3_3V,
+ * with default values.
+ */
+void SMARTCARD_PHY_TDA8035_GetDefaultConfig(smartcard_interface_config_t *config);
+
+/*!
+ * @brief Initializes a Smart card interface instance for operation.
+ *
+ * @param base The Smart card peripheral base address.
+ * @param config The user configuration structure of type smartcard_interface_config_t. The user
+ *  can call to fill out configuration structure function SMARTCARD_PHY_TDA8035_GetDefaultConfig().
+ * @param srcClock_Hz Smart card clock generation module source clock.
+ *
+ * @retval kStatus_SMARTCARD_Success or kStatus_SMARTCARD_OtherError in case of error.
+ */
+status_t SMARTCARD_PHY_TDA8035_Init(void *base, smartcard_interface_config_t const *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief De-initializes a Smart card interface. Stops Smart card clock and disable VCC.
+ *
+ * @param base The Smart card peripheral module base address.
+ * @param config The user configuration structure of type smartcard_interface_config_t.
+ */
+void SMARTCARD_PHY_TDA8035_Deinit(void *base, smartcard_interface_config_t *config);
+
+/*!
+ * @brief Activates the Smart card IC.
+ *
+ * @param base The Smart card peripheral module base address.
+ * @param context A pointer to a Smart card driver context structure.
+ * @param resetType type of reset to be performed, possible values
+ *                       = kSmartcardColdReset, kSmartcardWarmReset
+ *
+ * @retval kStatus_SMARTCARD_Success or kStatus_SMARTCARD_OtherError in case of error.
+ */
+status_t SMARTCARD_PHY_TDA8035_Activate(void *base, smartcard_context_t *context, smartcard_reset_type_t resetType);
+
+/*!
+ * @brief De-activates the Smart card IC.
+ *
+ * @param base The Smart card peripheral module base address.
+ * @param context A pointer to a Smart card driver context structure.
+ *
+ * @retval kStatus_SMARTCARD_Success or kStatus_SMARTCARD_OtherError in case of error.
+ */
+status_t SMARTCARD_PHY_TDA8035_Deactivate(void *base, smartcard_context_t *context);
+
+/*!
+ * @brief Controls Smart card interface IC.
+ *
+ * @param base The Smart card peripheral module base address.
+ * @param context A pointer to a Smart card driver context structure.
+ * @param control A interface command type.
+ * @param param Integer value specific to control type
+ *
+ * @retval kStatus_SMARTCARD_Success or kStatus_SMARTCARD_OtherError in case of error.
+ */
+status_t SMARTCARD_PHY_TDA8035_Control(void *base,
+                                       smartcard_context_t *context,
+                                       smartcard_interface_control_t control,
+                                       uint32_t param);
+
+/*!
+ * @brief Smart card interface IC IRQ ISR.
+ *
+ * @param base The Smart card peripheral module base address.
+ * @param context The Smart card context pointer.
+ */
+void SMARTCARD_PHY_TDA8035_IRQHandler(void *base, smartcard_context_t *context);
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_SMARTCARD_TDA8035_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smc.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smc.c
new file mode 100644
index 00000000000..45382fdffea
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smc.c
@@ -0,0 +1,366 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_smc.h"
+
+#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
+void SMC_GetParam(SMC_Type *base, smc_param_t *param)
+{
+    uint32_t reg = base->PARAM;
+    param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK);
+    param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK);
+    param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK);
+    param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK);
+}
+#endif /* FSL_FEATURE_SMC_HAS_PARAM */
+
+status_t SMC_SetPowerModeRun(SMC_Type *base)
+{
+    uint8_t reg;
+
+    reg = base->PMCTRL;
+    /* configure Normal RUN mode */
+    reg &= ~SMC_PMCTRL_RUNM_MASK;
+    reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT);
+    base->PMCTRL = reg;
+
+    return kStatus_Success;
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+status_t SMC_SetPowerModeHsrun(SMC_Type *base)
+{
+    uint8_t reg;
+
+    reg = base->PMCTRL;
+    /* configure High Speed RUN mode */
+    reg &= ~SMC_PMCTRL_RUNM_MASK;
+    reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT);
+    base->PMCTRL = reg;
+
+    return kStatus_Success;
+}
+#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+
+status_t SMC_SetPowerModeWait(SMC_Type *base)
+{
+    /* configure Normal Wait mode */
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return kStatus_Success;
+}
+
+status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option)
+{
+    uint8_t reg;
+
+#if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO)
+    /* configure the Partial Stop mode in Noraml Stop mode */
+    reg = base->STOPCTRL;
+    reg &= ~SMC_STOPCTRL_PSTOPO_MASK;
+    reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT);
+    base->STOPCTRL = reg;
+#endif
+
+    /* configure Normal Stop mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+    /* check whether the power mode enter Stop mode succeed */
+    if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+}
+
+status_t SMC_SetPowerModeVlpr(SMC_Type *base
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+                              ,
+                              bool wakeupMode
+#endif
+                              )
+{
+    uint8_t reg;
+
+    reg = base->PMCTRL;
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    /* configure whether the system remains in VLP mode on an interrupt */
+    if (wakeupMode)
+    {
+        /* exits to RUN mode on an interrupt */
+        reg |= SMC_PMCTRL_LPWUI_MASK;
+    }
+    else
+    {
+        /* remains in VLP mode on an interrupt */
+        reg &= ~SMC_PMCTRL_LPWUI_MASK;
+    }
+#endif /* FSL_FEATURE_SMC_HAS_LPWUI */
+
+    /* configure VLPR mode */
+    reg &= ~SMC_PMCTRL_RUNM_MASK;
+    reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT);
+    base->PMCTRL = reg;
+
+    return kStatus_Success;
+}
+
+status_t SMC_SetPowerModeVlpw(SMC_Type *base)
+{
+    /* configure VLPW mode */
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return kStatus_Success;
+}
+
+status_t SMC_SetPowerModeVlps(SMC_Type *base)
+{
+    uint8_t reg;
+
+    /* configure VLPS mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+    /* check whether the power mode enter VLPS mode succeed */
+    if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+status_t SMC_SetPowerModeLls(SMC_Type *base
+#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
+     (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO))
+                             ,
+                             const smc_power_mode_lls_config_t *config
+#endif
+                             )
+{
+    uint8_t reg;
+
+    /* configure to LLS mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+/* configure LLS sub-mode*/
+#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+    reg = base->STOPCTRL;
+    reg &= ~SMC_STOPCTRL_LLSM_MASK;
+    reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
+    base->STOPCTRL = reg;
+#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
+
+#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+    if (config->enableLpoClock)
+    {
+        base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK;
+    }
+    else
+    {
+        base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK;
+    }
+#endif /* FSL_FEATURE_SMC_HAS_LPOPO */
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+    /* check whether the power mode enter LLS mode succeed */
+    if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+}
+#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config)
+{
+    uint8_t reg;
+
+#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO)
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) ||     \
+    (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \
+    (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+    if (config->subMode == kSMC_StopSub0)
+#endif
+    {
+        /* configure whether the Por Detect work in Vlls0 mode */
+        if (config->enablePorDetectInVlls0)
+        {
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+            base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK;
+#else
+            base->STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK;
+#endif
+        }
+        else
+        {
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+            base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK;
+#else
+            base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK;
+#endif
+        }
+    }
+#endif /* FSL_FEATURE_SMC_HAS_PORPO */
+
+#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION)
+    else if (config->subMode == kSMC_StopSub2)
+    {
+        /* configure whether the Por Detect work in Vlls0 mode */
+        if (config->enableRam2InVlls2)
+        {
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+            base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK;
+#else
+            base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK;
+#endif
+        }
+        else
+        {
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+            base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK;
+#else
+            base->STOPCTRL &= ~SMC_STOPCTRL_RAM2PO_MASK;
+#endif
+        }
+    }
+    else
+    {
+    }
+#endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */
+
+    /* configure to VLLS mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+/* configure the VLLS sub-mode */
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
+    reg = base->VLLSCTRL;
+    reg &= ~SMC_VLLSCTRL_VLLSM_MASK;
+    reg |= ((uint32_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT);
+    base->VLLSCTRL = reg;
+#else
+#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+    reg = base->STOPCTRL;
+    reg &= ~SMC_STOPCTRL_LLSM_MASK;
+    reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
+    base->STOPCTRL = reg;
+#else
+    reg = base->STOPCTRL;
+    reg &= ~SMC_STOPCTRL_VLLSM_MASK;
+    reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT);
+    base->STOPCTRL = reg;
+#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
+#endif
+
+#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+    if (config->enableLpoClock)
+    {
+        base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK;
+    }
+    else
+    {
+        base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK;
+    }
+#endif /* FSL_FEATURE_SMC_HAS_LPOPO */
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+    /* check whether the power mode enter LLS mode succeed */
+    if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+}
+#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smc.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smc.h
new file mode 100644
index 00000000000..4148734a2a4
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_smc.h
@@ -0,0 +1,418 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_SMC_H_
+#define _FSL_SMC_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup smc */
+/*! @{ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief SMC driver version 2.0.2. */
+#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*!
+ * @brief Power Modes Protection
+ */
+typedef enum _smc_power_mode_protection
+{
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+    kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-Low-Leakage Stop Mode. */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+    kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-Leakage Stop Mode.      */
+#endif                                             /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+    kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-Power Mode.        */
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+    kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode.        */
+#endif                                                 /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+    kSMC_AllowPowerModeAll = (0U
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+                              |
+                              SMC_PMPROT_AVLLS_MASK
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+                              |
+                              SMC_PMPROT_ALLS_MASK
+#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+                              |
+                              SMC_PMPROT_AVLP_MASK
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+                              |
+                              kSMC_AllowPowerModeHsrun
+#endif                          /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+                              ) /*!< Allow all power mode.              */
+} smc_power_mode_protection_t;
+
+/*!
+ * @brief Power Modes in PMSTAT
+ */
+typedef enum _smc_power_state
+{
+    kSMC_PowerStateRun = 0x01U << 0U,  /*!< 0000_0001 - Current power mode is RUN   */
+    kSMC_PowerStateStop = 0x01U << 1U, /*!< 0000_0010 - Current power mode is STOP  */
+    kSMC_PowerStateVlpr = 0x01U << 2U, /*!< 0000_0100 - Current power mode is VLPR  */
+    kSMC_PowerStateVlpw = 0x01U << 3U, /*!< 0000_1000 - Current power mode is VLPW  */
+    kSMC_PowerStateVlps = 0x01U << 4U, /*!< 0001_0000 - Current power mode is VLPS  */
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+    kSMC_PowerStateLls = 0x01U << 5U, /*!< 0010_0000 - Current power mode is LLS   */
+#endif                                /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+    kSMC_PowerStateVlls = 0x01U << 6U, /*!< 0100_0000 - Current power mode is VLLS  */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+    kSMC_PowerStateHsrun = 0x01U << 7U /*!< 1000_0000 - Current power mode is HSRUN */
+#endif                                 /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+} smc_power_state_t;
+
+/*!
+ * @brief Run mode definition
+ */
+typedef enum _smc_run_mode
+{
+    kSMC_RunNormal = 0U, /*!< normal RUN mode.             */
+    kSMC_RunVlpr = 2U,   /*!< Very-Low-Power RUN mode.     */
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+    kSMC_Hsrun = 3U /*!< High Speed Run mode (HSRUN). */
+#endif              /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+} smc_run_mode_t;
+
+/*!
+ * @brief Stop mode definition
+ */
+typedef enum _smc_stop_mode
+{
+    kSMC_StopNormal = 0U, /*!< Normal STOP mode.           */
+    kSMC_StopVlps = 2U,   /*!< Very-Low-Power STOP mode.   */
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+    kSMC_StopLls = 3U, /*!< Low-Leakage Stop mode.      */
+#endif                 /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+    kSMC_StopVlls = 4U /*!< Very-Low-Leakage Stop mode. */
+#endif
+} smc_stop_mode_t;
+
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) ||     \
+    (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \
+    (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+/*!
+ * @brief VLLS/LLS stop sub mode definition
+ */
+typedef enum _smc_stop_submode
+{
+    kSMC_StopSub0 = 0U, /*!< Stop submode 0, for VLLS0/LLS0. */
+    kSMC_StopSub1 = 1U, /*!< Stop submode 1, for VLLS1/LLS1. */
+    kSMC_StopSub2 = 2U, /*!< Stop submode 2, for VLLS2/LLS2. */
+    kSMC_StopSub3 = 3U  /*!< Stop submode 3, for VLLS3/LLS3. */
+} smc_stop_submode_t;
+#endif
+
+/*!
+ * @brief Partial STOP option
+ */
+typedef enum _smc_partial_stop_mode
+{
+    kSMC_PartialStop = 0U,  /*!< STOP - Normal Stop mode*/
+    kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/
+    kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/
+} smc_partial_stop_option_t;
+
+/*!
+ * @brief SMC configuration status
+ */
+enum _smc_status
+{
+    kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0) /*!< Entering Stop mode is abort*/
+};
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID)
+/*!
+ * @brief IP version ID definition.
+ */
+typedef struct _smc_version_id
+{
+    uint16_t feature; /*!< Feature Specification Number. */
+    uint8_t minor;    /*!< Minor version number.         */
+    uint8_t major;    /*!< Major version number.         */
+} smc_version_id_t;
+#endif /* FSL_FEATURE_SMC_HAS_VERID */
+
+#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
+/*!
+ * @brief IP parameter definition.
+ */
+typedef struct _smc_param
+{
+    bool hsrunEnable; /*!< HSRUN mode enable. */
+    bool llsEnable;   /*!< LLS mode enable.   */
+    bool lls2Enable;  /*!< LLS2 mode enable.  */
+    bool vlls0Enable; /*!< VLLS0 mode enable. */
+} smc_param_t;
+#endif /* FSL_FEATURE_SMC_HAS_PARAM */
+
+#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
+    (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+/*!
+ * @brief SMC Low-Leakage Stop power mode config
+ */
+typedef struct _smc_power_mode_lls_config
+{
+#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+    smc_stop_submode_t subMode; /*!< Low-leakage Stop sub-mode */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+    bool enableLpoClock; /*!< Enable LPO clock in LLS mode */
+#endif
+} smc_power_mode_lls_config_t;
+#endif /* (FSL_FEATURE_SMC_HAS_LLS_SUBMODE || FSL_FEATURE_SMC_HAS_LPOPO) */
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+/*!
+ * @brief SMC Very Low-Leakage Stop power mode config
+ */
+typedef struct _smc_power_mode_vlls_config
+{
+#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) ||     \
+    (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \
+    (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
+    smc_stop_submode_t subMode; /*!< Very Low-leakage Stop sub-mode */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO)
+    bool enablePorDetectInVlls0; /*!< Enable Power on reset detect in VLLS mode */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION)
+    bool enableRam2InVlls2; /*!< Enable RAM2 power in VLLS2 */
+#endif
+#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
+    bool enableLpoClock; /*!< Enable LPO clock in VLLS mode */
+#endif
+} smc_power_mode_vlls_config_t;
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name System mode controller APIs*/
+/*@{*/
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID)
+/*!
+ * @brief Gets the SMC version ID.
+ *
+ * This function gets the SMC version ID, including major version number,
+ * minor version number and feature specification number.
+ *
+ * @param base SMC peripheral base address.
+ * @param versionId     Pointer to version ID structure.
+ */
+static inline void SMC_GetVersionId(SMC_Type *base, smc_version_id_t *versionId)
+{
+    *((uint32_t *)versionId) = base->VERID;
+}
+#endif /* FSL_FEATURE_SMC_HAS_VERID */
+
+#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
+/*!
+ * @brief Gets the SMC parameter.
+ *
+ * This function gets the SMC parameter, including the enabled power mdoes.
+ *
+ * @param base SMC peripheral base address.
+ * @param param         Pointer to SMC param structure.
+ */
+void SMC_GetParam(SMC_Type *base, smc_param_t *param);
+#endif
+
+/*!
+ * @brief Configures all power mode protection settings.
+ *
+ * This function  configures the power mode protection settings for
+ * supported power modes in the specified chip family. The available power modes
+ * are defined in the smc_power_mode_protection_t. This should be done at an early
+ * system level initialization stage. See the reference manual for details.
+ * This register can only write once after the power reset.
+ *
+ * The allowed modes are passed as bit map, for example, to allow LLS and VLLS,
+ * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeVlls | kSMC_AllowPowerModeVlps).
+ * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll).
+ *
+ * @param base SMC peripheral base address.
+ * @param allowedModes Bitmap of the allowed power modes.
+ */
+static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes)
+{
+    base->PMPROT = allowedModes;
+}
+
+/*!
+ * @brief Gets the current power mode status.
+ *
+ * This function  returns the current power mode stat. Once application
+ * switches the power mode, it should always check the stat to check whether it
+ * runs into the specified mode or not. An application  should  check
+ * this mode before switching to a different mode. The system  requires that
+ * only certain modes can switch to other specific modes. See the
+ * reference manual for details and the smc_power_state_t for information about
+ * the power stat.
+ *
+ * @param base SMC peripheral base address.
+ * @return Current power mode status.
+ */
+static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base)
+{
+    return (smc_power_state_t)base->PMSTAT;
+}
+
+/*!
+ * @brief Configure the system to RUN power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeRun(SMC_Type *base);
+
+#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
+/*!
+ * @brief Configure the system to HSRUN power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeHsrun(SMC_Type *base);
+#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
+
+/*!
+ * @brief Configure the system to WAIT power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeWait(SMC_Type *base);
+
+/*!
+ * @brief Configure the system to Stop power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param  option Partial Stop mode option.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option);
+
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+/*!
+ * @brief Configure the system to VLPR power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param  wakeupMode Enter Normal Run mode if true, else stay in VLPR mode.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpr(SMC_Type *base, bool wakeupMode);
+#else
+/*!
+ * @brief Configure the system to VLPR power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpr(SMC_Type *base);
+#endif /* FSL_FEATURE_SMC_HAS_LPWUI */
+
+/*!
+ * @brief Configure the system to VLPW power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpw(SMC_Type *base);
+
+/*!
+ * @brief Configure the system to VLPS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlps(SMC_Type *base);
+
+#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
+#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
+     (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO))
+/*!
+ * @brief Configure the system to LLS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param  config The LLS power mode configuration structure
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeLls(SMC_Type *base, const smc_power_mode_lls_config_t *config);
+#else
+/*!
+ * @brief Configure the system to LLS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeLls(SMC_Type *base);
+#endif
+#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
+
+#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
+/*!
+ * @brief Configure the system to VLLS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param  config The VLLS power mode configuration structure.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config);
+#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_SMC_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tpm.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tpm.c
new file mode 100644
index 00000000000..0571adbf638
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tpm.c
@@ -0,0 +1,729 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_tpm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define TPM_COMBINE_SHIFT (8U)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base TPM peripheral base address
+ *
+ * @return The TPM instance
+ */
+static uint32_t TPM_GetInstance(TPM_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to TPM bases for each instance. */
+static TPM_Type *const s_tpmBases[] = TPM_BASE_PTRS;
+
+/*! @brief Pointers to TPM clocks for each instance. */
+static const clock_ip_name_t s_tpmClocks[] = TPM_CLOCKS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t TPM_GetInstance(TPM_Type *base)
+{
+    uint32_t instance;
+    uint32_t tpmArrayCount = (sizeof(s_tpmBases) / sizeof(s_tpmBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < tpmArrayCount; instance++)
+    {
+        if (s_tpmBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < tpmArrayCount);
+
+    return instance;
+}
+
+void TPM_Init(TPM_Type *base, const tpm_config_t *config)
+{
+    assert(config);
+
+    /* Enable the module clock */
+    CLOCK_EnableClock(s_tpmClocks[TPM_GetInstance(base)]);
+
+#if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL
+    /* TPM reset is available on certain SoC's */
+    TPM_Reset(base);
+#endif
+
+    /* Set the clock prescale factor */
+    base->SC = TPM_SC_PS(config->prescale);
+
+    /* Setup the counter operation */
+    base->CONF = TPM_CONF_DOZEEN(config->enableDoze) |
+                 TPM_CONF_GTBEEN(config->useGlobalTimeBase) | TPM_CONF_CROT(config->enableReloadOnTrigger) |
+                 TPM_CONF_CSOT(config->enableStartOnTrigger) | TPM_CONF_CSOO(config->enableStopOnOverflow) |
+#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
+                 TPM_CONF_CPOT(config->enablePauseOnTrigger) |
+#endif
+#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
+                 TPM_CONF_TRGSRC(config->triggerSource) |
+#endif
+                 TPM_CONF_TRGSEL(config->triggerSelect);
+    if (config->enableDebugMode)
+    {
+        base->CONF |= TPM_CONF_DBGMODE_MASK;
+    }
+    else
+    {
+        base->CONF &= ~TPM_CONF_DBGMODE_MASK;
+    }
+}
+
+void TPM_Deinit(TPM_Type *base)
+{
+    /* Stop the counter */
+    base->SC &= ~TPM_SC_CMOD_MASK;
+    /* Gate the TPM clock */
+    CLOCK_DisableClock(s_tpmClocks[TPM_GetInstance(base)]);
+}
+
+void TPM_GetDefaultConfig(tpm_config_t *config)
+{
+    assert(config);
+
+    /* TPM clock divide by 1 */
+    config->prescale = kTPM_Prescale_Divide_1;
+    /* Use internal TPM counter as timebase */
+    config->useGlobalTimeBase = false;
+    /* TPM counter continues in doze mode */
+    config->enableDoze = false;
+    /* TPM counter pauses when in debug mode */
+    config->enableDebugMode = false;
+    /* TPM counter will not be reloaded on input trigger */
+    config->enableReloadOnTrigger = false;
+    /* TPM counter continues running after overflow */
+    config->enableStopOnOverflow = false;
+    /* TPM counter starts immediately once it is enabled */
+    config->enableStartOnTrigger = false;
+#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
+    config->enablePauseOnTrigger = false;
+#endif
+    /* Choose trigger select 0 as input trigger for controlling counter operation */
+    config->triggerSelect = kTPM_Trigger_Select_0;
+#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
+    /* Choose external trigger source to control counter operation */
+    config->triggerSource = kTPM_TriggerSource_External;
+#endif
+}
+
+status_t TPM_SetupPwm(TPM_Type *base,
+                      const tpm_chnl_pwm_signal_param_t *chnlParams,
+                      uint8_t numOfChnls,
+                      tpm_pwm_mode_t mode,
+                      uint32_t pwmFreq_Hz,
+                      uint32_t srcClock_Hz)
+{
+    assert(chnlParams);
+    assert(pwmFreq_Hz);
+    assert(numOfChnls);
+    assert(srcClock_Hz);
+
+    uint32_t mod;
+    uint32_t tpmClock = (srcClock_Hz / (1U << (base->SC & TPM_SC_PS_MASK)));
+    uint16_t cnv;
+    uint8_t i;
+
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+    /* Clear quadrature Decoder mode because in quadrature Decoder mode PWM doesn't operate*/
+    base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+#endif
+
+    switch (mode)
+    {
+        case kTPM_EdgeAlignedPwm:
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+        case kTPM_CombinedPwm:
+#endif
+            base->SC &= ~TPM_SC_CPWMS_MASK;
+            mod = (tpmClock / pwmFreq_Hz) - 1;
+            break;
+        case kTPM_CenterAlignedPwm:
+            base->SC |= TPM_SC_CPWMS_MASK;
+            mod = tpmClock / (pwmFreq_Hz * 2);
+            break;
+        default:
+            return kStatus_Fail;
+    }
+
+    /* Return an error in case we overflow the registers, probably would require changing
+     * clock source to get the desired frequency */
+    if (mod > 65535U)
+    {
+        return kStatus_Fail;
+    }
+    /* Set the PWM period */
+    base->MOD = mod;
+
+    /* Setup each TPM channel */
+    for (i = 0; i < numOfChnls; i++)
+    {
+        /* Return error if requested dutycycle is greater than the max allowed */
+        if (chnlParams->dutyCyclePercent > 100)
+        {
+            return kStatus_Fail;
+        }
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+        if (mode == kTPM_CombinedPwm)
+        {
+            uint16_t cnvFirstEdge;
+
+            /* This check is added for combined mode as the channel number should be the pair number */
+            if (chnlParams->chnlNumber >= (FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2))
+            {
+                return kStatus_Fail;
+            }
+
+            /* Return error if requested value is greater than the max allowed */
+            if (chnlParams->firstEdgeDelayPercent > 100)
+            {
+                return kStatus_Fail;
+            }
+            /* Configure delay of the first edge */
+            if (chnlParams->firstEdgeDelayPercent == 0)
+            {
+                /* No delay for the first edge */
+                cnvFirstEdge = 0;
+            }
+            else
+            {
+                cnvFirstEdge = (mod * chnlParams->firstEdgeDelayPercent) / 100;
+            }
+            /* Configure dutycycle */
+            if (chnlParams->dutyCyclePercent == 0)
+            {
+                /* Signal stays low */
+                cnv = 0;
+                cnvFirstEdge = 0;
+            }
+            else
+            {
+                cnv = (mod * chnlParams->dutyCyclePercent) / 100;
+                /* For 100% duty cycle */
+                if (cnv >= mod)
+                {
+                    cnv = mod + 1;
+                }
+            }
+
+            /* Set the combine bit for the channel pair */
+            base->COMBINE |= (1U << (TPM_COMBINE_COMBINE0_SHIFT + (TPM_COMBINE_SHIFT * chnlParams->chnlNumber)));
+
+            /* When switching mode, disable channel n first */
+            base->CONTROLS[chnlParams->chnlNumber * 2].CnSC &=
+                ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+
+            /* Wait till mode change to disable channel is acknowledged */
+            while ((base->CONTROLS[chnlParams->chnlNumber * 2].CnSC &
+                    (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+            {
+            }
+
+            /* Set the requested PWM mode for channel n, PWM output requires mode select to be set to 2 */
+            base->CONTROLS[chnlParams->chnlNumber * 2].CnSC |=
+                ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT));
+
+            /* Wait till mode change is acknowledged */
+            while (!(base->CONTROLS[chnlParams->chnlNumber * 2].CnSC &
+                     (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+            {
+            }
+            /* Set the channel pair values */
+            base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge;
+
+            /* When switching mode, disable channel n + 1 first */
+            base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC &=
+                ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+
+            /* Wait till mode change to disable channel is acknowledged */
+            while ((base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC &
+                    (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+            {
+            }
+
+            /* Set the requested PWM mode for channel n + 1, PWM output requires mode select to be set to 2 */
+            base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC |=
+                ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT));
+
+            /* Wait till mode change is acknowledged */
+            while (!(base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC &
+                     (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+            {
+            }
+            /* Set the channel pair values */
+            base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv;
+        }
+        else
+        {
+#endif
+            if (chnlParams->dutyCyclePercent == 0)
+            {
+                /* Signal stays low */
+                cnv = 0;
+            }
+            else
+            {
+                cnv = (mod * chnlParams->dutyCyclePercent) / 100;
+                /* For 100% duty cycle */
+                if (cnv >= mod)
+                {
+                    cnv = mod + 1;
+                }
+            }
+
+            /* When switching mode, disable channel first */
+            base->CONTROLS[chnlParams->chnlNumber].CnSC &=
+                ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+
+            /* Wait till mode change to disable channel is acknowledged */
+            while ((base->CONTROLS[chnlParams->chnlNumber].CnSC &
+                    (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+            {
+            }
+
+            /* Set the requested PWM mode, PWM output requires mode select to be set to 2 */
+            base->CONTROLS[chnlParams->chnlNumber].CnSC |=
+                ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT));
+
+            /* Wait till mode change is acknowledged */
+            while (!(base->CONTROLS[chnlParams->chnlNumber].CnSC &
+                     (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+            {
+            }
+            base->CONTROLS[chnlParams->chnlNumber].CnV = cnv;
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+        }
+#endif
+
+        chnlParams++;
+    }
+
+    return kStatus_Success;
+}
+
+void TPM_UpdatePwmDutycycle(TPM_Type *base,
+                            tpm_chnl_t chnlNumber,
+                            tpm_pwm_mode_t currentPwmMode,
+                            uint8_t dutyCyclePercent)
+{
+    assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base));
+
+    uint16_t cnv, mod;
+
+    mod = base->MOD;
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    if (currentPwmMode == kTPM_CombinedPwm)
+    {
+        uint16_t cnvFirstEdge;
+
+        /* This check is added for combined mode as the channel number should be the pair number */
+        if (chnlNumber >= (FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2))
+        {
+            return;
+        }
+        cnv = (mod * dutyCyclePercent) / 100;
+        cnvFirstEdge = base->CONTROLS[chnlNumber * 2].CnV;
+        /* For 100% duty cycle */
+        if (cnv >= mod)
+        {
+            cnv = mod + 1;
+        }
+        base->CONTROLS[(chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv;
+    }
+    else
+    {
+#endif
+        cnv = (mod * dutyCyclePercent) / 100;
+        /* For 100% duty cycle */
+        if (cnv >= mod)
+        {
+            cnv = mod + 1;
+        }
+        base->CONTROLS[chnlNumber].CnV = cnv;
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    }
+#endif
+}
+
+void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level)
+{
+    assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base));
+
+    uint32_t reg = base->CONTROLS[chnlNumber].CnSC & ~(TPM_CnSC_CHF_MASK);
+
+    /* When switching mode, disable channel first  */
+    base->CONTROLS[chnlNumber].CnSC &=
+        ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+
+    /* Wait till mode change to disable channel is acknowledged */
+    while ((base->CONTROLS[chnlNumber].CnSC &
+            (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+    {
+    }
+
+    /* Clear the field and write the new level value */
+    reg &= ~(TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+    reg |= ((uint32_t)level << TPM_CnSC_ELSA_SHIFT) & (TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+
+    base->CONTROLS[chnlNumber].CnSC = reg;
+
+    /* Wait till mode change is acknowledged */
+    reg &= (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+    while (reg != (base->CONTROLS[chnlNumber].CnSC &
+                   (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+    {
+    }
+}
+
+void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode)
+{
+    assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base));
+
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+    /* Clear quadrature Decoder mode for channel 0 or 1*/
+    if (chnlNumber == 0 || chnlNumber == 1)
+    {
+        base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+    }
+#endif
+
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    /* Clear the combine bit for chnlNumber */
+    base->COMBINE &= ~(1U << TPM_COMBINE_COMBINE1_SHIFT *(chnlNumber/2));
+#endif
+
+    /* When switching mode, disable channel first  */
+    base->CONTROLS[chnlNumber].CnSC &=
+        ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+
+    /* Wait till mode change to disable channel is acknowledged */
+    while ((base->CONTROLS[chnlNumber].CnSC &
+            (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+    {
+    }
+
+    /* Set the requested input capture mode */
+    base->CONTROLS[chnlNumber].CnSC |= captureMode;
+
+    /* Wait till mode change is acknowledged */
+    while (!(base->CONTROLS[chnlNumber].CnSC &
+             (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+    {
+    }
+}
+
+void TPM_SetupOutputCompare(TPM_Type *base,
+                            tpm_chnl_t chnlNumber,
+                            tpm_output_compare_mode_t compareMode,
+                            uint32_t compareValue)
+{
+    assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base));
+
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+    /* Clear quadrature Decoder mode for channel 0 or 1 */
+    if (chnlNumber == 0 || chnlNumber == 1)
+    {
+        base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+    }
+#endif
+
+    /* When switching mode, disable channel first  */
+    base->CONTROLS[chnlNumber].CnSC &=
+        ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+
+    /* Wait till mode change to disable channel is acknowledged */
+    while ((base->CONTROLS[chnlNumber].CnSC &
+            (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+    {
+    }
+
+    /* Setup the channel output behaviour when a match occurs with the compare value */
+    base->CONTROLS[chnlNumber].CnSC |= compareMode;
+
+    /* Setup the compare value */
+    base->CONTROLS[chnlNumber].CnV = compareValue;
+
+    /* Wait till mode change is acknowledged */
+    while (!(base->CONTROLS[chnlNumber].CnSC &
+             (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+    {
+    }
+}
+
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+void TPM_SetupDualEdgeCapture(TPM_Type *base,
+                              tpm_chnl_t chnlPairNumber,
+                              const tpm_dual_edge_capture_param_t *edgeParam,
+                              uint32_t filterValue)
+{
+    assert(edgeParam);
+    assert(chnlPairNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)/2);
+
+    uint32_t reg;
+    /* Clear quadrature Decoder mode for channel 0 or 1*/
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+    if (chnlPairNumber == 0)
+    {
+        base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+    }
+#endif
+
+    /* Unlock: When switching mode, disable channel first */
+    base->CONTROLS[chnlPairNumber * 2].CnSC &=
+        ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+
+    /* Wait till mode change to disable channel is acknowledged */
+    while ((base->CONTROLS[chnlPairNumber * 2].CnSC &
+            (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+    {
+    }
+
+    base->CONTROLS[chnlPairNumber * 2 + 1].CnSC &=
+        ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+
+    /* Wait till mode change to disable channel is acknowledged */
+    while ((base->CONTROLS[chnlPairNumber * 2 + 1].CnSC &
+            (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+    {
+    }
+
+    /* Now, the registers for input mode can be operated. */
+    if (edgeParam->enableSwap)
+    {
+        /* Set the combine and swap bits for the channel pair */
+        base->COMBINE |= (TPM_COMBINE_COMBINE0_MASK | TPM_COMBINE_COMSWAP0_MASK)
+                         << (TPM_COMBINE_SHIFT * chnlPairNumber);
+
+        /* Input filter setup for channel n+1 input */
+        reg = base->FILTER;
+        reg &= ~(TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * (chnlPairNumber + 1)));
+        reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * (chnlPairNumber + 1)));
+        base->FILTER = reg;
+    }
+    else
+    {
+        reg = base->COMBINE;
+        /* Clear the swap bit for the channel pair */
+        reg &= ~(TPM_COMBINE_COMSWAP0_MASK << (TPM_COMBINE_COMSWAP0_SHIFT * chnlPairNumber));
+
+        /* Set the combine bit for the channel pair */
+        reg |= TPM_COMBINE_COMBINE0_MASK << (TPM_COMBINE_SHIFT * chnlPairNumber);
+        base->COMBINE = reg;
+
+        /* Input filter setup for channel n input */
+        reg = base->FILTER;
+        reg &= ~(TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * chnlPairNumber));
+        reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * chnlPairNumber));
+        base->FILTER = reg;
+    }
+
+    /* Setup the edge detection from channel n */
+    base->CONTROLS[chnlPairNumber * 2].CnSC |= edgeParam->currChanEdgeMode;
+
+    /* Wait till mode change is acknowledged */
+    while (!(base->CONTROLS[chnlPairNumber * 2].CnSC &
+             (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+    {
+    }
+
+    /* Setup the edge detection from channel n+1 */
+    base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC |= edgeParam->nextChanEdgeMode;
+
+    /* Wait till mode change is acknowledged */
+    while (!(base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC &
+             (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+    {
+    }
+}
+#endif
+
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+void TPM_SetupQuadDecode(TPM_Type *base,
+                         const tpm_phase_params_t *phaseAParams,
+                         const tpm_phase_params_t *phaseBParams,
+                         tpm_quad_decode_mode_t quadMode)
+{
+    assert(phaseAParams);
+    assert(phaseBParams);
+
+    base->CONTROLS[0].CnSC &=
+                ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+
+    /* Wait till mode change to disable channel is acknowledged */
+    while ((base->CONTROLS[0].CnSC &
+                    (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+    {
+    }
+    uint32_t reg;
+
+    /* Set Phase A filter value */
+    reg = base->FILTER;
+    reg &= ~(TPM_FILTER_CH0FVAL_MASK);
+    reg |= TPM_FILTER_CH0FVAL(phaseAParams->phaseFilterVal);
+    base->FILTER = reg;
+
+#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL
+    /* Set Phase A polarity */
+    if (phaseAParams->phasePolarity)
+    {
+        base->POL |= TPM_POL_POL0_MASK;
+    }
+    else
+    {
+        base->POL &= ~TPM_POL_POL0_MASK;
+    }
+#endif
+
+    base->CONTROLS[1].CnSC &=
+                ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
+
+    /* Wait till mode change to disable channel is acknowledged */
+    while ((base->CONTROLS[1].CnSC &
+                    (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+    {
+    }
+    /* Set Phase B filter value */
+    reg = base->FILTER;
+    reg &= ~(TPM_FILTER_CH1FVAL_MASK);
+    reg |= TPM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal);
+    base->FILTER = reg;
+#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL
+    /* Set Phase B polarity */
+    if (phaseBParams->phasePolarity)
+    {
+        base->POL |= TPM_POL_POL1_MASK;
+    }
+    else
+    {
+        base->POL &= ~TPM_POL_POL1_MASK;
+    }
+#endif
+
+    /* Set Quadrature mode */
+    reg = base->QDCTRL;
+    reg &= ~(TPM_QDCTRL_QUADMODE_MASK);
+    reg |= TPM_QDCTRL_QUADMODE(quadMode);
+    base->QDCTRL = reg;
+
+    /* Enable Quad decode */
+    base->QDCTRL |= TPM_QDCTRL_QUADEN_MASK;
+}
+
+#endif
+
+void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask)
+{
+    uint32_t chnlInterrupts = (mask & 0xFF);
+    uint8_t chnlNumber = 0;
+
+    /* Enable the timer overflow interrupt */
+    if (mask & kTPM_TimeOverflowInterruptEnable)
+    {
+        base->SC |= TPM_SC_TOIE_MASK;
+    }
+
+    /* Enable the channel interrupts */
+    while (chnlInterrupts)
+    {
+        if (chnlInterrupts & 0x1)
+        {
+            base->CONTROLS[chnlNumber].CnSC |= TPM_CnSC_CHIE_MASK;
+        }
+        chnlNumber++;
+        chnlInterrupts = chnlInterrupts >> 1U;
+    }
+}
+
+void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask)
+{
+    uint32_t chnlInterrupts = (mask & 0xFF);
+    uint8_t chnlNumber = 0;
+
+    /* Disable the timer overflow interrupt */
+    if (mask & kTPM_TimeOverflowInterruptEnable)
+    {
+        base->SC &= ~TPM_SC_TOIE_MASK;
+    }
+
+    /* Disable the channel interrupts */
+    while (chnlInterrupts)
+    {
+        if (chnlInterrupts & 0x1)
+        {
+            base->CONTROLS[chnlNumber].CnSC &= ~TPM_CnSC_CHIE_MASK;
+        }
+        chnlNumber++;
+        chnlInterrupts = chnlInterrupts >> 1U;
+    }
+}
+
+uint32_t TPM_GetEnabledInterrupts(TPM_Type *base)
+{
+    uint32_t enabledInterrupts = 0;
+    int8_t chnlCount = FSL_FEATURE_TPM_CHANNEL_COUNTn(base);
+
+    /* The CHANNEL_COUNT macro returns -1 if it cannot match the TPM instance */
+    assert(chnlCount != -1);
+
+    /* Check if timer overflow interrupt is enabled */
+    if (base->SC & TPM_SC_TOIE_MASK)
+    {
+        enabledInterrupts |= kTPM_TimeOverflowInterruptEnable;
+    }
+
+    /* Check if the channel interrupts are enabled */
+    while (chnlCount > 0)
+    {
+        chnlCount--;
+        if (base->CONTROLS[chnlCount].CnSC & TPM_CnSC_CHIE_MASK)
+        {
+            enabledInterrupts |= (1U << chnlCount);
+        }
+    }
+
+    return enabledInterrupts;
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tpm.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tpm.h
new file mode 100644
index 00000000000..e83a92ab52d
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tpm.h
@@ -0,0 +1,589 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_TPM_H_
+#define _FSL_TPM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup tpm
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_TPM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */
+/*@}*/
+
+/*!
+ * @brief List of TPM channels.
+ * @note Actual number of available channels is SoC dependent
+ */
+typedef enum _tpm_chnl
+{
+    kTPM_Chnl_0 = 0U, /*!< TPM channel number 0*/
+    kTPM_Chnl_1,      /*!< TPM channel number 1 */
+    kTPM_Chnl_2,      /*!< TPM channel number 2 */
+    kTPM_Chnl_3,      /*!< TPM channel number 3 */
+    kTPM_Chnl_4,      /*!< TPM channel number 4 */
+    kTPM_Chnl_5,      /*!< TPM channel number 5 */
+    kTPM_Chnl_6,      /*!< TPM channel number 6 */
+    kTPM_Chnl_7       /*!< TPM channel number 7 */
+} tpm_chnl_t;
+
+/*! @brief TPM PWM operation modes */
+typedef enum _tpm_pwm_mode
+{
+    kTPM_EdgeAlignedPwm = 0U, /*!< Edge aligned PWM */
+    kTPM_CenterAlignedPwm,    /*!< Center aligned PWM */
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    kTPM_CombinedPwm /*!< Combined PWM */
+#endif
+} tpm_pwm_mode_t;
+
+/*! @brief TPM PWM output pulse mode: high-true, low-true or no output */
+typedef enum _tpm_pwm_level_select
+{
+    kTPM_NoPwmSignal = 0U, /*!< No PWM output on pin */
+    kTPM_LowTrue,          /*!< Low true pulses */
+    kTPM_HighTrue          /*!< High true pulses */
+} tpm_pwm_level_select_t;
+
+/*! @brief Options to configure a TPM channel's PWM signal */
+typedef struct _tpm_chnl_pwm_signal_param
+{
+    tpm_chnl_t chnlNumber;        /*!< TPM channel to configure.
+                                       In combined mode (available in some SoC's, this represents the
+                                       channel pair number */
+    tpm_pwm_level_select_t level; /*!< PWM output active level select */
+    uint8_t dutyCyclePercent;     /*!< PWM pulse width, value should be between 0 to 100
+                                       0=inactive signal(0% duty cycle)...
+                                       100=always active signal (100% duty cycle)*/
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM.
+                                        Specifies the delay to the first edge in a PWM period.
+                                        If unsure, leave as 0; Should be specified as
+                                        percentage of the PWM period */
+#endif
+} tpm_chnl_pwm_signal_param_t;
+
+/*!
+ * @brief Trigger options available.
+ *
+ * This is used for both internal & external trigger sources (external option available in certain SoC's)
+ *
+ * @note The actual trigger options available is SoC-specific.
+ */
+typedef enum _tpm_trigger_select
+{
+    kTPM_Trigger_Select_0 = 0U,
+    kTPM_Trigger_Select_1,
+    kTPM_Trigger_Select_2,
+    kTPM_Trigger_Select_3,
+    kTPM_Trigger_Select_4,
+    kTPM_Trigger_Select_5,
+    kTPM_Trigger_Select_6,
+    kTPM_Trigger_Select_7,
+    kTPM_Trigger_Select_8,
+    kTPM_Trigger_Select_9,
+    kTPM_Trigger_Select_10,
+    kTPM_Trigger_Select_11,
+    kTPM_Trigger_Select_12,
+    kTPM_Trigger_Select_13,
+    kTPM_Trigger_Select_14,
+    kTPM_Trigger_Select_15
+} tpm_trigger_select_t;
+
+#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
+/*!
+ * @brief Trigger source options available
+ *
+ * @note This selection is available only on some SoC's. For SoC's without this selection, the only
+ * trigger source available is internal triger.
+ */
+typedef enum _tpm_trigger_source
+{
+    kTPM_TriggerSource_External = 0U, /*!< Use external trigger input */
+    kTPM_TriggerSource_Internal       /*!< Use internal trigger */
+} tpm_trigger_source_t;
+#endif
+
+/*! @brief TPM output compare modes */
+typedef enum _tpm_output_compare_mode
+{
+    kTPM_NoOutputSignal = (1U << TPM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV  */
+    kTPM_ToggleOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)),   /*!< Toggle output */
+    kTPM_ClearOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)),    /*!< Clear output */
+    kTPM_SetOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (3U << TPM_CnSC_ELSA_SHIFT)),      /*!< Set output */
+    kTPM_HighPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Pulse output high */
+    kTPM_LowPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT))   /*!< Pulse output low */
+} tpm_output_compare_mode_t;
+
+/*! @brief TPM input capture edge */
+typedef enum _tpm_input_capture_edge
+{
+    kTPM_RisingEdge = (1U << TPM_CnSC_ELSA_SHIFT),     /*!< Capture on rising edge only */
+    kTPM_FallingEdge = (2U << TPM_CnSC_ELSA_SHIFT),    /*!< Capture on falling edge only */
+    kTPM_RiseAndFallEdge = (3U << TPM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */
+} tpm_input_capture_edge_t;
+
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+/*!
+ * @brief TPM dual edge capture parameters
+ *
+ * @note This mode is available only on some SoC's.
+ */
+typedef struct _tpm_dual_edge_capture_param
+{
+    bool enableSwap;                           /*!< true: Use channel n+1 input, channel n input is ignored;
+                                                    false: Use channel n input, channel n+1 input is ignored */
+    tpm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */
+    tpm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */
+} tpm_dual_edge_capture_param_t;
+#endif
+
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+/*!
+ * @brief TPM quadrature decode modes
+ *
+ * @note This mode is available only on some SoC's.
+ */
+typedef enum _tpm_quad_decode_mode
+{
+    kTPM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */
+    kTPM_QuadCountAndDir       /*!< Count and direction encoding mode */
+} tpm_quad_decode_mode_t;
+
+/*! @brief TPM quadrature phase polarities */
+typedef enum _tpm_phase_polarity
+{
+    kTPM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */
+    kTPM_QuadPhaseInvert       /*!< Phase input signal is inverted */
+} tpm_phase_polarity_t;
+
+/*! @brief TPM quadrature decode phase parameters */
+typedef struct _tpm_phase_param
+{
+    uint32_t phaseFilterVal;            /*!< Filter value, filter is disabled when the value is zero */
+    tpm_phase_polarity_t phasePolarity; /*!< Phase polarity */
+} tpm_phase_params_t;
+#endif
+
+/*! @brief TPM clock source selection*/
+typedef enum _tpm_clock_source
+{
+    kTPM_SystemClock = 1U, /*!< System clock */
+    kTPM_ExternalClock     /*!< External clock */
+} tpm_clock_source_t;
+
+/*! @brief TPM prescale value selection for the clock source*/
+typedef enum _tpm_clock_prescale
+{
+    kTPM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */
+    kTPM_Prescale_Divide_2,      /*!< Divide by 2 */
+    kTPM_Prescale_Divide_4,      /*!< Divide by 4 */
+    kTPM_Prescale_Divide_8,      /*!< Divide by 8 */
+    kTPM_Prescale_Divide_16,     /*!< Divide by 16 */
+    kTPM_Prescale_Divide_32,     /*!< Divide by 32 */
+    kTPM_Prescale_Divide_64,     /*!< Divide by 64 */
+    kTPM_Prescale_Divide_128     /*!< Divide by 128 */
+} tpm_clock_prescale_t;
+
+/*!
+ * @brief TPM config structure
+ *
+ * This structure holds the configuration settings for the TPM peripheral. To initialize this
+ * structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The config struct can be made const so it resides in flash
+ */
+typedef struct _tpm_config
+{
+    tpm_clock_prescale_t prescale;      /*!< Select TPM clock prescale value */
+    bool useGlobalTimeBase;             /*!< true: Use of an external global time base is enabled;
+                                             false: disabled */
+    tpm_trigger_select_t triggerSelect; /*!< Input trigger to use for controlling the counter operation */
+#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
+    tpm_trigger_source_t triggerSource; /*!< Decides if we use external or internal trigger. */
+#endif
+    bool enableDoze;            /*!< true: TPM counter is paused in doze mode;
+                                     false: TPM counter continues in doze mode */
+    bool enableDebugMode;       /*!< true: TPM counter continues in debug mode;
+                                     false: TPM counter is paused in debug mode */
+    bool enableReloadOnTrigger; /*!< true: TPM counter is reloaded on trigger;
+                                     false: TPM counter not reloaded */
+    bool enableStopOnOverflow;  /*!< true: TPM counter stops after overflow;
+                                     false: TPM counter continues running after overflow */
+    bool enableStartOnTrigger;  /*!< true: TPM counter only starts when a trigger is detected;
+                                     false: TPM counter starts immediately */
+#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
+    bool enablePauseOnTrigger; /*!< true: TPM counter will pause while trigger remains asserted;
+                                    false: TPM counter continues running */
+#endif
+} tpm_config_t;
+
+/*! @brief List of TPM interrupts */
+typedef enum _tpm_interrupt_enable
+{
+    kTPM_Chnl0InterruptEnable = (1U << 0),       /*!< Channel 0 interrupt.*/
+    kTPM_Chnl1InterruptEnable = (1U << 1),       /*!< Channel 1 interrupt.*/
+    kTPM_Chnl2InterruptEnable = (1U << 2),       /*!< Channel 2 interrupt.*/
+    kTPM_Chnl3InterruptEnable = (1U << 3),       /*!< Channel 3 interrupt.*/
+    kTPM_Chnl4InterruptEnable = (1U << 4),       /*!< Channel 4 interrupt.*/
+    kTPM_Chnl5InterruptEnable = (1U << 5),       /*!< Channel 5 interrupt.*/
+    kTPM_Chnl6InterruptEnable = (1U << 6),       /*!< Channel 6 interrupt.*/
+    kTPM_Chnl7InterruptEnable = (1U << 7),       /*!< Channel 7 interrupt.*/
+    kTPM_TimeOverflowInterruptEnable = (1U << 8) /*!< Time overflow interrupt.*/
+} tpm_interrupt_enable_t;
+
+/*! @brief List of TPM flags */
+typedef enum _tpm_status_flags
+{
+    kTPM_Chnl0Flag = (1U << 0),       /*!< Channel 0 flag */
+    kTPM_Chnl1Flag = (1U << 1),       /*!< Channel 1 flag */
+    kTPM_Chnl2Flag = (1U << 2),       /*!< Channel 2 flag */
+    kTPM_Chnl3Flag = (1U << 3),       /*!< Channel 3 flag */
+    kTPM_Chnl4Flag = (1U << 4),       /*!< Channel 4 flag */
+    kTPM_Chnl5Flag = (1U << 5),       /*!< Channel 5 flag */
+    kTPM_Chnl6Flag = (1U << 6),       /*!< Channel 6 flag */
+    kTPM_Chnl7Flag = (1U << 7),       /*!< Channel 7 flag */
+    kTPM_TimeOverflowFlag = (1U << 8) /*!< Time overflow flag */
+} tpm_status_flags_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the TPM clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application using the TPM driver.
+ *
+ * @param base   TPM peripheral base address
+ * @param config Pointer to user's TPM config structure.
+ */
+void TPM_Init(TPM_Type *base, const tpm_config_t *config);
+
+/*!
+ * @brief Stops the counter and gates the TPM clock
+ *
+ * @param base TPM peripheral base address
+ */
+void TPM_Deinit(TPM_Type *base);
+
+/*!
+ * @brief  Fill in the TPM config struct with the default settings
+ *
+ * The default values are:
+ * @code
+ *     config->prescale = kTPM_Prescale_Divide_1;
+ *     config->useGlobalTimeBase = false;
+ *     config->dozeEnable = false;
+ *     config->dbgMode = false;
+ *     config->enableReloadOnTrigger = false;
+ *     config->enableStopOnOverflow = false;
+ *     config->enableStartOnTrigger = false;
+ *#if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
+ *     config->enablePauseOnTrigger = false;
+ *#endif
+ *     config->triggerSelect = kTPM_Trigger_Select_0;
+ *#if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
+ *     config->triggerSource = kTPM_TriggerSource_External;
+ *#endif
+ * @endcode
+ * @param config Pointer to user's TPM config structure.
+ */
+void TPM_GetDefaultConfig(tpm_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name Channel mode operations
+ * @{
+ */
+
+/*!
+ * @brief Configures the PWM signal parameters
+ *
+ * User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this
+ * function to configure all the TPM channels that will be used to output a PWM signal
+ *
+ * @param base        TPM peripheral base address
+ * @param chnlParams  Array of PWM channel parameters to configure the channel(s)
+ * @param numOfChnls  Number of channels to configure, this should be the size of the array passed in
+ * @param mode        PWM operation mode, options available in enumeration ::tpm_pwm_mode_t
+ * @param pwmFreq_Hz  PWM signal frequency in Hz
+ * @param srcClock_Hz TPM counter clock in Hz
+ *
+ * @return kStatus_Success if the PWM setup was successful,
+ *         kStatus_Error on failure
+ */
+status_t TPM_SetupPwm(TPM_Type *base,
+                      const tpm_chnl_pwm_signal_param_t *chnlParams,
+                      uint8_t numOfChnls,
+                      tpm_pwm_mode_t mode,
+                      uint32_t pwmFreq_Hz,
+                      uint32_t srcClock_Hz);
+
+/*!
+ * @brief Update the duty cycle of an active PWM signal
+ *
+ * @param base              TPM peripheral base address
+ * @param chnlNumber        The channel number. In combined mode, this represents
+ *                          the channel pair number
+ * @param currentPwmMode    The current PWM mode set during PWM setup
+ * @param dutyCyclePercent  New PWM pulse width, value should be between 0 to 100
+ *                          0=inactive signal(0% duty cycle)...
+ *                          100=active signal (100% duty cycle)
+ */
+void TPM_UpdatePwmDutycycle(TPM_Type *base,
+                            tpm_chnl_t chnlNumber,
+                            tpm_pwm_mode_t currentPwmMode,
+                            uint8_t dutyCyclePercent);
+
+/*!
+ * @brief Update the edge level selection for a channel
+ *
+ * @param base       TPM peripheral base address
+ * @param chnlNumber The channel number
+ * @param level      The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11.
+ *                   See the appropriate SoC reference manual for details about this field.
+ */
+void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level);
+
+/*!
+ * @brief Enables capturing an input signal on the channel using the function parameters.
+ *
+ * When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into
+ * the CnV register. The user has to read the CnV register separately to get this value.
+ *
+ * @param base        TPM peripheral base address
+ * @param chnlNumber  The channel number
+ * @param captureMode Specifies which edge to capture
+ */
+void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode);
+
+/*!
+ * @brief Configures the TPM to generate timed pulses.
+ *
+ * When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel
+ * output is changed based on what is specified in the compareMode argument.
+ *
+ * @param base         TPM peripheral base address
+ * @param chnlNumber   The channel number
+ * @param compareMode  Action to take on the channel output when the compare condition is met
+ * @param compareValue Value to be programmed in the CnV register.
+ */
+void TPM_SetupOutputCompare(TPM_Type *base,
+                            tpm_chnl_t chnlNumber,
+                            tpm_output_compare_mode_t compareMode,
+                            uint32_t compareValue);
+
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+/*!
+ * @brief Configures the dual edge capture mode of the TPM.
+ *
+ * This function allows to measure a pulse width of the signal on the input of channel of a
+ * channel pair. The filter function is disabled if the filterVal argument passed is zero.
+ *
+ * @param base           TPM peripheral base address
+ * @param chnlPairNumber The TPM channel pair number; options are 0, 1, 2, 3
+ * @param edgeParam      Sets up the dual edge capture function
+ * @param filterValue    Filter value, specify 0 to disable filter.
+ */
+void TPM_SetupDualEdgeCapture(TPM_Type *base,
+                              tpm_chnl_t chnlPairNumber,
+                              const tpm_dual_edge_capture_param_t *edgeParam,
+                              uint32_t filterValue);
+#endif
+
+#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
+/*!
+ * @brief Configures the parameters and activates the quadrature decode mode.
+ *
+ * @param base         TPM peripheral base address
+ * @param phaseAParams Phase A configuration parameters
+ * @param phaseBParams Phase B configuration parameters
+ * @param quadMode     Selects encoding mode used in quadrature decoder mode
+ */
+void TPM_SetupQuadDecode(TPM_Type *base,
+                         const tpm_phase_params_t *phaseAParams,
+                         const tpm_phase_params_t *phaseBParams,
+                         tpm_quad_decode_mode_t quadMode);
+#endif
+
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected TPM interrupts.
+ *
+ * @param base TPM peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::tpm_interrupt_enable_t
+ */
+void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the selected TPM interrupts.
+ *
+ * @param base TPM peripheral base address
+ * @param mask The interrupts to disable. This is a logical OR of members of the
+ *             enumeration ::tpm_interrupt_enable_t
+ */
+void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets the enabled TPM interrupts.
+ *
+ * @param base TPM peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::tpm_interrupt_enable_t
+ */
+uint32_t TPM_GetEnabledInterrupts(TPM_Type *base);
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the TPM status flags
+ *
+ * @param base TPM peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::tpm_status_flags_t
+ */
+static inline uint32_t TPM_GetStatusFlags(TPM_Type *base)
+{
+    return base->STATUS;
+}
+
+/*!
+ * @brief Clears the TPM status flags
+ *
+ * @param base TPM peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::tpm_status_flags_t
+ */
+static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask)
+{
+    /* Clear the status flags */
+    base->STATUS = mask;
+}
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the TPM counter.
+ *
+ *
+ * @param base        TPM peripheral base address
+ * @param clockSource TPM clock source; once clock source is set the counter will start running
+ */
+static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource)
+{
+    uint32_t reg = base->SC;
+
+    reg &= ~(TPM_SC_CMOD_MASK);
+    reg |= TPM_SC_CMOD(clockSource);
+    base->SC = reg;
+}
+
+/*!
+ * @brief Stops the TPM counter.
+ *
+ * @param base TPM peripheral base address
+ */
+static inline void TPM_StopTimer(TPM_Type *base)
+{
+    /* Set clock source to none to disable counter */
+    base->SC &= ~(TPM_SC_CMOD_MASK);
+
+    /* Wait till this reads as zero acknowledging the counter is disabled */
+    while (base->SC & TPM_SC_CMOD_MASK)
+    {
+    }
+}
+
+/*! @}*/
+
+#if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL
+/*!
+ * @brief Performs a software reset on the TPM module.
+ *
+ * Reset all internal logic and registers, except the Global Register. Remains set until cleared by software..
+ *
+ * @note TPM software reset is available on certain SoC's only
+ *
+ * @param base TPM peripheral base address
+ */
+static inline void TPM_Reset(TPM_Type *base)
+{
+    base->GLOBAL |= TPM_GLOBAL_RST_MASK;
+    base->GLOBAL &= ~TPM_GLOBAL_RST_MASK;
+}
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_TPM_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_trng.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_trng.c
new file mode 100644
index 00000000000..a5fd937dcd5
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_trng.c
@@ -0,0 +1,1618 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_trng.h"
+
+#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+/* Default values for user configuration structure.*/
+#if (defined(KW40Z4_SERIES) || defined(KW41Z4_SERIES) || defined(KW31Z4_SERIES) || defined(KW21Z4_SERIES))
+#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv8
+#elif(defined(KV56F22_SERIES) || defined(KV58F22_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \
+      defined(KL82Z7_SERIES))
+#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv4
+#elif defined(K81F25615_SERIES)
+#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv2
+#else
+#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv0
+#endif
+
+#define TRNG_USER_CONFIG_DEFAULT_LOCK 0
+#define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 3200
+#define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 2500
+#define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 63
+#define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1
+#define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 34
+
+#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 1384
+#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 268)
+#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 405
+#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 178)
+#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 220
+#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 122)
+#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 125
+#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 88)
+#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 75
+#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM - 64)
+#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 47
+#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM - 46)
+#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 47
+#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 46)
+#define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 26912
+#define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM (TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM - 2467)
+#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 25600
+#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM 1600
+
+/*! @brief TRNG work mode */
+typedef enum _trng_work_mode
+{
+    kTRNG_WorkModeRun = 0U,    /*!< Run Mode. */
+    kTRNG_WorkModeProgram = 1U /*!< Program Mode. */
+} trng_work_mode_t;
+
+/*! @brief TRNG statistical check type*/
+typedef enum _trng_statistical_check
+{
+    kTRNG_StatisticalCheckMonobit =
+        1U,                        /*!< Statistical check of number of ones/zero detected during entropy generation. */
+    kTRNG_StatisticalCheckRunBit1, /*!< Statistical check of number of runs of length 1 detected during entropy
+                                      generation. */
+    kTRNG_StatisticalCheckRunBit2, /*!< Statistical check of number of runs of length 2 detected during entropy
+                                      generation. */
+    kTRNG_StatisticalCheckRunBit3, /*!< Statistical check of number of runs of length 3 detected during entropy
+                                      generation. */
+    kTRNG_StatisticalCheckRunBit4, /*!< Statistical check of number of runs of length 4 detected during entropy
+                                      generation. */
+    kTRNG_StatisticalCheckRunBit5, /*!< Statistical check of number of runs of length 5 detected during entropy
+                                      generation. */
+    kTRNG_StatisticalCheckRunBit6Plus,   /*!< Statistical check of number of runs of length 6 or more detected during
+                                            entropy generation. */
+    kTRNG_StatisticalCheckPoker,         /*!< Statistical check of "Poker Test". */
+    kTRNG_StatisticalCheckFrequencyCount /*!< Statistical check of entropy sample frequency count. */
+} trng_statistical_check_t;
+
+/*******************************************************************************
+ * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register
+ ******************************************************************************/
+/*!
+ * @name Register TRNG_SCMISC, field RTY_CT[19:16] (RW)
+ *
+ * RETRY COUNT. If a statistical check fails during the TRNG Entropy Generation,
+ * the RTY_CT value indicates the number of times a retry should occur before
+ * generating an error. This field is writable only if MCTL[PRGM] bit is 1. This
+ * field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 1h by writing
+ * the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCMISC_RTY_CT field. */
+#define TRNG_RD_SCMISC_RTY_CT(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_RTY_CT_MASK) >> TRNG_SCMISC_RTY_CT_SHIFT)
+
+/*! @brief Set the RTY_CT field to a new value. */
+#define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCMISC_RTY_CT(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_SCML - RNG Statistical Check Monobit Limit Register
+ ******************************************************************************/
+/*!
+ * @brief TRNG_SCML - RNG Statistical Check Monobit Limit Register (RW)
+ *
+ * Reset value: 0x010C0568U
+ *
+ * The RNG Statistical Check Monobit Limit Register defines the allowable
+ * maximum and minimum number of ones/zero detected during entropy generation. To pass
+ * the test, the number of ones/zeroes generated must be less than the programmed
+ * maximum value, and the number of ones/zeroes generated must be greater than
+ * (maximum - range). If this test fails, the Retry Counter in SCMISC will be
+ * decremented, and a retry will occur if the Retry Count has not reached zero. If
+ * the Retry Count has reached zero, an error will be generated. Note that this
+ * offset (0xBASE_0620) is used as SCML only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0,
+ * this offset is used as SCMC readback register.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_SCML register
+ */
+/*@{*/
+#define TRNG_SCML_REG(base) ((base)->SCML)
+#define TRNG_RD_SCML(base) (TRNG_SCML_REG(base))
+#define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value))
+#define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (value)))
+/*@}*/
+/*!
+ * @name Register TRNG_SCML, field MONO_MAX[15:0] (RW)
+ *
+ * Monobit Maximum Limit. Defines the maximum allowable count taken during
+ * entropy generation. The number of ones/zeroes detected during entropy generation
+ * must be less than MONO_MAX, else a retry or error will occur. This register is
+ * cleared to 00056Bh (decimal 1387) by writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCML_MONO_MAX field. */
+#define TRNG_RD_SCML_MONO_MAX(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_MAX_MASK) >> TRNG_SCML_MONO_MAX_SHIFT)
+
+/*! @brief Set the MONO_MAX field to a new value. */
+#define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_MONO_MAX(value)))
+/*@}*/
+/*!
+ * @name Register TRNG_SCML, field MONO_RNG[31:16] (RW)
+ *
+ * Monobit Range. The number of ones/zeroes detected during entropy generation
+ * must be greater than MONO_MAX - MONO_RNG, else a retry or error will occur.
+ * This register is cleared to 000112h (decimal 274) by writing the MCTL[RST_DEF]
+ * bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCML_MONO_RNG field. */
+#define TRNG_RD_SCML_MONO_RNG(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_RNG_MASK) >> TRNG_SCML_MONO_RNG_SHIFT)
+
+/*! @brief Set the MONO_RNG field to a new value. */
+#define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_MONO_RNG(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register (RW)
+ *
+ * Reset value: 0x00B20195U
+ *
+ * The RNG Statistical Check Run Length 1 Limit Register defines the allowable
+ * maximum and minimum number of runs of length 1 detected during entropy
+ * generation. To pass the test, the number of runs of length 1 (for samples of both 0
+ * and 1) must be less than the programmed maximum value, and the number of runs of
+ * length 1 must be greater than (maximum - range). If this test fails, the
+ * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
+ * Count has not reached zero. If the Retry Count has reached zero, an error will
+ * be generated. Note that this address (0xBASE_0624) is used as SCR1L only if
+ * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR1C readback
+ * register.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_SCR1L register
+ */
+/*@{*/
+#define TRNG_SCR1L_REG(base) ((base)->SCR1L)
+#define TRNG_RD_SCR1L(base) (TRNG_SCR1L_REG(base))
+#define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value))
+#define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_SCR1L, field RUN1_MAX[14:0] (RW)
+ *
+ * Run Length 1 Maximum Limit. Defines the maximum allowable runs of length 1
+ * (for both 0 and 1) detected during entropy generation. The number of runs of
+ * length 1 detected during entropy generation must be less than RUN1_MAX, else a
+ * retry or error will occur. This register is cleared to 01E5h (decimal 485) by
+ * writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCR1L_RUN1_MAX field. */
+#define TRNG_RD_SCR1L_RUN1_MAX(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_MAX_MASK) >> TRNG_SCR1L_RUN1_MAX_SHIFT)
+
+/*! @brief Set the RUN1_MAX field to a new value. */
+#define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SCR1L_RUN1_MAX(value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_SCR1L, field RUN1_RNG[30:16] (RW)
+ *
+ * Run Length 1 Range. The number of runs of length 1 (for both 0 and 1)
+ * detected during entropy generation must be greater than RUN1_MAX - RUN1_RNG, else a
+ * retry or error will occur. This register is cleared to 0102h (decimal 258) by
+ * writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCR1L_RUN1_RNG field. */
+#define TRNG_RD_SCR1L_RUN1_RNG(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_RNG_MASK) >> TRNG_SCR1L_RUN1_RNG_SHIFT)
+
+/*! @brief Set the RUN1_RNG field to a new value. */
+#define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SCR1L_RUN1_RNG(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register (RW)
+ *
+ * Reset value: 0x007A00DCU
+ *
+ * The RNG Statistical Check Run Length 2 Limit Register defines the allowable
+ * maximum and minimum number of runs of length 2 detected during entropy
+ * generation. To pass the test, the number of runs of length 2 (for samples of both 0
+ * and 1) must be less than the programmed maximum value, and the number of runs of
+ * length 2 must be greater than (maximum - range). If this test fails, the
+ * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
+ * Count has not reached zero. If the Retry Count has reached zero, an error will
+ * be generated. Note that this address (0xBASE_0628) is used as SCR2L only if
+ * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR2C readback
+ * register.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_SCR2L register
+ */
+/*@{*/
+#define TRNG_SCR2L_REG(base) ((base)->SCR2L)
+#define TRNG_RD_SCR2L(base) (TRNG_SCR2L_REG(base))
+#define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value))
+#define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TRNG_SCR2L bitfields
+ */
+
+/*!
+ * @name Register TRNG_SCR2L, field RUN2_MAX[13:0] (RW)
+ *
+ * Run Length 2 Maximum Limit. Defines the maximum allowable runs of length 2
+ * (for both 0 and 1) detected during entropy generation. The number of runs of
+ * length 2 detected during entropy generation must be less than RUN2_MAX, else a
+ * retry or error will occur. This register is cleared to 00DCh (decimal 220) by
+ * writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCR2L_RUN2_MAX field. */
+#define TRNG_RD_SCR2L_RUN2_MAX(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_MAX_MASK) >> TRNG_SCR2L_RUN2_MAX_SHIFT)
+
+/*! @brief Set the RUN2_MAX field to a new value. */
+#define TRNG_WR_SCR2L_RUN2_MAX(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_MAX_MASK, TRNG_SCR2L_RUN2_MAX(value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_SCR2L, field RUN2_RNG[29:16] (RW)
+ *
+ * Run Length 2 Range. The number of runs of length 2 (for both 0 and 1)
+ * detected during entropy generation must be greater than RUN2_MAX - RUN2_RNG, else a
+ * retry or error will occur. This register is cleared to 007Ah (decimal 122) by
+ * writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCR2L_RUN2_RNG field. */
+#define TRNG_RD_SCR2L_RUN2_RNG(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_RNG_MASK) >> TRNG_SCR2L_RUN2_RNG_SHIFT)
+
+/*! @brief Set the RUN2_RNG field to a new value. */
+#define TRNG_WR_SCR2L_RUN2_RNG(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_RNG_MASK, TRNG_SCR2L_RUN2_RNG(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register (RW)
+ *
+ * Reset value: 0x0058007DU
+ *
+ * The RNG Statistical Check Run Length 3 Limit Register defines the allowable
+ * maximum and minimum number of runs of length 3 detected during entropy
+ * generation. To pass the test, the number of runs of length 3 (for samples of both 0
+ * and 1) must be less than the programmed maximum value, and the number of runs of
+ * length 3 must be greater than (maximum - range). If this test fails, the
+ * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
+ * Count has not reached zero. If the Retry Count has reached zero, an error will
+ * be generated. Note that this address (0xBASE_062C) is used as SCR3L only if
+ * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR3C readback
+ * register.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_SCR3L register
+ */
+/*@{*/
+#define TRNG_SCR3L_REG(base) ((base)->SCR3L)
+#define TRNG_RD_SCR3L(base) (TRNG_SCR3L_REG(base))
+#define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value))
+#define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TRNG_SCR3L bitfields
+ */
+
+/*!
+ * @name Register TRNG_SCR3L, field RUN3_MAX[12:0] (RW)
+ *
+ * Run Length 3 Maximum Limit. Defines the maximum allowable runs of length 3
+ * (for both 0 and 1) detected during entropy generation. The number of runs of
+ * length 3 detected during entropy generation must be less than RUN3_MAX, else a
+ * retry or error will occur. This register is cleared to 007Dh (decimal 125) by
+ * writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCR3L_RUN3_MAX field. */
+#define TRNG_RD_SCR3L_RUN3_MAX(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_MAX_MASK) >> TRNG_SCR3L_RUN3_MAX_SHIFT)
+
+/*! @brief Set the RUN3_MAX field to a new value. */
+#define TRNG_WR_SCR3L_RUN3_MAX(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_MAX_MASK, TRNG_SCR3L_RUN3_MAX(value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_SCR3L, field RUN3_RNG[28:16] (RW)
+ *
+ * Run Length 3 Range. The number of runs of length 3 (for both 0 and 1)
+ * detected during entropy generation must be greater than RUN3_MAX - RUN3_RNG, else a
+ * retry or error will occur. This register is cleared to 0058h (decimal 88) by
+ * writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCR3L_RUN3_RNG field. */
+#define TRNG_RD_SCR3L_RUN3_RNG(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_RNG_MASK) >> TRNG_SCR3L_RUN3_RNG_SHIFT)
+
+/*! @brief Set the RUN3_RNG field to a new value. */
+#define TRNG_WR_SCR3L_RUN3_RNG(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_RNG_MASK, TRNG_SCR3L_RUN3_RNG(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register (RW)
+ *
+ * Reset value: 0x0040004BU
+ *
+ * The RNG Statistical Check Run Length 4 Limit Register defines the allowable
+ * maximum and minimum number of runs of length 4 detected during entropy
+ * generation. To pass the test, the number of runs of length 4 (for samples of both 0
+ * and 1) must be less than the programmed maximum value, and the number of runs of
+ * length 4 must be greater than (maximum - range). If this test fails, the
+ * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
+ * Count has not reached zero. If the Retry Count has reached zero, an error will
+ * be generated. Note that this address (0xBASE_0630) is used as SCR4L only if
+ * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR4C readback
+ * register.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_SCR4L register
+ */
+/*@{*/
+#define TRNG_SCR4L_REG(base) ((base)->SCR4L)
+#define TRNG_RD_SCR4L(base) (TRNG_SCR4L_REG(base))
+#define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value))
+#define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TRNG_SCR4L bitfields
+ */
+
+/*!
+ * @name Register TRNG_SCR4L, field RUN4_MAX[11:0] (RW)
+ *
+ * Run Length 4 Maximum Limit. Defines the maximum allowable runs of length 4
+ * (for both 0 and 1) detected during entropy generation. The number of runs of
+ * length 4 detected during entropy generation must be less than RUN4_MAX, else a
+ * retry or error will occur. This register is cleared to 004Bh (decimal 75) by
+ * writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCR4L_RUN4_MAX field. */
+#define TRNG_RD_SCR4L_RUN4_MAX(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_MAX_MASK) >> TRNG_SCR4L_RUN4_MAX_SHIFT)
+
+/*! @brief Set the RUN4_MAX field to a new value. */
+#define TRNG_WR_SCR4L_RUN4_MAX(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_MAX_MASK, TRNG_SCR4L_RUN4_MAX(value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_SCR4L, field RUN4_RNG[27:16] (RW)
+ *
+ * Run Length 4 Range. The number of runs of length 4 (for both 0 and 1)
+ * detected during entropy generation must be greater than RUN4_MAX - RUN4_RNG, else a
+ * retry or error will occur. This register is cleared to 0040h (decimal 64) by
+ * writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCR4L_RUN4_RNG field. */
+#define TRNG_RD_SCR4L_RUN4_RNG(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_RNG_MASK) >> TRNG_SCR4L_RUN4_RNG_SHIFT)
+
+/*! @brief Set the RUN4_RNG field to a new value. */
+#define TRNG_WR_SCR4L_RUN4_RNG(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_RNG_MASK, TRNG_SCR4L_RUN4_RNG(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register (RW)
+ *
+ * Reset value: 0x002E002FU
+ *
+ * The RNG Statistical Check Run Length 5 Limit Register defines the allowable
+ * maximum and minimum number of runs of length 5 detected during entropy
+ * generation. To pass the test, the number of runs of length 5 (for samples of both 0
+ * and 1) must be less than the programmed maximum value, and the number of runs of
+ * length 5 must be greater than (maximum - range). If this test fails, the
+ * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
+ * Count has not reached zero. If the Retry Count has reached zero, an error will
+ * be generated. Note that this address (0xBASE_0634) is used as SCR5L only if
+ * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR5C readback
+ * register.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_SCR5L register
+ */
+/*@{*/
+#define TRNG_SCR5L_REG(base) ((base)->SCR5L)
+#define TRNG_RD_SCR5L(base) (TRNG_SCR5L_REG(base))
+#define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value))
+#define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TRNG_SCR5L bitfields
+ */
+
+/*!
+ * @name Register TRNG_SCR5L, field RUN5_MAX[10:0] (RW)
+ *
+ * Run Length 5 Maximum Limit. Defines the maximum allowable runs of length 5
+ * (for both 0 and 1) detected during entropy generation. The number of runs of
+ * length 5 detected during entropy generation must be less than RUN5_MAX, else a
+ * retry or error will occur. This register is cleared to 002Fh (decimal 47) by
+ * writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCR5L_RUN5_MAX field. */
+#define TRNG_RD_SCR5L_RUN5_MAX(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_MAX_MASK) >> TRNG_SCR5L_RUN5_MAX_SHIFT)
+
+/*! @brief Set the RUN5_MAX field to a new value. */
+#define TRNG_WR_SCR5L_RUN5_MAX(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_MAX_MASK, TRNG_SCR5L_RUN5_MAX(value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_SCR5L, field RUN5_RNG[26:16] (RW)
+ *
+ * Run Length 5 Range. The number of runs of length 5 (for both 0 and 1)
+ * detected during entropy generation must be greater than RUN5_MAX - RUN5_RNG, else a
+ * retry or error will occur. This register is cleared to 002Eh (decimal 46) by
+ * writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCR5L_RUN5_RNG field. */
+#define TRNG_RD_SCR5L_RUN5_RNG(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_RNG_MASK) >> TRNG_SCR5L_RUN5_RNG_SHIFT)
+
+/*! @brief Set the RUN5_RNG field to a new value. */
+#define TRNG_WR_SCR5L_RUN5_RNG(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_RNG_MASK, TRNG_SCR5L_RUN5_RNG(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register (RW)
+ *
+ * Reset value: 0x002E002FU
+ *
+ * The RNG Statistical Check Run Length 6+ Limit Register defines the allowable
+ * maximum and minimum number of runs of length 6 or more detected during entropy
+ * generation. To pass the test, the number of runs of length 6 or more (for
+ * samples of both 0 and 1) must be less than the programmed maximum value, and the
+ * number of runs of length 6 or more must be greater than (maximum - range). If
+ * this test fails, the Retry Counter in SCMISC will be decremented, and a retry
+ * will occur if the Retry Count has not reached zero. If the Retry Count has
+ * reached zero, an error will be generated. Note that this offset (0xBASE_0638) is
+ * used as SCR6PL only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is
+ * used as SCR6PC readback register.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_SCR6PL register
+ */
+/*@{*/
+#define TRNG_SCR6PL_REG(base) ((base)->SCR6PL)
+#define TRNG_RD_SCR6PL(base) (TRNG_SCR6PL_REG(base))
+#define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value))
+#define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TRNG_SCR6PL bitfields
+ */
+
+/*!
+ * @name Register TRNG_SCR6PL, field RUN6P_MAX[10:0] (RW)
+ *
+ * Run Length 6+ Maximum Limit. Defines the maximum allowable runs of length 6
+ * or more (for both 0 and 1) detected during entropy generation. The number of
+ * runs of length 6 or more detected during entropy generation must be less than
+ * RUN6P_MAX, else a retry or error will occur. This register is cleared to 002Fh
+ * (decimal 47) by writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_MAX field. */
+#define TRNG_RD_SCR6PL_RUN6P_MAX(base) \
+    ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_MAX_MASK) >> TRNG_SCR6PL_RUN6P_MAX_SHIFT)
+
+/*! @brief Set the RUN6P_MAX field to a new value. */
+#define TRNG_WR_SCR6PL_RUN6P_MAX(base, value) \
+    (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_MAX_MASK, TRNG_SCR6PL_RUN6P_MAX(value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_SCR6PL, field RUN6P_RNG[26:16] (RW)
+ *
+ * Run Length 6+ Range. The number of runs of length 6 or more (for both 0 and
+ * 1) detected during entropy generation must be greater than RUN6P_MAX -
+ * RUN6P_RNG, else a retry or error will occur. This register is cleared to 002Eh
+ * (decimal 46) by writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_RNG field. */
+#define TRNG_RD_SCR6PL_RUN6P_RNG(base) \
+    ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_RNG_MASK) >> TRNG_SCR6PL_RUN6P_RNG_SHIFT)
+
+/*! @brief Set the RUN6P_RNG field to a new value. */
+#define TRNG_WR_SCR6PL_RUN6P_RNG(base, value) \
+    (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_RNG_MASK, TRNG_SCR6PL_RUN6P_RNG(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_PKRMAX - RNG Poker Maximum Limit Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_PKRMAX - RNG Poker Maximum Limit Register (RW)
+ *
+ * Reset value: 0x00006920U
+ *
+ * The RNG Poker Maximum Limit Register defines Maximum Limit allowable during
+ * the TRNG Statistical Check Poker Test. Note that this offset (0xBASE_060C) is
+ * used as PKRMAX only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used
+ * as the PKRSQ readback register.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_PKRMAX register
+ */
+/*@{*/
+#define TRNG_PKRMAX_REG(base) ((base)->PKRMAX)
+#define TRNG_RD_PKRMAX(base) (TRNG_PKRMAX_REG(base))
+#define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value))
+#define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TRNG_PKRMAX bitfields
+ */
+
+/*!
+ * @name Register TRNG_PKRMAX, field PKR_MAX[23:0] (RW)
+ *
+ * Poker Maximum Limit. During the TRNG Statistical Checks, a "Poker Test" is
+ * run which requires a maximum and minimum limit. The maximum allowable result is
+ * programmed in the PKRMAX[PKR_MAX] register. This field is writable only if
+ * MCTL[PRGM] bit is 1. This register is cleared to 006920h (decimal 26912) by
+ * writing the MCTL[RST_DEF] bit to 1. Note that the PKRMAX and PKRRNG registers
+ * combined are used to define the minimum allowable Poker result, which is PKR_MAX -
+ * PKR_RNG + 1. Note that if MCTL[PRGM] bit is 0, this register address is used
+ * to read the Poker Test Square Calculation result in register PKRSQ, as defined
+ * in the following section.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_PKRMAX_PKR_MAX field. */
+#define TRNG_RD_PKRMAX_PKR_MAX(base) ((TRNG_PKRMAX_REG(base) & TRNG_PKRMAX_PKR_MAX_MASK) >> TRNG_PKRMAX_PKR_MAX_SHIFT)
+
+/*! @brief Set the PKR_MAX field to a new value. */
+#define TRNG_WR_PKRMAX_PKR_MAX(base, value) \
+    (TRNG_RMW_PKRMAX(base, TRNG_PKRMAX_PKR_MAX_MASK, TRNG_PKRMAX_PKR_MAX(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_PKRRNG - RNG Poker Range Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_PKRRNG - RNG Poker Range Register (RW)
+ *
+ * Reset value: 0x000009A3U
+ *
+ * The RNG Poker Range Register defines the difference between the TRNG Poker
+ * Maximum Limit and the minimum limit. These limits are used during the TRNG
+ * Statistical Check Poker Test.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_PKRRNG register
+ */
+/*@{*/
+#define TRNG_PKRRNG_REG(base) ((base)->PKRRNG)
+#define TRNG_RD_PKRRNG(base) (TRNG_PKRRNG_REG(base))
+#define TRNG_WR_PKRRNG(base, value) (TRNG_PKRRNG_REG(base) = (value))
+#define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TRNG_PKRRNG bitfields
+ */
+
+/*!
+ * @name Register TRNG_PKRRNG, field PKR_RNG[15:0] (RW)
+ *
+ * Poker Range. During the TRNG Statistical Checks, a "Poker Test" is run which
+ * requires a maximum and minimum limit. The maximum is programmed in the
+ * RTPKRMAX[PKR_MAX] register, and the minimum is derived by subtracting the PKR_RNG
+ * value from the programmed maximum value. This field is writable only if
+ * MCTL[PRGM] bit is 1. This field will read zeroes if MCTL[PRGM] = 0. This field is
+ * cleared to 09A3h (decimal 2467) by writing the MCTL[RST_DEF] bit to 1. Note that
+ * the minimum allowable Poker result is PKR_MAX - PKR_RNG + 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_PKRRNG_PKR_RNG field. */
+#define TRNG_RD_PKRRNG_PKR_RNG(base) ((TRNG_PKRRNG_REG(base) & TRNG_PKRRNG_PKR_RNG_MASK) >> TRNG_PKRRNG_PKR_RNG_SHIFT)
+
+/*! @brief Set the PKR_RNG field to a new value. */
+#define TRNG_WR_PKRRNG_PKR_RNG(base, value) \
+    (TRNG_RMW_PKRRNG(base, TRNG_PKRRNG_PKR_RNG_MASK, TRNG_PKRRNG_PKR_RNG(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register (RW)
+ *
+ * Reset value: 0x00006400U
+ *
+ * The RNG Frequency Count Maximum Limit Register defines the maximum allowable
+ * count taken by the Entropy sample counter during each Entropy sample. During
+ * any sample period, if the count is greater than this programmed maximum, a
+ * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. Note
+ * that this address (061C) is used as FRQMAX only if MCTL[PRGM] is 1. If
+ * MCTL[PRGM] is 0, this address is used as FRQCNT readback register.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_FRQMAX register
+ */
+/*@{*/
+#define TRNG_FRQMAX_REG(base) ((base)->FRQMAX)
+#define TRNG_RD_FRQMAX(base) (TRNG_FRQMAX_REG(base))
+#define TRNG_WR_FRQMAX(base, value) (TRNG_FRQMAX_REG(base) = (value))
+#define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TRNG_FRQMAX bitfields
+ */
+
+/*!
+ * @name Register TRNG_FRQMAX, field FRQ_MAX[21:0] (RW)
+ *
+ * Frequency Counter Maximum Limit. Defines the maximum allowable count taken
+ * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1.
+ * This register is cleared to 000640h by writing the MCTL[RST_DEF] bit to 1.
+ * Note that if MCTL[PRGM] bit is 0, this register address is used to read the
+ * Frequency Count result in register FRQCNT, as defined in the following section.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_FRQMAX_FRQ_MAX field. */
+#define TRNG_RD_FRQMAX_FRQ_MAX(base) ((TRNG_FRQMAX_REG(base) & TRNG_FRQMAX_FRQ_MAX_MASK) >> TRNG_FRQMAX_FRQ_MAX_SHIFT)
+
+/*! @brief Set the FRQ_MAX field to a new value. */
+#define TRNG_WR_FRQMAX_FRQ_MAX(base, value) \
+    (TRNG_RMW_FRQMAX(base, TRNG_FRQMAX_FRQ_MAX_MASK, TRNG_FRQMAX_FRQ_MAX(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register (RW)
+ *
+ * Reset value: 0x00000640U
+ *
+ * The RNG Frequency Count Minimum Limit Register defines the minimum allowable
+ * count taken by the Entropy sample counter during each Entropy sample. During
+ * any sample period, if the count is less than this programmed minimum, a
+ * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_FRQMIN register
+ */
+/*@{*/
+#define TRNG_FRQMIN_REG(base) ((base)->FRQMIN)
+#define TRNG_RD_FRQMIN(base) (TRNG_FRQMIN_REG(base))
+#define TRNG_WR_FRQMIN(base, value) (TRNG_FRQMIN_REG(base) = (value))
+#define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TRNG_FRQMIN bitfields
+ */
+
+/*!
+ * @name Register TRNG_FRQMIN, field FRQ_MIN[21:0] (RW)
+ *
+ * Frequency Count Minimum Limit. Defines the minimum allowable count taken
+ * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1.
+ * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 0000h64
+ * by writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_FRQMIN_FRQ_MIN field. */
+#define TRNG_RD_FRQMIN_FRQ_MIN(base) ((TRNG_FRQMIN_REG(base) & TRNG_FRQMIN_FRQ_MIN_MASK) >> TRNG_FRQMIN_FRQ_MIN_SHIFT)
+
+/*! @brief Set the FRQ_MIN field to a new value. */
+#define TRNG_WR_FRQMIN_FRQ_MIN(base, value) \
+    (TRNG_RMW_FRQMIN(base, TRNG_FRQMIN_FRQ_MIN_MASK, TRNG_FRQMIN_FRQ_MIN(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_MCTL - RNG Miscellaneous Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_MCTL - RNG Miscellaneous Control Register (RW)
+ *
+ * Reset value: 0x00012001U
+ *
+ * This register is intended to be used for programming, configuring and testing
+ * the RNG. It is the main register to read/write, in order to enable Entropy
+ * generation, to stop entropy generation and to block access to entropy registers.
+ * This is done via the special TRNG_ACC and PRGM bits below. The RNG
+ * Miscellaneous Control Register is a read/write register used to control the RNG's True
+ * Random Number Generator (TRNG) access, operation and test. Note that in many
+ * cases two RNG registers share the same address, and a particular register at the
+ * shared address is selected based upon the value in the PRGM field of the MCTL
+ * register.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_MCTL register
+ */
+/*@{*/
+#define TRNG_MCTL_REG(base) ((base)->MCTL)
+#define TRNG_RD_MCTL(base) (TRNG_MCTL_REG(base))
+#define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value))
+#define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_MCTL, field FOR_SCLK[7] (RW)
+ *
+ * Force System Clock. If set, the system clock is used to operate the TRNG,
+ * instead of the ring oscillator. This is for test use only, and indeterminate
+ * results may occur. This bit is writable only if PRGM bit is 1, or PRGM bit is
+ * being written to 1 simultaneously to writing this bit. This bit is cleared by
+ * writing the RST_DEF bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_MCTL_FOR_SCLK field. */
+#define TRNG_RD_MCTL_FOR_SCLK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FOR_SCLK_MASK) >> TRNG_MCTL_FOR_SCLK_SHIFT)
+
+/*! @brief Set the FOR_SCLK field to a new value. */
+#define TRNG_WR_MCTL_FOR_SCLK(base, value) \
+    (TRNG_RMW_MCTL(base, (TRNG_MCTL_FOR_SCLK_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_FOR_SCLK(value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_MCTL, field OSC_DIV[3:2] (RW)
+ *
+ * Oscillator Divide. Determines the amount of dividing done to the ring
+ * oscillator before it is used by the TRNG.This field is writable only if PRGM bit is
+ * 1, or PRGM bit is being written to 1 simultaneously to writing this field. This
+ * field is cleared to 00 by writing the RST_DEF bit to 1.
+ *
+ * Values:
+ * - 0b00 - use ring oscillator with no divide
+ * - 0b01 - use ring oscillator divided-by-2
+ * - 0b10 - use ring oscillator divided-by-4
+ * - 0b11 - use ring oscillator divided-by-8
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_MCTL_OSC_DIV field. */
+#define TRNG_RD_MCTL_OSC_DIV(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_OSC_DIV_MASK) >> TRNG_MCTL_OSC_DIV_SHIFT)
+
+/*! @brief Set the OSC_DIV field to a new value. */
+#define TRNG_WR_MCTL_OSC_DIV(base, value) \
+    (TRNG_RMW_MCTL(base, (TRNG_MCTL_OSC_DIV_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_OSC_DIV(value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_MCTL, field SAMP_MODE[1:0] (RW)
+ *
+ * Sample Mode. Determines the method of sampling the ring oscillator while
+ * generating the Entropy value:This field is writable only if PRGM bit is 1, or PRGM
+ * bit is being written to 1 simultaneously with writing this field. This field
+ * is cleared to 01 by writing the RST_DEF bit to 1.
+ *
+ * Values:
+ * - 0b00 - use Von Neumann data into both Entropy shifter and Statistical
+ *     Checker
+ * - 0b01 - use raw data into both Entropy shifter and Statistical Checker
+ * - 0b10 - use Von Neumann data into Entropy shifter. Use raw data into
+ *     Statistical Checker
+ * - 0b11 - reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_MCTL_SAMP_MODE field. */
+#define TRNG_RD_MCTL_SAMP_MODE(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_SAMP_MODE_MASK) >> TRNG_MCTL_SAMP_MODE_SHIFT)
+
+/*! @brief Set the SAMP_MODE field to a new value. */
+#define TRNG_WR_MCTL_SAMP_MODE(base, value) \
+    (TRNG_RMW_MCTL(base, (TRNG_MCTL_SAMP_MODE_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_SAMP_MODE(value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_MCTL, field PRGM[16] (RW)
+ *
+ * Programming Mode Select. When this bit is 1, the TRNG is in Program Mode,
+ * otherwise it is in Run Mode. No Entropy value will be generated while the TRNG is
+ * in Program Mode. Note that different RNG registers are accessible at the same
+ * address depending on whether PRGM is set to 1 or 0. This is noted in the RNG
+ * register descriptions.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_MCTL_PRGM field. */
+#define TRNG_RD_MCTL_PRGM(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_PRGM_MASK) >> TRNG_MCTL_PRGM_SHIFT)
+
+/*! @brief Set the PRGM field to a new value. */
+#define TRNG_WR_MCTL_PRGM(base, value) \
+    (TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_PRGM(value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_MCTL, field RST_DEF[6] (WO)
+ *
+ * Reset Defaults. Writing a 1 to this bit clears various TRNG registers, and
+ * bits within registers, to their default state. This bit is writable only if PRGM
+ * bit is 1, or PRGM bit is being written to 1 simultaneously to writing this
+ * bit. Reading this bit always produces a 0.
+ */
+/*@{*/
+/*! @brief Set the RST_DEF field to a new value. */
+#define TRNG_WR_MCTL_RST_DEF(base, value) \
+    (TRNG_RMW_MCTL(base, (TRNG_MCTL_RST_DEF_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_RST_DEF(value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_MCTL, field TRNG_ACC[5] (RW)
+ *
+ * TRNG Access Mode. If this bit is set to 1, the TRNG will generate an Entropy
+ * value that can be read via the ENT0-ENT15 registers. The Entropy value may be
+ * read once the ENT VAL bit is asserted. Also see ENTa register descriptions
+ * (For a = 0 to 15).
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_MCTL_TRNG_ACC field. */
+#define TRNG_RD_MCTL_TRNG_ACC(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TRNG_ACC_MASK) >> TRNG_MCTL_TRNG_ACC_SHIFT)
+
+/*! @brief Set the TRNG_ACC field to a new value. */
+#define TRNG_WR_MCTL_TRNG_ACC(base, value) \
+    (TRNG_RMW_MCTL(base, (TRNG_MCTL_TRNG_ACC_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_TRNG_ACC(value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_MCTL, field TSTOP_OK[13] (RO)
+ *
+ * TRNG_OK_TO_STOP. Software should check that this bit is a 1 before
+ * transitioning RNG to low power mode (RNG clock stopped). RNG turns on the TRNG
+ * free-running ring oscillator whenever new entropy is being generated and turns off the
+ * ring oscillator when entropy generation is complete. If the RNG clock is
+ * stopped while the TRNG ring oscillator is running, the oscillator will continue
+ * running even though the RNG clock is stopped. TSTOP_OK is asserted when the TRNG
+ * ring oscillator is not running. and therefore it is ok to stop the RNG clock.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_MCTL_TSTOP_OK field. */
+#define TRNG_RD_MCTL_TSTOP_OK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TSTOP_OK_MASK) >> TRNG_MCTL_TSTOP_OK_SHIFT)
+/*@}*/
+
+/*!
+ * @name Register TRNG_MCTL, field ENT_VAL[10] (RO)
+ *
+ * Read only: Entropy Valid. Will assert only if TRNG ACC bit is set, and then
+ * after an entropy value is generated. Will be cleared when ENT15 is read. (ENT0
+ * through ENT14 should be read before reading ENT15).
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_MCTL_ENT_VAL field. */
+#define TRNG_RD_MCTL_ENT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ENT_VAL_MASK) >> TRNG_MCTL_ENT_VAL_SHIFT)
+/*@}*/
+
+/*!
+ * @name Register TRNG_MCTL, field ERR[12] (W1C)
+ *
+ * Read: Error status. 1 = error detected. 0 = no error.Write: Write 1 to clear
+ * errors. Writing 0 has no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_MCTL_ERR field. */
+#define TRNG_RD_MCTL_ERR(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ERR_MASK) >> TRNG_MCTL_ERR_SHIFT)
+
+/*! @brief Set the ERR field to a new value. */
+#define TRNG_WR_MCTL_ERR(base, value) (TRNG_RMW_MCTL(base, TRNG_MCTL_ERR_MASK, TRNG_MCTL_ERR(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_SDCTL - RNG Seed Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_SDCTL - RNG Seed Control Register (RW)
+ *
+ * Reset value: 0x0C8009C4U
+ *
+ * The RNG Seed Control Register contains two fields. One field defines the
+ * length (in system clocks) of each Entropy sample (ENT_DLY), and the other field
+ * indicates the number of samples that will taken during each TRNG Entropy
+ * generation (SAMP_SIZE).
+ */
+/*!
+ * @name Constants and macros for entire TRNG_SDCTL register
+ */
+/*@{*/
+#define TRNG_SDCTL_REG(base) ((base)->SDCTL)
+#define TRNG_RD_SDCTL(base) (TRNG_SDCTL_REG(base))
+#define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value))
+#define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TRNG_SDCTL bitfields
+ */
+
+/*!
+ * @name Register TRNG_SDCTL, field SAMP_SIZE[15:0] (RW)
+ *
+ * Sample Size. Defines the total number of Entropy samples that will be taken
+ * during Entropy generation. This field is writable only if MCTL[PRGM] bit is 1.
+ * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 09C4h
+ * (decimal 2500) by writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SDCTL_SAMP_SIZE field. */
+#define TRNG_RD_SDCTL_SAMP_SIZE(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_SAMP_SIZE_MASK) >> TRNG_SDCTL_SAMP_SIZE_SHIFT)
+
+/*! @brief Set the SAMP_SIZE field to a new value. */
+#define TRNG_WR_SDCTL_SAMP_SIZE(base, value) \
+    (TRNG_RMW_SDCTL(base, TRNG_SDCTL_SAMP_SIZE_MASK, TRNG_SDCTL_SAMP_SIZE(value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_SDCTL, field ENT_DLY[31:16] (RW)
+ *
+ * Entropy Delay. Defines the length (in system clocks) of each Entropy sample
+ * taken. This field is writable only if MCTL[PRGM] bit is 1. This field will read
+ * zeroes if MCTL[PRGM] = 0. This field is cleared to 0C80h (decimal 3200) by
+ * writing the MCTL[RST_DEF] bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SDCTL_ENT_DLY field. */
+#define TRNG_RD_SDCTL_ENT_DLY(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_ENT_DLY_MASK) >> TRNG_SDCTL_ENT_DLY_SHIFT)
+
+/*! @brief Set the ENT_DLY field to a new value. */
+#define TRNG_WR_SDCTL_ENT_DLY(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_ENT_DLY_MASK, TRNG_SDCTL_ENT_DLY(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_SBLIM - RNG Sparse Bit Limit Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_SBLIM - RNG Sparse Bit Limit Register (RW)
+ *
+ * Reset value: 0x0000003FU
+ *
+ * The RNG Sparse Bit Limit Register is used when Von Neumann sampling is
+ * selected during Entropy Generation. It defines the maximum number of consecutive Von
+ * Neumann samples which may be discarded before an error is generated. Note
+ * that this address (0xBASE_0614) is used as SBLIM only if MCTL[PRGM] is 1. If
+ * MCTL[PRGM] is 0, this address is used as TOTSAM readback register.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_SBLIM register
+ */
+/*@{*/
+#define TRNG_SBLIM_REG(base) ((base)->SBLIM)
+#define TRNG_RD_SBLIM(base) (TRNG_SBLIM_REG(base))
+#define TRNG_WR_SBLIM(base, value) (TRNG_SBLIM_REG(base) = (value))
+#define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TRNG_SBLIM bitfields
+ */
+
+/*!
+ * @name Register TRNG_SBLIM, field SB_LIM[9:0] (RW)
+ *
+ * Sparse Bit Limit. During Von Neumann sampling (if enabled by MCTL[SAMP_MODE],
+ * samples are discarded if two consecutive raw samples are both 0 or both 1. If
+ * this discarding occurs for a long period of time, it indicates that there is
+ * insufficient Entropy. The Sparse Bit Limit defines the maximum number of
+ * consecutive samples that may be discarded before an error is generated. This field
+ * is writable only if MCTL[PRGM] bit is 1. This register is cleared to 03hF by
+ * writing the MCTL[RST_DEF] bit to 1. Note that if MCTL[PRGM] bit is 0, this
+ * register address is used to read the Total Samples count in register TOTSAM, as
+ * defined in the following section.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SBLIM_SB_LIM field. */
+#define TRNG_RD_SBLIM_SB_LIM(base) ((TRNG_SBLIM_REG(base) & TRNG_SBLIM_SB_LIM_MASK) >> TRNG_SBLIM_SB_LIM_SHIFT)
+
+/*! @brief Set the SB_LIM field to a new value. */
+#define TRNG_WR_SBLIM_SB_LIM(base, value) (TRNG_RMW_SBLIM(base, TRNG_SBLIM_SB_LIM_MASK, TRNG_SBLIM_SB_LIM(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_SCMISC - RNG Statistical Check Miscellaneous Register (RW)
+ *
+ * Reset value: 0x0001001FU
+ *
+ * The RNG Statistical Check Miscellaneous Register contains the Long Run
+ * Maximum Limit value and the Retry Count value. This register is accessible only when
+ * the MCTL[PRGM] bit is 1, otherwise this register will read zeroes, and cannot
+ * be written.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_SCMISC register
+ */
+/*@{*/
+#define TRNG_SCMISC_REG(base) ((base)->SCMISC)
+#define TRNG_RD_SCMISC(base) (TRNG_SCMISC_REG(base))
+#define TRNG_WR_SCMISC(base, value) (TRNG_SCMISC_REG(base) = (value))
+#define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual TRNG_SCMISC bitfields
+ */
+
+/*!
+ * @name Register TRNG_SCMISC, field LRUN_MAX[7:0] (RW)
+ *
+ * LONG RUN MAX LIMIT. This value is the largest allowable number of consecutive
+ * samples of all 1, or all 0, that is allowed during the Entropy generation.
+ * This field is writable only if MCTL[PRGM] bit is 1. This field will read zeroes
+ * if MCTL[PRGM] = 0. This field is cleared to 22h by writing the MCTL[RST_DEF]
+ * bit to 1.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SCMISC_LRUN_MAX field. */
+#define TRNG_RD_SCMISC_LRUN_MAX(base) \
+    ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_LRUN_MAX_MASK) >> TRNG_SCMISC_LRUN_MAX_SHIFT)
+
+/*! @brief Set the LRUN_MAX field to a new value. */
+#define TRNG_WR_SCMISC_LRUN_MAX(base, value) \
+    (TRNG_RMW_SCMISC(base, TRNG_SCMISC_LRUN_MAX_MASK, TRNG_SCMISC_LRUN_MAX(value)))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_ENT - RNG TRNG Entropy Read Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_ENT - RNG TRNG Entropy Read Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The RNG TRNG can be programmed to generate an entropy value that is readable
+ * via the SkyBlue bus. To do this, set the MCTL[TRNG_ACC] bit to 1. Once the
+ * entropy value has been generated, the MCTL[ENT_VAL] bit will be set to 1. At this
+ * point, ENT0 through ENT15 may be read to retrieve the 512-bit entropy value.
+ * Note that once ENT15 is read, the entropy value will be cleared and a new
+ * value will begin generation, so it is important that ENT15 be read last. These
+ * registers are readable only when MCTL[PRGM] = 0 (Run Mode), MCTL[TRNG_ACC] = 1
+ * (TRNG access mode) and MCTL[ENT_VAL] = 1, otherwise zeroes will be read.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_ENT register
+ */
+/*@{*/
+#define TRNG_ENT_REG(base, index) ((base)->ENT[index])
+#define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * TRNG_SEC_CFG - RNG Security Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief TRNG_SEC_CFG - RNG Security Configuration Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The RNG Security Configuration Register is a read/write register used to
+ * control the test mode, programmability and state modes of the RNG. Many bits are
+ * place holders for this version. More configurability will be added here. Clears
+ * on asynchronous reset. For SA-TRNG releases before 2014/July/01, offsets 0xA0
+ * to 0xAC used to be 0xB0 to 0xBC respectively. So, update newer tests that use
+ * these registers, if hard coded.
+ */
+/*!
+ * @name Constants and macros for entire TRNG_SEC_CFG register
+ */
+/*@{*/
+#define TRNG_SEC_CFG_REG(base) ((base)->SEC_CFG)
+#define TRNG_RD_SEC_CFG(base) (TRNG_SEC_CFG_REG(base))
+#define TRNG_WR_SEC_CFG(base, value) (TRNG_SEC_CFG_REG(base) = (value))
+#define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*!
+ * @name Register TRNG_SEC_CFG, field NO_PRGM[1] (RW)
+ *
+ * If set the TRNG registers cannot be programmed. That is, regardless of the
+ * TRNG access mode in the SA-TRNG Miscellaneous Control Register.
+ *
+ * Values:
+ * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous
+ *     Control Register's access mode bit.
+ * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents
+ *     TRNG register programming.
+ */
+/*@{*/
+/*! @brief Read current value of the TRNG_SEC_CFG_NO_PRGM field. */
+#define TRNG_RD_SEC_CFG_NO_PRGM(base) \
+    ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_NO_PRGM_MASK) >> TRNG_SEC_CFG_NO_PRGM_SHIFT)
+
+/*! @brief Set the NO_PRGM field to a new value. */
+#define TRNG_WR_SEC_CFG_NO_PRGM(base, value) \
+    (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_NO_PRGM_MASK, TRNG_SEC_CFG_NO_PRGM(value)))
+/*@}*/
+
+/*******************************************************************************
+ * Prototypes
+ *******************************************************************************/
+static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig);
+static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count);
+static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base,
+                                              trng_statistical_check_t statistical_check,
+                                              const trng_statistical_check_limit_t *limit);
+static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : TRNG_InitUserConfigDefault
+ * Description   :  Initializes user configuration structure to default settings.
+ *
+ *END*************************************************************************/
+status_t TRNG_GetDefaultConfig(trng_config_t *userConfig)
+{
+    status_t result;
+
+    if (userConfig != 0)
+    {
+        userConfig->lock = TRNG_USER_CONFIG_DEFAULT_LOCK;
+        userConfig->clockMode = kTRNG_ClockModeRingOscillator;
+        userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV;
+        userConfig->sampleMode = kTRNG_SampleModeRaw;
+        userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY;
+        userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE;
+        userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT;
+
+        /* Statistical Check Parameters.*/
+        userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT;
+        userConfig->longRunMaxLimit = TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT;
+
+        userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM;
+        userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM;
+        userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM;
+        userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM;
+        userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM;
+        userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM;
+        userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM;
+        userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM;
+        userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM;
+        userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM;
+        userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM;
+        userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM;
+        userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM;
+        userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM;
+        userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM;
+        userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM;
+        userConfig->frequencyCountLimit.maximum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM;
+        userConfig->frequencyCountLimit.minimum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM;
+
+        result = kStatus_Success;
+    }
+    else
+    {
+        result = kStatus_InvalidArgument;
+    }
+
+    return result;
+}
+
+/*!
+ * @brief Sets the TRNG retry count.
+ *
+ * This function sets the retry counter which defines the number of times a
+ * statistical check may fails during the TRNG Entropy Generation before
+ * generating an error.
+*/
+static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count)
+{
+    status_t status;
+
+    if ((retry_count >= 1u) && (retry_count <= 15u))
+    {
+        /* Set retry count.*/
+        TRNG_WR_SCMISC_RTY_CT(base, retry_count);
+        status = kStatus_Success;
+    }
+    else
+    {
+        status = kStatus_InvalidArgument;
+    }
+    return status;
+}
+
+/*!
+ * @brief Sets statistical check limits.
+ *
+ * This function is used to set minimum and maximum limits of statistical checks.
+ *
+ */
+static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base,
+                                              trng_statistical_check_t statistical_check,
+                                              const trng_statistical_check_limit_t *limit)
+{
+    uint32_t range;
+    status_t status = kStatus_Success;
+
+    if (limit && (limit->maximum > limit->minimum))
+    {
+        range = limit->maximum - limit->minimum; /* Registers use range instead of minimum value.*/
+
+        switch (statistical_check)
+        {
+            case kTRNG_StatisticalCheckMonobit: /* Allowable maximum and minimum number of ones/zero detected during
+                                                   entropy generation. */
+                if ((range <= 0xffffu) && (limit->maximum <= 0xffffu))
+                {
+                    TRNG_WR_SCML_MONO_MAX(base, limit->maximum);
+                    TRNG_WR_SCML_MONO_RNG(base, range);
+                }
+                else
+                {
+                    status = kStatus_InvalidArgument;
+                }
+                break;
+            case kTRNG_StatisticalCheckRunBit1: /* Allowable maximum and minimum number of runs of length 1 detected
+                                                   during entropy generation. */
+                if ((range <= 0x7fffu) && (limit->maximum <= 0x7fffu))
+                {
+                    TRNG_WR_SCR1L_RUN1_MAX(base, limit->maximum);
+                    TRNG_WR_SCR1L_RUN1_RNG(base, range);
+                }
+                else
+                {
+                    status = kStatus_InvalidArgument;
+                }
+                break;
+            case kTRNG_StatisticalCheckRunBit2: /* Allowable maximum and minimum number of runs of length 2 detected
+                                                   during entropy generation. */
+                if ((range <= 0x3fffu) && (limit->maximum <= 0x3fffu))
+                {
+                    TRNG_WR_SCR2L_RUN2_MAX(base, limit->maximum);
+                    TRNG_WR_SCR2L_RUN2_RNG(base, range);
+                }
+                else
+                {
+                    status = kStatus_InvalidArgument;
+                }
+                break;
+            case kTRNG_StatisticalCheckRunBit3: /* Allowable maximum and minimum number of runs of length 3 detected
+                                                   during entropy generation. */
+                if ((range <= 0x1fffu) && (limit->maximum <= 0x1fffu))
+                {
+                    TRNG_WR_SCR3L_RUN3_MAX(base, limit->maximum);
+                    TRNG_WR_SCR3L_RUN3_RNG(base, range);
+                }
+                else
+                {
+                    status = kStatus_InvalidArgument;
+                }
+                break;
+            case kTRNG_StatisticalCheckRunBit4: /* Allowable maximum and minimum number of runs of length 4 detected
+                                                   during entropy generation. */
+                if ((range <= 0xfffu) && (limit->maximum <= 0xfffu))
+                {
+                    TRNG_WR_SCR4L_RUN4_MAX(base, limit->maximum);
+                    TRNG_WR_SCR4L_RUN4_RNG(base, range);
+                }
+                else
+                {
+                    status = kStatus_InvalidArgument;
+                }
+                break;
+            case kTRNG_StatisticalCheckRunBit5: /* Allowable maximum and minimum number of runs of length 5 detected
+                                                   during entropy generation. */
+                if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu))
+                {
+                    TRNG_WR_SCR5L_RUN5_MAX(base, limit->maximum);
+                    TRNG_WR_SCR5L_RUN5_RNG(base, range);
+                }
+                else
+                {
+                    status = kStatus_InvalidArgument;
+                }
+                break;
+            case kTRNG_StatisticalCheckRunBit6Plus: /* Allowable maximum and minimum number of length 6 or more detected
+                                                       during entropy generation */
+                if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu))
+                {
+                    TRNG_WR_SCR6PL_RUN6P_MAX(base, limit->maximum);
+                    TRNG_WR_SCR6PL_RUN6P_RNG(base, range);
+                }
+                else
+                {
+                    status = kStatus_InvalidArgument;
+                }
+                break;
+            case kTRNG_StatisticalCheckPoker: /* Allowable maximum and minimum limit of "Poker Test" detected during
+                                                 entropy generation . */
+                if ((range <= 0xffffu) && (limit->maximum <= 0xffffffu))
+                {
+                    TRNG_WR_PKRMAX_PKR_MAX(base, limit->maximum);
+                    TRNG_WR_PKRRNG_PKR_RNG(base, range);
+                }
+                else
+                {
+                    status = kStatus_InvalidArgument;
+                }
+                break;
+            case kTRNG_StatisticalCheckFrequencyCount: /* Allowable maximum and minimum limit of entropy sample frquency
+                                                          count during entropy generation . */
+                if ((limit->minimum <= 0x3fffffu) && (limit->maximum <= 0x3fffffu))
+                {
+                    TRNG_WR_FRQMAX_FRQ_MAX(base, limit->maximum);
+                    TRNG_WR_FRQMIN_FRQ_MIN(base, limit->minimum);
+                }
+                else
+                {
+                    status = kStatus_InvalidArgument;
+                }
+                break;
+            default:
+                status = kStatus_InvalidArgument;
+                break;
+        }
+    }
+
+    return status;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : trng_ApplyUserConfig
+ * Description   : Apply user configuration settings to TRNG module.
+ *
+ *END*************************************************************************/
+static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig)
+{
+    status_t status;
+
+    if (((status = trng_SetRetryCount(base, userConfig->retryCount)) == kStatus_Success) &&
+        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit)) ==
+         kStatus_Success) &&
+        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit)) ==
+         kStatus_Success) &&
+        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit)) ==
+         kStatus_Success) &&
+        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit)) ==
+         kStatus_Success) &&
+        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit)) ==
+         kStatus_Success) &&
+        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit)) ==
+         kStatus_Success) &&
+        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus,
+                                                 &userConfig->runBit6PlusLimit)) == kStatus_Success) &&
+        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit)) ==
+         kStatus_Success) &&
+        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount,
+                                                 &userConfig->frequencyCountLimit)) == kStatus_Success))
+    {
+        TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode);
+        TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv);
+        TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode);
+        TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay);
+        TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize);
+        TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit);
+        TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit);
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Gets a entry data from the TRNG.
+ *
+ * This function gets an entropy data from TRNG.
+ * Entropy data is spread over TRNG_ENT_COUNT registers.
+ * Read register number is defined by index parameter.
+*/
+static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index)
+{
+    uint32_t data;
+
+    index = index % TRNG_ENT_COUNT; /* This way we can use incremental index without limit control from application.*/
+
+    data = TRNG_RD_ENT(base, index);
+
+    if (index == (TRNG_ENT_COUNT - 1))
+    {
+        /* Dummy read. Defect workaround.
+         * TRNG could not clear ENT_VAL  flag automatically, application
+         * had to do a dummy reading operation for anyone TRNG register
+         * to clear it firstly, then to read the RTENT0 to RTENT15 again */
+        index = TRNG_RD_ENT(base, 0);
+    }
+
+    return data;
+}
+
+status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig)
+{
+    status_t result;
+
+    /* Check input parameters.*/
+    if ((base != 0) && (userConfig != 0))
+    {
+        /* Enable the clock gate. */
+        CLOCK_EnableClock(kCLOCK_Trng0);
+
+        /* Reset the registers of TRNG module to reset state. */
+        /* Must be in program mode.*/
+        TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram);
+        /* Reset Defaults.*/
+        TRNG_WR_MCTL_RST_DEF(base, 1);
+
+        /* Set configuration.*/
+        if ((result = trng_ApplyUserConfig(base, userConfig)) == kStatus_Success)
+        {
+            /* Start entropy generation.*/
+            /* Set to Run mode.*/
+            TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeRun);
+            /* Enable TRNG Access Mode. To generate an Entropy
+            * value that can be read via the true0-true15 registers.*/
+            TRNG_WR_MCTL_TRNG_ACC(base, 1);
+
+            if (userConfig->lock == 1) /* Disable programmability of TRNG registers. */
+            {
+                TRNG_WR_SEC_CFG_NO_PRGM(base, 1);
+            }
+
+            result = kStatus_Success;
+        }
+    }
+    else
+    {
+        result = kStatus_InvalidArgument;
+    }
+
+    return result;
+}
+
+void TRNG_Deinit(TRNG_Type *base)
+{
+    /* Check input parameters.*/
+    if (base)
+    {
+        /* Move to program mode. Stop entropy generation.*/
+        TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram);
+
+        /* Check before clock stop.
+         TRNG turns on the TRNG free-running ring oscillator whenever new entropy
+         is being generated and turns off the ring oscillator when entropy generation
+         is complete. If the TRNG clock is stopped while the TRNG ring oscillator
+         is running, the oscillator continues running though the RNG clock.
+         is stopped. */
+        while (TRNG_RD_MCTL_TSTOP_OK(base) == 0)
+        {
+        }
+
+        /* Disable Clock*/
+        CLOCK_DisableClock(kCLOCK_Trng0);
+    }
+}
+
+status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize)
+{
+    status_t result = kStatus_Success;
+    uint32_t random_32;
+    uint8_t *random_p;
+    uint32_t random_size;
+    uint8_t *data_p = (uint8_t *)data;
+    uint32_t i;
+    int index = 0;
+
+    /* Check input parameters.*/
+    if (base && data && dataSize)
+    {
+        do
+        {
+            /* Wait for Valid or Error flag*/
+            while ((TRNG_RD_MCTL_ENT_VAL(base) == 0) && (TRNG_RD_MCTL_ERR(base) == 0))
+            {
+            }
+
+            /* Check HW error.*/
+            if (TRNG_RD_MCTL_ERR(base))
+            {
+                result = kStatus_Fail; /* TRNG module error occurred */
+                /* Clear error.*/
+                TRNG_WR_MCTL_ERR(base, 1);
+                break; /* No sense stay here.*/
+            }
+
+            /* Read Entropy.*/
+            random_32 = trng_ReadEntropy(base, index++);
+
+            random_p = (uint8_t *)&random_32;
+
+            if (dataSize < sizeof(random_32))
+            {
+                random_size = dataSize;
+            }
+            else
+            {
+                random_size = sizeof(random_32);
+            }
+
+            for (i = 0U; i < random_size; i++)
+            {
+                *data_p++ = *random_p++;
+            }
+
+            dataSize -= random_size;
+        } while (dataSize > 0);
+
+        /* Start a new entropy generation.
+        It is done by reading of the last entropy register.*/
+        if ((index % TRNG_ENT_COUNT) != (TRNG_ENT_COUNT - 1))
+        {
+            trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1));
+        }
+    }
+    else
+    {
+        result = kStatus_InvalidArgument;
+    }
+
+    return result;
+}
+
+#endif /* FSL_FEATURE_SOC_TRNG_COUNT */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_trng.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_trng.h
new file mode 100644
index 00000000000..53354c04991
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_trng.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_TRNG_DRIVER_H_
+#define _FSL_TRNG_DRIVER_H_
+
+#include "fsl_common.h"
+
+#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT
+
+/*!
+ * @addtogroup trng_driver
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief TRNG driver version 2.0.1. 
+ *
+ * Current version: 2.0.1
+ *
+ * Change log:
+ * - Version 2.0.1
+ *   - add support for KL8x and KL28Z
+ *   - update default OSCDIV for K81 to divide by 2
+ */
+#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*! @brief TRNG sample mode. Used by trng_config_t. */
+typedef enum _trng_sample_mode
+{
+    kTRNG_SampleModeVonNeumann = 0U, /*!< Use von Neumann data in both Entropy shifter and Statistical Checker. */
+    kTRNG_SampleModeRaw = 1U,        /*!< Use raw data into both Entropy shifter and Statistical Checker. */
+    kTRNG_SampleModeVonNeumannRaw =
+        2U /*!< Use von Neumann data in Entropy shifter. Use raw data into Statistical Checker. */
+} trng_sample_mode_t;
+
+/*! @brief TRNG clock mode. Used by trng_config_t. */
+typedef enum _trng_clock_mode
+{
+    kTRNG_ClockModeRingOscillator = 0U, /*!< Ring oscillator is used to operate the TRNG (default). */
+    kTRNG_ClockModeSystem = 1U          /*!< System clock is used to operate the TRNG. This is for test use only, and
+                                           indeterminate results may occur. */
+} trng_clock_mode_t;
+
+/*! @brief TRNG ring oscillator divide. Used by trng_config_t. */
+typedef enum _trng_ring_osc_div
+{
+    kTRNG_RingOscDiv0 = 0U, /*!< Ring oscillator with no divide */
+    kTRNG_RingOscDiv2 = 1U, /*!< Ring oscillator divided-by-2. */
+    kTRNG_RingOscDiv4 = 2U, /*!< Ring oscillator divided-by-4. */
+    kTRNG_RingOscDiv8 = 3U  /*!< Ring oscillator divided-by-8. */
+} trng_ring_osc_div_t;
+
+/*! @brief Data structure for definition of statistical check limits. Used by trng_config_t. */
+typedef struct _trng_statistical_check_limit
+{
+    uint32_t maximum; /*!< Maximum limit.*/
+    uint32_t minimum; /*!< Minimum limit.*/
+} trng_statistical_check_limit_t;
+
+/*!
+ * @brief Data structure for the TRNG initialization
+ *
+ * This structure initializes the TRNG by calling the the TRNG_Init() function.
+ * It contains all TRNG configurations.
+ */
+typedef struct _trng_user_config
+{
+    bool lock;                      /*!< @brief Disable programmability of TRNG registers.  */
+    trng_clock_mode_t clockMode;    /*!< @brief Clock mode used to operate TRNG.*/
+    trng_ring_osc_div_t ringOscDiv; /*!< @brief Ring oscillator divide used by TRNG. */
+    trng_sample_mode_t sampleMode;  /*!< @brief Sample mode of the TRNG ring oscillator. */
+    /* Seed Control*/
+    uint16_t
+        entropyDelay; /*!< @brief Entropy Delay. Defines the length (in system clocks) of each Entropy sample taken. */
+    uint16_t sampleSize; /*!< @brief Sample Size. Defines the total number of Entropy samples that will be taken during
+                            Entropy generation. */
+    uint16_t
+        sparseBitLimit; /*!< @brief Sparse Bit Limit which defines the maximum number of
+                        * consecutive samples that may be discarded before an error is generated.
+                        * This limit is used only for during von Neumann sampling (enabled by TRNG_HAL_SetSampleMode()).
+                        * Samples are discarded if two consecutive raw samples are both 0 or both 1. If
+                        * this discarding occurs for a long period of time, it indicates that there is
+                        * insufficient Entropy. */
+    /* Statistical Check Parameters.*/
+    uint8_t retryCount;      /*!< @brief Retry count. It defines the number of times a statistical check may fails
+                             * during the TRNG Entropy Generation before generating an error. */
+    uint8_t longRunMaxLimit; /*!< @brief Largest allowable number of consecutive samples of all 1, or all 0,
+                             * that is allowed during the Entropy generation. */
+    trng_statistical_check_limit_t
+        monobitLimit; /*!< @brief Maximum and minimum limits for statistical check of number of ones/zero detected
+                         during entropy generation. */
+    trng_statistical_check_limit_t
+        runBit1Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 1
+                         detected during entropy generation. */
+    trng_statistical_check_limit_t
+        runBit2Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 2
+                         detected during entropy generation. */
+    trng_statistical_check_limit_t
+        runBit3Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 3
+                         detected during entropy generation. */
+    trng_statistical_check_limit_t
+        runBit4Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 4
+                         detected during entropy generation. */
+    trng_statistical_check_limit_t
+        runBit5Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 5
+                         detected during entropy generation. */
+    trng_statistical_check_limit_t runBit6PlusLimit; /*!< @brief Maximum and minimum limits for statistical check of
+                                                        number of runs of length 6 or more detected during entropy
+                                                        generation. */
+    trng_statistical_check_limit_t
+        pokerLimit; /*!< @brief Maximum and minimum limits for statistical check of "Poker Test". */
+    trng_statistical_check_limit_t
+        frequencyCountLimit; /*!< @brief Maximum and minimum limits for statistical check of entropy sample frequency
+                                count. */
+} trng_config_t;
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes user configuration structure to default.
+ *
+ * This function initializes the configure structure to default value. the default
+ * value are:
+ * @code
+ *     user_config->lock = 0;
+ *     user_config->clockMode = kTRNG_ClockModeRingOscillator;
+ *     user_config->ringOscDiv = kTRNG_RingOscDiv0;  Or  to other kTRNG_RingOscDiv[2|8] depending on platform.
+ *     user_config->sampleMode = kTRNG_SampleModeRaw;
+ *     user_config->entropyDelay = 3200;
+ *     user_config->sampleSize = 2500;
+ *     user_config->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT;
+ *     user_config->retryCount = 63;
+ *     user_config->longRunMaxLimit = 34;
+ *     user_config->monobitLimit.maximum = 1384;
+ *     user_config->monobitLimit.minimum = 1116;
+ *     user_config->runBit1Limit.maximum = 405;
+ *     user_config->runBit1Limit.minimum = 227;
+ *     user_config->runBit2Limit.maximum = 220;
+ *     user_config->runBit2Limit.minimum = 98;
+ *     user_config->runBit3Limit.maximum = 125;
+ *     user_config->runBit3Limit.minimum = 37;
+ *     user_config->runBit4Limit.maximum = 75;
+ *     user_config->runBit4Limit.minimum = 11;
+ *     user_config->runBit5Limit.maximum = 47;
+ *     user_config->runBit5Limit.minimum = 1;
+ *     user_config->runBit6PlusLimit.maximum = 47;
+ *     user_config->runBit6PlusLimit.minimum = 1;
+ *     user_config->pokerLimit.maximum = 26912;
+ *     user_config->pokerLimit.minimum = 24445;
+ *     user_config->frequencyCountLimit.maximum = 25600;
+ *     user_config->frequencyCountLimit.minimum = 1600;
+ * @endcode
+ *
+ * @param user_config   User configuration structure.
+ * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error.
+ */
+status_t TRNG_GetDefaultConfig(trng_config_t *userConfig);
+
+/*!
+ * @brief Initializes the TRNG.
+ *
+ * This function initializes the TRNG.
+ * When called, the TRNG entropy generation starts immediately.
+ *
+ * @param base  TRNG base address
+ * @param userConfig    Pointer to initialize configuration structure.
+ * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error.
+ */
+status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig);
+
+/*!
+ * @brief Shuts down the TRNG.
+ *
+ * This function shuts down the TRNG.
+ *
+ * @param base  TRNG base address
+ */
+void TRNG_Deinit(TRNG_Type *base);
+
+/*!
+ * @brief Gets random data.
+ *
+ * This function gets random data from the TRNG.
+ *
+ * @param base  TRNG base address
+ * @param data  Pointer address used to store random data
+ * @param dataSize  Size of the buffer pointed by the data parameter
+ * @return random data
+ */
+status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_TRNG_COUNT */
+#endif /*_FSL_TRNG_H_*/
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tsi_v4.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tsi_v4.c
new file mode 100644
index 00000000000..841627e6fdd
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tsi_v4.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_tsi_v4.h"
+
+void TSI_Init(TSI_Type *base, const tsi_config_t *config)
+{
+    assert(config != NULL);
+
+    bool is_module_enabled = false;
+    bool is_int_enabled = false;
+
+    CLOCK_EnableClock(kCLOCK_Tsi0);
+    if (base->GENCS & TSI_GENCS_TSIEN_MASK)
+    {
+        is_module_enabled = true;
+        TSI_EnableModule(base, false);
+    }
+    if (base->GENCS & TSI_GENCS_TSIIEN_MASK)
+    {
+        is_int_enabled = true;
+        TSI_DisableInterrupts(base, kTSI_GlobalInterruptEnable);
+    }
+
+    TSI_SetHighThreshold(base, config->thresh);
+    TSI_SetLowThreshold(base, config->thresl);
+    TSI_SetElectrodeOSCPrescaler(base, config->prescaler);
+    TSI_SetReferenceChargeCurrent(base, config->refchrg);
+    TSI_SetElectrodeChargeCurrent(base, config->extchrg);
+    TSI_SetNumberOfScans(base, config->nscn);
+    TSI_SetAnalogMode(base, config->mode);
+    TSI_SetOscVoltageRails(base, config->dvolt);
+    TSI_SetElectrodeSeriesResistor(base, config->resistor);
+    TSI_SetFilterBits(base, config->filter);
+
+    if (is_module_enabled)
+    {
+        TSI_EnableModule(base, true);
+    }
+    if (is_int_enabled)
+    {
+        TSI_EnableInterrupts(base, kTSI_GlobalInterruptEnable);
+    }
+}
+
+void TSI_Deinit(TSI_Type *base)
+{
+    base->GENCS = 0U;
+    base->DATA = 0U;
+    base->TSHD = 0U;
+    CLOCK_DisableClock(kCLOCK_Tsi0);
+}
+
+void TSI_GetNormalModeDefaultConfig(tsi_config_t *userConfig)
+{
+    userConfig->thresh = 0U;
+    userConfig->thresl = 0U;
+    userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
+    userConfig->extchrg = kTSI_ExtOscChargeCurrent_4uA;
+    userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
+    userConfig->nscn = kTSI_ConsecutiveScansNumber_5time;
+    userConfig->mode = kTSI_AnalogModeSel_Capacitive;
+    userConfig->dvolt = kTSI_OscVolRailsOption_0;
+    userConfig->resistor = kTSI_SeriesResistance_32k;
+    userConfig->filter = kTSI_FilterBits_3;
+}
+
+void TSI_GetLowPowerModeDefaultConfig(tsi_config_t *userConfig)
+{
+    userConfig->thresh = 400U;
+    userConfig->thresl = 0U;
+    userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
+    userConfig->extchrg = kTSI_ExtOscChargeCurrent_4uA;
+    userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
+    userConfig->nscn = kTSI_ConsecutiveScansNumber_5time;
+    userConfig->mode = kTSI_AnalogModeSel_Capacitive;
+    userConfig->dvolt = kTSI_OscVolRailsOption_0;
+    userConfig->resistor = kTSI_SeriesResistance_32k;
+    userConfig->filter = kTSI_FilterBits_3;
+}
+
+void TSI_Calibrate(TSI_Type *base, tsi_calibration_data_t *calBuff)
+{
+    assert(calBuff != NULL);
+
+    uint8_t i = 0U;
+    bool is_int_enabled = false;
+
+    if (base->GENCS & TSI_GENCS_TSIIEN_MASK)
+    {
+        is_int_enabled = true;
+        TSI_DisableInterrupts(base, kTSI_GlobalInterruptEnable);
+    }
+    for (i = 0U; i < FSL_FEATURE_TSI_CHANNEL_COUNT; i++)
+    {
+        TSI_SetMeasuredChannelNumber(base, i);
+        TSI_StartSoftwareTrigger(base);
+        while (!(TSI_GetStatusFlags(base) & kTSI_EndOfScanFlag))
+        {
+        }
+        calBuff->calibratedData[i] = TSI_GetCounter(base);
+        TSI_ClearStatusFlags(base, kTSI_EndOfScanFlag);
+    }
+    if (is_int_enabled)
+    {
+        TSI_EnableInterrupts(base, kTSI_GlobalInterruptEnable);
+    }
+}
+
+void TSI_EnableInterrupts(TSI_Type *base, uint32_t mask)
+{
+    uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK);
+
+    if (mask & kTSI_GlobalInterruptEnable)
+    {
+        regValue |= TSI_GENCS_TSIIEN_MASK;
+    }
+    if (mask & kTSI_OutOfRangeInterruptEnable)
+    {
+        regValue &= (~TSI_GENCS_ESOR_MASK);
+    }
+    if (mask & kTSI_EndOfScanInterruptEnable)
+    {
+        regValue |= TSI_GENCS_ESOR_MASK;
+    }
+
+    base->GENCS = regValue;     /* write value to register */
+}
+
+void TSI_DisableInterrupts(TSI_Type *base, uint32_t mask)
+{
+    uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK);
+
+    if (mask & kTSI_GlobalInterruptEnable)
+    {
+        regValue &= (~TSI_GENCS_TSIIEN_MASK);
+    }
+    if (mask & kTSI_OutOfRangeInterruptEnable)
+    {
+        regValue |= TSI_GENCS_ESOR_MASK;
+    }
+    if (mask & kTSI_EndOfScanInterruptEnable)
+    {
+        regValue &= (~TSI_GENCS_ESOR_MASK);
+    }
+
+    base->GENCS = regValue;     /* write value to register */
+}
+
+void TSI_ClearStatusFlags(TSI_Type *base, uint32_t mask)
+{
+    uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK);
+
+    if (mask & kTSI_EndOfScanFlag)
+    {
+        regValue |= TSI_GENCS_EOSF_MASK;
+    }
+    if (mask & kTSI_OutOfRangeFlag)
+    {
+        regValue |= TSI_GENCS_OUTRGF_MASK;
+    }
+
+    base->GENCS = regValue;     /* write value to register */
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tsi_v4.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tsi_v4.h
new file mode 100644
index 00000000000..e4f189ef226
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_tsi_v4.h
@@ -0,0 +1,710 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_TSI_V4_H_
+#define _FSL_TSI_V4_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup tsi_v4_driver
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief TSI driver version */
+#define FSL_TSI_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
+/*@}*/
+
+/*! @brief TSI status flags macro collection */
+#define ALL_FLAGS_MASK  (TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK)
+
+/*! @brief resistor bit shift in EXTCHRG bit-field */
+#define TSI_V4_EXTCHRG_RESISTOR_BIT_SHIFT TSI_GENCS_EXTCHRG_SHIFT
+
+/*! @brief filter bits shift in EXTCHRG bit-field  */
+#define TSI_V4_EXTCHRG_FILTER_BITS_SHIFT (1U + TSI_GENCS_EXTCHRG_SHIFT)
+
+/*! @brief macro of clearing the resistor bit in EXTCHRG bit-field */
+#define TSI_V4_EXTCHRG_RESISTOR_BIT_CLEAR \
+    ((uint32_t)((~(ALL_FLAGS_MASK | TSI_GENCS_EXTCHRG_MASK)) | (3U << TSI_V4_EXTCHRG_FILTER_BITS_SHIFT)))
+
+/*! @brief macro of clearing the filter bits in EXTCHRG bit-field */
+#define TSI_V4_EXTCHRG_FILTER_BITS_CLEAR \
+    ((uint32_t)((~(ALL_FLAGS_MASK | TSI_GENCS_EXTCHRG_MASK)) | (1U << TSI_V4_EXTCHRG_RESISTOR_BIT_SHIFT)))
+
+/*!
+ * @brief TSI number of scan intervals for each electrode.
+ *
+ * These constants define the tsi number of consecutive scans in a TSI instance for each electrode.
+ */
+typedef enum _tsi_n_consecutive_scans
+{
+    kTSI_ConsecutiveScansNumber_1time = 0U,   /*!< Once per electrode */
+    kTSI_ConsecutiveScansNumber_2time = 1U,   /*!< Twice per electrode */
+    kTSI_ConsecutiveScansNumber_3time = 2U,   /*!< 3 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_4time = 3U,   /*!< 4 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_5time = 4U,   /*!< 5 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_6time = 5U,   /*!< 6 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_7time = 6U,   /*!< 7 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_8time = 7U,   /*!< 8 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_9time = 8U,   /*!< 9 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_10time = 9U,  /*!< 10 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_11time = 10U, /*!< 11 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_12time = 11U, /*!< 12 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_13time = 12U, /*!< 13 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_14time = 13U, /*!< 14 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_15time = 14U, /*!< 15 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_16time = 15U, /*!< 16 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_17time = 16U, /*!< 17 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_18time = 17U, /*!< 18 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_19time = 18U, /*!< 19 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_20time = 19U, /*!< 20 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_21time = 20U, /*!< 21 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_22time = 21U, /*!< 22 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_23time = 22U, /*!< 23 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_24time = 23U, /*!< 24 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_25time = 24U, /*!< 25 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_26time = 25U, /*!< 26 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_27time = 26U, /*!< 27 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_28time = 27U, /*!< 28 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_29time = 28U, /*!< 29 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_30time = 29U, /*!< 30 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_31time = 30U, /*!< 31 times consecutive scan */
+    kTSI_ConsecutiveScansNumber_32time = 31U  /*!< 32 times consecutive scan */
+} tsi_n_consecutive_scans_t;
+
+/*!
+ * @brief TSI electrode oscillator prescaler.
+ *
+ * These constants define the TSI electrode oscillator prescaler in a TSI instance.
+ */
+typedef enum _tsi_electrode_osc_prescaler
+{
+    kTSI_ElecOscPrescaler_1div = 0U,  /*!< Electrode oscillator frequency divided by 1 */
+    kTSI_ElecOscPrescaler_2div = 1U,  /*!< Electrode oscillator frequency divided by 2 */
+    kTSI_ElecOscPrescaler_4div = 2U,  /*!< Electrode oscillator frequency divided by 4 */
+    kTSI_ElecOscPrescaler_8div = 3U,  /*!< Electrode oscillator frequency divided by 8 */
+    kTSI_ElecOscPrescaler_16div = 4U, /*!< Electrode oscillator frequency divided by 16 */
+    kTSI_ElecOscPrescaler_32div = 5U, /*!< Electrode oscillator frequency divided by 32 */
+    kTSI_ElecOscPrescaler_64div = 6U, /*!< Electrode oscillator frequency divided by 64 */
+    kTSI_ElecOscPrescaler_128div = 7U /*!< Electrode oscillator frequency divided by 128 */
+} tsi_electrode_osc_prescaler_t;
+
+/*!
+ * @brief TSI analog mode select.
+ *
+ * Set up TSI analog modes in a TSI instance.
+ */
+typedef enum _tsi_analog_mode
+{
+    kTSI_AnalogModeSel_Capacitive = 0U,     /*!< Active TSI capacitive sensing mode */
+    kTSI_AnalogModeSel_NoiseNoFreqLim = 4U, /*!< Single threshold noise detection mode with no freq. limitation. */
+    kTSI_AnalogModeSel_NoiseFreqLim = 8U,   /*!< Single threshold noise detection mode with freq. limitation. */
+    kTSI_AnalogModeSel_AutoNoise = 12U      /*!< Active TSI analog in automatic noise detection mode */
+} tsi_analog_mode_t;
+
+/*!
+ * @brief TSI Reference oscillator charge and discharge current select.
+ *
+ * These constants define the TSI Reference oscillator charge current select in a TSI (REFCHRG) instance.
+ */
+typedef enum _tsi_reference_osc_charge_current
+{
+    kTSI_RefOscChargeCurrent_500nA = 0U, /*!< Reference oscillator charge current is 500 µA */
+    kTSI_RefOscChargeCurrent_1uA = 1U,   /*!< Reference oscillator charge current is 1 µA */
+    kTSI_RefOscChargeCurrent_2uA = 2U,   /*!< Reference oscillator charge current is 2 µA */
+    kTSI_RefOscChargeCurrent_4uA = 3U,   /*!< Reference oscillator charge current is 4 µA */
+    kTSI_RefOscChargeCurrent_8uA = 4U,   /*!< Reference oscillator charge current is 8 µA */
+    kTSI_RefOscChargeCurrent_16uA = 5U,  /*!< Reference oscillator charge current is 16 µA */
+    kTSI_RefOscChargeCurrent_32uA = 6U,  /*!< Reference oscillator charge current is 32 µA */
+    kTSI_RefOscChargeCurrent_64uA = 7U   /*!< Reference oscillator charge current is 64 µA */
+} tsi_reference_osc_charge_current_t;
+
+/*!
+ * @brief TSI oscilator's voltage rails.
+ *
+ * These bits indicate the oscillator's voltage rails.
+ */
+typedef enum _tsi_osc_voltage_rails
+{
+    kTSI_OscVolRailsOption_0 = 0U, /*!< DVOLT value option 0, the value may differ on different platforms */
+    kTSI_OscVolRailsOption_1 = 1U, /*!< DVOLT value option 1, the value may differ on different platforms */
+    kTSI_OscVolRailsOption_2 = 2U, /*!< DVOLT value option 2, the value may differ on different platforms */
+    kTSI_OscVolRailsOption_3 = 3U  /*!< DVOLT value option 3, the value may differ on different platforms */
+} tsi_osc_voltage_rails_t;
+
+/*!
+ * @brief TSI External oscillator charge and discharge current select.
+ *
+ * These bits indicate the electrode oscillator charge and discharge current value
+ * in TSI (EXTCHRG) instance.
+ */
+typedef enum _tsi_external_osc_charge_current
+{
+    kTSI_ExtOscChargeCurrent_500nA = 0U, /*!< External oscillator charge current is 500 µA */
+    kTSI_ExtOscChargeCurrent_1uA = 1U,   /*!< External oscillator charge current is 1 µA */
+    kTSI_ExtOscChargeCurrent_2uA = 2U,   /*!< External oscillator charge current is 2 µA */
+    kTSI_ExtOscChargeCurrent_4uA = 3U,   /*!< External oscillator charge current is 4 µA */
+    kTSI_ExtOscChargeCurrent_8uA = 4U,   /*!< External oscillator charge current is 8 µA */
+    kTSI_ExtOscChargeCurrent_16uA = 5U,  /*!< External oscillator charge current is 16 µA */
+    kTSI_ExtOscChargeCurrent_32uA = 6U,  /*!< External oscillator charge current is 32 µA */
+    kTSI_ExtOscChargeCurrent_64uA = 7U   /*!< External oscillator charge current is 64 µA */
+} tsi_external_osc_charge_current_t;
+
+/*!
+ * @brief TSI series resistance RS value select.
+ *
+ * These bits indicate the electrode RS series resistance for the noise mode
+ * in TSI (EXTCHRG) instance.
+ */
+typedef enum _tsi_series_resistance
+{
+    kTSI_SeriesResistance_32k = 0U, /*!< Series Resistance is 32 kilo ohms   */
+    kTSI_SeriesResistance_187k = 1U /*!< Series Resistance is 18 7 kilo ohms  */
+} tsi_series_resistor_t;
+
+/*!
+ * @brief TSI series filter bits select.
+ *
+ * These bits indicate the count of the filter bits
+ * in TSI noise mode EXTCHRG[2:1] bits
+ */
+typedef enum _tsi_filter_bits
+{
+    kTSI_FilterBits_3 = 0U, /*!< 3 filter bits, 8 peaks increments the cnt+1 */
+    kTSI_FilterBits_2 = 1U, /*!< 2 filter bits, 4 peaks increments the cnt+1 */
+    kTSI_FilterBits_1 = 2U, /*!< 1 filter bits, 2 peaks increments the cnt+1 */
+    kTSI_FilterBits_0 = 3U  /*!< no filter bits,1 peak  increments the cnt+1 */
+} tsi_filter_bits_t;
+
+/*! @brief TSI status flags. */
+typedef enum _tsi_status_flags
+{
+    kTSI_EndOfScanFlag = TSI_GENCS_EOSF_MASK,   /*!< End-Of-Scan flag */
+    kTSI_OutOfRangeFlag = TSI_GENCS_OUTRGF_MASK /*!< Out-Of-Range flag */
+} tsi_status_flags_t;
+
+/*! @brief TSI feature interrupt source.*/
+typedef enum _tsi_interrupt_enable
+{
+    kTSI_GlobalInterruptEnable = 1U,     /*!< TSI module global interrupt */
+    kTSI_OutOfRangeInterruptEnable = 2U, /*!< Out-Of-Range interrupt */
+    kTSI_EndOfScanInterruptEnable = 4U   /*!< End-Of-Scan interrupt */
+} tsi_interrupt_enable_t;
+
+/*! @brief TSI calibration data storage. */
+typedef struct _tsi_calibration_data
+{
+    uint16_t calibratedData[FSL_FEATURE_TSI_CHANNEL_COUNT]; /*!< TSI calibration data storage buffer */
+} tsi_calibration_data_t;
+
+/*!
+ * @brief TSI configuration structure.
+ *
+ * This structure contains the settings for the most common TSI configurations including
+ * the TSI module charge currents, number of scans, thresholds, and so on.
+ */
+typedef struct _tsi_config
+{
+    uint16_t thresh;                            /*!< High threshold. */
+    uint16_t thresl;                            /*!< Low threshold. */
+    tsi_electrode_osc_prescaler_t prescaler;    /*!< Prescaler */
+    tsi_external_osc_charge_current_t extchrg;  /*!< Electrode charge current */
+    tsi_reference_osc_charge_current_t refchrg; /*!< Reference charge current */
+    tsi_n_consecutive_scans_t nscn;             /*!< Number of scans. */
+    tsi_analog_mode_t mode;                     /*!< TSI mode of operation. */
+    tsi_osc_voltage_rails_t dvolt;              /*!< Oscillator's voltage rails. */
+    tsi_series_resistor_t resistor;             /*!< Series resistance value  */
+    tsi_filter_bits_t filter;                   /*!< Noise mode filter bits   */
+} tsi_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes hardware.
+ *
+ * @details Initializes the peripheral to the targeted state specified by parameter configuration,
+ *          such as sets prescalers, number of scans, clocks, delta voltage
+ *          series resistor, filter bits, reference, and electrode charge current and threshold.
+ * @param  base    TSI peripheral base address.
+ * @param  config  Pointer to TSI module configuration structure.
+ * @return none
+ */
+void TSI_Init(TSI_Type *base, const tsi_config_t *config);
+
+/*!
+ * @brief De-initializes hardware.
+ *
+ * @details De-initializes the peripheral to default state.
+ *
+ * @param  base  TSI peripheral base address.
+ * @return none
+ */
+void TSI_Deinit(TSI_Type *base);
+
+/*!
+ * @brief Gets the TSI normal mode user configuration structure.
+ * This interface sets userConfig structure to a default value. The configuration structure only
+ * includes the settings for the whole TSI.
+ * The user configure is set to these values:
+ * @code
+    userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
+    userConfig->extchrg = kTSI_ExtOscChargeCurrent_4uA;
+    userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
+    userConfig->nscn = kTSI_ConsecutiveScansNumber_10time;
+    userConfig->mode = kTSI_AnalogModeSel_Capacitive;
+    userConfig->dvolt = kTSI_OscVolRailsOption_0;
+    userConfig->resistor = kTSI_SeriesResistance_32k;
+    userConfig->filter = kTSI_FilterBits_1;
+    userConfig->thresh = 0U;
+    userConfig->thresl = 0U;
+   @endcode
+ *
+ * @param userConfig Pointer to the TSI user configuration structure.
+ */
+void TSI_GetNormalModeDefaultConfig(tsi_config_t *userConfig);
+
+/*!
+ * @brief Gets the TSI low power mode default user configuration structure.
+ * This interface sets userConfig structure to a default value. The configuration structure only
+ * includes the settings for the whole TSI.
+ * The user configure is set to these values:
+ * @code
+    userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
+    userConfig->extchrg = kTSI_ExtOscChargeCurrent_4uA;
+    userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
+    userConfig->nscn = kTSI_ConsecutiveScansNumber_10time;
+    userConfig->mode = kTSI_AnalogModeSel_Capacitive;
+    userConfig->dvolt = kTSI_OscVolRailsOption_0;
+    userConfig->resistor = kTSI_SeriesResistance_32k;
+    userConfig->filter = kTSI_FilterBits_1;
+    userConfig->thresh = 400U;
+    userConfig->thresl = 0U;
+   @endcode
+ *
+ * @param userConfig Pointer to the TSI user configuration structure.
+ */
+void TSI_GetLowPowerModeDefaultConfig(tsi_config_t *userConfig);
+
+/*!
+ * @brief Hardware calibration.
+ *
+ * @details Calibrates the peripheral to fetch the initial counter value of
+ *          the enabled electrodes.
+ *          This API is mostly used at initial application setup. Call
+ *          this function after the \ref TSI_Init API and use the calibrated
+ *          counter values to set up applications (such as to determine
+ *          under which counter value we can confirm a touch event occurs).
+ *
+ * @param   base    TSI peripheral base address.
+ * @param   calBuff Data buffer that store the calibrated counter value.
+ * @return none
+ *
+ */
+void TSI_Calibrate(TSI_Type *base, tsi_calibration_data_t *calBuff);
+
+/*!
+ * @brief Enables the TSI interrupt requests.
+ * @param base TSI peripheral base address.
+ * @param mask interrupt source
+ *     The parameter can be combination of the following source if defined:
+ *     @arg kTSI_GlobalInterruptEnable
+ *     @arg kTSI_EndOfScanInterruptEnable
+ *     @arg kTSI_OutOfRangeInterruptEnable
+ */
+void TSI_EnableInterrupts(TSI_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the TSI interrupt requests.
+ * @param base TSI peripheral base address.
+ * @param mask interrupt source
+ *     The parameter can be combination of the following source if defined:
+ *     @arg kTSI_GlobalInterruptEnable
+ *     @arg kTSI_EndOfScanInterruptEnable
+ *     @arg kTSI_OutOfRangeInterruptEnable
+ */
+void TSI_DisableInterrupts(TSI_Type *base, uint32_t mask);
+
+/*!
+* @brief Gets an interrupt flag.
+* This function gets the TSI interrupt flags.
+*
+* @param    base  TSI peripheral base address.
+* @return         The mask of these status flags combination.
+*/
+static inline uint32_t TSI_GetStatusFlags(TSI_Type *base)
+{
+    return (base->GENCS & (kTSI_EndOfScanFlag | kTSI_OutOfRangeFlag));
+}
+
+/*!
+ * @brief Clears the interrupt flag.
+ *
+ * This function clears the TSI interrupt flag,
+ * automatically cleared flags can't be cleared by this function.
+ *
+ * @param base TSI peripheral base address.
+ * @param mask The status flags to clear.
+ */
+void TSI_ClearStatusFlags(TSI_Type *base, uint32_t mask);
+
+/*!
+* @brief Gets the TSI scan trigger mode.
+*
+* @param  base  TSI peripheral base address.
+* @return       Scan trigger mode.
+*/
+static inline uint32_t TSI_GetScanTriggerMode(TSI_Type *base)
+{
+    return (base->GENCS & TSI_GENCS_STM_MASK);
+}
+
+/*!
+* @brief Gets the scan in progress flag.
+*
+* @param    base TSI peripheral base address.
+* @return   True  - scan is in progress.
+*           False - scan is not in progress.
+*/
+static inline bool TSI_IsScanInProgress(TSI_Type *base)
+{
+    return (base->GENCS & TSI_GENCS_SCNIP_MASK);
+}
+
+/*!
+* @brief Sets the prescaler.
+*
+* @param    base      TSI peripheral base address.
+* @param    prescaler Prescaler value.
+* @return   none.
+*/
+static inline void TSI_SetElectrodeOSCPrescaler(TSI_Type *base, tsi_electrode_osc_prescaler_t prescaler)
+{
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_PS_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_PS(prescaler));
+}
+
+/*!
+* @brief Sets the number of scans (NSCN).
+*
+* @param    base    TSI peripheral base address.
+* @param    number  Number of scans.
+* @return   none.
+*/
+static inline void TSI_SetNumberOfScans(TSI_Type *base, tsi_n_consecutive_scans_t number)
+{
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_NSCN_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_NSCN(number));
+}
+
+/*!
+* @brief Enables/disables the TSI module.
+*
+* @param   base   TSI peripheral base address.
+* @param   enable Choose whether to enable or disable module;
+*                 - true   Enable TSI module;
+*                 - false  Disable TSI module;
+* @return  none.
+*/
+static inline void TSI_EnableModule(TSI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_TSIEN_MASK;    /* Enable module */
+    }
+    else
+    {
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_TSIEN_MASK); /* Disable module */
+    }
+}
+
+/*!
+* @brief Sets the TSI low power STOP mode as enabled or disabled.
+*        This enables the TSI module function in low power modes.
+*
+* @param    base    TSI peripheral base address.
+* @param    enable  Choose to enable or disable STOP mode.
+*                   - true   Enable module in STOP mode;
+*                   - false  Disable module in STOP mode;
+* @return   none.
+*/
+static inline void TSI_EnableLowPower(TSI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_STPE_MASK;    /* Module enabled in low power stop modes */
+    }
+    else
+    {
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_STPE_MASK); /* Module disabled in low power stop modes */
+    }
+}
+
+/*!
+* @brief Enables/disables the hardware trigger scan.
+*
+* @param    base TSI peripheral base address.
+* @param    enable Choose to enable hardware trigger or software trigger scan.
+*                  - true    Enable hardware trigger scan;
+*                  - false   Enable software trigger scan;
+* @return   none.
+*/
+static inline void TSI_EnableHardwareTriggerScan(TSI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_STM_MASK;    /* Enable hardware trigger scan */
+    }
+    else
+    {
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_STM_MASK); /* Enable software trigger scan */
+    }
+}
+
+/*!
+* @brief Starts a software trigger measurement (triggers a new measurement).
+*
+* @param    base TSI peripheral base address.
+* @return   none.
+*/
+static inline void TSI_StartSoftwareTrigger(TSI_Type *base)
+{
+    base->DATA |= TSI_DATA_SWTS_MASK;
+}
+
+/*!
+* @brief Sets the the measured channel number.
+*
+* @param    base    TSI peripheral base address.
+* @param    channel Channel number 0 ... 15.
+* @return   none.
+*/
+static inline void TSI_SetMeasuredChannelNumber(TSI_Type *base, uint8_t channel)
+{
+    assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT);
+
+    base->DATA = ((base->DATA) & ~TSI_DATA_TSICH_MASK) | (TSI_DATA_TSICH(channel));
+}
+
+/*!
+* @brief Gets the current measured channel number.
+*
+* @param    base    TSI peripheral base address.
+* @return   uint8_t    Channel number 0 ... 15.
+*/
+static inline uint8_t TSI_GetMeasuredChannelNumber(TSI_Type *base)
+{
+    return (uint8_t)((base->DATA & TSI_DATA_TSICH_MASK) >> TSI_DATA_TSICH_SHIFT);
+}
+
+/*!
+* @brief Enables/disables the DMA transfer.
+*
+* @param   base   TSI peripheral base address.
+* @param   enable Choose to enable DMA transfer or not.
+*                 - true    Enable DMA transfer;
+*                 - false   Disable DMA transfer;
+* @return  none.
+*/
+static inline void TSI_EnableDmaTransfer(TSI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->DATA |= TSI_DATA_DMAEN_MASK; /* Enable DMA transfer */
+    }
+    else
+    {
+        base->DATA &= ~TSI_DATA_DMAEN_MASK; /* Disable DMA transfer */
+    }
+}
+
+#if defined(FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE) && (FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE == 1)
+/*!
+* @brief Decides whether to enable end of scan DMA transfer request only.
+*
+* @param    base TSI peripheral base address.
+* @param    enable  Choose whether to enable End of Scan DMA transfer request only.
+*                   - true  Enable End of Scan DMA transfer request only;
+*                   - false Both End-of-Scan and Out-of-Range can generate DMA transfer request.
+* @return   none.
+*/
+static inline void TSI_EnableEndOfScanDmaTransferOnly(TSI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_EOSDMEO_MASK; /* Enable End of Scan DMA transfer request only; */
+    }
+    else
+    {
+        base->GENCS =
+            (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_EOSDMEO_MASK); /* Both End-of-Scan and Out-of-Range can generate DMA transfer request. */
+    }
+}
+#endif /* End of (FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE == 1)*/
+
+/*!
+* @brief Gets the conversion counter value.
+*
+* @param    base TSI peripheral base address.
+* @return   Accumulated scan counter value ticked by the reference clock.
+*/
+static inline uint16_t TSI_GetCounter(TSI_Type *base)
+{
+    return (uint16_t)(base->DATA & TSI_DATA_TSICNT_MASK);
+}
+
+/*!
+* @brief Sets the TSI wake-up channel low threshold.
+*
+* @param    base           TSI peripheral base address.
+* @param    low_threshold  Low counter threshold.
+* @return   none.
+*/
+static inline void TSI_SetLowThreshold(TSI_Type *base, uint16_t low_threshold)
+{
+    assert(low_threshold < 0xFFFFU);
+
+    base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESL_MASK) | (TSI_TSHD_THRESL(low_threshold));
+}
+
+/*!
+* @brief Sets the TSI wake-up channel high threshold.
+*
+* @param    base            TSI peripheral base address.
+* @param    high_threshold  High counter threshold.
+* @return   none.
+*/
+static inline void TSI_SetHighThreshold(TSI_Type *base, uint16_t high_threshold)
+{
+    assert(high_threshold < 0xFFFFU);
+
+    base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESH_MASK) | (TSI_TSHD_THRESH(high_threshold));
+}
+
+/*!
+* @brief Sets the analog mode of the TSI module.
+*
+* @param    base   TSI peripheral base address.
+* @param    mode   Mode value.
+* @return   none.
+*/
+static inline void TSI_SetAnalogMode(TSI_Type *base, tsi_analog_mode_t mode)
+{
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_MODE_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_MODE(mode));
+}
+
+/*!
+* @brief Gets the noise mode result of the TSI module.
+*
+* @param   base  TSI peripheral base address.
+* @return        Value of the GENCS[MODE] bit-fields.
+*/
+static inline uint8_t TSI_GetNoiseModeResult(TSI_Type *base)
+{
+    return (base->GENCS & TSI_GENCS_MODE_MASK) >> TSI_GENCS_MODE_SHIFT;
+}
+
+/*!
+* @brief Sets the reference oscillator charge current.
+*
+* @param   base    TSI peripheral base address.
+* @param   current The reference oscillator charge current.
+* @return  none.
+*/
+static inline void TSI_SetReferenceChargeCurrent(TSI_Type *base, tsi_reference_osc_charge_current_t current)
+{
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_REFCHRG_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_REFCHRG(current));
+}
+
+/*!
+* @brief Sets the external electrode charge current.
+*
+* @param    base    TSI peripheral base address.
+* @param    current External electrode charge current.
+* @return   none.
+*/
+static inline void TSI_SetElectrodeChargeCurrent(TSI_Type *base, tsi_external_osc_charge_current_t current)
+{
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_EXTCHRG_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_EXTCHRG(current));
+}
+
+/*!
+* @brief Sets the oscillator's voltage rails.
+*
+* @param    base    TSI peripheral base address.
+* @param    dvolt   The voltage rails.
+* @return   none.
+*/
+static inline void TSI_SetOscVoltageRails(TSI_Type *base, tsi_osc_voltage_rails_t dvolt)
+{
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_DVOLT_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_DVOLT(dvolt));
+}
+
+/*!
+* @brief Sets the electrode series resistance value in EXTCHRG[0] bit.
+*
+* @param    base     TSI peripheral base address.
+* @param    resistor Series resistance.
+* @return   none.
+*/
+static inline void TSI_SetElectrodeSeriesResistor(TSI_Type *base, tsi_series_resistor_t resistor)
+{
+    base->GENCS = (base->GENCS & TSI_V4_EXTCHRG_RESISTOR_BIT_CLEAR) | TSI_GENCS_EXTCHRG(resistor);
+}
+
+/*!
+* @brief Sets the electrode filter bits value in EXTCHRG[2:1] bits.
+*
+* @param    base    TSI peripheral base address.
+* @param    filter  Series resistance.
+* @return   none.
+*/
+static inline void TSI_SetFilterBits(TSI_Type *base, tsi_filter_bits_t filter)
+{
+    base->GENCS = (base->GENCS & TSI_V4_EXTCHRG_FILTER_BITS_CLEAR) | (filter << TSI_V4_EXTCHRG_FILTER_BITS_SHIFT);
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_TSI_V4_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_vref.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_vref.c
new file mode 100644
index 00000000000..248132c6179
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_vref.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_vref.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base VREF peripheral base address
+ *
+ * @return The VREF instance
+ */
+static uint32_t VREF_GetInstance(VREF_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to VREF bases for each instance. */
+static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS;
+
+/*! @brief Pointers to VREF clocks for each instance. */
+static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t VREF_GetInstance(VREF_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_VREF_COUNT; instance++)
+    {
+        if (s_vrefBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_VREF_COUNT);
+
+    return instance;
+}
+
+void VREF_Init(VREF_Type *base, const vref_config_t *config)
+{
+    assert(config != NULL);
+
+    uint8_t reg = 0U;
+
+    /* Ungate clock for VREF */
+    CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]);
+
+/* Configure VREF to a known state */
+#if defined(FSL_FEATURE_VREF_HAS_CHOP_OSC) && FSL_FEATURE_VREF_HAS_CHOP_OSC
+    /* Set chop oscillator bit */
+    base->TRM |= VREF_TRM_CHOPEN_MASK;
+#endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */
+    /* Get current SC register */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    reg = base->VREFH_SC;
+#else
+    reg = base->SC;
+#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+    /* Clear old buffer mode selection bits */
+    reg &= ~VREF_SC_MODE_LV_MASK;
+    /* Set buffer Mode selection and Regulator enable bit */
+    reg |= VREF_SC_MODE_LV(config->bufferMode) | VREF_SC_REGEN(1U);
+#if defined(FSL_FEATURE_VREF_HAS_COMPENSATION) && FSL_FEATURE_VREF_HAS_COMPENSATION
+    /* Set second order curvature compensation enable bit */
+    reg |= VREF_SC_ICOMPEN(1U);
+#endif /* FSL_FEATURE_VREF_HAS_COMPENSATION */
+    /* Enable VREF module */
+    reg |= VREF_SC_VREFEN(1U);
+    /* Update bit-field from value to Status and Control register */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    base->VREFH_SC = reg;
+#else
+    base->SC = reg;
+#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    reg = base->VREFL_TRM;
+    /* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits */
+    reg &= ~(VREF_VREFL_TRM_VREFL_EN_MASK | VREF_VREFL_TRM_VREFL_SEL_MASK);
+    /* Select external voltage reference and set VREFL (0.4 V) reference buffer enable */
+    reg |= VREF_VREFL_TRM_VREFL_SEL(config->enableExternalVoltRef) | VREF_VREFL_TRM_VREFL_EN(config->enableLowRef);
+    base->VREFL_TRM = reg;
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+    reg = base->TRM4;
+    /* Clear old select internal voltage reference bit (2.1V) */
+    reg &= ~VREF_TRM4_VREF2V1_EN_MASK;
+    /* Select internal voltage reference (2.1V) */
+    reg |= VREF_TRM4_VREF2V1_EN(config->enable2V1VoltRef);
+    base->TRM4 = reg;
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
+
+    /* Wait until internal voltage stable */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+     while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0)
+#else
+    while ((base->SC & VREF_SC_VREFST_MASK) == 0)
+#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+    {
+    }
+}
+
+void VREF_Deinit(VREF_Type *base)
+{
+    /* Gate clock for VREF */
+    CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]);
+}
+
+void VREF_GetDefaultConfig(vref_config_t *config)
+{
+    assert(config);
+
+/* Set High power buffer mode in */
+#if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE
+    config->bufferMode = kVREF_ModeHighPowerBuffer;
+#else
+    config->bufferMode = kVREF_ModeTightRegulationBuffer;
+#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */
+
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    /* Select internal voltage reference */
+    config->enableExternalVoltRef = false;
+    /* Set VREFL (0.4 V) reference buffer disable */
+    config->enableLowRef = false;
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+    /* Disable internal voltage reference (2.1V) */
+    config->enable2V1VoltRef = false;
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
+}
+
+void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue)
+{
+    uint8_t reg = 0U;
+
+    /* Set TRIM bits value in voltage reference */
+    reg = base->TRM;
+    reg = ((reg & ~VREF_TRM_TRIM_MASK) | VREF_TRM_TRIM(trimValue));
+    base->TRM = reg;
+    /* Wait until internal voltage stable */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+     while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0)
+#else
+    while ((base->SC & VREF_SC_VREFST_MASK) == 0)
+#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+    {
+    }
+}
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue)
+{
+    uint8_t reg = 0U;
+
+    /* Set TRIM bits value in voltage reference (2V1) */
+    reg = base->TRM4;
+    reg = ((reg & ~VREF_TRM4_TRIM2V1_MASK) | VREF_TRM4_TRIM2V1(trimValue));
+    base->TRM4 = reg;
+    /* Wait until internal voltage stable */
+    while ((base->SC & VREF_SC_VREFST_MASK) == 0)
+    {
+    }
+}
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
+
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue)
+{
+    /* The values 111b and 110b are NOT valid/allowed */
+    assert((trimValue != 0x7U) && (trimValue != 0x6U));
+
+    uint8_t reg = 0U;
+
+    /* Set TRIM bits value in low voltage reference */
+    reg = base->VREFL_TRM;
+    reg = ((reg & ~VREF_VREFL_TRM_VREFL_TRIM_MASK) | VREF_VREFL_TRM_VREFL_TRIM(trimValue));
+    base->VREFL_TRM = reg;
+    /* Wait until internal voltage stable */
+
+     while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0)
+    {
+    }
+}
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_vref.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_vref.h
new file mode 100644
index 00000000000..349c124dc35
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_vref.h
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_VREF_H_
+#define _FSL_VREF_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup vref
+ * @{
+ */
+
+
+/******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
+/*@}*/
+
+/* Those macros below defined to support SoC family which have VREFL (0.4V) reference */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+#define VREF_SC_MODE_LV VREF_VREFH_SC_MODE_LV
+#define VREF_SC_REGEN VREF_VREFH_SC_REGEN
+#define VREF_SC_VREFEN VREF_VREFH_SC_VREFEN
+#define VREF_SC_ICOMPEN VREF_VREFH_SC_ICOMPEN
+#define VREF_SC_REGEN_MASK VREF_VREFH_SC_REGEN_MASK
+#define VREF_SC_VREFST_MASK VREF_VREFH_SC_VREFST_MASK
+#define VREF_SC_VREFEN_MASK VREF_VREFH_SC_VREFEN_MASK
+#define VREF_SC_MODE_LV_MASK VREF_VREFH_SC_MODE_LV_MASK
+#define VREF_SC_ICOMPEN_MASK VREF_VREFH_SC_ICOMPEN_MASK
+#define TRM VREFH_TRM
+#define VREF_TRM_TRIM VREF_VREFH_TRM_TRIM
+#define VREF_TRM_CHOPEN_MASK VREF_VREFH_TRM_CHOPEN_MASK
+#define VREF_TRM_TRIM_MASK VREF_VREFH_TRM_TRIM_MASK
+#define VREF_TRM_CHOPEN_SHIFT VREF_VREFH_TRM_CHOPEN_SHIFT
+#define VREF_TRM_TRIM_SHIFT VREF_VREFH_TRM_TRIM_SHIFT
+#define VREF_SC_MODE_LV_SHIFT VREF_VREFH_SC_MODE_LV_SHIFT
+#define VREF_SC_REGEN_SHIFT VREF_VREFH_SC_REGEN_SHIFT
+#define VREF_SC_VREFST_SHIFT VREF_VREFH_SC_VREFST_SHIFT
+#define VREF_SC_ICOMPEN_SHIFT VREF_VREFH_SC_ICOMPEN_SHIFT
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+
+/*!
+ * @brief VREF modes.
+ */
+typedef enum _vref_buffer_mode
+{
+    kVREF_ModeBandgapOnly = 0U, /*!< Bandgap on only, for stabilization and startup */
+#if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE
+    kVREF_ModeHighPowerBuffer = 1U, /*!< High power buffer mode enabled */
+    kVREF_ModeLowPowerBuffer = 2U   /*!< Low power buffer mode enabled */
+#else
+    kVREF_ModeTightRegulationBuffer = 2U /*!< Tight regulation buffer enabled */
+#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */
+} vref_buffer_mode_t;
+
+/*!
+ * @brief The description structure for the VREF module.
+ */
+typedef struct _vref_config
+{
+    vref_buffer_mode_t bufferMode; /*!< Buffer mode selection */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    bool enableLowRef;          /*!< Set VREFL (0.4 V) reference buffer enable or disable */
+    bool enableExternalVoltRef; /*!< Select external voltage reference or not (internal) */
+#endif                          /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+    bool enable2V1VoltRef; /*!< Enable Internal Voltage Reference (2.1V) */
+#endif                     /* FSL_FEATURE_VREF_HAS_TRM4 */
+} vref_config_t;
+
+/******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name VREF functional operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the clock gate and configures the VREF module according to the configuration structure.
+ *
+ * This function must be called before calling all the other VREF driver functions,
+ * read/write registers, and configurations with user-defined settings.
+ * The example below shows how to set up  vref_config_t parameters and
+ * how to call the VREF_Init function by passing in these parameters:
+ * Example:
+ * @code
+ *   vref_config_t vrefConfig;
+ *   vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer;
+ *   vrefConfig.enableExternalVoltRef = false;
+ *   vrefConfig.enableLowRef = false;
+ *   VREF_Init(VREF, &vrefConfig);
+ * @endcode
+ *
+ * @param base VREF peripheral address.
+ * @param config Pointer to the configuration structure.
+ */
+void VREF_Init(VREF_Type *base, const vref_config_t *config);
+
+/*!
+ * @brief Stops and disables the clock for the VREF module.
+ *
+ * This function should be called to shut down the module.
+ * Example:
+ * @code
+ *   vref_config_t vrefUserConfig;
+ *   VREF_Init(VREF);
+ *   VREF_GetDefaultConfig(&vrefUserConfig);
+ *   ...
+ *   VREF_Deinit(VREF);
+ * @endcode
+ *
+ * @param base VREF peripheral address.
+ */
+void VREF_Deinit(VREF_Type *base);
+
+/*!
+ * @brief Initializes the VREF configuration structure.
+ *
+ * This function initializes the VREF configuration structure to a default value.
+ * Example:
+ * @code
+ *   vrefConfig->bufferMode = kVREF_ModeHighPowerBuffer;
+ *   vrefConfig->enableExternalVoltRef = false;
+ *   vrefConfig->enableLowRef = false;
+ * @endcode
+ *
+ * @param config Pointer to the initialization structure.
+ */
+void VREF_GetDefaultConfig(vref_config_t *config);
+
+/*!
+ * @brief Sets a TRIM value for reference voltage.
+ *
+ * This function sets a TRIM value for reference voltage.
+ * Note that the TRIM value maximum is 0x3F.
+ *
+ * @param base VREF peripheral address.
+ * @param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)).
+ */
+void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue);
+
+/*!
+ * @brief Reads the value of the TRIM meaning output voltage.
+ *
+ * This function gets the TRIM value from the TRM register.
+ *
+ * @param base VREF peripheral address.
+ * @return Six-bit value of trim setting.
+ */
+static inline uint8_t VREF_GetTrimVal(VREF_Type *base)
+{
+    return (base->TRM & VREF_TRM_TRIM_MASK);
+}
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+/*!
+ * @brief Sets a TRIM value for reference voltage (2V1).
+ *
+ * This function sets a TRIM value for reference voltage (2V1).
+ * Note that the TRIM value maximum is 0x3F.
+ *
+ * @param base VREF peripheral address.
+ * @param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)).
+ */
+void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue);
+
+/*!
+ * @brief Reads the value of the TRIM meaning output voltage (2V1).
+ *
+ * This function gets the TRIM value from the VREF_TRM4 register.
+ *
+ * @param base VREF peripheral address.
+ * @return Six-bit value of trim setting.
+ */
+static inline uint8_t VREF_GetTrim2V1Val(VREF_Type *base)
+{
+    return (base->TRM4 & VREF_TRM4_TRIM2V1_MASK);
+}
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
+
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+
+/*!
+ * @brief Sets the TRIM value for low voltage reference.
+ *
+ * This function sets the TRIM value for low reference voltage.
+ * NOTE:
+ *      - The TRIM value maximum is 0x05U
+ *      - The values 111b and 110b are not valid/allowed.
+ *
+ * @param base VREF peripheral address.
+ * @param trimValue Value of the trim register to set output low reference voltage (maximum 0x05U (3-bit)).
+ */
+void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue);
+
+/*!
+ * @brief Reads the value of the TRIM meaning output voltage.
+ *
+ * This function gets the TRIM value from the VREFL_TRM register.
+ *
+ * @param base VREF peripheral address.
+ * @return Three-bit value of the trim setting.
+ */
+static inline uint8_t VREF_GetLowReferenceTrimVal(VREF_Type *base)
+{
+    return (base->VREFL_TRM & VREF_VREFL_TRM_VREFL_TRIM_MASK);
+}
+#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_VREF_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_wdog.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_wdog.c
new file mode 100644
index 00000000000..489798ca889
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_wdog.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_wdog.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void WDOG_GetDefaultConfig(wdog_config_t *config)
+{
+    assert(config);
+
+    config->enableWdog = true;
+    config->clockSource = kWDOG_LpoClockSource;
+    config->prescaler = kWDOG_ClockPrescalerDivide1;
+#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN
+    config->workMode.enableWait = true;
+#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */
+    config->workMode.enableStop = false;
+    config->workMode.enableDebug = false;
+    config->enableUpdate = true;
+    config->enableInterrupt = false;
+    config->enableWindowMode = false;
+    config->windowValue = 0U;
+    config->timeoutValue = 0xFFFFU;
+}
+
+void WDOG_Init(WDOG_Type *base, const wdog_config_t *config)
+{
+    assert(config);
+
+    uint32_t value = 0U;
+    uint32_t primaskValue = 0U;
+
+    value = WDOG_STCTRLH_WDOGEN(config->enableWdog) | WDOG_STCTRLH_CLKSRC(config->clockSource) |
+            WDOG_STCTRLH_IRQRSTEN(config->enableInterrupt) | WDOG_STCTRLH_WINEN(config->enableWindowMode) |
+            WDOG_STCTRLH_ALLOWUPDATE(config->enableUpdate) | WDOG_STCTRLH_DBGEN(config->workMode.enableDebug) |
+            WDOG_STCTRLH_STOPEN(config->workMode.enableStop) |
+#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN
+            WDOG_STCTRLH_WAITEN(config->workMode.enableWait) |
+#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */
+            WDOG_STCTRLH_DISTESTWDOG(1U);
+
+    /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence
+     * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */
+    primaskValue = DisableGlobalIRQ();
+    WDOG_Unlock(base);
+    /* Wait one bus clock cycle */
+    base->RSTCNT = 0U;
+    /* Set configruation */
+    base->PRESC = WDOG_PRESC_PRESCVAL(config->prescaler);
+    base->WINH = (uint16_t)((config->windowValue >> 16U) & 0xFFFFU);
+    base->WINL = (uint16_t)((config->windowValue) & 0xFFFFU);
+    base->TOVALH = (uint16_t)((config->timeoutValue >> 16U) & 0xFFFFU);
+    base->TOVALL = (uint16_t)((config->timeoutValue) & 0xFFFFU);
+    base->STCTRLH = value;
+    EnableGlobalIRQ(primaskValue);
+}
+
+void WDOG_Deinit(WDOG_Type *base)
+{
+    uint32_t primaskValue = 0U;
+
+    /* Disable the global interrupts */
+    primaskValue = DisableGlobalIRQ();
+    WDOG_Unlock(base);
+    /* Wait one bus clock cycle */
+    base->RSTCNT = 0U;
+    WDOG_Disable(base);
+    EnableGlobalIRQ(primaskValue);
+    WDOG_ClearResetCount(base);
+}
+
+void WDOG_SetTestModeConfig(WDOG_Type *base, wdog_test_config_t *config)
+{
+    assert(config);
+
+    uint32_t value = 0U;
+    uint32_t primaskValue = 0U;
+
+    value = WDOG_STCTRLH_DISTESTWDOG(0U) | WDOG_STCTRLH_TESTWDOG(1U) | WDOG_STCTRLH_TESTSEL(config->testMode) |
+            WDOG_STCTRLH_BYTESEL(config->testedByte) | WDOG_STCTRLH_IRQRSTEN(0U) | WDOG_STCTRLH_WDOGEN(1U) |
+            WDOG_STCTRLH_ALLOWUPDATE(1U);
+
+    /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence
+     * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */
+    primaskValue = DisableGlobalIRQ();
+    WDOG_Unlock(base);
+    /* Wait one bus clock cycle */
+    base->RSTCNT = 0U;
+    /* Set configruation */
+    base->TOVALH = (uint16_t)((config->timeoutValue >> 16U) & 0xFFFFU);
+    base->TOVALL = (uint16_t)((config->timeoutValue) & 0xFFFFU);
+    base->STCTRLH = value;
+    EnableGlobalIRQ(primaskValue);
+}
+
+uint32_t WDOG_GetStatusFlags(WDOG_Type *base)
+{
+    uint32_t status_flag = 0U;
+
+    status_flag |= (base->STCTRLH & WDOG_STCTRLH_WDOGEN_MASK);
+    status_flag |= (base->STCTRLL & WDOG_STCTRLL_INTFLG_MASK);
+
+    return status_flag;
+}
+
+void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask)
+{
+    if (mask & kWDOG_TimeoutFlag)
+    {
+        base->STCTRLL |= WDOG_STCTRLL_INTFLG_MASK;
+    }
+}
+
+void WDOG_Refresh(WDOG_Type *base)
+{
+    uint32_t primaskValue = 0U;
+
+    /* Disable the global interrupt to protect refresh sequence */
+    primaskValue = DisableGlobalIRQ();
+    base->REFRESH = WDOG_FIRST_WORD_OF_REFRESH;
+    base->REFRESH = WDOG_SECOND_WORD_OF_REFRESH;
+    EnableGlobalIRQ(primaskValue);
+}
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_wdog.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_wdog.h
new file mode 100644
index 00000000000..f49740667b9
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/drivers/fsl_wdog.h
@@ -0,0 +1,433 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_WDOG_H_
+#define _FSL_WDOG_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup wdog
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines WDOG driver version 2.0.0. */
+#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @name Unlock sequence */
+/*@{*/
+#define WDOG_FIRST_WORD_OF_UNLOCK (0xC520U)  /*!< First word of unlock sequence */
+#define WDOG_SECOND_WORD_OF_UNLOCK (0xD928U) /*!< Second word of unlock sequence */
+/*@}*/
+
+/*! @name Refresh sequence */
+/*@{*/
+#define WDOG_FIRST_WORD_OF_REFRESH (0xA602U)  /*!< First word of refresh sequence */
+#define WDOG_SECOND_WORD_OF_REFRESH (0xB480U) /*!< Second word of refresh sequence */
+/*@}*/
+
+/*! @brief Describes WDOG clock source. */
+typedef enum _wdog_clock_source
+{
+    kWDOG_LpoClockSource = 0U,       /*!< WDOG clock sourced from LPO*/
+    kWDOG_AlternateClockSource = 1U, /*!< WDOG clock sourced from alternate clock source*/
+} wdog_clock_source_t;
+
+/*! @brief Defines WDOG work mode. */
+typedef struct _wdog_work_mode
+{
+#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN
+    bool enableWait;  /*!< Enables or disables WDOG in wait mode  */
+#endif                /* FSL_FEATURE_WDOG_HAS_WAITEN */
+    bool enableStop;  /*!< Enables or disables WDOG in stop mode  */
+    bool enableDebug; /*!< Enables or disables WDOG in debug mode */
+} wdog_work_mode_t;
+
+/*! @brief Describes the selection of the clock prescaler. */
+typedef enum _wdog_clock_prescaler
+{
+    kWDOG_ClockPrescalerDivide1 = 0x0U, /*!< Divided by 1 */
+    kWDOG_ClockPrescalerDivide2 = 0x1U, /*!< Divided by 2 */
+    kWDOG_ClockPrescalerDivide3 = 0x2U, /*!< Divided by 3 */
+    kWDOG_ClockPrescalerDivide4 = 0x3U, /*!< Divided by 4 */
+    kWDOG_ClockPrescalerDivide5 = 0x4U, /*!< Divided by 5 */
+    kWDOG_ClockPrescalerDivide6 = 0x5U, /*!< Divided by 6 */
+    kWDOG_ClockPrescalerDivide7 = 0x6U, /*!< Divided by 7 */
+    kWDOG_ClockPrescalerDivide8 = 0x7U, /*!< Divided by 8 */
+} wdog_clock_prescaler_t;
+
+/*! @brief Describes WDOG configuration structure. */
+typedef struct _wdog_config
+{
+    bool enableWdog;                  /*!< Enables or disables WDOG */
+    wdog_clock_source_t clockSource;  /*!< Clock source select */
+    wdog_clock_prescaler_t prescaler; /*!< Clock prescaler value */
+    wdog_work_mode_t workMode;        /*!< Configures WDOG work mode in debug stop and wait mode */
+    bool enableUpdate;                /*!< Update write-once register enable */
+    bool enableInterrupt;             /*!< Enables or disables WDOG interrupt */
+    bool enableWindowMode;            /*!< Enables or disables WDOG window mode */
+    uint32_t windowValue;             /*!< Window value */
+    uint32_t timeoutValue;            /*!< Timeout value */
+} wdog_config_t;
+
+/*! @brief Describes WDOG test mode. */
+typedef enum _wdog_test_mode
+{
+    kWDOG_QuickTest = 0U, /*!< Selects quick test */
+    kWDOG_ByteTest = 1U,  /*!< Selects byte test */
+} wdog_test_mode_t;
+
+/*! @brief Describes WDOG tested byte selection in byte test mode. */
+typedef enum _wdog_tested_byte
+{
+    kWDOG_TestByte0 = 0U, /*!< Byte 0 selected in byte test mode */
+    kWDOG_TestByte1 = 1U, /*!< Byte 1 selected in byte test mode */
+    kWDOG_TestByte2 = 2U, /*!< Byte 2 selected in byte test mode */
+    kWDOG_TestByte3 = 3U, /*!< Byte 3 selected in byte test mode */
+} wdog_tested_byte_t;
+
+/*! @brief Describes WDOG test mode configuration structure. */
+typedef struct _wdog_test_config
+{
+    wdog_test_mode_t testMode;     /*!< Selects test mode */
+    wdog_tested_byte_t testedByte; /*!< Selects tested byte in byte test mode */
+    uint32_t timeoutValue;         /*!< Timeout value */
+} wdog_test_config_t;
+
+/*!
+ * @brief WDOG interrupt configuration structure, default settings all disabled.
+ *
+ * This structure contains the settings for all of the WDOG interrupt configurations.
+ */
+enum _wdog_interrupt_enable_t
+{
+    kWDOG_InterruptEnable = WDOG_STCTRLH_IRQRSTEN_MASK, /*!< WDOG timeout generates an interrupt before reset*/
+};
+
+/*!
+ * @brief WDOG status flags.
+ *
+ * This structure contains the WDOG status flags for use in the WDOG functions.
+ */
+enum _wdog_status_flags_t
+{
+    kWDOG_RunningFlag = WDOG_STCTRLH_WDOGEN_MASK, /*!< Running flag, set when WDOG is enabled*/
+    kWDOG_TimeoutFlag = WDOG_STCTRLL_INTFLG_MASK, /*!< Interrupt flag, set when an exception occurs*/
+};
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name WDOG Initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes WDOG configure sturcture.
+ *
+ * This function initializes the WDOG configuration structure to default value. The default
+ * values are:
+ * @code
+ *   wdogConfig->enableWdog = true;
+ *   wdogConfig->clockSource = kWDOG_LpoClockSource;
+ *   wdogConfig->prescaler = kWDOG_ClockPrescalerDivide1;
+ *   wdogConfig->workMode.enableWait = true;
+ *   wdogConfig->workMode.enableStop = false;
+ *   wdogConfig->workMode.enableDebug = false;
+ *   wdogConfig->enableUpdate = true;
+ *   wdogConfig->enableInterrupt = false;
+ *   wdogConfig->enableWindowMode = false;
+ *   wdogConfig->windowValue = 0;
+ *   wdogConfig->timeoutValue = 0xFFFFU;
+ * @endcode
+ *
+ * @param config Pointer to WDOG config structure.
+ * @see wdog_config_t
+ */
+void WDOG_GetDefaultConfig(wdog_config_t *config);
+
+/*!
+ * @brief Initializes the WDOG.
+ *
+ * This function initializes the WDOG. When called, the WDOG runs according to the configuration.
+ * If user wants to reconfigure WDOG without forcing a reset first, enableUpdate must be set to true
+ * in configuration.
+ *
+ * Example:
+ * @code
+ *   wdog_config_t config;
+ *   WDOG_GetDefaultConfig(&config);
+ *   config.timeoutValue = 0x7ffU;
+ *   config.enableUpdate = true;
+ *   WDOG_Init(wdog_base,&config);
+ * @endcode
+ *
+ * @param base   WDOG peripheral base address
+ * @param config The configuration of WDOG
+ */
+void WDOG_Init(WDOG_Type *base, const wdog_config_t *config);
+
+/*!
+ * @brief Shuts down the WDOG.
+ *
+ * This function shuts down the WDOG.
+ * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled.
+ */
+void WDOG_Deinit(WDOG_Type *base);
+
+/*!
+ * @brief Configures WDOG functional test.
+ *
+ * This function is used to configure the WDOG functional test. When called, the WDOG goes into test mode
+ * and runs according to the configuration.
+ * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled.
+ *
+ * Example:
+ * @code
+ *   wdog_test_config_t test_config;
+ *   test_config.testMode = kWDOG_QuickTest;
+ *   test_config.timeoutValue = 0xfffffu;
+ *   WDOG_SetTestModeConfig(wdog_base, &test_config);
+ * @endcode
+ * @param base   WDOG peripheral base address
+ * @param config The functional test configuration of WDOG
+ */
+void WDOG_SetTestModeConfig(WDOG_Type *base, wdog_test_config_t *config);
+
+/* @} */
+
+/*!
+ * @name WDOG Functional Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the WDOG module.
+ *
+ * This function write value into WDOG_STCTRLH register to enable the WDOG, it is a write-once register,
+ * make sure that the WCT window is still open and this register has not been written in this WCT
+ * while this function is called.
+ *
+ * @param base WDOG peripheral base address
+ */
+static inline void WDOG_Enable(WDOG_Type *base)
+{
+    base->STCTRLH |= WDOG_STCTRLH_WDOGEN_MASK;
+}
+
+/*!
+ * @brief Disables the WDOG module.
+ *
+ * This function write value into WDOG_STCTRLH register to disable the WDOG, it is a write-once register,
+ * make sure that the WCT window is still open and this register has not been written in this WCT
+ * while this function is called.
+ *
+ * @param base WDOG peripheral base address
+ */
+static inline void WDOG_Disable(WDOG_Type *base)
+{
+    base->STCTRLH &= ~WDOG_STCTRLH_WDOGEN_MASK;
+}
+
+/*!
+ * @brief Enable WDOG interrupt.
+ *
+ * This function write value into WDOG_STCTRLH register to enable WDOG interrupt, it is a write-once register,
+ * make sure that the WCT window is still open and this register has not been written in this WCT
+ * while this function is called.
+ *
+ * @param base WDOG peripheral base address
+ * @param mask The interrupts to enable
+ *        The parameter can be combination of the following source if defined:
+ *        @arg kWDOG_InterruptEnable
+ */
+static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint32_t mask)
+{
+    base->STCTRLH |= mask;
+}
+
+/*!
+ * @brief Disable WDOG interrupt.
+ *
+ * This function write value into WDOG_STCTRLH register to disable WDOG interrupt, it is a write-once register,
+ * make sure that the WCT window is still open and this register has not been written in this WCT
+ * while this function is called.
+ *
+ * @param base WDOG peripheral base address
+ * @param mask The interrupts to disable
+ *        The parameter can be combination of the following source if defined:
+ *        @arg kWDOG_InterruptEnable
+ */
+static inline void WDOG_DisableInterrupts(WDOG_Type *base, uint32_t mask)
+{
+    base->STCTRLH &= ~mask;
+}
+
+/*!
+ * @brief Gets WDOG all status flags.
+ *
+ * This function gets all status flags.
+ *
+ * Example for getting Running Flag:
+ * @code
+ *   uint32_t status;
+ *   status = WDOG_GetStatusFlags(wdog_base) & kWDOG_RunningFlag;
+ * @endcode
+ * @param base        WDOG peripheral base address
+ * @return            State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags_t
+ *                    - true: a related status flag has been set.
+ *                    - false: a related status flag is not set.
+ */
+uint32_t WDOG_GetStatusFlags(WDOG_Type *base);
+
+/*!
+ * @brief Clear WDOG flag.
+ *
+ * This function clears WDOG status flag.
+ *
+ * Example for clearing timeout(interrupt) flag:
+ * @code
+ *   WDOG_ClearStatusFlags(wdog_base,kWDOG_TimeoutFlag);
+ * @endcode
+ * @param base        WDOG peripheral base address
+ * @param mask        The status flags to clear.
+ *                    The parameter could be any combination of the following values:
+ *                    kWDOG_TimeoutFlag
+ */
+void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask);
+
+/*!
+ * @brief Set the WDOG timeout value.
+ *
+ * This function sets the timeout value.
+ * It should be ensured that the time-out value for the WDOG is always greater than
+ * 2xWCT time + 20 bus clock cycles.
+ * This function write value into WDOG_TOVALH and WDOG_TOVALL registers which are wirte-once.
+ * Make sure the WCT window is still open and these two registers have not been written in this WCT
+ * while this function is called.
+ *
+ * @param base WDOG peripheral base address
+ * @param timeoutCount WDOG timeout value, count of WDOG clock tick.
+ */
+static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint32_t timeoutCount)
+{
+    base->TOVALH = (uint16_t)((timeoutCount >> 16U) & 0xFFFFU);
+    base->TOVALL = (uint16_t)((timeoutCount)&0xFFFFU);
+}
+
+/*!
+ * @brief Sets the WDOG window value.
+ *
+ * This function sets the WDOG window value.
+ * This function write value into WDOG_WINH and WDOG_WINL registers which are wirte-once.
+ * Make sure the WCT window is still open and these two registers have not been written in this WCT
+ * while this function is called.
+ *
+ * @param base WDOG peripheral base address
+ * @param windowValue WDOG window value.
+ */
+static inline void WDOG_SetWindowValue(WDOG_Type *base, uint32_t windowValue)
+{
+    base->WINH = (uint16_t)((windowValue >> 16U) & 0xFFFFU);
+    base->WINL = (uint16_t)((windowValue)&0xFFFFU);
+}
+
+/*!
+ * @brief Unlocks the WDOG register written.
+ *
+ * This function unlocks the WDOG register written.
+ * Before starting the unlock sequence and following congfiguration, disable the global interrupts.
+ * Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire,
+ * After the configuration finishes, re-enable the global interrupts.
+ *
+ * @param base WDOG peripheral base address
+ */
+static inline void WDOG_Unlock(WDOG_Type *base)
+{
+    base->UNLOCK = WDOG_FIRST_WORD_OF_UNLOCK;
+    base->UNLOCK = WDOG_SECOND_WORD_OF_UNLOCK;
+}
+
+/*!
+ * @brief Refreshes the WDOG timer.
+ *
+ * This function feeds the WDOG.
+ * This function should be called before WDOG timer is in timeout. Otherwise, a reset is asserted.
+ *
+ * @param base WDOG peripheral base address
+ */
+void WDOG_Refresh(WDOG_Type *base);
+
+/*!
+ * @brief Gets the WDOG reset count.
+ *
+ * This function gets the WDOG reset count value.
+ *
+ * @param base WDOG peripheral base address
+ * @return     WDOG reset count value
+ */
+static inline uint16_t WDOG_GetResetCount(WDOG_Type *base)
+{
+    return base->RSTCNT;
+}
+/*!
+ * @brief Clears the WDOG reset count.
+ *
+ * This function clears the WDOG reset count value.
+ *
+ * @param base WDOG peripheral base address
+ */
+static inline void WDOG_ClearResetCount(WDOG_Type *base)
+{
+    base->RSTCNT |= UINT16_MAX;
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_WDOG_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/peripheral_clock_defines.h b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/peripheral_clock_defines.h
new file mode 100644
index 00000000000..0f2d38d8adb
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/peripheral_clock_defines.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_PERIPHERAL_CLOCK_H_
+#define _FSL_PERIPHERAL_CLOCK_H_
+
+#include "fsl_clock.h"
+
+/* Array for LPUART module clocks */
+#define LPUART_CLOCK_FREQS                         \
+    {                                              \
+        kCLOCK_Osc0ErClk, kCLOCK_Osc0ErClk, kCLOCK_Osc0ErClk   \
+    }
+
+/* Array for I2C module clocks */
+#define I2C_CLOCK_FREQS               \
+    {                                 \
+        I2C0_CLK_SRC, I2C1_CLK_SRC    \
+    }
+
+/* Array for DSPI module clocks */
+#define SPI_CLOCK_FREQS              \
+    {                                \
+        DSPI0_CLK_SRC, DSPI1_CLK_SRC   \
+    }
+
+#endif /* _FSL_PERIPHERAL_CLOCK_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/pwmout_api.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/pwmout_api.c
new file mode 100644
index 00000000000..a2a90e8b8b2
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/pwmout_api.c
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pwmout_api.h"
+
+#if DEVICE_PWMOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "fsl_tpm.h"
+#include "PeripheralPins.h"
+
+static float pwm_clock_mhz;
+/* Array of TPM peripheral base address. */
+static TPM_Type *const tpm_addrs[] = TPM_BASE_PTRS;
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+    MBED_ASSERT(pwm != (PWMName)NC);
+
+    obj->pwm_name = pwm;
+
+    uint32_t pwm_base_clock;
+
+    /* Set the TPM clock source to be IRC 48M */
+    CLOCK_SetTpmClock(1U);
+    pwm_base_clock = CLOCK_GetFreq(kCLOCK_McgIrc48MClk);
+    float clkval = (float)pwm_base_clock / 1000000.0f;
+    uint32_t clkdiv = 0;
+    while (clkval > 1) {
+        clkdiv++;
+        clkval /= 2.0f;
+        if (clkdiv == 7) {
+            break;
+        }
+    }
+
+    pwm_clock_mhz = clkval;
+    uint32_t channel = pwm & 0xF;
+    uint32_t instance = pwm >> TPM_SHIFT;
+    tpm_config_t tpmInfo;
+
+    TPM_GetDefaultConfig(&tpmInfo);
+    tpmInfo.prescale = (tpm_clock_prescale_t)clkdiv;
+    /* Initialize TPM module */
+    TPM_Init(tpm_addrs[instance], &tpmInfo);
+
+    tpm_chnl_pwm_signal_param_t config = {
+        .chnlNumber = (tpm_chnl_t)channel,
+        .level = kTPM_HighTrue,
+        .dutyCyclePercent = 0,
+    };
+    // default to 20ms: standard for servos, and fine for e.g. brightness control
+    TPM_SetupPwm(tpm_addrs[instance], &config, 1, kTPM_EdgeAlignedPwm, 50, pwm_base_clock);
+
+    TPM_StartTimer(tpm_addrs[instance], kTPM_SystemClock);
+
+    // Wire pinout
+    pinmap_pinout(pin, PinMap_PWM);
+}
+
+void pwmout_free(pwmout_t* obj) {
+    TPM_Deinit(tpm_addrs[obj->pwm_name >> TPM_SHIFT]);
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+    if (value < 0.0f) {
+        value = 0.0f;
+    } else if (value > 1.0f) {
+        value = 1.0f;
+    }
+
+    TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT];
+    uint16_t mod = base->MOD & TPM_MOD_MOD_MASK;
+    uint32_t new_count = (uint32_t)((float)(mod) * value);
+    // Update of CnV register
+    base->CONTROLS[obj->pwm_name & 0xF].CnV = new_count;
+    base->CNT = 0;
+}
+
+float pwmout_read(pwmout_t* obj) {
+    TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT];
+    uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & TPM_CnV_VAL_MASK;
+    uint16_t mod = base->MOD & TPM_MOD_MOD_MASK;
+
+    if (mod == 0)
+        return 0.0;
+    float v = (float)(count) / (float)(mod);
+    return (v > 1.0f) ? (1.0f) : (v);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+    pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+    pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+    TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT];
+    float dc = pwmout_read(obj);
+
+    // Stop TPM clock to ensure instant update of MOD register
+    base->MOD = TPM_MOD_MOD((pwm_clock_mhz * (float)us) - 1);
+    pwmout_write(obj, dc);
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+    TPM_Type *base = tpm_addrs[obj->pwm_name >> TPM_SHIFT];
+    uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us);
+
+    // Update of CnV register
+    base->CONTROLS[obj->pwm_name & 0xF].CnV = value;
+}
+
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/serial_api.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/serial_api.c
new file mode 100644
index 00000000000..bea40787f12
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/serial_api.c
@@ -0,0 +1,262 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include "mbed_assert.h"
+
+#include <string.h>
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "fsl_lpuart.h"
+#include "peripheral_clock_defines.h"
+#include "PeripheralPins.h"
+#include "fsl_clock_config.h"
+
+static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT] = {0};
+static uart_irq_handler irq_handler;
+/* Array of UART peripheral base address. */
+static LPUART_Type *const uart_addrs[] = LPUART_BASE_PTRS;
+/* Array of LPUART bus clock frequencies */
+static clock_name_t const uart_clocks[] = LPUART_CLOCK_FREQS;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+    uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
+    uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
+    obj->index = pinmap_merge(uart_tx, uart_rx);
+    MBED_ASSERT((int)obj->index != NC);
+
+    // Need to initialize the clocks here as ticker init gets called before mbed_sdk_init
+    if (SystemCoreClock == DEFAULT_SYSTEM_CLOCK)
+        BOARD_BootClockRUN();
+
+    /* Set the LPUART clock source */
+    CLOCK_SetLpuartClock(2U);
+
+    lpuart_config_t config;
+    LPUART_GetDefaultConfig(&config);
+    config.baudRate_Bps = 9600;
+    config.enableTx = false;
+    config.enableRx = false;
+
+    LPUART_Init(uart_addrs[obj->index], &config, CLOCK_GetFreq(uart_clocks[obj->index]));
+
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+
+    if (tx != NC) {
+        LPUART_EnableTx(uart_addrs[obj->index], true);
+        pin_mode(tx, PullUp);
+    }
+    if (rx != NC) {
+        LPUART_EnableRx(uart_addrs[obj->index], true);
+        pin_mode(rx, PullUp);
+    }
+
+    if (obj->index == STDIO_UART) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj) {
+    LPUART_Deinit(uart_addrs[obj->index]);
+    serial_irq_ids[obj->index] = 0;
+}
+
+void serial_baud(serial_t *obj, int baudrate) {
+    LPUART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index]));
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+    LPUART_Type *base = uart_addrs[obj->index];
+    uint8_t temp;
+    /* Set bit count and parity mode. */
+    temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK);
+    if (parity != ParityNone)
+    {
+        /* Enable Parity */
+        temp |= (LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK);
+        if (parity == ParityOdd) {
+            temp |= LPUART_CTRL_PT_MASK;
+        } else if (parity == ParityEven) {
+            // PT=0 so nothing more to do
+        } else {
+            // Hardware does not support forced parity
+            MBED_ASSERT(0);
+        }
+    }
+    base->CTRL = temp;
+
+#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
+    /* set stop bit per char */
+    temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK;
+    base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)--stop_bits);
+#endif
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) {
+    LPUART_Type *base = uart_addrs[index];
+
+    /* If RX overrun. */
+    if (LPUART_STAT_OR_MASK & base->STAT)
+    {
+        /* Read base->D, otherwise the RX does not work. */
+        (void)base->DATA;
+        LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag);
+    }
+
+    if (serial_irq_ids[index] != 0) {
+        if (transmit_empty)
+            irq_handler(serial_irq_ids[index], TxIrq);
+
+        if (receive_full)
+            irq_handler(serial_irq_ids[index], RxIrq);
+    }
+}
+
+void uart0_irq() {
+    uint32_t status_flags = LPUART0->STAT;
+    uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 0);
+}
+
+void uart1_irq() {
+    uint32_t status_flags = LPUART1->STAT;
+    uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 1);
+}
+
+void uart2_irq() {
+    uint32_t status_flags = LPUART2->STAT;
+    uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 2);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    IRQn_Type uart_irqs[] = LPUART_RX_TX_IRQS;
+    uint32_t vector = 0;
+
+    switch (obj->index) {
+        case 0:
+            vector = (uint32_t)&uart0_irq;
+            break;
+        case 1:
+            vector = (uint32_t)&uart1_irq;
+            break;
+        case 2:
+            vector = (uint32_t)&uart2_irq;
+            break;
+        default:
+            break;
+    }
+
+    if (enable) {
+        switch (irq) {
+            case RxIrq:
+                LPUART_EnableInterrupts(uart_addrs[obj->index], kLPUART_RxDataRegFullInterruptEnable);
+                break;
+            case TxIrq:
+                LPUART_EnableInterrupts(uart_addrs[obj->index], kLPUART_TxDataRegEmptyInterruptEnable);
+                break;
+            default:
+                break;
+        }
+        NVIC_SetVector(uart_irqs[obj->index], vector);
+        NVIC_EnableIRQ(uart_irqs[obj->index]);
+
+    } else { // disable
+        int all_disabled = 0;
+        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+        switch (irq) {
+            case RxIrq:
+                LPUART_DisableInterrupts(uart_addrs[obj->index], kLPUART_RxDataRegFullInterruptEnable);
+                break;
+            case TxIrq:
+                LPUART_DisableInterrupts(uart_addrs[obj->index], kLPUART_TxDataRegEmptyInterruptEnable);
+                break;
+            default:
+                break;
+        }
+        switch (other_irq) {
+            case RxIrq:
+                all_disabled = ((LPUART_GetEnabledInterrupts(uart_addrs[obj->index]) & kLPUART_RxDataRegFullInterruptEnable) == 0);
+                break;
+            case TxIrq:
+                all_disabled = ((LPUART_GetEnabledInterrupts(uart_addrs[obj->index]) & kLPUART_TxDataRegEmptyInterruptEnable) == 0);
+                break;
+            default:
+                break;
+        }
+        if (all_disabled)
+            NVIC_DisableIRQ(uart_irqs[obj->index]);
+    }
+}
+
+int serial_getc(serial_t *obj) {
+    uint8_t data;
+
+    LPUART_ReadBlocking(uart_addrs[obj->index], &data, 1);
+    return data;
+}
+
+void serial_putc(serial_t *obj, int c) {
+    while (!serial_writable(obj));
+    LPUART_WriteByte(uart_addrs[obj->index], (uint8_t)c);
+}
+
+int serial_readable(serial_t *obj) {
+    uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]);
+    if (status_flags & kLPUART_RxOverrunFlag)
+        LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag);
+    return (status_flags & kLPUART_RxDataRegFullFlag);
+}
+
+int serial_writable(serial_t *obj) {
+    uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]);
+    if (status_flags & kLPUART_RxOverrunFlag)
+        LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag);
+    return (status_flags & kLPUART_TxDataRegEmptyFlag);
+}
+
+void serial_clear(serial_t *obj) {
+}
+
+void serial_pinout_tx(PinName tx) {
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+    uart_addrs[obj->index]->CTRL |= LPUART_CTRL_SBK_MASK;
+}
+
+void serial_break_clear(serial_t *obj) {
+    uart_addrs[obj->index]->CTRL &= ~LPUART_CTRL_SBK_MASK;
+}
+
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/spi_api.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/spi_api.c
new file mode 100644
index 00000000000..54b4d177615
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/spi_api.c
@@ -0,0 +1,132 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+#include "mbed_assert.h"
+
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "fsl_dspi.h"
+#include "peripheral_clock_defines.h"
+#include "PeripheralPins.h"
+
+/* Array of SPI peripheral base address. */
+static SPI_Type *const spi_address[] = SPI_BASE_PTRS;
+/* Array of SPI bus clock frequencies */
+static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    // determine the SPI to use
+    uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
+    uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
+    uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
+
+    obj->instance = pinmap_merge(spi_data, spi_cntl);
+    MBED_ASSERT((int)obj->instance != NC);
+
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+}
+
+void spi_free(spi_t *obj) {
+    DSPI_Deinit(spi_address[obj->instance]);
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+
+    dspi_master_config_t master_config;
+    dspi_slave_config_t slave_config;
+
+    if (slave) {
+        /* Slave config */
+        DSPI_SlaveGetDefaultConfig(&slave_config);
+        slave_config.whichCtar = kDSPI_Ctar0;
+        slave_config.ctarConfig.bitsPerFrame = (uint32_t)bits;;
+        slave_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
+        slave_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
+
+        DSPI_SlaveInit(spi_address[obj->instance], &slave_config);
+    } else {
+        /* Master config */
+        DSPI_MasterGetDefaultConfig(&master_config);
+        master_config.ctarConfig.bitsPerFrame = (uint32_t)bits;;
+        master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
+        master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
+        master_config.ctarConfig.direction = kDSPI_MsbFirst;
+        master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
+
+        DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
+    }
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+    uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]);
+    DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock);
+    //Half clock period delay after SPI transfer
+    DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
+}
+
+static inline int spi_readable(spi_t * obj) {
+    return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
+}
+
+int spi_master_write(spi_t *obj, int value) {
+    dspi_command_data_config_t command;
+    uint32_t rx_data;
+    DSPI_GetDefaultDataCommandConfig(&command);
+    command.isEndOfQueue = true;
+
+    DSPI_MasterWriteDataBlocking(spi_address[obj->instance], &command, (uint16_t)value);
+
+    DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_TxFifoFillRequestFlag);
+
+    // wait rx buffer full
+    while (!spi_readable(obj));
+    rx_data = DSPI_ReadData(spi_address[obj->instance]);
+    DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag);
+    return rx_data & 0xffff;
+}
+
+int spi_slave_receive(spi_t *obj) {
+    return spi_readable(obj);
+}
+
+int spi_slave_read(spi_t *obj) {
+    uint32_t rx_data;
+
+    while (!spi_readable(obj));
+    rx_data = DSPI_ReadData(spi_address[obj->instance]);
+    DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag);
+    return rx_data & 0xffff;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+    DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value);
+}
+
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/us_ticker.c b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/us_ticker.c
new file mode 100644
index 00000000000..0603a867a20
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL82Z/us_ticker.c
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+#include "fsl_pit.h"
+#include "fsl_clock_config.h"
+
+static int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+    if (us_ticker_inited) {
+        return;
+    }
+    us_ticker_inited = 1;
+    // Need to initialize the clocks here as ticker init gets called before mbed_sdk_init
+    if (SystemCoreClock == DEFAULT_SYSTEM_CLOCK)
+        BOARD_BootClockRUN();
+    //Common for ticker/timer
+    uint32_t busClock;
+    // Structure to initialize PIT
+    pit_config_t pitConfig;
+
+    PIT_GetDefaultConfig(&pitConfig);
+    PIT_Init(PIT, &pitConfig);
+
+    busClock = CLOCK_GetFreq(kCLOCK_BusClk);
+
+    //Timer
+    PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, busClock / 1000000 - 1);
+    PIT_SetTimerPeriod(PIT, kPIT_Chnl_1, 0xFFFFFFFF);
+    PIT_SetTimerChainMode(PIT, kPIT_Chnl_1, true);
+    PIT_StartTimer(PIT, kPIT_Chnl_0);
+    PIT_StartTimer(PIT, kPIT_Chnl_1);
+
+    //Ticker
+    PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1);
+    PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true);
+    NVIC_SetVector(PIT0_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_EnableIRQ(PIT0_IRQn);
+}
+
+
+uint32_t us_ticker_read() {
+    if (!us_ticker_inited) {
+        us_ticker_init();
+    }
+
+    return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1));
+}
+
+void us_ticker_disable_interrupt(void) {
+    PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
+}
+
+void us_ticker_clear_interrupt(void) {
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp) {
+    int delta = (int)(timestamp - us_ticker_read());
+    if (delta <= 0) {
+        // This event was in the past.
+        // Set the interrupt as pending, but don't process it here.
+        // This prevents a recurive loop under heavy load
+        // which can lead to a stack overflow.
+        NVIC_SetPendingIRQ(PIT0_IRQn);
+        return;
+    }
+
+    PIT_StopTimer(PIT, kPIT_Chnl_3);
+    PIT_StopTimer(PIT, kPIT_Chnl_2);
+    PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
+    PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
+    PIT_StartTimer(PIT, kPIT_Chnl_3);
+    PIT_StartTimer(PIT, kPIT_Chnl_2);
+}
diff --git a/targets/TARGET_Freescale/mbed_rtx.h b/targets/TARGET_Freescale/mbed_rtx.h
index c0943d5aa98..0d208973c4f 100644
--- a/targets/TARGET_Freescale/mbed_rtx.h
+++ b/targets/TARGET_Freescale/mbed_rtx.h
@@ -167,6 +167,21 @@
 #define OS_CLOCK                48000000
 #endif
 
+#elif defined(TARGET_KL82Z)
+
+#ifndef INITIAL_SP
+#define INITIAL_SP              (0x20012000UL)
+#endif
+#ifndef OS_TASKCNT
+#define OS_TASKCNT              14
+#endif
+#ifndef OS_MAINSTKSIZE
+#define OS_MAINSTKSIZE          256
+#endif
+#ifndef OS_CLOCK
+#define OS_CLOCK                72000000
+#endif
+
 #elif defined(TARGET_K64F)
 
 #ifndef INITIAL_SP
diff --git a/targets/targets.json b/targets/targets.json
index d4108cea399..4cf2d398999 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -523,6 +523,19 @@
         "release_versions": ["2", "5"],
         "device_name": "MKL43Z256xxx4"
     },
+    "KL82Z": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M0+",
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "extra_labels": ["Freescale", "KSDK2_MCUS", "FRDM"],
+        "macros": ["CPU_MKL82Z128VLK7", "FSL_RTOS_MBED"],
+        "is_disk_virtual": true,
+        "inherits": ["Target"],
+        "progen": {"target": "frdm-kl82z"},
+        "detect_code": ["0218"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"]
+    },
     "K64F": {
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M4F",

From 504b2ac6b6377b2302a757ac38fa7d3eb509c504 Mon Sep 17 00:00:00 2001
From: Mahadevan Mahesh <Mahesh.Mahadevan@nxp.com>
Date: Mon, 19 Sep 2016 09:43:43 -0500
Subject: [PATCH 68/89] Update tests to add support for FRDM KL43Z and FRDM
 KL82Z

Signed-off-by: Mahadevan Mahesh <Mahesh.Mahadevan@nxp.com>
---
 features/unsupported/tests/mbed/analog/main.cpp          | 6 +++++-
 features/unsupported/tests/mbed/i2c_eeprom/main.cpp      | 6 ++++++
 features/unsupported/tests/mbed/i2c_eeprom_line/main.cpp | 6 ++++++
 features/unsupported/tests/rtos/mbed/file/main.cpp       | 2 +-
 4 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/features/unsupported/tests/mbed/analog/main.cpp b/features/unsupported/tests/mbed/analog/main.cpp
index d23121c65ff..31bc2d54d3d 100644
--- a/features/unsupported/tests/mbed/analog/main.cpp
+++ b/features/unsupported/tests/mbed/analog/main.cpp
@@ -20,10 +20,14 @@ AnalogOut out(PTE30);
 AnalogIn in(PTB11);  // D9
 AnalogOut out(PTB1); // D1
 
-#elif defined(TARGET_KL46Z)
+#elif defined(TARGET_KL46Z) || defined(TARGET_KL43Z)
 AnalogIn in(PTB0);
 AnalogOut out(PTE30);
 
+#elif defined(TARGET_KL82Z)
+AnalogIn in(A2);
+AnalogOut out(DAC0_OUT);
+
 #elif defined(TARGET_LPC1549)
 AnalogIn in(A0);
 AnalogOut out(D12); //D12 is P0_12, the DAC output pin
diff --git a/features/unsupported/tests/mbed/i2c_eeprom/main.cpp b/features/unsupported/tests/mbed/i2c_eeprom/main.cpp
index 62dfc98714f..47294dee051 100644
--- a/features/unsupported/tests/mbed/i2c_eeprom/main.cpp
+++ b/features/unsupported/tests/mbed/i2c_eeprom/main.cpp
@@ -30,6 +30,12 @@ I2C i2c(PTD6, PTD7);
 #elif defined(TARGET_KL46Z)
 I2C i2c(PTC9, PTC8);
 
+#elif defined(TARGET_KL43Z)
+I2C i2c(PTE0, PTE1);
+
+#elif defined(TARGET_KL82Z)
+I2C i2c(PTC11, PTC10);
+
 #elif defined(TARGET_K64F)
 I2C i2c(PTE25, PTE24);
 
diff --git a/features/unsupported/tests/mbed/i2c_eeprom_line/main.cpp b/features/unsupported/tests/mbed/i2c_eeprom_line/main.cpp
index 34a718b2975..28214efcfd5 100644
--- a/features/unsupported/tests/mbed/i2c_eeprom_line/main.cpp
+++ b/features/unsupported/tests/mbed/i2c_eeprom_line/main.cpp
@@ -40,6 +40,12 @@ I2C i2c(PTD6, PTD7);
 #elif defined(TARGET_KL46Z)
 I2C i2c(PTC9, PTC8);
 
+#elif defined(TARGET_KL43Z)
+I2C i2c(PTE0, PTE1);
+
+#elif defined(TARGET_KL82Z)
+I2C i2c(PTC11, PTC10);
+
 #elif defined(TARGET_K64F)
 I2C i2c(PTE25, PTE24);
 
diff --git a/features/unsupported/tests/rtos/mbed/file/main.cpp b/features/unsupported/tests/rtos/mbed/file/main.cpp
index c542ae821ec..738be7cb7a8 100644
--- a/features/unsupported/tests/rtos/mbed/file/main.cpp
+++ b/features/unsupported/tests/rtos/mbed/file/main.cpp
@@ -24,7 +24,7 @@ void sd_thread(void const *argument)
 #if defined(TARGET_KL25Z)
     SDFileSystem sd(PTD2, PTD3, PTD1, PTD0, "sd");
 
-#elif defined(TARGET_KL46Z)
+#elif defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_KL82Z)
     SDFileSystem sd(PTD6, PTD7, PTD5, PTD4, "sd");
 
 #elif defined(TARGET_K64F) || defined(TARGET_K66F)

From 0e5d0bda91bee986c52c45b6aa418002a6002a64 Mon Sep 17 00:00:00 2001
From: Laurent MEUNIER <laurent.meuniert.com>
Date: Tue, 30 Aug 2016 15:27:24 +0200
Subject: [PATCH 69/89] Deploy SPI_ASYNCH to all family

the SPI_ASYNCH feature has been already activated for STM32F4.
This patchset makes it supported on all STM32 families by:
- moving spi_s structure at family level instead of board level
- using the F4 spi_api.c reference implementation and making it a common
stm_spi_api.c file which makes maintenance a lot easier.
- the only part that needs to be implemented for each family is the computation
of the clock frequency input to the spi peripheral which is not the same
accross families. So this is what remains in the spi_api.c of each family.

Because of the introduction of the common file, all the above modifications
needs to be done at once.
---
 .../TARGET_DISCO_F051R8/objects.h             |  14 -
 .../TARGET_NUCLEO_F030R8/objects.h            |  14 -
 .../TARGET_NUCLEO_F031K6/objects.h            |  14 -
 .../TARGET_NUCLEO_F042K6/objects.h            |  14 -
 .../TARGET_NUCLEO_F070RB/objects.h            |  14 -
 .../TARGET_NUCLEO_F072RB/objects.h            |  14 -
 .../TARGET_NUCLEO_F091RC/objects.h            |  14 -
 .../TARGET_STM32F0/common_objects.h           |  15 +
 targets/TARGET_STM/TARGET_STM32F0/spi_api.c   | 257 +-------
 .../TARGET_BLUEPILL_F103C8/objects.h          |  14 -
 .../TARGET_DISCO_F100RB/objects.h             |  14 -
 .../TARGET_NUCLEO_F103RB/objects.h            |  14 -
 .../TARGET_STM32F1/common_objects.h           |  15 +
 targets/TARGET_STM/TARGET_STM32F1/spi_api.c   | 275 +-------
 targets/TARGET_STM/TARGET_STM32F2/objects.h   |  13 +-
 targets/TARGET_STM/TARGET_STM32F2/spi_api.c   | 298 +--------
 .../TARGET_DISCO_F303VC/objects.h             |  14 -
 .../TARGET_DISCO_F334C8/objects.h             |  14 -
 .../TARGET_NUCLEO_F302R8/objects.h            |  14 -
 .../TARGET_NUCLEO_F303K8/objects.h            |  14 -
 .../TARGET_NUCLEO_F303RE/objects.h            |  14 -
 .../TARGET_NUCLEO_F303ZE/objects.h            |  14 -
 .../TARGET_NUCLEO_F334R8/objects.h            |  14 -
 .../TARGET_STM32F3/common_objects.h           |  15 +
 targets/TARGET_STM/TARGET_STM32F3/spi_api.c   | 308 +--------
 targets/TARGET_STM/TARGET_STM32F4/spi_api.c   | 517 +--------------
 .../TARGET_DISCO_F746NG/objects.h             |  14 -
 .../TARGET_DISCO_F769NI/objects.h             |  14 -
 .../TARGET_NUCLEO_F746ZG/objects.h            |  14 -
 .../TARGET_NUCLEO_F767ZI/objects.h            |  14 -
 .../TARGET_STM32F7/common_objects.h           |  15 +
 targets/TARGET_STM/TARGET_STM32F7/spi_api.c   | 317 +--------
 .../TARGET_DISCO_L053C8/objects.h             |  14 -
 .../TARGET_NUCLEO_L011K4/objects.h            |  14 -
 .../TARGET_NUCLEO_L031K6/objects.h            |  14 -
 .../TARGET_NUCLEO_L053R8/objects.h            |  14 -
 .../TARGET_NUCLEO_L073RZ/objects.h            |  14 -
 .../TARGET_STM32L0/common_objects.h           |  15 +
 targets/TARGET_STM/TARGET_STM32L0/spi_api.c   | 248 +------
 .../TARGET_MOTE_L152RC/objects.h              |  14 -
 .../TARGET_NUCLEO_L152RE/objects.h            |  14 -
 .../TARGET_NZ32_SC151/objects.h               |  14 -
 .../TARGET_STM32L1/common_objects.h           |  15 +
 targets/TARGET_STM/TARGET_STM32L1/spi_api.c   | 252 +------
 .../TARGET_DISCO_L476VG/objects.h             |  14 -
 .../TARGET_NUCLEO_L432KC/objects.h            |  14 -
 .../TARGET_NUCLEO_L476RG/objects.h            |  14 -
 .../TARGET_STM32L4/common_objects.h           |  15 +
 targets/TARGET_STM/TARGET_STM32L4/spi_api.c   | 314 +--------
 targets/TARGET_STM/stm_spi_api.c              | 613 ++++++++++++++++++
 50 files changed, 852 insertions(+), 3113 deletions(-)
 create mode 100644 targets/TARGET_STM/stm_spi_api.c

diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h
index 4a19b70bd67..70b7bcf2a43 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/objects.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/objects.h
index 16c179a610f..f006abac8a9 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/objects.h
@@ -60,20 +60,6 @@ struct analogin_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/objects.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/objects.h
index 16c179a610f..f006abac8a9 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/objects.h
@@ -60,20 +60,6 @@ struct analogin_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h
index 10cf3d139bd..6a4a844c468 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h
@@ -60,20 +60,6 @@ struct analogin_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/objects.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/objects.h
index 16c179a610f..f006abac8a9 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/objects.h
@@ -60,20 +60,6 @@ struct analogin_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h
index 8f908717dc5..11c94c05072 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h
index 8f908717dc5..11c94c05072 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h
index 41fa23726fe..3bbfc82717d 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h
@@ -49,6 +49,21 @@ struct pwmout_s {
     uint8_t inverted;
 };
 
+struct spi_s {
+    SPI_HandleTypeDef handle;
+    IRQn_Type spiIRQ;
+    SPIName spi;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+#ifdef DEVICE_SPI_ASYNCH
+    uint32_t event;
+    uint8_t module;
+    uint8_t transfer_type;
+#endif
+};
+
 struct serial_s {
     UARTName uart;
     int index; // Used by irq
diff --git a/targets/TARGET_STM/TARGET_STM32F0/spi_api.c b/targets/TARGET_STM/TARGET_STM32F0/spi_api.c
index 117a441ded0..d7dc4c10dd1 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/spi_api.c
+++ b/targets/TARGET_STM/TARGET_STM32F0/spi_api.c
@@ -32,260 +32,23 @@
 #include "spi_api.h"
 
 #if DEVICE_SPI
-
-#include <math.h>
 #include "cmsis.h"
 #include "pinmap.h"
 #include "PeripheralPins.h"
 
-static SPI_HandleTypeDef SpiHandle;
-
-static void init_spi(spi_t *obj) {
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-
-    __HAL_SPI_DISABLE(&SpiHandle);
-
-    SpiHandle.Init.Mode              = obj->mode;
-    SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
-    SpiHandle.Init.Direction         = SPI_DIRECTION_2LINES;
-    SpiHandle.Init.CLKPhase          = obj->cpha;
-    SpiHandle.Init.CLKPolarity       = obj->cpol;
-    SpiHandle.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLED;
-    SpiHandle.Init.CRCPolynomial     = 7;
-    SpiHandle.Init.DataSize          = obj->bits;
-    SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
-    SpiHandle.Init.NSS               = obj->nss;
-    SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLED;
-
-    HAL_SPI_Init(&SpiHandle);
-
-    __HAL_SPI_ENABLE(&SpiHandle);
-}
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
-    // Determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
-    obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
-    MBED_ASSERT(obj->spi != (SPIName)NC);
-
-    // Enable SPI clock
-    if (obj->spi == SPI_1) {
-        __SPI1_CLK_ENABLE();
-    }
-#if defined(SPI2_BASE)
-    if (obj->spi == SPI_2) {
-        __SPI2_CLK_ENABLE();
-    }
+#if DEVICE_SPI_ASYNCH
+    #define SPI_S(obj)    (( struct spi_s *)(&(obj->spi)))
+#else
+    #define SPI_S(obj)    (( struct spi_s *)(obj))
 #endif
 
-    // Configure the SPI pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-
-    // Save new values
-    obj->bits = SPI_DATASIZE_8BIT;
-    obj->cpol = SPI_POLARITY_LOW;
-    obj->cpha = SPI_PHASE_1EDGE;
-    obj->br_presc = SPI_BAUDRATEPRESCALER_256;
-
-    obj->pin_miso = miso;
-    obj->pin_mosi = mosi;
-    obj->pin_sclk = sclk;
-    obj->pin_ssel = ssel;
-
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    } else {
-        obj->nss = SPI_NSS_SOFT;
-    }
-
-    init_spi(obj);
-}
-
-void spi_free(spi_t *obj) {
-    // Reset SPI and disable clock
-    if (obj->spi == SPI_1) {
-        __SPI1_FORCE_RESET();
-        __SPI1_RELEASE_RESET();
-        __SPI1_CLK_DISABLE();
-    }
-
-#if defined(SPI2_BASE)
-    if (obj->spi == SPI_2) {
-        __SPI2_FORCE_RESET();
-        __SPI2_RELEASE_RESET();
-        __SPI2_CLK_DISABLE();
-    }
-#endif
-
-    // Configure GPIOs
-    pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
-    // Save new values
-    if (bits == 16) {
-        obj->bits = SPI_DATASIZE_16BIT;
-    } else {
-        obj->bits = SPI_DATASIZE_8BIT;
-    }
-
-    switch (mode) {
-        case 0:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        case 1:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-        case 2:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        default:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-    }
-
-    if (obj->nss != SPI_NSS_SOFT) {
-        obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
-    }
-
-    obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
-
-    init_spi(obj);
-}
-
-static const uint16_t baudrate_prescaler_table[] =	{SPI_BAUDRATEPRESCALER_2,
-                                                    SPI_BAUDRATEPRESCALER_4,
-                                                    SPI_BAUDRATEPRESCALER_8,
-                                                    SPI_BAUDRATEPRESCALER_16,
-                                                    SPI_BAUDRATEPRESCALER_32,
-                                                    SPI_BAUDRATEPRESCALER_64,
-                                                    SPI_BAUDRATEPRESCALER_128,
-                                                    SPI_BAUDRATEPRESCALER_256};
-
-void spi_frequency(spi_t *obj, int hz) {
-	int spi_hz = 0;
-	uint8_t prescaler_rank = 0;
-
+/*
+ * Only the frequency is managed in the family specific part
+ * the rest of SPI management is common to all STM32 families
+ */
+int spi_get_clock_freq(spi_t *obj) {
 	/* SPI_1, SPI_2. Source CLK is PCKL1 */
-	spi_hz = HAL_RCC_GetPCLK1Freq();
-
-	/* Define pre-scaler in order to get highest available frequency below requested frequency */
-	while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
-		spi_hz = spi_hz / 2;
-		prescaler_rank++;
-	}
-
-	if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
-		obj->br_presc = baudrate_prescaler_table[prescaler_rank-1];
-	} else {
-		error("Couldn't setup requested SPI frequency");
-	}
-
-    init_spi(obj);
-}
-
-static inline int ssp_readable(spi_t *obj) {
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is received
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline int ssp_writeable(spi_t *obj) {
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is transmitted
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline void ssp_write(spi_t *obj, int value) {
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        *p_spi_dr = (uint8_t)value;
-    } else { // SPI_DATASIZE_16BIT
-        spi->DR = (uint16_t)value;
-    }
-}
-
-static inline int ssp_read(spi_t *obj) {
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        return (int)(*p_spi_dr);
-    } else {
-        return (int)spi->DR;
-    }
-}
-
-static inline int ssp_busy(spi_t *obj) {
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
-    return status;
-}
-
-int spi_master_write(spi_t *obj, int value) {
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj) {
-    return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
-};
-
-int spi_slave_read(spi_t *obj) {
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        return (int)(*p_spi_dr);
-    } else {
-        return (int)spi->DR;
-    }
-}
-
-void spi_slave_write(spi_t *obj, int value) {
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        *p_spi_dr = (uint8_t)value;
-    } else { // SPI_DATASIZE_16BIT
-        spi->DR = (uint16_t)value;
-    }
-}
-
-int spi_busy(spi_t *obj) {
-    return ssp_busy(obj);
+    return HAL_RCC_GetPCLK1Freq();
 }
 
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h
index 3fc3ed5c335..708f2f5f7cb 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h
@@ -60,20 +60,6 @@ struct analogin_s {
     uint8_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h
index fa4a7243520..da4126e6ce5 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h
@@ -60,20 +60,6 @@ struct analogin_s {
     uint8_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h
index e16970c065b..b0b234ba744 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h
@@ -60,20 +60,6 @@ struct analogin_s {
     uint8_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h
index 585d323084c..e39a16c0198 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h
@@ -68,6 +68,21 @@ struct serial_s {
 #endif
 };
 
+struct spi_s {
+    SPI_HandleTypeDef handle;
+    IRQn_Type spiIRQ;
+    SPIName spi;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+#ifdef DEVICE_SPI_ASYNCH
+    uint32_t event;
+    uint8_t module;
+    uint8_t transfer_type;
+#endif
+};
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F1/spi_api.c b/targets/TARGET_STM/TARGET_STM32F1/spi_api.c
index 198c29acb83..6cd4d8af9da 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/spi_api.c
+++ b/targets/TARGET_STM/TARGET_STM32F1/spi_api.c
@@ -32,159 +32,26 @@
 #include "spi_api.h"
 
 #if DEVICE_SPI
-
-#include <math.h>
 #include "cmsis.h"
 #include "pinmap.h"
 #include "PeripheralPins.h"
 
-static SPI_HandleTypeDef SpiHandle;
-
-static void init_spi(spi_t *obj)
-{
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-
-    __HAL_SPI_DISABLE(&SpiHandle);
-
-    SpiHandle.Init.Mode              = obj->mode;
-    SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
-    SpiHandle.Init.Direction         = SPI_DIRECTION_2LINES;
-    SpiHandle.Init.CLKPhase          = obj->cpha;
-    SpiHandle.Init.CLKPolarity       = obj->cpol;
-    SpiHandle.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLED;
-    SpiHandle.Init.CRCPolynomial     = 7;
-    SpiHandle.Init.DataSize          = obj->bits;
-    SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
-    SpiHandle.Init.NSS               = obj->nss;
-    SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLED;
-
-    HAL_SPI_Init(&SpiHandle);
-
-    __HAL_SPI_ENABLE(&SpiHandle);
-}
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
-{
-    // Determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
-    obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
-    MBED_ASSERT(obj->spi != (SPIName)NC);
-
-    // Enable SPI clock
-    if (obj->spi == SPI_1) {
-        __SPI1_CLK_ENABLE();
-    }
-    if (obj->spi == SPI_2) {
-        __SPI2_CLK_ENABLE();
-    }
-
-    // Configure the SPI pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-
-    // Save new values
-    obj->bits = SPI_DATASIZE_8BIT;
-    obj->cpol = SPI_POLARITY_LOW;
-    obj->cpha = SPI_PHASE_1EDGE;
-    obj->br_presc = SPI_BAUDRATEPRESCALER_256;
-
-    obj->pin_miso = miso;
-    obj->pin_mosi = mosi;
-    obj->pin_sclk = sclk;
-    obj->pin_ssel = ssel;
-
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    } else {
-        obj->nss = SPI_NSS_SOFT;
-    }
-
-    init_spi(obj);
-}
-
-void spi_free(spi_t *obj)
-{
-    // Reset SPI and disable clock
-    if (obj->spi == SPI_1) {
-        __SPI1_FORCE_RESET();
-        __SPI1_RELEASE_RESET();
-        __SPI1_CLK_DISABLE();
-    }
-
-    if (obj->spi == SPI_2) {
-        __SPI2_FORCE_RESET();
-        __SPI2_RELEASE_RESET();
-        __SPI2_CLK_DISABLE();
-    }
-
-    // Configure GPIOs
-    pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave)
-{
-    // Save new values
-    if (bits == 16) {
-        obj->bits = SPI_DATASIZE_16BIT;
-    } else {
-        obj->bits = SPI_DATASIZE_8BIT;
-    }
-
-    switch (mode) {
-        case 0:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        case 1:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-        case 2:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        default:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-    }
-
-    if (obj->nss != SPI_NSS_SOFT) {
-        obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
-    }
-
-    obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
-
-    init_spi(obj);
-}
-
-static const uint16_t baudrate_prescaler_table[] =	{SPI_BAUDRATEPRESCALER_2,
-                                                    SPI_BAUDRATEPRESCALER_4,
-                                                    SPI_BAUDRATEPRESCALER_8,
-                                                    SPI_BAUDRATEPRESCALER_16,
-                                                    SPI_BAUDRATEPRESCALER_32,
-                                                    SPI_BAUDRATEPRESCALER_64,
-                                                    SPI_BAUDRATEPRESCALER_128,
-                                                    SPI_BAUDRATEPRESCALER_256};
+#if DEVICE_SPI_ASYNCH
+    #define SPI_S(obj)    (( struct spi_s *)(&(obj->spi)))
+#else
+    #define SPI_S(obj)    (( struct spi_s *)(obj))
+#endif
 
-void spi_frequency(spi_t *obj, int hz)
-{
-    int spi_hz = 0;
-	uint8_t prescaler_rank = 0;
+/*
+ * Only the frequency is managed in the family specific part
+ * the rest of SPI management is common to all STM32 families
+ */
+int spi_get_clock_freq(spi_t *obj) {
+    struct spi_s *spiobj = SPI_S(obj);
+	int spi_hz = 0;
 
 	/* Get source clock depending on SPI instance */
-    switch ((int)obj->spi) {
+    switch ((int)spiobj->spi) {
         case SPI_1:
 			/* SPI_1. Source CLK is PCKL2 */
 			spi_hz = HAL_RCC_GetPCLK2Freq();
@@ -194,120 +61,10 @@ void spi_frequency(spi_t *obj, int hz)
 			spi_hz = HAL_RCC_GetPCLK1Freq();
 			break;
 		default:
-			error("SPI instance not set");
-    }
-
-	/* Define pre-scaler in order to get highest available frequency below requested frequency */
-	while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
-		spi_hz = spi_hz / 2;
-		prescaler_rank++;
-	}
-
-	if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
-		obj->br_presc = baudrate_prescaler_table[prescaler_rank-1];
-	} else {
-		error("Couldn't setup requested SPI frequency");
-	}
-
-    init_spi(obj);
-}
-
-static inline int ssp_readable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is received
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline int ssp_writeable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is transmitted
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline void ssp_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        *p_spi_dr = (uint8_t)value;
-    } else { // SPI_DATASIZE_16BIT
-        spi->DR = (uint16_t)value;
-    }
-}
-
-static inline int ssp_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        return (int)(*p_spi_dr);
-    } else {
-        return (int)spi->DR;
-    }
-}
-
-static inline int ssp_busy(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
-    return status;
-}
-
-int spi_master_write(spi_t *obj, int value)
-{
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj)
-{
-    return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
-};
-
-int spi_slave_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        return (int)(*p_spi_dr);
-    } else {
-        return (int)spi->DR;
-    }
-}
-
-void spi_slave_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        *p_spi_dr = (uint8_t)value;
-    } else { // SPI_DATASIZE_16BIT
-        spi->DR = (uint16_t)value;
+			error("CLK: SPI instance not set");
+            break;
     }
-}
-
-int spi_busy(spi_t *obj)
-{
-    return ssp_busy(obj);
+    return spi_hz;
 }
 
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32F2/objects.h b/targets/TARGET_STM/TARGET_STM32F2/objects.h
index a2cf58dc60f..5834dcd655a 100644
--- a/targets/TARGET_STM/TARGET_STM32F2/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F2/objects.h
@@ -85,17 +85,18 @@ struct serial_s {
 };
 
 struct spi_s {
+    SPI_HandleTypeDef handle;
+    IRQn_Type spiIRQ;
     SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
     PinName pin_miso;
     PinName pin_mosi;
     PinName pin_sclk;
     PinName pin_ssel;
+#ifdef DEVICE_SPI_ASYNCH
+    uint32_t event;
+    uint8_t module;
+    uint8_t transfer_type;
+#endif
 };
 
 struct i2c_s {
diff --git a/targets/TARGET_STM/TARGET_STM32F2/spi_api.c b/targets/TARGET_STM/TARGET_STM32F2/spi_api.c
index 095ed728acc..39ffb1d152e 100644
--- a/targets/TARGET_STM/TARGET_STM32F2/spi_api.c
+++ b/targets/TARGET_STM/TARGET_STM32F2/spi_api.c
@@ -33,217 +33,27 @@
 
 #if DEVICE_SPI
 
-#include <math.h>
 #include "cmsis.h"
 #include "pinmap.h"
 #include "PeripheralPins.h"
 #include "mbed_error.h"
 
-static SPI_HandleTypeDef SpiHandle;
-
-static void init_spi(spi_t *obj)
-{
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-
-    __HAL_SPI_DISABLE(&SpiHandle);
-
-    SpiHandle.Init.Mode              = obj->mode;
-    SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
-    SpiHandle.Init.Direction         = SPI_DIRECTION_2LINES;
-    SpiHandle.Init.CLKPhase          = obj->cpha;
-    SpiHandle.Init.CLKPolarity       = obj->cpol;
-    SpiHandle.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLED;
-    SpiHandle.Init.CRCPolynomial     = 7;
-    SpiHandle.Init.DataSize          = obj->bits;
-    SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
-    SpiHandle.Init.NSS               = obj->nss;
-    SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLED;
-
-    if (HAL_SPI_Init(&SpiHandle) != HAL_OK) {
-        error("Cannot initialize SPI");
-    }
-
-    __HAL_SPI_ENABLE(&SpiHandle);
-}
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
-{
-    // Determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
-    obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
-    MBED_ASSERT(obj->spi != (SPIName)NC);
-
-    // Enable SPI clock
-    if (obj->spi == SPI_1) {
-        __HAL_RCC_SPI1_CLK_ENABLE();
-    }
-
-    if (obj->spi == SPI_2) {
-        __HAL_RCC_SPI2_CLK_ENABLE();
-    }
-
-#if defined SPI3_BASE
-    if (obj->spi == SPI_3) {
-        __HAL_RCC_SPI3_CLK_ENABLE();
-    }
-#endif
-
-#if defined SPI4_BASE
-    if (obj->spi == SPI_4) {
-        __HAL_RCC_SPI4_CLK_ENABLE();
-    }
-#endif
-
-#if defined SPI5_BASE
-    if (obj->spi == SPI_5) {
-        __HAL_RCC_SPI5_CLK_ENABLE();
-    }
-#endif
-
-#if defined SPI6_BASE
-    if (obj->spi == SPI_6) {
-        __HAL_RCC_SPI6_CLK_ENABLE();
-    }
-#endif
-
-    // Configure the SPI pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-
-    // Save new values
-    obj->bits = SPI_DATASIZE_8BIT;
-    obj->cpol = SPI_POLARITY_LOW;
-    obj->cpha = SPI_PHASE_1EDGE;
-    obj->br_presc = SPI_BAUDRATEPRESCALER_256;
-
-    obj->pin_miso = miso;
-    obj->pin_mosi = mosi;
-    obj->pin_sclk = sclk;
-    obj->pin_ssel = ssel;
-
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    } else {
-        obj->nss = SPI_NSS_SOFT;
-    }
-
-    init_spi(obj);
-}
-
-void spi_free(spi_t *obj)
-{
-    // Reset SPI and disable clock
-    if (obj->spi == SPI_1) {
-        __HAL_RCC_SPI1_FORCE_RESET();
-        __HAL_RCC_SPI1_RELEASE_RESET();
-        __HAL_RCC_SPI1_CLK_DISABLE();
-    }
-
-    if (obj->spi == SPI_2) {
-        __HAL_RCC_SPI2_FORCE_RESET();
-        __HAL_RCC_SPI2_RELEASE_RESET();
-        __HAL_RCC_SPI2_CLK_DISABLE();
-    }
-#if defined SPI3_BASE
-    if (obj->spi == SPI_3) {
-        __HAL_RCC_SPI3_FORCE_RESET();
-        __HAL_RCC_SPI3_RELEASE_RESET();
-        __HAL_RCC_SPI3_CLK_DISABLE();
-    }
-#endif
-
-#if defined SPI4_BASE
-    if (obj->spi == SPI_4) {
-        __HAL_RCC_SPI4_FORCE_RESET();
-        __HAL_RCC_SPI4_RELEASE_RESET();
-        __HAL_RCC_SPI4_CLK_DISABLE();
-    }
-#endif
-
-#if defined SPI5_BASE
-    if (obj->spi == SPI_5) {
-        __HAL_RCC_SPI5_FORCE_RESET();
-        __HAL_RCC_SPI5_RELEASE_RESET();
-        __HAL_RCC_SPI5_CLK_DISABLE();
-    }
-#endif
-
-#if defined SPI6_BASE
-    if (obj->spi == SPI_6) {
-        __HAL_RCC_SPI6_FORCE_RESET();
-        __HAL_RCC_SPI6_RELEASE_RESET();
-        __HAL_RCC_SPI6_CLK_DISABLE();
-    }
+#if DEVICE_SPI_ASYNCH
+    #define SPI_S(obj)    (( struct spi_s *)(&(obj->spi)))
+#else
+    #define SPI_S(obj)    (( struct spi_s *)(obj))
 #endif
 
-    // Configure GPIOs
-    pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave)
-{
-    // Save new values
-    if (bits == 16) {
-        obj->bits = SPI_DATASIZE_16BIT;
-    } else {
-        obj->bits = SPI_DATASIZE_8BIT;
-    }
-
-    switch (mode) {
-        case 0:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        case 1:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-        case 2:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        default:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-    }
-
-    if (obj->nss != SPI_NSS_SOFT) {
-        obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
-    }
-
-    obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
-
-    init_spi(obj);
-}
-
-static const uint16_t baudrate_prescaler_table[] =	{SPI_BAUDRATEPRESCALER_2,
-                                                    SPI_BAUDRATEPRESCALER_4,
-                                                    SPI_BAUDRATEPRESCALER_8,
-                                                    SPI_BAUDRATEPRESCALER_16,
-                                                    SPI_BAUDRATEPRESCALER_32,
-                                                    SPI_BAUDRATEPRESCALER_64,
-                                                    SPI_BAUDRATEPRESCALER_128,
-                                                    SPI_BAUDRATEPRESCALER_256};
-
-void spi_frequency(spi_t *obj, int hz)
-{
+/*
+ * Only the frequency is managed in the family specific part
+ * the rest of SPI management is common to all STM32 families
+ */
+int spi_get_clock_freq(spi_t *obj) {
+    struct spi_s *spiobj = SPI_S(obj);
 	int spi_hz = 0;
-	uint8_t prescaler_rank = 0;
 
 	/* Get source clock depending on SPI instance */
-    switch ((int)obj->spi) {
+    switch ((int)spiobj->spi) {
         case SPI_1:
 #if defined SPI4_BASE
         case SPI_4:
@@ -266,91 +76,9 @@ void spi_frequency(spi_t *obj, int hz)
             break;
         default:
             error("SPI instance not set");
+            break;
     }
-
-	/* Define pre-scaler in order to get highest available frequency below requested frequency */
-	while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
-		spi_hz = spi_hz / 2;
-		prescaler_rank++;
-	}
-
-	if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
-		obj->br_presc = baudrate_prescaler_table[prescaler_rank-1];
-	} else {
-		error("Couldn't setup requested SPI frequency");
-	}
-
-    init_spi(obj);
-}
-
-static inline int ssp_readable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is received
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline int ssp_writeable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is transmitted
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline void ssp_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    spi->DR = (uint16_t)value;
-}
-
-static inline int ssp_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    return (int)spi->DR;
-}
-
-static inline int ssp_busy(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
-    return status;
-}
-
-int spi_master_write(spi_t *obj, int value)
-{
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj)
-{
-    return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
-};
-
-int spi_slave_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    return (int)spi->DR;
-}
-
-void spi_slave_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    spi->DR = (uint16_t)value;
-}
-
-int spi_busy(spi_t *obj)
-{
-    return ssp_busy(obj);
+    return spi_hz;
 }
 
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/objects.h
index e784a105d34..aeabfa3307a 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/objects.h
index e784a105d34..aeabfa3307a 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/objects.h
index 9650260ca46..61a56f7c047 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/objects.h
index 9650260ca46..61a56f7c047 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/objects.h
index 9650260ca46..61a56f7c047 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h
index 81ebc1d3710..f410f62461f 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h
@@ -77,20 +77,6 @@ struct serial_s {
     PinName pin_rx;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/objects.h
index 9650260ca46..61a56f7c047 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h
index 585d323084c..fd235f0781f 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h
@@ -49,6 +49,21 @@ struct pwmout_s {
     uint8_t inverted;
 };
 
+struct spi_s {
+    SPI_HandleTypeDef handle;
+    IRQn_Type spiIRQ;
+    SPIName spi;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+#ifdef DEVICE_SPI_ASYNCH
+    uint32_t event;
+    uint8_t module;
+    uint8_t transfer_type;
+#endif
+};
+
 struct serial_s {
     UARTName uart;
     int index; // Used by irq
diff --git a/targets/TARGET_STM/TARGET_STM32F3/spi_api.c b/targets/TARGET_STM/TARGET_STM32F3/spi_api.c
index 674b0936455..c7082808e6c 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/spi_api.c
+++ b/targets/TARGET_STM/TARGET_STM32F3/spi_api.c
@@ -33,199 +33,27 @@
 
 #if DEVICE_SPI
 
-#include <math.h>
 #include "cmsis.h"
 #include "pinmap.h"
 #include "PeripheralPins.h"
 
-static SPI_HandleTypeDef SpiHandle;
 
-static void init_spi(spi_t *obj)
-{
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-
-    __HAL_SPI_DISABLE(&SpiHandle);
-
-    SpiHandle.Init.Mode              = obj->mode;
-    SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
-    SpiHandle.Init.Direction         = SPI_DIRECTION_2LINES;
-    SpiHandle.Init.CLKPhase          = obj->cpha;
-    SpiHandle.Init.CLKPolarity       = obj->cpol;
-    SpiHandle.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLED;
-    SpiHandle.Init.CRCPolynomial     = 7;
-    SpiHandle.Init.DataSize          = obj->bits;
-    SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
-    SpiHandle.Init.NSS               = obj->nss;
-    SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLED;
-
-    HAL_SPI_Init(&SpiHandle);
-
-    __HAL_SPI_ENABLE(&SpiHandle);
-}
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
-{
-    // Determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
-    obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
-    MBED_ASSERT(obj->spi != (SPIName)NC);
-
-    // Enable SPI clock
-#if defined(SPI1_BASE)
-    if (obj->spi == SPI_1) {
-        __SPI1_CLK_ENABLE();
-    }
-#endif
-
-#if defined(SPI2_BASE)
-    if (obj->spi == SPI_2) {
-        __SPI2_CLK_ENABLE();
-    }
-#endif
-
-#if defined(SPI3_BASE)
-    if (obj->spi == SPI_3) {
-        __SPI3_CLK_ENABLE();
-    }
-#endif
-
-#if defined(SPI4_BASE)
-    if (obj->spi == SPI_3) {
-        __SPI4_CLK_ENABLE();
-    }
-#endif
-
-    // Configure the SPI pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-
-    // Save new values
-    obj->bits = SPI_DATASIZE_8BIT;
-    obj->cpol = SPI_POLARITY_LOW;
-    obj->cpha = SPI_PHASE_1EDGE;
-#if defined(TARGET_STM32F334C8)
-    obj->br_presc = SPI_BAUDRATEPRESCALER_256;
+#if DEVICE_SPI_ASYNCH
+    #define SPI_S(obj)    (( struct spi_s *)(&(obj->spi)))
 #else
-    obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1 MHz (HSI) or 1.13 MHz (HSE)
+    #define SPI_S(obj)    (( struct spi_s *)(obj))
 #endif
 
-    obj->pin_miso = miso;
-    obj->pin_mosi = mosi;
-    obj->pin_sclk = sclk;
-    obj->pin_ssel = ssel;
-
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    } else {
-        obj->nss = SPI_NSS_SOFT;
-    }
-
-    init_spi(obj);
-}
-
-void spi_free(spi_t *obj)
-{
-    // Reset SPI and disable clock
-#if defined(SPI1_BASE)
-    if (obj->spi == SPI_1) {
-        __SPI1_FORCE_RESET();
-        __SPI1_RELEASE_RESET();
-        __SPI1_CLK_DISABLE();
-    }
-#endif
-
-#if defined(SPI2_BASE)
-    if (obj->spi == SPI_2) {
-        __SPI2_FORCE_RESET();
-        __SPI2_RELEASE_RESET();
-        __SPI2_CLK_DISABLE();
-    }
-#endif
-
-#if defined(SPI3_BASE)
-    if (obj->spi == SPI_3) {
-        __SPI3_FORCE_RESET();
-        __SPI3_RELEASE_RESET();
-        __SPI3_CLK_DISABLE();
-    }
-#endif
-
-#if defined(SPI4_BASE)
-    if (obj->spi == SPI_4) {
-        __SPI4_FORCE_RESET();
-        __SPI4_RELEASE_RESET();
-        __SPI4_CLK_DISABLE();
-    }
-#endif
-
-    // Configure GPIOs
-    pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave)
-{
-    // Save new values
-    if (bits == 16) {
-        obj->bits = SPI_DATASIZE_16BIT;
-    } else {
-        obj->bits = SPI_DATASIZE_8BIT;
-    }
-
-    switch (mode) {
-        case 0:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        case 1:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-        case 2:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        default:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-    }
-
-    if (obj->nss != SPI_NSS_SOFT) {
-        obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
-    }
-
-    obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
-
-    init_spi(obj);
-}
-
-static const uint16_t baudrate_prescaler_table[] =	{SPI_BAUDRATEPRESCALER_2,
-                                                    SPI_BAUDRATEPRESCALER_4,
-                                                    SPI_BAUDRATEPRESCALER_8,
-                                                    SPI_BAUDRATEPRESCALER_16,
-                                                    SPI_BAUDRATEPRESCALER_32,
-                                                    SPI_BAUDRATEPRESCALER_64,
-                                                    SPI_BAUDRATEPRESCALER_128,
-                                                    SPI_BAUDRATEPRESCALER_256};
-
-void spi_frequency(spi_t *obj, int hz)
-{
+/*
+ * Only the frequency is managed in the family specific part
+ * the rest of SPI management is common to all STM32 families
+ */
+int spi_get_clock_freq(spi_t *obj) {
+    struct spi_s *spiobj = SPI_S(obj);
 	int spi_hz = 0;
-	uint8_t prescaler_rank = 0;
 
 	/* Get source clock depending on SPI instance */
-    switch ((int)obj->spi) {
+    switch ((int)spiobj->spi) {
 #if defined SPI1_BASE
 	case SPI_1:
 			/* SPI_1. Source CLK is PCKL2 */
@@ -245,120 +73,10 @@ void spi_frequency(spi_t *obj, int hz)
 			spi_hz = HAL_RCC_GetPCLK1Freq();
 			break;
 		default:
-			error("SPI instance not set");
-    }
-
-	/* Define pre-scaler in order to get highest available frequency below requested frequency */
-	while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
-		spi_hz = spi_hz / 2;
-		prescaler_rank++;
-	}
-
-	if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
-		obj->br_presc = baudrate_prescaler_table[prescaler_rank-1];
-	} else {
-		error("Couldn't setup requested SPI frequency");
-	}
-
-    init_spi(obj);
-}
-
-static inline int ssp_readable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is received
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline int ssp_writeable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is transmitted
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline void ssp_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        *p_spi_dr = (uint8_t)value;
-    } else { // SPI_DATASIZE_16BIT
-        spi->DR = (uint16_t)value;
-    }
-}
-
-static inline int ssp_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        return (int)(*p_spi_dr);
-    } else {
-        return (int)spi->DR;
-    }
-}
-
-static inline int ssp_busy(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
-    return status;
-}
-
-int spi_master_write(spi_t *obj, int value)
-{
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj)
-{
-    return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
-};
-
-int spi_slave_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        return (int)(*p_spi_dr);
-    } else {
-        return (int)spi->DR;
-    }
-}
-
-void spi_slave_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        *p_spi_dr = (uint8_t)value;
-    } else { // SPI_DATASIZE_16BIT
-        spi->DR = (uint16_t)value;
+			error("CLK: SPI instance not set");
+            break;
     }
-}
-
-int spi_busy(spi_t *obj)
-{
-    return ssp_busy(obj);
+    return spi_hz;
 }
 
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/spi_api.c b/targets/TARGET_STM/TARGET_STM32F4/spi_api.c
index aa1a8b7b4ec..af4414c1501 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/spi_api.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/spi_api.c
@@ -39,248 +39,19 @@
 #include "pinmap.h"
 #include "PeripheralPins.h"
 
-#if DEVICE_SPI_ASYNCH
-    #define SPI_INST(obj)    ((SPI_TypeDef *)(obj->spi.spi))
-#else
-    #define SPI_INST(obj)    ((SPI_TypeDef *)(obj->spi))
-#endif
-
 #if DEVICE_SPI_ASYNCH
     #define SPI_S(obj)    (( struct spi_s *)(&(obj->spi)))
 #else
     #define SPI_S(obj)    (( struct spi_s *)(obj))
 #endif
 
-#ifndef DEBUG_STDIO
-#   define DEBUG_STDIO 0
-#endif
-
-#if DEBUG_STDIO
-#   include <stdio.h>
-#   define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
-#else
-#   define DEBUG_PRINTF(...) {}
-#endif
-
-static void init_spi(spi_t *obj)
-{
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
-
-    __HAL_SPI_DISABLE(handle);
-
-    DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance);
-    if (HAL_SPI_Init(handle) != HAL_OK) {
-        error("Cannot initialize SPI");
-    }
-
-    __HAL_SPI_ENABLE(handle);
-}
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
-{
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
-
-    // Determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
-    spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
-    MBED_ASSERT(spiobj->spi != (SPIName)NC);
-
-    // Enable SPI clock
-    if (spiobj->spi == SPI_1) {
-        __HAL_RCC_SPI1_CLK_ENABLE();
-        spiobj->spiIRQ = SPI1_IRQn;
-    }
-
-    if (spiobj->spi == SPI_2) {
-        __HAL_RCC_SPI2_CLK_ENABLE();
-        spiobj->spiIRQ = SPI2_IRQn;
-    }
-
-#if defined SPI3_BASE
-    if (spiobj->spi == SPI_3) {
-        __HAL_RCC_SPI3_CLK_ENABLE();
-        spiobj->spiIRQ = SPI3_IRQn;
-    }
-#endif
-
-#if defined SPI4_BASE
-    if (spiobj->spi == SPI_4) {
-        __HAL_RCC_SPI4_CLK_ENABLE();
-        spiobj->spiIRQ = SPI4_IRQn;
-    }
-#endif
-
-#if defined SPI5_BASE
-    if (spiobj->spi == SPI_5) {
-        __HAL_RCC_SPI5_CLK_ENABLE();
-        spiobj->spiIRQ = SPI5_IRQn;
-    }
-#endif
-
-#if defined SPI6_BASE
-    if (spiobj->spi == SPI_6) {
-        __HAL_RCC_SPI6_CLK_ENABLE();
-        spiobj->spiIRQ = SPI6_IRQn;
-    }
-#endif
-
-    // Configure the SPI pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-    spiobj->pin_miso = miso;
-    spiobj->pin_mosi = mosi;
-    spiobj->pin_sclk = sclk;
-    spiobj->pin_ssel = ssel;
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    } else {
-        handle->Init.NSS = SPI_NSS_SOFT;
-    }
-
-    /* Fill default value */
-    handle->Instance = SPI_INST(obj);
-    handle->Init.Mode              = SPI_MODE_MASTER;
-    handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
-    handle->Init.Direction         = SPI_DIRECTION_2LINES;
-    handle->Init.CLKPhase          = SPI_PHASE_1EDGE;
-    handle->Init.CLKPolarity       = SPI_POLARITY_LOW;
-    handle->Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLED;
-    handle->Init.CRCPolynomial     = 7;
-    handle->Init.DataSize          = SPI_DATASIZE_8BIT;
-    handle->Init.FirstBit          = SPI_FIRSTBIT_MSB;
-    handle->Init.TIMode            = SPI_TIMODE_DISABLED;
-
-    init_spi(obj);
-}
-
-void spi_free(spi_t *obj)
-{
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
-
-    DEBUG_PRINTF("spi_free\r\n");
-
-    __HAL_SPI_DISABLE(handle);
-    HAL_SPI_DeInit(handle);
-
-    // Reset SPI and disable clock
-    if (spiobj->spi == SPI_1) {
-        __HAL_RCC_SPI1_FORCE_RESET();
-        __HAL_RCC_SPI1_RELEASE_RESET();
-        __HAL_RCC_SPI1_CLK_DISABLE();
-    }
-
-    if (spiobj->spi == SPI_2) {
-        __HAL_RCC_SPI2_FORCE_RESET();
-        __HAL_RCC_SPI2_RELEASE_RESET();
-        __HAL_RCC_SPI2_CLK_DISABLE();
-    }
-#if defined SPI3_BASE
-    if (spiobj->spi == SPI_3) {
-        __HAL_RCC_SPI3_FORCE_RESET();
-        __HAL_RCC_SPI3_RELEASE_RESET();
-        __HAL_RCC_SPI3_CLK_DISABLE();
-    }
-#endif
-
-#if defined SPI4_BASE
-    if (spiobj->spi == SPI_4) {
-        __HAL_RCC_SPI4_FORCE_RESET();
-        __HAL_RCC_SPI4_RELEASE_RESET();
-        __HAL_RCC_SPI4_CLK_DISABLE();
-    }
-#endif
-
-#if defined SPI5_BASE
-    if (spiobj->spi == SPI_5) {
-        __HAL_RCC_SPI5_FORCE_RESET();
-        __HAL_RCC_SPI5_RELEASE_RESET();
-        __HAL_RCC_SPI5_CLK_DISABLE();
-    }
-#endif
-
-#if defined SPI6_BASE
-    if (spiobj->spi == SPI_6) {
-        __HAL_RCC_SPI6_FORCE_RESET();
-        __HAL_RCC_SPI6_RELEASE_RESET();
-        __HAL_RCC_SPI6_CLK_DISABLE();
-    }
-#endif
-
-    // Configure GPIOs
-    pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    if (handle->Init.NSS != SPI_NSS_SOFT) {
-        pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    }
-}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave)
-{
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
-
-    DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave);
-
-    // Save new values
-    handle->Init.DataSize          = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
-
-    switch (mode) {
-        case 0:
-            handle->Init.CLKPolarity = SPI_POLARITY_LOW;
-            handle->Init.CLKPhase = SPI_PHASE_1EDGE;
-            break;
-        case 1:
-            handle->Init.CLKPolarity = SPI_POLARITY_LOW;
-            handle->Init.CLKPhase = SPI_PHASE_2EDGE;
-            break;
-        case 2:
-            handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
-            handle->Init.CLKPhase = SPI_PHASE_1EDGE;
-            break;
-        default:
-            handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
-            handle->Init.CLKPhase = SPI_PHASE_2EDGE;
-            break;
-    }
-
-    if (handle->Init.NSS != SPI_NSS_SOFT) {
-        handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
-    }
-
-    handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
-
-    init_spi(obj);
-}
-
-static const uint16_t baudrate_prescaler_table[] =	{SPI_BAUDRATEPRESCALER_2,
-                                                    SPI_BAUDRATEPRESCALER_4,
-                                                    SPI_BAUDRATEPRESCALER_8,
-                                                    SPI_BAUDRATEPRESCALER_16,
-                                                    SPI_BAUDRATEPRESCALER_32,
-                                                    SPI_BAUDRATEPRESCALER_64,
-                                                    SPI_BAUDRATEPRESCALER_128,
-                                                    SPI_BAUDRATEPRESCALER_256};
-
-void spi_frequency(spi_t *obj, int hz)
-{
+/*
+ * Only the frequency is managed in the family specific part
+ * the rest of SPI management is common to all STM32 families
+ */
+int spi_get_clock_freq(spi_t *obj) {
     struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
 	int spi_hz = 0;
-	uint8_t prescaler_rank = 0;
-
-    DEBUG_PRINTF("spi_frequency:%d\r\n", hz);
 
 	/* Get source clock depending on SPI instance */
     switch ((int)spiobj->spi) {
@@ -305,284 +76,10 @@ void spi_frequency(spi_t *obj, int hz)
             spi_hz = HAL_RCC_GetPCLK1Freq();
             break;
         default:
-            error("SPI instance not set");
-    }
-
-	/* Define pre-scaler in order to get highest available frequency below requested frequency */
-	while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
-		spi_hz = spi_hz / 2;
-		prescaler_rank++;
-	}
-
-	if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
-		handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank-1];
-	} else {
-		error("Couldn't setup requested SPI frequency");
-	}
-
-    init_spi(obj);
-}
-
-static inline int ssp_readable(spi_t *obj)
-{
-    int status;
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
-
-    // Check if data is received
-    status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline int ssp_writeable(spi_t *obj)
-{
-    int status;
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
-
-    // Check if data is transmitted
-    status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline void ssp_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = SPI_INST(obj);
-    while (!ssp_writeable(obj));
-    spi->DR = (uint16_t)value;
-}
-
-static inline int ssp_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = SPI_INST(obj);
-    while (!ssp_readable(obj));
-    return (int)spi->DR;
-}
-
-static inline int ssp_busy(spi_t *obj)
-{
-    int status;
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
-
-    status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
-    return status;
-}
-
-int spi_master_write(spi_t *obj, int value)
-{
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj)
-{
-    return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
-};
-
-int spi_slave_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = SPI_INST(obj);
-    while (!ssp_readable(obj));
-    return (int)spi->DR;
-}
-
-void spi_slave_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = SPI_INST(obj);
-    while (!ssp_writeable(obj));
-    spi->DR = (uint16_t)value;
-}
-
-int spi_busy(spi_t *obj)
-{
-    return ssp_busy(obj);
-}
-
-#ifdef DEVICE_SPI_ASYNCH
-typedef enum {
-    SPI_TRANSFER_TYPE_NONE = 0,
-    SPI_TRANSFER_TYPE_TX = 1,
-    SPI_TRANSFER_TYPE_RX = 2,
-    SPI_TRANSFER_TYPE_TXRX = 3,
-} transfer_type_t;
-
-
-/// @returns the number of bytes transferred, or `0` if nothing transferred
-static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length)
-{
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
-    bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
-    // the HAL expects number of transfers instead of number of bytes
-    // so for 16 bit transfer width the count needs to be halved
-    size_t words;
-
-    DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length);
-
-    obj->spi.transfer_type = transfer_type;
-
-    if (is16bit) words = length / 2;
-    else         words = length;
-
-    // enable the interrupt
-    IRQn_Type irq_n = spiobj->spiIRQ;
-    NVIC_ClearPendingIRQ(irq_n);
-    NVIC_DisableIRQ(irq_n);
-    NVIC_SetPriority(irq_n, 1);
-    NVIC_EnableIRQ(irq_n);
-
-    // enable the right hal transfer
-    //static uint16_t sink;
-    int rc = 0;
-    switch(transfer_type) {
-        case SPI_TRANSFER_TYPE_TXRX:
-            rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words);
-            break;
-        case SPI_TRANSFER_TYPE_TX:
-            // TODO: we do not use `HAL_SPI_Transmit_IT`, since it has some unknown bug
-            // and makes the HAL keep some state and then that fails successive transfers
-            rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words);
-            //rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)&sink, 1);
-            //length = is16bit ? 2 : 1;
+            error("CLK: SPI instance not set");
             break;
-        case SPI_TRANSFER_TYPE_RX:
-            // the receive function also "transmits" the receive buffer so in order
-            // to guarantee that 0xff is on the line, we explicitly memset it here
-            memset(rx, SPI_FILL_WORD, length);
-            rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words);
-            break;
-        default:
-            length = 0;
-    }
-
-    if (rc) {
-        DEBUG_PRINTF("SPI: RC=%u\n", rc);
-        length = 0;
-    }
-
-    return length;
-}
-
-// asynchronous API
-void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
-{
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
-
-    // TODO: DMA usage is currently ignored
-    (void) hint;
-
-    // check which use-case we have
-    bool use_tx = (tx != NULL && tx_length > 0);
-    bool use_rx = (rx != NULL && rx_length > 0);
-    bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
-
-    // don't do anything, if the buffers aren't valid
-    if (!use_tx && !use_rx)
-        return;
-
-    // copy the buffers to the SPI object
-    obj->tx_buff.buffer = (void *) tx;
-    obj->tx_buff.length = tx_length;
-    obj->tx_buff.pos = 0;
-    obj->tx_buff.width = is16bit ? 16 : 8;
-
-    obj->rx_buff.buffer = rx;
-    obj->rx_buff.length = rx_length;
-    obj->rx_buff.pos = 0;
-    obj->rx_buff.width = obj->tx_buff.width;
-
-    obj->spi.event = event;
-
-    DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length);
-
-    // register the thunking handler
-    IRQn_Type irq_n = spiobj->spiIRQ;
-    NVIC_SetVector(irq_n, (uint32_t)handler);
-
-    // enable the right hal transfer
-    if (use_tx && use_rx) {
-        // we cannot manage different rx / tx sizes, let's use smaller one
-        size_t size = (tx_length < rx_length)? tx_length : rx_length;
-        if(tx_length != rx_length) {
-            DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size);
-            obj->tx_buff.length = size;
-            obj->rx_buff.length = size;
-        }
-        spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size);
-    } else if (use_tx) {
-        spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length);
-    } else if (use_rx) {
-        spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length);
     }
+    return spi_hz;
 }
 
-uint32_t spi_irq_handler_asynch(spi_t *obj)
-{
-    // use the right instance
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &spiobj->handle;
-    int event = 0;
-
-    // call the CubeF4 handler, this will update the handle
-    HAL_SPI_IRQHandler(handle);
-
-    if (HAL_SPI_GetState(handle) == HAL_SPI_STATE_READY) {
-        // When HAL SPI is back to READY state, check if there was an error
-        int error = HAL_SPI_GetError(handle);
-        if(error != HAL_SPI_ERROR_NONE) {
-            // something went wrong and the transfer has definitely completed
-            event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
-
-            if (error & HAL_SPI_ERROR_OVR) {
-                // buffer overrun
-                event |= SPI_EVENT_RX_OVERFLOW;
-            }
-        } else {
-            // else we're done
-            event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
-       }
-    }
-
-    if (event) DEBUG_PRINTF("SPI: Event: 0x%x\n", event);
-
-    return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE));
-}
-
-uint8_t spi_active(spi_t *obj)
-{
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
-    HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle);
-
-    switch(state) {
-        case HAL_SPI_STATE_RESET:
-        case HAL_SPI_STATE_READY:
-        case HAL_SPI_STATE_ERROR:
-            return 0;
-        default:
-            return 1;
-    }
-}
-
-void spi_abort_asynch(spi_t *obj)
-{
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
-
-    // disable interrupt
-    IRQn_Type irq_n = spiobj->spiIRQ;
-    NVIC_ClearPendingIRQ(irq_n);
-    NVIC_DisableIRQ(irq_n);
-
-    // clean-up
-    __HAL_SPI_DISABLE(handle);
-    HAL_SPI_DeInit(handle);
-    HAL_SPI_Init(handle);
-    __HAL_SPI_ENABLE(handle);
-}
-
-#endif //DEVICE_SPI_ASYNCH
-
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/objects.h
index 84c61ff5448..40972f65744 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/objects.h
index 7639c231df1..3e253f11acd 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/objects.h
index e8af139f961..84fc17241de 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/objects.h
index 7639c231df1..3e253f11acd 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32F7/common_objects.h b/targets/TARGET_STM/TARGET_STM32F7/common_objects.h
index eef1f6aced4..1aa659360e7 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/common_objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/common_objects.h
@@ -49,6 +49,21 @@ struct pwmout_s {
     uint8_t inverted;
 };
 
+struct spi_s {
+    SPI_HandleTypeDef handle;
+    IRQn_Type spiIRQ;
+    SPIName spi;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+#ifdef DEVICE_SPI_ASYNCH
+    uint32_t event;
+    uint8_t module;
+    uint8_t transfer_type;
+#endif
+};
+
 struct serial_s {
     UARTName uart;
     int index; // Used by irq
diff --git a/targets/TARGET_STM/TARGET_STM32F7/spi_api.c b/targets/TARGET_STM/TARGET_STM32F7/spi_api.c
index 255e03d38d1..6e54e2bf937 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/spi_api.c
+++ b/targets/TARGET_STM/TARGET_STM32F7/spi_api.c
@@ -33,202 +33,27 @@
 
 #if DEVICE_SPI
 
-#include <math.h>
 #include "cmsis.h"
 #include "pinmap.h"
 #include "PeripheralPins.h"
 #include "mbed_error.h"
 
-static SPI_HandleTypeDef SpiHandle;
-
-static void init_spi(spi_t *obj)
-{
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-
-    __HAL_SPI_DISABLE(&SpiHandle);
-
-    SpiHandle.Init.Mode              = obj->mode;
-    SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
-    SpiHandle.Init.Direction         = SPI_DIRECTION_2LINES;
-    SpiHandle.Init.CLKPhase          = obj->cpha;
-    SpiHandle.Init.CLKPolarity       = obj->cpol;
-    SpiHandle.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLED;
-    SpiHandle.Init.CRCPolynomial     = 7;
-    SpiHandle.Init.DataSize          = obj->bits;
-    SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
-    SpiHandle.Init.NSS               = obj->nss;
-    SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLED;
-
-    if (HAL_SPI_Init(&SpiHandle) != HAL_OK) {
-        error("Cannot initialize SPI");
-    }
-
-    __HAL_SPI_ENABLE(&SpiHandle);
-}
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
-{
-    // Determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
-    obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
-    MBED_ASSERT(obj->spi != (SPIName)NC);
-
-    // Enable SPI clock
-    if (obj->spi == SPI_1) {
-        __HAL_RCC_SPI1_CLK_ENABLE();
-    }
-
-    if (obj->spi == SPI_2) {
-        __HAL_RCC_SPI2_CLK_ENABLE();
-    }
-
-    if (obj->spi == SPI_3) {
-        __HAL_RCC_SPI3_CLK_ENABLE();
-    }
-
-    if (obj->spi == SPI_4) {
-        __HAL_RCC_SPI4_CLK_ENABLE();
-    }
-
-    if (obj->spi == SPI_5) {
-        __HAL_RCC_SPI5_CLK_ENABLE();
-    }
-
-    if (obj->spi == SPI_6) {
-        __HAL_RCC_SPI6_CLK_ENABLE();
-    }
-
-    // Configure the SPI pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-
-    // Save new values
-    obj->bits = SPI_DATASIZE_8BIT;
-    obj->cpol = SPI_POLARITY_LOW;
-    obj->cpha = SPI_PHASE_1EDGE;
-    obj->br_presc = SPI_BAUDRATEPRESCALER_256;
-
-    obj->pin_miso = miso;
-    obj->pin_mosi = mosi;
-    obj->pin_sclk = sclk;
-    obj->pin_ssel = ssel;
-
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    } else {
-        obj->nss = SPI_NSS_SOFT;
-    }
-
-    init_spi(obj);
-}
-
-void spi_free(spi_t *obj)
-{
-    // Reset SPI and disable clock
-    if (obj->spi == SPI_1) {
-        __HAL_RCC_SPI1_FORCE_RESET();
-        __HAL_RCC_SPI1_RELEASE_RESET();
-        __HAL_RCC_SPI1_CLK_DISABLE();
-    }
-
-    if (obj->spi == SPI_2) {
-        __HAL_RCC_SPI2_FORCE_RESET();
-        __HAL_RCC_SPI2_RELEASE_RESET();
-        __HAL_RCC_SPI2_CLK_DISABLE();
-    }
-
-    if (obj->spi == SPI_3) {
-        __HAL_RCC_SPI3_FORCE_RESET();
-        __HAL_RCC_SPI3_RELEASE_RESET();
-        __HAL_RCC_SPI3_CLK_DISABLE();
-    }
-    
-    if (obj->spi == SPI_4) {
-        __HAL_RCC_SPI4_FORCE_RESET();
-        __HAL_RCC_SPI4_RELEASE_RESET();
-        __HAL_RCC_SPI4_CLK_DISABLE();
-    }
-
-    if (obj->spi == SPI_5) {
-        __HAL_RCC_SPI5_FORCE_RESET();
-        __HAL_RCC_SPI5_RELEASE_RESET();
-        __HAL_RCC_SPI5_CLK_DISABLE();
-    }
-
-    if (obj->spi == SPI_6) {
-        __HAL_RCC_SPI6_FORCE_RESET();
-        __HAL_RCC_SPI6_RELEASE_RESET();
-        __HAL_RCC_SPI6_CLK_DISABLE();
-    }
-
-    // Configure GPIOs
-    pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave)
-{
-    // Save new values
-    if (bits == 16) {
-        obj->bits = SPI_DATASIZE_16BIT;
-    } else {
-        obj->bits = SPI_DATASIZE_8BIT;
-    }
-
-    switch (mode) {
-        case 0:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        case 1:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-        case 2:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        default:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-    }
-
-    if (obj->nss != SPI_NSS_SOFT) {
-        obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
-    }
-
-    obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
-
-    init_spi(obj);
-}
-
-static const uint16_t baudrate_prescaler_table[] =	{SPI_BAUDRATEPRESCALER_2,
-                                                    SPI_BAUDRATEPRESCALER_4,
-                                                    SPI_BAUDRATEPRESCALER_8,
-                                                    SPI_BAUDRATEPRESCALER_16,
-                                                    SPI_BAUDRATEPRESCALER_32,
-                                                    SPI_BAUDRATEPRESCALER_64,
-                                                    SPI_BAUDRATEPRESCALER_128,
-                                                    SPI_BAUDRATEPRESCALER_256};
+#if DEVICE_SPI_ASYNCH
+    #define SPI_S(obj)    (( struct spi_s *)(&(obj->spi)))
+#else
+    #define SPI_S(obj)    (( struct spi_s *)(obj))
+#endif
 
-void spi_frequency(spi_t *obj, int hz)
-{
+/*
+ * Only the frequency is managed in the family specific part
+ * the rest of SPI management is common to all STM32 families
+ */
+int spi_get_clock_freq(spi_t *obj) {
+    struct spi_s *spiobj = SPI_S(obj);
 	int spi_hz = 0;
-	uint8_t prescaler_rank = 0;
-	
+
 	/* Get source clock depending on SPI instance */
-    switch ((int)obj->spi) {
+    switch ((int)spiobj->spi) {
         case SPI_1:
 		case SPI_4:
 		case SPI_5:
@@ -242,120 +67,10 @@ void spi_frequency(spi_t *obj, int hz)
 			spi_hz = HAL_RCC_GetPCLK1Freq();
 			break;
 		default:
-			error("SPI instance not set");
-    }
-
-	/* Define pre-scaler in order to get highest available frequency below requested frequency */
-	while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
-		spi_hz = spi_hz / 2;
-		prescaler_rank++;
-	}
-
-	if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
-		obj->br_presc = baudrate_prescaler_table[prescaler_rank-1];
-	} else {
-		error("Couldn't setup requested SPI frequency");
-	}
-
-    init_spi(obj);
-}
-
-static inline int ssp_readable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is received
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline int ssp_writeable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is transmitted
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline void ssp_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        *p_spi_dr = (uint8_t)value;
-    } else { // SPI_DATASIZE_16BIT
-        spi->DR = (uint16_t)value;
-    }
-}
-
-static inline int ssp_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        return (int)(*p_spi_dr);
-    } else {
-        return (int)spi->DR;
-    }
-}
-
-static inline int ssp_busy(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
-    return status;
-}
-
-int spi_master_write(spi_t *obj, int value)
-{
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj)
-{
-    return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
-};
-
-int spi_slave_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        return (int)(*p_spi_dr);
-    } else {
-        return (int)spi->DR;
-    }
-}
-
-void spi_slave_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        *p_spi_dr = (uint8_t)value;
-    } else { // SPI_DATASIZE_16BIT
-        spi->DR = (uint16_t)value;
+			error("CLK: SPI instance not set");
+            break;
     }
-}
-
-int spi_busy(spi_t *obj)
-{
-    return ssp_busy(obj);
+    return spi_hz;
 }
 
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h
index 3932d461284..5f05cd5bdaf 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/objects.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/objects.h
index 2d78a15eedb..f006abac8a9 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/objects.h
@@ -60,20 +60,6 @@ struct analogin_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/objects.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/objects.h
index 2d78a15eedb..f006abac8a9 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/objects.h
@@ -60,20 +60,6 @@ struct analogin_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/objects.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/objects.h
index b464a5f2e79..617ccbb6973 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h
index 3932d461284..5f05cd5bdaf 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32L0/common_objects.h b/targets/TARGET_STM/TARGET_STM32L0/common_objects.h
index 585d323084c..fd235f0781f 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/common_objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/common_objects.h
@@ -49,6 +49,21 @@ struct pwmout_s {
     uint8_t inverted;
 };
 
+struct spi_s {
+    SPI_HandleTypeDef handle;
+    IRQn_Type spiIRQ;
+    SPIName spi;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+#ifdef DEVICE_SPI_ASYNCH
+    uint32_t event;
+    uint8_t module;
+    uint8_t transfer_type;
+#endif
+};
+
 struct serial_s {
     UARTName uart;
     int index; // Used by irq
diff --git a/targets/TARGET_STM/TARGET_STM32L0/spi_api.c b/targets/TARGET_STM/TARGET_STM32L0/spi_api.c
index bbd0838a1fb..44c422c9f2b 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/spi_api.c
+++ b/targets/TARGET_STM/TARGET_STM32L0/spi_api.c
@@ -33,166 +33,28 @@
 
 #if DEVICE_SPI
 
-#include <math.h>
 #include "cmsis.h"
 #include "pinmap.h"
 #include "mbed_error.h"
 #include "PeripheralPins.h"
 
-static SPI_HandleTypeDef SpiHandle;
-
-static void init_spi(spi_t *obj)
-{
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-
-    __HAL_SPI_DISABLE(&SpiHandle);
-
-    SpiHandle.Init.Mode              = obj->mode;
-    SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
-    SpiHandle.Init.Direction         = SPI_DIRECTION_2LINES;
-    SpiHandle.Init.CLKPhase          = obj->cpha;
-    SpiHandle.Init.CLKPolarity       = obj->cpol;
-    SpiHandle.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLED;
-    SpiHandle.Init.CRCPolynomial     = 7;
-    SpiHandle.Init.DataSize          = obj->bits;
-    SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
-    SpiHandle.Init.NSS               = obj->nss;
-    SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLED;
-
-    if (HAL_SPI_Init(&SpiHandle) != HAL_OK) {
-        error("Cannot initialize SPI");
-    }
-
-    __HAL_SPI_ENABLE(&SpiHandle);
-}
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
-{
-    // Determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
-    obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
-    MBED_ASSERT(obj->spi != (SPIName)NC);
-
-    // Enable SPI clock
-    if (obj->spi == SPI_1) {
-        __SPI1_CLK_ENABLE();
-    }
-
-#if defined(SPI2_BASE)
-    if (obj->spi == SPI_2) {
-        __SPI2_CLK_ENABLE();
-    }
-#endif
-
-    // Configure the SPI pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-
-    // Save new values
-    obj->bits = SPI_DATASIZE_8BIT;
-    obj->cpol = SPI_POLARITY_LOW;
-    obj->cpha = SPI_PHASE_1EDGE;
-    obj->br_presc = SPI_BAUDRATEPRESCALER_256;
-
-    obj->pin_miso = miso;
-    obj->pin_mosi = mosi;
-    obj->pin_sclk = sclk;
-    obj->pin_ssel = ssel;
-
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    } else {
-        obj->nss = SPI_NSS_SOFT;
-    }
-
-    init_spi(obj);
-}
-
-void spi_free(spi_t *obj)
-{
-    // Reset SPI and disable clock
-    if (obj->spi == SPI_1) {
-        __SPI1_FORCE_RESET();
-        __SPI1_RELEASE_RESET();
-        __SPI1_CLK_DISABLE();
-    }
-
-#if defined(SPI2_BASE)
-    if (obj->spi == SPI_2) {
-        __SPI2_FORCE_RESET();
-        __SPI2_RELEASE_RESET();
-        __SPI2_CLK_DISABLE();
-    }
+#if DEVICE_SPI_ASYNCH
+    #define SPI_S(obj)    (( struct spi_s *)(&(obj->spi)))
+#else
+    #define SPI_S(obj)    (( struct spi_s *)(obj))
 #endif
 
-    // Configure GPIO
-    pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave)
-{
-    // Save new values
-    if (bits == 16) {
-        obj->bits = SPI_DATASIZE_16BIT;
-    } else {
-        obj->bits = SPI_DATASIZE_8BIT;
-    }
 
-    switch (mode) {
-        case 0:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        case 1:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-        case 2:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        default:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-    }
-
-    if (obj->nss != SPI_NSS_SOFT) {
-        obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
-    }
-
-    obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
-
-    init_spi(obj);
-}
-
-static const uint16_t baudrate_prescaler_table[] =	{SPI_BAUDRATEPRESCALER_2,
-                                                    SPI_BAUDRATEPRESCALER_4,
-                                                    SPI_BAUDRATEPRESCALER_8,
-                                                    SPI_BAUDRATEPRESCALER_16,
-                                                    SPI_BAUDRATEPRESCALER_32,
-                                                    SPI_BAUDRATEPRESCALER_64,
-                                                    SPI_BAUDRATEPRESCALER_128,
-                                                    SPI_BAUDRATEPRESCALER_256};
-
-void spi_frequency(spi_t *obj, int hz)
-{
+/*
+ * Only the frequency is managed in the family specific part
+ * the rest of SPI management is common to all STM32 families
+ */
+int spi_get_clock_freq(spi_t *obj) {
+    struct spi_s *spiobj = SPI_S(obj);
 	int spi_hz = 0;
-	uint8_t prescaler_rank = 0;
 
 	/* Get source clock depending on SPI instance */
-    switch ((int)obj->spi) {
+    switch ((int)spiobj->spi) {
         case SPI_1:
 			/* SPI_1. Source CLK is PCKL2 */
 			spi_hz = HAL_RCC_GetPCLK2Freq();
@@ -204,92 +66,10 @@ void spi_frequency(spi_t *obj, int hz)
 			break;
 #endif
 		default:
-			error("SPI instance not set");
+			error("CLK: SPI instance not set");
+            break;
     }
-
-	/* Define pre-scaler in order to get highest available frequency below requested frequency */
-	while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
-		spi_hz = spi_hz / 2;
-		prescaler_rank++;
-	}
-
-	if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
-		obj->br_presc = baudrate_prescaler_table[prescaler_rank-1];
-	} else {
-		error("Couldn't setup requested SPI frequency");
-	}
-
-    init_spi(obj);
-}
-
-static inline int ssp_readable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is received
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline int ssp_writeable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is transmitted
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline void ssp_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    spi->DR = (uint16_t)value;
-}
-
-static inline int ssp_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    return (int)spi->DR;
-}
-
-static inline int ssp_busy(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
-    return status;
-}
-
-int spi_master_write(spi_t *obj, int value)
-{
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj)
-{
-    return (ssp_readable(obj) ? 1 : 0);
-};
-
-int spi_slave_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    return (int)spi->DR;
-}
-
-void spi_slave_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    spi->DR = (uint16_t)value;
-}
-
-int spi_busy(spi_t *obj)
-{
-    return ssp_busy(obj);
+    return spi_hz;
 }
 
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h
index 7a0d5f1489f..84754ae7488 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h
@@ -65,20 +65,6 @@ struct dac_s {
     PinName pin;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/objects.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/objects.h
index 7a0d5f1489f..84754ae7488 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/objects.h
@@ -65,20 +65,6 @@ struct dac_s {
     PinName pin;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/objects.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/objects.h
index 7a0d5f1489f..84754ae7488 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/objects.h
@@ -65,20 +65,6 @@ struct dac_s {
     PinName pin;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32L1/common_objects.h b/targets/TARGET_STM/TARGET_STM32L1/common_objects.h
index 335b444aac0..fbbbc9868a7 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/common_objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L1/common_objects.h
@@ -66,6 +66,21 @@ struct serial_s {
 #endif
 };
 
+struct spi_s {
+    SPI_HandleTypeDef handle;
+    IRQn_Type spiIRQ;
+    SPIName spi;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+#ifdef DEVICE_SPI_ASYNCH
+    uint32_t event;
+    uint8_t module;
+    uint8_t transfer_type;
+#endif
+};
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32L1/spi_api.c b/targets/TARGET_STM/TARGET_STM32L1/spi_api.c
index e312af1e4c7..ed3efe7a8e8 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/spi_api.c
+++ b/targets/TARGET_STM/TARGET_STM32L1/spi_api.c
@@ -33,167 +33,27 @@
 
 #if DEVICE_SPI
 
-#include <math.h>
 #include "cmsis.h"
 #include "pinmap.h"
 #include "PeripheralPins.h"
 
-static SPI_HandleTypeDef SpiHandle;
 
-static void init_spi(spi_t *obj)
-{
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-
-    __HAL_SPI_DISABLE(&SpiHandle);
-
-    SpiHandle.Init.Mode              = obj->mode;
-    SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
-    SpiHandle.Init.Direction         = SPI_DIRECTION_2LINES;
-    SpiHandle.Init.CLKPhase          = obj->cpha;
-    SpiHandle.Init.CLKPolarity       = obj->cpol;
-    SpiHandle.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLED;
-    SpiHandle.Init.CRCPolynomial     = 7;
-    SpiHandle.Init.DataSize          = obj->bits;
-    SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
-    SpiHandle.Init.NSS               = obj->nss;
-    SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLED;
-
-    HAL_SPI_Init(&SpiHandle);
-
-    __HAL_SPI_ENABLE(&SpiHandle);
-}
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
-{
-    // Determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
-    obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
-    MBED_ASSERT(obj->spi != (SPIName)NC);
-
-    // Enable SPI clock
-    if (obj->spi == SPI_1) {
-        __SPI1_CLK_ENABLE();
-    }
-    if (obj->spi == SPI_2) {
-        __SPI2_CLK_ENABLE();
-    }
-    if (obj->spi == SPI_3) {
-        __SPI3_CLK_ENABLE();
-    }
-
-    // Configure the SPI pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-
-    // Save new values
-    obj->bits = SPI_DATASIZE_8BIT;
-    obj->cpol = SPI_POLARITY_LOW;
-    obj->cpha = SPI_PHASE_1EDGE;
-    obj->br_presc = SPI_BAUDRATEPRESCALER_256;
-
-    obj->pin_miso = miso;
-    obj->pin_mosi = mosi;
-    obj->pin_sclk = sclk;
-    obj->pin_ssel = ssel;
-
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    } else {
-        obj->nss = SPI_NSS_SOFT;
-    }
-
-    init_spi(obj);
-}
-
-void spi_free(spi_t *obj)
-{
-    // Reset SPI and disable clock
-    if (obj->spi == SPI_1) {
-        __SPI1_FORCE_RESET();
-        __SPI1_RELEASE_RESET();
-        __SPI1_CLK_DISABLE();
-    }
-
-    if (obj->spi == SPI_2) {
-        __SPI2_FORCE_RESET();
-        __SPI2_RELEASE_RESET();
-        __SPI2_CLK_DISABLE();
-    }
-
-    if (obj->spi == SPI_3) {
-        __SPI3_FORCE_RESET();
-        __SPI3_RELEASE_RESET();
-        __SPI3_CLK_DISABLE();
-    }
-
-    // Configure GPIO
-    pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave)
-{
-    // Save new values
-    if (bits == 16) {
-        obj->bits = SPI_DATASIZE_16BIT;
-    } else {
-        obj->bits = SPI_DATASIZE_8BIT;
-    }
-
-    switch (mode) {
-        case 0:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        case 1:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-        case 2:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        default:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-    }
-
-    if (obj->nss != SPI_NSS_SOFT) {
-        obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
-    }
-
-    obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
-
-    init_spi(obj);
-}
-
-static const uint16_t baudrate_prescaler_table[] =	{SPI_BAUDRATEPRESCALER_2,
-                                                    SPI_BAUDRATEPRESCALER_4,
-                                                    SPI_BAUDRATEPRESCALER_8,
-                                                    SPI_BAUDRATEPRESCALER_16,
-                                                    SPI_BAUDRATEPRESCALER_32,
-                                                    SPI_BAUDRATEPRESCALER_64,
-                                                    SPI_BAUDRATEPRESCALER_128,
-                                                    SPI_BAUDRATEPRESCALER_256};
+#if DEVICE_SPI_ASYNCH
+    #define SPI_S(obj)    (( struct spi_s *)(&(obj->spi)))
+#else
+    #define SPI_S(obj)    (( struct spi_s *)(obj))
+#endif
 
-void spi_frequency(spi_t *obj, int hz)
-{
+/*
+ * Only the frequency is managed in the family specific part
+ * the rest of SPI management is common to all STM32 families
+ */
+int spi_get_clock_freq(spi_t *obj) {
+    struct spi_s *spiobj = SPI_S(obj);
 	int spi_hz = 0;
-	uint8_t prescaler_rank = 0;
 
 	/* Get source clock depending on SPI instance */
-    switch ((int)obj->spi) {
+    switch ((int)spiobj->spi) {
         case SPI_1:
 			/* SPI_1. Source CLK is PCKL2 */
 			spi_hz = HAL_RCC_GetPCLK2Freq();
@@ -204,92 +64,10 @@ void spi_frequency(spi_t *obj, int hz)
 			spi_hz = HAL_RCC_GetPCLK1Freq();
 			break;
 		default:
-			error("SPI instance not set");
+			error("CLK: SPI instance not set");
+            break;
     }
-
-	/* Define pre-scaler in order to get highest available frequency below requested frequency */
-	while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
-		spi_hz = spi_hz / 2;
-		prescaler_rank++;
-	}
-
-	if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
-		obj->br_presc = baudrate_prescaler_table[prescaler_rank-1];
-	} else {
-		error("Couldn't setup requested SPI frequency");
-	}
-
-    init_spi(obj);
-}
-
-static inline int ssp_readable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is received
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline int ssp_writeable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is transmitted
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline void ssp_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    spi->DR = (uint16_t)value;
-}
-
-static inline int ssp_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    return (int)spi->DR;
-}
-
-static inline int ssp_busy(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
-    return status;
-}
-
-int spi_master_write(spi_t *obj, int value)
-{
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj)
-{
-    return (ssp_readable(obj) ? 1 : 0);
-};
-
-int spi_slave_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    return (int)spi->DR;
-}
-
-void spi_slave_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    spi->DR = (uint16_t)value;
-}
-
-int spi_busy(spi_t *obj)
-{
-    return ssp_busy(obj);
+    return spi_hz;
 }
 
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/objects.h
index 20556881d81..6d890131c39 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/objects.h
index c3407b008d6..689609d7979 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/objects.h
index 20556881d81..6d890131c39 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/objects.h
@@ -66,20 +66,6 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
diff --git a/targets/TARGET_STM/TARGET_STM32L4/common_objects.h b/targets/TARGET_STM/TARGET_STM32L4/common_objects.h
index 585d323084c..fd235f0781f 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/common_objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/common_objects.h
@@ -49,6 +49,21 @@ struct pwmout_s {
     uint8_t inverted;
 };
 
+struct spi_s {
+    SPI_HandleTypeDef handle;
+    IRQn_Type spiIRQ;
+    SPIName spi;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+#ifdef DEVICE_SPI_ASYNCH
+    uint32_t event;
+    uint8_t module;
+    uint8_t transfer_type;
+#endif
+};
+
 struct serial_s {
     UARTName uart;
     int index; // Used by irq
diff --git a/targets/TARGET_STM/TARGET_STM32L4/spi_api.c b/targets/TARGET_STM/TARGET_STM32L4/spi_api.c
index c0ec856511f..d383c9d31f2 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/spi_api.c
+++ b/targets/TARGET_STM/TARGET_STM32L4/spi_api.c
@@ -32,311 +32,43 @@
 
 #if DEVICE_SPI
 
-#include <math.h>
 #include "cmsis.h"
 #include "pinmap.h"
 #include "mbed_error.h"
 #include "PeripheralPins.h"
 
-static SPI_HandleTypeDef SpiHandle;
-
-static void init_spi(spi_t *obj)
-{
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-
-    __HAL_SPI_DISABLE(&SpiHandle);
-
-    SpiHandle.Init.Mode              = obj->mode;
-    SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
-    SpiHandle.Init.Direction         = SPI_DIRECTION_2LINES;
-    SpiHandle.Init.CLKPhase          = obj->cpha;
-    SpiHandle.Init.CLKPolarity       = obj->cpol;
-    SpiHandle.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLE;
-    SpiHandle.Init.CRCPolynomial     = 7;
-    SpiHandle.Init.CRCLength         = SPI_CRC_LENGTH_8BIT;
-    SpiHandle.Init.DataSize          = obj->bits;
-    SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
-    SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLE;
-    SpiHandle.Init.NSS               = obj->nss;
-    SpiHandle.Init.NSSPMode          = SPI_NSS_PULSE_DISABLE;
-
-    if (HAL_SPI_Init(&SpiHandle) != HAL_OK) {
-        error("Cannot initialize SPI\n");
-    }
-
-    __HAL_SPI_ENABLE(&SpiHandle);
-}
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
-{
-    // Determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
-    obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
-    MBED_ASSERT(obj->spi != (SPIName)NC);
-
-    // Enable SPI clock
-    if (obj->spi == SPI_1) {
-        __HAL_RCC_SPI1_CLK_ENABLE();
-    }
-#if defined(SPI2_BASE)
-    if (obj->spi == SPI_2) {
-        __HAL_RCC_SPI2_CLK_ENABLE();
-    }
+#if DEVICE_SPI_ASYNCH
+    #define SPI_S(obj)    (( struct spi_s *)(&(obj->spi)))
+#else
+    #define SPI_S(obj)    (( struct spi_s *)(obj))
 #endif
-    if (obj->spi == SPI_3) {
-        __HAL_RCC_SPI3_CLK_ENABLE();
-    }
-
-    // Configure the SPI pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-
-    // Save new values
-    obj->bits = SPI_DATASIZE_8BIT;
-    obj->cpol = SPI_POLARITY_LOW;
-    obj->cpha = SPI_PHASE_1EDGE;
-    obj->br_presc = SPI_BAUDRATEPRESCALER_256;
-
-    obj->pin_miso = miso;
-    obj->pin_mosi = mosi;
-    obj->pin_sclk = sclk;
-    obj->pin_ssel = ssel;
-
-    if (ssel == NC) { // SW NSS Master mode
-        obj->mode = SPI_MODE_MASTER;
-        obj->nss = SPI_NSS_SOFT;
-    } else { // Slave
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-        obj->mode = SPI_MODE_SLAVE;
-        obj->nss = SPI_NSS_HARD_INPUT;
-    }
 
-    init_spi(obj);
-}
-
-void spi_free(spi_t *obj)
-{
-    // Reset SPI and disable clock
-    if (obj->spi == SPI_1) {
-        __HAL_RCC_SPI1_FORCE_RESET();
-        __HAL_RCC_SPI1_RELEASE_RESET();
-        __HAL_RCC_SPI1_CLK_DISABLE();
-    }
-
-#if defined(SPI2_BASE)
-    if (obj->spi == SPI_2) {
-        __HAL_RCC_SPI2_FORCE_RESET();
-        __HAL_RCC_SPI2_RELEASE_RESET();
-        __HAL_RCC_SPI2_CLK_DISABLE();
-    }
-#endif
-
-    if (obj->spi == SPI_3) {
-        __HAL_RCC_SPI3_FORCE_RESET();
-        __HAL_RCC_SPI3_RELEASE_RESET();
-        __HAL_RCC_SPI3_CLK_DISABLE();
-    }
-
-    // Configure GPIO
-    pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave)
-{
-    // Save new values
-    if (bits == 16) {
-        obj->bits = SPI_DATASIZE_16BIT;
-    } else {
-        obj->bits = SPI_DATASIZE_8BIT;
-    }
-
-    switch (mode) {
-        case 0:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        case 1:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-        case 2:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        default:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-    }
-
-    if (slave == 0) {
-        obj->mode = SPI_MODE_MASTER;
-        obj->nss = SPI_NSS_SOFT;
-    } else {
-        obj->mode = SPI_MODE_SLAVE;
-        obj->nss = SPI_NSS_HARD_INPUT;
-    }
-
-    init_spi(obj);
-}
-
-static const uint16_t baudrate_prescaler_table[] =	{SPI_BAUDRATEPRESCALER_2,
-                                                    SPI_BAUDRATEPRESCALER_4,
-                                                    SPI_BAUDRATEPRESCALER_8,
-                                                    SPI_BAUDRATEPRESCALER_16,
-                                                    SPI_BAUDRATEPRESCALER_32,
-                                                    SPI_BAUDRATEPRESCALER_64,
-                                                    SPI_BAUDRATEPRESCALER_128,
-                                                    SPI_BAUDRATEPRESCALER_256};
-
-void spi_frequency(spi_t *obj, int hz)
-{
+/*
+ * Only the frequency is managed in the family specific part
+ * the rest of SPI management is common to all STM32 families
+ */
+int spi_get_clock_freq(spi_t *obj) {
+    struct spi_s *spiobj = SPI_S(obj);
 	int spi_hz = 0;
-	uint8_t prescaler_rank = 0;
 
 	/* Get source clock depending on SPI instance */
-    switch ((int)obj->spi) {
+    switch ((int)spiobj->spi) {
         case SPI_1:
-    			/* SPI_1. Source CLK is PCKL2 */
-    			spi_hz = HAL_RCC_GetPCLK2Freq();
-    			break;
+            /* SPI_1. Source CLK is PCKL2 */
+            spi_hz = HAL_RCC_GetPCLK2Freq();
+            break;
 #if defined(SPI2_BASE)
-    		case SPI_2:
+        case SPI_2:
 #endif
-    		case SPI_3:
-    			/* SPI_2, SPI_3. Source CLK is PCKL1 */
-    			spi_hz = HAL_RCC_GetPCLK1Freq();
-    			break;
-    		default:
-    			error("SPI instance not set");
-    }
-
-	/* Define pre-scaler in order to get highest available frequency below requested frequency */
-	while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
-		spi_hz = spi_hz / 2;
-		prescaler_rank++;
-	}
-
-	if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
-		obj->br_presc = baudrate_prescaler_table[prescaler_rank-1];
-	} else {
-		error("Couldn't setup requested SPI frequency");
-	}
-
-    init_spi(obj);
-}
-
-static inline int ssp_readable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is received
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline int ssp_writeable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is transmitted
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline void ssp_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    //spi->DR = (uint16_t)value;
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        *p_spi_dr = (uint8_t)value;
-    } else { // SPI_DATASIZE_16BIT
-        spi->DR = (uint16_t)value;
-    }
-}
-
-static inline int ssp_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    //return (int)spi->DR;
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        return (int)(*p_spi_dr);
-    } else {
-        return (int)spi->DR;
-    }
-}
-
-static inline int ssp_busy(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
-    return status;
-}
-
-int spi_master_write(spi_t *obj, int value)
-{
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj)
-{
-    return (ssp_readable(obj) ? 1 : 0);
-};
-
-int spi_slave_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    //return (int)spi->DR;
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        return (int)(*p_spi_dr);
-    } else {
-        return (int)spi->DR;
-    }
-}
-
-void spi_slave_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    //spi->DR = (uint16_t)value;
-    if (obj->bits == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        *p_spi_dr = (uint8_t)value;
-    } else { // SPI_DATASIZE_16BIT
-        spi->DR = (uint16_t)value;
+        case SPI_3:
+            /* SPI_2, SPI_3. Source CLK is PCKL1 */
+            spi_hz = HAL_RCC_GetPCLK1Freq();
+            break;
+        default:
+			error("CLK: SPI instance not set");
+            break;
     }
-}
-
-int spi_busy(spi_t *obj)
-{
-    return ssp_busy(obj);
+    return spi_hz;
 }
 
 #endif
diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c
new file mode 100644
index 00000000000..b8b0f79cbac
--- /dev/null
+++ b/targets/TARGET_STM/stm_spi_api.c
@@ -0,0 +1,613 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "spi_api.h"
+
+#if DEVICE_SPI
+#include <stdbool.h>
+#include <math.h>
+#include <string.h>
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+#if DEVICE_SPI_ASYNCH
+    #define SPI_INST(obj)    ((SPI_TypeDef *)(obj->spi.spi))
+#else
+    #define SPI_INST(obj)    ((SPI_TypeDef *)(obj->spi))
+#endif
+
+#if DEVICE_SPI_ASYNCH
+    #define SPI_S(obj)    (( struct spi_s *)(&(obj->spi)))
+#else
+    #define SPI_S(obj)    (( struct spi_s *)(obj))
+#endif
+
+#ifndef DEBUG_STDIO
+#   define DEBUG_STDIO 0
+#endif
+
+#if DEBUG_STDIO
+#   include <stdio.h>
+#   define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
+#else
+#   define DEBUG_PRINTF(...) {}
+#endif
+
+void init_spi(spi_t *obj)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    __HAL_SPI_DISABLE(handle);
+
+    DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance);
+    if (HAL_SPI_Init(handle) != HAL_OK) {
+        error("Cannot initialize SPI");
+    }
+
+    __HAL_SPI_ENABLE(handle);
+}
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    // Determine the SPI to use
+    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+
+    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+
+    spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
+    MBED_ASSERT(spiobj->spi != (SPIName)NC);
+
+#if defined SPI1_BASE
+    // Enable SPI clock
+    if (spiobj->spi == SPI_1) {
+        __HAL_RCC_SPI1_CLK_ENABLE();
+        spiobj->spiIRQ = SPI1_IRQn;
+    }
+#endif
+
+#if defined SPI2_BASE
+    if (spiobj->spi == SPI_2) {
+        __HAL_RCC_SPI2_CLK_ENABLE();
+        spiobj->spiIRQ = SPI2_IRQn;
+    }
+#endif
+
+#if defined SPI3_BASE
+    if (spiobj->spi == SPI_3) {
+        __HAL_RCC_SPI3_CLK_ENABLE();
+        spiobj->spiIRQ = SPI3_IRQn;
+    }
+#endif
+
+#if defined SPI4_BASE
+    if (spiobj->spi == SPI_4) {
+        __HAL_RCC_SPI4_CLK_ENABLE();
+        spiobj->spiIRQ = SPI4_IRQn;
+    }
+#endif
+
+#if defined SPI5_BASE
+    if (spiobj->spi == SPI_5) {
+        __HAL_RCC_SPI5_CLK_ENABLE();
+        spiobj->spiIRQ = SPI5_IRQn;
+    }
+#endif
+
+#if defined SPI6_BASE
+    if (spiobj->spi == SPI_6) {
+        __HAL_RCC_SPI6_CLK_ENABLE();
+        spiobj->spiIRQ = SPI6_IRQn;
+    }
+#endif
+
+    // Configure the SPI pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    spiobj->pin_miso = miso;
+    spiobj->pin_mosi = mosi;
+    spiobj->pin_sclk = sclk;
+    spiobj->pin_ssel = ssel;
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    } else {
+        handle->Init.NSS = SPI_NSS_SOFT;
+    }
+
+    /* Fill default value */
+    handle->Instance = SPI_INST(obj);
+    handle->Init.Mode              = SPI_MODE_MASTER;
+    handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
+    handle->Init.Direction         = SPI_DIRECTION_2LINES;
+    handle->Init.CLKPhase          = SPI_PHASE_1EDGE;
+    handle->Init.CLKPolarity       = SPI_POLARITY_LOW;
+    handle->Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLED;
+    handle->Init.CRCPolynomial     = 7;
+    handle->Init.DataSize          = SPI_DATASIZE_8BIT;
+    handle->Init.FirstBit          = SPI_FIRSTBIT_MSB;
+    handle->Init.TIMode            = SPI_TIMODE_DISABLED;
+
+    init_spi(obj);
+}
+
+void spi_free(spi_t *obj)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    DEBUG_PRINTF("spi_free\r\n");
+
+    __HAL_SPI_DISABLE(handle);
+    HAL_SPI_DeInit(handle);
+
+#if defined SPI1_BASE
+    // Reset SPI and disable clock
+    if (spiobj->spi == SPI_1) {
+        __HAL_RCC_SPI1_FORCE_RESET();
+        __HAL_RCC_SPI1_RELEASE_RESET();
+        __HAL_RCC_SPI1_CLK_DISABLE();
+    }
+#endif
+#if defined SPI2_BASE
+    if (spiobj->spi == SPI_2) {
+        __HAL_RCC_SPI2_FORCE_RESET();
+        __HAL_RCC_SPI2_RELEASE_RESET();
+        __HAL_RCC_SPI2_CLK_DISABLE();
+    }
+#endif
+
+#if defined SPI3_BASE
+    if (spiobj->spi == SPI_3) {
+        __HAL_RCC_SPI3_FORCE_RESET();
+        __HAL_RCC_SPI3_RELEASE_RESET();
+        __HAL_RCC_SPI3_CLK_DISABLE();
+    }
+#endif
+
+#if defined SPI4_BASE
+    if (spiobj->spi == SPI_4) {
+        __HAL_RCC_SPI4_FORCE_RESET();
+        __HAL_RCC_SPI4_RELEASE_RESET();
+        __HAL_RCC_SPI4_CLK_DISABLE();
+    }
+#endif
+
+#if defined SPI5_BASE
+    if (spiobj->spi == SPI_5) {
+        __HAL_RCC_SPI5_FORCE_RESET();
+        __HAL_RCC_SPI5_RELEASE_RESET();
+        __HAL_RCC_SPI5_CLK_DISABLE();
+    }
+#endif
+
+#if defined SPI6_BASE
+    if (spiobj->spi == SPI_6) {
+        __HAL_RCC_SPI6_FORCE_RESET();
+        __HAL_RCC_SPI6_RELEASE_RESET();
+        __HAL_RCC_SPI6_CLK_DISABLE();
+    }
+#endif
+
+    // Configure GPIOs
+    pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    if (handle->Init.NSS != SPI_NSS_SOFT) {
+        pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    }
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave);
+
+    // Save new values
+    handle->Init.DataSize          = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
+
+    switch (mode) {
+        case 0:
+            handle->Init.CLKPolarity = SPI_POLARITY_LOW;
+            handle->Init.CLKPhase = SPI_PHASE_1EDGE;
+            break;
+        case 1:
+            handle->Init.CLKPolarity = SPI_POLARITY_LOW;
+            handle->Init.CLKPhase = SPI_PHASE_2EDGE;
+            break;
+        case 2:
+            handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
+            handle->Init.CLKPhase = SPI_PHASE_1EDGE;
+            break;
+        default:
+            handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
+            handle->Init.CLKPhase = SPI_PHASE_2EDGE;
+            break;
+    }
+
+    if (handle->Init.NSS != SPI_NSS_SOFT) {
+        handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
+    }
+
+    handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
+
+    init_spi(obj);
+}
+
+/*
+ * Only the IP clock input is family dependant so it computed
+ * separately in spi_get_clock_freq
+ */
+extern int spi_get_clock_freq(spi_t *obj);
+
+static const uint16_t baudrate_prescaler_table[] =	{SPI_BAUDRATEPRESCALER_2,
+                                                    SPI_BAUDRATEPRESCALER_4,
+                                                    SPI_BAUDRATEPRESCALER_8,
+                                                    SPI_BAUDRATEPRESCALER_16,
+                                                    SPI_BAUDRATEPRESCALER_32,
+                                                    SPI_BAUDRATEPRESCALER_64,
+                                                    SPI_BAUDRATEPRESCALER_128,
+                                                    SPI_BAUDRATEPRESCALER_256};
+
+void spi_frequency(spi_t *obj, int hz) {
+    struct spi_s *spiobj = SPI_S(obj);
+	int spi_hz = 0;
+	uint8_t prescaler_rank = 0;
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+	/* Get the clock of the peripheral */
+	spi_hz = spi_get_clock_freq(obj);
+
+	/* Define pre-scaler in order to get highest available frequency below requested frequency */
+	while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
+		spi_hz = spi_hz / 2;
+		prescaler_rank++;
+	}
+
+	if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
+		handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank-1];
+	} else {
+		error("Couldn't setup requested SPI frequency");
+	}
+
+    init_spi(obj);
+}
+
+static inline int ssp_readable(spi_t *obj)
+{
+    int status;
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    // Check if data is received
+    status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
+    return status;
+}
+
+static inline int ssp_writeable(spi_t *obj)
+{
+    int status;
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    // Check if data is transmitted
+    status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
+    return status;
+}
+
+static inline void ssp_write(spi_t *obj, int value)
+{
+    SPI_TypeDef *spi = SPI_INST(obj);
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    while (!ssp_writeable(obj));
+
+    //spi->DR = (uint16_t)value;
+    if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
+        // Force 8-bit access to the data register
+        uint8_t *p_spi_dr = 0;
+        p_spi_dr = (uint8_t *) & (spi->DR);
+        *p_spi_dr = (uint8_t)value;
+    } else { // SPI_DATASIZE_16BIT
+        spi->DR = (uint16_t)value;
+    }
+}
+
+static inline int ssp_read(spi_t *obj)
+{
+    SPI_TypeDef *spi = SPI_INST(obj);
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+    while (!ssp_readable(obj));
+    //return (int)spi->DR;
+    if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
+        // Force 8-bit access to the data register
+        uint8_t *p_spi_dr = 0;
+        p_spi_dr = (uint8_t *) & (spi->DR);
+        return (int)(*p_spi_dr);
+    } else {
+        return (int)spi->DR;
+    }
+}
+
+static inline int ssp_busy(spi_t *obj)
+{
+    int status;
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+    status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
+    return status;
+}
+
+int spi_master_write(spi_t *obj, int value)
+{
+    ssp_write(obj, value);
+    return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj)
+{
+    return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
+};
+
+int spi_slave_read(spi_t *obj)
+{
+    SPI_TypeDef *spi = SPI_INST(obj);
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+    while (!ssp_readable(obj));
+    //return (int)spi->DR;
+    if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
+        // Force 8-bit access to the data register
+        uint8_t *p_spi_dr = 0;
+        p_spi_dr = (uint8_t *) & (spi->DR);
+        return (int)(*p_spi_dr);
+    } else {
+        return (int)spi->DR;
+    }
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+    SPI_TypeDef *spi = SPI_INST(obj);
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+    while (!ssp_writeable(obj));
+    //spi->DR = (uint16_t)value;
+    if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
+        // Force 8-bit access to the data register
+        uint8_t *p_spi_dr = 0;
+        p_spi_dr = (uint8_t *) & (spi->DR);
+        *p_spi_dr = (uint8_t)value;
+    } else { // SPI_DATASIZE_16BIT
+        spi->DR = (uint16_t)value;
+    }
+}
+
+int spi_busy(spi_t *obj)
+{
+    return ssp_busy(obj);
+}
+
+#ifdef DEVICE_SPI_ASYNCH
+typedef enum {
+    SPI_TRANSFER_TYPE_NONE = 0,
+    SPI_TRANSFER_TYPE_TX = 1,
+    SPI_TRANSFER_TYPE_RX = 2,
+    SPI_TRANSFER_TYPE_TXRX = 3,
+} transfer_type_t;
+
+
+/// @returns the number of bytes transferred, or `0` if nothing transferred
+static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+    bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
+    // the HAL expects number of transfers instead of number of bytes
+    // so for 16 bit transfer width the count needs to be halved
+    size_t words;
+
+    DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length);
+
+    obj->spi.transfer_type = transfer_type;
+
+    if (is16bit) words = length / 2;
+    else         words = length;
+
+    // enable the interrupt
+    IRQn_Type irq_n = spiobj->spiIRQ;
+    NVIC_ClearPendingIRQ(irq_n);
+    NVIC_DisableIRQ(irq_n);
+    NVIC_SetPriority(irq_n, 1);
+    NVIC_EnableIRQ(irq_n);
+
+    // enable the right hal transfer
+    //static uint16_t sink;
+    int rc = 0;
+    switch(transfer_type) {
+        case SPI_TRANSFER_TYPE_TXRX:
+            rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words);
+            break;
+        case SPI_TRANSFER_TYPE_TX:
+            rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words);
+            break;
+        case SPI_TRANSFER_TYPE_RX:
+            // the receive function also "transmits" the receive buffer so in order
+            // to guarantee that 0xff is on the line, we explicitly memset it here
+            memset(rx, SPI_FILL_WORD, length);
+            rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words);
+            break;
+        default:
+            length = 0;
+    }
+
+    if (rc) {
+        DEBUG_PRINTF("SPI: RC=%u\n", rc);
+        length = 0;
+    }
+
+    return length;
+}
+
+// asynchronous API
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    // TODO: DMA usage is currently ignored
+    (void) hint;
+
+    // check which use-case we have
+    bool use_tx = (tx != NULL && tx_length > 0);
+    bool use_rx = (rx != NULL && rx_length > 0);
+    bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
+
+    // don't do anything, if the buffers aren't valid
+    if (!use_tx && !use_rx)
+        return;
+
+    // copy the buffers to the SPI object
+    obj->tx_buff.buffer = (void *) tx;
+    obj->tx_buff.length = tx_length;
+    obj->tx_buff.pos = 0;
+    obj->tx_buff.width = is16bit ? 16 : 8;
+
+    obj->rx_buff.buffer = rx;
+    obj->rx_buff.length = rx_length;
+    obj->rx_buff.pos = 0;
+    obj->rx_buff.width = obj->tx_buff.width;
+
+    obj->spi.event = event;
+
+    DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length);
+
+    // register the thunking handler
+    IRQn_Type irq_n = spiobj->spiIRQ;
+    NVIC_SetVector(irq_n, (uint32_t)handler);
+
+    // enable the right hal transfer
+    if (use_tx && use_rx) {
+        // we cannot manage different rx / tx sizes, let's use smaller one
+        size_t size = (tx_length < rx_length)? tx_length : rx_length;
+        if(tx_length != rx_length) {
+            DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size);
+            obj->tx_buff.length = size;
+            obj->rx_buff.length = size;
+        }
+        spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size);
+    } else if (use_tx) {
+        spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length);
+    } else if (use_rx) {
+        spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length);
+    }
+}
+
+uint32_t spi_irq_handler_asynch(spi_t *obj)
+{
+    // use the right instance
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &spiobj->handle;
+    int event = 0;
+
+    // call the CubeF4 handler, this will update the handle
+    HAL_SPI_IRQHandler(handle);
+
+    if (HAL_SPI_GetState(handle) == HAL_SPI_STATE_READY) {
+        // When HAL SPI is back to READY state, check if there was an error
+        int error = HAL_SPI_GetError(handle);
+        if(error != HAL_SPI_ERROR_NONE) {
+            // something went wrong and the transfer has definitely completed
+            event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
+
+            if (error & HAL_SPI_ERROR_OVR) {
+                // buffer overrun
+                event |= SPI_EVENT_RX_OVERFLOW;
+            }
+        } else {
+            // else we're done
+            event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
+       }
+    }
+
+    if (event) DEBUG_PRINTF("SPI: Event: 0x%x\n", event);
+
+    return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE));
+}
+
+uint8_t spi_active(spi_t *obj)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+    HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle);
+
+    switch(state) {
+        case HAL_SPI_STATE_RESET:
+        case HAL_SPI_STATE_READY:
+        case HAL_SPI_STATE_ERROR:
+            return 0;
+        default:
+            return 1;
+    }
+}
+
+void spi_abort_asynch(spi_t *obj)
+{
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    // disable interrupt
+    IRQn_Type irq_n = spiobj->spiIRQ;
+    NVIC_ClearPendingIRQ(irq_n);
+    NVIC_DisableIRQ(irq_n);
+
+    // clean-up
+    __HAL_SPI_DISABLE(handle);
+    HAL_SPI_DeInit(handle);
+    HAL_SPI_Init(handle);
+    __HAL_SPI_ENABLE(handle);
+}
+
+#endif //DEVICE_SPI_ASYNCH
+
+#endif

From 0dcd5083f346c02982b94fc4ca362c2ef943659f Mon Sep 17 00:00:00 2001
From: Laurent MEUNIER <laurent.meuniert.com>
Date: Thu, 29 Sep 2016 09:18:37 +0200
Subject: [PATCH 70/89] spi_master_write - rely on HAL

ASYNCH SPI transfer support has been added based on STM HAL services.
To have both ASYNCH and SYNCH work together, we're also moving the
write API to STM HAL instead of direct registers access.
---
 targets/TARGET_STM/stm_spi_api.c | 54 +++++++++-----------------------
 1 file changed, 15 insertions(+), 39 deletions(-)

diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c
index b8b0f79cbac..6153a0aef2c 100644
--- a/targets/TARGET_STM/stm_spi_api.c
+++ b/targets/TARGET_STM/stm_spi_api.c
@@ -333,42 +333,6 @@ static inline int ssp_writeable(spi_t *obj)
     return status;
 }
 
-static inline void ssp_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = SPI_INST(obj);
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
-
-    while (!ssp_writeable(obj));
-
-    //spi->DR = (uint16_t)value;
-    if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        *p_spi_dr = (uint8_t)value;
-    } else { // SPI_DATASIZE_16BIT
-        spi->DR = (uint16_t)value;
-    }
-}
-
-static inline int ssp_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = SPI_INST(obj);
-    struct spi_s *spiobj = SPI_S(obj);
-    SPI_HandleTypeDef *handle = &(spiobj->handle);
-    while (!ssp_readable(obj));
-    //return (int)spi->DR;
-    if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
-        // Force 8-bit access to the data register
-        uint8_t *p_spi_dr = 0;
-        p_spi_dr = (uint8_t *) & (spi->DR);
-        return (int)(*p_spi_dr);
-    } else {
-        return (int)spi->DR;
-    }
-}
-
 static inline int ssp_busy(spi_t *obj)
 {
     int status;
@@ -380,8 +344,21 @@ static inline int ssp_busy(spi_t *obj)
 
 int spi_master_write(spi_t *obj, int value)
 {
-    ssp_write(obj, value);
-    return ssp_read(obj);
+    uint16_t size, Rx, ret;
+    struct spi_s *spiobj = SPI_S(obj);
+    SPI_HandleTypeDef *handle = &(spiobj->handle);
+
+    size = (handle->Init.DataSize == SPI_DATASIZE_16BIT) ? 2 : 1;
+
+    /*  Use 10ms timeout */
+    ret = HAL_SPI_TransmitReceive(handle,(uint8_t*)&value,(uint8_t*)&Rx,size,10);
+
+    if(ret == HAL_OK) {
+        return Rx;
+    } else {
+        DEBUG_PRINTF("SPI inst=0x%8X ERROR in write\r\n", (int)handle->Instance);
+        return -1;
+    }
 }
 
 int spi_slave_receive(spi_t *obj)
@@ -395,7 +372,6 @@ int spi_slave_read(spi_t *obj)
     struct spi_s *spiobj = SPI_S(obj);
     SPI_HandleTypeDef *handle = &(spiobj->handle);
     while (!ssp_readable(obj));
-    //return (int)spi->DR;
     if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
         // Force 8-bit access to the data register
         uint8_t *p_spi_dr = 0;

From 5376654581525211e1ce634ef7d90ceb188c89a0 Mon Sep 17 00:00:00 2001
From: Laurent MEUNIER <laurent.meuniert.com>
Date: Tue, 30 Aug 2016 15:27:24 +0200
Subject: [PATCH 71/89] Enable SPI_ASYNCH on STM32 boards

Now that SPI_ASYNCH is supported on all STM32 based boards,
let's activate the feature.

Using a default SPI QUEUE of size 2 - this can be later modified if this
prives to be to low. (or too high)
---
 targets/targets.json | 84 +++++++++++++++++++++++++++-----------------
 1 file changed, 52 insertions(+), 32 deletions(-)

diff --git a/targets/targets.json b/targets/targets.json
index 4cf2d398999..11143b43eca 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -595,7 +595,8 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0725"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32F030R8"
@@ -605,11 +606,11 @@
         "core": "Cortex-M0",
         "default_toolchain": "uARM",
         "extra_labels": ["STM", "STM32F0", "STM32F031K6"],
-        "macros": ["RTC_LSI=1"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0791"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["RTC_LSI=1", "TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32F031K6"
@@ -619,11 +620,11 @@
         "core": "Cortex-M0",
         "default_toolchain": "uARM",
         "extra_labels": ["STM", "STM32F0", "STM32F042K6"],
-        "macros": ["RTC_LSI=1"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0785"],
-        "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["RTC_LSI=1", "TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32F042K6"
@@ -636,7 +637,8 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0755"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F070RB"
     },
@@ -648,7 +650,8 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0730"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F072RB"
     },
@@ -660,7 +663,8 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0750"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F091RC"
     },
@@ -672,7 +676,8 @@
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "inherits": ["Target"],
         "detect_code": ["0700"],
-        "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F103RB"
     },
@@ -684,7 +689,8 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0835"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "features": ["LWIP"],
         "release_versions": ["2", "5"],
         "device_name" : "STM32F207ZG"
@@ -697,7 +703,8 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0705"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32F302R8"
@@ -707,12 +714,12 @@
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
         "extra_labels": ["STM", "STM32F3", "STM32F303K8"],
-        "macros": ["RTC_LSI=1"],
+        "macros": ["RTC_LSI=1", "TRANSACTION_QUEUE_SIZE_SPI=2"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0775"],
         "default_lib": "small",
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "release_versions": ["2"],
         "device_name": "STM32F303K8"
     },
@@ -724,7 +731,8 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0745"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F303RE"
     },
@@ -736,7 +744,8 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0747"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F303RE"
     },
@@ -748,7 +757,8 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0735"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32F334R8"
@@ -788,7 +798,7 @@
         "inherits": ["Target"],
         "detect_code": ["0740"],
         "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
-        "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F411RE"
     },
@@ -866,9 +876,10 @@
         "extra_labels": ["STM", "STM32F7", "STM32F746", "STM32F746ZG"],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "default_toolchain": "ARM",
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
         "supported_form_factors": ["ARDUINO"],
         "detect_code": ["0816"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"],
         "features": ["LWIP"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F746ZG"
@@ -880,8 +891,9 @@
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "default_toolchain": "ARM",
         "supported_form_factors": ["ARDUINO"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
         "detect_code": ["0818"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"],
         "features": ["LWIP"],
         "release_versions": ["2", "5"],
         "device_name" : "STM32F767ZI"
@@ -957,7 +969,8 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0770"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "CAN", "STDIO_MESSAGES", "TRNG"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "CAN", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"],
         "release_versions": ["2", "5"],
         "device_name" : "STM32L432KC"
     },
@@ -969,7 +982,8 @@
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0765"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"],
         "release_versions": ["2", "5"],
         "device_name": "stm32l476rg"
     },
@@ -994,7 +1008,8 @@
         "extra_labels": ["STM", "STM32F4", "STM32F407", "STM32F407VG"],
         "macros": ["LSI_VALUE=32000"],
         "inherits": ["Target"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "release_versions": ["2"],
         "device_name": "STM32F407VG"
     },
@@ -1004,7 +1019,8 @@
         "default_toolchain": "ARM",
         "extra_labels": ["STM", "STM32F0", "STM32F051", "STM32F051R8"],
         "supported_toolchains": ["GCC_ARM"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "device_name": "STM32F051R8"
     },
     "DISCO_F100RB": {
@@ -1013,7 +1029,8 @@
         "default_toolchain": "ARM",
         "extra_labels": ["STM", "STM32F1", "STM32F100RB"],
         "supported_toolchains": ["GCC_ARM"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "device_name": "STM32F100RB"
     },
     "DISCO_F303VC": {
@@ -1021,9 +1038,9 @@
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
         "extra_labels": ["STM", "STM32F3", "STM32F303", "STM32F303VC"],
-        "macros": ["RTC_LSI=1"],
+        "macros": ["RTC_LSI=1", "TRANSACTION_QUEUE_SIZE_SPI=2"],
         "supported_toolchains": ["GCC_ARM"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "device_name": "STM32F303VC"
     },
     "DISCO_F334C8": {
@@ -1031,10 +1048,10 @@
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
         "extra_labels": ["STM", "STM32F3", "STM32F334C8"],
-        "macros": ["RTC_LSI=1"],
+        "macros": ["RTC_LSI=1", "TRANSACTION_QUEUE_SIZE_SPI=2"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "detect_code": ["0810"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32F334C8"
@@ -1068,7 +1085,7 @@
         "inherits": ["Target"],
         "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
         "detect_code": ["0788"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F469NI"
     },
@@ -1091,7 +1108,8 @@
         "default_toolchain": "ARM",
         "supported_form_factors": ["ARDUINO"],
         "detect_code": ["0815"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"],
         "features": ["LWIP"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F746NG"
@@ -1103,7 +1121,8 @@
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
         "default_toolchain": "ARM",
         "detect_code": ["0817"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "features": ["LWIP"],
         "release_versions": ["2"],
         "device_name": "STM32F769NI"
@@ -1115,7 +1134,8 @@
         "extra_labels": ["STM", "STM32L4", "STM32L476VG"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "detect_code": ["0820"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"],
         "release_versions": ["2", "5"],
         "device_name": "stm32l476vg"
     },

From 6b3d9b24279f8e20bfdc77cee1343f42679e95af Mon Sep 17 00:00:00 2001
From: Laurent MEUNIER <laurent.meuniert.com>
Date: Tue, 30 Aug 2016 15:27:24 +0200
Subject: [PATCH 72/89] SPI Peripheral pin - allow SPI3 to be used

Let's swap default PA_4 pin mapping to SPI_3 otherwise SPI3 cannot be used
---
 .../TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c        | 4 ++--
 .../TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c      | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c
index 056931c0399..f8f4654c527 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c
@@ -196,8 +196,8 @@ const PinMap PinMap_SPI_SCLK[] = {
 };
 
 const PinMap PinMap_SPI_SSEL[] = {
-    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
-//  {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+   //  {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+    {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
     {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
 //  {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
     {PB_1,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c
index dd952ad24f0..0a4fd7d9cd8 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c
@@ -208,8 +208,8 @@ const PinMap PinMap_SPI_SCLK[] = {
 };
 
 const PinMap PinMap_SPI_SSEL[] = {
-    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
-//  {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+//    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+  {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
     {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
 //  {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
     {PB_1,  SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},

From 37f84ca840ce18260aa94cbedd4755cceac50115 Mon Sep 17 00:00:00 2001
From: Laurent MEUNIER <laurent.meunier@st.com>
Date: Tue, 11 Oct 2016 18:55:40 +0200
Subject: [PATCH 73/89] Clean-up style issues

Fix indentation issues, remove useless comments, correct if/else format
---
 targets/TARGET_STM/stm_spi_api.c | 37 ++++++++++++++++----------------
 1 file changed, 19 insertions(+), 18 deletions(-)

diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c
index 6153a0aef2c..4068a4cca35 100644
--- a/targets/TARGET_STM/stm_spi_api.c
+++ b/targets/TARGET_STM/stm_spi_api.c
@@ -289,24 +289,24 @@ static const uint16_t baudrate_prescaler_table[] =	{SPI_BAUDRATEPRESCALER_2,
 
 void spi_frequency(spi_t *obj, int hz) {
     struct spi_s *spiobj = SPI_S(obj);
-	int spi_hz = 0;
-	uint8_t prescaler_rank = 0;
+    int spi_hz = 0;
+    uint8_t prescaler_rank = 0;
     SPI_HandleTypeDef *handle = &(spiobj->handle);
 
-	/* Get the clock of the peripheral */
-	spi_hz = spi_get_clock_freq(obj);
+    /* Get the clock of the peripheral */
+    spi_hz = spi_get_clock_freq(obj);
 
-	/* Define pre-scaler in order to get highest available frequency below requested frequency */
-	while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
-		spi_hz = spi_hz / 2;
-		prescaler_rank++;
-	}
+    /* Define pre-scaler in order to get highest available frequency below requested frequency */
+    while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
+        spi_hz = spi_hz / 2;
+        prescaler_rank++;
+    }
 
-	if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
-		handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank-1];
-	} else {
-		error("Couldn't setup requested SPI frequency");
-	}
+    if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
+        handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank-1];
+    } else {
+        error("Couldn't setup requested SPI frequency");
+    }
 
     init_spi(obj);
 }
@@ -388,7 +388,6 @@ void spi_slave_write(spi_t *obj, int value)
     struct spi_s *spiobj = SPI_S(obj);
     SPI_HandleTypeDef *handle = &(spiobj->handle);
     while (!ssp_writeable(obj));
-    //spi->DR = (uint16_t)value;
     if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
         // Force 8-bit access to the data register
         uint8_t *p_spi_dr = 0;
@@ -427,8 +426,11 @@ static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer
 
     obj->spi.transfer_type = transfer_type;
 
-    if (is16bit) words = length / 2;
-    else         words = length;
+    if (is16bit) {
+        words = length / 2;
+    } else {
+        words = length;
+    }
 
     // enable the interrupt
     IRQn_Type irq_n = spiobj->spiIRQ;
@@ -438,7 +440,6 @@ static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer
     NVIC_EnableIRQ(irq_n);
 
     // enable the right hal transfer
-    //static uint16_t sink;
     int rc = 0;
     switch(transfer_type) {
         case SPI_TRANSFER_TYPE_TXRX:

From 1807983a73d96a59ba2861f60b4f8e786121d5b8 Mon Sep 17 00:00:00 2001
From: Laurent MEUNIER <laurent.meunier@st.com>
Date: Wed, 12 Oct 2016 09:10:35 +0200
Subject: [PATCH 74/89] Update objects definition

STM32F303ZE was introduced in parallel to the changes which consist in
having family wide definitions like device.h file and a common objects
definition.

This target is updated accordingly now to benefit of SPI definitions.
---
 .../TARGET_NUCLEO_F303ZE/device.h             | 54 -------------------
 .../TARGET_NUCLEO_F303ZE/objects.h            | 22 +-------
 2 files changed, 1 insertion(+), 75 deletions(-)
 delete mode 100644 targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device.h

diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device.h
deleted file mode 100644
index bdad16c6f18..00000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device.h
+++ /dev/null
@@ -1,54 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-
-
-
-
-
-
-
-
-
-//=======================================
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-#include "objects.h"
-
-#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h
index f410f62461f..61a56f7c047 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h
@@ -66,37 +66,17 @@ struct dac_s {
     uint32_t channel;
 };
 
-struct serial_s {
-    UARTName uart;
-    int index; // Used by irq
-    uint32_t baudrate;
-    uint32_t databits;
-    uint32_t stopbits;
-    uint32_t parity;
-    PinName pin_tx;
-    PinName pin_rx;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;
 };
 
-struct pwmout_s {
-    PWMName pwm;
-    PinName pin;
-    uint32_t prescaler;
-    uint32_t period;
-    uint32_t pulse;
-    uint32_t channel;
-    uint32_t inverted;
-};
-
 struct can_s {
     CANName can;
     int index;
 };
 
+#include "common_objects.h"
 #include "gpio_object.h"
 
 #ifdef __cplusplus

From ac0caaba9a6f2639c73c6a924ef275c96e4293c5 Mon Sep 17 00:00:00 2001
From: Bartek Szatkowski <bulislaw@linux.com>
Date: Tue, 11 Oct 2016 09:40:09 -0500
Subject: [PATCH 75/89] DNS: Rework DNS query

Don't ask multiple DNS servers in case of successful connection, even if
the response is negative. Make sure the return value is correct.
---
 features/netsocket/nsapi_dns.cpp | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/features/netsocket/nsapi_dns.cpp b/features/netsocket/nsapi_dns.cpp
index de498660210..efeb84f0338 100644
--- a/features/netsocket/nsapi_dns.cpp
+++ b/features/netsocket/nsapi_dns.cpp
@@ -217,7 +217,7 @@ static int nsapi_dns_query_multiple(NetworkStack *stack, const char *host,
         return NSAPI_ERROR_NO_MEMORY;
     }
 
-    int result = NSAPI_ERROR_OK;
+    int result = NSAPI_ERROR_DNS_FAILURE;
 
     // check against each dns server
     for (unsigned i = 0; i < DNS_SERVERS_SIZE; i++) {
@@ -243,11 +243,12 @@ static int nsapi_dns_query_multiple(NetworkStack *stack, const char *host,
         }
 
         const uint8_t *response = packet;
-        if (!dns_scan_response(&response, addr, addr_count)) {
-            result = NSAPI_ERROR_DNS_FAILURE;
-        } else {
-            break;
+        if (dns_scan_response(&response, addr, addr_count) > 0) {
+            result = NSAPI_ERROR_OK;
         }
+
+        /* The DNS response is final, no need to check other servers */
+        break;
     }
 
     // clean up packet

From fa4df0998c5270b4a3087d43ba01c56c905d839d Mon Sep 17 00:00:00 2001
From: Sarah Marsh <Sarah.Marsh@arm.com>
Date: Tue, 11 Oct 2016 18:25:07 +0100
Subject: [PATCH 76/89] NRF52_DK support for IAR exporter

---
 tools/export/iar/iar_definitions.json | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json
index 82169c160bb..641705cb9bd 100644
--- a/tools/export/iar/iar_definitions.json
+++ b/tools/export/iar/iar_definitions.json
@@ -146,5 +146,8 @@
     },
     "STM32F407VG": {
         "OGChipSelectEditMenu": "STM32F407VG\tST STM32F407VG"
+    },
+    "nRF52832_xxAA":{
+        "OGChipSelectEditMenu": "nRF52832-xxAA\tNordicSemi nRF52832-xxAA"
     }
 }

From 0e292ed57b164ec9682900cde8b5a7d42fef483e Mon Sep 17 00:00:00 2001
From: Russ Butler <russ.butler@arm.com>
Date: Tue, 11 Oct 2016 18:03:28 -0500
Subject: [PATCH 77/89] Properly set flags for default_lib = small

Use newlib nano for targets which have the key "default_lib" set to
"small". Also support the legacy key of "default_build".
---
 tools/toolchains/gcc.py | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/tools/toolchains/gcc.py b/tools/toolchains/gcc.py
index 190f7f9f748..f21ce54624b 100644
--- a/tools/toolchains/gcc.py
+++ b/tools/toolchains/gcc.py
@@ -35,6 +35,17 @@ def __init__(self, target,  notify=None, macros=None,
                                extra_verbose=extra_verbose,
                                build_profile=build_profile)
 
+        # Add flags for current size setting
+        default_lib = "std"
+        if hasattr(target, "default_lib"):
+            default_lib = target.default_lib
+        elif hasattr(target, "default_build"): # Legacy
+            default_lib = target.default_build
+
+        if default_lib == "small":
+            self.flags["common"].append("-DMBED_RTOS_SINGLE_THREAD")
+            self.flags["ld"].append("--specs=nano.specs")
+
         if target.core == "Cortex-M0+":
             cpu = "cortex-m0plus"
         elif target.core == "Cortex-M4F":

From 3a33de65778261fa6eac0557434d7a70672fdc34 Mon Sep 17 00:00:00 2001
From: Martin Kojtal <c0170@rocketmail.com>
Date: Wed, 12 Oct 2016 14:24:21 +0100
Subject: [PATCH 78/89] lwip-interface: fix issue #2993

DEVICE_ are passed as command line -D, thus no inclusion is required.
``platform.h`` is C++ header file, should not be pulled in C files
---
 features/FEATURE_LWIP/lwip-interface/emac_lwip.c         | 2 --
 features/FEATURE_LWIP/lwip-interface/emac_stack_lwip.cpp | 2 --
 features/netsocket/emac_stack_mem.h                      | 2 --
 hal/hal/emac_api.h                                       | 3 ---
 4 files changed, 9 deletions(-)

diff --git a/features/FEATURE_LWIP/lwip-interface/emac_lwip.c b/features/FEATURE_LWIP/lwip-interface/emac_lwip.c
index 01f09faf0f9..f79be5d4717 100644
--- a/features/FEATURE_LWIP/lwip-interface/emac_lwip.c
+++ b/features/FEATURE_LWIP/lwip-interface/emac_lwip.c
@@ -14,8 +14,6 @@
  * limitations under the License.
  */
 
-#include "platform.h"
-
 #if DEVICE_EMAC
 
 #include "emac_api.h"
diff --git a/features/FEATURE_LWIP/lwip-interface/emac_stack_lwip.cpp b/features/FEATURE_LWIP/lwip-interface/emac_stack_lwip.cpp
index d543529fd6d..44de56e6ae2 100644
--- a/features/FEATURE_LWIP/lwip-interface/emac_stack_lwip.cpp
+++ b/features/FEATURE_LWIP/lwip-interface/emac_stack_lwip.cpp
@@ -14,8 +14,6 @@
  * limitations under the License.
  */
 
-#include "platform.h"
-
 #if DEVICE_EMAC
 
 #include "emac_stack_mem.h"
diff --git a/features/netsocket/emac_stack_mem.h b/features/netsocket/emac_stack_mem.h
index b407308fd58..1a88bde94d3 100644
--- a/features/netsocket/emac_stack_mem.h
+++ b/features/netsocket/emac_stack_mem.h
@@ -16,8 +16,6 @@
 #ifndef MBED_EMAC_STACK_MEM_H
 #define MBED_EMAC_STACK_MEM_H
 
-#include "platform.h"
-
 #if DEVICE_EMAC
 
 #include <stdint.h>
diff --git a/hal/hal/emac_api.h b/hal/hal/emac_api.h
index bebd56f7072..e5fbd1a9419 100644
--- a/hal/hal/emac_api.h
+++ b/hal/hal/emac_api.h
@@ -17,9 +17,6 @@
 #ifndef MBED_EMAC_API_H
 #define MBED_EMAC_API_H
 
-#include "platform.h"
-
-
 #if DEVICE_EMAC
 
 #include <stdbool.h>

From a5cbb71b988a2e7e8b13feb9c319025dcb42e56c Mon Sep 17 00:00:00 2001
From: jeromecoutant <jerome.coutant@st.com>
Date: Wed, 12 Oct 2016 16:52:26 +0200
Subject: [PATCH 79/89] NUCLEO_F303ZE: Enable all I2C instances

---
 .../TARGET_NUCLEO_F303ZE/PeripheralPins.c          | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralPins.c
index f07f0816243..f5b57f3a868 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralPins.c
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralPins.c
@@ -117,24 +117,24 @@ const PinMap PinMap_DAC[] = {
 //*** I2C ***
 
 const PinMap PinMap_I2C_SDA[] = {
-    //{PA_10, I2C_2   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, //(pin used for usb)
+    {PA_10, I2C_2   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // warning: pin can be used for usb
     //{PA_14, I2C_1   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},// (pin used for stmc)
-   // {PB_5,  I2C_3   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)},// I2C3 not useable with usb , no SCL available.
+    {PB_5,  I2C_3   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)},// warning: I2C3 not useable with usb as no SCL available.
     //{PB_7,  I2C_1   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},//(pin used by LED2)
     {PB_9,  I2C_1   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, //- ARDUINO D14 
-    //{PC_9,  I2C_3   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C3)},
+    {PC_9,  I2C_3   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C3)},
     //{PF_0,  I2C_2   , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},// PF_0 not useable on board , need resistors changes I2C2 not useable
     {NC,    NC,    0}
 };
 
 const PinMap PinMap_I2C_SCL[] = {
-    //{PA_8,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C3)}, //(pin used for usb)
-    //{PA_9,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, //(pin used for usb)
+    {PA_8,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C3)}, // warning: pin can be used for usb
+    {PA_9,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // warning: pin can be used for usb
    // {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
    // {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
     {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, //- ARDUINO D15
-    //{PF_1,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},// I2C2 not useable due to PF_0 not useable
-    //{PF_6,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},// I2C2 not useable due to PF_0 not useable
+    {PF_1,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PF_6,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
     {NC,    NC,    0}
 };
 

From d111b09eb2d36690092ad3fe986528a65605975e Mon Sep 17 00:00:00 2001
From: Christopher Haster <chaster@utexas.edu>
Date: Wed, 12 Oct 2016 17:48:54 -0500
Subject: [PATCH 80/89] callback - Fixed missing workaround for IAR issue with
 type information

Related to commit abba0c2
---
 events/Event.h      | 90 ++++++---------------------------------------
 events/EventQueue.h | 40 ++++++++++----------
 2 files changed, 31 insertions(+), 99 deletions(-)

diff --git a/events/Event.h b/events/Event.h
index 9659192cd48..e9a9161c26f 100644
--- a/events/Event.h
+++ b/events/Event.h
@@ -212,8 +212,8 @@ class Event<void()> {
         new (p) C(*(F*)(e + 1));
         equeue_event_delay(p, e->delay);
         equeue_event_period(p, e->period);
-        equeue_event_dtor(p, &Event::function_dtor<C>);
-        return equeue_post(e->equeue, &Event::function_call<C>, p);
+        equeue_event_dtor(p, &EventQueue::function_dtor<C>);
+        return equeue_post(e->equeue, &EventQueue::function_call<C>, p);
     }
 
     template <typename F>
@@ -221,17 +221,6 @@ class Event<void()> {
         ((F*)(e + 1))->~F();
     }
 
-    // Function attributes
-    template <typename F>
-    static void function_call(void *p) {
-        (*(F*)p)();
-    }
-
-    template <typename F>
-    static void function_dtor(void *p) {
-        ((F*)p)->~F();
-    }
-
 public:
     /** Create an event
      *  @see Event::Event
@@ -616,8 +605,8 @@ class Event<void(A0)> {
         new (p) C(*(F*)(e + 1), a0);
         equeue_event_delay(p, e->delay);
         equeue_event_period(p, e->period);
-        equeue_event_dtor(p, &Event::function_dtor<C>);
-        return equeue_post(e->equeue, &Event::function_call<C>, p);
+        equeue_event_dtor(p, &EventQueue::function_dtor<C>);
+        return equeue_post(e->equeue, &EventQueue::function_call<C>, p);
     }
 
     template <typename F>
@@ -625,17 +614,6 @@ class Event<void(A0)> {
         ((F*)(e + 1))->~F();
     }
 
-    // Function attributes
-    template <typename F>
-    static void function_call(void *p) {
-        (*(F*)p)();
-    }
-
-    template <typename F>
-    static void function_dtor(void *p) {
-        ((F*)p)->~F();
-    }
-
 public:
     /** Create an event
      *  @see Event::Event
@@ -1020,8 +998,8 @@ class Event<void(A0, A1)> {
         new (p) C(*(F*)(e + 1), a0, a1);
         equeue_event_delay(p, e->delay);
         equeue_event_period(p, e->period);
-        equeue_event_dtor(p, &Event::function_dtor<C>);
-        return equeue_post(e->equeue, &Event::function_call<C>, p);
+        equeue_event_dtor(p, &EventQueue::function_dtor<C>);
+        return equeue_post(e->equeue, &EventQueue::function_call<C>, p);
     }
 
     template <typename F>
@@ -1029,17 +1007,6 @@ class Event<void(A0, A1)> {
         ((F*)(e + 1))->~F();
     }
 
-    // Function attributes
-    template <typename F>
-    static void function_call(void *p) {
-        (*(F*)p)();
-    }
-
-    template <typename F>
-    static void function_dtor(void *p) {
-        ((F*)p)->~F();
-    }
-
 public:
     /** Create an event
      *  @see Event::Event
@@ -1424,8 +1391,8 @@ class Event<void(A0, A1, A2)> {
         new (p) C(*(F*)(e + 1), a0, a1, a2);
         equeue_event_delay(p, e->delay);
         equeue_event_period(p, e->period);
-        equeue_event_dtor(p, &Event::function_dtor<C>);
-        return equeue_post(e->equeue, &Event::function_call<C>, p);
+        equeue_event_dtor(p, &EventQueue::function_dtor<C>);
+        return equeue_post(e->equeue, &EventQueue::function_call<C>, p);
     }
 
     template <typename F>
@@ -1433,17 +1400,6 @@ class Event<void(A0, A1, A2)> {
         ((F*)(e + 1))->~F();
     }
 
-    // Function attributes
-    template <typename F>
-    static void function_call(void *p) {
-        (*(F*)p)();
-    }
-
-    template <typename F>
-    static void function_dtor(void *p) {
-        ((F*)p)->~F();
-    }
-
 public:
     /** Create an event
      *  @see Event::Event
@@ -1828,8 +1784,8 @@ class Event<void(A0, A1, A2, A3)> {
         new (p) C(*(F*)(e + 1), a0, a1, a2, a3);
         equeue_event_delay(p, e->delay);
         equeue_event_period(p, e->period);
-        equeue_event_dtor(p, &Event::function_dtor<C>);
-        return equeue_post(e->equeue, &Event::function_call<C>, p);
+        equeue_event_dtor(p, &EventQueue::function_dtor<C>);
+        return equeue_post(e->equeue, &EventQueue::function_call<C>, p);
     }
 
     template <typename F>
@@ -1837,17 +1793,6 @@ class Event<void(A0, A1, A2, A3)> {
         ((F*)(e + 1))->~F();
     }
 
-    // Function attributes
-    template <typename F>
-    static void function_call(void *p) {
-        (*(F*)p)();
-    }
-
-    template <typename F>
-    static void function_dtor(void *p) {
-        ((F*)p)->~F();
-    }
-
 public:
     /** Create an event
      *  @see Event::Event
@@ -2232,8 +2177,8 @@ class Event<void(A0, A1, A2, A3, A4)> {
         new (p) C(*(F*)(e + 1), a0, a1, a2, a3, a4);
         equeue_event_delay(p, e->delay);
         equeue_event_period(p, e->period);
-        equeue_event_dtor(p, &Event::function_dtor<C>);
-        return equeue_post(e->equeue, &Event::function_call<C>, p);
+        equeue_event_dtor(p, &EventQueue::function_dtor<C>);
+        return equeue_post(e->equeue, &EventQueue::function_call<C>, p);
     }
 
     template <typename F>
@@ -2241,17 +2186,6 @@ class Event<void(A0, A1, A2, A3, A4)> {
         ((F*)(e + 1))->~F();
     }
 
-    // Function attributes
-    template <typename F>
-    static void function_call(void *p) {
-        (*(F*)p)();
-    }
-
-    template <typename F>
-    static void function_dtor(void *p) {
-        ((F*)p)->~F();
-    }
-
 public:
     /** Create an event
      *  @see Event::Event
diff --git a/events/EventQueue.h b/events/EventQueue.h
index 9ae9c1ce2a0..cf1ae224880 100644
--- a/events/EventQueue.h
+++ b/events/EventQueue.h
@@ -13,6 +13,7 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
+
 #ifndef EVENT_QUEUE_H
 #define EVENT_QUEUE_H
 
@@ -173,19 +174,14 @@ class EventQueue {
      */
     template <typename F>
     int call(F f) {
-        struct local {
-            static void call(void *p) { (*static_cast<F*>(p))(); }
-            static void dtor(void *p) { static_cast<F*>(p)->~F(); }
-        };
-
         void *p = equeue_alloc(&_equeue, sizeof(F));
         if (!p) {
             return 0;
         }
 
         F *e = new (p) F(f);
-        equeue_event_dtor(e, &local::dtor);
-        return equeue_post(&_equeue, &local::call, e);
+        equeue_event_dtor(e, &EventQueue::function_dtor<F>);
+        return equeue_post(&_equeue, &EventQueue::function_call<F>, e);
     }
 
     /** Calls an event on the queue
@@ -437,11 +433,6 @@ class EventQueue {
      */
     template <typename F>
     int call_in(int ms, F f) {
-        struct local {
-            static void call(void *p) { (*static_cast<F*>(p))(); }
-            static void dtor(void *p) { static_cast<F*>(p)->~F(); }
-        };
-
         void *p = equeue_alloc(&_equeue, sizeof(F));
         if (!p) {
             return 0;
@@ -449,8 +440,8 @@ class EventQueue {
 
         F *e = new (p) F(f);
         equeue_event_delay(e, ms);
-        equeue_event_dtor(e, &local::dtor);
-        return equeue_post(&_equeue, &local::call, e);
+        equeue_event_dtor(e, &EventQueue::function_dtor<F>);
+        return equeue_post(&_equeue, &EventQueue::function_call<F>, e);
     }
 
     /** Calls an event on the queue after a specified delay
@@ -702,11 +693,6 @@ class EventQueue {
      */
     template <typename F>
     int call_every(int ms, F f) {
-        struct local {
-            static void call(void *p) { (*static_cast<F*>(p))(); }
-            static void dtor(void *p) { static_cast<F*>(p)->~F(); }
-        };
-
         void *p = equeue_alloc(&_equeue, sizeof(F));
         if (!p) {
             return 0;
@@ -715,8 +701,8 @@ class EventQueue {
         F *e = new (p) F(f);
         equeue_event_delay(e, ms);
         equeue_event_period(e, ms);
-        equeue_event_dtor(e, &local::dtor);
-        return equeue_post(&_equeue, &local::call, e);
+        equeue_event_dtor(e, &EventQueue::function_dtor<F>);
+        return equeue_post(&_equeue, &EventQueue::function_call<F>, e);
     }
 
     /** Calls an event on the queue periodically
@@ -2044,6 +2030,18 @@ class EventQueue {
     struct equeue _equeue;
     mbed::Callback<void(int)> _update;
 
+    // Function attributes
+    template <typename F>
+    static void function_call(void *p) {
+        (*(F*)p)();
+    }
+
+    template <typename F>
+    static void function_dtor(void *p) {
+        ((F*)p)->~F();
+    }
+
+    // Context structures
     template <typename F>
     struct context00 {
         F f;

From 1b61b2cc0ceca69a58cff1ccad38098039e90186 Mon Sep 17 00:00:00 2001
From: Brian Daniels <brianddaniels@gmail.com>
Date: Thu, 13 Oct 2016 12:43:27 -0500
Subject: [PATCH 81/89] Remove shared spi_s struct from XDOT_L151CC

---
 .../TARGET_STM32L1/TARGET_XDOT_L151CC/objects.h    | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/objects.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/objects.h
index 7a0d5f1489f..84754ae7488 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/objects.h
@@ -65,20 +65,6 @@ struct dac_s {
     PinName pin;
 };
 
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
 struct i2c_s {
     I2CName  i2c;
     uint32_t slave;

From 283a82f23e919dc706459560d0142e18c45031cf Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Mon, 10 Oct 2016 18:31:45 +0200
Subject: [PATCH 82/89] ADD NEW TARGET : NUCLEO_F439ZI, based on existing
 NUCLEO_F429ZI

---
 .../stm32f4_eth_init.c                        |    0
 .../PeripheralNames.h                         |    0
 .../PeripheralPins.c                          |    0
 .../PinNames.h                                |    0
 .../PortNames.h                               |    0
 .../TARGET_NUCLEO_F429ZI/device/stm32f429xx.h |    0
 .../TARGET_NUCLEO_F429ZI/device/stm32f4xx.h   |    0
 .../TARGET_NUCLEO_F439ZI/device/stm32f439xx.h | 9308 +++++++++++++++++
 .../TARGET_NUCLEO_F439ZI/device/stm32f4xx.h   |  264 +
 .../TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s |    0
 .../TOOLCHAIN_ARM_MICRO/stm32f429xx.sct       |    0
 .../TOOLCHAIN_ARM_STD/startup_stm32f429xx.s   |    0
 .../device/TOOLCHAIN_ARM_STD/stm32f429xx.sct  |    0
 .../device/TOOLCHAIN_ARM_STD/sys.cpp          |    0
 .../device/TOOLCHAIN_GCC_ARM/STM32F429ZI.ld   |    0
 .../TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S   |    0
 .../TOOLCHAIN_IAR/startup_stm32f429xx.S       |    0
 .../TOOLCHAIN_IAR/stm32f429xx_flash.icf       |    0
 .../device/cmsis.h                            |    0
 .../device/cmsis_nvic.c                       |    0
 .../device/cmsis_nvic.h                       |    0
 .../device/hal_tick.c                         |    0
 .../device/hal_tick.h                         |    0
 .../device/stm32f4xx_hal_conf.h               |    0
 .../device/system_stm32f4xx.c                 |    0
 .../device/system_stm32f4xx.h                 |    0
 .../objects.h                                 |    0
 targets/TARGET_STM/mbed_rtx.h                 |    2 +-
 targets/targets.json                          |   17 +-
 29 files changed, 9589 insertions(+), 2 deletions(-)
 rename features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/stm32f4_eth_init.c (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/PeripheralNames.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/PeripheralPins.c (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/PinNames.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/PortNames.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{ => TARGET_F429_F439}/TARGET_NUCLEO_F429ZI/device/stm32f429xx.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{ => TARGET_F429_F439}/TARGET_NUCLEO_F429ZI/device/stm32f4xx.h (100%)
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/TARGET_NUCLEO_F439ZI/device/stm32f439xx.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/TARGET_NUCLEO_F439ZI/device/stm32f4xx.h
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/TOOLCHAIN_ARM_MICRO/stm32f429xx.sct (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.s (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/TOOLCHAIN_ARM_STD/sys.cpp (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/TOOLCHAIN_GCC_ARM/STM32F429ZI.ld (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/TOOLCHAIN_IAR/startup_stm32f429xx.S (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/cmsis.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/cmsis_nvic.c (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/cmsis_nvic.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/hal_tick.c (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/hal_tick.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/stm32f4xx_hal_conf.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/system_stm32f4xx.c (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/device/system_stm32f4xx.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F4/{TARGET_NUCLEO_F429ZI => TARGET_F429_F439}/objects.h (100%)

diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_init.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/stm32f4_eth_init.c
similarity index 100%
rename from features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_init.c
rename to features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/stm32f4_eth_init.c
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/PeripheralNames.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PeripheralNames.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/PeripheralNames.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/PeripheralPins.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PeripheralPins.c
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/PeripheralPins.c
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/PinNames.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PinNames.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/PinNames.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PortNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/PortNames.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/PortNames.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/PortNames.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/stm32f429xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/TARGET_NUCLEO_F429ZI/device/stm32f429xx.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/stm32f429xx.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/TARGET_NUCLEO_F429ZI/device/stm32f429xx.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/stm32f4xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/TARGET_NUCLEO_F429ZI/device/stm32f4xx.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/stm32f4xx.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/TARGET_NUCLEO_F429ZI/device/stm32f4xx.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/TARGET_NUCLEO_F439ZI/device/stm32f439xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/TARGET_NUCLEO_F439ZI/device/stm32f439xx.h
new file mode 100644
index 00000000000..37f22294967
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/TARGET_NUCLEO_F439ZI/device/stm32f439xx.h
@@ -0,0 +1,9308 @@
+/**
+  ******************************************************************************
+  * @file    stm32f439xx.h
+  * @author  MCD Application Team
+  * @version V2.5.0
+  * @date    22-April-2016
+  * @brief   CMSIS STM32F439xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - peripherals registers declarations and bits definition
+  *           - Macros to access peripheral�s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32f439xx
+  * @{
+  */
+    
+#ifndef __STM32F439xx_H
+#define __STM32F439xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
+  */
+#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#endif /* __FPU_PRESENT */
+
+/**
+  * @}
+  */
+   
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
+  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                              */
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                        */
+  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
+  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
+  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
+                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+  
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+  
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+  
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
+  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
+  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
+  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/** 
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+  uint32_t      RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+  uint32_t      RESERVED1[2];
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+  uint32_t      RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+  uint32_t      RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+  uint32_t      RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+  uint32_t      RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+  uint32_t      RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+  uint32_t      RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+  __IO uint32_t RESERVED8;
+  __IO uint32_t PTPTSSR;
+  uint32_t      RESERVED9[565];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+  __IO uint32_t DMARSWTR;
+  uint32_t      RESERVED10[8];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
+  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
+  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
+  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
+  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
+  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
+  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
+  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
+} FMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank2
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
+  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
+  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank4
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
+  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
+  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
+  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
+  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
+} FMC_Bank4_TypeDef; 
+
+/** 
+  * @brief Flexible Memory Controller Bank5_6
+  */
+  
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
+} FMC_Bank5_6_TypeDef; 
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;    /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/** 
+  * @brief System configuration controller
+  */
+  
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
+  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
+  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
+  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
+  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
+  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
+  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
+  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
+  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
+  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/** 
+  * @brief LCD-TFT Display Controller
+  */
+  
+typedef struct
+{
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                       Address offset: 0x48 */
+} LTDC_TypeDef;  
+
+/** 
+  * @brief LCD-TFT Display layer x Controller
+  */
+  
+typedef struct
+{  
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
+  uint32_t      RESERVED0[2];  /*!< Reserved */
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
+  uint32_t      RESERVED1[3];  /*!< Reserved */
+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
+  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
+  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
+  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
+  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
+  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
+  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
+  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
+  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
+  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
+  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
+  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
+  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
+  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
+  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
+  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
+
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
+  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
+  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
+  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
+  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
+  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
+  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
+  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
+  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
+  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
+  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
+  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
+  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
+  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
+  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
+  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
+  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
+  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
+  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
+  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
+  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
+  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
+} RTC_TypeDef;
+
+/** 
+  * @brief Serial Audio Interface
+  */
+  
+typedef struct
+{
+  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+} SPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+} TIM_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
+  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
+  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
+  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
+  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
+  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** 
+  * @brief Crypto Processor
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
+  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/** 
+  * @brief HASH
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
+  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/** 
+  * @brief HASH_DIGEST
+  */
+  
+typedef struct 
+{
+  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */ 
+} HASH_DIGEST_TypeDef;
+
+/** 
+  * @brief RNG
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+ 
+/** 
+  * @brief __USB_OTG_Core_register
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;      /*!<  USB_OTG Control and Status Register    000h */
+  __IO uint32_t GOTGINT;      /*!<  USB_OTG Interrupt Register             004h */
+  __IO uint32_t GAHBCFG;      /*!<  Core AHB Configuration Register        008h */
+  __IO uint32_t GUSBCFG;      /*!<  Core USB Configuration Register        00Ch */
+  __IO uint32_t GRSTCTL;      /*!<  Core Reset Register                    010h */
+  __IO uint32_t GINTSTS;      /*!<  Core Interrupt Register                014h */
+  __IO uint32_t GINTMSK;      /*!<  Core Interrupt Mask Register           018h */
+  __IO uint32_t GRXSTSR;      /*!<  Receive Sts Q Read Register            01Ch */
+  __IO uint32_t GRXSTSP;      /*!<  Receive Sts Q Read & POP Register      020h */
+  __IO uint32_t GRXFSIZ;      /* Receive FIFO Size Register                024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register 028h*/
+  __IO uint32_t HNPTXSTS;     /*!<  Non Periodic Tx FIFO/Queue Sts reg     02Ch */
+  uint32_t Reserved30[2];     /* Reserved                           030h*/
+  __IO uint32_t GCCFG;        /* General Purpose IO Register        038h*/
+  __IO uint32_t CID;          /* User ID Register                   03Ch*/
+  uint32_t  Reserved40[48];   /* Reserved                      040h-0FFh*/
+  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg     100h*/
+  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+/** 
+  * @brief __device_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DCFG;         /* dev Configuration Register   800h*/
+  __IO uint32_t DCTL;         /* dev Control Register         804h*/
+  __IO uint32_t DSTS;         /* dev Status Register (RO)     808h*/
+  uint32_t Reserved0C;           /* Reserved                     80Ch*/
+  __IO uint32_t DIEPMSK;   /* dev IN Endpoint Mask         810h*/
+  __IO uint32_t DOEPMSK;  /* dev OUT Endpoint Mask        814h*/
+  __IO uint32_t DAINT;     /* dev All Endpoints Itr Reg    818h*/
+  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask   81Ch*/
+  uint32_t  Reserved20;          /* Reserved                     820h*/
+  uint32_t Reserved9;       /* Reserved                     824h*/
+  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
+  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
+  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
+  __IO uint32_t DIEPEMPMSK; /* dev empty msk             834h*/
+  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
+  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
+  uint32_t Reserved40;      /* dedicated EP mask           840h*/
+  __IO uint32_t DINEP1MSK;  /* dedicated EP mask           844h*/
+  uint32_t  Reserved44[15];      /* Reserved                 844-87Ch*/
+  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk            884h*/   
+}
+USB_OTG_DeviceTypeDef;
+
+
+/** 
+  * @brief __IN_Endpoint-Specific_Register
+  */
+typedef struct 
+{
+  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;             /* Reserved                       900h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;             /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
+  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+  uint32_t Reserved18;             /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/** 
+  * @brief __OUT_Endpoint-Specific_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
+  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/** 
+  * @brief __Host_Mode_Register_Structures
+  */
+typedef struct 
+{
+  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
+  __IO uint32_t HFIR;      /* Host Frame Interval Register   404h*/
+  __IO uint32_t HFNUM;         /* Host Frame Nbr/Frame Remaining 408h*/
+  uint32_t Reserved40C;                   /* Reserved                       40Ch*/
+  __IO uint32_t HPTXSTS;   /* Host Periodic Tx FIFO/ Queue Status 410h*/
+  __IO uint32_t HAINT;   /* Host All Channels Interrupt Register 414h*/
+  __IO uint32_t HAINTMSK;   /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+/** 
+  * @brief __Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;
+  __IO uint32_t HCSPLT;
+  __IO uint32_t HCINT;
+  __IO uint32_t HCINTMSK;
+  __IO uint32_t HCTSIZ;
+  __IO uint32_t HCDMA;
+  uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+/**
+  * @}
+  */
+    
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region                         */
+#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
+#define SRAM3_BASE            0x20020000U /*!< SRAM3(64 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                             */
+#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                              */
+#define SRAM3_BB_BASE         0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region                              */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                                */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
+#define FLASH_END             0x081FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
+#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U) 
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
+#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
+#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000U)
+#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400U)
+#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710U)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
+#define FMC_Bank2_3_R_BASE    (FMC_R_BASE + 0x0060U)
+#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0U)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE               0x40040000U
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
+
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
+#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH                ((HASH_TypeDef *) HASH_BASE)
+#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3         ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion */
+#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      0xFFFFU            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      0xFFFFU            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      0xFFFFU            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      0xFFFFU            /*!<Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
+
+/*******************  Bit definition for ADC_CSR register  ********************/
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 DMA overrun  flag */
+
+/* Legacy defines */
+#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
+#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
+#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
+
+/*******************  Bit definition for ADC_CDR register  ********************/
+#define  ADC_CDR_DATA1                      0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset */
+#define  CAN_MCR_DBF                         0x00010000U        /*!<bxCAN Debug freeze */
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define  CAN_MSR_INAK                        0x0001U            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        0x0002U            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        0x0004U            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        0x0008U            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       0x0010U            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         0x0100U            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         0x0200U            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        0x0400U            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          0x0800U            /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code */
+
+#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
+
+#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define  CAN_RF0R_FMP0                       0x03U               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      0x08U               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      0x10U               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      0x20U               /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define  CAN_RF1R_FMP1                       0x03U               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      0x08U               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      0x10U               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      0x20U               /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error warning interrupt enable */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error passive interrupt enable */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-off interrupt enable */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last error code interrupt enable */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error interrupt enable */
+
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
+
+#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
+
+#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1 */
+#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
+#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
+#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
+#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
+#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2 */
+#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
+#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
+#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
+#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
+#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
+#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define  CAN_FMR_FINIT                       0x01U               /*!<Filter Init Mode */
+#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define  CAN_FM1R_FBM                        0x0FFFFFFFU        /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       0x00000001U        /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       0x00000002U        /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       0x00000004U        /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       0x00000008U        /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       0x00000010U        /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       0x00000020U        /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       0x00000040U        /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       0x00000080U        /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       0x00000100U        /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       0x00000200U        /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      0x00000400U        /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      0x00000800U        /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      0x00001000U        /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      0x00002000U        /*!<Filter Init Mode bit 13 */
+#define  CAN_FM1R_FBM14                      0x00004000U        /*!<Filter Init Mode bit 14 */
+#define  CAN_FM1R_FBM15                      0x00008000U        /*!<Filter Init Mode bit 15 */
+#define  CAN_FM1R_FBM16                      0x00010000U        /*!<Filter Init Mode bit 16 */
+#define  CAN_FM1R_FBM17                      0x00020000U        /*!<Filter Init Mode bit 17 */
+#define  CAN_FM1R_FBM18                      0x00040000U        /*!<Filter Init Mode bit 18 */
+#define  CAN_FM1R_FBM19                      0x00080000U        /*!<Filter Init Mode bit 19 */
+#define  CAN_FM1R_FBM20                      0x00100000U        /*!<Filter Init Mode bit 20 */
+#define  CAN_FM1R_FBM21                      0x00200000U        /*!<Filter Init Mode bit 21 */
+#define  CAN_FM1R_FBM22                      0x00400000U        /*!<Filter Init Mode bit 22 */
+#define  CAN_FM1R_FBM23                      0x00800000U        /*!<Filter Init Mode bit 23 */
+#define  CAN_FM1R_FBM24                      0x01000000U        /*!<Filter Init Mode bit 24 */
+#define  CAN_FM1R_FBM25                      0x02000000U        /*!<Filter Init Mode bit 25 */
+#define  CAN_FM1R_FBM26                      0x04000000U        /*!<Filter Init Mode bit 26 */
+#define  CAN_FM1R_FBM27                      0x08000000U        /*!<Filter Init Mode bit 27 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define  CAN_FS1R_FSC                        0x0FFFFFFFU        /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
+#define  CAN_FS1R_FSC14                      0x00004000U        /*!<Filter Scale Configuration bit 14 */
+#define  CAN_FS1R_FSC15                      0x00008000U        /*!<Filter Scale Configuration bit 15 */
+#define  CAN_FS1R_FSC16                      0x00010000U        /*!<Filter Scale Configuration bit 16 */
+#define  CAN_FS1R_FSC17                      0x00020000U        /*!<Filter Scale Configuration bit 17 */
+#define  CAN_FS1R_FSC18                      0x00040000U        /*!<Filter Scale Configuration bit 18 */
+#define  CAN_FS1R_FSC19                      0x00080000U        /*!<Filter Scale Configuration bit 19 */
+#define  CAN_FS1R_FSC20                      0x00100000U        /*!<Filter Scale Configuration bit 20 */
+#define  CAN_FS1R_FSC21                      0x00200000U        /*!<Filter Scale Configuration bit 21 */
+#define  CAN_FS1R_FSC22                      0x00400000U        /*!<Filter Scale Configuration bit 22 */
+#define  CAN_FS1R_FSC23                      0x00800000U        /*!<Filter Scale Configuration bit 23 */
+#define  CAN_FS1R_FSC24                      0x01000000U        /*!<Filter Scale Configuration bit 24 */
+#define  CAN_FS1R_FSC25                      0x02000000U        /*!<Filter Scale Configuration bit 25 */
+#define  CAN_FS1R_FSC26                      0x04000000U        /*!<Filter Scale Configuration bit 26 */
+#define  CAN_FS1R_FSC27                      0x08000000U        /*!<Filter Scale Configuration bit 27 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define  CAN_FFA1R_FFA                        0x0FFFFFFFU        /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                       0x00000001U        /*!<Filter FIFO Assignment bit 0 */
+#define  CAN_FFA1R_FFA1                       0x00000002U        /*!<Filter FIFO Assignment bit 1 */
+#define  CAN_FFA1R_FFA2                       0x00000004U        /*!<Filter FIFO Assignment bit 2 */
+#define  CAN_FFA1R_FFA3                       0x00000008U        /*!<Filter FIFO Assignment bit 3 */
+#define  CAN_FFA1R_FFA4                       0x00000010U        /*!<Filter FIFO Assignment bit 4 */
+#define  CAN_FFA1R_FFA5                       0x00000020U        /*!<Filter FIFO Assignment bit 5 */
+#define  CAN_FFA1R_FFA6                       0x00000040U        /*!<Filter FIFO Assignment bit 6 */
+#define  CAN_FFA1R_FFA7                       0x00000080U        /*!<Filter FIFO Assignment bit 7 */
+#define  CAN_FFA1R_FFA8                       0x00000100U        /*!<Filter FIFO Assignment bit 8 */
+#define  CAN_FFA1R_FFA9                       0x00000200U        /*!<Filter FIFO Assignment bit 9 */
+#define  CAN_FFA1R_FFA10                      0x00000400U        /*!<Filter FIFO Assignment bit 10 */
+#define  CAN_FFA1R_FFA11                      0x00000800U        /*!<Filter FIFO Assignment bit 11 */
+#define  CAN_FFA1R_FFA12                      0x00001000U        /*!<Filter FIFO Assignment bit 12 */
+#define  CAN_FFA1R_FFA13                      0x00002000U        /*!<Filter FIFO Assignment bit 13 */
+#define  CAN_FFA1R_FFA14                      0x00004000U        /*!<Filter FIFO Assignment bit 14 */
+#define  CAN_FFA1R_FFA15                      0x00008000U        /*!<Filter FIFO Assignment bit 15 */
+#define  CAN_FFA1R_FFA16                      0x00010000U        /*!<Filter FIFO Assignment bit 16 */
+#define  CAN_FFA1R_FFA17                      0x00020000U        /*!<Filter FIFO Assignment bit 17 */
+#define  CAN_FFA1R_FFA18                      0x00040000U        /*!<Filter FIFO Assignment bit 18 */
+#define  CAN_FFA1R_FFA19                      0x00080000U        /*!<Filter FIFO Assignment bit 19 */
+#define  CAN_FFA1R_FFA20                      0x00100000U        /*!<Filter FIFO Assignment bit 20 */
+#define  CAN_FFA1R_FFA21                      0x00200000U        /*!<Filter FIFO Assignment bit 21 */
+#define  CAN_FFA1R_FFA22                      0x00400000U        /*!<Filter FIFO Assignment bit 22 */
+#define  CAN_FFA1R_FFA23                      0x00800000U        /*!<Filter FIFO Assignment bit 23 */
+#define  CAN_FFA1R_FFA24                      0x01000000U        /*!<Filter FIFO Assignment bit 24 */
+#define  CAN_FFA1R_FFA25                      0x02000000U        /*!<Filter FIFO Assignment bit 25 */
+#define  CAN_FFA1R_FFA26                      0x04000000U        /*!<Filter FIFO Assignment bit 26 */
+#define  CAN_FFA1R_FFA27                      0x08000000U        /*!<Filter FIFO Assignment bit 27 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define  CAN_FA1R_FACT                        0x0FFFFFFFU        /*!<Filter Active */
+#define  CAN_FA1R_FACT0                       0x00000001U        /*!<Filter Active bit 0 */
+#define  CAN_FA1R_FACT1                       0x00000002U        /*!<Filter Active bit 1 */
+#define  CAN_FA1R_FACT2                       0x00000004U        /*!<Filter Active bit 2 */
+#define  CAN_FA1R_FACT3                       0x00000008U        /*!<Filter Active bit 3 */
+#define  CAN_FA1R_FACT4                       0x00000010U        /*!<Filter Active bit 4 */
+#define  CAN_FA1R_FACT5                       0x00000020U        /*!<Filter Active bit 5 */
+#define  CAN_FA1R_FACT6                       0x00000040U        /*!<Filter Active bit 6 */
+#define  CAN_FA1R_FACT7                       0x00000080U        /*!<Filter Active bit 7 */
+#define  CAN_FA1R_FACT8                       0x00000100U        /*!<Filter Active bit 8 */
+#define  CAN_FA1R_FACT9                       0x00000200U        /*!<Filter Active bit 9 */
+#define  CAN_FA1R_FACT10                      0x00000400U        /*!<Filter Active bit 10 */
+#define  CAN_FA1R_FACT11                      0x00000800U        /*!<Filter Active bit 11 */
+#define  CAN_FA1R_FACT12                      0x00001000U        /*!<Filter Active bit 12 */
+#define  CAN_FA1R_FACT13                      0x00002000U        /*!<Filter Active bit 13 */
+#define  CAN_FA1R_FACT14                      0x00004000U        /*!<Filter Active bit 14 */
+#define  CAN_FA1R_FACT15                      0x00008000U        /*!<Filter Active bit 15 */
+#define  CAN_FA1R_FACT16                      0x00010000U        /*!<Filter Active bit 16 */
+#define  CAN_FA1R_FACT17                      0x00020000U        /*!<Filter Active bit 17 */
+#define  CAN_FA1R_FACT18                      0x00040000U        /*!<Filter Active bit 18 */
+#define  CAN_FA1R_FACT19                      0x00080000U        /*!<Filter Active bit 19 */
+#define  CAN_FA1R_FACT20                      0x00100000U        /*!<Filter Active bit 20 */
+#define  CAN_FA1R_FACT21                      0x00200000U        /*!<Filter Active bit 21 */
+#define  CAN_FA1R_FACT22                      0x00400000U        /*!<Filter Active bit 22 */
+#define  CAN_FA1R_FACT23                      0x00800000U        /*!<Filter Active bit 23 */
+#define  CAN_FA1R_FACT24                      0x01000000U        /*!<Filter Active bit 24 */
+#define  CAN_FA1R_FACT25                      0x02000000U        /*!<Filter Active bit 25 */
+#define  CAN_FA1R_FACT26                      0x04000000U        /*!<Filter Active bit 26 */
+#define  CAN_FA1R_FACT27                      0x08000000U        /*!<Filter Active bit 27 */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           0xFFFFFFFFU /*!< Data register bits */
+
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         0xFFU        /*!< General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        0x01U        /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Crypto Processor                                */
+/*                                                                            */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register  ********************/
+#define CRYP_CR_ALGODIR                      0x00000004U
+
+#define CRYP_CR_ALGOMODE                     0x00080038U
+#define CRYP_CR_ALGOMODE_0                   0x00000008U
+#define CRYP_CR_ALGOMODE_1                   0x00000010U
+#define CRYP_CR_ALGOMODE_2                   0x00000020U
+#define CRYP_CR_ALGOMODE_TDES_ECB            0x00000000U
+#define CRYP_CR_ALGOMODE_TDES_CBC            0x00000008U
+#define CRYP_CR_ALGOMODE_DES_ECB             0x00000010U
+#define CRYP_CR_ALGOMODE_DES_CBC             0x00000018U
+#define CRYP_CR_ALGOMODE_AES_ECB             0x00000020U
+#define CRYP_CR_ALGOMODE_AES_CBC             0x00000028U
+#define CRYP_CR_ALGOMODE_AES_CTR             0x00000030U
+#define CRYP_CR_ALGOMODE_AES_KEY             0x00000038U
+
+#define CRYP_CR_DATATYPE                     0x000000C0U
+#define CRYP_CR_DATATYPE_0                   0x00000040U
+#define CRYP_CR_DATATYPE_1                   0x00000080U
+#define CRYP_CR_KEYSIZE                      0x00000300U
+#define CRYP_CR_KEYSIZE_0                    0x00000100U
+#define CRYP_CR_KEYSIZE_1                    0x00000200U
+#define CRYP_CR_FFLUSH                       0x00004000U
+#define CRYP_CR_CRYPEN                       0x00008000U
+
+#define CRYP_CR_GCM_CCMPH                    0x00030000U
+#define CRYP_CR_GCM_CCMPH_0                  0x00010000U
+#define CRYP_CR_GCM_CCMPH_1                  0x00020000U
+#define CRYP_CR_ALGOMODE_3                   0x00080000U 
+
+/****************** Bits definition for CRYP_SR register  *********************/
+#define CRYP_SR_IFEM                         0x00000001U
+#define CRYP_SR_IFNF                         0x00000002U
+#define CRYP_SR_OFNE                         0x00000004U
+#define CRYP_SR_OFFU                         0x00000008U
+#define CRYP_SR_BUSY                         0x00000010U
+/****************** Bits definition for CRYP_DMACR register  ******************/
+#define CRYP_DMACR_DIEN                      0x00000001U
+#define CRYP_DMACR_DOEN                      0x00000002U
+/*****************  Bits definition for CRYP_IMSCR register  ******************/
+#define CRYP_IMSCR_INIM                      0x00000001U
+#define CRYP_IMSCR_OUTIM                     0x00000002U
+/****************** Bits definition for CRYP_RISR register  *******************/
+#define CRYP_RISR_OUTRIS                     0x00000001U
+#define CRYP_RISR_INRIS                      0x00000002U
+/****************** Bits definition for CRYP_MISR register  *******************/
+#define CRYP_MISR_INMIS                      0x00000001U
+#define CRYP_MISR_OUTMIS                     0x00000002U
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable*/
+#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable */
+
+#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE                      0x00000001U
+#define DCMI_CR_CM                           0x00000002U
+#define DCMI_CR_CROP                         0x00000004U
+#define DCMI_CR_JPEG                         0x00000008U
+#define DCMI_CR_ESS                          0x00000010U
+#define DCMI_CR_PCKPOL                       0x00000020U
+#define DCMI_CR_HSPOL                        0x00000040U
+#define DCMI_CR_VSPOL                        0x00000080U
+#define DCMI_CR_FCRC_0                       0x00000100U
+#define DCMI_CR_FCRC_1                       0x00000200U
+#define DCMI_CR_EDM_0                        0x00000400U
+#define DCMI_CR_EDM_1                        0x00000800U
+#define DCMI_CR_CRE                          0x00001000U
+#define DCMI_CR_ENABLE                       0x00004000U
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC                        0x00000001U
+#define DCMI_SR_VSYNC                        0x00000002U
+#define DCMI_SR_FNE                          0x00000004U
+
+/********************  Bits definition for DCMI_RIS register  ****************/
+#define DCMI_RIS_FRAME_RIS                   0x00000001U
+#define DCMI_RIS_OVR_RIS                     0x00000002U
+#define DCMI_RIS_ERR_RIS                     0x00000004U
+#define DCMI_RIS_VSYNC_RIS                   0x00000008U
+#define DCMI_RIS_LINE_RIS                    0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE                    0x00000001U
+#define DCMI_IER_OVR_IE                      0x00000002U
+#define DCMI_IER_ERR_IE                      0x00000004U
+#define DCMI_IER_VSYNC_IE                    0x00000008U
+#define DCMI_IER_LINE_IE                     0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS                   0x00000001U
+#define DCMI_MIS_OVR_MIS                     0x00000002U
+#define DCMI_MIS_ERR_MIS                     0x00000004U
+#define DCMI_MIS_VSYNC_MIS                   0x00000008U
+#define DCMI_MIS_LINE_MIS                    0x00000010U
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC                   0x00000001U
+#define DCMI_ICR_OVR_ISC                     0x00000002U
+#define DCMI_ICR_ERR_ISC                     0x00000004U
+#define DCMI_ICR_VSYNC_ISC                   0x00000008U
+#define DCMI_ICR_LINE_ISC                    0x00000010U
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC                        0x000000FFU
+#define DCMI_ESCR_LSC                        0x0000FF00U
+#define DCMI_ESCR_LEC                        0x00FF0000U
+#define DCMI_ESCR_FEC                        0xFF000000U
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU                        0x000000FFU
+#define DCMI_ESUR_LSU                        0x0000FF00U
+#define DCMI_ESUR_LEU                        0x00FF0000U
+#define DCMI_ESUR_FEU                        0xFF000000U
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
+#define DCMI_CWSTRT_VST                      0x1FFF0000U
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
+#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0                        0x000000FFU
+#define DCMI_DR_BYTE1                        0x0000FF00U
+#define DCMI_DR_BYTE2                        0x00FF0000U
+#define DCMI_DR_BYTE3                        0xFF000000U
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK                         0x00100000U
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
+
+/********************  Bits definition for DMA_SxFCR register  ****************/ 
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
+
+/********************  Bits definition for DMA_LISR register  *****************/ 
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
+
+/********************  Bits definition for DMA_HISR register  *****************/ 
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
+
+/********************  Bits definition for DMA_LIFCR register  ****************/ 
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/ 
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer */
+#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer */
+#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer */
+#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0 */
+#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+
+#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
+#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
+#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
+#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
+#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
+#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
+#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
+#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
+#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
+#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
+#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
+#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
+#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
+#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
+#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
+#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
+#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
+#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
+
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+                                                                     
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
+#define FLASH_ACR_LATENCY_8WS                0x00000008U
+#define FLASH_ACR_LATENCY_9WS                0x00000009U
+#define FLASH_ACR_LATENCY_10WS               0x0000000AU
+#define FLASH_ACR_LATENCY_11WS               0x0000000BU
+#define FLASH_ACR_LATENCY_12WS               0x0000000CU
+#define FLASH_ACR_LATENCY_13WS               0x0000000DU
+#define FLASH_ACR_LATENCY_14WS               0x0000000EU
+#define FLASH_ACR_LATENCY_15WS               0x0000000FU
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ICEN                       0x00000200U
+#define FLASH_ACR_DCEN                       0x00000400U
+#define FLASH_ACR_ICRST                      0x00000800U
+#define FLASH_ACR_DCRST                      0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS              0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS              0x40023C03U
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_SOP                         0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_PGSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
+#define FLASH_CR_MER1                        FLASH_CR_MER
+#define FLASH_CR_SNB                         0x000000F8U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_SNB_4                       0x00000080U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_MER2                        0x00008000U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_LOCK                        0x80000000U
+
+/*******************  Bits definition for FLASH_OPTCR register  ***************/
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
+#define FLASH_OPTCR_BFB2                    0x00000010U
+#define FLASH_OPTCR_WDG_SW                  0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_nWRP_8                  0x01000000U
+#define FLASH_OPTCR_nWRP_9                  0x02000000U
+#define FLASH_OPTCR_nWRP_10                 0x04000000U
+#define FLASH_OPTCR_nWRP_11                 0x08000000U
+#define FLASH_OPTCR_DB1M                    0x40000000U 
+#define FLASH_OPTCR_SPRMOD                  0x80000000U 
+                                             
+/******************  Bits definition for FLASH_OPTCR1 register  ***************/
+#define FLASH_OPTCR1_nWRP                    0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0                  0x00010000U
+#define FLASH_OPTCR1_nWRP_1                  0x00020000U
+#define FLASH_OPTCR1_nWRP_2                  0x00040000U
+#define FLASH_OPTCR1_nWRP_3                  0x00080000U
+#define FLASH_OPTCR1_nWRP_4                  0x00100000U
+#define FLASH_OPTCR1_nWRP_5                  0x00200000U
+#define FLASH_OPTCR1_nWRP_6                  0x00400000U
+#define FLASH_OPTCR1_nWRP_7                  0x00800000U
+#define FLASH_OPTCR1_nWRP_8                  0x01000000U
+#define FLASH_OPTCR1_nWRP_9                  0x02000000U
+#define FLASH_OPTCR1_nWRP_10                 0x04000000U
+#define FLASH_OPTCR1_nWRP_11                 0x08000000U
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
+
+#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
+
+#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
+
+#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
+
+/******************  Bit definition for FMC_BCR2 register  *******************/
+#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
+
+#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
+
+#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
+
+#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR3 register  *******************/
+#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
+
+#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
+
+#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
+
+#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR4 register  *******************/
+#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
+
+#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
+
+#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
+
+#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size */
+#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTR1 register  ******************/
+#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
+
+#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
+
+#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
+
+#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
+
+#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
+
+#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
+
+#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BTR2 register  *******************/
+#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
+
+#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
+
+#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
+
+#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
+
+#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
+
+#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
+
+#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
+
+/*******************  Bit definition for FMC_BTR3 register  *******************/
+#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
+
+#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
+
+#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
+
+#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
+
+#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
+
+#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
+
+#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BTR4 register  *******************/
+#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
+
+#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
+
+#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
+
+#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
+
+#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
+
+#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
+
+#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR1 register  ******************/
+#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
+
+#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
+
+#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
+
+#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+
+#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR2 register  ******************/
+#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
+
+#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
+
+#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
+
+#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+
+#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR3 register  ******************/
+#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
+
+#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
+
+#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
+
+#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+
+#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR4 register  ******************/
+#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
+
+#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
+
+#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
+
+#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+
+#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_PCR2 register  *******************/
+#define  FMC_PCR2_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR2_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR2_PTYP                      0x00000008U        /*!<Memory type                               */
+
+#define  FMC_PCR2_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR2_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR2_PWID_1                    0x00000020U        /*!<Bit 1 */
+
+#define  FMC_PCR2_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
+
+#define  FMC_PCR2_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR2_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR2_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR2_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR2_TCLR_3                    0x00001000U        /*!<Bit 3 */
+
+#define  FMC_PCR2_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR2_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR2_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR2_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR2_TAR_3                     0x00010000U        /*!<Bit 3 */
+
+#define  FMC_PCR2_ECCPS                     0x000E0000U        /*!<ECCPS[1:0] bits (ECC page size)           */
+#define  FMC_PCR2_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR2_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR2_ECCPS_2                   0x00080000U        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_PCR3 register  *******************/
+#define  FMC_PCR3_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR3_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR3_PTYP                      0x00000008U        /*!<Memory type                               */
+
+#define  FMC_PCR3_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR3_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR3_PWID_1                    0x00000020U        /*!<Bit 1 */
+
+#define  FMC_PCR3_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
+
+#define  FMC_PCR3_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR3_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR3_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR3_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR3_TCLR_3                    0x00001000U        /*!<Bit 3 */
+
+#define  FMC_PCR3_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR3_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR3_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR3_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR3_TAR_3                     0x00010000U        /*!<Bit 3 */
+
+#define  FMC_PCR3_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
+#define  FMC_PCR3_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR3_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR3_ECCPS_2                   0x00080000U        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_PCR4 register  *******************/
+#define  FMC_PCR4_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR4_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR4_PTYP                      0x00000008U        /*!<Memory type                               */
+
+#define  FMC_PCR4_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR4_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR4_PWID_1                    0x00000020U        /*!<Bit 1 */
+
+#define  FMC_PCR4_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
+
+#define  FMC_PCR4_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR4_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR4_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR4_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR4_TCLR_3                    0x00001000U        /*!<Bit 3 */
+
+#define  FMC_PCR4_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR4_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR4_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR4_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR4_TAR_3                     0x00010000U        /*!<Bit 3 */
+
+#define  FMC_PCR4_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
+#define  FMC_PCR4_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR4_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR4_ECCPS_2                   0x00080000U        /*!<Bit 2 */
+
+/*******************  Bit definition for FMC_SR2 register  *******************/
+#define  FMC_SR2_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR2_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FMC_SR2_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR2_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR2_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR2_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR2_FEMPT                      0x40U               /*!<FIFO empty                                  */
+
+/*******************  Bit definition for FMC_SR3 register  *******************/
+#define  FMC_SR3_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR3_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FMC_SR3_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR3_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR3_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR3_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR3_FEMPT                      0x40U               /*!<FIFO empty                                  */
+
+/*******************  Bit definition for FMC_SR4 register  *******************/
+#define  FMC_SR4_IRS                        0x01U               /*!<Interrupt Rising Edge status                */
+#define  FMC_SR4_ILS                        0x02U               /*!<Interrupt Level status                      */
+#define  FMC_SR4_IFS                        0x04U               /*!<Interrupt Falling Edge status               */
+#define  FMC_SR4_IREN                       0x08U               /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR4_ILEN                       0x10U               /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR4_IFEN                       0x20U               /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR4_FEMPT                      0x40U               /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM2 register  ******************/
+#define  FMC_PMEM2_MEMSET2                  0x000000FFU        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FMC_PMEM2_MEMSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMSET2_7                0x00000080U        /*!<Bit 7 */
+
+#define  FMC_PMEM2_MEMWAIT2                 0x0000FF00U        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FMC_PMEM2_MEMWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMWAIT2_7               0x00008000U        /*!<Bit 7 */
+
+#define  FMC_PMEM2_MEMHOLD2                 0x00FF0000U        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FMC_PMEM2_MEMHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMHOLD2_7               0x00800000U        /*!<Bit 7 */
+
+#define  FMC_PMEM2_MEMHIZ2                  0xFF000000U        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FMC_PMEM2_MEMHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM2_MEMHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM2_MEMHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM2_MEMHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM2_MEMHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM2_MEMHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM2_MEMHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM2_MEMHIZ2_7                0x80000000U        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PMEM3 register  ******************/
+#define  FMC_PMEM3_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FMC_PMEM3_MEMSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMSET3_7                0x00000080U        /*!<Bit 7 */
+
+#define  FMC_PMEM3_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FMC_PMEM3_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
+
+#define  FMC_PMEM3_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FMC_PMEM3_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
+
+#define  FMC_PMEM3_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FMC_PMEM3_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM3_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM3_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM3_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM3_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM3_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM3_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM3_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PMEM4 register  ******************/
+#define  FMC_PMEM4_MEMSET4                  0x000000FFU        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define  FMC_PMEM4_MEMSET4_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMSET4_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMSET4_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMSET4_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMSET4_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMSET4_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMSET4_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMSET4_7                0x00000080U        /*!<Bit 7 */
+
+#define  FMC_PMEM4_MEMWAIT4                 0x0000FF00U        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define  FMC_PMEM4_MEMWAIT4_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMWAIT4_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMWAIT4_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMWAIT4_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMWAIT4_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMWAIT4_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMWAIT4_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMWAIT4_7               0x00008000U        /*!<Bit 7 */
+
+#define  FMC_PMEM4_MEMHOLD4                 0x00FF0000U        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define  FMC_PMEM4_MEMHOLD4_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMHOLD4_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMHOLD4_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMHOLD4_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMHOLD4_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMHOLD4_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMHOLD4_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMHOLD4_7               0x00800000U        /*!<Bit 7 */
+
+#define  FMC_PMEM4_MEMHIZ4                  0xFF000000U        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define  FMC_PMEM4_MEMHIZ4_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM4_MEMHIZ4_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM4_MEMHIZ4_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM4_MEMHIZ4_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM4_MEMHIZ4_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM4_MEMHIZ4_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM4_MEMHIZ4_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM4_MEMHIZ4_7                0x80000000U        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PATT2 register  ******************/
+#define  FMC_PATT2_ATTSET2                  0x000000FFU        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FMC_PATT2_ATTSET2_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT2_ATTSET2_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT2_ATTSET2_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT2_ATTSET2_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT2_ATTSET2_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT2_ATTSET2_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT2_ATTSET2_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT2_ATTSET2_7                0x00000080U        /*!<Bit 7 */
+
+#define  FMC_PATT2_ATTWAIT2                 0x0000FF00U        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FMC_PATT2_ATTWAIT2_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT2_ATTWAIT2_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT2_ATTWAIT2_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT2_ATTWAIT2_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT2_ATTWAIT2_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT2_ATTWAIT2_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT2_ATTWAIT2_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT2_ATTWAIT2_7               0x00008000U        /*!<Bit 7 */
+
+#define  FMC_PATT2_ATTHOLD2                 0x00FF0000U        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FMC_PATT2_ATTHOLD2_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT2_ATTHOLD2_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT2_ATTHOLD2_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT2_ATTHOLD2_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT2_ATTHOLD2_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT2_ATTHOLD2_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT2_ATTHOLD2_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT2_ATTHOLD2_7               0x00800000U        /*!<Bit 7 */
+
+#define  FMC_PATT2_ATTHIZ2                  0xFF000000U        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FMC_PATT2_ATTHIZ2_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT2_ATTHIZ2_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT2_ATTHIZ2_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT2_ATTHIZ2_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT2_ATTHIZ2_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT2_ATTHIZ2_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT2_ATTHIZ2_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT2_ATTHIZ2_7                0x80000000U        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PATT3 register  ******************/
+#define  FMC_PATT3_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FMC_PATT3_ATTSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT3_ATTSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT3_ATTSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT3_ATTSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT3_ATTSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT3_ATTSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT3_ATTSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT3_ATTSET3_7                0x00000080U        /*!<Bit 7 */
+
+#define  FMC_PATT3_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FMC_PATT3_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT3_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT3_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT3_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT3_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT3_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT3_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT3_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
+
+#define  FMC_PATT3_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FMC_PATT3_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT3_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT3_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT3_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT3_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT3_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT3_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT3_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
+
+#define  FMC_PATT3_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FMC_PATT3_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT3_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT3_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT3_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT3_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT3_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT3_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT3_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PATT4 register  ******************/
+#define  FMC_PATT4_ATTSET4                  0x000000FFU        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define  FMC_PATT4_ATTSET4_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT4_ATTSET4_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT4_ATTSET4_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT4_ATTSET4_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT4_ATTSET4_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT4_ATTSET4_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT4_ATTSET4_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT4_ATTSET4_7                0x00000080U        /*!<Bit 7 */
+
+#define  FMC_PATT4_ATTWAIT4                 0x0000FF00U        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define  FMC_PATT4_ATTWAIT4_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT4_ATTWAIT4_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT4_ATTWAIT4_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT4_ATTWAIT4_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT4_ATTWAIT4_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT4_ATTWAIT4_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT4_ATTWAIT4_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT4_ATTWAIT4_7               0x00008000U        /*!<Bit 7 */
+
+#define  FMC_PATT4_ATTHOLD4                 0x00FF0000U        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define  FMC_PATT4_ATTHOLD4_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT4_ATTHOLD4_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT4_ATTHOLD4_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT4_ATTHOLD4_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT4_ATTHOLD4_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT4_ATTHOLD4_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT4_ATTHOLD4_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT4_ATTHOLD4_7               0x00800000U        /*!<Bit 7 */
+
+#define  FMC_PATT4_ATTHIZ4                  0xFF000000U        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define  FMC_PATT4_ATTHIZ4_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT4_ATTHIZ4_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT4_ATTHIZ4_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT4_ATTHIZ4_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT4_ATTHIZ4_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT4_ATTHIZ4_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT4_ATTHIZ4_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT4_ATTHIZ4_7                0x80000000U        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PIO4 register  *******************/
+#define  FMC_PIO4_IOSET4                    0x000000FFU        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define  FMC_PIO4_IOSET4_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_PIO4_IOSET4_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_PIO4_IOSET4_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_PIO4_IOSET4_3                  0x00000008U        /*!<Bit 3 */
+#define  FMC_PIO4_IOSET4_4                  0x00000010U        /*!<Bit 4 */
+#define  FMC_PIO4_IOSET4_5                  0x00000020U        /*!<Bit 5 */
+#define  FMC_PIO4_IOSET4_6                  0x00000040U        /*!<Bit 6 */
+#define  FMC_PIO4_IOSET4_7                  0x00000080U        /*!<Bit 7 */
+
+#define  FMC_PIO4_IOWAIT4                   0x0000FF00U        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define  FMC_PIO4_IOWAIT4_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_PIO4_IOWAIT4_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_PIO4_IOWAIT4_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_PIO4_IOWAIT4_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_PIO4_IOWAIT4_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_PIO4_IOWAIT4_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_PIO4_IOWAIT4_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_PIO4_IOWAIT4_7                 0x00008000U        /*!<Bit 7 */
+
+#define  FMC_PIO4_IOHOLD4                   0x00FF0000U        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define  FMC_PIO4_IOHOLD4_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_PIO4_IOHOLD4_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_PIO4_IOHOLD4_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_PIO4_IOHOLD4_3                 0x00080000U        /*!<Bit 3 */
+#define  FMC_PIO4_IOHOLD4_4                 0x00100000U        /*!<Bit 4 */
+#define  FMC_PIO4_IOHOLD4_5                 0x00200000U        /*!<Bit 5 */
+#define  FMC_PIO4_IOHOLD4_6                 0x00400000U        /*!<Bit 6 */
+#define  FMC_PIO4_IOHOLD4_7                 0x00800000U        /*!<Bit 7 */
+
+#define  FMC_PIO4_IOHIZ4                    0xFF000000U        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define  FMC_PIO4_IOHIZ4_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_PIO4_IOHIZ4_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_PIO4_IOHIZ4_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_PIO4_IOHIZ4_3                  0x08000000U        /*!<Bit 3 */
+#define  FMC_PIO4_IOHIZ4_4                  0x10000000U        /*!<Bit 4 */
+#define  FMC_PIO4_IOHIZ4_5                  0x20000000U        /*!<Bit 5 */
+#define  FMC_PIO4_IOHIZ4_6                  0x40000000U        /*!<Bit 6 */
+#define  FMC_PIO4_IOHIZ4_7                  0x80000000U        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_ECCR2 register  ******************/
+#define  FMC_ECCR2_ECC2                     0xFFFFFFFFU        /*!<ECC result */
+
+/******************  Bit definition for FMC_ECCR3 register  ******************/
+#define  FMC_ECCR3_ECC3                     0xFFFFFFFFU        /*!<ECC result */
+
+/******************  Bit definition for FMC_SDCR1 register  ******************/
+#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
+
+#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
+
+#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
+
+#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
+
+#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
+
+#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
+
+#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
+#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
+
+#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
+
+#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
+#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_SDCR2 register  ******************/
+#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
+
+#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
+
+#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
+
+#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
+
+#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
+
+#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
+
+#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
+
+#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
+
+#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
+#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_SDTR1 register  ******************/
+#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
+                                            
+#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
+
+#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
+
+#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
+
+#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
+
+#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
+
+#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_SDTR2 register  ******************/
+#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
+                                            
+#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
+
+#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
+
+#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
+
+#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
+
+#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
+
+#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_SDCMR register  ******************/
+#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
+#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDCMR_MODE_2                   0x00000004U        /*!<Bit 2 */
+                                            
+#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
+
+#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
+
+#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
+#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
+#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
+#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
+
+#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
+
+/******************  Bit definition for FMC_SDRTR register  ******************/
+#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
+
+#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ******************/
+#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
+
+#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
+
+#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
+#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
+
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
+
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
+
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
+
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
+
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
+
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
+
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
+
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
+
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
+
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
+
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
+
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
+
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
+
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
+
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
+
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
+
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
+
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
+
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
+
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
+
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
+
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
+
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
+
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
+
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    HASH                                    */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for HASH_CR register  ********************/
+#define HASH_CR_INIT                         0x00000004U
+#define HASH_CR_DMAE                         0x00000008U
+#define HASH_CR_DATATYPE                     0x00000030U
+#define HASH_CR_DATATYPE_0                   0x00000010U
+#define HASH_CR_DATATYPE_1                   0x00000020U
+#define HASH_CR_MODE                         0x00000040U
+#define HASH_CR_ALGO                         0x00040080U
+#define HASH_CR_ALGO_0                       0x00000080U
+#define HASH_CR_ALGO_1                       0x00040000U
+#define HASH_CR_NBW                          0x00000F00U
+#define HASH_CR_NBW_0                        0x00000100U
+#define HASH_CR_NBW_1                        0x00000200U
+#define HASH_CR_NBW_2                        0x00000400U
+#define HASH_CR_NBW_3                        0x00000800U
+#define HASH_CR_DINNE                        0x00001000U
+#define HASH_CR_MDMAT                        0x00002000U
+#define HASH_CR_LKEY                         0x00010000U
+
+/******************  Bits definition for HASH_STR register  *******************/
+#define HASH_STR_NBLW                        0x0000001FU
+#define HASH_STR_NBLW_0                      0x00000001U
+#define HASH_STR_NBLW_1                      0x00000002U
+#define HASH_STR_NBLW_2                      0x00000004U
+#define HASH_STR_NBLW_3                      0x00000008U
+#define HASH_STR_NBLW_4                      0x00000010U
+#define HASH_STR_DCAL                        0x00000100U
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW                         HASH_STR_NBLW
+#define HASH_STR_NBW_0                       HASH_STR_NBLW_0
+#define HASH_STR_NBW_1                       HASH_STR_NBLW_1
+#define HASH_STR_NBW_2                       HASH_STR_NBLW_2
+#define HASH_STR_NBW_3                       HASH_STR_NBLW_3
+#define HASH_STR_NBW_4                       HASH_STR_NBLW_4
+
+/******************  Bits definition for HASH_IMR register  *******************/
+#define HASH_IMR_DINIE                       0x00000001U
+#define HASH_IMR_DCIE                        0x00000002U
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM                       HASH_IMR_DINIE
+#define HASH_IMR_DCIM                        HASH_IMR_DCIE
+
+/******************  Bits definition for HASH_SR register  ********************/
+#define HASH_SR_DINIS                        0x00000001U
+#define HASH_SR_DCIS                         0x00000002U
+#define HASH_SR_DMAS                         0x00000004U
+#define HASH_SR_BUSY                         0x00000008U
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  ********************/
+#define  I2C_CR1_PE                          0x00000001U     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       0x00000002U     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     0x00000008U     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       0x00000010U     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       0x00000020U     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        0x00000040U     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   0x00000080U     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       0x00000100U     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        0x00000200U     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         0x00000400U     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         0x00000800U     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         0x00001000U     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       0x00002000U     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       0x00008000U     /*!<Software Reset                                */
+
+/*******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_FREQ                        0x0000003FU     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      0x00000001U     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      0x00000002U     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      0x00000004U     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      0x00000008U     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      0x00000010U     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      0x00000020U     /*!<Bit 5 */
+
+#define  I2C_CR2_ITERREN                     0x00000100U     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     0x00000200U     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     0x00000400U     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       0x00000800U     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        0x00001000U     /*!<DMA Last Transfer       */
+
+/*******************  Bit definition for I2C_OAR1 register  *******************/
+#define  I2C_OAR1_ADD1_7                     0x000000FEU     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     0x00000300U     /*!<Interface Address */
+
+#define  I2C_OAR1_ADD0                       0x00000001U     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       0x00000002U     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       0x00000004U     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       0x00000008U     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       0x00000010U     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       0x00000020U     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       0x00000040U     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       0x00000080U     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       0x00000100U     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       0x00000200U     /*!<Bit 9 */
+
+#define  I2C_OAR1_ADDMODE                    0x00008000U     /*!<Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define  I2C_OAR2_ENDUAL                     0x00000001U        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       0x000000FEU        /*!<Interface address           */
+
+/********************  Bit definition for I2C_DR register  ********************/
+#define  I2C_DR_DR                           0x000000FFU        /*!<8-bit Data Register         */
+
+/*******************  Bit definition for I2C_SR1 register  ********************/
+#define  I2C_SR1_SB                          0x00000001U     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        0x00000002U     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         0x00000004U     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       0x00000008U     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       0x00000010U     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        0x00000040U     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         0x00000080U     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        0x00000100U     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        0x00000200U     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          0x00000400U     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         0x00000800U     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      0x00001000U     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     0x00004000U     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    0x00008000U     /*!<SMBus Alert                                     */
+
+/*******************  Bit definition for I2C_SR2 register  ********************/
+#define  I2C_SR2_MSL                         0x00000001U     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        0x00000002U     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         0x00000004U     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     0x00000010U     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  0x00000020U     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     0x00000040U     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       0x00000080U     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         0x0000FF00U     /*!<Packet Error Checking Register            */
+
+/*******************  Bit definition for I2C_CCR register  ********************/
+#define  I2C_CCR_CCR                         0x00000FFFU     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        0x00004000U     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          0x00008000U     /*!<I2C Master Mode Selection                                  */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define  I2C_TRISE_TRISE                     0x0000003FU     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************  Bit definition for I2C_FLTR register  *******************/
+#define  I2C_FLTR_DNF                        0x0000000FU     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      0x00000010U     /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         0x01U               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         0x02U               /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for LTDC_SSCR register  *****************/
+
+#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
+
+/********************  Bit definition for LTDC_BPCR register  *****************/
+
+#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
+
+/********************  Bit definition for LTDC_AWCR register  *****************/
+
+#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
+
+/********************  Bit definition for LTDC_TWCR register  *****************/
+
+#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
+
+/********************  Bit definition for LTDC_GCR register  ******************/
+
+#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width */
+#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width */
+#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width */
+#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable */
+#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
+
+/* Legacy defines */
+#define LTDC_GCR_DTEN                       LTDC_GCR_DEN
+
+/********************  Bit definition for LTDC_SRCR register  *****************/
+
+#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload */
+#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
+
+/********************  Bit definition for LTDC_BCCR register  *****************/
+
+#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
+#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value */
+
+/********************  Bit definition for LTDC_IER register  ******************/
+
+#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
+
+/********************  Bit definition for LTDC_ISR register  ******************/
+
+#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_ICR register  ******************/
+
+#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_LIPCR register  ****************/
+
+#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
+
+/********************  Bit definition for LTDC_CPSR register  *****************/
+
+#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
+
+/********************  Bit definition for LTDC_CDSR register  *****************/
+
+#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
+
+/********************  Bit definition for LTDC_LxCR register  *****************/
+
+#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
+
+/********************  Bit definition for LTDC_LxWHPCR register  **************/
+
+#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position */
+
+/********************  Bit definition for LTDC_LxWVPCR register  **************/
+
+#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position */
+
+/********************  Bit definition for LTDC_LxCKCR register  ***************/
+
+#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value */
+
+/********************  Bit definition for LTDC_LxPFCR register  ***************/
+
+#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
+
+/********************  Bit definition for LTDC_LxCACR register  ***************/
+
+#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
+
+/********************  Bit definition for LTDC_LxDCCR register  ***************/
+
+#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
+                                
+/********************  Bit definition for LTDC_LxBFCR register  ***************/
+
+#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
+
+/********************  Bit definition for LTDC_LxCFBAR register  **************/
+
+#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
+
+/********************  Bit definition for LTDC_LxCFBLR register  **************/
+
+#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
+
+/********************  Bit definition for LTDC_LxCFBLNR register  *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
+
+/********************  Bit definition for LTDC_LxCLUTWR register  *************/
+
+#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value */
+#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         0x00000004U     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
+
+#define  PWR_CR_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        0x00000080U     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
+#define  PWR_CR_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       0x00000400U     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
+#define  PWR_CR_MRLVDS                       0x00000800U     /*!< Main regulator Low Voltage Scaling in Stop mode            */
+#define  PWR_CR_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
+#define  PWR_CR_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        0x00008000U     /*!< Bit 1 */
+#define  PWR_CR_ODEN                         0x00010000U     /*!< Over Drive enable                   */
+#define  PWR_CR_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
+#define  PWR_CR_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
+#define  PWR_CR_UDEN_0                       0x00040000U     /*!< Bit 0                               */
+#define  PWR_CR_UDEN_1                       0x00080000U     /*!< Bit 1                               */
+
+/* Legacy define */
+#define  PWR_CR_PMODE                        PWR_CR_VOS
+#define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode          */
+#define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode               */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         0x00000001U     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        0x00000100U     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
+#define  PWR_CSR_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
+#define  PWR_CSR_UDSWRDY                     0x000C0000U     /*!< Under Drive ready                                */
+
+/* Legacy define */
+#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
+
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U/*!<Bit 4 */
+
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U/*!<Bit 7 */
+
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
+#define  RCC_CR_PLLSAION                     0x10000000U
+#define  RCC_CR_PLLSAIRDY                    0x20000000U
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
+
+#define  RCC_PLLCFGR_PLLN                     0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                   0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                   0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                   0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                   0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                   0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                   0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                   0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                   0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                   0x00004000U
+
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
+
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
+
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
+
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
+
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
+
+/*!< MCO1 configuration */
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
+
+#define  RCC_CFGR_I2SSRC                     0x00800000U
+
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
+
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
+
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
+
+/********************  Bit definition for RCC_CIR register  *******************/
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
+#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
+#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
+#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
+#define  RCC_CIR_CSSC                        0x00800000U
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
+#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
+#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
+#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
+#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
+#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
+#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
+#define  RCC_AHB2RSTR_CRYPRST                0x00000010U
+#define  RCC_AHB2RSTR_HASHRST                0x00000020U
+ /* maintained for legacy purpose */
+ #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
+#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+#define  RCC_AHB3RSTR_FMCRST                0x00000001U
+
+/********************  Bit definition for RCC_APB1RSTR register  **************/
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_TIM6RST                0x00000010U
+#define  RCC_APB1RSTR_TIM7RST                0x00000020U
+#define  RCC_APB1RSTR_TIM12RST               0x00000040U
+#define  RCC_APB1RSTR_TIM13RST               0x00000080U
+#define  RCC_APB1RSTR_TIM14RST               0x00000100U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_USART3RST              0x00040000U
+#define  RCC_APB1RSTR_UART4RST               0x00080000U
+#define  RCC_APB1RSTR_UART5RST               0x00100000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_CAN1RST                0x02000000U
+#define  RCC_APB1RSTR_CAN2RST                0x04000000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
+#define  RCC_APB1RSTR_DACRST                 0x20000000U
+#define  RCC_APB1RSTR_UART7RST               0x40000000U
+#define  RCC_APB1RSTR_UART8RST               0x80000000U
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_TIM8RST                0x00000002U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDIORST                0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
+#define  RCC_APB2RSTR_SPI5RST                0x00100000U
+#define  RCC_APB2RSTR_SPI6RST                0x00200000U
+#define  RCC_APB2RSTR_SAI1RST                0x00400000U
+#define  RCC_APB2RSTR_LTDCRST                0x04000000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
+#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
+#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
+#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
+
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_CCMDATARAMEN            0x00100000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
+#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
+
+#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
+#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
+#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
+#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
+#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
+#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
+#define  RCC_AHB2ENR_CRYPEN                  0x00000010U
+#define  RCC_AHB2ENR_HASHEN                  0x00000020U
+#define  RCC_AHB2ENR_RNGEN                   0x00000040U
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+#define  RCC_AHB3ENR_FMCEN                  0x00000001U
+
+/********************  Bit definition for RCC_APB1ENR register  ***************/
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_TIM6EN                  0x00000010U
+#define  RCC_APB1ENR_TIM7EN                  0x00000020U
+#define  RCC_APB1ENR_TIM12EN                 0x00000040U
+#define  RCC_APB1ENR_TIM13EN                 0x00000080U
+#define  RCC_APB1ENR_TIM14EN                 0x00000100U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_USART3EN                0x00040000U
+#define  RCC_APB1ENR_UART4EN                 0x00080000U
+#define  RCC_APB1ENR_UART5EN                 0x00100000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_CAN1EN                  0x02000000U
+#define  RCC_APB1ENR_CAN2EN                  0x04000000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
+#define  RCC_APB1ENR_DACEN                   0x20000000U
+#define  RCC_APB1ENR_UART7EN                 0x40000000U
+#define  RCC_APB1ENR_UART8EN                 0x80000000U
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_TIM8EN                  0x00000002U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_ADC2EN                  0x00000200U
+#define  RCC_APB2ENR_ADC3EN                  0x00000400U
+#define  RCC_APB2ENR_SDIOEN                  0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SPI5EN                  0x00100000U
+#define  RCC_APB2ENR_SPI6EN                  0x00200000U
+#define  RCC_APB2ENR_SAI1EN                  0x00400000U
+#define  RCC_APB2ENR_LTDCEN                  0x04000000U
+
+/********************  Bit definition for RCC_AHB1LPENR register  *************/
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
+#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
+#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
+#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
+
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_SRAM3LPEN             0x00080000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
+#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
+
+#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
+#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
+#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
+#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
+#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
+
+/********************  Bit definition for RCC_AHB2LPENR register  *************/
+#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
+#define  RCC_AHB2LPENR_CRYPLPEN              0x00000010U
+#define  RCC_AHB2LPENR_HASHLPEN              0x00000020U
+#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
+
+/********************  Bit definition for RCC_AHB3LPENR register  *************/
+#define  RCC_AHB3LPENR_FMCLPEN              0x00000001U
+
+/********************  Bit definition for RCC_APB1LPENR register  *************/
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
+#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
+#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
+#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
+#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
+#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
+#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
+#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
+#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
+#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
+
+/********************  Bit definition for RCC_APB2LPENR register  *************/
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
+#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
+#define  RCC_APB2LPENR_SDIOLPEN              0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
+#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
+#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
+#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
+#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
+
+#define  RCC_BDCR_RTCSEL                    0x00000300U
+#define  RCC_BDCR_RTCSEL_0                  0x00000100U
+#define  RCC_BDCR_RTCSEL_1                  0x00000200U
+
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PADRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_WDGRSTF                     0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
+
+/********************  Bit definition for RCC_SSCGR register  *****************/
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
+
+/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
+
+#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
+
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
+
+
+/********************  Bit definition for RCC_PLLSAICFGR register  ************/
+#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
+#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
+#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
+#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
+#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
+#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
+#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
+#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
+#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
+#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
+
+#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
+
+#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
+
+/********************  Bit definition for RCC_DCKCFGR register  ***************/
+#define  RCC_DCKCFGR_PLLI2SDIVQ              0x0000001FU
+#define  RCC_DCKCFGR_PLLSAIDIVQ              0x00001F00U
+#define  RCC_DCKCFGR_PLLSAIDIVR              0x00030000U
+#define  RCC_DCKCFGR_SAI1ASRC                0x00300000U
+#define  RCC_DCKCFGR_SAI1ASRC_0              0x00100000U
+#define  RCC_DCKCFGR_SAI1ASRC_1              0x00200000U
+#define  RCC_DCKCFGR_SAI1BSRC                0x00C00000U
+#define  RCC_DCKCFGR_SAI1BSRC_0              0x00400000U
+#define  RCC_DCKCFGR_SAI1BSRC_1              0x00800000U
+#define  RCC_DCKCFGR_TIMPRE                  0x01000000U
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN                         0x00000004U
+#define RNG_CR_IE                            0x00000008U
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY                          0x00000001U
+#define RNG_SR_CECS                          0x00000002U
+#define RNG_SR_SECS                          0x00000004U
+#define RNG_SR_CEIS                          0x00000020U
+#define RNG_SR_SEIS                          0x00000040U
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_DCE                           0x00000080U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT                         0x0000FFFFU
+
+/********************  Bits definition for RTC_CALIBR register  ***************/
+#define RTC_CALIBR_DCS                       0x00000080U
+#define RTC_CALIBR_DC                        0x0000001FU
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          0x000000FFU
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           0x0000FFFFU
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         0x0000FFFFU
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE               0x00040000U
+#define RTC_TAFCR_TSINSEL                    0x00020000U
+#define RTC_TAFCR_TAMPINSEL                  0x00010000U
+#define RTC_TAFCR_TAMPPUDIS                  0x00008000U
+#define RTC_TAFCR_TAMPPRCH                   0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0                 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1                 0x00004000U
+#define RTC_TAFCR_TAMPFLT                    0x00001800U
+#define RTC_TAFCR_TAMPFLT_0                  0x00000800U
+#define RTC_TAFCR_TAMPFLT_1                  0x00001000U
+#define RTC_TAFCR_TAMPFREQ                   0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0                 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1                 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2                 0x00000400U
+#define RTC_TAFCR_TAMPTS                     0x00000080U
+#define RTC_TAFCR_TAMP2TRG                   0x00000010U
+#define RTC_TAFCR_TAMP2E                     0x00000008U
+#define RTC_TAFCR_TAMPIE                     0x00000004U
+#define RTC_TAFCR_TAMP1TRG                   0x00000002U
+#define RTC_TAFCR_TAMP1E                     0x00000001U
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R                           0xFFFFFFFFU
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define  SAI_GCR_SYNCIN                  0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define  SAI_GCR_SYNCIN_0                0x00000001U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCIN_1                0x00000002U        /*!<Bit 1 */
+
+#define  SAI_GCR_SYNCOUT                 0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define  SAI_GCR_SYNCOUT_0               0x00000010U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCOUT_1               0x00000020U        /*!<Bit 1 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define  SAI_xCR1_MODE                    0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define  SAI_xCR1_MODE_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR1_MODE_1                  0x00000002U        /*!<Bit 1 */
+
+#define  SAI_xCR1_PRTCFG                  0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define  SAI_xCR1_PRTCFG_0                0x00000004U        /*!<Bit 0 */
+#define  SAI_xCR1_PRTCFG_1                0x00000008U        /*!<Bit 1 */
+
+#define  SAI_xCR1_DS                      0x000000E0U        /*!<DS[1:0] bits (Data Size) */
+#define  SAI_xCR1_DS_0                    0x00000020U        /*!<Bit 0 */
+#define  SAI_xCR1_DS_1                    0x00000040U        /*!<Bit 1 */
+#define  SAI_xCR1_DS_2                    0x00000080U        /*!<Bit 2 */
+
+#define  SAI_xCR1_LSBFIRST                0x00000100U        /*!<LSB First Configuration  */
+#define  SAI_xCR1_CKSTR                   0x00000200U        /*!<ClocK STRobing edge      */
+
+#define  SAI_xCR1_SYNCEN                  0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define  SAI_xCR1_SYNCEN_0                0x00000400U        /*!<Bit 0 */
+#define  SAI_xCR1_SYNCEN_1                0x00000800U        /*!<Bit 1 */
+
+#define  SAI_xCR1_MONO                    0x00001000U        /*!<Mono mode                  */
+#define  SAI_xCR1_OUTDRIV                 0x00002000U        /*!<Output Drive               */
+#define  SAI_xCR1_SAIEN                   0x00010000U        /*!<Audio Block enable         */
+#define  SAI_xCR1_DMAEN                   0x00020000U        /*!<DMA enable                 */
+#define  SAI_xCR1_NODIV                   0x00080000U        /*!<No Divider Configuration   */
+
+#define  SAI_xCR1_MCKDIV                  0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define  SAI_xCR1_MCKDIV_0                0x00100000U        /*!<Bit 0  */
+#define  SAI_xCR1_MCKDIV_1                0x00200000U        /*!<Bit 1  */
+#define  SAI_xCR1_MCKDIV_2                0x00400000U        /*!<Bit 2  */
+#define  SAI_xCR1_MCKDIV_3                0x00800000U        /*!<Bit 3  */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define  SAI_xCR2_FTH                     0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
+#define  SAI_xCR2_FTH_0                   0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR2_FTH_1                   0x00000002U        /*!<Bit 1 */
+#define  SAI_xCR2_FTH_2                   0x00000004U        /*!<Bit 2 */
+
+#define  SAI_xCR2_FFLUSH                  0x00000008U        /*!<Fifo FLUSH                       */
+#define  SAI_xCR2_TRIS                    0x00000010U        /*!<TRIState Management on data line */
+#define  SAI_xCR2_MUTE                    0x00000020U        /*!<Mute mode                        */
+#define  SAI_xCR2_MUTEVAL                 0x00000040U        /*!<Muate value                      */
+
+#define  SAI_xCR2_MUTECNT                  0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
+#define  SAI_xCR2_MUTECNT_0               0x00000080U        /*!<Bit 0 */
+#define  SAI_xCR2_MUTECNT_1               0x00000100U        /*!<Bit 1 */
+#define  SAI_xCR2_MUTECNT_2               0x00000200U        /*!<Bit 2 */
+#define  SAI_xCR2_MUTECNT_3               0x00000400U        /*!<Bit 3 */
+#define  SAI_xCR2_MUTECNT_4               0x00000800U        /*!<Bit 4 */
+#define  SAI_xCR2_MUTECNT_5               0x00001000U        /*!<Bit 5 */
+
+#define  SAI_xCR2_CPL                     0x00002000U        /*!< Complement Bit             */
+
+#define  SAI_xCR2_COMP                    0x0000C000U        /*!<COMP[1:0] (Companding mode) */
+#define  SAI_xCR2_COMP_0                  0x00004000U        /*!<Bit 0 */
+#define  SAI_xCR2_COMP_1                  0x00008000U        /*!<Bit 1 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define  SAI_xFRCR_FRL                    0x000000FFU        /*!<FRL[1:0](Frame length)  */
+#define  SAI_xFRCR_FRL_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xFRCR_FRL_1                  0x00000002U        /*!<Bit 1 */
+#define  SAI_xFRCR_FRL_2                  0x00000004U        /*!<Bit 2 */
+#define  SAI_xFRCR_FRL_3                  0x00000008U        /*!<Bit 3 */
+#define  SAI_xFRCR_FRL_4                  0x00000010U        /*!<Bit 4 */
+#define  SAI_xFRCR_FRL_5                  0x00000020U        /*!<Bit 5 */
+#define  SAI_xFRCR_FRL_6                  0x00000040U        /*!<Bit 6 */
+#define  SAI_xFRCR_FRL_7                  0x00000080U        /*!<Bit 7 */
+
+#define  SAI_xFRCR_FSALL                  0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
+#define  SAI_xFRCR_FSALL_0                0x00000100U        /*!<Bit 0 */
+#define  SAI_xFRCR_FSALL_1                0x00000200U        /*!<Bit 1 */
+#define  SAI_xFRCR_FSALL_2                0x00000400U        /*!<Bit 2 */
+#define  SAI_xFRCR_FSALL_3                0x00000800U        /*!<Bit 3 */
+#define  SAI_xFRCR_FSALL_4                0x00001000U        /*!<Bit 4 */
+#define  SAI_xFRCR_FSALL_5                0x00002000U        /*!<Bit 5 */
+#define  SAI_xFRCR_FSALL_6                0x00004000U        /*!<Bit 6 */
+
+#define  SAI_xFRCR_FSDEF                  0x00010000U        /*!< Frame Synchronization Definition */
+#define  SAI_xFRCR_FSPOL                  0x00020000U        /*!<Frame Synchronization POLarity    */
+#define  SAI_xFRCR_FSOFF                  0x00040000U        /*!<Frame Synchronization OFFset      */
+/* Legacy defines */
+#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define  SAI_xSLOTR_FBOFF                 0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
+#define  SAI_xSLOTR_FBOFF_0               0x00000001U        /*!<Bit 0 */
+#define  SAI_xSLOTR_FBOFF_1               0x00000002U        /*!<Bit 1 */
+#define  SAI_xSLOTR_FBOFF_2               0x00000004U        /*!<Bit 2 */
+#define  SAI_xSLOTR_FBOFF_3               0x00000008U        /*!<Bit 3 */
+#define  SAI_xSLOTR_FBOFF_4               0x00000010U        /*!<Bit 4 */
+
+#define  SAI_xSLOTR_SLOTSZ                0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
+#define  SAI_xSLOTR_SLOTSZ_0              0x00000040U        /*!<Bit 0 */
+#define  SAI_xSLOTR_SLOTSZ_1              0x00000080U        /*!<Bit 1 */
+
+#define  SAI_xSLOTR_NBSLOT                0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define  SAI_xSLOTR_NBSLOT_0              0x00000100U        /*!<Bit 0 */
+#define  SAI_xSLOTR_NBSLOT_1              0x00000200U        /*!<Bit 1 */
+#define  SAI_xSLOTR_NBSLOT_2              0x00000400U        /*!<Bit 2 */
+#define  SAI_xSLOTR_NBSLOT_3              0x00000800U        /*!<Bit 3 */
+
+#define  SAI_xSLOTR_SLOTEN                0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define  SAI_xIMR_OVRUDRIE                0x00000001U        /*!<Overrun underrun interrupt enable                              */
+#define  SAI_xIMR_MUTEDETIE               0x00000002U        /*!<Mute detection interrupt enable                                */
+#define  SAI_xIMR_WCKCFGIE                0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
+#define  SAI_xIMR_FREQIE                  0x00000008U        /*!<FIFO request interrupt enable                                  */
+#define  SAI_xIMR_CNRDYIE                 0x00000010U        /*!<Codec not ready interrupt enable                               */
+#define  SAI_xIMR_AFSDETIE                0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
+#define  SAI_xIMR_LFSDETIE                0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define  SAI_xSR_OVRUDR                   0x00000001U         /*!<Overrun underrun                               */
+#define  SAI_xSR_MUTEDET                  0x00000002U         /*!<Mute detection                                 */
+#define  SAI_xSR_WCKCFG                   0x00000004U         /*!<Wrong Clock Configuration                      */
+#define  SAI_xSR_FREQ                     0x00000008U         /*!<FIFO request                                   */
+#define  SAI_xSR_CNRDY                    0x00000010U         /*!<Codec not ready                                */
+#define  SAI_xSR_AFSDET                   0x00000020U         /*!<Anticipated frame synchronization detection    */
+#define  SAI_xSR_LFSDET                   0x00000040U         /*!<Late frame synchronization detection           */
+
+#define  SAI_xSR_FLVL                     0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define  SAI_xSR_FLVL_0                   0x00010000U         /*!<Bit 0 */
+#define  SAI_xSR_FLVL_1                   0x00020000U         /*!<Bit 1 */
+#define  SAI_xSR_FLVL_2                   0x00040000U         /*!<Bit 2 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define  SAI_xCLRFR_COVRUDR               0x00000001U        /*!<Clear Overrun underrun                               */
+#define  SAI_xCLRFR_CMUTEDET              0x00000002U        /*!<Clear Mute detection                                 */
+#define  SAI_xCLRFR_CWCKCFG               0x00000004U        /*!<Clear Wrong Clock Configuration                      */
+#define  SAI_xCLRFR_CFREQ                 0x00000008U        /*!<Clear FIFO request                                   */
+#define  SAI_xCLRFR_CCNRDY                0x00000010U        /*!<Clear Codec not ready                                */
+#define  SAI_xCLRFR_CAFSDET               0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
+#define  SAI_xCLRFR_CLFSDET               0x00000040U        /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define  SAI_xDR_DATA                     0xFFFFFFFFU        
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDIO_POWER register  ******************/
+#define  SDIO_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
+
+/******************  Bit definition for SDIO_CLKCR register  ******************/
+#define  SDIO_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
+
+#define  SDIO_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
+
+#define  SDIO_CLKCR_NEGEDGE                  0x2000U            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDIO_ARG register  *******************/
+#define  SDIO_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
+
+/*******************  Bit definition for SDIO_CMD register  *******************/
+#define  SDIO_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
+
+#define  SDIO_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
+
+#define  SDIO_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 0x1000U            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       0x2000U            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   0x4000U            /*!<CE-ATA command       */
+
+/*****************  Bit definition for SDIO_RESPCMD register  *****************/
+#define  SDIO_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
+
+/******************  Bit definition for SDIO_RESP0 register  ******************/
+#define  SDIO_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP1 register  ******************/
+#define  SDIO_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP2 register  ******************/
+#define  SDIO_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP3 register  ******************/
+#define  SDIO_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP4 register  ******************/
+#define  SDIO_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDIO_DTIMER register  *****************/
+#define  SDIO_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
+
+/******************  Bit definition for SDIO_DLEN register  *******************/
+#define  SDIO_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
+
+/******************  Bit definition for SDIO_DCTRL register  ******************/
+#define  SDIO_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
+
+#define  SDIO_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
+
+#define  SDIO_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDIO_DCOUNT register  *****************/
+#define  SDIO_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
+
+/******************  Bit definition for SDIO_STA register  ********************/
+#define  SDIO_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   0x00000200U        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     0x00400000U        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   0x00800000U        /*!<CE-ATA command completion signal received for CMD61 */
+
+/*******************  Bit definition for SDIO_ICR register  *******************/
+#define  SDIO_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  0x00000200U        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    0x00400000U        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  0x00800000U        /*!<CEATAEND flag clear bit */
+
+/******************  Bit definition for SDIO_MASK register  *******************/
+#define  SDIO_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                0x00000200U        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  0x00400000U        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                0x00800000U        /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
+#define  SDIO_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDIO_FIFO register  *******************/
+#define  SDIO_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        0x00000001U            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        0x00000002U            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        0x00000004U            /*!<Master Selection */
+
+#define  SPI_CR1_BR                          0x00000038U            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        0x00000008U            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U            /*!<Bit 2 */
+
+#define  SPI_CR1_SPE                         0x00000040U            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         0x00000800U            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     0x00001000U            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U            /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     0x00000001U               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         0x00000010U               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       0x00000020U               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U               /*!<Tx buffer Empty Interrupt Enable     */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         0x00000001U               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          0x00000002U               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       0x00000004U               /*!<Channel side             */
+#define  SPI_SR_UDR                          0x00000008U               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       0x00000010U               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         0x00000020U               /*!<Mode fault               */
+#define  SPI_SR_OVR                          0x00000040U               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          0x00000080U               /*!<Busy flag                */
+#define  SPI_SR_FRE                          0x00000100U               /*!<Frame format error flag  */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           0x0000FFFFU            /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   0x0000FFFFU            /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    0x0000FFFFU            /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    0x0000FFFFU            /*!<Tx CRC Register         */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U            /*!<Channel length (number of bits per audio channel) */
+
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U            /*!<steady state clock polarity               */
+
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U            /*!<PCM frame synchronization                 */
+
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_I2SE                    0x00000400U            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    0x000000FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x00000100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x00000200U            /*!<Master Clock Output Enable   */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
+#define SYSCFG_MEMRMP_MEM_MODE          0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1        0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2        0x00000004U
+
+#define SYSCFG_MEMRMP_UFB_MODE          0x00000100U /*!< User Flash Bank mode    */
+#define SYSCFG_SWP_FMC                  0x00000C00U /*!< FMC memory mapping swap */
+
+/******************  Bit definition for SYSCFG_PMC register  ******************/
+#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
+
+#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
+/** 
+  * @brief   EXTI0 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
+
+/** 
+  * @brief   EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
+
+
+/** 
+  * @brief   EXTI2 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
+
+
+/** 
+  * @brief   EXTI3 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
+
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
+/** 
+  * @brief   EXTI4 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
+
+/** 
+  * @brief   EXTI5 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
+
+/** 
+  * @brief   EXTI6 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
+
+
+/** 
+  * @brief   EXTI7 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
+           
+/** 
+  * @brief   EXTI8 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
+
+/** 
+  * @brief   EXTI9 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
+
+
+/** 
+  * @brief   EXTI10 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
+
+
+/** 
+  * @brief   EXTI11 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
+
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
+/** 
+  * @brief   EXTI12 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
+
+
+/** 
+  * @brief   EXTI13 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        0x0009U /*!<PJ[13] pin */
+
+
+/** 
+  * @brief   EXTI14 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
+
+
+/** 
+  * @brief   EXTI15 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
+
+/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
+
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
+
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        0x0001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x0004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x0008U            /*!<Capture/Compare DMA Selection            */
+
+#define  TIM_CR2_MMS                         0x0070U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        0x0007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x0004U            /*!<Bit 2 */
+
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
+
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          0x01U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x02U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x04U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x08U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x10U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x20U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x40U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x80U               /*!<Break Generation                          */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      0x0003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x0002U            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     0x0004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x0008U            /*!<Output Compare 1 Preload enable              */
+
+#define  TIM_CCMR1_OC1M                      0x0070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x0040U            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     0x0080U            /*!<Output Compare 1Clear Enable                 */
+
+#define  TIM_CCMR1_CC2S                      0x0300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x0200U            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     0x0400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x0800U            /*!<Output Compare 2 Preload enable              */
+
+#define  TIM_CCMR1_OC2M                      0x7000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x4000U            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     0x8000U            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      0x0003U            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x0001U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x0002U            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     0x0004U            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x0008U            /*!<Output Compare 3 Preload enable        */
+
+#define  TIM_CCMR2_OC3M                      0x0070U            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x0040U            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     0x0080U            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      0x0300U            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x0100U            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x0200U            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     0x0400U            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x0800U            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      0x7000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x4000U            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       0x0001U            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       0x0002U            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      0x0004U            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      0x0008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x0010U            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       0x0020U            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      0x0040U            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      0x0080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x0100U            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       0x0200U            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      0x0400U            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      0x0800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x1000U            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       0x2000U            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      0x8000U            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         0xFFU               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        0x00FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x0001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x0002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x0004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x0008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x0010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x0020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x0040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x0080U            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       0x0300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x0100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x0200U            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       0x0400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x0800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x1000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x2000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x4000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x8000U            /*!<Main Output enable                */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for USART_SR register  *******************/
+#define  USART_SR_PE                         0x0001U            /*!<Parity Error                 */
+#define  USART_SR_FE                         0x0002U            /*!<Framing Error                */
+#define  USART_SR_NE                         0x0004U            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        0x0008U            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       0x0010U            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       0x0020U            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         0x0040U            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        0x0080U            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        0x0100U            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        0x0200U            /*!<CTS Flag                     */
+
+/*******************  Bit definition for USART_DR register  *******************/
+#define  USART_DR_DR                         0x01FFU            /*!<Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_Fraction              0x000FU            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              0xFFF0U            /*!<Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_SBK                       0x0001U            /*!<Send Break                             */
+#define  USART_CR1_RWU                       0x0002U            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        0x0004U            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        0x0008U            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    0x0010U            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    0x0020U            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      0x0040U            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     0x0080U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      0x0100U            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        0x0200U            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       0x0400U            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      0x0800U            /*!<Wakeup method                          */
+#define  USART_CR1_M                         0x1000U            /*!<Word length                            */
+#define  USART_CR1_UE                        0x2000U            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     0x8000U            /*!<USART Oversampling by 8 enable         */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADD                       0x000FU            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      0x0020U            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     0x0040U            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      0x0100U            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      0x0200U            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      0x0400U            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     0x0800U            /*!<Clock Enable                         */
+
+#define  USART_CR2_STOP                      0x3000U            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    0x1000U            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    0x2000U            /*!<Bit 1 */
+
+#define  USART_CR2_LINEN                     0x4000U            /*!<LIN mode enable */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       0x0001U            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      0x0002U            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      0x0004U            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     0x0008U            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      0x0010U            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      0x0020U            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      0x0040U            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      0x0080U            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      0x0100U            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      0x0200U            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     0x0400U            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    0x0800U            /*!<USART One bit method enable */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      0x00FFU            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    0x0001U            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    0x0002U            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    0x0004U            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    0x0008U            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    0x0010U            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    0x0020U            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    0x0040U            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    0x0080U            /*!<Bit 7 */
+
+#define  USART_GTPR_GT                       0xFF00U            /*!<Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           0x7FU               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                         0x01U               /*!<Bit 0 */
+#define  WWDG_CR_T_1                         0x02U               /*!<Bit 1 */
+#define  WWDG_CR_T_2                         0x04U               /*!<Bit 2 */
+#define  WWDG_CR_T_3                         0x08U               /*!<Bit 3 */
+#define  WWDG_CR_T_4                         0x10U               /*!<Bit 4 */
+#define  WWDG_CR_T_5                         0x20U               /*!<Bit 5 */
+#define  WWDG_CR_T_6                         0x40U               /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
+
+#define  WWDG_CR_WDGA                        0x80U               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          0x007FU            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U            /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U            /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U            /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U            /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U            /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U            /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U            /*!<Bit 6 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
+
+#define  WWDG_CFR_WDGTB                      0x0180U            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U            /*!<Bit 1 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
+
+#define  WWDG_CFR_EWI                        0x0200U            /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        0x01U               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
+
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U/*!<Bit 1 */
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       0x00040000U
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD      0x00800000U  /* Watchdog disable */
+#define ETH_MACCR_JD      0x00400000U  /* Jabber disable */
+#define ETH_MACCR_IFG     0x000E0000U  /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit     0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
+  #define ETH_MACCR_IFG_88Bit     0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
+  #define ETH_MACCR_IFG_80Bit     0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
+  #define ETH_MACCR_IFG_72Bit     0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
+  #define ETH_MACCR_IFG_64Bit     0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
+  #define ETH_MACCR_IFG_56Bit     0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
+  #define ETH_MACCR_IFG_48Bit     0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
+  #define ETH_MACCR_IFG_40Bit     0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
+#define ETH_MACCR_CSD     0x00010000U  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES     0x00004000U  /* Fast ethernet speed */
+#define ETH_MACCR_ROD     0x00002000U  /* Receive own disable */
+#define ETH_MACCR_LM      0x00001000U  /* loopback mode */
+#define ETH_MACCR_DM      0x00000800U  /* Duplex mode */
+#define ETH_MACCR_IPCO    0x00000400U  /* IP Checksum offload */
+#define ETH_MACCR_RD      0x00000200U  /* Retry disable */
+#define ETH_MACCR_APCS    0x00000080U  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL      0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
+  #define ETH_MACCR_BL_10    0x00000000U  /* k = min (n, 10) */
+  #define ETH_MACCR_BL_8     0x00000020U  /* k = min (n, 8) */
+  #define ETH_MACCR_BL_4     0x00000040U  /* k = min (n, 4) */
+  #define ETH_MACCR_BL_1     0x00000060U  /* k = min (n, 1) */ 
+#define ETH_MACCR_DC      0x00000010U  /* Defferal check */
+#define ETH_MACCR_TE      0x00000008U  /* Transmitter enable */
+#define ETH_MACCR_RE      0x00000004U  /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA     0x80000000U  /* Receive all */ 
+#define ETH_MACFFR_HPF    0x00000400U  /* Hash or perfect filter */ 
+#define ETH_MACFFR_SAF    0x00000200U  /* Source address filter enable */ 
+#define ETH_MACFFR_SAIF   0x00000100U  /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF    0x000000C0U  /* Pass control frames: 3 cases */
+  #define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
+  #define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
+  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD    0x00000020U  /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM    0x00000010U  /* Pass all mutlicast */ 
+#define ETH_MACFFR_DAIF   0x00000008U  /* DA Inverse filtering */ 
+#define ETH_MACFFR_HM     0x00000004U  /* Hash multicast */ 
+#define ETH_MACFFR_HU     0x00000002U  /* Hash unicast */
+#define ETH_MACFFR_PM     0x00000001U  /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH   0xFFFFFFFFU  /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL   0xFFFFFFFFU  /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA   0x0000F800U  /* Physical layer address */ 
+#define ETH_MACMIIAR_MR   0x000007C0U  /* MII register in the selected PHY */ 
+#define ETH_MACMIIAR_CR   0x0000001CU  /* CR clock range: 6 cases */ 
+  #define ETH_MACMIIAR_CR_Div42   0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+  #define ETH_MACMIIAR_CR_Div62   0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+  #define ETH_MACMIIAR_CR_Div16   0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+  #define ETH_MACMIIAR_CR_Div26   0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+  #define ETH_MACMIIAR_CR_Div102  0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
+#define ETH_MACMIIAR_MW   0x00000002U  /* MII write */ 
+#define ETH_MACMIIAR_MB   0x00000001U  /* MII busy */ 
+  
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD   0x0000FFFFU  /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT     0xFFFF0000U  /* Pause time */
+#define ETH_MACFCR_ZQPD   0x00000080U  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT    0x00000030U  /* Pause low threshold: 4 cases */
+  #define ETH_MACFCR_PLT_Minus4   0x00000000U  /* Pause time minus 4 slot times */
+  #define ETH_MACFCR_PLT_Minus28  0x00000010U  /* Pause time minus 28 slot times */
+  #define ETH_MACFCR_PLT_Minus144 0x00000020U  /* Pause time minus 144 slot times */
+  #define ETH_MACFCR_PLT_Minus256 0x00000030U  /* Pause time minus 256 slot times */      
+#define ETH_MACFCR_UPFD   0x00000008U  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE   0x00000004U  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE   0x00000002U  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA 0x00000001U  /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC 0x00010000U  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
+#define ETH_MACRWUFFR_D   0xFFFFFFFFU  /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU     0x00000200U  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR    0x00000040U  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR    0x00000020U  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE    0x00000004U  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE    0x00000002U  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD     0x00000001U  /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
+#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
+#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
+#define ETH_MACA1HR_MACA1H   0x0000FFFFU  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
+#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
+#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU    0x00000020U  /* Addend register update */
+#define ETH_PTPTSCR_TSITE    0x00000010U  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU    0x00000008U  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI    0x00000004U  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU    0x00000002U  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE      0x00000001U  /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI    0x000000FFU  /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS      0xFFFFFFFFU  /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS    0x80000000U  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS     0x7FFFFFFFU  /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS    0xFFFFFFFFU  /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS  0x80000000U  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU  /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA      0xFFFFFFFFU  /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH     0xFFFFFFFFU  /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL     0xFFFFFFFFU  /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR    0x00000020U  /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO     0x00000010U  /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB       0x02000000U  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
+#define ETH_DMABMR_USP       0x00800000U  /* Use separate PBL */
+#define ETH_DMABMR_RDP       0x007E0000U  /* RxDMA PBL */
+  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
+  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
+#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
+#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
+  /* combination with EBS[2:0] for GetFlagStatus function */
+  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
+#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
+#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
+#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         0x00000040U  /* Receive status */
+#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
+#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
+#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
+#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
+#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG			                        */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U            /*!< Session request success  */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U            /*!< Session request          */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U            /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U            /*!< HNP request              */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U            /*!< Host set HNP enable      */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U            /*!< Device HNP enabled       */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U            /*!< Connector ID status      */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U            /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U            /*!< A-session valid          */
+#define USB_OTG_GOTGCTL_BSVLD                   0x00080000U            /*!< B-session valid          */
+
+/********************  Bit definition forUSB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
+
+/********************  Bit definition forUSB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
+
+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
+
+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
+
+/********************  Bit definition forUSB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
+
+/********************  Bit definition forUSB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
+
+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
+
+/********************  Bit definition forUSB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
+
+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
+
+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
+
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
+
+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
+
+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
+
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
+
+/********************  Bit definition forUSB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT                   0x0000FFFFU            /*!< Channel interrupts */
+
+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
+
+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation           */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt             */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                       */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                      */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                     */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty            */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective            */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                            */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                              */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                         */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt          */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition forUSB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
+
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
+
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
+
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
+
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
+
+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP                  0x00000FFFU            /*!< Device VBUS pulsing time */
+
+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
+
+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
+
+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               0x0000FFFFU            /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT                 0x00000002U            /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT                 0x00020000U            /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_PWRDWN                  0x00010000U            /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN                0x00020000U            /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN                0x00040000U            /*!< Enable the VBUS sensing device                               */
+#define USB_OTG_GCCFG_VBUSBSEN                0x00080000U            /*!< Enable the VBUS sensing device                               */
+#define USB_OTG_GCCFG_SOFOUTEN                0x00100000U            /*!< SOF output enable                                            */
+#define USB_OTG_GCCFG_NOVBUSSENS              0x00200000U            /*!< VBUS sensing disable option                                  */
+
+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM                0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition forUSB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID              0xFFFFFFFFU            /*!< Product ID field */
+
+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  0x00000100U            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume   */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend  */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset    */
+
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
+
+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM                     0x00000008U            /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  0x00000100U            /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM                     0x00000200U            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   0x00001000U            /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    0x00002000U            /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   0x00004000U            /*!< NYET interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
+
+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
+
+/********************  Bit definition forUSB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
+
+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
+
+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
+
+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
+
+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+                                       ((INSTANCE) == CAN2))
+ 
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+                                              ((INSTANCE) == DMA1_Stream1) || \
+                                              ((INSTANCE) == DMA1_Stream2) || \
+                                              ((INSTANCE) == DMA1_Stream3) || \
+                                              ((INSTANCE) == DMA1_Stream4) || \
+                                              ((INSTANCE) == DMA1_Stream5) || \
+                                              ((INSTANCE) == DMA1_Stream6) || \
+                                              ((INSTANCE) == DMA1_Stream7) || \
+                                              ((INSTANCE) == DMA2_Stream0) || \
+                                              ((INSTANCE) == DMA2_Stream1) || \
+                                              ((INSTANCE) == DMA2_Stream2) || \
+                                              ((INSTANCE) == DMA2_Stream3) || \
+                                              ((INSTANCE) == DMA2_Stream4) || \
+                                              ((INSTANCE) == DMA2_Stream5) || \
+                                              ((INSTANCE) == DMA2_Stream6) || \
+                                              ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH) || \
+                                        ((INSTANCE) == GPIOI) || \
+                                        ((INSTANCE) == GPIOJ) || \
+                                        ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
+                                        ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
+                                          ((INSTANCE) == SPI3)    || \
+                                          ((INSTANCE) == I2S2ext) || \
+                                          ((INSTANCE) == I2S3ext))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+                                     ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3) || \
+                                       ((INSTANCE) == SPI4) || \
+                                       ((INSTANCE) == SPI5) || \
+                                       ((INSTANCE) == SPI6))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
+                                           ((INSTANCE) == SPI2)    || \
+                                           ((INSTANCE) == SPI3)    || \
+                                           ((INSTANCE) == SPI4)    || \
+                                           ((INSTANCE) == SPI5)    || \
+                                           ((INSTANCE) == SPI6)    || \
+                                           ((INSTANCE) == I2S2ext) || \
+                                           ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                   ((INSTANCE) == TIM2)   || \
+                                   ((INSTANCE) == TIM3)   || \
+                                   ((INSTANCE) == TIM4)   || \
+                                   ((INSTANCE) == TIM5)   || \
+                                   ((INSTANCE) == TIM6)   || \
+                                   ((INSTANCE) == TIM7)   || \
+                                   ((INSTANCE) == TIM8)   || \
+                                   ((INSTANCE) == TIM9)   || \
+                                   ((INSTANCE) == TIM10)  || \
+                                   ((INSTANCE) == TIM11)  || \
+                                   ((INSTANCE) == TIM12)  || \
+                                   ((INSTANCE) == TIM13)  || \
+                                   ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
+                                         ((INSTANCE) == TIM2)  || \
+                                         ((INSTANCE) == TIM3)  || \
+                                         ((INSTANCE) == TIM4)  || \
+                                         ((INSTANCE) == TIM5)  || \
+                                         ((INSTANCE) == TIM8)  || \
+                                         ((INSTANCE) == TIM9)  || \
+                                         ((INSTANCE) == TIM10) || \
+                                         ((INSTANCE) == TIM11) || \
+                                         ((INSTANCE) == TIM12) || \
+                                         ((INSTANCE) == TIM13) || \
+                                         ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5) || \
+                                       ((INSTANCE) == TIM8) || \
+                                       ((INSTANCE) == TIM9) || \
+                                       ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5) || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5) || \
+                                       ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                            ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5) || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5) || \
+                                       ((INSTANCE) == TIM6) || \
+                                       ((INSTANCE) == TIM7) || \
+                                       ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM2) || \
+                                          ((INSTANCE) == TIM3) || \
+                                          ((INSTANCE) == TIM4) || \
+                                          ((INSTANCE) == TIM5) || \
+                                          ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM2) || \
+                                          ((INSTANCE) == TIM3) || \
+                                          ((INSTANCE) == TIM4) || \
+                                          ((INSTANCE) == TIM5) || \
+                                          ((INSTANCE) == TIM8)) 
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                             ((INSTANCE) == TIM2) || \
+                                             ((INSTANCE) == TIM3) || \
+                                             ((INSTANCE) == TIM4) || \
+                                             ((INSTANCE) == TIM5) || \
+                                             ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM2) || \
+                                          ((INSTANCE) == TIM3) || \
+                                          ((INSTANCE) == TIM4) || \
+                                          ((INSTANCE) == TIM5) || \
+                                          ((INSTANCE) == TIM6) || \
+                                          ((INSTANCE) == TIM7) || \
+                                          ((INSTANCE) == TIM8) || \
+                                          ((INSTANCE) == TIM9) || \
+                                          ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5) || \
+                                         ((INSTANCE) == TIM8) || \
+                                         ((INSTANCE) == TIM9) || \
+                                         ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+                                              ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                        ((INSTANCE) == TIM2) || \
+                                        ((INSTANCE) == TIM3) || \
+                                        ((INSTANCE) == TIM4) || \
+                                        ((INSTANCE) == TIM5) || \
+                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                         ((INSTANCE) == TIM5)  || \
+                                         ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM2) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM3) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM4) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM5) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM8) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM9) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((INSTANCE) == TIM10) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM11) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM12) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((INSTANCE) == TIM13) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM14) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM8) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3) || \
+                                     ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))     
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                        ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                       ((INSTANCE) == USB_OTG_HS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32F4xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */
+/*  product lines within the same STM32F4 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define FSMC_IRQn              FMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FSMC_IRQHandler        FMC_IRQHandler
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F439xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/TARGET_NUCLEO_F439ZI/device/stm32f4xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/TARGET_NUCLEO_F439ZI/device/stm32f4xx.h
new file mode 100644
index 00000000000..c13e84f3a0d
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/TARGET_NUCLEO_F439ZI/device/stm32f4xx.h
@@ -0,0 +1,264 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx.h
+  * @author  MCD Application Team
+  * @version V2.5.0
+  * @date    22-April-2016
+  * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32F4xx device used in the target application
+  *              - To use or not the peripheral's drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral's registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx
+  * @{
+  */
+    
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+   
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/**
+  * @brief STM32 Family
+  */
+#if !defined  (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+    !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+    !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx)
+  /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+  /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+  /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
+  /* #define STM32F417xx */   /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+  /* #define STM32F427xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+  /* #define STM32F437xx */   /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+  /*#define STM32F429xx  */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, 
+                                   STM32F439NI, STM32F429IG  and STM32F429II Devices */
+#define STM32F439xx    /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, 
+                                   STM32F439NI, STM32F439IG and STM32F439II Devices */
+  /* #define STM32F401xC */   /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+  /*  #define STM32F401xE */         /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+  /* #define STM32F410Tx */   /*!< STM32F410T8 and STM32F410TB Devices */
+  /* #define STM32F410Cx */   /*!< STM32F410C8 and STM32F410CB Devices */
+  /* #define STM32F410Rx */   /*!< STM32F410R8 and STM32F410RB Devices */
+  /* #define STM32F411xE */   /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+  /* #define STM32F446xx */   /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, 
+                                   and STM32F446ZE Devices */
+  /* #define STM32F469xx */   /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, 
+                                   STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+  /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
+                                   and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+#endif
+   
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS version number V2.5.0
+  */
+#define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+                                         |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32F405xx)
+  #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+  #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+  #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+  #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+  #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+  #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+  #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+  #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+  #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+  #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+  #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+  #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+  #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+  #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+  #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+  #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+  #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  RESET = 0U, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0U, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  ERROR = 0U, 
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_ARM_MICRO/stm32f429xx.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_ARM_MICRO/stm32f429xx.sct
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_ARM_MICRO/stm32f429xx.sct
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_ARM_MICRO/stm32f429xx.sct
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.s
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.s
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.s
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_ARM_STD/sys.cpp
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_ARM_STD/sys.cpp
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_ARM_STD/sys.cpp
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_GCC_ARM/STM32F429ZI.ld b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_GCC_ARM/STM32F429ZI.ld
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_GCC_ARM/STM32F429ZI.ld
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_GCC_ARM/STM32F429ZI.ld
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_IAR/startup_stm32f429xx.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_IAR/startup_stm32f429xx.S
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/cmsis.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/cmsis.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/cmsis.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/cmsis_nvic.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/cmsis_nvic.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/cmsis_nvic.c
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/cmsis_nvic.c
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/cmsis_nvic.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/cmsis_nvic.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/cmsis_nvic.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/hal_tick.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/hal_tick.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/hal_tick.c
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/hal_tick.c
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/hal_tick.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/hal_tick.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/hal_tick.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/stm32f4xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/stm32f4xx_hal_conf.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/stm32f4xx_hal_conf.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/stm32f4xx_hal_conf.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/system_stm32f4xx.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/system_stm32f4xx.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/system_stm32f4xx.c
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/system_stm32f4xx.c
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/system_stm32f4xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/system_stm32f4xx.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/device/system_stm32f4xx.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/device/system_stm32f4xx.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/objects.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/objects.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/objects.h
diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h
index 77febaaf6da..3f598f6c952 100644
--- a/targets/TARGET_STM/mbed_rtx.h
+++ b/targets/TARGET_STM/mbed_rtx.h
@@ -272,7 +272,7 @@
 #define OS_CLOCK                84000000
 #endif
 
-#elif defined(TARGET_STM32F429ZI)
+#elif (defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F439ZI))
 
 #ifndef INITIAL_SP
 #define INITIAL_SP              (0x20030000UL)
diff --git a/targets/targets.json b/targets/targets.json
index 11143b43eca..d05bf59ca64 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -821,7 +821,7 @@
         "inherits": ["Target"],
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
-        "extra_labels": ["STM", "STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx"],
+        "extra_labels": ["STM", "STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx", "F429_F439"],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "progen": {"target": "nucleo-f429zi"},
         "macros": ["RTC_LSI=1", "TRANSACTION_QUEUE_SIZE_SPI=2"],
@@ -831,6 +831,21 @@
         "release_versions": ["2", "5"],
         "device_name" : "STM32F429ZI"
     },
+    "NUCLEO_F439ZI": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "default_toolchain": "ARM",
+        "extra_labels": ["STM", "STM32F4", "STM32F439", "STM32F439ZI", "STM32F439xx", "F429_F439"],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "progen": {"target": "nucleo-f439zi"},
+        "macros": ["RTC_LSI=1", "TRANSACTION_QUEUE_SIZE_SPI=2"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"],
+        "detect_code": ["0797"],
+        "features": ["LWIP"],
+        "release_versions": ["2", "5"],
+        "device_name" : "STM32F429ZI"
+    },
     "NUCLEO_F446RE": {
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M4F",

From 025a041462316677248c132d26e84afed4189138 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Tue, 11 Oct 2016 09:45:41 +0200
Subject: [PATCH 83/89] ADD NEW TARGET : NUCLEO_L486RG, based on existing
 NUCLEO_L476RG

---
 .../PeripheralNames.h                         |     0
 .../PeripheralPins.c                          |     0
 .../PinNames.h                                |     0
 .../PortNames.h                               |     0
 .../TARGET_NUCLEO_L476RG/device/stm32l476xx.h |     0
 .../TARGET_NUCLEO_L476RG/device/stm32l4xx.h   |     0
 .../TARGET_NUCLEO_L486RG/device/stm32l486xx.h | 18737 ++++++++++++++++
 .../TARGET_NUCLEO_L486RG/device/stm32l4xx.h   |   241 +
 .../TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S |     0
 .../TOOLCHAIN_ARM_MICRO/stm32l476xx.sct       |     0
 .../TOOLCHAIN_ARM_STD/startup_stm32l476xx.S   |     0
 .../device/TOOLCHAIN_ARM_STD/stm32l476xx.sct  |     0
 .../device/TOOLCHAIN_ARM_STD/sys.cpp          |     0
 .../device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld   |     0
 .../TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S   |     0
 .../TOOLCHAIN_IAR/startup_stm32l476xx.S       |     0
 .../device/TOOLCHAIN_IAR/stm32l476xx.icf      |     0
 .../device/cmsis.h                            |     0
 .../device/cmsis_nvic.c                       |     0
 .../device/cmsis_nvic.h                       |     0
 .../device/hal_tick.c                         |     0
 .../device/hal_tick.h                         |     0
 .../device/stm32l4xx_hal_conf.h               |     0
 .../device/system_stm32l4xx.c                 |     0
 .../device/system_stm32l4xx.h                 |     0
 .../objects.h                                 |     0
 targets/TARGET_STM/mbed_rtx.h                 |     2 +-
 targets/targets.json                          |    14 +-
 28 files changed, 18992 insertions(+), 2 deletions(-)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/PeripheralNames.h (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/PeripheralPins.c (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/PinNames.h (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/PortNames.h (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{ => TARGET_L476_L486}/TARGET_NUCLEO_L476RG/device/stm32l476xx.h (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{ => TARGET_L476_L486}/TARGET_NUCLEO_L476RG/device/stm32l4xx.h (100%)
 create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/TARGET_NUCLEO_L486RG/device/stm32l486xx.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/TARGET_NUCLEO_L486RG/device/stm32l4xx.h
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/TOOLCHAIN_ARM_STD/startup_stm32l476xx.S (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/TOOLCHAIN_ARM_STD/stm32l476xx.sct (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/TOOLCHAIN_ARM_STD/sys.cpp (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/TOOLCHAIN_IAR/startup_stm32l476xx.S (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/TOOLCHAIN_IAR/stm32l476xx.icf (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/cmsis.h (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/cmsis_nvic.c (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/cmsis_nvic.h (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/hal_tick.c (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/hal_tick.h (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/stm32l4xx_hal_conf.h (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/system_stm32l4xx.c (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/device/system_stm32l4xx.h (100%)
 rename targets/TARGET_STM/TARGET_STM32L4/{TARGET_NUCLEO_L476RG => TARGET_L476_L486}/objects.h (100%)

diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/PeripheralNames.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PeripheralNames.h
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/PeripheralNames.h
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/PeripheralPins.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PeripheralPins.c
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/PeripheralPins.c
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/PinNames.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PinNames.h
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/PinNames.h
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PortNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/PortNames.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PortNames.h
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/PortNames.h
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/stm32l476xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/TARGET_NUCLEO_L476RG/device/stm32l476xx.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/stm32l476xx.h
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/TARGET_NUCLEO_L476RG/device/stm32l476xx.h
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/TARGET_NUCLEO_L476RG/device/stm32l4xx.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/stm32l4xx.h
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/TARGET_NUCLEO_L476RG/device/stm32l4xx.h
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/TARGET_NUCLEO_L486RG/device/stm32l486xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/TARGET_NUCLEO_L486RG/device/stm32l486xx.h
new file mode 100644
index 00000000000..3d209d91795
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/TARGET_NUCLEO_L486RG/device/stm32l486xx.h
@@ -0,0 +1,18737 @@
+/**
+  ******************************************************************************
+  * @file    stm32l486xx.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    29-April-2016
+  * @brief   CMSIS STM32L486xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral�s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32l486xx
+  * @{
+  */
+
+#ifndef __STM32L486xx_H
+#define __STM32L486xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+   */
+#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1       /*!< STM32L4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4       /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32L4XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts    */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */
+  ADC1_2_IRQn                 = 18,     /*!< ADC1, ADC2 SAR global Interrupts                                  */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  DFSDM1_FLT3_IRQn            = 42,     /*!< DFSDM1 Filter 3 global Interrupt                                  */
+  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */
+  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */
+  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  ADC3_IRQn                   = 47,     /*!< ADC3 global  Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
+  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
+  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */
+  DFSDM1_FLT2_IRQn            = 63,     /*!< DFSDM1 Filter 2 global Interrupt                                  */
+  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 Interrupts                                        */
+  LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */
+  LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */
+  DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */
+  LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */
+  QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  SAI1_IRQn                   = 74,     /*!< Serial Audio Interface 1 global interrupt                         */
+  SAI2_IRQn                   = 75,     /*!< Serial Audio Interface 2 global interrupt                         */
+  SWPMI1_IRQn                 = 76,     /*!< Serial Wire Interface 1 global interrupt                          */
+  TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */
+  LCD_IRQn                    = 78,     /*!< LCD global interrupt                                              */
+  AES_IRQn                    = 79,     /*!< AES global interrupt                                              */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32l4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
+  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
+  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
+  __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
+  __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
+  __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
+       uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
+  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
+  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
+  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
+       uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
+  __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
+  __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
+  __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
+  __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
+  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
+       uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
+       uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
+  __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
+       uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
+  __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
+  __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
+  __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
+  __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
+       uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
+  __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
+  __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
+  __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
+  __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
+       uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
+  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
+       uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
+       uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
+  __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
+  __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< ADC common status register,                    Address offset: ADC1 base address + 0x300 */
+  uint32_t      RESERVED;     /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
+  __IO uint32_t CDR;          /*!< ADC common group regular data register         Address offset: ADC1 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+
+/**
+  * @brief Controller Area Network TxMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FIFOMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FilterRegister
+  */
+
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+  * @brief Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
+  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+} DAC_TypeDef;
+
+/**
+  * @brief DFSDM module registers
+  */
+typedef struct
+{
+  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */
+  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */
+  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
+  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
+  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
+  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */
+  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */
+  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */
+  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
+  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
+  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
+  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
+  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
+  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
+  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+  * @brief DFSDM channel configuration registers
+  */
+typedef struct
+{
+  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
+  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
+  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
+                                  short circuit detector register,                  Address offset: 0x08 */
+  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
+  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
+  __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
+  __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
+  __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
+  __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
+} DBGMCU_TypeDef;
+
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
+  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
+  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
+  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
+  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSELR;       /*!< DMA channel selection register              */
+} DMA_Request_TypeDef;
+
+/* Legacy define */
+#define DMA_request_TypeDef  DMA_Request_TypeDef
+
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
+  __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
+  __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
+  __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
+  __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
+  __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
+  uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
+  __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
+  __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
+  __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
+  __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
+  __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
+  __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
+} EXTI_TypeDef;
+
+
+/**
+  * @brief Firewall
+  */
+
+typedef struct
+{
+  __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */
+  __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */
+  __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
+  __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
+  __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
+  __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */
+  uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */
+  __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */
+} FIREWALL_TypeDef;
+
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
+  __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
+  __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
+  __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
+  __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
+  __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
+  __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
+  __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
+  __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
+  __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
+  __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
+  __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
+  __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
+       uint32_t RESERVED2[4];     /*!< Reserved2,                                Address offset: 0x34 */
+  __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
+  __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */
+  __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */
+  __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */
+} FLASH_TypeDef;
+
+
+/**
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+
+typedef struct
+{
+  __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
+  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
+  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
+  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
+  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
+  __IO uint32_t ASCR;        /*!< GPIO analog switch control register,   Address offset: 0x2C     */
+
+} GPIO_TypeDef;
+
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief LCD
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< LCD control register,              Address offset: 0x00 */
+  __IO uint32_t FCR;         /*!< LCD frame control register,        Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< LCD status register,               Address offset: 0x08 */
+  __IO uint32_t CLR;         /*!< LCD clear register,                Address offset: 0x0C */
+  uint32_t RESERVED;         /*!< Reserved,                          Address offset: 0x10 */
+  __IO uint32_t RAM[16];     /*!< LCD display memory,           Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/**
+  * @brief LPTIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
+  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
+  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
+  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
+  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
+  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
+  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
+  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
+  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
+  __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
+  __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
+} OPAMP_Common_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
+  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */
+  __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */
+  __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */
+  __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */
+  __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */
+  __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */
+  uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */
+  __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */
+  __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
+  __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */
+  __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
+  __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */
+  __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
+  __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */
+  __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
+  __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */
+  __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
+  __IO uint32_t PUCRF; /*!< Pull_up control register of portF,   Address offset: 0x48 */
+  __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
+  __IO uint32_t PUCRG; /*!< Pull_up control register of portG,   Address offset: 0x50 */
+  __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
+  __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */
+  __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
+} PWR_TypeDef;
+
+
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
+  __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
+  __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
+  __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
+  __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */
+  __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register,                                     Address offset: 0x14 */
+  __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
+  __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
+  __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
+  uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */
+  __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
+  __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
+  __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
+  uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */
+  __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
+  __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
+  __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */
+  __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
+  __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
+  __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
+  uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */
+  __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
+  __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
+  __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
+  uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */
+  __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
+  __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
+  __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
+  uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */
+  __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
+  __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
+  __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
+  uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */
+  __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
+  __IO uint32_t RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */
+  __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
+  __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;         /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t reserved;    /*!< Reserved  */
+  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;      /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;       /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;      /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;      /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;      /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;      /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;      /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;      /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;      /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;      /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;      /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;      /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;      /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;      /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;         /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,    Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
+  __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
+  __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
+  __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
+  uint32_t  RESERVED1;       /*!< Reserved,                                            Address offset: 0x1C */
+  uint32_t  RESERVED2;       /*!< Reserved,                                            Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+  * @brief Single Wire Protocol Master Interface SPWMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */
+  __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */
+  __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */
+} SYSCFG_TypeDef;
+
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
+  __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
+  __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */
+  __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */
+} TIM_TypeDef;
+
+
+/**
+  * @brief Touch Sensing Controller (TSC)
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
+  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+/**
+  * @brief VREFBUF
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @brief AES hardware accelerator
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
+  __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
+  __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
+  __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
+  __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
+  __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
+  __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
+  __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
+  __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
+  __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
+  __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
+  __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
+  __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
+  __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
+  __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
+  __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
+  __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
+  __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
+  __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
+  __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
+  __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
+  __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
+  __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
+  __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x6C */
+} AES_TypeDef;
+
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/** 
+  * @brief USB_OTG_Core_register
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register          000h*/
+  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                   004h*/
+  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register              008h*/
+  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register              00Ch*/
+  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                          010h*/
+  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                      014h*/
+  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                 018h*/
+  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                  01Ch*/
+  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register            020h*/
+  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                      024h*/
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register     028h*/
+  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg           02Ch*/
+  uint32_t Reserved30[2];             /* Reserved                                        030h*/
+  __IO uint32_t GCCFG;                /* General Purpose IO Register                     038h*/
+  __IO uint32_t CID;                  /* User ID Register                                03Ch*/
+  uint32_t  Reserved5[3];             /* Reserved                                        040h-048h*/
+  __IO uint32_t GHWCFG3;              /* User HW config3                                 04Ch*/
+  uint32_t  Reserved6;                /* Reserved                                        050h*/ 
+  __IO uint32_t GLPMCFG;              /* LPM Register                                    054h*/
+  __IO uint32_t GPWRDN;               /* Power Down Register                             058h*/
+  __IO uint32_t GDFIFOCFG;            /* DFIFO Software Config Register                  05Ch*/
+   __IO uint32_t GADPCTL;             /* ADP Timer, Control and Status Register          60Ch*/
+    uint32_t  Reserved43[39];         /* Reserved                                        058h-0FFh*/
+  __IO uint32_t HPTXFSIZ;             /* Host Periodic Tx FIFO Size Reg                  100h*/
+  __IO uint32_t DIEPTXF[0x0F];        /* dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/** 
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DCFG;        /* dev Configuration Register   800h*/
+  __IO uint32_t DCTL;        /* dev Control Register         804h*/
+  __IO uint32_t DSTS;        /* dev Status Register (RO)     808h*/
+  uint32_t Reserved0C;       /* Reserved                     80Ch*/
+  __IO uint32_t DIEPMSK;     /* dev IN Endpoint Mask         810h*/
+  __IO uint32_t DOEPMSK;     /* dev OUT Endpoint Mask        814h*/
+  __IO uint32_t DAINT;       /* dev All Endpoints Itr Reg    818h*/
+  __IO uint32_t DAINTMSK;    /* dev All Endpoints Itr Mask   81Ch*/
+  uint32_t  Reserved20;      /* Reserved                     820h*/
+  uint32_t Reserved9;        /* Reserved                     824h*/
+  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
+  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
+  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
+  __IO uint32_t DIEPEMPMSK;  /* dev empty msk             834h*/
+  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
+  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
+  uint32_t Reserved40;       /* dedicated EP mask           840h*/
+  __IO uint32_t DINEP1MSK;   /* dedicated EP mask           844h*/
+  uint32_t  Reserved44[15];  /* Reserved                 844-87Ch*/
+  __IO uint32_t DOUTEP1MSK;  /* dedicated EP msk            884h*/   
+} USB_OTG_DeviceTypeDef;
+
+/** 
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;     /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;       /* Reserved                       900h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DIEPINT;     /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;       /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DIEPTSIZ;    /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DIEPDMA;     /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
+  __IO uint32_t DTXFSTS;     /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+  uint32_t Reserved18;       /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+} USB_OTG_INEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;     /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;       /* Reserved                      B00h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DOEPINT;     /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;       /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DOEPTSIZ;    /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DOEPDMA;     /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
+  uint32_t Reserved18[2];    /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+} USB_OTG_OUTEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct 
+{
+  __IO uint32_t HCFG;        /* Host Configuration Register    400h*/
+  __IO uint32_t HFIR;        /* Host Frame Interval Register   404h*/
+  __IO uint32_t HFNUM;       /* Host Frame Nbr/Frame Remaining 408h*/
+  uint32_t Reserved40C;      /* Reserved                       40Ch*/
+  __IO uint32_t HPTXSTS;     /* Host Periodic Tx FIFO/ Queue Status 410h*/
+  __IO uint32_t HAINT;       /* Host All Channels Interrupt Register 414h*/
+  __IO uint32_t HAINTMSK;    /* Host All Channels Interrupt Mask 418h*/
+} USB_OTG_HostTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;
+  __IO uint32_t HCSPLT;
+  __IO uint32_t HCINT;
+  __IO uint32_t HCINTMSK;
+  __IO uint32_t HCTSIZ;
+  __IO uint32_t HCDMA;
+  uint32_t Reserved[2];
+} USB_OTG_HostChannelTypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
+#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */
+#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address */
+#define FMC_BASE              ((uint32_t)0x60000000U) /*!< FMC base address */
+#define SRAM2_BASE            ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */
+#define QSPI_BASE             ((uint32_t)0x90000000U) /*!< QSPI memories accessible over AHB base address */
+#define FMC_R_BASE            ((uint32_t)0xA0000000U) /*!< FMC  control registers base address */
+#define QSPI_R_BASE           ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
+#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
+#define SRAM2_BB_BASE         ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
+
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+#define SRAM1_SIZE_MAX        ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */
+#define SRAM2_SIZE            ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000U)
+
+#define FMC_BANK1             FMC_BASE
+#define FMC_BANK1_1           FMC_BANK1
+#define FMC_BANK1_2           (FMC_BANK1 + 0x04000000U)
+#define FMC_BANK1_3           (FMC_BANK1 + 0x08000000U)
+#define FMC_BANK1_4           (FMC_BANK1 + 0x0C000000U)
+#define FMC_BANK3             (FMC_BASE  + 0x20000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
+#define LCD_BASE              (APB1PERIPH_BASE + 0x2400U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
+#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400U)
+#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP2_BASE           (APB1PERIPH_BASE + 0x7810U)
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00U)
+#define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000U)
+#define SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800U)
+#define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400U)
+
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000U)
+#define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030U)
+#define COMP1_BASE            (APB2PERIPH_BASE + 0x0200U)
+#define COMP2_BASE            (APB2PERIPH_BASE + 0x0204U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400U)
+#define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00U)
+#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800U)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000U)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400U)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800U)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
+#define SAI2_BASE             (APB2PERIPH_BASE + 0x5800U)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024)
+#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000U)
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00)
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20)
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40)
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60)
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80)
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0)
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0)
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0)
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100)
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180)
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200)
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE             (AHB1PERIPH_BASE)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define TSC_BASE              (AHB1PERIPH_BASE + 0x4000U)
+
+
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008U)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CU)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030U)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044U)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058U)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CU)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080U)
+#define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8U)
+
+
+#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008U)
+#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CU)
+#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030U)
+#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044U)
+#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058U)
+#define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CU)
+#define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080U)
+#define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8U)
+
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00U)
+
+#define USBOTG_BASE           (AHB2PERIPH_BASE + 0x08000000U)
+
+#define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000U)
+#define ADC2_BASE             (AHB2PERIPH_BASE + 0x08040100U)
+#define ADC3_BASE             (AHB2PERIPH_BASE + 0x08040200U)
+#define ADC123_COMMON_BASE    (AHB2PERIPH_BASE + 0x08040300U)
+
+
+#define AES_BASE              (AHB2PERIPH_BASE + 0x08060000U)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800U)
+
+
+/*!< FMC Banks registers base  address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           ((uint32_t)0xE0042000U)
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE               ((uint32_t)0x50000000U)
+
+#define USB_OTG_GLOBAL_BASE                  ((uint32_t)0x00000000U)
+#define USB_OTG_DEVICE_BASE                  ((uint32_t)0x00000800U)
+#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t)0x00000900U)
+#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t)0x00000B00U)
+#define USB_OTG_EP_REG_SIZE                  ((uint32_t)0x00000020U)
+#define USB_OTG_HOST_BASE                    ((uint32_t)0x00000400U)
+#define USB_OTG_HOST_PORT_BASE               ((uint32_t)0x00000440U)
+#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t)0x00000500U)
+#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t)0x00000020U)
+#define USB_OTG_PCGCCTL_BASE                 ((uint32_t)0x00000E00U)
+#define USB_OTG_FIFO_BASE                    ((uint32_t)0x00001000U)
+#define USB_OTG_FIFO_SIZE                    ((uint32_t)0x00001000U)
+
+
+#define PACKAGE_BASE          ((uint32_t)0x1FFF7500U)        /*!< Package data register base address     */
+#define UID_BASE              ((uint32_t)0x1FFF7590U)        /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE        ((uint32_t)0x1FFF75E0U)        /*!< Flash size data register base address  */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define LCD                 ((LCD_TypeDef *) LCD_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC1_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+/* Aliases to keep compatibility after DFSDM renaming */
+#define DFSDM_Channel0      DFSDM1_Channel0
+#define DFSDM_Channel1      DFSDM1_Channel1
+#define DFSDM_Channel2      DFSDM1_Channel2
+#define DFSDM_Channel3      DFSDM1_Channel3
+#define DFSDM_Channel4      DFSDM1_Channel4
+#define DFSDM_Channel5      DFSDM1_Channel5
+#define DFSDM_Channel6      DFSDM1_Channel6
+#define DFSDM_Channel7      DFSDM1_Channel7
+#define DFSDM_Filter0       DFSDM1_Filter0
+#define DFSDM_Filter1       DFSDM1_Filter1
+#define DFSDM_Filter2       DFSDM1_Filter2
+#define DFSDM_Filter3       DFSDM1_Filter3
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+#define AES                 ((AES_TypeDef *) AES_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+
+
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR          ((DMA_request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
+#define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
+#define DMA2_CSELR          ((DMA_request_TypeDef *) DMA2_CSELR_BASE)
+
+
+#define FMC_Bank1_R         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3_R         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+
+#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/********************  Bit definition for ADC_ISR register  *******************/
+#define ADC_ISR_ADRDY_Pos       (0U)                                           
+#define ADC_ISR_ADRDY_Msk       (0x1U << ADC_ISR_ADRDY_Pos)                    /*!< 0x00000001 */
+#define ADC_ISR_ADRDY           ADC_ISR_ADRDY_Msk                              /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos       (1U)                                           
+#define ADC_ISR_EOSMP_Msk       (0x1U << ADC_ISR_EOSMP_Pos)                    /*!< 0x00000002 */
+#define ADC_ISR_EOSMP           ADC_ISR_EOSMP_Msk                              /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos         (2U)                                           
+#define ADC_ISR_EOC_Msk         (0x1U << ADC_ISR_EOC_Pos)                      /*!< 0x00000004 */
+#define ADC_ISR_EOC             ADC_ISR_EOC_Msk                                /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos         (3U)                                           
+#define ADC_ISR_EOS_Msk         (0x1U << ADC_ISR_EOS_Pos)                      /*!< 0x00000008 */
+#define ADC_ISR_EOS             ADC_ISR_EOS_Msk                                /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos         (4U)                                           
+#define ADC_ISR_OVR_Msk         (0x1U << ADC_ISR_OVR_Pos)                      /*!< 0x00000010 */
+#define ADC_ISR_OVR             ADC_ISR_OVR_Msk                                /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos        (5U)                                           
+#define ADC_ISR_JEOC_Msk        (0x1U << ADC_ISR_JEOC_Pos)                     /*!< 0x00000020 */
+#define ADC_ISR_JEOC            ADC_ISR_JEOC_Msk                               /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos        (6U)                                           
+#define ADC_ISR_JEOS_Msk        (0x1U << ADC_ISR_JEOS_Pos)                     /*!< 0x00000040 */
+#define ADC_ISR_JEOS            ADC_ISR_JEOS_Msk                               /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos        (7U)                                           
+#define ADC_ISR_AWD1_Msk        (0x1U << ADC_ISR_AWD1_Pos)                     /*!< 0x00000080 */
+#define ADC_ISR_AWD1            ADC_ISR_AWD1_Msk                               /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos        (8U)                                           
+#define ADC_ISR_AWD2_Msk        (0x1U << ADC_ISR_AWD2_Pos)                     /*!< 0x00000100 */
+#define ADC_ISR_AWD2            ADC_ISR_AWD2_Msk                               /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos        (9U)                                           
+#define ADC_ISR_AWD3_Msk        (0x1U << ADC_ISR_AWD3_Pos)                     /*!< 0x00000200 */
+#define ADC_ISR_AWD3            ADC_ISR_AWD3_Msk                               /*!< ADC analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos       (10U)                                          
+#define ADC_ISR_JQOVF_Msk       (0x1U << ADC_ISR_JQOVF_Pos)                    /*!< 0x00000400 */
+#define ADC_ISR_JQOVF           ADC_ISR_JQOVF_Msk                              /*!< ADC group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_IER register  *******************/
+#define ADC_IER_ADRDYIE_Pos     (0U)                                           
+#define ADC_IER_ADRDYIE_Msk     (0x1U << ADC_IER_ADRDYIE_Pos)                  /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE         ADC_IER_ADRDYIE_Msk                            /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos     (1U)                                           
+#define ADC_IER_EOSMPIE_Msk     (0x1U << ADC_IER_EOSMPIE_Pos)                  /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE         ADC_IER_EOSMPIE_Msk                            /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos       (2U)                                           
+#define ADC_IER_EOCIE_Msk       (0x1U << ADC_IER_EOCIE_Pos)                    /*!< 0x00000004 */
+#define ADC_IER_EOCIE           ADC_IER_EOCIE_Msk                              /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos       (3U)                                           
+#define ADC_IER_EOSIE_Msk       (0x1U << ADC_IER_EOSIE_Pos)                    /*!< 0x00000008 */
+#define ADC_IER_EOSIE           ADC_IER_EOSIE_Msk                              /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos       (4U)                                           
+#define ADC_IER_OVRIE_Msk       (0x1U << ADC_IER_OVRIE_Pos)                    /*!< 0x00000010 */
+#define ADC_IER_OVRIE           ADC_IER_OVRIE_Msk                              /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos      (5U)                                           
+#define ADC_IER_JEOCIE_Msk      (0x1U << ADC_IER_JEOCIE_Pos)                   /*!< 0x00000020 */
+#define ADC_IER_JEOCIE          ADC_IER_JEOCIE_Msk                             /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos      (6U)                                           
+#define ADC_IER_JEOSIE_Msk      (0x1U << ADC_IER_JEOSIE_Pos)                   /*!< 0x00000040 */
+#define ADC_IER_JEOSIE          ADC_IER_JEOSIE_Msk                             /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos      (7U)                                           
+#define ADC_IER_AWD1IE_Msk      (0x1U << ADC_IER_AWD1IE_Pos)                   /*!< 0x00000080 */
+#define ADC_IER_AWD1IE          ADC_IER_AWD1IE_Msk                             /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos      (8U)                                           
+#define ADC_IER_AWD2IE_Msk      (0x1U << ADC_IER_AWD2IE_Pos)                   /*!< 0x00000100 */
+#define ADC_IER_AWD2IE          ADC_IER_AWD2IE_Msk                             /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos      (9U)                                           
+#define ADC_IER_AWD3IE_Msk      (0x1U << ADC_IER_AWD3IE_Pos)                   /*!< 0x00000200 */
+#define ADC_IER_AWD3IE          ADC_IER_AWD3IE_Msk                             /*!< ADC analog watchdog 3 interrupt */
+#define ADC_IER_JQOVFIE_Pos     (10U)                                          
+#define ADC_IER_JQOVFIE_Msk     (0x1U << ADC_IER_JQOVFIE_Pos)                  /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE         ADC_IER_JQOVFIE_Msk                            /*!< ADC group injected contexts queue overflow interrupt */
+
+/* Legacy defines */
+#define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)
+#define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
+#define ADC_IER_EOC             (ADC_IER_EOCIE)
+#define ADC_IER_EOS             (ADC_IER_EOSIE)
+#define ADC_IER_OVR             (ADC_IER_OVRIE)
+#define ADC_IER_JEOC            (ADC_IER_JEOCIE)
+#define ADC_IER_JEOS            (ADC_IER_JEOSIE)
+#define ADC_IER_AWD1            (ADC_IER_AWD1IE)
+#define ADC_IER_AWD2            (ADC_IER_AWD2IE)
+#define ADC_IER_AWD3            (ADC_IER_AWD3IE)
+#define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos         (0U)                                           
+#define ADC_CR_ADEN_Msk         (0x1U << ADC_CR_ADEN_Pos)                      /*!< 0x00000001 */
+#define ADC_CR_ADEN             ADC_CR_ADEN_Msk                                /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos        (1U)                                           
+#define ADC_CR_ADDIS_Msk        (0x1U << ADC_CR_ADDIS_Pos)                     /*!< 0x00000002 */
+#define ADC_CR_ADDIS            ADC_CR_ADDIS_Msk                               /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos      (2U)                                           
+#define ADC_CR_ADSTART_Msk      (0x1U << ADC_CR_ADSTART_Pos)                   /*!< 0x00000004 */
+#define ADC_CR_ADSTART          ADC_CR_ADSTART_Msk                             /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos     (3U)                                           
+#define ADC_CR_JADSTART_Msk     (0x1U << ADC_CR_JADSTART_Pos)                  /*!< 0x00000008 */
+#define ADC_CR_JADSTART         ADC_CR_JADSTART_Msk                            /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos        (4U)                                           
+#define ADC_CR_ADSTP_Msk        (0x1U << ADC_CR_ADSTP_Pos)                     /*!< 0x00000010 */
+#define ADC_CR_ADSTP            ADC_CR_ADSTP_Msk                               /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos       (5U)                                           
+#define ADC_CR_JADSTP_Msk       (0x1U << ADC_CR_JADSTP_Pos)                    /*!< 0x00000020 */
+#define ADC_CR_JADSTP           ADC_CR_JADSTP_Msk                              /*!< ADC group injected conversion stop */
+#define ADC_CR_ADVREGEN_Pos     (28U)                                          
+#define ADC_CR_ADVREGEN_Msk     (0x1U << ADC_CR_ADVREGEN_Pos)                  /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN         ADC_CR_ADVREGEN_Msk                            /*!< ADC voltage regulator enable */
+#define ADC_CR_DEEPPWD_Pos      (29U)                                          
+#define ADC_CR_DEEPPWD_Msk      (0x1U << ADC_CR_DEEPPWD_Pos)                   /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD          ADC_CR_DEEPPWD_Msk                             /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos     (30U)                                          
+#define ADC_CR_ADCALDIF_Msk     (0x1U << ADC_CR_ADCALDIF_Pos)                  /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF         ADC_CR_ADCALDIF_Msk                            /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos        (31U)                                          
+#define ADC_CR_ADCAL_Msk        (0x1U << ADC_CR_ADCAL_Pos)                     /*!< 0x80000000 */
+#define ADC_CR_ADCAL            ADC_CR_ADCAL_Msk                               /*!< ADC calibration */
+
+/********************  Bit definition for ADC_CFGR register  ******************/
+#define ADC_CFGR_DMAEN_Pos      (0U)                                           
+#define ADC_CFGR_DMAEN_Msk      (0x1U << ADC_CFGR_DMAEN_Pos)                   /*!< 0x00000001 */
+#define ADC_CFGR_DMAEN          ADC_CFGR_DMAEN_Msk                             /*!< ADC DMA transfer enable */
+#define ADC_CFGR_DMACFG_Pos     (1U)                                           
+#define ADC_CFGR_DMACFG_Msk     (0x1U << ADC_CFGR_DMACFG_Pos)                  /*!< 0x00000002 */
+#define ADC_CFGR_DMACFG         ADC_CFGR_DMACFG_Msk                            /*!< ADC DMA transfer configuration */
+
+#define ADC_CFGR_RES_Pos        (3U)                                           
+#define ADC_CFGR_RES_Msk        (0x3U << ADC_CFGR_RES_Pos)                     /*!< 0x00000018 */
+#define ADC_CFGR_RES            ADC_CFGR_RES_Msk                               /*!< ADC data resolution */
+#define ADC_CFGR_RES_0          (0x1U << ADC_CFGR_RES_Pos)                     /*!< 0x00000008 */
+#define ADC_CFGR_RES_1          (0x2U << ADC_CFGR_RES_Pos)                     /*!< 0x00000010 */
+
+#define ADC_CFGR_ALIGN_Pos      (5U)                                           
+#define ADC_CFGR_ALIGN_Msk      (0x1U << ADC_CFGR_ALIGN_Pos)                   /*!< 0x00000020 */
+#define ADC_CFGR_ALIGN          ADC_CFGR_ALIGN_Msk                             /*!< ADC data alignement */
+
+#define ADC_CFGR_EXTSEL_Pos     (6U)                                           
+#define ADC_CFGR_EXTSEL_Msk     (0xFU << ADC_CFGR_EXTSEL_Pos)                  /*!< 0x000003C0 */
+#define ADC_CFGR_EXTSEL         ADC_CFGR_EXTSEL_Msk                            /*!< ADC group regular external trigger source */
+#define ADC_CFGR_EXTSEL_0       (0x1U << ADC_CFGR_EXTSEL_Pos)                  /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_1       (0x2U << ADC_CFGR_EXTSEL_Pos)                  /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_2       (0x4U << ADC_CFGR_EXTSEL_Pos)                  /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_3       (0x8U << ADC_CFGR_EXTSEL_Pos)                  /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos      (10U)                                          
+#define ADC_CFGR_EXTEN_Msk      (0x3U << ADC_CFGR_EXTEN_Pos)                   /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN          ADC_CFGR_EXTEN_Msk                             /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR_EXTEN_0        (0x1U << ADC_CFGR_EXTEN_Pos)                   /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1        (0x2U << ADC_CFGR_EXTEN_Pos)                   /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos     (12U)                                          
+#define ADC_CFGR_OVRMOD_Msk     (0x1U << ADC_CFGR_OVRMOD_Pos)                  /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD         ADC_CFGR_OVRMOD_Msk                            /*!< ADC group regular overrun configuration */
+#define ADC_CFGR_CONT_Pos       (13U)                                          
+#define ADC_CFGR_CONT_Msk       (0x1U << ADC_CFGR_CONT_Pos)                    /*!< 0x00002000 */
+#define ADC_CFGR_CONT           ADC_CFGR_CONT_Msk                              /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR_AUTDLY_Pos     (14U)                                          
+#define ADC_CFGR_AUTDLY_Msk     (0x1U << ADC_CFGR_AUTDLY_Pos)                  /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY         ADC_CFGR_AUTDLY_Msk                            /*!< ADC low power auto wait */
+
+#define ADC_CFGR_DISCEN_Pos     (16U)                                          
+#define ADC_CFGR_DISCEN_Msk     (0x1U << ADC_CFGR_DISCEN_Pos)                  /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN         ADC_CFGR_DISCEN_Msk                            /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR_DISCNUM_Pos    (17U)                                          
+#define ADC_CFGR_DISCNUM_Msk    (0x7U << ADC_CFGR_DISCNUM_Pos)                 /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM        ADC_CFGR_DISCNUM_Msk                           /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR_DISCNUM_0      (0x1U << ADC_CFGR_DISCNUM_Pos)                 /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1      (0x2U << ADC_CFGR_DISCNUM_Pos)                 /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2      (0x4U << ADC_CFGR_DISCNUM_Pos)                 /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos    (20U)                                          
+#define ADC_CFGR_JDISCEN_Msk    (0x1U << ADC_CFGR_JDISCEN_Pos)                 /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN        ADC_CFGR_JDISCEN_Msk                           /*!< ADC group injected sequencer discontinuous mode */
+#define ADC_CFGR_JQM_Pos        (21U)                                          
+#define ADC_CFGR_JQM_Msk        (0x1U << ADC_CFGR_JQM_Pos)                     /*!< 0x00200000 */
+#define ADC_CFGR_JQM            ADC_CFGR_JQM_Msk                               /*!< ADC group injected contexts queue mode */
+#define ADC_CFGR_AWD1SGL_Pos    (22U)                                          
+#define ADC_CFGR_AWD1SGL_Msk    (0x1U << ADC_CFGR_AWD1SGL_Pos)                 /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL        ADC_CFGR_AWD1SGL_Msk                           /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR_AWD1EN_Pos     (23U)                                          
+#define ADC_CFGR_AWD1EN_Msk     (0x1U << ADC_CFGR_AWD1EN_Pos)                  /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN         ADC_CFGR_AWD1EN_Msk                            /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR_JAWD1EN_Pos    (24U)                                          
+#define ADC_CFGR_JAWD1EN_Msk    (0x1U << ADC_CFGR_JAWD1EN_Pos)                 /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN        ADC_CFGR_JAWD1EN_Msk                           /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR_JAUTO_Pos      (25U)                                          
+#define ADC_CFGR_JAUTO_Msk      (0x1U << ADC_CFGR_JAUTO_Pos)                   /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO          ADC_CFGR_JAUTO_Msk                             /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR_AWD1CH_Pos     (26U)                                          
+#define ADC_CFGR_AWD1CH_Msk     (0x1FU << ADC_CFGR_AWD1CH_Pos)                 /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH         ADC_CFGR_AWD1CH_Msk                            /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR_AWD1CH_0       (0x01U << ADC_CFGR_AWD1CH_Pos)                 /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1       (0x02U << ADC_CFGR_AWD1CH_Pos)                 /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2       (0x04U << ADC_CFGR_AWD1CH_Pos)                 /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3       (0x08U << ADC_CFGR_AWD1CH_Pos)                 /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4       (0x10U << ADC_CFGR_AWD1CH_Pos)                 /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos      (31U)                                          
+#define ADC_CFGR_JQDIS_Msk      (0x1U << ADC_CFGR_JQDIS_Pos)                   /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS          ADC_CFGR_JQDIS_Msk                             /*!< ADC group injected contexts queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  *****************/
+#define ADC_CFGR2_ROVSE_Pos     (0U)                                           
+#define ADC_CFGR2_ROVSE_Msk     (0x1U << ADC_CFGR2_ROVSE_Pos)                  /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE         ADC_CFGR2_ROVSE_Msk                            /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos     (1U)                                           
+#define ADC_CFGR2_JOVSE_Msk     (0x1U << ADC_CFGR2_JOVSE_Pos)                  /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE         ADC_CFGR2_JOVSE_Msk                            /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSR_Pos      (2U)                                           
+#define ADC_CFGR2_OVSR_Msk      (0x7U << ADC_CFGR2_OVSR_Pos)                   /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR          ADC_CFGR2_OVSR_Msk                             /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0        (0x1U << ADC_CFGR2_OVSR_Pos)                   /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1        (0x2U << ADC_CFGR2_OVSR_Pos)                   /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2        (0x4U << ADC_CFGR2_OVSR_Pos)                   /*!< 0x00000010 */
+
+#define ADC_CFGR2_OVSS_Pos      (5U)                                           
+#define ADC_CFGR2_OVSS_Msk      (0xFU << ADC_CFGR2_OVSS_Pos)                   /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS          ADC_CFGR2_OVSS_Msk                             /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0        (0x1U << ADC_CFGR2_OVSS_Pos)                   /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1        (0x2U << ADC_CFGR2_OVSS_Pos)                   /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2        (0x4U << ADC_CFGR2_OVSS_Pos)                   /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3        (0x8U << ADC_CFGR2_OVSS_Pos)                   /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos     (9U)                                           
+#define ADC_CFGR2_TROVS_Msk     (0x1U << ADC_CFGR2_TROVS_Pos)                  /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS         ADC_CFGR2_TROVS_Msk                            /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos     (10U)                                          
+#define ADC_CFGR2_ROVSM_Msk     (0x1U << ADC_CFGR2_ROVSM_Pos)                  /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM         ADC_CFGR2_ROVSM_Msk                            /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+/********************  Bit definition for ADC_SMPR1 register  *****************/
+#define ADC_SMPR1_SMP0_Pos      (0U)                                           
+#define ADC_SMPR1_SMP0_Msk      (0x7U << ADC_SMPR1_SMP0_Pos)                   /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0          ADC_SMPR1_SMP0_Msk                             /*!< ADC channel 0 sampling time selection  */
+#define ADC_SMPR1_SMP0_0        (0x1U << ADC_SMPR1_SMP0_Pos)                   /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1        (0x2U << ADC_SMPR1_SMP0_Pos)                   /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2        (0x4U << ADC_SMPR1_SMP0_Pos)                   /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos      (3U)                                           
+#define ADC_SMPR1_SMP1_Msk      (0x7U << ADC_SMPR1_SMP1_Pos)                   /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1          ADC_SMPR1_SMP1_Msk                             /*!< ADC channel 1 sampling time selection  */
+#define ADC_SMPR1_SMP1_0        (0x1U << ADC_SMPR1_SMP1_Pos)                   /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1        (0x2U << ADC_SMPR1_SMP1_Pos)                   /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2        (0x4U << ADC_SMPR1_SMP1_Pos)                   /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos      (6U)                                           
+#define ADC_SMPR1_SMP2_Msk      (0x7U << ADC_SMPR1_SMP2_Pos)                   /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2          ADC_SMPR1_SMP2_Msk                             /*!< ADC channel 2 sampling time selection  */
+#define ADC_SMPR1_SMP2_0        (0x1U << ADC_SMPR1_SMP2_Pos)                   /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1        (0x2U << ADC_SMPR1_SMP2_Pos)                   /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2        (0x4U << ADC_SMPR1_SMP2_Pos)                   /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos      (9U)                                           
+#define ADC_SMPR1_SMP3_Msk      (0x7U << ADC_SMPR1_SMP3_Pos)                   /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3          ADC_SMPR1_SMP3_Msk                             /*!< ADC channel 3 sampling time selection  */
+#define ADC_SMPR1_SMP3_0        (0x1U << ADC_SMPR1_SMP3_Pos)                   /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1        (0x2U << ADC_SMPR1_SMP3_Pos)                   /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2        (0x4U << ADC_SMPR1_SMP3_Pos)                   /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos      (12U)                                          
+#define ADC_SMPR1_SMP4_Msk      (0x7U << ADC_SMPR1_SMP4_Pos)                   /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4          ADC_SMPR1_SMP4_Msk                             /*!< ADC channel 4 sampling time selection  */
+#define ADC_SMPR1_SMP4_0        (0x1U << ADC_SMPR1_SMP4_Pos)                   /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1        (0x2U << ADC_SMPR1_SMP4_Pos)                   /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2        (0x4U << ADC_SMPR1_SMP4_Pos)                   /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos      (15U)                                          
+#define ADC_SMPR1_SMP5_Msk      (0x7U << ADC_SMPR1_SMP5_Pos)                   /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5          ADC_SMPR1_SMP5_Msk                             /*!< ADC channel 5 sampling time selection  */
+#define ADC_SMPR1_SMP5_0        (0x1U << ADC_SMPR1_SMP5_Pos)                   /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1        (0x2U << ADC_SMPR1_SMP5_Pos)                   /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2        (0x4U << ADC_SMPR1_SMP5_Pos)                   /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos      (18U)                                          
+#define ADC_SMPR1_SMP6_Msk      (0x7U << ADC_SMPR1_SMP6_Pos)                   /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6          ADC_SMPR1_SMP6_Msk                             /*!< ADC channel 6 sampling time selection  */
+#define ADC_SMPR1_SMP6_0        (0x1U << ADC_SMPR1_SMP6_Pos)                   /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1        (0x2U << ADC_SMPR1_SMP6_Pos)                   /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2        (0x4U << ADC_SMPR1_SMP6_Pos)                   /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos      (21U)                                          
+#define ADC_SMPR1_SMP7_Msk      (0x7U << ADC_SMPR1_SMP7_Pos)                   /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7          ADC_SMPR1_SMP7_Msk                             /*!< ADC channel 7 sampling time selection  */
+#define ADC_SMPR1_SMP7_0        (0x1U << ADC_SMPR1_SMP7_Pos)                   /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1        (0x2U << ADC_SMPR1_SMP7_Pos)                   /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2        (0x4U << ADC_SMPR1_SMP7_Pos)                   /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos      (24U)                                          
+#define ADC_SMPR1_SMP8_Msk      (0x7U << ADC_SMPR1_SMP8_Pos)                   /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8          ADC_SMPR1_SMP8_Msk                             /*!< ADC channel 8 sampling time selection  */
+#define ADC_SMPR1_SMP8_0        (0x1U << ADC_SMPR1_SMP8_Pos)                   /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1        (0x2U << ADC_SMPR1_SMP8_Pos)                   /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2        (0x4U << ADC_SMPR1_SMP8_Pos)                   /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos      (27U)                                          
+#define ADC_SMPR1_SMP9_Msk      (0x7U << ADC_SMPR1_SMP9_Pos)                   /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9          ADC_SMPR1_SMP9_Msk                             /*!< ADC channel 9 sampling time selection  */
+#define ADC_SMPR1_SMP9_0        (0x1U << ADC_SMPR1_SMP9_Pos)                   /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1        (0x2U << ADC_SMPR1_SMP9_Pos)                   /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2        (0x4U << ADC_SMPR1_SMP9_Pos)                   /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  *****************/
+#define ADC_SMPR2_SMP10_Pos     (0U)                                           
+#define ADC_SMPR2_SMP10_Msk     (0x7U << ADC_SMPR2_SMP10_Pos)                  /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10         ADC_SMPR2_SMP10_Msk                            /*!< ADC channel 10 sampling time selection  */
+#define ADC_SMPR2_SMP10_0       (0x1U << ADC_SMPR2_SMP10_Pos)                  /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1       (0x2U << ADC_SMPR2_SMP10_Pos)                  /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2       (0x4U << ADC_SMPR2_SMP10_Pos)                  /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos     (3U)                                           
+#define ADC_SMPR2_SMP11_Msk     (0x7U << ADC_SMPR2_SMP11_Pos)                  /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11         ADC_SMPR2_SMP11_Msk                            /*!< ADC channel 11 sampling time selection  */
+#define ADC_SMPR2_SMP11_0       (0x1U << ADC_SMPR2_SMP11_Pos)                  /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1       (0x2U << ADC_SMPR2_SMP11_Pos)                  /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2       (0x4U << ADC_SMPR2_SMP11_Pos)                  /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos     (6U)                                           
+#define ADC_SMPR2_SMP12_Msk     (0x7U << ADC_SMPR2_SMP12_Pos)                  /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12         ADC_SMPR2_SMP12_Msk                            /*!< ADC channel 12 sampling time selection  */
+#define ADC_SMPR2_SMP12_0       (0x1U << ADC_SMPR2_SMP12_Pos)                  /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1       (0x2U << ADC_SMPR2_SMP12_Pos)                  /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2       (0x4U << ADC_SMPR2_SMP12_Pos)                  /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos     (9U)                                           
+#define ADC_SMPR2_SMP13_Msk     (0x7U << ADC_SMPR2_SMP13_Pos)                  /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13         ADC_SMPR2_SMP13_Msk                            /*!< ADC channel 13 sampling time selection  */
+#define ADC_SMPR2_SMP13_0       (0x1U << ADC_SMPR2_SMP13_Pos)                  /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1       (0x2U << ADC_SMPR2_SMP13_Pos)                  /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2       (0x4U << ADC_SMPR2_SMP13_Pos)                  /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos     (12U)                                          
+#define ADC_SMPR2_SMP14_Msk     (0x7U << ADC_SMPR2_SMP14_Pos)                  /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14         ADC_SMPR2_SMP14_Msk                            /*!< ADC channel 14 sampling time selection  */
+#define ADC_SMPR2_SMP14_0       (0x1U << ADC_SMPR2_SMP14_Pos)                  /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1       (0x2U << ADC_SMPR2_SMP14_Pos)                  /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2       (0x4U << ADC_SMPR2_SMP14_Pos)                  /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos     (15U)                                          
+#define ADC_SMPR2_SMP15_Msk     (0x7U << ADC_SMPR2_SMP15_Pos)                  /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15         ADC_SMPR2_SMP15_Msk                            /*!< ADC channel 15 sampling time selection  */
+#define ADC_SMPR2_SMP15_0       (0x1U << ADC_SMPR2_SMP15_Pos)                  /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1       (0x2U << ADC_SMPR2_SMP15_Pos)                  /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2       (0x4U << ADC_SMPR2_SMP15_Pos)                  /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos     (18U)                                          
+#define ADC_SMPR2_SMP16_Msk     (0x7U << ADC_SMPR2_SMP16_Pos)                  /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16         ADC_SMPR2_SMP16_Msk                            /*!< ADC channel 16 sampling time selection  */
+#define ADC_SMPR2_SMP16_0       (0x1U << ADC_SMPR2_SMP16_Pos)                  /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1       (0x2U << ADC_SMPR2_SMP16_Pos)                  /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2       (0x4U << ADC_SMPR2_SMP16_Pos)                  /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos     (21U)                                          
+#define ADC_SMPR2_SMP17_Msk     (0x7U << ADC_SMPR2_SMP17_Pos)                  /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17         ADC_SMPR2_SMP17_Msk                            /*!< ADC channel 17 sampling time selection  */
+#define ADC_SMPR2_SMP17_0       (0x1U << ADC_SMPR2_SMP17_Pos)                  /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1       (0x2U << ADC_SMPR2_SMP17_Pos)                  /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2       (0x4U << ADC_SMPR2_SMP17_Pos)                  /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos     (24U)                                          
+#define ADC_SMPR2_SMP18_Msk     (0x7U << ADC_SMPR2_SMP18_Pos)                  /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18         ADC_SMPR2_SMP18_Msk                            /*!< ADC channel 18 sampling time selection  */
+#define ADC_SMPR2_SMP18_0       (0x1U << ADC_SMPR2_SMP18_Pos)                  /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1       (0x2U << ADC_SMPR2_SMP18_Pos)                  /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2       (0x4U << ADC_SMPR2_SMP18_Pos)                  /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_TR1 register  *******************/
+#define ADC_TR1_LT1_Pos         (0U)                                           
+#define ADC_TR1_LT1_Msk         (0xFFFU << ADC_TR1_LT1_Pos)                    /*!< 0x00000FFF */
+#define ADC_TR1_LT1             ADC_TR1_LT1_Msk                                /*!< ADC analog watchdog 1 threshold low */
+#define ADC_TR1_LT1_0           (0x001U << ADC_TR1_LT1_Pos)                    /*!< 0x00000001 */
+#define ADC_TR1_LT1_1           (0x002U << ADC_TR1_LT1_Pos)                    /*!< 0x00000002 */
+#define ADC_TR1_LT1_2           (0x004U << ADC_TR1_LT1_Pos)                    /*!< 0x00000004 */
+#define ADC_TR1_LT1_3           (0x008U << ADC_TR1_LT1_Pos)                    /*!< 0x00000008 */
+#define ADC_TR1_LT1_4           (0x010U << ADC_TR1_LT1_Pos)                    /*!< 0x00000010 */
+#define ADC_TR1_LT1_5           (0x020U << ADC_TR1_LT1_Pos)                    /*!< 0x00000020 */
+#define ADC_TR1_LT1_6           (0x040U << ADC_TR1_LT1_Pos)                    /*!< 0x00000040 */
+#define ADC_TR1_LT1_7           (0x080U << ADC_TR1_LT1_Pos)                    /*!< 0x00000080 */
+#define ADC_TR1_LT1_8           (0x100U << ADC_TR1_LT1_Pos)                    /*!< 0x00000100 */
+#define ADC_TR1_LT1_9           (0x200U << ADC_TR1_LT1_Pos)                    /*!< 0x00000200 */
+#define ADC_TR1_LT1_10          (0x400U << ADC_TR1_LT1_Pos)                    /*!< 0x00000400 */
+#define ADC_TR1_LT1_11          (0x800U << ADC_TR1_LT1_Pos)                    /*!< 0x00000800 */
+
+#define ADC_TR1_HT1_Pos         (16U)                                          
+#define ADC_TR1_HT1_Msk         (0xFFFU << ADC_TR1_HT1_Pos)                    /*!< 0x0FFF0000 */
+#define ADC_TR1_HT1             ADC_TR1_HT1_Msk                                /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_TR1_HT1_0           (0x001U << ADC_TR1_HT1_Pos)                    /*!< 0x00010000 */
+#define ADC_TR1_HT1_1           (0x002U << ADC_TR1_HT1_Pos)                    /*!< 0x00020000 */
+#define ADC_TR1_HT1_2           (0x004U << ADC_TR1_HT1_Pos)                    /*!< 0x00040000 */
+#define ADC_TR1_HT1_3           (0x008U << ADC_TR1_HT1_Pos)                    /*!< 0x00080000 */
+#define ADC_TR1_HT1_4           (0x010U << ADC_TR1_HT1_Pos)                    /*!< 0x00100000 */
+#define ADC_TR1_HT1_5           (0x020U << ADC_TR1_HT1_Pos)                    /*!< 0x00200000 */
+#define ADC_TR1_HT1_6           (0x040U << ADC_TR1_HT1_Pos)                    /*!< 0x00400000 */
+#define ADC_TR1_HT1_7           (0x080U << ADC_TR1_HT1_Pos)                    /*!< 0x00800000 */
+#define ADC_TR1_HT1_8           (0x100U << ADC_TR1_HT1_Pos)                    /*!< 0x01000000 */
+#define ADC_TR1_HT1_9           (0x200U << ADC_TR1_HT1_Pos)                    /*!< 0x02000000 */
+#define ADC_TR1_HT1_10          (0x400U << ADC_TR1_HT1_Pos)                    /*!< 0x04000000 */
+#define ADC_TR1_HT1_11          (0x800U << ADC_TR1_HT1_Pos)                    /*!< 0x08000000 */
+
+/********************  Bit definition for ADC_TR2 register  *******************/
+#define ADC_TR2_LT2_Pos         (0U)                                           
+#define ADC_TR2_LT2_Msk         (0xFFU << ADC_TR2_LT2_Pos)                     /*!< 0x000000FF */
+#define ADC_TR2_LT2             ADC_TR2_LT2_Msk                                /*!< ADC analog watchdog 2 threshold low */
+#define ADC_TR2_LT2_0           (0x01U << ADC_TR2_LT2_Pos)                     /*!< 0x00000001 */
+#define ADC_TR2_LT2_1           (0x02U << ADC_TR2_LT2_Pos)                     /*!< 0x00000002 */
+#define ADC_TR2_LT2_2           (0x04U << ADC_TR2_LT2_Pos)                     /*!< 0x00000004 */
+#define ADC_TR2_LT2_3           (0x08U << ADC_TR2_LT2_Pos)                     /*!< 0x00000008 */
+#define ADC_TR2_LT2_4           (0x10U << ADC_TR2_LT2_Pos)                     /*!< 0x00000010 */
+#define ADC_TR2_LT2_5           (0x20U << ADC_TR2_LT2_Pos)                     /*!< 0x00000020 */
+#define ADC_TR2_LT2_6           (0x40U << ADC_TR2_LT2_Pos)                     /*!< 0x00000040 */
+#define ADC_TR2_LT2_7           (0x80U << ADC_TR2_LT2_Pos)                     /*!< 0x00000080 */
+
+#define ADC_TR2_HT2_Pos         (16U)                                          
+#define ADC_TR2_HT2_Msk         (0xFFU << ADC_TR2_HT2_Pos)                     /*!< 0x00FF0000 */
+#define ADC_TR2_HT2             ADC_TR2_HT2_Msk                                /*!< ADC analog watchdog 2 threshold high */
+#define ADC_TR2_HT2_0           (0x01U << ADC_TR2_HT2_Pos)                     /*!< 0x00010000 */
+#define ADC_TR2_HT2_1           (0x02U << ADC_TR2_HT2_Pos)                     /*!< 0x00020000 */
+#define ADC_TR2_HT2_2           (0x04U << ADC_TR2_HT2_Pos)                     /*!< 0x00040000 */
+#define ADC_TR2_HT2_3           (0x08U << ADC_TR2_HT2_Pos)                     /*!< 0x00080000 */
+#define ADC_TR2_HT2_4           (0x10U << ADC_TR2_HT2_Pos)                     /*!< 0x00100000 */
+#define ADC_TR2_HT2_5           (0x20U << ADC_TR2_HT2_Pos)                     /*!< 0x00200000 */
+#define ADC_TR2_HT2_6           (0x40U << ADC_TR2_HT2_Pos)                     /*!< 0x00400000 */
+#define ADC_TR2_HT2_7           (0x80U << ADC_TR2_HT2_Pos)                     /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_TR3 register  *******************/
+#define ADC_TR3_LT3_Pos         (0U)                                           
+#define ADC_TR3_LT3_Msk         (0xFFU << ADC_TR3_LT3_Pos)                     /*!< 0x000000FF */
+#define ADC_TR3_LT3             ADC_TR3_LT3_Msk                                /*!< ADC analog watchdog 3 threshold low */
+#define ADC_TR3_LT3_0           (0x01U << ADC_TR3_LT3_Pos)                     /*!< 0x00000001 */
+#define ADC_TR3_LT3_1           (0x02U << ADC_TR3_LT3_Pos)                     /*!< 0x00000002 */
+#define ADC_TR3_LT3_2           (0x04U << ADC_TR3_LT3_Pos)                     /*!< 0x00000004 */
+#define ADC_TR3_LT3_3           (0x08U << ADC_TR3_LT3_Pos)                     /*!< 0x00000008 */
+#define ADC_TR3_LT3_4           (0x10U << ADC_TR3_LT3_Pos)                     /*!< 0x00000010 */
+#define ADC_TR3_LT3_5           (0x20U << ADC_TR3_LT3_Pos)                     /*!< 0x00000020 */
+#define ADC_TR3_LT3_6           (0x40U << ADC_TR3_LT3_Pos)                     /*!< 0x00000040 */
+#define ADC_TR3_LT3_7           (0x80U << ADC_TR3_LT3_Pos)                     /*!< 0x00000080 */
+
+#define ADC_TR3_HT3_Pos         (16U)                                          
+#define ADC_TR3_HT3_Msk         (0xFFU << ADC_TR3_HT3_Pos)                     /*!< 0x00FF0000 */
+#define ADC_TR3_HT3             ADC_TR3_HT3_Msk                                /*!< ADC analog watchdog 3 threshold high */
+#define ADC_TR3_HT3_0           (0x01U << ADC_TR3_HT3_Pos)                     /*!< 0x00010000 */
+#define ADC_TR3_HT3_1           (0x02U << ADC_TR3_HT3_Pos)                     /*!< 0x00020000 */
+#define ADC_TR3_HT3_2           (0x04U << ADC_TR3_HT3_Pos)                     /*!< 0x00040000 */
+#define ADC_TR3_HT3_3           (0x08U << ADC_TR3_HT3_Pos)                     /*!< 0x00080000 */
+#define ADC_TR3_HT3_4           (0x10U << ADC_TR3_HT3_Pos)                     /*!< 0x00100000 */
+#define ADC_TR3_HT3_5           (0x20U << ADC_TR3_HT3_Pos)                     /*!< 0x00200000 */
+#define ADC_TR3_HT3_6           (0x40U << ADC_TR3_HT3_Pos)                     /*!< 0x00400000 */
+#define ADC_TR3_HT3_7           (0x80U << ADC_TR3_HT3_Pos)                     /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_SQR1 register  ******************/
+#define ADC_SQR1_L_Pos          (0U)                                           
+#define ADC_SQR1_L_Msk          (0xFU << ADC_SQR1_L_Pos)                       /*!< 0x0000000F */
+#define ADC_SQR1_L              ADC_SQR1_L_Msk                                 /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0            (0x1U << ADC_SQR1_L_Pos)                       /*!< 0x00000001 */
+#define ADC_SQR1_L_1            (0x2U << ADC_SQR1_L_Pos)                       /*!< 0x00000002 */
+#define ADC_SQR1_L_2            (0x4U << ADC_SQR1_L_Pos)                       /*!< 0x00000004 */
+#define ADC_SQR1_L_3            (0x8U << ADC_SQR1_L_Pos)                       /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos        (6U)                                           
+#define ADC_SQR1_SQ1_Msk        (0x1FU << ADC_SQR1_SQ1_Pos)                    /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1            ADC_SQR1_SQ1_Msk                               /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0          (0x01U << ADC_SQR1_SQ1_Pos)                    /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1          (0x02U << ADC_SQR1_SQ1_Pos)                    /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2          (0x04U << ADC_SQR1_SQ1_Pos)                    /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3          (0x08U << ADC_SQR1_SQ1_Pos)                    /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4          (0x10U << ADC_SQR1_SQ1_Pos)                    /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos        (12U)                                          
+#define ADC_SQR1_SQ2_Msk        (0x1FU << ADC_SQR1_SQ2_Pos)                    /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2            ADC_SQR1_SQ2_Msk                               /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0          (0x01U << ADC_SQR1_SQ2_Pos)                    /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1          (0x02U << ADC_SQR1_SQ2_Pos)                    /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2          (0x04U << ADC_SQR1_SQ2_Pos)                    /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3          (0x08U << ADC_SQR1_SQ2_Pos)                    /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4          (0x10U << ADC_SQR1_SQ2_Pos)                    /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos        (18U)                                          
+#define ADC_SQR1_SQ3_Msk        (0x1FU << ADC_SQR1_SQ3_Pos)                    /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3            ADC_SQR1_SQ3_Msk                               /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0          (0x01U << ADC_SQR1_SQ3_Pos)                    /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1          (0x02U << ADC_SQR1_SQ3_Pos)                    /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2          (0x04U << ADC_SQR1_SQ3_Pos)                    /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3          (0x08U << ADC_SQR1_SQ3_Pos)                    /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4          (0x10U << ADC_SQR1_SQ3_Pos)                    /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos        (24U)                                          
+#define ADC_SQR1_SQ4_Msk        (0x1FU << ADC_SQR1_SQ4_Pos)                    /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4            ADC_SQR1_SQ4_Msk                               /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0          (0x01U << ADC_SQR1_SQ4_Pos)                    /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1          (0x02U << ADC_SQR1_SQ4_Pos)                    /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2          (0x04U << ADC_SQR1_SQ4_Pos)                    /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3          (0x08U << ADC_SQR1_SQ4_Pos)                    /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4          (0x10U << ADC_SQR1_SQ4_Pos)                    /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ******************/
+#define ADC_SQR2_SQ5_Pos        (0U)                                           
+#define ADC_SQR2_SQ5_Msk        (0x1FU << ADC_SQR2_SQ5_Pos)                    /*!< 0x0000001F */
+#define ADC_SQR2_SQ5            ADC_SQR2_SQ5_Msk                               /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0          (0x01U << ADC_SQR2_SQ5_Pos)                    /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1          (0x02U << ADC_SQR2_SQ5_Pos)                    /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2          (0x04U << ADC_SQR2_SQ5_Pos)                    /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3          (0x08U << ADC_SQR2_SQ5_Pos)                    /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4          (0x10U << ADC_SQR2_SQ5_Pos)                    /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos        (6U)                                           
+#define ADC_SQR2_SQ6_Msk        (0x1FU << ADC_SQR2_SQ6_Pos)                    /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6            ADC_SQR2_SQ6_Msk                               /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0          (0x01U << ADC_SQR2_SQ6_Pos)                    /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1          (0x02U << ADC_SQR2_SQ6_Pos)                    /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2          (0x04U << ADC_SQR2_SQ6_Pos)                    /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3          (0x08U << ADC_SQR2_SQ6_Pos)                    /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4          (0x10U << ADC_SQR2_SQ6_Pos)                    /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos        (12U)                                          
+#define ADC_SQR2_SQ7_Msk        (0x1FU << ADC_SQR2_SQ7_Pos)                    /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7            ADC_SQR2_SQ7_Msk                               /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0          (0x01U << ADC_SQR2_SQ7_Pos)                    /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1          (0x02U << ADC_SQR2_SQ7_Pos)                    /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2          (0x04U << ADC_SQR2_SQ7_Pos)                    /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3          (0x08U << ADC_SQR2_SQ7_Pos)                    /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4          (0x10U << ADC_SQR2_SQ7_Pos)                    /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos        (18U)                                          
+#define ADC_SQR2_SQ8_Msk        (0x1FU << ADC_SQR2_SQ8_Pos)                    /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8            ADC_SQR2_SQ8_Msk                               /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0          (0x01U << ADC_SQR2_SQ8_Pos)                    /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1          (0x02U << ADC_SQR2_SQ8_Pos)                    /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2          (0x04U << ADC_SQR2_SQ8_Pos)                    /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3          (0x08U << ADC_SQR2_SQ8_Pos)                    /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4          (0x10U << ADC_SQR2_SQ8_Pos)                    /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos        (24U)                                          
+#define ADC_SQR2_SQ9_Msk        (0x1FU << ADC_SQR2_SQ9_Pos)                    /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9            ADC_SQR2_SQ9_Msk                               /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0          (0x01U << ADC_SQR2_SQ9_Pos)                    /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1          (0x02U << ADC_SQR2_SQ9_Pos)                    /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2          (0x04U << ADC_SQR2_SQ9_Pos)                    /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3          (0x08U << ADC_SQR2_SQ9_Pos)                    /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4          (0x10U << ADC_SQR2_SQ9_Pos)                    /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ******************/
+#define ADC_SQR3_SQ10_Pos       (0U)                                           
+#define ADC_SQR3_SQ10_Msk       (0x1FU << ADC_SQR3_SQ10_Pos)                   /*!< 0x0000001F */
+#define ADC_SQR3_SQ10           ADC_SQR3_SQ10_Msk                              /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0         (0x01U << ADC_SQR3_SQ10_Pos)                   /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1         (0x02U << ADC_SQR3_SQ10_Pos)                   /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2         (0x04U << ADC_SQR3_SQ10_Pos)                   /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3         (0x08U << ADC_SQR3_SQ10_Pos)                   /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4         (0x10U << ADC_SQR3_SQ10_Pos)                   /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos       (6U)                                           
+#define ADC_SQR3_SQ11_Msk       (0x1FU << ADC_SQR3_SQ11_Pos)                   /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11           ADC_SQR3_SQ11_Msk                              /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0         (0x01U << ADC_SQR3_SQ11_Pos)                   /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1         (0x02U << ADC_SQR3_SQ11_Pos)                   /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2         (0x04U << ADC_SQR3_SQ11_Pos)                   /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3         (0x08U << ADC_SQR3_SQ11_Pos)                   /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4         (0x10U << ADC_SQR3_SQ11_Pos)                   /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos       (12U)                                          
+#define ADC_SQR3_SQ12_Msk       (0x1FU << ADC_SQR3_SQ12_Pos)                   /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12           ADC_SQR3_SQ12_Msk                              /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0         (0x01U << ADC_SQR3_SQ12_Pos)                   /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1         (0x02U << ADC_SQR3_SQ12_Pos)                   /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2         (0x04U << ADC_SQR3_SQ12_Pos)                   /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3         (0x08U << ADC_SQR3_SQ12_Pos)                   /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4         (0x10U << ADC_SQR3_SQ12_Pos)                   /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos       (18U)                                          
+#define ADC_SQR3_SQ13_Msk       (0x1FU << ADC_SQR3_SQ13_Pos)                   /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13           ADC_SQR3_SQ13_Msk                              /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0         (0x01U << ADC_SQR3_SQ13_Pos)                   /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1         (0x02U << ADC_SQR3_SQ13_Pos)                   /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2         (0x04U << ADC_SQR3_SQ13_Pos)                   /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3         (0x08U << ADC_SQR3_SQ13_Pos)                   /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4         (0x10U << ADC_SQR3_SQ13_Pos)                   /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos       (24U)                                          
+#define ADC_SQR3_SQ14_Msk       (0x1FU << ADC_SQR3_SQ14_Pos)                   /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14           ADC_SQR3_SQ14_Msk                              /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0         (0x01U << ADC_SQR3_SQ14_Pos)                   /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1         (0x02U << ADC_SQR3_SQ14_Pos)                   /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2         (0x04U << ADC_SQR3_SQ14_Pos)                   /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3         (0x08U << ADC_SQR3_SQ14_Pos)                   /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4         (0x10U << ADC_SQR3_SQ14_Pos)                   /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ******************/
+#define ADC_SQR4_SQ15_Pos       (0U)                                           
+#define ADC_SQR4_SQ15_Msk       (0x1FU << ADC_SQR4_SQ15_Pos)                   /*!< 0x0000001F */
+#define ADC_SQR4_SQ15           ADC_SQR4_SQ15_Msk                              /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0         (0x01U << ADC_SQR4_SQ15_Pos)                   /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1         (0x02U << ADC_SQR4_SQ15_Pos)                   /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2         (0x04U << ADC_SQR4_SQ15_Pos)                   /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3         (0x08U << ADC_SQR4_SQ15_Pos)                   /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4         (0x10U << ADC_SQR4_SQ15_Pos)                   /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos       (6U)                                           
+#define ADC_SQR4_SQ16_Msk       (0x1FU << ADC_SQR4_SQ16_Pos)                   /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16           ADC_SQR4_SQ16_Msk                              /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0         (0x01U << ADC_SQR4_SQ16_Pos)                   /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1         (0x02U << ADC_SQR4_SQ16_Pos)                   /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2         (0x04U << ADC_SQR4_SQ16_Pos)                   /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3         (0x08U << ADC_SQR4_SQ16_Pos)                   /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4         (0x10U << ADC_SQR4_SQ16_Pos)                   /*!< 0x00000400 */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos        (0U)                                           
+#define ADC_DR_RDATA_Msk        (0xFFFFU << ADC_DR_RDATA_Pos)                  /*!< 0x0000FFFF */
+#define ADC_DR_RDATA            ADC_DR_RDATA_Msk                               /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0          (0x0001U << ADC_DR_RDATA_Pos)                  /*!< 0x00000001 */
+#define ADC_DR_RDATA_1          (0x0002U << ADC_DR_RDATA_Pos)                  /*!< 0x00000002 */
+#define ADC_DR_RDATA_2          (0x0004U << ADC_DR_RDATA_Pos)                  /*!< 0x00000004 */
+#define ADC_DR_RDATA_3          (0x0008U << ADC_DR_RDATA_Pos)                  /*!< 0x00000008 */
+#define ADC_DR_RDATA_4          (0x0010U << ADC_DR_RDATA_Pos)                  /*!< 0x00000010 */
+#define ADC_DR_RDATA_5          (0x0020U << ADC_DR_RDATA_Pos)                  /*!< 0x00000020 */
+#define ADC_DR_RDATA_6          (0x0040U << ADC_DR_RDATA_Pos)                  /*!< 0x00000040 */
+#define ADC_DR_RDATA_7          (0x0080U << ADC_DR_RDATA_Pos)                  /*!< 0x00000080 */
+#define ADC_DR_RDATA_8          (0x0100U << ADC_DR_RDATA_Pos)                  /*!< 0x00000100 */
+#define ADC_DR_RDATA_9          (0x0200U << ADC_DR_RDATA_Pos)                  /*!< 0x00000200 */
+#define ADC_DR_RDATA_10         (0x0400U << ADC_DR_RDATA_Pos)                  /*!< 0x00000400 */
+#define ADC_DR_RDATA_11         (0x0800U << ADC_DR_RDATA_Pos)                  /*!< 0x00000800 */
+#define ADC_DR_RDATA_12         (0x1000U << ADC_DR_RDATA_Pos)                  /*!< 0x00001000 */
+#define ADC_DR_RDATA_13         (0x2000U << ADC_DR_RDATA_Pos)                  /*!< 0x00002000 */
+#define ADC_DR_RDATA_14         (0x4000U << ADC_DR_RDATA_Pos)                  /*!< 0x00004000 */
+#define ADC_DR_RDATA_15         (0x8000U << ADC_DR_RDATA_Pos)                  /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JSQR register  ******************/
+#define ADC_JSQR_JL_Pos         (0U)                                           
+#define ADC_JSQR_JL_Msk         (0x3U << ADC_JSQR_JL_Pos)                      /*!< 0x00000003 */
+#define ADC_JSQR_JL             ADC_JSQR_JL_Msk                                /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0           (0x1U << ADC_JSQR_JL_Pos)                      /*!< 0x00000001 */
+#define ADC_JSQR_JL_1           (0x2U << ADC_JSQR_JL_Pos)                      /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos    (2U)                                           
+#define ADC_JSQR_JEXTSEL_Msk    (0xFU << ADC_JSQR_JEXTSEL_Pos)                 /*!< 0x0000003C */
+#define ADC_JSQR_JEXTSEL        ADC_JSQR_JEXTSEL_Msk                           /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0      (0x1U << ADC_JSQR_JEXTSEL_Pos)                 /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1      (0x2U << ADC_JSQR_JEXTSEL_Pos)                 /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2      (0x4U << ADC_JSQR_JEXTSEL_Pos)                 /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3      (0x8U << ADC_JSQR_JEXTSEL_Pos)                 /*!< 0x00000020 */
+
+#define ADC_JSQR_JEXTEN_Pos     (6U)                                           
+#define ADC_JSQR_JEXTEN_Msk     (0x3U << ADC_JSQR_JEXTEN_Pos)                  /*!< 0x000000C0 */
+#define ADC_JSQR_JEXTEN         ADC_JSQR_JEXTEN_Msk                            /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0       (0x1U << ADC_JSQR_JEXTEN_Pos)                  /*!< 0x00000040 */
+#define ADC_JSQR_JEXTEN_1       (0x2U << ADC_JSQR_JEXTEN_Pos)                  /*!< 0x00000080 */
+
+#define ADC_JSQR_JSQ1_Pos       (8U)                                           
+#define ADC_JSQR_JSQ1_Msk       (0x1FU << ADC_JSQR_JSQ1_Pos)                   /*!< 0x00001F00 */
+#define ADC_JSQR_JSQ1           ADC_JSQR_JSQ1_Msk                              /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0         (0x01U << ADC_JSQR_JSQ1_Pos)                   /*!< 0x00000100 */
+#define ADC_JSQR_JSQ1_1         (0x02U << ADC_JSQR_JSQ1_Pos)                   /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_2         (0x04U << ADC_JSQR_JSQ1_Pos)                   /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_3         (0x08U << ADC_JSQR_JSQ1_Pos)                   /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_4         (0x10U << ADC_JSQR_JSQ1_Pos)                   /*!< 0x00001000 */
+
+#define ADC_JSQR_JSQ2_Pos       (14U)                                          
+#define ADC_JSQR_JSQ2_Msk       (0x1FU << ADC_JSQR_JSQ2_Pos)                   /*!< 0x0007C000 */
+#define ADC_JSQR_JSQ2           ADC_JSQR_JSQ2_Msk                              /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0         (0x01U << ADC_JSQR_JSQ2_Pos)                   /*!< 0x00004000 */
+#define ADC_JSQR_JSQ2_1         (0x02U << ADC_JSQR_JSQ2_Pos)                   /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_2         (0x04U << ADC_JSQR_JSQ2_Pos)                   /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_3         (0x08U << ADC_JSQR_JSQ2_Pos)                   /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_4         (0x10U << ADC_JSQR_JSQ2_Pos)                   /*!< 0x00040000 */
+
+#define ADC_JSQR_JSQ3_Pos       (20U)                                          
+#define ADC_JSQR_JSQ3_Msk       (0x1FU << ADC_JSQR_JSQ3_Pos)                   /*!< 0x01F00000 */
+#define ADC_JSQR_JSQ3           ADC_JSQR_JSQ3_Msk                              /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0         (0x01U << ADC_JSQR_JSQ3_Pos)                   /*!< 0x00100000 */
+#define ADC_JSQR_JSQ3_1         (0x02U << ADC_JSQR_JSQ3_Pos)                   /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_2         (0x04U << ADC_JSQR_JSQ3_Pos)                   /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_3         (0x08U << ADC_JSQR_JSQ3_Pos)                   /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_4         (0x10U << ADC_JSQR_JSQ3_Pos)                   /*!< 0x01000000 */
+
+#define ADC_JSQR_JSQ4_Pos       (26U)                                          
+#define ADC_JSQR_JSQ4_Msk       (0x1FU << ADC_JSQR_JSQ4_Pos)                   /*!< 0x7C000000 */
+#define ADC_JSQR_JSQ4           ADC_JSQR_JSQ4_Msk                              /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0         (0x01U << ADC_JSQR_JSQ4_Pos)                   /*!< 0x04000000 */
+#define ADC_JSQR_JSQ4_1         (0x02U << ADC_JSQR_JSQ4_Pos)                   /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_2         (0x04U << ADC_JSQR_JSQ4_Pos)                   /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_3         (0x08U << ADC_JSQR_JSQ4_Pos)                   /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_4         (0x10U << ADC_JSQR_JSQ4_Pos)                   /*!< 0x40000000 */
+
+
+/********************  Bit definition for ADC_OFR1 register  ******************/
+#define ADC_OFR1_OFFSET1_Pos    (0U)                                           
+#define ADC_OFR1_OFFSET1_Msk    (0xFFFU << ADC_OFR1_OFFSET1_Pos)               /*!< 0x00000FFF */
+#define ADC_OFR1_OFFSET1        ADC_OFR1_OFFSET1_Msk                           /*!< ADC offset number 1 offset level */
+#define ADC_OFR1_OFFSET1_0      (0x001U << ADC_OFR1_OFFSET1_Pos)               /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1      (0x002U << ADC_OFR1_OFFSET1_Pos)               /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2      (0x004U << ADC_OFR1_OFFSET1_Pos)               /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3      (0x008U << ADC_OFR1_OFFSET1_Pos)               /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4      (0x010U << ADC_OFR1_OFFSET1_Pos)               /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5      (0x020U << ADC_OFR1_OFFSET1_Pos)               /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6      (0x040U << ADC_OFR1_OFFSET1_Pos)               /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7      (0x080U << ADC_OFR1_OFFSET1_Pos)               /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8      (0x100U << ADC_OFR1_OFFSET1_Pos)               /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9      (0x200U << ADC_OFR1_OFFSET1_Pos)               /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10     (0x400U << ADC_OFR1_OFFSET1_Pos)               /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11     (0x800U << ADC_OFR1_OFFSET1_Pos)               /*!< 0x00000800 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos (26U)                                          
+#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos)             /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH     ADC_OFR1_OFFSET1_CH_Msk                        /*!< ADC offset number 1 channel selection */
+#define ADC_OFR1_OFFSET1_CH_0   (0x01U << ADC_OFR1_OFFSET1_CH_Pos)             /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1   (0x02U << ADC_OFR1_OFFSET1_CH_Pos)             /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2   (0x04U << ADC_OFR1_OFFSET1_CH_Pos)             /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3   (0x08U << ADC_OFR1_OFFSET1_CH_Pos)             /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4   (0x10U << ADC_OFR1_OFFSET1_CH_Pos)             /*!< 0x40000000 */
+
+#define ADC_OFR1_OFFSET1_EN_Pos (31U)                                          
+#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos)              /*!< 0x80000000 */
+#define ADC_OFR1_OFFSET1_EN     ADC_OFR1_OFFSET1_EN_Msk                        /*!< ADC offset number 1 enable */
+
+/********************  Bit definition for ADC_OFR2 register  ******************/
+#define ADC_OFR2_OFFSET2_Pos    (0U)                                           
+#define ADC_OFR2_OFFSET2_Msk    (0xFFFU << ADC_OFR2_OFFSET2_Pos)               /*!< 0x00000FFF */
+#define ADC_OFR2_OFFSET2        ADC_OFR2_OFFSET2_Msk                           /*!< ADC offset number 2 offset level */
+#define ADC_OFR2_OFFSET2_0      (0x001U << ADC_OFR2_OFFSET2_Pos)               /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1      (0x002U << ADC_OFR2_OFFSET2_Pos)               /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2      (0x004U << ADC_OFR2_OFFSET2_Pos)               /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3      (0x008U << ADC_OFR2_OFFSET2_Pos)               /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4      (0x010U << ADC_OFR2_OFFSET2_Pos)               /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5      (0x020U << ADC_OFR2_OFFSET2_Pos)               /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6      (0x040U << ADC_OFR2_OFFSET2_Pos)               /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7      (0x080U << ADC_OFR2_OFFSET2_Pos)               /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8      (0x100U << ADC_OFR2_OFFSET2_Pos)               /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9      (0x200U << ADC_OFR2_OFFSET2_Pos)               /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10     (0x400U << ADC_OFR2_OFFSET2_Pos)               /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11     (0x800U << ADC_OFR2_OFFSET2_Pos)               /*!< 0x00000800 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos (26U)                                          
+#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos)             /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH     ADC_OFR2_OFFSET2_CH_Msk                        /*!< ADC offset number 2 channel selection */
+#define ADC_OFR2_OFFSET2_CH_0   (0x01U << ADC_OFR2_OFFSET2_CH_Pos)             /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1   (0x02U << ADC_OFR2_OFFSET2_CH_Pos)             /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2   (0x04U << ADC_OFR2_OFFSET2_CH_Pos)             /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3   (0x08U << ADC_OFR2_OFFSET2_CH_Pos)             /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4   (0x10U << ADC_OFR2_OFFSET2_CH_Pos)             /*!< 0x40000000 */
+
+#define ADC_OFR2_OFFSET2_EN_Pos (31U)                                          
+#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos)              /*!< 0x80000000 */
+#define ADC_OFR2_OFFSET2_EN     ADC_OFR2_OFFSET2_EN_Msk                        /*!< ADC offset number 2 enable */
+
+/********************  Bit definition for ADC_OFR3 register  ******************/
+#define ADC_OFR3_OFFSET3_Pos    (0U)                                           
+#define ADC_OFR3_OFFSET3_Msk    (0xFFFU << ADC_OFR3_OFFSET3_Pos)               /*!< 0x00000FFF */
+#define ADC_OFR3_OFFSET3        ADC_OFR3_OFFSET3_Msk                           /*!< ADC offset number 3 offset level */
+#define ADC_OFR3_OFFSET3_0      (0x001U << ADC_OFR3_OFFSET3_Pos)               /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1      (0x002U << ADC_OFR3_OFFSET3_Pos)               /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2      (0x004U << ADC_OFR3_OFFSET3_Pos)               /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3      (0x008U << ADC_OFR3_OFFSET3_Pos)               /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4      (0x010U << ADC_OFR3_OFFSET3_Pos)               /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5      (0x020U << ADC_OFR3_OFFSET3_Pos)               /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6      (0x040U << ADC_OFR3_OFFSET3_Pos)               /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7      (0x080U << ADC_OFR3_OFFSET3_Pos)               /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8      (0x100U << ADC_OFR3_OFFSET3_Pos)               /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9      (0x200U << ADC_OFR3_OFFSET3_Pos)               /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10     (0x400U << ADC_OFR3_OFFSET3_Pos)               /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11     (0x800U << ADC_OFR3_OFFSET3_Pos)               /*!< 0x00000800 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos (26U)                                          
+#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos)             /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH     ADC_OFR3_OFFSET3_CH_Msk                        /*!< ADC offset number 3 channel selection */
+#define ADC_OFR3_OFFSET3_CH_0   (0x01U << ADC_OFR3_OFFSET3_CH_Pos)             /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1   (0x02U << ADC_OFR3_OFFSET3_CH_Pos)             /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2   (0x04U << ADC_OFR3_OFFSET3_CH_Pos)             /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3   (0x08U << ADC_OFR3_OFFSET3_CH_Pos)             /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4   (0x10U << ADC_OFR3_OFFSET3_CH_Pos)             /*!< 0x40000000 */
+
+#define ADC_OFR3_OFFSET3_EN_Pos (31U)                                          
+#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos)              /*!< 0x80000000 */
+#define ADC_OFR3_OFFSET3_EN     ADC_OFR3_OFFSET3_EN_Msk                        /*!< ADC offset number 3 enable */
+
+/********************  Bit definition for ADC_OFR4 register  ******************/
+#define ADC_OFR4_OFFSET4_Pos    (0U)                                           
+#define ADC_OFR4_OFFSET4_Msk    (0xFFFU << ADC_OFR4_OFFSET4_Pos)               /*!< 0x00000FFF */
+#define ADC_OFR4_OFFSET4        ADC_OFR4_OFFSET4_Msk                           /*!< ADC offset number 4 offset level */
+#define ADC_OFR4_OFFSET4_0      (0x001U << ADC_OFR4_OFFSET4_Pos)               /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1      (0x002U << ADC_OFR4_OFFSET4_Pos)               /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2      (0x004U << ADC_OFR4_OFFSET4_Pos)               /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3      (0x008U << ADC_OFR4_OFFSET4_Pos)               /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4      (0x010U << ADC_OFR4_OFFSET4_Pos)               /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5      (0x020U << ADC_OFR4_OFFSET4_Pos)               /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6      (0x040U << ADC_OFR4_OFFSET4_Pos)               /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7      (0x080U << ADC_OFR4_OFFSET4_Pos)               /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8      (0x100U << ADC_OFR4_OFFSET4_Pos)               /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9      (0x200U << ADC_OFR4_OFFSET4_Pos)               /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10     (0x400U << ADC_OFR4_OFFSET4_Pos)               /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11     (0x800U << ADC_OFR4_OFFSET4_Pos)               /*!< 0x00000800 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos (26U)                                          
+#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos)             /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH     ADC_OFR4_OFFSET4_CH_Msk                        /*!< ADC offset number 4 channel selection */
+#define ADC_OFR4_OFFSET4_CH_0   (0x01U << ADC_OFR4_OFFSET4_CH_Pos)             /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1   (0x02U << ADC_OFR4_OFFSET4_CH_Pos)             /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2   (0x04U << ADC_OFR4_OFFSET4_CH_Pos)             /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3   (0x08U << ADC_OFR4_OFFSET4_CH_Pos)             /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4   (0x10U << ADC_OFR4_OFFSET4_CH_Pos)             /*!< 0x40000000 */
+
+#define ADC_OFR4_OFFSET4_EN_Pos (31U)                                          
+#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos)              /*!< 0x80000000 */
+#define ADC_OFR4_OFFSET4_EN     ADC_OFR4_OFFSET4_EN_Msk                        /*!< ADC offset number 4 enable */
+
+/********************  Bit definition for ADC_JDR1 register  ******************/
+#define ADC_JDR1_JDATA_Pos      (0U)                                           
+#define ADC_JDR1_JDATA_Msk      (0xFFFFU << ADC_JDR1_JDATA_Pos)                /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA          ADC_JDR1_JDATA_Msk                             /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0        (0x0001U << ADC_JDR1_JDATA_Pos)                /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1        (0x0002U << ADC_JDR1_JDATA_Pos)                /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2        (0x0004U << ADC_JDR1_JDATA_Pos)                /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3        (0x0008U << ADC_JDR1_JDATA_Pos)                /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4        (0x0010U << ADC_JDR1_JDATA_Pos)                /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5        (0x0020U << ADC_JDR1_JDATA_Pos)                /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6        (0x0040U << ADC_JDR1_JDATA_Pos)                /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7        (0x0080U << ADC_JDR1_JDATA_Pos)                /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8        (0x0100U << ADC_JDR1_JDATA_Pos)                /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9        (0x0200U << ADC_JDR1_JDATA_Pos)                /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10       (0x0400U << ADC_JDR1_JDATA_Pos)                /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11       (0x0800U << ADC_JDR1_JDATA_Pos)                /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12       (0x1000U << ADC_JDR1_JDATA_Pos)                /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13       (0x2000U << ADC_JDR1_JDATA_Pos)                /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14       (0x4000U << ADC_JDR1_JDATA_Pos)                /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15       (0x8000U << ADC_JDR1_JDATA_Pos)                /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR2 register  ******************/
+#define ADC_JDR2_JDATA_Pos      (0U)                                           
+#define ADC_JDR2_JDATA_Msk      (0xFFFFU << ADC_JDR2_JDATA_Pos)                /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA          ADC_JDR2_JDATA_Msk                             /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0        (0x0001U << ADC_JDR2_JDATA_Pos)                /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1        (0x0002U << ADC_JDR2_JDATA_Pos)                /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2        (0x0004U << ADC_JDR2_JDATA_Pos)                /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3        (0x0008U << ADC_JDR2_JDATA_Pos)                /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4        (0x0010U << ADC_JDR2_JDATA_Pos)                /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5        (0x0020U << ADC_JDR2_JDATA_Pos)                /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6        (0x0040U << ADC_JDR2_JDATA_Pos)                /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7        (0x0080U << ADC_JDR2_JDATA_Pos)                /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8        (0x0100U << ADC_JDR2_JDATA_Pos)                /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9        (0x0200U << ADC_JDR2_JDATA_Pos)                /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10       (0x0400U << ADC_JDR2_JDATA_Pos)                /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11       (0x0800U << ADC_JDR2_JDATA_Pos)                /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12       (0x1000U << ADC_JDR2_JDATA_Pos)                /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13       (0x2000U << ADC_JDR2_JDATA_Pos)                /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14       (0x4000U << ADC_JDR2_JDATA_Pos)                /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15       (0x8000U << ADC_JDR2_JDATA_Pos)                /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR3 register  ******************/
+#define ADC_JDR3_JDATA_Pos      (0U)                                           
+#define ADC_JDR3_JDATA_Msk      (0xFFFFU << ADC_JDR3_JDATA_Pos)                /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA          ADC_JDR3_JDATA_Msk                             /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0        (0x0001U << ADC_JDR3_JDATA_Pos)                /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1        (0x0002U << ADC_JDR3_JDATA_Pos)                /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2        (0x0004U << ADC_JDR3_JDATA_Pos)                /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3        (0x0008U << ADC_JDR3_JDATA_Pos)                /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4        (0x0010U << ADC_JDR3_JDATA_Pos)                /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5        (0x0020U << ADC_JDR3_JDATA_Pos)                /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6        (0x0040U << ADC_JDR3_JDATA_Pos)                /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7        (0x0080U << ADC_JDR3_JDATA_Pos)                /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8        (0x0100U << ADC_JDR3_JDATA_Pos)                /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9        (0x0200U << ADC_JDR3_JDATA_Pos)                /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10       (0x0400U << ADC_JDR3_JDATA_Pos)                /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11       (0x0800U << ADC_JDR3_JDATA_Pos)                /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12       (0x1000U << ADC_JDR3_JDATA_Pos)                /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13       (0x2000U << ADC_JDR3_JDATA_Pos)                /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14       (0x4000U << ADC_JDR3_JDATA_Pos)                /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15       (0x8000U << ADC_JDR3_JDATA_Pos)                /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR4 register  ******************/
+#define ADC_JDR4_JDATA_Pos      (0U)                                           
+#define ADC_JDR4_JDATA_Msk      (0xFFFFU << ADC_JDR4_JDATA_Pos)                /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA          ADC_JDR4_JDATA_Msk                             /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0        (0x0001U << ADC_JDR4_JDATA_Pos)                /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1        (0x0002U << ADC_JDR4_JDATA_Pos)                /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2        (0x0004U << ADC_JDR4_JDATA_Pos)                /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3        (0x0008U << ADC_JDR4_JDATA_Pos)                /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4        (0x0010U << ADC_JDR4_JDATA_Pos)                /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5        (0x0020U << ADC_JDR4_JDATA_Pos)                /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6        (0x0040U << ADC_JDR4_JDATA_Pos)                /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7        (0x0080U << ADC_JDR4_JDATA_Pos)                /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8        (0x0100U << ADC_JDR4_JDATA_Pos)                /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9        (0x0200U << ADC_JDR4_JDATA_Pos)                /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10       (0x0400U << ADC_JDR4_JDATA_Pos)                /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11       (0x0800U << ADC_JDR4_JDATA_Pos)                /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12       (0x1000U << ADC_JDR4_JDATA_Pos)                /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13       (0x2000U << ADC_JDR4_JDATA_Pos)                /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14       (0x4000U << ADC_JDR4_JDATA_Pos)                /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15       (0x8000U << ADC_JDR4_JDATA_Pos)                /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ****************/
+#define ADC_AWD2CR_AWD2CH_Pos   (0U)                                           
+#define ADC_AWD2CR_AWD2CH_Msk   (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x0007FFFF */
+#define ADC_AWD2CR_AWD2CH       ADC_AWD2CR_AWD2CH_Msk                          /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0     (0x00001U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1     (0x00002U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2     (0x00004U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3     (0x00008U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4     (0x00010U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5     (0x00020U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6     (0x00040U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7     (0x00080U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8     (0x00100U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9     (0x00200U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10    (0x00400U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11    (0x00800U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12    (0x01000U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13    (0x02000U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14    (0x04000U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15    (0x08000U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16    (0x10000U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17    (0x20000U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18    (0x40000U << ADC_AWD2CR_AWD2CH_Pos)            /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ****************/
+#define ADC_AWD3CR_AWD3CH_Pos   (0U)                                           
+#define ADC_AWD3CR_AWD3CH_Msk   (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x0007FFFF */
+#define ADC_AWD3CR_AWD3CH       ADC_AWD3CR_AWD3CH_Msk                          /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0     (0x00001U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1     (0x00002U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2     (0x00004U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3     (0x00008U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4     (0x00010U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5     (0x00020U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6     (0x00040U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7     (0x00080U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8     (0x00100U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9     (0x00200U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10    (0x00400U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11    (0x00800U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12    (0x01000U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13    (0x02000U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14    (0x04000U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15    (0x08000U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16    (0x10000U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17    (0x20000U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18    (0x40000U << ADC_AWD3CR_AWD3CH_Pos)            /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ****************/
+#define ADC_DIFSEL_DIFSEL_Pos   (0U)                                           
+#define ADC_DIFSEL_DIFSEL_Msk   (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x0007FFFF */
+#define ADC_DIFSEL_DIFSEL       ADC_DIFSEL_DIFSEL_Msk                          /*!< ADC channel differential or single-ended mode */
+#define ADC_DIFSEL_DIFSEL_0     (0x00001U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1     (0x00002U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2     (0x00004U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3     (0x00008U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4     (0x00010U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5     (0x00020U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6     (0x00040U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7     (0x00080U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8     (0x00100U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9     (0x00200U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10    (0x00400U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11    (0x00800U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12    (0x01000U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13    (0x02000U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14    (0x04000U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15    (0x08000U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16    (0x10000U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17    (0x20000U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18    (0x40000U << ADC_DIFSEL_DIFSEL_Pos)            /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_CALFACT register  ***************/
+#define ADC_CALFACT_CALFACT_S_Pos (0U)                                         
+#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos)         /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT_S   ADC_CALFACT_CALFACT_S_Msk                      /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos)           /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos)           /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos)           /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos)           /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos)           /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos)           /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos)           /*!< 0x00000040 */
+
+#define ADC_CALFACT_CALFACT_D_Pos (16U)                                        
+#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos)         /*!< 0x007F0000 */
+#define ADC_CALFACT_CALFACT_D   ADC_CALFACT_CALFACT_D_Msk                      /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos)           /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos)           /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos)           /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos)           /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos)           /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos)           /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos)           /*!< 0x00400000 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  *******************/
+#define ADC_CSR_ADRDY_MST_Pos   (0U)                                           
+#define ADC_CSR_ADRDY_MST_Msk   (0x1U << ADC_CSR_ADRDY_MST_Pos)                /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST       ADC_CSR_ADRDY_MST_Msk                          /*!< ADC multimode master ready flag */
+#define ADC_CSR_EOSMP_MST_Pos   (1U)                                           
+#define ADC_CSR_EOSMP_MST_Msk   (0x1U << ADC_CSR_EOSMP_MST_Pos)                /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST       ADC_CSR_EOSMP_MST_Msk                          /*!< ADC multimode master group regular end of sampling flag */
+#define ADC_CSR_EOC_MST_Pos     (2U)                                           
+#define ADC_CSR_EOC_MST_Msk     (0x1U << ADC_CSR_EOC_MST_Pos)                  /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST         ADC_CSR_EOC_MST_Msk                            /*!< ADC multimode master group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_MST_Pos     (3U)                                           
+#define ADC_CSR_EOS_MST_Msk     (0x1U << ADC_CSR_EOS_MST_Pos)                  /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST         ADC_CSR_EOS_MST_Msk                            /*!< ADC multimode master group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_MST_Pos     (4U)                                           
+#define ADC_CSR_OVR_MST_Msk     (0x1U << ADC_CSR_OVR_MST_Pos)                  /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST         ADC_CSR_OVR_MST_Msk                            /*!< ADC multimode master group regular overrun flag */
+#define ADC_CSR_JEOC_MST_Pos    (5U)                                           
+#define ADC_CSR_JEOC_MST_Msk    (0x1U << ADC_CSR_JEOC_MST_Pos)                 /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST        ADC_CSR_JEOC_MST_Msk                           /*!< ADC multimode master group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_MST_Pos    (6U)                                           
+#define ADC_CSR_JEOS_MST_Msk    (0x1U << ADC_CSR_JEOS_MST_Pos)                 /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST        ADC_CSR_JEOS_MST_Msk                           /*!< ADC multimode master group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_MST_Pos    (7U)                                           
+#define ADC_CSR_AWD1_MST_Msk    (0x1U << ADC_CSR_AWD1_MST_Pos)                 /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST        ADC_CSR_AWD1_MST_Msk                           /*!< ADC multimode master analog watchdog 1 flag */
+#define ADC_CSR_AWD2_MST_Pos    (8U)                                           
+#define ADC_CSR_AWD2_MST_Msk    (0x1U << ADC_CSR_AWD2_MST_Pos)                 /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST        ADC_CSR_AWD2_MST_Msk                           /*!< ADC multimode master analog watchdog 2 flag */
+#define ADC_CSR_AWD3_MST_Pos    (9U)                                           
+#define ADC_CSR_AWD3_MST_Msk    (0x1U << ADC_CSR_AWD3_MST_Pos)                 /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST        ADC_CSR_AWD3_MST_Msk                           /*!< ADC multimode master analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_MST_Pos   (10U)                                          
+#define ADC_CSR_JQOVF_MST_Msk   (0x1U << ADC_CSR_JQOVF_MST_Pos)                /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST       ADC_CSR_JQOVF_MST_Msk                          /*!< ADC multimode master group injected contexts queue overflow flag */
+
+#define ADC_CSR_ADRDY_SLV_Pos   (16U)                                          
+#define ADC_CSR_ADRDY_SLV_Msk   (0x1U << ADC_CSR_ADRDY_SLV_Pos)                /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV       ADC_CSR_ADRDY_SLV_Msk                          /*!< ADC multimode slave ready flag */
+#define ADC_CSR_EOSMP_SLV_Pos   (17U)                                          
+#define ADC_CSR_EOSMP_SLV_Msk   (0x1U << ADC_CSR_EOSMP_SLV_Pos)                /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV       ADC_CSR_EOSMP_SLV_Msk                          /*!< ADC multimode slave group regular end of sampling flag */
+#define ADC_CSR_EOC_SLV_Pos     (18U)                                          
+#define ADC_CSR_EOC_SLV_Msk     (0x1U << ADC_CSR_EOC_SLV_Pos)                  /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV         ADC_CSR_EOC_SLV_Msk                            /*!< ADC multimode slave group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_SLV_Pos     (19U)                                          
+#define ADC_CSR_EOS_SLV_Msk     (0x1U << ADC_CSR_EOS_SLV_Pos)                  /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV         ADC_CSR_EOS_SLV_Msk                            /*!< ADC multimode slave group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_SLV_Pos     (20U)                                          
+#define ADC_CSR_OVR_SLV_Msk     (0x1U << ADC_CSR_OVR_SLV_Pos)                  /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV         ADC_CSR_OVR_SLV_Msk                            /*!< ADC multimode slave group regular overrun flag */
+#define ADC_CSR_JEOC_SLV_Pos    (21U)                                          
+#define ADC_CSR_JEOC_SLV_Msk    (0x1U << ADC_CSR_JEOC_SLV_Pos)                 /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV        ADC_CSR_JEOC_SLV_Msk                           /*!< ADC multimode slave group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_SLV_Pos    (22U)                                          
+#define ADC_CSR_JEOS_SLV_Msk    (0x1U << ADC_CSR_JEOS_SLV_Pos)                 /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV        ADC_CSR_JEOS_SLV_Msk                           /*!< ADC multimode slave group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_SLV_Pos    (23U)                                          
+#define ADC_CSR_AWD1_SLV_Msk    (0x1U << ADC_CSR_AWD1_SLV_Pos)                 /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV        ADC_CSR_AWD1_SLV_Msk                           /*!< ADC multimode slave analog watchdog 1 flag */
+#define ADC_CSR_AWD2_SLV_Pos    (24U)                                          
+#define ADC_CSR_AWD2_SLV_Msk    (0x1U << ADC_CSR_AWD2_SLV_Pos)                 /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV        ADC_CSR_AWD2_SLV_Msk                           /*!< ADC multimode slave analog watchdog 2 flag */
+#define ADC_CSR_AWD3_SLV_Pos    (25U)                                          
+#define ADC_CSR_AWD3_SLV_Msk    (0x1U << ADC_CSR_AWD3_SLV_Pos)                 /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV        ADC_CSR_AWD3_SLV_Msk                           /*!< ADC multimode slave analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_SLV_Pos   (26U)                                          
+#define ADC_CSR_JQOVF_SLV_Msk   (0x1U << ADC_CSR_JQOVF_SLV_Pos)                /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV       ADC_CSR_JQOVF_SLV_Msk                          /*!< ADC multimode slave group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_CCR register  *******************/
+#define ADC_CCR_DUAL_Pos        (0U)                                           
+#define ADC_CCR_DUAL_Msk        (0x1FU << ADC_CCR_DUAL_Pos)                    /*!< 0x0000001F */
+#define ADC_CCR_DUAL            ADC_CCR_DUAL_Msk                               /*!< ADC multimode mode selection */
+#define ADC_CCR_DUAL_0          (0x01U << ADC_CCR_DUAL_Pos)                    /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1          (0x02U << ADC_CCR_DUAL_Pos)                    /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2          (0x04U << ADC_CCR_DUAL_Pos)                    /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3          (0x08U << ADC_CCR_DUAL_Pos)                    /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4          (0x10U << ADC_CCR_DUAL_Pos)                    /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos       (8U)                                           
+#define ADC_CCR_DELAY_Msk       (0xFU << ADC_CCR_DELAY_Pos)                    /*!< 0x00000F00 */
+#define ADC_CCR_DELAY           ADC_CCR_DELAY_Msk                              /*!< ADC multimode delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0         (0x1U << ADC_CCR_DELAY_Pos)                    /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1         (0x2U << ADC_CCR_DELAY_Pos)                    /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2         (0x4U << ADC_CCR_DELAY_Pos)                    /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3         (0x8U << ADC_CCR_DELAY_Pos)                    /*!< 0x00000800 */
+
+#define ADC_CCR_DMACFG_Pos      (13U)                                          
+#define ADC_CCR_DMACFG_Msk      (0x1U << ADC_CCR_DMACFG_Pos)                   /*!< 0x00002000 */
+#define ADC_CCR_DMACFG          ADC_CCR_DMACFG_Msk                             /*!< ADC multimode DMA transfer configuration */
+
+#define ADC_CCR_MDMA_Pos        (14U)                                          
+#define ADC_CCR_MDMA_Msk        (0x3U << ADC_CCR_MDMA_Pos)                     /*!< 0x0000C000 */
+#define ADC_CCR_MDMA            ADC_CCR_MDMA_Msk                               /*!< ADC multimode DMA transfer enable */
+#define ADC_CCR_MDMA_0          (0x1U << ADC_CCR_MDMA_Pos)                     /*!< 0x00004000 */
+#define ADC_CCR_MDMA_1          (0x2U << ADC_CCR_MDMA_Pos)                     /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos      (16U)                                          
+#define ADC_CCR_CKMODE_Msk      (0x3U << ADC_CCR_CKMODE_Pos)                   /*!< 0x00030000 */
+#define ADC_CCR_CKMODE          ADC_CCR_CKMODE_Msk                             /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
+#define ADC_CCR_CKMODE_0        (0x1U << ADC_CCR_CKMODE_Pos)                   /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1        (0x2U << ADC_CCR_CKMODE_Pos)                   /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos       (18U)                                          
+#define ADC_CCR_PRESC_Msk       (0xFU << ADC_CCR_PRESC_Pos)                    /*!< 0x003C0000 */
+#define ADC_CCR_PRESC           ADC_CCR_PRESC_Msk                              /*!< ADC common clock prescaler, only for clock source asynchronous */
+#define ADC_CCR_PRESC_0         (0x1U << ADC_CCR_PRESC_Pos)                    /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1         (0x2U << ADC_CCR_PRESC_Pos)                    /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2         (0x4U << ADC_CCR_PRESC_Pos)                    /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3         (0x8U << ADC_CCR_PRESC_Pos)                    /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos      (22U)                                          
+#define ADC_CCR_VREFEN_Msk      (0x1U << ADC_CCR_VREFEN_Pos)                   /*!< 0x00400000 */
+#define ADC_CCR_VREFEN          ADC_CCR_VREFEN_Msk                             /*!< ADC internal path to VrefInt enable */
+#define ADC_CCR_TSEN_Pos        (23U)                                          
+#define ADC_CCR_TSEN_Msk        (0x1U << ADC_CCR_TSEN_Pos)                     /*!< 0x00800000 */
+#define ADC_CCR_TSEN            ADC_CCR_TSEN_Msk                               /*!< ADC internal path to temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos      (24U)                                          
+#define ADC_CCR_VBATEN_Msk      (0x1U << ADC_CCR_VBATEN_Pos)                   /*!< 0x01000000 */
+#define ADC_CCR_VBATEN          ADC_CCR_VBATEN_Msk                             /*!< ADC internal path to battery voltage enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos   (0U)                                           
+#define ADC_CDR_RDATA_MST_Msk   (0xFFFFU << ADC_CDR_RDATA_MST_Pos)             /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST       ADC_CDR_RDATA_MST_Msk                          /*!< ADC multimode master group regular conversion data */
+#define ADC_CDR_RDATA_MST_0     (0x0001U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00000001 */
+#define ADC_CDR_RDATA_MST_1     (0x0002U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00000002 */
+#define ADC_CDR_RDATA_MST_2     (0x0004U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00000004 */
+#define ADC_CDR_RDATA_MST_3     (0x0008U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00000008 */
+#define ADC_CDR_RDATA_MST_4     (0x0010U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00000010 */
+#define ADC_CDR_RDATA_MST_5     (0x0020U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00000020 */
+#define ADC_CDR_RDATA_MST_6     (0x0040U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00000040 */
+#define ADC_CDR_RDATA_MST_7     (0x0080U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00000080 */
+#define ADC_CDR_RDATA_MST_8     (0x0100U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00000100 */
+#define ADC_CDR_RDATA_MST_9     (0x0200U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00000200 */
+#define ADC_CDR_RDATA_MST_10    (0x0400U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00000400 */
+#define ADC_CDR_RDATA_MST_11    (0x0800U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00000800 */
+#define ADC_CDR_RDATA_MST_12    (0x1000U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00001000 */
+#define ADC_CDR_RDATA_MST_13    (0x2000U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00002000 */
+#define ADC_CDR_RDATA_MST_14    (0x4000U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00004000 */
+#define ADC_CDR_RDATA_MST_15    (0x8000U << ADC_CDR_RDATA_MST_Pos)             /*!< 0x00008000 */
+
+#define ADC_CDR_RDATA_SLV_Pos   (16U)                                          
+#define ADC_CDR_RDATA_SLV_Msk   (0xFFFFU << ADC_CDR_RDATA_SLV_Pos)             /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV       ADC_CDR_RDATA_SLV_Msk                          /*!< ADC multimode slave group regular conversion data */
+#define ADC_CDR_RDATA_SLV_0     (0x0001U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x00010000 */
+#define ADC_CDR_RDATA_SLV_1     (0x0002U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x00020000 */
+#define ADC_CDR_RDATA_SLV_2     (0x0004U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x00040000 */
+#define ADC_CDR_RDATA_SLV_3     (0x0008U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x00080000 */
+#define ADC_CDR_RDATA_SLV_4     (0x0010U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x00100000 */
+#define ADC_CDR_RDATA_SLV_5     (0x0020U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x00200000 */
+#define ADC_CDR_RDATA_SLV_6     (0x0040U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x00400000 */
+#define ADC_CDR_RDATA_SLV_7     (0x0080U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x00800000 */
+#define ADC_CDR_RDATA_SLV_8     (0x0100U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x01000000 */
+#define ADC_CDR_RDATA_SLV_9     (0x0200U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x02000000 */
+#define ADC_CDR_RDATA_SLV_10    (0x0400U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x04000000 */
+#define ADC_CDR_RDATA_SLV_11    (0x0800U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x08000000 */
+#define ADC_CDR_RDATA_SLV_12    (0x1000U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x10000000 */
+#define ADC_CDR_RDATA_SLV_13    (0x2000U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x20000000 */
+#define ADC_CDR_RDATA_SLV_14    (0x4000U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x40000000 */
+#define ADC_CDR_RDATA_SLV_15    (0x8000U << ADC_CDR_RDATA_SLV_Pos)             /*!< 0x80000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define CAN_MCR_INRQ_Pos       (0U)                                            
+#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
+#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos      (1U)                                            
+#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
+#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos       (2U)                                            
+#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
+#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos       (3U)                                            
+#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
+#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos       (4U)                                            
+#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
+#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos       (5U)                                            
+#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
+#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos       (6U)                                            
+#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
+#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos       (7U)                                            
+#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
+#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos      (15U)                                           
+#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
+#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define CAN_MSR_INAK_Pos       (0U)                                            
+#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
+#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos       (1U)                                            
+#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
+#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos       (2U)                                            
+#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
+#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos       (3U)                                            
+#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
+#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos      (4U)                                            
+#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
+#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos        (8U)                                            
+#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
+#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos        (9U)                                            
+#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
+#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos       (10U)                                           
+#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
+#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos         (11U)                                           
+#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
+#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define CAN_TSR_RQCP0_Pos      (0U)                                            
+#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
+#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos      (1U)                                            
+#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
+#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos      (2U)                                            
+#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
+#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos      (3U)                                            
+#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
+#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos      (7U)                                            
+#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos      (8U)                                            
+#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
+#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos      (9U)                                            
+#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
+#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos      (10U)                                           
+#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
+#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos      (11U)                                           
+#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
+#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos      (15U)                                           
+#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos      (16U)                                           
+#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
+#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos      (17U)                                           
+#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
+#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos      (18U)                                           
+#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
+#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos      (19U)                                           
+#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
+#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos      (23U)                                           
+#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos       (24U)                                           
+#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
+#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos        (26U)                                           
+#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
+#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos       (26U)                                           
+#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
+#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos       (27U)                                           
+#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
+#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos       (28U)                                           
+#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
+#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos        (29U)                                           
+#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
+#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos       (29U)                                           
+#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
+#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos       (30U)                                           
+#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
+#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos       (31U)                                           
+#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
+#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define CAN_RF0R_FMP0_Pos      (0U)                                            
+#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
+#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos     (3U)                                            
+#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
+#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos     (4U)                                            
+#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos     (5U)                                            
+#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define CAN_RF1R_FMP1_Pos      (0U)                                            
+#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
+#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos     (3U)                                            
+#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
+#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos     (4U)                                            
+#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos     (5U)                                            
+#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define CAN_IER_TMEIE_Pos      (0U)                                            
+#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
+#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos     (1U)                                            
+#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
+#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos      (2U)                                            
+#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
+#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos     (3U)                                            
+#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
+#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos     (4U)                                            
+#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
+#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos      (5U)                                            
+#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
+#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos     (6U)                                            
+#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
+#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
+#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos      (9U)                                            
+#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
+#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos      (10U)                                           
+#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
+#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos      (11U)                                           
+#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
+#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos      (15U)                                           
+#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
+#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos      (16U)                                           
+#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
+#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos      (17U)                                           
+#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
+#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define CAN_ESR_EWGF_Pos       (0U)                                            
+#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
+#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos       (1U)                                            
+#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
+#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos       (2U)                                            
+#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
+#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos        (4U)                                            
+#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
+#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
+#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
+#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos        (16U)                                           
+#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
+#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos        (24U)                                           
+#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
+#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define CAN_BTR_BRP_Pos        (0U)                                            
+#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
+#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos        (16U)                                           
+#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
+#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
+#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
+#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
+#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos        (20U)                                           
+#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
+#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
+#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
+#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos        (24U)                                           
+#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
+#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
+#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos       (30U)                                           
+#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
+#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos       (31U)                                           
+#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
+#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define CAN_TI0R_TXRQ_Pos      (0U)                                            
+#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos       (1U)                                            
+#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos       (2U)                                            
+#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos      (3U)                                            
+#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos      (21U)                                           
+#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define CAN_TDT0R_DLC_Pos      (0U)                                            
+#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos      (8U)                                            
+#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos     (16U)                                           
+#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define CAN_TDL0R_DATA0_Pos    (0U)                                            
+#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos    (8U)                                            
+#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos    (16U)                                           
+#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos    (24U)                                           
+#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define CAN_TDH0R_DATA4_Pos    (0U)                                            
+#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos    (8U)                                            
+#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos    (16U)                                           
+#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos    (24U)                                           
+#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define CAN_TI1R_TXRQ_Pos      (0U)                                            
+#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos       (1U)                                            
+#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos       (2U)                                            
+#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos      (3U)                                            
+#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos      (21U)                                           
+#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define CAN_TDT1R_DLC_Pos      (0U)                                            
+#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos      (8U)                                            
+#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos     (16U)                                           
+#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define CAN_TDL1R_DATA0_Pos    (0U)                                            
+#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos    (8U)                                            
+#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos    (16U)                                           
+#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos    (24U)                                           
+#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define CAN_TDH1R_DATA4_Pos    (0U)                                            
+#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos    (8U)                                            
+#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos    (16U)                                           
+#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos    (24U)                                           
+#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define CAN_TI2R_TXRQ_Pos      (0U)                                            
+#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos       (1U)                                            
+#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos       (2U)                                            
+#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos      (3U)                                            
+#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos      (21U)                                           
+#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/
+#define CAN_TDT2R_DLC_Pos      (0U)                                            
+#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos      (8U)                                            
+#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos     (16U)                                           
+#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define CAN_TDL2R_DATA0_Pos    (0U)                                            
+#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos    (8U)                                            
+#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos    (16U)                                           
+#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos    (24U)                                           
+#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define CAN_TDH2R_DATA4_Pos    (0U)                                            
+#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos    (8U)                                            
+#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos    (16U)                                           
+#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos    (24U)                                           
+#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define CAN_RI0R_RTR_Pos       (1U)                                            
+#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos       (2U)                                            
+#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos      (3U)                                            
+#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos      (21U)                                           
+#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define CAN_RDT0R_DLC_Pos      (0U)                                            
+#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos      (8U)                                            
+#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos     (16U)                                           
+#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define CAN_RDL0R_DATA0_Pos    (0U)                                            
+#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos    (8U)                                            
+#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos    (16U)                                           
+#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos    (24U)                                           
+#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define CAN_RDH0R_DATA4_Pos    (0U)                                            
+#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos    (8U)                                            
+#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos    (16U)                                           
+#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos    (24U)                                           
+#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define CAN_RI1R_RTR_Pos       (1U)                                            
+#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos       (2U)                                            
+#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos      (3U)                                            
+#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos      (21U)                                           
+#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define CAN_RDT1R_DLC_Pos      (0U)                                            
+#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos      (8U)                                            
+#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos     (16U)                                           
+#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define CAN_RDL1R_DATA0_Pos    (0U)                                            
+#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos    (8U)                                            
+#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos    (16U)                                           
+#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos    (24U)                                           
+#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define CAN_RDH1R_DATA4_Pos    (0U)                                            
+#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos    (8U)                                            
+#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos    (16U)                                           
+#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos    (24U)                                           
+#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define CAN_FMR_FINIT_Pos      (0U)                                            
+#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
+#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define CAN_FM1R_FBM_Pos       (0U)                                            
+#define CAN_FM1R_FBM_Msk       (0x3FFFU << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */
+#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos      (0U)                                            
+#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
+#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos      (1U)                                            
+#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
+#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos      (2U)                                            
+#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
+#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos      (3U)                                            
+#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
+#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos      (4U)                                            
+#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
+#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos      (5U)                                            
+#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
+#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos      (6U)                                            
+#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
+#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos      (7U)                                            
+#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
+#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos      (8U)                                            
+#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
+#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos      (9U)                                            
+#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
+#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos     (10U)                                           
+#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
+#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos     (11U)                                           
+#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
+#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos     (12U)                                           
+#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
+#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos     (13U)                                           
+#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
+#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define CAN_FS1R_FSC_Pos       (0U)                                            
+#define CAN_FS1R_FSC_Msk       (0x3FFFU << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */
+#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos      (0U)                                            
+#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
+#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos      (1U)                                            
+#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
+#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos      (2U)                                            
+#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
+#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos      (3U)                                            
+#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
+#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos      (4U)                                            
+#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
+#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos      (5U)                                            
+#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
+#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos      (6U)                                            
+#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
+#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos      (7U)                                            
+#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
+#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos      (8U)                                            
+#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
+#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos      (9U)                                            
+#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
+#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos     (10U)                                           
+#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
+#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos     (11U)                                           
+#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
+#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos     (12U)                                           
+#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
+#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos     (13U)                                           
+#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
+#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define CAN_FFA1R_FFA_Pos      (0U)                                            
+#define CAN_FFA1R_FFA_Msk      (0x3FFFU << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos     (0U)                                            
+#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1_Pos     (1U)                                            
+#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2_Pos     (2U)                                            
+#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3_Pos     (3U)                                            
+#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4_Pos     (4U)                                            
+#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5_Pos     (5U)                                            
+#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6_Pos     (6U)                                            
+#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7_Pos     (7U)                                            
+#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8_Pos     (8U)                                            
+#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9_Pos     (9U)                                            
+#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10_Pos    (10U)                                           
+#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11_Pos    (11U)                                           
+#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12_Pos    (12U)                                           
+#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13_Pos    (13U)                                           
+#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define CAN_FA1R_FACT_Pos      (0U)                                            
+#define CAN_FA1R_FACT_Msk      (0x3FFFU << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */
+#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos     (0U)                                            
+#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
+#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos     (1U)                                            
+#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
+#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos     (2U)                                            
+#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
+#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos     (3U)                                            
+#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
+#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos     (4U)                                            
+#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
+#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos     (5U)                                            
+#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
+#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos     (6U)                                            
+#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
+#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos     (7U)                                            
+#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
+#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos     (8U)                                            
+#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
+#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos     (9U)                                            
+#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
+#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos    (10U)                                           
+#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
+#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos    (11U)                                           
+#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
+#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos    (12U)                                           
+#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
+#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos    (13U)                                           
+#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
+#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define CAN_F0R1_FB0_Pos       (0U)                                            
+#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos       (1U)                                            
+#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos       (2U)                                            
+#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos       (3U)                                            
+#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos       (4U)                                            
+#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos       (5U)                                            
+#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos       (6U)                                            
+#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos       (7U)                                            
+#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos       (8U)                                            
+#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos       (9U)                                            
+#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos      (10U)                                           
+#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos      (11U)                                           
+#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos      (12U)                                           
+#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos      (13U)                                           
+#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos      (14U)                                           
+#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos      (15U)                                           
+#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos      (16U)                                           
+#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos      (17U)                                           
+#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos      (18U)                                           
+#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos      (19U)                                           
+#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos      (20U)                                           
+#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos      (21U)                                           
+#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos      (22U)                                           
+#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos      (23U)                                           
+#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos      (24U)                                           
+#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos      (25U)                                           
+#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos      (26U)                                           
+#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos      (27U)                                           
+#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos      (28U)                                           
+#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos      (29U)                                           
+#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos      (30U)                                           
+#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos      (31U)                                           
+#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define CAN_F1R1_FB0_Pos       (0U)                                            
+#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos       (1U)                                            
+#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos       (2U)                                            
+#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos       (3U)                                            
+#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos       (4U)                                            
+#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos       (5U)                                            
+#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos       (6U)                                            
+#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos       (7U)                                            
+#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos       (8U)                                            
+#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos       (9U)                                            
+#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos      (10U)                                           
+#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos      (11U)                                           
+#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos      (12U)                                           
+#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos      (13U)                                           
+#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos      (14U)                                           
+#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos      (15U)                                           
+#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos      (16U)                                           
+#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos      (17U)                                           
+#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos      (18U)                                           
+#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos      (19U)                                           
+#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos      (20U)                                           
+#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos      (21U)                                           
+#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos      (22U)                                           
+#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos      (23U)                                           
+#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos      (24U)                                           
+#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos      (25U)                                           
+#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos      (26U)                                           
+#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos      (27U)                                           
+#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos      (28U)                                           
+#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos      (29U)                                           
+#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos      (30U)                                           
+#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos      (31U)                                           
+#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define CAN_F2R1_FB0_Pos       (0U)                                            
+#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos       (1U)                                            
+#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos       (2U)                                            
+#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos       (3U)                                            
+#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos       (4U)                                            
+#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos       (5U)                                            
+#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos       (6U)                                            
+#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos       (7U)                                            
+#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos       (8U)                                            
+#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos       (9U)                                            
+#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos      (10U)                                           
+#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos      (11U)                                           
+#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos      (12U)                                           
+#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos      (13U)                                           
+#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos      (14U)                                           
+#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos      (15U)                                           
+#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos      (16U)                                           
+#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos      (17U)                                           
+#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos      (18U)                                           
+#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos      (19U)                                           
+#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos      (20U)                                           
+#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos      (21U)                                           
+#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos      (22U)                                           
+#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos      (23U)                                           
+#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos      (24U)                                           
+#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos      (25U)                                           
+#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos      (26U)                                           
+#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos      (27U)                                           
+#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos      (28U)                                           
+#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos      (29U)                                           
+#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos      (30U)                                           
+#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos      (31U)                                           
+#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define CAN_F3R1_FB0_Pos       (0U)                                            
+#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos       (1U)                                            
+#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos       (2U)                                            
+#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos       (3U)                                            
+#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos       (4U)                                            
+#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos       (5U)                                            
+#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos       (6U)                                            
+#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos       (7U)                                            
+#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos       (8U)                                            
+#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos       (9U)                                            
+#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos      (10U)                                           
+#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos      (11U)                                           
+#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos      (12U)                                           
+#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos      (13U)                                           
+#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos      (14U)                                           
+#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos      (15U)                                           
+#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos      (16U)                                           
+#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos      (17U)                                           
+#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos      (18U)                                           
+#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos      (19U)                                           
+#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos      (20U)                                           
+#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos      (21U)                                           
+#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos      (22U)                                           
+#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos      (23U)                                           
+#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos      (24U)                                           
+#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos      (25U)                                           
+#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos      (26U)                                           
+#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos      (27U)                                           
+#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos      (28U)                                           
+#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos      (29U)                                           
+#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos      (30U)                                           
+#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos      (31U)                                           
+#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define CAN_F4R1_FB0_Pos       (0U)                                            
+#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos       (1U)                                            
+#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos       (2U)                                            
+#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos       (3U)                                            
+#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos       (4U)                                            
+#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos       (5U)                                            
+#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos       (6U)                                            
+#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos       (7U)                                            
+#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos       (8U)                                            
+#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos       (9U)                                            
+#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos      (10U)                                           
+#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos      (11U)                                           
+#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos      (12U)                                           
+#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos      (13U)                                           
+#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos      (14U)                                           
+#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos      (15U)                                           
+#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos      (16U)                                           
+#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos      (17U)                                           
+#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos      (18U)                                           
+#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos      (19U)                                           
+#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos      (20U)                                           
+#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos      (21U)                                           
+#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos      (22U)                                           
+#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos      (23U)                                           
+#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos      (24U)                                           
+#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos      (25U)                                           
+#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos      (26U)                                           
+#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos      (27U)                                           
+#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos      (28U)                                           
+#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos      (29U)                                           
+#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos      (30U)                                           
+#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos      (31U)                                           
+#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define CAN_F5R1_FB0_Pos       (0U)                                            
+#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos       (1U)                                            
+#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos       (2U)                                            
+#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos       (3U)                                            
+#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos       (4U)                                            
+#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos       (5U)                                            
+#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos       (6U)                                            
+#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos       (7U)                                            
+#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos       (8U)                                            
+#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos       (9U)                                            
+#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos      (10U)                                           
+#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos      (11U)                                           
+#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos      (12U)                                           
+#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos      (13U)                                           
+#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos      (14U)                                           
+#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos      (15U)                                           
+#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos      (16U)                                           
+#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos      (17U)                                           
+#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos      (18U)                                           
+#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos      (19U)                                           
+#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos      (20U)                                           
+#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos      (21U)                                           
+#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos      (22U)                                           
+#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos      (23U)                                           
+#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos      (24U)                                           
+#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos      (25U)                                           
+#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos      (26U)                                           
+#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos      (27U)                                           
+#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos      (28U)                                           
+#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos      (29U)                                           
+#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos      (30U)                                           
+#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos      (31U)                                           
+#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define CAN_F6R1_FB0_Pos       (0U)                                            
+#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos       (1U)                                            
+#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos       (2U)                                            
+#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos       (3U)                                            
+#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos       (4U)                                            
+#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos       (5U)                                            
+#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos       (6U)                                            
+#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos       (7U)                                            
+#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos       (8U)                                            
+#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos       (9U)                                            
+#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos      (10U)                                           
+#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos      (11U)                                           
+#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos      (12U)                                           
+#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos      (13U)                                           
+#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos      (14U)                                           
+#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos      (15U)                                           
+#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos      (16U)                                           
+#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos      (17U)                                           
+#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos      (18U)                                           
+#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos      (19U)                                           
+#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos      (20U)                                           
+#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos      (21U)                                           
+#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos      (22U)                                           
+#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos      (23U)                                           
+#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos      (24U)                                           
+#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos      (25U)                                           
+#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos      (26U)                                           
+#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos      (27U)                                           
+#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos      (28U)                                           
+#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos      (29U)                                           
+#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos      (30U)                                           
+#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos      (31U)                                           
+#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define CAN_F7R1_FB0_Pos       (0U)                                            
+#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos       (1U)                                            
+#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos       (2U)                                            
+#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos       (3U)                                            
+#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos       (4U)                                            
+#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos       (5U)                                            
+#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos       (6U)                                            
+#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos       (7U)                                            
+#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos       (8U)                                            
+#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos       (9U)                                            
+#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos      (10U)                                           
+#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos      (11U)                                           
+#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos      (12U)                                           
+#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos      (13U)                                           
+#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos      (14U)                                           
+#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos      (15U)                                           
+#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos      (16U)                                           
+#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos      (17U)                                           
+#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos      (18U)                                           
+#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos      (19U)                                           
+#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos      (20U)                                           
+#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos      (21U)                                           
+#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos      (22U)                                           
+#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos      (23U)                                           
+#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos      (24U)                                           
+#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos      (25U)                                           
+#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos      (26U)                                           
+#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos      (27U)                                           
+#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos      (28U)                                           
+#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos      (29U)                                           
+#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos      (30U)                                           
+#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos      (31U)                                           
+#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define CAN_F8R1_FB0_Pos       (0U)                                            
+#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos       (1U)                                            
+#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos       (2U)                                            
+#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos       (3U)                                            
+#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos       (4U)                                            
+#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos       (5U)                                            
+#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos       (6U)                                            
+#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos       (7U)                                            
+#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos       (8U)                                            
+#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos       (9U)                                            
+#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos      (10U)                                           
+#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos      (11U)                                           
+#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos      (12U)                                           
+#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos      (13U)                                           
+#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos      (14U)                                           
+#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos      (15U)                                           
+#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos      (16U)                                           
+#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos      (17U)                                           
+#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos      (18U)                                           
+#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos      (19U)                                           
+#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos      (20U)                                           
+#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos      (21U)                                           
+#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos      (22U)                                           
+#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos      (23U)                                           
+#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos      (24U)                                           
+#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos      (25U)                                           
+#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos      (26U)                                           
+#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos      (27U)                                           
+#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos      (28U)                                           
+#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos      (29U)                                           
+#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos      (30U)                                           
+#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos      (31U)                                           
+#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define CAN_F9R1_FB0_Pos       (0U)                                            
+#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos       (1U)                                            
+#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos       (2U)                                            
+#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos       (3U)                                            
+#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos       (4U)                                            
+#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos       (5U)                                            
+#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos       (6U)                                            
+#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos       (7U)                                            
+#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos       (8U)                                            
+#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos       (9U)                                            
+#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos      (10U)                                           
+#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos      (11U)                                           
+#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos      (12U)                                           
+#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos      (13U)                                           
+#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos      (14U)                                           
+#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos      (15U)                                           
+#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos      (16U)                                           
+#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos      (17U)                                           
+#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos      (18U)                                           
+#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos      (19U)                                           
+#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos      (20U)                                           
+#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos      (21U)                                           
+#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos      (22U)                                           
+#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos      (23U)                                           
+#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos      (24U)                                           
+#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos      (25U)                                           
+#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos      (26U)                                           
+#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos      (27U)                                           
+#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos      (28U)                                           
+#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos      (29U)                                           
+#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos      (30U)                                           
+#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos      (31U)                                           
+#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define CAN_F10R1_FB0_Pos      (0U)                                            
+#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos      (1U)                                            
+#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos      (2U)                                            
+#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos      (3U)                                            
+#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos      (4U)                                            
+#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos      (5U)                                            
+#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos      (6U)                                            
+#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos      (7U)                                            
+#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos      (8U)                                            
+#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos      (9U)                                            
+#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos     (10U)                                           
+#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos     (11U)                                           
+#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos     (12U)                                           
+#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos     (13U)                                           
+#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos     (14U)                                           
+#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos     (15U)                                           
+#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos     (16U)                                           
+#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos     (17U)                                           
+#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos     (18U)                                           
+#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos     (19U)                                           
+#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos     (20U)                                           
+#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos     (21U)                                           
+#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos     (22U)                                           
+#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos     (23U)                                           
+#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos     (24U)                                           
+#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos     (25U)                                           
+#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos     (26U)                                           
+#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos     (27U)                                           
+#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos     (28U)                                           
+#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos     (29U)                                           
+#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos     (30U)                                           
+#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos     (31U)                                           
+#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define CAN_F11R1_FB0_Pos      (0U)                                            
+#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos      (1U)                                            
+#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos      (2U)                                            
+#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos      (3U)                                            
+#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos      (4U)                                            
+#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos      (5U)                                            
+#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos      (6U)                                            
+#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos      (7U)                                            
+#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos      (8U)                                            
+#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos      (9U)                                            
+#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos     (10U)                                           
+#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos     (11U)                                           
+#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos     (12U)                                           
+#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos     (13U)                                           
+#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos     (14U)                                           
+#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos     (15U)                                           
+#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos     (16U)                                           
+#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos     (17U)                                           
+#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos     (18U)                                           
+#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos     (19U)                                           
+#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos     (20U)                                           
+#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos     (21U)                                           
+#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos     (22U)                                           
+#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos     (23U)                                           
+#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos     (24U)                                           
+#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos     (25U)                                           
+#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos     (26U)                                           
+#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos     (27U)                                           
+#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos     (28U)                                           
+#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos     (29U)                                           
+#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos     (30U)                                           
+#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos     (31U)                                           
+#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define CAN_F12R1_FB0_Pos      (0U)                                            
+#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos      (1U)                                            
+#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos      (2U)                                            
+#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos      (3U)                                            
+#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos      (4U)                                            
+#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos      (5U)                                            
+#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos      (6U)                                            
+#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos      (7U)                                            
+#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos      (8U)                                            
+#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos      (9U)                                            
+#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos     (10U)                                           
+#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos     (11U)                                           
+#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos     (12U)                                           
+#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos     (13U)                                           
+#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos     (14U)                                           
+#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos     (15U)                                           
+#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos     (16U)                                           
+#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos     (17U)                                           
+#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos     (18U)                                           
+#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos     (19U)                                           
+#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos     (20U)                                           
+#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos     (21U)                                           
+#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos     (22U)                                           
+#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos     (23U)                                           
+#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos     (24U)                                           
+#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos     (25U)                                           
+#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos     (26U)                                           
+#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos     (27U)                                           
+#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos     (28U)                                           
+#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos     (29U)                                           
+#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos     (30U)                                           
+#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos     (31U)                                           
+#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define CAN_F13R1_FB0_Pos      (0U)                                            
+#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos      (1U)                                            
+#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos      (2U)                                            
+#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos      (3U)                                            
+#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos      (4U)                                            
+#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos      (5U)                                            
+#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos      (6U)                                            
+#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos      (7U)                                            
+#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos      (8U)                                            
+#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos      (9U)                                            
+#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos     (10U)                                           
+#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos     (11U)                                           
+#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos     (12U)                                           
+#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos     (13U)                                           
+#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos     (14U)                                           
+#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos     (15U)                                           
+#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos     (16U)                                           
+#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos     (17U)                                           
+#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos     (18U)                                           
+#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos     (19U)                                           
+#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos     (20U)                                           
+#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos     (21U)                                           
+#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos     (22U)                                           
+#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos     (23U)                                           
+#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos     (24U)                                           
+#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos     (25U)                                           
+#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos     (26U)                                           
+#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos     (27U)                                           
+#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos     (28U)                                           
+#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos     (29U)                                           
+#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos     (30U)                                           
+#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos     (31U)                                           
+#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define CAN_F0R2_FB0_Pos       (0U)                                            
+#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos       (1U)                                            
+#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos       (2U)                                            
+#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos       (3U)                                            
+#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos       (4U)                                            
+#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos       (5U)                                            
+#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos       (6U)                                            
+#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos       (7U)                                            
+#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos       (8U)                                            
+#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos       (9U)                                            
+#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos      (10U)                                           
+#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos      (11U)                                           
+#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos      (12U)                                           
+#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos      (13U)                                           
+#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos      (14U)                                           
+#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos      (15U)                                           
+#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos      (16U)                                           
+#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos      (17U)                                           
+#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos      (18U)                                           
+#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos      (19U)                                           
+#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos      (20U)                                           
+#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos      (21U)                                           
+#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos      (22U)                                           
+#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos      (23U)                                           
+#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos      (24U)                                           
+#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos      (25U)                                           
+#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos      (26U)                                           
+#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos      (27U)                                           
+#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos      (28U)                                           
+#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos      (29U)                                           
+#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos      (30U)                                           
+#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos      (31U)                                           
+#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define CAN_F1R2_FB0_Pos       (0U)                                            
+#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos       (1U)                                            
+#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos       (2U)                                            
+#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos       (3U)                                            
+#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos       (4U)                                            
+#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos       (5U)                                            
+#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos       (6U)                                            
+#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos       (7U)                                            
+#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos       (8U)                                            
+#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos       (9U)                                            
+#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos      (10U)                                           
+#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos      (11U)                                           
+#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos      (12U)                                           
+#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos      (13U)                                           
+#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos      (14U)                                           
+#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos      (15U)                                           
+#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos      (16U)                                           
+#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos      (17U)                                           
+#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos      (18U)                                           
+#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos      (19U)                                           
+#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos      (20U)                                           
+#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos      (21U)                                           
+#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos      (22U)                                           
+#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos      (23U)                                           
+#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos      (24U)                                           
+#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos      (25U)                                           
+#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos      (26U)                                           
+#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos      (27U)                                           
+#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos      (28U)                                           
+#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos      (29U)                                           
+#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos      (30U)                                           
+#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos      (31U)                                           
+#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define CAN_F2R2_FB0_Pos       (0U)                                            
+#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos       (1U)                                            
+#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos       (2U)                                            
+#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos       (3U)                                            
+#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos       (4U)                                            
+#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos       (5U)                                            
+#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos       (6U)                                            
+#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos       (7U)                                            
+#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos       (8U)                                            
+#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos       (9U)                                            
+#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos      (10U)                                           
+#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos      (11U)                                           
+#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos      (12U)                                           
+#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos      (13U)                                           
+#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos      (14U)                                           
+#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos      (15U)                                           
+#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos      (16U)                                           
+#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos      (17U)                                           
+#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos      (18U)                                           
+#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos      (19U)                                           
+#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos      (20U)                                           
+#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos      (21U)                                           
+#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos      (22U)                                           
+#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos      (23U)                                           
+#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos      (24U)                                           
+#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos      (25U)                                           
+#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos      (26U)                                           
+#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos      (27U)                                           
+#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos      (28U)                                           
+#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos      (29U)                                           
+#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos      (30U)                                           
+#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos      (31U)                                           
+#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define CAN_F3R2_FB0_Pos       (0U)                                            
+#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos       (1U)                                            
+#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos       (2U)                                            
+#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos       (3U)                                            
+#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos       (4U)                                            
+#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos       (5U)                                            
+#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos       (6U)                                            
+#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos       (7U)                                            
+#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos       (8U)                                            
+#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos       (9U)                                            
+#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos      (10U)                                           
+#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos      (11U)                                           
+#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos      (12U)                                           
+#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos      (13U)                                           
+#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos      (14U)                                           
+#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos      (15U)                                           
+#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos      (16U)                                           
+#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos      (17U)                                           
+#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos      (18U)                                           
+#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos      (19U)                                           
+#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos      (20U)                                           
+#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos      (21U)                                           
+#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos      (22U)                                           
+#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos      (23U)                                           
+#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos      (24U)                                           
+#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos      (25U)                                           
+#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos      (26U)                                           
+#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos      (27U)                                           
+#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos      (28U)                                           
+#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos      (29U)                                           
+#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos      (30U)                                           
+#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos      (31U)                                           
+#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define CAN_F4R2_FB0_Pos       (0U)                                            
+#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos       (1U)                                            
+#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos       (2U)                                            
+#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos       (3U)                                            
+#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos       (4U)                                            
+#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos       (5U)                                            
+#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos       (6U)                                            
+#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos       (7U)                                            
+#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos       (8U)                                            
+#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos       (9U)                                            
+#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos      (10U)                                           
+#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos      (11U)                                           
+#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos      (12U)                                           
+#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos      (13U)                                           
+#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos      (14U)                                           
+#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos      (15U)                                           
+#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos      (16U)                                           
+#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos      (17U)                                           
+#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos      (18U)                                           
+#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos      (19U)                                           
+#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos      (20U)                                           
+#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos      (21U)                                           
+#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos      (22U)                                           
+#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos      (23U)                                           
+#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos      (24U)                                           
+#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos      (25U)                                           
+#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos      (26U)                                           
+#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos      (27U)                                           
+#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos      (28U)                                           
+#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos      (29U)                                           
+#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos      (30U)                                           
+#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos      (31U)                                           
+#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define CAN_F5R2_FB0_Pos       (0U)                                            
+#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos       (1U)                                            
+#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos       (2U)                                            
+#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos       (3U)                                            
+#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos       (4U)                                            
+#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos       (5U)                                            
+#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos       (6U)                                            
+#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos       (7U)                                            
+#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos       (8U)                                            
+#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos       (9U)                                            
+#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos      (10U)                                           
+#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos      (11U)                                           
+#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos      (12U)                                           
+#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos      (13U)                                           
+#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos      (14U)                                           
+#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos      (15U)                                           
+#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos      (16U)                                           
+#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos      (17U)                                           
+#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos      (18U)                                           
+#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos      (19U)                                           
+#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos      (20U)                                           
+#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos      (21U)                                           
+#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos      (22U)                                           
+#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos      (23U)                                           
+#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos      (24U)                                           
+#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos      (25U)                                           
+#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos      (26U)                                           
+#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos      (27U)                                           
+#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos      (28U)                                           
+#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos      (29U)                                           
+#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos      (30U)                                           
+#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos      (31U)                                           
+#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define CAN_F6R2_FB0_Pos       (0U)                                            
+#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos       (1U)                                            
+#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos       (2U)                                            
+#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos       (3U)                                            
+#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos       (4U)                                            
+#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos       (5U)                                            
+#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos       (6U)                                            
+#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos       (7U)                                            
+#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos       (8U)                                            
+#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos       (9U)                                            
+#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos      (10U)                                           
+#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos      (11U)                                           
+#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos      (12U)                                           
+#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos      (13U)                                           
+#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos      (14U)                                           
+#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos      (15U)                                           
+#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos      (16U)                                           
+#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos      (17U)                                           
+#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos      (18U)                                           
+#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos      (19U)                                           
+#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos      (20U)                                           
+#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos      (21U)                                           
+#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos      (22U)                                           
+#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos      (23U)                                           
+#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos      (24U)                                           
+#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos      (25U)                                           
+#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos      (26U)                                           
+#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos      (27U)                                           
+#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos      (28U)                                           
+#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos      (29U)                                           
+#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos      (30U)                                           
+#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos      (31U)                                           
+#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define CAN_F7R2_FB0_Pos       (0U)                                            
+#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos       (1U)                                            
+#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos       (2U)                                            
+#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos       (3U)                                            
+#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos       (4U)                                            
+#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos       (5U)                                            
+#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos       (6U)                                            
+#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos       (7U)                                            
+#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos       (8U)                                            
+#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos       (9U)                                            
+#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos      (10U)                                           
+#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos      (11U)                                           
+#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos      (12U)                                           
+#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos      (13U)                                           
+#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos      (14U)                                           
+#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos      (15U)                                           
+#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos      (16U)                                           
+#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos      (17U)                                           
+#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos      (18U)                                           
+#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos      (19U)                                           
+#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos      (20U)                                           
+#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos      (21U)                                           
+#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos      (22U)                                           
+#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos      (23U)                                           
+#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos      (24U)                                           
+#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos      (25U)                                           
+#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos      (26U)                                           
+#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos      (27U)                                           
+#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos      (28U)                                           
+#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos      (29U)                                           
+#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos      (30U)                                           
+#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos      (31U)                                           
+#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define CAN_F8R2_FB0_Pos       (0U)                                            
+#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos       (1U)                                            
+#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos       (2U)                                            
+#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos       (3U)                                            
+#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos       (4U)                                            
+#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos       (5U)                                            
+#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos       (6U)                                            
+#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos       (7U)                                            
+#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos       (8U)                                            
+#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos       (9U)                                            
+#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos      (10U)                                           
+#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos      (11U)                                           
+#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos      (12U)                                           
+#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos      (13U)                                           
+#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos      (14U)                                           
+#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos      (15U)                                           
+#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos      (16U)                                           
+#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos      (17U)                                           
+#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos      (18U)                                           
+#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos      (19U)                                           
+#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos      (20U)                                           
+#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos      (21U)                                           
+#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos      (22U)                                           
+#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos      (23U)                                           
+#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos      (24U)                                           
+#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos      (25U)                                           
+#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos      (26U)                                           
+#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos      (27U)                                           
+#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos      (28U)                                           
+#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos      (29U)                                           
+#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos      (30U)                                           
+#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos      (31U)                                           
+#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define CAN_F9R2_FB0_Pos       (0U)                                            
+#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos       (1U)                                            
+#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos       (2U)                                            
+#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos       (3U)                                            
+#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos       (4U)                                            
+#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos       (5U)                                            
+#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos       (6U)                                            
+#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos       (7U)                                            
+#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos       (8U)                                            
+#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos       (9U)                                            
+#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos      (10U)                                           
+#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos      (11U)                                           
+#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos      (12U)                                           
+#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos      (13U)                                           
+#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos      (14U)                                           
+#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos      (15U)                                           
+#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos      (16U)                                           
+#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos      (17U)                                           
+#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos      (18U)                                           
+#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos      (19U)                                           
+#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos      (20U)                                           
+#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos      (21U)                                           
+#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos      (22U)                                           
+#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos      (23U)                                           
+#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos      (24U)                                           
+#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos      (25U)                                           
+#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos      (26U)                                           
+#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos      (27U)                                           
+#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos      (28U)                                           
+#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos      (29U)                                           
+#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos      (30U)                                           
+#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos      (31U)                                           
+#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define CAN_F10R2_FB0_Pos      (0U)                                            
+#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos      (1U)                                            
+#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos      (2U)                                            
+#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos      (3U)                                            
+#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos      (4U)                                            
+#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos      (5U)                                            
+#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos      (6U)                                            
+#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos      (7U)                                            
+#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos      (8U)                                            
+#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos      (9U)                                            
+#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos     (10U)                                           
+#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos     (11U)                                           
+#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos     (12U)                                           
+#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos     (13U)                                           
+#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos     (14U)                                           
+#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos     (15U)                                           
+#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos     (16U)                                           
+#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos     (17U)                                           
+#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos     (18U)                                           
+#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos     (19U)                                           
+#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos     (20U)                                           
+#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos     (21U)                                           
+#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos     (22U)                                           
+#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos     (23U)                                           
+#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos     (24U)                                           
+#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos     (25U)                                           
+#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos     (26U)                                           
+#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos     (27U)                                           
+#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos     (28U)                                           
+#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos     (29U)                                           
+#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos     (30U)                                           
+#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos     (31U)                                           
+#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define CAN_F11R2_FB0_Pos      (0U)                                            
+#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos      (1U)                                            
+#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos      (2U)                                            
+#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos      (3U)                                            
+#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos      (4U)                                            
+#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos      (5U)                                            
+#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos      (6U)                                            
+#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos      (7U)                                            
+#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos      (8U)                                            
+#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos      (9U)                                            
+#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos     (10U)                                           
+#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos     (11U)                                           
+#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos     (12U)                                           
+#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos     (13U)                                           
+#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos     (14U)                                           
+#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos     (15U)                                           
+#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos     (16U)                                           
+#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos     (17U)                                           
+#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos     (18U)                                           
+#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos     (19U)                                           
+#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos     (20U)                                           
+#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos     (21U)                                           
+#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos     (22U)                                           
+#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos     (23U)                                           
+#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos     (24U)                                           
+#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos     (25U)                                           
+#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos     (26U)                                           
+#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos     (27U)                                           
+#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos     (28U)                                           
+#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos     (29U)                                           
+#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos     (30U)                                           
+#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos     (31U)                                           
+#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define CAN_F12R2_FB0_Pos      (0U)                                            
+#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos      (1U)                                            
+#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos      (2U)                                            
+#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos      (3U)                                            
+#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos      (4U)                                            
+#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos      (5U)                                            
+#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos      (6U)                                            
+#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos      (7U)                                            
+#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos      (8U)                                            
+#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos      (9U)                                            
+#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos     (10U)                                           
+#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos     (11U)                                           
+#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos     (12U)                                           
+#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos     (13U)                                           
+#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos     (14U)                                           
+#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos     (15U)                                           
+#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos     (16U)                                           
+#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos     (17U)                                           
+#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos     (18U)                                           
+#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos     (19U)                                           
+#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos     (20U)                                           
+#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos     (21U)                                           
+#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos     (22U)                                           
+#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos     (23U)                                           
+#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos     (24U)                                           
+#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos     (25U)                                           
+#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos     (26U)                                           
+#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos     (27U)                                           
+#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos     (28U)                                           
+#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos     (29U)                                           
+#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos     (30U)                                           
+#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos     (31U)                                           
+#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define CAN_F13R2_FB0_Pos      (0U)                                            
+#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos      (1U)                                            
+#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos      (2U)                                            
+#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos      (3U)                                            
+#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos      (4U)                                            
+#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos      (5U)                                            
+#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos      (6U)                                            
+#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos      (7U)                                            
+#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos      (8U)                                            
+#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos      (9U)                                            
+#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos     (10U)                                           
+#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos     (11U)                                           
+#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos     (12U)                                           
+#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos     (13U)                                           
+#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos     (14U)                                           
+#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos     (15U)                                           
+#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos     (16U)                                           
+#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos     (17U)                                           
+#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos     (18U)                                           
+#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos     (19U)                                           
+#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos     (20U)                                           
+#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos     (21U)                                           
+#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos     (22U)                                           
+#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos     (23U)                                           
+#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos     (24U)                                           
+#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos     (25U)                                           
+#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos     (26U)                                           
+#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos     (27U)                                           
+#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos     (28U)                                           
+#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos     (29U)                                           
+#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos     (30U)                                           
+#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos     (31U)                                           
+#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos                       (0U)                               
+#define CRC_DR_DR_Msk                       (0xFFFFFFFFU << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR                         ((uint8_t)0xFFU)                   /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos                    (0U)                               
+#define CRC_CR_RESET_Msk                    (0x1U << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
+#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos                 (3U)                               
+#define CRC_CR_POLYSIZE_Msk                 (0x3U << CRC_CR_POLYSIZE_Pos)      /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE                     CRC_CR_POLYSIZE_Msk                /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0                   (0x1U << CRC_CR_POLYSIZE_Pos)      /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1                   (0x2U << CRC_CR_POLYSIZE_Pos)      /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos                   (5U)                               
+#define CRC_CR_REV_IN_Msk                   (0x3U << CRC_CR_REV_IN_Pos)        /*!< 0x00000060 */
+#define CRC_CR_REV_IN                       CRC_CR_REV_IN_Msk                  /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0                     (0x1U << CRC_CR_REV_IN_Pos)        /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1                     (0x2U << CRC_CR_REV_IN_Pos)        /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos                  (7U)                               
+#define CRC_CR_REV_OUT_Msk                  (0x1U << CRC_CR_REV_OUT_Pos)       /*!< 0x00000080 */
+#define CRC_CR_REV_OUT                      CRC_CR_REV_OUT_Msk                 /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos                   (0U)                               
+#define CRC_INIT_INIT_Msk                   (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT                       CRC_INIT_INIT_Msk                  /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos                     (0U)                               
+#define CRC_POL_POL_Msk                     (0xFFFFFFFFU << CRC_POL_POL_Pos)   /*!< 0xFFFFFFFF */
+#define CRC_POL_POL                         CRC_POL_POL_Msk                    /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Advanced Encryption Standard (AES)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for AES_CR register  *********************/
+#define AES_CR_EN_Pos                        (0U)                              
+#define AES_CR_EN_Msk                        (0x1U << AES_CR_EN_Pos)           /*!< 0x00000001 */
+#define AES_CR_EN                            AES_CR_EN_Msk                     /*!< AES Enable */
+#define AES_CR_DATATYPE_Pos                  (1U)                              
+#define AES_CR_DATATYPE_Msk                  (0x3U << AES_CR_DATATYPE_Pos)     /*!< 0x00000006 */
+#define AES_CR_DATATYPE                      AES_CR_DATATYPE_Msk               /*!< Data type selection */
+#define AES_CR_DATATYPE_0                    (0x1U << AES_CR_DATATYPE_Pos)     /*!< 0x00000002 */
+#define AES_CR_DATATYPE_1                    (0x2U << AES_CR_DATATYPE_Pos)     /*!< 0x00000004 */
+
+#define AES_CR_MODE_Pos                      (3U)                              
+#define AES_CR_MODE_Msk                      (0x3U << AES_CR_MODE_Pos)         /*!< 0x00000018 */
+#define AES_CR_MODE                          AES_CR_MODE_Msk                   /*!< AES Mode Of Operation */
+#define AES_CR_MODE_0                        (0x1U << AES_CR_MODE_Pos)         /*!< 0x00000008 */
+#define AES_CR_MODE_1                        (0x2U << AES_CR_MODE_Pos)         /*!< 0x00000010 */
+
+#define AES_CR_CHMOD_Pos                     (5U)                              
+#define AES_CR_CHMOD_Msk                     (0x803U << AES_CR_CHMOD_Pos)      /*!< 0x00010060 */
+#define AES_CR_CHMOD                         AES_CR_CHMOD_Msk                  /*!< AES Chaining Mode */
+#define AES_CR_CHMOD_0                       (0x001U << AES_CR_CHMOD_Pos)      /*!< 0x00000020 */
+#define AES_CR_CHMOD_1                       (0x002U << AES_CR_CHMOD_Pos)      /*!< 0x00000040 */
+#define AES_CR_CHMOD_2                       (0x800U << AES_CR_CHMOD_Pos)      /*!< 0x00010000 */
+
+#define AES_CR_CCFC_Pos                      (7U)                              
+#define AES_CR_CCFC_Msk                      (0x1U << AES_CR_CCFC_Pos)         /*!< 0x00000080 */
+#define AES_CR_CCFC                          AES_CR_CCFC_Msk                   /*!< Computation Complete Flag Clear */
+#define AES_CR_ERRC_Pos                      (8U)                              
+#define AES_CR_ERRC_Msk                      (0x1U << AES_CR_ERRC_Pos)         /*!< 0x00000100 */
+#define AES_CR_ERRC                          AES_CR_ERRC_Msk                   /*!< Error Clear */
+#define AES_CR_CCFIE_Pos                     (9U)                              
+#define AES_CR_CCFIE_Msk                     (0x1U << AES_CR_CCFIE_Pos)        /*!< 0x00000200 */
+#define AES_CR_CCFIE                         AES_CR_CCFIE_Msk                  /*!< Computation Complete Flag Interrupt Enable */
+#define AES_CR_ERRIE_Pos                     (10U)                             
+#define AES_CR_ERRIE_Msk                     (0x1U << AES_CR_ERRIE_Pos)        /*!< 0x00000400 */
+#define AES_CR_ERRIE                         AES_CR_ERRIE_Msk                  /*!< Error Interrupt Enable */
+#define AES_CR_DMAINEN_Pos                   (11U)                             
+#define AES_CR_DMAINEN_Msk                   (0x1U << AES_CR_DMAINEN_Pos)      /*!< 0x00000800 */
+#define AES_CR_DMAINEN                       AES_CR_DMAINEN_Msk                /*!< Enable data input phase DMA management  */
+#define AES_CR_DMAOUTEN_Pos                  (12U)                             
+#define AES_CR_DMAOUTEN_Msk                  (0x1U << AES_CR_DMAOUTEN_Pos)     /*!< 0x00001000 */
+#define AES_CR_DMAOUTEN                      AES_CR_DMAOUTEN_Msk               /*!< Enable data output phase DMA management */
+
+#define AES_CR_GCMPH_Pos                     (13U)                             
+#define AES_CR_GCMPH_Msk                     (0x3U << AES_CR_GCMPH_Pos)        /*!< 0x00006000 */
+#define AES_CR_GCMPH                         AES_CR_GCMPH_Msk                  /*!< GCM Phase */
+#define AES_CR_GCMPH_0                       (0x1U << AES_CR_GCMPH_Pos)        /*!< 0x00002000 */
+#define AES_CR_GCMPH_1                       (0x2U << AES_CR_GCMPH_Pos)        /*!< 0x00004000 */
+
+#define AES_CR_KEYSIZE_Pos                   (18U)                             
+#define AES_CR_KEYSIZE_Msk                   (0x1U << AES_CR_KEYSIZE_Pos)      /*!< 0x00040000 */
+#define AES_CR_KEYSIZE                       AES_CR_KEYSIZE_Msk                /*!< Key size selection */
+
+/*******************  Bit definition for AES_SR register  *********************/
+#define AES_SR_CCF_Pos                       (0U)                              
+#define AES_SR_CCF_Msk                       (0x1U << AES_SR_CCF_Pos)          /*!< 0x00000001 */
+#define AES_SR_CCF                           AES_SR_CCF_Msk                    /*!< Computation Complete Flag */
+#define AES_SR_RDERR_Pos                     (1U)                              
+#define AES_SR_RDERR_Msk                     (0x1U << AES_SR_RDERR_Pos)        /*!< 0x00000002 */
+#define AES_SR_RDERR                         AES_SR_RDERR_Msk                  /*!< Read Error Flag */
+#define AES_SR_WRERR_Pos                     (2U)                              
+#define AES_SR_WRERR_Msk                     (0x1U << AES_SR_WRERR_Pos)        /*!< 0x00000004 */
+#define AES_SR_WRERR                         AES_SR_WRERR_Msk                  /*!< Write Error Flag */
+#define AES_SR_BUSY_Pos                      (3U)                              
+#define AES_SR_BUSY_Msk                      (0x1U << AES_SR_BUSY_Pos)         /*!< 0x00000008 */
+#define AES_SR_BUSY                          AES_SR_BUSY_Msk                   /*!< Busy Flag */
+
+/*******************  Bit definition for AES_DINR register  *******************/
+#define AES_DINR_Pos                         (0U)                              
+#define AES_DINR_Msk                         (0xFFFFFFFFU << AES_DINR_Pos)     /*!< 0xFFFFFFFF */
+#define AES_DINR                             AES_DINR_Msk                      /*!< AES Data Input Register */
+
+/*******************  Bit definition for AES_DOUTR register  ******************/
+#define AES_DOUTR_Pos                        (0U)                              
+#define AES_DOUTR_Msk                        (0xFFFFFFFFU << AES_DOUTR_Pos)    /*!< 0xFFFFFFFF */
+#define AES_DOUTR                            AES_DOUTR_Msk                     /*!< AES Data Output Register */
+
+/*******************  Bit definition for AES_KEYR0 register  ******************/
+#define AES_KEYR0_Pos                        (0U)                              
+#define AES_KEYR0_Msk                        (0xFFFFFFFFU << AES_KEYR0_Pos)    /*!< 0xFFFFFFFF */
+#define AES_KEYR0                            AES_KEYR0_Msk                     /*!< AES Key Register 0 */
+
+/*******************  Bit definition for AES_KEYR1 register  ******************/
+#define AES_KEYR1_Pos                        (0U)                              
+#define AES_KEYR1_Msk                        (0xFFFFFFFFU << AES_KEYR1_Pos)    /*!< 0xFFFFFFFF */
+#define AES_KEYR1                            AES_KEYR1_Msk                     /*!< AES Key Register 1 */
+
+/*******************  Bit definition for AES_KEYR2 register  ******************/
+#define AES_KEYR2_Pos                        (0U)                              
+#define AES_KEYR2_Msk                        (0xFFFFFFFFU << AES_KEYR2_Pos)    /*!< 0xFFFFFFFF */
+#define AES_KEYR2                            AES_KEYR2_Msk                     /*!< AES Key Register 2 */
+
+/*******************  Bit definition for AES_KEYR3 register  ******************/
+#define AES_KEYR3_Pos                        (0U)                              
+#define AES_KEYR3_Msk                        (0xFFFFFFFFU << AES_KEYR3_Pos)    /*!< 0xFFFFFFFF */
+#define AES_KEYR3                            AES_KEYR3_Msk                     /*!< AES Key Register 3 */
+
+/*******************  Bit definition for AES_KEYR4 register  ******************/
+#define AES_KEYR4_Pos                        (0U)                              
+#define AES_KEYR4_Msk                        (0xFFFFFFFFU << AES_KEYR4_Pos)    /*!< 0xFFFFFFFF */
+#define AES_KEYR4                            AES_KEYR4_Msk                     /*!< AES Key Register 4 */
+
+/*******************  Bit definition for AES_KEYR5 register  ******************/
+#define AES_KEYR5_Pos                        (0U)                              
+#define AES_KEYR5_Msk                        (0xFFFFFFFFU << AES_KEYR5_Pos)    /*!< 0xFFFFFFFF */
+#define AES_KEYR5                            AES_KEYR5_Msk                     /*!< AES Key Register 5 */
+
+/*******************  Bit definition for AES_KEYR6 register  ******************/
+#define AES_KEYR6_Pos                        (0U)                              
+#define AES_KEYR6_Msk                        (0xFFFFFFFFU << AES_KEYR6_Pos)    /*!< 0xFFFFFFFF */
+#define AES_KEYR6                            AES_KEYR6_Msk                     /*!< AES Key Register 6 */
+
+/*******************  Bit definition for AES_KEYR7 register  ******************/
+#define AES_KEYR7_Pos                        (0U)                              
+#define AES_KEYR7_Msk                        (0xFFFFFFFFU << AES_KEYR7_Pos)    /*!< 0xFFFFFFFF */
+#define AES_KEYR7                            AES_KEYR7_Msk                     /*!< AES Key Register 7 */
+
+/*******************  Bit definition for AES_IVR0 register   ******************/
+#define AES_IVR0_Pos                         (0U)                              
+#define AES_IVR0_Msk                         (0xFFFFFFFFU << AES_IVR0_Pos)     /*!< 0xFFFFFFFF */
+#define AES_IVR0                             AES_IVR0_Msk                      /*!< AES Initialization Vector Register 0 */
+
+/*******************  Bit definition for AES_IVR1 register   ******************/
+#define AES_IVR1_Pos                         (0U)                              
+#define AES_IVR1_Msk                         (0xFFFFFFFFU << AES_IVR1_Pos)     /*!< 0xFFFFFFFF */
+#define AES_IVR1                             AES_IVR1_Msk                      /*!< AES Initialization Vector Register 1 */
+
+/*******************  Bit definition for AES_IVR2 register   ******************/
+#define AES_IVR2_Pos                         (0U)                              
+#define AES_IVR2_Msk                         (0xFFFFFFFFU << AES_IVR2_Pos)     /*!< 0xFFFFFFFF */
+#define AES_IVR2                             AES_IVR2_Msk                      /*!< AES Initialization Vector Register 2 */
+
+/*******************  Bit definition for AES_IVR3 register   ******************/
+#define AES_IVR3_Pos                         (0U)                              
+#define AES_IVR3_Msk                         (0xFFFFFFFFU << AES_IVR3_Pos)     /*!< 0xFFFFFFFF */
+#define AES_IVR3                             AES_IVR3_Msk                      /*!< AES Initialization Vector Register 3 */
+
+/*******************  Bit definition for AES_SUSP0R register  ******************/
+#define AES_SUSP0R_Pos                       (0U)                              
+#define AES_SUSP0R_Msk                       (0xFFFFFFFFU << AES_SUSP0R_Pos)   /*!< 0xFFFFFFFF */
+#define AES_SUSP0R                           AES_SUSP0R_Msk                    /*!< AES Suspend registers 0 */
+
+/*******************  Bit definition for AES_SUSP1R register  ******************/
+#define AES_SUSP1R_Pos                       (0U)                              
+#define AES_SUSP1R_Msk                       (0xFFFFFFFFU << AES_SUSP1R_Pos)   /*!< 0xFFFFFFFF */
+#define AES_SUSP1R                           AES_SUSP1R_Msk                    /*!< AES Suspend registers 1 */
+
+/*******************  Bit definition for AES_SUSP2R register  ******************/
+#define AES_SUSP2R_Pos                       (0U)                              
+#define AES_SUSP2R_Msk                       (0xFFFFFFFFU << AES_SUSP2R_Pos)   /*!< 0xFFFFFFFF */
+#define AES_SUSP2R                           AES_SUSP2R_Msk                    /*!< AES Suspend registers 2 */
+
+/*******************  Bit definition for AES_SUSP3R register  ******************/
+#define AES_SUSP3R_Pos                       (0U)                              
+#define AES_SUSP3R_Msk                       (0xFFFFFFFFU << AES_SUSP3R_Pos)   /*!< 0xFFFFFFFF */
+#define AES_SUSP3R                           AES_SUSP3R_Msk                    /*!< AES Suspend registers 3 */
+
+/*******************  Bit definition for AES_SUSP4R register  ******************/
+#define AES_SUSP4R_Pos                       (0U)                              
+#define AES_SUSP4R_Msk                       (0xFFFFFFFFU << AES_SUSP4R_Pos)   /*!< 0xFFFFFFFF */
+#define AES_SUSP4R                           AES_SUSP4R_Msk                    /*!< AES Suspend registers 4 */
+
+/*******************  Bit definition for AES_SUSP5R register  ******************/
+#define AES_SUSP5R_Pos                       (0U)                              
+#define AES_SUSP5R_Msk                       (0xFFFFFFFFU << AES_SUSP5R_Pos)   /*!< 0xFFFFFFFF */
+#define AES_SUSP5R                           AES_SUSP5R_Msk                    /*!< AES Suspend registers 5 */
+
+/*******************  Bit definition for AES_SUSP6R register  ******************/
+#define AES_SUSP6R_Pos                       (0U)                              
+#define AES_SUSP6R_Msk                       (0xFFFFFFFFU << AES_SUSP6R_Pos)   /*!< 0xFFFFFFFF */
+#define AES_SUSP6R                           AES_SUSP6R_Msk                    /*!< AES Suspend registers 6 */
+
+/*******************  Bit definition for AES_SUSP7R register  ******************/
+#define AES_SUSP7R_Pos                       (0U)                              
+#define AES_SUSP7R_Msk                       (0xFFFFFFFFU << AES_SUSP7R_Pos)   /*!< 0xFFFFFFFF */
+#define AES_SUSP7R                           AES_SUSP7R_Msk                    /*!< AES Suspend registers 7 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos                       (0U)                              
+#define DAC_CR_EN1_Msk                       (0x1U << DAC_CR_EN1_Pos)          /*!< 0x00000001 */
+#define DAC_CR_EN1                           DAC_CR_EN1_Msk                    /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos                      (2U)                              
+#define DAC_CR_TEN1_Msk                      (0x1U << DAC_CR_TEN1_Pos)         /*!< 0x00000004 */
+#define DAC_CR_TEN1                          DAC_CR_TEN1_Msk                   /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos                     (3U)                              
+#define DAC_CR_TSEL1_Msk                     (0x7U << DAC_CR_TSEL1_Pos)        /*!< 0x00000038 */
+#define DAC_CR_TSEL1                         DAC_CR_TSEL1_Msk                  /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0                       (0x1U << DAC_CR_TSEL1_Pos)        /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1                       (0x2U << DAC_CR_TSEL1_Pos)        /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2                       (0x4U << DAC_CR_TSEL1_Pos)        /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos                     (6U)                              
+#define DAC_CR_WAVE1_Msk                     (0x3U << DAC_CR_WAVE1_Pos)        /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                         DAC_CR_WAVE1_Msk                  /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0                       (0x1U << DAC_CR_WAVE1_Pos)        /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1                       (0x2U << DAC_CR_WAVE1_Pos)        /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos                     (8U)                              
+#define DAC_CR_MAMP1_Msk                     (0xFU << DAC_CR_MAMP1_Pos)        /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                         DAC_CR_MAMP1_Msk                  /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0                       (0x1U << DAC_CR_MAMP1_Pos)        /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1                       (0x2U << DAC_CR_MAMP1_Pos)        /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2                       (0x4U << DAC_CR_MAMP1_Pos)        /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3                       (0x8U << DAC_CR_MAMP1_Pos)        /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos                    (12U)                             
+#define DAC_CR_DMAEN1_Msk                    (0x1U << DAC_CR_DMAEN1_Pos)       /*!< 0x00001000 */
+#define DAC_CR_DMAEN1                        DAC_CR_DMAEN1_Msk                 /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos                 (13U)                             
+#define DAC_CR_DMAUDRIE1_Msk                 (0x1U << DAC_CR_DMAUDRIE1_Pos)    /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1                     DAC_CR_DMAUDRIE1_Msk              /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos                      (14U)                             
+#define DAC_CR_CEN1_Msk                      (0x1U << DAC_CR_CEN1_Pos)         /*!< 0x00004000 */
+#define DAC_CR_CEN1                          DAC_CR_CEN1_Msk                   /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos                       (16U)                             
+#define DAC_CR_EN2_Msk                       (0x1U << DAC_CR_EN2_Pos)          /*!< 0x00010000 */
+#define DAC_CR_EN2                           DAC_CR_EN2_Msk                    /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos                      (18U)                             
+#define DAC_CR_TEN2_Msk                      (0x1U << DAC_CR_TEN2_Pos)         /*!< 0x00040000 */
+#define DAC_CR_TEN2                          DAC_CR_TEN2_Msk                   /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos                     (19U)                             
+#define DAC_CR_TSEL2_Msk                     (0x7U << DAC_CR_TSEL2_Pos)        /*!< 0x00380000 */
+#define DAC_CR_TSEL2                         DAC_CR_TSEL2_Msk                  /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0                       (0x1U << DAC_CR_TSEL2_Pos)        /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1                       (0x2U << DAC_CR_TSEL2_Pos)        /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2                       (0x4U << DAC_CR_TSEL2_Pos)        /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos                     (22U)                             
+#define DAC_CR_WAVE2_Msk                     (0x3U << DAC_CR_WAVE2_Pos)        /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                         DAC_CR_WAVE2_Msk                  /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0                       (0x1U << DAC_CR_WAVE2_Pos)        /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1                       (0x2U << DAC_CR_WAVE2_Pos)        /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos                     (24U)                             
+#define DAC_CR_MAMP2_Msk                     (0xFU << DAC_CR_MAMP2_Pos)        /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                         DAC_CR_MAMP2_Msk                  /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0                       (0x1U << DAC_CR_MAMP2_Pos)        /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1                       (0x2U << DAC_CR_MAMP2_Pos)        /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2                       (0x4U << DAC_CR_MAMP2_Pos)        /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3                       (0x8U << DAC_CR_MAMP2_Pos)        /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos                    (28U)                             
+#define DAC_CR_DMAEN2_Msk                    (0x1U << DAC_CR_DMAEN2_Pos)       /*!< 0x10000000 */
+#define DAC_CR_DMAEN2                        DAC_CR_DMAEN2_Msk                 /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos                 (29U)                             
+#define DAC_CR_DMAUDRIE2_Msk                 (0x1U << DAC_CR_DMAUDRIE2_Pos)    /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2                     DAC_CR_DMAUDRIE2_Msk              /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos                      (30U)                             
+#define DAC_CR_CEN2_Msk                      (0x1U << DAC_CR_CEN2_Pos)         /*!< 0x40000000 */
+#define DAC_CR_CEN2                          DAC_CR_CEN2_Msk                   /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos              (0U)                              
+#define DAC_SWTRIGR_SWTRIG1_Msk              (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1                  DAC_SWTRIGR_SWTRIG1_Msk           /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos              (1U)                              
+#define DAC_SWTRIGR_SWTRIG2_Msk              (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2                  DAC_SWTRIGR_SWTRIG2_Msk           /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos             (0U)                              
+#define DAC_DHR12R1_DACC1DHR_Msk             (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR                 DAC_DHR12R1_DACC1DHR_Msk          /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos             (4U)                              
+#define DAC_DHR12L1_DACC1DHR_Msk             (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR                 DAC_DHR12L1_DACC1DHR_Msk          /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos              (0U)                              
+#define DAC_DHR8R1_DACC1DHR_Msk              (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR                  DAC_DHR8R1_DACC1DHR_Msk           /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos             (0U)                              
+#define DAC_DHR12R2_DACC2DHR_Msk             (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR                 DAC_DHR12R2_DACC2DHR_Msk          /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos             (4U)                              
+#define DAC_DHR12L2_DACC2DHR_Msk             (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR                 DAC_DHR12L2_DACC2DHR_Msk          /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos              (0U)                              
+#define DAC_DHR8R2_DACC2DHR_Msk              (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR                  DAC_DHR8R2_DACC2DHR_Msk           /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos             (0U)                              
+#define DAC_DHR12RD_DACC1DHR_Msk             (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR                 DAC_DHR12RD_DACC1DHR_Msk          /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos             (16U)                             
+#define DAC_DHR12RD_DACC2DHR_Msk             (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR                 DAC_DHR12RD_DACC2DHR_Msk          /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos             (4U)                              
+#define DAC_DHR12LD_DACC1DHR_Msk             (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR                 DAC_DHR12LD_DACC1DHR_Msk          /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos             (20U)                             
+#define DAC_DHR12LD_DACC2DHR_Msk             (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR                 DAC_DHR12LD_DACC2DHR_Msk          /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos              (0U)                              
+#define DAC_DHR8RD_DACC1DHR_Msk              (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR                  DAC_DHR8RD_DACC1DHR_Msk           /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos              (8U)                              
+#define DAC_DHR8RD_DACC2DHR_Msk              (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR                  DAC_DHR8RD_DACC2DHR_Msk           /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos                (0U)                              
+#define DAC_DOR1_DACC1DOR_Msk                (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR                    DAC_DOR1_DACC1DOR_Msk             /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos                (0U)                              
+#define DAC_DOR2_DACC2DOR_Msk                (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR                    DAC_DOR2_DACC2DOR_Msk             /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos                   (13U)                             
+#define DAC_SR_DMAUDR1_Msk                   (0x1U << DAC_SR_DMAUDR1_Pos)      /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1                       DAC_SR_DMAUDR1_Msk                /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos                 (14U)                             
+#define DAC_SR_CAL_FLAG1_Msk                 (0x1U << DAC_SR_CAL_FLAG1_Pos)    /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1                     DAC_SR_CAL_FLAG1_Msk              /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos                     (15U)                             
+#define DAC_SR_BWST1_Msk                     (0x4001U << DAC_SR_BWST1_Pos)     /*!< 0x20008000 */
+#define DAC_SR_BWST1                         DAC_SR_BWST1_Msk                  /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos                   (29U)                             
+#define DAC_SR_DMAUDR2_Msk                   (0x1U << DAC_SR_DMAUDR2_Pos)      /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2                       DAC_SR_DMAUDR2_Msk                /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos                 (30U)                             
+#define DAC_SR_CAL_FLAG2_Msk                 (0x1U << DAC_SR_CAL_FLAG2_Pos)    /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2                     DAC_SR_CAL_FLAG2_Msk              /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos                     (31U)                             
+#define DAC_SR_BWST2_Msk                     (0x1U << DAC_SR_BWST2_Pos)        /*!< 0x80000000 */
+#define DAC_SR_BWST2                         DAC_SR_BWST2_Msk                  /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos                   (0U)                              
+#define DAC_CCR_OTRIM1_Msk                   (0x1FU << DAC_CCR_OTRIM1_Pos)     /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1                       DAC_CCR_OTRIM1_Msk                /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos                   (16U)                             
+#define DAC_CCR_OTRIM2_Msk                   (0x1FU << DAC_CCR_OTRIM2_Pos)     /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2                       DAC_CCR_OTRIM2_Msk                /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos                    (0U)                              
+#define DAC_MCR_MODE1_Msk                    (0x7U << DAC_MCR_MODE1_Pos)       /*!< 0x00000007 */
+#define DAC_MCR_MODE1                        DAC_MCR_MODE1_Msk                 /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0                      (0x1U << DAC_MCR_MODE1_Pos)       /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1                      (0x2U << DAC_MCR_MODE1_Pos)       /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2                      (0x4U << DAC_MCR_MODE1_Pos)       /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos                    (16U)                             
+#define DAC_MCR_MODE2_Msk                    (0x7U << DAC_MCR_MODE2_Pos)       /*!< 0x00070000 */
+#define DAC_MCR_MODE2                        DAC_MCR_MODE2_Msk                 /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0                      (0x1U << DAC_MCR_MODE2_Pos)       /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1                      (0x2U << DAC_MCR_MODE2_Pos)       /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2                      (0x4U << DAC_MCR_MODE2_Pos)       /*!< 0x00040000 */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos               (0U)                              
+#define DAC_SHSR1_TSAMPLE1_Msk               (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1                   DAC_SHSR1_TSAMPLE1_Msk            /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos               (0U)                              
+#define DAC_SHSR2_TSAMPLE2_Msk               (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2                   DAC_SHSR2_TSAMPLE2_Msk            /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos                  (0U)                              
+#define DAC_SHHR_THOLD1_Msk                  (0x3FFU << DAC_SHHR_THOLD1_Pos)   /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1                      DAC_SHHR_THOLD1_Msk               /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos                  (16U)                             
+#define DAC_SHHR_THOLD2_Msk                  (0x3FFU << DAC_SHHR_THOLD2_Pos)   /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2                      DAC_SHHR_THOLD2_Msk               /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos               (0U)                              
+#define DAC_SHRR_TREFRESH1_Msk               (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1                   DAC_SHRR_TREFRESH1_Msk            /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos               (16U)                             
+#define DAC_SHRR_TREFRESH2_Msk               (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2                   DAC_SHRR_TREFRESH2_Msk            /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital Filter for Sigma Delta Modulators                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************   DFSDM channel configuration registers  ********************/
+
+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos            (31U)                             
+#define DFSDM_CHCFGR1_DFSDMEN_Msk            (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN                DFSDM_CHCFGR1_DFSDMEN_Msk         /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos           (30U)                             
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk           (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC               DFSDM_CHCFGR1_CKOUTSRC_Msk        /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos           (16U)                             
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk           (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV               DFSDM_CHCFGR1_CKOUTDIV_Msk        /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos            (14U)                             
+#define DFSDM_CHCFGR1_DATPACK_Msk            (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK                DFSDM_CHCFGR1_DATPACK_Msk         /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1              (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0              (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos             (12U)                             
+#define DFSDM_CHCFGR1_DATMPX_Msk             (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX                 DFSDM_CHCFGR1_DATMPX_Msk          /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1               (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0               (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos            (8U)                              
+#define DFSDM_CHCFGR1_CHINSEL_Msk            (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL                DFSDM_CHCFGR1_CHINSEL_Msk         /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos               (7U)                              
+#define DFSDM_CHCFGR1_CHEN_Msk               (0x1U << DFSDM_CHCFGR1_CHEN_Pos)  /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN                   DFSDM_CHCFGR1_CHEN_Msk            /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos             (6U)                              
+#define DFSDM_CHCFGR1_CKABEN_Msk             (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN                 DFSDM_CHCFGR1_CKABEN_Msk          /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos              (5U)                              
+#define DFSDM_CHCFGR1_SCDEN_Msk              (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN                  DFSDM_CHCFGR1_SCDEN_Msk           /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos           (2U)                              
+#define DFSDM_CHCFGR1_SPICKSEL_Msk           (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL               DFSDM_CHCFGR1_SPICKSEL_Msk        /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1             (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0             (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos               (0U)                              
+#define DFSDM_CHCFGR1_SITP_Msk               (0x3U << DFSDM_CHCFGR1_SITP_Pos)  /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP                   DFSDM_CHCFGR1_SITP_Msk            /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1                 (0x2U << DFSDM_CHCFGR1_SITP_Pos)  /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0                 (0x1U << DFSDM_CHCFGR1_SITP_Pos)  /*!< 0x00000001 */
+
+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos             (8U)                              
+#define DFSDM_CHCFGR2_OFFSET_Msk             (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET                 DFSDM_CHCFGR2_OFFSET_Msk          /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos              (3U)                              
+#define DFSDM_CHCFGR2_DTRBS_Msk              (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS                  DFSDM_CHCFGR2_DTRBS_Msk           /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/****************  Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos            (22U)                             
+#define DFSDM_CHAWSCDR_AWFORD_Msk            (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD                DFSDM_CHAWSCDR_AWFORD_Msk         /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1              (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0              (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos            (16U)                             
+#define DFSDM_CHAWSCDR_AWFOSR_Msk            (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR                DFSDM_CHAWSCDR_AWFOSR_Msk         /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos             (12U)                             
+#define DFSDM_CHAWSCDR_BKSCD_Msk             (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD                 DFSDM_CHAWSCDR_BKSCD_Msk          /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos              (0U)                              
+#define DFSDM_CHAWSCDR_SCDT_Msk              (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT                  DFSDM_CHAWSCDR_SCDT_Msk           /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/****************  Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos              (0U)                              
+#define DFSDM_CHWDATR_WDATA_Msk              (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA                  DFSDM_CHWDATR_WDATA_Msk           /*!< WDATA[15:0] Input channel y watchdog data */
+
+/****************  Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos            (0U)                              
+#define DFSDM_CHDATINR_INDAT0_Msk            (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0                DFSDM_CHDATINR_INDAT0_Msk         /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos            (16U)                             
+#define DFSDM_CHDATINR_INDAT1_Msk            (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1                DFSDM_CHDATINR_INDAT1_Msk         /*!< INDAT0[15:0] Input data for channel y */
+
+/************************   DFSDM module registers  ****************************/
+
+/*****************  Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos              (30U)                             
+#define DFSDM_FLTCR1_AWFSEL_Msk              (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL                  DFSDM_FLTCR1_AWFSEL_Msk           /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos                (29U)                             
+#define DFSDM_FLTCR1_FAST_Msk                (0x1U << DFSDM_FLTCR1_FAST_Pos)   /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST                    DFSDM_FLTCR1_FAST_Msk             /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos                 (24U)                             
+#define DFSDM_FLTCR1_RCH_Msk                 (0x7U << DFSDM_FLTCR1_RCH_Pos)    /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH                     DFSDM_FLTCR1_RCH_Msk              /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos              (21U)                             
+#define DFSDM_FLTCR1_RDMAEN_Msk              (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN                  DFSDM_FLTCR1_RDMAEN_Msk           /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos               (19U)                             
+#define DFSDM_FLTCR1_RSYNC_Msk               (0x1U << DFSDM_FLTCR1_RSYNC_Pos)  /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC                   DFSDM_FLTCR1_RSYNC_Msk            /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos               (18U)                             
+#define DFSDM_FLTCR1_RCONT_Msk               (0x1U << DFSDM_FLTCR1_RCONT_Pos)  /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT                   DFSDM_FLTCR1_RCONT_Msk            /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos            (17U)                             
+#define DFSDM_FLTCR1_RSWSTART_Msk            (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART                DFSDM_FLTCR1_RSWSTART_Msk         /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos              (13U)                             
+#define DFSDM_FLTCR1_JEXTEN_Msk              (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN                  DFSDM_FLTCR1_JEXTEN_Msk           /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1                (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0                (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos             (8U)                              
+#define DFSDM_FLTCR1_JEXTSEL_Msk             (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000700 */
+#define DFSDM_FLTCR1_JEXTSEL                 DFSDM_FLTCR1_JEXTSEL_Msk          /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_2               (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_1               (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_0               (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JDMAEN_Pos              (5U)                              
+#define DFSDM_FLTCR1_JDMAEN_Msk              (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN                  DFSDM_FLTCR1_JDMAEN_Msk           /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos               (4U)                              
+#define DFSDM_FLTCR1_JSCAN_Msk               (0x1U << DFSDM_FLTCR1_JSCAN_Pos)  /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN                   DFSDM_FLTCR1_JSCAN_Msk            /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos               (3U)                              
+#define DFSDM_FLTCR1_JSYNC_Msk               (0x1U << DFSDM_FLTCR1_JSYNC_Pos)  /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC                   DFSDM_FLTCR1_JSYNC_Msk            /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
+#define DFSDM_FLTCR1_JSWSTART_Pos            (1U)                              
+#define DFSDM_FLTCR1_JSWSTART_Msk            (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART                DFSDM_FLTCR1_JSWSTART_Msk         /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos                (0U)                              
+#define DFSDM_FLTCR1_DFEN_Msk                (0x1U << DFSDM_FLTCR1_DFEN_Pos)   /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN                    DFSDM_FLTCR1_DFEN_Msk             /*!< DFSDM enable */
+
+/*****************  Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos               (16U)                             
+#define DFSDM_FLTCR2_AWDCH_Msk               (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH                   DFSDM_FLTCR2_AWDCH_Msk            /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos                (8U)                              
+#define DFSDM_FLTCR2_EXCH_Msk                (0xFFU << DFSDM_FLTCR2_EXCH_Pos)  /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH                    DFSDM_FLTCR2_EXCH_Msk             /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos              (6U)                              
+#define DFSDM_FLTCR2_CKABIE_Msk              (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE                  DFSDM_FLTCR2_CKABIE_Msk           /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos               (5U)                              
+#define DFSDM_FLTCR2_SCDIE_Msk               (0x1U << DFSDM_FLTCR2_SCDIE_Pos)  /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE                   DFSDM_FLTCR2_SCDIE_Msk            /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos               (4U)                              
+#define DFSDM_FLTCR2_AWDIE_Msk               (0x1U << DFSDM_FLTCR2_AWDIE_Pos)  /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE                   DFSDM_FLTCR2_AWDIE_Msk            /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos              (3U)                              
+#define DFSDM_FLTCR2_ROVRIE_Msk              (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE                  DFSDM_FLTCR2_ROVRIE_Msk           /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos              (2U)                              
+#define DFSDM_FLTCR2_JOVRIE_Msk              (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE                  DFSDM_FLTCR2_JOVRIE_Msk           /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos              (1U)                              
+#define DFSDM_FLTCR2_REOCIE_Msk              (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE                  DFSDM_FLTCR2_REOCIE_Msk           /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos              (0U)                              
+#define DFSDM_FLTCR2_JEOCIE_Msk              (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE                  DFSDM_FLTCR2_JEOCIE_Msk           /*!< Injected end of conversion interrupt enable */
+
+/*****************  Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos                (24U)                             
+#define DFSDM_FLTISR_SCDF_Msk                (0xFFU << DFSDM_FLTISR_SCDF_Pos)  /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF                    DFSDM_FLTISR_SCDF_Msk             /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos               (16U)                             
+#define DFSDM_FLTISR_CKABF_Msk               (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF                   DFSDM_FLTISR_CKABF_Msk            /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos                (14U)                             
+#define DFSDM_FLTISR_RCIP_Msk                (0x1U << DFSDM_FLTISR_RCIP_Pos)   /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP                    DFSDM_FLTISR_RCIP_Msk             /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos                (13U)                             
+#define DFSDM_FLTISR_JCIP_Msk                (0x1U << DFSDM_FLTISR_JCIP_Pos)   /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP                    DFSDM_FLTISR_JCIP_Msk             /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos                (4U)                              
+#define DFSDM_FLTISR_AWDF_Msk                (0x1U << DFSDM_FLTISR_AWDF_Pos)   /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF                    DFSDM_FLTISR_AWDF_Msk             /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos               (3U)                              
+#define DFSDM_FLTISR_ROVRF_Msk               (0x1U << DFSDM_FLTISR_ROVRF_Pos)  /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF                   DFSDM_FLTISR_ROVRF_Msk            /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos               (2U)                              
+#define DFSDM_FLTISR_JOVRF_Msk               (0x1U << DFSDM_FLTISR_JOVRF_Pos)  /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF                   DFSDM_FLTISR_JOVRF_Msk            /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos               (1U)                              
+#define DFSDM_FLTISR_REOCF_Msk               (0x1U << DFSDM_FLTISR_REOCF_Pos)  /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF                   DFSDM_FLTISR_REOCF_Msk            /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos               (0U)                              
+#define DFSDM_FLTISR_JEOCF_Msk               (0x1U << DFSDM_FLTISR_JEOCF_Pos)  /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF                   DFSDM_FLTISR_JEOCF_Msk            /*!< End of injected conversion flag */
+
+/*****************  Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCSDF_Pos            (24U)                             
+#define DFSDM_FLTICR_CLRSCSDF_Msk            (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCSDF                DFSDM_FLTICR_CLRSCSDF_Msk         /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos            (16U)                             
+#define DFSDM_FLTICR_CLRCKABF_Msk            (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF                DFSDM_FLTICR_CLRCKABF_Msk         /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos            (3U)                              
+#define DFSDM_FLTICR_CLRROVRF_Msk            (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF                DFSDM_FLTICR_CLRROVRF_Msk         /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos            (2U)                              
+#define DFSDM_FLTICR_CLRJOVRF_Msk            (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF                DFSDM_FLTICR_CLRJOVRF_Msk         /*!< Clear the injected conversion overrun flag */
+
+/****************  Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos              (0U)                              
+#define DFSDM_FLTJCHGR_JCHG_Msk              (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG                  DFSDM_FLTJCHGR_JCHG_Msk           /*!< JCHG[7:0] Injected channel group selection */
+
+/*****************  Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos                (29U)                             
+#define DFSDM_FLTFCR_FORD_Msk                (0x7U << DFSDM_FLTFCR_FORD_Pos)   /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD                    DFSDM_FLTFCR_FORD_Msk             /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2                  (0x4U << DFSDM_FLTFCR_FORD_Pos)   /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1                  (0x2U << DFSDM_FLTFCR_FORD_Pos)   /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0                  (0x1U << DFSDM_FLTFCR_FORD_Pos)   /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos                (16U)                             
+#define DFSDM_FLTFCR_FOSR_Msk                (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR                    DFSDM_FLTFCR_FOSR_Msk             /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos                (0U)                              
+#define DFSDM_FLTFCR_IOSR_Msk                (0xFFU << DFSDM_FLTFCR_IOSR_Pos)  /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR                    DFSDM_FLTFCR_IOSR_Msk             /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/***************  Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos            (8U)                              
+#define DFSDM_FLTJDATAR_JDATA_Msk            (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA                DFSDM_FLTJDATAR_JDATA_Msk         /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos          (0U)                              
+#define DFSDM_FLTJDATAR_JDATACH_Msk          (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH              DFSDM_FLTJDATAR_JDATACH_Msk       /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/***************  Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos            (8U)                              
+#define DFSDM_FLTRDATAR_RDATA_Msk            (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA                DFSDM_FLTRDATAR_RDATA_Msk         /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos            (4U)                              
+#define DFSDM_FLTRDATAR_RPEND_Msk            (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND                DFSDM_FLTRDATAR_RPEND_Msk         /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos          (0U)                              
+#define DFSDM_FLTRDATAR_RDATACH_Msk          (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH              DFSDM_FLTRDATAR_RDATACH_Msk       /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/***************  Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos              (8U)                              
+#define DFSDM_FLTAWHTR_AWHT_Msk              (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT                  DFSDM_FLTAWHTR_AWHT_Msk           /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos             (0U)                              
+#define DFSDM_FLTAWHTR_BKAWH_Msk             (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH                 DFSDM_FLTAWHTR_BKAWH_Msk          /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/***************  Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos              (8U)                              
+#define DFSDM_FLTAWLTR_AWLT_Msk              (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT                  DFSDM_FLTAWLTR_AWLT_Msk           /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos             (0U)                              
+#define DFSDM_FLTAWLTR_BKAWL_Msk             (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL                 DFSDM_FLTAWLTR_BKAWL_Msk          /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/***************  Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos              (8U)                              
+#define DFSDM_FLTAWSR_AWHTF_Msk              (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF                  DFSDM_FLTAWSR_AWHTF_Msk           /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos              (0U)                              
+#define DFSDM_FLTAWSR_AWLTF_Msk              (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF                  DFSDM_FLTAWSR_AWLTF_Msk           /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/***************  Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos          (8U)                              
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk          (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF              DFSDM_FLTAWCFR_CLRAWHTF_Msk       /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos          (0U)                              
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk          (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF              DFSDM_FLTAWCFR_CLRAWLTF_Msk       /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/***************  Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos             (8U)                              
+#define DFSDM_FLTEXMAX_EXMAX_Msk             (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX                 DFSDM_FLTEXMAX_EXMAX_Msk          /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos           (0U)                              
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk           (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH               DFSDM_FLTEXMAX_EXMAXCH_Msk        /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/***************  Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos             (8U)                              
+#define DFSDM_FLTEXMIN_EXMIN_Msk             (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN                 DFSDM_FLTEXMIN_EXMIN_Msk          /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos           (0U)                              
+#define DFSDM_FLTEXMIN_EXMINCH_Msk           (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH               DFSDM_FLTEXMIN_EXMINCH_Msk        /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos          (4U)                              
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk          (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT              DFSDM_FLTCNVTIMR_CNVCNT_Msk       /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define DMA_ISR_GIF1_Pos                       (0U)                            
+#define DMA_ISR_GIF1_Msk                       (0x1U << DMA_ISR_GIF1_Pos)      /*!< 0x00000001 */
+#define DMA_ISR_GIF1                           DMA_ISR_GIF1_Msk                /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos                      (1U)                            
+#define DMA_ISR_TCIF1_Msk                      (0x1U << DMA_ISR_TCIF1_Pos)     /*!< 0x00000002 */
+#define DMA_ISR_TCIF1                          DMA_ISR_TCIF1_Msk               /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos                      (2U)                            
+#define DMA_ISR_HTIF1_Msk                      (0x1U << DMA_ISR_HTIF1_Pos)     /*!< 0x00000004 */
+#define DMA_ISR_HTIF1                          DMA_ISR_HTIF1_Msk               /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos                      (3U)                            
+#define DMA_ISR_TEIF1_Msk                      (0x1U << DMA_ISR_TEIF1_Pos)     /*!< 0x00000008 */
+#define DMA_ISR_TEIF1                          DMA_ISR_TEIF1_Msk               /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos                       (4U)                            
+#define DMA_ISR_GIF2_Msk                       (0x1U << DMA_ISR_GIF2_Pos)      /*!< 0x00000010 */
+#define DMA_ISR_GIF2                           DMA_ISR_GIF2_Msk                /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos                      (5U)                            
+#define DMA_ISR_TCIF2_Msk                      (0x1U << DMA_ISR_TCIF2_Pos)     /*!< 0x00000020 */
+#define DMA_ISR_TCIF2                          DMA_ISR_TCIF2_Msk               /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos                      (6U)                            
+#define DMA_ISR_HTIF2_Msk                      (0x1U << DMA_ISR_HTIF2_Pos)     /*!< 0x00000040 */
+#define DMA_ISR_HTIF2                          DMA_ISR_HTIF2_Msk               /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos                      (7U)                            
+#define DMA_ISR_TEIF2_Msk                      (0x1U << DMA_ISR_TEIF2_Pos)     /*!< 0x00000080 */
+#define DMA_ISR_TEIF2                          DMA_ISR_TEIF2_Msk               /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos                       (8U)                            
+#define DMA_ISR_GIF3_Msk                       (0x1U << DMA_ISR_GIF3_Pos)      /*!< 0x00000100 */
+#define DMA_ISR_GIF3                           DMA_ISR_GIF3_Msk                /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos                      (9U)                            
+#define DMA_ISR_TCIF3_Msk                      (0x1U << DMA_ISR_TCIF3_Pos)     /*!< 0x00000200 */
+#define DMA_ISR_TCIF3                          DMA_ISR_TCIF3_Msk               /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos                      (10U)                           
+#define DMA_ISR_HTIF3_Msk                      (0x1U << DMA_ISR_HTIF3_Pos)     /*!< 0x00000400 */
+#define DMA_ISR_HTIF3                          DMA_ISR_HTIF3_Msk               /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos                      (11U)                           
+#define DMA_ISR_TEIF3_Msk                      (0x1U << DMA_ISR_TEIF3_Pos)     /*!< 0x00000800 */
+#define DMA_ISR_TEIF3                          DMA_ISR_TEIF3_Msk               /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos                       (12U)                           
+#define DMA_ISR_GIF4_Msk                       (0x1U << DMA_ISR_GIF4_Pos)      /*!< 0x00001000 */
+#define DMA_ISR_GIF4                           DMA_ISR_GIF4_Msk                /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos                      (13U)                           
+#define DMA_ISR_TCIF4_Msk                      (0x1U << DMA_ISR_TCIF4_Pos)     /*!< 0x00002000 */
+#define DMA_ISR_TCIF4                          DMA_ISR_TCIF4_Msk               /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos                      (14U)                           
+#define DMA_ISR_HTIF4_Msk                      (0x1U << DMA_ISR_HTIF4_Pos)     /*!< 0x00004000 */
+#define DMA_ISR_HTIF4                          DMA_ISR_HTIF4_Msk               /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos                      (15U)                           
+#define DMA_ISR_TEIF4_Msk                      (0x1U << DMA_ISR_TEIF4_Pos)     /*!< 0x00008000 */
+#define DMA_ISR_TEIF4                          DMA_ISR_TEIF4_Msk               /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos                       (16U)                           
+#define DMA_ISR_GIF5_Msk                       (0x1U << DMA_ISR_GIF5_Pos)      /*!< 0x00010000 */
+#define DMA_ISR_GIF5                           DMA_ISR_GIF5_Msk                /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos                      (17U)                           
+#define DMA_ISR_TCIF5_Msk                      (0x1U << DMA_ISR_TCIF5_Pos)     /*!< 0x00020000 */
+#define DMA_ISR_TCIF5                          DMA_ISR_TCIF5_Msk               /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos                      (18U)                           
+#define DMA_ISR_HTIF5_Msk                      (0x1U << DMA_ISR_HTIF5_Pos)     /*!< 0x00040000 */
+#define DMA_ISR_HTIF5                          DMA_ISR_HTIF5_Msk               /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos                      (19U)                           
+#define DMA_ISR_TEIF5_Msk                      (0x1U << DMA_ISR_TEIF5_Pos)     /*!< 0x00080000 */
+#define DMA_ISR_TEIF5                          DMA_ISR_TEIF5_Msk               /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos                       (20U)                           
+#define DMA_ISR_GIF6_Msk                       (0x1U << DMA_ISR_GIF6_Pos)      /*!< 0x00100000 */
+#define DMA_ISR_GIF6                           DMA_ISR_GIF6_Msk                /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos                      (21U)                           
+#define DMA_ISR_TCIF6_Msk                      (0x1U << DMA_ISR_TCIF6_Pos)     /*!< 0x00200000 */
+#define DMA_ISR_TCIF6                          DMA_ISR_TCIF6_Msk               /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos                      (22U)                           
+#define DMA_ISR_HTIF6_Msk                      (0x1U << DMA_ISR_HTIF6_Pos)     /*!< 0x00400000 */
+#define DMA_ISR_HTIF6                          DMA_ISR_HTIF6_Msk               /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos                      (23U)                           
+#define DMA_ISR_TEIF6_Msk                      (0x1U << DMA_ISR_TEIF6_Pos)     /*!< 0x00800000 */
+#define DMA_ISR_TEIF6                          DMA_ISR_TEIF6_Msk               /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos                       (24U)                           
+#define DMA_ISR_GIF7_Msk                       (0x1U << DMA_ISR_GIF7_Pos)      /*!< 0x01000000 */
+#define DMA_ISR_GIF7                           DMA_ISR_GIF7_Msk                /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos                      (25U)                           
+#define DMA_ISR_TCIF7_Msk                      (0x1U << DMA_ISR_TCIF7_Pos)     /*!< 0x02000000 */
+#define DMA_ISR_TCIF7                          DMA_ISR_TCIF7_Msk               /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos                      (26U)                           
+#define DMA_ISR_HTIF7_Msk                      (0x1U << DMA_ISR_HTIF7_Pos)     /*!< 0x04000000 */
+#define DMA_ISR_HTIF7                          DMA_ISR_HTIF7_Msk               /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos                      (27U)                           
+#define DMA_ISR_TEIF7_Msk                      (0x1U << DMA_ISR_TEIF7_Pos)     /*!< 0x08000000 */
+#define DMA_ISR_TEIF7                          DMA_ISR_TEIF7_Msk               /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define DMA_IFCR_CGIF1_Pos                     (0U)                            
+#define DMA_IFCR_CGIF1_Msk                     (0x1U << DMA_IFCR_CGIF1_Pos)    /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1                         DMA_IFCR_CGIF1_Msk              /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1_Pos                    (1U)                            
+#define DMA_IFCR_CTCIF1_Msk                    (0x1U << DMA_IFCR_CTCIF1_Pos)   /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1                        DMA_IFCR_CTCIF1_Msk             /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos                    (2U)                            
+#define DMA_IFCR_CHTIF1_Msk                    (0x1U << DMA_IFCR_CHTIF1_Pos)   /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1                        DMA_IFCR_CHTIF1_Msk             /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos                    (3U)                            
+#define DMA_IFCR_CTEIF1_Msk                    (0x1U << DMA_IFCR_CTEIF1_Pos)   /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1                        DMA_IFCR_CTEIF1_Msk             /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos                     (4U)                            
+#define DMA_IFCR_CGIF2_Msk                     (0x1U << DMA_IFCR_CGIF2_Pos)    /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2                         DMA_IFCR_CGIF2_Msk              /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos                    (5U)                            
+#define DMA_IFCR_CTCIF2_Msk                    (0x1U << DMA_IFCR_CTCIF2_Pos)   /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2                        DMA_IFCR_CTCIF2_Msk             /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos                    (6U)                            
+#define DMA_IFCR_CHTIF2_Msk                    (0x1U << DMA_IFCR_CHTIF2_Pos)   /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2                        DMA_IFCR_CHTIF2_Msk             /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos                    (7U)                            
+#define DMA_IFCR_CTEIF2_Msk                    (0x1U << DMA_IFCR_CTEIF2_Pos)   /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2                        DMA_IFCR_CTEIF2_Msk             /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos                     (8U)                            
+#define DMA_IFCR_CGIF3_Msk                     (0x1U << DMA_IFCR_CGIF3_Pos)    /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3                         DMA_IFCR_CGIF3_Msk              /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos                    (9U)                            
+#define DMA_IFCR_CTCIF3_Msk                    (0x1U << DMA_IFCR_CTCIF3_Pos)   /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3                        DMA_IFCR_CTCIF3_Msk             /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos                    (10U)                           
+#define DMA_IFCR_CHTIF3_Msk                    (0x1U << DMA_IFCR_CHTIF3_Pos)   /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3                        DMA_IFCR_CHTIF3_Msk             /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos                    (11U)                           
+#define DMA_IFCR_CTEIF3_Msk                    (0x1U << DMA_IFCR_CTEIF3_Pos)   /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3                        DMA_IFCR_CTEIF3_Msk             /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos                     (12U)                           
+#define DMA_IFCR_CGIF4_Msk                     (0x1U << DMA_IFCR_CGIF4_Pos)    /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4                         DMA_IFCR_CGIF4_Msk              /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos                    (13U)                           
+#define DMA_IFCR_CTCIF4_Msk                    (0x1U << DMA_IFCR_CTCIF4_Pos)   /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4                        DMA_IFCR_CTCIF4_Msk             /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos                    (14U)                           
+#define DMA_IFCR_CHTIF4_Msk                    (0x1U << DMA_IFCR_CHTIF4_Pos)   /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4                        DMA_IFCR_CHTIF4_Msk             /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos                    (15U)                           
+#define DMA_IFCR_CTEIF4_Msk                    (0x1U << DMA_IFCR_CTEIF4_Pos)   /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4                        DMA_IFCR_CTEIF4_Msk             /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos                     (16U)                           
+#define DMA_IFCR_CGIF5_Msk                     (0x1U << DMA_IFCR_CGIF5_Pos)    /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5                         DMA_IFCR_CGIF5_Msk              /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos                    (17U)                           
+#define DMA_IFCR_CTCIF5_Msk                    (0x1U << DMA_IFCR_CTCIF5_Pos)   /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5                        DMA_IFCR_CTCIF5_Msk             /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos                    (18U)                           
+#define DMA_IFCR_CHTIF5_Msk                    (0x1U << DMA_IFCR_CHTIF5_Pos)   /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5                        DMA_IFCR_CHTIF5_Msk             /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos                    (19U)                           
+#define DMA_IFCR_CTEIF5_Msk                    (0x1U << DMA_IFCR_CTEIF5_Pos)   /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5                        DMA_IFCR_CTEIF5_Msk             /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos                     (20U)                           
+#define DMA_IFCR_CGIF6_Msk                     (0x1U << DMA_IFCR_CGIF6_Pos)    /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6                         DMA_IFCR_CGIF6_Msk              /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos                    (21U)                           
+#define DMA_IFCR_CTCIF6_Msk                    (0x1U << DMA_IFCR_CTCIF6_Pos)   /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6                        DMA_IFCR_CTCIF6_Msk             /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos                    (22U)                           
+#define DMA_IFCR_CHTIF6_Msk                    (0x1U << DMA_IFCR_CHTIF6_Pos)   /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6                        DMA_IFCR_CHTIF6_Msk             /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos                    (23U)                           
+#define DMA_IFCR_CTEIF6_Msk                    (0x1U << DMA_IFCR_CTEIF6_Pos)   /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6                        DMA_IFCR_CTEIF6_Msk             /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos                     (24U)                           
+#define DMA_IFCR_CGIF7_Msk                     (0x1U << DMA_IFCR_CGIF7_Pos)    /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7                         DMA_IFCR_CGIF7_Msk              /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos                    (25U)                           
+#define DMA_IFCR_CTCIF7_Msk                    (0x1U << DMA_IFCR_CTCIF7_Pos)   /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7                        DMA_IFCR_CTCIF7_Msk             /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos                    (26U)                           
+#define DMA_IFCR_CHTIF7_Msk                    (0x1U << DMA_IFCR_CHTIF7_Pos)   /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7                        DMA_IFCR_CHTIF7_Msk             /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos                    (27U)                           
+#define DMA_IFCR_CTEIF7_Msk                    (0x1U << DMA_IFCR_CTEIF7_Pos)   /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7                        DMA_IFCR_CTEIF7_Msk             /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos                         (0U)                            
+#define DMA_CCR_EN_Msk                         (0x1U << DMA_CCR_EN_Pos)        /*!< 0x00000001 */
+#define DMA_CCR_EN                             DMA_CCR_EN_Msk                  /*!< Channel enable                      */
+#define DMA_CCR_TCIE_Pos                       (1U)                            
+#define DMA_CCR_TCIE_Msk                       (0x1U << DMA_CCR_TCIE_Pos)      /*!< 0x00000002 */
+#define DMA_CCR_TCIE                           DMA_CCR_TCIE_Msk                /*!< Transfer complete interrupt enable  */
+#define DMA_CCR_HTIE_Pos                       (2U)                            
+#define DMA_CCR_HTIE_Msk                       (0x1U << DMA_CCR_HTIE_Pos)      /*!< 0x00000004 */
+#define DMA_CCR_HTIE                           DMA_CCR_HTIE_Msk                /*!< Half Transfer interrupt enable      */
+#define DMA_CCR_TEIE_Pos                       (3U)                            
+#define DMA_CCR_TEIE_Msk                       (0x1U << DMA_CCR_TEIE_Pos)      /*!< 0x00000008 */
+#define DMA_CCR_TEIE                           DMA_CCR_TEIE_Msk                /*!< Transfer error interrupt enable     */
+#define DMA_CCR_DIR_Pos                        (4U)                            
+#define DMA_CCR_DIR_Msk                        (0x1U << DMA_CCR_DIR_Pos)       /*!< 0x00000010 */
+#define DMA_CCR_DIR                            DMA_CCR_DIR_Msk                 /*!< Data transfer direction             */
+#define DMA_CCR_CIRC_Pos                       (5U)                            
+#define DMA_CCR_CIRC_Msk                       (0x1U << DMA_CCR_CIRC_Pos)      /*!< 0x00000020 */
+#define DMA_CCR_CIRC                           DMA_CCR_CIRC_Msk                /*!< Circular mode                       */
+#define DMA_CCR_PINC_Pos                       (6U)                            
+#define DMA_CCR_PINC_Msk                       (0x1U << DMA_CCR_PINC_Pos)      /*!< 0x00000040 */
+#define DMA_CCR_PINC                           DMA_CCR_PINC_Msk                /*!< Peripheral increment mode           */
+#define DMA_CCR_MINC_Pos                       (7U)                            
+#define DMA_CCR_MINC_Msk                       (0x1U << DMA_CCR_MINC_Pos)      /*!< 0x00000080 */
+#define DMA_CCR_MINC                           DMA_CCR_MINC_Msk                /*!< Memory increment mode               */
+
+#define DMA_CCR_PSIZE_Pos                      (8U)                            
+#define DMA_CCR_PSIZE_Msk                      (0x3U << DMA_CCR_PSIZE_Pos)     /*!< 0x00000300 */
+#define DMA_CCR_PSIZE                          DMA_CCR_PSIZE_Msk               /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define DMA_CCR_PSIZE_0                        (0x1U << DMA_CCR_PSIZE_Pos)     /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1                        (0x2U << DMA_CCR_PSIZE_Pos)     /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos                      (10U)                           
+#define DMA_CCR_MSIZE_Msk                      (0x3U << DMA_CCR_MSIZE_Pos)     /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE                          DMA_CCR_MSIZE_Msk               /*!< MSIZE[1:0] bits (Memory size)       */
+#define DMA_CCR_MSIZE_0                        (0x1U << DMA_CCR_MSIZE_Pos)     /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1                        (0x2U << DMA_CCR_MSIZE_Pos)     /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos                         (12U)                           
+#define DMA_CCR_PL_Msk                         (0x3U << DMA_CCR_PL_Pos)        /*!< 0x00003000 */
+#define DMA_CCR_PL                             DMA_CCR_PL_Msk                  /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0                           (0x1U << DMA_CCR_PL_Pos)        /*!< 0x00001000 */
+#define DMA_CCR_PL_1                           (0x2U << DMA_CCR_PL_Pos)        /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos                    (14U)                           
+#define DMA_CCR_MEM2MEM_Msk                    (0x1U << DMA_CCR_MEM2MEM_Pos)   /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM                        DMA_CCR_MEM2MEM_Msk             /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define DMA_CNDTR_NDT_Pos                      (0U)                            
+#define DMA_CNDTR_NDT_Msk                      (0xFFFFU << DMA_CNDTR_NDT_Pos)  /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT                          DMA_CNDTR_NDT_Msk               /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define DMA_CPAR_PA_Pos                        (0U)                            
+#define DMA_CPAR_PA_Msk                        (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA                            DMA_CPAR_PA_Msk                 /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define DMA_CMAR_MA_Pos                        (0U)                            
+#define DMA_CMAR_MA_Msk                        (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA                            DMA_CMAR_MA_Msk                 /*!< Memory Address                      */
+
+
+/*******************  Bit definition for DMA_CSELR register  *******************/
+#define DMA_CSELR_C1S_Pos                      (0U)                            
+#define DMA_CSELR_C1S_Msk                      (0xFU << DMA_CSELR_C1S_Pos)     /*!< 0x0000000F */
+#define DMA_CSELR_C1S                          DMA_CSELR_C1S_Msk               /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos                      (4U)                            
+#define DMA_CSELR_C2S_Msk                      (0xFU << DMA_CSELR_C2S_Pos)     /*!< 0x000000F0 */
+#define DMA_CSELR_C2S                          DMA_CSELR_C2S_Msk               /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos                      (8U)                            
+#define DMA_CSELR_C3S_Msk                      (0xFU << DMA_CSELR_C3S_Pos)     /*!< 0x00000F00 */
+#define DMA_CSELR_C3S                          DMA_CSELR_C3S_Msk               /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos                      (12U)                           
+#define DMA_CSELR_C4S_Msk                      (0xFU << DMA_CSELR_C4S_Pos)     /*!< 0x0000F000 */
+#define DMA_CSELR_C4S                          DMA_CSELR_C4S_Msk               /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos                      (16U)                           
+#define DMA_CSELR_C5S_Msk                      (0xFU << DMA_CSELR_C5S_Pos)     /*!< 0x000F0000 */
+#define DMA_CSELR_C5S                          DMA_CSELR_C5S_Msk               /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos                      (20U)                           
+#define DMA_CSELR_C6S_Msk                      (0xFU << DMA_CSELR_C6S_Pos)     /*!< 0x00F00000 */
+#define DMA_CSELR_C6S                          DMA_CSELR_C6S_Msk               /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos                      (24U)                           
+#define DMA_CSELR_C7S_Msk                      (0xFU << DMA_CSELR_C7S_Pos)     /*!< 0x0F000000 */
+#define DMA_CSELR_C7S                          DMA_CSELR_C7S_Msk               /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR1 register  ******************/
+#define EXTI_IMR1_IM0_Pos                    (0U)                              
+#define EXTI_IMR1_IM0_Msk                    (0x1U << EXTI_IMR1_IM0_Pos)       /*!< 0x00000001 */
+#define EXTI_IMR1_IM0                        EXTI_IMR1_IM0_Msk                 /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos                    (1U)                              
+#define EXTI_IMR1_IM1_Msk                    (0x1U << EXTI_IMR1_IM1_Pos)       /*!< 0x00000002 */
+#define EXTI_IMR1_IM1                        EXTI_IMR1_IM1_Msk                 /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos                    (2U)                              
+#define EXTI_IMR1_IM2_Msk                    (0x1U << EXTI_IMR1_IM2_Pos)       /*!< 0x00000004 */
+#define EXTI_IMR1_IM2                        EXTI_IMR1_IM2_Msk                 /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos                    (3U)                              
+#define EXTI_IMR1_IM3_Msk                    (0x1U << EXTI_IMR1_IM3_Pos)       /*!< 0x00000008 */
+#define EXTI_IMR1_IM3                        EXTI_IMR1_IM3_Msk                 /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos                    (4U)                              
+#define EXTI_IMR1_IM4_Msk                    (0x1U << EXTI_IMR1_IM4_Pos)       /*!< 0x00000010 */
+#define EXTI_IMR1_IM4                        EXTI_IMR1_IM4_Msk                 /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos                    (5U)                              
+#define EXTI_IMR1_IM5_Msk                    (0x1U << EXTI_IMR1_IM5_Pos)       /*!< 0x00000020 */
+#define EXTI_IMR1_IM5                        EXTI_IMR1_IM5_Msk                 /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos                    (6U)                              
+#define EXTI_IMR1_IM6_Msk                    (0x1U << EXTI_IMR1_IM6_Pos)       /*!< 0x00000040 */
+#define EXTI_IMR1_IM6                        EXTI_IMR1_IM6_Msk                 /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos                    (7U)                              
+#define EXTI_IMR1_IM7_Msk                    (0x1U << EXTI_IMR1_IM7_Pos)       /*!< 0x00000080 */
+#define EXTI_IMR1_IM7                        EXTI_IMR1_IM7_Msk                 /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos                    (8U)                              
+#define EXTI_IMR1_IM8_Msk                    (0x1U << EXTI_IMR1_IM8_Pos)       /*!< 0x00000100 */
+#define EXTI_IMR1_IM8                        EXTI_IMR1_IM8_Msk                 /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos                    (9U)                              
+#define EXTI_IMR1_IM9_Msk                    (0x1U << EXTI_IMR1_IM9_Pos)       /*!< 0x00000200 */
+#define EXTI_IMR1_IM9                        EXTI_IMR1_IM9_Msk                 /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos                   (10U)                             
+#define EXTI_IMR1_IM10_Msk                   (0x1U << EXTI_IMR1_IM10_Pos)      /*!< 0x00000400 */
+#define EXTI_IMR1_IM10                       EXTI_IMR1_IM10_Msk                /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos                   (11U)                             
+#define EXTI_IMR1_IM11_Msk                   (0x1U << EXTI_IMR1_IM11_Pos)      /*!< 0x00000800 */
+#define EXTI_IMR1_IM11                       EXTI_IMR1_IM11_Msk                /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos                   (12U)                             
+#define EXTI_IMR1_IM12_Msk                   (0x1U << EXTI_IMR1_IM12_Pos)      /*!< 0x00001000 */
+#define EXTI_IMR1_IM12                       EXTI_IMR1_IM12_Msk                /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos                   (13U)                             
+#define EXTI_IMR1_IM13_Msk                   (0x1U << EXTI_IMR1_IM13_Pos)      /*!< 0x00002000 */
+#define EXTI_IMR1_IM13                       EXTI_IMR1_IM13_Msk                /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos                   (14U)                             
+#define EXTI_IMR1_IM14_Msk                   (0x1U << EXTI_IMR1_IM14_Pos)      /*!< 0x00004000 */
+#define EXTI_IMR1_IM14                       EXTI_IMR1_IM14_Msk                /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos                   (15U)                             
+#define EXTI_IMR1_IM15_Msk                   (0x1U << EXTI_IMR1_IM15_Pos)      /*!< 0x00008000 */
+#define EXTI_IMR1_IM15                       EXTI_IMR1_IM15_Msk                /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos                   (16U)                             
+#define EXTI_IMR1_IM16_Msk                   (0x1U << EXTI_IMR1_IM16_Pos)      /*!< 0x00010000 */
+#define EXTI_IMR1_IM16                       EXTI_IMR1_IM16_Msk                /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos                   (17U)                             
+#define EXTI_IMR1_IM17_Msk                   (0x1U << EXTI_IMR1_IM17_Pos)      /*!< 0x00020000 */
+#define EXTI_IMR1_IM17                       EXTI_IMR1_IM17_Msk                /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos                   (18U)                             
+#define EXTI_IMR1_IM18_Msk                   (0x1U << EXTI_IMR1_IM18_Pos)      /*!< 0x00040000 */
+#define EXTI_IMR1_IM18                       EXTI_IMR1_IM18_Msk                /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos                   (19U)                             
+#define EXTI_IMR1_IM19_Msk                   (0x1U << EXTI_IMR1_IM19_Pos)      /*!< 0x00080000 */
+#define EXTI_IMR1_IM19                       EXTI_IMR1_IM19_Msk                /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos                   (20U)                             
+#define EXTI_IMR1_IM20_Msk                   (0x1U << EXTI_IMR1_IM20_Pos)      /*!< 0x00100000 */
+#define EXTI_IMR1_IM20                       EXTI_IMR1_IM20_Msk                /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos                   (21U)                             
+#define EXTI_IMR1_IM21_Msk                   (0x1U << EXTI_IMR1_IM21_Pos)      /*!< 0x00200000 */
+#define EXTI_IMR1_IM21                       EXTI_IMR1_IM21_Msk                /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos                   (22U)                             
+#define EXTI_IMR1_IM22_Msk                   (0x1U << EXTI_IMR1_IM22_Pos)      /*!< 0x00400000 */
+#define EXTI_IMR1_IM22                       EXTI_IMR1_IM22_Msk                /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos                   (23U)                             
+#define EXTI_IMR1_IM23_Msk                   (0x1U << EXTI_IMR1_IM23_Pos)      /*!< 0x00800000 */
+#define EXTI_IMR1_IM23                       EXTI_IMR1_IM23_Msk                /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos                   (24U)                             
+#define EXTI_IMR1_IM24_Msk                   (0x1U << EXTI_IMR1_IM24_Pos)      /*!< 0x01000000 */
+#define EXTI_IMR1_IM24                       EXTI_IMR1_IM24_Msk                /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos                   (25U)                             
+#define EXTI_IMR1_IM25_Msk                   (0x1U << EXTI_IMR1_IM25_Pos)      /*!< 0x02000000 */
+#define EXTI_IMR1_IM25                       EXTI_IMR1_IM25_Msk                /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos                   (26U)                             
+#define EXTI_IMR1_IM26_Msk                   (0x1U << EXTI_IMR1_IM26_Pos)      /*!< 0x04000000 */
+#define EXTI_IMR1_IM26                       EXTI_IMR1_IM26_Msk                /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos                   (27U)                             
+#define EXTI_IMR1_IM27_Msk                   (0x1U << EXTI_IMR1_IM27_Pos)      /*!< 0x08000000 */
+#define EXTI_IMR1_IM27                       EXTI_IMR1_IM27_Msk                /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos                   (28U)                             
+#define EXTI_IMR1_IM28_Msk                   (0x1U << EXTI_IMR1_IM28_Pos)      /*!< 0x10000000 */
+#define EXTI_IMR1_IM28                       EXTI_IMR1_IM28_Msk                /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos                   (29U)                             
+#define EXTI_IMR1_IM29_Msk                   (0x1U << EXTI_IMR1_IM29_Pos)      /*!< 0x20000000 */
+#define EXTI_IMR1_IM29                       EXTI_IMR1_IM29_Msk                /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos                   (30U)                             
+#define EXTI_IMR1_IM30_Msk                   (0x1U << EXTI_IMR1_IM30_Pos)      /*!< 0x40000000 */
+#define EXTI_IMR1_IM30                       EXTI_IMR1_IM30_Msk                /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos                   (31U)                             
+#define EXTI_IMR1_IM31_Msk                   (0x1U << EXTI_IMR1_IM31_Pos)      /*!< 0x80000000 */
+#define EXTI_IMR1_IM31                       EXTI_IMR1_IM31_Msk                /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos                     (0U)                              
+#define EXTI_IMR1_IM_Msk                     (0xFFFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
+#define EXTI_IMR1_IM                         EXTI_IMR1_IM_Msk                  /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR1 register  ******************/
+#define EXTI_EMR1_EM0_Pos                    (0U)                              
+#define EXTI_EMR1_EM0_Msk                    (0x1U << EXTI_EMR1_EM0_Pos)       /*!< 0x00000001 */
+#define EXTI_EMR1_EM0                        EXTI_EMR1_EM0_Msk                 /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos                    (1U)                              
+#define EXTI_EMR1_EM1_Msk                    (0x1U << EXTI_EMR1_EM1_Pos)       /*!< 0x00000002 */
+#define EXTI_EMR1_EM1                        EXTI_EMR1_EM1_Msk                 /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos                    (2U)                              
+#define EXTI_EMR1_EM2_Msk                    (0x1U << EXTI_EMR1_EM2_Pos)       /*!< 0x00000004 */
+#define EXTI_EMR1_EM2                        EXTI_EMR1_EM2_Msk                 /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos                    (3U)                              
+#define EXTI_EMR1_EM3_Msk                    (0x1U << EXTI_EMR1_EM3_Pos)       /*!< 0x00000008 */
+#define EXTI_EMR1_EM3                        EXTI_EMR1_EM3_Msk                 /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos                    (4U)                              
+#define EXTI_EMR1_EM4_Msk                    (0x1U << EXTI_EMR1_EM4_Pos)       /*!< 0x00000010 */
+#define EXTI_EMR1_EM4                        EXTI_EMR1_EM4_Msk                 /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos                    (5U)                              
+#define EXTI_EMR1_EM5_Msk                    (0x1U << EXTI_EMR1_EM5_Pos)       /*!< 0x00000020 */
+#define EXTI_EMR1_EM5                        EXTI_EMR1_EM5_Msk                 /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos                    (6U)                              
+#define EXTI_EMR1_EM6_Msk                    (0x1U << EXTI_EMR1_EM6_Pos)       /*!< 0x00000040 */
+#define EXTI_EMR1_EM6                        EXTI_EMR1_EM6_Msk                 /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos                    (7U)                              
+#define EXTI_EMR1_EM7_Msk                    (0x1U << EXTI_EMR1_EM7_Pos)       /*!< 0x00000080 */
+#define EXTI_EMR1_EM7                        EXTI_EMR1_EM7_Msk                 /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos                    (8U)                              
+#define EXTI_EMR1_EM8_Msk                    (0x1U << EXTI_EMR1_EM8_Pos)       /*!< 0x00000100 */
+#define EXTI_EMR1_EM8                        EXTI_EMR1_EM8_Msk                 /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos                    (9U)                              
+#define EXTI_EMR1_EM9_Msk                    (0x1U << EXTI_EMR1_EM9_Pos)       /*!< 0x00000200 */
+#define EXTI_EMR1_EM9                        EXTI_EMR1_EM9_Msk                 /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos                   (10U)                             
+#define EXTI_EMR1_EM10_Msk                   (0x1U << EXTI_EMR1_EM10_Pos)      /*!< 0x00000400 */
+#define EXTI_EMR1_EM10                       EXTI_EMR1_EM10_Msk                /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos                   (11U)                             
+#define EXTI_EMR1_EM11_Msk                   (0x1U << EXTI_EMR1_EM11_Pos)      /*!< 0x00000800 */
+#define EXTI_EMR1_EM11                       EXTI_EMR1_EM11_Msk                /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos                   (12U)                             
+#define EXTI_EMR1_EM12_Msk                   (0x1U << EXTI_EMR1_EM12_Pos)      /*!< 0x00001000 */
+#define EXTI_EMR1_EM12                       EXTI_EMR1_EM12_Msk                /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos                   (13U)                             
+#define EXTI_EMR1_EM13_Msk                   (0x1U << EXTI_EMR1_EM13_Pos)      /*!< 0x00002000 */
+#define EXTI_EMR1_EM13                       EXTI_EMR1_EM13_Msk                /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos                   (14U)                             
+#define EXTI_EMR1_EM14_Msk                   (0x1U << EXTI_EMR1_EM14_Pos)      /*!< 0x00004000 */
+#define EXTI_EMR1_EM14                       EXTI_EMR1_EM14_Msk                /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos                   (15U)                             
+#define EXTI_EMR1_EM15_Msk                   (0x1U << EXTI_EMR1_EM15_Pos)      /*!< 0x00008000 */
+#define EXTI_EMR1_EM15                       EXTI_EMR1_EM15_Msk                /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos                   (16U)                             
+#define EXTI_EMR1_EM16_Msk                   (0x1U << EXTI_EMR1_EM16_Pos)      /*!< 0x00010000 */
+#define EXTI_EMR1_EM16                       EXTI_EMR1_EM16_Msk                /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos                   (17U)                             
+#define EXTI_EMR1_EM17_Msk                   (0x1U << EXTI_EMR1_EM17_Pos)      /*!< 0x00020000 */
+#define EXTI_EMR1_EM17                       EXTI_EMR1_EM17_Msk                /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos                   (18U)                             
+#define EXTI_EMR1_EM18_Msk                   (0x1U << EXTI_EMR1_EM18_Pos)      /*!< 0x00040000 */
+#define EXTI_EMR1_EM18                       EXTI_EMR1_EM18_Msk                /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos                   (19U)                             
+#define EXTI_EMR1_EM19_Msk                   (0x1U << EXTI_EMR1_EM19_Pos)      /*!< 0x00080000 */
+#define EXTI_EMR1_EM19                       EXTI_EMR1_EM19_Msk                /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos                   (20U)                             
+#define EXTI_EMR1_EM20_Msk                   (0x1U << EXTI_EMR1_EM20_Pos)      /*!< 0x00100000 */
+#define EXTI_EMR1_EM20                       EXTI_EMR1_EM20_Msk                /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos                   (21U)                             
+#define EXTI_EMR1_EM21_Msk                   (0x1U << EXTI_EMR1_EM21_Pos)      /*!< 0x00200000 */
+#define EXTI_EMR1_EM21                       EXTI_EMR1_EM21_Msk                /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos                   (22U)                             
+#define EXTI_EMR1_EM22_Msk                   (0x1U << EXTI_EMR1_EM22_Pos)      /*!< 0x00400000 */
+#define EXTI_EMR1_EM22                       EXTI_EMR1_EM22_Msk                /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos                   (23U)                             
+#define EXTI_EMR1_EM23_Msk                   (0x1U << EXTI_EMR1_EM23_Pos)      /*!< 0x00800000 */
+#define EXTI_EMR1_EM23                       EXTI_EMR1_EM23_Msk                /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos                   (24U)                             
+#define EXTI_EMR1_EM24_Msk                   (0x1U << EXTI_EMR1_EM24_Pos)      /*!< 0x01000000 */
+#define EXTI_EMR1_EM24                       EXTI_EMR1_EM24_Msk                /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos                   (25U)                             
+#define EXTI_EMR1_EM25_Msk                   (0x1U << EXTI_EMR1_EM25_Pos)      /*!< 0x02000000 */
+#define EXTI_EMR1_EM25                       EXTI_EMR1_EM25_Msk                /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos                   (26U)                             
+#define EXTI_EMR1_EM26_Msk                   (0x1U << EXTI_EMR1_EM26_Pos)      /*!< 0x04000000 */
+#define EXTI_EMR1_EM26                       EXTI_EMR1_EM26_Msk                /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos                   (27U)                             
+#define EXTI_EMR1_EM27_Msk                   (0x1U << EXTI_EMR1_EM27_Pos)      /*!< 0x08000000 */
+#define EXTI_EMR1_EM27                       EXTI_EMR1_EM27_Msk                /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos                   (28U)                             
+#define EXTI_EMR1_EM28_Msk                   (0x1U << EXTI_EMR1_EM28_Pos)      /*!< 0x10000000 */
+#define EXTI_EMR1_EM28                       EXTI_EMR1_EM28_Msk                /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos                   (29U)                             
+#define EXTI_EMR1_EM29_Msk                   (0x1U << EXTI_EMR1_EM29_Pos)      /*!< 0x20000000 */
+#define EXTI_EMR1_EM29                       EXTI_EMR1_EM29_Msk                /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos                   (30U)                             
+#define EXTI_EMR1_EM30_Msk                   (0x1U << EXTI_EMR1_EM30_Pos)      /*!< 0x40000000 */
+#define EXTI_EMR1_EM30                       EXTI_EMR1_EM30_Msk                /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos                   (31U)                             
+#define EXTI_EMR1_EM31_Msk                   (0x1U << EXTI_EMR1_EM31_Pos)      /*!< 0x80000000 */
+#define EXTI_EMR1_EM31                       EXTI_EMR1_EM31_Msk                /*!< Event Mask on line 31 */
+
+/******************  Bit definition for EXTI_RTSR1 register  ******************/
+#define EXTI_RTSR1_RT0_Pos                   (0U)                              
+#define EXTI_RTSR1_RT0_Msk                   (0x1U << EXTI_RTSR1_RT0_Pos)      /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0                       EXTI_RTSR1_RT0_Msk                /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_RT1_Pos                   (1U)                              
+#define EXTI_RTSR1_RT1_Msk                   (0x1U << EXTI_RTSR1_RT1_Pos)      /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1                       EXTI_RTSR1_RT1_Msk                /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_RT2_Pos                   (2U)                              
+#define EXTI_RTSR1_RT2_Msk                   (0x1U << EXTI_RTSR1_RT2_Pos)      /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2                       EXTI_RTSR1_RT2_Msk                /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_RT3_Pos                   (3U)                              
+#define EXTI_RTSR1_RT3_Msk                   (0x1U << EXTI_RTSR1_RT3_Pos)      /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3                       EXTI_RTSR1_RT3_Msk                /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_RT4_Pos                   (4U)                              
+#define EXTI_RTSR1_RT4_Msk                   (0x1U << EXTI_RTSR1_RT4_Pos)      /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4                       EXTI_RTSR1_RT4_Msk                /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_RT5_Pos                   (5U)                              
+#define EXTI_RTSR1_RT5_Msk                   (0x1U << EXTI_RTSR1_RT5_Pos)      /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5                       EXTI_RTSR1_RT5_Msk                /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_RT6_Pos                   (6U)                              
+#define EXTI_RTSR1_RT6_Msk                   (0x1U << EXTI_RTSR1_RT6_Pos)      /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6                       EXTI_RTSR1_RT6_Msk                /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_RT7_Pos                   (7U)                              
+#define EXTI_RTSR1_RT7_Msk                   (0x1U << EXTI_RTSR1_RT7_Pos)      /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7                       EXTI_RTSR1_RT7_Msk                /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_RT8_Pos                   (8U)                              
+#define EXTI_RTSR1_RT8_Msk                   (0x1U << EXTI_RTSR1_RT8_Pos)      /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8                       EXTI_RTSR1_RT8_Msk                /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_RT9_Pos                   (9U)                              
+#define EXTI_RTSR1_RT9_Msk                   (0x1U << EXTI_RTSR1_RT9_Pos)      /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9                       EXTI_RTSR1_RT9_Msk                /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_RT10_Pos                  (10U)                             
+#define EXTI_RTSR1_RT10_Msk                  (0x1U << EXTI_RTSR1_RT10_Pos)     /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10                      EXTI_RTSR1_RT10_Msk               /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_RT11_Pos                  (11U)                             
+#define EXTI_RTSR1_RT11_Msk                  (0x1U << EXTI_RTSR1_RT11_Pos)     /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11                      EXTI_RTSR1_RT11_Msk               /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_RT12_Pos                  (12U)                             
+#define EXTI_RTSR1_RT12_Msk                  (0x1U << EXTI_RTSR1_RT12_Pos)     /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12                      EXTI_RTSR1_RT12_Msk               /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_RT13_Pos                  (13U)                             
+#define EXTI_RTSR1_RT13_Msk                  (0x1U << EXTI_RTSR1_RT13_Pos)     /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13                      EXTI_RTSR1_RT13_Msk               /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_RT14_Pos                  (14U)                             
+#define EXTI_RTSR1_RT14_Msk                  (0x1U << EXTI_RTSR1_RT14_Pos)     /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14                      EXTI_RTSR1_RT14_Msk               /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_RT15_Pos                  (15U)                             
+#define EXTI_RTSR1_RT15_Msk                  (0x1U << EXTI_RTSR1_RT15_Pos)     /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15                      EXTI_RTSR1_RT15_Msk               /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_RT16_Pos                  (16U)                             
+#define EXTI_RTSR1_RT16_Msk                  (0x1U << EXTI_RTSR1_RT16_Pos)     /*!< 0x00010000 */
+#define EXTI_RTSR1_RT16                      EXTI_RTSR1_RT16_Msk               /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_RT18_Pos                  (18U)                             
+#define EXTI_RTSR1_RT18_Msk                  (0x1U << EXTI_RTSR1_RT18_Pos)     /*!< 0x00040000 */
+#define EXTI_RTSR1_RT18                      EXTI_RTSR1_RT18_Msk               /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_RT19_Pos                  (19U)                             
+#define EXTI_RTSR1_RT19_Msk                  (0x1U << EXTI_RTSR1_RT19_Pos)     /*!< 0x00080000 */
+#define EXTI_RTSR1_RT19                      EXTI_RTSR1_RT19_Msk               /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_RT20_Pos                  (20U)                             
+#define EXTI_RTSR1_RT20_Msk                  (0x1U << EXTI_RTSR1_RT20_Pos)     /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20                      EXTI_RTSR1_RT20_Msk               /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_RT21_Pos                  (21U)                             
+#define EXTI_RTSR1_RT21_Msk                  (0x1U << EXTI_RTSR1_RT21_Pos)     /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21                      EXTI_RTSR1_RT21_Msk               /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR1_RT22_Pos                  (22U)                             
+#define EXTI_RTSR1_RT22_Msk                  (0x1U << EXTI_RTSR1_RT22_Pos)     /*!< 0x00400000 */
+#define EXTI_RTSR1_RT22                      EXTI_RTSR1_RT22_Msk               /*!< Rising trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_FTSR1 register  ******************/
+#define EXTI_FTSR1_FT0_Pos                   (0U)                              
+#define EXTI_FTSR1_FT0_Msk                   (0x1U << EXTI_FTSR1_FT0_Pos)      /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0                       EXTI_FTSR1_FT0_Msk                /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_FT1_Pos                   (1U)                              
+#define EXTI_FTSR1_FT1_Msk                   (0x1U << EXTI_FTSR1_FT1_Pos)      /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1                       EXTI_FTSR1_FT1_Msk                /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_FT2_Pos                   (2U)                              
+#define EXTI_FTSR1_FT2_Msk                   (0x1U << EXTI_FTSR1_FT2_Pos)      /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2                       EXTI_FTSR1_FT2_Msk                /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_FT3_Pos                   (3U)                              
+#define EXTI_FTSR1_FT3_Msk                   (0x1U << EXTI_FTSR1_FT3_Pos)      /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3                       EXTI_FTSR1_FT3_Msk                /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_FT4_Pos                   (4U)                              
+#define EXTI_FTSR1_FT4_Msk                   (0x1U << EXTI_FTSR1_FT4_Pos)      /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4                       EXTI_FTSR1_FT4_Msk                /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_FT5_Pos                   (5U)                              
+#define EXTI_FTSR1_FT5_Msk                   (0x1U << EXTI_FTSR1_FT5_Pos)      /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5                       EXTI_FTSR1_FT5_Msk                /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_FT6_Pos                   (6U)                              
+#define EXTI_FTSR1_FT6_Msk                   (0x1U << EXTI_FTSR1_FT6_Pos)      /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6                       EXTI_FTSR1_FT6_Msk                /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_FT7_Pos                   (7U)                              
+#define EXTI_FTSR1_FT7_Msk                   (0x1U << EXTI_FTSR1_FT7_Pos)      /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7                       EXTI_FTSR1_FT7_Msk                /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_FT8_Pos                   (8U)                              
+#define EXTI_FTSR1_FT8_Msk                   (0x1U << EXTI_FTSR1_FT8_Pos)      /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8                       EXTI_FTSR1_FT8_Msk                /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_FT9_Pos                   (9U)                              
+#define EXTI_FTSR1_FT9_Msk                   (0x1U << EXTI_FTSR1_FT9_Pos)      /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9                       EXTI_FTSR1_FT9_Msk                /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_FT10_Pos                  (10U)                             
+#define EXTI_FTSR1_FT10_Msk                  (0x1U << EXTI_FTSR1_FT10_Pos)     /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10                      EXTI_FTSR1_FT10_Msk               /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_FT11_Pos                  (11U)                             
+#define EXTI_FTSR1_FT11_Msk                  (0x1U << EXTI_FTSR1_FT11_Pos)     /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11                      EXTI_FTSR1_FT11_Msk               /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_FT12_Pos                  (12U)                             
+#define EXTI_FTSR1_FT12_Msk                  (0x1U << EXTI_FTSR1_FT12_Pos)     /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12                      EXTI_FTSR1_FT12_Msk               /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_FT13_Pos                  (13U)                             
+#define EXTI_FTSR1_FT13_Msk                  (0x1U << EXTI_FTSR1_FT13_Pos)     /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13                      EXTI_FTSR1_FT13_Msk               /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_FT14_Pos                  (14U)                             
+#define EXTI_FTSR1_FT14_Msk                  (0x1U << EXTI_FTSR1_FT14_Pos)     /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14                      EXTI_FTSR1_FT14_Msk               /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_FT15_Pos                  (15U)                             
+#define EXTI_FTSR1_FT15_Msk                  (0x1U << EXTI_FTSR1_FT15_Pos)     /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15                      EXTI_FTSR1_FT15_Msk               /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_FT16_Pos                  (16U)                             
+#define EXTI_FTSR1_FT16_Msk                  (0x1U << EXTI_FTSR1_FT16_Pos)     /*!< 0x00010000 */
+#define EXTI_FTSR1_FT16                      EXTI_FTSR1_FT16_Msk               /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_FT18_Pos                  (18U)                             
+#define EXTI_FTSR1_FT18_Msk                  (0x1U << EXTI_FTSR1_FT18_Pos)     /*!< 0x00040000 */
+#define EXTI_FTSR1_FT18                      EXTI_FTSR1_FT18_Msk               /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_FT19_Pos                  (19U)                             
+#define EXTI_FTSR1_FT19_Msk                  (0x1U << EXTI_FTSR1_FT19_Pos)     /*!< 0x00080000 */
+#define EXTI_FTSR1_FT19                      EXTI_FTSR1_FT19_Msk               /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_FT20_Pos                  (20U)                             
+#define EXTI_FTSR1_FT20_Msk                  (0x1U << EXTI_FTSR1_FT20_Pos)     /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20                      EXTI_FTSR1_FT20_Msk               /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_FT21_Pos                  (21U)                             
+#define EXTI_FTSR1_FT21_Msk                  (0x1U << EXTI_FTSR1_FT21_Pos)     /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21                      EXTI_FTSR1_FT21_Msk               /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR1_FT22_Pos                  (22U)                             
+#define EXTI_FTSR1_FT22_Msk                  (0x1U << EXTI_FTSR1_FT22_Pos)     /*!< 0x00400000 */
+#define EXTI_FTSR1_FT22                      EXTI_FTSR1_FT22_Msk               /*!< Falling trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_SWIER1 register  *****************/
+#define EXTI_SWIER1_SWI0_Pos                 (0U)                              
+#define EXTI_SWIER1_SWI0_Msk                 (0x1U << EXTI_SWIER1_SWI0_Pos)    /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0                     EXTI_SWIER1_SWI0_Msk              /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos                 (1U)                              
+#define EXTI_SWIER1_SWI1_Msk                 (0x1U << EXTI_SWIER1_SWI1_Pos)    /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1                     EXTI_SWIER1_SWI1_Msk              /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos                 (2U)                              
+#define EXTI_SWIER1_SWI2_Msk                 (0x1U << EXTI_SWIER1_SWI2_Pos)    /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2                     EXTI_SWIER1_SWI2_Msk              /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos                 (3U)                              
+#define EXTI_SWIER1_SWI3_Msk                 (0x1U << EXTI_SWIER1_SWI3_Pos)    /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3                     EXTI_SWIER1_SWI3_Msk              /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos                 (4U)                              
+#define EXTI_SWIER1_SWI4_Msk                 (0x1U << EXTI_SWIER1_SWI4_Pos)    /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4                     EXTI_SWIER1_SWI4_Msk              /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos                 (5U)                              
+#define EXTI_SWIER1_SWI5_Msk                 (0x1U << EXTI_SWIER1_SWI5_Pos)    /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5                     EXTI_SWIER1_SWI5_Msk              /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos                 (6U)                              
+#define EXTI_SWIER1_SWI6_Msk                 (0x1U << EXTI_SWIER1_SWI6_Pos)    /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6                     EXTI_SWIER1_SWI6_Msk              /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos                 (7U)                              
+#define EXTI_SWIER1_SWI7_Msk                 (0x1U << EXTI_SWIER1_SWI7_Pos)    /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7                     EXTI_SWIER1_SWI7_Msk              /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos                 (8U)                              
+#define EXTI_SWIER1_SWI8_Msk                 (0x1U << EXTI_SWIER1_SWI8_Pos)    /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8                     EXTI_SWIER1_SWI8_Msk              /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos                 (9U)                              
+#define EXTI_SWIER1_SWI9_Msk                 (0x1U << EXTI_SWIER1_SWI9_Pos)    /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9                     EXTI_SWIER1_SWI9_Msk              /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos                (10U)                             
+#define EXTI_SWIER1_SWI10_Msk                (0x1U << EXTI_SWIER1_SWI10_Pos)   /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10                    EXTI_SWIER1_SWI10_Msk             /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos                (11U)                             
+#define EXTI_SWIER1_SWI11_Msk                (0x1U << EXTI_SWIER1_SWI11_Pos)   /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11                    EXTI_SWIER1_SWI11_Msk             /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos                (12U)                             
+#define EXTI_SWIER1_SWI12_Msk                (0x1U << EXTI_SWIER1_SWI12_Pos)   /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12                    EXTI_SWIER1_SWI12_Msk             /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos                (13U)                             
+#define EXTI_SWIER1_SWI13_Msk                (0x1U << EXTI_SWIER1_SWI13_Pos)   /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13                    EXTI_SWIER1_SWI13_Msk             /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos                (14U)                             
+#define EXTI_SWIER1_SWI14_Msk                (0x1U << EXTI_SWIER1_SWI14_Pos)   /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14                    EXTI_SWIER1_SWI14_Msk             /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos                (15U)                             
+#define EXTI_SWIER1_SWI15_Msk                (0x1U << EXTI_SWIER1_SWI15_Pos)   /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15                    EXTI_SWIER1_SWI15_Msk             /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI16_Pos                (16U)                             
+#define EXTI_SWIER1_SWI16_Msk                (0x1U << EXTI_SWIER1_SWI16_Pos)   /*!< 0x00010000 */
+#define EXTI_SWIER1_SWI16                    EXTI_SWIER1_SWI16_Msk             /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWI18_Pos                (18U)                             
+#define EXTI_SWIER1_SWI18_Msk                (0x1U << EXTI_SWIER1_SWI18_Pos)   /*!< 0x00040000 */
+#define EXTI_SWIER1_SWI18                    EXTI_SWIER1_SWI18_Msk             /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWI19_Pos                (19U)                             
+#define EXTI_SWIER1_SWI19_Msk                (0x1U << EXTI_SWIER1_SWI19_Pos)   /*!< 0x00080000 */
+#define EXTI_SWIER1_SWI19                    EXTI_SWIER1_SWI19_Msk             /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWI20_Pos                (20U)                             
+#define EXTI_SWIER1_SWI20_Msk                (0x1U << EXTI_SWIER1_SWI20_Pos)   /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20                    EXTI_SWIER1_SWI20_Msk             /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos                (21U)                             
+#define EXTI_SWIER1_SWI21_Msk                (0x1U << EXTI_SWIER1_SWI21_Pos)   /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21                    EXTI_SWIER1_SWI21_Msk             /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER1_SWI22_Pos                (22U)                             
+#define EXTI_SWIER1_SWI22_Msk                (0x1U << EXTI_SWIER1_SWI22_Pos)   /*!< 0x00400000 */
+#define EXTI_SWIER1_SWI22                    EXTI_SWIER1_SWI22_Msk             /*!< Software Interrupt on line 22 */
+
+/*******************  Bit definition for EXTI_PR1 register  *******************/
+#define EXTI_PR1_PIF0_Pos                    (0U)                              
+#define EXTI_PR1_PIF0_Msk                    (0x1U << EXTI_PR1_PIF0_Pos)       /*!< 0x00000001 */
+#define EXTI_PR1_PIF0                        EXTI_PR1_PIF0_Msk                 /*!< Pending bit for line 0 */
+#define EXTI_PR1_PIF1_Pos                    (1U)                              
+#define EXTI_PR1_PIF1_Msk                    (0x1U << EXTI_PR1_PIF1_Pos)       /*!< 0x00000002 */
+#define EXTI_PR1_PIF1                        EXTI_PR1_PIF1_Msk                 /*!< Pending bit for line 1 */
+#define EXTI_PR1_PIF2_Pos                    (2U)                              
+#define EXTI_PR1_PIF2_Msk                    (0x1U << EXTI_PR1_PIF2_Pos)       /*!< 0x00000004 */
+#define EXTI_PR1_PIF2                        EXTI_PR1_PIF2_Msk                 /*!< Pending bit for line 2 */
+#define EXTI_PR1_PIF3_Pos                    (3U)                              
+#define EXTI_PR1_PIF3_Msk                    (0x1U << EXTI_PR1_PIF3_Pos)       /*!< 0x00000008 */
+#define EXTI_PR1_PIF3                        EXTI_PR1_PIF3_Msk                 /*!< Pending bit for line 3 */
+#define EXTI_PR1_PIF4_Pos                    (4U)                              
+#define EXTI_PR1_PIF4_Msk                    (0x1U << EXTI_PR1_PIF4_Pos)       /*!< 0x00000010 */
+#define EXTI_PR1_PIF4                        EXTI_PR1_PIF4_Msk                 /*!< Pending bit for line 4 */
+#define EXTI_PR1_PIF5_Pos                    (5U)                              
+#define EXTI_PR1_PIF5_Msk                    (0x1U << EXTI_PR1_PIF5_Pos)       /*!< 0x00000020 */
+#define EXTI_PR1_PIF5                        EXTI_PR1_PIF5_Msk                 /*!< Pending bit for line 5 */
+#define EXTI_PR1_PIF6_Pos                    (6U)                              
+#define EXTI_PR1_PIF6_Msk                    (0x1U << EXTI_PR1_PIF6_Pos)       /*!< 0x00000040 */
+#define EXTI_PR1_PIF6                        EXTI_PR1_PIF6_Msk                 /*!< Pending bit for line 6 */
+#define EXTI_PR1_PIF7_Pos                    (7U)                              
+#define EXTI_PR1_PIF7_Msk                    (0x1U << EXTI_PR1_PIF7_Pos)       /*!< 0x00000080 */
+#define EXTI_PR1_PIF7                        EXTI_PR1_PIF7_Msk                 /*!< Pending bit for line 7 */
+#define EXTI_PR1_PIF8_Pos                    (8U)                              
+#define EXTI_PR1_PIF8_Msk                    (0x1U << EXTI_PR1_PIF8_Pos)       /*!< 0x00000100 */
+#define EXTI_PR1_PIF8                        EXTI_PR1_PIF8_Msk                 /*!< Pending bit for line 8 */
+#define EXTI_PR1_PIF9_Pos                    (9U)                              
+#define EXTI_PR1_PIF9_Msk                    (0x1U << EXTI_PR1_PIF9_Pos)       /*!< 0x00000200 */
+#define EXTI_PR1_PIF9                        EXTI_PR1_PIF9_Msk                 /*!< Pending bit for line 9 */
+#define EXTI_PR1_PIF10_Pos                   (10U)                             
+#define EXTI_PR1_PIF10_Msk                   (0x1U << EXTI_PR1_PIF10_Pos)      /*!< 0x00000400 */
+#define EXTI_PR1_PIF10                       EXTI_PR1_PIF10_Msk                /*!< Pending bit for line 10 */
+#define EXTI_PR1_PIF11_Pos                   (11U)                             
+#define EXTI_PR1_PIF11_Msk                   (0x1U << EXTI_PR1_PIF11_Pos)      /*!< 0x00000800 */
+#define EXTI_PR1_PIF11                       EXTI_PR1_PIF11_Msk                /*!< Pending bit for line 11 */
+#define EXTI_PR1_PIF12_Pos                   (12U)                             
+#define EXTI_PR1_PIF12_Msk                   (0x1U << EXTI_PR1_PIF12_Pos)      /*!< 0x00001000 */
+#define EXTI_PR1_PIF12                       EXTI_PR1_PIF12_Msk                /*!< Pending bit for line 12 */
+#define EXTI_PR1_PIF13_Pos                   (13U)                             
+#define EXTI_PR1_PIF13_Msk                   (0x1U << EXTI_PR1_PIF13_Pos)      /*!< 0x00002000 */
+#define EXTI_PR1_PIF13                       EXTI_PR1_PIF13_Msk                /*!< Pending bit for line 13 */
+#define EXTI_PR1_PIF14_Pos                   (14U)                             
+#define EXTI_PR1_PIF14_Msk                   (0x1U << EXTI_PR1_PIF14_Pos)      /*!< 0x00004000 */
+#define EXTI_PR1_PIF14                       EXTI_PR1_PIF14_Msk                /*!< Pending bit for line 14 */
+#define EXTI_PR1_PIF15_Pos                   (15U)                             
+#define EXTI_PR1_PIF15_Msk                   (0x1U << EXTI_PR1_PIF15_Pos)      /*!< 0x00008000 */
+#define EXTI_PR1_PIF15                       EXTI_PR1_PIF15_Msk                /*!< Pending bit for line 15 */
+#define EXTI_PR1_PIF16_Pos                   (16U)                             
+#define EXTI_PR1_PIF16_Msk                   (0x1U << EXTI_PR1_PIF16_Pos)      /*!< 0x00010000 */
+#define EXTI_PR1_PIF16                       EXTI_PR1_PIF16_Msk                /*!< Pending bit for line 16 */
+#define EXTI_PR1_PIF18_Pos                   (18U)                             
+#define EXTI_PR1_PIF18_Msk                   (0x1U << EXTI_PR1_PIF18_Pos)      /*!< 0x00040000 */
+#define EXTI_PR1_PIF18                       EXTI_PR1_PIF18_Msk                /*!< Pending bit for line 18 */
+#define EXTI_PR1_PIF19_Pos                   (19U)                             
+#define EXTI_PR1_PIF19_Msk                   (0x1U << EXTI_PR1_PIF19_Pos)      /*!< 0x00080000 */
+#define EXTI_PR1_PIF19                       EXTI_PR1_PIF19_Msk                /*!< Pending bit for line 19 */
+#define EXTI_PR1_PIF20_Pos                   (20U)                             
+#define EXTI_PR1_PIF20_Msk                   (0x1U << EXTI_PR1_PIF20_Pos)      /*!< 0x00100000 */
+#define EXTI_PR1_PIF20                       EXTI_PR1_PIF20_Msk                /*!< Pending bit for line 20 */
+#define EXTI_PR1_PIF21_Pos                   (21U)                             
+#define EXTI_PR1_PIF21_Msk                   (0x1U << EXTI_PR1_PIF21_Pos)      /*!< 0x00200000 */
+#define EXTI_PR1_PIF21                       EXTI_PR1_PIF21_Msk                /*!< Pending bit for line 21 */
+#define EXTI_PR1_PIF22_Pos                   (22U)                             
+#define EXTI_PR1_PIF22_Msk                   (0x1U << EXTI_PR1_PIF22_Pos)      /*!< 0x00400000 */
+#define EXTI_PR1_PIF22                       EXTI_PR1_PIF22_Msk                /*!< Pending bit for line 22 */
+
+/*******************  Bit definition for EXTI_IMR2 register  ******************/
+#define EXTI_IMR2_IM32_Pos                   (0U)                              
+#define EXTI_IMR2_IM32_Msk                   (0x1U << EXTI_IMR2_IM32_Pos)      /*!< 0x00000001 */
+#define EXTI_IMR2_IM32                       EXTI_IMR2_IM32_Msk                /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos                   (1U)                              
+#define EXTI_IMR2_IM33_Msk                   (0x1U << EXTI_IMR2_IM33_Pos)      /*!< 0x00000002 */
+#define EXTI_IMR2_IM33                       EXTI_IMR2_IM33_Msk                /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos                   (2U)                              
+#define EXTI_IMR2_IM34_Msk                   (0x1U << EXTI_IMR2_IM34_Pos)      /*!< 0x00000004 */
+#define EXTI_IMR2_IM34                       EXTI_IMR2_IM34_Msk                /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos                   (3U)                              
+#define EXTI_IMR2_IM35_Msk                   (0x1U << EXTI_IMR2_IM35_Pos)      /*!< 0x00000008 */
+#define EXTI_IMR2_IM35                       EXTI_IMR2_IM35_Msk                /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos                   (4U)                              
+#define EXTI_IMR2_IM36_Msk                   (0x1U << EXTI_IMR2_IM36_Pos)      /*!< 0x00000010 */
+#define EXTI_IMR2_IM36                       EXTI_IMR2_IM36_Msk                /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos                   (5U)                              
+#define EXTI_IMR2_IM37_Msk                   (0x1U << EXTI_IMR2_IM37_Pos)      /*!< 0x00000020 */
+#define EXTI_IMR2_IM37                       EXTI_IMR2_IM37_Msk                /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos                   (6U)                              
+#define EXTI_IMR2_IM38_Msk                   (0x1U << EXTI_IMR2_IM38_Pos)      /*!< 0x00000040 */
+#define EXTI_IMR2_IM38                       EXTI_IMR2_IM38_Msk                /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos                   (7U)                              
+#define EXTI_IMR2_IM39_Msk                   (0x1U << EXTI_IMR2_IM39_Pos)      /*!< 0x00000080 */
+#define EXTI_IMR2_IM39                       EXTI_IMR2_IM39_Msk                /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM_Pos                     (0U)                              
+#define EXTI_IMR2_IM_Msk                     (0xFFU << EXTI_IMR2_IM_Pos)       /*!< 0x000000FF */
+#define EXTI_IMR2_IM                         EXTI_IMR2_IM_Msk                  /*!< Interrupt Mask all        */
+
+/*******************  Bit definition for EXTI_EMR2 register  ******************/
+#define EXTI_EMR2_EM32_Pos                   (0U)                              
+#define EXTI_EMR2_EM32_Msk                   (0x1U << EXTI_EMR2_EM32_Pos)      /*!< 0x00000001 */
+#define EXTI_EMR2_EM32                       EXTI_EMR2_EM32_Msk                /*!< Event Mask on line 32 */
+#define EXTI_EMR2_EM33_Pos                   (1U)                              
+#define EXTI_EMR2_EM33_Msk                   (0x1U << EXTI_EMR2_EM33_Pos)      /*!< 0x00000002 */
+#define EXTI_EMR2_EM33                       EXTI_EMR2_EM33_Msk                /*!< Event Mask on line 33 */
+#define EXTI_EMR2_EM34_Pos                   (2U)                              
+#define EXTI_EMR2_EM34_Msk                   (0x1U << EXTI_EMR2_EM34_Pos)      /*!< 0x00000004 */
+#define EXTI_EMR2_EM34                       EXTI_EMR2_EM34_Msk                /*!< Event Mask on line 34 */
+#define EXTI_EMR2_EM35_Pos                   (3U)                              
+#define EXTI_EMR2_EM35_Msk                   (0x1U << EXTI_EMR2_EM35_Pos)      /*!< 0x00000008 */
+#define EXTI_EMR2_EM35                       EXTI_EMR2_EM35_Msk                /*!< Event Mask on line 35 */
+#define EXTI_EMR2_EM36_Pos                   (4U)                              
+#define EXTI_EMR2_EM36_Msk                   (0x1U << EXTI_EMR2_EM36_Pos)      /*!< 0x00000010 */
+#define EXTI_EMR2_EM36                       EXTI_EMR2_EM36_Msk                /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos                   (5U)                              
+#define EXTI_EMR2_EM37_Msk                   (0x1U << EXTI_EMR2_EM37_Pos)      /*!< 0x00000020 */
+#define EXTI_EMR2_EM37                       EXTI_EMR2_EM37_Msk                /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos                   (6U)                              
+#define EXTI_EMR2_EM38_Msk                   (0x1U << EXTI_EMR2_EM38_Pos)      /*!< 0x00000040 */
+#define EXTI_EMR2_EM38                       EXTI_EMR2_EM38_Msk                /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM39_Pos                   (7U)                              
+#define EXTI_EMR2_EM39_Msk                   (0x1U << EXTI_EMR2_EM39_Pos)      /*!< 0x00000080 */
+#define EXTI_EMR2_EM39                       EXTI_EMR2_EM39_Msk                /*!< Event Mask on line 39 */
+
+/******************  Bit definition for EXTI_RTSR2 register  ******************/
+#define EXTI_RTSR2_RT35_Pos                  (3U)                              
+#define EXTI_RTSR2_RT35_Msk                  (0x1U << EXTI_RTSR2_RT35_Pos)     /*!< 0x00000008 */
+#define EXTI_RTSR2_RT35                      EXTI_RTSR2_RT35_Msk               /*!< Rising trigger event configuration bit of line 35 */
+#define EXTI_RTSR2_RT36_Pos                  (4U)                              
+#define EXTI_RTSR2_RT36_Msk                  (0x1U << EXTI_RTSR2_RT36_Pos)     /*!< 0x00000010 */
+#define EXTI_RTSR2_RT36                      EXTI_RTSR2_RT36_Msk               /*!< Rising trigger event configuration bit of line 36 */
+#define EXTI_RTSR2_RT37_Pos                  (5U)                              
+#define EXTI_RTSR2_RT37_Msk                  (0x1U << EXTI_RTSR2_RT37_Pos)     /*!< 0x00000020 */
+#define EXTI_RTSR2_RT37                      EXTI_RTSR2_RT37_Msk               /*!< Rising trigger event configuration bit of line 37 */
+#define EXTI_RTSR2_RT38_Pos                  (6U)                              
+#define EXTI_RTSR2_RT38_Msk                  (0x1U << EXTI_RTSR2_RT38_Pos)     /*!< 0x00000040 */
+#define EXTI_RTSR2_RT38                      EXTI_RTSR2_RT38_Msk               /*!< Rising trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_FTSR2 register  ******************/
+#define EXTI_FTSR2_FT35_Pos                  (3U)                              
+#define EXTI_FTSR2_FT35_Msk                  (0x1U << EXTI_FTSR2_FT35_Pos)     /*!< 0x00000008 */
+#define EXTI_FTSR2_FT35                      EXTI_FTSR2_FT35_Msk               /*!< Falling trigger event configuration bit of line 35 */
+#define EXTI_FTSR2_FT36_Pos                  (4U)                              
+#define EXTI_FTSR2_FT36_Msk                  (0x1U << EXTI_FTSR2_FT36_Pos)     /*!< 0x00000010 */
+#define EXTI_FTSR2_FT36                      EXTI_FTSR2_FT36_Msk               /*!< Falling trigger event configuration bit of line 36 */
+#define EXTI_FTSR2_FT37_Pos                  (5U)                              
+#define EXTI_FTSR2_FT37_Msk                  (0x1U << EXTI_FTSR2_FT37_Pos)     /*!< 0x00000020 */
+#define EXTI_FTSR2_FT37                      EXTI_FTSR2_FT37_Msk               /*!< Falling trigger event configuration bit of line 37 */
+#define EXTI_FTSR2_FT38_Pos                  (6U)                              
+#define EXTI_FTSR2_FT38_Msk                  (0x1U << EXTI_FTSR2_FT38_Pos)     /*!< 0x00000040 */
+#define EXTI_FTSR2_FT38                      EXTI_FTSR2_FT38_Msk               /*!< Falling trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_SWIER2 register  *****************/
+#define EXTI_SWIER2_SWI35_Pos                (3U)                              
+#define EXTI_SWIER2_SWI35_Msk                (0x1U << EXTI_SWIER2_SWI35_Pos)   /*!< 0x00000008 */
+#define EXTI_SWIER2_SWI35                    EXTI_SWIER2_SWI35_Msk             /*!< Software Interrupt on line 35 */
+#define EXTI_SWIER2_SWI36_Pos                (4U)                              
+#define EXTI_SWIER2_SWI36_Msk                (0x1U << EXTI_SWIER2_SWI36_Pos)   /*!< 0x00000010 */
+#define EXTI_SWIER2_SWI36                    EXTI_SWIER2_SWI36_Msk             /*!< Software Interrupt on line 36 */
+#define EXTI_SWIER2_SWI37_Pos                (5U)                              
+#define EXTI_SWIER2_SWI37_Msk                (0x1U << EXTI_SWIER2_SWI37_Pos)   /*!< 0x00000020 */
+#define EXTI_SWIER2_SWI37                    EXTI_SWIER2_SWI37_Msk             /*!< Software Interrupt on line 37 */
+#define EXTI_SWIER2_SWI38_Pos                (6U)                              
+#define EXTI_SWIER2_SWI38_Msk                (0x1U << EXTI_SWIER2_SWI38_Pos)   /*!< 0x00000040 */
+#define EXTI_SWIER2_SWI38                    EXTI_SWIER2_SWI38_Msk             /*!< Software Interrupt on line 38 */
+
+/*******************  Bit definition for EXTI_PR2 register  *******************/
+#define EXTI_PR2_PIF35_Pos                   (3U)                              
+#define EXTI_PR2_PIF35_Msk                   (0x1U << EXTI_PR2_PIF35_Pos)      /*!< 0x00000008 */
+#define EXTI_PR2_PIF35                       EXTI_PR2_PIF35_Msk                /*!< Pending bit for line 35 */
+#define EXTI_PR2_PIF36_Pos                   (4U)                              
+#define EXTI_PR2_PIF36_Msk                   (0x1U << EXTI_PR2_PIF36_Pos)      /*!< 0x00000010 */
+#define EXTI_PR2_PIF36                       EXTI_PR2_PIF36_Msk                /*!< Pending bit for line 36 */
+#define EXTI_PR2_PIF37_Pos                   (5U)                              
+#define EXTI_PR2_PIF37_Msk                   (0x1U << EXTI_PR2_PIF37_Pos)      /*!< 0x00000020 */
+#define EXTI_PR2_PIF37                       EXTI_PR2_PIF37_Msk                /*!< Pending bit for line 37 */
+#define EXTI_PR2_PIF38_Pos                   (6U)                              
+#define EXTI_PR2_PIF38_Msk                   (0x1U << EXTI_PR2_PIF38_Pos)      /*!< 0x00000040 */
+#define EXTI_PR2_PIF38                       EXTI_PR2_PIF38_Msk                /*!< Pending bit for line 38 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY_Pos                (0U)                              
+#define FLASH_ACR_LATENCY_Msk                (0x7U << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             
+#define FLASH_ACR_LATENCY_0WS                (0x00000000U)                     
+#define FLASH_ACR_LATENCY_1WS                (0x00000001U)                     
+#define FLASH_ACR_LATENCY_2WS                (0x00000002U)                     
+#define FLASH_ACR_LATENCY_3WS                (0x00000003U)                     
+#define FLASH_ACR_LATENCY_4WS                (0x00000004U)                     
+#define FLASH_ACR_PRFTEN_Pos                 (8U)                              
+#define FLASH_ACR_PRFTEN_Msk                 (0x1U << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              
+#define FLASH_ACR_ICEN_Pos                   (9U)                              
+#define FLASH_ACR_ICEN_Msk                   (0x1U << FLASH_ACR_ICEN_Pos)      /*!< 0x00000200 */
+#define FLASH_ACR_ICEN                       FLASH_ACR_ICEN_Msk                
+#define FLASH_ACR_DCEN_Pos                   (10U)                             
+#define FLASH_ACR_DCEN_Msk                   (0x1U << FLASH_ACR_DCEN_Pos)      /*!< 0x00000400 */
+#define FLASH_ACR_DCEN                       FLASH_ACR_DCEN_Msk                
+#define FLASH_ACR_ICRST_Pos                  (11U)                             
+#define FLASH_ACR_ICRST_Msk                  (0x1U << FLASH_ACR_ICRST_Pos)     /*!< 0x00000800 */
+#define FLASH_ACR_ICRST                      FLASH_ACR_ICRST_Msk               
+#define FLASH_ACR_DCRST_Pos                  (12U)                             
+#define FLASH_ACR_DCRST_Msk                  (0x1U << FLASH_ACR_DCRST_Pos)     /*!< 0x00001000 */
+#define FLASH_ACR_DCRST                      FLASH_ACR_DCRST_Msk               
+#define FLASH_ACR_RUN_PD_Pos                 (13U)                             
+#define FLASH_ACR_RUN_PD_Msk                 (0x1U << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00002000 */
+#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash power down mode during run */
+#define FLASH_ACR_SLEEP_PD_Pos               (14U)                             
+#define FLASH_ACR_SLEEP_PD_Msk               (0x1U << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00004000 */
+#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash power down mode during sleep */
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP_Pos                     (0U)                              
+#define FLASH_SR_EOP_Msk                     (0x1U << FLASH_SR_EOP_Pos)        /*!< 0x00000001 */
+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  
+#define FLASH_SR_OPERR_Pos                   (1U)                              
+#define FLASH_SR_OPERR_Msk                   (0x1U << FLASH_SR_OPERR_Pos)      /*!< 0x00000002 */
+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                
+#define FLASH_SR_PROGERR_Pos                 (3U)                              
+#define FLASH_SR_PROGERR_Msk                 (0x1U << FLASH_SR_PROGERR_Pos)    /*!< 0x00000008 */
+#define FLASH_SR_PROGERR                     FLASH_SR_PROGERR_Msk              
+#define FLASH_SR_WRPERR_Pos                  (4U)                              
+#define FLASH_SR_WRPERR_Msk                  (0x1U << FLASH_SR_WRPERR_Pos)     /*!< 0x00000010 */
+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               
+#define FLASH_SR_PGAERR_Pos                  (5U)                              
+#define FLASH_SR_PGAERR_Msk                  (0x1U << FLASH_SR_PGAERR_Pos)     /*!< 0x00000020 */
+#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               
+#define FLASH_SR_SIZERR_Pos                  (6U)                              
+#define FLASH_SR_SIZERR_Msk                  (0x1U << FLASH_SR_SIZERR_Pos)     /*!< 0x00000040 */
+#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               
+#define FLASH_SR_PGSERR_Pos                  (7U)                              
+#define FLASH_SR_PGSERR_Msk                  (0x1U << FLASH_SR_PGSERR_Pos)     /*!< 0x00000080 */
+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               
+#define FLASH_SR_MISERR_Pos                  (8U)                              
+#define FLASH_SR_MISERR_Msk                  (0x1U << FLASH_SR_MISERR_Pos)     /*!< 0x00000100 */
+#define FLASH_SR_MISERR                      FLASH_SR_MISERR_Msk               
+#define FLASH_SR_FASTERR_Pos                 (9U)                              
+#define FLASH_SR_FASTERR_Msk                 (0x1U << FLASH_SR_FASTERR_Pos)    /*!< 0x00000200 */
+#define FLASH_SR_FASTERR                     FLASH_SR_FASTERR_Msk              
+#define FLASH_SR_RDERR_Pos                   (14U)                             
+#define FLASH_SR_RDERR_Msk                   (0x1U << FLASH_SR_RDERR_Pos)      /*!< 0x00004000 */
+#define FLASH_SR_RDERR                       FLASH_SR_RDERR_Msk                
+#define FLASH_SR_OPTVERR_Pos                 (15U)                             
+#define FLASH_SR_OPTVERR_Msk                 (0x1U << FLASH_SR_OPTVERR_Pos)    /*!< 0x00008000 */
+#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              
+#define FLASH_SR_BSY_Pos                     (16U)                             
+#define FLASH_SR_BSY_Msk                     (0x1U << FLASH_SR_BSY_Pos)        /*!< 0x00010000 */
+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG_Pos                      (0U)                              
+#define FLASH_CR_PG_Msk                      (0x1U << FLASH_CR_PG_Pos)         /*!< 0x00000001 */
+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   
+#define FLASH_CR_PER_Pos                     (1U)                              
+#define FLASH_CR_PER_Msk                     (0x1U << FLASH_CR_PER_Pos)        /*!< 0x00000002 */
+#define FLASH_CR_PER                         FLASH_CR_PER_Msk                  
+#define FLASH_CR_MER1_Pos                    (2U)                              
+#define FLASH_CR_MER1_Msk                    (0x1U << FLASH_CR_MER1_Pos)       /*!< 0x00000004 */
+#define FLASH_CR_MER1                        FLASH_CR_MER1_Msk                 
+#define FLASH_CR_PNB_Pos                     (3U)                              
+#define FLASH_CR_PNB_Msk                     (0xFFU << FLASH_CR_PNB_Pos)       /*!< 0x000007F8 */
+#define FLASH_CR_PNB                         FLASH_CR_PNB_Msk                  
+#define FLASH_CR_BKER_Pos                    (11U)                             
+#define FLASH_CR_BKER_Msk                    (0x1U << FLASH_CR_BKER_Pos)       /*!< 0x00000800 */
+#define FLASH_CR_BKER                        FLASH_CR_BKER_Msk                 
+#define FLASH_CR_MER2_Pos                    (15U)                             
+#define FLASH_CR_MER2_Msk                    (0x1U << FLASH_CR_MER2_Pos)       /*!< 0x00008000 */
+#define FLASH_CR_MER2                        FLASH_CR_MER2_Msk                 
+#define FLASH_CR_STRT_Pos                    (16U)                             
+#define FLASH_CR_STRT_Msk                    (0x1U << FLASH_CR_STRT_Pos)       /*!< 0x00010000 */
+#define FLASH_CR_STRT                        FLASH_CR_STRT_Msk                 
+#define FLASH_CR_OPTSTRT_Pos                 (17U)                             
+#define FLASH_CR_OPTSTRT_Msk                 (0x1U << FLASH_CR_OPTSTRT_Pos)    /*!< 0x00020000 */
+#define FLASH_CR_OPTSTRT                     FLASH_CR_OPTSTRT_Msk              
+#define FLASH_CR_FSTPG_Pos                   (18U)                             
+#define FLASH_CR_FSTPG_Msk                   (0x1U << FLASH_CR_FSTPG_Pos)      /*!< 0x00040000 */
+#define FLASH_CR_FSTPG                       FLASH_CR_FSTPG_Msk                
+#define FLASH_CR_EOPIE_Pos                   (24U)                             
+#define FLASH_CR_EOPIE_Msk                   (0x1U << FLASH_CR_EOPIE_Pos)      /*!< 0x01000000 */
+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                
+#define FLASH_CR_ERRIE_Pos                   (25U)                             
+#define FLASH_CR_ERRIE_Msk                   (0x1U << FLASH_CR_ERRIE_Pos)      /*!< 0x02000000 */
+#define FLASH_CR_ERRIE                       FLASH_CR_ERRIE_Msk                
+#define FLASH_CR_RDERRIE_Pos                 (26U)                             
+#define FLASH_CR_RDERRIE_Msk                 (0x1U << FLASH_CR_RDERRIE_Pos)    /*!< 0x04000000 */
+#define FLASH_CR_RDERRIE                     FLASH_CR_RDERRIE_Msk              
+#define FLASH_CR_OBL_LAUNCH_Pos              (27U)                             
+#define FLASH_CR_OBL_LAUNCH_Msk              (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
+#define FLASH_CR_OBL_LAUNCH                  FLASH_CR_OBL_LAUNCH_Msk           
+#define FLASH_CR_OPTLOCK_Pos                 (30U)                             
+#define FLASH_CR_OPTLOCK_Msk                 (0x1U << FLASH_CR_OPTLOCK_Pos)    /*!< 0x40000000 */
+#define FLASH_CR_OPTLOCK                     FLASH_CR_OPTLOCK_Msk              
+#define FLASH_CR_LOCK_Pos                    (31U)                             
+#define FLASH_CR_LOCK_Msk                    (0x1U << FLASH_CR_LOCK_Pos)       /*!< 0x80000000 */
+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 
+
+/*******************  Bits definition for FLASH_ECCR register  ***************/
+#define FLASH_ECCR_ADDR_ECC_Pos              (0U)                              
+#define FLASH_ECCR_ADDR_ECC_Msk              (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
+#define FLASH_ECCR_ADDR_ECC                  FLASH_ECCR_ADDR_ECC_Msk           
+#define FLASH_ECCR_BK_ECC_Pos                (19U)                             
+#define FLASH_ECCR_BK_ECC_Msk                (0x1U << FLASH_ECCR_BK_ECC_Pos)   /*!< 0x00080000 */
+#define FLASH_ECCR_BK_ECC                    FLASH_ECCR_BK_ECC_Msk             
+#define FLASH_ECCR_SYSF_ECC_Pos              (20U)                             
+#define FLASH_ECCR_SYSF_ECC_Msk              (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
+#define FLASH_ECCR_SYSF_ECC                  FLASH_ECCR_SYSF_ECC_Msk           
+#define FLASH_ECCR_ECCIE_Pos                 (24U)                             
+#define FLASH_ECCR_ECCIE_Msk                 (0x1U << FLASH_ECCR_ECCIE_Pos)    /*!< 0x01000000 */
+#define FLASH_ECCR_ECCIE                     FLASH_ECCR_ECCIE_Msk              
+#define FLASH_ECCR_ECCC_Pos                  (30U)                             
+#define FLASH_ECCR_ECCC_Msk                  (0x1U << FLASH_ECCR_ECCC_Pos)     /*!< 0x40000000 */
+#define FLASH_ECCR_ECCC                      FLASH_ECCR_ECCC_Msk               
+#define FLASH_ECCR_ECCD_Pos                  (31U)                             
+#define FLASH_ECCR_ECCD_Msk                  (0x1U << FLASH_ECCR_ECCD_Pos)     /*!< 0x80000000 */
+#define FLASH_ECCR_ECCD                      FLASH_ECCR_ECCD_Msk               
+
+/*******************  Bits definition for FLASH_OPTR register  ***************/
+#define FLASH_OPTR_RDP_Pos                   (0U)                              
+#define FLASH_OPTR_RDP_Msk                   (0xFFU << FLASH_OPTR_RDP_Pos)     /*!< 0x000000FF */
+#define FLASH_OPTR_RDP                       FLASH_OPTR_RDP_Msk                
+#define FLASH_OPTR_BOR_LEV_Pos               (8U)                              
+#define FLASH_OPTR_BOR_LEV_Msk               (0x7U << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000700 */
+#define FLASH_OPTR_BOR_LEV                   FLASH_OPTR_BOR_LEV_Msk            
+#define FLASH_OPTR_BOR_LEV_0                 (0x0U << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000000 */
+#define FLASH_OPTR_BOR_LEV_1                 (0x1U << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000100 */
+#define FLASH_OPTR_BOR_LEV_2                 (0x2U << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000200 */
+#define FLASH_OPTR_BOR_LEV_3                 (0x3U << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000300 */
+#define FLASH_OPTR_BOR_LEV_4                 (0x4U << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000400 */
+#define FLASH_OPTR_nRST_STOP_Pos             (12U)                             
+#define FLASH_OPTR_nRST_STOP_Msk             (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
+#define FLASH_OPTR_nRST_STOP                 FLASH_OPTR_nRST_STOP_Msk          
+#define FLASH_OPTR_nRST_STDBY_Pos            (13U)                             
+#define FLASH_OPTR_nRST_STDBY_Msk            (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
+#define FLASH_OPTR_nRST_STDBY                FLASH_OPTR_nRST_STDBY_Msk         
+#define FLASH_OPTR_nRST_SHDW_Pos             (14U)                             
+#define FLASH_OPTR_nRST_SHDW_Msk             (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
+#define FLASH_OPTR_nRST_SHDW                 FLASH_OPTR_nRST_SHDW_Msk          
+#define FLASH_OPTR_IWDG_SW_Pos               (16U)                             
+#define FLASH_OPTR_IWDG_SW_Msk               (0x1U << FLASH_OPTR_IWDG_SW_Pos)  /*!< 0x00010000 */
+#define FLASH_OPTR_IWDG_SW                   FLASH_OPTR_IWDG_SW_Msk            
+#define FLASH_OPTR_IWDG_STOP_Pos             (17U)                             
+#define FLASH_OPTR_IWDG_STOP_Msk             (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTR_IWDG_STOP                 FLASH_OPTR_IWDG_STOP_Msk          
+#define FLASH_OPTR_IWDG_STDBY_Pos            (18U)                             
+#define FLASH_OPTR_IWDG_STDBY_Msk            (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
+#define FLASH_OPTR_IWDG_STDBY                FLASH_OPTR_IWDG_STDBY_Msk         
+#define FLASH_OPTR_WWDG_SW_Pos               (19U)                             
+#define FLASH_OPTR_WWDG_SW_Msk               (0x1U << FLASH_OPTR_WWDG_SW_Pos)  /*!< 0x00080000 */
+#define FLASH_OPTR_WWDG_SW                   FLASH_OPTR_WWDG_SW_Msk            
+#define FLASH_OPTR_BFB2_Pos                  (20U)                             
+#define FLASH_OPTR_BFB2_Msk                  (0x1U << FLASH_OPTR_BFB2_Pos)     /*!< 0x00100000 */
+#define FLASH_OPTR_BFB2                      FLASH_OPTR_BFB2_Msk               
+#define FLASH_OPTR_DUALBANK_Pos              (21U)                             
+#define FLASH_OPTR_DUALBANK_Msk              (0x1U << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_DUALBANK                  FLASH_OPTR_DUALBANK_Msk           
+#define FLASH_OPTR_nBOOT1_Pos                (23U)                             
+#define FLASH_OPTR_nBOOT1_Msk                (0x1U << FLASH_OPTR_nBOOT1_Pos)   /*!< 0x00800000 */
+#define FLASH_OPTR_nBOOT1                    FLASH_OPTR_nBOOT1_Msk             
+#define FLASH_OPTR_SRAM2_PE_Pos              (24U)                             
+#define FLASH_OPTR_SRAM2_PE_Msk              (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
+#define FLASH_OPTR_SRAM2_PE                  FLASH_OPTR_SRAM2_PE_Msk           
+#define FLASH_OPTR_SRAM2_RST_Pos             (25U)                             
+#define FLASH_OPTR_SRAM2_RST_Msk             (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
+#define FLASH_OPTR_SRAM2_RST                 FLASH_OPTR_SRAM2_RST_Msk          
+
+/******************  Bits definition for FLASH_PCROP1SR register  **********/
+#define FLASH_PCROP1SR_PCROP1_STRT_Pos       (0U)                              
+#define FLASH_PCROP1SR_PCROP1_STRT_Msk       (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1SR_PCROP1_STRT           FLASH_PCROP1SR_PCROP1_STRT_Msk    
+
+/******************  Bits definition for FLASH_PCROP1ER register  ***********/
+#define FLASH_PCROP1ER_PCROP1_END_Pos        (0U)                              
+#define FLASH_PCROP1ER_PCROP1_END_Msk        (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1ER_PCROP1_END            FLASH_PCROP1ER_PCROP1_END_Msk     
+#define FLASH_PCROP1ER_PCROP_RDP_Pos         (31U)                             
+#define FLASH_PCROP1ER_PCROP_RDP_Msk         (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
+#define FLASH_PCROP1ER_PCROP_RDP             FLASH_PCROP1ER_PCROP_RDP_Msk      
+
+/******************  Bits definition for FLASH_WRP1AR register  ***************/
+#define FLASH_WRP1AR_WRP1A_STRT_Pos          (0U)                              
+#define FLASH_WRP1AR_WRP1A_STRT_Msk          (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1AR_WRP1A_STRT              FLASH_WRP1AR_WRP1A_STRT_Msk       
+#define FLASH_WRP1AR_WRP1A_END_Pos           (16U)                             
+#define FLASH_WRP1AR_WRP1A_END_Msk           (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1AR_WRP1A_END               FLASH_WRP1AR_WRP1A_END_Msk        
+
+/******************  Bits definition for FLASH_WRPB1R register  ***************/
+#define FLASH_WRP1BR_WRP1B_STRT_Pos          (0U)                              
+#define FLASH_WRP1BR_WRP1B_STRT_Msk          (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1BR_WRP1B_STRT              FLASH_WRP1BR_WRP1B_STRT_Msk       
+#define FLASH_WRP1BR_WRP1B_END_Pos           (16U)                             
+#define FLASH_WRP1BR_WRP1B_END_Msk           (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1BR_WRP1B_END               FLASH_WRP1BR_WRP1B_END_Msk        
+
+/******************  Bits definition for FLASH_PCROP2SR register  **********/
+#define FLASH_PCROP2SR_PCROP2_STRT_Pos       (0U)                              
+#define FLASH_PCROP2SR_PCROP2_STRT_Msk       (0xFFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP2SR_PCROP2_STRT           FLASH_PCROP2SR_PCROP2_STRT_Msk    
+
+/******************  Bits definition for FLASH_PCROP2ER register  ***********/
+#define FLASH_PCROP2ER_PCROP2_END_Pos        (0U)                              
+#define FLASH_PCROP2ER_PCROP2_END_Msk        (0xFFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP2ER_PCROP2_END            FLASH_PCROP2ER_PCROP2_END_Msk     
+
+/******************  Bits definition for FLASH_WRP2AR register  ***************/
+#define FLASH_WRP2AR_WRP2A_STRT_Pos          (0U)                              
+#define FLASH_WRP2AR_WRP2A_STRT_Msk          (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2AR_WRP2A_STRT              FLASH_WRP2AR_WRP2A_STRT_Msk       
+#define FLASH_WRP2AR_WRP2A_END_Pos           (16U)                             
+#define FLASH_WRP2AR_WRP2A_END_Msk           (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2AR_WRP2A_END               FLASH_WRP2AR_WRP2A_END_Msk        
+
+/******************  Bits definition for FLASH_WRP2BR register  ***************/
+#define FLASH_WRP2BR_WRP2B_STRT_Pos          (0U)                              
+#define FLASH_WRP2BR_WRP2B_STRT_Msk          (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2BR_WRP2B_STRT              FLASH_WRP2BR_WRP2B_STRT_Msk       
+#define FLASH_WRP2BR_WRP2B_END_Pos           (16U)                             
+#define FLASH_WRP2BR_WRP2B_END_Msk           (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2BR_WRP2B_END               FLASH_WRP2BR_WRP2B_END_Msk        
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_CCLKEN_Pos                (20U)                               
+#define FMC_BCR1_CCLKEN_Msk                (0x1U << FMC_BCR1_CCLKEN_Pos)       /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN                    FMC_BCR1_CCLKEN_Msk                 /*!<Continous clock enable     */
+
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
+#define FMC_BCRx_MBKEN_Pos                 (0U)                                
+#define FMC_BCRx_MBKEN_Msk                 (0x1U << FMC_BCRx_MBKEN_Pos)        /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN                     FMC_BCRx_MBKEN_Msk                  /*!<Memory bank enable bit                 */
+#define FMC_BCRx_MUXEN_Pos                 (1U)                                
+#define FMC_BCRx_MUXEN_Msk                 (0x1U << FMC_BCRx_MUXEN_Pos)        /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN                     FMC_BCRx_MUXEN_Msk                  /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCRx_MTYP_Pos                  (2U)                                
+#define FMC_BCRx_MTYP_Msk                  (0x3U << FMC_BCRx_MTYP_Pos)         /*!< 0x0000000C */
+#define FMC_BCRx_MTYP                      FMC_BCRx_MTYP_Msk                   /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCRx_MTYP_0                    (0x1U << FMC_BCRx_MTYP_Pos)         /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1                    (0x2U << FMC_BCRx_MTYP_Pos)         /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos                  (4U)                                
+#define FMC_BCRx_MWID_Msk                  (0x3U << FMC_BCRx_MWID_Pos)         /*!< 0x00000030 */
+#define FMC_BCRx_MWID                      FMC_BCRx_MWID_Msk                   /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0                    (0x1U << FMC_BCRx_MWID_Pos)         /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1                    (0x2U << FMC_BCRx_MWID_Pos)         /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos                (6U)                                
+#define FMC_BCRx_FACCEN_Msk                (0x1U << FMC_BCRx_FACCEN_Pos)       /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN                    FMC_BCRx_FACCEN_Msk                 /*!<Flash access enable        */
+#define FMC_BCRx_BURSTEN_Pos               (8U)                                
+#define FMC_BCRx_BURSTEN_Msk               (0x1U << FMC_BCRx_BURSTEN_Pos)      /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN                   FMC_BCRx_BURSTEN_Msk                /*!<Burst enable bit           */
+#define FMC_BCRx_WAITPOL_Pos               (9U)                                
+#define FMC_BCRx_WAITPOL_Msk               (0x1U << FMC_BCRx_WAITPOL_Pos)      /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL                   FMC_BCRx_WAITPOL_Msk                /*!<Wait signal polarity bit   */
+#define FMC_BCRx_WAITCFG_Pos               (11U)                               
+#define FMC_BCRx_WAITCFG_Msk               (0x1U << FMC_BCRx_WAITCFG_Pos)      /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG                   FMC_BCRx_WAITCFG_Msk                /*!<Wait timing configuration  */
+#define FMC_BCRx_WREN_Pos                  (12U)                               
+#define FMC_BCRx_WREN_Msk                  (0x1U << FMC_BCRx_WREN_Pos)         /*!< 0x00001000 */
+#define FMC_BCRx_WREN                      FMC_BCRx_WREN_Msk                   /*!<Write enable bit           */
+#define FMC_BCRx_WAITEN_Pos                (13U)                               
+#define FMC_BCRx_WAITEN_Msk                (0x1U << FMC_BCRx_WAITEN_Pos)       /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN                    FMC_BCRx_WAITEN_Msk                 /*!<Wait enable bit            */
+#define FMC_BCRx_EXTMOD_Pos                (14U)                               
+#define FMC_BCRx_EXTMOD_Msk                (0x1U << FMC_BCRx_EXTMOD_Pos)       /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD                    FMC_BCRx_EXTMOD_Msk                 /*!<Extended mode enable       */
+#define FMC_BCRx_ASYNCWAIT_Pos             (15U)                               
+#define FMC_BCRx_ASYNCWAIT_Msk             (0x1U << FMC_BCRx_ASYNCWAIT_Pos)    /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT                 FMC_BCRx_ASYNCWAIT_Msk              /*!<Asynchronous wait          */
+
+#define FMC_BCRx_CPSIZE_Pos                (16U)                               
+#define FMC_BCRx_CPSIZE_Msk                (0x7U << FMC_BCRx_CPSIZE_Pos)       /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE                    FMC_BCRx_CPSIZE_Msk                 /*!<CRAM page size             */
+#define FMC_BCRx_CPSIZE_0                  (0x1U << FMC_BCRx_CPSIZE_Pos)       /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1                  (0x2U << FMC_BCRx_CPSIZE_Pos)       /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2                  (0x4U << FMC_BCRx_CPSIZE_Pos)       /*!< 0x00040000 */
+
+#define FMC_BCRx_CBURSTRW_Pos              (19U)                               
+#define FMC_BCRx_CBURSTRW_Msk              (0x1U << FMC_BCRx_CBURSTRW_Pos)     /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW                  FMC_BCRx_CBURSTRW_Msk               /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
+#define FMC_BTRx_ADDSET_Pos                (0U)                                
+#define FMC_BTRx_ADDSET_Msk                (0xFU << FMC_BTRx_ADDSET_Pos)       /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET                    FMC_BTRx_ADDSET_Msk                 /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0                  (0x1U << FMC_BTRx_ADDSET_Pos)       /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1                  (0x2U << FMC_BTRx_ADDSET_Pos)       /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2                  (0x4U << FMC_BTRx_ADDSET_Pos)       /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3                  (0x8U << FMC_BTRx_ADDSET_Pos)       /*!< 0x00000008 */
+
+#define FMC_BTRx_ADDHLD_Pos                (4U)                                
+#define FMC_BTRx_ADDHLD_Msk                (0xFU << FMC_BTRx_ADDHLD_Pos)       /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD                    FMC_BTRx_ADDHLD_Msk                 /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTRx_ADDHLD_0                  (0x1U << FMC_BTRx_ADDHLD_Pos)       /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1                  (0x2U << FMC_BTRx_ADDHLD_Pos)       /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2                  (0x4U << FMC_BTRx_ADDHLD_Pos)       /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3                  (0x8U << FMC_BTRx_ADDHLD_Pos)       /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos                (8U)                                
+#define FMC_BTRx_DATAST_Msk                (0xFFU << FMC_BTRx_DATAST_Pos)      /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST                    FMC_BTRx_DATAST_Msk                 /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTRx_DATAST_0                  (0x01U << FMC_BTRx_DATAST_Pos)      /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1                  (0x02U << FMC_BTRx_DATAST_Pos)      /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2                  (0x04U << FMC_BTRx_DATAST_Pos)      /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3                  (0x08U << FMC_BTRx_DATAST_Pos)      /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4                  (0x10U << FMC_BTRx_DATAST_Pos)      /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5                  (0x20U << FMC_BTRx_DATAST_Pos)      /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6                  (0x40U << FMC_BTRx_DATAST_Pos)      /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7                  (0x80U << FMC_BTRx_DATAST_Pos)      /*!< 0x00008000 */
+
+#define FMC_BTRx_BUSTURN_Pos               (16U)                               
+#define FMC_BTRx_BUSTURN_Msk               (0xFU << FMC_BTRx_BUSTURN_Pos)      /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN                   FMC_BTRx_BUSTURN_Msk                /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0                 (0x1U << FMC_BTRx_BUSTURN_Pos)      /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1                 (0x2U << FMC_BTRx_BUSTURN_Pos)      /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2                 (0x4U << FMC_BTRx_BUSTURN_Pos)      /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3                 (0x8U << FMC_BTRx_BUSTURN_Pos)      /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos                (20U)                               
+#define FMC_BTRx_CLKDIV_Msk                (0xFU << FMC_BTRx_CLKDIV_Pos)       /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV                    FMC_BTRx_CLKDIV_Msk                 /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0                  (0x1U << FMC_BTRx_CLKDIV_Pos)       /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1                  (0x2U << FMC_BTRx_CLKDIV_Pos)       /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2                  (0x4U << FMC_BTRx_CLKDIV_Pos)       /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3                  (0x8U << FMC_BTRx_CLKDIV_Pos)       /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos                (24U)                               
+#define FMC_BTRx_DATLAT_Msk                (0xFU << FMC_BTRx_DATLAT_Pos)       /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT                    FMC_BTRx_DATLAT_Msk                 /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0                  (0x1U << FMC_BTRx_DATLAT_Pos)       /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1                  (0x2U << FMC_BTRx_DATLAT_Pos)       /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2                  (0x4U << FMC_BTRx_DATLAT_Pos)       /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3                  (0x8U << FMC_BTRx_DATLAT_Pos)       /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos                (28U)                               
+#define FMC_BTRx_ACCMOD_Msk                (0x3U << FMC_BTRx_ACCMOD_Pos)       /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD                    FMC_BTRx_ACCMOD_Msk                 /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0                  (0x1U << FMC_BTRx_ACCMOD_Pos)       /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1                  (0x2U << FMC_BTRx_ACCMOD_Pos)       /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos               (0U)                                
+#define FMC_BWTRx_ADDSET_Msk               (0xFU << FMC_BWTRx_ADDSET_Pos)      /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET                   FMC_BWTRx_ADDSET_Msk                /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0                 (0x1U << FMC_BWTRx_ADDSET_Pos)      /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1                 (0x2U << FMC_BWTRx_ADDSET_Pos)      /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2                 (0x4U << FMC_BWTRx_ADDSET_Pos)      /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3                 (0x8U << FMC_BWTRx_ADDSET_Pos)      /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos               (4U)                                
+#define FMC_BWTRx_ADDHLD_Msk               (0xFU << FMC_BWTRx_ADDHLD_Pos)      /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD                   FMC_BWTRx_ADDHLD_Msk                /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0                 (0x1U << FMC_BWTRx_ADDHLD_Pos)      /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1                 (0x2U << FMC_BWTRx_ADDHLD_Pos)      /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2                 (0x4U << FMC_BWTRx_ADDHLD_Pos)      /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3                 (0x8U << FMC_BWTRx_ADDHLD_Pos)      /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos               (8U)                                
+#define FMC_BWTRx_DATAST_Msk               (0xFFU << FMC_BWTRx_DATAST_Pos)     /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST                   FMC_BWTRx_DATAST_Msk                /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0                 (0x01U << FMC_BWTRx_DATAST_Pos)     /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1                 (0x02U << FMC_BWTRx_DATAST_Pos)     /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2                 (0x04U << FMC_BWTRx_DATAST_Pos)     /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3                 (0x08U << FMC_BWTRx_DATAST_Pos)     /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4                 (0x10U << FMC_BWTRx_DATAST_Pos)     /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5                 (0x20U << FMC_BWTRx_DATAST_Pos)     /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6                 (0x40U << FMC_BWTRx_DATAST_Pos)     /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7                 (0x80U << FMC_BWTRx_DATAST_Pos)     /*!< 0x00008000 */
+
+#define FMC_BWTRx_BUSTURN_Pos              (16U)                               
+#define FMC_BWTRx_BUSTURN_Msk              (0xFU << FMC_BWTRx_BUSTURN_Pos)     /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN                  FMC_BWTRx_BUSTURN_Msk               /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTRx_BUSTURN_0                (0x1U << FMC_BWTRx_BUSTURN_Pos)     /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1                (0x2U << FMC_BWTRx_BUSTURN_Pos)     /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2                (0x4U << FMC_BWTRx_BUSTURN_Pos)     /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3                (0x8U << FMC_BWTRx_BUSTURN_Pos)     /*!< 0x00080000 */
+
+#define FMC_BWTRx_ACCMOD_Pos               (28U)                               
+#define FMC_BWTRx_ACCMOD_Msk               (0x3U << FMC_BWTRx_ACCMOD_Pos)      /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD                   FMC_BWTRx_ACCMOD_Msk                /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0                 (0x1U << FMC_BWTRx_ACCMOD_Pos)      /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1                 (0x2U << FMC_BWTRx_ACCMOD_Pos)      /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCR register  ********************/
+#define FMC_PCR_PWAITEN_Pos                (1U)                                
+#define FMC_PCR_PWAITEN_Msk                (0x1U << FMC_PCR_PWAITEN_Pos)       /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN                    FMC_PCR_PWAITEN_Msk                 /*!<Wait feature enable bit                   */
+#define FMC_PCR_PBKEN_Pos                  (2U)                                
+#define FMC_PCR_PBKEN_Msk                  (0x1U << FMC_PCR_PBKEN_Pos)         /*!< 0x00000004 */
+#define FMC_PCR_PBKEN                      FMC_PCR_PBKEN_Msk                   /*!<NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP_Pos                   (3U)                                
+#define FMC_PCR_PTYP_Msk                   (0x1U << FMC_PCR_PTYP_Pos)          /*!< 0x00000008 */
+#define FMC_PCR_PTYP                       FMC_PCR_PTYP_Msk                    /*!<Memory type                               */
+
+#define FMC_PCR_PWID_Pos                   (4U)                                
+#define FMC_PCR_PWID_Msk                   (0x3U << FMC_PCR_PWID_Pos)          /*!< 0x00000030 */
+#define FMC_PCR_PWID                       FMC_PCR_PWID_Msk                    /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0                     (0x1U << FMC_PCR_PWID_Pos)          /*!< 0x00000010 */
+#define FMC_PCR_PWID_1                     (0x2U << FMC_PCR_PWID_Pos)          /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos                  (6U)                                
+#define FMC_PCR_ECCEN_Msk                  (0x1U << FMC_PCR_ECCEN_Pos)         /*!< 0x00000040 */
+#define FMC_PCR_ECCEN                      FMC_PCR_ECCEN_Msk                   /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR_TCLR_Pos                   (9U)                                
+#define FMC_PCR_TCLR_Msk                   (0xFU << FMC_PCR_TCLR_Pos)          /*!< 0x00001E00 */
+#define FMC_PCR_TCLR                       FMC_PCR_TCLR_Msk                    /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR_TCLR_0                     (0x1U << FMC_PCR_TCLR_Pos)          /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1                     (0x2U << FMC_PCR_TCLR_Pos)          /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2                     (0x4U << FMC_PCR_TCLR_Pos)          /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3                     (0x8U << FMC_PCR_TCLR_Pos)          /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos                    (13U)                               
+#define FMC_PCR_TAR_Msk                    (0xFU << FMC_PCR_TAR_Pos)           /*!< 0x0001E000 */
+#define FMC_PCR_TAR                        FMC_PCR_TAR_Msk                     /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR_TAR_0                      (0x1U << FMC_PCR_TAR_Pos)           /*!< 0x00002000 */
+#define FMC_PCR_TAR_1                      (0x2U << FMC_PCR_TAR_Pos)           /*!< 0x00004000 */
+#define FMC_PCR_TAR_2                      (0x4U << FMC_PCR_TAR_Pos)           /*!< 0x00008000 */
+#define FMC_PCR_TAR_3                      (0x8U << FMC_PCR_TAR_Pos)           /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos                  (17U)                               
+#define FMC_PCR_ECCPS_Msk                  (0x7U << FMC_PCR_ECCPS_Pos)         /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS                      FMC_PCR_ECCPS_Msk                   /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR_ECCPS_0                    (0x1U << FMC_PCR_ECCPS_Pos)         /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1                    (0x2U << FMC_PCR_ECCPS_Pos)         /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2                    (0x4U << FMC_PCR_ECCPS_Pos)         /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SR register  ********************/
+#define FMC_SR_IRS_Pos                     (0U)                                
+#define FMC_SR_IRS_Msk                     (0x1U << FMC_SR_IRS_Pos)            /*!< 0x00000001 */
+#define FMC_SR_IRS                         FMC_SR_IRS_Msk                      /*!<Interrupt Rising Edge status                */
+#define FMC_SR_ILS_Pos                     (1U)                                
+#define FMC_SR_ILS_Msk                     (0x1U << FMC_SR_ILS_Pos)            /*!< 0x00000002 */
+#define FMC_SR_ILS                         FMC_SR_ILS_Msk                      /*!<Interrupt Level status                      */
+#define FMC_SR_IFS_Pos                     (2U)                                
+#define FMC_SR_IFS_Msk                     (0x1U << FMC_SR_IFS_Pos)            /*!< 0x00000004 */
+#define FMC_SR_IFS                         FMC_SR_IFS_Msk                      /*!<Interrupt Falling Edge status               */
+#define FMC_SR_IREN_Pos                    (3U)                                
+#define FMC_SR_IREN_Msk                    (0x1U << FMC_SR_IREN_Pos)           /*!< 0x00000008 */
+#define FMC_SR_IREN                        FMC_SR_IREN_Msk                     /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR_ILEN_Pos                    (4U)                                
+#define FMC_SR_ILEN_Msk                    (0x1U << FMC_SR_ILEN_Pos)           /*!< 0x00000010 */
+#define FMC_SR_ILEN                        FMC_SR_ILEN_Msk                     /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR_IFEN_Pos                    (5U)                                
+#define FMC_SR_IFEN_Msk                    (0x1U << FMC_SR_IFEN_Pos)           /*!< 0x00000020 */
+#define FMC_SR_IFEN                        FMC_SR_IFEN_Msk                     /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos                   (6U)                                
+#define FMC_SR_FEMPT_Msk                   (0x1U << FMC_SR_FEMPT_Pos)          /*!< 0x00000040 */
+#define FMC_SR_FEMPT                       FMC_SR_FEMPT_Msk                    /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define FMC_PMEM_MEMSET_Pos                (0U)                                
+#define FMC_PMEM_MEMSET_Msk                (0xFFU << FMC_PMEM_MEMSET_Pos)      /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET                    FMC_PMEM_MEMSET_Msk                 /*!<MEMSET[7:0] bits (Common memory setup time) */
+#define FMC_PMEM_MEMSET_0                  (0x01U << FMC_PMEM_MEMSET_Pos)      /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1                  (0x02U << FMC_PMEM_MEMSET_Pos)      /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2                  (0x04U << FMC_PMEM_MEMSET_Pos)      /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3                  (0x08U << FMC_PMEM_MEMSET_Pos)      /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4                  (0x10U << FMC_PMEM_MEMSET_Pos)      /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5                  (0x20U << FMC_PMEM_MEMSET_Pos)      /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6                  (0x40U << FMC_PMEM_MEMSET_Pos)      /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7                  (0x80U << FMC_PMEM_MEMSET_Pos)      /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT_Pos               (8U)                                
+#define FMC_PMEM_MEMWAIT_Msk               (0xFFU << FMC_PMEM_MEMWAIT_Pos)     /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT                   FMC_PMEM_MEMWAIT_Msk                /*!<MEMWAIT[7:0] bits (Common memory wait time) */
+#define FMC_PMEM_MEMWAIT_0                 (0x01U << FMC_PMEM_MEMWAIT_Pos)     /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1                 (0x02U << FMC_PMEM_MEMWAIT_Pos)     /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2                 (0x04U << FMC_PMEM_MEMWAIT_Pos)     /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3                 (0x08U << FMC_PMEM_MEMWAIT_Pos)     /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4                 (0x10U << FMC_PMEM_MEMWAIT_Pos)     /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5                 (0x20U << FMC_PMEM_MEMWAIT_Pos)     /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6                 (0x40U << FMC_PMEM_MEMWAIT_Pos)     /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7                 (0x80U << FMC_PMEM_MEMWAIT_Pos)     /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD_Pos               (16U)                               
+#define FMC_PMEM_MEMHOLD_Msk               (0xFFU << FMC_PMEM_MEMHOLD_Pos)     /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD                   FMC_PMEM_MEMHOLD_Msk                /*!<MEMHOLD[7:0] bits (Common memory hold time) */
+#define FMC_PMEM_MEMHOLD_0                 (0x01U << FMC_PMEM_MEMHOLD_Pos)     /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1                 (0x02U << FMC_PMEM_MEMHOLD_Pos)     /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2                 (0x04U << FMC_PMEM_MEMHOLD_Pos)     /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3                 (0x08U << FMC_PMEM_MEMHOLD_Pos)     /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4                 (0x10U << FMC_PMEM_MEMHOLD_Pos)     /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5                 (0x20U << FMC_PMEM_MEMHOLD_Pos)     /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6                 (0x40U << FMC_PMEM_MEMHOLD_Pos)     /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7                 (0x80U << FMC_PMEM_MEMHOLD_Pos)     /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ_Pos                (24U)                               
+#define FMC_PMEM_MEMHIZ_Msk                (0xFFU << FMC_PMEM_MEMHIZ_Pos)      /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ                    FMC_PMEM_MEMHIZ_Msk                 /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
+#define FMC_PMEM_MEMHIZ_0                  (0x01U << FMC_PMEM_MEMHIZ_Pos)      /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1                  (0x02U << FMC_PMEM_MEMHIZ_Pos)      /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2                  (0x04U << FMC_PMEM_MEMHIZ_Pos)      /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3                  (0x08U << FMC_PMEM_MEMHIZ_Pos)      /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4                  (0x10U << FMC_PMEM_MEMHIZ_Pos)      /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5                  (0x20U << FMC_PMEM_MEMHIZ_Pos)      /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6                  (0x40U << FMC_PMEM_MEMHIZ_Pos)      /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7                  (0x80U << FMC_PMEM_MEMHIZ_Pos)      /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  *******************/
+#define FMC_PATT_ATTSET_Pos                (0U)                                
+#define FMC_PATT_ATTSET_Msk                (0xFFU << FMC_PATT_ATTSET_Pos)      /*!< 0x000000FF */
+#define FMC_PATT_ATTSET                    FMC_PATT_ATTSET_Msk                 /*!<ATTSET[7:0] bits (Attribute memory setup time) */
+#define FMC_PATT_ATTSET_0                  (0x01U << FMC_PATT_ATTSET_Pos)      /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1                  (0x02U << FMC_PATT_ATTSET_Pos)      /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2                  (0x04U << FMC_PATT_ATTSET_Pos)      /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3                  (0x08U << FMC_PATT_ATTSET_Pos)      /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4                  (0x10U << FMC_PATT_ATTSET_Pos)      /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5                  (0x20U << FMC_PATT_ATTSET_Pos)      /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6                  (0x40U << FMC_PATT_ATTSET_Pos)      /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7                  (0x80U << FMC_PATT_ATTSET_Pos)      /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT_Pos               (8U)                                
+#define FMC_PATT_ATTWAIT_Msk               (0xFFU << FMC_PATT_ATTWAIT_Pos)     /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT                   FMC_PATT_ATTWAIT_Msk                /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
+#define FMC_PATT_ATTWAIT_0                 (0x01U << FMC_PATT_ATTWAIT_Pos)     /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1                 (0x02U << FMC_PATT_ATTWAIT_Pos)     /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2                 (0x04U << FMC_PATT_ATTWAIT_Pos)     /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3                 (0x08U << FMC_PATT_ATTWAIT_Pos)     /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4                 (0x10U << FMC_PATT_ATTWAIT_Pos)     /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5                 (0x20U << FMC_PATT_ATTWAIT_Pos)     /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6                 (0x40U << FMC_PATT_ATTWAIT_Pos)     /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7                 (0x80U << FMC_PATT_ATTWAIT_Pos)     /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD_Pos               (16U)                               
+#define FMC_PATT_ATTHOLD_Msk               (0xFFU << FMC_PATT_ATTHOLD_Pos)     /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD                   FMC_PATT_ATTHOLD_Msk                /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
+#define FMC_PATT_ATTHOLD_0                 (0x01U << FMC_PATT_ATTHOLD_Pos)     /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1                 (0x02U << FMC_PATT_ATTHOLD_Pos)     /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2                 (0x04U << FMC_PATT_ATTHOLD_Pos)     /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3                 (0x08U << FMC_PATT_ATTHOLD_Pos)     /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4                 (0x10U << FMC_PATT_ATTHOLD_Pos)     /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5                 (0x20U << FMC_PATT_ATTHOLD_Pos)     /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6                 (0x40U << FMC_PATT_ATTHOLD_Pos)     /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7                 (0x80U << FMC_PATT_ATTHOLD_Pos)     /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ_Pos                (24U)                               
+#define FMC_PATT_ATTHIZ_Msk                (0xFFU << FMC_PATT_ATTHIZ_Pos)      /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ                    FMC_PATT_ATTHIZ_Msk                 /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
+#define FMC_PATT_ATTHIZ_0                  (0x01U << FMC_PATT_ATTHIZ_Pos)      /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1                  (0x02U << FMC_PATT_ATTHIZ_Pos)      /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2                  (0x04U << FMC_PATT_ATTHIZ_Pos)      /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3                  (0x08U << FMC_PATT_ATTHIZ_Pos)      /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4                  (0x10U << FMC_PATT_ATTHIZ_Pos)      /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5                  (0x20U << FMC_PATT_ATTHIZ_Pos)      /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6                  (0x40U << FMC_PATT_ATTHIZ_Pos)      /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7                  (0x80U << FMC_PATT_ATTHIZ_Pos)      /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_ECCR register  *******************/
+#define FMC_ECCR_ECC_Pos                   (0U)                                
+#define FMC_ECCR_ECC_Msk                   (0xFFFFFFFFU << FMC_ECCR_ECC_Pos)   /*!< 0xFFFFFFFF */
+#define FMC_ECCR_ECC                       FMC_ECCR_ECC_Msk                    /*!<ECC result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos                 (0U)                              
+#define GPIO_MODER_MODE0_Msk                 (0x3U << GPIO_MODER_MODE0_Pos)    /*!< 0x00000003 */
+#define GPIO_MODER_MODE0                     GPIO_MODER_MODE0_Msk              
+#define GPIO_MODER_MODE0_0                   (0x1U << GPIO_MODER_MODE0_Pos)    /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1                   (0x2U << GPIO_MODER_MODE0_Pos)    /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos                 (2U)                              
+#define GPIO_MODER_MODE1_Msk                 (0x3U << GPIO_MODER_MODE1_Pos)    /*!< 0x0000000C */
+#define GPIO_MODER_MODE1                     GPIO_MODER_MODE1_Msk              
+#define GPIO_MODER_MODE1_0                   (0x1U << GPIO_MODER_MODE1_Pos)    /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1                   (0x2U << GPIO_MODER_MODE1_Pos)    /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos                 (4U)                              
+#define GPIO_MODER_MODE2_Msk                 (0x3U << GPIO_MODER_MODE2_Pos)    /*!< 0x00000030 */
+#define GPIO_MODER_MODE2                     GPIO_MODER_MODE2_Msk              
+#define GPIO_MODER_MODE2_0                   (0x1U << GPIO_MODER_MODE2_Pos)    /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1                   (0x2U << GPIO_MODER_MODE2_Pos)    /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos                 (6U)                              
+#define GPIO_MODER_MODE3_Msk                 (0x3U << GPIO_MODER_MODE3_Pos)    /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3                     GPIO_MODER_MODE3_Msk              
+#define GPIO_MODER_MODE3_0                   (0x1U << GPIO_MODER_MODE3_Pos)    /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1                   (0x2U << GPIO_MODER_MODE3_Pos)    /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos                 (8U)                              
+#define GPIO_MODER_MODE4_Msk                 (0x3U << GPIO_MODER_MODE4_Pos)    /*!< 0x00000300 */
+#define GPIO_MODER_MODE4                     GPIO_MODER_MODE4_Msk              
+#define GPIO_MODER_MODE4_0                   (0x1U << GPIO_MODER_MODE4_Pos)    /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1                   (0x2U << GPIO_MODER_MODE4_Pos)    /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos                 (10U)                             
+#define GPIO_MODER_MODE5_Msk                 (0x3U << GPIO_MODER_MODE5_Pos)    /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5                     GPIO_MODER_MODE5_Msk              
+#define GPIO_MODER_MODE5_0                   (0x1U << GPIO_MODER_MODE5_Pos)    /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1                   (0x2U << GPIO_MODER_MODE5_Pos)    /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos                 (12U)                             
+#define GPIO_MODER_MODE6_Msk                 (0x3U << GPIO_MODER_MODE6_Pos)    /*!< 0x00003000 */
+#define GPIO_MODER_MODE6                     GPIO_MODER_MODE6_Msk              
+#define GPIO_MODER_MODE6_0                   (0x1U << GPIO_MODER_MODE6_Pos)    /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1                   (0x2U << GPIO_MODER_MODE6_Pos)    /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos                 (14U)                             
+#define GPIO_MODER_MODE7_Msk                 (0x3U << GPIO_MODER_MODE7_Pos)    /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7                     GPIO_MODER_MODE7_Msk              
+#define GPIO_MODER_MODE7_0                   (0x1U << GPIO_MODER_MODE7_Pos)    /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1                   (0x2U << GPIO_MODER_MODE7_Pos)    /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos                 (16U)                             
+#define GPIO_MODER_MODE8_Msk                 (0x3U << GPIO_MODER_MODE8_Pos)    /*!< 0x00030000 */
+#define GPIO_MODER_MODE8                     GPIO_MODER_MODE8_Msk              
+#define GPIO_MODER_MODE8_0                   (0x1U << GPIO_MODER_MODE8_Pos)    /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1                   (0x2U << GPIO_MODER_MODE8_Pos)    /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos                 (18U)                             
+#define GPIO_MODER_MODE9_Msk                 (0x3U << GPIO_MODER_MODE9_Pos)    /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9                     GPIO_MODER_MODE9_Msk              
+#define GPIO_MODER_MODE9_0                   (0x1U << GPIO_MODER_MODE9_Pos)    /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1                   (0x2U << GPIO_MODER_MODE9_Pos)    /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos                (20U)                             
+#define GPIO_MODER_MODE10_Msk                (0x3U << GPIO_MODER_MODE10_Pos)   /*!< 0x00300000 */
+#define GPIO_MODER_MODE10                    GPIO_MODER_MODE10_Msk             
+#define GPIO_MODER_MODE10_0                  (0x1U << GPIO_MODER_MODE10_Pos)   /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1                  (0x2U << GPIO_MODER_MODE10_Pos)   /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos                (22U)                             
+#define GPIO_MODER_MODE11_Msk                (0x3U << GPIO_MODER_MODE11_Pos)   /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11                    GPIO_MODER_MODE11_Msk             
+#define GPIO_MODER_MODE11_0                  (0x1U << GPIO_MODER_MODE11_Pos)   /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1                  (0x2U << GPIO_MODER_MODE11_Pos)   /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos                (24U)                             
+#define GPIO_MODER_MODE12_Msk                (0x3U << GPIO_MODER_MODE12_Pos)   /*!< 0x03000000 */
+#define GPIO_MODER_MODE12                    GPIO_MODER_MODE12_Msk             
+#define GPIO_MODER_MODE12_0                  (0x1U << GPIO_MODER_MODE12_Pos)   /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1                  (0x2U << GPIO_MODER_MODE12_Pos)   /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos                (26U)                             
+#define GPIO_MODER_MODE13_Msk                (0x3U << GPIO_MODER_MODE13_Pos)   /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13                    GPIO_MODER_MODE13_Msk             
+#define GPIO_MODER_MODE13_0                  (0x1U << GPIO_MODER_MODE13_Pos)   /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1                  (0x2U << GPIO_MODER_MODE13_Pos)   /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos                (28U)                             
+#define GPIO_MODER_MODE14_Msk                (0x3U << GPIO_MODER_MODE14_Pos)   /*!< 0x30000000 */
+#define GPIO_MODER_MODE14                    GPIO_MODER_MODE14_Msk             
+#define GPIO_MODER_MODE14_0                  (0x1U << GPIO_MODER_MODE14_Pos)   /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1                  (0x2U << GPIO_MODER_MODE14_Pos)   /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos                (30U)                             
+#define GPIO_MODER_MODE15_Msk                (0x3U << GPIO_MODER_MODE15_Pos)   /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15                    GPIO_MODER_MODE15_Msk             
+#define GPIO_MODER_MODE15_0                  (0x1U << GPIO_MODER_MODE15_Pos)   /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1                  (0x2U << GPIO_MODER_MODE15_Pos)   /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
+#define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
+#define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
+#define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
+#define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
+#define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
+#define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
+#define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
+#define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
+#define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
+#define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
+#define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
+#define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
+#define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
+#define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
+#define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
+#define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
+#define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
+#define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
+#define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
+#define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
+#define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
+#define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
+#define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
+#define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
+#define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
+#define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
+#define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
+#define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
+#define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
+#define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
+#define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
+#define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
+#define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
+#define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
+#define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
+#define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
+#define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
+#define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
+#define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
+#define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
+#define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
+#define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
+#define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
+#define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
+#define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
+#define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
+#define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos                  (0U)                              
+#define GPIO_OTYPER_OT0_Msk                  (0x1U << GPIO_OTYPER_OT0_Pos)     /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                      GPIO_OTYPER_OT0_Msk               
+#define GPIO_OTYPER_OT1_Pos                  (1U)                              
+#define GPIO_OTYPER_OT1_Msk                  (0x1U << GPIO_OTYPER_OT1_Pos)     /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                      GPIO_OTYPER_OT1_Msk               
+#define GPIO_OTYPER_OT2_Pos                  (2U)                              
+#define GPIO_OTYPER_OT2_Msk                  (0x1U << GPIO_OTYPER_OT2_Pos)     /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                      GPIO_OTYPER_OT2_Msk               
+#define GPIO_OTYPER_OT3_Pos                  (3U)                              
+#define GPIO_OTYPER_OT3_Msk                  (0x1U << GPIO_OTYPER_OT3_Pos)     /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                      GPIO_OTYPER_OT3_Msk               
+#define GPIO_OTYPER_OT4_Pos                  (4U)                              
+#define GPIO_OTYPER_OT4_Msk                  (0x1U << GPIO_OTYPER_OT4_Pos)     /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                      GPIO_OTYPER_OT4_Msk               
+#define GPIO_OTYPER_OT5_Pos                  (5U)                              
+#define GPIO_OTYPER_OT5_Msk                  (0x1U << GPIO_OTYPER_OT5_Pos)     /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                      GPIO_OTYPER_OT5_Msk               
+#define GPIO_OTYPER_OT6_Pos                  (6U)                              
+#define GPIO_OTYPER_OT6_Msk                  (0x1U << GPIO_OTYPER_OT6_Pos)     /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                      GPIO_OTYPER_OT6_Msk               
+#define GPIO_OTYPER_OT7_Pos                  (7U)                              
+#define GPIO_OTYPER_OT7_Msk                  (0x1U << GPIO_OTYPER_OT7_Pos)     /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                      GPIO_OTYPER_OT7_Msk               
+#define GPIO_OTYPER_OT8_Pos                  (8U)                              
+#define GPIO_OTYPER_OT8_Msk                  (0x1U << GPIO_OTYPER_OT8_Pos)     /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                      GPIO_OTYPER_OT8_Msk               
+#define GPIO_OTYPER_OT9_Pos                  (9U)                              
+#define GPIO_OTYPER_OT9_Msk                  (0x1U << GPIO_OTYPER_OT9_Pos)     /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                      GPIO_OTYPER_OT9_Msk               
+#define GPIO_OTYPER_OT10_Pos                 (10U)                             
+#define GPIO_OTYPER_OT10_Msk                 (0x1U << GPIO_OTYPER_OT10_Pos)    /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10                     GPIO_OTYPER_OT10_Msk              
+#define GPIO_OTYPER_OT11_Pos                 (11U)                             
+#define GPIO_OTYPER_OT11_Msk                 (0x1U << GPIO_OTYPER_OT11_Pos)    /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11                     GPIO_OTYPER_OT11_Msk              
+#define GPIO_OTYPER_OT12_Pos                 (12U)                             
+#define GPIO_OTYPER_OT12_Msk                 (0x1U << GPIO_OTYPER_OT12_Pos)    /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12                     GPIO_OTYPER_OT12_Msk              
+#define GPIO_OTYPER_OT13_Pos                 (13U)                             
+#define GPIO_OTYPER_OT13_Msk                 (0x1U << GPIO_OTYPER_OT13_Pos)    /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13                     GPIO_OTYPER_OT13_Msk              
+#define GPIO_OTYPER_OT14_Pos                 (14U)                             
+#define GPIO_OTYPER_OT14_Msk                 (0x1U << GPIO_OTYPER_OT14_Pos)    /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14                     GPIO_OTYPER_OT14_Msk              
+#define GPIO_OTYPER_OT15_Pos                 (15U)                             
+#define GPIO_OTYPER_OT15_Msk                 (0x1U << GPIO_OTYPER_OT15_Pos)    /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15                     GPIO_OTYPER_OT15_Msk              
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos             (0U)                              
+#define GPIO_OSPEEDR_OSPEED0_Msk             (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0                 GPIO_OSPEEDR_OSPEED0_Msk          
+#define GPIO_OSPEEDR_OSPEED0_0               (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1               (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos             (2U)                              
+#define GPIO_OSPEEDR_OSPEED1_Msk             (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1                 GPIO_OSPEEDR_OSPEED1_Msk          
+#define GPIO_OSPEEDR_OSPEED1_0               (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1               (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos             (4U)                              
+#define GPIO_OSPEEDR_OSPEED2_Msk             (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2                 GPIO_OSPEEDR_OSPEED2_Msk          
+#define GPIO_OSPEEDR_OSPEED2_0               (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1               (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos             (6U)                              
+#define GPIO_OSPEEDR_OSPEED3_Msk             (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3                 GPIO_OSPEEDR_OSPEED3_Msk          
+#define GPIO_OSPEEDR_OSPEED3_0               (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1               (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos             (8U)                              
+#define GPIO_OSPEEDR_OSPEED4_Msk             (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4                 GPIO_OSPEEDR_OSPEED4_Msk          
+#define GPIO_OSPEEDR_OSPEED4_0               (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1               (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos             (10U)                             
+#define GPIO_OSPEEDR_OSPEED5_Msk             (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5                 GPIO_OSPEEDR_OSPEED5_Msk          
+#define GPIO_OSPEEDR_OSPEED5_0               (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1               (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos             (12U)                             
+#define GPIO_OSPEEDR_OSPEED6_Msk             (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6                 GPIO_OSPEEDR_OSPEED6_Msk          
+#define GPIO_OSPEEDR_OSPEED6_0               (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1               (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos             (14U)                             
+#define GPIO_OSPEEDR_OSPEED7_Msk             (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7                 GPIO_OSPEEDR_OSPEED7_Msk          
+#define GPIO_OSPEEDR_OSPEED7_0               (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1               (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos             (16U)                             
+#define GPIO_OSPEEDR_OSPEED8_Msk             (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8                 GPIO_OSPEEDR_OSPEED8_Msk          
+#define GPIO_OSPEEDR_OSPEED8_0               (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1               (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos             (18U)                             
+#define GPIO_OSPEEDR_OSPEED9_Msk             (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9                 GPIO_OSPEEDR_OSPEED9_Msk          
+#define GPIO_OSPEEDR_OSPEED9_0               (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1               (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos            (20U)                             
+#define GPIO_OSPEEDR_OSPEED10_Msk            (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10                GPIO_OSPEEDR_OSPEED10_Msk         
+#define GPIO_OSPEEDR_OSPEED10_0              (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1              (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos            (22U)                             
+#define GPIO_OSPEEDR_OSPEED11_Msk            (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11                GPIO_OSPEEDR_OSPEED11_Msk         
+#define GPIO_OSPEEDR_OSPEED11_0              (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1              (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos            (24U)                             
+#define GPIO_OSPEEDR_OSPEED12_Msk            (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12                GPIO_OSPEEDR_OSPEED12_Msk         
+#define GPIO_OSPEEDR_OSPEED12_0              (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1              (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos            (26U)                             
+#define GPIO_OSPEEDR_OSPEED13_Msk            (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13                GPIO_OSPEEDR_OSPEED13_Msk         
+#define GPIO_OSPEEDR_OSPEED13_0              (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1              (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos            (28U)                             
+#define GPIO_OSPEEDR_OSPEED14_Msk            (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14                GPIO_OSPEEDR_OSPEED14_Msk         
+#define GPIO_OSPEEDR_OSPEED14_0              (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1              (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos            (30U)                             
+#define GPIO_OSPEEDR_OSPEED15_Msk            (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15                GPIO_OSPEEDR_OSPEED15_Msk         
+#define GPIO_OSPEEDR_OSPEED15_0              (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1              (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos                 (0U)                              
+#define GPIO_PUPDR_PUPD0_Msk                 (0x3U << GPIO_PUPDR_PUPD0_Pos)    /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0                     GPIO_PUPDR_PUPD0_Msk              
+#define GPIO_PUPDR_PUPD0_0                   (0x1U << GPIO_PUPDR_PUPD0_Pos)    /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1                   (0x2U << GPIO_PUPDR_PUPD0_Pos)    /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos                 (2U)                              
+#define GPIO_PUPDR_PUPD1_Msk                 (0x3U << GPIO_PUPDR_PUPD1_Pos)    /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1                     GPIO_PUPDR_PUPD1_Msk              
+#define GPIO_PUPDR_PUPD1_0                   (0x1U << GPIO_PUPDR_PUPD1_Pos)    /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1                   (0x2U << GPIO_PUPDR_PUPD1_Pos)    /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos                 (4U)                              
+#define GPIO_PUPDR_PUPD2_Msk                 (0x3U << GPIO_PUPDR_PUPD2_Pos)    /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2                     GPIO_PUPDR_PUPD2_Msk              
+#define GPIO_PUPDR_PUPD2_0                   (0x1U << GPIO_PUPDR_PUPD2_Pos)    /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1                   (0x2U << GPIO_PUPDR_PUPD2_Pos)    /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos                 (6U)                              
+#define GPIO_PUPDR_PUPD3_Msk                 (0x3U << GPIO_PUPDR_PUPD3_Pos)    /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3                     GPIO_PUPDR_PUPD3_Msk              
+#define GPIO_PUPDR_PUPD3_0                   (0x1U << GPIO_PUPDR_PUPD3_Pos)    /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1                   (0x2U << GPIO_PUPDR_PUPD3_Pos)    /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos                 (8U)                              
+#define GPIO_PUPDR_PUPD4_Msk                 (0x3U << GPIO_PUPDR_PUPD4_Pos)    /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4                     GPIO_PUPDR_PUPD4_Msk              
+#define GPIO_PUPDR_PUPD4_0                   (0x1U << GPIO_PUPDR_PUPD4_Pos)    /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1                   (0x2U << GPIO_PUPDR_PUPD4_Pos)    /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos                 (10U)                             
+#define GPIO_PUPDR_PUPD5_Msk                 (0x3U << GPIO_PUPDR_PUPD5_Pos)    /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5                     GPIO_PUPDR_PUPD5_Msk              
+#define GPIO_PUPDR_PUPD5_0                   (0x1U << GPIO_PUPDR_PUPD5_Pos)    /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1                   (0x2U << GPIO_PUPDR_PUPD5_Pos)    /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos                 (12U)                             
+#define GPIO_PUPDR_PUPD6_Msk                 (0x3U << GPIO_PUPDR_PUPD6_Pos)    /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6                     GPIO_PUPDR_PUPD6_Msk              
+#define GPIO_PUPDR_PUPD6_0                   (0x1U << GPIO_PUPDR_PUPD6_Pos)    /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1                   (0x2U << GPIO_PUPDR_PUPD6_Pos)    /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos                 (14U)                             
+#define GPIO_PUPDR_PUPD7_Msk                 (0x3U << GPIO_PUPDR_PUPD7_Pos)    /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7                     GPIO_PUPDR_PUPD7_Msk              
+#define GPIO_PUPDR_PUPD7_0                   (0x1U << GPIO_PUPDR_PUPD7_Pos)    /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1                   (0x2U << GPIO_PUPDR_PUPD7_Pos)    /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos                 (16U)                             
+#define GPIO_PUPDR_PUPD8_Msk                 (0x3U << GPIO_PUPDR_PUPD8_Pos)    /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8                     GPIO_PUPDR_PUPD8_Msk              
+#define GPIO_PUPDR_PUPD8_0                   (0x1U << GPIO_PUPDR_PUPD8_Pos)    /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1                   (0x2U << GPIO_PUPDR_PUPD8_Pos)    /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos                 (18U)                             
+#define GPIO_PUPDR_PUPD9_Msk                 (0x3U << GPIO_PUPDR_PUPD9_Pos)    /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9                     GPIO_PUPDR_PUPD9_Msk              
+#define GPIO_PUPDR_PUPD9_0                   (0x1U << GPIO_PUPDR_PUPD9_Pos)    /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1                   (0x2U << GPIO_PUPDR_PUPD9_Pos)    /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos                (20U)                             
+#define GPIO_PUPDR_PUPD10_Msk                (0x3U << GPIO_PUPDR_PUPD10_Pos)   /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10                    GPIO_PUPDR_PUPD10_Msk             
+#define GPIO_PUPDR_PUPD10_0                  (0x1U << GPIO_PUPDR_PUPD10_Pos)   /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1                  (0x2U << GPIO_PUPDR_PUPD10_Pos)   /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos                (22U)                             
+#define GPIO_PUPDR_PUPD11_Msk                (0x3U << GPIO_PUPDR_PUPD11_Pos)   /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11                    GPIO_PUPDR_PUPD11_Msk             
+#define GPIO_PUPDR_PUPD11_0                  (0x1U << GPIO_PUPDR_PUPD11_Pos)   /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1                  (0x2U << GPIO_PUPDR_PUPD11_Pos)   /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos                (24U)                             
+#define GPIO_PUPDR_PUPD12_Msk                (0x3U << GPIO_PUPDR_PUPD12_Pos)   /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12                    GPIO_PUPDR_PUPD12_Msk             
+#define GPIO_PUPDR_PUPD12_0                  (0x1U << GPIO_PUPDR_PUPD12_Pos)   /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1                  (0x2U << GPIO_PUPDR_PUPD12_Pos)   /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos                (26U)                             
+#define GPIO_PUPDR_PUPD13_Msk                (0x3U << GPIO_PUPDR_PUPD13_Pos)   /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13                    GPIO_PUPDR_PUPD13_Msk             
+#define GPIO_PUPDR_PUPD13_0                  (0x1U << GPIO_PUPDR_PUPD13_Pos)   /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1                  (0x2U << GPIO_PUPDR_PUPD13_Pos)   /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos                (28U)                             
+#define GPIO_PUPDR_PUPD14_Msk                (0x3U << GPIO_PUPDR_PUPD14_Pos)   /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14                    GPIO_PUPDR_PUPD14_Msk             
+#define GPIO_PUPDR_PUPD14_0                  (0x1U << GPIO_PUPDR_PUPD14_Pos)   /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1                  (0x2U << GPIO_PUPDR_PUPD14_Pos)   /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos                (30U)                             
+#define GPIO_PUPDR_PUPD15_Msk                (0x3U << GPIO_PUPDR_PUPD15_Pos)   /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15                    GPIO_PUPDR_PUPD15_Msk             
+#define GPIO_PUPDR_PUPD15_0                  (0x1U << GPIO_PUPDR_PUPD15_Pos)   /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1                  (0x2U << GPIO_PUPDR_PUPD15_Pos)   /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos                     (0U)                              
+#define GPIO_IDR_ID0_Msk                     (0x1U << GPIO_IDR_ID0_Pos)        /*!< 0x00000001 */
+#define GPIO_IDR_ID0                         GPIO_IDR_ID0_Msk                  
+#define GPIO_IDR_ID1_Pos                     (1U)                              
+#define GPIO_IDR_ID1_Msk                     (0x1U << GPIO_IDR_ID1_Pos)        /*!< 0x00000002 */
+#define GPIO_IDR_ID1                         GPIO_IDR_ID1_Msk                  
+#define GPIO_IDR_ID2_Pos                     (2U)                              
+#define GPIO_IDR_ID2_Msk                     (0x1U << GPIO_IDR_ID2_Pos)        /*!< 0x00000004 */
+#define GPIO_IDR_ID2                         GPIO_IDR_ID2_Msk                  
+#define GPIO_IDR_ID3_Pos                     (3U)                              
+#define GPIO_IDR_ID3_Msk                     (0x1U << GPIO_IDR_ID3_Pos)        /*!< 0x00000008 */
+#define GPIO_IDR_ID3                         GPIO_IDR_ID3_Msk                  
+#define GPIO_IDR_ID4_Pos                     (4U)                              
+#define GPIO_IDR_ID4_Msk                     (0x1U << GPIO_IDR_ID4_Pos)        /*!< 0x00000010 */
+#define GPIO_IDR_ID4                         GPIO_IDR_ID4_Msk                  
+#define GPIO_IDR_ID5_Pos                     (5U)                              
+#define GPIO_IDR_ID5_Msk                     (0x1U << GPIO_IDR_ID5_Pos)        /*!< 0x00000020 */
+#define GPIO_IDR_ID5                         GPIO_IDR_ID5_Msk                  
+#define GPIO_IDR_ID6_Pos                     (6U)                              
+#define GPIO_IDR_ID6_Msk                     (0x1U << GPIO_IDR_ID6_Pos)        /*!< 0x00000040 */
+#define GPIO_IDR_ID6                         GPIO_IDR_ID6_Msk                  
+#define GPIO_IDR_ID7_Pos                     (7U)                              
+#define GPIO_IDR_ID7_Msk                     (0x1U << GPIO_IDR_ID7_Pos)        /*!< 0x00000080 */
+#define GPIO_IDR_ID7                         GPIO_IDR_ID7_Msk                  
+#define GPIO_IDR_ID8_Pos                     (8U)                              
+#define GPIO_IDR_ID8_Msk                     (0x1U << GPIO_IDR_ID8_Pos)        /*!< 0x00000100 */
+#define GPIO_IDR_ID8                         GPIO_IDR_ID8_Msk                  
+#define GPIO_IDR_ID9_Pos                     (9U)                              
+#define GPIO_IDR_ID9_Msk                     (0x1U << GPIO_IDR_ID9_Pos)        /*!< 0x00000200 */
+#define GPIO_IDR_ID9                         GPIO_IDR_ID9_Msk                  
+#define GPIO_IDR_ID10_Pos                    (10U)                             
+#define GPIO_IDR_ID10_Msk                    (0x1U << GPIO_IDR_ID10_Pos)       /*!< 0x00000400 */
+#define GPIO_IDR_ID10                        GPIO_IDR_ID10_Msk                 
+#define GPIO_IDR_ID11_Pos                    (11U)                             
+#define GPIO_IDR_ID11_Msk                    (0x1U << GPIO_IDR_ID11_Pos)       /*!< 0x00000800 */
+#define GPIO_IDR_ID11                        GPIO_IDR_ID11_Msk                 
+#define GPIO_IDR_ID12_Pos                    (12U)                             
+#define GPIO_IDR_ID12_Msk                    (0x1U << GPIO_IDR_ID12_Pos)       /*!< 0x00001000 */
+#define GPIO_IDR_ID12                        GPIO_IDR_ID12_Msk                 
+#define GPIO_IDR_ID13_Pos                    (13U)                             
+#define GPIO_IDR_ID13_Msk                    (0x1U << GPIO_IDR_ID13_Pos)       /*!< 0x00002000 */
+#define GPIO_IDR_ID13                        GPIO_IDR_ID13_Msk                 
+#define GPIO_IDR_ID14_Pos                    (14U)                             
+#define GPIO_IDR_ID14_Msk                    (0x1U << GPIO_IDR_ID14_Pos)       /*!< 0x00004000 */
+#define GPIO_IDR_ID14                        GPIO_IDR_ID14_Msk                 
+#define GPIO_IDR_ID15_Pos                    (15U)                             
+#define GPIO_IDR_ID15_Msk                    (0x1U << GPIO_IDR_ID15_Pos)       /*!< 0x00008000 */
+#define GPIO_IDR_ID15                        GPIO_IDR_ID15_Msk                 
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
+
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
+#define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
+#define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
+#define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
+#define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
+#define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
+#define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
+#define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
+#define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
+#define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
+#define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
+#define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
+#define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
+#define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
+#define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
+#define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos                     (0U)                              
+#define GPIO_ODR_OD0_Msk                     (0x1U << GPIO_ODR_OD0_Pos)        /*!< 0x00000001 */
+#define GPIO_ODR_OD0                         GPIO_ODR_OD0_Msk                  
+#define GPIO_ODR_OD1_Pos                     (1U)                              
+#define GPIO_ODR_OD1_Msk                     (0x1U << GPIO_ODR_OD1_Pos)        /*!< 0x00000002 */
+#define GPIO_ODR_OD1                         GPIO_ODR_OD1_Msk                  
+#define GPIO_ODR_OD2_Pos                     (2U)                              
+#define GPIO_ODR_OD2_Msk                     (0x1U << GPIO_ODR_OD2_Pos)        /*!< 0x00000004 */
+#define GPIO_ODR_OD2                         GPIO_ODR_OD2_Msk                  
+#define GPIO_ODR_OD3_Pos                     (3U)                              
+#define GPIO_ODR_OD3_Msk                     (0x1U << GPIO_ODR_OD3_Pos)        /*!< 0x00000008 */
+#define GPIO_ODR_OD3                         GPIO_ODR_OD3_Msk                  
+#define GPIO_ODR_OD4_Pos                     (4U)                              
+#define GPIO_ODR_OD4_Msk                     (0x1U << GPIO_ODR_OD4_Pos)        /*!< 0x00000010 */
+#define GPIO_ODR_OD4                         GPIO_ODR_OD4_Msk                  
+#define GPIO_ODR_OD5_Pos                     (5U)                              
+#define GPIO_ODR_OD5_Msk                     (0x1U << GPIO_ODR_OD5_Pos)        /*!< 0x00000020 */
+#define GPIO_ODR_OD5                         GPIO_ODR_OD5_Msk                  
+#define GPIO_ODR_OD6_Pos                     (6U)                              
+#define GPIO_ODR_OD6_Msk                     (0x1U << GPIO_ODR_OD6_Pos)        /*!< 0x00000040 */
+#define GPIO_ODR_OD6                         GPIO_ODR_OD6_Msk                  
+#define GPIO_ODR_OD7_Pos                     (7U)                              
+#define GPIO_ODR_OD7_Msk                     (0x1U << GPIO_ODR_OD7_Pos)        /*!< 0x00000080 */
+#define GPIO_ODR_OD7                         GPIO_ODR_OD7_Msk                  
+#define GPIO_ODR_OD8_Pos                     (8U)                              
+#define GPIO_ODR_OD8_Msk                     (0x1U << GPIO_ODR_OD8_Pos)        /*!< 0x00000100 */
+#define GPIO_ODR_OD8                         GPIO_ODR_OD8_Msk                  
+#define GPIO_ODR_OD9_Pos                     (9U)                              
+#define GPIO_ODR_OD9_Msk                     (0x1U << GPIO_ODR_OD9_Pos)        /*!< 0x00000200 */
+#define GPIO_ODR_OD9                         GPIO_ODR_OD9_Msk                  
+#define GPIO_ODR_OD10_Pos                    (10U)                             
+#define GPIO_ODR_OD10_Msk                    (0x1U << GPIO_ODR_OD10_Pos)       /*!< 0x00000400 */
+#define GPIO_ODR_OD10                        GPIO_ODR_OD10_Msk                 
+#define GPIO_ODR_OD11_Pos                    (11U)                             
+#define GPIO_ODR_OD11_Msk                    (0x1U << GPIO_ODR_OD11_Pos)       /*!< 0x00000800 */
+#define GPIO_ODR_OD11                        GPIO_ODR_OD11_Msk                 
+#define GPIO_ODR_OD12_Pos                    (12U)                             
+#define GPIO_ODR_OD12_Msk                    (0x1U << GPIO_ODR_OD12_Pos)       /*!< 0x00001000 */
+#define GPIO_ODR_OD12                        GPIO_ODR_OD12_Msk                 
+#define GPIO_ODR_OD13_Pos                    (13U)                             
+#define GPIO_ODR_OD13_Msk                    (0x1U << GPIO_ODR_OD13_Pos)       /*!< 0x00002000 */
+#define GPIO_ODR_OD13                        GPIO_ODR_OD13_Msk                 
+#define GPIO_ODR_OD14_Pos                    (14U)                             
+#define GPIO_ODR_OD14_Msk                    (0x1U << GPIO_ODR_OD14_Pos)       /*!< 0x00004000 */
+#define GPIO_ODR_OD14                        GPIO_ODR_OD14_Msk                 
+#define GPIO_ODR_OD15_Pos                    (15U)                             
+#define GPIO_ODR_OD15_Msk                    (0x1U << GPIO_ODR_OD15_Pos)       /*!< 0x00008000 */
+#define GPIO_ODR_OD15                        GPIO_ODR_OD15_Msk                 
+
+/* Legacy defines */
+#define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
+
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
+#define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
+#define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
+#define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
+#define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
+#define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
+#define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
+#define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
+#define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
+#define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
+#define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
+#define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
+#define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
+#define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
+#define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
+#define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos                    (0U)                              
+#define GPIO_BSRR_BS0_Msk                    (0x1U << GPIO_BSRR_BS0_Pos)       /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                        GPIO_BSRR_BS0_Msk                 
+#define GPIO_BSRR_BS1_Pos                    (1U)                              
+#define GPIO_BSRR_BS1_Msk                    (0x1U << GPIO_BSRR_BS1_Pos)       /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                        GPIO_BSRR_BS1_Msk                 
+#define GPIO_BSRR_BS2_Pos                    (2U)                              
+#define GPIO_BSRR_BS2_Msk                    (0x1U << GPIO_BSRR_BS2_Pos)       /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                        GPIO_BSRR_BS2_Msk                 
+#define GPIO_BSRR_BS3_Pos                    (3U)                              
+#define GPIO_BSRR_BS3_Msk                    (0x1U << GPIO_BSRR_BS3_Pos)       /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                        GPIO_BSRR_BS3_Msk                 
+#define GPIO_BSRR_BS4_Pos                    (4U)                              
+#define GPIO_BSRR_BS4_Msk                    (0x1U << GPIO_BSRR_BS4_Pos)       /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                        GPIO_BSRR_BS4_Msk                 
+#define GPIO_BSRR_BS5_Pos                    (5U)                              
+#define GPIO_BSRR_BS5_Msk                    (0x1U << GPIO_BSRR_BS5_Pos)       /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                        GPIO_BSRR_BS5_Msk                 
+#define GPIO_BSRR_BS6_Pos                    (6U)                              
+#define GPIO_BSRR_BS6_Msk                    (0x1U << GPIO_BSRR_BS6_Pos)       /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                        GPIO_BSRR_BS6_Msk                 
+#define GPIO_BSRR_BS7_Pos                    (7U)                              
+#define GPIO_BSRR_BS7_Msk                    (0x1U << GPIO_BSRR_BS7_Pos)       /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                        GPIO_BSRR_BS7_Msk                 
+#define GPIO_BSRR_BS8_Pos                    (8U)                              
+#define GPIO_BSRR_BS8_Msk                    (0x1U << GPIO_BSRR_BS8_Pos)       /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                        GPIO_BSRR_BS8_Msk                 
+#define GPIO_BSRR_BS9_Pos                    (9U)                              
+#define GPIO_BSRR_BS9_Msk                    (0x1U << GPIO_BSRR_BS9_Pos)       /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                        GPIO_BSRR_BS9_Msk                 
+#define GPIO_BSRR_BS10_Pos                   (10U)                             
+#define GPIO_BSRR_BS10_Msk                   (0x1U << GPIO_BSRR_BS10_Pos)      /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                       GPIO_BSRR_BS10_Msk                
+#define GPIO_BSRR_BS11_Pos                   (11U)                             
+#define GPIO_BSRR_BS11_Msk                   (0x1U << GPIO_BSRR_BS11_Pos)      /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                       GPIO_BSRR_BS11_Msk                
+#define GPIO_BSRR_BS12_Pos                   (12U)                             
+#define GPIO_BSRR_BS12_Msk                   (0x1U << GPIO_BSRR_BS12_Pos)      /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                       GPIO_BSRR_BS12_Msk                
+#define GPIO_BSRR_BS13_Pos                   (13U)                             
+#define GPIO_BSRR_BS13_Msk                   (0x1U << GPIO_BSRR_BS13_Pos)      /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                       GPIO_BSRR_BS13_Msk                
+#define GPIO_BSRR_BS14_Pos                   (14U)                             
+#define GPIO_BSRR_BS14_Msk                   (0x1U << GPIO_BSRR_BS14_Pos)      /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                       GPIO_BSRR_BS14_Msk                
+#define GPIO_BSRR_BS15_Pos                   (15U)                             
+#define GPIO_BSRR_BS15_Msk                   (0x1U << GPIO_BSRR_BS15_Pos)      /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                       GPIO_BSRR_BS15_Msk                
+#define GPIO_BSRR_BR0_Pos                    (16U)                             
+#define GPIO_BSRR_BR0_Msk                    (0x1U << GPIO_BSRR_BR0_Pos)       /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                        GPIO_BSRR_BR0_Msk                 
+#define GPIO_BSRR_BR1_Pos                    (17U)                             
+#define GPIO_BSRR_BR1_Msk                    (0x1U << GPIO_BSRR_BR1_Pos)       /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                        GPIO_BSRR_BR1_Msk                 
+#define GPIO_BSRR_BR2_Pos                    (18U)                             
+#define GPIO_BSRR_BR2_Msk                    (0x1U << GPIO_BSRR_BR2_Pos)       /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                        GPIO_BSRR_BR2_Msk                 
+#define GPIO_BSRR_BR3_Pos                    (19U)                             
+#define GPIO_BSRR_BR3_Msk                    (0x1U << GPIO_BSRR_BR3_Pos)       /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                        GPIO_BSRR_BR3_Msk                 
+#define GPIO_BSRR_BR4_Pos                    (20U)                             
+#define GPIO_BSRR_BR4_Msk                    (0x1U << GPIO_BSRR_BR4_Pos)       /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                        GPIO_BSRR_BR4_Msk                 
+#define GPIO_BSRR_BR5_Pos                    (21U)                             
+#define GPIO_BSRR_BR5_Msk                    (0x1U << GPIO_BSRR_BR5_Pos)       /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                        GPIO_BSRR_BR5_Msk                 
+#define GPIO_BSRR_BR6_Pos                    (22U)                             
+#define GPIO_BSRR_BR6_Msk                    (0x1U << GPIO_BSRR_BR6_Pos)       /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                        GPIO_BSRR_BR6_Msk                 
+#define GPIO_BSRR_BR7_Pos                    (23U)                             
+#define GPIO_BSRR_BR7_Msk                    (0x1U << GPIO_BSRR_BR7_Pos)       /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                        GPIO_BSRR_BR7_Msk                 
+#define GPIO_BSRR_BR8_Pos                    (24U)                             
+#define GPIO_BSRR_BR8_Msk                    (0x1U << GPIO_BSRR_BR8_Pos)       /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                        GPIO_BSRR_BR8_Msk                 
+#define GPIO_BSRR_BR9_Pos                    (25U)                             
+#define GPIO_BSRR_BR9_Msk                    (0x1U << GPIO_BSRR_BR9_Pos)       /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                        GPIO_BSRR_BR9_Msk                 
+#define GPIO_BSRR_BR10_Pos                   (26U)                             
+#define GPIO_BSRR_BR10_Msk                   (0x1U << GPIO_BSRR_BR10_Pos)      /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                       GPIO_BSRR_BR10_Msk                
+#define GPIO_BSRR_BR11_Pos                   (27U)                             
+#define GPIO_BSRR_BR11_Msk                   (0x1U << GPIO_BSRR_BR11_Pos)      /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                       GPIO_BSRR_BR11_Msk                
+#define GPIO_BSRR_BR12_Pos                   (28U)                             
+#define GPIO_BSRR_BR12_Msk                   (0x1U << GPIO_BSRR_BR12_Pos)      /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                       GPIO_BSRR_BR12_Msk                
+#define GPIO_BSRR_BR13_Pos                   (29U)                             
+#define GPIO_BSRR_BR13_Msk                   (0x1U << GPIO_BSRR_BR13_Pos)      /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                       GPIO_BSRR_BR13_Msk                
+#define GPIO_BSRR_BR14_Pos                   (30U)                             
+#define GPIO_BSRR_BR14_Msk                   (0x1U << GPIO_BSRR_BR14_Pos)      /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                       GPIO_BSRR_BR14_Msk                
+#define GPIO_BSRR_BR15_Pos                   (31U)                             
+#define GPIO_BSRR_BR15_Msk                   (0x1U << GPIO_BSRR_BR15_Pos)      /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                       GPIO_BSRR_BR15_Msk                
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos                   (0U)                              
+#define GPIO_LCKR_LCK0_Msk                   (0x1U << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                
+#define GPIO_LCKR_LCK1_Pos                   (1U)                              
+#define GPIO_LCKR_LCK1_Msk                   (0x1U << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                
+#define GPIO_LCKR_LCK2_Pos                   (2U)                              
+#define GPIO_LCKR_LCK2_Msk                   (0x1U << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                
+#define GPIO_LCKR_LCK3_Pos                   (3U)                              
+#define GPIO_LCKR_LCK3_Msk                   (0x1U << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                
+#define GPIO_LCKR_LCK4_Pos                   (4U)                              
+#define GPIO_LCKR_LCK4_Msk                   (0x1U << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                
+#define GPIO_LCKR_LCK5_Pos                   (5U)                              
+#define GPIO_LCKR_LCK5_Msk                   (0x1U << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                
+#define GPIO_LCKR_LCK6_Pos                   (6U)                              
+#define GPIO_LCKR_LCK6_Msk                   (0x1U << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                
+#define GPIO_LCKR_LCK7_Pos                   (7U)                              
+#define GPIO_LCKR_LCK7_Msk                   (0x1U << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                
+#define GPIO_LCKR_LCK8_Pos                   (8U)                              
+#define GPIO_LCKR_LCK8_Msk                   (0x1U << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                
+#define GPIO_LCKR_LCK9_Pos                   (9U)                              
+#define GPIO_LCKR_LCK9_Msk                   (0x1U << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                
+#define GPIO_LCKR_LCK10_Pos                  (10U)                             
+#define GPIO_LCKR_LCK10_Msk                  (0x1U << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               
+#define GPIO_LCKR_LCK11_Pos                  (11U)                             
+#define GPIO_LCKR_LCK11_Msk                  (0x1U << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               
+#define GPIO_LCKR_LCK12_Pos                  (12U)                             
+#define GPIO_LCKR_LCK12_Msk                  (0x1U << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               
+#define GPIO_LCKR_LCK13_Pos                  (13U)                             
+#define GPIO_LCKR_LCK13_Msk                  (0x1U << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               
+#define GPIO_LCKR_LCK14_Pos                  (14U)                             
+#define GPIO_LCKR_LCK14_Msk                  (0x1U << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               
+#define GPIO_LCKR_LCK15_Pos                  (15U)                             
+#define GPIO_LCKR_LCK15_Msk                  (0x1U << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               
+#define GPIO_LCKR_LCKK_Pos                   (16U)                             
+#define GPIO_LCKR_LCKK_Msk                   (0x1U << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos                 (0U)                              
+#define GPIO_AFRL_AFSEL0_Msk                 (0xFU << GPIO_AFRL_AFSEL0_Pos)    /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                     GPIO_AFRL_AFSEL0_Msk              
+#define GPIO_AFRL_AFSEL0_0                   (0x1U << GPIO_AFRL_AFSEL0_Pos)    /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1                   (0x2U << GPIO_AFRL_AFSEL0_Pos)    /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2                   (0x4U << GPIO_AFRL_AFSEL0_Pos)    /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3                   (0x8U << GPIO_AFRL_AFSEL0_Pos)    /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos                 (4U)                              
+#define GPIO_AFRL_AFSEL1_Msk                 (0xFU << GPIO_AFRL_AFSEL1_Pos)    /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                     GPIO_AFRL_AFSEL1_Msk              
+#define GPIO_AFRL_AFSEL1_0                   (0x1U << GPIO_AFRL_AFSEL1_Pos)    /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1                   (0x2U << GPIO_AFRL_AFSEL1_Pos)    /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2                   (0x4U << GPIO_AFRL_AFSEL1_Pos)    /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3                   (0x8U << GPIO_AFRL_AFSEL1_Pos)    /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos                 (8U)                              
+#define GPIO_AFRL_AFSEL2_Msk                 (0xFU << GPIO_AFRL_AFSEL2_Pos)    /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                     GPIO_AFRL_AFSEL2_Msk              
+#define GPIO_AFRL_AFSEL2_0                   (0x1U << GPIO_AFRL_AFSEL2_Pos)    /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1                   (0x2U << GPIO_AFRL_AFSEL2_Pos)    /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2                   (0x4U << GPIO_AFRL_AFSEL2_Pos)    /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3                   (0x8U << GPIO_AFRL_AFSEL2_Pos)    /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos                 (12U)                             
+#define GPIO_AFRL_AFSEL3_Msk                 (0xFU << GPIO_AFRL_AFSEL3_Pos)    /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                     GPIO_AFRL_AFSEL3_Msk              
+#define GPIO_AFRL_AFSEL3_0                   (0x1U << GPIO_AFRL_AFSEL3_Pos)    /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1                   (0x2U << GPIO_AFRL_AFSEL3_Pos)    /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2                   (0x4U << GPIO_AFRL_AFSEL3_Pos)    /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3                   (0x8U << GPIO_AFRL_AFSEL3_Pos)    /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos                 (16U)                             
+#define GPIO_AFRL_AFSEL4_Msk                 (0xFU << GPIO_AFRL_AFSEL4_Pos)    /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                     GPIO_AFRL_AFSEL4_Msk              
+#define GPIO_AFRL_AFSEL4_0                   (0x1U << GPIO_AFRL_AFSEL4_Pos)    /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1                   (0x2U << GPIO_AFRL_AFSEL4_Pos)    /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2                   (0x4U << GPIO_AFRL_AFSEL4_Pos)    /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3                   (0x8U << GPIO_AFRL_AFSEL4_Pos)    /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos                 (20U)                             
+#define GPIO_AFRL_AFSEL5_Msk                 (0xFU << GPIO_AFRL_AFSEL5_Pos)    /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                     GPIO_AFRL_AFSEL5_Msk              
+#define GPIO_AFRL_AFSEL5_0                   (0x1U << GPIO_AFRL_AFSEL5_Pos)    /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1                   (0x2U << GPIO_AFRL_AFSEL5_Pos)    /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2                   (0x4U << GPIO_AFRL_AFSEL5_Pos)    /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3                   (0x8U << GPIO_AFRL_AFSEL5_Pos)    /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos                 (24U)                             
+#define GPIO_AFRL_AFSEL6_Msk                 (0xFU << GPIO_AFRL_AFSEL6_Pos)    /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                     GPIO_AFRL_AFSEL6_Msk              
+#define GPIO_AFRL_AFSEL6_0                   (0x1U << GPIO_AFRL_AFSEL6_Pos)    /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1                   (0x2U << GPIO_AFRL_AFSEL6_Pos)    /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2                   (0x4U << GPIO_AFRL_AFSEL6_Pos)    /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3                   (0x8U << GPIO_AFRL_AFSEL6_Pos)    /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos                 (28U)                             
+#define GPIO_AFRL_AFSEL7_Msk                 (0xFU << GPIO_AFRL_AFSEL7_Pos)    /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                     GPIO_AFRL_AFSEL7_Msk              
+#define GPIO_AFRL_AFSEL7_0                   (0x1U << GPIO_AFRL_AFSEL7_Pos)    /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1                   (0x2U << GPIO_AFRL_AFSEL7_Pos)    /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2                   (0x4U << GPIO_AFRL_AFSEL7_Pos)    /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3                   (0x8U << GPIO_AFRL_AFSEL7_Pos)    /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos                 (0U)                              
+#define GPIO_AFRH_AFSEL8_Msk                 (0xFU << GPIO_AFRH_AFSEL8_Pos)    /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                     GPIO_AFRH_AFSEL8_Msk              
+#define GPIO_AFRH_AFSEL8_0                   (0x1U << GPIO_AFRH_AFSEL8_Pos)    /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1                   (0x2U << GPIO_AFRH_AFSEL8_Pos)    /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2                   (0x4U << GPIO_AFRH_AFSEL8_Pos)    /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3                   (0x8U << GPIO_AFRH_AFSEL8_Pos)    /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos                 (4U)                              
+#define GPIO_AFRH_AFSEL9_Msk                 (0xFU << GPIO_AFRH_AFSEL9_Pos)    /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                     GPIO_AFRH_AFSEL9_Msk              
+#define GPIO_AFRH_AFSEL9_0                   (0x1U << GPIO_AFRH_AFSEL9_Pos)    /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1                   (0x2U << GPIO_AFRH_AFSEL9_Pos)    /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2                   (0x4U << GPIO_AFRH_AFSEL9_Pos)    /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3                   (0x8U << GPIO_AFRH_AFSEL9_Pos)    /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos                (8U)                              
+#define GPIO_AFRH_AFSEL10_Msk                (0xFU << GPIO_AFRH_AFSEL10_Pos)   /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10                    GPIO_AFRH_AFSEL10_Msk             
+#define GPIO_AFRH_AFSEL10_0                  (0x1U << GPIO_AFRH_AFSEL10_Pos)   /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1                  (0x2U << GPIO_AFRH_AFSEL10_Pos)   /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2                  (0x4U << GPIO_AFRH_AFSEL10_Pos)   /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3                  (0x8U << GPIO_AFRH_AFSEL10_Pos)   /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos                (12U)                             
+#define GPIO_AFRH_AFSEL11_Msk                (0xFU << GPIO_AFRH_AFSEL11_Pos)   /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11                    GPIO_AFRH_AFSEL11_Msk             
+#define GPIO_AFRH_AFSEL11_0                  (0x1U << GPIO_AFRH_AFSEL11_Pos)   /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1                  (0x2U << GPIO_AFRH_AFSEL11_Pos)   /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2                  (0x4U << GPIO_AFRH_AFSEL11_Pos)   /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3                  (0x8U << GPIO_AFRH_AFSEL11_Pos)   /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos                (16U)                             
+#define GPIO_AFRH_AFSEL12_Msk                (0xFU << GPIO_AFRH_AFSEL12_Pos)   /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12                    GPIO_AFRH_AFSEL12_Msk             
+#define GPIO_AFRH_AFSEL12_0                  (0x1U << GPIO_AFRH_AFSEL12_Pos)   /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1                  (0x2U << GPIO_AFRH_AFSEL12_Pos)   /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2                  (0x4U << GPIO_AFRH_AFSEL12_Pos)   /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3                  (0x8U << GPIO_AFRH_AFSEL12_Pos)   /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos                (20U)                             
+#define GPIO_AFRH_AFSEL13_Msk                (0xFU << GPIO_AFRH_AFSEL13_Pos)   /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13                    GPIO_AFRH_AFSEL13_Msk             
+#define GPIO_AFRH_AFSEL13_0                  (0x1U << GPIO_AFRH_AFSEL13_Pos)   /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1                  (0x2U << GPIO_AFRH_AFSEL13_Pos)   /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2                  (0x4U << GPIO_AFRH_AFSEL13_Pos)   /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3                  (0x8U << GPIO_AFRH_AFSEL13_Pos)   /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos                (24U)                             
+#define GPIO_AFRH_AFSEL14_Msk                (0xFU << GPIO_AFRH_AFSEL14_Pos)   /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14                    GPIO_AFRH_AFSEL14_Msk             
+#define GPIO_AFRH_AFSEL14_0                  (0x1U << GPIO_AFRH_AFSEL14_Pos)   /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1                  (0x2U << GPIO_AFRH_AFSEL14_Pos)   /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2                  (0x4U << GPIO_AFRH_AFSEL14_Pos)   /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3                  (0x8U << GPIO_AFRH_AFSEL14_Pos)   /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos                (28U)                             
+#define GPIO_AFRH_AFSEL15_Msk                (0xFU << GPIO_AFRH_AFSEL15_Pos)   /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15                    GPIO_AFRH_AFSEL15_Msk             
+#define GPIO_AFRH_AFSEL15_0                  (0x1U << GPIO_AFRH_AFSEL15_Pos)   /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1                  (0x2U << GPIO_AFRH_AFSEL15_Pos)   /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2                  (0x4U << GPIO_AFRH_AFSEL15_Pos)   /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3                  (0x8U << GPIO_AFRH_AFSEL15_Pos)   /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************  Bits definition for GPIO_BRR register  ******************/
+#define GPIO_BRR_BR0_Pos                     (0U)                              
+#define GPIO_BRR_BR0_Msk                     (0x1U << GPIO_BRR_BR0_Pos)        /*!< 0x00000001 */
+#define GPIO_BRR_BR0                         GPIO_BRR_BR0_Msk                  
+#define GPIO_BRR_BR1_Pos                     (1U)                              
+#define GPIO_BRR_BR1_Msk                     (0x1U << GPIO_BRR_BR1_Pos)        /*!< 0x00000002 */
+#define GPIO_BRR_BR1                         GPIO_BRR_BR1_Msk                  
+#define GPIO_BRR_BR2_Pos                     (2U)                              
+#define GPIO_BRR_BR2_Msk                     (0x1U << GPIO_BRR_BR2_Pos)        /*!< 0x00000004 */
+#define GPIO_BRR_BR2                         GPIO_BRR_BR2_Msk                  
+#define GPIO_BRR_BR3_Pos                     (3U)                              
+#define GPIO_BRR_BR3_Msk                     (0x1U << GPIO_BRR_BR3_Pos)        /*!< 0x00000008 */
+#define GPIO_BRR_BR3                         GPIO_BRR_BR3_Msk                  
+#define GPIO_BRR_BR4_Pos                     (4U)                              
+#define GPIO_BRR_BR4_Msk                     (0x1U << GPIO_BRR_BR4_Pos)        /*!< 0x00000010 */
+#define GPIO_BRR_BR4                         GPIO_BRR_BR4_Msk                  
+#define GPIO_BRR_BR5_Pos                     (5U)                              
+#define GPIO_BRR_BR5_Msk                     (0x1U << GPIO_BRR_BR5_Pos)        /*!< 0x00000020 */
+#define GPIO_BRR_BR5                         GPIO_BRR_BR5_Msk                  
+#define GPIO_BRR_BR6_Pos                     (6U)                              
+#define GPIO_BRR_BR6_Msk                     (0x1U << GPIO_BRR_BR6_Pos)        /*!< 0x00000040 */
+#define GPIO_BRR_BR6                         GPIO_BRR_BR6_Msk                  
+#define GPIO_BRR_BR7_Pos                     (7U)                              
+#define GPIO_BRR_BR7_Msk                     (0x1U << GPIO_BRR_BR7_Pos)        /*!< 0x00000080 */
+#define GPIO_BRR_BR7                         GPIO_BRR_BR7_Msk                  
+#define GPIO_BRR_BR8_Pos                     (8U)                              
+#define GPIO_BRR_BR8_Msk                     (0x1U << GPIO_BRR_BR8_Pos)        /*!< 0x00000100 */
+#define GPIO_BRR_BR8                         GPIO_BRR_BR8_Msk                  
+#define GPIO_BRR_BR9_Pos                     (9U)                              
+#define GPIO_BRR_BR9_Msk                     (0x1U << GPIO_BRR_BR9_Pos)        /*!< 0x00000200 */
+#define GPIO_BRR_BR9                         GPIO_BRR_BR9_Msk                  
+#define GPIO_BRR_BR10_Pos                    (10U)                             
+#define GPIO_BRR_BR10_Msk                    (0x1U << GPIO_BRR_BR10_Pos)       /*!< 0x00000400 */
+#define GPIO_BRR_BR10                        GPIO_BRR_BR10_Msk                 
+#define GPIO_BRR_BR11_Pos                    (11U)                             
+#define GPIO_BRR_BR11_Msk                    (0x1U << GPIO_BRR_BR11_Pos)       /*!< 0x00000800 */
+#define GPIO_BRR_BR11                        GPIO_BRR_BR11_Msk                 
+#define GPIO_BRR_BR12_Pos                    (12U)                             
+#define GPIO_BRR_BR12_Msk                    (0x1U << GPIO_BRR_BR12_Pos)       /*!< 0x00001000 */
+#define GPIO_BRR_BR12                        GPIO_BRR_BR12_Msk                 
+#define GPIO_BRR_BR13_Pos                    (13U)                             
+#define GPIO_BRR_BR13_Msk                    (0x1U << GPIO_BRR_BR13_Pos)       /*!< 0x00002000 */
+#define GPIO_BRR_BR13                        GPIO_BRR_BR13_Msk                 
+#define GPIO_BRR_BR14_Pos                    (14U)                             
+#define GPIO_BRR_BR14_Msk                    (0x1U << GPIO_BRR_BR14_Pos)       /*!< 0x00004000 */
+#define GPIO_BRR_BR14                        GPIO_BRR_BR14_Msk                 
+#define GPIO_BRR_BR15_Pos                    (15U)                             
+#define GPIO_BRR_BR15_Msk                    (0x1U << GPIO_BRR_BR15_Pos)       /*!< 0x00008000 */
+#define GPIO_BRR_BR15                        GPIO_BRR_BR15_Msk                 
+
+/* Legacy defines */
+#define GPIO_BRR_BR_0                       GPIO_BRR_BR0
+#define GPIO_BRR_BR_1                       GPIO_BRR_BR1
+#define GPIO_BRR_BR_2                       GPIO_BRR_BR2
+#define GPIO_BRR_BR_3                       GPIO_BRR_BR3
+#define GPIO_BRR_BR_4                       GPIO_BRR_BR4
+#define GPIO_BRR_BR_5                       GPIO_BRR_BR5
+#define GPIO_BRR_BR_6                       GPIO_BRR_BR6
+#define GPIO_BRR_BR_7                       GPIO_BRR_BR7
+#define GPIO_BRR_BR_8                       GPIO_BRR_BR8
+#define GPIO_BRR_BR_9                       GPIO_BRR_BR9
+#define GPIO_BRR_BR_10                      GPIO_BRR_BR10
+#define GPIO_BRR_BR_11                      GPIO_BRR_BR11
+#define GPIO_BRR_BR_12                      GPIO_BRR_BR12
+#define GPIO_BRR_BR_13                      GPIO_BRR_BR13
+#define GPIO_BRR_BR_14                      GPIO_BRR_BR14
+#define GPIO_BRR_BR_15                      GPIO_BRR_BR15
+
+
+/******************  Bits definition for GPIO_ASCR register  *******************/
+#define GPIO_ASCR_ASC0_Pos                   (0U)                              
+#define GPIO_ASCR_ASC0_Msk                   (0x1U << GPIO_ASCR_ASC0_Pos)      /*!< 0x00000001 */
+#define GPIO_ASCR_ASC0                       GPIO_ASCR_ASC0_Msk                
+#define GPIO_ASCR_ASC1_Pos                   (1U)                              
+#define GPIO_ASCR_ASC1_Msk                   (0x1U << GPIO_ASCR_ASC1_Pos)      /*!< 0x00000002 */
+#define GPIO_ASCR_ASC1                       GPIO_ASCR_ASC1_Msk                
+#define GPIO_ASCR_ASC2_Pos                   (2U)                              
+#define GPIO_ASCR_ASC2_Msk                   (0x1U << GPIO_ASCR_ASC2_Pos)      /*!< 0x00000004 */
+#define GPIO_ASCR_ASC2                       GPIO_ASCR_ASC2_Msk                
+#define GPIO_ASCR_ASC3_Pos                   (3U)                              
+#define GPIO_ASCR_ASC3_Msk                   (0x1U << GPIO_ASCR_ASC3_Pos)      /*!< 0x00000008 */
+#define GPIO_ASCR_ASC3                       GPIO_ASCR_ASC3_Msk                
+#define GPIO_ASCR_ASC4_Pos                   (4U)                              
+#define GPIO_ASCR_ASC4_Msk                   (0x1U << GPIO_ASCR_ASC4_Pos)      /*!< 0x00000010 */
+#define GPIO_ASCR_ASC4                       GPIO_ASCR_ASC4_Msk                
+#define GPIO_ASCR_ASC5_Pos                   (5U)                              
+#define GPIO_ASCR_ASC5_Msk                   (0x1U << GPIO_ASCR_ASC5_Pos)      /*!< 0x00000020 */
+#define GPIO_ASCR_ASC5                       GPIO_ASCR_ASC5_Msk                
+#define GPIO_ASCR_ASC6_Pos                   (6U)                              
+#define GPIO_ASCR_ASC6_Msk                   (0x1U << GPIO_ASCR_ASC6_Pos)      /*!< 0x00000040 */
+#define GPIO_ASCR_ASC6                       GPIO_ASCR_ASC6_Msk                
+#define GPIO_ASCR_ASC7_Pos                   (7U)                              
+#define GPIO_ASCR_ASC7_Msk                   (0x1U << GPIO_ASCR_ASC7_Pos)      /*!< 0x00000080 */
+#define GPIO_ASCR_ASC7                       GPIO_ASCR_ASC7_Msk                
+#define GPIO_ASCR_ASC8_Pos                   (8U)                              
+#define GPIO_ASCR_ASC8_Msk                   (0x1U << GPIO_ASCR_ASC8_Pos)      /*!< 0x00000100 */
+#define GPIO_ASCR_ASC8                       GPIO_ASCR_ASC8_Msk                
+#define GPIO_ASCR_ASC9_Pos                   (9U)                              
+#define GPIO_ASCR_ASC9_Msk                   (0x1U << GPIO_ASCR_ASC9_Pos)      /*!< 0x00000200 */
+#define GPIO_ASCR_ASC9                       GPIO_ASCR_ASC9_Msk                
+#define GPIO_ASCR_ASC10_Pos                  (10U)                             
+#define GPIO_ASCR_ASC10_Msk                  (0x1U << GPIO_ASCR_ASC10_Pos)     /*!< 0x00000400 */
+#define GPIO_ASCR_ASC10                      GPIO_ASCR_ASC10_Msk               
+#define GPIO_ASCR_ASC11_Pos                  (11U)                             
+#define GPIO_ASCR_ASC11_Msk                  (0x1U << GPIO_ASCR_ASC11_Pos)     /*!< 0x00000800 */
+#define GPIO_ASCR_ASC11                      GPIO_ASCR_ASC11_Msk               
+#define GPIO_ASCR_ASC12_Pos                  (12U)                             
+#define GPIO_ASCR_ASC12_Msk                  (0x1U << GPIO_ASCR_ASC12_Pos)     /*!< 0x00001000 */
+#define GPIO_ASCR_ASC12                      GPIO_ASCR_ASC12_Msk               
+#define GPIO_ASCR_ASC13_Pos                  (13U)                             
+#define GPIO_ASCR_ASC13_Msk                  (0x1U << GPIO_ASCR_ASC13_Pos)     /*!< 0x00002000 */
+#define GPIO_ASCR_ASC13                      GPIO_ASCR_ASC13_Msk               
+#define GPIO_ASCR_ASC14_Pos                  (14U)                             
+#define GPIO_ASCR_ASC14_Msk                  (0x1U << GPIO_ASCR_ASC14_Pos)     /*!< 0x00004000 */
+#define GPIO_ASCR_ASC14                      GPIO_ASCR_ASC14_Msk               
+#define GPIO_ASCR_ASC15_Pos                  (15U)                             
+#define GPIO_ASCR_ASC15_Msk                  (0x1U << GPIO_ASCR_ASC15_Pos)     /*!< 0x00008000 */
+#define GPIO_ASCR_ASC15                      GPIO_ASCR_ASC15_Msk               
+
+/* Legacy defines */
+#define GPIO_ASCR_EN_0                      GPIO_ASCR_ASC0
+#define GPIO_ASCR_EN_1                      GPIO_ASCR_ASC1
+#define GPIO_ASCR_EN_2                      GPIO_ASCR_ASC2
+#define GPIO_ASCR_EN_3                      GPIO_ASCR_ASC3
+#define GPIO_ASCR_EN_4                      GPIO_ASCR_ASC4
+#define GPIO_ASCR_EN_5                      GPIO_ASCR_ASC5
+#define GPIO_ASCR_EN_6                      GPIO_ASCR_ASC6
+#define GPIO_ASCR_EN_7                      GPIO_ASCR_ASC7
+#define GPIO_ASCR_EN_8                      GPIO_ASCR_ASC8
+#define GPIO_ASCR_EN_9                      GPIO_ASCR_ASC9
+#define GPIO_ASCR_EN_10                     GPIO_ASCR_ASC10
+#define GPIO_ASCR_EN_11                     GPIO_ASCR_ASC11
+#define GPIO_ASCR_EN_12                     GPIO_ASCR_ASC12
+#define GPIO_ASCR_EN_13                     GPIO_ASCR_ASC13
+#define GPIO_ASCR_EN_14                     GPIO_ASCR_ASC14
+#define GPIO_ASCR_EN_15                     GPIO_ASCR_ASC15
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos                      (0U)                               
+#define I2C_CR1_PE_Msk                      (0x1U << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
+#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral enable                   */
+#define I2C_CR1_TXIE_Pos                    (1U)                               
+#define I2C_CR1_TXIE_Msk                    (0x1U << I2C_CR1_TXIE_Pos)         /*!< 0x00000002 */
+#define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                   /*!< TX interrupt enable                 */
+#define I2C_CR1_RXIE_Pos                    (2U)                               
+#define I2C_CR1_RXIE_Msk                    (0x1U << I2C_CR1_RXIE_Pos)         /*!< 0x00000004 */
+#define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                   /*!< RX interrupt enable                 */
+#define I2C_CR1_ADDRIE_Pos                  (3U)                               
+#define I2C_CR1_ADDRIE_Msk                  (0x1U << I2C_CR1_ADDRIE_Pos)       /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                 /*!< Address match interrupt enable      */
+#define I2C_CR1_NACKIE_Pos                  (4U)                               
+#define I2C_CR1_NACKIE_Msk                  (0x1U << I2C_CR1_NACKIE_Pos)       /*!< 0x00000010 */
+#define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                 /*!< NACK received interrupt enable      */
+#define I2C_CR1_STOPIE_Pos                  (5U)                               
+#define I2C_CR1_STOPIE_Msk                  (0x1U << I2C_CR1_STOPIE_Pos)       /*!< 0x00000020 */
+#define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                 /*!< STOP detection interrupt enable     */
+#define I2C_CR1_TCIE_Pos                    (6U)                               
+#define I2C_CR1_TCIE_Msk                    (0x1U << I2C_CR1_TCIE_Pos)         /*!< 0x00000040 */
+#define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                   /*!< Transfer complete interrupt enable  */
+#define I2C_CR1_ERRIE_Pos                   (7U)                               
+#define I2C_CR1_ERRIE_Msk                   (0x1U << I2C_CR1_ERRIE_Pos)        /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                  /*!< Errors interrupt enable             */
+#define I2C_CR1_DNF_Pos                     (8U)                               
+#define I2C_CR1_DNF_Msk                     (0xFU << I2C_CR1_DNF_Pos)          /*!< 0x00000F00 */
+#define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                    /*!< Digital noise filter                */
+#define I2C_CR1_ANFOFF_Pos                  (12U)                              
+#define I2C_CR1_ANFOFF_Msk                  (0x1U << I2C_CR1_ANFOFF_Pos)       /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                 /*!< Analog noise filter OFF             */
+#define I2C_CR1_SWRST_Pos                   (13U)                              
+#define I2C_CR1_SWRST_Msk                   (0x1U << I2C_CR1_SWRST_Pos)        /*!< 0x00002000 */
+#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software reset                      */
+#define I2C_CR1_TXDMAEN_Pos                 (14U)                              
+#define I2C_CR1_TXDMAEN_Msk                 (0x1U << I2C_CR1_TXDMAEN_Pos)      /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                /*!< DMA transmission requests enable    */
+#define I2C_CR1_RXDMAEN_Pos                 (15U)                              
+#define I2C_CR1_RXDMAEN_Msk                 (0x1U << I2C_CR1_RXDMAEN_Pos)      /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                /*!< DMA reception requests enable       */
+#define I2C_CR1_SBC_Pos                     (16U)                              
+#define I2C_CR1_SBC_Msk                     (0x1U << I2C_CR1_SBC_Pos)          /*!< 0x00010000 */
+#define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                    /*!< Slave byte control                  */
+#define I2C_CR1_NOSTRETCH_Pos               (17U)                              
+#define I2C_CR1_NOSTRETCH_Msk               (0x1U << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock stretching disable            */
+#define I2C_CR1_WUPEN_Pos                   (18U)                              
+#define I2C_CR1_WUPEN_Msk                   (0x1U << I2C_CR1_WUPEN_Pos)        /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                  /*!< Wakeup from STOP enable             */
+#define I2C_CR1_GCEN_Pos                    (19U)                              
+#define I2C_CR1_GCEN_Msk                    (0x1U << I2C_CR1_GCEN_Pos)         /*!< 0x00080000 */
+#define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                   /*!< General call enable                 */
+#define I2C_CR1_SMBHEN_Pos                  (20U)                              
+#define I2C_CR1_SMBHEN_Msk                  (0x1U << I2C_CR1_SMBHEN_Pos)       /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN                      I2C_CR1_SMBHEN_Msk                 /*!< SMBus host address enable           */
+#define I2C_CR1_SMBDEN_Pos                  (21U)                              
+#define I2C_CR1_SMBDEN_Msk                  (0x1U << I2C_CR1_SMBDEN_Pos)       /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN                      I2C_CR1_SMBDEN_Msk                 /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos                 (22U)                              
+#define I2C_CR1_ALERTEN_Msk                 (0x1U << I2C_CR1_ALERTEN_Pos)      /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN                     I2C_CR1_ALERTEN_Msk                /*!< SMBus alert enable                  */
+#define I2C_CR1_PECEN_Pos                   (23U)                              
+#define I2C_CR1_PECEN_Msk                   (0x1U << I2C_CR1_PECEN_Pos)        /*!< 0x00800000 */
+#define I2C_CR1_PECEN                       I2C_CR1_PECEN_Msk                  /*!< PEC enable                          */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos                    (0U)                               
+#define I2C_CR2_SADD_Msk                    (0x3FFU << I2C_CR2_SADD_Pos)       /*!< 0x000003FF */
+#define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                   /*!< Slave address (master mode)                             */
+#define I2C_CR2_RD_WRN_Pos                  (10U)                              
+#define I2C_CR2_RD_WRN_Msk                  (0x1U << I2C_CR2_RD_WRN_Pos)       /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                 /*!< Transfer direction (master mode)                        */
+#define I2C_CR2_ADD10_Pos                   (11U)                              
+#define I2C_CR2_ADD10_Msk                   (0x1U << I2C_CR2_ADD10_Pos)        /*!< 0x00000800 */
+#define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                  /*!< 10-bit addressing mode (master mode)                    */
+#define I2C_CR2_HEAD10R_Pos                 (12U)                              
+#define I2C_CR2_HEAD10R_Msk                 (0x1U << I2C_CR2_HEAD10R_Pos)      /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos                   (13U)                              
+#define I2C_CR2_START_Msk                   (0x1U << I2C_CR2_START_Pos)        /*!< 0x00002000 */
+#define I2C_CR2_START                       I2C_CR2_START_Msk                  /*!< START generation                                        */
+#define I2C_CR2_STOP_Pos                    (14U)                              
+#define I2C_CR2_STOP_Msk                    (0x1U << I2C_CR2_STOP_Pos)         /*!< 0x00004000 */
+#define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                   /*!< STOP generation (master mode)                           */
+#define I2C_CR2_NACK_Pos                    (15U)                              
+#define I2C_CR2_NACK_Msk                    (0x1U << I2C_CR2_NACK_Pos)         /*!< 0x00008000 */
+#define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                   /*!< NACK generation (slave mode)                            */
+#define I2C_CR2_NBYTES_Pos                  (16U)                              
+#define I2C_CR2_NBYTES_Msk                  (0xFFU << I2C_CR2_NBYTES_Pos)      /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                 /*!< Number of bytes                                         */
+#define I2C_CR2_RELOAD_Pos                  (24U)                              
+#define I2C_CR2_RELOAD_Msk                  (0x1U << I2C_CR2_RELOAD_Pos)       /*!< 0x01000000 */
+#define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                 /*!< NBYTES reload mode                                      */
+#define I2C_CR2_AUTOEND_Pos                 (25U)                              
+#define I2C_CR2_AUTOEND_Msk                 (0x1U << I2C_CR2_AUTOEND_Pos)      /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                /*!< Automatic end mode (master mode)                        */
+#define I2C_CR2_PECBYTE_Pos                 (26U)                              
+#define I2C_CR2_PECBYTE_Msk                 (0x1U << I2C_CR2_PECBYTE_Pos)      /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE                     I2C_CR2_PECBYTE_Msk                /*!< Packet error checking byte                              */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos                    (0U)                               
+#define I2C_OAR1_OA1_Msk                    (0x3FFU << I2C_OAR1_OA1_Pos)       /*!< 0x000003FF */
+#define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                   /*!< Interface own address 1   */
+#define I2C_OAR1_OA1MODE_Pos                (10U)                              
+#define I2C_OAR1_OA1MODE_Msk                (0x1U << I2C_OAR1_OA1MODE_Pos)     /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk               /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos                  (15U)                              
+#define I2C_OAR1_OA1EN_Msk                  (0x1U << I2C_OAR1_OA1EN_Pos)       /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                 /*!< Own address 1 enable      */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos                    (1U)                               
+#define I2C_OAR2_OA2_Msk                    (0x7FU << I2C_OAR2_OA2_Pos)        /*!< 0x000000FE */
+#define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                   /*!< Interface own address 2                        */
+#define I2C_OAR2_OA2MSK_Pos                 (8U)                               
+#define I2C_OAR2_OA2MSK_Msk                 (0x7U << I2C_OAR2_OA2MSK_Pos)      /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                /*!< Own address 2 masks                            */
+#define I2C_OAR2_OA2NOMASK                  (0x00000000U)                      /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos              (8U)                               
+#define I2C_OAR2_OA2MASK01_Msk              (0x1U << I2C_OAR2_OA2MASK01_Pos)   /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk             /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos              (9U)                               
+#define I2C_OAR2_OA2MASK02_Msk              (0x1U << I2C_OAR2_OA2MASK02_Pos)   /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk             /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos              (8U)                               
+#define I2C_OAR2_OA2MASK03_Msk              (0x3U << I2C_OAR2_OA2MASK03_Pos)   /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk             /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos              (10U)                              
+#define I2C_OAR2_OA2MASK04_Msk              (0x1U << I2C_OAR2_OA2MASK04_Pos)   /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk             /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos              (8U)                               
+#define I2C_OAR2_OA2MASK05_Msk              (0x5U << I2C_OAR2_OA2MASK05_Pos)   /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk             /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos              (9U)                               
+#define I2C_OAR2_OA2MASK06_Msk              (0x3U << I2C_OAR2_OA2MASK06_Pos)   /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk             /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos              (8U)                               
+#define I2C_OAR2_OA2MASK07_Msk              (0x7U << I2C_OAR2_OA2MASK07_Pos)   /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk             /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos                  (15U)                              
+#define I2C_OAR2_OA2EN_Msk                  (0x1U << I2C_OAR2_OA2EN_Pos)       /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                 /*!< Own address 2 enable                           */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos                (0U)                               
+#define I2C_TIMINGR_SCLL_Msk                (0xFFU << I2C_TIMINGR_SCLL_Pos)    /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk               /*!< SCL low period (master mode)  */
+#define I2C_TIMINGR_SCLH_Pos                (8U)                               
+#define I2C_TIMINGR_SCLH_Msk                (0xFFU << I2C_TIMINGR_SCLH_Pos)    /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk               /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos              (16U)                              
+#define I2C_TIMINGR_SDADEL_Msk              (0xFU << I2C_TIMINGR_SDADEL_Pos)   /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk             /*!< Data hold time                */
+#define I2C_TIMINGR_SCLDEL_Pos              (20U)                              
+#define I2C_TIMINGR_SCLDEL_Msk              (0xFU << I2C_TIMINGR_SCLDEL_Pos)   /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk             /*!< Data setup time               */
+#define I2C_TIMINGR_PRESC_Pos               (28U)                              
+#define I2C_TIMINGR_PRESC_Msk               (0xFU << I2C_TIMINGR_PRESC_Pos)    /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk              /*!< Timings prescaler             */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos           (0U)                               
+#define I2C_TIMEOUTR_TIMEOUTA_Msk           (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA               I2C_TIMEOUTR_TIMEOUTA_Msk          /*!< Bus timeout A                 */
+#define I2C_TIMEOUTR_TIDLE_Pos              (12U)                              
+#define I2C_TIMEOUTR_TIDLE_Msk              (0x1U << I2C_TIMEOUTR_TIDLE_Pos)   /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE                  I2C_TIMEOUTR_TIDLE_Msk             /*!< Idle clock timeout detection  */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos           (15U)                              
+#define I2C_TIMEOUTR_TIMOUTEN_Msk           (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN               I2C_TIMEOUTR_TIMOUTEN_Msk          /*!< Clock timeout enable          */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos           (16U)                              
+#define I2C_TIMEOUTR_TIMEOUTB_Msk           (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB               I2C_TIMEOUTR_TIMEOUTB_Msk          /*!< Bus timeout B                 */
+#define I2C_TIMEOUTR_TEXTEN_Pos             (31U)                              
+#define I2C_TIMEOUTR_TEXTEN_Msk             (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)  /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN                 I2C_TIMEOUTR_TEXTEN_Msk            /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos                     (0U)                               
+#define I2C_ISR_TXE_Msk                     (0x1U << I2C_ISR_TXE_Pos)          /*!< 0x00000001 */
+#define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                    /*!< Transmit data register empty    */
+#define I2C_ISR_TXIS_Pos                    (1U)                               
+#define I2C_ISR_TXIS_Msk                    (0x1U << I2C_ISR_TXIS_Pos)         /*!< 0x00000002 */
+#define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                   /*!< Transmit interrupt status       */
+#define I2C_ISR_RXNE_Pos                    (2U)                               
+#define I2C_ISR_RXNE_Msk                    (0x1U << I2C_ISR_RXNE_Pos)         /*!< 0x00000004 */
+#define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                   /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos                    (3U)                               
+#define I2C_ISR_ADDR_Msk                    (0x1U << I2C_ISR_ADDR_Pos)         /*!< 0x00000008 */
+#define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                   /*!< Address matched (slave mode)    */
+#define I2C_ISR_NACKF_Pos                   (4U)                               
+#define I2C_ISR_NACKF_Msk                   (0x1U << I2C_ISR_NACKF_Pos)        /*!< 0x00000010 */
+#define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                  /*!< NACK received flag              */
+#define I2C_ISR_STOPF_Pos                   (5U)                               
+#define I2C_ISR_STOPF_Msk                   (0x1U << I2C_ISR_STOPF_Pos)        /*!< 0x00000020 */
+#define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                  /*!< STOP detection flag             */
+#define I2C_ISR_TC_Pos                      (6U)                               
+#define I2C_ISR_TC_Msk                      (0x1U << I2C_ISR_TC_Pos)           /*!< 0x00000040 */
+#define I2C_ISR_TC                          I2C_ISR_TC_Msk                     /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos                     (7U)                               
+#define I2C_ISR_TCR_Msk                     (0x1U << I2C_ISR_TCR_Pos)          /*!< 0x00000080 */
+#define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                    /*!< Transfer complete reload        */
+#define I2C_ISR_BERR_Pos                    (8U)                               
+#define I2C_ISR_BERR_Msk                    (0x1U << I2C_ISR_BERR_Pos)         /*!< 0x00000100 */
+#define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                   /*!< Bus error                       */
+#define I2C_ISR_ARLO_Pos                    (9U)                               
+#define I2C_ISR_ARLO_Msk                    (0x1U << I2C_ISR_ARLO_Pos)         /*!< 0x00000200 */
+#define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                   /*!< Arbitration lost                */
+#define I2C_ISR_OVR_Pos                     (10U)                              
+#define I2C_ISR_OVR_Msk                     (0x1U << I2C_ISR_OVR_Pos)          /*!< 0x00000400 */
+#define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                    /*!< Overrun/Underrun                */
+#define I2C_ISR_PECERR_Pos                  (11U)                              
+#define I2C_ISR_PECERR_Msk                  (0x1U << I2C_ISR_PECERR_Pos)       /*!< 0x00000800 */
+#define I2C_ISR_PECERR                      I2C_ISR_PECERR_Msk                 /*!< PEC error in reception          */
+#define I2C_ISR_TIMEOUT_Pos                 (12U)                              
+#define I2C_ISR_TIMEOUT_Msk                 (0x1U << I2C_ISR_TIMEOUT_Pos)      /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT                     I2C_ISR_TIMEOUT_Msk                /*!< Timeout or Tlow detection flag  */
+#define I2C_ISR_ALERT_Pos                   (13U)                              
+#define I2C_ISR_ALERT_Msk                   (0x1U << I2C_ISR_ALERT_Pos)        /*!< 0x00002000 */
+#define I2C_ISR_ALERT                       I2C_ISR_ALERT_Msk                  /*!< SMBus alert                     */
+#define I2C_ISR_BUSY_Pos                    (15U)                              
+#define I2C_ISR_BUSY_Msk                    (0x1U << I2C_ISR_BUSY_Pos)         /*!< 0x00008000 */
+#define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                   /*!< Bus busy                        */
+#define I2C_ISR_DIR_Pos                     (16U)                              
+#define I2C_ISR_DIR_Msk                     (0x1U << I2C_ISR_DIR_Pos)          /*!< 0x00010000 */
+#define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                    /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos                 (17U)                              
+#define I2C_ISR_ADDCODE_Msk                 (0x7FU << I2C_ISR_ADDCODE_Pos)     /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos                  (3U)                               
+#define I2C_ICR_ADDRCF_Msk                  (0x1U << I2C_ICR_ADDRCF_Pos)       /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                 /*!< Address matched clear flag  */
+#define I2C_ICR_NACKCF_Pos                  (4U)                               
+#define I2C_ICR_NACKCF_Msk                  (0x1U << I2C_ICR_NACKCF_Pos)       /*!< 0x00000010 */
+#define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                 /*!< NACK clear flag             */
+#define I2C_ICR_STOPCF_Pos                  (5U)                               
+#define I2C_ICR_STOPCF_Msk                  (0x1U << I2C_ICR_STOPCF_Pos)       /*!< 0x00000020 */
+#define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                 /*!< STOP detection clear flag   */
+#define I2C_ICR_BERRCF_Pos                  (8U)                               
+#define I2C_ICR_BERRCF_Msk                  (0x1U << I2C_ICR_BERRCF_Pos)       /*!< 0x00000100 */
+#define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                 /*!< Bus error clear flag        */
+#define I2C_ICR_ARLOCF_Pos                  (9U)                               
+#define I2C_ICR_ARLOCF_Msk                  (0x1U << I2C_ICR_ARLOCF_Pos)       /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                 /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos                   (10U)                              
+#define I2C_ICR_OVRCF_Msk                   (0x1U << I2C_ICR_OVRCF_Pos)        /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                  /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos                   (11U)                              
+#define I2C_ICR_PECCF_Msk                   (0x1U << I2C_ICR_PECCF_Pos)        /*!< 0x00000800 */
+#define I2C_ICR_PECCF                       I2C_ICR_PECCF_Msk                  /*!< PAC error clear flag        */
+#define I2C_ICR_TIMOUTCF_Pos                (12U)                              
+#define I2C_ICR_TIMOUTCF_Msk                (0x1U << I2C_ICR_TIMOUTCF_Pos)     /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF                    I2C_ICR_TIMOUTCF_Msk               /*!< Timeout clear flag          */
+#define I2C_ICR_ALERTCF_Pos                 (13U)                              
+#define I2C_ICR_ALERTCF_Msk                 (0x1U << I2C_ICR_ALERTCF_Pos)      /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF                     I2C_ICR_ALERTCF_Msk                /*!< Alert clear flag            */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos                    (0U)                               
+#define I2C_PECR_PEC_Msk                    (0xFFU << I2C_PECR_PEC_Pos)        /*!< 0x000000FF */
+#define I2C_PECR_PEC                        I2C_PECR_PEC_Msk                   /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos                 (0U)                               
+#define I2C_RXDR_RXDATA_Msk                 (0xFFU << I2C_RXDR_RXDATA_Pos)     /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos                 (0U)                               
+#define I2C_TXDR_TXDATA_Msk                 (0xFFU << I2C_TXDR_TXDATA_Pos)     /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos                     (0U)                               
+#define IWDG_KR_KEY_Msk                     (0xFFFFU << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
+#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos                      (0U)                               
+#define IWDG_PR_PR_Msk                      (0x7U << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
+#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0                        (0x1U << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
+#define IWDG_PR_PR_1                        (0x2U << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
+#define IWDG_PR_PR_2                        (0x4U << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos                     (0U)                               
+#define IWDG_RLR_RL_Msk                     (0xFFFU << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
+#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos                     (0U)                               
+#define IWDG_SR_PVU_Msk                     (0x1U << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
+#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos                     (1U)                               
+#define IWDG_SR_RVU_Msk                     (0x1U << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
+#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos                     (2U)                               
+#define IWDG_SR_WVU_Msk                     (0x1U << IWDG_SR_WVU_Pos)          /*!< 0x00000004 */
+#define IWDG_SR_WVU                         IWDG_SR_WVU_Msk                    /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos                   (0U)                               
+#define IWDG_WINR_WIN_Msk                   (0xFFFU << IWDG_WINR_WIN_Pos)      /*!< 0x00000FFF */
+#define IWDG_WINR_WIN                       IWDG_WINR_WIN_Msk                  /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                     Firewall                               */
+/*                                                                            */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL;LSSA;LSL register */
+#define FW_CSSA_ADD_Pos               (8U)                                     
+#define FW_CSSA_ADD_Msk               (0xFFFFU << FW_CSSA_ADD_Pos)             /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD                   FW_CSSA_ADD_Msk                          /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos               (8U)                                     
+#define FW_CSL_LENG_Msk               (0x3FFFU << FW_CSL_LENG_Pos)             /*!< 0x003FFF00 */
+#define FW_CSL_LENG                   FW_CSL_LENG_Msk                          /*!< Code Segment Length        */
+#define FW_NVDSSA_ADD_Pos             (8U)                                     
+#define FW_NVDSSA_ADD_Msk             (0xFFFFU << FW_NVDSSA_ADD_Pos)           /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD                 FW_NVDSSA_ADD_Msk                        /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos             (8U)                                     
+#define FW_NVDSL_LENG_Msk             (0x3FFFU << FW_NVDSL_LENG_Pos)           /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG                 FW_NVDSL_LENG_Msk                        /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos              (6U)                                     
+#define FW_VDSSA_ADD_Msk              (0x7FFU << FW_VDSSA_ADD_Pos)             /*!< 0x0001FFC0 */
+#define FW_VDSSA_ADD                  FW_VDSSA_ADD_Msk                         /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos              (6U)                                     
+#define FW_VDSL_LENG_Msk              (0x7FFU << FW_VDSL_LENG_Pos)             /*!< 0x0001FFC0 */
+#define FW_VDSL_LENG                  FW_VDSL_LENG_Msk                         /*!< Volatile Data Segment Length */
+#define FW_LSSA_ADD_Pos               (7U)                                     
+#define FW_LSSA_ADD_Msk               (0xFFFU << FW_LSSA_ADD_Pos)              /*!< 0x0007FF80 */
+#define FW_LSSA_ADD                   FW_LSSA_ADD_Msk                          /*!< Library Segment Start Address*/
+#define FW_LSL_LENG_Pos               (7U)                                     
+#define FW_LSL_LENG_Msk               (0xFFFU << FW_LSL_LENG_Pos)              /*!< 0x0007FF80 */
+#define FW_LSL_LENG                   FW_LSL_LENG_Msk                          /*!< Library Segment Length*/
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos                 (0U)                                     
+#define FW_CR_FPA_Msk                 (0x1U << FW_CR_FPA_Pos)                  /*!< 0x00000001 */
+#define FW_CR_FPA                     FW_CR_FPA_Msk                            /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos                 (1U)                                     
+#define FW_CR_VDS_Msk                 (0x1U << FW_CR_VDS_Pos)                  /*!< 0x00000002 */
+#define FW_CR_VDS                     FW_CR_VDS_Msk                            /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos                 (2U)                                     
+#define FW_CR_VDE_Msk                 (0x1U << FW_CR_VDE_Pos)                  /*!< 0x00000004 */
+#define FW_CR_VDE                     FW_CR_VDE_Msk                            /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR1 register  ********************/
+
+#define PWR_CR1_LPR_Pos                     (14U)                              
+#define PWR_CR1_LPR_Msk                     (0x1U << PWR_CR1_LPR_Pos)          /*!< 0x00004000 */
+#define PWR_CR1_LPR                         PWR_CR1_LPR_Msk                    /*!< Regulator low-power mode */
+#define PWR_CR1_VOS_Pos                     (9U)                               
+#define PWR_CR1_VOS_Msk                     (0x3U << PWR_CR1_VOS_Pos)          /*!< 0x00000600 */
+#define PWR_CR1_VOS                         PWR_CR1_VOS_Msk                    /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR1_VOS_0                       (0x1U << PWR_CR1_VOS_Pos)          /*!< 0x00000200 */
+#define PWR_CR1_VOS_1                       (0x2U << PWR_CR1_VOS_Pos)          /*!< 0x00000400 */
+#define PWR_CR1_DBP_Pos                     (8U)                               
+#define PWR_CR1_DBP_Msk                     (0x1U << PWR_CR1_DBP_Pos)          /*!< 0x00000100 */
+#define PWR_CR1_DBP                         PWR_CR1_DBP_Msk                    /*!< Disable Back-up domain Protection */
+#define PWR_CR1_LPMS_Pos                    (0U)                               
+#define PWR_CR1_LPMS_Msk                    (0x7U << PWR_CR1_LPMS_Pos)         /*!< 0x00000007 */
+#define PWR_CR1_LPMS                        PWR_CR1_LPMS_Msk                   /*!< Low-power mode selection field */
+#define PWR_CR1_LPMS_STOP0                  (0x00000000U)                      /*!< Stop 0 mode */
+#define PWR_CR1_LPMS_STOP1_Pos              (0U)                               
+#define PWR_CR1_LPMS_STOP1_Msk              (0x1U << PWR_CR1_LPMS_STOP1_Pos)   /*!< 0x00000001 */
+#define PWR_CR1_LPMS_STOP1                  PWR_CR1_LPMS_STOP1_Msk             /*!< Stop 1 mode */
+#define PWR_CR1_LPMS_STOP2_Pos              (1U)                               
+#define PWR_CR1_LPMS_STOP2_Msk              (0x1U << PWR_CR1_LPMS_STOP2_Pos)   /*!< 0x00000002 */
+#define PWR_CR1_LPMS_STOP2                  PWR_CR1_LPMS_STOP2_Msk             /*!< Stop 2 mode */
+#define PWR_CR1_LPMS_STANDBY_Pos            (0U)                               
+#define PWR_CR1_LPMS_STANDBY_Msk            (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
+#define PWR_CR1_LPMS_STANDBY                PWR_CR1_LPMS_STANDBY_Msk           /*!< Stand-by mode */
+#define PWR_CR1_LPMS_SHUTDOWN_Pos           (2U)                               
+#define PWR_CR1_LPMS_SHUTDOWN_Msk           (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
+#define PWR_CR1_LPMS_SHUTDOWN               PWR_CR1_LPMS_SHUTDOWN_Msk          /*!< Shut-down mode */
+
+
+/********************  Bit definition for PWR_CR2 register  ********************/
+#define PWR_CR2_USV_Pos                     (10U)                              
+#define PWR_CR2_USV_Msk                     (0x1U << PWR_CR2_USV_Pos)          /*!< 0x00000400 */
+#define PWR_CR2_USV                         PWR_CR2_USV_Msk                    /*!< VDD USB Supply Valid */
+#define PWR_CR2_IOSV_Pos                    (9U)                               
+#define PWR_CR2_IOSV_Msk                    (0x1U << PWR_CR2_IOSV_Pos)         /*!< 0x00000200 */
+#define PWR_CR2_IOSV                        PWR_CR2_IOSV_Msk                   /*!< VDD IO2 independent I/Os Supply Valid */
+/*!< PVME  Peripheral Voltage Monitor Enable */
+#define PWR_CR2_PVME_Pos                    (4U)                               
+#define PWR_CR2_PVME_Msk                    (0xFU << PWR_CR2_PVME_Pos)         /*!< 0x000000F0 */
+#define PWR_CR2_PVME                        PWR_CR2_PVME_Msk                   /*!< PVM bits field */
+#define PWR_CR2_PVME4_Pos                   (7U)                               
+#define PWR_CR2_PVME4_Msk                   (0x1U << PWR_CR2_PVME4_Pos)        /*!< 0x00000080 */
+#define PWR_CR2_PVME4                       PWR_CR2_PVME4_Msk                  /*!< PVM 4 Enable */
+#define PWR_CR2_PVME3_Pos                   (6U)                               
+#define PWR_CR2_PVME3_Msk                   (0x1U << PWR_CR2_PVME3_Pos)        /*!< 0x00000040 */
+#define PWR_CR2_PVME3                       PWR_CR2_PVME3_Msk                  /*!< PVM 3 Enable */
+#define PWR_CR2_PVME2_Pos                   (5U)                               
+#define PWR_CR2_PVME2_Msk                   (0x1U << PWR_CR2_PVME2_Pos)        /*!< 0x00000020 */
+#define PWR_CR2_PVME2                       PWR_CR2_PVME2_Msk                  /*!< PVM 2 Enable */
+#define PWR_CR2_PVME1_Pos                   (4U)                               
+#define PWR_CR2_PVME1_Msk                   (0x1U << PWR_CR2_PVME1_Pos)        /*!< 0x00000010 */
+#define PWR_CR2_PVME1                       PWR_CR2_PVME1_Msk                  /*!< PVM 1 Enable */
+/*!< PVD level configuration */
+#define PWR_CR2_PLS_Pos                     (1U)                               
+#define PWR_CR2_PLS_Msk                     (0x7U << PWR_CR2_PLS_Pos)          /*!< 0x0000000E */
+#define PWR_CR2_PLS                         PWR_CR2_PLS_Msk                    /*!< PVD level selection */
+#define PWR_CR2_PLS_LEV0                    (0x00000000U)                      /*!< PVD level 0 */
+#define PWR_CR2_PLS_LEV1_Pos                (1U)                               
+#define PWR_CR2_PLS_LEV1_Msk                (0x1U << PWR_CR2_PLS_LEV1_Pos)     /*!< 0x00000002 */
+#define PWR_CR2_PLS_LEV1                    PWR_CR2_PLS_LEV1_Msk               /*!< PVD level 1 */
+#define PWR_CR2_PLS_LEV2_Pos                (2U)                               
+#define PWR_CR2_PLS_LEV2_Msk                (0x1U << PWR_CR2_PLS_LEV2_Pos)     /*!< 0x00000004 */
+#define PWR_CR2_PLS_LEV2                    PWR_CR2_PLS_LEV2_Msk               /*!< PVD level 2 */
+#define PWR_CR2_PLS_LEV3_Pos                (1U)                               
+#define PWR_CR2_PLS_LEV3_Msk                (0x3U << PWR_CR2_PLS_LEV3_Pos)     /*!< 0x00000006 */
+#define PWR_CR2_PLS_LEV3                    PWR_CR2_PLS_LEV3_Msk               /*!< PVD level 3 */
+#define PWR_CR2_PLS_LEV4_Pos                (3U)                               
+#define PWR_CR2_PLS_LEV4_Msk                (0x1U << PWR_CR2_PLS_LEV4_Pos)     /*!< 0x00000008 */
+#define PWR_CR2_PLS_LEV4                    PWR_CR2_PLS_LEV4_Msk               /*!< PVD level 4 */
+#define PWR_CR2_PLS_LEV5_Pos                (1U)                               
+#define PWR_CR2_PLS_LEV5_Msk                (0x5U << PWR_CR2_PLS_LEV5_Pos)     /*!< 0x0000000A */
+#define PWR_CR2_PLS_LEV5                    PWR_CR2_PLS_LEV5_Msk               /*!< PVD level 5 */
+#define PWR_CR2_PLS_LEV6_Pos                (2U)                               
+#define PWR_CR2_PLS_LEV6_Msk                (0x3U << PWR_CR2_PLS_LEV6_Pos)     /*!< 0x0000000C */
+#define PWR_CR2_PLS_LEV6                    PWR_CR2_PLS_LEV6_Msk               /*!< PVD level 6 */
+#define PWR_CR2_PLS_LEV7_Pos                (1U)                               
+#define PWR_CR2_PLS_LEV7_Msk                (0x7U << PWR_CR2_PLS_LEV7_Pos)     /*!< 0x0000000E */
+#define PWR_CR2_PLS_LEV7                    PWR_CR2_PLS_LEV7_Msk               /*!< PVD level 7 */
+#define PWR_CR2_PVDE_Pos                    (0U)                               
+#define PWR_CR2_PVDE_Msk                    (0x1U << PWR_CR2_PVDE_Pos)         /*!< 0x00000001 */
+#define PWR_CR2_PVDE                        PWR_CR2_PVDE_Msk                   /*!< Power Voltage Detector Enable */
+
+/********************  Bit definition for PWR_CR3 register  ********************/
+#define PWR_CR3_EIWF_Pos                    (15U)                              
+#define PWR_CR3_EIWF_Msk                    (0x1U << PWR_CR3_EIWF_Pos)         /*!< 0x00008000 */
+#define PWR_CR3_EIWF                        PWR_CR3_EIWF_Msk                   /*!< Enable Internal Wake-up line */
+#define PWR_CR3_APC_Pos                     (10U)                              
+#define PWR_CR3_APC_Msk                     (0x1U << PWR_CR3_APC_Pos)          /*!< 0x00000400 */
+#define PWR_CR3_APC                         PWR_CR3_APC_Msk                    /*!< Apply pull-up and pull-down configuration */
+#define PWR_CR3_RRS_Pos                     (8U)                               
+#define PWR_CR3_RRS_Msk                     (0x1U << PWR_CR3_RRS_Pos)          /*!< 0x00000100 */
+#define PWR_CR3_RRS                         PWR_CR3_RRS_Msk                    /*!< SRAM2 Retention in Stand-by mode */
+#define PWR_CR3_EWUP5_Pos                   (4U)                               
+#define PWR_CR3_EWUP5_Msk                   (0x1U << PWR_CR3_EWUP5_Pos)        /*!< 0x00000010 */
+#define PWR_CR3_EWUP5                       PWR_CR3_EWUP5_Msk                  /*!< Enable Wake-Up Pin 5 */
+#define PWR_CR3_EWUP4_Pos                   (3U)                               
+#define PWR_CR3_EWUP4_Msk                   (0x1U << PWR_CR3_EWUP4_Pos)        /*!< 0x00000008 */
+#define PWR_CR3_EWUP4                       PWR_CR3_EWUP4_Msk                  /*!< Enable Wake-Up Pin 4 */
+#define PWR_CR3_EWUP3_Pos                   (2U)                               
+#define PWR_CR3_EWUP3_Msk                   (0x1U << PWR_CR3_EWUP3_Pos)        /*!< 0x00000004 */
+#define PWR_CR3_EWUP3                       PWR_CR3_EWUP3_Msk                  /*!< Enable Wake-Up Pin 3 */
+#define PWR_CR3_EWUP2_Pos                   (1U)                               
+#define PWR_CR3_EWUP2_Msk                   (0x1U << PWR_CR3_EWUP2_Pos)        /*!< 0x00000002 */
+#define PWR_CR3_EWUP2                       PWR_CR3_EWUP2_Msk                  /*!< Enable Wake-Up Pin 2 */
+#define PWR_CR3_EWUP1_Pos                   (0U)                               
+#define PWR_CR3_EWUP1_Msk                   (0x1U << PWR_CR3_EWUP1_Pos)        /*!< 0x00000001 */
+#define PWR_CR3_EWUP1                       PWR_CR3_EWUP1_Msk                  /*!< Enable Wake-Up Pin 1 */
+#define PWR_CR3_EWUP_Pos                    (0U)                               
+#define PWR_CR3_EWUP_Msk                    (0x1FU << PWR_CR3_EWUP_Pos)        /*!< 0x0000001F */
+#define PWR_CR3_EWUP                        PWR_CR3_EWUP_Msk                   /*!< Enable Wake-Up Pins  */
+
+/********************  Bit definition for PWR_CR4 register  ********************/
+#define PWR_CR4_VBRS_Pos                    (9U)                               
+#define PWR_CR4_VBRS_Msk                    (0x1U << PWR_CR4_VBRS_Pos)         /*!< 0x00000200 */
+#define PWR_CR4_VBRS                        PWR_CR4_VBRS_Msk                   /*!< VBAT Battery charging Resistor Selection */
+#define PWR_CR4_VBE_Pos                     (8U)                               
+#define PWR_CR4_VBE_Msk                     (0x1U << PWR_CR4_VBE_Pos)          /*!< 0x00000100 */
+#define PWR_CR4_VBE                         PWR_CR4_VBE_Msk                    /*!< VBAT Battery charging Enable  */
+#define PWR_CR4_WP5_Pos                     (4U)                               
+#define PWR_CR4_WP5_Msk                     (0x1U << PWR_CR4_WP5_Pos)          /*!< 0x00000010 */
+#define PWR_CR4_WP5                         PWR_CR4_WP5_Msk                    /*!< Wake-Up Pin 5 polarity */
+#define PWR_CR4_WP4_Pos                     (3U)                               
+#define PWR_CR4_WP4_Msk                     (0x1U << PWR_CR4_WP4_Pos)          /*!< 0x00000008 */
+#define PWR_CR4_WP4                         PWR_CR4_WP4_Msk                    /*!< Wake-Up Pin 4 polarity */
+#define PWR_CR4_WP3_Pos                     (2U)                               
+#define PWR_CR4_WP3_Msk                     (0x1U << PWR_CR4_WP3_Pos)          /*!< 0x00000004 */
+#define PWR_CR4_WP3                         PWR_CR4_WP3_Msk                    /*!< Wake-Up Pin 3 polarity */
+#define PWR_CR4_WP2_Pos                     (1U)                               
+#define PWR_CR4_WP2_Msk                     (0x1U << PWR_CR4_WP2_Pos)          /*!< 0x00000002 */
+#define PWR_CR4_WP2                         PWR_CR4_WP2_Msk                    /*!< Wake-Up Pin 2 polarity */
+#define PWR_CR4_WP1_Pos                     (0U)                               
+#define PWR_CR4_WP1_Msk                     (0x1U << PWR_CR4_WP1_Pos)          /*!< 0x00000001 */
+#define PWR_CR4_WP1                         PWR_CR4_WP1_Msk                    /*!< Wake-Up Pin 1 polarity */
+
+/********************  Bit definition for PWR_SR1 register  ********************/
+#define PWR_SR1_WUFI_Pos                    (15U)                              
+#define PWR_SR1_WUFI_Msk                    (0x1U << PWR_SR1_WUFI_Pos)         /*!< 0x00008000 */
+#define PWR_SR1_WUFI                        PWR_SR1_WUFI_Msk                   /*!< Wake-Up Flag Internal */
+#define PWR_SR1_SBF_Pos                     (8U)                               
+#define PWR_SR1_SBF_Msk                     (0x1U << PWR_SR1_SBF_Pos)          /*!< 0x00000100 */
+#define PWR_SR1_SBF                         PWR_SR1_SBF_Msk                    /*!< Stand-By Flag */
+#define PWR_SR1_WUF_Pos                     (0U)                               
+#define PWR_SR1_WUF_Msk                     (0x1FU << PWR_SR1_WUF_Pos)         /*!< 0x0000001F */
+#define PWR_SR1_WUF                         PWR_SR1_WUF_Msk                    /*!< Wake-up Flags */
+#define PWR_SR1_WUF5_Pos                    (4U)                               
+#define PWR_SR1_WUF5_Msk                    (0x1U << PWR_SR1_WUF5_Pos)         /*!< 0x00000010 */
+#define PWR_SR1_WUF5                        PWR_SR1_WUF5_Msk                   /*!< Wake-up Flag 5 */
+#define PWR_SR1_WUF4_Pos                    (3U)                               
+#define PWR_SR1_WUF4_Msk                    (0x1U << PWR_SR1_WUF4_Pos)         /*!< 0x00000008 */
+#define PWR_SR1_WUF4                        PWR_SR1_WUF4_Msk                   /*!< Wake-up Flag 4 */
+#define PWR_SR1_WUF3_Pos                    (2U)                               
+#define PWR_SR1_WUF3_Msk                    (0x1U << PWR_SR1_WUF3_Pos)         /*!< 0x00000004 */
+#define PWR_SR1_WUF3                        PWR_SR1_WUF3_Msk                   /*!< Wake-up Flag 3 */
+#define PWR_SR1_WUF2_Pos                    (1U)                               
+#define PWR_SR1_WUF2_Msk                    (0x1U << PWR_SR1_WUF2_Pos)         /*!< 0x00000002 */
+#define PWR_SR1_WUF2                        PWR_SR1_WUF2_Msk                   /*!< Wake-up Flag 2 */
+#define PWR_SR1_WUF1_Pos                    (0U)                               
+#define PWR_SR1_WUF1_Msk                    (0x1U << PWR_SR1_WUF1_Pos)         /*!< 0x00000001 */
+#define PWR_SR1_WUF1                        PWR_SR1_WUF1_Msk                   /*!< Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_SR2 register  ********************/
+#define PWR_SR2_PVMO4_Pos                   (15U)                              
+#define PWR_SR2_PVMO4_Msk                   (0x1U << PWR_SR2_PVMO4_Pos)        /*!< 0x00008000 */
+#define PWR_SR2_PVMO4                       PWR_SR2_PVMO4_Msk                  /*!< Peripheral Voltage Monitoring Output 4 */
+#define PWR_SR2_PVMO3_Pos                   (14U)                              
+#define PWR_SR2_PVMO3_Msk                   (0x1U << PWR_SR2_PVMO3_Pos)        /*!< 0x00004000 */
+#define PWR_SR2_PVMO3                       PWR_SR2_PVMO3_Msk                  /*!< Peripheral Voltage Monitoring Output 3 */
+#define PWR_SR2_PVMO2_Pos                   (13U)                              
+#define PWR_SR2_PVMO2_Msk                   (0x1U << PWR_SR2_PVMO2_Pos)        /*!< 0x00002000 */
+#define PWR_SR2_PVMO2                       PWR_SR2_PVMO2_Msk                  /*!< Peripheral Voltage Monitoring Output 2 */
+#define PWR_SR2_PVMO1_Pos                   (12U)                              
+#define PWR_SR2_PVMO1_Msk                   (0x1U << PWR_SR2_PVMO1_Pos)        /*!< 0x00001000 */
+#define PWR_SR2_PVMO1                       PWR_SR2_PVMO1_Msk                  /*!< Peripheral Voltage Monitoring Output 1 */
+#define PWR_SR2_PVDO_Pos                    (11U)                              
+#define PWR_SR2_PVDO_Msk                    (0x1U << PWR_SR2_PVDO_Pos)         /*!< 0x00000800 */
+#define PWR_SR2_PVDO                        PWR_SR2_PVDO_Msk                   /*!< Power Voltage Detector Output */
+#define PWR_SR2_VOSF_Pos                    (10U)                              
+#define PWR_SR2_VOSF_Msk                    (0x1U << PWR_SR2_VOSF_Pos)         /*!< 0x00000400 */
+#define PWR_SR2_VOSF                        PWR_SR2_VOSF_Msk                   /*!< Voltage Scaling Flag */
+#define PWR_SR2_REGLPF_Pos                  (9U)                               
+#define PWR_SR2_REGLPF_Msk                  (0x1U << PWR_SR2_REGLPF_Pos)       /*!< 0x00000200 */
+#define PWR_SR2_REGLPF                      PWR_SR2_REGLPF_Msk                 /*!< Low-power Regulator Flag */
+#define PWR_SR2_REGLPS_Pos                  (8U)                               
+#define PWR_SR2_REGLPS_Msk                  (0x1U << PWR_SR2_REGLPS_Pos)       /*!< 0x00000100 */
+#define PWR_SR2_REGLPS                      PWR_SR2_REGLPS_Msk                 /*!< Low-power Regulator Started */
+
+/********************  Bit definition for PWR_SCR register  ********************/
+#define PWR_SCR_CSBF_Pos                    (8U)                               
+#define PWR_SCR_CSBF_Msk                    (0x1U << PWR_SCR_CSBF_Pos)         /*!< 0x00000100 */
+#define PWR_SCR_CSBF                        PWR_SCR_CSBF_Msk                   /*!< Clear Stand-By Flag */
+#define PWR_SCR_CWUF_Pos                    (0U)                               
+#define PWR_SCR_CWUF_Msk                    (0x1FU << PWR_SCR_CWUF_Pos)        /*!< 0x0000001F */
+#define PWR_SCR_CWUF                        PWR_SCR_CWUF_Msk                   /*!< Clear Wake-up Flags  */
+#define PWR_SCR_CWUF5_Pos                   (4U)                               
+#define PWR_SCR_CWUF5_Msk                   (0x1U << PWR_SCR_CWUF5_Pos)        /*!< 0x00000010 */
+#define PWR_SCR_CWUF5                       PWR_SCR_CWUF5_Msk                  /*!< Clear Wake-up Flag 5 */
+#define PWR_SCR_CWUF4_Pos                   (3U)                               
+#define PWR_SCR_CWUF4_Msk                   (0x1U << PWR_SCR_CWUF4_Pos)        /*!< 0x00000008 */
+#define PWR_SCR_CWUF4                       PWR_SCR_CWUF4_Msk                  /*!< Clear Wake-up Flag 4 */
+#define PWR_SCR_CWUF3_Pos                   (2U)                               
+#define PWR_SCR_CWUF3_Msk                   (0x1U << PWR_SCR_CWUF3_Pos)        /*!< 0x00000004 */
+#define PWR_SCR_CWUF3                       PWR_SCR_CWUF3_Msk                  /*!< Clear Wake-up Flag 3 */
+#define PWR_SCR_CWUF2_Pos                   (1U)                               
+#define PWR_SCR_CWUF2_Msk                   (0x1U << PWR_SCR_CWUF2_Pos)        /*!< 0x00000002 */
+#define PWR_SCR_CWUF2                       PWR_SCR_CWUF2_Msk                  /*!< Clear Wake-up Flag 2 */
+#define PWR_SCR_CWUF1_Pos                   (0U)                               
+#define PWR_SCR_CWUF1_Msk                   (0x1U << PWR_SCR_CWUF1_Pos)        /*!< 0x00000001 */
+#define PWR_SCR_CWUF1                       PWR_SCR_CWUF1_Msk                  /*!< Clear Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_PUCRA register  ********************/
+#define PWR_PUCRA_PA15_Pos                  (15U)                              
+#define PWR_PUCRA_PA15_Msk                  (0x1U << PWR_PUCRA_PA15_Pos)       /*!< 0x00008000 */
+#define PWR_PUCRA_PA15                      PWR_PUCRA_PA15_Msk                 /*!< Port PA15 Pull-Up set */
+#define PWR_PUCRA_PA13_Pos                  (13U)                              
+#define PWR_PUCRA_PA13_Msk                  (0x1U << PWR_PUCRA_PA13_Pos)       /*!< 0x00002000 */
+#define PWR_PUCRA_PA13                      PWR_PUCRA_PA13_Msk                 /*!< Port PA13 Pull-Up set */
+#define PWR_PUCRA_PA12_Pos                  (12U)                              
+#define PWR_PUCRA_PA12_Msk                  (0x1U << PWR_PUCRA_PA12_Pos)       /*!< 0x00001000 */
+#define PWR_PUCRA_PA12                      PWR_PUCRA_PA12_Msk                 /*!< Port PA12 Pull-Up set */
+#define PWR_PUCRA_PA11_Pos                  (11U)                              
+#define PWR_PUCRA_PA11_Msk                  (0x1U << PWR_PUCRA_PA11_Pos)       /*!< 0x00000800 */
+#define PWR_PUCRA_PA11                      PWR_PUCRA_PA11_Msk                 /*!< Port PA11 Pull-Up set */
+#define PWR_PUCRA_PA10_Pos                  (10U)                              
+#define PWR_PUCRA_PA10_Msk                  (0x1U << PWR_PUCRA_PA10_Pos)       /*!< 0x00000400 */
+#define PWR_PUCRA_PA10                      PWR_PUCRA_PA10_Msk                 /*!< Port PA10 Pull-Up set */
+#define PWR_PUCRA_PA9_Pos                   (9U)                               
+#define PWR_PUCRA_PA9_Msk                   (0x1U << PWR_PUCRA_PA9_Pos)        /*!< 0x00000200 */
+#define PWR_PUCRA_PA9                       PWR_PUCRA_PA9_Msk                  /*!< Port PA9 Pull-Up set  */
+#define PWR_PUCRA_PA8_Pos                   (8U)                               
+#define PWR_PUCRA_PA8_Msk                   (0x1U << PWR_PUCRA_PA8_Pos)        /*!< 0x00000100 */
+#define PWR_PUCRA_PA8                       PWR_PUCRA_PA8_Msk                  /*!< Port PA8 Pull-Up set  */
+#define PWR_PUCRA_PA7_Pos                   (7U)                               
+#define PWR_PUCRA_PA7_Msk                   (0x1U << PWR_PUCRA_PA7_Pos)        /*!< 0x00000080 */
+#define PWR_PUCRA_PA7                       PWR_PUCRA_PA7_Msk                  /*!< Port PA7 Pull-Up set  */
+#define PWR_PUCRA_PA6_Pos                   (6U)                               
+#define PWR_PUCRA_PA6_Msk                   (0x1U << PWR_PUCRA_PA6_Pos)        /*!< 0x00000040 */
+#define PWR_PUCRA_PA6                       PWR_PUCRA_PA6_Msk                  /*!< Port PA6 Pull-Up set  */
+#define PWR_PUCRA_PA5_Pos                   (5U)                               
+#define PWR_PUCRA_PA5_Msk                   (0x1U << PWR_PUCRA_PA5_Pos)        /*!< 0x00000020 */
+#define PWR_PUCRA_PA5                       PWR_PUCRA_PA5_Msk                  /*!< Port PA5 Pull-Up set  */
+#define PWR_PUCRA_PA4_Pos                   (4U)                               
+#define PWR_PUCRA_PA4_Msk                   (0x1U << PWR_PUCRA_PA4_Pos)        /*!< 0x00000010 */
+#define PWR_PUCRA_PA4                       PWR_PUCRA_PA4_Msk                  /*!< Port PA4 Pull-Up set  */
+#define PWR_PUCRA_PA3_Pos                   (3U)                               
+#define PWR_PUCRA_PA3_Msk                   (0x1U << PWR_PUCRA_PA3_Pos)        /*!< 0x00000008 */
+#define PWR_PUCRA_PA3                       PWR_PUCRA_PA3_Msk                  /*!< Port PA3 Pull-Up set  */
+#define PWR_PUCRA_PA2_Pos                   (2U)                               
+#define PWR_PUCRA_PA2_Msk                   (0x1U << PWR_PUCRA_PA2_Pos)        /*!< 0x00000004 */
+#define PWR_PUCRA_PA2                       PWR_PUCRA_PA2_Msk                  /*!< Port PA2 Pull-Up set  */
+#define PWR_PUCRA_PA1_Pos                   (1U)                               
+#define PWR_PUCRA_PA1_Msk                   (0x1U << PWR_PUCRA_PA1_Pos)        /*!< 0x00000002 */
+#define PWR_PUCRA_PA1                       PWR_PUCRA_PA1_Msk                  /*!< Port PA1 Pull-Up set  */
+#define PWR_PUCRA_PA0_Pos                   (0U)                               
+#define PWR_PUCRA_PA0_Msk                   (0x1U << PWR_PUCRA_PA0_Pos)        /*!< 0x00000001 */
+#define PWR_PUCRA_PA0                       PWR_PUCRA_PA0_Msk                  /*!< Port PA0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRA register  ********************/
+#define PWR_PDCRA_PA14_Pos                  (14U)                              
+#define PWR_PDCRA_PA14_Msk                  (0x1U << PWR_PDCRA_PA14_Pos)       /*!< 0x00004000 */
+#define PWR_PDCRA_PA14                      PWR_PDCRA_PA14_Msk                 /*!< Port PA14 Pull-Down set */
+#define PWR_PDCRA_PA12_Pos                  (12U)                              
+#define PWR_PDCRA_PA12_Msk                  (0x1U << PWR_PDCRA_PA12_Pos)       /*!< 0x00001000 */
+#define PWR_PDCRA_PA12                      PWR_PDCRA_PA12_Msk                 /*!< Port PA12 Pull-Down set */
+#define PWR_PDCRA_PA11_Pos                  (11U)                              
+#define PWR_PDCRA_PA11_Msk                  (0x1U << PWR_PDCRA_PA11_Pos)       /*!< 0x00000800 */
+#define PWR_PDCRA_PA11                      PWR_PDCRA_PA11_Msk                 /*!< Port PA11 Pull-Down set */
+#define PWR_PDCRA_PA10_Pos                  (10U)                              
+#define PWR_PDCRA_PA10_Msk                  (0x1U << PWR_PDCRA_PA10_Pos)       /*!< 0x00000400 */
+#define PWR_PDCRA_PA10                      PWR_PDCRA_PA10_Msk                 /*!< Port PA10 Pull-Down set */
+#define PWR_PDCRA_PA9_Pos                   (9U)                               
+#define PWR_PDCRA_PA9_Msk                   (0x1U << PWR_PDCRA_PA9_Pos)        /*!< 0x00000200 */
+#define PWR_PDCRA_PA9                       PWR_PDCRA_PA9_Msk                  /*!< Port PA9 Pull-Down set  */
+#define PWR_PDCRA_PA8_Pos                   (8U)                               
+#define PWR_PDCRA_PA8_Msk                   (0x1U << PWR_PDCRA_PA8_Pos)        /*!< 0x00000100 */
+#define PWR_PDCRA_PA8                       PWR_PDCRA_PA8_Msk                  /*!< Port PA8 Pull-Down set  */
+#define PWR_PDCRA_PA7_Pos                   (7U)                               
+#define PWR_PDCRA_PA7_Msk                   (0x1U << PWR_PDCRA_PA7_Pos)        /*!< 0x00000080 */
+#define PWR_PDCRA_PA7                       PWR_PDCRA_PA7_Msk                  /*!< Port PA7 Pull-Down set  */
+#define PWR_PDCRA_PA6_Pos                   (6U)                               
+#define PWR_PDCRA_PA6_Msk                   (0x1U << PWR_PDCRA_PA6_Pos)        /*!< 0x00000040 */
+#define PWR_PDCRA_PA6                       PWR_PDCRA_PA6_Msk                  /*!< Port PA6 Pull-Down set  */
+#define PWR_PDCRA_PA5_Pos                   (5U)                               
+#define PWR_PDCRA_PA5_Msk                   (0x1U << PWR_PDCRA_PA5_Pos)        /*!< 0x00000020 */
+#define PWR_PDCRA_PA5                       PWR_PDCRA_PA5_Msk                  /*!< Port PA5 Pull-Down set  */
+#define PWR_PDCRA_PA4_Pos                   (4U)                               
+#define PWR_PDCRA_PA4_Msk                   (0x1U << PWR_PDCRA_PA4_Pos)        /*!< 0x00000010 */
+#define PWR_PDCRA_PA4                       PWR_PDCRA_PA4_Msk                  /*!< Port PA4 Pull-Down set  */
+#define PWR_PDCRA_PA3_Pos                   (3U)                               
+#define PWR_PDCRA_PA3_Msk                   (0x1U << PWR_PDCRA_PA3_Pos)        /*!< 0x00000008 */
+#define PWR_PDCRA_PA3                       PWR_PDCRA_PA3_Msk                  /*!< Port PA3 Pull-Down set  */
+#define PWR_PDCRA_PA2_Pos                   (2U)                               
+#define PWR_PDCRA_PA2_Msk                   (0x1U << PWR_PDCRA_PA2_Pos)        /*!< 0x00000004 */
+#define PWR_PDCRA_PA2                       PWR_PDCRA_PA2_Msk                  /*!< Port PA2 Pull-Down set  */
+#define PWR_PDCRA_PA1_Pos                   (1U)                               
+#define PWR_PDCRA_PA1_Msk                   (0x1U << PWR_PDCRA_PA1_Pos)        /*!< 0x00000002 */
+#define PWR_PDCRA_PA1                       PWR_PDCRA_PA1_Msk                  /*!< Port PA1 Pull-Down set  */
+#define PWR_PDCRA_PA0_Pos                   (0U)                               
+#define PWR_PDCRA_PA0_Msk                   (0x1U << PWR_PDCRA_PA0_Pos)        /*!< 0x00000001 */
+#define PWR_PDCRA_PA0                       PWR_PDCRA_PA0_Msk                  /*!< Port PA0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRB register  ********************/
+#define PWR_PUCRB_PB15_Pos                  (15U)                              
+#define PWR_PUCRB_PB15_Msk                  (0x1U << PWR_PUCRB_PB15_Pos)       /*!< 0x00008000 */
+#define PWR_PUCRB_PB15                      PWR_PUCRB_PB15_Msk                 /*!< Port PB15 Pull-Up set */
+#define PWR_PUCRB_PB14_Pos                  (14U)                              
+#define PWR_PUCRB_PB14_Msk                  (0x1U << PWR_PUCRB_PB14_Pos)       /*!< 0x00004000 */
+#define PWR_PUCRB_PB14                      PWR_PUCRB_PB14_Msk                 /*!< Port PB14 Pull-Up set */
+#define PWR_PUCRB_PB13_Pos                  (13U)                              
+#define PWR_PUCRB_PB13_Msk                  (0x1U << PWR_PUCRB_PB13_Pos)       /*!< 0x00002000 */
+#define PWR_PUCRB_PB13                      PWR_PUCRB_PB13_Msk                 /*!< Port PB13 Pull-Up set */
+#define PWR_PUCRB_PB12_Pos                  (12U)                              
+#define PWR_PUCRB_PB12_Msk                  (0x1U << PWR_PUCRB_PB12_Pos)       /*!< 0x00001000 */
+#define PWR_PUCRB_PB12                      PWR_PUCRB_PB12_Msk                 /*!< Port PB12 Pull-Up set */
+#define PWR_PUCRB_PB11_Pos                  (11U)                              
+#define PWR_PUCRB_PB11_Msk                  (0x1U << PWR_PUCRB_PB11_Pos)       /*!< 0x00000800 */
+#define PWR_PUCRB_PB11                      PWR_PUCRB_PB11_Msk                 /*!< Port PB11 Pull-Up set */
+#define PWR_PUCRB_PB10_Pos                  (10U)                              
+#define PWR_PUCRB_PB10_Msk                  (0x1U << PWR_PUCRB_PB10_Pos)       /*!< 0x00000400 */
+#define PWR_PUCRB_PB10                      PWR_PUCRB_PB10_Msk                 /*!< Port PB10 Pull-Up set */
+#define PWR_PUCRB_PB9_Pos                   (9U)                               
+#define PWR_PUCRB_PB9_Msk                   (0x1U << PWR_PUCRB_PB9_Pos)        /*!< 0x00000200 */
+#define PWR_PUCRB_PB9                       PWR_PUCRB_PB9_Msk                  /*!< Port PB9 Pull-Up set  */
+#define PWR_PUCRB_PB8_Pos                   (8U)                               
+#define PWR_PUCRB_PB8_Msk                   (0x1U << PWR_PUCRB_PB8_Pos)        /*!< 0x00000100 */
+#define PWR_PUCRB_PB8                       PWR_PUCRB_PB8_Msk                  /*!< Port PB8 Pull-Up set  */
+#define PWR_PUCRB_PB7_Pos                   (7U)                               
+#define PWR_PUCRB_PB7_Msk                   (0x1U << PWR_PUCRB_PB7_Pos)        /*!< 0x00000080 */
+#define PWR_PUCRB_PB7                       PWR_PUCRB_PB7_Msk                  /*!< Port PB7 Pull-Up set  */
+#define PWR_PUCRB_PB6_Pos                   (6U)                               
+#define PWR_PUCRB_PB6_Msk                   (0x1U << PWR_PUCRB_PB6_Pos)        /*!< 0x00000040 */
+#define PWR_PUCRB_PB6                       PWR_PUCRB_PB6_Msk                  /*!< Port PB6 Pull-Up set  */
+#define PWR_PUCRB_PB5_Pos                   (5U)                               
+#define PWR_PUCRB_PB5_Msk                   (0x1U << PWR_PUCRB_PB5_Pos)        /*!< 0x00000020 */
+#define PWR_PUCRB_PB5                       PWR_PUCRB_PB5_Msk                  /*!< Port PB5 Pull-Up set  */
+#define PWR_PUCRB_PB4_Pos                   (4U)                               
+#define PWR_PUCRB_PB4_Msk                   (0x1U << PWR_PUCRB_PB4_Pos)        /*!< 0x00000010 */
+#define PWR_PUCRB_PB4                       PWR_PUCRB_PB4_Msk                  /*!< Port PB4 Pull-Up set  */
+#define PWR_PUCRB_PB3_Pos                   (3U)                               
+#define PWR_PUCRB_PB3_Msk                   (0x1U << PWR_PUCRB_PB3_Pos)        /*!< 0x00000008 */
+#define PWR_PUCRB_PB3                       PWR_PUCRB_PB3_Msk                  /*!< Port PB3 Pull-Up set  */
+#define PWR_PUCRB_PB2_Pos                   (2U)                               
+#define PWR_PUCRB_PB2_Msk                   (0x1U << PWR_PUCRB_PB2_Pos)        /*!< 0x00000004 */
+#define PWR_PUCRB_PB2                       PWR_PUCRB_PB2_Msk                  /*!< Port PB2 Pull-Up set  */
+#define PWR_PUCRB_PB1_Pos                   (1U)                               
+#define PWR_PUCRB_PB1_Msk                   (0x1U << PWR_PUCRB_PB1_Pos)        /*!< 0x00000002 */
+#define PWR_PUCRB_PB1                       PWR_PUCRB_PB1_Msk                  /*!< Port PB1 Pull-Up set  */
+#define PWR_PUCRB_PB0_Pos                   (0U)                               
+#define PWR_PUCRB_PB0_Msk                   (0x1U << PWR_PUCRB_PB0_Pos)        /*!< 0x00000001 */
+#define PWR_PUCRB_PB0                       PWR_PUCRB_PB0_Msk                  /*!< Port PB0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRB register  ********************/
+#define PWR_PDCRB_PB15_Pos                  (15U)                              
+#define PWR_PDCRB_PB15_Msk                  (0x1U << PWR_PDCRB_PB15_Pos)       /*!< 0x00008000 */
+#define PWR_PDCRB_PB15                      PWR_PDCRB_PB15_Msk                 /*!< Port PB15 Pull-Down set */
+#define PWR_PDCRB_PB14_Pos                  (14U)                              
+#define PWR_PDCRB_PB14_Msk                  (0x1U << PWR_PDCRB_PB14_Pos)       /*!< 0x00004000 */
+#define PWR_PDCRB_PB14                      PWR_PDCRB_PB14_Msk                 /*!< Port PB14 Pull-Down set */
+#define PWR_PDCRB_PB13_Pos                  (13U)                              
+#define PWR_PDCRB_PB13_Msk                  (0x1U << PWR_PDCRB_PB13_Pos)       /*!< 0x00002000 */
+#define PWR_PDCRB_PB13                      PWR_PDCRB_PB13_Msk                 /*!< Port PB13 Pull-Down set */
+#define PWR_PDCRB_PB12_Pos                  (12U)                              
+#define PWR_PDCRB_PB12_Msk                  (0x1U << PWR_PDCRB_PB12_Pos)       /*!< 0x00001000 */
+#define PWR_PDCRB_PB12                      PWR_PDCRB_PB12_Msk                 /*!< Port PB12 Pull-Down set */
+#define PWR_PDCRB_PB11_Pos                  (11U)                              
+#define PWR_PDCRB_PB11_Msk                  (0x1U << PWR_PDCRB_PB11_Pos)       /*!< 0x00000800 */
+#define PWR_PDCRB_PB11                      PWR_PDCRB_PB11_Msk                 /*!< Port PB11 Pull-Down set */
+#define PWR_PDCRB_PB10_Pos                  (10U)                              
+#define PWR_PDCRB_PB10_Msk                  (0x1U << PWR_PDCRB_PB10_Pos)       /*!< 0x00000400 */
+#define PWR_PDCRB_PB10                      PWR_PDCRB_PB10_Msk                 /*!< Port PB10 Pull-Down set */
+#define PWR_PDCRB_PB9_Pos                   (9U)                               
+#define PWR_PDCRB_PB9_Msk                   (0x1U << PWR_PDCRB_PB9_Pos)        /*!< 0x00000200 */
+#define PWR_PDCRB_PB9                       PWR_PDCRB_PB9_Msk                  /*!< Port PB9 Pull-Down set  */
+#define PWR_PDCRB_PB8_Pos                   (8U)                               
+#define PWR_PDCRB_PB8_Msk                   (0x1U << PWR_PDCRB_PB8_Pos)        /*!< 0x00000100 */
+#define PWR_PDCRB_PB8                       PWR_PDCRB_PB8_Msk                  /*!< Port PB8 Pull-Down set  */
+#define PWR_PDCRB_PB7_Pos                   (7U)                               
+#define PWR_PDCRB_PB7_Msk                   (0x1U << PWR_PDCRB_PB7_Pos)        /*!< 0x00000080 */
+#define PWR_PDCRB_PB7                       PWR_PDCRB_PB7_Msk                  /*!< Port PB7 Pull-Down set  */
+#define PWR_PDCRB_PB6_Pos                   (6U)                               
+#define PWR_PDCRB_PB6_Msk                   (0x1U << PWR_PDCRB_PB6_Pos)        /*!< 0x00000040 */
+#define PWR_PDCRB_PB6                       PWR_PDCRB_PB6_Msk                  /*!< Port PB6 Pull-Down set  */
+#define PWR_PDCRB_PB5_Pos                   (5U)                               
+#define PWR_PDCRB_PB5_Msk                   (0x1U << PWR_PDCRB_PB5_Pos)        /*!< 0x00000020 */
+#define PWR_PDCRB_PB5                       PWR_PDCRB_PB5_Msk                  /*!< Port PB5 Pull-Down set  */
+#define PWR_PDCRB_PB3_Pos                   (3U)                               
+#define PWR_PDCRB_PB3_Msk                   (0x1U << PWR_PDCRB_PB3_Pos)        /*!< 0x00000008 */
+#define PWR_PDCRB_PB3                       PWR_PDCRB_PB3_Msk                  /*!< Port PB3 Pull-Down set  */
+#define PWR_PDCRB_PB2_Pos                   (2U)                               
+#define PWR_PDCRB_PB2_Msk                   (0x1U << PWR_PDCRB_PB2_Pos)        /*!< 0x00000004 */
+#define PWR_PDCRB_PB2                       PWR_PDCRB_PB2_Msk                  /*!< Port PB2 Pull-Down set  */
+#define PWR_PDCRB_PB1_Pos                   (1U)                               
+#define PWR_PDCRB_PB1_Msk                   (0x1U << PWR_PDCRB_PB1_Pos)        /*!< 0x00000002 */
+#define PWR_PDCRB_PB1                       PWR_PDCRB_PB1_Msk                  /*!< Port PB1 Pull-Down set  */
+#define PWR_PDCRB_PB0_Pos                   (0U)                               
+#define PWR_PDCRB_PB0_Msk                   (0x1U << PWR_PDCRB_PB0_Pos)        /*!< 0x00000001 */
+#define PWR_PDCRB_PB0                       PWR_PDCRB_PB0_Msk                  /*!< Port PB0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRC register  ********************/
+#define PWR_PUCRC_PC15_Pos                  (15U)                              
+#define PWR_PUCRC_PC15_Msk                  (0x1U << PWR_PUCRC_PC15_Pos)       /*!< 0x00008000 */
+#define PWR_PUCRC_PC15                      PWR_PUCRC_PC15_Msk                 /*!< Port PC15 Pull-Up set */
+#define PWR_PUCRC_PC14_Pos                  (14U)                              
+#define PWR_PUCRC_PC14_Msk                  (0x1U << PWR_PUCRC_PC14_Pos)       /*!< 0x00004000 */
+#define PWR_PUCRC_PC14                      PWR_PUCRC_PC14_Msk                 /*!< Port PC14 Pull-Up set */
+#define PWR_PUCRC_PC13_Pos                  (13U)                              
+#define PWR_PUCRC_PC13_Msk                  (0x1U << PWR_PUCRC_PC13_Pos)       /*!< 0x00002000 */
+#define PWR_PUCRC_PC13                      PWR_PUCRC_PC13_Msk                 /*!< Port PC13 Pull-Up set */
+#define PWR_PUCRC_PC12_Pos                  (12U)                              
+#define PWR_PUCRC_PC12_Msk                  (0x1U << PWR_PUCRC_PC12_Pos)       /*!< 0x00001000 */
+#define PWR_PUCRC_PC12                      PWR_PUCRC_PC12_Msk                 /*!< Port PC12 Pull-Up set */
+#define PWR_PUCRC_PC11_Pos                  (11U)                              
+#define PWR_PUCRC_PC11_Msk                  (0x1U << PWR_PUCRC_PC11_Pos)       /*!< 0x00000800 */
+#define PWR_PUCRC_PC11                      PWR_PUCRC_PC11_Msk                 /*!< Port PC11 Pull-Up set */
+#define PWR_PUCRC_PC10_Pos                  (10U)                              
+#define PWR_PUCRC_PC10_Msk                  (0x1U << PWR_PUCRC_PC10_Pos)       /*!< 0x00000400 */
+#define PWR_PUCRC_PC10                      PWR_PUCRC_PC10_Msk                 /*!< Port PC10 Pull-Up set */
+#define PWR_PUCRC_PC9_Pos                   (9U)                               
+#define PWR_PUCRC_PC9_Msk                   (0x1U << PWR_PUCRC_PC9_Pos)        /*!< 0x00000200 */
+#define PWR_PUCRC_PC9                       PWR_PUCRC_PC9_Msk                  /*!< Port PC9 Pull-Up set  */
+#define PWR_PUCRC_PC8_Pos                   (8U)                               
+#define PWR_PUCRC_PC8_Msk                   (0x1U << PWR_PUCRC_PC8_Pos)        /*!< 0x00000100 */
+#define PWR_PUCRC_PC8                       PWR_PUCRC_PC8_Msk                  /*!< Port PC8 Pull-Up set  */
+#define PWR_PUCRC_PC7_Pos                   (7U)                               
+#define PWR_PUCRC_PC7_Msk                   (0x1U << PWR_PUCRC_PC7_Pos)        /*!< 0x00000080 */
+#define PWR_PUCRC_PC7                       PWR_PUCRC_PC7_Msk                  /*!< Port PC7 Pull-Up set  */
+#define PWR_PUCRC_PC6_Pos                   (6U)                               
+#define PWR_PUCRC_PC6_Msk                   (0x1U << PWR_PUCRC_PC6_Pos)        /*!< 0x00000040 */
+#define PWR_PUCRC_PC6                       PWR_PUCRC_PC6_Msk                  /*!< Port PC6 Pull-Up set  */
+#define PWR_PUCRC_PC5_Pos                   (5U)                               
+#define PWR_PUCRC_PC5_Msk                   (0x1U << PWR_PUCRC_PC5_Pos)        /*!< 0x00000020 */
+#define PWR_PUCRC_PC5                       PWR_PUCRC_PC5_Msk                  /*!< Port PC5 Pull-Up set  */
+#define PWR_PUCRC_PC4_Pos                   (4U)                               
+#define PWR_PUCRC_PC4_Msk                   (0x1U << PWR_PUCRC_PC4_Pos)        /*!< 0x00000010 */
+#define PWR_PUCRC_PC4                       PWR_PUCRC_PC4_Msk                  /*!< Port PC4 Pull-Up set  */
+#define PWR_PUCRC_PC3_Pos                   (3U)                               
+#define PWR_PUCRC_PC3_Msk                   (0x1U << PWR_PUCRC_PC3_Pos)        /*!< 0x00000008 */
+#define PWR_PUCRC_PC3                       PWR_PUCRC_PC3_Msk                  /*!< Port PC3 Pull-Up set  */
+#define PWR_PUCRC_PC2_Pos                   (2U)                               
+#define PWR_PUCRC_PC2_Msk                   (0x1U << PWR_PUCRC_PC2_Pos)        /*!< 0x00000004 */
+#define PWR_PUCRC_PC2                       PWR_PUCRC_PC2_Msk                  /*!< Port PC2 Pull-Up set  */
+#define PWR_PUCRC_PC1_Pos                   (1U)                               
+#define PWR_PUCRC_PC1_Msk                   (0x1U << PWR_PUCRC_PC1_Pos)        /*!< 0x00000002 */
+#define PWR_PUCRC_PC1                       PWR_PUCRC_PC1_Msk                  /*!< Port PC1 Pull-Up set  */
+#define PWR_PUCRC_PC0_Pos                   (0U)                               
+#define PWR_PUCRC_PC0_Msk                   (0x1U << PWR_PUCRC_PC0_Pos)        /*!< 0x00000001 */
+#define PWR_PUCRC_PC0                       PWR_PUCRC_PC0_Msk                  /*!< Port PC0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRC register  ********************/
+#define PWR_PDCRC_PC15_Pos                  (15U)                              
+#define PWR_PDCRC_PC15_Msk                  (0x1U << PWR_PDCRC_PC15_Pos)       /*!< 0x00008000 */
+#define PWR_PDCRC_PC15                      PWR_PDCRC_PC15_Msk                 /*!< Port PC15 Pull-Down set */
+#define PWR_PDCRC_PC14_Pos                  (14U)                              
+#define PWR_PDCRC_PC14_Msk                  (0x1U << PWR_PDCRC_PC14_Pos)       /*!< 0x00004000 */
+#define PWR_PDCRC_PC14                      PWR_PDCRC_PC14_Msk                 /*!< Port PC14 Pull-Down set */
+#define PWR_PDCRC_PC13_Pos                  (13U)                              
+#define PWR_PDCRC_PC13_Msk                  (0x1U << PWR_PDCRC_PC13_Pos)       /*!< 0x00002000 */
+#define PWR_PDCRC_PC13                      PWR_PDCRC_PC13_Msk                 /*!< Port PC13 Pull-Down set */
+#define PWR_PDCRC_PC12_Pos                  (12U)                              
+#define PWR_PDCRC_PC12_Msk                  (0x1U << PWR_PDCRC_PC12_Pos)       /*!< 0x00001000 */
+#define PWR_PDCRC_PC12                      PWR_PDCRC_PC12_Msk                 /*!< Port PC12 Pull-Down set */
+#define PWR_PDCRC_PC11_Pos                  (11U)                              
+#define PWR_PDCRC_PC11_Msk                  (0x1U << PWR_PDCRC_PC11_Pos)       /*!< 0x00000800 */
+#define PWR_PDCRC_PC11                      PWR_PDCRC_PC11_Msk                 /*!< Port PC11 Pull-Down set */
+#define PWR_PDCRC_PC10_Pos                  (10U)                              
+#define PWR_PDCRC_PC10_Msk                  (0x1U << PWR_PDCRC_PC10_Pos)       /*!< 0x00000400 */
+#define PWR_PDCRC_PC10                      PWR_PDCRC_PC10_Msk                 /*!< Port PC10 Pull-Down set */
+#define PWR_PDCRC_PC9_Pos                   (9U)                               
+#define PWR_PDCRC_PC9_Msk                   (0x1U << PWR_PDCRC_PC9_Pos)        /*!< 0x00000200 */
+#define PWR_PDCRC_PC9                       PWR_PDCRC_PC9_Msk                  /*!< Port PC9 Pull-Down set  */
+#define PWR_PDCRC_PC8_Pos                   (8U)                               
+#define PWR_PDCRC_PC8_Msk                   (0x1U << PWR_PDCRC_PC8_Pos)        /*!< 0x00000100 */
+#define PWR_PDCRC_PC8                       PWR_PDCRC_PC8_Msk                  /*!< Port PC8 Pull-Down set  */
+#define PWR_PDCRC_PC7_Pos                   (7U)                               
+#define PWR_PDCRC_PC7_Msk                   (0x1U << PWR_PDCRC_PC7_Pos)        /*!< 0x00000080 */
+#define PWR_PDCRC_PC7                       PWR_PDCRC_PC7_Msk                  /*!< Port PC7 Pull-Down set  */
+#define PWR_PDCRC_PC6_Pos                   (6U)                               
+#define PWR_PDCRC_PC6_Msk                   (0x1U << PWR_PDCRC_PC6_Pos)        /*!< 0x00000040 */
+#define PWR_PDCRC_PC6                       PWR_PDCRC_PC6_Msk                  /*!< Port PC6 Pull-Down set  */
+#define PWR_PDCRC_PC5_Pos                   (5U)                               
+#define PWR_PDCRC_PC5_Msk                   (0x1U << PWR_PDCRC_PC5_Pos)        /*!< 0x00000020 */
+#define PWR_PDCRC_PC5                       PWR_PDCRC_PC5_Msk                  /*!< Port PC5 Pull-Down set  */
+#define PWR_PDCRC_PC4_Pos                   (4U)                               
+#define PWR_PDCRC_PC4_Msk                   (0x1U << PWR_PDCRC_PC4_Pos)        /*!< 0x00000010 */
+#define PWR_PDCRC_PC4                       PWR_PDCRC_PC4_Msk                  /*!< Port PC4 Pull-Down set  */
+#define PWR_PDCRC_PC3_Pos                   (3U)                               
+#define PWR_PDCRC_PC3_Msk                   (0x1U << PWR_PDCRC_PC3_Pos)        /*!< 0x00000008 */
+#define PWR_PDCRC_PC3                       PWR_PDCRC_PC3_Msk                  /*!< Port PC3 Pull-Down set  */
+#define PWR_PDCRC_PC2_Pos                   (2U)                               
+#define PWR_PDCRC_PC2_Msk                   (0x1U << PWR_PDCRC_PC2_Pos)        /*!< 0x00000004 */
+#define PWR_PDCRC_PC2                       PWR_PDCRC_PC2_Msk                  /*!< Port PC2 Pull-Down set  */
+#define PWR_PDCRC_PC1_Pos                   (1U)                               
+#define PWR_PDCRC_PC1_Msk                   (0x1U << PWR_PDCRC_PC1_Pos)        /*!< 0x00000002 */
+#define PWR_PDCRC_PC1                       PWR_PDCRC_PC1_Msk                  /*!< Port PC1 Pull-Down set  */
+#define PWR_PDCRC_PC0_Pos                   (0U)                               
+#define PWR_PDCRC_PC0_Msk                   (0x1U << PWR_PDCRC_PC0_Pos)        /*!< 0x00000001 */
+#define PWR_PDCRC_PC0                       PWR_PDCRC_PC0_Msk                  /*!< Port PC0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRD register  ********************/
+#define PWR_PUCRD_PD15_Pos                  (15U)                              
+#define PWR_PUCRD_PD15_Msk                  (0x1U << PWR_PUCRD_PD15_Pos)       /*!< 0x00008000 */
+#define PWR_PUCRD_PD15                      PWR_PUCRD_PD15_Msk                 /*!< Port PD15 Pull-Up set */
+#define PWR_PUCRD_PD14_Pos                  (14U)                              
+#define PWR_PUCRD_PD14_Msk                  (0x1U << PWR_PUCRD_PD14_Pos)       /*!< 0x00004000 */
+#define PWR_PUCRD_PD14                      PWR_PUCRD_PD14_Msk                 /*!< Port PD14 Pull-Up set */
+#define PWR_PUCRD_PD13_Pos                  (13U)                              
+#define PWR_PUCRD_PD13_Msk                  (0x1U << PWR_PUCRD_PD13_Pos)       /*!< 0x00002000 */
+#define PWR_PUCRD_PD13                      PWR_PUCRD_PD13_Msk                 /*!< Port PD13 Pull-Up set */
+#define PWR_PUCRD_PD12_Pos                  (12U)                              
+#define PWR_PUCRD_PD12_Msk                  (0x1U << PWR_PUCRD_PD12_Pos)       /*!< 0x00001000 */
+#define PWR_PUCRD_PD12                      PWR_PUCRD_PD12_Msk                 /*!< Port PD12 Pull-Up set */
+#define PWR_PUCRD_PD11_Pos                  (11U)                              
+#define PWR_PUCRD_PD11_Msk                  (0x1U << PWR_PUCRD_PD11_Pos)       /*!< 0x00000800 */
+#define PWR_PUCRD_PD11                      PWR_PUCRD_PD11_Msk                 /*!< Port PD11 Pull-Up set */
+#define PWR_PUCRD_PD10_Pos                  (10U)                              
+#define PWR_PUCRD_PD10_Msk                  (0x1U << PWR_PUCRD_PD10_Pos)       /*!< 0x00000400 */
+#define PWR_PUCRD_PD10                      PWR_PUCRD_PD10_Msk                 /*!< Port PD10 Pull-Up set */
+#define PWR_PUCRD_PD9_Pos                   (9U)                               
+#define PWR_PUCRD_PD9_Msk                   (0x1U << PWR_PUCRD_PD9_Pos)        /*!< 0x00000200 */
+#define PWR_PUCRD_PD9                       PWR_PUCRD_PD9_Msk                  /*!< Port PD9 Pull-Up set  */
+#define PWR_PUCRD_PD8_Pos                   (8U)                               
+#define PWR_PUCRD_PD8_Msk                   (0x1U << PWR_PUCRD_PD8_Pos)        /*!< 0x00000100 */
+#define PWR_PUCRD_PD8                       PWR_PUCRD_PD8_Msk                  /*!< Port PD8 Pull-Up set  */
+#define PWR_PUCRD_PD7_Pos                   (7U)                               
+#define PWR_PUCRD_PD7_Msk                   (0x1U << PWR_PUCRD_PD7_Pos)        /*!< 0x00000080 */
+#define PWR_PUCRD_PD7                       PWR_PUCRD_PD7_Msk                  /*!< Port PD7 Pull-Up set  */
+#define PWR_PUCRD_PD6_Pos                   (6U)                               
+#define PWR_PUCRD_PD6_Msk                   (0x1U << PWR_PUCRD_PD6_Pos)        /*!< 0x00000040 */
+#define PWR_PUCRD_PD6                       PWR_PUCRD_PD6_Msk                  /*!< Port PD6 Pull-Up set  */
+#define PWR_PUCRD_PD5_Pos                   (5U)                               
+#define PWR_PUCRD_PD5_Msk                   (0x1U << PWR_PUCRD_PD5_Pos)        /*!< 0x00000020 */
+#define PWR_PUCRD_PD5                       PWR_PUCRD_PD5_Msk                  /*!< Port PD5 Pull-Up set  */
+#define PWR_PUCRD_PD4_Pos                   (4U)                               
+#define PWR_PUCRD_PD4_Msk                   (0x1U << PWR_PUCRD_PD4_Pos)        /*!< 0x00000010 */
+#define PWR_PUCRD_PD4                       PWR_PUCRD_PD4_Msk                  /*!< Port PD4 Pull-Up set  */
+#define PWR_PUCRD_PD3_Pos                   (3U)                               
+#define PWR_PUCRD_PD3_Msk                   (0x1U << PWR_PUCRD_PD3_Pos)        /*!< 0x00000008 */
+#define PWR_PUCRD_PD3                       PWR_PUCRD_PD3_Msk                  /*!< Port PD3 Pull-Up set  */
+#define PWR_PUCRD_PD2_Pos                   (2U)                               
+#define PWR_PUCRD_PD2_Msk                   (0x1U << PWR_PUCRD_PD2_Pos)        /*!< 0x00000004 */
+#define PWR_PUCRD_PD2                       PWR_PUCRD_PD2_Msk                  /*!< Port PD2 Pull-Up set  */
+#define PWR_PUCRD_PD1_Pos                   (1U)                               
+#define PWR_PUCRD_PD1_Msk                   (0x1U << PWR_PUCRD_PD1_Pos)        /*!< 0x00000002 */
+#define PWR_PUCRD_PD1                       PWR_PUCRD_PD1_Msk                  /*!< Port PD1 Pull-Up set  */
+#define PWR_PUCRD_PD0_Pos                   (0U)                               
+#define PWR_PUCRD_PD0_Msk                   (0x1U << PWR_PUCRD_PD0_Pos)        /*!< 0x00000001 */
+#define PWR_PUCRD_PD0                       PWR_PUCRD_PD0_Msk                  /*!< Port PD0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRD register  ********************/
+#define PWR_PDCRD_PD15_Pos                  (15U)                              
+#define PWR_PDCRD_PD15_Msk                  (0x1U << PWR_PDCRD_PD15_Pos)       /*!< 0x00008000 */
+#define PWR_PDCRD_PD15                      PWR_PDCRD_PD15_Msk                 /*!< Port PD15 Pull-Down set */
+#define PWR_PDCRD_PD14_Pos                  (14U)                              
+#define PWR_PDCRD_PD14_Msk                  (0x1U << PWR_PDCRD_PD14_Pos)       /*!< 0x00004000 */
+#define PWR_PDCRD_PD14                      PWR_PDCRD_PD14_Msk                 /*!< Port PD14 Pull-Down set */
+#define PWR_PDCRD_PD13_Pos                  (13U)                              
+#define PWR_PDCRD_PD13_Msk                  (0x1U << PWR_PDCRD_PD13_Pos)       /*!< 0x00002000 */
+#define PWR_PDCRD_PD13                      PWR_PDCRD_PD13_Msk                 /*!< Port PD13 Pull-Down set */
+#define PWR_PDCRD_PD12_Pos                  (12U)                              
+#define PWR_PDCRD_PD12_Msk                  (0x1U << PWR_PDCRD_PD12_Pos)       /*!< 0x00001000 */
+#define PWR_PDCRD_PD12                      PWR_PDCRD_PD12_Msk                 /*!< Port PD12 Pull-Down set */
+#define PWR_PDCRD_PD11_Pos                  (11U)                              
+#define PWR_PDCRD_PD11_Msk                  (0x1U << PWR_PDCRD_PD11_Pos)       /*!< 0x00000800 */
+#define PWR_PDCRD_PD11                      PWR_PDCRD_PD11_Msk                 /*!< Port PD11 Pull-Down set */
+#define PWR_PDCRD_PD10_Pos                  (10U)                              
+#define PWR_PDCRD_PD10_Msk                  (0x1U << PWR_PDCRD_PD10_Pos)       /*!< 0x00000400 */
+#define PWR_PDCRD_PD10                      PWR_PDCRD_PD10_Msk                 /*!< Port PD10 Pull-Down set */
+#define PWR_PDCRD_PD9_Pos                   (9U)                               
+#define PWR_PDCRD_PD9_Msk                   (0x1U << PWR_PDCRD_PD9_Pos)        /*!< 0x00000200 */
+#define PWR_PDCRD_PD9                       PWR_PDCRD_PD9_Msk                  /*!< Port PD9 Pull-Down set  */
+#define PWR_PDCRD_PD8_Pos                   (8U)                               
+#define PWR_PDCRD_PD8_Msk                   (0x1U << PWR_PDCRD_PD8_Pos)        /*!< 0x00000100 */
+#define PWR_PDCRD_PD8                       PWR_PDCRD_PD8_Msk                  /*!< Port PD8 Pull-Down set  */
+#define PWR_PDCRD_PD7_Pos                   (7U)                               
+#define PWR_PDCRD_PD7_Msk                   (0x1U << PWR_PDCRD_PD7_Pos)        /*!< 0x00000080 */
+#define PWR_PDCRD_PD7                       PWR_PDCRD_PD7_Msk                  /*!< Port PD7 Pull-Down set  */
+#define PWR_PDCRD_PD6_Pos                   (6U)                               
+#define PWR_PDCRD_PD6_Msk                   (0x1U << PWR_PDCRD_PD6_Pos)        /*!< 0x00000040 */
+#define PWR_PDCRD_PD6                       PWR_PDCRD_PD6_Msk                  /*!< Port PD6 Pull-Down set  */
+#define PWR_PDCRD_PD5_Pos                   (5U)                               
+#define PWR_PDCRD_PD5_Msk                   (0x1U << PWR_PDCRD_PD5_Pos)        /*!< 0x00000020 */
+#define PWR_PDCRD_PD5                       PWR_PDCRD_PD5_Msk                  /*!< Port PD5 Pull-Down set  */
+#define PWR_PDCRD_PD4_Pos                   (4U)                               
+#define PWR_PDCRD_PD4_Msk                   (0x1U << PWR_PDCRD_PD4_Pos)        /*!< 0x00000010 */
+#define PWR_PDCRD_PD4                       PWR_PDCRD_PD4_Msk                  /*!< Port PD4 Pull-Down set  */
+#define PWR_PDCRD_PD3_Pos                   (3U)                               
+#define PWR_PDCRD_PD3_Msk                   (0x1U << PWR_PDCRD_PD3_Pos)        /*!< 0x00000008 */
+#define PWR_PDCRD_PD3                       PWR_PDCRD_PD3_Msk                  /*!< Port PD3 Pull-Down set  */
+#define PWR_PDCRD_PD2_Pos                   (2U)                               
+#define PWR_PDCRD_PD2_Msk                   (0x1U << PWR_PDCRD_PD2_Pos)        /*!< 0x00000004 */
+#define PWR_PDCRD_PD2                       PWR_PDCRD_PD2_Msk                  /*!< Port PD2 Pull-Down set  */
+#define PWR_PDCRD_PD1_Pos                   (1U)                               
+#define PWR_PDCRD_PD1_Msk                   (0x1U << PWR_PDCRD_PD1_Pos)        /*!< 0x00000002 */
+#define PWR_PDCRD_PD1                       PWR_PDCRD_PD1_Msk                  /*!< Port PD1 Pull-Down set  */
+#define PWR_PDCRD_PD0_Pos                   (0U)                               
+#define PWR_PDCRD_PD0_Msk                   (0x1U << PWR_PDCRD_PD0_Pos)        /*!< 0x00000001 */
+#define PWR_PDCRD_PD0                       PWR_PDCRD_PD0_Msk                  /*!< Port PD0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRE register  ********************/
+#define PWR_PUCRE_PE15_Pos                  (15U)                              
+#define PWR_PUCRE_PE15_Msk                  (0x1U << PWR_PUCRE_PE15_Pos)       /*!< 0x00008000 */
+#define PWR_PUCRE_PE15                      PWR_PUCRE_PE15_Msk                 /*!< Port PE15 Pull-Up set */
+#define PWR_PUCRE_PE14_Pos                  (14U)                              
+#define PWR_PUCRE_PE14_Msk                  (0x1U << PWR_PUCRE_PE14_Pos)       /*!< 0x00004000 */
+#define PWR_PUCRE_PE14                      PWR_PUCRE_PE14_Msk                 /*!< Port PE14 Pull-Up set */
+#define PWR_PUCRE_PE13_Pos                  (13U)                              
+#define PWR_PUCRE_PE13_Msk                  (0x1U << PWR_PUCRE_PE13_Pos)       /*!< 0x00002000 */
+#define PWR_PUCRE_PE13                      PWR_PUCRE_PE13_Msk                 /*!< Port PE13 Pull-Up set */
+#define PWR_PUCRE_PE12_Pos                  (12U)                              
+#define PWR_PUCRE_PE12_Msk                  (0x1U << PWR_PUCRE_PE12_Pos)       /*!< 0x00001000 */
+#define PWR_PUCRE_PE12                      PWR_PUCRE_PE12_Msk                 /*!< Port PE12 Pull-Up set */
+#define PWR_PUCRE_PE11_Pos                  (11U)                              
+#define PWR_PUCRE_PE11_Msk                  (0x1U << PWR_PUCRE_PE11_Pos)       /*!< 0x00000800 */
+#define PWR_PUCRE_PE11                      PWR_PUCRE_PE11_Msk                 /*!< Port PE11 Pull-Up set */
+#define PWR_PUCRE_PE10_Pos                  (10U)                              
+#define PWR_PUCRE_PE10_Msk                  (0x1U << PWR_PUCRE_PE10_Pos)       /*!< 0x00000400 */
+#define PWR_PUCRE_PE10                      PWR_PUCRE_PE10_Msk                 /*!< Port PE10 Pull-Up set */
+#define PWR_PUCRE_PE9_Pos                   (9U)                               
+#define PWR_PUCRE_PE9_Msk                   (0x1U << PWR_PUCRE_PE9_Pos)        /*!< 0x00000200 */
+#define PWR_PUCRE_PE9                       PWR_PUCRE_PE9_Msk                  /*!< Port PE9 Pull-Up set  */
+#define PWR_PUCRE_PE8_Pos                   (8U)                               
+#define PWR_PUCRE_PE8_Msk                   (0x1U << PWR_PUCRE_PE8_Pos)        /*!< 0x00000100 */
+#define PWR_PUCRE_PE8                       PWR_PUCRE_PE8_Msk                  /*!< Port PE8 Pull-Up set  */
+#define PWR_PUCRE_PE7_Pos                   (7U)                               
+#define PWR_PUCRE_PE7_Msk                   (0x1U << PWR_PUCRE_PE7_Pos)        /*!< 0x00000080 */
+#define PWR_PUCRE_PE7                       PWR_PUCRE_PE7_Msk                  /*!< Port PE7 Pull-Up set  */
+#define PWR_PUCRE_PE6_Pos                   (6U)                               
+#define PWR_PUCRE_PE6_Msk                   (0x1U << PWR_PUCRE_PE6_Pos)        /*!< 0x00000040 */
+#define PWR_PUCRE_PE6                       PWR_PUCRE_PE6_Msk                  /*!< Port PE6 Pull-Up set  */
+#define PWR_PUCRE_PE5_Pos                   (5U)                               
+#define PWR_PUCRE_PE5_Msk                   (0x1U << PWR_PUCRE_PE5_Pos)        /*!< 0x00000020 */
+#define PWR_PUCRE_PE5                       PWR_PUCRE_PE5_Msk                  /*!< Port PE5 Pull-Up set  */
+#define PWR_PUCRE_PE4_Pos                   (4U)                               
+#define PWR_PUCRE_PE4_Msk                   (0x1U << PWR_PUCRE_PE4_Pos)        /*!< 0x00000010 */
+#define PWR_PUCRE_PE4                       PWR_PUCRE_PE4_Msk                  /*!< Port PE4 Pull-Up set  */
+#define PWR_PUCRE_PE3_Pos                   (3U)                               
+#define PWR_PUCRE_PE3_Msk                   (0x1U << PWR_PUCRE_PE3_Pos)        /*!< 0x00000008 */
+#define PWR_PUCRE_PE3                       PWR_PUCRE_PE3_Msk                  /*!< Port PE3 Pull-Up set  */
+#define PWR_PUCRE_PE2_Pos                   (2U)                               
+#define PWR_PUCRE_PE2_Msk                   (0x1U << PWR_PUCRE_PE2_Pos)        /*!< 0x00000004 */
+#define PWR_PUCRE_PE2                       PWR_PUCRE_PE2_Msk                  /*!< Port PE2 Pull-Up set  */
+#define PWR_PUCRE_PE1_Pos                   (1U)                               
+#define PWR_PUCRE_PE1_Msk                   (0x1U << PWR_PUCRE_PE1_Pos)        /*!< 0x00000002 */
+#define PWR_PUCRE_PE1                       PWR_PUCRE_PE1_Msk                  /*!< Port PE1 Pull-Up set  */
+#define PWR_PUCRE_PE0_Pos                   (0U)                               
+#define PWR_PUCRE_PE0_Msk                   (0x1U << PWR_PUCRE_PE0_Pos)        /*!< 0x00000001 */
+#define PWR_PUCRE_PE0                       PWR_PUCRE_PE0_Msk                  /*!< Port PE0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRE register  ********************/
+#define PWR_PDCRE_PE15_Pos                  (15U)                              
+#define PWR_PDCRE_PE15_Msk                  (0x1U << PWR_PDCRE_PE15_Pos)       /*!< 0x00008000 */
+#define PWR_PDCRE_PE15                      PWR_PDCRE_PE15_Msk                 /*!< Port PE15 Pull-Down set */
+#define PWR_PDCRE_PE14_Pos                  (14U)                              
+#define PWR_PDCRE_PE14_Msk                  (0x1U << PWR_PDCRE_PE14_Pos)       /*!< 0x00004000 */
+#define PWR_PDCRE_PE14                      PWR_PDCRE_PE14_Msk                 /*!< Port PE14 Pull-Down set */
+#define PWR_PDCRE_PE13_Pos                  (13U)                              
+#define PWR_PDCRE_PE13_Msk                  (0x1U << PWR_PDCRE_PE13_Pos)       /*!< 0x00002000 */
+#define PWR_PDCRE_PE13                      PWR_PDCRE_PE13_Msk                 /*!< Port PE13 Pull-Down set */
+#define PWR_PDCRE_PE12_Pos                  (12U)                              
+#define PWR_PDCRE_PE12_Msk                  (0x1U << PWR_PDCRE_PE12_Pos)       /*!< 0x00001000 */
+#define PWR_PDCRE_PE12                      PWR_PDCRE_PE12_Msk                 /*!< Port PE12 Pull-Down set */
+#define PWR_PDCRE_PE11_Pos                  (11U)                              
+#define PWR_PDCRE_PE11_Msk                  (0x1U << PWR_PDCRE_PE11_Pos)       /*!< 0x00000800 */
+#define PWR_PDCRE_PE11                      PWR_PDCRE_PE11_Msk                 /*!< Port PE11 Pull-Down set */
+#define PWR_PDCRE_PE10_Pos                  (10U)                              
+#define PWR_PDCRE_PE10_Msk                  (0x1U << PWR_PDCRE_PE10_Pos)       /*!< 0x00000400 */
+#define PWR_PDCRE_PE10                      PWR_PDCRE_PE10_Msk                 /*!< Port PE10 Pull-Down set */
+#define PWR_PDCRE_PE9_Pos                   (9U)                               
+#define PWR_PDCRE_PE9_Msk                   (0x1U << PWR_PDCRE_PE9_Pos)        /*!< 0x00000200 */
+#define PWR_PDCRE_PE9                       PWR_PDCRE_PE9_Msk                  /*!< Port PE9 Pull-Down set  */
+#define PWR_PDCRE_PE8_Pos                   (8U)                               
+#define PWR_PDCRE_PE8_Msk                   (0x1U << PWR_PDCRE_PE8_Pos)        /*!< 0x00000100 */
+#define PWR_PDCRE_PE8                       PWR_PDCRE_PE8_Msk                  /*!< Port PE8 Pull-Down set  */
+#define PWR_PDCRE_PE7_Pos                   (7U)                               
+#define PWR_PDCRE_PE7_Msk                   (0x1U << PWR_PDCRE_PE7_Pos)        /*!< 0x00000080 */
+#define PWR_PDCRE_PE7                       PWR_PDCRE_PE7_Msk                  /*!< Port PE7 Pull-Down set  */
+#define PWR_PDCRE_PE6_Pos                   (6U)                               
+#define PWR_PDCRE_PE6_Msk                   (0x1U << PWR_PDCRE_PE6_Pos)        /*!< 0x00000040 */
+#define PWR_PDCRE_PE6                       PWR_PDCRE_PE6_Msk                  /*!< Port PE6 Pull-Down set  */
+#define PWR_PDCRE_PE5_Pos                   (5U)                               
+#define PWR_PDCRE_PE5_Msk                   (0x1U << PWR_PDCRE_PE5_Pos)        /*!< 0x00000020 */
+#define PWR_PDCRE_PE5                       PWR_PDCRE_PE5_Msk                  /*!< Port PE5 Pull-Down set  */
+#define PWR_PDCRE_PE4_Pos                   (4U)                               
+#define PWR_PDCRE_PE4_Msk                   (0x1U << PWR_PDCRE_PE4_Pos)        /*!< 0x00000010 */
+#define PWR_PDCRE_PE4                       PWR_PDCRE_PE4_Msk                  /*!< Port PE4 Pull-Down set  */
+#define PWR_PDCRE_PE3_Pos                   (3U)                               
+#define PWR_PDCRE_PE3_Msk                   (0x1U << PWR_PDCRE_PE3_Pos)        /*!< 0x00000008 */
+#define PWR_PDCRE_PE3                       PWR_PDCRE_PE3_Msk                  /*!< Port PE3 Pull-Down set  */
+#define PWR_PDCRE_PE2_Pos                   (2U)                               
+#define PWR_PDCRE_PE2_Msk                   (0x1U << PWR_PDCRE_PE2_Pos)        /*!< 0x00000004 */
+#define PWR_PDCRE_PE2                       PWR_PDCRE_PE2_Msk                  /*!< Port PE2 Pull-Down set  */
+#define PWR_PDCRE_PE1_Pos                   (1U)                               
+#define PWR_PDCRE_PE1_Msk                   (0x1U << PWR_PDCRE_PE1_Pos)        /*!< 0x00000002 */
+#define PWR_PDCRE_PE1                       PWR_PDCRE_PE1_Msk                  /*!< Port PE1 Pull-Down set  */
+#define PWR_PDCRE_PE0_Pos                   (0U)                               
+#define PWR_PDCRE_PE0_Msk                   (0x1U << PWR_PDCRE_PE0_Pos)        /*!< 0x00000001 */
+#define PWR_PDCRE_PE0                       PWR_PDCRE_PE0_Msk                  /*!< Port PE0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRF register  ********************/
+#define PWR_PUCRF_PF15_Pos                  (15U)                              
+#define PWR_PUCRF_PF15_Msk                  (0x1U << PWR_PUCRF_PF15_Pos)       /*!< 0x00008000 */
+#define PWR_PUCRF_PF15                      PWR_PUCRF_PF15_Msk                 /*!< Port PF15 Pull-Up set */
+#define PWR_PUCRF_PF14_Pos                  (14U)                              
+#define PWR_PUCRF_PF14_Msk                  (0x1U << PWR_PUCRF_PF14_Pos)       /*!< 0x00004000 */
+#define PWR_PUCRF_PF14                      PWR_PUCRF_PF14_Msk                 /*!< Port PF14 Pull-Up set */
+#define PWR_PUCRF_PF13_Pos                  (13U)                              
+#define PWR_PUCRF_PF13_Msk                  (0x1U << PWR_PUCRF_PF13_Pos)       /*!< 0x00002000 */
+#define PWR_PUCRF_PF13                      PWR_PUCRF_PF13_Msk                 /*!< Port PF13 Pull-Up set */
+#define PWR_PUCRF_PF12_Pos                  (12U)                              
+#define PWR_PUCRF_PF12_Msk                  (0x1U << PWR_PUCRF_PF12_Pos)       /*!< 0x00001000 */
+#define PWR_PUCRF_PF12                      PWR_PUCRF_PF12_Msk                 /*!< Port PF12 Pull-Up set */
+#define PWR_PUCRF_PF11_Pos                  (11U)                              
+#define PWR_PUCRF_PF11_Msk                  (0x1U << PWR_PUCRF_PF11_Pos)       /*!< 0x00000800 */
+#define PWR_PUCRF_PF11                      PWR_PUCRF_PF11_Msk                 /*!< Port PF11 Pull-Up set */
+#define PWR_PUCRF_PF10_Pos                  (10U)                              
+#define PWR_PUCRF_PF10_Msk                  (0x1U << PWR_PUCRF_PF10_Pos)       /*!< 0x00000400 */
+#define PWR_PUCRF_PF10                      PWR_PUCRF_PF10_Msk                 /*!< Port PF10 Pull-Up set */
+#define PWR_PUCRF_PF9_Pos                   (9U)                               
+#define PWR_PUCRF_PF9_Msk                   (0x1U << PWR_PUCRF_PF9_Pos)        /*!< 0x00000200 */
+#define PWR_PUCRF_PF9                       PWR_PUCRF_PF9_Msk                  /*!< Port PF9 Pull-Up set  */
+#define PWR_PUCRF_PF8_Pos                   (8U)                               
+#define PWR_PUCRF_PF8_Msk                   (0x1U << PWR_PUCRF_PF8_Pos)        /*!< 0x00000100 */
+#define PWR_PUCRF_PF8                       PWR_PUCRF_PF8_Msk                  /*!< Port PF8 Pull-Up set  */
+#define PWR_PUCRF_PF7_Pos                   (7U)                               
+#define PWR_PUCRF_PF7_Msk                   (0x1U << PWR_PUCRF_PF7_Pos)        /*!< 0x00000080 */
+#define PWR_PUCRF_PF7                       PWR_PUCRF_PF7_Msk                  /*!< Port PF7 Pull-Up set  */
+#define PWR_PUCRF_PF6_Pos                   (6U)                               
+#define PWR_PUCRF_PF6_Msk                   (0x1U << PWR_PUCRF_PF6_Pos)        /*!< 0x00000040 */
+#define PWR_PUCRF_PF6                       PWR_PUCRF_PF6_Msk                  /*!< Port PF6 Pull-Up set  */
+#define PWR_PUCRF_PF5_Pos                   (5U)                               
+#define PWR_PUCRF_PF5_Msk                   (0x1U << PWR_PUCRF_PF5_Pos)        /*!< 0x00000020 */
+#define PWR_PUCRF_PF5                       PWR_PUCRF_PF5_Msk                  /*!< Port PF5 Pull-Up set  */
+#define PWR_PUCRF_PF4_Pos                   (4U)                               
+#define PWR_PUCRF_PF4_Msk                   (0x1U << PWR_PUCRF_PF4_Pos)        /*!< 0x00000010 */
+#define PWR_PUCRF_PF4                       PWR_PUCRF_PF4_Msk                  /*!< Port PF4 Pull-Up set  */
+#define PWR_PUCRF_PF3_Pos                   (3U)                               
+#define PWR_PUCRF_PF3_Msk                   (0x1U << PWR_PUCRF_PF3_Pos)        /*!< 0x00000008 */
+#define PWR_PUCRF_PF3                       PWR_PUCRF_PF3_Msk                  /*!< Port PF3 Pull-Up set  */
+#define PWR_PUCRF_PF2_Pos                   (2U)                               
+#define PWR_PUCRF_PF2_Msk                   (0x1U << PWR_PUCRF_PF2_Pos)        /*!< 0x00000004 */
+#define PWR_PUCRF_PF2                       PWR_PUCRF_PF2_Msk                  /*!< Port PF2 Pull-Up set  */
+#define PWR_PUCRF_PF1_Pos                   (1U)                               
+#define PWR_PUCRF_PF1_Msk                   (0x1U << PWR_PUCRF_PF1_Pos)        /*!< 0x00000002 */
+#define PWR_PUCRF_PF1                       PWR_PUCRF_PF1_Msk                  /*!< Port PF1 Pull-Up set  */
+#define PWR_PUCRF_PF0_Pos                   (0U)                               
+#define PWR_PUCRF_PF0_Msk                   (0x1U << PWR_PUCRF_PF0_Pos)        /*!< 0x00000001 */
+#define PWR_PUCRF_PF0                       PWR_PUCRF_PF0_Msk                  /*!< Port PF0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRF register  ********************/
+#define PWR_PDCRF_PF15_Pos                  (15U)                              
+#define PWR_PDCRF_PF15_Msk                  (0x1U << PWR_PDCRF_PF15_Pos)       /*!< 0x00008000 */
+#define PWR_PDCRF_PF15                      PWR_PDCRF_PF15_Msk                 /*!< Port PF15 Pull-Down set */
+#define PWR_PDCRF_PF14_Pos                  (14U)                              
+#define PWR_PDCRF_PF14_Msk                  (0x1U << PWR_PDCRF_PF14_Pos)       /*!< 0x00004000 */
+#define PWR_PDCRF_PF14                      PWR_PDCRF_PF14_Msk                 /*!< Port PF14 Pull-Down set */
+#define PWR_PDCRF_PF13_Pos                  (13U)                              
+#define PWR_PDCRF_PF13_Msk                  (0x1U << PWR_PDCRF_PF13_Pos)       /*!< 0x00002000 */
+#define PWR_PDCRF_PF13                      PWR_PDCRF_PF13_Msk                 /*!< Port PF13 Pull-Down set */
+#define PWR_PDCRF_PF12_Pos                  (12U)                              
+#define PWR_PDCRF_PF12_Msk                  (0x1U << PWR_PDCRF_PF12_Pos)       /*!< 0x00001000 */
+#define PWR_PDCRF_PF12                      PWR_PDCRF_PF12_Msk                 /*!< Port PF12 Pull-Down set */
+#define PWR_PDCRF_PF11_Pos                  (11U)                              
+#define PWR_PDCRF_PF11_Msk                  (0x1U << PWR_PDCRF_PF11_Pos)       /*!< 0x00000800 */
+#define PWR_PDCRF_PF11                      PWR_PDCRF_PF11_Msk                 /*!< Port PF11 Pull-Down set */
+#define PWR_PDCRF_PF10_Pos                  (10U)                              
+#define PWR_PDCRF_PF10_Msk                  (0x1U << PWR_PDCRF_PF10_Pos)       /*!< 0x00000400 */
+#define PWR_PDCRF_PF10                      PWR_PDCRF_PF10_Msk                 /*!< Port PF10 Pull-Down set */
+#define PWR_PDCRF_PF9_Pos                   (9U)                               
+#define PWR_PDCRF_PF9_Msk                   (0x1U << PWR_PDCRF_PF9_Pos)        /*!< 0x00000200 */
+#define PWR_PDCRF_PF9                       PWR_PDCRF_PF9_Msk                  /*!< Port PF9 Pull-Down set  */
+#define PWR_PDCRF_PF8_Pos                   (8U)                               
+#define PWR_PDCRF_PF8_Msk                   (0x1U << PWR_PDCRF_PF8_Pos)        /*!< 0x00000100 */
+#define PWR_PDCRF_PF8                       PWR_PDCRF_PF8_Msk                  /*!< Port PF8 Pull-Down set  */
+#define PWR_PDCRF_PF7_Pos                   (7U)                               
+#define PWR_PDCRF_PF7_Msk                   (0x1U << PWR_PDCRF_PF7_Pos)        /*!< 0x00000080 */
+#define PWR_PDCRF_PF7                       PWR_PDCRF_PF7_Msk                  /*!< Port PF7 Pull-Down set  */
+#define PWR_PDCRF_PF6_Pos                   (6U)                               
+#define PWR_PDCRF_PF6_Msk                   (0x1U << PWR_PDCRF_PF6_Pos)        /*!< 0x00000040 */
+#define PWR_PDCRF_PF6                       PWR_PDCRF_PF6_Msk                  /*!< Port PF6 Pull-Down set  */
+#define PWR_PDCRF_PF5_Pos                   (5U)                               
+#define PWR_PDCRF_PF5_Msk                   (0x1U << PWR_PDCRF_PF5_Pos)        /*!< 0x00000020 */
+#define PWR_PDCRF_PF5                       PWR_PDCRF_PF5_Msk                  /*!< Port PF5 Pull-Down set  */
+#define PWR_PDCRF_PF4_Pos                   (4U)                               
+#define PWR_PDCRF_PF4_Msk                   (0x1U << PWR_PDCRF_PF4_Pos)        /*!< 0x00000010 */
+#define PWR_PDCRF_PF4                       PWR_PDCRF_PF4_Msk                  /*!< Port PF4 Pull-Down set  */
+#define PWR_PDCRF_PF3_Pos                   (3U)                               
+#define PWR_PDCRF_PF3_Msk                   (0x1U << PWR_PDCRF_PF3_Pos)        /*!< 0x00000008 */
+#define PWR_PDCRF_PF3                       PWR_PDCRF_PF3_Msk                  /*!< Port PF3 Pull-Down set  */
+#define PWR_PDCRF_PF2_Pos                   (2U)                               
+#define PWR_PDCRF_PF2_Msk                   (0x1U << PWR_PDCRF_PF2_Pos)        /*!< 0x00000004 */
+#define PWR_PDCRF_PF2                       PWR_PDCRF_PF2_Msk                  /*!< Port PF2 Pull-Down set  */
+#define PWR_PDCRF_PF1_Pos                   (1U)                               
+#define PWR_PDCRF_PF1_Msk                   (0x1U << PWR_PDCRF_PF1_Pos)        /*!< 0x00000002 */
+#define PWR_PDCRF_PF1                       PWR_PDCRF_PF1_Msk                  /*!< Port PF1 Pull-Down set  */
+#define PWR_PDCRF_PF0_Pos                   (0U)                               
+#define PWR_PDCRF_PF0_Msk                   (0x1U << PWR_PDCRF_PF0_Pos)        /*!< 0x00000001 */
+#define PWR_PDCRF_PF0                       PWR_PDCRF_PF0_Msk                  /*!< Port PF0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRG register  ********************/
+#define PWR_PUCRG_PG15_Pos                  (15U)                              
+#define PWR_PUCRG_PG15_Msk                  (0x1U << PWR_PUCRG_PG15_Pos)       /*!< 0x00008000 */
+#define PWR_PUCRG_PG15                      PWR_PUCRG_PG15_Msk                 /*!< Port PG15 Pull-Up set */
+#define PWR_PUCRG_PG14_Pos                  (14U)                              
+#define PWR_PUCRG_PG14_Msk                  (0x1U << PWR_PUCRG_PG14_Pos)       /*!< 0x00004000 */
+#define PWR_PUCRG_PG14                      PWR_PUCRG_PG14_Msk                 /*!< Port PG14 Pull-Up set */
+#define PWR_PUCRG_PG13_Pos                  (13U)                              
+#define PWR_PUCRG_PG13_Msk                  (0x1U << PWR_PUCRG_PG13_Pos)       /*!< 0x00002000 */
+#define PWR_PUCRG_PG13                      PWR_PUCRG_PG13_Msk                 /*!< Port PG13 Pull-Up set */
+#define PWR_PUCRG_PG12_Pos                  (12U)                              
+#define PWR_PUCRG_PG12_Msk                  (0x1U << PWR_PUCRG_PG12_Pos)       /*!< 0x00001000 */
+#define PWR_PUCRG_PG12                      PWR_PUCRG_PG12_Msk                 /*!< Port PG12 Pull-Up set */
+#define PWR_PUCRG_PG11_Pos                  (11U)                              
+#define PWR_PUCRG_PG11_Msk                  (0x1U << PWR_PUCRG_PG11_Pos)       /*!< 0x00000800 */
+#define PWR_PUCRG_PG11                      PWR_PUCRG_PG11_Msk                 /*!< Port PG11 Pull-Up set */
+#define PWR_PUCRG_PG10_Pos                  (10U)                              
+#define PWR_PUCRG_PG10_Msk                  (0x1U << PWR_PUCRG_PG10_Pos)       /*!< 0x00000400 */
+#define PWR_PUCRG_PG10                      PWR_PUCRG_PG10_Msk                 /*!< Port PG10 Pull-Up set */
+#define PWR_PUCRG_PG9_Pos                   (9U)                               
+#define PWR_PUCRG_PG9_Msk                   (0x1U << PWR_PUCRG_PG9_Pos)        /*!< 0x00000200 */
+#define PWR_PUCRG_PG9                       PWR_PUCRG_PG9_Msk                  /*!< Port PG9 Pull-Up set  */
+#define PWR_PUCRG_PG8_Pos                   (8U)                               
+#define PWR_PUCRG_PG8_Msk                   (0x1U << PWR_PUCRG_PG8_Pos)        /*!< 0x00000100 */
+#define PWR_PUCRG_PG8                       PWR_PUCRG_PG8_Msk                  /*!< Port PG8 Pull-Up set  */
+#define PWR_PUCRG_PG7_Pos                   (7U)                               
+#define PWR_PUCRG_PG7_Msk                   (0x1U << PWR_PUCRG_PG7_Pos)        /*!< 0x00000080 */
+#define PWR_PUCRG_PG7                       PWR_PUCRG_PG7_Msk                  /*!< Port PG7 Pull-Up set  */
+#define PWR_PUCRG_PG6_Pos                   (6U)                               
+#define PWR_PUCRG_PG6_Msk                   (0x1U << PWR_PUCRG_PG6_Pos)        /*!< 0x00000040 */
+#define PWR_PUCRG_PG6                       PWR_PUCRG_PG6_Msk                  /*!< Port PG6 Pull-Up set  */
+#define PWR_PUCRG_PG5_Pos                   (5U)                               
+#define PWR_PUCRG_PG5_Msk                   (0x1U << PWR_PUCRG_PG5_Pos)        /*!< 0x00000020 */
+#define PWR_PUCRG_PG5                       PWR_PUCRG_PG5_Msk                  /*!< Port PG5 Pull-Up set  */
+#define PWR_PUCRG_PG4_Pos                   (4U)                               
+#define PWR_PUCRG_PG4_Msk                   (0x1U << PWR_PUCRG_PG4_Pos)        /*!< 0x00000010 */
+#define PWR_PUCRG_PG4                       PWR_PUCRG_PG4_Msk                  /*!< Port PG4 Pull-Up set  */
+#define PWR_PUCRG_PG3_Pos                   (3U)                               
+#define PWR_PUCRG_PG3_Msk                   (0x1U << PWR_PUCRG_PG3_Pos)        /*!< 0x00000008 */
+#define PWR_PUCRG_PG3                       PWR_PUCRG_PG3_Msk                  /*!< Port PG3 Pull-Up set  */
+#define PWR_PUCRG_PG2_Pos                   (2U)                               
+#define PWR_PUCRG_PG2_Msk                   (0x1U << PWR_PUCRG_PG2_Pos)        /*!< 0x00000004 */
+#define PWR_PUCRG_PG2                       PWR_PUCRG_PG2_Msk                  /*!< Port PG2 Pull-Up set  */
+#define PWR_PUCRG_PG1_Pos                   (1U)                               
+#define PWR_PUCRG_PG1_Msk                   (0x1U << PWR_PUCRG_PG1_Pos)        /*!< 0x00000002 */
+#define PWR_PUCRG_PG1                       PWR_PUCRG_PG1_Msk                  /*!< Port PG1 Pull-Up set  */
+#define PWR_PUCRG_PG0_Pos                   (0U)                               
+#define PWR_PUCRG_PG0_Msk                   (0x1U << PWR_PUCRG_PG0_Pos)        /*!< 0x00000001 */
+#define PWR_PUCRG_PG0                       PWR_PUCRG_PG0_Msk                  /*!< Port PG0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRG register  ********************/
+#define PWR_PDCRG_PG15_Pos                  (15U)                              
+#define PWR_PDCRG_PG15_Msk                  (0x1U << PWR_PDCRG_PG15_Pos)       /*!< 0x00008000 */
+#define PWR_PDCRG_PG15                      PWR_PDCRG_PG15_Msk                 /*!< Port PG15 Pull-Down set */
+#define PWR_PDCRG_PG14_Pos                  (14U)                              
+#define PWR_PDCRG_PG14_Msk                  (0x1U << PWR_PDCRG_PG14_Pos)       /*!< 0x00004000 */
+#define PWR_PDCRG_PG14                      PWR_PDCRG_PG14_Msk                 /*!< Port PG14 Pull-Down set */
+#define PWR_PDCRG_PG13_Pos                  (13U)                              
+#define PWR_PDCRG_PG13_Msk                  (0x1U << PWR_PDCRG_PG13_Pos)       /*!< 0x00002000 */
+#define PWR_PDCRG_PG13                      PWR_PDCRG_PG13_Msk                 /*!< Port PG13 Pull-Down set */
+#define PWR_PDCRG_PG12_Pos                  (12U)                              
+#define PWR_PDCRG_PG12_Msk                  (0x1U << PWR_PDCRG_PG12_Pos)       /*!< 0x00001000 */
+#define PWR_PDCRG_PG12                      PWR_PDCRG_PG12_Msk                 /*!< Port PG12 Pull-Down set */
+#define PWR_PDCRG_PG11_Pos                  (11U)                              
+#define PWR_PDCRG_PG11_Msk                  (0x1U << PWR_PDCRG_PG11_Pos)       /*!< 0x00000800 */
+#define PWR_PDCRG_PG11                      PWR_PDCRG_PG11_Msk                 /*!< Port PG11 Pull-Down set */
+#define PWR_PDCRG_PG10_Pos                  (10U)                              
+#define PWR_PDCRG_PG10_Msk                  (0x1U << PWR_PDCRG_PG10_Pos)       /*!< 0x00000400 */
+#define PWR_PDCRG_PG10                      PWR_PDCRG_PG10_Msk                 /*!< Port PG10 Pull-Down set */
+#define PWR_PDCRG_PG9_Pos                   (9U)                               
+#define PWR_PDCRG_PG9_Msk                   (0x1U << PWR_PDCRG_PG9_Pos)        /*!< 0x00000200 */
+#define PWR_PDCRG_PG9                       PWR_PDCRG_PG9_Msk                  /*!< Port PG9 Pull-Down set  */
+#define PWR_PDCRG_PG8_Pos                   (8U)                               
+#define PWR_PDCRG_PG8_Msk                   (0x1U << PWR_PDCRG_PG8_Pos)        /*!< 0x00000100 */
+#define PWR_PDCRG_PG8                       PWR_PDCRG_PG8_Msk                  /*!< Port PG8 Pull-Down set  */
+#define PWR_PDCRG_PG7_Pos                   (7U)                               
+#define PWR_PDCRG_PG7_Msk                   (0x1U << PWR_PDCRG_PG7_Pos)        /*!< 0x00000080 */
+#define PWR_PDCRG_PG7                       PWR_PDCRG_PG7_Msk                  /*!< Port PG7 Pull-Down set  */
+#define PWR_PDCRG_PG6_Pos                   (6U)                               
+#define PWR_PDCRG_PG6_Msk                   (0x1U << PWR_PDCRG_PG6_Pos)        /*!< 0x00000040 */
+#define PWR_PDCRG_PG6                       PWR_PDCRG_PG6_Msk                  /*!< Port PG6 Pull-Down set  */
+#define PWR_PDCRG_PG5_Pos                   (5U)                               
+#define PWR_PDCRG_PG5_Msk                   (0x1U << PWR_PDCRG_PG5_Pos)        /*!< 0x00000020 */
+#define PWR_PDCRG_PG5                       PWR_PDCRG_PG5_Msk                  /*!< Port PG5 Pull-Down set  */
+#define PWR_PDCRG_PG4_Pos                   (4U)                               
+#define PWR_PDCRG_PG4_Msk                   (0x1U << PWR_PDCRG_PG4_Pos)        /*!< 0x00000010 */
+#define PWR_PDCRG_PG4                       PWR_PDCRG_PG4_Msk                  /*!< Port PG4 Pull-Down set  */
+#define PWR_PDCRG_PG3_Pos                   (3U)                               
+#define PWR_PDCRG_PG3_Msk                   (0x1U << PWR_PDCRG_PG3_Pos)        /*!< 0x00000008 */
+#define PWR_PDCRG_PG3                       PWR_PDCRG_PG3_Msk                  /*!< Port PG3 Pull-Down set  */
+#define PWR_PDCRG_PG2_Pos                   (2U)                               
+#define PWR_PDCRG_PG2_Msk                   (0x1U << PWR_PDCRG_PG2_Pos)        /*!< 0x00000004 */
+#define PWR_PDCRG_PG2                       PWR_PDCRG_PG2_Msk                  /*!< Port PG2 Pull-Down set  */
+#define PWR_PDCRG_PG1_Pos                   (1U)                               
+#define PWR_PDCRG_PG1_Msk                   (0x1U << PWR_PDCRG_PG1_Pos)        /*!< 0x00000002 */
+#define PWR_PDCRG_PG1                       PWR_PDCRG_PG1_Msk                  /*!< Port PG1 Pull-Down set  */
+#define PWR_PDCRG_PG0_Pos                   (0U)                               
+#define PWR_PDCRG_PG0_Msk                   (0x1U << PWR_PDCRG_PG0_Pos)        /*!< 0x00000001 */
+#define PWR_PDCRG_PG0                       PWR_PDCRG_PG0_Msk                  /*!< Port PG0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRH register  ********************/
+#define PWR_PUCRH_PH1_Pos                   (1U)                               
+#define PWR_PUCRH_PH1_Msk                   (0x1U << PWR_PUCRH_PH1_Pos)        /*!< 0x00000002 */
+#define PWR_PUCRH_PH1                       PWR_PUCRH_PH1_Msk                  /*!< Port PH1 Pull-Up set  */
+#define PWR_PUCRH_PH0_Pos                   (0U)                               
+#define PWR_PUCRH_PH0_Msk                   (0x1U << PWR_PUCRH_PH0_Pos)        /*!< 0x00000001 */
+#define PWR_PUCRH_PH0                       PWR_PUCRH_PH0_Msk                  /*!< Port PH0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRH register  ********************/
+#define PWR_PDCRH_PH1_Pos                   (1U)                               
+#define PWR_PDCRH_PH1_Msk                   (0x1U << PWR_PDCRH_PH1_Pos)        /*!< 0x00000002 */
+#define PWR_PDCRH_PH1                       PWR_PDCRH_PH1_Msk                  /*!< Port PH1 Pull-Down set  */
+#define PWR_PDCRH_PH0_Pos                   (0U)                               
+#define PWR_PDCRH_PH0_Msk                   (0x1U << PWR_PDCRH_PH0_Pos)        /*!< 0x00000001 */
+#define PWR_PDCRH_PH0                       PWR_PDCRH_PH0_Msk                  /*!< Port PH0 Pull-Down set  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions  (not present on all devices in the STM32L4 serie)
+*/
+#define RCC_PLLSAI2_SUPPORT
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_MSION_Pos                    (0U)                               
+#define RCC_CR_MSION_Msk                    (0x1U << RCC_CR_MSION_Pos)         /*!< 0x00000001 */
+#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed oscillator (MSI) clock enable */
+#define RCC_CR_MSIRDY_Pos                   (1U)                               
+#define RCC_CR_MSIRDY_Msk                   (0x1U << RCC_CR_MSIRDY_Pos)        /*!< 0x00000002 */
+#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
+#define RCC_CR_MSIPLLEN_Pos                 (2U)                               
+#define RCC_CR_MSIPLLEN_Msk                 (0x1U << RCC_CR_MSIPLLEN_Pos)      /*!< 0x00000004 */
+#define RCC_CR_MSIPLLEN                     RCC_CR_MSIPLLEN_Msk                /*!< Internal Multi Speed oscillator (MSI) PLL enable */
+#define RCC_CR_MSIRGSEL_Pos                 (3U)                               
+#define RCC_CR_MSIRGSEL_Msk                 (0x1U << RCC_CR_MSIRGSEL_Pos)      /*!< 0x00000008 */
+#define RCC_CR_MSIRGSEL                     RCC_CR_MSIRGSEL_Msk                /*!< Internal Multi Speed oscillator (MSI) range selection */
+
+/*!< MSIRANGE configuration : 12 frequency ranges available */
+#define RCC_CR_MSIRANGE_Pos                 (4U)                               
+#define RCC_CR_MSIRANGE_Msk                 (0xFU << RCC_CR_MSIRANGE_Pos)      /*!< 0x000000F0 */
+#define RCC_CR_MSIRANGE                     RCC_CR_MSIRANGE_Msk                /*!< Internal Multi Speed oscillator (MSI) clock Range */
+#define RCC_CR_MSIRANGE_0                   (0x0U << RCC_CR_MSIRANGE_Pos)      /*!< 0x00000000 */
+#define RCC_CR_MSIRANGE_1                   (0x1U << RCC_CR_MSIRANGE_Pos)      /*!< 0x00000010 */
+#define RCC_CR_MSIRANGE_2                   (0x2U << RCC_CR_MSIRANGE_Pos)      /*!< 0x00000020 */
+#define RCC_CR_MSIRANGE_3                   (0x3U << RCC_CR_MSIRANGE_Pos)      /*!< 0x00000030 */
+#define RCC_CR_MSIRANGE_4                   (0x4U << RCC_CR_MSIRANGE_Pos)      /*!< 0x00000040 */
+#define RCC_CR_MSIRANGE_5                   (0x5U << RCC_CR_MSIRANGE_Pos)      /*!< 0x00000050 */
+#define RCC_CR_MSIRANGE_6                   (0x6U << RCC_CR_MSIRANGE_Pos)      /*!< 0x00000060 */
+#define RCC_CR_MSIRANGE_7                   (0x7U << RCC_CR_MSIRANGE_Pos)      /*!< 0x00000070 */
+#define RCC_CR_MSIRANGE_8                   (0x8U << RCC_CR_MSIRANGE_Pos)      /*!< 0x00000080 */
+#define RCC_CR_MSIRANGE_9                   (0x9U << RCC_CR_MSIRANGE_Pos)      /*!< 0x00000090 */
+#define RCC_CR_MSIRANGE_10                  (0xAU << RCC_CR_MSIRANGE_Pos)      /*!< 0x000000A0 */
+#define RCC_CR_MSIRANGE_11                  (0xBU << RCC_CR_MSIRANGE_Pos)      /*!< 0x000000B0 */
+
+#define RCC_CR_HSION_Pos                    (8U)                               
+#define RCC_CR_HSION_Msk                    (0x1U << RCC_CR_HSION_Pos)         /*!< 0x00000100 */
+#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed oscillator (HSI16) clock enable */
+#define RCC_CR_HSIKERON_Pos                 (9U)                               
+#define RCC_CR_HSIKERON_Msk                 (0x1U << RCC_CR_HSIKERON_Pos)      /*!< 0x00000200 */
+#define RCC_CR_HSIKERON                     RCC_CR_HSIKERON_Msk                /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                   (10U)                              
+#define RCC_CR_HSIRDY_Msk                   (0x1U << RCC_CR_HSIRDY_Pos)        /*!< 0x00000400 */
+#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed oscillator (HSI16) clock ready flag */
+#define RCC_CR_HSIASFS_Pos                  (11U)                              
+#define RCC_CR_HSIASFS_Msk                  (0x1U << RCC_CR_HSIASFS_Pos)       /*!< 0x00000800 */
+#define RCC_CR_HSIASFS                      RCC_CR_HSIASFS_Msk                 /*!< HSI16 Automatic Start from Stop */
+
+#define RCC_CR_HSEON_Pos                    (16U)                              
+#define RCC_CR_HSEON_Msk                    (0x1U << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
+#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed oscillator (HSE) clock enable */
+#define RCC_CR_HSERDY_Pos                   (17U)                              
+#define RCC_CR_HSERDY_Msk                   (0x1U << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
+#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed oscillator (HSE) clock ready */
+#define RCC_CR_HSEBYP_Pos                   (18U)                              
+#define RCC_CR_HSEBYP_Msk                   (0x1U << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed oscillator (HSE) clock bypass */
+#define RCC_CR_CSSON_Pos                    (19U)                              
+#define RCC_CR_CSSON_Msk                    (0x1U << RCC_CR_CSSON_Pos)         /*!< 0x00080000 */
+#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< HSE Clock Security System enable */
+
+#define RCC_CR_PLLON_Pos                    (24U)                              
+#define RCC_CR_PLLON_Msk                    (0x1U << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
+#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                   (25U)                              
+#define RCC_CR_PLLRDY_Msk                   (0x1U << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< System PLL clock ready */
+#define RCC_CR_PLLSAI1ON_Pos                (26U)                              
+#define RCC_CR_PLLSAI1ON_Msk                (0x1U << RCC_CR_PLLSAI1ON_Pos)     /*!< 0x04000000 */
+#define RCC_CR_PLLSAI1ON                    RCC_CR_PLLSAI1ON_Msk               /*!< SAI1 PLL enable */
+#define RCC_CR_PLLSAI1RDY_Pos               (27U)                              
+#define RCC_CR_PLLSAI1RDY_Msk               (0x1U << RCC_CR_PLLSAI1RDY_Pos)    /*!< 0x08000000 */
+#define RCC_CR_PLLSAI1RDY                   RCC_CR_PLLSAI1RDY_Msk              /*!< SAI1 PLL ready */
+#define RCC_CR_PLLSAI2ON_Pos                (28U)                              
+#define RCC_CR_PLLSAI2ON_Msk                (0x1U << RCC_CR_PLLSAI2ON_Pos)     /*!< 0x10000000 */
+#define RCC_CR_PLLSAI2ON                    RCC_CR_PLLSAI2ON_Msk               /*!< SAI2 PLL enable */
+#define RCC_CR_PLLSAI2RDY_Pos               (29U)                              
+#define RCC_CR_PLLSAI2RDY_Msk               (0x1U << RCC_CR_PLLSAI2RDY_Pos)    /*!< 0x20000000 */
+#define RCC_CR_PLLSAI2RDY                   RCC_CR_PLLSAI2RDY_Msk              /*!< SAI2 PLL ready */
+
+/********************  Bit definition for RCC_ICSCR register  ***************/
+/*!< MSICAL configuration */
+#define RCC_ICSCR_MSICAL_Pos                (0U)                               
+#define RCC_ICSCR_MSICAL_Msk                (0xFFU << RCC_ICSCR_MSICAL_Pos)    /*!< 0x000000FF */
+#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< MSICAL[7:0] bits */
+#define RCC_ICSCR_MSICAL_0                  (0x01U << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00000001 */
+#define RCC_ICSCR_MSICAL_1                  (0x02U << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00000002 */
+#define RCC_ICSCR_MSICAL_2                  (0x04U << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00000004 */
+#define RCC_ICSCR_MSICAL_3                  (0x08U << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00000008 */
+#define RCC_ICSCR_MSICAL_4                  (0x10U << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00000010 */
+#define RCC_ICSCR_MSICAL_5                  (0x20U << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00000020 */
+#define RCC_ICSCR_MSICAL_6                  (0x40U << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00000040 */
+#define RCC_ICSCR_MSICAL_7                  (0x80U << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00000080 */
+
+/*!< MSITRIM configuration */
+#define RCC_ICSCR_MSITRIM_Pos               (8U)                               
+#define RCC_ICSCR_MSITRIM_Msk               (0xFFU << RCC_ICSCR_MSITRIM_Pos)   /*!< 0x0000FF00 */
+#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< MSITRIM[7:0] bits */
+#define RCC_ICSCR_MSITRIM_0                 (0x01U << RCC_ICSCR_MSITRIM_Pos)   /*!< 0x00000100 */
+#define RCC_ICSCR_MSITRIM_1                 (0x02U << RCC_ICSCR_MSITRIM_Pos)   /*!< 0x00000200 */
+#define RCC_ICSCR_MSITRIM_2                 (0x04U << RCC_ICSCR_MSITRIM_Pos)   /*!< 0x00000400 */
+#define RCC_ICSCR_MSITRIM_3                 (0x08U << RCC_ICSCR_MSITRIM_Pos)   /*!< 0x00000800 */
+#define RCC_ICSCR_MSITRIM_4                 (0x10U << RCC_ICSCR_MSITRIM_Pos)   /*!< 0x00001000 */
+#define RCC_ICSCR_MSITRIM_5                 (0x20U << RCC_ICSCR_MSITRIM_Pos)   /*!< 0x00002000 */
+#define RCC_ICSCR_MSITRIM_6                 (0x40U << RCC_ICSCR_MSITRIM_Pos)   /*!< 0x00004000 */
+#define RCC_ICSCR_MSITRIM_7                 (0x80U << RCC_ICSCR_MSITRIM_Pos)   /*!< 0x00008000 */
+
+/*!< HSICAL configuration */
+#define RCC_ICSCR_HSICAL_Pos                (16U)                              
+#define RCC_ICSCR_HSICAL_Msk                (0xFFU << RCC_ICSCR_HSICAL_Pos)    /*!< 0x00FF0000 */
+#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< HSICAL[7:0] bits */
+#define RCC_ICSCR_HSICAL_0                  (0x01U << RCC_ICSCR_HSICAL_Pos)    /*!< 0x00010000 */
+#define RCC_ICSCR_HSICAL_1                  (0x02U << RCC_ICSCR_HSICAL_Pos)    /*!< 0x00020000 */
+#define RCC_ICSCR_HSICAL_2                  (0x04U << RCC_ICSCR_HSICAL_Pos)    /*!< 0x00040000 */
+#define RCC_ICSCR_HSICAL_3                  (0x08U << RCC_ICSCR_HSICAL_Pos)    /*!< 0x00080000 */
+#define RCC_ICSCR_HSICAL_4                  (0x10U << RCC_ICSCR_HSICAL_Pos)    /*!< 0x00100000 */
+#define RCC_ICSCR_HSICAL_5                  (0x20U << RCC_ICSCR_HSICAL_Pos)    /*!< 0x00200000 */
+#define RCC_ICSCR_HSICAL_6                  (0x40U << RCC_ICSCR_HSICAL_Pos)    /*!< 0x00400000 */
+#define RCC_ICSCR_HSICAL_7                  (0x80U << RCC_ICSCR_HSICAL_Pos)    /*!< 0x00800000 */
+
+/*!< HSITRIM configuration */
+#define RCC_ICSCR_HSITRIM_Pos               (24U)                              
+#define RCC_ICSCR_HSITRIM_Msk               (0x1FU << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x1F000000 */
+#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< HSITRIM[4:0] bits */
+#define RCC_ICSCR_HSITRIM_0                 (0x01U << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x01000000 */
+#define RCC_ICSCR_HSITRIM_1                 (0x02U << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x02000000 */
+#define RCC_ICSCR_HSITRIM_2                 (0x04U << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x04000000 */
+#define RCC_ICSCR_HSITRIM_3                 (0x08U << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x08000000 */
+#define RCC_ICSCR_HSITRIM_4                 (0x10U << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x10000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                     (0U)                               
+#define RCC_CFGR_SW_Msk                     (0x3U << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
+#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                       (0x1U << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                       (0x2U << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI oscillator selection as system clock */
+#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI16 oscillator selection as system clock */
+#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE oscillator selection as system clock */
+#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                    (2U)                               
+#define RCC_CFGR_SWS_Msk                    (0x3U << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
+#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                      (0x1U << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                      (0x2U << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI16 oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos                   (4U)                               
+#define RCC_CFGR_HPRE_Msk                   (0xFU << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                     (0x1U << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                     (0x2U << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                     (0x4U << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                     (0x8U << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos                  (8U)                               
+#define RCC_CFGR_PPRE1_Msk                  (0x7U << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE1_0                    (0x1U << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1                    (0x2U << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2                    (0x4U << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos                  (11U)                              
+#define RCC_CFGR_PPRE2_Msk                  (0x7U << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                    (0x1U << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1                    (0x2U << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2                    (0x4U << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos               (15U)                              
+#define RCC_CFGR_STOPWUCK_Msk               (0x1U << RCC_CFGR_STOPWUCK_Pos)    /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK                   RCC_CFGR_STOPWUCK_Msk              /*!< Wake Up from stop and CSS backup clock selection */
+
+/*!< MCOSEL configuration */
+#define RCC_CFGR_MCOSEL_Pos                 (24U)                              
+#define RCC_CFGR_MCOSEL_Msk                 (0x7U << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCOSEL [2:0] bits (Clock output selection) */
+#define RCC_CFGR_MCOSEL_0                   (0x1U << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1                   (0x2U << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2                   (0x4U << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
+
+#define RCC_CFGR_MCOPRE_Pos                 (28U)                              
+#define RCC_CFGR_MCOPRE_Msk                 (0x7U << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0                   (0x1U << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1                   (0x2U << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2                   (0x4U << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
+ 
+#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
+ 
+/* Legacy aliases */
+#define  RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE
+#define  RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1
+#define  RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2
+#define  RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4
+#define  RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8
+#define  RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define RCC_PLLCFGR_PLLSRC_Pos              (0U)                               
+#define RCC_PLLCFGR_PLLSRC_Msk              (0x3U << RCC_PLLCFGR_PLLSRC_Pos)   /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC                  RCC_PLLCFGR_PLLSRC_Msk             
+
+#define RCC_PLLCFGR_PLLSRC_MSI_Pos          (0U)                               
+#define RCC_PLLCFGR_PLLSRC_MSI_Msk          (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLSRC_MSI              RCC_PLLCFGR_PLLSRC_MSI_Msk         /*!< MSI oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSI_Pos          (1U)                               
+#define RCC_PLLCFGR_PLLSRC_HSI_Msk          (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLSRC_HSI              RCC_PLLCFGR_PLLSRC_HSI_Msk         /*!< HSI16 oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos          (0U)                               
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk          (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC_HSE              RCC_PLLCFGR_PLLSRC_HSE_Msk         /*!< HSE oscillator source clock selected */
+
+#define RCC_PLLCFGR_PLLM_Pos                (4U)                               
+#define RCC_PLLCFGR_PLLM_Msk                (0x7U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000070 */
+#define RCC_PLLCFGR_PLLM                    RCC_PLLCFGR_PLLM_Msk               
+#define RCC_PLLCFGR_PLLM_0                  (0x1U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_1                  (0x2U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLLM_2                  (0x4U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000040 */
+
+#define RCC_PLLCFGR_PLLN_Pos                (8U)                               
+#define RCC_PLLCFGR_PLLN_Msk                (0x7FU << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007F00 */
+#define RCC_PLLCFGR_PLLN                    RCC_PLLCFGR_PLLN_Msk               
+#define RCC_PLLCFGR_PLLN_0                  (0x01U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_1                  (0x02U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_2                  (0x04U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_3                  (0x08U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_4                  (0x10U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_5                  (0x20U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_6                  (0x40U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLPEN_Pos              (16U)                              
+#define RCC_PLLCFGR_PLLPEN_Msk              (0x1U << RCC_PLLCFGR_PLLPEN_Pos)   /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLPEN                  RCC_PLLCFGR_PLLPEN_Msk             
+#define RCC_PLLCFGR_PLLP_Pos                (17U)                              
+#define RCC_PLLCFGR_PLLP_Msk                (0x1U << RCC_PLLCFGR_PLLP_Pos)     /*!< 0x00020000 */
+#define RCC_PLLCFGR_PLLP                    RCC_PLLCFGR_PLLP_Msk               
+#define RCC_PLLCFGR_PLLQEN_Pos              (20U)                              
+#define RCC_PLLCFGR_PLLQEN_Msk              (0x1U << RCC_PLLCFGR_PLLQEN_Pos)   /*!< 0x00100000 */
+#define RCC_PLLCFGR_PLLQEN                  RCC_PLLCFGR_PLLQEN_Msk             
+
+#define RCC_PLLCFGR_PLLQ_Pos                (21U)                              
+#define RCC_PLLCFGR_PLLQ_Msk                (0x3U << RCC_PLLCFGR_PLLQ_Pos)     /*!< 0x00600000 */
+#define RCC_PLLCFGR_PLLQ                    RCC_PLLCFGR_PLLQ_Msk               
+#define RCC_PLLCFGR_PLLQ_0                  (0x1U << RCC_PLLCFGR_PLLQ_Pos)     /*!< 0x00200000 */
+#define RCC_PLLCFGR_PLLQ_1                  (0x2U << RCC_PLLCFGR_PLLQ_Pos)     /*!< 0x00400000 */
+
+#define RCC_PLLCFGR_PLLREN_Pos              (24U)                              
+#define RCC_PLLCFGR_PLLREN_Msk              (0x1U << RCC_PLLCFGR_PLLREN_Pos)   /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLREN                  RCC_PLLCFGR_PLLREN_Msk             
+#define RCC_PLLCFGR_PLLR_Pos                (25U)                              
+#define RCC_PLLCFGR_PLLR_Msk                (0x3U << RCC_PLLCFGR_PLLR_Pos)     /*!< 0x06000000 */
+#define RCC_PLLCFGR_PLLR                    RCC_PLLCFGR_PLLR_Msk               
+#define RCC_PLLCFGR_PLLR_0                  (0x1U << RCC_PLLCFGR_PLLR_Pos)     /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLR_1                  (0x2U << RCC_PLLCFGR_PLLR_Pos)     /*!< 0x04000000 */
+
+/********************  Bit definition for RCC_PLLSAI1CFGR register  ************/
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos        (8U)                               
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk        (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N            RCC_PLLSAI1CFGR_PLLSAI1N_Msk       
+#define RCC_PLLSAI1CFGR_PLLSAI1N_0          (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_1          (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_2          (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_3          (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_4          (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_5          (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_6          (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos      (16U)                              
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk      (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN          RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk     
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos        (17U)                              
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk        (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1P            RCC_PLLSAI1CFGR_PLLSAI1P_Msk       
+
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos      (20U)                              
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk      (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN          RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk     
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos        (21U)                              
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk        (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q            RCC_PLLSAI1CFGR_PLLSAI1Q_Msk       
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_0          (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_1          (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos      (24U)                              
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk      (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1REN          RCC_PLLSAI1CFGR_PLLSAI1REN_Msk     
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos        (25U)                              
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk        (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R            RCC_PLLSAI1CFGR_PLLSAI1R_Msk       
+#define RCC_PLLSAI1CFGR_PLLSAI1R_0          (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R_1          (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for RCC_PLLSAI2CFGR register  ************/
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos        (8U)                               
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk        (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N            RCC_PLLSAI2CFGR_PLLSAI2N_Msk       
+#define RCC_PLLSAI2CFGR_PLLSAI2N_0          (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_1          (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_2          (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_3          (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_4          (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_5          (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_6          (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos      (16U)                              
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk      (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN          RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk     
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos        (17U)                              
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk        (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2P            RCC_PLLSAI2CFGR_PLLSAI2P_Msk       
+
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos      (24U)                              
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk      (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2REN          RCC_PLLSAI2CFGR_PLLSAI2REN_Msk     
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos        (25U)                              
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk        (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R            RCC_PLLSAI2CFGR_PLLSAI2R_Msk       
+#define RCC_PLLSAI2CFGR_PLLSAI2R_0          (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R_1          (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos               (0U)                               
+#define RCC_CIER_LSIRDYIE_Msk               (0x1U << RCC_CIER_LSIRDYIE_Pos)    /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                   RCC_CIER_LSIRDYIE_Msk              
+#define RCC_CIER_LSERDYIE_Pos               (1U)                               
+#define RCC_CIER_LSERDYIE_Msk               (0x1U << RCC_CIER_LSERDYIE_Pos)    /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                   RCC_CIER_LSERDYIE_Msk              
+#define RCC_CIER_MSIRDYIE_Pos               (2U)                               
+#define RCC_CIER_MSIRDYIE_Msk               (0x1U << RCC_CIER_MSIRDYIE_Pos)    /*!< 0x00000004 */
+#define RCC_CIER_MSIRDYIE                   RCC_CIER_MSIRDYIE_Msk              
+#define RCC_CIER_HSIRDYIE_Pos               (3U)                               
+#define RCC_CIER_HSIRDYIE_Msk               (0x1U << RCC_CIER_HSIRDYIE_Pos)    /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE                   RCC_CIER_HSIRDYIE_Msk              
+#define RCC_CIER_HSERDYIE_Pos               (4U)                               
+#define RCC_CIER_HSERDYIE_Msk               (0x1U << RCC_CIER_HSERDYIE_Pos)    /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE                   RCC_CIER_HSERDYIE_Msk              
+#define RCC_CIER_PLLRDYIE_Pos               (5U)                               
+#define RCC_CIER_PLLRDYIE_Msk               (0x1U << RCC_CIER_PLLRDYIE_Pos)    /*!< 0x00000020 */
+#define RCC_CIER_PLLRDYIE                   RCC_CIER_PLLRDYIE_Msk              
+#define RCC_CIER_PLLSAI1RDYIE_Pos           (6U)                               
+#define RCC_CIER_PLLSAI1RDYIE_Msk           (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLLSAI1RDYIE               RCC_CIER_PLLSAI1RDYIE_Msk          
+#define RCC_CIER_PLLSAI2RDYIE_Pos           (7U)                               
+#define RCC_CIER_PLLSAI2RDYIE_Msk           (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_PLLSAI2RDYIE               RCC_CIER_PLLSAI2RDYIE_Msk          
+#define RCC_CIER_LSECSSIE_Pos               (9U)                               
+#define RCC_CIER_LSECSSIE_Msk               (0x1U << RCC_CIER_LSECSSIE_Pos)    /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                   RCC_CIER_LSECSSIE_Msk              
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                (0U)                               
+#define RCC_CIFR_LSIRDYF_Msk                (0x1U << RCC_CIFR_LSIRDYF_Pos)     /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                    RCC_CIFR_LSIRDYF_Msk               
+#define RCC_CIFR_LSERDYF_Pos                (1U)                               
+#define RCC_CIFR_LSERDYF_Msk                (0x1U << RCC_CIFR_LSERDYF_Pos)     /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                    RCC_CIFR_LSERDYF_Msk               
+#define RCC_CIFR_MSIRDYF_Pos                (2U)                               
+#define RCC_CIFR_MSIRDYF_Msk                (0x1U << RCC_CIFR_MSIRDYF_Pos)     /*!< 0x00000004 */
+#define RCC_CIFR_MSIRDYF                    RCC_CIFR_MSIRDYF_Msk               
+#define RCC_CIFR_HSIRDYF_Pos                (3U)                               
+#define RCC_CIFR_HSIRDYF_Msk                (0x1U << RCC_CIFR_HSIRDYF_Pos)     /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF                    RCC_CIFR_HSIRDYF_Msk               
+#define RCC_CIFR_HSERDYF_Pos                (4U)                               
+#define RCC_CIFR_HSERDYF_Msk                (0x1U << RCC_CIFR_HSERDYF_Pos)     /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF                    RCC_CIFR_HSERDYF_Msk               
+#define RCC_CIFR_PLLRDYF_Pos                (5U)                               
+#define RCC_CIFR_PLLRDYF_Msk                (0x1U << RCC_CIFR_PLLRDYF_Pos)     /*!< 0x00000020 */
+#define RCC_CIFR_PLLRDYF                    RCC_CIFR_PLLRDYF_Msk               
+#define RCC_CIFR_PLLSAI1RDYF_Pos            (6U)                               
+#define RCC_CIFR_PLLSAI1RDYF_Msk            (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLSAI1RDYF                RCC_CIFR_PLLSAI1RDYF_Msk           
+#define RCC_CIFR_PLLSAI2RDYF_Pos            (7U)                               
+#define RCC_CIFR_PLLSAI2RDYF_Msk            (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_PLLSAI2RDYF                RCC_CIFR_PLLSAI2RDYF_Msk           
+#define RCC_CIFR_CSSF_Pos                   (8U)                               
+#define RCC_CIFR_CSSF_Msk                   (0x1U << RCC_CIFR_CSSF_Pos)        /*!< 0x00000100 */
+#define RCC_CIFR_CSSF                       RCC_CIFR_CSSF_Msk                  
+#define RCC_CIFR_LSECSSF_Pos                (9U)                               
+#define RCC_CIFR_LSECSSF_Msk                (0x1U << RCC_CIFR_LSECSSF_Pos)     /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                    RCC_CIFR_LSECSSF_Msk               
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                (0U)                               
+#define RCC_CICR_LSIRDYC_Msk                (0x1U << RCC_CICR_LSIRDYC_Pos)     /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                    RCC_CICR_LSIRDYC_Msk               
+#define RCC_CICR_LSERDYC_Pos                (1U)                               
+#define RCC_CICR_LSERDYC_Msk                (0x1U << RCC_CICR_LSERDYC_Pos)     /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                    RCC_CICR_LSERDYC_Msk               
+#define RCC_CICR_MSIRDYC_Pos                (2U)                               
+#define RCC_CICR_MSIRDYC_Msk                (0x1U << RCC_CICR_MSIRDYC_Pos)     /*!< 0x00000004 */
+#define RCC_CICR_MSIRDYC                    RCC_CICR_MSIRDYC_Msk               
+#define RCC_CICR_HSIRDYC_Pos                (3U)                               
+#define RCC_CICR_HSIRDYC_Msk                (0x1U << RCC_CICR_HSIRDYC_Pos)     /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC                    RCC_CICR_HSIRDYC_Msk               
+#define RCC_CICR_HSERDYC_Pos                (4U)                               
+#define RCC_CICR_HSERDYC_Msk                (0x1U << RCC_CICR_HSERDYC_Pos)     /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC                    RCC_CICR_HSERDYC_Msk               
+#define RCC_CICR_PLLRDYC_Pos                (5U)                               
+#define RCC_CICR_PLLRDYC_Msk                (0x1U << RCC_CICR_PLLRDYC_Pos)     /*!< 0x00000020 */
+#define RCC_CICR_PLLRDYC                    RCC_CICR_PLLRDYC_Msk               
+#define RCC_CICR_PLLSAI1RDYC_Pos            (6U)                               
+#define RCC_CICR_PLLSAI1RDYC_Msk            (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLSAI1RDYC                RCC_CICR_PLLSAI1RDYC_Msk           
+#define RCC_CICR_PLLSAI2RDYC_Pos            (7U)                               
+#define RCC_CICR_PLLSAI2RDYC_Msk            (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_PLLSAI2RDYC                RCC_CICR_PLLSAI2RDYC_Msk           
+#define RCC_CICR_CSSC_Pos                   (8U)                               
+#define RCC_CICR_CSSC_Msk                   (0x1U << RCC_CICR_CSSC_Pos)        /*!< 0x00000100 */
+#define RCC_CICR_CSSC                       RCC_CICR_CSSC_Msk                  
+#define RCC_CICR_LSECSSC_Pos                (9U)                               
+#define RCC_CICR_LSECSSC_Msk                (0x1U << RCC_CICR_LSECSSC_Pos)     /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                    RCC_CICR_LSECSSC_Msk               
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define RCC_AHB1RSTR_DMA1RST_Pos            (0U)                               
+#define RCC_AHB1RSTR_DMA1RST_Msk            (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                RCC_AHB1RSTR_DMA1RST_Msk           
+#define RCC_AHB1RSTR_DMA2RST_Pos            (1U)                               
+#define RCC_AHB1RSTR_DMA2RST_Msk            (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                RCC_AHB1RSTR_DMA2RST_Msk           
+#define RCC_AHB1RSTR_FLASHRST_Pos           (8U)                               
+#define RCC_AHB1RSTR_FLASHRST_Msk           (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_FLASHRST               RCC_AHB1RSTR_FLASHRST_Msk          
+#define RCC_AHB1RSTR_CRCRST_Pos             (12U)                              
+#define RCC_AHB1RSTR_CRCRST_Msk             (0x1U << RCC_AHB1RSTR_CRCRST_Pos)  /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST                 RCC_AHB1RSTR_CRCRST_Msk            
+#define RCC_AHB1RSTR_TSCRST_Pos             (16U)                              
+#define RCC_AHB1RSTR_TSCRST_Msk             (0x1U << RCC_AHB1RSTR_TSCRST_Pos)  /*!< 0x00010000 */
+#define RCC_AHB1RSTR_TSCRST                 RCC_AHB1RSTR_TSCRST_Msk            
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define RCC_AHB2RSTR_GPIOARST_Pos           (0U)                               
+#define RCC_AHB2RSTR_GPIOARST_Msk           (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_GPIOARST               RCC_AHB2RSTR_GPIOARST_Msk          
+#define RCC_AHB2RSTR_GPIOBRST_Pos           (1U)                               
+#define RCC_AHB2RSTR_GPIOBRST_Msk           (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB2RSTR_GPIOBRST               RCC_AHB2RSTR_GPIOBRST_Msk          
+#define RCC_AHB2RSTR_GPIOCRST_Pos           (2U)                               
+#define RCC_AHB2RSTR_GPIOCRST_Msk           (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB2RSTR_GPIOCRST               RCC_AHB2RSTR_GPIOCRST_Msk          
+#define RCC_AHB2RSTR_GPIODRST_Pos           (3U)                               
+#define RCC_AHB2RSTR_GPIODRST_Msk           (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB2RSTR_GPIODRST               RCC_AHB2RSTR_GPIODRST_Msk          
+#define RCC_AHB2RSTR_GPIOERST_Pos           (4U)                               
+#define RCC_AHB2RSTR_GPIOERST_Msk           (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB2RSTR_GPIOERST               RCC_AHB2RSTR_GPIOERST_Msk          
+#define RCC_AHB2RSTR_GPIOFRST_Pos           (5U)                               
+#define RCC_AHB2RSTR_GPIOFRST_Msk           (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB2RSTR_GPIOFRST               RCC_AHB2RSTR_GPIOFRST_Msk          
+#define RCC_AHB2RSTR_GPIOGRST_Pos           (6U)                               
+#define RCC_AHB2RSTR_GPIOGRST_Msk           (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_GPIOGRST               RCC_AHB2RSTR_GPIOGRST_Msk          
+#define RCC_AHB2RSTR_GPIOHRST_Pos           (7U)                               
+#define RCC_AHB2RSTR_GPIOHRST_Msk           (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_GPIOHRST               RCC_AHB2RSTR_GPIOHRST_Msk          
+#define RCC_AHB2RSTR_OTGFSRST_Pos           (12U)                              
+#define RCC_AHB2RSTR_OTGFSRST_Msk           (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTR_OTGFSRST               RCC_AHB2RSTR_OTGFSRST_Msk          
+#define RCC_AHB2RSTR_ADCRST_Pos             (13U)                              
+#define RCC_AHB2RSTR_ADCRST_Msk             (0x1U << RCC_AHB2RSTR_ADCRST_Pos)  /*!< 0x00002000 */
+#define RCC_AHB2RSTR_ADCRST                 RCC_AHB2RSTR_ADCRST_Msk            
+#define RCC_AHB2RSTR_AESRST_Pos             (16U)                              
+#define RCC_AHB2RSTR_AESRST_Msk             (0x1U << RCC_AHB2RSTR_AESRST_Pos)  /*!< 0x00010000 */
+#define RCC_AHB2RSTR_AESRST                 RCC_AHB2RSTR_AESRST_Msk            
+#define RCC_AHB2RSTR_RNGRST_Pos             (18U)                              
+#define RCC_AHB2RSTR_RNGRST_Msk             (0x1U << RCC_AHB2RSTR_RNGRST_Pos)  /*!< 0x00040000 */
+#define RCC_AHB2RSTR_RNGRST                 RCC_AHB2RSTR_RNGRST_Msk            
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+#define RCC_AHB3RSTR_FMCRST_Pos             (0U)                               
+#define RCC_AHB3RSTR_FMCRST_Msk             (0x1U << RCC_AHB3RSTR_FMCRST_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST                 RCC_AHB3RSTR_FMCRST_Msk            
+#define RCC_AHB3RSTR_QSPIRST_Pos            (8U)                               
+#define RCC_AHB3RSTR_QSPIRST_Msk            (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB3RSTR_QSPIRST                RCC_AHB3RSTR_QSPIRST_Msk           
+
+/********************  Bit definition for RCC_APB1RSTR1 register  **************/
+#define RCC_APB1RSTR1_TIM2RST_Pos           (0U)                               
+#define RCC_APB1RSTR1_TIM2RST_Msk           (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST               RCC_APB1RSTR1_TIM2RST_Msk          
+#define RCC_APB1RSTR1_TIM3RST_Pos           (1U)                               
+#define RCC_APB1RSTR1_TIM3RST_Msk           (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR1_TIM3RST               RCC_APB1RSTR1_TIM3RST_Msk          
+#define RCC_APB1RSTR1_TIM4RST_Pos           (2U)                               
+#define RCC_APB1RSTR1_TIM4RST_Msk           (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR1_TIM4RST               RCC_APB1RSTR1_TIM4RST_Msk          
+#define RCC_APB1RSTR1_TIM5RST_Pos           (3U)                               
+#define RCC_APB1RSTR1_TIM5RST_Msk           (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR1_TIM5RST               RCC_APB1RSTR1_TIM5RST_Msk          
+#define RCC_APB1RSTR1_TIM6RST_Pos           (4U)                               
+#define RCC_APB1RSTR1_TIM6RST_Msk           (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST               RCC_APB1RSTR1_TIM6RST_Msk          
+#define RCC_APB1RSTR1_TIM7RST_Pos           (5U)                               
+#define RCC_APB1RSTR1_TIM7RST_Msk           (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST               RCC_APB1RSTR1_TIM7RST_Msk          
+#define RCC_APB1RSTR1_LCDRST_Pos            (9U)                               
+#define RCC_APB1RSTR1_LCDRST_Msk            (0x1U << RCC_APB1RSTR1_LCDRST_Pos) /*!< 0x00000200 */
+#define RCC_APB1RSTR1_LCDRST                RCC_APB1RSTR1_LCDRST_Msk           
+#define RCC_APB1RSTR1_SPI2RST_Pos           (14U)                              
+#define RCC_APB1RSTR1_SPI2RST_Msk           (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR1_SPI2RST               RCC_APB1RSTR1_SPI2RST_Msk          
+#define RCC_APB1RSTR1_SPI3RST_Pos           (15U)                              
+#define RCC_APB1RSTR1_SPI3RST_Msk           (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST               RCC_APB1RSTR1_SPI3RST_Msk          
+#define RCC_APB1RSTR1_USART2RST_Pos         (17U)                              
+#define RCC_APB1RSTR1_USART2RST_Msk         (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST             RCC_APB1RSTR1_USART2RST_Msk        
+#define RCC_APB1RSTR1_USART3RST_Pos         (18U)                              
+#define RCC_APB1RSTR1_USART3RST_Msk         (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR1_USART3RST             RCC_APB1RSTR1_USART3RST_Msk        
+#define RCC_APB1RSTR1_UART4RST_Pos          (19U)                              
+#define RCC_APB1RSTR1_UART4RST_Msk          (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR1_UART4RST              RCC_APB1RSTR1_UART4RST_Msk         
+#define RCC_APB1RSTR1_UART5RST_Pos          (20U)                              
+#define RCC_APB1RSTR1_UART5RST_Msk          (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR1_UART5RST              RCC_APB1RSTR1_UART5RST_Msk         
+#define RCC_APB1RSTR1_I2C1RST_Pos           (21U)                              
+#define RCC_APB1RSTR1_I2C1RST_Msk           (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST               RCC_APB1RSTR1_I2C1RST_Msk          
+#define RCC_APB1RSTR1_I2C2RST_Pos           (22U)                              
+#define RCC_APB1RSTR1_I2C2RST_Msk           (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR1_I2C2RST               RCC_APB1RSTR1_I2C2RST_Msk          
+#define RCC_APB1RSTR1_I2C3RST_Pos           (23U)                              
+#define RCC_APB1RSTR1_I2C3RST_Msk           (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR1_I2C3RST               RCC_APB1RSTR1_I2C3RST_Msk          
+#define RCC_APB1RSTR1_CAN1RST_Pos           (25U)                              
+#define RCC_APB1RSTR1_CAN1RST_Msk           (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR1_CAN1RST               RCC_APB1RSTR1_CAN1RST_Msk          
+#define RCC_APB1RSTR1_PWRRST_Pos            (28U)                              
+#define RCC_APB1RSTR1_PWRRST_Msk            (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR1_PWRRST                RCC_APB1RSTR1_PWRRST_Msk           
+#define RCC_APB1RSTR1_DAC1RST_Pos           (29U)                              
+#define RCC_APB1RSTR1_DAC1RST_Msk           (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR1_DAC1RST               RCC_APB1RSTR1_DAC1RST_Msk          
+#define RCC_APB1RSTR1_OPAMPRST_Pos          (30U)                              
+#define RCC_APB1RSTR1_OPAMPRST_Msk          (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR1_OPAMPRST              RCC_APB1RSTR1_OPAMPRST_Msk         
+#define RCC_APB1RSTR1_LPTIM1RST_Pos         (31U)                              
+#define RCC_APB1RSTR1_LPTIM1RST_Msk         (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR1_LPTIM1RST             RCC_APB1RSTR1_LPTIM1RST_Msk        
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1RSTR2_LPUART1RST_Pos        (0U)                               
+#define RCC_APB1RSTR2_LPUART1RST_Msk        (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR2_LPUART1RST            RCC_APB1RSTR2_LPUART1RST_Msk       
+#define RCC_APB1RSTR2_SWPMI1RST_Pos         (2U)                               
+#define RCC_APB1RSTR2_SWPMI1RST_Msk         (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR2_SWPMI1RST             RCC_APB1RSTR2_SWPMI1RST_Msk        
+#define RCC_APB1RSTR2_LPTIM2RST_Pos         (5U)                               
+#define RCC_APB1RSTR2_LPTIM2RST_Msk         (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR2_LPTIM2RST             RCC_APB1RSTR2_LPTIM2RST_Msk        
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)                               
+#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         
+#define RCC_APB2RSTR_SDMMC1RST_Pos          (10U)                              
+#define RCC_APB2RSTR_SDMMC1RST_Msk          (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_SDMMC1RST              RCC_APB2RSTR_SDMMC1RST_Msk         
+#define RCC_APB2RSTR_TIM1RST_Pos            (11U)                              
+#define RCC_APB2RSTR_TIM1RST_Msk            (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST                RCC_APB2RSTR_TIM1RST_Msk           
+#define RCC_APB2RSTR_SPI1RST_Pos            (12U)                              
+#define RCC_APB2RSTR_SPI1RST_Msk            (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           
+#define RCC_APB2RSTR_TIM8RST_Pos            (13U)                              
+#define RCC_APB2RSTR_TIM8RST_Msk            (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_TIM8RST                RCC_APB2RSTR_TIM8RST_Msk           
+#define RCC_APB2RSTR_USART1RST_Pos          (14U)                              
+#define RCC_APB2RSTR_USART1RST_Msk          (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         
+#define RCC_APB2RSTR_TIM15RST_Pos           (16U)                              
+#define RCC_APB2RSTR_TIM15RST_Msk           (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST               RCC_APB2RSTR_TIM15RST_Msk          
+#define RCC_APB2RSTR_TIM16RST_Pos           (17U)                              
+#define RCC_APB2RSTR_TIM16RST_Msk           (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST               RCC_APB2RSTR_TIM16RST_Msk          
+#define RCC_APB2RSTR_TIM17RST_Pos           (18U)                              
+#define RCC_APB2RSTR_TIM17RST_Msk           (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST               RCC_APB2RSTR_TIM17RST_Msk          
+#define RCC_APB2RSTR_SAI1RST_Pos            (21U)                              
+#define RCC_APB2RSTR_SAI1RST_Msk            (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST                RCC_APB2RSTR_SAI1RST_Msk           
+#define RCC_APB2RSTR_SAI2RST_Pos            (22U)                              
+#define RCC_APB2RSTR_SAI2RST_Msk            (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI2RST                RCC_APB2RSTR_SAI2RST_Msk           
+#define RCC_APB2RSTR_DFSDM1RST_Pos          (24U)                              
+#define RCC_APB2RSTR_DFSDM1RST_Msk          (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_DFSDM1RST              RCC_APB2RSTR_DFSDM1RST_Msk         
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos              (0U)                               
+#define RCC_AHB1ENR_DMA1EN_Msk              (0x1U << RCC_AHB1ENR_DMA1EN_Pos)   /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                  RCC_AHB1ENR_DMA1EN_Msk             
+#define RCC_AHB1ENR_DMA2EN_Pos              (1U)                               
+#define RCC_AHB1ENR_DMA2EN_Msk              (0x1U << RCC_AHB1ENR_DMA2EN_Pos)   /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                  RCC_AHB1ENR_DMA2EN_Msk             
+#define RCC_AHB1ENR_FLASHEN_Pos             (8U)                               
+#define RCC_AHB1ENR_FLASHEN_Msk             (0x1U << RCC_AHB1ENR_FLASHEN_Pos)  /*!< 0x00000100 */
+#define RCC_AHB1ENR_FLASHEN                 RCC_AHB1ENR_FLASHEN_Msk            
+#define RCC_AHB1ENR_CRCEN_Pos               (12U)                              
+#define RCC_AHB1ENR_CRCEN_Msk               (0x1U << RCC_AHB1ENR_CRCEN_Pos)    /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN                   RCC_AHB1ENR_CRCEN_Msk              
+#define RCC_AHB1ENR_TSCEN_Pos               (16U)                              
+#define RCC_AHB1ENR_TSCEN_Msk               (0x1U << RCC_AHB1ENR_TSCEN_Pos)    /*!< 0x00010000 */
+#define RCC_AHB1ENR_TSCEN                   RCC_AHB1ENR_TSCEN_Msk              
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_GPIOAEN_Pos             (0U)                               
+#define RCC_AHB2ENR_GPIOAEN_Msk             (0x1U << RCC_AHB2ENR_GPIOAEN_Pos)  /*!< 0x00000001 */
+#define RCC_AHB2ENR_GPIOAEN                 RCC_AHB2ENR_GPIOAEN_Msk            
+#define RCC_AHB2ENR_GPIOBEN_Pos             (1U)                               
+#define RCC_AHB2ENR_GPIOBEN_Msk             (0x1U << RCC_AHB2ENR_GPIOBEN_Pos)  /*!< 0x00000002 */
+#define RCC_AHB2ENR_GPIOBEN                 RCC_AHB2ENR_GPIOBEN_Msk            
+#define RCC_AHB2ENR_GPIOCEN_Pos             (2U)                               
+#define RCC_AHB2ENR_GPIOCEN_Msk             (0x1U << RCC_AHB2ENR_GPIOCEN_Pos)  /*!< 0x00000004 */
+#define RCC_AHB2ENR_GPIOCEN                 RCC_AHB2ENR_GPIOCEN_Msk            
+#define RCC_AHB2ENR_GPIODEN_Pos             (3U)                               
+#define RCC_AHB2ENR_GPIODEN_Msk             (0x1U << RCC_AHB2ENR_GPIODEN_Pos)  /*!< 0x00000008 */
+#define RCC_AHB2ENR_GPIODEN                 RCC_AHB2ENR_GPIODEN_Msk            
+#define RCC_AHB2ENR_GPIOEEN_Pos             (4U)                               
+#define RCC_AHB2ENR_GPIOEEN_Msk             (0x1U << RCC_AHB2ENR_GPIOEEN_Pos)  /*!< 0x00000010 */
+#define RCC_AHB2ENR_GPIOEEN                 RCC_AHB2ENR_GPIOEEN_Msk            
+#define RCC_AHB2ENR_GPIOFEN_Pos             (5U)                               
+#define RCC_AHB2ENR_GPIOFEN_Msk             (0x1U << RCC_AHB2ENR_GPIOFEN_Pos)  /*!< 0x00000020 */
+#define RCC_AHB2ENR_GPIOFEN                 RCC_AHB2ENR_GPIOFEN_Msk            
+#define RCC_AHB2ENR_GPIOGEN_Pos             (6U)                               
+#define RCC_AHB2ENR_GPIOGEN_Msk             (0x1U << RCC_AHB2ENR_GPIOGEN_Pos)  /*!< 0x00000040 */
+#define RCC_AHB2ENR_GPIOGEN                 RCC_AHB2ENR_GPIOGEN_Msk            
+#define RCC_AHB2ENR_GPIOHEN_Pos             (7U)                               
+#define RCC_AHB2ENR_GPIOHEN_Msk             (0x1U << RCC_AHB2ENR_GPIOHEN_Pos)  /*!< 0x00000080 */
+#define RCC_AHB2ENR_GPIOHEN                 RCC_AHB2ENR_GPIOHEN_Msk            
+#define RCC_AHB2ENR_OTGFSEN_Pos             (12U)                              
+#define RCC_AHB2ENR_OTGFSEN_Msk             (0x1U << RCC_AHB2ENR_OTGFSEN_Pos)  /*!< 0x00001000 */
+#define RCC_AHB2ENR_OTGFSEN                 RCC_AHB2ENR_OTGFSEN_Msk            
+#define RCC_AHB2ENR_ADCEN_Pos               (13U)                              
+#define RCC_AHB2ENR_ADCEN_Msk               (0x1U << RCC_AHB2ENR_ADCEN_Pos)    /*!< 0x00002000 */
+#define RCC_AHB2ENR_ADCEN                   RCC_AHB2ENR_ADCEN_Msk              
+#define RCC_AHB2ENR_AESEN_Pos               (16U)                              
+#define RCC_AHB2ENR_AESEN_Msk               (0x1U << RCC_AHB2ENR_AESEN_Pos)    /*!< 0x00010000 */
+#define RCC_AHB2ENR_AESEN                   RCC_AHB2ENR_AESEN_Msk              
+#define RCC_AHB2ENR_RNGEN_Pos               (18U)                              
+#define RCC_AHB2ENR_RNGEN_Msk               (0x1U << RCC_AHB2ENR_RNGEN_Pos)    /*!< 0x00040000 */
+#define RCC_AHB2ENR_RNGEN                   RCC_AHB2ENR_RNGEN_Msk              
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+#define RCC_AHB3ENR_FMCEN_Pos               (0U)                               
+#define RCC_AHB3ENR_FMCEN_Msk               (0x1U << RCC_AHB3ENR_FMCEN_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN                   RCC_AHB3ENR_FMCEN_Msk              
+#define RCC_AHB3ENR_QSPIEN_Pos              (8U)                               
+#define RCC_AHB3ENR_QSPIEN_Msk              (0x1U << RCC_AHB3ENR_QSPIEN_Pos)   /*!< 0x00000100 */
+#define RCC_AHB3ENR_QSPIEN                  RCC_AHB3ENR_QSPIEN_Msk             
+
+/********************  Bit definition for RCC_APB1ENR1 register  ***************/
+#define RCC_APB1ENR1_TIM2EN_Pos             (0U)                               
+#define RCC_APB1ENR1_TIM2EN_Msk             (0x1U << RCC_APB1ENR1_TIM2EN_Pos)  /*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN                 RCC_APB1ENR1_TIM2EN_Msk            
+#define RCC_APB1ENR1_TIM3EN_Pos             (1U)                               
+#define RCC_APB1ENR1_TIM3EN_Msk             (0x1U << RCC_APB1ENR1_TIM3EN_Pos)  /*!< 0x00000002 */
+#define RCC_APB1ENR1_TIM3EN                 RCC_APB1ENR1_TIM3EN_Msk            
+#define RCC_APB1ENR1_TIM4EN_Pos             (2U)                               
+#define RCC_APB1ENR1_TIM4EN_Msk             (0x1U << RCC_APB1ENR1_TIM4EN_Pos)  /*!< 0x00000004 */
+#define RCC_APB1ENR1_TIM4EN                 RCC_APB1ENR1_TIM4EN_Msk            
+#define RCC_APB1ENR1_TIM5EN_Pos             (3U)                               
+#define RCC_APB1ENR1_TIM5EN_Msk             (0x1U << RCC_APB1ENR1_TIM5EN_Pos)  /*!< 0x00000008 */
+#define RCC_APB1ENR1_TIM5EN                 RCC_APB1ENR1_TIM5EN_Msk            
+#define RCC_APB1ENR1_TIM6EN_Pos             (4U)                               
+#define RCC_APB1ENR1_TIM6EN_Msk             (0x1U << RCC_APB1ENR1_TIM6EN_Pos)  /*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN                 RCC_APB1ENR1_TIM6EN_Msk            
+#define RCC_APB1ENR1_TIM7EN_Pos             (5U)                               
+#define RCC_APB1ENR1_TIM7EN_Msk             (0x1U << RCC_APB1ENR1_TIM7EN_Pos)  /*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN                 RCC_APB1ENR1_TIM7EN_Msk            
+#define RCC_APB1ENR1_LCDEN_Pos              (9U)                               
+#define RCC_APB1ENR1_LCDEN_Msk              (0x1U << RCC_APB1ENR1_LCDEN_Pos)   /*!< 0x00000200 */
+#define RCC_APB1ENR1_LCDEN                  RCC_APB1ENR1_LCDEN_Msk             
+#define RCC_APB1ENR1_WWDGEN_Pos             (11U)                              
+#define RCC_APB1ENR1_WWDGEN_Msk             (0x1U << RCC_APB1ENR1_WWDGEN_Pos)  /*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN                 RCC_APB1ENR1_WWDGEN_Msk            
+#define RCC_APB1ENR1_SPI2EN_Pos             (14U)                              
+#define RCC_APB1ENR1_SPI2EN_Msk             (0x1U << RCC_APB1ENR1_SPI2EN_Pos)  /*!< 0x00004000 */
+#define RCC_APB1ENR1_SPI2EN                 RCC_APB1ENR1_SPI2EN_Msk            
+#define RCC_APB1ENR1_SPI3EN_Pos             (15U)                              
+#define RCC_APB1ENR1_SPI3EN_Msk             (0x1U << RCC_APB1ENR1_SPI3EN_Pos)  /*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN                 RCC_APB1ENR1_SPI3EN_Msk            
+#define RCC_APB1ENR1_USART2EN_Pos           (17U)                              
+#define RCC_APB1ENR1_USART2EN_Msk           (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN               RCC_APB1ENR1_USART2EN_Msk          
+#define RCC_APB1ENR1_USART3EN_Pos           (18U)                              
+#define RCC_APB1ENR1_USART3EN_Msk           (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR1_USART3EN               RCC_APB1ENR1_USART3EN_Msk          
+#define RCC_APB1ENR1_UART4EN_Pos            (19U)                              
+#define RCC_APB1ENR1_UART4EN_Msk            (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR1_UART4EN                RCC_APB1ENR1_UART4EN_Msk           
+#define RCC_APB1ENR1_UART5EN_Pos            (20U)                              
+#define RCC_APB1ENR1_UART5EN_Msk            (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR1_UART5EN                RCC_APB1ENR1_UART5EN_Msk           
+#define RCC_APB1ENR1_I2C1EN_Pos             (21U)                              
+#define RCC_APB1ENR1_I2C1EN_Msk             (0x1U << RCC_APB1ENR1_I2C1EN_Pos)  /*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN                 RCC_APB1ENR1_I2C1EN_Msk            
+#define RCC_APB1ENR1_I2C2EN_Pos             (22U)                              
+#define RCC_APB1ENR1_I2C2EN_Msk             (0x1U << RCC_APB1ENR1_I2C2EN_Pos)  /*!< 0x00400000 */
+#define RCC_APB1ENR1_I2C2EN                 RCC_APB1ENR1_I2C2EN_Msk            
+#define RCC_APB1ENR1_I2C3EN_Pos             (23U)                              
+#define RCC_APB1ENR1_I2C3EN_Msk             (0x1U << RCC_APB1ENR1_I2C3EN_Pos)  /*!< 0x00800000 */
+#define RCC_APB1ENR1_I2C3EN                 RCC_APB1ENR1_I2C3EN_Msk            
+#define RCC_APB1ENR1_CAN1EN_Pos             (25U)                              
+#define RCC_APB1ENR1_CAN1EN_Msk             (0x1U << RCC_APB1ENR1_CAN1EN_Pos)  /*!< 0x02000000 */
+#define RCC_APB1ENR1_CAN1EN                 RCC_APB1ENR1_CAN1EN_Msk            
+#define RCC_APB1ENR1_PWREN_Pos              (28U)                              
+#define RCC_APB1ENR1_PWREN_Msk              (0x1U << RCC_APB1ENR1_PWREN_Pos)   /*!< 0x10000000 */
+#define RCC_APB1ENR1_PWREN                  RCC_APB1ENR1_PWREN_Msk             
+#define RCC_APB1ENR1_DAC1EN_Pos             (29U)                              
+#define RCC_APB1ENR1_DAC1EN_Msk             (0x1U << RCC_APB1ENR1_DAC1EN_Pos)  /*!< 0x20000000 */
+#define RCC_APB1ENR1_DAC1EN                 RCC_APB1ENR1_DAC1EN_Msk            
+#define RCC_APB1ENR1_OPAMPEN_Pos            (30U)                              
+#define RCC_APB1ENR1_OPAMPEN_Msk            (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR1_OPAMPEN                RCC_APB1ENR1_OPAMPEN_Msk           
+#define RCC_APB1ENR1_LPTIM1EN_Pos           (31U)                              
+#define RCC_APB1ENR1_LPTIM1EN_Msk           (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR1_LPTIM1EN               RCC_APB1ENR1_LPTIM1EN_Msk          
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1ENR2_LPUART1EN_Pos          (0U)                               
+#define RCC_APB1ENR2_LPUART1EN_Msk          (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR2_LPUART1EN              RCC_APB1ENR2_LPUART1EN_Msk         
+#define RCC_APB1ENR2_SWPMI1EN_Pos           (2U)                               
+#define RCC_APB1ENR2_SWPMI1EN_Msk           (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR2_SWPMI1EN               RCC_APB1ENR2_SWPMI1EN_Msk          
+#define RCC_APB1ENR2_LPTIM2EN_Pos           (5U)                               
+#define RCC_APB1ENR2_LPTIM2EN_Msk           (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR2_LPTIM2EN               RCC_APB1ENR2_LPTIM2EN_Msk          
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)                               
+#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           
+#define RCC_APB2ENR_FWEN_Pos                (7U)                               
+#define RCC_APB2ENR_FWEN_Msk                (0x1U << RCC_APB2ENR_FWEN_Pos)     /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN                    RCC_APB2ENR_FWEN_Msk               
+#define RCC_APB2ENR_SDMMC1EN_Pos            (10U)                              
+#define RCC_APB2ENR_SDMMC1EN_Msk            (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_SDMMC1EN                RCC_APB2ENR_SDMMC1EN_Msk           
+#define RCC_APB2ENR_TIM1EN_Pos              (11U)                              
+#define RCC_APB2ENR_TIM1EN_Msk              (0x1U << RCC_APB2ENR_TIM1EN_Pos)   /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN                  RCC_APB2ENR_TIM1EN_Msk             
+#define RCC_APB2ENR_SPI1EN_Pos              (12U)                              
+#define RCC_APB2ENR_SPI1EN_Msk              (0x1U << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             
+#define RCC_APB2ENR_TIM8EN_Pos              (13U)                              
+#define RCC_APB2ENR_TIM8EN_Msk              (0x1U << RCC_APB2ENR_TIM8EN_Pos)   /*!< 0x00002000 */
+#define RCC_APB2ENR_TIM8EN                  RCC_APB2ENR_TIM8EN_Msk             
+#define RCC_APB2ENR_USART1EN_Pos            (14U)                              
+#define RCC_APB2ENR_USART1EN_Msk            (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           
+#define RCC_APB2ENR_TIM15EN_Pos             (16U)                              
+#define RCC_APB2ENR_TIM15EN_Msk             (0x1U << RCC_APB2ENR_TIM15EN_Pos)  /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                 RCC_APB2ENR_TIM15EN_Msk            
+#define RCC_APB2ENR_TIM16EN_Pos             (17U)                              
+#define RCC_APB2ENR_TIM16EN_Msk             (0x1U << RCC_APB2ENR_TIM16EN_Pos)  /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                 RCC_APB2ENR_TIM16EN_Msk            
+#define RCC_APB2ENR_TIM17EN_Pos             (18U)                              
+#define RCC_APB2ENR_TIM17EN_Msk             (0x1U << RCC_APB2ENR_TIM17EN_Pos)  /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                 RCC_APB2ENR_TIM17EN_Msk            
+#define RCC_APB2ENR_SAI1EN_Pos              (21U)                              
+#define RCC_APB2ENR_SAI1EN_Msk              (0x1U << RCC_APB2ENR_SAI1EN_Pos)   /*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN                  RCC_APB2ENR_SAI1EN_Msk             
+#define RCC_APB2ENR_SAI2EN_Pos              (22U)                              
+#define RCC_APB2ENR_SAI2EN_Msk              (0x1U << RCC_APB2ENR_SAI2EN_Pos)   /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI2EN                  RCC_APB2ENR_SAI2EN_Msk             
+#define RCC_APB2ENR_DFSDM1EN_Pos            (24U)                              
+#define RCC_APB2ENR_DFSDM1EN_Msk            (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_DFSDM1EN                RCC_APB2ENR_DFSDM1EN_Msk           
+
+/********************  Bit definition for RCC_AHB1SMENR register  ***************/
+#define RCC_AHB1SMENR_DMA1SMEN_Pos          (0U)                               
+#define RCC_AHB1SMENR_DMA1SMEN_Msk          (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1SMENR_DMA1SMEN              RCC_AHB1SMENR_DMA1SMEN_Msk         
+#define RCC_AHB1SMENR_DMA2SMEN_Pos          (1U)                               
+#define RCC_AHB1SMENR_DMA2SMEN_Msk          (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1SMENR_DMA2SMEN              RCC_AHB1SMENR_DMA2SMEN_Msk         
+#define RCC_AHB1SMENR_FLASHSMEN_Pos         (8U)                               
+#define RCC_AHB1SMENR_FLASHSMEN_Msk         (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1SMENR_FLASHSMEN             RCC_AHB1SMENR_FLASHSMEN_Msk        
+#define RCC_AHB1SMENR_SRAM1SMEN_Pos         (9U)                               
+#define RCC_AHB1SMENR_SRAM1SMEN_Msk         (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1SMENR_SRAM1SMEN             RCC_AHB1SMENR_SRAM1SMEN_Msk        
+#define RCC_AHB1SMENR_CRCSMEN_Pos           (12U)                              
+#define RCC_AHB1SMENR_CRCSMEN_Msk           (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1SMENR_CRCSMEN               RCC_AHB1SMENR_CRCSMEN_Msk          
+#define RCC_AHB1SMENR_TSCSMEN_Pos           (16U)                              
+#define RCC_AHB1SMENR_TSCSMEN_Msk           (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1SMENR_TSCSMEN               RCC_AHB1SMENR_TSCSMEN_Msk          
+
+/********************  Bit definition for RCC_AHB2SMENR register  *************/
+#define RCC_AHB2SMENR_GPIOASMEN_Pos         (0U)                               
+#define RCC_AHB2SMENR_GPIOASMEN_Msk         (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2SMENR_GPIOASMEN             RCC_AHB2SMENR_GPIOASMEN_Msk        
+#define RCC_AHB2SMENR_GPIOBSMEN_Pos         (1U)                               
+#define RCC_AHB2SMENR_GPIOBSMEN_Msk         (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2SMENR_GPIOBSMEN             RCC_AHB2SMENR_GPIOBSMEN_Msk        
+#define RCC_AHB2SMENR_GPIOCSMEN_Pos         (2U)                               
+#define RCC_AHB2SMENR_GPIOCSMEN_Msk         (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2SMENR_GPIOCSMEN             RCC_AHB2SMENR_GPIOCSMEN_Msk        
+#define RCC_AHB2SMENR_GPIODSMEN_Pos         (3U)                               
+#define RCC_AHB2SMENR_GPIODSMEN_Msk         (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2SMENR_GPIODSMEN             RCC_AHB2SMENR_GPIODSMEN_Msk        
+#define RCC_AHB2SMENR_GPIOESMEN_Pos         (4U)                               
+#define RCC_AHB2SMENR_GPIOESMEN_Msk         (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2SMENR_GPIOESMEN             RCC_AHB2SMENR_GPIOESMEN_Msk        
+#define RCC_AHB2SMENR_GPIOFSMEN_Pos         (5U)                               
+#define RCC_AHB2SMENR_GPIOFSMEN_Msk         (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2SMENR_GPIOFSMEN             RCC_AHB2SMENR_GPIOFSMEN_Msk        
+#define RCC_AHB2SMENR_GPIOGSMEN_Pos         (6U)                               
+#define RCC_AHB2SMENR_GPIOGSMEN_Msk         (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2SMENR_GPIOGSMEN             RCC_AHB2SMENR_GPIOGSMEN_Msk        
+#define RCC_AHB2SMENR_GPIOHSMEN_Pos         (7U)                               
+#define RCC_AHB2SMENR_GPIOHSMEN_Msk         (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2SMENR_GPIOHSMEN             RCC_AHB2SMENR_GPIOHSMEN_Msk        
+#define RCC_AHB2SMENR_SRAM2SMEN_Pos         (9U)                               
+#define RCC_AHB2SMENR_SRAM2SMEN_Msk         (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2SMENR_SRAM2SMEN             RCC_AHB2SMENR_SRAM2SMEN_Msk        
+#define RCC_AHB2SMENR_OTGFSSMEN_Pos         (12U)                              
+#define RCC_AHB2SMENR_OTGFSSMEN_Msk         (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2SMENR_OTGFSSMEN             RCC_AHB2SMENR_OTGFSSMEN_Msk        
+#define RCC_AHB2SMENR_ADCSMEN_Pos           (13U)                              
+#define RCC_AHB2SMENR_ADCSMEN_Msk           (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
+#define RCC_AHB2SMENR_ADCSMEN               RCC_AHB2SMENR_ADCSMEN_Msk          
+#define RCC_AHB2SMENR_AESSMEN_Pos           (16U)                              
+#define RCC_AHB2SMENR_AESSMEN_Msk           (0x1U << RCC_AHB2SMENR_AESSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB2SMENR_AESSMEN               RCC_AHB2SMENR_AESSMEN_Msk          
+#define RCC_AHB2SMENR_RNGSMEN_Pos           (18U)                              
+#define RCC_AHB2SMENR_RNGSMEN_Msk           (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB2SMENR_RNGSMEN               RCC_AHB2SMENR_RNGSMEN_Msk          
+
+/********************  Bit definition for RCC_AHB3SMENR register  *************/
+#define RCC_AHB3SMENR_FMCSMEN_Pos           (0U)                               
+#define RCC_AHB3SMENR_FMCSMEN_Msk           (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3SMENR_FMCSMEN               RCC_AHB3SMENR_FMCSMEN_Msk          
+#define RCC_AHB3SMENR_QSPISMEN_Pos          (8U)                               
+#define RCC_AHB3SMENR_QSPISMEN_Msk          (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB3SMENR_QSPISMEN              RCC_AHB3SMENR_QSPISMEN_Msk         
+
+/********************  Bit definition for RCC_APB1SMENR1 register  *************/
+#define RCC_APB1SMENR1_TIM2SMEN_Pos         (0U)                               
+#define RCC_APB1SMENR1_TIM2SMEN_Msk         (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR1_TIM2SMEN             RCC_APB1SMENR1_TIM2SMEN_Msk        
+#define RCC_APB1SMENR1_TIM3SMEN_Pos         (1U)                               
+#define RCC_APB1SMENR1_TIM3SMEN_Msk         (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1SMENR1_TIM3SMEN             RCC_APB1SMENR1_TIM3SMEN_Msk        
+#define RCC_APB1SMENR1_TIM4SMEN_Pos         (2U)                               
+#define RCC_APB1SMENR1_TIM4SMEN_Msk         (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR1_TIM4SMEN             RCC_APB1SMENR1_TIM4SMEN_Msk        
+#define RCC_APB1SMENR1_TIM5SMEN_Pos         (3U)                               
+#define RCC_APB1SMENR1_TIM5SMEN_Msk         (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1SMENR1_TIM5SMEN             RCC_APB1SMENR1_TIM5SMEN_Msk        
+#define RCC_APB1SMENR1_TIM6SMEN_Pos         (4U)                               
+#define RCC_APB1SMENR1_TIM6SMEN_Msk         (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR1_TIM6SMEN             RCC_APB1SMENR1_TIM6SMEN_Msk        
+#define RCC_APB1SMENR1_TIM7SMEN_Pos         (5U)                               
+#define RCC_APB1SMENR1_TIM7SMEN_Msk         (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR1_TIM7SMEN             RCC_APB1SMENR1_TIM7SMEN_Msk        
+#define RCC_APB1SMENR1_LCDSMEN_Pos          (9U)                               
+#define RCC_APB1SMENR1_LCDSMEN_Msk          (0x1U << RCC_APB1SMENR1_LCDSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1SMENR1_LCDSMEN              RCC_APB1SMENR1_LCDSMEN_Msk         
+#define RCC_APB1SMENR1_WWDGSMEN_Pos         (11U)                              
+#define RCC_APB1SMENR1_WWDGSMEN_Msk         (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR1_WWDGSMEN             RCC_APB1SMENR1_WWDGSMEN_Msk        
+#define RCC_APB1SMENR1_SPI2SMEN_Pos         (14U)                              
+#define RCC_APB1SMENR1_SPI2SMEN_Msk         (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR1_SPI2SMEN             RCC_APB1SMENR1_SPI2SMEN_Msk        
+#define RCC_APB1SMENR1_SPI3SMEN_Pos         (15U)                              
+#define RCC_APB1SMENR1_SPI3SMEN_Msk         (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1SMENR1_SPI3SMEN             RCC_APB1SMENR1_SPI3SMEN_Msk        
+#define RCC_APB1SMENR1_USART2SMEN_Pos       (17U)                              
+#define RCC_APB1SMENR1_USART2SMEN_Msk       (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR1_USART2SMEN           RCC_APB1SMENR1_USART2SMEN_Msk      
+#define RCC_APB1SMENR1_USART3SMEN_Pos       (18U)                              
+#define RCC_APB1SMENR1_USART3SMEN_Msk       (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR1_USART3SMEN           RCC_APB1SMENR1_USART3SMEN_Msk      
+#define RCC_APB1SMENR1_UART4SMEN_Pos        (19U)                              
+#define RCC_APB1SMENR1_UART4SMEN_Msk        (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1SMENR1_UART4SMEN            RCC_APB1SMENR1_UART4SMEN_Msk       
+#define RCC_APB1SMENR1_UART5SMEN_Pos        (20U)                              
+#define RCC_APB1SMENR1_UART5SMEN_Msk        (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1SMENR1_UART5SMEN            RCC_APB1SMENR1_UART5SMEN_Msk       
+#define RCC_APB1SMENR1_I2C1SMEN_Pos         (21U)                              
+#define RCC_APB1SMENR1_I2C1SMEN_Msk         (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR1_I2C1SMEN             RCC_APB1SMENR1_I2C1SMEN_Msk        
+#define RCC_APB1SMENR1_I2C2SMEN_Pos         (22U)                              
+#define RCC_APB1SMENR1_I2C2SMEN_Msk         (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR1_I2C2SMEN             RCC_APB1SMENR1_I2C2SMEN_Msk        
+#define RCC_APB1SMENR1_I2C3SMEN_Pos         (23U)                              
+#define RCC_APB1SMENR1_I2C3SMEN_Msk         (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR1_I2C3SMEN             RCC_APB1SMENR1_I2C3SMEN_Msk        
+#define RCC_APB1SMENR1_CAN1SMEN_Pos         (25U)                              
+#define RCC_APB1SMENR1_CAN1SMEN_Msk         (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1SMENR1_CAN1SMEN             RCC_APB1SMENR1_CAN1SMEN_Msk        
+#define RCC_APB1SMENR1_PWRSMEN_Pos          (28U)                              
+#define RCC_APB1SMENR1_PWRSMEN_Msk          (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR1_PWRSMEN              RCC_APB1SMENR1_PWRSMEN_Msk         
+#define RCC_APB1SMENR1_DAC1SMEN_Pos         (29U)                              
+#define RCC_APB1SMENR1_DAC1SMEN_Msk         (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR1_DAC1SMEN             RCC_APB1SMENR1_DAC1SMEN_Msk        
+#define RCC_APB1SMENR1_OPAMPSMEN_Pos        (30U)                              
+#define RCC_APB1SMENR1_OPAMPSMEN_Msk        (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1SMENR1_OPAMPSMEN            RCC_APB1SMENR1_OPAMPSMEN_Msk       
+#define RCC_APB1SMENR1_LPTIM1SMEN_Pos       (31U)                              
+#define RCC_APB1SMENR1_LPTIM1SMEN_Msk       (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR1_LPTIM1SMEN           RCC_APB1SMENR1_LPTIM1SMEN_Msk      
+
+/********************  Bit definition for RCC_APB1SMENR2 register  *************/
+#define RCC_APB1SMENR2_LPUART1SMEN_Pos      (0U)                               
+#define RCC_APB1SMENR2_LPUART1SMEN_Msk      (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR2_LPUART1SMEN          RCC_APB1SMENR2_LPUART1SMEN_Msk     
+#define RCC_APB1SMENR2_SWPMI1SMEN_Pos       (2U)                               
+#define RCC_APB1SMENR2_SWPMI1SMEN_Msk       (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR2_SWPMI1SMEN           RCC_APB1SMENR2_SWPMI1SMEN_Msk      
+#define RCC_APB1SMENR2_LPTIM2SMEN_Pos       (5U)                               
+#define RCC_APB1SMENR2_LPTIM2SMEN_Msk       (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR2_LPTIM2SMEN           RCC_APB1SMENR2_LPTIM2SMEN_Msk      
+
+/********************  Bit definition for RCC_APB2SMENR register  *************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos        (0U)                               
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk        (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN            RCC_APB2SMENR_SYSCFGSMEN_Msk       
+#define RCC_APB2SMENR_SDMMC1SMEN_Pos        (10U)                              
+#define RCC_APB2SMENR_SDMMC1SMEN_Msk        (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2SMENR_SDMMC1SMEN            RCC_APB2SMENR_SDMMC1SMEN_Msk       
+#define RCC_APB2SMENR_TIM1SMEN_Pos          (11U)                              
+#define RCC_APB2SMENR_TIM1SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2SMENR_TIM1SMEN              RCC_APB2SMENR_TIM1SMEN_Msk         
+#define RCC_APB2SMENR_SPI1SMEN_Pos          (12U)                              
+#define RCC_APB2SMENR_SPI1SMEN_Msk          (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN              RCC_APB2SMENR_SPI1SMEN_Msk         
+#define RCC_APB2SMENR_TIM8SMEN_Pos          (13U)                              
+#define RCC_APB2SMENR_TIM8SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2SMENR_TIM8SMEN              RCC_APB2SMENR_TIM8SMEN_Msk         
+#define RCC_APB2SMENR_USART1SMEN_Pos        (14U)                              
+#define RCC_APB2SMENR_USART1SMEN_Msk        (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN            RCC_APB2SMENR_USART1SMEN_Msk       
+#define RCC_APB2SMENR_TIM15SMEN_Pos         (16U)                              
+#define RCC_APB2SMENR_TIM15SMEN_Msk         (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2SMENR_TIM15SMEN             RCC_APB2SMENR_TIM15SMEN_Msk        
+#define RCC_APB2SMENR_TIM16SMEN_Pos         (17U)                              
+#define RCC_APB2SMENR_TIM16SMEN_Msk         (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2SMENR_TIM16SMEN             RCC_APB2SMENR_TIM16SMEN_Msk        
+#define RCC_APB2SMENR_TIM17SMEN_Pos         (18U)                              
+#define RCC_APB2SMENR_TIM17SMEN_Msk         (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2SMENR_TIM17SMEN             RCC_APB2SMENR_TIM17SMEN_Msk        
+#define RCC_APB2SMENR_SAI1SMEN_Pos          (21U)                              
+#define RCC_APB2SMENR_SAI1SMEN_Msk          (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2SMENR_SAI1SMEN              RCC_APB2SMENR_SAI1SMEN_Msk         
+#define RCC_APB2SMENR_SAI2SMEN_Pos          (22U)                              
+#define RCC_APB2SMENR_SAI2SMEN_Msk          (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_SAI2SMEN              RCC_APB2SMENR_SAI2SMEN_Msk         
+#define RCC_APB2SMENR_DFSDM1SMEN_Pos        (24U)                              
+#define RCC_APB2SMENR_DFSDM1SMEN_Msk        (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2SMENR_DFSDM1SMEN            RCC_APB2SMENR_DFSDM1SMEN_Msk       
+
+/********************  Bit definition for RCC_CCIPR register  ******************/
+#define RCC_CCIPR_USART1SEL_Pos             (0U)                               
+#define RCC_CCIPR_USART1SEL_Msk             (0x3U << RCC_CCIPR_USART1SEL_Pos)  /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL                 RCC_CCIPR_USART1SEL_Msk            
+#define RCC_CCIPR_USART1SEL_0               (0x1U << RCC_CCIPR_USART1SEL_Pos)  /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1               (0x2U << RCC_CCIPR_USART1SEL_Pos)  /*!< 0x00000002 */
+
+#define RCC_CCIPR_USART2SEL_Pos             (2U)                               
+#define RCC_CCIPR_USART2SEL_Msk             (0x3U << RCC_CCIPR_USART2SEL_Pos)  /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL                 RCC_CCIPR_USART2SEL_Msk            
+#define RCC_CCIPR_USART2SEL_0               (0x1U << RCC_CCIPR_USART2SEL_Pos)  /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1               (0x2U << RCC_CCIPR_USART2SEL_Pos)  /*!< 0x00000008 */
+
+#define RCC_CCIPR_USART3SEL_Pos             (4U)                               
+#define RCC_CCIPR_USART3SEL_Msk             (0x3U << RCC_CCIPR_USART3SEL_Pos)  /*!< 0x00000030 */
+#define RCC_CCIPR_USART3SEL                 RCC_CCIPR_USART3SEL_Msk            
+#define RCC_CCIPR_USART3SEL_0               (0x1U << RCC_CCIPR_USART3SEL_Pos)  /*!< 0x00000010 */
+#define RCC_CCIPR_USART3SEL_1               (0x2U << RCC_CCIPR_USART3SEL_Pos)  /*!< 0x00000020 */
+
+#define RCC_CCIPR_UART4SEL_Pos              (6U)                               
+#define RCC_CCIPR_UART4SEL_Msk              (0x3U << RCC_CCIPR_UART4SEL_Pos)   /*!< 0x000000C0 */
+#define RCC_CCIPR_UART4SEL                  RCC_CCIPR_UART4SEL_Msk             
+#define RCC_CCIPR_UART4SEL_0                (0x1U << RCC_CCIPR_UART4SEL_Pos)   /*!< 0x00000040 */
+#define RCC_CCIPR_UART4SEL_1                (0x2U << RCC_CCIPR_UART4SEL_Pos)   /*!< 0x00000080 */
+
+#define RCC_CCIPR_UART5SEL_Pos              (8U)                               
+#define RCC_CCIPR_UART5SEL_Msk              (0x3U << RCC_CCIPR_UART5SEL_Pos)   /*!< 0x00000300 */
+#define RCC_CCIPR_UART5SEL                  RCC_CCIPR_UART5SEL_Msk             
+#define RCC_CCIPR_UART5SEL_0                (0x1U << RCC_CCIPR_UART5SEL_Pos)   /*!< 0x00000100 */
+#define RCC_CCIPR_UART5SEL_1                (0x2U << RCC_CCIPR_UART5SEL_Pos)   /*!< 0x00000200 */
+
+#define RCC_CCIPR_LPUART1SEL_Pos            (10U)                              
+#define RCC_CCIPR_LPUART1SEL_Msk            (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL                RCC_CCIPR_LPUART1SEL_Msk           
+#define RCC_CCIPR_LPUART1SEL_0              (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
+#define RCC_CCIPR_LPUART1SEL_1              (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
+
+#define RCC_CCIPR_I2C1SEL_Pos               (12U)                              
+#define RCC_CCIPR_I2C1SEL_Msk               (0x3U << RCC_CCIPR_I2C1SEL_Pos)    /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL                   RCC_CCIPR_I2C1SEL_Msk              
+#define RCC_CCIPR_I2C1SEL_0                 (0x1U << RCC_CCIPR_I2C1SEL_Pos)    /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1                 (0x2U << RCC_CCIPR_I2C1SEL_Pos)    /*!< 0x00002000 */
+
+#define RCC_CCIPR_I2C2SEL_Pos               (14U)                              
+#define RCC_CCIPR_I2C2SEL_Msk               (0x3U << RCC_CCIPR_I2C2SEL_Pos)    /*!< 0x0000C000 */
+#define RCC_CCIPR_I2C2SEL                   RCC_CCIPR_I2C2SEL_Msk              
+#define RCC_CCIPR_I2C2SEL_0                 (0x1U << RCC_CCIPR_I2C2SEL_Pos)    /*!< 0x00004000 */
+#define RCC_CCIPR_I2C2SEL_1                 (0x2U << RCC_CCIPR_I2C2SEL_Pos)    /*!< 0x00008000 */
+
+#define RCC_CCIPR_I2C3SEL_Pos               (16U)                              
+#define RCC_CCIPR_I2C3SEL_Msk               (0x3U << RCC_CCIPR_I2C3SEL_Pos)    /*!< 0x00030000 */
+#define RCC_CCIPR_I2C3SEL                   RCC_CCIPR_I2C3SEL_Msk              
+#define RCC_CCIPR_I2C3SEL_0                 (0x1U << RCC_CCIPR_I2C3SEL_Pos)    /*!< 0x00010000 */
+#define RCC_CCIPR_I2C3SEL_1                 (0x2U << RCC_CCIPR_I2C3SEL_Pos)    /*!< 0x00020000 */
+
+#define RCC_CCIPR_LPTIM1SEL_Pos             (18U)                              
+#define RCC_CCIPR_LPTIM1SEL_Msk             (0x3U << RCC_CCIPR_LPTIM1SEL_Pos)  /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL                 RCC_CCIPR_LPTIM1SEL_Msk            
+#define RCC_CCIPR_LPTIM1SEL_0               (0x1U << RCC_CCIPR_LPTIM1SEL_Pos)  /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1               (0x2U << RCC_CCIPR_LPTIM1SEL_Pos)  /*!< 0x00080000 */
+
+#define RCC_CCIPR_LPTIM2SEL_Pos             (20U)                              
+#define RCC_CCIPR_LPTIM2SEL_Msk             (0x3U << RCC_CCIPR_LPTIM2SEL_Pos)  /*!< 0x00300000 */
+#define RCC_CCIPR_LPTIM2SEL                 RCC_CCIPR_LPTIM2SEL_Msk            
+#define RCC_CCIPR_LPTIM2SEL_0               (0x1U << RCC_CCIPR_LPTIM2SEL_Pos)  /*!< 0x00100000 */
+#define RCC_CCIPR_LPTIM2SEL_1               (0x2U << RCC_CCIPR_LPTIM2SEL_Pos)  /*!< 0x00200000 */
+
+#define RCC_CCIPR_SAI1SEL_Pos               (22U)                              
+#define RCC_CCIPR_SAI1SEL_Msk               (0x3U << RCC_CCIPR_SAI1SEL_Pos)    /*!< 0x00C00000 */
+#define RCC_CCIPR_SAI1SEL                   RCC_CCIPR_SAI1SEL_Msk              
+#define RCC_CCIPR_SAI1SEL_0                 (0x1U << RCC_CCIPR_SAI1SEL_Pos)    /*!< 0x00400000 */
+#define RCC_CCIPR_SAI1SEL_1                 (0x2U << RCC_CCIPR_SAI1SEL_Pos)    /*!< 0x00800000 */
+
+#define RCC_CCIPR_SAI2SEL_Pos               (24U)                              
+#define RCC_CCIPR_SAI2SEL_Msk               (0x3U << RCC_CCIPR_SAI2SEL_Pos)    /*!< 0x03000000 */
+#define RCC_CCIPR_SAI2SEL                   RCC_CCIPR_SAI2SEL_Msk              
+#define RCC_CCIPR_SAI2SEL_0                 (0x1U << RCC_CCIPR_SAI2SEL_Pos)    /*!< 0x01000000 */
+#define RCC_CCIPR_SAI2SEL_1                 (0x2U << RCC_CCIPR_SAI2SEL_Pos)    /*!< 0x02000000 */
+
+#define RCC_CCIPR_CLK48SEL_Pos              (26U)                              
+#define RCC_CCIPR_CLK48SEL_Msk              (0x3U << RCC_CCIPR_CLK48SEL_Pos)   /*!< 0x0C000000 */
+#define RCC_CCIPR_CLK48SEL                  RCC_CCIPR_CLK48SEL_Msk             
+#define RCC_CCIPR_CLK48SEL_0                (0x1U << RCC_CCIPR_CLK48SEL_Pos)   /*!< 0x04000000 */
+#define RCC_CCIPR_CLK48SEL_1                (0x2U << RCC_CCIPR_CLK48SEL_Pos)   /*!< 0x08000000 */
+
+#define RCC_CCIPR_ADCSEL_Pos                (28U)                              
+#define RCC_CCIPR_ADCSEL_Msk                (0x3U << RCC_CCIPR_ADCSEL_Pos)     /*!< 0x30000000 */
+#define RCC_CCIPR_ADCSEL                    RCC_CCIPR_ADCSEL_Msk               
+#define RCC_CCIPR_ADCSEL_0                  (0x1U << RCC_CCIPR_ADCSEL_Pos)     /*!< 0x10000000 */
+#define RCC_CCIPR_ADCSEL_1                  (0x2U << RCC_CCIPR_ADCSEL_Pos)     /*!< 0x20000000 */
+
+#define RCC_CCIPR_SWPMI1SEL_Pos             (30U)                              
+#define RCC_CCIPR_SWPMI1SEL_Msk             (0x1U << RCC_CCIPR_SWPMI1SEL_Pos)  /*!< 0x40000000 */
+#define RCC_CCIPR_SWPMI1SEL                 RCC_CCIPR_SWPMI1SEL_Msk            
+
+#define RCC_CCIPR_DFSDM1SEL_Pos             (31U)                              
+#define RCC_CCIPR_DFSDM1SEL_Msk             (0x1U << RCC_CCIPR_DFSDM1SEL_Pos)  /*!< 0x80000000 */
+#define RCC_CCIPR_DFSDM1SEL                 RCC_CCIPR_DFSDM1SEL_Msk            
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                  (0U)                               
+#define RCC_BDCR_LSEON_Msk                  (0x1U << RCC_BDCR_LSEON_Pos)       /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                      RCC_BDCR_LSEON_Msk                 
+#define RCC_BDCR_LSERDY_Pos                 (1U)                               
+#define RCC_BDCR_LSERDY_Msk                 (0x1U << RCC_BDCR_LSERDY_Pos)      /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                     RCC_BDCR_LSERDY_Msk                
+#define RCC_BDCR_LSEBYP_Pos                 (2U)                               
+#define RCC_BDCR_LSEBYP_Msk                 (0x1U << RCC_BDCR_LSEBYP_Pos)      /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                     RCC_BDCR_LSEBYP_Msk                
+
+#define RCC_BDCR_LSEDRV_Pos                 (3U)                               
+#define RCC_BDCR_LSEDRV_Msk                 (0x3U << RCC_BDCR_LSEDRV_Pos)      /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                     RCC_BDCR_LSEDRV_Msk                
+#define RCC_BDCR_LSEDRV_0                   (0x1U << RCC_BDCR_LSEDRV_Pos)      /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                   (0x2U << RCC_BDCR_LSEDRV_Pos)      /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos               (5U)                               
+#define RCC_BDCR_LSECSSON_Msk               (0x1U << RCC_BDCR_LSECSSON_Pos)    /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                   RCC_BDCR_LSECSSON_Msk              
+#define RCC_BDCR_LSECSSD_Pos                (6U)                               
+#define RCC_BDCR_LSECSSD_Msk                (0x1U << RCC_BDCR_LSECSSD_Pos)     /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                    RCC_BDCR_LSECSSD_Msk               
+
+#define RCC_BDCR_RTCSEL_Pos                 (8U)                               
+#define RCC_BDCR_RTCSEL_Msk                 (0x3U << RCC_BDCR_RTCSEL_Pos)      /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                     RCC_BDCR_RTCSEL_Msk                
+#define RCC_BDCR_RTCSEL_0                   (0x1U << RCC_BDCR_RTCSEL_Pos)      /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                   (0x2U << RCC_BDCR_RTCSEL_Pos)      /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                  (15U)                              
+#define RCC_BDCR_RTCEN_Msk                  (0x1U << RCC_BDCR_RTCEN_Pos)       /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                      RCC_BDCR_RTCEN_Msk                 
+#define RCC_BDCR_BDRST_Pos                  (16U)                              
+#define RCC_BDCR_BDRST_Msk                  (0x1U << RCC_BDCR_BDRST_Pos)       /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                      RCC_BDCR_BDRST_Msk                 
+#define RCC_BDCR_LSCOEN_Pos                 (24U)                              
+#define RCC_BDCR_LSCOEN_Msk                 (0x1U << RCC_BDCR_LSCOEN_Pos)      /*!< 0x01000000 */
+#define RCC_BDCR_LSCOEN                     RCC_BDCR_LSCOEN_Msk                
+#define RCC_BDCR_LSCOSEL_Pos                (25U)                              
+#define RCC_BDCR_LSCOSEL_Msk                (0x1U << RCC_BDCR_LSCOSEL_Pos)     /*!< 0x02000000 */
+#define RCC_BDCR_LSCOSEL                    RCC_BDCR_LSCOSEL_Msk               
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                   (0U)                               
+#define RCC_CSR_LSION_Msk                   (0x1U << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
+#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  
+#define RCC_CSR_LSIRDY_Pos                  (1U)                               
+#define RCC_CSR_LSIRDY_Msk                  (0x1U << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 
+
+#define RCC_CSR_MSISRANGE_Pos               (8U)                               
+#define RCC_CSR_MSISRANGE_Msk               (0xFU << RCC_CSR_MSISRANGE_Pos)    /*!< 0x00000F00 */
+#define RCC_CSR_MSISRANGE                   RCC_CSR_MSISRANGE_Msk              
+#define RCC_CSR_MSISRANGE_1                 (0x4U << RCC_CSR_MSISRANGE_Pos)    /*!< 0x00000400 */
+#define RCC_CSR_MSISRANGE_2                 (0x5U << RCC_CSR_MSISRANGE_Pos)    /*!< 0x00000500 */
+#define RCC_CSR_MSISRANGE_4                 (0x6U << RCC_CSR_MSISRANGE_Pos)    /*!< 0x00000600 */
+#define RCC_CSR_MSISRANGE_8                 (0x7U << RCC_CSR_MSISRANGE_Pos)    /*!< 0x00000700 */
+
+#define RCC_CSR_RMVF_Pos                    (23U)                              
+#define RCC_CSR_RMVF_Msk                    (0x1U << RCC_CSR_RMVF_Pos)         /*!< 0x00800000 */
+#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   
+#define RCC_CSR_FWRSTF_Pos                  (24U)                              
+#define RCC_CSR_FWRSTF_Msk                  (0x1U << RCC_CSR_FWRSTF_Pos)       /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF                      RCC_CSR_FWRSTF_Msk                 
+#define RCC_CSR_OBLRSTF_Pos                 (25U)                              
+#define RCC_CSR_OBLRSTF_Msk                 (0x1U << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                
+#define RCC_CSR_PINRSTF_Pos                 (26U)                              
+#define RCC_CSR_PINRSTF_Msk                 (0x1U << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                
+#define RCC_CSR_BORRSTF_Pos                 (27U)                              
+#define RCC_CSR_BORRSTF_Msk                 (0x1U << RCC_CSR_BORRSTF_Pos)      /*!< 0x08000000 */
+#define RCC_CSR_BORRSTF                     RCC_CSR_BORRSTF_Msk                
+#define RCC_CSR_SFTRSTF_Pos                 (28U)                              
+#define RCC_CSR_SFTRSTF_Msk                 (0x1U << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                
+#define RCC_CSR_IWDGRSTF_Pos                (29U)                              
+#define RCC_CSR_IWDGRSTF_Msk                (0x1U << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               
+#define RCC_CSR_WWDGRSTF_Pos                (30U)                              
+#define RCC_CSR_WWDGRSTF_Msk                (0x1U << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               
+#define RCC_CSR_LPWRRSTF_Pos                (31U)                              
+#define RCC_CSR_LPWRRSTF_Msk                (0x1U << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos                     (2U)                              
+#define RNG_CR_RNGEN_Msk                     (0x1U << RNG_CR_RNGEN_Pos)        /*!< 0x00000004 */
+#define RNG_CR_RNGEN                         RNG_CR_RNGEN_Msk                  
+#define RNG_CR_IE_Pos                        (3U)                              
+#define RNG_CR_IE_Msk                        (0x1U << RNG_CR_IE_Pos)           /*!< 0x00000008 */
+#define RNG_CR_IE                            RNG_CR_IE_Msk                     
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos                      (0U)                              
+#define RNG_SR_DRDY_Msk                      (0x1U << RNG_SR_DRDY_Pos)         /*!< 0x00000001 */
+#define RNG_SR_DRDY                          RNG_SR_DRDY_Msk                   
+#define RNG_SR_CECS_Pos                      (1U)                              
+#define RNG_SR_CECS_Msk                      (0x1U << RNG_SR_CECS_Pos)         /*!< 0x00000002 */
+#define RNG_SR_CECS                          RNG_SR_CECS_Msk                   
+#define RNG_SR_SECS_Pos                      (2U)                              
+#define RNG_SR_SECS_Msk                      (0x1U << RNG_SR_SECS_Pos)         /*!< 0x00000004 */
+#define RNG_SR_SECS                          RNG_SR_SECS_Msk                   
+#define RNG_SR_CEIS_Pos                      (5U)                              
+#define RNG_SR_CEIS_Msk                      (0x1U << RNG_SR_CEIS_Pos)         /*!< 0x00000020 */
+#define RNG_SR_CEIS                          RNG_SR_CEIS_Msk                   
+#define RNG_SR_SEIS_Pos                      (6U)                              
+#define RNG_SR_SEIS_Msk                      (0x1U << RNG_SR_SEIS_Pos)         /*!< 0x00000040 */
+#define RNG_SR_SEIS                          RNG_SR_SEIS_Msk                   
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                        (22U)                             
+#define RTC_TR_PM_Msk                        (0x1U << RTC_TR_PM_Pos)           /*!< 0x00400000 */
+#define RTC_TR_PM                            RTC_TR_PM_Msk                     
+#define RTC_TR_HT_Pos                        (20U)                             
+#define RTC_TR_HT_Msk                        (0x3U << RTC_TR_HT_Pos)           /*!< 0x00300000 */
+#define RTC_TR_HT                            RTC_TR_HT_Msk                     
+#define RTC_TR_HT_0                          (0x1U << RTC_TR_HT_Pos)           /*!< 0x00100000 */
+#define RTC_TR_HT_1                          (0x2U << RTC_TR_HT_Pos)           /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                        (16U)                             
+#define RTC_TR_HU_Msk                        (0xFU << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
+#define RTC_TR_HU                            RTC_TR_HU_Msk                     
+#define RTC_TR_HU_0                          (0x1U << RTC_TR_HU_Pos)           /*!< 0x00010000 */
+#define RTC_TR_HU_1                          (0x2U << RTC_TR_HU_Pos)           /*!< 0x00020000 */
+#define RTC_TR_HU_2                          (0x4U << RTC_TR_HU_Pos)           /*!< 0x00040000 */
+#define RTC_TR_HU_3                          (0x8U << RTC_TR_HU_Pos)           /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                       (12U)                             
+#define RTC_TR_MNT_Msk                       (0x7U << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
+#define RTC_TR_MNT                           RTC_TR_MNT_Msk                    
+#define RTC_TR_MNT_0                         (0x1U << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
+#define RTC_TR_MNT_1                         (0x2U << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
+#define RTC_TR_MNT_2                         (0x4U << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                       (8U)                              
+#define RTC_TR_MNU_Msk                       (0xFU << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
+#define RTC_TR_MNU                           RTC_TR_MNU_Msk                    
+#define RTC_TR_MNU_0                         (0x1U << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
+#define RTC_TR_MNU_1                         (0x2U << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
+#define RTC_TR_MNU_2                         (0x4U << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
+#define RTC_TR_MNU_3                         (0x8U << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                        (4U)                              
+#define RTC_TR_ST_Msk                        (0x7U << RTC_TR_ST_Pos)           /*!< 0x00000070 */
+#define RTC_TR_ST                            RTC_TR_ST_Msk                     
+#define RTC_TR_ST_0                          (0x1U << RTC_TR_ST_Pos)           /*!< 0x00000010 */
+#define RTC_TR_ST_1                          (0x2U << RTC_TR_ST_Pos)           /*!< 0x00000020 */
+#define RTC_TR_ST_2                          (0x4U << RTC_TR_ST_Pos)           /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                        (0U)                              
+#define RTC_TR_SU_Msk                        (0xFU << RTC_TR_SU_Pos)           /*!< 0x0000000F */
+#define RTC_TR_SU                            RTC_TR_SU_Msk                     
+#define RTC_TR_SU_0                          (0x1U << RTC_TR_SU_Pos)           /*!< 0x00000001 */
+#define RTC_TR_SU_1                          (0x2U << RTC_TR_SU_Pos)           /*!< 0x00000002 */
+#define RTC_TR_SU_2                          (0x4U << RTC_TR_SU_Pos)           /*!< 0x00000004 */
+#define RTC_TR_SU_3                          (0x8U << RTC_TR_SU_Pos)           /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                        (20U)                             
+#define RTC_DR_YT_Msk                        (0xFU << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
+#define RTC_DR_YT                            RTC_DR_YT_Msk                     
+#define RTC_DR_YT_0                          (0x1U << RTC_DR_YT_Pos)           /*!< 0x00100000 */
+#define RTC_DR_YT_1                          (0x2U << RTC_DR_YT_Pos)           /*!< 0x00200000 */
+#define RTC_DR_YT_2                          (0x4U << RTC_DR_YT_Pos)           /*!< 0x00400000 */
+#define RTC_DR_YT_3                          (0x8U << RTC_DR_YT_Pos)           /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                        (16U)                             
+#define RTC_DR_YU_Msk                        (0xFU << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
+#define RTC_DR_YU                            RTC_DR_YU_Msk                     
+#define RTC_DR_YU_0                          (0x1U << RTC_DR_YU_Pos)           /*!< 0x00010000 */
+#define RTC_DR_YU_1                          (0x2U << RTC_DR_YU_Pos)           /*!< 0x00020000 */
+#define RTC_DR_YU_2                          (0x4U << RTC_DR_YU_Pos)           /*!< 0x00040000 */
+#define RTC_DR_YU_3                          (0x8U << RTC_DR_YU_Pos)           /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                       (13U)                             
+#define RTC_DR_WDU_Msk                       (0x7U << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
+#define RTC_DR_WDU                           RTC_DR_WDU_Msk                    
+#define RTC_DR_WDU_0                         (0x1U << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
+#define RTC_DR_WDU_1                         (0x2U << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
+#define RTC_DR_WDU_2                         (0x4U << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                        (12U)                             
+#define RTC_DR_MT_Msk                        (0x1U << RTC_DR_MT_Pos)           /*!< 0x00001000 */
+#define RTC_DR_MT                            RTC_DR_MT_Msk                     
+#define RTC_DR_MU_Pos                        (8U)                              
+#define RTC_DR_MU_Msk                        (0xFU << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
+#define RTC_DR_MU                            RTC_DR_MU_Msk                     
+#define RTC_DR_MU_0                          (0x1U << RTC_DR_MU_Pos)           /*!< 0x00000100 */
+#define RTC_DR_MU_1                          (0x2U << RTC_DR_MU_Pos)           /*!< 0x00000200 */
+#define RTC_DR_MU_2                          (0x4U << RTC_DR_MU_Pos)           /*!< 0x00000400 */
+#define RTC_DR_MU_3                          (0x8U << RTC_DR_MU_Pos)           /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                        (4U)                              
+#define RTC_DR_DT_Msk                        (0x3U << RTC_DR_DT_Pos)           /*!< 0x00000030 */
+#define RTC_DR_DT                            RTC_DR_DT_Msk                     
+#define RTC_DR_DT_0                          (0x1U << RTC_DR_DT_Pos)           /*!< 0x00000010 */
+#define RTC_DR_DT_1                          (0x2U << RTC_DR_DT_Pos)           /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                        (0U)                              
+#define RTC_DR_DU_Msk                        (0xFU << RTC_DR_DU_Pos)           /*!< 0x0000000F */
+#define RTC_DR_DU                            RTC_DR_DU_Msk                     
+#define RTC_DR_DU_0                          (0x1U << RTC_DR_DU_Pos)           /*!< 0x00000001 */
+#define RTC_DR_DU_1                          (0x2U << RTC_DR_DU_Pos)           /*!< 0x00000002 */
+#define RTC_DR_DU_2                          (0x4U << RTC_DR_DU_Pos)           /*!< 0x00000004 */
+#define RTC_DR_DU_3                          (0x8U << RTC_DR_DU_Pos)           /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE_Pos                      (24U)                             
+#define RTC_CR_ITSE_Msk                      (0x1U << RTC_CR_ITSE_Pos)         /*!< 0x01000000 */
+#define RTC_CR_ITSE                          RTC_CR_ITSE_Msk                   
+#define RTC_CR_COE_Pos                       (23U)                             
+#define RTC_CR_COE_Msk                       (0x1U << RTC_CR_COE_Pos)          /*!< 0x00800000 */
+#define RTC_CR_COE                           RTC_CR_COE_Msk                    
+#define RTC_CR_OSEL_Pos                      (21U)                             
+#define RTC_CR_OSEL_Msk                      (0x3U << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
+#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk                   
+#define RTC_CR_OSEL_0                        (0x1U << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                        (0x2U << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                       (20U)                             
+#define RTC_CR_POL_Msk                       (0x1U << RTC_CR_POL_Pos)          /*!< 0x00100000 */
+#define RTC_CR_POL                           RTC_CR_POL_Msk                    
+#define RTC_CR_COSEL_Pos                     (19U)                             
+#define RTC_CR_COSEL_Msk                     (0x1U << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
+#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
+#define RTC_CR_BCK_Pos                       (18U)                             
+#define RTC_CR_BCK_Msk                       (0x1U << RTC_CR_BCK_Pos)          /*!< 0x00040000 */
+#define RTC_CR_BCK                           RTC_CR_BCK_Msk                    
+#define RTC_CR_SUB1H_Pos                     (17U)                             
+#define RTC_CR_SUB1H_Msk                     (0x1U << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
+#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
+#define RTC_CR_ADD1H_Pos                     (16U)                             
+#define RTC_CR_ADD1H_Msk                     (0x1U << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
+#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk                  
+#define RTC_CR_TSIE_Pos                      (15U)                             
+#define RTC_CR_TSIE_Msk                      (0x1U << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
+#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk                   
+#define RTC_CR_WUTIE_Pos                     (14U)                             
+#define RTC_CR_WUTIE_Msk                     (0x1U << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
+#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk                  
+#define RTC_CR_ALRBIE_Pos                    (13U)                             
+#define RTC_CR_ALRBIE_Msk                    (0x1U << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk                 
+#define RTC_CR_ALRAIE_Pos                    (12U)                             
+#define RTC_CR_ALRAIE_Msk                    (0x1U << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk                 
+#define RTC_CR_TSE_Pos                       (11U)                             
+#define RTC_CR_TSE_Msk                       (0x1U << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
+#define RTC_CR_TSE                           RTC_CR_TSE_Msk                    
+#define RTC_CR_WUTE_Pos                      (10U)                             
+#define RTC_CR_WUTE_Msk                      (0x1U << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
+#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk                   
+#define RTC_CR_ALRBE_Pos                     (9U)                              
+#define RTC_CR_ALRBE_Msk                     (0x1U << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
+#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk                  
+#define RTC_CR_ALRAE_Pos                     (8U)                              
+#define RTC_CR_ALRAE_Msk                     (0x1U << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
+#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk                  
+#define RTC_CR_FMT_Pos                       (6U)                              
+#define RTC_CR_FMT_Msk                       (0x1U << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
+#define RTC_CR_FMT                           RTC_CR_FMT_Msk                    
+#define RTC_CR_BYPSHAD_Pos                   (5U)                              
+#define RTC_CR_BYPSHAD_Msk                   (0x1U << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk                
+#define RTC_CR_REFCKON_Pos                   (4U)                              
+#define RTC_CR_REFCKON_Msk                   (0x1U << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
+#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk                
+#define RTC_CR_TSEDGE_Pos                    (3U)                              
+#define RTC_CR_TSEDGE_Msk                    (0x1U << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk                 
+#define RTC_CR_WUCKSEL_Pos                   (0U)                              
+#define RTC_CR_WUCKSEL_Msk                   (0x7U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk                
+#define RTC_CR_WUCKSEL_0                     (0x1U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1                     (0x2U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2                     (0x4U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF_Pos                     (17U)                             
+#define RTC_ISR_ITSF_Msk                     (0x1U << RTC_ISR_ITSF_Pos)        /*!< 0x00020000 */
+#define RTC_ISR_ITSF                         RTC_ISR_ITSF_Msk                  
+#define RTC_ISR_RECALPF_Pos                  (16U)                             
+#define RTC_ISR_RECALPF_Msk                  (0x1U << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk               
+#define RTC_ISR_TAMP3F_Pos                   (15U)                             
+#define RTC_ISR_TAMP3F_Msk                   (0x1U << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk                
+#define RTC_ISR_TAMP2F_Pos                   (14U)                             
+#define RTC_ISR_TAMP2F_Msk                   (0x1U << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk                
+#define RTC_ISR_TAMP1F_Pos                   (13U)                             
+#define RTC_ISR_TAMP1F_Msk                   (0x1U << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk                
+#define RTC_ISR_TSOVF_Pos                    (12U)                             
+#define RTC_ISR_TSOVF_Msk                    (0x1U << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk                 
+#define RTC_ISR_TSF_Pos                      (11U)                             
+#define RTC_ISR_TSF_Msk                      (0x1U << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
+#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk                   
+#define RTC_ISR_WUTF_Pos                     (10U)                             
+#define RTC_ISR_WUTF_Msk                     (0x1U << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
+#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk                  
+#define RTC_ISR_ALRBF_Pos                    (9U)                              
+#define RTC_ISR_ALRBF_Msk                    (0x1U << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk                 
+#define RTC_ISR_ALRAF_Pos                    (8U)                              
+#define RTC_ISR_ALRAF_Msk                    (0x1U << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk                 
+#define RTC_ISR_INIT_Pos                     (7U)                              
+#define RTC_ISR_INIT_Msk                     (0x1U << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
+#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk                  
+#define RTC_ISR_INITF_Pos                    (6U)                              
+#define RTC_ISR_INITF_Msk                    (0x1U << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
+#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk                 
+#define RTC_ISR_RSF_Pos                      (5U)                              
+#define RTC_ISR_RSF_Msk                      (0x1U << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
+#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk                   
+#define RTC_ISR_INITS_Pos                    (4U)                              
+#define RTC_ISR_INITS_Msk                    (0x1U << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
+#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk                 
+#define RTC_ISR_SHPF_Pos                     (3U)                              
+#define RTC_ISR_SHPF_Msk                     (0x1U << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
+#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk                  
+#define RTC_ISR_WUTWF_Pos                    (2U)                              
+#define RTC_ISR_WUTWF_Msk                    (0x1U << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk                 
+#define RTC_ISR_ALRBWF_Pos                   (1U)                              
+#define RTC_ISR_ALRBWF_Msk                   (0x1U << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk                
+#define RTC_ISR_ALRAWF_Pos                   (0U)                              
+#define RTC_ISR_ALRAWF_Msk                   (0x1U << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk                
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos                (16U)                             
+#define RTC_PRER_PREDIV_A_Msk                (0x7FU << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk             
+#define RTC_PRER_PREDIV_S_Pos                (0U)                              
+#define RTC_PRER_PREDIV_S_Msk                (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk             
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos                     (0U)                              
+#define RTC_WUTR_WUT_Msk                     (0xFFFFU << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk                  
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos                  (31U)                             
+#define RTC_ALRMAR_MSK4_Msk                  (0x1U << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk               
+#define RTC_ALRMAR_WDSEL_Pos                 (30U)                             
+#define RTC_ALRMAR_WDSEL_Msk                 (0x1U << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk              
+#define RTC_ALRMAR_DT_Pos                    (28U)                             
+#define RTC_ALRMAR_DT_Msk                    (0x3U << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk                 
+#define RTC_ALRMAR_DT_0                      (0x1U << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                      (0x2U << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos                    (24U)                             
+#define RTC_ALRMAR_DU_Msk                    (0xFU << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk                 
+#define RTC_ALRMAR_DU_0                      (0x1U << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                      (0x2U << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                      (0x4U << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                      (0x8U << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos                  (23U)                             
+#define RTC_ALRMAR_MSK3_Msk                  (0x1U << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk               
+#define RTC_ALRMAR_PM_Pos                    (22U)                             
+#define RTC_ALRMAR_PM_Msk                    (0x1U << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk                 
+#define RTC_ALRMAR_HT_Pos                    (20U)                             
+#define RTC_ALRMAR_HT_Msk                    (0x3U << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk                 
+#define RTC_ALRMAR_HT_0                      (0x1U << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                      (0x2U << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos                    (16U)                             
+#define RTC_ALRMAR_HU_Msk                    (0xFU << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk                 
+#define RTC_ALRMAR_HU_0                      (0x1U << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                      (0x2U << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                      (0x4U << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                      (0x8U << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos                  (15U)                             
+#define RTC_ALRMAR_MSK2_Msk                  (0x1U << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk               
+#define RTC_ALRMAR_MNT_Pos                   (12U)                             
+#define RTC_ALRMAR_MNT_Msk                   (0x7U << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk                
+#define RTC_ALRMAR_MNT_0                     (0x1U << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1                     (0x2U << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2                     (0x4U << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos                   (8U)                              
+#define RTC_ALRMAR_MNU_Msk                   (0xFU << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk                
+#define RTC_ALRMAR_MNU_0                     (0x1U << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1                     (0x2U << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2                     (0x4U << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3                     (0x8U << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos                  (7U)                              
+#define RTC_ALRMAR_MSK1_Msk                  (0x1U << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk               
+#define RTC_ALRMAR_ST_Pos                    (4U)                              
+#define RTC_ALRMAR_ST_Msk                    (0x7U << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk                 
+#define RTC_ALRMAR_ST_0                      (0x1U << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                      (0x2U << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                      (0x4U << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos                    (0U)                              
+#define RTC_ALRMAR_SU_Msk                    (0xFU << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk                 
+#define RTC_ALRMAR_SU_0                      (0x1U << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                      (0x2U << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                      (0x4U << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                      (0x8U << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos                  (31U)                             
+#define RTC_ALRMBR_MSK4_Msk                  (0x1U << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk               
+#define RTC_ALRMBR_WDSEL_Pos                 (30U)                             
+#define RTC_ALRMBR_WDSEL_Msk                 (0x1U << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk              
+#define RTC_ALRMBR_DT_Pos                    (28U)                             
+#define RTC_ALRMBR_DT_Msk                    (0x3U << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk                 
+#define RTC_ALRMBR_DT_0                      (0x1U << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                      (0x2U << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos                    (24U)                             
+#define RTC_ALRMBR_DU_Msk                    (0xFU << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk                 
+#define RTC_ALRMBR_DU_0                      (0x1U << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                      (0x2U << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                      (0x4U << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                      (0x8U << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos                  (23U)                             
+#define RTC_ALRMBR_MSK3_Msk                  (0x1U << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk               
+#define RTC_ALRMBR_PM_Pos                    (22U)                             
+#define RTC_ALRMBR_PM_Msk                    (0x1U << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk                 
+#define RTC_ALRMBR_HT_Pos                    (20U)                             
+#define RTC_ALRMBR_HT_Msk                    (0x3U << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk                 
+#define RTC_ALRMBR_HT_0                      (0x1U << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                      (0x2U << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos                    (16U)                             
+#define RTC_ALRMBR_HU_Msk                    (0xFU << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk                 
+#define RTC_ALRMBR_HU_0                      (0x1U << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                      (0x2U << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                      (0x4U << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                      (0x8U << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos                  (15U)                             
+#define RTC_ALRMBR_MSK2_Msk                  (0x1U << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk               
+#define RTC_ALRMBR_MNT_Pos                   (12U)                             
+#define RTC_ALRMBR_MNT_Msk                   (0x7U << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk                
+#define RTC_ALRMBR_MNT_0                     (0x1U << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1                     (0x2U << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2                     (0x4U << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos                   (8U)                              
+#define RTC_ALRMBR_MNU_Msk                   (0xFU << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk                
+#define RTC_ALRMBR_MNU_0                     (0x1U << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1                     (0x2U << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2                     (0x4U << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3                     (0x8U << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos                  (7U)                              
+#define RTC_ALRMBR_MSK1_Msk                  (0x1U << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk               
+#define RTC_ALRMBR_ST_Pos                    (4U)                              
+#define RTC_ALRMBR_ST_Msk                    (0x7U << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk                 
+#define RTC_ALRMBR_ST_0                      (0x1U << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                      (0x2U << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                      (0x4U << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos                    (0U)                              
+#define RTC_ALRMBR_SU_Msk                    (0xFU << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk                 
+#define RTC_ALRMBR_SU_0                      (0x1U << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                      (0x2U << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                      (0x4U << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                      (0x8U << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                      (0U)                              
+#define RTC_WPR_KEY_Msk                      (0xFFU << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
+#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk                   
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                       (0U)                              
+#define RTC_SSR_SS_Msk                       (0xFFFFU << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
+#define RTC_SSR_SS                           RTC_SSR_SS_Msk                    
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos                 (0U)                              
+#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk              
+#define RTC_SHIFTR_ADD1S_Pos                 (31U)                             
+#define RTC_SHIFTR_ADD1S_Msk                 (0x1U << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk              
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                      (22U)                             
+#define RTC_TSTR_PM_Msk                      (0x1U << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
+#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk                   
+#define RTC_TSTR_HT_Pos                      (20U)                             
+#define RTC_TSTR_HT_Msk                      (0x3U << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
+#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk                   
+#define RTC_TSTR_HT_0                        (0x1U << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                        (0x2U << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                      (16U)                             
+#define RTC_TSTR_HU_Msk                      (0xFU << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
+#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk                   
+#define RTC_TSTR_HU_0                        (0x1U << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                        (0x2U << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                        (0x4U << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                        (0x8U << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos                     (12U)                             
+#define RTC_TSTR_MNT_Msk                     (0x7U << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
+#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk                  
+#define RTC_TSTR_MNT_0                       (0x1U << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                       (0x2U << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                       (0x4U << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos                     (8U)                              
+#define RTC_TSTR_MNU_Msk                     (0xFU << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk                  
+#define RTC_TSTR_MNU_0                       (0x1U << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                       (0x2U << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                       (0x4U << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                       (0x8U << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                      (4U)                              
+#define RTC_TSTR_ST_Msk                      (0x7U << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
+#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk                   
+#define RTC_TSTR_ST_0                        (0x1U << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                        (0x2U << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                        (0x4U << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                      (0U)                              
+#define RTC_TSTR_SU_Msk                      (0xFU << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
+#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk                   
+#define RTC_TSTR_SU_0                        (0x1U << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                        (0x2U << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                        (0x4U << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                        (0x8U << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos                     (13U)                             
+#define RTC_TSDR_WDU_Msk                     (0x7U << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk                  
+#define RTC_TSDR_WDU_0                       (0x1U << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                       (0x2U << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                       (0x4U << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                      (12U)                             
+#define RTC_TSDR_MT_Msk                      (0x1U << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
+#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk                   
+#define RTC_TSDR_MU_Pos                      (8U)                              
+#define RTC_TSDR_MU_Msk                      (0xFU << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
+#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk                   
+#define RTC_TSDR_MU_0                        (0x1U << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                        (0x2U << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                        (0x4U << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                        (0x8U << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                      (4U)                              
+#define RTC_TSDR_DT_Msk                      (0x3U << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
+#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk                   
+#define RTC_TSDR_DT_0                        (0x1U << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                        (0x2U << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                      (0U)                              
+#define RTC_TSDR_DU_Msk                      (0xFU << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
+#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk                   
+#define RTC_TSDR_DU_0                        (0x1U << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                        (0x2U << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                        (0x4U << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                        (0x8U << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos                     (0U)                              
+#define RTC_TSSSR_SS_Msk                     (0xFFFFU << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk                  
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP_Pos                    (15U)                             
+#define RTC_CALR_CALP_Msk                    (0x1U << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
+#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk                 
+#define RTC_CALR_CALW8_Pos                   (14U)                             
+#define RTC_CALR_CALW8_Msk                   (0x1U << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
+#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk                
+#define RTC_CALR_CALW16_Pos                  (13U)                             
+#define RTC_CALR_CALW16_Msk                  (0x1U << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
+#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk               
+#define RTC_CALR_CALM_Pos                    (0U)                              
+#define RTC_CALR_CALM_Msk                    (0x1FFU << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
+#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk                 
+#define RTC_CALR_CALM_0                      (0x001U << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                      (0x002U << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                      (0x004U << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                      (0x008U << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                      (0x010U << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                      (0x020U << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                      (0x040U << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                      (0x080U << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                      (0x100U << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAMPCR register  ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos               (24U)                             
+#define RTC_TAMPCR_TAMP3MF_Msk               (0x1U << RTC_TAMPCR_TAMP3MF_Pos)  /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF                   RTC_TAMPCR_TAMP3MF_Msk            
+#define RTC_TAMPCR_TAMP3NOERASE_Pos          (23U)                             
+#define RTC_TAMPCR_TAMP3NOERASE_Msk          (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE              RTC_TAMPCR_TAMP3NOERASE_Msk       
+#define RTC_TAMPCR_TAMP3IE_Pos               (22U)                             
+#define RTC_TAMPCR_TAMP3IE_Msk               (0x1U << RTC_TAMPCR_TAMP3IE_Pos)  /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE                   RTC_TAMPCR_TAMP3IE_Msk            
+#define RTC_TAMPCR_TAMP2MF_Pos               (21U)                             
+#define RTC_TAMPCR_TAMP2MF_Msk               (0x1U << RTC_TAMPCR_TAMP2MF_Pos)  /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF                   RTC_TAMPCR_TAMP2MF_Msk            
+#define RTC_TAMPCR_TAMP2NOERASE_Pos          (20U)                             
+#define RTC_TAMPCR_TAMP2NOERASE_Msk          (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE              RTC_TAMPCR_TAMP2NOERASE_Msk       
+#define RTC_TAMPCR_TAMP2IE_Pos               (19U)                             
+#define RTC_TAMPCR_TAMP2IE_Msk               (0x1U << RTC_TAMPCR_TAMP2IE_Pos)  /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE                   RTC_TAMPCR_TAMP2IE_Msk            
+#define RTC_TAMPCR_TAMP1MF_Pos               (18U)                             
+#define RTC_TAMPCR_TAMP1MF_Msk               (0x1U << RTC_TAMPCR_TAMP1MF_Pos)  /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF                   RTC_TAMPCR_TAMP1MF_Msk            
+#define RTC_TAMPCR_TAMP1NOERASE_Pos          (17U)                             
+#define RTC_TAMPCR_TAMP1NOERASE_Msk          (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE              RTC_TAMPCR_TAMP1NOERASE_Msk       
+#define RTC_TAMPCR_TAMP1IE_Pos               (16U)                             
+#define RTC_TAMPCR_TAMP1IE_Msk               (0x1U << RTC_TAMPCR_TAMP1IE_Pos)  /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE                   RTC_TAMPCR_TAMP1IE_Msk            
+#define RTC_TAMPCR_TAMPPUDIS_Pos             (15U)                             
+#define RTC_TAMPCR_TAMPPUDIS_Msk             (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS                 RTC_TAMPCR_TAMPPUDIS_Msk          
+#define RTC_TAMPCR_TAMPPRCH_Pos              (13U)                             
+#define RTC_TAMPCR_TAMPPRCH_Msk              (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH                  RTC_TAMPCR_TAMPPRCH_Msk           
+#define RTC_TAMPCR_TAMPPRCH_0                (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1                (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos               (11U)                             
+#define RTC_TAMPCR_TAMPFLT_Msk               (0x3U << RTC_TAMPCR_TAMPFLT_Pos)  /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT                   RTC_TAMPCR_TAMPFLT_Msk            
+#define RTC_TAMPCR_TAMPFLT_0                 (0x1U << RTC_TAMPCR_TAMPFLT_Pos)  /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1                 (0x2U << RTC_TAMPCR_TAMPFLT_Pos)  /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos              (8U)                              
+#define RTC_TAMPCR_TAMPFREQ_Msk              (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ                  RTC_TAMPCR_TAMPFREQ_Msk           
+#define RTC_TAMPCR_TAMPFREQ_0                (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1                (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2                (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos                (7U)                              
+#define RTC_TAMPCR_TAMPTS_Msk                (0x1U << RTC_TAMPCR_TAMPTS_Pos)   /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS                    RTC_TAMPCR_TAMPTS_Msk             
+#define RTC_TAMPCR_TAMP3TRG_Pos              (6U)                              
+#define RTC_TAMPCR_TAMP3TRG_Msk              (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG                  RTC_TAMPCR_TAMP3TRG_Msk           
+#define RTC_TAMPCR_TAMP3E_Pos                (5U)                              
+#define RTC_TAMPCR_TAMP3E_Msk                (0x1U << RTC_TAMPCR_TAMP3E_Pos)   /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E                    RTC_TAMPCR_TAMP3E_Msk             
+#define RTC_TAMPCR_TAMP2TRG_Pos              (4U)                              
+#define RTC_TAMPCR_TAMP2TRG_Msk              (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG                  RTC_TAMPCR_TAMP2TRG_Msk           
+#define RTC_TAMPCR_TAMP2E_Pos                (3U)                              
+#define RTC_TAMPCR_TAMP2E_Msk                (0x1U << RTC_TAMPCR_TAMP2E_Pos)   /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E                    RTC_TAMPCR_TAMP2E_Msk             
+#define RTC_TAMPCR_TAMPIE_Pos                (2U)                              
+#define RTC_TAMPCR_TAMPIE_Msk                (0x1U << RTC_TAMPCR_TAMPIE_Pos)   /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE                    RTC_TAMPCR_TAMPIE_Msk             
+#define RTC_TAMPCR_TAMP1TRG_Pos              (1U)                              
+#define RTC_TAMPCR_TAMP1TRG_Msk              (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG                  RTC_TAMPCR_TAMP1TRG_Msk           
+#define RTC_TAMPCR_TAMP1E_Pos                (0U)                              
+#define RTC_TAMPCR_TAMP1E_Msk                (0x1U << RTC_TAMPCR_TAMP1E_Pos)   /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E                    RTC_TAMPCR_TAMP1E_Msk             
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos              (24U)                             
+#define RTC_ALRMASSR_MASKSS_Msk              (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk           
+#define RTC_ALRMASSR_MASKSS_0                (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1                (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2                (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3                (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos                  (0U)                              
+#define RTC_ALRMASSR_SS_Msk                  (0x7FFFU << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk               
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos              (24U)                             
+#define RTC_ALRMBSSR_MASKSS_Msk              (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk           
+#define RTC_ALRMBSSR_MASKSS_0                (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1                (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2                (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3                (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos                  (0U)                              
+#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFU << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk               
+
+/********************  Bits definition for RTC_0R register  *******************/
+#define RTC_OR_OUT_RMP_Pos                   (1U)                              
+#define RTC_OR_OUT_RMP_Msk                   (0x1U << RTC_OR_OUT_RMP_Pos)      /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                       RTC_OR_OUT_RMP_Msk                
+#define RTC_OR_ALARMOUTTYPE_Pos              (0U)                              
+#define RTC_OR_ALARMOUTTYPE_Msk              (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE                  RTC_OR_ALARMOUTTYPE_Msk           
+
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                        (0U)                              
+#define RTC_BKP0R_Msk                        (0xFFFFFFFFU << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                            RTC_BKP0R_Msk                     
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                        (0U)                              
+#define RTC_BKP1R_Msk                        (0xFFFFFFFFU << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                            RTC_BKP1R_Msk                     
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                        (0U)                              
+#define RTC_BKP2R_Msk                        (0xFFFFFFFFU << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                            RTC_BKP2R_Msk                     
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                        (0U)                              
+#define RTC_BKP3R_Msk                        (0xFFFFFFFFU << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                            RTC_BKP3R_Msk                     
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                        (0U)                              
+#define RTC_BKP4R_Msk                        (0xFFFFFFFFU << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                            RTC_BKP4R_Msk                     
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                        (0U)                              
+#define RTC_BKP5R_Msk                        (0xFFFFFFFFU << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                            RTC_BKP5R_Msk                     
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                        (0U)                              
+#define RTC_BKP6R_Msk                        (0xFFFFFFFFU << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                            RTC_BKP6R_Msk                     
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                        (0U)                              
+#define RTC_BKP7R_Msk                        (0xFFFFFFFFU << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                            RTC_BKP7R_Msk                     
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                        (0U)                              
+#define RTC_BKP8R_Msk                        (0xFFFFFFFFU << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                            RTC_BKP8R_Msk                     
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                        (0U)                              
+#define RTC_BKP9R_Msk                        (0xFFFFFFFFU << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                            RTC_BKP9R_Msk                     
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                       (0U)                              
+#define RTC_BKP10R_Msk                       (0xFFFFFFFFU << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                           RTC_BKP10R_Msk                    
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                       (0U)                              
+#define RTC_BKP11R_Msk                       (0xFFFFFFFFU << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                           RTC_BKP11R_Msk                    
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                       (0U)                              
+#define RTC_BKP12R_Msk                       (0xFFFFFFFFU << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                           RTC_BKP12R_Msk                    
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                       (0U)                              
+#define RTC_BKP13R_Msk                       (0xFFFFFFFFU << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                           RTC_BKP13R_Msk                    
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                       (0U)                              
+#define RTC_BKP14R_Msk                       (0xFFFFFFFFU << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                           RTC_BKP14R_Msk                    
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                       (0U)                              
+#define RTC_BKP15R_Msk                       (0xFFFFFFFFU << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                           RTC_BKP15R_Msk                    
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                       (0U)                              
+#define RTC_BKP16R_Msk                       (0xFFFFFFFFU << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                           RTC_BKP16R_Msk                    
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                       (0U)                              
+#define RTC_BKP17R_Msk                       (0xFFFFFFFFU << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                           RTC_BKP17R_Msk                    
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                       (0U)                              
+#define RTC_BKP18R_Msk                       (0xFFFFFFFFU << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                           RTC_BKP18R_Msk                    
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                       (0U)                              
+#define RTC_BKP19R_Msk                       (0xFFFFFFFFU << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                           RTC_BKP19R_Msk                    
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R_Pos                       (0U)                              
+#define RTC_BKP20R_Msk                       (0xFFFFFFFFU << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP20R                           RTC_BKP20R_Msk                    
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R_Pos                       (0U)                              
+#define RTC_BKP21R_Msk                       (0xFFFFFFFFU << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP21R                           RTC_BKP21R_Msk                    
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R_Pos                       (0U)                              
+#define RTC_BKP22R_Msk                       (0xFFFFFFFFU << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP22R                           RTC_BKP22R_Msk                    
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R_Pos                       (0U)                              
+#define RTC_BKP23R_Msk                       (0xFFFFFFFFU << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP23R                           RTC_BKP23R_Msk                    
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R_Pos                       (0U)                              
+#define RTC_BKP24R_Msk                       (0xFFFFFFFFU << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP24R                           RTC_BKP24R_Msk                    
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R_Pos                       (0U)                              
+#define RTC_BKP25R_Msk                       (0xFFFFFFFFU << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP25R                           RTC_BKP25R_Msk                    
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R_Pos                       (0U)                              
+#define RTC_BKP26R_Msk                       (0xFFFFFFFFU << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP26R                           RTC_BKP26R_Msk                    
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R_Pos                       (0U)                              
+#define RTC_BKP27R_Msk                       (0xFFFFFFFFU << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP27R                           RTC_BKP27R_Msk                    
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R_Pos                       (0U)                              
+#define RTC_BKP28R_Msk                       (0xFFFFFFFFU << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP28R                           RTC_BKP28R_Msk                    
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R_Pos                       (0U)                              
+#define RTC_BKP29R_Msk                       (0xFFFFFFFFU << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP29R                           RTC_BKP29R_Msk                    
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R_Pos                       (0U)                              
+#define RTC_BKP30R_Msk                       (0xFFFFFFFFU << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP30R                           RTC_BKP30R_Msk                    
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R_Pos                       (0U)                              
+#define RTC_BKP31R_Msk                       (0xFFFFFFFFU << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_BKP31R                           RTC_BKP31R_Msk                    
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       32U
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos               (0U)                                  
+#define SAI_GCR_SYNCIN_Msk               (0x3U << SAI_GCR_SYNCIN_Pos)          /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN                   SAI_GCR_SYNCIN_Msk                    /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0                 (0x1U << SAI_GCR_SYNCIN_Pos)          /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1                 (0x2U << SAI_GCR_SYNCIN_Pos)          /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos              (4U)                                  
+#define SAI_GCR_SYNCOUT_Msk              (0x3U << SAI_GCR_SYNCOUT_Pos)         /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT                  SAI_GCR_SYNCOUT_Msk                   /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0                (0x1U << SAI_GCR_SYNCOUT_Pos)         /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1                (0x2U << SAI_GCR_SYNCOUT_Pos)         /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos                (0U)                                  
+#define SAI_xCR1_MODE_Msk                (0x3U << SAI_xCR1_MODE_Pos)           /*!< 0x00000003 */
+#define SAI_xCR1_MODE                    SAI_xCR1_MODE_Msk                     /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0                  (0x1U << SAI_xCR1_MODE_Pos)           /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1                  (0x2U << SAI_xCR1_MODE_Pos)           /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos              (2U)                                  
+#define SAI_xCR1_PRTCFG_Msk              (0x3U << SAI_xCR1_PRTCFG_Pos)         /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG                  SAI_xCR1_PRTCFG_Msk                   /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0                (0x1U << SAI_xCR1_PRTCFG_Pos)         /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1                (0x2U << SAI_xCR1_PRTCFG_Pos)         /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos                  (5U)                                  
+#define SAI_xCR1_DS_Msk                  (0x7U << SAI_xCR1_DS_Pos)             /*!< 0x000000E0 */
+#define SAI_xCR1_DS                      SAI_xCR1_DS_Msk                       /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0                    (0x1U << SAI_xCR1_DS_Pos)             /*!< 0x00000020 */
+#define SAI_xCR1_DS_1                    (0x2U << SAI_xCR1_DS_Pos)             /*!< 0x00000040 */
+#define SAI_xCR1_DS_2                    (0x4U << SAI_xCR1_DS_Pos)             /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos            (8U)                                  
+#define SAI_xCR1_LSBFIRST_Msk            (0x1U << SAI_xCR1_LSBFIRST_Pos)       /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST                SAI_xCR1_LSBFIRST_Msk                 /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos               (9U)                                  
+#define SAI_xCR1_CKSTR_Msk               (0x1U << SAI_xCR1_CKSTR_Pos)          /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR                   SAI_xCR1_CKSTR_Msk                    /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos              (10U)                                 
+#define SAI_xCR1_SYNCEN_Msk              (0x3U << SAI_xCR1_SYNCEN_Pos)         /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN                  SAI_xCR1_SYNCEN_Msk                   /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0                (0x1U << SAI_xCR1_SYNCEN_Pos)         /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1                (0x2U << SAI_xCR1_SYNCEN_Pos)         /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos                (12U)                                 
+#define SAI_xCR1_MONO_Msk                (0x1U << SAI_xCR1_MONO_Pos)           /*!< 0x00001000 */
+#define SAI_xCR1_MONO                    SAI_xCR1_MONO_Msk                     /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos             (13U)                                 
+#define SAI_xCR1_OUTDRIV_Msk             (0x1U << SAI_xCR1_OUTDRIV_Pos)        /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV                 SAI_xCR1_OUTDRIV_Msk                  /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos               (16U)                                 
+#define SAI_xCR1_SAIEN_Msk               (0x1U << SAI_xCR1_SAIEN_Pos)          /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN                   SAI_xCR1_SAIEN_Msk                    /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos               (17U)                                 
+#define SAI_xCR1_DMAEN_Msk               (0x1U << SAI_xCR1_DMAEN_Pos)          /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN                   SAI_xCR1_DMAEN_Msk                    /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos               (19U)                                 
+#define SAI_xCR1_NODIV_Msk               (0x1U << SAI_xCR1_NODIV_Pos)          /*!< 0x00080000 */
+#define SAI_xCR1_NODIV                   SAI_xCR1_NODIV_Msk                    /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos              (20U)                                 
+#define SAI_xCR1_MCKDIV_Msk              (0xFU << SAI_xCR1_MCKDIV_Pos)         /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV                  SAI_xCR1_MCKDIV_Msk                   /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0                (0x00100000U)                         /*!<Bit 0  */
+#define SAI_xCR1_MCKDIV_1                (0x00200000U)                         /*!<Bit 1  */
+#define SAI_xCR1_MCKDIV_2                (0x00400000U)                         /*!<Bit 2  */
+#define SAI_xCR1_MCKDIV_3                (0x00800000U)                         /*!<Bit 3  */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos                 (0U)                                  
+#define SAI_xCR2_FTH_Msk                 (0x7U << SAI_xCR2_FTH_Pos)            /*!< 0x00000007 */
+#define SAI_xCR2_FTH                     SAI_xCR2_FTH_Msk                      /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0                   (0x1U << SAI_xCR2_FTH_Pos)            /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1                   (0x2U << SAI_xCR2_FTH_Pos)            /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2                   (0x4U << SAI_xCR2_FTH_Pos)            /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos              (3U)                                  
+#define SAI_xCR2_FFLUSH_Msk              (0x1U << SAI_xCR2_FFLUSH_Pos)         /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH                  SAI_xCR2_FFLUSH_Msk                   /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos                (4U)                                  
+#define SAI_xCR2_TRIS_Msk                (0x1U << SAI_xCR2_TRIS_Pos)           /*!< 0x00000010 */
+#define SAI_xCR2_TRIS                    SAI_xCR2_TRIS_Msk                     /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos                (5U)                                  
+#define SAI_xCR2_MUTE_Msk                (0x1U << SAI_xCR2_MUTE_Pos)           /*!< 0x00000020 */
+#define SAI_xCR2_MUTE                    SAI_xCR2_MUTE_Msk                     /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos             (6U)                                  
+#define SAI_xCR2_MUTEVAL_Msk             (0x1U << SAI_xCR2_MUTEVAL_Pos)        /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL                 SAI_xCR2_MUTEVAL_Msk                  /*!<Muate value                      */
+
+
+#define SAI_xCR2_MUTECNT_Pos             (7U)                                  
+#define SAI_xCR2_MUTECNT_Msk             (0x3FU << SAI_xCR2_MUTECNT_Pos)       /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT                 SAI_xCR2_MUTECNT_Msk                  /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0               (0x01U << SAI_xCR2_MUTECNT_Pos)       /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1               (0x02U << SAI_xCR2_MUTECNT_Pos)       /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2               (0x04U << SAI_xCR2_MUTECNT_Pos)       /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3               (0x08U << SAI_xCR2_MUTECNT_Pos)       /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4               (0x10U << SAI_xCR2_MUTECNT_Pos)       /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5               (0x20U << SAI_xCR2_MUTECNT_Pos)       /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos                 (13U)                                 
+#define SAI_xCR2_CPL_Msk                 (0x1U << SAI_xCR2_CPL_Pos)            /*!< 0x00002000 */
+#define SAI_xCR2_CPL                     SAI_xCR2_CPL_Msk                      /*!<CPL mode                    */
+#define SAI_xCR2_COMP_Pos                (14U)                                 
+#define SAI_xCR2_COMP_Msk                (0x3U << SAI_xCR2_COMP_Pos)           /*!< 0x0000C000 */
+#define SAI_xCR2_COMP                    SAI_xCR2_COMP_Msk                     /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0                  (0x1U << SAI_xCR2_COMP_Pos)           /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1                  (0x2U << SAI_xCR2_COMP_Pos)           /*!< 0x00008000 */
+
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos                (0U)                                  
+#define SAI_xFRCR_FRL_Msk                (0xFFU << SAI_xFRCR_FRL_Pos)          /*!< 0x000000FF */
+#define SAI_xFRCR_FRL                    SAI_xFRCR_FRL_Msk                     /*!<FRL[7:0](Frame length)  */
+#define SAI_xFRCR_FRL_0                  (0x01U << SAI_xFRCR_FRL_Pos)          /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1                  (0x02U << SAI_xFRCR_FRL_Pos)          /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2                  (0x04U << SAI_xFRCR_FRL_Pos)          /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3                  (0x08U << SAI_xFRCR_FRL_Pos)          /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4                  (0x10U << SAI_xFRCR_FRL_Pos)          /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5                  (0x20U << SAI_xFRCR_FRL_Pos)          /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6                  (0x40U << SAI_xFRCR_FRL_Pos)          /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7                  (0x80U << SAI_xFRCR_FRL_Pos)          /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos              (8U)                                  
+#define SAI_xFRCR_FSALL_Msk              (0x7FU << SAI_xFRCR_FSALL_Pos)        /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL                  SAI_xFRCR_FSALL_Msk                   /*!<FRL[6:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0                (0x01U << SAI_xFRCR_FSALL_Pos)        /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1                (0x02U << SAI_xFRCR_FSALL_Pos)        /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2                (0x04U << SAI_xFRCR_FSALL_Pos)        /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3                (0x08U << SAI_xFRCR_FSALL_Pos)        /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4                (0x10U << SAI_xFRCR_FSALL_Pos)        /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5                (0x20U << SAI_xFRCR_FSALL_Pos)        /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6                (0x40U << SAI_xFRCR_FSALL_Pos)        /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos              (16U)                                 
+#define SAI_xFRCR_FSDEF_Msk              (0x1U << SAI_xFRCR_FSDEF_Pos)         /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF                  SAI_xFRCR_FSDEF_Msk                   /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos              (17U)                                 
+#define SAI_xFRCR_FSPOL_Msk              (0x1U << SAI_xFRCR_FSPOL_Pos)         /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL                  SAI_xFRCR_FSPOL_Msk                   /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos              (18U)                                 
+#define SAI_xFRCR_FSOFF_Msk              (0x1U << SAI_xFRCR_FSOFF_Pos)         /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF                  SAI_xFRCR_FSOFF_Msk                   /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos             (0U)                                  
+#define SAI_xSLOTR_FBOFF_Msk             (0x1FU << SAI_xSLOTR_FBOFF_Pos)       /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF                 SAI_xSLOTR_FBOFF_Msk                  /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0               (0x01U << SAI_xSLOTR_FBOFF_Pos)       /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1               (0x02U << SAI_xSLOTR_FBOFF_Pos)       /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2               (0x04U << SAI_xSLOTR_FBOFF_Pos)       /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3               (0x08U << SAI_xSLOTR_FBOFF_Pos)       /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4               (0x10U << SAI_xSLOTR_FBOFF_Pos)       /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos            (6U)                                  
+#define SAI_xSLOTR_SLOTSZ_Msk            (0x3U << SAI_xSLOTR_SLOTSZ_Pos)       /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ                SAI_xSLOTR_SLOTSZ_Msk                 /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0              (0x1U << SAI_xSLOTR_SLOTSZ_Pos)       /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1              (0x2U << SAI_xSLOTR_SLOTSZ_Pos)       /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos            (8U)                                  
+#define SAI_xSLOTR_NBSLOT_Msk            (0xFU << SAI_xSLOTR_NBSLOT_Pos)       /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT                SAI_xSLOTR_NBSLOT_Msk                 /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0              (0x1U << SAI_xSLOTR_NBSLOT_Pos)       /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1              (0x2U << SAI_xSLOTR_NBSLOT_Pos)       /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2              (0x4U << SAI_xSLOTR_NBSLOT_Pos)       /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3              (0x8U << SAI_xSLOTR_NBSLOT_Pos)       /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos            (16U)                                 
+#define SAI_xSLOTR_SLOTEN_Msk            (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)    /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN                SAI_xSLOTR_SLOTEN_Msk                 /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos            (0U)                                  
+#define SAI_xIMR_OVRUDRIE_Msk            (0x1U << SAI_xIMR_OVRUDRIE_Pos)       /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE                SAI_xIMR_OVRUDRIE_Msk                 /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos           (1U)                                  
+#define SAI_xIMR_MUTEDETIE_Msk           (0x1U << SAI_xIMR_MUTEDETIE_Pos)      /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE               SAI_xIMR_MUTEDETIE_Msk                /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos            (2U)                                  
+#define SAI_xIMR_WCKCFGIE_Msk            (0x1U << SAI_xIMR_WCKCFGIE_Pos)       /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE                SAI_xIMR_WCKCFGIE_Msk                 /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos              (3U)                                  
+#define SAI_xIMR_FREQIE_Msk              (0x1U << SAI_xIMR_FREQIE_Pos)         /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE                  SAI_xIMR_FREQIE_Msk                   /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos             (4U)                                  
+#define SAI_xIMR_CNRDYIE_Msk             (0x1U << SAI_xIMR_CNRDYIE_Pos)        /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE                 SAI_xIMR_CNRDYIE_Msk                  /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos            (5U)                                  
+#define SAI_xIMR_AFSDETIE_Msk            (0x1U << SAI_xIMR_AFSDETIE_Pos)       /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE                SAI_xIMR_AFSDETIE_Msk                 /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos            (6U)                                  
+#define SAI_xIMR_LFSDETIE_Msk            (0x1U << SAI_xIMR_LFSDETIE_Pos)       /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE                SAI_xIMR_LFSDETIE_Msk                 /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos               (0U)                                  
+#define SAI_xSR_OVRUDR_Msk               (0x1U << SAI_xSR_OVRUDR_Pos)          /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR                   SAI_xSR_OVRUDR_Msk                    /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos              (1U)                                  
+#define SAI_xSR_MUTEDET_Msk              (0x1U << SAI_xSR_MUTEDET_Pos)         /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET                  SAI_xSR_MUTEDET_Msk                   /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos               (2U)                                  
+#define SAI_xSR_WCKCFG_Msk               (0x1U << SAI_xSR_WCKCFG_Pos)          /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG                   SAI_xSR_WCKCFG_Msk                    /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos                 (3U)                                  
+#define SAI_xSR_FREQ_Msk                 (0x1U << SAI_xSR_FREQ_Pos)            /*!< 0x00000008 */
+#define SAI_xSR_FREQ                     SAI_xSR_FREQ_Msk                      /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos                (4U)                                  
+#define SAI_xSR_CNRDY_Msk                (0x1U << SAI_xSR_CNRDY_Pos)           /*!< 0x00000010 */
+#define SAI_xSR_CNRDY                    SAI_xSR_CNRDY_Msk                     /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos               (5U)                                  
+#define SAI_xSR_AFSDET_Msk               (0x1U << SAI_xSR_AFSDET_Pos)          /*!< 0x00000020 */
+#define SAI_xSR_AFSDET                   SAI_xSR_AFSDET_Msk                    /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos               (6U)                                  
+#define SAI_xSR_LFSDET_Msk               (0x1U << SAI_xSR_LFSDET_Pos)          /*!< 0x00000040 */
+#define SAI_xSR_LFSDET                   SAI_xSR_LFSDET_Msk                    /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos                 (16U)                                 
+#define SAI_xSR_FLVL_Msk                 (0x7U << SAI_xSR_FLVL_Pos)            /*!< 0x00070000 */
+#define SAI_xSR_FLVL                     SAI_xSR_FLVL_Msk                      /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0                   (0x1U << SAI_xSR_FLVL_Pos)            /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1                   (0x2U << SAI_xSR_FLVL_Pos)            /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2                   (0x4U << SAI_xSR_FLVL_Pos)            /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos           (0U)                                  
+#define SAI_xCLRFR_COVRUDR_Msk           (0x1U << SAI_xCLRFR_COVRUDR_Pos)      /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR               SAI_xCLRFR_COVRUDR_Msk                /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos          (1U)                                  
+#define SAI_xCLRFR_CMUTEDET_Msk          (0x1U << SAI_xCLRFR_CMUTEDET_Pos)     /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET              SAI_xCLRFR_CMUTEDET_Msk               /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos           (2U)                                  
+#define SAI_xCLRFR_CWCKCFG_Msk           (0x1U << SAI_xCLRFR_CWCKCFG_Pos)      /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG               SAI_xCLRFR_CWCKCFG_Msk                /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos             (3U)                                  
+#define SAI_xCLRFR_CFREQ_Msk             (0x1U << SAI_xCLRFR_CFREQ_Pos)        /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ                 SAI_xCLRFR_CFREQ_Msk                  /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos            (4U)                                  
+#define SAI_xCLRFR_CCNRDY_Msk            (0x1U << SAI_xCLRFR_CCNRDY_Pos)       /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY                SAI_xCLRFR_CCNRDY_Msk                 /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos           (5U)                                  
+#define SAI_xCLRFR_CAFSDET_Msk           (0x1U << SAI_xCLRFR_CAFSDET_Pos)      /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET               SAI_xCLRFR_CAFSDET_Msk                /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos           (6U)                                  
+#define SAI_xCLRFR_CLFSDET_Msk           (0x1U << SAI_xCLRFR_CLFSDET_Pos)      /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET               SAI_xCLRFR_CLFSDET_Msk                /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos                 (0U)                                  
+#define SAI_xDR_DATA_Msk                 (0xFFFFFFFFU << SAI_xDR_DATA_Pos)     /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA                     SAI_xDR_DATA_Msk                      
+
+/******************************************************************************/
+/*                                                                            */
+/*                          LCD Controller (LCD)                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for LCD_CR register  *********************/
+#define LCD_CR_LCDEN_Pos           (0U)                                        
+#define LCD_CR_LCDEN_Msk           (0x1U << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
+#define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
+#define LCD_CR_VSEL_Pos            (1U)                                        
+#define LCD_CR_VSEL_Msk            (0x1U << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
+#define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY_Pos            (2U)                                        
+#define LCD_CR_DUTY_Msk            (0x7U << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
+#define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0              (0x1U << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
+#define LCD_CR_DUTY_1              (0x2U << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
+#define LCD_CR_DUTY_2              (0x4U << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
+
+#define LCD_CR_BIAS_Pos            (5U)                                        
+#define LCD_CR_BIAS_Msk            (0x3U << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
+#define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0              (0x1U << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
+#define LCD_CR_BIAS_1              (0x2U << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
+
+#define LCD_CR_MUX_SEG_Pos         (7U)                                        
+#define LCD_CR_MUX_SEG_Msk         (0x1U << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
+#define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
+#define LCD_CR_BUFEN_Pos           (8U)                                        
+#define LCD_CR_BUFEN_Msk           (0x1U << LCD_CR_BUFEN_Pos)                  /*!< 0x00000100 */
+#define LCD_CR_BUFEN               LCD_CR_BUFEN_Msk                            /*!< Voltage output buffer enable */
+
+/*******************  Bit definition for LCD_FCR register  ********************/
+#define LCD_FCR_HD_Pos             (0U)                                        
+#define LCD_FCR_HD_Msk             (0x1U << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
+#define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE_Pos          (1U)                                        
+#define LCD_FCR_SOFIE_Msk          (0x1U << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
+#define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE_Pos          (3U)                                        
+#define LCD_FCR_UDDIE_Msk          (0x1U << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
+#define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON_Pos            (4U)                                        
+#define LCD_FCR_PON_Msk            (0x7U << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
+#define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Pulse ON Duration) */
+#define LCD_FCR_PON_0              (0x1U << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
+#define LCD_FCR_PON_1              (0x2U << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
+#define LCD_FCR_PON_2              (0x4U << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
+
+#define LCD_FCR_DEAD_Pos           (7U)                                        
+#define LCD_FCR_DEAD_Msk           (0x7U << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
+#define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0             (0x1U << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
+#define LCD_FCR_DEAD_1             (0x2U << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
+#define LCD_FCR_DEAD_2             (0x4U << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
+
+#define LCD_FCR_CC_Pos             (10U)                                       
+#define LCD_FCR_CC_Msk             (0x7U << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
+#define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0               (0x1U << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
+#define LCD_FCR_CC_1               (0x2U << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
+#define LCD_FCR_CC_2               (0x4U << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
+
+#define LCD_FCR_BLINKF_Pos         (13U)                                       
+#define LCD_FCR_BLINKF_Msk         (0x7U << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
+#define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0           (0x1U << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
+#define LCD_FCR_BLINKF_1           (0x2U << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
+#define LCD_FCR_BLINKF_2           (0x4U << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
+
+#define LCD_FCR_BLINK_Pos          (16U)                                       
+#define LCD_FCR_BLINK_Msk          (0x3U << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
+#define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0            (0x1U << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
+#define LCD_FCR_BLINK_1            (0x2U << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
+
+#define LCD_FCR_DIV_Pos            (18U)                                       
+#define LCD_FCR_DIV_Msk            (0xFU << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
+#define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS_Pos             (22U)                                       
+#define LCD_FCR_PS_Msk             (0xFU << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
+#define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
+
+/*******************  Bit definition for LCD_SR register  *********************/
+#define LCD_SR_ENS_Pos             (0U)                                        
+#define LCD_SR_ENS_Msk             (0x1U << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
+#define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
+#define LCD_SR_SOF_Pos             (1U)                                        
+#define LCD_SR_SOF_Msk             (0x1U << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
+#define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR_Pos             (2U)                                        
+#define LCD_SR_UDR_Msk             (0x1U << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
+#define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
+#define LCD_SR_UDD_Pos             (3U)                                        
+#define LCD_SR_UDD_Msk             (0x1U << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
+#define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY_Pos             (4U)                                        
+#define LCD_SR_RDY_Msk             (0x1U << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
+#define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR_Pos           (5U)                                        
+#define LCD_SR_FCRSR_Msk           (0x1U << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
+#define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
+
+/*******************  Bit definition for LCD_CLR register  ********************/
+#define LCD_CLR_SOFC_Pos           (1U)                                        
+#define LCD_CLR_SOFC_Msk           (0x1U << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
+#define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC_Pos           (3U)                                        
+#define LCD_CLR_UDDC_Msk           (0x1U << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
+#define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
+
+/*******************  Bit definition for LCD_RAM register  ********************/
+#define LCD_RAM_SEGMENT_DATA_Pos   (0U)                                        
+#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
+#define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos              (0U)                              
+#define SDMMC_POWER_PWRCTRL_Msk              (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL                  SDMMC_POWER_PWRCTRL_Msk           /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0                (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1                (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos               (0U)                              
+#define SDMMC_CLKCR_CLKDIV_Msk               (0xFFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDMMC_CLKCR_CLKDIV                   SDMMC_CLKCR_CLKDIV_Msk            /*!<Clock divide factor             */
+#define SDMMC_CLKCR_CLKEN_Pos                (8U)                              
+#define SDMMC_CLKCR_CLKEN_Msk                (0x1U << SDMMC_CLKCR_CLKEN_Pos)   /*!< 0x00000100 */
+#define SDMMC_CLKCR_CLKEN                    SDMMC_CLKCR_CLKEN_Msk             /*!<Clock enable bit                */
+#define SDMMC_CLKCR_PWRSAV_Pos               (9U)                              
+#define SDMMC_CLKCR_PWRSAV_Msk               (0x1U << SDMMC_CLKCR_PWRSAV_Pos)  /*!< 0x00000200 */
+#define SDMMC_CLKCR_PWRSAV                   SDMMC_CLKCR_PWRSAV_Msk            /*!<Power saving configuration bit  */
+#define SDMMC_CLKCR_BYPASS_Pos               (10U)                              
+#define SDMMC_CLKCR_BYPASS_Msk               (0x1U << SDMMC_CLKCR_BYPASS_Pos)  /*!< 0x00000400 */
+#define SDMMC_CLKCR_BYPASS                   SDMMC_CLKCR_BYPASS_Msk            /*!<Clock divider bypass enable bit */
+#define SDMMC_CLKCR_WIDBUS_Pos               (11U)                              
+#define SDMMC_CLKCR_WIDBUS_Msk               (0x3U << SDMMC_CLKCR_WIDBUS_Pos)  /*!< 0x00001800 */
+#define SDMMC_CLKCR_WIDBUS                   SDMMC_CLKCR_WIDBUS_Msk            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0                 (0x1U << SDMMC_CLKCR_WIDBUS_Pos)  /*!< 0x00000800 */
+#define SDMMC_CLKCR_WIDBUS_1                 (0x2U << SDMMC_CLKCR_WIDBUS_Pos)  /*!< 0x00001000 */
+#define SDMMC_CLKCR_NEGEDGE_Pos              (13U)                              
+#define SDMMC_CLKCR_NEGEDGE_Msk              (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDMMC_CLKCR_NEGEDGE                  SDMMC_CLKCR_NEGEDGE_Msk           /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos              (14U)                              
+#define SDMMC_CLKCR_HWFC_EN_Msk              (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDMMC_CLKCR_HWFC_EN                  SDMMC_CLKCR_HWFC_EN_Msk           /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos                 (0U)                              
+#define SDMMC_ARG_CMDARG_Msk                 (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                     SDMMC_ARG_CMDARG_Msk              /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos               (0U)                              
+#define SDMMC_CMD_CMDINDEX_Msk               (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX                   SDMMC_CMD_CMDINDEX_Msk            /*!<Command Index                               */
+#define SDMMC_CMD_WAITRESP_Pos               (6U)                              
+#define SDMMC_CMD_WAITRESP_Msk               (0x3U << SDMMC_CMD_WAITRESP_Pos)  /*!< 0x000000C0 */
+#define SDMMC_CMD_WAITRESP                   SDMMC_CMD_WAITRESP_Msk            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0                 (0x1U << SDMMC_CMD_WAITRESP_Pos)  /*!< 0x00000040 */
+#define SDMMC_CMD_WAITRESP_1                 (0x2U << SDMMC_CMD_WAITRESP_Pos)  /*!< 0x00000080 */
+#define SDMMC_CMD_WAITINT_Pos                (8U)                              
+#define SDMMC_CMD_WAITINT_Msk                (0x1U << SDMMC_CMD_WAITINT_Pos)   /*!< 0x00000100 */
+#define SDMMC_CMD_WAITINT                    SDMMC_CMD_WAITINT_Msk             /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos               (9U)                              
+#define SDMMC_CMD_WAITPEND_Msk               (0x1U << SDMMC_CMD_WAITPEND_Pos)  /*!< 0x00000200 */
+#define SDMMC_CMD_WAITPEND                   SDMMC_CMD_WAITPEND_Msk            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos                 (10U)                              
+#define SDMMC_CMD_CPSMEN_Msk                 (0x1U << SDMMC_CMD_CPSMEN_Pos)    /*!< 0x00000400 */
+#define SDMMC_CMD_CPSMEN                     SDMMC_CMD_CPSMEN_Msk              /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_SDIOSUSPEND_Pos            (11U)                              
+#define SDMMC_CMD_SDIOSUSPEND_Msk            (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDMMC_CMD_SDIOSUSPEND                SDMMC_CMD_SDIOSUSPEND_Msk           /*!<SD I/O suspend command                                       */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos            (0U)                              
+#define SDMMC_RESPCMD_RESPCMD_Msk            (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD                SDMMC_RESPCMD_RESPCMD_Msk         /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP0 register  ******************/
+#define SDMMC_RESP0_CARDSTATUS0_Pos          (0U)                              
+#define SDMMC_RESP0_CARDSTATUS0_Msk          (0xFFFFFFFFU << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP0_CARDSTATUS0              SDMMC_RESP0_CARDSTATUS0_Msk       /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos          (0U)                              
+#define SDMMC_RESP1_CARDSTATUS1_Msk          (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1              SDMMC_RESP1_CARDSTATUS1_Msk       /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos          (0U)                              
+#define SDMMC_RESP2_CARDSTATUS2_Msk          (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2              SDMMC_RESP2_CARDSTATUS2_Msk       /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos          (0U)                              
+#define SDMMC_RESP3_CARDSTATUS3_Msk          (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3              SDMMC_RESP3_CARDSTATUS3_Msk       /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos          (0U)                              
+#define SDMMC_RESP4_CARDSTATUS4_Msk          (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4              SDMMC_RESP4_CARDSTATUS4_Msk       /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos            (0U)                              
+#define SDMMC_DTIMER_DATATIME_Msk            (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME                SDMMC_DTIMER_DATATIME_Msk         /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos            (0U)                              
+#define SDMMC_DLEN_DATALENGTH_Msk            (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH                SDMMC_DLEN_DATALENGTH_Msk         /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos                 (0U)                              
+#define SDMMC_DCTRL_DTEN_Msk                 (0x1U << SDMMC_DCTRL_DTEN_Pos)    /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                     SDMMC_DCTRL_DTEN_Msk              /*!<Data transfer enabled bit         */
+#define SDMMC_DCTRL_DTDIR_Pos                (1U)                              
+#define SDMMC_DCTRL_DTDIR_Msk                (0x1U << SDMMC_DCTRL_DTDIR_Pos)   /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR                    SDMMC_DCTRL_DTDIR_Msk             /*!<Data transfer direction selection */
+#define SDMMC_DCTRL_DTMODE_Pos               (2U)                              
+#define SDMMC_DCTRL_DTMODE_Msk               (0x1U << SDMMC_DCTRL_DTMODE_Pos)  /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE                   SDMMC_DCTRL_DTMODE_Msk            /*!<Data transfer mode selection      */
+#define SDMMC_DCTRL_DMAEN_Pos                (3U)                              
+#define SDMMC_DCTRL_DMAEN_Msk                (0x1U << SDMMC_DCTRL_DMAEN_Pos)   /*!< 0x00000008 */
+#define SDMMC_DCTRL_DMAEN                    SDMMC_DCTRL_DMAEN_Msk             /*!<DMA enabled bit                   */
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos           (4U)                              
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk           (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE               SDMMC_DCTRL_DBLOCKSIZE_Msk        /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0             (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1             (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2             (0x3U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3             (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
+#define SDMMC_DCTRL_RWSTART_Pos              (8U)                              
+#define SDMMC_DCTRL_RWSTART_Msk              (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART                  SDMMC_DCTRL_RWSTART_Msk           /*!<Read wait start         */
+#define SDMMC_DCTRL_RWSTOP_Pos               (9U)                              
+#define SDMMC_DCTRL_RWSTOP_Msk               (0x1U << SDMMC_DCTRL_RWSTOP_Pos)  /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP                   SDMMC_DCTRL_RWSTOP_Msk            /*!<Read wait stop          */
+#define SDMMC_DCTRL_RWMOD_Pos                (10U)                              
+#define SDMMC_DCTRL_RWMOD_Msk                (0x1U << SDMMC_DCTRL_RWMOD_Pos)   /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD                    SDMMC_DCTRL_RWMOD_Msk             /*!<Read wait mode          */
+#define SDMMC_DCTRL_SDIOEN_Pos               (11U)                              
+#define SDMMC_DCTRL_SDIOEN_Msk               (0x1U << SDMMC_DCTRL_SDIOEN_Pos)  /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN                   SDMMC_DCTRL_SDIOEN_Msk            /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos           (0U)                              
+#define SDMMC_DCOUNT_DATACOUNT_Msk           (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT               SDMMC_DCOUNT_DATACOUNT_Msk        /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos               (0U)                              
+#define SDMMC_STA_CCRCFAIL_Msk               (0x1U << SDMMC_STA_CCRCFAIL_Pos)  /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL                   SDMMC_STA_CCRCFAIL_Msk            /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos               (1U)                              
+#define SDMMC_STA_DCRCFAIL_Msk               (0x1U << SDMMC_STA_DCRCFAIL_Pos)  /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL                   SDMMC_STA_DCRCFAIL_Msk            /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos               (2U)                              
+#define SDMMC_STA_CTIMEOUT_Msk               (0x1U << SDMMC_STA_CTIMEOUT_Pos)  /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT                   SDMMC_STA_CTIMEOUT_Msk            /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos               (3U)                              
+#define SDMMC_STA_DTIMEOUT_Msk               (0x1U << SDMMC_STA_DTIMEOUT_Pos)  /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT                   SDMMC_STA_DTIMEOUT_Msk            /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos               (4U)                              
+#define SDMMC_STA_TXUNDERR_Msk               (0x1U << SDMMC_STA_TXUNDERR_Pos)  /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR                   SDMMC_STA_TXUNDERR_Msk            /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos                (5U)                              
+#define SDMMC_STA_RXOVERR_Msk                (0x1U << SDMMC_STA_RXOVERR_Pos)   /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR                    SDMMC_STA_RXOVERR_Msk             /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos                (6U)                              
+#define SDMMC_STA_CMDREND_Msk                (0x1U << SDMMC_STA_CMDREND_Pos)   /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND                    SDMMC_STA_CMDREND_Msk             /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos                (7U)                              
+#define SDMMC_STA_CMDSENT_Msk                (0x1U << SDMMC_STA_CMDSENT_Pos)   /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT                    SDMMC_STA_CMDSENT_Msk             /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos                (8U)                              
+#define SDMMC_STA_DATAEND_Msk                (0x1U << SDMMC_STA_DATAEND_Pos)   /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND                    SDMMC_STA_DATAEND_Msk             /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_STBITERR_Pos               (9U)                              
+#define SDMMC_STA_STBITERR_Msk               (0x1U << SDMMC_STA_STBITERR_Pos)  /*!< 0x00000200 */
+#define SDMMC_STA_STBITERR                   SDMMC_STA_STBITERR_Msk            /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDMMC_STA_DBCKEND_Pos                (10U)                             
+#define SDMMC_STA_DBCKEND_Msk                (0x1U << SDMMC_STA_DBCKEND_Pos)   /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND                    SDMMC_STA_DBCKEND_Msk             /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_CMDACT_Pos                 (11U)                             
+#define SDMMC_STA_CMDACT_Msk                 (0x1U << SDMMC_STA_CMDACT_Pos)    /*!< 0x00000800 */
+#define SDMMC_STA_CMDACT                     SDMMC_STA_CMDACT_Msk              /*!<Command transfer in progress                  */
+#define SDMMC_STA_TXACT_Pos                  (12U)                             
+#define SDMMC_STA_TXACT_Msk                  (0x1U << SDMMC_STA_TXACT_Pos)     /*!< 0x00001000 */
+#define SDMMC_STA_TXACT                      SDMMC_STA_TXACT_Msk               /*!<Data transmit in progress                     */
+#define SDMMC_STA_RXACT_Pos                  (13U)                             
+#define SDMMC_STA_RXACT_Msk                  (0x1U << SDMMC_STA_RXACT_Pos)     /*!< 0x00002000 */
+#define SDMMC_STA_RXACT                      SDMMC_STA_RXACT_Msk               /*!<Data receive in progress                      */
+#define SDMMC_STA_TXFIFOHE_Pos               (14U)                             
+#define SDMMC_STA_TXFIFOHE_Msk               (0x1U << SDMMC_STA_TXFIFOHE_Pos)  /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE                   SDMMC_STA_TXFIFOHE_Msk            /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos               (15U)                             
+#define SDMMC_STA_RXFIFOHF_Msk               (0x1U << SDMMC_STA_RXFIFOHF_Pos)  /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF                   SDMMC_STA_RXFIFOHF_Msk            /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos                (16U)                             
+#define SDMMC_STA_TXFIFOF_Msk                (0x1U << SDMMC_STA_TXFIFOF_Pos)   /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF                    SDMMC_STA_TXFIFOF_Msk             /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos                (17U)                             
+#define SDMMC_STA_RXFIFOF_Msk                (0x1U << SDMMC_STA_RXFIFOF_Pos)   /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF                    SDMMC_STA_RXFIFOF_Msk             /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos                (18U)                             
+#define SDMMC_STA_TXFIFOE_Msk                (0x1U << SDMMC_STA_TXFIFOE_Pos)   /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE                    SDMMC_STA_TXFIFOE_Msk             /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos                (19U)                             
+#define SDMMC_STA_RXFIFOE_Msk                (0x1U << SDMMC_STA_RXFIFOE_Pos)   /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE                    SDMMC_STA_RXFIFOE_Msk             /*!<Receive FIFO empty                            */
+#define SDMMC_STA_TXDAVL_Pos                 (20U)                             
+#define SDMMC_STA_TXDAVL_Msk                 (0x1U << SDMMC_STA_TXDAVL_Pos)    /*!< 0x00100000 */
+#define SDMMC_STA_TXDAVL                     SDMMC_STA_TXDAVL_Msk              /*!<Data available in transmit FIFO               */
+#define SDMMC_STA_RXDAVL_Pos                 (21U)                             
+#define SDMMC_STA_RXDAVL_Msk                 (0x1U << SDMMC_STA_RXDAVL_Pos)    /*!< 0x00200000 */
+#define SDMMC_STA_RXDAVL                     SDMMC_STA_RXDAVL_Msk              /*!<Data available in receive FIFO                */
+#define SDMMC_STA_SDIOIT_Pos                 (22U)                             
+#define SDMMC_STA_SDIOIT_Msk                 (0x1U << SDMMC_STA_SDIOIT_Pos)    /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                     SDMMC_STA_SDIOIT_Msk              /*!<SDIO interrupt received                       */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos              (0U)                              
+#define SDMMC_ICR_CCRCFAILC_Msk              (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC                  SDMMC_ICR_CCRCFAILC_Msk           /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos              (1U)                              
+#define SDMMC_ICR_DCRCFAILC_Msk              (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC                  SDMMC_ICR_DCRCFAILC_Msk           /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos              (2U)                              
+#define SDMMC_ICR_CTIMEOUTC_Msk              (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC                  SDMMC_ICR_CTIMEOUTC_Msk           /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos              (3U)                              
+#define SDMMC_ICR_DTIMEOUTC_Msk              (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC                  SDMMC_ICR_DTIMEOUTC_Msk           /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos              (4U)                              
+#define SDMMC_ICR_TXUNDERRC_Msk              (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC                  SDMMC_ICR_TXUNDERRC_Msk           /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos               (5U)                              
+#define SDMMC_ICR_RXOVERRC_Msk               (0x1U << SDMMC_ICR_RXOVERRC_Pos)  /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC                   SDMMC_ICR_RXOVERRC_Msk            /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos               (6U)                              
+#define SDMMC_ICR_CMDRENDC_Msk               (0x1U << SDMMC_ICR_CMDRENDC_Pos)  /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC                   SDMMC_ICR_CMDRENDC_Msk            /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos               (7U)                              
+#define SDMMC_ICR_CMDSENTC_Msk               (0x1U << SDMMC_ICR_CMDSENTC_Pos)  /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC                   SDMMC_ICR_CMDSENTC_Msk            /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos               (8U)                              
+#define SDMMC_ICR_DATAENDC_Msk               (0x1U << SDMMC_ICR_DATAENDC_Pos)  /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC                   SDMMC_ICR_DATAENDC_Msk            /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_STBITERRC_Pos              (9U)                              
+#define SDMMC_ICR_STBITERRC_Msk              (0x1U << SDMMC_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDMMC_ICR_STBITERRC                  SDMMC_ICR_STBITERRC_Msk           /*!<STBITERR flag clear bit */
+#define SDMMC_ICR_DBCKENDC_Pos               (10U)                             
+#define SDMMC_ICR_DBCKENDC_Msk               (0x1U << SDMMC_ICR_DBCKENDC_Pos)  /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC                   SDMMC_ICR_DBCKENDC_Msk            /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos                (22U)                             
+#define SDMMC_ICR_SDIOITC_Msk                (0x1U << SDMMC_ICR_SDIOITC_Pos)   /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC                    SDMMC_ICR_SDIOITC_Msk             /*!<SDIOIT flag clear bit   */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos            (0U)                              
+#define SDMMC_MASK_CCRCFAILIE_Msk            (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE                SDMMC_MASK_CCRCFAILIE_Msk         /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos            (1U)                              
+#define SDMMC_MASK_DCRCFAILIE_Msk            (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE                SDMMC_MASK_DCRCFAILIE_Msk         /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos            (2U)                              
+#define SDMMC_MASK_CTIMEOUTIE_Msk            (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE                SDMMC_MASK_CTIMEOUTIE_Msk         /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos            (3U)                              
+#define SDMMC_MASK_DTIMEOUTIE_Msk            (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE                SDMMC_MASK_DTIMEOUTIE_Msk         /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos            (4U)                              
+#define SDMMC_MASK_TXUNDERRIE_Msk            (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE                SDMMC_MASK_TXUNDERRIE_Msk         /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos             (5U)                              
+#define SDMMC_MASK_RXOVERRIE_Msk             (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE                 SDMMC_MASK_RXOVERRIE_Msk          /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos             (6U)                              
+#define SDMMC_MASK_CMDRENDIE_Msk             (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE                 SDMMC_MASK_CMDRENDIE_Msk          /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos             (7U)                              
+#define SDMMC_MASK_CMDSENTIE_Msk             (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE                 SDMMC_MASK_CMDSENTIE_Msk          /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos             (8U)                              
+#define SDMMC_MASK_DATAENDIE_Msk             (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE                 SDMMC_MASK_DATAENDIE_Msk          /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DBCKENDIE_Pos             (10U)                             
+#define SDMMC_MASK_DBCKENDIE_Msk             (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE                 SDMMC_MASK_DBCKENDIE_Msk          /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_CMDACTIE_Pos              (11U)                             
+#define SDMMC_MASK_CMDACTIE_Msk              (0x1U << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDMMC_MASK_CMDACTIE                  SDMMC_MASK_CMDACTIE_Msk           /*!<CCommand Acting Interrupt Enable           */
+#define SDMMC_MASK_TXACTIE_Pos               (12U)                             
+#define SDMMC_MASK_TXACTIE_Msk               (0x1U << SDMMC_MASK_TXACTIE_Pos)  /*!< 0x00001000 */
+#define SDMMC_MASK_TXACTIE                   SDMMC_MASK_TXACTIE_Msk            /*!<Data Transmit Acting Interrupt Enable      */
+#define SDMMC_MASK_RXACTIE_Pos               (13U)                             
+#define SDMMC_MASK_RXACTIE_Msk               (0x1U << SDMMC_MASK_RXACTIE_Pos)  /*!< 0x00002000 */
+#define SDMMC_MASK_RXACTIE                   SDMMC_MASK_RXACTIE_Msk            /*!<Data receive acting interrupt enabled      */
+#define SDMMC_MASK_TXFIFOHEIE_Pos            (14U)                             
+#define SDMMC_MASK_TXFIFOHEIE_Msk            (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE                SDMMC_MASK_TXFIFOHEIE_Msk         /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos            (15U)                             
+#define SDMMC_MASK_RXFIFOHFIE_Msk            (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE                SDMMC_MASK_RXFIFOHFIE_Msk         /*!<Rx FIFO Half Full interrupt Enable         */
+#define SDMMC_MASK_TXFIFOFIE_Pos             (16U)                             
+#define SDMMC_MASK_TXFIFOFIE_Msk             (0x1U << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDMMC_MASK_TXFIFOFIE                 SDMMC_MASK_TXFIFOFIE_Msk          /*!<Tx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_RXFIFOFIE_Pos             (17U)                             
+#define SDMMC_MASK_RXFIFOFIE_Msk             (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE                 SDMMC_MASK_RXFIFOFIE_Msk          /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos             (18U)                             
+#define SDMMC_MASK_TXFIFOEIE_Msk             (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE                 SDMMC_MASK_TXFIFOEIE_Msk          /*!<Tx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_RXFIFOEIE_Pos             (19U)                             
+#define SDMMC_MASK_RXFIFOEIE_Msk             (0x1U << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDMMC_MASK_RXFIFOEIE                 SDMMC_MASK_RXFIFOEIE_Msk          /*!<Rx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_TXDAVLIE_Pos              (20U)                             
+#define SDMMC_MASK_TXDAVLIE_Msk              (0x1U << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDMMC_MASK_TXDAVLIE                  SDMMC_MASK_TXDAVLIE_Msk           /*!<Data available in Tx FIFO interrupt Enable */
+#define SDMMC_MASK_RXDAVLIE_Pos              (21U)                             
+#define SDMMC_MASK_RXDAVLIE_Msk              (0x1U << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDMMC_MASK_RXDAVLIE                  SDMMC_MASK_RXDAVLIE_Msk           /*!<Data available in Rx FIFO interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos              (22U)                             
+#define SDMMC_MASK_SDIOITIE_Msk              (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE                  SDMMC_MASK_SDIOITIE_Msk           /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
+#define SDMMC_FIFOCNT_FIFOCOUNT_Pos          (0U)                              
+#define SDMMC_FIFOCNT_FIFOCOUNT_Msk          (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDMMC_FIFOCNT_FIFOCOUNT              SDMMC_FIFOCNT_FIFOCOUNT_Msk       /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos              (0U)                              
+#define SDMMC_FIFO_FIFODATA_Msk              (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA                  SDMMC_FIFO_FIFODATA_Msk           /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos                    (0U)                               
+#define SPI_CR1_CPHA_Msk                    (0x1U << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
+#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!<Clock Phase      */
+#define SPI_CR1_CPOL_Pos                    (1U)                               
+#define SPI_CR1_CPOL_Msk                    (0x1U << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
+#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!<Clock Polarity   */
+#define SPI_CR1_MSTR_Pos                    (2U)                               
+#define SPI_CR1_MSTR_Msk                    (0x1U << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
+#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos                      (3U)                               
+#define SPI_CR1_BR_Msk                      (0x7U << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
+#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0                        (0x1U << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
+#define SPI_CR1_BR_1                        (0x2U << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
+#define SPI_CR1_BR_2                        (0x4U << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos                     (6U)                               
+#define SPI_CR1_SPE_Msk                     (0x1U << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
+#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!<SPI Enable                          */
+#define SPI_CR1_LSBFIRST_Pos                (7U)                               
+#define SPI_CR1_LSBFIRST_Msk                (0x1U << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!<Frame Format                        */
+#define SPI_CR1_SSI_Pos                     (8U)                               
+#define SPI_CR1_SSI_Msk                     (0x1U << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
+#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!<Internal slave select               */
+#define SPI_CR1_SSM_Pos                     (9U)                               
+#define SPI_CR1_SSM_Msk                     (0x1U << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
+#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!<Software slave management           */
+#define SPI_CR1_RXONLY_Pos                  (10U)                              
+#define SPI_CR1_RXONLY_Msk                  (0x1U << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
+#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!<Receive only                        */
+#define SPI_CR1_CRCL_Pos                    (11U)                              
+#define SPI_CR1_CRCL_Msk                    (0x1U << SPI_CR1_CRCL_Pos)         /*!< 0x00000800 */
+#define SPI_CR1_CRCL                        SPI_CR1_CRCL_Msk                   /*!< CRC Length */
+#define SPI_CR1_CRCNEXT_Pos                 (12U)                              
+#define SPI_CR1_CRCNEXT_Msk                 (0x1U << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!<Transmit CRC next                   */
+#define SPI_CR1_CRCEN_Pos                   (13U)                              
+#define SPI_CR1_CRCEN_Msk                   (0x1U << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
+#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!<Hardware CRC calculation enable     */
+#define SPI_CR1_BIDIOE_Pos                  (14U)                              
+#define SPI_CR1_BIDIOE_Msk                  (0x1U << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos                (15U)                              
+#define SPI_CR1_BIDIMODE_Msk                (0x1U << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos                 (0U)                               
+#define SPI_CR2_RXDMAEN_Msk                 (0x1U << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos                 (1U)                               
+#define SPI_CR2_TXDMAEN_Msk                 (0x1U << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos                    (2U)                               
+#define SPI_CR2_SSOE_Msk                    (0x1U << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
+#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
+#define SPI_CR2_NSSP_Pos                    (3U)                               
+#define SPI_CR2_NSSP_Msk                    (0x1U << SPI_CR2_NSSP_Pos)         /*!< 0x00000008 */
+#define SPI_CR2_NSSP                        SPI_CR2_NSSP_Msk                   /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF_Pos                     (4U)                               
+#define SPI_CR2_FRF_Msk                     (0x1U << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
+#define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos                   (5U)                               
+#define SPI_CR2_ERRIE_Msk                   (0x1U << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
+#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos                  (6U)                               
+#define SPI_CR2_RXNEIE_Msk                  (0x1U << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos                   (7U)                               
+#define SPI_CR2_TXEIE_Msk                   (0x1U << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
+#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS_Pos                      (8U)                               
+#define SPI_CR2_DS_Msk                      (0xFU << SPI_CR2_DS_Pos)           /*!< 0x00000F00 */
+#define SPI_CR2_DS                          SPI_CR2_DS_Msk                     /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0                        (0x1U << SPI_CR2_DS_Pos)           /*!< 0x00000100 */
+#define SPI_CR2_DS_1                        (0x2U << SPI_CR2_DS_Pos)           /*!< 0x00000200 */
+#define SPI_CR2_DS_2                        (0x4U << SPI_CR2_DS_Pos)           /*!< 0x00000400 */
+#define SPI_CR2_DS_3                        (0x8U << SPI_CR2_DS_Pos)           /*!< 0x00000800 */
+#define SPI_CR2_FRXTH_Pos                   (12U)                              
+#define SPI_CR2_FRXTH_Msk                   (0x1U << SPI_CR2_FRXTH_Pos)        /*!< 0x00001000 */
+#define SPI_CR2_FRXTH                       SPI_CR2_FRXTH_Msk                  /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX_Pos                  (13U)                              
+#define SPI_CR2_LDMARX_Msk                  (0x1U << SPI_CR2_LDMARX_Pos)       /*!< 0x00002000 */
+#define SPI_CR2_LDMARX                      SPI_CR2_LDMARX_Msk                 /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX_Pos                  (14U)                              
+#define SPI_CR2_LDMATX_Msk                  (0x1U << SPI_CR2_LDMATX_Pos)       /*!< 0x00004000 */
+#define SPI_CR2_LDMATX                      SPI_CR2_LDMATX_Msk                 /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos                     (0U)                               
+#define SPI_SR_RXNE_Msk                     (0x1U << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
+#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos                      (1U)                               
+#define SPI_SR_TXE_Msk                      (0x1U << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
+#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos                   (2U)                               
+#define SPI_SR_CHSIDE_Msk                   (0x1U << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
+#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
+#define SPI_SR_UDR_Pos                      (3U)                               
+#define SPI_SR_UDR_Msk                      (0x1U << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
+#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos                   (4U)                               
+#define SPI_SR_CRCERR_Msk                   (0x1U << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
+#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos                     (5U)                               
+#define SPI_SR_MODF_Msk                     (0x1U << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
+#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
+#define SPI_SR_OVR_Pos                      (6U)                               
+#define SPI_SR_OVR_Msk                      (0x1U << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
+#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
+#define SPI_SR_BSY_Pos                      (7U)                               
+#define SPI_SR_BSY_Msk                      (0x1U << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
+#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
+#define SPI_SR_FRE_Pos                      (8U)                               
+#define SPI_SR_FRE_Msk                      (0x1U << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
+#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!< TI frame format error */
+#define SPI_SR_FRLVL_Pos                    (9U)                               
+#define SPI_SR_FRLVL_Msk                    (0x3U << SPI_SR_FRLVL_Pos)         /*!< 0x00000600 */
+#define SPI_SR_FRLVL                        SPI_SR_FRLVL_Msk                   /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0                      (0x1U << SPI_SR_FRLVL_Pos)         /*!< 0x00000200 */
+#define SPI_SR_FRLVL_1                      (0x2U << SPI_SR_FRLVL_Pos)         /*!< 0x00000400 */
+#define SPI_SR_FTLVL_Pos                    (11U)                              
+#define SPI_SR_FTLVL_Msk                    (0x3U << SPI_SR_FTLVL_Pos)         /*!< 0x00001800 */
+#define SPI_SR_FTLVL                        SPI_SR_FTLVL_Msk                   /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0                      (0x1U << SPI_SR_FTLVL_Pos)         /*!< 0x00000800 */
+#define SPI_SR_FTLVL_1                      (0x2U << SPI_SR_FTLVL_Pos)         /*!< 0x00001000 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos                       (0U)                               
+#define SPI_DR_DR_Msk                       (0xFFFFU << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
+#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               
+#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos                (0U)                               
+#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos                (0U)                               
+#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!<Tx CRC Register         */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos                        (0U)                          
+#define QUADSPI_CR_EN_Msk                        (0x1U << QUADSPI_CR_EN_Pos)   /*!< 0x00000001 */
+#define QUADSPI_CR_EN                            QUADSPI_CR_EN_Msk             /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos                     (1U)                          
+#define QUADSPI_CR_ABORT_Msk                     (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT                         QUADSPI_CR_ABORT_Msk          /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos                     (2U)                          
+#define QUADSPI_CR_DMAEN_Msk                     (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN                         QUADSPI_CR_DMAEN_Msk          /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos                      (3U)                          
+#define QUADSPI_CR_TCEN_Msk                      (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                          QUADSPI_CR_TCEN_Msk           /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos                    (4U)                          
+#define QUADSPI_CR_SSHIFT_Msk                    (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT                        QUADSPI_CR_SSHIFT_Msk         /*!< Sample Shift */
+#define QUADSPI_CR_FTHRES_Pos                    (8U)                          
+#define QUADSPI_CR_FTHRES_Msk                    (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
+#define QUADSPI_CR_FTHRES                        QUADSPI_CR_FTHRES_Msk         /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_TEIE_Pos                      (16U)                         
+#define QUADSPI_CR_TEIE_Msk                      (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                          QUADSPI_CR_TEIE_Msk           /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos                      (17U)                         
+#define QUADSPI_CR_TCIE_Msk                      (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                          QUADSPI_CR_TCIE_Msk           /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos                      (18U)                         
+#define QUADSPI_CR_FTIE_Msk                      (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                          QUADSPI_CR_FTIE_Msk           /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos                      (19U)                         
+#define QUADSPI_CR_SMIE_Msk                      (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                          QUADSPI_CR_SMIE_Msk           /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos                      (20U)                         
+#define QUADSPI_CR_TOIE_Msk                      (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                          QUADSPI_CR_TOIE_Msk           /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos                      (22U)                         
+#define QUADSPI_CR_APMS_Msk                      (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                          QUADSPI_CR_APMS_Msk           /*!< Automatic Polling Mode Stop */
+#define QUADSPI_CR_PMM_Pos                       (23U)                         
+#define QUADSPI_CR_PMM_Msk                       (0x1U << QUADSPI_CR_PMM_Pos)  /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                           QUADSPI_CR_PMM_Msk            /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos                 (24U)                         
+#define QUADSPI_CR_PRESCALER_Msk                 (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER                     QUADSPI_CR_PRESCALER_Msk      /*!< PRESCALER[7:0] Clock prescaler */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos                   (0U)                          
+#define QUADSPI_DCR_CKMODE_Msk                   (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE                       QUADSPI_DCR_CKMODE_Msk        /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos                     (8U)                          
+#define QUADSPI_DCR_CSHT_Msk                     (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT                         QUADSPI_DCR_CSHT_Msk          /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0                       (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1                       (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2                       (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos                    (16U)                         
+#define QUADSPI_DCR_FSIZE_Msk                    (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE                        QUADSPI_DCR_FSIZE_Msk         /*!< FSIZE[4:0]: Flash Size */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos                       (0U)                          
+#define QUADSPI_SR_TEF_Msk                       (0x1U << QUADSPI_SR_TEF_Pos)  /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                           QUADSPI_SR_TEF_Msk            /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos                       (1U)                          
+#define QUADSPI_SR_TCF_Msk                       (0x1U << QUADSPI_SR_TCF_Pos)  /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                           QUADSPI_SR_TCF_Msk            /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos                       (2U)                          
+#define QUADSPI_SR_FTF_Msk                       (0x1U << QUADSPI_SR_FTF_Pos)  /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                           QUADSPI_SR_FTF_Msk            /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos                       (3U)                          
+#define QUADSPI_SR_SMF_Msk                       (0x1U << QUADSPI_SR_SMF_Pos)  /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                           QUADSPI_SR_SMF_Msk            /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos                       (4U)                          
+#define QUADSPI_SR_TOF_Msk                       (0x1U << QUADSPI_SR_TOF_Pos)  /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                           QUADSPI_SR_TOF_Msk            /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos                      (5U)                          
+#define QUADSPI_SR_BUSY_Msk                      (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                          QUADSPI_SR_BUSY_Msk           /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos                    (8U)                          
+#define QUADSPI_SR_FLEVEL_Msk                    (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
+#define QUADSPI_SR_FLEVEL                        QUADSPI_SR_FLEVEL_Msk         /*!< FIFO Threshlod Flag */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos                     (0U)                          
+#define QUADSPI_FCR_CTEF_Msk                     (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF                         QUADSPI_FCR_CTEF_Msk          /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos                     (1U)                          
+#define QUADSPI_FCR_CTCF_Msk                     (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF                         QUADSPI_FCR_CTCF_Msk          /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos                     (3U)                          
+#define QUADSPI_FCR_CSMF_Msk                     (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF                         QUADSPI_FCR_CSMF_Msk          /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos                     (4U)                          
+#define QUADSPI_FCR_CTOF_Msk                     (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF                         QUADSPI_FCR_CTOF_Msk          /*!< Clear Timeout Flag */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos                       (0U)                          
+#define QUADSPI_DLR_DL_Msk                       (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                           QUADSPI_DLR_DL_Msk            /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos              (0U)                          
+#define QUADSPI_CCR_INSTRUCTION_Msk              (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION                  QUADSPI_CCR_INSTRUCTION_Msk   /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_IMODE_Pos                    (8U)                          
+#define QUADSPI_CCR_IMODE_Msk                    (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE                        QUADSPI_CCR_IMODE_Msk         /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0                      (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1                      (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos                   (10U)                         
+#define QUADSPI_CCR_ADMODE_Msk                   (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE                       QUADSPI_CCR_ADMODE_Msk        /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0                     (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1                     (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos                   (12U)                         
+#define QUADSPI_CCR_ADSIZE_Msk                   (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE                       QUADSPI_CCR_ADSIZE_Msk        /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0                     (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1                     (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos                   (14U)                         
+#define QUADSPI_CCR_ABMODE_Msk                   (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE                       QUADSPI_CCR_ABMODE_Msk        /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0                     (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1                     (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos                   (16U)                         
+#define QUADSPI_CCR_ABSIZE_Msk                   (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE                       QUADSPI_CCR_ABSIZE_Msk        /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0                     (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1                     (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos                     (18U)                         
+#define QUADSPI_CCR_DCYC_Msk                     (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC                         QUADSPI_CCR_DCYC_Msk          /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DMODE_Pos                    (24U)                         
+#define QUADSPI_CCR_DMODE_Msk                    (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE                        QUADSPI_CCR_DMODE_Msk         /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0                      (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1                      (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos                    (26U)                         
+#define QUADSPI_CCR_FMODE_Msk                    (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE                        QUADSPI_CCR_FMODE_Msk         /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0                      (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1                      (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos                     (28U)                         
+#define QUADSPI_CCR_SIOO_Msk                     (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO                         QUADSPI_CCR_SIOO_Msk          /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DDRM_Pos                     (31U)                         
+#define QUADSPI_CCR_DDRM_Msk                     (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM                         QUADSPI_CCR_DDRM_Msk          /*!< DDRM: Double Data Rate Mode */
+
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos                   (0U)                          
+#define QUADSPI_AR_ADDRESS_Msk                   (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS                       QUADSPI_AR_ADDRESS_Msk        /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos                (0U)                          
+#define QUADSPI_ABR_ALTERNATE_Msk                (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE                    QUADSPI_ABR_ALTERNATE_Msk     /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos                      (0U)                          
+#define QUADSPI_DR_DATA_Msk                      (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                          QUADSPI_DR_DATA_Msk           /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos                   (0U)                          
+#define QUADSPI_PSMKR_MASK_Msk                   (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK                       QUADSPI_PSMKR_MASK_Msk        /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos                  (0U)                          
+#define QUADSPI_PSMAR_MATCH_Msk                  (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH                      QUADSPI_PSMAR_MATCH_Msk       /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos                 (0U)                          
+#define QUADSPI_PIR_INTERVAL_Msk                 (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL                     QUADSPI_PIR_INTERVAL_Msk      /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos                 (0U)                          
+#define QUADSPI_LPTR_TIMEOUT_Msk                 (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT                     QUADSPI_LPTR_TIMEOUT_Msk      /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos          (0U)                               
+#define SYSCFG_MEMRMP_MEM_MODE_Msk          (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE              SYSCFG_MEMRMP_MEM_MODE_Msk         /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0            (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1            (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2            (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
+
+#define SYSCFG_MEMRMP_FB_MODE_Pos           (8U)                               
+#define SYSCFG_MEMRMP_FB_MODE_Msk           (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_FB_MODE               SYSCFG_MEMRMP_FB_MODE_Msk          /*!< Flash Bank mode selection */
+
+/******************  Bit definition for SYSCFG_CFGR1 register  ******************/
+#define SYSCFG_CFGR1_FWDIS_Pos              (0U)                               
+#define SYSCFG_CFGR1_FWDIS_Msk              (0x1U << SYSCFG_CFGR1_FWDIS_Pos)   /*!< 0x00000001 */
+#define SYSCFG_CFGR1_FWDIS                  SYSCFG_CFGR1_FWDIS_Msk             /*!< FIREWALL access enable*/
+#define SYSCFG_CFGR1_BOOSTEN_Pos            (8U)                               
+#define SYSCFG_CFGR1_BOOSTEN_Msk            (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOSTEN                SYSCFG_CFGR1_BOOSTEN_Msk           /*!< I/O analog switch voltage booster enable */
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos        (16U)                              
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk        (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
+#define SYSCFG_CFGR1_I2C_PB6_FMP            SYSCFG_CFGR1_I2C_PB6_FMP_Msk       /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos        (17U)                              
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk        (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
+#define SYSCFG_CFGR1_I2C_PB7_FMP            SYSCFG_CFGR1_I2C_PB7_FMP_Msk       /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos        (18U)                              
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk        (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
+#define SYSCFG_CFGR1_I2C_PB8_FMP            SYSCFG_CFGR1_I2C_PB8_FMP_Msk       /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos        (19U)                              
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk        (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
+#define SYSCFG_CFGR1_I2C_PB9_FMP            SYSCFG_CFGR1_I2C_PB9_FMP_Msk       /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP_Pos           (20U)                              
+#define SYSCFG_CFGR1_I2C1_FMP_Msk           (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
+#define SYSCFG_CFGR1_I2C1_FMP               SYSCFG_CFGR1_I2C1_FMP_Msk          /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP_Pos           (21U)                              
+#define SYSCFG_CFGR1_I2C2_FMP_Msk           (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
+#define SYSCFG_CFGR1_I2C2_FMP               SYSCFG_CFGR1_I2C2_FMP_Msk          /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_I2C3_FMP_Pos           (22U)                              
+#define SYSCFG_CFGR1_I2C3_FMP_Msk           (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
+#define SYSCFG_CFGR1_I2C3_FMP               SYSCFG_CFGR1_I2C3_FMP_Msk          /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE_0               (0x04000000U)                      /*!<  Invalid operation Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_1               (0x08000000U)                      /*!<  Divide-by-zero Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_2               (0x10000000U)                      /*!<  Underflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_3               (0x20000000U)                      /*!<  Overflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_4               (0x40000000U)                      /*!<  Input denormal Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_5               (0x80000000U)                      /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos            (0U)                               
+#define SYSCFG_EXTICR1_EXTI0_Msk            (0x7U << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
+#define SYSCFG_EXTICR1_EXTI0                SYSCFG_EXTICR1_EXTI0_Msk           /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos            (4U)                               
+#define SYSCFG_EXTICR1_EXTI1_Msk            (0x7U << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */
+#define SYSCFG_EXTICR1_EXTI1                SYSCFG_EXTICR1_EXTI1_Msk           /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos            (8U)                               
+#define SYSCFG_EXTICR1_EXTI2_Msk            (0x7U << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */
+#define SYSCFG_EXTICR1_EXTI2                SYSCFG_EXTICR1_EXTI2_Msk           /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos            (12U)                              
+#define SYSCFG_EXTICR1_EXTI3_Msk            (0x7U << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */
+#define SYSCFG_EXTICR1_EXTI3                SYSCFG_EXTICR1_EXTI3_Msk           /*!<EXTI 3 configuration */
+
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005U)                      /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006U)                      /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007U)                      /*!<PH[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050U)                      /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060U)                      /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070U)                      /*!<PH[1] pin */
+
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500U)                      /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600U)                      /*!<PG[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000U)                      /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos            (0U)                               
+#define SYSCFG_EXTICR2_EXTI4_Msk            (0x7U << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
+#define SYSCFG_EXTICR2_EXTI4                SYSCFG_EXTICR2_EXTI4_Msk           /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos            (4U)                               
+#define SYSCFG_EXTICR2_EXTI5_Msk            (0x7U << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */
+#define SYSCFG_EXTICR2_EXTI5                SYSCFG_EXTICR2_EXTI5_Msk           /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos            (8U)                               
+#define SYSCFG_EXTICR2_EXTI6_Msk            (0x7U << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */
+#define SYSCFG_EXTICR2_EXTI6                SYSCFG_EXTICR2_EXTI6_Msk           /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos            (12U)                              
+#define SYSCFG_EXTICR2_EXTI7_Msk            (0x7U << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */
+#define SYSCFG_EXTICR2_EXTI7                SYSCFG_EXTICR2_EXTI7_Msk           /*!<EXTI 7 configuration */
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005U)                      /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006U)                      /*!<PG[4] pin */
+
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050U)                      /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060U)                      /*!<PG[5] pin */
+
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500U)                      /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600U)                      /*!<PG[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000U)                      /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000U)                      /*!<PG[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos            (0U)                               
+#define SYSCFG_EXTICR3_EXTI8_Msk            (0x7U << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
+#define SYSCFG_EXTICR3_EXTI8                SYSCFG_EXTICR3_EXTI8_Msk           /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos            (4U)                               
+#define SYSCFG_EXTICR3_EXTI9_Msk            (0x7U << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */
+#define SYSCFG_EXTICR3_EXTI9                SYSCFG_EXTICR3_EXTI9_Msk           /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos           (8U)                               
+#define SYSCFG_EXTICR3_EXTI10_Msk           (0x7U << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */
+#define SYSCFG_EXTICR3_EXTI10               SYSCFG_EXTICR3_EXTI10_Msk          /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos           (12U)                              
+#define SYSCFG_EXTICR3_EXTI11_Msk           (0x7U << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x00007000 */
+#define SYSCFG_EXTICR3_EXTI11               SYSCFG_EXTICR3_EXTI11_Msk          /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005U)                      /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006U)                      /*!<PG[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050U)                      /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060U)                      /*!<PG[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500U)                      /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG            (0x00000600U)                      /*!<PG[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000U)                      /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG            (0x00006000U)                      /*!<PG[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos           (0U)                               
+#define SYSCFG_EXTICR4_EXTI12_Msk           (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
+#define SYSCFG_EXTICR4_EXTI12               SYSCFG_EXTICR4_EXTI12_Msk          /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos           (4U)                               
+#define SYSCFG_EXTICR4_EXTI13_Msk           (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
+#define SYSCFG_EXTICR4_EXTI13               SYSCFG_EXTICR4_EXTI13_Msk          /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos           (8U)                               
+#define SYSCFG_EXTICR4_EXTI14_Msk           (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
+#define SYSCFG_EXTICR4_EXTI14               SYSCFG_EXTICR4_EXTI14_Msk          /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos           (12U)                              
+#define SYSCFG_EXTICR4_EXTI15_Msk           (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
+#define SYSCFG_EXTICR4_EXTI15               SYSCFG_EXTICR4_EXTI15_Msk          /*!<EXTI 15 configuration */
+
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005U)                      /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG            (0x00000006U)                      /*!<PG[12] pin */
+
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050U)                      /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG            (0x00000060U)                      /*!<PG[13] pin */
+
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500U)                      /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG            (0x00000600U)                      /*!<PG[14] pin */
+
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000U)                      /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG            (0x00006000U)                      /*!<PG[15] pin */
+
+/******************  Bit definition for SYSCFG_SCSR register  ****************/
+#define SYSCFG_SCSR_SRAM2ER_Pos             (0U)                               
+#define SYSCFG_SCSR_SRAM2ER_Msk             (0x1U << SYSCFG_SCSR_SRAM2ER_Pos)  /*!< 0x00000001 */
+#define SYSCFG_SCSR_SRAM2ER                 SYSCFG_SCSR_SRAM2ER_Msk            /*!< SRAM2 Erase Request */
+#define SYSCFG_SCSR_SRAM2BSY_Pos            (1U)                               
+#define SYSCFG_SCSR_SRAM2BSY_Msk            (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
+#define SYSCFG_SCSR_SRAM2BSY                SYSCFG_SCSR_SRAM2BSY_Msk           /*!< SRAM2 Erase Ongoing */
+
+/******************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_CLL_Pos                (0U)                               
+#define SYSCFG_CFGR2_CLL_Msk                (0x1U << SYSCFG_CFGR2_CLL_Pos)     /*!< 0x00000001 */
+#define SYSCFG_CFGR2_CLL                    SYSCFG_CFGR2_CLL_Msk               /*!< Core Lockup Lock */
+#define SYSCFG_CFGR2_SPL_Pos                (1U)                               
+#define SYSCFG_CFGR2_SPL_Msk                (0x1U << SYSCFG_CFGR2_SPL_Pos)     /*!< 0x00000002 */
+#define SYSCFG_CFGR2_SPL                    SYSCFG_CFGR2_SPL_Msk               /*!< SRAM Parity Lock*/
+#define SYSCFG_CFGR2_PVDL_Pos               (2U)                               
+#define SYSCFG_CFGR2_PVDL_Msk               (0x1U << SYSCFG_CFGR2_PVDL_Pos)    /*!< 0x00000004 */
+#define SYSCFG_CFGR2_PVDL                   SYSCFG_CFGR2_PVDL_Msk              /*!<  PVD Lock */
+#define SYSCFG_CFGR2_ECCL_Pos               (3U)                               
+#define SYSCFG_CFGR2_ECCL_Msk               (0x1U << SYSCFG_CFGR2_ECCL_Pos)    /*!< 0x00000008 */
+#define SYSCFG_CFGR2_ECCL                   SYSCFG_CFGR2_ECCL_Msk              /*!< ECC Lock*/
+#define SYSCFG_CFGR2_SPF_Pos                (8U)                               
+#define SYSCFG_CFGR2_SPF_Msk                (0x1U << SYSCFG_CFGR2_SPF_Pos)     /*!< 0x00000100 */
+#define SYSCFG_CFGR2_SPF                    SYSCFG_CFGR2_SPF_Msk               /*!< SRAM Parity Flag */
+
+/******************  Bit definition for SYSCFG_SWPR register  ****************/
+#define SYSCFG_SWPR_PAGE0_Pos               (0U)                               
+#define SYSCFG_SWPR_PAGE0_Msk               (0x1U << SYSCFG_SWPR_PAGE0_Pos)    /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0                   SYSCFG_SWPR_PAGE0_Msk              /*!< SRAM2 Write protection page 0 */
+#define SYSCFG_SWPR_PAGE1_Pos               (1U)                               
+#define SYSCFG_SWPR_PAGE1_Msk               (0x1U << SYSCFG_SWPR_PAGE1_Pos)    /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1                   SYSCFG_SWPR_PAGE1_Msk              /*!< SRAM2 Write protection page 1 */
+#define SYSCFG_SWPR_PAGE2_Pos               (2U)                               
+#define SYSCFG_SWPR_PAGE2_Msk               (0x1U << SYSCFG_SWPR_PAGE2_Pos)    /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2                   SYSCFG_SWPR_PAGE2_Msk              /*!< SRAM2 Write protection page 2 */
+#define SYSCFG_SWPR_PAGE3_Pos               (3U)                               
+#define SYSCFG_SWPR_PAGE3_Msk               (0x1U << SYSCFG_SWPR_PAGE3_Pos)    /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3                   SYSCFG_SWPR_PAGE3_Msk              /*!< SRAM2 Write protection page 3 */
+#define SYSCFG_SWPR_PAGE4_Pos               (4U)                               
+#define SYSCFG_SWPR_PAGE4_Msk               (0x1U << SYSCFG_SWPR_PAGE4_Pos)    /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4                   SYSCFG_SWPR_PAGE4_Msk              /*!< SRAM2 Write protection page 4 */
+#define SYSCFG_SWPR_PAGE5_Pos               (5U)                               
+#define SYSCFG_SWPR_PAGE5_Msk               (0x1U << SYSCFG_SWPR_PAGE5_Pos)    /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5                   SYSCFG_SWPR_PAGE5_Msk              /*!< SRAM2 Write protection page 5 */
+#define SYSCFG_SWPR_PAGE6_Pos               (6U)                               
+#define SYSCFG_SWPR_PAGE6_Msk               (0x1U << SYSCFG_SWPR_PAGE6_Pos)    /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6                   SYSCFG_SWPR_PAGE6_Msk              /*!< SRAM2 Write protection page 6 */
+#define SYSCFG_SWPR_PAGE7_Pos               (7U)                               
+#define SYSCFG_SWPR_PAGE7_Msk               (0x1U << SYSCFG_SWPR_PAGE7_Pos)    /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7                   SYSCFG_SWPR_PAGE7_Msk              /*!< SRAM2 Write protection page 7 */
+#define SYSCFG_SWPR_PAGE8_Pos               (8U)                               
+#define SYSCFG_SWPR_PAGE8_Msk               (0x1U << SYSCFG_SWPR_PAGE8_Pos)    /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8                   SYSCFG_SWPR_PAGE8_Msk              /*!< SRAM2 Write protection page 8 */
+#define SYSCFG_SWPR_PAGE9_Pos               (9U)                               
+#define SYSCFG_SWPR_PAGE9_Msk               (0x1U << SYSCFG_SWPR_PAGE9_Pos)    /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9                   SYSCFG_SWPR_PAGE9_Msk              /*!< SRAM2 Write protection page 9 */
+#define SYSCFG_SWPR_PAGE10_Pos              (10U)                              
+#define SYSCFG_SWPR_PAGE10_Msk              (0x1U << SYSCFG_SWPR_PAGE10_Pos)   /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10                  SYSCFG_SWPR_PAGE10_Msk             /*!< SRAM2 Write protection page 10*/
+#define SYSCFG_SWPR_PAGE11_Pos              (11U)                              
+#define SYSCFG_SWPR_PAGE11_Msk              (0x1U << SYSCFG_SWPR_PAGE11_Pos)   /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11                  SYSCFG_SWPR_PAGE11_Msk             /*!< SRAM2 Write protection page 11*/
+#define SYSCFG_SWPR_PAGE12_Pos              (12U)                              
+#define SYSCFG_SWPR_PAGE12_Msk              (0x1U << SYSCFG_SWPR_PAGE12_Pos)   /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12                  SYSCFG_SWPR_PAGE12_Msk             /*!< SRAM2 Write protection page 12*/
+#define SYSCFG_SWPR_PAGE13_Pos              (13U)                              
+#define SYSCFG_SWPR_PAGE13_Msk              (0x1U << SYSCFG_SWPR_PAGE13_Pos)   /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13                  SYSCFG_SWPR_PAGE13_Msk             /*!< SRAM2 Write protection page 13*/
+#define SYSCFG_SWPR_PAGE14_Pos              (14U)                              
+#define SYSCFG_SWPR_PAGE14_Msk              (0x1U << SYSCFG_SWPR_PAGE14_Pos)   /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14                  SYSCFG_SWPR_PAGE14_Msk             /*!< SRAM2 Write protection page 14*/
+#define SYSCFG_SWPR_PAGE15_Pos              (15U)                              
+#define SYSCFG_SWPR_PAGE15_Msk              (0x1U << SYSCFG_SWPR_PAGE15_Pos)   /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15                  SYSCFG_SWPR_PAGE15_Msk             /*!< SRAM2 Write protection page 15*/
+#define SYSCFG_SWPR_PAGE16_Pos              (16U)                              
+#define SYSCFG_SWPR_PAGE16_Msk              (0x1U << SYSCFG_SWPR_PAGE16_Pos)   /*!< 0x00010000 */
+#define SYSCFG_SWPR_PAGE16                  SYSCFG_SWPR_PAGE16_Msk             /*!< SRAM2 Write protection page 16*/
+#define SYSCFG_SWPR_PAGE17_Pos              (17U)                              
+#define SYSCFG_SWPR_PAGE17_Msk              (0x1U << SYSCFG_SWPR_PAGE17_Pos)   /*!< 0x00020000 */
+#define SYSCFG_SWPR_PAGE17                  SYSCFG_SWPR_PAGE17_Msk             /*!< SRAM2 Write protection page 17*/
+#define SYSCFG_SWPR_PAGE18_Pos              (18U)                              
+#define SYSCFG_SWPR_PAGE18_Msk              (0x1U << SYSCFG_SWPR_PAGE18_Pos)   /*!< 0x00040000 */
+#define SYSCFG_SWPR_PAGE18                  SYSCFG_SWPR_PAGE18_Msk             /*!< SRAM2 Write protection page 18*/
+#define SYSCFG_SWPR_PAGE19_Pos              (19U)                              
+#define SYSCFG_SWPR_PAGE19_Msk              (0x1U << SYSCFG_SWPR_PAGE19_Pos)   /*!< 0x00080000 */
+#define SYSCFG_SWPR_PAGE19                  SYSCFG_SWPR_PAGE19_Msk             /*!< SRAM2 Write protection page 19*/
+#define SYSCFG_SWPR_PAGE20_Pos              (20U)                              
+#define SYSCFG_SWPR_PAGE20_Msk              (0x1U << SYSCFG_SWPR_PAGE20_Pos)   /*!< 0x00100000 */
+#define SYSCFG_SWPR_PAGE20                  SYSCFG_SWPR_PAGE20_Msk             /*!< SRAM2 Write protection page 20*/
+#define SYSCFG_SWPR_PAGE21_Pos              (21U)                              
+#define SYSCFG_SWPR_PAGE21_Msk              (0x1U << SYSCFG_SWPR_PAGE21_Pos)   /*!< 0x00200000 */
+#define SYSCFG_SWPR_PAGE21                  SYSCFG_SWPR_PAGE21_Msk             /*!< SRAM2 Write protection page 21*/
+#define SYSCFG_SWPR_PAGE22_Pos              (22U)                              
+#define SYSCFG_SWPR_PAGE22_Msk              (0x1U << SYSCFG_SWPR_PAGE22_Pos)   /*!< 0x00400000 */
+#define SYSCFG_SWPR_PAGE22                  SYSCFG_SWPR_PAGE22_Msk             /*!< SRAM2 Write protection page 22*/
+#define SYSCFG_SWPR_PAGE23_Pos              (23U)                              
+#define SYSCFG_SWPR_PAGE23_Msk              (0x1U << SYSCFG_SWPR_PAGE23_Pos)   /*!< 0x00800000 */
+#define SYSCFG_SWPR_PAGE23                  SYSCFG_SWPR_PAGE23_Msk             /*!< SRAM2 Write protection page 23*/
+#define SYSCFG_SWPR_PAGE24_Pos              (24U)                              
+#define SYSCFG_SWPR_PAGE24_Msk              (0x1U << SYSCFG_SWPR_PAGE24_Pos)   /*!< 0x01000000 */
+#define SYSCFG_SWPR_PAGE24                  SYSCFG_SWPR_PAGE24_Msk             /*!< SRAM2 Write protection page 24*/
+#define SYSCFG_SWPR_PAGE25_Pos              (25U)                              
+#define SYSCFG_SWPR_PAGE25_Msk              (0x1U << SYSCFG_SWPR_PAGE25_Pos)   /*!< 0x02000000 */
+#define SYSCFG_SWPR_PAGE25                  SYSCFG_SWPR_PAGE25_Msk             /*!< SRAM2 Write protection page 25*/
+#define SYSCFG_SWPR_PAGE26_Pos              (26U)                              
+#define SYSCFG_SWPR_PAGE26_Msk              (0x1U << SYSCFG_SWPR_PAGE26_Pos)   /*!< 0x04000000 */
+#define SYSCFG_SWPR_PAGE26                  SYSCFG_SWPR_PAGE26_Msk             /*!< SRAM2 Write protection page 26*/
+#define SYSCFG_SWPR_PAGE27_Pos              (27U)                              
+#define SYSCFG_SWPR_PAGE27_Msk              (0x1U << SYSCFG_SWPR_PAGE27_Pos)   /*!< 0x08000000 */
+#define SYSCFG_SWPR_PAGE27                  SYSCFG_SWPR_PAGE27_Msk             /*!< SRAM2 Write protection page 27*/
+#define SYSCFG_SWPR_PAGE28_Pos              (28U)                              
+#define SYSCFG_SWPR_PAGE28_Msk              (0x1U << SYSCFG_SWPR_PAGE28_Pos)   /*!< 0x10000000 */
+#define SYSCFG_SWPR_PAGE28                  SYSCFG_SWPR_PAGE28_Msk             /*!< SRAM2 Write protection page 28*/
+#define SYSCFG_SWPR_PAGE29_Pos              (29U)                              
+#define SYSCFG_SWPR_PAGE29_Msk              (0x1U << SYSCFG_SWPR_PAGE29_Pos)   /*!< 0x20000000 */
+#define SYSCFG_SWPR_PAGE29                  SYSCFG_SWPR_PAGE29_Msk             /*!< SRAM2 Write protection page 29*/
+#define SYSCFG_SWPR_PAGE30_Pos              (30U)                              
+#define SYSCFG_SWPR_PAGE30_Msk              (0x1U << SYSCFG_SWPR_PAGE30_Pos)   /*!< 0x40000000 */
+#define SYSCFG_SWPR_PAGE30                  SYSCFG_SWPR_PAGE30_Msk             /*!< SRAM2 Write protection page 30*/
+#define SYSCFG_SWPR_PAGE31_Pos              (31U)                              
+#define SYSCFG_SWPR_PAGE31_Msk              (0x1U << SYSCFG_SWPR_PAGE31_Pos)   /*!< 0x80000000 */
+#define SYSCFG_SWPR_PAGE31                  SYSCFG_SWPR_PAGE31_Msk             /*!< SRAM2 Write protection page 31*/
+
+/******************  Bit definition for SYSCFG_SKR register  ****************/
+#define SYSCFG_SKR_KEY_Pos                  (0U)                               
+#define SYSCFG_SKR_KEY_Msk                  (0xFFU << SYSCFG_SKR_KEY_Pos)      /*!< 0x000000FF */
+#define SYSCFG_SKR_KEY                      SYSCFG_SKR_KEY_Msk                 /*!<  SRAM2 write protection key for software erase  */
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)                                         
+#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)                                         
+#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)                                         
+#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)                                         
+#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)                                         
+#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)                                         
+#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)                                         
+#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)                                         
+#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)                                        
+#define TIM_CR1_UIFREMAP_Msk      (0x1U << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)                                         
+#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)                                         
+#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)                                         
+#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)                                         
+#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)                                         
+#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)                                         
+#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)                                         
+#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)                                        
+#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)                                        
+#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)                                        
+#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)                                        
+#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)                                        
+#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)                                        
+#define TIM_CR2_OIS5_Msk          (0x1U << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos          (18U)                                        
+#define TIM_CR2_OIS6_Msk          (0x1U << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)                                        
+#define TIM_CR2_MMS2_Msk          (0xFU << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1U << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2U << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4U << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8U << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)                                         
+#define TIM_SMCR_SMS_Msk          (0x10007U << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001U << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002U << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004U << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000U << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
+
+#define TIM_SMCR_OCCS_Pos         (3U)                                         
+#define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
+#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos           (4U)                                         
+#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos          (7U)                                         
+#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)                                         
+#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)                                        
+#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)                                        
+#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)                                        
+#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)                                         
+#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)                                         
+#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)                                         
+#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)                                         
+#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)                                         
+#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)                                         
+#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)                                         
+#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)                                         
+#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)                                         
+#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)                                         
+#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)                                        
+#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)                                        
+#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)                                        
+#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)                                        
+#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)                                        
+#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)                                         
+#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)                                         
+#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)                                         
+#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)                                         
+#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)                                         
+#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)                                         
+#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)                                         
+#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)                                         
+#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)                                         
+#define TIM_SR_B2IF_Msk           (0x1U << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)                                         
+#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)                                        
+#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)                                        
+#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)                                        
+#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos           (13U)                                        
+#define TIM_SR_SBIF_Msk           (0x1U << TIM_SR_SBIF_Pos)                    /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos          (16U)                                        
+#define TIM_SR_CC5IF_Msk          (0x1U << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)                                        
+#define TIM_SR_CC6IF_Msk          (0x1U << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)                                         
+#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)                                         
+#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)                                         
+#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)                                         
+#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)                                         
+#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)                                         
+#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)                                         
+#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)                                         
+#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)                                         
+#define TIM_EGR_B2G_Msk           (0x1U << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)                                         
+#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
+#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
+#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)                                         
+#define TIM_CCMR1_OC1M_Msk        (0x1007U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
+#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)                                         
+#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
+#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
+#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)                                        
+#define TIM_CCMR1_OC2M_Msk        (0x1007U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
+#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
+#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)                                         
+#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
+#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)                                        
+#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)                                         
+#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
+#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
+#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)                                         
+#define TIM_CCMR2_OC3M_Msk        (0x1007U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x0001U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x0002U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x0004U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
+#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)                                         
+#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
+#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
+#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)                                        
+#define TIM_CCMR2_OC4M_Msk        (0x1007U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x0001U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x0002U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x0004U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
+#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
+#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)                                         
+#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
+#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)                                        
+#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)                                         
+#define TIM_CCMR3_OC5FE_Msk       (0x1U << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)                                         
+#define TIM_CCMR3_OC5PE_Msk       (0x1U << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)                                         
+#define TIM_CCMR3_OC5M_Msk        (0x1007U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x0001U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x0002U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x0004U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)                                         
+#define TIM_CCMR3_OC5CE_Msk       (0x1U << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)                                        
+#define TIM_CCMR3_OC6FE_Msk       (0x1U << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)                                        
+#define TIM_CCMR3_OC6PE_Msk       (0x1U << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)                                        
+#define TIM_CCMR3_OC6M_Msk        (0x1007U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x0001U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x0002U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x0004U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)                                        
+#define TIM_CCMR3_OC6CE_Msk       (0x1U << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)                                         
+#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)                                         
+#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)                                         
+#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)                                         
+#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)                                         
+#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)                                         
+#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)                                         
+#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)                                         
+#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)                                         
+#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)                                         
+#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)                                        
+#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)                                        
+#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)                                        
+#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)                                        
+#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)                                        
+#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)                                        
+#define TIM_CCER_CC5E_Msk         (0x1U << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)                                        
+#define TIM_CCER_CC5P_Msk         (0x1U << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)                                        
+#define TIM_CCER_CC6E_Msk         (0x1U << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)                                        
+#define TIM_CCER_CC6P_Msk         (0x1U << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)                                         
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)                                        
+#define TIM_CNT_UIFCPY_Msk        (0x1U << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)                                         
+#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)                                         
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)                                         
+#define TIM_RCR_REP_Msk           (0xFFFFU << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)                                         
+#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)                                         
+#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)                                         
+#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)                                         
+#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)                                         
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)                                        
+#define TIM_CCR5_GC5C1_Msk        (0x1U << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)                                        
+#define TIM_CCR5_GC5C2_Msk        (0x1U << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)                                        
+#define TIM_CCR5_GC5C3_Msk        (0x1U << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)                                         
+#define TIM_CCR6_CCR6_Msk         (0xFFFFU << TIM_CCR6_CCR6_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)                                         
+#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)                                         
+#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)                                        
+#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)                                        
+#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)                                        
+#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)                                        
+#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)                                        
+#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)                                        
+#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)                                        
+#define TIM_BDTR_BKF_Msk          (0xFU << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos         (20U)                                        
+#define TIM_BDTR_BK2F_Msk         (0xFU << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)                                        
+#define TIM_BDTR_BK2E_Msk         (0x1U << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos         (25U)                                        
+#define TIM_BDTR_BK2P_Msk         (0x1U << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)                                         
+#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)                                         
+#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)                                         
+#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM1_OR1 register  *******************/
+#define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)                                    
+#define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000003 */
+#define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
+#define TIM1_OR1_ETR_ADC1_RMP_0        (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000001 */
+#define TIM1_OR1_ETR_ADC1_RMP_1        (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000002 */
+
+#define TIM1_OR1_ETR_ADC3_RMP_Pos      (2U)                                    
+#define TIM1_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */
+#define TIM1_OR1_ETR_ADC3_RMP          TIM1_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
+#define TIM1_OR1_ETR_ADC3_RMP_0        (0x1U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */
+#define TIM1_OR1_ETR_ADC3_RMP_1        (0x2U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */
+
+#define TIM1_OR1_TI1_RMP_Pos           (4U)                                    
+#define TIM1_OR1_TI1_RMP_Msk           (0x1U << TIM1_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
+#define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */
+
+/*******************  Bit definition for TIM1_OR2 register  *******************/
+#define TIM1_OR2_BKINE_Pos             (0U)                                    
+#define TIM1_OR2_BKINE_Msk             (0x1U << TIM1_OR2_BKINE_Pos)            /*!< 0x00000001 */
+#define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
+#define TIM1_OR2_BKCMP1E_Pos           (1U)                                    
+#define TIM1_OR2_BKCMP1E_Msk           (0x1U << TIM1_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
+#define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
+#define TIM1_OR2_BKCMP2E_Pos           (2U)                                    
+#define TIM1_OR2_BKCMP2E_Msk           (0x1U << TIM1_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
+#define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
+#define TIM1_OR2_BKDF1BK0E_Pos         (8U)                                    
+#define TIM1_OR2_BKDF1BK0E_Msk         (0x1U << TIM1_OR2_BKDF1BK0E_Pos)        /*!< 0x00000100 */
+#define TIM1_OR2_BKDF1BK0E             TIM1_OR2_BKDF1BK0E_Msk                  /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM1_OR2_BKINP_Pos             (9U)                                    
+#define TIM1_OR2_BKINP_Msk             (0x1U << TIM1_OR2_BKINP_Pos)            /*!< 0x00000200 */
+#define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
+#define TIM1_OR2_BKCMP1P_Pos           (10U)                                   
+#define TIM1_OR2_BKCMP1P_Msk           (0x1U << TIM1_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
+#define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
+#define TIM1_OR2_BKCMP2P_Pos           (11U)                                   
+#define TIM1_OR2_BKCMP2P_Msk           (0x1U << TIM1_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
+#define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
+
+#define TIM1_OR2_ETRSEL_Pos            (14U)                                   
+#define TIM1_OR2_ETRSEL_Msk            (0x7U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
+#define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
+#define TIM1_OR2_ETRSEL_0              (0x1U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
+#define TIM1_OR2_ETRSEL_1              (0x2U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
+#define TIM1_OR2_ETRSEL_2              (0x4U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM1_OR3 register  *******************/
+#define TIM1_OR3_BK2INE_Pos            (0U)                                    
+#define TIM1_OR3_BK2INE_Msk            (0x1U << TIM1_OR3_BK2INE_Pos)           /*!< 0x00000001 */
+#define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
+#define TIM1_OR3_BK2CMP1E_Pos          (1U)                                    
+#define TIM1_OR3_BK2CMP1E_Msk          (0x1U << TIM1_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
+#define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
+#define TIM1_OR3_BK2CMP2E_Pos          (2U)                                    
+#define TIM1_OR3_BK2CMP2E_Msk          (0x1U << TIM1_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
+#define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
+#define TIM1_OR3_BK2DF1BK1E_Pos        (8U)                                    
+#define TIM1_OR3_BK2DF1BK1E_Msk        (0x1U << TIM1_OR3_BK2DF1BK1E_Pos)       /*!< 0x00000100 */
+#define TIM1_OR3_BK2DF1BK1E            TIM1_OR3_BK2DF1BK1E_Msk                 /*!<BRK2 DFSDM1_BREAK[1] enable */
+#define TIM1_OR3_BK2INP_Pos            (9U)                                    
+#define TIM1_OR3_BK2INP_Msk            (0x1U << TIM1_OR3_BK2INP_Pos)           /*!< 0x00000200 */
+#define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
+#define TIM1_OR3_BK2CMP1P_Pos          (10U)                                   
+#define TIM1_OR3_BK2CMP1P_Msk          (0x1U << TIM1_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
+#define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
+#define TIM1_OR3_BK2CMP2P_Pos          (11U)                                   
+#define TIM1_OR3_BK2CMP2P_Msk          (0x1U << TIM1_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
+#define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM8_OR1 register  *******************/
+#define TIM8_OR1_ETR_ADC2_RMP_Pos      (0U)                                    
+#define TIM8_OR1_ETR_ADC2_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000003 */
+#define TIM8_OR1_ETR_ADC2_RMP          TIM8_OR1_ETR_ADC2_RMP_Msk               /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
+#define TIM8_OR1_ETR_ADC2_RMP_0        (0x1U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000001 */
+#define TIM8_OR1_ETR_ADC2_RMP_1        (0x2U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000002 */
+
+#define TIM8_OR1_ETR_ADC3_RMP_Pos      (2U)                                    
+#define TIM8_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */
+#define TIM8_OR1_ETR_ADC3_RMP          TIM8_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
+#define TIM8_OR1_ETR_ADC3_RMP_0        (0x1U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */
+#define TIM8_OR1_ETR_ADC3_RMP_1        (0x2U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */
+
+#define TIM8_OR1_TI1_RMP_Pos           (4U)                                    
+#define TIM8_OR1_TI1_RMP_Msk           (0x1U << TIM8_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
+#define TIM8_OR1_TI1_RMP               TIM8_OR1_TI1_RMP_Msk                    /*!<TIM8 Input Capture 1 remap */
+
+/*******************  Bit definition for TIM8_OR2 register  *******************/
+#define TIM8_OR2_BKINE_Pos             (0U)                                    
+#define TIM8_OR2_BKINE_Msk             (0x1U << TIM8_OR2_BKINE_Pos)            /*!< 0x00000001 */
+#define TIM8_OR2_BKINE                 TIM8_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
+#define TIM8_OR2_BKCMP1E_Pos           (1U)                                    
+#define TIM8_OR2_BKCMP1E_Msk           (0x1U << TIM8_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
+#define TIM8_OR2_BKCMP1E               TIM8_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
+#define TIM8_OR2_BKCMP2E_Pos           (2U)                                    
+#define TIM8_OR2_BKCMP2E_Msk           (0x1U << TIM8_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
+#define TIM8_OR2_BKCMP2E               TIM8_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
+#define TIM8_OR2_BKDF1BK2E_Pos         (8U)                                    
+#define TIM8_OR2_BKDF1BK2E_Msk         (0x1U << TIM8_OR2_BKDF1BK2E_Pos)        /*!< 0x00000100 */
+#define TIM8_OR2_BKDF1BK2E             TIM8_OR2_BKDF1BK2E_Msk                  /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM8_OR2_BKINP_Pos             (9U)                                    
+#define TIM8_OR2_BKINP_Msk             (0x1U << TIM8_OR2_BKINP_Pos)            /*!< 0x00000200 */
+#define TIM8_OR2_BKINP                 TIM8_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
+#define TIM8_OR2_BKCMP1P_Pos           (10U)                                   
+#define TIM8_OR2_BKCMP1P_Msk           (0x1U << TIM8_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
+#define TIM8_OR2_BKCMP1P               TIM8_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
+#define TIM8_OR2_BKCMP2P_Pos           (11U)                                   
+#define TIM8_OR2_BKCMP2P_Msk           (0x1U << TIM8_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
+#define TIM8_OR2_BKCMP2P               TIM8_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
+
+#define TIM8_OR2_ETRSEL_Pos            (14U)                                   
+#define TIM8_OR2_ETRSEL_Msk            (0x7U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
+#define TIM8_OR2_ETRSEL                TIM8_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
+#define TIM8_OR2_ETRSEL_0              (0x1U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
+#define TIM8_OR2_ETRSEL_1              (0x2U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
+#define TIM8_OR2_ETRSEL_2              (0x4U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM8_OR3 register  *******************/
+#define TIM8_OR3_BK2INE_Pos            (0U)                                    
+#define TIM8_OR3_BK2INE_Msk            (0x1U << TIM8_OR3_BK2INE_Pos)           /*!< 0x00000001 */
+#define TIM8_OR3_BK2INE                TIM8_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
+#define TIM8_OR3_BK2CMP1E_Pos          (1U)                                    
+#define TIM8_OR3_BK2CMP1E_Msk          (0x1U << TIM8_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
+#define TIM8_OR3_BK2CMP1E              TIM8_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
+#define TIM8_OR3_BK2CMP2E_Pos          (2U)                                    
+#define TIM8_OR3_BK2CMP2E_Msk          (0x1U << TIM8_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
+#define TIM8_OR3_BK2CMP2E              TIM8_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
+#define TIM8_OR3_BK2DF1BK3E_Pos        (8U)                                    
+#define TIM8_OR3_BK2DF1BK3E_Msk        (0x1U << TIM8_OR3_BK2DF1BK3E_Pos)       /*!< 0x00000100 */
+#define TIM8_OR3_BK2DF1BK3E            TIM8_OR3_BK2DF1BK3E_Msk                 /*!<BRK2 DFSDM1_BREAK[3] enable */
+#define TIM8_OR3_BK2INP_Pos            (9U)                                    
+#define TIM8_OR3_BK2INP_Msk            (0x1U << TIM8_OR3_BK2INP_Pos)           /*!< 0x00000200 */
+#define TIM8_OR3_BK2INP                TIM8_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
+#define TIM8_OR3_BK2CMP1P_Pos          (10U)                                   
+#define TIM8_OR3_BK2CMP1P_Msk          (0x1U << TIM8_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
+#define TIM8_OR3_BK2CMP1P              TIM8_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
+#define TIM8_OR3_BK2CMP2P_Pos          (11U)                                   
+#define TIM8_OR3_BK2CMP2P_Msk          (0x1U << TIM8_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
+#define TIM8_OR3_BK2CMP2P              TIM8_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM2_OR1 register  *******************/
+#define TIM2_OR1_ITR1_RMP_Pos      (0U)                                        
+#define TIM2_OR1_ITR1_RMP_Msk      (0x1U << TIM2_OR1_ITR1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM2_OR1_ITR1_RMP          TIM2_OR1_ITR1_RMP_Msk                       /*!<TIM2 Internal trigger 1 remap */
+#define TIM2_OR1_ETR1_RMP_Pos      (1U)                                        
+#define TIM2_OR1_ETR1_RMP_Msk      (0x1U << TIM2_OR1_ETR1_RMP_Pos)             /*!< 0x00000002 */
+#define TIM2_OR1_ETR1_RMP          TIM2_OR1_ETR1_RMP_Msk                       /*!<TIM2 External trigger 1 remap */
+
+#define TIM2_OR1_TI4_RMP_Pos       (2U)                                        
+#define TIM2_OR1_TI4_RMP_Msk       (0x3U << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x0000000C */
+#define TIM2_OR1_TI4_RMP           TIM2_OR1_TI4_RMP_Msk                        /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
+#define TIM2_OR1_TI4_RMP_0         (0x1U << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x00000004 */
+#define TIM2_OR1_TI4_RMP_1         (0x2U << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x00000008 */
+
+/*******************  Bit definition for TIM2_OR2 register  *******************/
+#define TIM2_OR2_ETRSEL_Pos        (14U)                                       
+#define TIM2_OR2_ETRSEL_Msk        (0x7U << TIM2_OR2_ETRSEL_Pos)               /*!< 0x0001C000 */
+#define TIM2_OR2_ETRSEL            TIM2_OR2_ETRSEL_Msk                         /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
+#define TIM2_OR2_ETRSEL_0          (0x1U << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00004000 */
+#define TIM2_OR2_ETRSEL_1          (0x2U << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00008000 */
+#define TIM2_OR2_ETRSEL_2          (0x4U << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM3_OR1 register  *******************/
+#define TIM3_OR1_TI1_RMP_Pos       (0U)                                        
+#define TIM3_OR1_TI1_RMP_Msk       (0x3U << TIM3_OR1_TI1_RMP_Pos)              /*!< 0x00000003 */
+#define TIM3_OR1_TI1_RMP           TIM3_OR1_TI1_RMP_Msk                        /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
+#define TIM3_OR1_TI1_RMP_0         (0x1U << TIM3_OR1_TI1_RMP_Pos)              /*!< 0x00000001 */
+#define TIM3_OR1_TI1_RMP_1         (0x2U << TIM3_OR1_TI1_RMP_Pos)              /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM3_OR2 register  *******************/
+#define TIM3_OR2_ETRSEL_Pos        (14U)                                       
+#define TIM3_OR2_ETRSEL_Msk        (0x7U << TIM3_OR2_ETRSEL_Pos)               /*!< 0x0001C000 */
+#define TIM3_OR2_ETRSEL            TIM3_OR2_ETRSEL_Msk                         /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
+#define TIM3_OR2_ETRSEL_0          (0x1U << TIM3_OR2_ETRSEL_Pos)               /*!< 0x00004000 */
+#define TIM3_OR2_ETRSEL_1          (0x2U << TIM3_OR2_ETRSEL_Pos)               /*!< 0x00008000 */
+#define TIM3_OR2_ETRSEL_2          (0x4U << TIM3_OR2_ETRSEL_Pos)               /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM15_OR1 register  ******************/
+#define TIM15_OR1_TI1_RMP_Pos      (0U)                                        
+#define TIM15_OR1_TI1_RMP_Msk      (0x1U << TIM15_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM15_OR1_TI1_RMP          TIM15_OR1_TI1_RMP_Msk                       /*!<TIM15 Input Capture 1 remap */
+
+#define TIM15_OR1_ENCODER_MODE_Pos (1U)                                        
+#define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos)        /*!< 0x00000006 */
+#define TIM15_OR1_ENCODER_MODE     TIM15_OR1_ENCODER_MODE_Msk                  /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
+#define TIM15_OR1_ENCODER_MODE_0   (0x1U << TIM15_OR1_ENCODER_MODE_Pos)        /*!< 0x00000002 */
+#define TIM15_OR1_ENCODER_MODE_1   (0x2U << TIM15_OR1_ENCODER_MODE_Pos)        /*!< 0x00000004 */
+
+/*******************  Bit definition for TIM15_OR2 register  ******************/
+#define TIM15_OR2_BKINE_Pos        (0U)                                        
+#define TIM15_OR2_BKINE_Msk        (0x1U << TIM15_OR2_BKINE_Pos)               /*!< 0x00000001 */
+#define TIM15_OR2_BKINE            TIM15_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
+#define TIM15_OR2_BKCMP1E_Pos      (1U)                                        
+#define TIM15_OR2_BKCMP1E_Msk      (0x1U << TIM15_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
+#define TIM15_OR2_BKCMP1E          TIM15_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
+#define TIM15_OR2_BKCMP2E_Pos      (2U)                                        
+#define TIM15_OR2_BKCMP2E_Msk      (0x1U << TIM15_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
+#define TIM15_OR2_BKCMP2E          TIM15_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
+#define TIM15_OR2_BKDF1BK0E_Pos    (8U)                                        
+#define TIM15_OR2_BKDF1BK0E_Msk    (0x1U << TIM15_OR2_BKDF1BK0E_Pos)           /*!< 0x00000100 */
+#define TIM15_OR2_BKDF1BK0E        TIM15_OR2_BKDF1BK0E_Msk                     /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM15_OR2_BKINP_Pos        (9U)                                        
+#define TIM15_OR2_BKINP_Msk        (0x1U << TIM15_OR2_BKINP_Pos)               /*!< 0x00000200 */
+#define TIM15_OR2_BKINP            TIM15_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
+#define TIM15_OR2_BKCMP1P_Pos      (10U)                                       
+#define TIM15_OR2_BKCMP1P_Msk      (0x1U << TIM15_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
+#define TIM15_OR2_BKCMP1P          TIM15_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
+#define TIM15_OR2_BKCMP2P_Pos      (11U)                                       
+#define TIM15_OR2_BKCMP2P_Msk      (0x1U << TIM15_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
+#define TIM15_OR2_BKCMP2P          TIM15_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
+
+/*******************  Bit definition for TIM16_OR1 register  ******************/
+#define TIM16_OR1_TI1_RMP_Pos      (0U)                                        
+#define TIM16_OR1_TI1_RMP_Msk      (0x3U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000003 */
+#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
+#define TIM16_OR1_TI1_RMP_0        (0x1U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM16_OR1_TI1_RMP_1        (0x2U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM16_OR2 register  ******************/
+#define TIM16_OR2_BKINE_Pos        (0U)                                        
+#define TIM16_OR2_BKINE_Msk        (0x1U << TIM16_OR2_BKINE_Pos)               /*!< 0x00000001 */
+#define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
+#define TIM16_OR2_BKCMP1E_Pos      (1U)                                        
+#define TIM16_OR2_BKCMP1E_Msk      (0x1U << TIM16_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
+#define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
+#define TIM16_OR2_BKCMP2E_Pos      (2U)                                        
+#define TIM16_OR2_BKCMP2E_Msk      (0x1U << TIM16_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
+#define TIM16_OR2_BKCMP2E          TIM16_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
+#define TIM16_OR2_BKDF1BK1E_Pos    (8U)                                        
+#define TIM16_OR2_BKDF1BK1E_Msk    (0x1U << TIM16_OR2_BKDF1BK1E_Pos)           /*!< 0x00000100 */
+#define TIM16_OR2_BKDF1BK1E        TIM16_OR2_BKDF1BK1E_Msk                     /*!<BRK DFSDM1_BREAK[1] enable */
+#define TIM16_OR2_BKINP_Pos        (9U)                                        
+#define TIM16_OR2_BKINP_Msk        (0x1U << TIM16_OR2_BKINP_Pos)               /*!< 0x00000200 */
+#define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
+#define TIM16_OR2_BKCMP1P_Pos      (10U)                                       
+#define TIM16_OR2_BKCMP1P_Msk      (0x1U << TIM16_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
+#define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
+#define TIM16_OR2_BKCMP2P_Pos      (11U)                                       
+#define TIM16_OR2_BKCMP2P_Msk      (0x1U << TIM16_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
+#define TIM16_OR2_BKCMP2P          TIM16_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
+
+/*******************  Bit definition for TIM17_OR1 register  ******************/
+#define TIM17_OR1_TI1_RMP_Pos      (0U)                                        
+#define TIM17_OR1_TI1_RMP_Msk      (0x3U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000003 */
+#define TIM17_OR1_TI1_RMP          TIM17_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
+#define TIM17_OR1_TI1_RMP_0        (0x1U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM17_OR1_TI1_RMP_1        (0x2U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM17_OR2 register  ******************/
+#define TIM17_OR2_BKINE_Pos        (0U)                                        
+#define TIM17_OR2_BKINE_Msk        (0x1U << TIM17_OR2_BKINE_Pos)               /*!< 0x00000001 */
+#define TIM17_OR2_BKINE            TIM17_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
+#define TIM17_OR2_BKCMP1E_Pos      (1U)                                        
+#define TIM17_OR2_BKCMP1E_Msk      (0x1U << TIM17_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
+#define TIM17_OR2_BKCMP1E          TIM17_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
+#define TIM17_OR2_BKCMP2E_Pos      (2U)                                        
+#define TIM17_OR2_BKCMP2E_Msk      (0x1U << TIM17_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
+#define TIM17_OR2_BKCMP2E          TIM17_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
+#define TIM17_OR2_BKDF1BK2E_Pos    (8U)                                        
+#define TIM17_OR2_BKDF1BK2E_Msk    (0x1U << TIM17_OR2_BKDF1BK2E_Pos)           /*!< 0x00000100 */
+#define TIM17_OR2_BKDF1BK2E        TIM17_OR2_BKDF1BK2E_Msk                     /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM17_OR2_BKINP_Pos        (9U)                                        
+#define TIM17_OR2_BKINP_Msk        (0x1U << TIM17_OR2_BKINP_Pos)               /*!< 0x00000200 */
+#define TIM17_OR2_BKINP            TIM17_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
+#define TIM17_OR2_BKCMP1P_Pos      (10U)                                       
+#define TIM17_OR2_BKCMP1P_Msk      (0x1U << TIM17_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
+#define TIM17_OR2_BKCMP1P          TIM17_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
+#define TIM17_OR2_BKCMP2P_Pos      (11U)                                       
+#define TIM17_OR2_BKCMP2P_Msk      (0x1U << TIM17_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
+#define TIM17_OR2_BKCMP2P          TIM17_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos                     (0U)                            
+#define LPTIM_ISR_CMPM_Msk                     (0x1U << LPTIM_ISR_CMPM_Pos)    /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM                         LPTIM_ISR_CMPM_Msk              /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos                     (1U)                            
+#define LPTIM_ISR_ARRM_Msk                     (0x1U << LPTIM_ISR_ARRM_Pos)    /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM                         LPTIM_ISR_ARRM_Msk              /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos                  (2U)                            
+#define LPTIM_ISR_EXTTRIG_Msk                  (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG                      LPTIM_ISR_EXTTRIG_Msk           /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos                    (3U)                            
+#define LPTIM_ISR_CMPOK_Msk                    (0x1U << LPTIM_ISR_CMPOK_Pos)   /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK                        LPTIM_ISR_CMPOK_Msk             /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos                    (4U)                            
+#define LPTIM_ISR_ARROK_Msk                    (0x1U << LPTIM_ISR_ARROK_Pos)   /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK                        LPTIM_ISR_ARROK_Msk             /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos                       (5U)                            
+#define LPTIM_ISR_UP_Msk                       (0x1U << LPTIM_ISR_UP_Pos)      /*!< 0x00000020 */
+#define LPTIM_ISR_UP                           LPTIM_ISR_UP_Msk                /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos                     (6U)                            
+#define LPTIM_ISR_DOWN_Msk                     (0x1U << LPTIM_ISR_DOWN_Pos)    /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN                         LPTIM_ISR_DOWN_Msk              /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos                   (0U)                            
+#define LPTIM_ICR_CMPMCF_Msk                   (0x1U << LPTIM_ICR_CMPMCF_Pos)  /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF                       LPTIM_ICR_CMPMCF_Msk            /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos                   (1U)                            
+#define LPTIM_ICR_ARRMCF_Msk                   (0x1U << LPTIM_ICR_ARRMCF_Pos)  /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF                       LPTIM_ICR_ARRMCF_Msk            /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos                (2U)                            
+#define LPTIM_ICR_EXTTRIGCF_Msk                (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF                    LPTIM_ICR_EXTTRIGCF_Msk         /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos                  (3U)                            
+#define LPTIM_ICR_CMPOKCF_Msk                  (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF                      LPTIM_ICR_CMPOKCF_Msk           /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos                  (4U)                            
+#define LPTIM_ICR_ARROKCF_Msk                  (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF                      LPTIM_ICR_ARROKCF_Msk           /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos                     (5U)                            
+#define LPTIM_ICR_UPCF_Msk                     (0x1U << LPTIM_ICR_UPCF_Pos)    /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF                         LPTIM_ICR_UPCF_Msk              /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos                   (6U)                            
+#define LPTIM_ICR_DOWNCF_Msk                   (0x1U << LPTIM_ICR_DOWNCF_Pos)  /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF                       LPTIM_ICR_DOWNCF_Msk            /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos                   (0U)                            
+#define LPTIM_IER_CMPMIE_Msk                   (0x1U << LPTIM_IER_CMPMIE_Pos)  /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE                       LPTIM_IER_CMPMIE_Msk            /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos                   (1U)                            
+#define LPTIM_IER_ARRMIE_Msk                   (0x1U << LPTIM_IER_ARRMIE_Pos)  /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE                       LPTIM_IER_ARRMIE_Msk            /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos                (2U)                            
+#define LPTIM_IER_EXTTRIGIE_Msk                (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE                    LPTIM_IER_EXTTRIGIE_Msk         /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos                  (3U)                            
+#define LPTIM_IER_CMPOKIE_Msk                  (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE                      LPTIM_IER_CMPOKIE_Msk           /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos                  (4U)                            
+#define LPTIM_IER_ARROKIE_Msk                  (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE                      LPTIM_IER_ARROKIE_Msk           /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos                     (5U)                            
+#define LPTIM_IER_UPIE_Msk                     (0x1U << LPTIM_IER_UPIE_Pos)    /*!< 0x00000020 */
+#define LPTIM_IER_UPIE                         LPTIM_IER_UPIE_Msk              /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos                   (6U)                            
+#define LPTIM_IER_DOWNIE_Msk                   (0x1U << LPTIM_IER_DOWNIE_Pos)  /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE                       LPTIM_IER_DOWNIE_Msk            /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos                   (0U)                            
+#define LPTIM_CFGR_CKSEL_Msk                   (0x1U << LPTIM_CFGR_CKSEL_Pos)  /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL                       LPTIM_CFGR_CKSEL_Msk            /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos                   (1U)                            
+#define LPTIM_CFGR_CKPOL_Msk                   (0x3U << LPTIM_CFGR_CKPOL_Pos)  /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL                       LPTIM_CFGR_CKPOL_Msk            /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0                     (0x1U << LPTIM_CFGR_CKPOL_Pos)  /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1                     (0x2U << LPTIM_CFGR_CKPOL_Pos)  /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos                   (3U)                            
+#define LPTIM_CFGR_CKFLT_Msk                   (0x3U << LPTIM_CFGR_CKFLT_Pos)  /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT                       LPTIM_CFGR_CKFLT_Msk            /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0                     (0x1U << LPTIM_CFGR_CKFLT_Pos)  /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1                     (0x2U << LPTIM_CFGR_CKFLT_Pos)  /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos                  (6U)                            
+#define LPTIM_CFGR_TRGFLT_Msk                  (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT                      LPTIM_CFGR_TRGFLT_Msk           /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0                    (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1                    (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos                   (9U)                            
+#define LPTIM_CFGR_PRESC_Msk                   (0x7U << LPTIM_CFGR_PRESC_Pos)  /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC                       LPTIM_CFGR_PRESC_Msk            /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0                     (0x1U << LPTIM_CFGR_PRESC_Pos)  /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1                     (0x2U << LPTIM_CFGR_PRESC_Pos)  /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2                     (0x4U << LPTIM_CFGR_PRESC_Pos)  /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos                 (13U)                           
+#define LPTIM_CFGR_TRIGSEL_Msk                 (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL                     LPTIM_CFGR_TRIGSEL_Msk          /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0                   (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1                   (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2                   (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos                  (17U)                           
+#define LPTIM_CFGR_TRIGEN_Msk                  (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN                      LPTIM_CFGR_TRIGEN_Msk           /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0                    (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1                    (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos                  (19U)                           
+#define LPTIM_CFGR_TIMOUT_Msk                  (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT                      LPTIM_CFGR_TIMOUT_Msk           /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos                    (20U)                           
+#define LPTIM_CFGR_WAVE_Msk                    (0x1U << LPTIM_CFGR_WAVE_Pos)   /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE                        LPTIM_CFGR_WAVE_Msk             /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos                  (21U)                           
+#define LPTIM_CFGR_WAVPOL_Msk                  (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL                      LPTIM_CFGR_WAVPOL_Msk           /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos                 (22U)                           
+#define LPTIM_CFGR_PRELOAD_Msk                 (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD                     LPTIM_CFGR_PRELOAD_Msk          /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos               (23U)                           
+#define LPTIM_CFGR_COUNTMODE_Msk               (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE                   LPTIM_CFGR_COUNTMODE_Msk        /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos                     (24U)                           
+#define LPTIM_CFGR_ENC_Msk                     (0x1U << LPTIM_CFGR_ENC_Pos)    /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC                         LPTIM_CFGR_ENC_Msk              /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos                    (0U)                            
+#define LPTIM_CR_ENABLE_Msk                    (0x1U << LPTIM_CR_ENABLE_Pos)   /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE                        LPTIM_CR_ENABLE_Msk             /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos                   (1U)                            
+#define LPTIM_CR_SNGSTRT_Msk                   (0x1U << LPTIM_CR_SNGSTRT_Pos)  /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT                       LPTIM_CR_SNGSTRT_Msk            /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos                   (2U)                            
+#define LPTIM_CR_CNTSTRT_Msk                   (0x1U << LPTIM_CR_CNTSTRT_Pos)  /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT                       LPTIM_CR_CNTSTRT_Msk            /*!< Timer start in continuous mode */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos                      (0U)                            
+#define LPTIM_CMP_CMP_Msk                      (0xFFFFU << LPTIM_CMP_CMP_Pos)  /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP                          LPTIM_CMP_CMP_Msk               /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos                      (0U)                            
+#define LPTIM_ARR_ARR_Msk                      (0xFFFFU << LPTIM_ARR_ARR_Pos)  /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR                          LPTIM_ARR_ARR_Msk               /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos                      (0U)                            
+#define LPTIM_CNT_CNT_Msk                      (0xFFFFU << LPTIM_CNT_CNT_Pos)  /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT                          LPTIM_CNT_CNT_Msk               /*!< Counter register */
+
+/******************  Bit definition for LPTIM_OR register  *******************/
+#define LPTIM_OR_OR_Pos                        (0U)                            
+#define LPTIM_OR_OR_Msk                        (0x3U << LPTIM_OR_OR_Pos)       /*!< 0x00000003 */
+#define LPTIM_OR_OR                            LPTIM_OR_OR_Msk                 /*!< LPTIMER[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0                          (0x1U << LPTIM_OR_OR_Pos)       /*!< 0x00000001 */
+#define LPTIM_OR_OR_1                          (0x2U << LPTIM_OR_OR_Pos)       /*!< 0x00000002 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/**********************  Bit definition for COMP_CSR register  ****************/
+#define COMP_CSR_EN_Pos                (0U)                                    
+#define COMP_CSR_EN_Msk                (0x1U << COMP_CSR_EN_Pos)               /*!< 0x00000001 */
+#define COMP_CSR_EN                    COMP_CSR_EN_Msk                         /*!< Comparator enable */
+
+#define COMP_CSR_PWRMODE_Pos           (2U)                                    
+#define COMP_CSR_PWRMODE_Msk           (0x3U << COMP_CSR_PWRMODE_Pos)          /*!< 0x0000000C */
+#define COMP_CSR_PWRMODE               COMP_CSR_PWRMODE_Msk                    /*!< Comparator power mode */
+#define COMP_CSR_PWRMODE_0             (0x1U << COMP_CSR_PWRMODE_Pos)          /*!< 0x00000004 */
+#define COMP_CSR_PWRMODE_1             (0x2U << COMP_CSR_PWRMODE_Pos)          /*!< 0x00000008 */
+
+#define COMP_CSR_INMSEL_Pos            (4U)                                    
+#define COMP_CSR_INMSEL_Msk            (0x7U << COMP_CSR_INMSEL_Pos)           /*!< 0x00000070 */
+#define COMP_CSR_INMSEL                COMP_CSR_INMSEL_Msk                     /*!< Comparator input minus selection */
+#define COMP_CSR_INMSEL_0              (0x1U << COMP_CSR_INMSEL_Pos)           /*!< 0x00000010 */
+#define COMP_CSR_INMSEL_1              (0x2U << COMP_CSR_INMSEL_Pos)           /*!< 0x00000020 */
+#define COMP_CSR_INMSEL_2              (0x4U << COMP_CSR_INMSEL_Pos)           /*!< 0x00000040 */
+
+#define COMP_CSR_INPSEL_Pos            (7U)                                    
+#define COMP_CSR_INPSEL_Msk            (0x1U << COMP_CSR_INPSEL_Pos)           /*!< 0x00000080 */
+#define COMP_CSR_INPSEL                COMP_CSR_INPSEL_Msk                     /*!< Comparator input plus selection */
+#define COMP_CSR_INPSEL_0              (0x1U << COMP_CSR_INPSEL_Pos)           /*!< 0x00000080 */
+
+#define COMP_CSR_WINMODE_Pos           (9U)                                    
+#define COMP_CSR_WINMODE_Msk           (0x1U << COMP_CSR_WINMODE_Pos)          /*!< 0x00000200 */
+#define COMP_CSR_WINMODE               COMP_CSR_WINMODE_Msk                    /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
+
+#define COMP_CSR_POLARITY_Pos          (15U)                                   
+#define COMP_CSR_POLARITY_Msk          (0x1U << COMP_CSR_POLARITY_Pos)         /*!< 0x00008000 */
+#define COMP_CSR_POLARITY              COMP_CSR_POLARITY_Msk                   /*!< Comparator output polarity */
+
+#define COMP_CSR_HYST_Pos              (16U)                                   
+#define COMP_CSR_HYST_Msk              (0x3U << COMP_CSR_HYST_Pos)             /*!< 0x00030000 */
+#define COMP_CSR_HYST                  COMP_CSR_HYST_Msk                       /*!< Comparator hysteresis */
+#define COMP_CSR_HYST_0                (0x1U << COMP_CSR_HYST_Pos)             /*!< 0x00010000 */
+#define COMP_CSR_HYST_1                (0x2U << COMP_CSR_HYST_Pos)             /*!< 0x00020000 */
+
+#define COMP_CSR_BLANKING_Pos          (18U)                                   
+#define COMP_CSR_BLANKING_Msk          (0x7U << COMP_CSR_BLANKING_Pos)         /*!< 0x001C0000 */
+#define COMP_CSR_BLANKING              COMP_CSR_BLANKING_Msk                   /*!< Comparator blanking source */
+#define COMP_CSR_BLANKING_0            (0x1U << COMP_CSR_BLANKING_Pos)         /*!< 0x00040000 */
+#define COMP_CSR_BLANKING_1            (0x2U << COMP_CSR_BLANKING_Pos)         /*!< 0x00080000 */
+#define COMP_CSR_BLANKING_2            (0x4U << COMP_CSR_BLANKING_Pos)         /*!< 0x00100000 */
+
+#define COMP_CSR_BRGEN_Pos             (22U)                                   
+#define COMP_CSR_BRGEN_Msk             (0x1U << COMP_CSR_BRGEN_Pos)            /*!< 0x00400000 */
+#define COMP_CSR_BRGEN                 COMP_CSR_BRGEN_Msk                      /*!< Comparator voltage scaler enable */
+#define COMP_CSR_SCALEN_Pos            (23U)                                   
+#define COMP_CSR_SCALEN_Msk            (0x1U << COMP_CSR_SCALEN_Pos)           /*!< 0x00800000 */
+#define COMP_CSR_SCALEN                COMP_CSR_SCALEN_Msk                     /*!< Comparator scaler bridge enable */
+
+#define COMP_CSR_VALUE_Pos             (30U)                                   
+#define COMP_CSR_VALUE_Msk             (0x1U << COMP_CSR_VALUE_Pos)            /*!< 0x40000000 */
+#define COMP_CSR_VALUE                 COMP_CSR_VALUE_Msk                      /*!< Comparator output level */
+
+#define COMP_CSR_LOCK_Pos              (31U)                                   
+#define COMP_CSR_LOCK_Msk              (0x1U << COMP_CSR_LOCK_Pos)             /*!< 0x80000000 */
+#define COMP_CSR_LOCK                  COMP_CSR_LOCK_Msk                       /*!< Comparator lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)                                  
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1U << OPAMP_CSR_OPAMPxEN_Pos)      /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
+#define OPAMP_CSR_OPALPM_Pos             (1U)                                  
+#define OPAMP_CSR_OPALPM_Msk             (0x1U << OPAMP_CSR_OPALPM_Pos)        /*!< 0x00000002 */
+#define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */
+
+#define OPAMP_CSR_OPAMODE_Pos            (2U)                                  
+#define OPAMP_CSR_OPAMODE_Msk            (0x3U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x0000000C */
+#define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */
+#define OPAMP_CSR_OPAMODE_0              (0x1U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000004 */
+#define OPAMP_CSR_OPAMODE_1              (0x2U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000008 */
+
+#define OPAMP_CSR_PGGAIN_Pos             (4U)                                  
+#define OPAMP_CSR_PGGAIN_Msk             (0x3U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000030 */
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0               (0x1U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000010 */
+#define OPAMP_CSR_PGGAIN_1               (0x2U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000020 */
+
+#define OPAMP_CSR_VMSEL_Pos              (8U)                                  
+#define OPAMP_CSR_VMSEL_Msk              (0x3U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000300 */
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                (0x1U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000100 */
+#define OPAMP_CSR_VMSEL_1                (0x2U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000200 */
+
+#define OPAMP_CSR_VPSEL_Pos              (10U)                                 
+#define OPAMP_CSR_VPSEL_Msk              (0x1U << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000400 */
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
+#define OPAMP_CSR_CALON_Pos              (12U)                                 
+#define OPAMP_CSR_CALON_Msk              (0x1U << OPAMP_CSR_CALON_Pos)         /*!< 0x00001000 */
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL_Pos             (13U)                                 
+#define OPAMP_CSR_CALSEL_Msk             (0x1U << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
+#define OPAMP_CSR_USERTRIM_Pos           (14U)                                 
+#define OPAMP_CSR_USERTRIM_Msk           (0x1U << OPAMP_CSR_USERTRIM_Pos)      /*!< 0x00004000 */
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
+#define OPAMP_CSR_CALOUT_Pos             (15U)                                 
+#define OPAMP_CSR_CALOUT_Msk             (0x1U << OPAMP_CSR_CALOUT_Pos)        /*!< 0x00008000 */
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */
+
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAEN_Pos              (0U)                                 
+#define OPAMP1_CSR_OPAEN_Msk              (0x1U << OPAMP1_CSR_OPAEN_Pos)       /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_OPALPM_Pos             (1U)                                 
+#define OPAMP1_CSR_OPALPM_Msk             (0x1U << OPAMP1_CSR_OPALPM_Pos)      /*!< 0x00000002 */
+#define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */
+
+#define OPAMP1_CSR_OPAMODE_Pos            (2U)                                 
+#define OPAMP1_CSR_OPAMODE_Msk            (0x3U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
+#define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */
+#define OPAMP1_CSR_OPAMODE_0              (0x1U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
+#define OPAMP1_CSR_OPAMODE_1              (0x2U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
+
+#define OPAMP1_CSR_PGAGAIN_Pos            (4U)                                 
+#define OPAMP1_CSR_PGAGAIN_Msk            (0x3U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
+#define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGAGAIN_0              (0x1U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
+#define OPAMP1_CSR_PGAGAIN_1              (0x2U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
+
+#define OPAMP1_CSR_VMSEL_Pos              (8U)                                 
+#define OPAMP1_CSR_VMSEL_Msk              (0x3U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000300 */
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                (0x1U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000100 */
+#define OPAMP1_CSR_VMSEL_1                (0x2U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000200 */
+
+#define OPAMP1_CSR_VPSEL_Pos              (10U)                                
+#define OPAMP1_CSR_VPSEL_Msk              (0x1U << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000400 */
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP1_CSR_CALON_Pos              (12U)                                
+#define OPAMP1_CSR_CALON_Msk              (0x1U << OPAMP1_CSR_CALON_Pos)       /*!< 0x00001000 */
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL_Pos             (13U)                                
+#define OPAMP1_CSR_CALSEL_Msk             (0x1U << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP1_CSR_USERTRIM_Pos           (14U)                                
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1U << OPAMP1_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP1_CSR_CALOUT_Pos             (15U)                                
+#define OPAMP1_CSR_CALOUT_Msk             (0x1U << OPAMP1_CSR_CALOUT_Pos)      /*!< 0x00008000 */
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
+
+#define OPAMP1_CSR_OPARANGE_Pos           (31U)                                
+#define OPAMP1_CSR_OPARANGE_Msk           (0x1U << OPAMP1_CSR_OPARANGE_Pos)    /*!< 0x80000000 */
+#define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
+
+/*********************  Bit definition for OPAMP2_CSR register  ***************/
+#define OPAMP2_CSR_OPAEN_Pos              (0U)                                 
+#define OPAMP2_CSR_OPAEN_Msk              (0x1U << OPAMP2_CSR_OPAEN_Pos)       /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_OPALPM_Pos             (1U)                                 
+#define OPAMP2_CSR_OPALPM_Msk             (0x1U << OPAMP2_CSR_OPALPM_Pos)      /*!< 0x00000002 */
+#define OPAMP2_CSR_OPALPM                 OPAMP2_CSR_OPALPM_Msk                /*!< Operational amplifier2 Low Power Mode */
+
+#define OPAMP2_CSR_OPAMODE_Pos            (2U)                                 
+#define OPAMP2_CSR_OPAMODE_Msk            (0x3U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
+#define OPAMP2_CSR_OPAMODE                OPAMP2_CSR_OPAMODE_Msk               /*!< Operational amplifier2 PGA mode */
+#define OPAMP2_CSR_OPAMODE_0              (0x1U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
+#define OPAMP2_CSR_OPAMODE_1              (0x2U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
+
+#define OPAMP2_CSR_PGAGAIN_Pos            (4U)                                 
+#define OPAMP2_CSR_PGAGAIN_Msk            (0x3U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
+#define OPAMP2_CSR_PGAGAIN                OPAMP2_CSR_PGAGAIN_Msk               /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGAGAIN_0              (0x1U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
+#define OPAMP2_CSR_PGAGAIN_1              (0x2U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
+
+#define OPAMP2_CSR_VMSEL_Pos              (8U)                                 
+#define OPAMP2_CSR_VMSEL_Msk              (0x3U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000300 */
+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0                (0x1U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000100 */
+#define OPAMP2_CSR_VMSEL_1                (0x2U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000200 */
+
+#define OPAMP2_CSR_VPSEL_Pos              (10U)                                
+#define OPAMP2_CSR_VPSEL_Msk              (0x1U << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000400 */
+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP2_CSR_CALON_Pos              (12U)                                
+#define OPAMP2_CSR_CALON_Msk              (0x1U << OPAMP2_CSR_CALON_Pos)       /*!< 0x00001000 */
+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL_Pos             (13U)                                
+#define OPAMP2_CSR_CALSEL_Msk             (0x1U << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP2_CSR_USERTRIM_Pos           (14U)                                
+#define OPAMP2_CSR_USERTRIM_Msk           (0x1U << OPAMP2_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP2_CSR_CALOUT_Pos             (15U)                                
+#define OPAMP2_CSR_CALOUT_Msk             (0x1U << OPAMP2_CSR_CALOUT_Pos)      /*!< 0x00008000 */
+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)                                  
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos)  /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)                                  
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos)  /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_OTR register  ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)                                 
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)                                 
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_OTR register  ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)                                 
+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)                                 
+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP_LPOTR register  ****************/
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_LPOTR register  ****************/
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_LPOTR register  ****************/
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                 
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_LPOTR_TRIMLPOFFSETN        OPAMP2_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                 
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP        OPAMP2_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Touch Sensing Controller (TSC)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TSC_CR register  *********************/
+#define TSC_CR_TSCE_Pos                     (0U)                               
+#define TSC_CR_TSCE_Msk                     (0x1U << TSC_CR_TSCE_Pos)          /*!< 0x00000001 */
+#define TSC_CR_TSCE                         TSC_CR_TSCE_Msk                    /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos                    (1U)                               
+#define TSC_CR_START_Msk                    (0x1U << TSC_CR_START_Pos)         /*!< 0x00000002 */
+#define TSC_CR_START                        TSC_CR_START_Msk                   /*!<Start acquisition */
+#define TSC_CR_AM_Pos                       (2U)                               
+#define TSC_CR_AM_Msk                       (0x1U << TSC_CR_AM_Pos)            /*!< 0x00000004 */
+#define TSC_CR_AM                           TSC_CR_AM_Msk                      /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos                  (3U)                               
+#define TSC_CR_SYNCPOL_Msk                  (0x1U << TSC_CR_SYNCPOL_Pos)       /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL                      TSC_CR_SYNCPOL_Msk                 /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos                    (4U)                               
+#define TSC_CR_IODEF_Msk                    (0x1U << TSC_CR_IODEF_Pos)         /*!< 0x00000010 */
+#define TSC_CR_IODEF                        TSC_CR_IODEF_Msk                   /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos                      (5U)                               
+#define TSC_CR_MCV_Msk                      (0x7U << TSC_CR_MCV_Pos)           /*!< 0x000000E0 */
+#define TSC_CR_MCV                          TSC_CR_MCV_Msk                     /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0                        (0x1U << TSC_CR_MCV_Pos)           /*!< 0x00000020 */
+#define TSC_CR_MCV_1                        (0x2U << TSC_CR_MCV_Pos)           /*!< 0x00000040 */
+#define TSC_CR_MCV_2                        (0x4U << TSC_CR_MCV_Pos)           /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos                    (12U)                              
+#define TSC_CR_PGPSC_Msk                    (0x7U << TSC_CR_PGPSC_Pos)         /*!< 0x00007000 */
+#define TSC_CR_PGPSC                        TSC_CR_PGPSC_Msk                   /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0                      (0x1U << TSC_CR_PGPSC_Pos)         /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1                      (0x2U << TSC_CR_PGPSC_Pos)         /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2                      (0x4U << TSC_CR_PGPSC_Pos)         /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos                    (15U)                              
+#define TSC_CR_SSPSC_Msk                    (0x1U << TSC_CR_SSPSC_Pos)         /*!< 0x00008000 */
+#define TSC_CR_SSPSC                        TSC_CR_SSPSC_Msk                   /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos                      (16U)                              
+#define TSC_CR_SSE_Msk                      (0x1U << TSC_CR_SSE_Pos)           /*!< 0x00010000 */
+#define TSC_CR_SSE                          TSC_CR_SSE_Msk                     /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos                      (17U)                              
+#define TSC_CR_SSD_Msk                      (0x7FU << TSC_CR_SSD_Pos)          /*!< 0x00FE0000 */
+#define TSC_CR_SSD                          TSC_CR_SSD_Msk                     /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0                        (0x01U << TSC_CR_SSD_Pos)          /*!< 0x00020000 */
+#define TSC_CR_SSD_1                        (0x02U << TSC_CR_SSD_Pos)          /*!< 0x00040000 */
+#define TSC_CR_SSD_2                        (0x04U << TSC_CR_SSD_Pos)          /*!< 0x00080000 */
+#define TSC_CR_SSD_3                        (0x08U << TSC_CR_SSD_Pos)          /*!< 0x00100000 */
+#define TSC_CR_SSD_4                        (0x10U << TSC_CR_SSD_Pos)          /*!< 0x00200000 */
+#define TSC_CR_SSD_5                        (0x20U << TSC_CR_SSD_Pos)          /*!< 0x00400000 */
+#define TSC_CR_SSD_6                        (0x40U << TSC_CR_SSD_Pos)          /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos                     (24U)                              
+#define TSC_CR_CTPL_Msk                     (0xFU << TSC_CR_CTPL_Pos)          /*!< 0x0F000000 */
+#define TSC_CR_CTPL                         TSC_CR_CTPL_Msk                    /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0                       (0x1U << TSC_CR_CTPL_Pos)          /*!< 0x01000000 */
+#define TSC_CR_CTPL_1                       (0x2U << TSC_CR_CTPL_Pos)          /*!< 0x02000000 */
+#define TSC_CR_CTPL_2                       (0x4U << TSC_CR_CTPL_Pos)          /*!< 0x04000000 */
+#define TSC_CR_CTPL_3                       (0x8U << TSC_CR_CTPL_Pos)          /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos                     (28U)                              
+#define TSC_CR_CTPH_Msk                     (0xFU << TSC_CR_CTPH_Pos)          /*!< 0xF0000000 */
+#define TSC_CR_CTPH                         TSC_CR_CTPH_Msk                    /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0                       (0x1U << TSC_CR_CTPH_Pos)          /*!< 0x10000000 */
+#define TSC_CR_CTPH_1                       (0x2U << TSC_CR_CTPH_Pos)          /*!< 0x20000000 */
+#define TSC_CR_CTPH_2                       (0x4U << TSC_CR_CTPH_Pos)          /*!< 0x40000000 */
+#define TSC_CR_CTPH_3                       (0x8U << TSC_CR_CTPH_Pos)          /*!< 0x80000000 */
+
+/*******************  Bit definition for TSC_IER register  ********************/
+#define TSC_IER_EOAIE_Pos                   (0U)                               
+#define TSC_IER_EOAIE_Msk                   (0x1U << TSC_IER_EOAIE_Pos)        /*!< 0x00000001 */
+#define TSC_IER_EOAIE                       TSC_IER_EOAIE_Msk                  /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos                   (1U)                               
+#define TSC_IER_MCEIE_Msk                   (0x1U << TSC_IER_MCEIE_Pos)        /*!< 0x00000002 */
+#define TSC_IER_MCEIE                       TSC_IER_MCEIE_Msk                  /*!<Max count error interrupt enable */
+
+/*******************  Bit definition for TSC_ICR register  ********************/
+#define TSC_ICR_EOAIC_Pos                   (0U)                               
+#define TSC_ICR_EOAIC_Msk                   (0x1U << TSC_ICR_EOAIC_Pos)        /*!< 0x00000001 */
+#define TSC_ICR_EOAIC                       TSC_ICR_EOAIC_Msk                  /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos                   (1U)                               
+#define TSC_ICR_MCEIC_Msk                   (0x1U << TSC_ICR_MCEIC_Pos)        /*!< 0x00000002 */
+#define TSC_ICR_MCEIC                       TSC_ICR_MCEIC_Msk                  /*!<Max count error interrupt clear */
+
+/*******************  Bit definition for TSC_ISR register  ********************/
+#define TSC_ISR_EOAF_Pos                    (0U)                               
+#define TSC_ISR_EOAF_Msk                    (0x1U << TSC_ISR_EOAF_Pos)         /*!< 0x00000001 */
+#define TSC_ISR_EOAF                        TSC_ISR_EOAF_Msk                   /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos                    (1U)                               
+#define TSC_ISR_MCEF_Msk                    (0x1U << TSC_ISR_MCEF_Pos)         /*!< 0x00000002 */
+#define TSC_ISR_MCEF                        TSC_ISR_MCEF_Msk                   /*!<Max count error flag */
+
+/*******************  Bit definition for TSC_IOHCR register  ******************/
+#define TSC_IOHCR_G1_IO1_Pos                (0U)                               
+#define TSC_IOHCR_G1_IO1_Msk                (0x1U << TSC_IOHCR_G1_IO1_Pos)     /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1                    TSC_IOHCR_G1_IO1_Msk               /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos                (1U)                               
+#define TSC_IOHCR_G1_IO2_Msk                (0x1U << TSC_IOHCR_G1_IO2_Pos)     /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2                    TSC_IOHCR_G1_IO2_Msk               /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos                (2U)                               
+#define TSC_IOHCR_G1_IO3_Msk                (0x1U << TSC_IOHCR_G1_IO3_Pos)     /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3                    TSC_IOHCR_G1_IO3_Msk               /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos                (3U)                               
+#define TSC_IOHCR_G1_IO4_Msk                (0x1U << TSC_IOHCR_G1_IO4_Pos)     /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4                    TSC_IOHCR_G1_IO4_Msk               /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos                (4U)                               
+#define TSC_IOHCR_G2_IO1_Msk                (0x1U << TSC_IOHCR_G2_IO1_Pos)     /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1                    TSC_IOHCR_G2_IO1_Msk               /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos                (5U)                               
+#define TSC_IOHCR_G2_IO2_Msk                (0x1U << TSC_IOHCR_G2_IO2_Pos)     /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2                    TSC_IOHCR_G2_IO2_Msk               /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos                (6U)                               
+#define TSC_IOHCR_G2_IO3_Msk                (0x1U << TSC_IOHCR_G2_IO3_Pos)     /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3                    TSC_IOHCR_G2_IO3_Msk               /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos                (7U)                               
+#define TSC_IOHCR_G2_IO4_Msk                (0x1U << TSC_IOHCR_G2_IO4_Pos)     /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4                    TSC_IOHCR_G2_IO4_Msk               /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos                (8U)                               
+#define TSC_IOHCR_G3_IO1_Msk                (0x1U << TSC_IOHCR_G3_IO1_Pos)     /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1                    TSC_IOHCR_G3_IO1_Msk               /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos                (9U)                               
+#define TSC_IOHCR_G3_IO2_Msk                (0x1U << TSC_IOHCR_G3_IO2_Pos)     /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2                    TSC_IOHCR_G3_IO2_Msk               /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos                (10U)                              
+#define TSC_IOHCR_G3_IO3_Msk                (0x1U << TSC_IOHCR_G3_IO3_Pos)     /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3                    TSC_IOHCR_G3_IO3_Msk               /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos                (11U)                              
+#define TSC_IOHCR_G3_IO4_Msk                (0x1U << TSC_IOHCR_G3_IO4_Pos)     /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4                    TSC_IOHCR_G3_IO4_Msk               /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos                (12U)                              
+#define TSC_IOHCR_G4_IO1_Msk                (0x1U << TSC_IOHCR_G4_IO1_Pos)     /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1                    TSC_IOHCR_G4_IO1_Msk               /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos                (13U)                              
+#define TSC_IOHCR_G4_IO2_Msk                (0x1U << TSC_IOHCR_G4_IO2_Pos)     /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2                    TSC_IOHCR_G4_IO2_Msk               /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos                (14U)                              
+#define TSC_IOHCR_G4_IO3_Msk                (0x1U << TSC_IOHCR_G4_IO3_Pos)     /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3                    TSC_IOHCR_G4_IO3_Msk               /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos                (15U)                              
+#define TSC_IOHCR_G4_IO4_Msk                (0x1U << TSC_IOHCR_G4_IO4_Pos)     /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4                    TSC_IOHCR_G4_IO4_Msk               /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos                (16U)                              
+#define TSC_IOHCR_G5_IO1_Msk                (0x1U << TSC_IOHCR_G5_IO1_Pos)     /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1                    TSC_IOHCR_G5_IO1_Msk               /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos                (17U)                              
+#define TSC_IOHCR_G5_IO2_Msk                (0x1U << TSC_IOHCR_G5_IO2_Pos)     /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2                    TSC_IOHCR_G5_IO2_Msk               /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos                (18U)                              
+#define TSC_IOHCR_G5_IO3_Msk                (0x1U << TSC_IOHCR_G5_IO3_Pos)     /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3                    TSC_IOHCR_G5_IO3_Msk               /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos                (19U)                              
+#define TSC_IOHCR_G5_IO4_Msk                (0x1U << TSC_IOHCR_G5_IO4_Pos)     /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4                    TSC_IOHCR_G5_IO4_Msk               /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos                (20U)                              
+#define TSC_IOHCR_G6_IO1_Msk                (0x1U << TSC_IOHCR_G6_IO1_Pos)     /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1                    TSC_IOHCR_G6_IO1_Msk               /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos                (21U)                              
+#define TSC_IOHCR_G6_IO2_Msk                (0x1U << TSC_IOHCR_G6_IO2_Pos)     /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2                    TSC_IOHCR_G6_IO2_Msk               /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos                (22U)                              
+#define TSC_IOHCR_G6_IO3_Msk                (0x1U << TSC_IOHCR_G6_IO3_Pos)     /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3                    TSC_IOHCR_G6_IO3_Msk               /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos                (23U)                              
+#define TSC_IOHCR_G6_IO4_Msk                (0x1U << TSC_IOHCR_G6_IO4_Pos)     /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4                    TSC_IOHCR_G6_IO4_Msk               /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos                (24U)                              
+#define TSC_IOHCR_G7_IO1_Msk                (0x1U << TSC_IOHCR_G7_IO1_Pos)     /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1                    TSC_IOHCR_G7_IO1_Msk               /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos                (25U)                              
+#define TSC_IOHCR_G7_IO2_Msk                (0x1U << TSC_IOHCR_G7_IO2_Pos)     /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2                    TSC_IOHCR_G7_IO2_Msk               /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos                (26U)                              
+#define TSC_IOHCR_G7_IO3_Msk                (0x1U << TSC_IOHCR_G7_IO3_Pos)     /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3                    TSC_IOHCR_G7_IO3_Msk               /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos                (27U)                              
+#define TSC_IOHCR_G7_IO4_Msk                (0x1U << TSC_IOHCR_G7_IO4_Pos)     /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4                    TSC_IOHCR_G7_IO4_Msk               /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos                (28U)                              
+#define TSC_IOHCR_G8_IO1_Msk                (0x1U << TSC_IOHCR_G8_IO1_Pos)     /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1                    TSC_IOHCR_G8_IO1_Msk               /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos                (29U)                              
+#define TSC_IOHCR_G8_IO2_Msk                (0x1U << TSC_IOHCR_G8_IO2_Pos)     /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2                    TSC_IOHCR_G8_IO2_Msk               /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos                (30U)                              
+#define TSC_IOHCR_G8_IO3_Msk                (0x1U << TSC_IOHCR_G8_IO3_Pos)     /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3                    TSC_IOHCR_G8_IO3_Msk               /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos                (31U)                              
+#define TSC_IOHCR_G8_IO4_Msk                (0x1U << TSC_IOHCR_G8_IO4_Pos)     /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4                    TSC_IOHCR_G8_IO4_Msk               /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/*******************  Bit definition for TSC_IOASCR register  *****************/
+#define TSC_IOASCR_G1_IO1_Pos               (0U)                               
+#define TSC_IOASCR_G1_IO1_Msk               (0x1U << TSC_IOASCR_G1_IO1_Pos)    /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1                   TSC_IOASCR_G1_IO1_Msk              /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos               (1U)                               
+#define TSC_IOASCR_G1_IO2_Msk               (0x1U << TSC_IOASCR_G1_IO2_Pos)    /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2                   TSC_IOASCR_G1_IO2_Msk              /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos               (2U)                               
+#define TSC_IOASCR_G1_IO3_Msk               (0x1U << TSC_IOASCR_G1_IO3_Pos)    /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3                   TSC_IOASCR_G1_IO3_Msk              /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos               (3U)                               
+#define TSC_IOASCR_G1_IO4_Msk               (0x1U << TSC_IOASCR_G1_IO4_Pos)    /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4                   TSC_IOASCR_G1_IO4_Msk              /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos               (4U)                               
+#define TSC_IOASCR_G2_IO1_Msk               (0x1U << TSC_IOASCR_G2_IO1_Pos)    /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1                   TSC_IOASCR_G2_IO1_Msk              /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos               (5U)                               
+#define TSC_IOASCR_G2_IO2_Msk               (0x1U << TSC_IOASCR_G2_IO2_Pos)    /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2                   TSC_IOASCR_G2_IO2_Msk              /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos               (6U)                               
+#define TSC_IOASCR_G2_IO3_Msk               (0x1U << TSC_IOASCR_G2_IO3_Pos)    /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3                   TSC_IOASCR_G2_IO3_Msk              /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos               (7U)                               
+#define TSC_IOASCR_G2_IO4_Msk               (0x1U << TSC_IOASCR_G2_IO4_Pos)    /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4                   TSC_IOASCR_G2_IO4_Msk              /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos               (8U)                               
+#define TSC_IOASCR_G3_IO1_Msk               (0x1U << TSC_IOASCR_G3_IO1_Pos)    /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1                   TSC_IOASCR_G3_IO1_Msk              /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos               (9U)                               
+#define TSC_IOASCR_G3_IO2_Msk               (0x1U << TSC_IOASCR_G3_IO2_Pos)    /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2                   TSC_IOASCR_G3_IO2_Msk              /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos               (10U)                              
+#define TSC_IOASCR_G3_IO3_Msk               (0x1U << TSC_IOASCR_G3_IO3_Pos)    /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3                   TSC_IOASCR_G3_IO3_Msk              /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos               (11U)                              
+#define TSC_IOASCR_G3_IO4_Msk               (0x1U << TSC_IOASCR_G3_IO4_Pos)    /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4                   TSC_IOASCR_G3_IO4_Msk              /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos               (12U)                              
+#define TSC_IOASCR_G4_IO1_Msk               (0x1U << TSC_IOASCR_G4_IO1_Pos)    /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1                   TSC_IOASCR_G4_IO1_Msk              /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos               (13U)                              
+#define TSC_IOASCR_G4_IO2_Msk               (0x1U << TSC_IOASCR_G4_IO2_Pos)    /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2                   TSC_IOASCR_G4_IO2_Msk              /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos               (14U)                              
+#define TSC_IOASCR_G4_IO3_Msk               (0x1U << TSC_IOASCR_G4_IO3_Pos)    /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3                   TSC_IOASCR_G4_IO3_Msk              /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos               (15U)                              
+#define TSC_IOASCR_G4_IO4_Msk               (0x1U << TSC_IOASCR_G4_IO4_Pos)    /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4                   TSC_IOASCR_G4_IO4_Msk              /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos               (16U)                              
+#define TSC_IOASCR_G5_IO1_Msk               (0x1U << TSC_IOASCR_G5_IO1_Pos)    /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1                   TSC_IOASCR_G5_IO1_Msk              /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos               (17U)                              
+#define TSC_IOASCR_G5_IO2_Msk               (0x1U << TSC_IOASCR_G5_IO2_Pos)    /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2                   TSC_IOASCR_G5_IO2_Msk              /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos               (18U)                              
+#define TSC_IOASCR_G5_IO3_Msk               (0x1U << TSC_IOASCR_G5_IO3_Pos)    /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3                   TSC_IOASCR_G5_IO3_Msk              /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos               (19U)                              
+#define TSC_IOASCR_G5_IO4_Msk               (0x1U << TSC_IOASCR_G5_IO4_Pos)    /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4                   TSC_IOASCR_G5_IO4_Msk              /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos               (20U)                              
+#define TSC_IOASCR_G6_IO1_Msk               (0x1U << TSC_IOASCR_G6_IO1_Pos)    /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1                   TSC_IOASCR_G6_IO1_Msk              /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos               (21U)                              
+#define TSC_IOASCR_G6_IO2_Msk               (0x1U << TSC_IOASCR_G6_IO2_Pos)    /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2                   TSC_IOASCR_G6_IO2_Msk              /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos               (22U)                              
+#define TSC_IOASCR_G6_IO3_Msk               (0x1U << TSC_IOASCR_G6_IO3_Pos)    /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3                   TSC_IOASCR_G6_IO3_Msk              /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos               (23U)                              
+#define TSC_IOASCR_G6_IO4_Msk               (0x1U << TSC_IOASCR_G6_IO4_Pos)    /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4                   TSC_IOASCR_G6_IO4_Msk              /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos               (24U)                              
+#define TSC_IOASCR_G7_IO1_Msk               (0x1U << TSC_IOASCR_G7_IO1_Pos)    /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1                   TSC_IOASCR_G7_IO1_Msk              /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos               (25U)                              
+#define TSC_IOASCR_G7_IO2_Msk               (0x1U << TSC_IOASCR_G7_IO2_Pos)    /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2                   TSC_IOASCR_G7_IO2_Msk              /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos               (26U)                              
+#define TSC_IOASCR_G7_IO3_Msk               (0x1U << TSC_IOASCR_G7_IO3_Pos)    /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3                   TSC_IOASCR_G7_IO3_Msk              /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos               (27U)                              
+#define TSC_IOASCR_G7_IO4_Msk               (0x1U << TSC_IOASCR_G7_IO4_Pos)    /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4                   TSC_IOASCR_G7_IO4_Msk              /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos               (28U)                              
+#define TSC_IOASCR_G8_IO1_Msk               (0x1U << TSC_IOASCR_G8_IO1_Pos)    /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1                   TSC_IOASCR_G8_IO1_Msk              /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos               (29U)                              
+#define TSC_IOASCR_G8_IO2_Msk               (0x1U << TSC_IOASCR_G8_IO2_Pos)    /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2                   TSC_IOASCR_G8_IO2_Msk              /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos               (30U)                              
+#define TSC_IOASCR_G8_IO3_Msk               (0x1U << TSC_IOASCR_G8_IO3_Pos)    /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3                   TSC_IOASCR_G8_IO3_Msk              /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos               (31U)                              
+#define TSC_IOASCR_G8_IO4_Msk               (0x1U << TSC_IOASCR_G8_IO4_Pos)    /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4                   TSC_IOASCR_G8_IO4_Msk              /*!<GROUP8_IO4 analog switch enable */
+
+/*******************  Bit definition for TSC_IOSCR register  ******************/
+#define TSC_IOSCR_G1_IO1_Pos                (0U)                               
+#define TSC_IOSCR_G1_IO1_Msk                (0x1U << TSC_IOSCR_G1_IO1_Pos)     /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1                    TSC_IOSCR_G1_IO1_Msk               /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos                (1U)                               
+#define TSC_IOSCR_G1_IO2_Msk                (0x1U << TSC_IOSCR_G1_IO2_Pos)     /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2                    TSC_IOSCR_G1_IO2_Msk               /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos                (2U)                               
+#define TSC_IOSCR_G1_IO3_Msk                (0x1U << TSC_IOSCR_G1_IO3_Pos)     /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3                    TSC_IOSCR_G1_IO3_Msk               /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos                (3U)                               
+#define TSC_IOSCR_G1_IO4_Msk                (0x1U << TSC_IOSCR_G1_IO4_Pos)     /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4                    TSC_IOSCR_G1_IO4_Msk               /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos                (4U)                               
+#define TSC_IOSCR_G2_IO1_Msk                (0x1U << TSC_IOSCR_G2_IO1_Pos)     /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1                    TSC_IOSCR_G2_IO1_Msk               /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos                (5U)                               
+#define TSC_IOSCR_G2_IO2_Msk                (0x1U << TSC_IOSCR_G2_IO2_Pos)     /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2                    TSC_IOSCR_G2_IO2_Msk               /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos                (6U)                               
+#define TSC_IOSCR_G2_IO3_Msk                (0x1U << TSC_IOSCR_G2_IO3_Pos)     /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3                    TSC_IOSCR_G2_IO3_Msk               /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos                (7U)                               
+#define TSC_IOSCR_G2_IO4_Msk                (0x1U << TSC_IOSCR_G2_IO4_Pos)     /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4                    TSC_IOSCR_G2_IO4_Msk               /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos                (8U)                               
+#define TSC_IOSCR_G3_IO1_Msk                (0x1U << TSC_IOSCR_G3_IO1_Pos)     /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1                    TSC_IOSCR_G3_IO1_Msk               /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos                (9U)                               
+#define TSC_IOSCR_G3_IO2_Msk                (0x1U << TSC_IOSCR_G3_IO2_Pos)     /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2                    TSC_IOSCR_G3_IO2_Msk               /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos                (10U)                              
+#define TSC_IOSCR_G3_IO3_Msk                (0x1U << TSC_IOSCR_G3_IO3_Pos)     /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3                    TSC_IOSCR_G3_IO3_Msk               /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos                (11U)                              
+#define TSC_IOSCR_G3_IO4_Msk                (0x1U << TSC_IOSCR_G3_IO4_Pos)     /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4                    TSC_IOSCR_G3_IO4_Msk               /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos                (12U)                              
+#define TSC_IOSCR_G4_IO1_Msk                (0x1U << TSC_IOSCR_G4_IO1_Pos)     /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1                    TSC_IOSCR_G4_IO1_Msk               /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos                (13U)                              
+#define TSC_IOSCR_G4_IO2_Msk                (0x1U << TSC_IOSCR_G4_IO2_Pos)     /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2                    TSC_IOSCR_G4_IO2_Msk               /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos                (14U)                              
+#define TSC_IOSCR_G4_IO3_Msk                (0x1U << TSC_IOSCR_G4_IO3_Pos)     /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3                    TSC_IOSCR_G4_IO3_Msk               /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos                (15U)                              
+#define TSC_IOSCR_G4_IO4_Msk                (0x1U << TSC_IOSCR_G4_IO4_Pos)     /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4                    TSC_IOSCR_G4_IO4_Msk               /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos                (16U)                              
+#define TSC_IOSCR_G5_IO1_Msk                (0x1U << TSC_IOSCR_G5_IO1_Pos)     /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1                    TSC_IOSCR_G5_IO1_Msk               /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos                (17U)                              
+#define TSC_IOSCR_G5_IO2_Msk                (0x1U << TSC_IOSCR_G5_IO2_Pos)     /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2                    TSC_IOSCR_G5_IO2_Msk               /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos                (18U)                              
+#define TSC_IOSCR_G5_IO3_Msk                (0x1U << TSC_IOSCR_G5_IO3_Pos)     /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3                    TSC_IOSCR_G5_IO3_Msk               /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos                (19U)                              
+#define TSC_IOSCR_G5_IO4_Msk                (0x1U << TSC_IOSCR_G5_IO4_Pos)     /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4                    TSC_IOSCR_G5_IO4_Msk               /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos                (20U)                              
+#define TSC_IOSCR_G6_IO1_Msk                (0x1U << TSC_IOSCR_G6_IO1_Pos)     /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1                    TSC_IOSCR_G6_IO1_Msk               /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos                (21U)                              
+#define TSC_IOSCR_G6_IO2_Msk                (0x1U << TSC_IOSCR_G6_IO2_Pos)     /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2                    TSC_IOSCR_G6_IO2_Msk               /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos                (22U)                              
+#define TSC_IOSCR_G6_IO3_Msk                (0x1U << TSC_IOSCR_G6_IO3_Pos)     /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3                    TSC_IOSCR_G6_IO3_Msk               /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos                (23U)                              
+#define TSC_IOSCR_G6_IO4_Msk                (0x1U << TSC_IOSCR_G6_IO4_Pos)     /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4                    TSC_IOSCR_G6_IO4_Msk               /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos                (24U)                              
+#define TSC_IOSCR_G7_IO1_Msk                (0x1U << TSC_IOSCR_G7_IO1_Pos)     /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1                    TSC_IOSCR_G7_IO1_Msk               /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos                (25U)                              
+#define TSC_IOSCR_G7_IO2_Msk                (0x1U << TSC_IOSCR_G7_IO2_Pos)     /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2                    TSC_IOSCR_G7_IO2_Msk               /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos                (26U)                              
+#define TSC_IOSCR_G7_IO3_Msk                (0x1U << TSC_IOSCR_G7_IO3_Pos)     /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3                    TSC_IOSCR_G7_IO3_Msk               /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos                (27U)                              
+#define TSC_IOSCR_G7_IO4_Msk                (0x1U << TSC_IOSCR_G7_IO4_Pos)     /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4                    TSC_IOSCR_G7_IO4_Msk               /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos                (28U)                              
+#define TSC_IOSCR_G8_IO1_Msk                (0x1U << TSC_IOSCR_G8_IO1_Pos)     /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1                    TSC_IOSCR_G8_IO1_Msk               /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos                (29U)                              
+#define TSC_IOSCR_G8_IO2_Msk                (0x1U << TSC_IOSCR_G8_IO2_Pos)     /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2                    TSC_IOSCR_G8_IO2_Msk               /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos                (30U)                              
+#define TSC_IOSCR_G8_IO3_Msk                (0x1U << TSC_IOSCR_G8_IO3_Pos)     /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3                    TSC_IOSCR_G8_IO3_Msk               /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos                (31U)                              
+#define TSC_IOSCR_G8_IO4_Msk                (0x1U << TSC_IOSCR_G8_IO4_Pos)     /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4                    TSC_IOSCR_G8_IO4_Msk               /*!<GROUP8_IO4 sampling mode */
+
+/*******************  Bit definition for TSC_IOCCR register  ******************/
+#define TSC_IOCCR_G1_IO1_Pos                (0U)                               
+#define TSC_IOCCR_G1_IO1_Msk                (0x1U << TSC_IOCCR_G1_IO1_Pos)     /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1                    TSC_IOCCR_G1_IO1_Msk               /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos                (1U)                               
+#define TSC_IOCCR_G1_IO2_Msk                (0x1U << TSC_IOCCR_G1_IO2_Pos)     /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2                    TSC_IOCCR_G1_IO2_Msk               /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos                (2U)                               
+#define TSC_IOCCR_G1_IO3_Msk                (0x1U << TSC_IOCCR_G1_IO3_Pos)     /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3                    TSC_IOCCR_G1_IO3_Msk               /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos                (3U)                               
+#define TSC_IOCCR_G1_IO4_Msk                (0x1U << TSC_IOCCR_G1_IO4_Pos)     /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4                    TSC_IOCCR_G1_IO4_Msk               /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos                (4U)                               
+#define TSC_IOCCR_G2_IO1_Msk                (0x1U << TSC_IOCCR_G2_IO1_Pos)     /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1                    TSC_IOCCR_G2_IO1_Msk               /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos                (5U)                               
+#define TSC_IOCCR_G2_IO2_Msk                (0x1U << TSC_IOCCR_G2_IO2_Pos)     /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2                    TSC_IOCCR_G2_IO2_Msk               /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos                (6U)                               
+#define TSC_IOCCR_G2_IO3_Msk                (0x1U << TSC_IOCCR_G2_IO3_Pos)     /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3                    TSC_IOCCR_G2_IO3_Msk               /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos                (7U)                               
+#define TSC_IOCCR_G2_IO4_Msk                (0x1U << TSC_IOCCR_G2_IO4_Pos)     /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4                    TSC_IOCCR_G2_IO4_Msk               /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos                (8U)                               
+#define TSC_IOCCR_G3_IO1_Msk                (0x1U << TSC_IOCCR_G3_IO1_Pos)     /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1                    TSC_IOCCR_G3_IO1_Msk               /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos                (9U)                               
+#define TSC_IOCCR_G3_IO2_Msk                (0x1U << TSC_IOCCR_G3_IO2_Pos)     /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2                    TSC_IOCCR_G3_IO2_Msk               /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos                (10U)                              
+#define TSC_IOCCR_G3_IO3_Msk                (0x1U << TSC_IOCCR_G3_IO3_Pos)     /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3                    TSC_IOCCR_G3_IO3_Msk               /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos                (11U)                              
+#define TSC_IOCCR_G3_IO4_Msk                (0x1U << TSC_IOCCR_G3_IO4_Pos)     /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4                    TSC_IOCCR_G3_IO4_Msk               /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos                (12U)                              
+#define TSC_IOCCR_G4_IO1_Msk                (0x1U << TSC_IOCCR_G4_IO1_Pos)     /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1                    TSC_IOCCR_G4_IO1_Msk               /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos                (13U)                              
+#define TSC_IOCCR_G4_IO2_Msk                (0x1U << TSC_IOCCR_G4_IO2_Pos)     /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2                    TSC_IOCCR_G4_IO2_Msk               /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos                (14U)                              
+#define TSC_IOCCR_G4_IO3_Msk                (0x1U << TSC_IOCCR_G4_IO3_Pos)     /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3                    TSC_IOCCR_G4_IO3_Msk               /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos                (15U)                              
+#define TSC_IOCCR_G4_IO4_Msk                (0x1U << TSC_IOCCR_G4_IO4_Pos)     /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4                    TSC_IOCCR_G4_IO4_Msk               /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos                (16U)                              
+#define TSC_IOCCR_G5_IO1_Msk                (0x1U << TSC_IOCCR_G5_IO1_Pos)     /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1                    TSC_IOCCR_G5_IO1_Msk               /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos                (17U)                              
+#define TSC_IOCCR_G5_IO2_Msk                (0x1U << TSC_IOCCR_G5_IO2_Pos)     /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2                    TSC_IOCCR_G5_IO2_Msk               /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos                (18U)                              
+#define TSC_IOCCR_G5_IO3_Msk                (0x1U << TSC_IOCCR_G5_IO3_Pos)     /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3                    TSC_IOCCR_G5_IO3_Msk               /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos                (19U)                              
+#define TSC_IOCCR_G5_IO4_Msk                (0x1U << TSC_IOCCR_G5_IO4_Pos)     /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4                    TSC_IOCCR_G5_IO4_Msk               /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos                (20U)                              
+#define TSC_IOCCR_G6_IO1_Msk                (0x1U << TSC_IOCCR_G6_IO1_Pos)     /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1                    TSC_IOCCR_G6_IO1_Msk               /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos                (21U)                              
+#define TSC_IOCCR_G6_IO2_Msk                (0x1U << TSC_IOCCR_G6_IO2_Pos)     /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2                    TSC_IOCCR_G6_IO2_Msk               /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos                (22U)                              
+#define TSC_IOCCR_G6_IO3_Msk                (0x1U << TSC_IOCCR_G6_IO3_Pos)     /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3                    TSC_IOCCR_G6_IO3_Msk               /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos                (23U)                              
+#define TSC_IOCCR_G6_IO4_Msk                (0x1U << TSC_IOCCR_G6_IO4_Pos)     /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4                    TSC_IOCCR_G6_IO4_Msk               /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos                (24U)                              
+#define TSC_IOCCR_G7_IO1_Msk                (0x1U << TSC_IOCCR_G7_IO1_Pos)     /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1                    TSC_IOCCR_G7_IO1_Msk               /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos                (25U)                              
+#define TSC_IOCCR_G7_IO2_Msk                (0x1U << TSC_IOCCR_G7_IO2_Pos)     /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2                    TSC_IOCCR_G7_IO2_Msk               /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos                (26U)                              
+#define TSC_IOCCR_G7_IO3_Msk                (0x1U << TSC_IOCCR_G7_IO3_Pos)     /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3                    TSC_IOCCR_G7_IO3_Msk               /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos                (27U)                              
+#define TSC_IOCCR_G7_IO4_Msk                (0x1U << TSC_IOCCR_G7_IO4_Pos)     /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4                    TSC_IOCCR_G7_IO4_Msk               /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos                (28U)                              
+#define TSC_IOCCR_G8_IO1_Msk                (0x1U << TSC_IOCCR_G8_IO1_Pos)     /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1                    TSC_IOCCR_G8_IO1_Msk               /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos                (29U)                              
+#define TSC_IOCCR_G8_IO2_Msk                (0x1U << TSC_IOCCR_G8_IO2_Pos)     /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2                    TSC_IOCCR_G8_IO2_Msk               /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos                (30U)                              
+#define TSC_IOCCR_G8_IO3_Msk                (0x1U << TSC_IOCCR_G8_IO3_Pos)     /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3                    TSC_IOCCR_G8_IO3_Msk               /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos                (31U)                              
+#define TSC_IOCCR_G8_IO4_Msk                (0x1U << TSC_IOCCR_G8_IO4_Pos)     /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4                    TSC_IOCCR_G8_IO4_Msk               /*!<GROUP8_IO4 channel mode */
+
+/*******************  Bit definition for TSC_IOGCSR register  *****************/
+#define TSC_IOGCSR_G1E_Pos                  (0U)                               
+#define TSC_IOGCSR_G1E_Msk                  (0x1U << TSC_IOGCSR_G1E_Pos)       /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E                      TSC_IOGCSR_G1E_Msk                 /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos                  (1U)                               
+#define TSC_IOGCSR_G2E_Msk                  (0x1U << TSC_IOGCSR_G2E_Pos)       /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E                      TSC_IOGCSR_G2E_Msk                 /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos                  (2U)                               
+#define TSC_IOGCSR_G3E_Msk                  (0x1U << TSC_IOGCSR_G3E_Pos)       /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E                      TSC_IOGCSR_G3E_Msk                 /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos                  (3U)                               
+#define TSC_IOGCSR_G4E_Msk                  (0x1U << TSC_IOGCSR_G4E_Pos)       /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E                      TSC_IOGCSR_G4E_Msk                 /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos                  (4U)                               
+#define TSC_IOGCSR_G5E_Msk                  (0x1U << TSC_IOGCSR_G5E_Pos)       /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E                      TSC_IOGCSR_G5E_Msk                 /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos                  (5U)                               
+#define TSC_IOGCSR_G6E_Msk                  (0x1U << TSC_IOGCSR_G6E_Pos)       /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E                      TSC_IOGCSR_G6E_Msk                 /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos                  (6U)                               
+#define TSC_IOGCSR_G7E_Msk                  (0x1U << TSC_IOGCSR_G7E_Pos)       /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E                      TSC_IOGCSR_G7E_Msk                 /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos                  (7U)                               
+#define TSC_IOGCSR_G8E_Msk                  (0x1U << TSC_IOGCSR_G8E_Pos)       /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E                      TSC_IOGCSR_G8E_Msk                 /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos                  (16U)                              
+#define TSC_IOGCSR_G1S_Msk                  (0x1U << TSC_IOGCSR_G1S_Pos)       /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S                      TSC_IOGCSR_G1S_Msk                 /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos                  (17U)                              
+#define TSC_IOGCSR_G2S_Msk                  (0x1U << TSC_IOGCSR_G2S_Pos)       /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S                      TSC_IOGCSR_G2S_Msk                 /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos                  (18U)                              
+#define TSC_IOGCSR_G3S_Msk                  (0x1U << TSC_IOGCSR_G3S_Pos)       /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S                      TSC_IOGCSR_G3S_Msk                 /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos                  (19U)                              
+#define TSC_IOGCSR_G4S_Msk                  (0x1U << TSC_IOGCSR_G4S_Pos)       /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S                      TSC_IOGCSR_G4S_Msk                 /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos                  (20U)                              
+#define TSC_IOGCSR_G5S_Msk                  (0x1U << TSC_IOGCSR_G5S_Pos)       /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S                      TSC_IOGCSR_G5S_Msk                 /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos                  (21U)                              
+#define TSC_IOGCSR_G6S_Msk                  (0x1U << TSC_IOGCSR_G6S_Pos)       /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S                      TSC_IOGCSR_G6S_Msk                 /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos                  (22U)                              
+#define TSC_IOGCSR_G7S_Msk                  (0x1U << TSC_IOGCSR_G7S_Pos)       /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S                      TSC_IOGCSR_G7S_Msk                 /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos                  (23U)                              
+#define TSC_IOGCSR_G8S_Msk                  (0x1U << TSC_IOGCSR_G8S_Pos)       /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S                      TSC_IOGCSR_G8S_Msk                 /*!<Analog IO GROUP8 status */
+
+/*******************  Bit definition for TSC_IOGXCR register  *****************/
+#define TSC_IOGXCR_CNT_Pos                  (0U)                               
+#define TSC_IOGXCR_CNT_Msk                  (0x3FFFU << TSC_IOGXCR_CNT_Pos)    /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT                      TSC_IOGXCR_CNT_Msk                 /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos                    (0U)                               
+#define USART_CR1_UE_Msk                    (0x1U << USART_CR1_UE_Pos)         /*!< 0x00000001 */
+#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
+#define USART_CR1_UESM_Pos                  (1U)                               
+#define USART_CR1_UESM_Msk                  (0x1U << USART_CR1_UESM_Pos)       /*!< 0x00000002 */
+#define USART_CR1_UESM                      USART_CR1_UESM_Msk                 /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos                    (2U)                               
+#define USART_CR1_RE_Msk                    (0x1U << USART_CR1_RE_Pos)         /*!< 0x00000004 */
+#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
+#define USART_CR1_TE_Pos                    (3U)                               
+#define USART_CR1_TE_Msk                    (0x1U << USART_CR1_TE_Pos)         /*!< 0x00000008 */
+#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos                (4U)                               
+#define USART_CR1_IDLEIE_Msk                (0x1U << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
+#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos                (5U)                               
+#define USART_CR1_RXNEIE_Msk                (0x1U << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
+#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos                  (6U)                               
+#define USART_CR1_TCIE_Msk                  (0x1U << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
+#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos                 (7U)                               
+#define USART_CR1_TXEIE_Msk                 (0x1U << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
+#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos                  (8U)                               
+#define USART_CR1_PEIE_Msk                  (0x1U << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
+#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos                    (9U)                               
+#define USART_CR1_PS_Msk                    (0x1U << USART_CR1_PS_Pos)         /*!< 0x00000200 */
+#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
+#define USART_CR1_PCE_Pos                   (10U)                              
+#define USART_CR1_PCE_Msk                   (0x1U << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
+#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos                  (11U)                              
+#define USART_CR1_WAKE_Msk                  (0x1U << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
+#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos                     (12U)                              
+#define USART_CR1_M_Msk                     (0x10001U << USART_CR1_M_Pos)      /*!< 0x10001000 */
+#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
+#define USART_CR1_M0_Pos                    (12U)                              
+#define USART_CR1_M0_Msk                    (0x1U << USART_CR1_M0_Pos)         /*!< 0x00001000 */
+#define USART_CR1_M0                        USART_CR1_M0_Msk                   /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos                   (13U)                              
+#define USART_CR1_MME_Msk                   (0x1U << USART_CR1_MME_Pos)        /*!< 0x00002000 */
+#define USART_CR1_MME                       USART_CR1_MME_Msk                  /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos                  (14U)                              
+#define USART_CR1_CMIE_Msk                  (0x1U << USART_CR1_CMIE_Pos)       /*!< 0x00004000 */
+#define USART_CR1_CMIE                      USART_CR1_CMIE_Msk                 /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos                 (15U)                              
+#define USART_CR1_OVER8_Msk                 (0x1U << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
+#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos                  (16U)                              
+#define USART_CR1_DEDT_Msk                  (0x1FU << USART_CR1_DEDT_Pos)      /*!< 0x001F0000 */
+#define USART_CR1_DEDT                      USART_CR1_DEDT_Msk                 /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0                    (0x01U << USART_CR1_DEDT_Pos)      /*!< 0x00010000 */
+#define USART_CR1_DEDT_1                    (0x02U << USART_CR1_DEDT_Pos)      /*!< 0x00020000 */
+#define USART_CR1_DEDT_2                    (0x04U << USART_CR1_DEDT_Pos)      /*!< 0x00040000 */
+#define USART_CR1_DEDT_3                    (0x08U << USART_CR1_DEDT_Pos)      /*!< 0x00080000 */
+#define USART_CR1_DEDT_4                    (0x10U << USART_CR1_DEDT_Pos)      /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos                  (21U)                              
+#define USART_CR1_DEAT_Msk                  (0x1FU << USART_CR1_DEAT_Pos)      /*!< 0x03E00000 */
+#define USART_CR1_DEAT                      USART_CR1_DEAT_Msk                 /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0                    (0x01U << USART_CR1_DEAT_Pos)      /*!< 0x00200000 */
+#define USART_CR1_DEAT_1                    (0x02U << USART_CR1_DEAT_Pos)      /*!< 0x00400000 */
+#define USART_CR1_DEAT_2                    (0x04U << USART_CR1_DEAT_Pos)      /*!< 0x00800000 */
+#define USART_CR1_DEAT_3                    (0x08U << USART_CR1_DEAT_Pos)      /*!< 0x01000000 */
+#define USART_CR1_DEAT_4                    (0x10U << USART_CR1_DEAT_Pos)      /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos                 (26U)                              
+#define USART_CR1_RTOIE_Msk                 (0x1U << USART_CR1_RTOIE_Pos)      /*!< 0x04000000 */
+#define USART_CR1_RTOIE                     USART_CR1_RTOIE_Msk                /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos                 (27U)                              
+#define USART_CR1_EOBIE_Msk                 (0x1U << USART_CR1_EOBIE_Pos)      /*!< 0x08000000 */
+#define USART_CR1_EOBIE                     USART_CR1_EOBIE_Msk                /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos                    (28U)                              
+#define USART_CR1_M1_Msk                    (0x1U << USART_CR1_M1_Pos)         /*!< 0x10000000 */
+#define USART_CR1_M1                        USART_CR1_M1_Msk                   /*!< Word length - Bit 1 */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_ADDM7_Pos                 (4U)                               
+#define USART_CR2_ADDM7_Msk                 (0x1U << USART_CR2_ADDM7_Pos)      /*!< 0x00000010 */
+#define USART_CR2_ADDM7                     USART_CR2_ADDM7_Msk                /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos                  (5U)                               
+#define USART_CR2_LBDL_Msk                  (0x1U << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
+#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos                 (6U)                               
+#define USART_CR2_LBDIE_Msk                 (0x1U << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
+#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos                  (8U)                               
+#define USART_CR2_LBCL_Msk                  (0x1U << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
+#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos                  (9U)                               
+#define USART_CR2_CPHA_Msk                  (0x1U << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
+#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos                  (10U)                              
+#define USART_CR2_CPOL_Msk                  (0x1U << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
+#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos                 (11U)                              
+#define USART_CR2_CLKEN_Msk                 (0x1U << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
+#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
+#define USART_CR2_STOP_Pos                  (12U)                              
+#define USART_CR2_STOP_Msk                  (0x3U << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
+#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0                    (0x1U << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
+#define USART_CR2_STOP_1                    (0x2U << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos                 (14U)                              
+#define USART_CR2_LINEN_Msk                 (0x1U << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
+#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos                  (15U)                              
+#define USART_CR2_SWAP_Msk                  (0x1U << USART_CR2_SWAP_Pos)       /*!< 0x00008000 */
+#define USART_CR2_SWAP                      USART_CR2_SWAP_Msk                 /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos                 (16U)                              
+#define USART_CR2_RXINV_Msk                 (0x1U << USART_CR2_RXINV_Pos)      /*!< 0x00010000 */
+#define USART_CR2_RXINV                     USART_CR2_RXINV_Msk                /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos                 (17U)                              
+#define USART_CR2_TXINV_Msk                 (0x1U << USART_CR2_TXINV_Pos)      /*!< 0x00020000 */
+#define USART_CR2_TXINV                     USART_CR2_TXINV_Msk                /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos               (18U)                              
+#define USART_CR2_DATAINV_Msk               (0x1U << USART_CR2_DATAINV_Pos)    /*!< 0x00040000 */
+#define USART_CR2_DATAINV                   USART_CR2_DATAINV_Msk              /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos              (19U)                              
+#define USART_CR2_MSBFIRST_Msk              (0x1U << USART_CR2_MSBFIRST_Pos)   /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST                  USART_CR2_MSBFIRST_Msk             /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos                 (20U)                              
+#define USART_CR2_ABREN_Msk                 (0x1U << USART_CR2_ABREN_Pos)      /*!< 0x00100000 */
+#define USART_CR2_ABREN                     USART_CR2_ABREN_Msk                /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos               (21U)                              
+#define USART_CR2_ABRMODE_Msk               (0x3U << USART_CR2_ABRMODE_Pos)    /*!< 0x00600000 */
+#define USART_CR2_ABRMODE                   USART_CR2_ABRMODE_Msk              /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0                 (0x1U << USART_CR2_ABRMODE_Pos)    /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1                 (0x2U << USART_CR2_ABRMODE_Pos)    /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos                 (23U)                              
+#define USART_CR2_RTOEN_Msk                 (0x1U << USART_CR2_RTOEN_Pos)      /*!< 0x00800000 */
+#define USART_CR2_RTOEN                     USART_CR2_RTOEN_Msk                /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos                   (24U)                              
+#define USART_CR2_ADD_Msk                   (0xFFU << USART_CR2_ADD_Pos)       /*!< 0xFF000000 */
+#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos                   (0U)                               
+#define USART_CR3_EIE_Msk                   (0x1U << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
+#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos                  (1U)                               
+#define USART_CR3_IREN_Msk                  (0x1U << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
+#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos                  (2U)                               
+#define USART_CR3_IRLP_Msk                  (0x1U << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
+#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos                 (3U)                               
+#define USART_CR3_HDSEL_Msk                 (0x1U << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
+#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos                  (4U)                               
+#define USART_CR3_NACK_Msk                  (0x1U << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
+#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos                  (5U)                               
+#define USART_CR3_SCEN_Msk                  (0x1U << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
+#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos                  (6U)                               
+#define USART_CR3_DMAR_Msk                  (0x1U << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
+#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos                  (7U)                               
+#define USART_CR3_DMAT_Msk                  (0x1U << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
+#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos                  (8U)                               
+#define USART_CR3_RTSE_Msk                  (0x1U << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
+#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos                  (9U)                               
+#define USART_CR3_CTSE_Msk                  (0x1U << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
+#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos                 (10U)                              
+#define USART_CR3_CTSIE_Msk                 (0x1U << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
+#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos                (11U)                              
+#define USART_CR3_ONEBIT_Msk                (0x1U << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
+#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos                (12U)                              
+#define USART_CR3_OVRDIS_Msk                (0x1U << USART_CR3_OVRDIS_Pos)     /*!< 0x00001000 */
+#define USART_CR3_OVRDIS                    USART_CR3_OVRDIS_Msk               /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos                  (13U)                              
+#define USART_CR3_DDRE_Msk                  (0x1U << USART_CR3_DDRE_Pos)       /*!< 0x00002000 */
+#define USART_CR3_DDRE                      USART_CR3_DDRE_Msk                 /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos                   (14U)                              
+#define USART_CR3_DEM_Msk                   (0x1U << USART_CR3_DEM_Pos)        /*!< 0x00004000 */
+#define USART_CR3_DEM                       USART_CR3_DEM_Msk                  /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos                   (15U)                              
+#define USART_CR3_DEP_Msk                   (0x1U << USART_CR3_DEP_Pos)        /*!< 0x00008000 */
+#define USART_CR3_DEP                       USART_CR3_DEP_Msk                  /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos               (17U)                              
+#define USART_CR3_SCARCNT_Msk               (0x7U << USART_CR3_SCARCNT_Pos)    /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT                   USART_CR3_SCARCNT_Msk              /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0                 (0x1U << USART_CR3_SCARCNT_Pos)    /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1                 (0x2U << USART_CR3_SCARCNT_Pos)    /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2                 (0x4U << USART_CR3_SCARCNT_Pos)    /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos                   (20U)                              
+#define USART_CR3_WUS_Msk                   (0x3U << USART_CR3_WUS_Pos)        /*!< 0x00300000 */
+#define USART_CR3_WUS                       USART_CR3_WUS_Msk                  /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0                     (0x1U << USART_CR3_WUS_Pos)        /*!< 0x00100000 */
+#define USART_CR3_WUS_1                     (0x2U << USART_CR3_WUS_Pos)        /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos                 (22U)                              
+#define USART_CR3_WUFIE_Msk                 (0x1U << USART_CR3_WUFIE_Pos)      /*!< 0x00400000 */
+#define USART_CR3_WUFIE                     USART_CR3_WUFIE_Msk                /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos          (0U)                                     
+#define USART_BRR_DIV_FRACTION_Msk          (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos          (4U)                                     
+#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos                  (0U)                               
+#define USART_GTPR_PSC_Msk                  (0xFFU << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
+#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos                   (8U)                               
+#define USART_GTPR_GT_Msk                   (0xFFU << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
+#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos                  (0U)                               
+#define USART_RTOR_RTO_Msk                  (0xFFFFFFU << USART_RTOR_RTO_Pos)  /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                      USART_RTOR_RTO_Msk                 /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos                 (24U)                              
+#define USART_RTOR_BLEN_Msk                 (0xFFU << USART_RTOR_BLEN_Pos)     /*!< 0xFF000000 */
+#define USART_RTOR_BLEN                     USART_RTOR_BLEN_Msk                /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos                 (0U)                                     
+#define USART_RQR_ABRRQ_Msk                 (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
+#define USART_RQR_ABRRQ                     USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos                 (1U)                                     
+#define USART_RQR_SBKRQ_Msk                 (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
+#define USART_RQR_SBKRQ                     USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos                  (2U)                                     
+#define USART_RQR_MMRQ_Msk                  (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
+#define USART_RQR_MMRQ                      USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos                 (3U)                                     
+#define USART_RQR_RXFRQ_Msk                 (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
+#define USART_RQR_RXFRQ                     USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos                 (4U)                                     
+#define USART_RQR_TXFRQ_Msk                 (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
+#define USART_RQR_TXFRQ                     USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos                    (0U)                               
+#define USART_ISR_PE_Msk                    (0x1U << USART_ISR_PE_Pos)         /*!< 0x00000001 */
+#define USART_ISR_PE                        USART_ISR_PE_Msk                   /*!< Parity Error */
+#define USART_ISR_FE_Pos                    (1U)                               
+#define USART_ISR_FE_Msk                    (0x1U << USART_ISR_FE_Pos)         /*!< 0x00000002 */
+#define USART_ISR_FE                        USART_ISR_FE_Msk                   /*!< Framing Error */
+#define USART_ISR_NE_Pos                    (2U)                               
+#define USART_ISR_NE_Msk                    (0x1U << USART_ISR_NE_Pos)         /*!< 0x00000004 */
+#define USART_ISR_NE                        USART_ISR_NE_Msk                   /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos                   (3U)                               
+#define USART_ISR_ORE_Msk                   (0x1U << USART_ISR_ORE_Pos)        /*!< 0x00000008 */
+#define USART_ISR_ORE                       USART_ISR_ORE_Msk                  /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos                  (4U)                               
+#define USART_ISR_IDLE_Msk                  (0x1U << USART_ISR_IDLE_Pos)       /*!< 0x00000010 */
+#define USART_ISR_IDLE                      USART_ISR_IDLE_Msk                 /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos                  (5U)                               
+#define USART_ISR_RXNE_Msk                  (0x1U << USART_ISR_RXNE_Pos)       /*!< 0x00000020 */
+#define USART_ISR_RXNE                      USART_ISR_RXNE_Msk                 /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos                    (6U)                               
+#define USART_ISR_TC_Msk                    (0x1U << USART_ISR_TC_Pos)         /*!< 0x00000040 */
+#define USART_ISR_TC                        USART_ISR_TC_Msk                   /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos                   (7U)                               
+#define USART_ISR_TXE_Msk                   (0x1U << USART_ISR_TXE_Pos)        /*!< 0x00000080 */
+#define USART_ISR_TXE                       USART_ISR_TXE_Msk                  /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos                  (8U)                               
+#define USART_ISR_LBDF_Msk                  (0x1U << USART_ISR_LBDF_Pos)       /*!< 0x00000100 */
+#define USART_ISR_LBDF                      USART_ISR_LBDF_Msk                 /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos                 (9U)                               
+#define USART_ISR_CTSIF_Msk                 (0x1U << USART_ISR_CTSIF_Pos)      /*!< 0x00000200 */
+#define USART_ISR_CTSIF                     USART_ISR_CTSIF_Msk                /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos                   (10U)                              
+#define USART_ISR_CTS_Msk                   (0x1U << USART_ISR_CTS_Pos)        /*!< 0x00000400 */
+#define USART_ISR_CTS                       USART_ISR_CTS_Msk                  /*!< CTS flag */
+#define USART_ISR_RTOF_Pos                  (11U)                              
+#define USART_ISR_RTOF_Msk                  (0x1U << USART_ISR_RTOF_Pos)       /*!< 0x00000800 */
+#define USART_ISR_RTOF                      USART_ISR_RTOF_Msk                 /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos                  (12U)                              
+#define USART_ISR_EOBF_Msk                  (0x1U << USART_ISR_EOBF_Pos)       /*!< 0x00001000 */
+#define USART_ISR_EOBF                      USART_ISR_EOBF_Msk                 /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos                  (14U)                              
+#define USART_ISR_ABRE_Msk                  (0x1U << USART_ISR_ABRE_Pos)       /*!< 0x00004000 */
+#define USART_ISR_ABRE                      USART_ISR_ABRE_Msk                 /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos                  (15U)                              
+#define USART_ISR_ABRF_Msk                  (0x1U << USART_ISR_ABRF_Pos)       /*!< 0x00008000 */
+#define USART_ISR_ABRF                      USART_ISR_ABRF_Msk                 /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos                  (16U)                              
+#define USART_ISR_BUSY_Msk                  (0x1U << USART_ISR_BUSY_Pos)       /*!< 0x00010000 */
+#define USART_ISR_BUSY                      USART_ISR_BUSY_Msk                 /*!< Busy Flag */
+#define USART_ISR_CMF_Pos                   (17U)                              
+#define USART_ISR_CMF_Msk                   (0x1U << USART_ISR_CMF_Pos)        /*!< 0x00020000 */
+#define USART_ISR_CMF                       USART_ISR_CMF_Msk                  /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos                  (18U)                              
+#define USART_ISR_SBKF_Msk                  (0x1U << USART_ISR_SBKF_Pos)       /*!< 0x00040000 */
+#define USART_ISR_SBKF                      USART_ISR_SBKF_Msk                 /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos                   (19U)                              
+#define USART_ISR_RWU_Msk                   (0x1U << USART_ISR_RWU_Pos)        /*!< 0x00080000 */
+#define USART_ISR_RWU                       USART_ISR_RWU_Msk                  /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos                   (20U)                              
+#define USART_ISR_WUF_Msk                   (0x1U << USART_ISR_WUF_Pos)        /*!< 0x00100000 */
+#define USART_ISR_WUF                       USART_ISR_WUF_Msk                  /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos                 (21U)                              
+#define USART_ISR_TEACK_Msk                 (0x1U << USART_ISR_TEACK_Pos)      /*!< 0x00200000 */
+#define USART_ISR_TEACK                     USART_ISR_TEACK_Msk                /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos                 (22U)                              
+#define USART_ISR_REACK_Msk                 (0x1U << USART_ISR_REACK_Pos)      /*!< 0x00400000 */
+#define USART_ISR_REACK                     USART_ISR_REACK_Msk                /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos                  (0U)                               
+#define USART_ICR_PECF_Msk                  (0x1U << USART_ICR_PECF_Pos)       /*!< 0x00000001 */
+#define USART_ICR_PECF                      USART_ICR_PECF_Msk                 /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos                  (1U)                               
+#define USART_ICR_FECF_Msk                  (0x1U << USART_ICR_FECF_Pos)       /*!< 0x00000002 */
+#define USART_ICR_FECF                      USART_ICR_FECF_Msk                 /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos                   (2U)                               
+#define USART_ICR_NCF_Msk                   (0x1U << USART_ICR_NCF_Pos)        /*!< 0x00000004 */
+#define USART_ICR_NCF                       USART_ICR_NCF_Msk                  /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos                 (3U)                               
+#define USART_ICR_ORECF_Msk                 (0x1U << USART_ICR_ORECF_Pos)      /*!< 0x00000008 */
+#define USART_ICR_ORECF                     USART_ICR_ORECF_Msk                /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos                (4U)                               
+#define USART_ICR_IDLECF_Msk                (0x1U << USART_ICR_IDLECF_Pos)     /*!< 0x00000010 */
+#define USART_ICR_IDLECF                    USART_ICR_IDLECF_Msk               /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos                  (6U)                               
+#define USART_ICR_TCCF_Msk                  (0x1U << USART_ICR_TCCF_Pos)       /*!< 0x00000040 */
+#define USART_ICR_TCCF                      USART_ICR_TCCF_Msk                 /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos                 (8U)                               
+#define USART_ICR_LBDCF_Msk                 (0x1U << USART_ICR_LBDCF_Pos)      /*!< 0x00000100 */
+#define USART_ICR_LBDCF                     USART_ICR_LBDCF_Msk                /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos                 (9U)                               
+#define USART_ICR_CTSCF_Msk                 (0x1U << USART_ICR_CTSCF_Pos)      /*!< 0x00000200 */
+#define USART_ICR_CTSCF                     USART_ICR_CTSCF_Msk                /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos                 (11U)                              
+#define USART_ICR_RTOCF_Msk                 (0x1U << USART_ICR_RTOCF_Pos)      /*!< 0x00000800 */
+#define USART_ICR_RTOCF                     USART_ICR_RTOCF_Msk                /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos                 (12U)                              
+#define USART_ICR_EOBCF_Msk                 (0x1U << USART_ICR_EOBCF_Pos)      /*!< 0x00001000 */
+#define USART_ICR_EOBCF                     USART_ICR_EOBCF_Msk                /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos                  (17U)                              
+#define USART_ICR_CMCF_Msk                  (0x1U << USART_ICR_CMCF_Pos)       /*!< 0x00020000 */
+#define USART_ICR_CMCF                      USART_ICR_CMCF_Msk                 /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos                  (20U)                              
+#define USART_ICR_WUCF_Msk                  (0x1U << USART_ICR_WUCF_Pos)       /*!< 0x00100000 */
+#define USART_ICR_WUCF                      USART_ICR_WUCF_Msk                 /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos                   (0U)                                     
+#define USART_RDR_RDR_Msk                   (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
+#define USART_RDR_RDR                       USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos                   (0U)                                     
+#define USART_TDR_TDR_Msk                   (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
+#define USART_TDR_TDR                       USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*           Single Wire Protocol Master Interface (SWPMI)                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SWPMI_CR register   ********************/
+#define SWPMI_CR_RXDMA_Pos                  (0U)                               
+#define SWPMI_CR_RXDMA_Msk                  (0x1U << SWPMI_CR_RXDMA_Pos)       /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA                      SWPMI_CR_RXDMA_Msk                 /*!<Reception DMA enable                                 */
+#define SWPMI_CR_TXDMA_Pos                  (1U)                               
+#define SWPMI_CR_TXDMA_Msk                  (0x1U << SWPMI_CR_TXDMA_Pos)       /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA                      SWPMI_CR_TXDMA_Msk                 /*!<Transmission DMA enable                              */
+#define SWPMI_CR_RXMODE_Pos                 (2U)                               
+#define SWPMI_CR_RXMODE_Msk                 (0x1U << SWPMI_CR_RXMODE_Pos)      /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE                     SWPMI_CR_RXMODE_Msk                /*!<Reception buffering mode                             */
+#define SWPMI_CR_TXMODE_Pos                 (3U)                               
+#define SWPMI_CR_TXMODE_Msk                 (0x1U << SWPMI_CR_TXMODE_Pos)      /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE                     SWPMI_CR_TXMODE_Msk                /*!<Transmission buffering mode                          */
+#define SWPMI_CR_LPBK_Pos                   (4U)                               
+#define SWPMI_CR_LPBK_Msk                   (0x1U << SWPMI_CR_LPBK_Pos)        /*!< 0x00000010 */
+#define SWPMI_CR_LPBK                       SWPMI_CR_LPBK_Msk                  /*!<Loopback mode enable                                 */
+#define SWPMI_CR_SWPACT_Pos                 (5U)                               
+#define SWPMI_CR_SWPACT_Msk                 (0x1U << SWPMI_CR_SWPACT_Pos)      /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT                     SWPMI_CR_SWPACT_Msk                /*!<Single wire protocol master interface activate       */
+#define SWPMI_CR_DEACT_Pos                  (10U)                              
+#define SWPMI_CR_DEACT_Msk                  (0x1U << SWPMI_CR_DEACT_Pos)       /*!< 0x00000400 */
+#define SWPMI_CR_DEACT                      SWPMI_CR_DEACT_Msk                 /*!<Single wire protocol master interface deactivate     */
+
+/*******************  Bit definition for SWPMI_BRR register  ********************/
+#define SWPMI_BRR_BR_Pos                    (0U)                               
+#define SWPMI_BRR_BR_Msk                    (0x3FU << SWPMI_BRR_BR_Pos)        /*!< 0x0000003F */
+#define SWPMI_BRR_BR                        SWPMI_BRR_BR_Msk                   /*!<BR[5:0] bits (Bitrate prescaler) */
+
+/*******************  Bit definition for SWPMI_ISR register  ********************/
+#define SWPMI_ISR_RXBFF_Pos                 (0U)                               
+#define SWPMI_ISR_RXBFF_Msk                 (0x1U << SWPMI_ISR_RXBFF_Pos)      /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF                     SWPMI_ISR_RXBFF_Msk                /*!<Receive buffer full flag        */
+#define SWPMI_ISR_TXBEF_Pos                 (1U)                               
+#define SWPMI_ISR_TXBEF_Msk                 (0x1U << SWPMI_ISR_TXBEF_Pos)      /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF                     SWPMI_ISR_TXBEF_Msk                /*!<Transmit buffer empty flag      */
+#define SWPMI_ISR_RXBERF_Pos                (2U)                               
+#define SWPMI_ISR_RXBERF_Msk                (0x1U << SWPMI_ISR_RXBERF_Pos)     /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF                    SWPMI_ISR_RXBERF_Msk               /*!<Receive CRC error flag          */
+#define SWPMI_ISR_RXOVRF_Pos                (3U)                               
+#define SWPMI_ISR_RXOVRF_Msk                (0x1U << SWPMI_ISR_RXOVRF_Pos)     /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF                    SWPMI_ISR_RXOVRF_Msk               /*!<Receive overrun error flag      */
+#define SWPMI_ISR_TXUNRF_Pos                (4U)                               
+#define SWPMI_ISR_TXUNRF_Msk                (0x1U << SWPMI_ISR_TXUNRF_Pos)     /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF                    SWPMI_ISR_TXUNRF_Msk               /*!<Transmit underrun error flag    */
+#define SWPMI_ISR_RXNE_Pos                  (5U)                               
+#define SWPMI_ISR_RXNE_Msk                  (0x1U << SWPMI_ISR_RXNE_Pos)       /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE                      SWPMI_ISR_RXNE_Msk                 /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos                   (6U)                               
+#define SWPMI_ISR_TXE_Msk                   (0x1U << SWPMI_ISR_TXE_Pos)        /*!< 0x00000040 */
+#define SWPMI_ISR_TXE                       SWPMI_ISR_TXE_Msk                  /*!<Transmit data register empty    */
+#define SWPMI_ISR_TCF_Pos                   (7U)                               
+#define SWPMI_ISR_TCF_Msk                   (0x1U << SWPMI_ISR_TCF_Pos)        /*!< 0x00000080 */
+#define SWPMI_ISR_TCF                       SWPMI_ISR_TCF_Msk                  /*!<Transfer complete flag          */
+#define SWPMI_ISR_SRF_Pos                   (8U)                               
+#define SWPMI_ISR_SRF_Msk                   (0x1U << SWPMI_ISR_SRF_Pos)        /*!< 0x00000100 */
+#define SWPMI_ISR_SRF                       SWPMI_ISR_SRF_Msk                  /*!<Slave resume flag               */
+#define SWPMI_ISR_SUSP_Pos                  (9U)                               
+#define SWPMI_ISR_SUSP_Msk                  (0x1U << SWPMI_ISR_SUSP_Pos)       /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP                      SWPMI_ISR_SUSP_Msk                 /*!<SUSPEND flag                    */
+#define SWPMI_ISR_DEACTF_Pos                (10U)                              
+#define SWPMI_ISR_DEACTF_Msk                (0x1U << SWPMI_ISR_DEACTF_Pos)     /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF                    SWPMI_ISR_DEACTF_Msk               /*!<DEACTIVATED flag                */
+
+/*******************  Bit definition for SWPMI_ICR register  ********************/
+#define SWPMI_ICR_CRXBFF_Pos                (0U)                               
+#define SWPMI_ICR_CRXBFF_Msk                (0x1U << SWPMI_ICR_CRXBFF_Pos)     /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF                    SWPMI_ICR_CRXBFF_Msk               /*!<Clear receive buffer full flag       */
+#define SWPMI_ICR_CTXBEF_Pos                (1U)                               
+#define SWPMI_ICR_CTXBEF_Msk                (0x1U << SWPMI_ICR_CTXBEF_Pos)     /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF                    SWPMI_ICR_CTXBEF_Msk               /*!<Clear transmit buffer empty flag     */
+#define SWPMI_ICR_CRXBERF_Pos               (2U)                               
+#define SWPMI_ICR_CRXBERF_Msk               (0x1U << SWPMI_ICR_CRXBERF_Pos)    /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF                   SWPMI_ICR_CRXBERF_Msk              /*!<Clear receive CRC error flag         */
+#define SWPMI_ICR_CRXOVRF_Pos               (3U)                               
+#define SWPMI_ICR_CRXOVRF_Msk               (0x1U << SWPMI_ICR_CRXOVRF_Pos)    /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF                   SWPMI_ICR_CRXOVRF_Msk              /*!<Clear receive overrun error flag     */
+#define SWPMI_ICR_CTXUNRF_Pos               (4U)                               
+#define SWPMI_ICR_CTXUNRF_Msk               (0x1U << SWPMI_ICR_CTXUNRF_Pos)    /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF                   SWPMI_ICR_CTXUNRF_Msk              /*!<Clear transmit underrun error flag   */
+#define SWPMI_ICR_CTCF_Pos                  (7U)                               
+#define SWPMI_ICR_CTCF_Msk                  (0x1U << SWPMI_ICR_CTCF_Pos)       /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF                      SWPMI_ICR_CTCF_Msk                 /*!<Clear transfer complete flag         */
+#define SWPMI_ICR_CSRF_Pos                  (8U)                               
+#define SWPMI_ICR_CSRF_Msk                  (0x1U << SWPMI_ICR_CSRF_Pos)       /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF                      SWPMI_ICR_CSRF_Msk                 /*!<Clear slave resume flag              */
+
+/*******************  Bit definition for SWPMI_IER register  ********************/
+#define SWPMI_IER_SRIE_Pos                  (8U)                               
+#define SWPMI_IER_SRIE_Msk                  (0x1U << SWPMI_IER_SRIE_Pos)       /*!< 0x00000100 */
+#define SWPMI_IER_SRIE                      SWPMI_IER_SRIE_Msk                 /*!<Slave resume interrupt enable               */
+#define SWPMI_IER_TCIE_Pos                  (7U)                               
+#define SWPMI_IER_TCIE_Msk                  (0x1U << SWPMI_IER_TCIE_Pos)       /*!< 0x00000080 */
+#define SWPMI_IER_TCIE                      SWPMI_IER_TCIE_Msk                 /*!<Transmit complete interrupt enable          */
+#define SWPMI_IER_TIE_Pos                   (6U)                               
+#define SWPMI_IER_TIE_Msk                   (0x1U << SWPMI_IER_TIE_Pos)        /*!< 0x00000040 */
+#define SWPMI_IER_TIE                       SWPMI_IER_TIE_Msk                  /*!<Transmit interrupt enable                   */
+#define SWPMI_IER_RIE_Pos                   (5U)                               
+#define SWPMI_IER_RIE_Msk                   (0x1U << SWPMI_IER_RIE_Pos)        /*!< 0x00000020 */
+#define SWPMI_IER_RIE                       SWPMI_IER_RIE_Msk                  /*!<Receive interrupt enable                    */
+#define SWPMI_IER_TXUNRIE_Pos               (4U)                               
+#define SWPMI_IER_TXUNRIE_Msk               (0x1U << SWPMI_IER_TXUNRIE_Pos)    /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE                   SWPMI_IER_TXUNRIE_Msk              /*!<Transmit underrun error interrupt enable    */
+#define SWPMI_IER_RXOVRIE_Pos               (3U)                               
+#define SWPMI_IER_RXOVRIE_Msk               (0x1U << SWPMI_IER_RXOVRIE_Pos)    /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE                   SWPMI_IER_RXOVRIE_Msk              /*!<Receive overrun error interrupt enable      */
+#define SWPMI_IER_RXBERIE_Pos               (2U)                               
+#define SWPMI_IER_RXBERIE_Msk               (0x1U << SWPMI_IER_RXBERIE_Pos)    /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE                   SWPMI_IER_RXBERIE_Msk              /*!<Receive CRC error interrupt enable          */
+#define SWPMI_IER_TXBEIE_Pos                (1U)                               
+#define SWPMI_IER_TXBEIE_Msk                (0x1U << SWPMI_IER_TXBEIE_Pos)     /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE                    SWPMI_IER_TXBEIE_Msk               /*!<Transmit buffer empty interrupt enable      */
+#define SWPMI_IER_RXBFIE_Pos                (0U)                               
+#define SWPMI_IER_RXBFIE_Msk                (0x1U << SWPMI_IER_RXBFIE_Pos)     /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE                    SWPMI_IER_RXBFIE_Msk               /*!<Receive buffer full interrupt enable        */
+
+/*******************  Bit definition for SWPMI_RFL register  ********************/
+#define SWPMI_RFL_RFL_Pos                   (0U)                               
+#define SWPMI_RFL_RFL_Msk                   (0x1FU << SWPMI_RFL_RFL_Pos)       /*!< 0x0000001F */
+#define SWPMI_RFL_RFL                       SWPMI_RFL_RFL_Msk                  /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1                   (0x00000003U)                      /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/*******************  Bit definition for SWPMI_TDR register  ********************/
+#define SWPMI_TDR_TD_Pos                    (0U)                               
+#define SWPMI_TDR_TD_Msk                    (0xFFFFFFFFU << SWPMI_TDR_TD_Pos)  /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD                        SWPMI_TDR_TD_Msk                   /*!<Transmit Data Register         */
+
+/*******************  Bit definition for SWPMI_RDR register  ********************/
+#define SWPMI_RDR_RD_Pos                    (0U)                               
+#define SWPMI_RDR_RD_Msk                    (0xFFFFFFFFU << SWPMI_RDR_RD_Pos)  /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD                        SWPMI_RDR_RD_Msk                   /*!<Receive Data Register          */
+
+/*******************  Bit definition for SWPMI_OR register  ********************/
+#define SWPMI_OR_TBYP_Pos                   (0U)                               
+#define SWPMI_OR_TBYP_Msk                   (0x1U << SWPMI_OR_TBYP_Pos)        /*!< 0x00000001 */
+#define SWPMI_OR_TBYP                       SWPMI_OR_TBYP_Msk                  /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos                  (1U)                               
+#define SWPMI_OR_CLASS_Msk                  (0x1U << SWPMI_OR_CLASS_Pos)       /*!< 0x00000002 */
+#define SWPMI_OR_CLASS                      SWPMI_OR_CLASS_Msk                 /*!<SWP Voltage Class selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 VREFBUF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos                (0U)                               
+#define VREFBUF_CSR_ENVR_Msk                (0x1U << VREFBUF_CSR_ENVR_Pos)     /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR                    VREFBUF_CSR_ENVR_Msk               /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos                 (1U)                               
+#define VREFBUF_CSR_HIZ_Msk                 (0x1U << VREFBUF_CSR_HIZ_Pos)      /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ                     VREFBUF_CSR_HIZ_Msk                /*!<High impedance mode             */
+#define VREFBUF_CSR_VRS_Pos                 (2U)                               
+#define VREFBUF_CSR_VRS_Msk                 (0x1U << VREFBUF_CSR_VRS_Pos)      /*!< 0x00000004 */
+#define VREFBUF_CSR_VRS                     VREFBUF_CSR_VRS_Msk                /*!<Voltage reference scale         */
+#define VREFBUF_CSR_VRR_Pos                 (3U)                               
+#define VREFBUF_CSR_VRR_Msk                 (0x1U << VREFBUF_CSR_VRR_Pos)      /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR                     VREFBUF_CSR_VRR_Msk                /*!<Voltage reference buffer ready  */
+
+/*******************  Bit definition for VREFBUF_CCR register  ******************/
+#define VREFBUF_CCR_TRIM_Pos                (0U)                               
+#define VREFBUF_CCR_TRIM_Msk                (0x3FU << VREFBUF_CCR_TRIM_Pos)    /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM                    VREFBUF_CCR_TRIM_Msk               /*!<TRIM[5:0] bits (Trimming code)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos                       (0U)                               
+#define WWDG_CR_T_Msk                       (0x7FU << WWDG_CR_T_Pos)           /*!< 0x0000007F */
+#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0                         (0x01U << WWDG_CR_T_Pos)           /*!< 0x00000001 */
+#define WWDG_CR_T_1                         (0x02U << WWDG_CR_T_Pos)           /*!< 0x00000002 */
+#define WWDG_CR_T_2                         (0x04U << WWDG_CR_T_Pos)           /*!< 0x00000004 */
+#define WWDG_CR_T_3                         (0x08U << WWDG_CR_T_Pos)           /*!< 0x00000008 */
+#define WWDG_CR_T_4                         (0x10U << WWDG_CR_T_Pos)           /*!< 0x00000010 */
+#define WWDG_CR_T_5                         (0x20U << WWDG_CR_T_Pos)           /*!< 0x00000020 */
+#define WWDG_CR_T_6                         (0x40U << WWDG_CR_T_Pos)           /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos                    (7U)                               
+#define WWDG_CR_WDGA_Msk                    (0x1U << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
+#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos                      (0U)                               
+#define WWDG_CFR_W_Msk                      (0x7FU << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
+#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0                        (0x01U << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
+#define WWDG_CFR_W_1                        (0x02U << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
+#define WWDG_CFR_W_2                        (0x04U << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
+#define WWDG_CFR_W_3                        (0x08U << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
+#define WWDG_CFR_W_4                        (0x10U << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
+#define WWDG_CFR_W_5                        (0x20U << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
+#define WWDG_CFR_W_6                        (0x40U << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
+
+#define WWDG_CFR_WDGTB_Pos                  (7U)                               
+#define WWDG_CFR_WDGTB_Msk                  (0x3U << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0                    (0x1U << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1                    (0x2U << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
+
+#define WWDG_CFR_EWI_Pos                    (9U)                               
+#define WWDG_CFR_EWI_Msk                    (0x1U << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
+#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos                    (0U)                               
+#define WWDG_SR_EWIF_Msk                    (0x1U << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
+#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos            (0U)                               
+#define DBGMCU_IDCODE_DEV_ID_Msk            (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                DBGMCU_IDCODE_DEV_ID_Msk           
+#define DBGMCU_IDCODE_REV_ID_Pos            (16U)                              
+#define DBGMCU_IDCODE_REV_ID_Msk            (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                DBGMCU_IDCODE_REV_ID_Msk           
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos             (0U)                               
+#define DBGMCU_CR_DBG_SLEEP_Msk             (0x1U << DBGMCU_CR_DBG_SLEEP_Pos)  /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                 DBGMCU_CR_DBG_SLEEP_Msk            
+#define DBGMCU_CR_DBG_STOP_Pos              (1U)                               
+#define DBGMCU_CR_DBG_STOP_Msk              (0x1U << DBGMCU_CR_DBG_STOP_Pos)   /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                  DBGMCU_CR_DBG_STOP_Msk             
+#define DBGMCU_CR_DBG_STANDBY_Pos           (2U)                               
+#define DBGMCU_CR_DBG_STANDBY_Msk           (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY               DBGMCU_CR_DBG_STANDBY_Msk          
+#define DBGMCU_CR_TRACE_IOEN_Pos            (5U)                               
+#define DBGMCU_CR_TRACE_IOEN_Msk            (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN                DBGMCU_CR_TRACE_IOEN_Msk           
+
+#define DBGMCU_CR_TRACE_MODE_Pos            (6U)                               
+#define DBGMCU_CR_TRACE_MODE_Msk            (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE                DBGMCU_CR_TRACE_MODE_Msk           
+#define DBGMCU_CR_TRACE_MODE_0              (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1              (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos   (0U)                               
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk   (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP       DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk  
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos   (1U)                               
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk   (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP       DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk  
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos   (2U)                               
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk   (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP       DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk  
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos   (3U)                               
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk   (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP       DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk  
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos   (4U)                               
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk   (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP       DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk  
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos   (5U)                               
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk   (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP       DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk  
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos    (10U)                              
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk    (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP        DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk   
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos   (11U)                              
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk   (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP       DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk  
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos   (12U)                              
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk   (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP       DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk  
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos   (21U)                              
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk   (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP       DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk  
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos   (22U)                              
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk   (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP       DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk  
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos   (23U)                              
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk   (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP       DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk  
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos    (25U)                              
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk    (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP        DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk   
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)                              
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP     DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)                               
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP     DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB2FZ register  ************/
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos     (11U)                              
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk     (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP         DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk    
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos     (13U)                              
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk     (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP         DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk    
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos    (16U)                              
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk    (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP        DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk   
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos    (17U)                              
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk    (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP        DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk   
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos    (18U)                              
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk    (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP        DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk   
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos                   (0U)                      
+#define USB_OTG_GOTGCTL_SRQSCS_Msk                   (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                       USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                      (1U)                      
+#define USB_OTG_GOTGCTL_SRQ_Msk                      (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                          USB_OTG_GOTGCTL_SRQ_Msk   /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos                 (2U)                      
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk                 (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                     USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos                (3U)                      
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk                (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                    USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos                  (4U)                      
+#define USB_OTG_GOTGCTL_AVALOEN_Msk                  (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                      USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos                 (5U)                      
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk                 (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                     USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos                  (6U)                      
+#define USB_OTG_GOTGCTL_BVALOEN_Msk                  (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                      USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos                 (7U)                      
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk                 (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                     USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos                  (19U)                     
+#define USB_OTG_GOTGCTL_BSESVLD_Msk                  (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                      USB_OTG_GOTGCTL_BSESVLD_Msk /*!<  B-session valid*/
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                     (0U)                      
+#define USB_OTG_HCFG_FSLSPCS_Msk                     (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                         USB_OTG_HCFG_FSLSPCS_Msk  /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0                       (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                       (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                       (2U)                      
+#define USB_OTG_HCFG_FSLSS_Msk                       (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                           USB_OTG_HCFG_FSLSS_Msk    /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                        (0U)                      
+#define USB_OTG_DCFG_DSPD_Msk                        (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                            USB_OTG_DCFG_DSPD_Msk     /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                          (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                          (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                    (2U)                      
+#define USB_OTG_DCFG_NZLSOHSK_Msk                    (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                        USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DAD_Pos                         (4U)                      
+#define USB_OTG_DCFG_DAD_Msk                         (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                             USB_OTG_DCFG_DAD_Msk      /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                           (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                           (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                           (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                           (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                           (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                           (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                           (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCFG_PFIVL_Pos                       (11U)                     
+#define USB_OTG_DCFG_PFIVL_Msk                       (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                           USB_OTG_DCFG_PFIVL_Msk    /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                         (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                         (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+#define USB_OTG_DCFG_PERSCHIVL_Pos                   (24U)                     
+#define USB_OTG_DCFG_PERSCHIVL_Msk                   (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                       USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                     (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                     (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                    (0U)                      
+#define USB_OTG_PCGCR_STPPCLK_Msk                    (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                        USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos                   (1U)                      
+#define USB_OTG_PCGCR_GATEHCLK_Msk                   (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                       USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                    (4U)                      
+#define USB_OTG_PCGCR_PHYSUSP_Msk                    (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                        USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                    (2U)                      
+#define USB_OTG_GOTGINT_SEDET_Msk                    (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                        USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos                  (8U)                      
+#define USB_OTG_GOTGINT_SRSSCHG_Msk                  (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                      USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos                  (9U)                      
+#define USB_OTG_GOTGINT_HNSSCHG_Msk                  (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                      USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos                   (17U)                     
+#define USB_OTG_GOTGINT_HNGDET_Msk                   (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                       USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos                  (18U)                     
+#define USB_OTG_GOTGINT_ADTOCHG_Msk                  (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                      USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos                   (19U)                     
+#define USB_OTG_GOTGINT_DBCDNE_Msk                   (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                       USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                      (0U)                      
+#define USB_OTG_DCTL_RWUSIG_Msk                      (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                          USB_OTG_DCTL_RWUSIG_Msk   /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                        (1U)                      
+#define USB_OTG_DCTL_SDIS_Msk                        (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                            USB_OTG_DCTL_SDIS_Msk     /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos                      (2U)                      
+#define USB_OTG_DCTL_GINSTS_Msk                      (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                          USB_OTG_DCTL_GINSTS_Msk   /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos                      (3U)                      
+#define USB_OTG_DCTL_GONSTS_Msk                      (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                          USB_OTG_DCTL_GONSTS_Msk   /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos                        (4U)                      
+#define USB_OTG_DCTL_TCTL_Msk                        (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                            USB_OTG_DCTL_TCTL_Msk     /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                          (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                          (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                          (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                      (7U)                      
+#define USB_OTG_DCTL_SGINAK_Msk                      (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                          USB_OTG_DCTL_SGINAK_Msk   /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos                      (8U)                      
+#define USB_OTG_DCTL_CGINAK_Msk                      (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                          USB_OTG_DCTL_CGINAK_Msk   /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos                      (9U)                      
+#define USB_OTG_DCTL_SGONAK_Msk                      (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                          USB_OTG_DCTL_SGONAK_Msk   /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos                      (10U)                     
+#define USB_OTG_DCTL_CGONAK_Msk                      (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                          USB_OTG_DCTL_CGONAK_Msk   /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos                    (11U)                     
+#define USB_OTG_DCTL_POPRGDNE_Msk                    (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                        USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                       (0U)                      
+#define USB_OTG_HFIR_FRIVL_Msk                       (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                           USB_OTG_HFIR_FRIVL_Msk    /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                      (0U)                      
+#define USB_OTG_HFNUM_FRNUM_Msk                      (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                          USB_OTG_HFNUM_FRNUM_Msk   /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos                      (16U)                     
+#define USB_OTG_HFNUM_FTREM_Msk                      (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                          USB_OTG_HFNUM_FTREM_Msk   /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                     (0U)                      
+#define USB_OTG_DSTS_SUSPSTS_Msk                     (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                         USB_OTG_DSTS_SUSPSTS_Msk  /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                     (1U)                      
+#define USB_OTG_DSTS_ENUMSPD_Msk                     (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                         USB_OTG_DSTS_ENUMSPD_Msk  /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                       (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                       (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                        (3U)                      
+#define USB_OTG_DSTS_EERR_Msk                        (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                            USB_OTG_DSTS_EERR_Msk     /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos                       (8U)                      
+#define USB_OTG_DSTS_FNSOF_Msk                       (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                           USB_OTG_DSTS_FNSOF_Msk    /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                     (0U)                      
+#define USB_OTG_GAHBCFG_GINT_Msk                     (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                         USB_OTG_GAHBCFG_GINT_Msk  /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos                  (1U)                      
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk                  (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                      USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                    (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                    (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                    (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                    (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                    (5U)                      
+#define USB_OTG_GAHBCFG_DMAEN_Msk                    (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                        USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos                  (7U)                      
+#define USB_OTG_GAHBCFG_TXFELVL_Msk                  (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                      USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos                 (8U)                      
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk                 (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                     USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                    (0U)                      
+#define USB_OTG_GUSBCFG_TOCAL_Msk                    (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                        USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                      (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                      (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                      (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos                   (6U)                      
+#define USB_OTG_GUSBCFG_PHYSEL_Msk                   (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                       USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos                   (8U)                      
+#define USB_OTG_GUSBCFG_SRPCAP_Msk                   (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                       USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos                   (9U)                      
+#define USB_OTG_GUSBCFG_HNPCAP_Msk                   (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                       USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos                     (10U)                     
+#define USB_OTG_GUSBCFG_TRDT_Msk                     (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                         USB_OTG_GUSBCFG_TRDT_Msk  /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                       (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                       (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                       (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                       (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos                  (15U)                     
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk                  (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                      USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos                 (17U)                     
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk                 (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                     USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos                   (18U)                     
+#define USB_OTG_GUSBCFG_ULPIAR_Msk                   (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                       USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos                  (19U)                     
+#define USB_OTG_GUSBCFG_ULPICSM_Msk                  (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                      USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos               (20U)                     
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD                   USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos               (21U)                     
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI                   USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                    (22U)                     
+#define USB_OTG_GUSBCFG_TSDPS_Msk                    (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                        USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                     (23U)                     
+#define USB_OTG_GUSBCFG_PCCI_Msk                     (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                         USB_OTG_GUSBCFG_PCCI_Msk  /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos                     (24U)                     
+#define USB_OTG_GUSBCFG_PTCI_Msk                     (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                         USB_OTG_GUSBCFG_PTCI_Msk  /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos                  (25U)                     
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk                  (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                      USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                    (29U)                     
+#define USB_OTG_GUSBCFG_FHMOD_Msk                    (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                        USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                    (30U)                     
+#define USB_OTG_GUSBCFG_FDMOD_Msk                    (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                        USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos                   (31U)                     
+#define USB_OTG_GUSBCFG_CTXPKT_Msk                   (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                       USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                    (0U)                      
+#define USB_OTG_GRSTCTL_CSRST_Msk                    (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                        USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos                    (1U)                      
+#define USB_OTG_GRSTCTL_HSRST_Msk                    (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                        USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos                    (2U)                      
+#define USB_OTG_GRSTCTL_FCRST_Msk                    (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                        USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos                  (4U)                      
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk                  (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                      USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos                  (5U)                      
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk                  (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                      USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFNUM_Pos                   (6U)                      
+#define USB_OTG_GRSTCTL_TXFNUM_Msk                   (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                       USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                     (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                     (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                     (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                     (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                     (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos                   (30U)                     
+#define USB_OTG_GRSTCTL_DMAREQ_Msk                   (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                       USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos                   (31U)                     
+#define USB_OTG_GRSTCTL_AHBIDL_Msk                   (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                       USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                    (0U)                      
+#define USB_OTG_DIEPMSK_XFRCM_Msk                    (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                        USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos                     (1U)                      
+#define USB_OTG_DIEPMSK_EPDM_Msk                     (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                         USB_OTG_DIEPMSK_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos                      (3U)                      
+#define USB_OTG_DIEPMSK_TOM_Msk                      (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                          USB_OTG_DIEPMSK_TOM_Msk   /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos                (4U)                      
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk                (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                    USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos                  (5U)                      
+#define USB_OTG_DIEPMSK_INEPNMM_Msk                  (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                      USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos                  (6U)                      
+#define USB_OTG_DIEPMSK_INEPNEM_Msk                  (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                      USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos                   (8U)                      
+#define USB_OTG_DIEPMSK_TXFURM_Msk                   (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                       USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos                      (9U)                      
+#define USB_OTG_DIEPMSK_BIM_Msk                      (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                          USB_OTG_DIEPMSK_BIM_Msk   /*!< BNA interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos                 (0U)                      
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk                 (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                     USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos                  (16U)                     
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk                  (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                      USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                    (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                    (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                    (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                    (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                    (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                    (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                    (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                    (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos                  (24U)                     
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk                  (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                      USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                    (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                    (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                    (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                    (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                    (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                    (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                    (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                    (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                      (0U)                      
+#define USB_OTG_HAINT_HAINT_Msk                      (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                          USB_OTG_HAINT_HAINT_Msk   /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                    (0U)                      
+#define USB_OTG_DOEPMSK_XFRCM_Msk                    (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                        USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                     (1U)                      
+#define USB_OTG_DOEPMSK_EPDM_Msk                     (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                         USB_OTG_DOEPMSK_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos                    (3U)                      
+#define USB_OTG_DOEPMSK_STUPM_Msk                    (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                        USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos                   (4U)                      
+#define USB_OTG_DOEPMSK_OTEPDM_Msk                   (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                       USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos                  (6U)                      
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk                  (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                      USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos                     (8U)                      
+#define USB_OTG_DOEPMSK_OPEM_Msk                     (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                         USB_OTG_DOEPMSK_OPEM_Msk  /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos                     (9U)                      
+#define USB_OTG_DOEPMSK_BOIM_Msk                     (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                         USB_OTG_DOEPMSK_BOIM_Msk  /*!< BNA interrupt mask */
+
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                     (0U)                      
+#define USB_OTG_GINTSTS_CMOD_Msk                     (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                         USB_OTG_GINTSTS_CMOD_Msk  /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos                     (1U)                      
+#define USB_OTG_GINTSTS_MMIS_Msk                     (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                         USB_OTG_GINTSTS_MMIS_Msk  /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos                   (2U)                      
+#define USB_OTG_GINTSTS_OTGINT_Msk                   (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                       USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos                      (3U)                      
+#define USB_OTG_GINTSTS_SOF_Msk                      (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                          USB_OTG_GINTSTS_SOF_Msk   /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos                   (4U)                      
+#define USB_OTG_GINTSTS_RXFLVL_Msk                   (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                       USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos                   (5U)                      
+#define USB_OTG_GINTSTS_NPTXFE_Msk                   (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                       USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos                 (6U)                      
+#define USB_OTG_GINTSTS_GINAKEFF_Msk                 (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                     USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos               (7U)                      
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk               (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF                   USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos                    (10U)                     
+#define USB_OTG_GINTSTS_ESUSP_Msk                    (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                        USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos                  (11U)                     
+#define USB_OTG_GINTSTS_USBSUSP_Msk                  (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                      USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos                   (12U)                     
+#define USB_OTG_GINTSTS_USBRST_Msk                   (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                       USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos                  (13U)                     
+#define USB_OTG_GINTSTS_ENUMDNE_Msk                  (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                      USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos                  (14U)                     
+#define USB_OTG_GINTSTS_ISOODRP_Msk                  (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                      USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos                     (15U)                     
+#define USB_OTG_GINTSTS_EOPF_Msk                     (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                         USB_OTG_GINTSTS_EOPF_Msk  /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos                   (18U)                     
+#define USB_OTG_GINTSTS_IEPINT_Msk                   (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                       USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos                   (19U)                     
+#define USB_OTG_GINTSTS_OEPINT_Msk                   (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                       USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos                 (20U)                     
+#define USB_OTG_GINTSTS_IISOIXFR_Msk                 (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                     USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos        (21U)                     
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk        (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT            USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos                (22U)                     
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk                (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                    USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos                  (24U)                     
+#define USB_OTG_GINTSTS_HPRTINT_Msk                  (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                      USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos                    (25U)                     
+#define USB_OTG_GINTSTS_HCINT_Msk                    (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                        USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos                    (26U)                     
+#define USB_OTG_GINTSTS_PTXFE_Msk                    (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                        USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT_Pos                   (27U)                     
+#define USB_OTG_GINTSTS_LPMINT_Msk                   (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                       USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos                  (28U)                     
+#define USB_OTG_GINTSTS_CIDSCHG_Msk                  (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                      USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos                  (29U)                     
+#define USB_OTG_GINTSTS_DISCINT_Msk                  (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                      USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos                   (30U)                     
+#define USB_OTG_GINTSTS_SRQINT_Msk                   (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                       USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos                   (31U)                     
+#define USB_OTG_GINTSTS_WKUINT_Msk                   (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                       USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+
+#define USB_OTG_GINTMSK_MMISM_Pos                    (1U)                      
+#define USB_OTG_GINTMSK_MMISM_Msk                    (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                        USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos                   (2U)                      
+#define USB_OTG_GINTMSK_OTGINT_Msk                   (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                       USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos                     (3U)                      
+#define USB_OTG_GINTMSK_SOFM_Msk                     (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                         USB_OTG_GINTMSK_SOFM_Msk  /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos                  (4U)                      
+#define USB_OTG_GINTMSK_RXFLVLM_Msk                  (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                      USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos                  (5U)                      
+#define USB_OTG_GINTMSK_NPTXFEM_Msk                  (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                      USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos                (6U)                      
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk                (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                    USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos                (7U)                      
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk                (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                    USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos                   (10U)                     
+#define USB_OTG_GINTMSK_ESUSPM_Msk                   (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                       USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos                 (11U)                     
+#define USB_OTG_GINTMSK_USBSUSPM_Msk                 (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                     USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos                   (12U)                     
+#define USB_OTG_GINTMSK_USBRST_Msk                   (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                       USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos                 (13U)                     
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk                 (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                     USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos                 (14U)                     
+#define USB_OTG_GINTMSK_ISOODRPM_Msk                 (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                     USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos                    (15U)                     
+#define USB_OTG_GINTMSK_EOPFM_Msk                    (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                        USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos                   (17U)                     
+#define USB_OTG_GINTMSK_EPMISM_Msk                   (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                       USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos                   (18U)                     
+#define USB_OTG_GINTMSK_IEPINT_Msk                   (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                       USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos                   (19U)                     
+#define USB_OTG_GINTMSK_OEPINT_Msk                   (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                       USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos                (20U)                     
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk                (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                    USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos          (21U)                     
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk          (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM              USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos                   (22U)                     
+#define USB_OTG_GINTMSK_FSUSPM_Msk                   (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                       USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos                    (24U)                     
+#define USB_OTG_GINTMSK_PRTIM_Msk                    (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                        USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos                     (25U)                     
+#define USB_OTG_GINTMSK_HCIM_Msk                     (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                         USB_OTG_GINTMSK_HCIM_Msk  /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos                   (26U)                     
+#define USB_OTG_GINTMSK_PTXFEM_Msk                   (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                       USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM_Pos                  (27U)                     
+#define USB_OTG_GINTMSK_LPMINTM_Msk                  (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                      USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos                 (28U)                     
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk                 (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                     USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos                  (29U)                     
+#define USB_OTG_GINTMSK_DISCINT_Msk                  (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                      USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos                    (30U)                     
+#define USB_OTG_GINTMSK_SRQIM_Msk                    (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                        USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                     (31U)                     
+#define USB_OTG_GINTMSK_WUIM_Msk                     (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                         USB_OTG_GINTMSK_WUIM_Msk  /*!< Resume/remote wakeup detected interrupt mask */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                     (0U)                      
+#define USB_OTG_DAINT_IEPINT_Msk                     (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                         USB_OTG_DAINT_IEPINT_Msk  /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos                     (16U)                     
+#define USB_OTG_DAINT_OEPINT_Msk                     (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                         USB_OTG_DAINT_OEPINT_Msk  /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos                  (0U)                      
+#define USB_OTG_HAINTMSK_HAINTM_Msk                  (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                      USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                    (0U)                      
+#define USB_OTG_GRXSTSP_EPNUM_Msk                    (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                        USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos                     (4U)                      
+#define USB_OTG_GRXSTSP_BCNT_Msk                     (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                         USB_OTG_GRXSTSP_BCNT_Msk  /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                     (15U)                     
+#define USB_OTG_GRXSTSP_DPID_Msk                     (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                         USB_OTG_GRXSTSP_DPID_Msk  /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos                   (17U)                     
+#define USB_OTG_GRXSTSP_PKTSTS_Msk                   (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                       USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                    (0U)                      
+#define USB_OTG_DAINTMSK_IEPM_Msk                    (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                        USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                    (16U)                     
+#define USB_OTG_DAINTMSK_OEPM_Msk                    (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                        USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                            (0U)                      
+#define USB_OTG_CHNUM_Msk                            (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM                                USB_OTG_CHNUM_Msk         /*!< Channel number */
+#define USB_OTG_CHNUM_0                              (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                              (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                              (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                              (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                             (4U)                      
+#define USB_OTG_BCNT_Msk                             (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                                 USB_OTG_BCNT_Msk          /*!< Byte count */                                                                             
+#define USB_OTG_DPID_Pos                             (15U)                     
+#define USB_OTG_DPID_Msk                             (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID                                 USB_OTG_DPID_Msk          /*!< Data PID */
+#define USB_OTG_DPID_0                               (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1                               (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos                           (17U)                     
+#define USB_OTG_PKTSTS_Msk                           (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                               USB_OTG_PKTSTS_Msk        /*!< Packet status */
+#define USB_OTG_PKTSTS_0                             (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                             (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                             (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                             (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos                            (0U)                      
+#define USB_OTG_EPNUM_Msk                            (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM                                USB_OTG_EPNUM_Msk         /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                              (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                              (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                              (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                              (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos                           (21U)                     
+#define USB_OTG_FRMNUM_Msk                           (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                               USB_OTG_FRMNUM_Msk        /*!< Frame number */
+#define USB_OTG_FRMNUM_0                             (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                             (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                             (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                             (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                            (0U)                      
+#define USB_OTG_CHNUM_Msk                            (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM                                USB_OTG_CHNUM_Msk         /*!< Channel number */
+#define USB_OTG_CHNUM_0                              (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                              (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                              (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                              (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                             (4U)                      
+#define USB_OTG_BCNT_Msk                             (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                                 USB_OTG_BCNT_Msk          /*!< Byte count */                                                                         
+#define USB_OTG_DPID_Pos                             (15U)                     
+#define USB_OTG_DPID_Msk                             (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID                                 USB_OTG_DPID_Msk          /*!< Data PID */
+#define USB_OTG_DPID_0                               (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1                               (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos                           (17U)                     
+#define USB_OTG_PKTSTS_Msk                           (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                               USB_OTG_PKTSTS_Msk        /*!< Packet status */
+#define USB_OTG_PKTSTS_0                             (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                             (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                             (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                             (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos                            (0U)                      
+#define USB_OTG_EPNUM_Msk                            (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM                                USB_OTG_EPNUM_Msk         /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                              (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                              (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                              (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                              (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos                           (21U)                     
+#define USB_OTG_FRMNUM_Msk                           (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                               USB_OTG_FRMNUM_Msk        /*!< Frame number */
+#define USB_OTG_FRMNUM_0                             (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                             (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                             (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                             (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                     (0U)                      
+#define USB_OTG_GRXFSIZ_RXFD_Msk                     (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                         USB_OTG_GRXFSIZ_RXFD_Msk  /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos                  (0U)                      
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk                  (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                      USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                          (0U)                      
+#define USB_OTG_NPTXFSA_Msk                          (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                              USB_OTG_NPTXFSA_Msk       /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                           (16U)                     
+#define USB_OTG_NPTXFD_Msk                           (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                               USB_OTG_NPTXFD_Msk        /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos                           (0U)                      
+#define USB_OTG_TX0FSA_Msk                           (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                               USB_OTG_TX0FSA_Msk        /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos                            (16U)                     
+#define USB_OTG_TX0FD_Msk                            (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                                USB_OTG_TX0FD_Msk         /*!< Endpoint 0 TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos                (0U)                      
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk                (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                    USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos                (0U)                      
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk                (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                    USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos                (16U)                     
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk                (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                    USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0                  (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1                  (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2                  (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3                  (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4                  (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5                  (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6                  (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7                  (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos                (24U)                     
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk                (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                    USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0                  (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1                  (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2                  (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3                  (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4                  (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5                  (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6                  (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ***************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos              (0U)                      
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN                  USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos                 (1U)                      
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk                 (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                     USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos                 (2U)                      
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk                 (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                     USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0                   (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1                   (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2                   (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3                   (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4                   (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5                   (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6                   (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7                   (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8                   (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos                  (16U)                     
+#define USB_OTG_DTHRCTL_RXTHREN_Msk                  (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                      USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos                 (17U)                     
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk                 (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                     USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0                   (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1                   (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2                   (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3                   (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4                   (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5                   (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6                   (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7                   (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8                   (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                    (27U)                     
+#define USB_OTG_DTHRCTL_ARPEN_Msk                    (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                        USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ***************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos             (0U)                      
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk             (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM                 USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos                 (1U)                      
+#define USB_OTG_DEACHINT_IEP1INT_Msk                 (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                     USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos                 (17U)                     
+#define USB_OTG_DEACHINT_OEP1INT_Msk                 (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                     USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_DCDET_Pos                      (0U)                      
+#define USB_OTG_GCCFG_DCDET_Msk                      (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET                          USB_OTG_GCCFG_DCDET_Msk   /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos                       (1U)                      
+#define USB_OTG_GCCFG_PDET_Msk                       (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET                           USB_OTG_GCCFG_PDET_Msk    /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos                       (2U)                      
+#define USB_OTG_GCCFG_SDET_Msk                       (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET                           USB_OTG_GCCFG_SDET_Msk    /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos                     (3U)                      
+#define USB_OTG_GCCFG_PS2DET_Msk                     (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET                         USB_OTG_GCCFG_PS2DET_Msk  /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos                     (16U)                     
+#define USB_OTG_GCCFG_PWRDWN_Msk                     (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                         USB_OTG_GCCFG_PWRDWN_Msk  /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos                      (17U)                     
+#define USB_OTG_GCCFG_BCDEN_Msk                      (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN                          USB_OTG_GCCFG_BCDEN_Msk   /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos                      (18U)                     
+#define USB_OTG_GCCFG_DCDEN_Msk                      (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN                          USB_OTG_GCCFG_DCDEN_Msk   /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos                       (19U)                     
+#define USB_OTG_GCCFG_PDEN_Msk                       (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN                           USB_OTG_GCCFG_PDEN_Msk    /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos                       (20U)                     
+#define USB_OTG_GCCFG_SDEN_Msk                       (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN                           USB_OTG_GCCFG_SDEN_Msk    /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos                      (21U)                     
+#define USB_OTG_GCCFG_VBDEN_Msk                      (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN                          USB_OTG_GCCFG_VBDEN_Msk   /*!< Secondary detection (SD) mode enable */
+
+/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_DISABLEVBUS_Pos               (6U)                      
+#define USB_OTG_GPWRDN_DISABLEVBUS_Msk               (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */
+#define USB_OTG_GPWRDN_DISABLEVBUS                   USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos             (1U)                      
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk             (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM                 USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos             (17U)                     
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk             (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                 USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos                   (0U)                      
+#define USB_OTG_CID_PRODUCT_ID_Msk                   (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                       USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+
+/********************  Bit definition for USB_OTG_GHWCFG3 register  ********************/
+#define USB_OTG_GHWCFG3_LPMMode_Pos                  (14U)                     
+#define USB_OTG_GHWCFG3_LPMMode_Msk                  (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */
+#define USB_OTG_GHWCFG3_LPMMode                      USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ 
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_ENBESL_Pos                   (28U)                     
+#define USB_OTG_GLPMCFG_ENBESL_Msk                   (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                       USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ 
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos               (25U)                     
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk               (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS                   USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ 
+#define USB_OTG_GLPMCFG_SNDLPM_Pos                   (24U)                     
+#define USB_OTG_GLPMCFG_SNDLPM_Msk                   (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                       USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ 
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos                  (21U)                     
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk                  (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                      USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ 
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos                 (17U)                     
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk                 (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                     USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ 
+#define USB_OTG_GLPMCFG_L1ResumeOK_Pos               (16U)                     
+#define USB_OTG_GLPMCFG_L1ResumeOK_Msk               (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1ResumeOK                   USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ 
+#define USB_OTG_GLPMCFG_SLPSTS_Pos                   (15U)                     
+#define USB_OTG_GLPMCFG_SLPSTS_Msk                   (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                       USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ 
+#define USB_OTG_GLPMCFG_LPMRSP_Pos                   (13U)                     
+#define USB_OTG_GLPMCFG_LPMRSP_Msk                   (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                       USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ 
+#define USB_OTG_GLPMCFG_L1DSEN_Pos                   (12U)                     
+#define USB_OTG_GLPMCFG_L1DSEN_Msk                   (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                       USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ 
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos                 (8U)                      
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk                 (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                     USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ 
+#define USB_OTG_GLPMCFG_L1SSEN_Pos                   (7U)                      
+#define USB_OTG_GLPMCFG_L1SSEN_Msk                   (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                       USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ 
+#define USB_OTG_GLPMCFG_REMWAKE_Pos                  (6U)                      
+#define USB_OTG_GLPMCFG_REMWAKE_Msk                  (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                      USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ 
+#define USB_OTG_GLPMCFG_BESL_Pos                     (2U)                      
+#define USB_OTG_GLPMCFG_BESL_Msk                     (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                         USB_OTG_GLPMCFG_BESL_Msk  /* BESL value received with last ACKed LPM Token  */
+#define USB_OTG_GLPMCFG_LPMACK_Pos                   (1U)                      
+#define USB_OTG_GLPMCFG_LPMACK_Msk                   (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                       USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                    (0U)                      
+#define USB_OTG_GLPMCFG_LPMEN_Msk                    (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                        USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable  */
+
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos               (0U)                      
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk               (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos                (1U)                      
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk                (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos                 (3U)                      
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk                 (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                     USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos           (4U)                      
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos             (5U)                      
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos             (6U)                      
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos              (8U)                      
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk              (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos                 (9U)                      
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk                 (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                     USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos                (13U)                     
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk                (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                       (0U)                      
+#define USB_OTG_HPRT_PCSTS_Msk                       (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                           USB_OTG_HPRT_PCSTS_Msk    /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos                       (1U)                      
+#define USB_OTG_HPRT_PCDET_Msk                       (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                           USB_OTG_HPRT_PCDET_Msk    /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos                        (2U)                      
+#define USB_OTG_HPRT_PENA_Msk                        (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                            USB_OTG_HPRT_PENA_Msk     /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos                     (3U)                      
+#define USB_OTG_HPRT_PENCHNG_Msk                     (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                         USB_OTG_HPRT_PENCHNG_Msk  /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                        (4U)                      
+#define USB_OTG_HPRT_POCA_Msk                        (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                            USB_OTG_HPRT_POCA_Msk     /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos                     (5U)                      
+#define USB_OTG_HPRT_POCCHNG_Msk                     (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                         USB_OTG_HPRT_POCCHNG_Msk  /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos                        (6U)                      
+#define USB_OTG_HPRT_PRES_Msk                        (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                            USB_OTG_HPRT_PRES_Msk     /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos                       (7U)                      
+#define USB_OTG_HPRT_PSUSP_Msk                       (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                           USB_OTG_HPRT_PSUSP_Msk    /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos                        (8U)                      
+#define USB_OTG_HPRT_PRST_Msk                        (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                            USB_OTG_HPRT_PRST_Msk     /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos                       (10U)                     
+#define USB_OTG_HPRT_PLSTS_Msk                       (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                           USB_OTG_HPRT_PLSTS_Msk    /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                         (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                         (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                        (12U)                     
+#define USB_OTG_HPRT_PPWR_Msk                        (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                            USB_OTG_HPRT_PPWR_Msk     /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                       (13U)                     
+#define USB_OTG_HPRT_PTCTL_Msk                       (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                           USB_OTG_HPRT_PTCTL_Msk    /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                         (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                         (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                         (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                         (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                        (17U)                     
+#define USB_OTG_HPRT_PSPD_Msk                        (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                            USB_OTG_HPRT_PSPD_Msk     /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                          (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                          (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos               (0U)                      
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk               (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos                (1U)                      
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk                (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos                 (3U)                      
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk                 (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                     USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos           (4U)                      
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos             (5U)                      
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos             (6U)                      
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos              (8U)                      
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk              (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos                 (9U)                      
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk                 (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                     USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos               (12U)                     
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk               (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos                (13U)                     
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk                (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos               (14U)                     
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk               (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos                   (0U)                      
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk                   (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                       USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos                   (16U)                     
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk                   (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                       USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                    (0U)                      
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                    (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                        USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos                   (15U)                     
+#define USB_OTG_DIEPCTL_USBAEP_Msk                   (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                       USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos               (16U)                     
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk               (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID                   USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos                   (17U)                     
+#define USB_OTG_DIEPCTL_NAKSTS_Msk                   (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                       USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+                                                                             
+#define USB_OTG_DIEPCTL_EPTYP_Pos                    (18U)                     
+#define USB_OTG_DIEPCTL_EPTYP_Msk                    (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                        USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                      (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                      (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                    (21U)                     
+#define USB_OTG_DIEPCTL_STALL_Msk                    (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                        USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+                                                                             
+#define USB_OTG_DIEPCTL_TXFNUM_Pos                   (22U)                     
+#define USB_OTG_DIEPCTL_TXFNUM_Msk                   (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                       USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                     (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                     (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                     (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                     (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                     (26U)                     
+#define USB_OTG_DIEPCTL_CNAK_Msk                     (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                         USB_OTG_DIEPCTL_CNAK_Msk  /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                     (27U)                     
+#define USB_OTG_DIEPCTL_SNAK_Msk                     (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                         USB_OTG_DIEPCTL_SNAK_Msk  /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos           (28U)                     
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk           (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM               USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos                  (29U)                     
+#define USB_OTG_DIEPCTL_SODDFRM_Msk                  (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                      USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                    (30U)                     
+#define USB_OTG_DIEPCTL_EPDIS_Msk                    (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                        USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                    (31U)                     
+#define USB_OTG_DIEPCTL_EPENA_Msk                    (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                        USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                     (0U)                      
+#define USB_OTG_HCCHAR_MPSIZ_Msk                     (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                         USB_OTG_HCCHAR_MPSIZ_Msk  /*!< Maximum packet size */
+                                                                              
+#define USB_OTG_HCCHAR_EPNUM_Pos                     (11U)                     
+#define USB_OTG_HCCHAR_EPNUM_Msk                     (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                         USB_OTG_HCCHAR_EPNUM_Msk  /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                       (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                       (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                       (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                       (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                     (15U)                     
+#define USB_OTG_HCCHAR_EPDIR_Msk                     (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                         USB_OTG_HCCHAR_EPDIR_Msk  /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                     (17U)                     
+#define USB_OTG_HCCHAR_LSDEV_Msk                     (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                         USB_OTG_HCCHAR_LSDEV_Msk  /*!< Low-speed device */
+                                                                              
+#define USB_OTG_HCCHAR_EPTYP_Pos                     (18U)                     
+#define USB_OTG_HCCHAR_EPTYP_Msk                     (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                         USB_OTG_HCCHAR_EPTYP_Msk  /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                       (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                       (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+                                                                              
+#define USB_OTG_HCCHAR_MC_Pos                        (20U)                     
+#define USB_OTG_HCCHAR_MC_Msk                        (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                            USB_OTG_HCCHAR_MC_Msk     /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                          (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                          (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+                                                                              
+#define USB_OTG_HCCHAR_DAD_Pos                       (22U)                     
+#define USB_OTG_HCCHAR_DAD_Msk                       (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                           USB_OTG_HCCHAR_DAD_Msk    /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                         (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                         (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                         (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                         (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                         (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                         (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                         (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                    (29U)                     
+#define USB_OTG_HCCHAR_ODDFRM_Msk                    (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                        USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                     (30U)                     
+#define USB_OTG_HCCHAR_CHDIS_Msk                     (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                         USB_OTG_HCCHAR_CHDIS_Msk  /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                     (31U)                     
+#define USB_OTG_HCCHAR_CHENA_Msk                     (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                         USB_OTG_HCCHAR_CHENA_Msk  /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos                   (0U)                      
+#define USB_OTG_HCSPLT_PRTADDR_Msk                   (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                       USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                     (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                     (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                     (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                     (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                     (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                     (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                     (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+                                                                               
+#define USB_OTG_HCSPLT_HUBADDR_Pos                   (7U)                      
+#define USB_OTG_HCSPLT_HUBADDR_Msk                   (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                       USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                     (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                     (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                     (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                     (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                     (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                     (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                     (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+                                                                               
+#define USB_OTG_HCSPLT_XACTPOS_Pos                   (14U)                     
+#define USB_OTG_HCSPLT_XACTPOS_Msk                   (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                       USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                     (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                     (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos                 (16U)                     
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk                 (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                     USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos                   (31U)                     
+#define USB_OTG_HCSPLT_SPLITEN_Msk                   (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                       USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                       (0U)                      
+#define USB_OTG_HCINT_XFRC_Msk                       (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                           USB_OTG_HCINT_XFRC_Msk    /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                        (1U)                      
+#define USB_OTG_HCINT_CHH_Msk                        (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                            USB_OTG_HCINT_CHH_Msk     /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                     (2U)                      
+#define USB_OTG_HCINT_AHBERR_Msk                     (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                         USB_OTG_HCINT_AHBERR_Msk  /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                      (3U)                      
+#define USB_OTG_HCINT_STALL_Msk                      (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                          USB_OTG_HCINT_STALL_Msk   /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                        (4U)                      
+#define USB_OTG_HCINT_NAK_Msk                        (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                            USB_OTG_HCINT_NAK_Msk     /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                        (5U)                      
+#define USB_OTG_HCINT_ACK_Msk                        (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                            USB_OTG_HCINT_ACK_Msk     /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                       (6U)                      
+#define USB_OTG_HCINT_NYET_Msk                       (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                           USB_OTG_HCINT_NYET_Msk    /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                      (7U)                      
+#define USB_OTG_HCINT_TXERR_Msk                      (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                          USB_OTG_HCINT_TXERR_Msk   /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                      (8U)                      
+#define USB_OTG_HCINT_BBERR_Msk                      (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                          USB_OTG_HCINT_BBERR_Msk   /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                      (9U)                      
+#define USB_OTG_HCINT_FRMOR_Msk                      (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                          USB_OTG_HCINT_FRMOR_Msk   /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                      (10U)                     
+#define USB_OTG_HCINT_DTERR_Msk                      (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                          USB_OTG_HCINT_DTERR_Msk   /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                     (0U)                      
+#define USB_OTG_DIEPINT_XFRC_Msk                     (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                         USB_OTG_DIEPINT_XFRC_Msk  /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos                   (1U)                      
+#define USB_OTG_DIEPINT_EPDISD_Msk                   (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                       USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos                      (3U)                      
+#define USB_OTG_DIEPINT_TOC_Msk                      (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                          USB_OTG_DIEPINT_TOC_Msk   /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos                   (4U)                      
+#define USB_OTG_DIEPINT_ITTXFE_Msk                   (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                       USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos                   (6U)                      
+#define USB_OTG_DIEPINT_INEPNE_Msk                   (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                       USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                     (7U)                      
+#define USB_OTG_DIEPINT_TXFE_Msk                     (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                         USB_OTG_DIEPINT_TXFE_Msk  /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos               (8U)                      
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk               (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN                   USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                      (9U)                      
+#define USB_OTG_DIEPINT_BNA_Msk                      (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                          USB_OTG_DIEPINT_BNA_Msk   /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos                (11U)                     
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk                (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                    USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                     (12U)                     
+#define USB_OTG_DIEPINT_BERR_Msk                     (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                         USB_OTG_DIEPINT_BERR_Msk  /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                      (13U)                     
+#define USB_OTG_DIEPINT_NAK_Msk                      (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                          USB_OTG_DIEPINT_NAK_Msk   /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos                   (0U)                      
+#define USB_OTG_HCINTMSK_XFRCM_Msk                   (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                       USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                    (1U)                      
+#define USB_OTG_HCINTMSK_CHHM_Msk                    (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                        USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos                  (2U)                      
+#define USB_OTG_HCINTMSK_AHBERR_Msk                  (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                      USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos                  (3U)                      
+#define USB_OTG_HCINTMSK_STALLM_Msk                  (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                      USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                    (4U)                      
+#define USB_OTG_HCINTMSK_NAKM_Msk                    (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                        USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                    (5U)                      
+#define USB_OTG_HCINTMSK_ACKM_Msk                    (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                        USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                    (6U)                      
+#define USB_OTG_HCINTMSK_NYET_Msk                    (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                        USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos                  (7U)                      
+#define USB_OTG_HCINTMSK_TXERRM_Msk                  (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                      USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos                  (8U)                      
+#define USB_OTG_HCINTMSK_BBERRM_Msk                  (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                      USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos                  (9U)                      
+#define USB_OTG_HCINTMSK_FRMORM_Msk                  (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                      USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos                  (10U)                     
+#define USB_OTG_HCINTMSK_DTERRM_Msk                  (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                      USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos                  (0U)                      
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk                  (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                      USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos                  (19U)                     
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk                  (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                      USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos                  (29U)                     
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk                  (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                      USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                    (0U)                      
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                    (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                        USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                    (19U)                     
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                    (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                        USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                    (31U)                     
+#define USB_OTG_HCTSIZ_DOPING_Msk                    (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                        USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                      (29U)                     
+#define USB_OTG_HCTSIZ_DPID_Msk                      (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                          USB_OTG_HCTSIZ_DPID_Msk   /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                        (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                        (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos                  (0U)                      
+#define USB_OTG_DIEPDMA_DMAADDR_Msk                  (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                      USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                    (0U)                      
+#define USB_OTG_HCDMA_DMAADDR_Msk                    (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                        USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos                (0U)                      
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk                (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                    USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos                 (0U)                      
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk                 (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                     USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos                 (16U)                     
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk                 (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                     USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                    (0U)                      
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                    (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                        USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos                   (15U)                     
+#define USB_OTG_DOEPCTL_USBAEP_Msk                   (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                       USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos                   (17U)                     
+#define USB_OTG_DOEPCTL_NAKSTS_Msk                   (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                       USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos           (28U)                     
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk           (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM               USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos                  (29U)                     
+#define USB_OTG_DOEPCTL_SODDFRM_Msk                  (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                      USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                    (18U)                     
+#define USB_OTG_DOEPCTL_EPTYP_Msk                    (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                        USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                      (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                      (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                     (20U)                     
+#define USB_OTG_DOEPCTL_SNPM_Msk                     (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                         USB_OTG_DOEPCTL_SNPM_Msk  /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                    (21U)                     
+#define USB_OTG_DOEPCTL_STALL_Msk                    (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                        USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                     (26U)                     
+#define USB_OTG_DOEPCTL_CNAK_Msk                     (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                         USB_OTG_DOEPCTL_CNAK_Msk  /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                     (27U)                     
+#define USB_OTG_DOEPCTL_SNAK_Msk                     (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                         USB_OTG_DOEPCTL_SNAK_Msk  /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                    (30U)                     
+#define USB_OTG_DOEPCTL_EPDIS_Msk                    (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                        USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                    (31U)                     
+#define USB_OTG_DOEPCTL_EPENA_Msk                    (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                        USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                     (0U)                      
+#define USB_OTG_DOEPINT_XFRC_Msk                     (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                         USB_OTG_DOEPINT_XFRC_Msk  /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos                   (1U)                      
+#define USB_OTG_DOEPINT_EPDISD_Msk                   (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                       USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos                     (3U)                      
+#define USB_OTG_DOEPINT_STUP_Msk                     (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                         USB_OTG_DOEPINT_STUP_Msk  /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos                  (4U)                      
+#define USB_OTG_DOEPINT_OTEPDIS_Msk                  (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                      USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos                  (6U)                      
+#define USB_OTG_DOEPINT_B2BSTUP_Msk                  (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                      USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos                     (14U)                     
+#define USB_OTG_DOEPINT_NYET_Msk                     (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                         USB_OTG_DOEPINT_NYET_Msk  /*!< NYET interrupt */
+
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos                  (0U)                      
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk                  (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                      USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos                  (19U)                     
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk                  (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                      USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos                 (29U)                     
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk                 (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                     USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0                   (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1                   (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos                  (0U)                      
+#define USB_OTG_PCGCCTL_STOPCLK_Msk                  (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                      USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos                  (1U)                      
+#define USB_OTG_PCGCCTL_GATECLK_Msk                  (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                      USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos                  (4U)                      
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk                  (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                      USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************* AES Instances ********************************/
+#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
+
+/******************************** CAN Instances ******************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                        ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+                                                ((INSTANCE) == DFSDM1_Filter1) || \
+                                                ((INSTANCE) == DFSDM1_Filter2) || \
+                                                ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+                                                 ((INSTANCE) == DFSDM1_Channel1) || \
+                                                 ((INSTANCE) == DFSDM1_Channel2) || \
+                                                 ((INSTANCE) == DFSDM1_Channel3) || \
+                                                 ((INSTANCE) == DFSDM1_Channel4) || \
+                                                 ((INSTANCE) == DFSDM1_Channel5) || \
+                                                 ((INSTANCE) == DFSDM1_Channel6) || \
+                                                 ((INSTANCE) == DFSDM1_Channel7))
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+                                       ((INSTANCE) == DMA1_Channel2) || \
+                                       ((INSTANCE) == DMA1_Channel3) || \
+                                       ((INSTANCE) == DMA1_Channel4) || \
+                                       ((INSTANCE) == DMA1_Channel5) || \
+                                       ((INSTANCE) == DMA1_Channel6) || \
+                                       ((INSTANCE) == DMA1_Channel7) || \
+                                       ((INSTANCE) == DMA2_Channel1) || \
+                                       ((INSTANCE) == DMA2_Channel2) || \
+                                       ((INSTANCE) == DMA2_Channel3) || \
+                                       ((INSTANCE) == DMA2_Channel4) || \
+                                       ((INSTANCE) == DMA2_Channel5) || \
+                                       ((INSTANCE) == DMA2_Channel6) || \
+                                       ((INSTANCE) == DMA2_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH))
+
+/******************************* GPIO AF Instances ****************************/
+/* On L4, all GPIO Bank support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On L4, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************* LCD Instances ********************************/
+#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
+
+/******************************* HCD Instances *******************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+                                         ((INSTANCE) == OPAMP2))
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
+
+/******************************* PCD Instances *******************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/******************************* QSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/******************************** SAI Instances *******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+                                       ((INSTANCE) == SAI1_Block_B) || \
+                                       ((INSTANCE) == SAI2_Block_A) || \
+                                       ((INSTANCE) == SAI2_Block_B))
+
+/****************************** SDMMC Instances *******************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                         ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
+                                               ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8)    || \
+                                            ((INSTANCE) == TIM15)   || \
+                                            ((INSTANCE) == TIM16)   || \
+                                            ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM8)   || \
+                                               ((INSTANCE) == TIM15)  || \
+                                               ((INSTANCE) == TIM16)  || \
+                                               ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM3) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM4) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM5) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM8) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM17) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM8) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
+                                                    ((INSTANCE) == TIM2)    || \
+                                                    ((INSTANCE) == TIM3)    || \
+                                                    ((INSTANCE) == TIM4)    || \
+                                                    ((INSTANCE) == TIM5)    || \
+                                                    ((INSTANCE) == TIM8)    || \
+                                                    ((INSTANCE) == TIM15)   || \
+                                                    ((INSTANCE) == TIM16)   || \
+                                                    ((INSTANCE) == TIM17))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM8)   || \
+                                                     ((INSTANCE) == TIM15)  || \
+                                                     ((INSTANCE) == TIM16)  || \
+                                                     ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                      ((INSTANCE) == TIM2)  || \
+                                                      ((INSTANCE) == TIM3)  || \
+                                                      ((INSTANCE) == TIM4)  || \
+                                                      ((INSTANCE) == TIM5)  || \
+                                                      ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                         ((INSTANCE) == TIM2)   || \
+                                                         ((INSTANCE) == TIM3)   || \
+                                                         ((INSTANCE) == TIM4)   || \
+                                                         ((INSTANCE) == TIM5))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM8))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                             ((INSTANCE) == TIM2)  || \
+                                             ((INSTANCE) == TIM3)  || \
+                                             ((INSTANCE) == TIM8))
+      
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM6)  || \
+                                            ((INSTANCE) == TIM7)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
+                                                       ((INSTANCE) == TIM2) || \
+                                                       ((INSTANCE) == TIM3) || \
+                                                       ((INSTANCE) == TIM4) || \
+                                                       ((INSTANCE) == TIM5) || \
+                                                       ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15) || \
+                                            ((INSTANCE) == TIM16) || \
+                                            ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                       ((INSTANCE) == TIM8)  || \
+                                                       ((INSTANCE) == TIM15) || \
+                                                       ((INSTANCE) == TIM16) || \
+                                                       ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3) || \
+                                                            ((INSTANCE) == UART4)  || \
+                                                            ((INSTANCE) == UART5))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == UART4)  || \
+                                                      ((INSTANCE) == UART5)  || \
+                                                      ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                 ((INSTANCE) == USART2) || \
+                                                 ((INSTANCE) == USART3) || \
+                                                 ((INSTANCE) == UART4)  || \
+                                                 ((INSTANCE) == UART5)  || \
+                                                 ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == UART4)  || \
+                                           ((INSTANCE) == UART5)  || \
+                                           ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                          ((INSTANCE) == USART2) || \
+                                          ((INSTANCE) == USART3) || \
+                                          ((INSTANCE) == UART4)  || \
+                                          ((INSTANCE) == UART5))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == UART4)  || \
+                                                      ((INSTANCE) == UART5)  || \
+                                                      ((INSTANCE) == LPUART1))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5))
+
+/********************* USART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/**
+  * @}
+  */
+
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32L4xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */ 
+/*  product lines within the same STM32L4 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn                      ADC1_2_IRQn
+#define TIM1_TRG_COM_IRQn              TIM1_TRG_COM_TIM17_IRQn
+#define TIM8_IRQn                      TIM8_UP_IRQn
+#define DFSDM0_IRQn                    DFSDM1_FLT0_IRQn
+#define DFSDM1_IRQn                    DFSDM1_FLT1_IRQn
+#define DFSDM2_IRQn                    DFSDM1_FLT2_IRQn
+#define DFSDM3_IRQn                    DFSDM1_FLT3_IRQn
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler                ADC1_2_IRQHandler
+#define TIM1_TRG_COM_IRQHandler        TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM8_IRQHandler                TIM8_UP_IRQHandler
+#define DFSDM0_IRQHandler              DFSDM1_FLT0_IRQHandler
+#define DFSDM1_IRQHandler              DFSDM1_FLT1_IRQHandler
+#define DFSDM2_IRQHandler              DFSDM1_FLT2_IRQHandler
+#define DFSDM3_IRQHandler              DFSDM1_FLT3_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L486xx_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/TARGET_NUCLEO_L486RG/device/stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/TARGET_NUCLEO_L486RG/device/stm32l4xx.h
new file mode 100644
index 00000000000..1d744127dd8
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/TARGET_NUCLEO_L486RG/device/stm32l4xx.h
@@ -0,0 +1,241 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    29-April-2016
+  * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32L4xx device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral�s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx
+  * @{
+  */
+
+#ifndef __STM32L4xx_H
+#define __STM32L4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32L4)
+#define STM32L4
+#endif /* STM32L4 */
+
+/* Uncomment the line below according to the target STM32L4 device used in your
+   application
+  */
+
+#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
+    !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx)
+  /* #define STM32L431xx */   /*!< STM32L431xx Devices */
+  /* #define STM32L432xx */   /*!< STM32L432xx Devices */
+  /* #define STM32L433xx */   /*!< STM32L433xx Devices */
+  /* #define STM32L442xx */   /*!< STM32L442xx Devices */
+  /* #define STM32L443xx */   /*!< STM32L443xx Devices */
+  /* #define STM32L471xx */   /*!< STM32L471xx Devices */
+  /* #define STM32L475xx */   /*!< STM32L475xx Devices */
+  /* #define STM32L476xx */   /*!< STM32L476xx Devices */
+  /* #define STM32L485xx */   /*!< STM32L485xx Devices */
+  #define STM32L486xx         /*!< STM32L486xx Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.1.1
+  */
+#define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L4_CMSIS_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32L4_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32L4_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32L431xx)
+  #include "stm32l431xx.h"
+#elif defined(STM32L432xx)
+  #include "stm32l432xx.h"
+#elif defined(STM32L433xx)
+  #include "stm32l433xx.h"
+#elif defined(STM32L442xx)
+  #include "stm32l442xx.h"
+#elif defined(STM32L443xx)
+  #include "stm32l443xx.h"
+#elif defined(STM32L451xx)
+  #include "stm32l451xx.h"
+#elif defined(STM32L452xx)
+  #include "stm32l452xx.h"
+#elif defined(STM32L462xx)
+  #include "stm32l462xx.h"
+#elif defined(STM32L471xx)
+  #include "stm32l471xx.h"
+#elif defined(STM32L475xx)
+  #include "stm32l475xx.h"
+#elif defined(STM32L476xx)
+  #include "stm32l476xx.h"
+#elif defined(STM32L485xx)
+  #include "stm32l485xx.h"
+#elif defined(STM32L486xx)
+  #include "stm32l486xx.h"
+#elif defined(STM32L496xx)
+  #include "stm32l496xx.h"
+#elif defined(STM32L4A6xx)
+  #include "stm32l4a6xx.h"
+#elif defined(STM32L4R5xx)
+  #include "stm32l4r5xx.h"
+#elif defined(STM32L4R9xx)
+  #include "stm32l4r9xx.h"
+#elif defined(STM32L4S5xx)
+  #include "stm32l4s5xx.h"
+#elif defined(STM32L4S9xx)
+  #include "stm32l4s9xx.h"
+#else
+ #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_ARM_STD/startup_stm32l476xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_ARM_STD/startup_stm32l476xx.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_ARM_STD/startup_stm32l476xx.S
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_ARM_STD/startup_stm32l476xx.S
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_ARM_STD/stm32l476xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_ARM_STD/stm32l476xx.sct
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_ARM_STD/stm32l476xx.sct
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_ARM_STD/stm32l476xx.sct
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_ARM_STD/sys.cpp
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_ARM_STD/sys.cpp
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_ARM_STD/sys.cpp
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_IAR/startup_stm32l476xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_IAR/startup_stm32l476xx.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_IAR/startup_stm32l476xx.S
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_IAR/startup_stm32l476xx.S
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_IAR/stm32l476xx.icf b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_IAR/stm32l476xx.icf
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/TOOLCHAIN_IAR/stm32l476xx.icf
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/TOOLCHAIN_IAR/stm32l476xx.icf
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/cmsis.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/cmsis.h
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/cmsis.h
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/cmsis_nvic.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/cmsis_nvic.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/cmsis_nvic.c
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/cmsis_nvic.c
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/cmsis_nvic.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/cmsis_nvic.h
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/cmsis_nvic.h
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/hal_tick.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/hal_tick.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/hal_tick.c
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/hal_tick.c
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/hal_tick.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/hal_tick.h
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/hal_tick.h
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/stm32l4xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/stm32l4xx_hal_conf.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/stm32l4xx_hal_conf.h
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/stm32l4xx_hal_conf.h
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/system_stm32l4xx.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/system_stm32l4xx.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/system_stm32l4xx.c
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/system_stm32l4xx.c
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/system_stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/system_stm32l4xx.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device/system_stm32l4xx.h
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/system_stm32l4xx.h
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/objects.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/objects.h
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/objects.h
diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h
index 3f598f6c952..c46f27a052a 100644
--- a/targets/TARGET_STM/mbed_rtx.h
+++ b/targets/TARGET_STM/mbed_rtx.h
@@ -647,7 +647,7 @@
 #define OS_CLOCK                80000000
 #endif
 
-#elif defined(TARGET_STM32L476RG)
+#elif (defined(TARGET_STM32L476RG) || defined(TARGET_STM32L486RG))
 
 #ifndef INITIAL_SP
 #define INITIAL_SP              (0x20018000UL)
diff --git a/targets/targets.json b/targets/targets.json
index d05bf59ca64..7d6ea0c3f84 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -993,7 +993,7 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
-        "extra_labels": ["STM", "STM32L4", "STM32L476RG"],
+        "extra_labels": ["STM", "STM32L4", "STM32L476RG", "L476_L486"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "inherits": ["Target"],
         "detect_code": ["0765"],
@@ -1002,6 +1002,18 @@
         "release_versions": ["2", "5"],
         "device_name": "stm32l476rg"
     },
+    "NUCLEO_L486RG": {
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "default_toolchain": "ARM",
+        "extra_labels": ["STM", "STM32L4", "STM32L486RG", "L476_L486"],
+        "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
+        "inherits": ["Target"],
+        "detect_code": ["0827"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"],
+        "device_name": "stm32l486rg"
+    },
     "STM32F3XX": {
         "inherits": ["Target"],
         "core": "Cortex-M4",

From 899acb1627f0263354a5ebb35157cd3a4b91f397 Mon Sep 17 00:00:00 2001
From: adustm <adustm13@gmail.com>
Date: Tue, 11 Oct 2016 10:47:14 +0200
Subject: [PATCH 84/89] ADD NEW TARGET : NUCLEO_F756ZG, based on existing
 NUCLEO_F746ZG

---
 .../stm32f7_eth_init.c                        |    0
 .../PeripheralNames.h                         |    0
 .../PeripheralPins.c                          |    0
 .../PinNames.h                                |    0
 .../PortNames.h                               |    0
 .../TARGET_NUCLEO_F746ZG/device/stm32f746xx.h |    0
 .../TARGET_NUCLEO_F746ZG/device/stm32f7xx.h   |    0
 .../TARGET_NUCLEO_F756ZG/device/stm32f756xx.h | 9659 +++++++++++++++++
 .../TARGET_NUCLEO_F756ZG/device/stm32f7xx.h   |  216 +
 .../TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S |    0
 .../TOOLCHAIN_ARM_MICRO/stm32f746zg.sct       |    0
 .../TOOLCHAIN_ARM_STD/startup_stm32f746zg.S   |    0
 .../device/TOOLCHAIN_ARM_STD/stm32f746zg.sct  |    0
 .../device/TOOLCHAIN_ARM_STD/sys.cpp          |    0
 .../device/TOOLCHAIN_GCC_ARM/STM32F746ZG.ld   |    0
 .../TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S   |    0
 .../TOOLCHAIN_IAR/startup_stm32f746xx.S       |    0
 .../device/TOOLCHAIN_IAR/stm32f746zg.icf      |    0
 .../device/cmsis.h                            |    0
 .../device/cmsis_nvic.c                       |    0
 .../device/cmsis_nvic.h                       |    0
 .../device/hal_tick.c                         |    0
 .../device/hal_tick.h                         |    0
 .../device/stm32f7xx_hal_conf.h               |    0
 .../device/system_stm32f7xx.c                 |    0
 .../device/system_stm32f7xx.h                 |    0
 .../objects.h                                 |    0
 targets/TARGET_STM/mbed_rtx.h                 |    2 +-
 targets/targets.json                          |   15 +-
 29 files changed, 9890 insertions(+), 2 deletions(-)
 rename features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/stm32f7_eth_init.c (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/PeripheralNames.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/PeripheralPins.c (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/PinNames.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/PortNames.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{ => TARGET_F746_F756}/TARGET_NUCLEO_F746ZG/device/stm32f746xx.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{ => TARGET_F746_F756}/TARGET_NUCLEO_F746ZG/device/stm32f7xx.h (100%)
 create mode 100644 targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f756xx.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f7xx.h
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/TOOLCHAIN_ARM_MICRO/stm32f746zg.sct (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/TOOLCHAIN_ARM_STD/stm32f746zg.sct (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/TOOLCHAIN_ARM_STD/sys.cpp (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/TOOLCHAIN_GCC_ARM/STM32F746ZG.ld (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/TOOLCHAIN_IAR/startup_stm32f746xx.S (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/TOOLCHAIN_IAR/stm32f746zg.icf (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/cmsis.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/cmsis_nvic.c (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/cmsis_nvic.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/hal_tick.c (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/hal_tick.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/stm32f7xx_hal_conf.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/system_stm32f7xx.c (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/device/system_stm32f7xx.h (100%)
 rename targets/TARGET_STM/TARGET_STM32F7/{TARGET_NUCLEO_F746ZG => TARGET_F746_F756}/objects.h (100%)

diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/stm32f7_eth_init.c
similarity index 100%
rename from features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c
rename to features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/stm32f7_eth_init.c
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/PeripheralNames.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralNames.h
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/PeripheralNames.h
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/PeripheralPins.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PeripheralPins.c
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/PeripheralPins.c
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/PinNames.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PinNames.h
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/PinNames.h
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PortNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/PortNames.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/PortNames.h
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/PortNames.h
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/stm32f746xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F746ZG/device/stm32f746xx.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/stm32f746xx.h
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F746ZG/device/stm32f746xx.h
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/stm32f7xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F746ZG/device/stm32f7xx.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/stm32f7xx.h
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F746ZG/device/stm32f7xx.h
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f756xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f756xx.h
new file mode 100644
index 00000000000..286cf4ea6e0
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f756xx.h
@@ -0,0 +1,9659 @@
+/**
+  ******************************************************************************
+  * @file    stm32f756xx.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    22-April-2016
+  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral�s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32f756xx
+  * @{
+  */
+    
+#ifndef __STM32F756xx_H
+#define __STM32F756xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief STM32F7xx Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum
+{
+/******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M7 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M7 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M7 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M7 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M7 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M7 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M7 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
+  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+/**
+ * @brief Configuration of the Cortex-M7 Processor and Core Peripherals 
+ */
+#define __CM7_REV                 0x0001U  /*!< Cortex-M7 revision r0p1                       */
+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
+  
+  
+#include "system_stm32f7xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
+  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
+  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
+                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+  
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+  
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+  
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/** 
+  * @brief HDMI-CEC 
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
+}CEC_TypeDef;
+
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t  DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t   IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t        RESERVED0;   /*!< Reserved, 0x05                                                    */
+  uint16_t       RESERVED1;   /*!< Reserved, 0x06                                                    */
+  __IO uint32_t  CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t       RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t  INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t  POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/** 
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+  uint32_t      RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+  uint32_t      RESERVED1[2];
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+  uint32_t      RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+  uint32_t      RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+  uint32_t      RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+  uint32_t      RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+  uint32_t      RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+  uint32_t      RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+  __IO uint32_t RESERVED8;
+  __IO uint32_t PTPTSSR;
+  uint32_t      RESERVED9[565];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+  __IO uint32_t DMARSWTR;
+  uint32_t      RESERVED10[8];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
+  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
+  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
+  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;      /*!< FLASH access control register,     Address offset: 0x00 */
+  __IO uint32_t KEYR;     /*!< FLASH key register,                Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,         Address offset: 0x08 */
+  __IO uint32_t SR;       /*!< FLASH status register,             Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< FLASH control register,            Address offset: 0x10 */
+  __IO uint32_t OPTCR;    /*!< FLASH option control register ,    Address offset: 0x14 */
+  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1 ,  Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+
+/** 
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
+} FMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank3
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
+  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
+  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
+  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                          */
+  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+ 
+/** 
+  * @brief Flexible Memory Controller Bank5_6
+  */
+  
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
+} FMC_Bank5_6_TypeDef; 
+
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/** 
+  * @brief System configuration controller
+  */
+  
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
+  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */  
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */  
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+
+/** 
+  * @brief LCD-TFT Display Controller
+  */
+  
+typedef struct
+{
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
+} LTDC_TypeDef;  
+
+/** 
+  * @brief LCD-TFT Display layer x Controller
+  */
+  
+typedef struct
+{  
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
+  uint32_t      RESERVED0[2];  /*!< Reserved */
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
+  uint32_t      RESERVED1[3];  /*!< Reserved */
+  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
+  __IO uint32_t CSR1;  /*!< PWR power control/status register 2, Address offset: 0x04 */
+  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x08 */
+  __IO uint32_t CSR2;  /*!< PWR power control/status register 2, Address offset: 0x0C */
+} PWR_TypeDef;
+
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
+  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
+  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
+  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
+  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
+  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
+  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
+  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
+  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
+  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
+  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
+  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
+  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
+  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
+  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
+  __IO uint32_t DCKCFGR1;      /*!< RCC Dedicated Clocks configuration register1,                 Address offset: 0x8C */
+  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x90 */
+
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t reserved;   /*!< Reserved  */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/** 
+  * @brief Serial Audio Interface
+  */
+  
+typedef struct
+{
+  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/** 
+  * @brief SPDIF-RX Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */  
+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */ 
+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
+} SPDIFRX_TypeDef;
+
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMClock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+} SPI_TypeDef;
+
+/** 
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */                  
+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */    
+} QUADSPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare mode register5,       Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare mode register6,       Address offset: 0x5C */
+
+} TIM_TypeDef;
+
+/** 
+  * @brief LPTIMIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */
+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */
+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */                                               
+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+} USART_TypeDef;
+
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** 
+  * @brief Crypto Processor
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
+  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/** 
+  * @brief HASH
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
+  uint32_t      RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
+  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/** 
+  * @brief HASH_DIGEST
+  */
+  
+typedef struct 
+{
+  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */ 
+} HASH_DIGEST_TypeDef;
+
+/** 
+  * @brief RNG
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @}
+  */
+
+/** 
+  * @brief USB_OTG_Core_Registers
+  */
+typedef struct
+{
+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+  uint32_t  Reserved6;                /*!< Reserved                                     050h */ 
+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/** 
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+  uint32_t  Reserved20;          /*!< Reserved                     820h */
+  uint32_t Reserved9;            /*!< Reserved                     824h */
+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */  
+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */   
+} USB_OTG_DeviceTypeDef;
+
+
+/** 
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/** 
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/** 
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct 
+{
+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} USB_OTG_HostTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+  uint32_t Reserved[2];           /*!< Reserved                                      */
+} USB_OTG_HostChannelTypeDef;
+/**
+  * @}
+  */
+
+
+
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define RAMITCM_BASE           0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM  */
+#define FLASHITCM_BASE         0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory  accessible over ITCM              */                       
+#define FLASHAXI_BASE          0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI                */                       
+#define RAMDTCM_BASE           0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM                             */
+#define PERIPH_BASE            0x40000000U /*!< Base address of : AHB/ABP Peripherals                                                   */
+#define BKPSRAM_BASE           0x40024000U /*!< Base address of : Backup SRAM(4 KB)                                                     */
+#define QSPI_BASE              0x90000000U /*!< Base address of : QSPI memories  accessible over AXI                                    */
+#define FMC_R_BASE             0xA0000000U /*!< Base address of : FMC Control registers                                                 */
+#define QSPI_R_BASE            0xA0001000U /*!< Base address of : QSPI Control  registers                                               */
+#define SRAM1_BASE             0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB                                    */
+#define SRAM2_BASE             0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
+#define FLASH_END              0x080FFFFFU /*!< FLASH end address */
+
+/* Legacy define */
+#define FLASH_BASE     FLASHAXI_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
+#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
+#define I2C4_BASE             (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
+#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00U)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
+#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
+#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00U)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004U)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024U)
+#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U)
+/*!< AHB1 peripherals */
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
+#define UID_BASE              0x1FF0F420U                   /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE        0x1FF0F442U                   /*!< FLASH Size register base address */
+#define PACKAGESIZE_BASE      0x1FFF7BF0U                   /*!< Package size register base address */
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
+#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
+/*!< AHB2 peripherals */
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
+#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000U)
+#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400U)
+#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710U)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE               0x40040000U
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
+
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE) 
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
+#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH                ((HASH_TypeDef *) HASH_BASE)
+#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag                                 */
+#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion                                    */
+#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion                   */
+#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag                          */
+#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag                           */
+#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag                                         */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC                             */
+#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable                    */
+#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels               */
+#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion                  */
+#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels               */
+#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels              */
+#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels          */
+#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels           */
+#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution)                           */
+#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF                                       */
+#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion                                        */
+#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode                                    */
+#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC)                           */
+#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection                                  */
+#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment                                               */
+#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */
+
+/*******************  Bit definition for ADC_CSR register  ********************/
+#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag               */
+#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion                  */
+#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag        */
+#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag         */
+#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 Overrun flag                       */
+#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag               */
+#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion                  */
+#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag        */
+#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag         */
+#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 Overrun flag                       */
+#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag               */
+#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion                  */
+#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag        */
+#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag         */
+#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 Overrun flag                       */
+
+/* Legacy defines */
+#define  ADC_CSR_DOVR1                       ADC_CSR_OVR1
+#define  ADC_CSR_DOVR2                       ADC_CSR_OVR2
+#define  ADC_CSR_DOVR3                       ADC_CSR_OVR3
+
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */
+
+/*******************  Bit definition for ADC_CDR register  ********************/
+#define  ADC_CDR_DATA1                       0x0000FFFFU         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                       0xFFFF0000U         /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request            */
+#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request                */
+#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority            */
+#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode          */
+#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission       */
+#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode             */
+#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management      */
+#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset       */
+                                                                           
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define  CAN_MSR_INAK                        0x00000001U        /*!<Initialization Acknowledge  */
+#define  CAN_MSR_SLAK                        0x00000002U        /*!<Sleep Acknowledge           */
+#define  CAN_MSR_ERRI                        0x00000004U        /*!<Error Interrupt             */
+#define  CAN_MSR_WKUI                        0x00000008U        /*!<Wakeup Interrupt            */
+#define  CAN_MSR_SLAKI                       0x00000010U        /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         0x00000100U        /*!<Transmit Mode               */
+#define  CAN_MSR_RXM                         0x00000200U        /*!<Receive Mode                */
+#define  CAN_MSR_SAMP                        0x00000400U        /*!<Last Sample Point           */
+#define  CAN_MSR_RX                          0x00000800U        /*!<CAN Rx Signal               */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0      */
+#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0     */
+#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0   */
+#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0  */
+#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0      */
+#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1      */
+#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1     */
+#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1   */
+#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1  */
+#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1     */
+#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2      */
+#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2    */
+#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2  */
+#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2     */
+#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code                    */
+
+#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */
+
+#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define  CAN_RF0R_FMP0                       0x00000003U        /*!<FIFO 0 Message Pending        */
+#define  CAN_RF0R_FULL0                      0x00000008U        /*!<FIFO 0 Full                   */
+#define  CAN_RF0R_FOVR0                      0x00000010U        /*!<FIFO 0 Overrun                */
+#define  CAN_RF0R_RFOM0                      0x00000020U        /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define  CAN_RF1R_FMP1                       0x00000003U        /*!<FIFO 1 Message Pending        */
+#define  CAN_RF1R_FULL1                      0x00000008U        /*!<FIFO 1 Full                   */
+#define  CAN_RF1R_FOVR1                      0x00000010U        /*!<FIFO 1 Overrun                */
+#define  CAN_RF1R_RFOM1                      0x00000020U        /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable   */
+#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable              */
+#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable           */
+#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable   */
+#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable              */
+#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable           */
+#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable          */
+#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable          */
+#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable                */
+#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable        */
+#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable                  */
+#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable                 */
+#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable                  */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */
+
+#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */
+
+#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler           */
+#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1                */
+#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */
+#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */
+#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */
+#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */
+#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2                */
+#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */
+#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */
+#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */
+#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width  */
+#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */
+#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */
+#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug)        */
+#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode                   */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
+#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
+#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
+#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
+#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code     */
+#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
+#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
+#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
+#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
+#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code     */
+#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */
+#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
+#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension                       */
+#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
+#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code      */
+#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time  */
+#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp    */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
+#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */
+#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */
+#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */
+#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */
+#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */
+#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code   */
+#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define  CAN_FMR_FINIT                       ((uint8_t)0x01U)               /*!<Filter Init Mode */
+#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define  CAN_FM1R_FBM                        0x3FFFU            /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       0x0001U            /*!<Filter Init Mode bit 0  */
+#define  CAN_FM1R_FBM1                       0x0002U            /*!<Filter Init Mode bit 1  */
+#define  CAN_FM1R_FBM2                       0x0004U            /*!<Filter Init Mode bit 2  */
+#define  CAN_FM1R_FBM3                       0x0008U            /*!<Filter Init Mode bit 3  */
+#define  CAN_FM1R_FBM4                       0x0010U            /*!<Filter Init Mode bit 4  */
+#define  CAN_FM1R_FBM5                       0x0020U            /*!<Filter Init Mode bit 5  */
+#define  CAN_FM1R_FBM6                       0x0040U            /*!<Filter Init Mode bit 6  */
+#define  CAN_FM1R_FBM7                       0x0080U            /*!<Filter Init Mode bit 7  */
+#define  CAN_FM1R_FBM8                       0x0100U            /*!<Filter Init Mode bit 8  */
+#define  CAN_FM1R_FBM9                       0x0200U            /*!<Filter Init Mode bit 9  */
+#define  CAN_FM1R_FBM10                      0x0400U            /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      0x0800U            /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      0x1000U            /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      0x2000U            /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define  CAN_FS1R_FSC                        0x00003FFFU        /*!<Filter Scale Configuration        */
+#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0  */
+#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1  */
+#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2  */
+#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3  */
+#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4  */
+#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5  */
+#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6  */
+#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7  */
+#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8  */
+#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9  */
+#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define  CAN_FFA1R_FFA                       0x00003FFFU        /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                      0x00000001U        /*!<Filter FIFO Assignment for Filter 0 */
+#define  CAN_FFA1R_FFA1                      0x00000002U        /*!<Filter FIFO Assignment for Filter 1 */
+#define  CAN_FFA1R_FFA2                      0x00000004U        /*!<Filter FIFO Assignment for Filter 2 */
+#define  CAN_FFA1R_FFA3                      0x00000008U        /*!<Filter FIFO Assignment for Filter 3 */
+#define  CAN_FFA1R_FFA4                      0x00000010U        /*!<Filter FIFO Assignment for Filter 4 */
+#define  CAN_FFA1R_FFA5                      0x00000020U        /*!<Filter FIFO Assignment for Filter 5 */
+#define  CAN_FFA1R_FFA6                      0x00000040U        /*!<Filter FIFO Assignment for Filter 6 */
+#define  CAN_FFA1R_FFA7                      0x00000080U        /*!<Filter FIFO Assignment for Filter 7 */
+#define  CAN_FFA1R_FFA8                      0x00000100U        /*!<Filter FIFO Assignment for Filter 8 */
+#define  CAN_FFA1R_FFA9                      0x00000200U        /*!<Filter FIFO Assignment for Filter 9 */
+#define  CAN_FFA1R_FFA10                     0x00000400U        /*!<Filter FIFO Assignment for Filter 10 */
+#define  CAN_FFA1R_FFA11                     0x00000800U        /*!<Filter FIFO Assignment for Filter 11 */
+#define  CAN_FFA1R_FFA12                     0x00001000U        /*!<Filter FIFO Assignment for Filter 12 */
+#define  CAN_FFA1R_FFA13                     0x00002000U        /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define  CAN_FA1R_FACT                       0x00003FFFU        /*!<Filter Active    */
+#define  CAN_FA1R_FACT0                      0x00000001U        /*!<Filter 0 Active  */
+#define  CAN_FA1R_FACT1                      0x00000002U        /*!<Filter 1 Active  */
+#define  CAN_FA1R_FACT2                      0x00000004U        /*!<Filter 2 Active  */
+#define  CAN_FA1R_FACT3                      0x00000008U        /*!<Filter 3 Active  */
+#define  CAN_FA1R_FACT4                      0x00000010U        /*!<Filter 4 Active  */
+#define  CAN_FA1R_FACT5                      0x00000020U        /*!<Filter 5 Active  */
+#define  CAN_FA1R_FACT6                      0x00000040U        /*!<Filter 6 Active  */
+#define  CAN_FA1R_FACT7                      0x00000080U        /*!<Filter 7 Active  */
+#define  CAN_FA1R_FACT8                      0x00000100U        /*!<Filter 8 Active  */
+#define  CAN_FA1R_FACT9                      0x00000200U        /*!<Filter 9 Active  */
+#define  CAN_FA1R_FACT10                     0x00000400U        /*!<Filter 10 Active */
+#define  CAN_FA1R_FACT11                     0x00000800U        /*!<Filter 11 Active */
+#define  CAN_FA1R_FACT12                     0x00001000U        /*!<Filter 12 Active */
+#define  CAN_FA1R_FACT13                     0x00002000U        /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 HDMI-CEC (CEC)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define  CEC_CR_CECEN                        0x00000001U       /*!< CEC Enable                         */
+#define  CEC_CR_TXSOM                        0x00000002U       /*!< CEC Tx Start Of Message            */
+#define  CEC_CR_TXEOM                        0x00000004U       /*!< CEC Tx End Of Message              */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define  CEC_CFGR_SFT                        0x00000007U       /*!< CEC Signal Free Time               */
+#define  CEC_CFGR_RXTOL                      0x00000008U       /*!< CEC Tolerance                      */
+#define  CEC_CFGR_BRESTP                     0x00000010U       /*!< CEC Rx Stop                        */
+#define  CEC_CFGR_BREGEN                     0x00000020U       /*!< CEC Bit Rising Error generation    */
+#define  CEC_CFGR_LBPEGEN                    0x00000040U       /*!< CEC Long Period Error generation   */
+#define  CEC_CFGR_BRDNOGEN                   0x00000080U       /*!< CEC Broadcast no Error generation  */
+#define  CEC_CFGR_SFTOPT                     0x00000100U       /*!< CEC Signal Free Time optional      */
+#define  CEC_CFGR_OAR                        0x7FFF0000U       /*!< CEC Own Address                    */
+#define  CEC_CFGR_LSTN                       0x80000000U       /*!< CEC Listen mode                    */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define  CEC_TXDR_TXD                        0x000000FFU       /*!< CEC Tx Data                        */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define  CEC_TXDR_RXD                        0x000000FFU       /*!< CEC Rx Data                        */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define  CEC_ISR_RXBR                        0x00000001U       /*!< CEC Rx-Byte Received                   */
+#define  CEC_ISR_RXEND                       0x00000002U       /*!< CEC End Of Reception                   */
+#define  CEC_ISR_RXOVR                       0x00000004U       /*!< CEC Rx-Overrun                         */
+#define  CEC_ISR_BRE                         0x00000008U       /*!< CEC Rx Bit Rising Error                */
+#define  CEC_ISR_SBPE                        0x00000010U       /*!< CEC Rx Short Bit period Error          */
+#define  CEC_ISR_LBPE                        0x00000020U       /*!< CEC Rx Long Bit period Error           */
+#define  CEC_ISR_RXACKE                      0x00000040U       /*!< CEC Rx Missing Acknowledge             */
+#define  CEC_ISR_ARBLST                      0x00000080U       /*!< CEC Arbitration Lost                   */
+#define  CEC_ISR_TXBR                        0x00000100U       /*!< CEC Tx Byte Request                    */
+#define  CEC_ISR_TXEND                       0x00000200U       /*!< CEC End of Transmission                */
+#define  CEC_ISR_TXUDR                       0x00000400U       /*!< CEC Tx-Buffer Underrun                 */
+#define  CEC_ISR_TXERR                       0x00000800U       /*!< CEC Tx-Error                           */
+#define  CEC_ISR_TXACKE                      0x00001000U       /*!< CEC Tx Missing Acknowledge             */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define  CEC_IER_RXBRIE                      0x00000001U       /*!< CEC Rx-Byte Received IT Enable         */
+#define  CEC_IER_RXENDIE                     0x00000002U       /*!< CEC End Of Reception IT Enable         */
+#define  CEC_IER_RXOVRIE                     0x00000004U       /*!< CEC Rx-Overrun IT Enable               */
+#define  CEC_IER_BREIE                       0x00000008U       /*!< CEC Rx Bit Rising Error IT Enable      */
+#define  CEC_IER_SBPEIE                      0x00000010U       /*!< CEC Rx Short Bit period Error IT Enable*/
+#define  CEC_IER_LBPEIE                      0x00000020U       /*!< CEC Rx Long Bit period Error IT Enable */
+#define  CEC_IER_RXACKEIE                    0x00000040U       /*!< CEC Rx Missing Acknowledge IT Enable   */
+#define  CEC_IER_ARBLSTIE                    0x00000080U       /*!< CEC Arbitration Lost IT Enable         */
+#define  CEC_IER_TXBRIE                      0x00000100U       /*!< CEC Tx Byte Request  IT Enable         */
+#define  CEC_IER_TXENDIE                     0x00000200U       /*!< CEC End of Transmission IT Enable      */
+#define  CEC_IER_TXUDRIE                     0x00000400U       /*!< CEC Tx-Buffer Underrun IT Enable       */
+#define  CEC_IER_TXERRIE                     0x00000800U       /*!< CEC Tx-Error IT Enable                 */
+#define  CEC_IER_TXACKEIE                    0x00001000U       /*!< CEC Tx Missing Acknowledge IT Enable   */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           0xFFFFFFFFU     /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         0x000000FFU     /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        0x00000001U     /*!< RESET the CRC computation unit bit */
+#define  CRC_CR_POLYSIZE                     0x00000018U     /*!< Polynomial size bits               */
+#define  CRC_CR_POLYSIZE_0                   0x00000008U     /*!< Polynomial size bit 0              */
+#define  CRC_CR_POLYSIZE_1                   0x00000010U     /*!< Polynomial size bit 1              */
+#define  CRC_CR_REV_IN                       0x00000060U     /*!< REV_IN Reverse Input Data bits     */
+#define  CRC_CR_REV_IN_0                     0x00000020U     /*!< Bit 0 */
+#define  CRC_CR_REV_IN_1                     0x00000040U     /*!< Bit 1 */
+#define  CRC_CR_REV_OUT                      0x00000080U     /*!< REV_OUT Reverse Output Data bits   */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       0xFFFFFFFFU     /*!< Initial CRC value bits         */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define  CRC_POL_POL                         0xFFFFFFFFU     /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Crypto Processor                                */
+/*                                                                            */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register  ********************/
+#define CRYP_CR_ALGODIR                      0x00000004U
+
+#define CRYP_CR_ALGOMODE                     0x00080038U
+#define CRYP_CR_ALGOMODE_0                   0x00000008U
+#define CRYP_CR_ALGOMODE_1                   0x00000010U
+#define CRYP_CR_ALGOMODE_2                   0x00000020U
+#define CRYP_CR_ALGOMODE_TDES_ECB            0x00000000U
+#define CRYP_CR_ALGOMODE_TDES_CBC            0x00000008U
+#define CRYP_CR_ALGOMODE_DES_ECB             0x00000010U
+#define CRYP_CR_ALGOMODE_DES_CBC             0x00000018U
+#define CRYP_CR_ALGOMODE_AES_ECB             0x00000020U
+#define CRYP_CR_ALGOMODE_AES_CBC             0x00000028U
+#define CRYP_CR_ALGOMODE_AES_CTR             0x00000030U
+#define CRYP_CR_ALGOMODE_AES_KEY             0x00000038U
+
+#define CRYP_CR_DATATYPE                     0x000000C0U
+#define CRYP_CR_DATATYPE_0                   0x00000040U
+#define CRYP_CR_DATATYPE_1                   0x00000080U
+#define CRYP_CR_KEYSIZE                      0x00000300U
+#define CRYP_CR_KEYSIZE_0                    0x00000100U
+#define CRYP_CR_KEYSIZE_1                    0x00000200U
+#define CRYP_CR_FFLUSH                       0x00004000U
+#define CRYP_CR_CRYPEN                       0x00008000U
+
+#define CRYP_CR_GCM_CCMPH                    0x00030000U
+#define CRYP_CR_GCM_CCMPH_0                  0x00010000U
+#define CRYP_CR_GCM_CCMPH_1                  0x00020000U
+#define CRYP_CR_ALGOMODE_3                   0x00080000U 
+
+/****************** Bits definition for CRYP_SR register  *********************/
+#define CRYP_SR_IFEM                         0x00000001U
+#define CRYP_SR_IFNF                         0x00000002U
+#define CRYP_SR_OFNE                         0x00000004U
+#define CRYP_SR_OFFU                         0x00000008U
+#define CRYP_SR_BUSY                         0x00000010U
+/****************** Bits definition for CRYP_DMACR register  ******************/
+#define CRYP_DMACR_DIEN                      0x00000001U
+#define CRYP_DMACR_DOEN                      0x00000002U
+/*****************  Bits definition for CRYP_IMSCR register  ******************/
+#define CRYP_IMSCR_INIM                      0x00000001U
+#define CRYP_IMSCR_OUTIM                     0x00000002U
+/****************** Bits definition for CRYP_RISR register  *******************/
+#define CRYP_RISR_OUTRIS                     0x00000001U
+#define CRYP_RISR_INRIS                      0x00000002U
+/****************** Bits definition for CRYP_MISR register  *******************/
+#define CRYP_MISR_INMIS                      0x00000001U
+#define CRYP_MISR_OUTMIS                     0x00000002U
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable                         */
+#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable          */
+#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable                 */
+#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */
+#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
+#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */
+#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */
+#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable                     */
+#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable  */
+#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable                         */
+#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable          */
+#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable                 */
+#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */
+#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */
+#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */
+#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enable                    */
+#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable */
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE                      0x00000001U
+#define DCMI_CR_CM                           0x00000002U
+#define DCMI_CR_CROP                         0x00000004U
+#define DCMI_CR_JPEG                         0x00000008U
+#define DCMI_CR_ESS                          0x00000010U
+#define DCMI_CR_PCKPOL                       0x00000020U
+#define DCMI_CR_HSPOL                        0x00000040U
+#define DCMI_CR_VSPOL                        0x00000080U
+#define DCMI_CR_FCRC_0                       0x00000100U
+#define DCMI_CR_FCRC_1                       0x00000200U
+#define DCMI_CR_EDM_0                        0x00000400U
+#define DCMI_CR_EDM_1                        0x00000800U
+#define DCMI_CR_CRE                          0x00001000U
+#define DCMI_CR_ENABLE                       0x00004000U
+#define DCMI_CR_BSM                          0x00030000U
+#define DCMI_CR_BSM_0                        0x00010000U
+#define DCMI_CR_BSM_1                        0x00020000U
+#define DCMI_CR_OEBS                         0x00040000U
+#define DCMI_CR_LSM                          0x00080000U
+#define DCMI_CR_OELS                         0x00100000U
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC                        0x00000001U
+#define DCMI_SR_VSYNC                        0x00000002U
+#define DCMI_SR_FNE                          0x00000004U
+
+/********************  Bits definition for DCMI_RIS register   ****************/
+#define DCMI_RIS_FRAME_RIS                   0x00000001U
+#define DCMI_RIS_OVR_RIS                     0x00000002U
+#define DCMI_RIS_ERR_RIS                     0x00000004U
+#define DCMI_RIS_VSYNC_RIS                   0x00000008U
+#define DCMI_RIS_LINE_RIS                    0x00000010U
+
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE                    0x00000001U
+#define DCMI_IER_OVR_IE                      0x00000002U
+#define DCMI_IER_ERR_IE                      0x00000004U
+#define DCMI_IER_VSYNC_IE                    0x00000008U
+#define DCMI_IER_LINE_IE                     0x00000010U
+
+/* Legacy define */
+#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS                   0x00000001U
+#define DCMI_MIS_OVR_MIS                     0x00000002U
+#define DCMI_MIS_ERR_MIS                     0x00000004U
+#define DCMI_MIS_VSYNC_MIS                   0x00000008U
+#define DCMI_MIS_LINE_MIS                    0x00000010U
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC                   0x00000001U
+#define DCMI_ICR_OVR_ISC                     0x00000002U
+#define DCMI_ICR_ERR_ISC                     0x00000004U
+#define DCMI_ICR_VSYNC_ISC                   0x00000008U
+#define DCMI_ICR_LINE_ISC                    0x00000010U
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC                        0x000000FFU
+#define DCMI_ESCR_LSC                        0x0000FF00U
+#define DCMI_ESCR_LEC                        0x00FF0000U
+#define DCMI_ESCR_FEC                        0xFF000000U
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU                        0x000000FFU
+#define DCMI_ESUR_LSU                        0x0000FF00U
+#define DCMI_ESUR_LEU                        0x00FF0000U
+#define DCMI_ESUR_FEU                        0xFF000000U
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU
+#define DCMI_CWSTRT_VST                      0x1FFF0000U
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU
+#define DCMI_CWSIZE_VLINE                    0x3FFF0000U
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0                        0x000000FFU
+#define DCMI_DR_BYTE1                        0x0000FF00U
+#define DCMI_DR_BYTE2                        0x00FF0000U
+#define DCMI_DR_BYTE3                        0xFF000000U
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/ 
+#define DMA_SxCR_CHSEL                       0x0E000000U
+#define DMA_SxCR_CHSEL_0                     0x02000000U
+#define DMA_SxCR_CHSEL_1                     0x04000000U
+#define DMA_SxCR_CHSEL_2                     0x08000000U
+#define DMA_SxCR_MBURST                      0x01800000U
+#define DMA_SxCR_MBURST_0                    0x00800000U
+#define DMA_SxCR_MBURST_1                    0x01000000U
+#define DMA_SxCR_PBURST                      0x00600000U
+#define DMA_SxCR_PBURST_0                    0x00200000U
+#define DMA_SxCR_PBURST_1                    0x00400000U
+#define DMA_SxCR_CT                          0x00080000U  
+#define DMA_SxCR_DBM                         0x00040000U
+#define DMA_SxCR_PL                          0x00030000U
+#define DMA_SxCR_PL_0                        0x00010000U
+#define DMA_SxCR_PL_1                        0x00020000U
+#define DMA_SxCR_PINCOS                      0x00008000U
+#define DMA_SxCR_MSIZE                       0x00006000U
+#define DMA_SxCR_MSIZE_0                     0x00002000U
+#define DMA_SxCR_MSIZE_1                     0x00004000U
+#define DMA_SxCR_PSIZE                       0x00001800U
+#define DMA_SxCR_PSIZE_0                     0x00000800U
+#define DMA_SxCR_PSIZE_1                     0x00001000U
+#define DMA_SxCR_MINC                        0x00000400U
+#define DMA_SxCR_PINC                        0x00000200U
+#define DMA_SxCR_CIRC                        0x00000100U
+#define DMA_SxCR_DIR                         0x000000C0U
+#define DMA_SxCR_DIR_0                       0x00000040U
+#define DMA_SxCR_DIR_1                       0x00000080U
+#define DMA_SxCR_PFCTRL                      0x00000020U
+#define DMA_SxCR_TCIE                        0x00000010U
+#define DMA_SxCR_HTIE                        0x00000008U
+#define DMA_SxCR_TEIE                        0x00000004U
+#define DMA_SxCR_DMEIE                       0x00000002U
+#define DMA_SxCR_EN                          0x00000001U
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT                            0x0000FFFFU
+#define DMA_SxNDT_0                          0x00000001U
+#define DMA_SxNDT_1                          0x00000002U
+#define DMA_SxNDT_2                          0x00000004U
+#define DMA_SxNDT_3                          0x00000008U
+#define DMA_SxNDT_4                          0x00000010U
+#define DMA_SxNDT_5                          0x00000020U
+#define DMA_SxNDT_6                          0x00000040U
+#define DMA_SxNDT_7                          0x00000080U
+#define DMA_SxNDT_8                          0x00000100U
+#define DMA_SxNDT_9                          0x00000200U
+#define DMA_SxNDT_10                         0x00000400U
+#define DMA_SxNDT_11                         0x00000800U
+#define DMA_SxNDT_12                         0x00001000U
+#define DMA_SxNDT_13                         0x00002000U
+#define DMA_SxNDT_14                         0x00004000U
+#define DMA_SxNDT_15                         0x00008000U
+
+/********************  Bits definition for DMA_SxFCR register  ****************/ 
+#define DMA_SxFCR_FEIE                       0x00000080U
+#define DMA_SxFCR_FS                         0x00000038U
+#define DMA_SxFCR_FS_0                       0x00000008U
+#define DMA_SxFCR_FS_1                       0x00000010U
+#define DMA_SxFCR_FS_2                       0x00000020U
+#define DMA_SxFCR_DMDIS                      0x00000004U
+#define DMA_SxFCR_FTH                        0x00000003U
+#define DMA_SxFCR_FTH_0                      0x00000001U
+#define DMA_SxFCR_FTH_1                      0x00000002U
+
+/********************  Bits definition for DMA_LISR register  *****************/ 
+#define DMA_LISR_TCIF3                       0x08000000U
+#define DMA_LISR_HTIF3                       0x04000000U
+#define DMA_LISR_TEIF3                       0x02000000U
+#define DMA_LISR_DMEIF3                      0x01000000U
+#define DMA_LISR_FEIF3                       0x00400000U
+#define DMA_LISR_TCIF2                       0x00200000U
+#define DMA_LISR_HTIF2                       0x00100000U
+#define DMA_LISR_TEIF2                       0x00080000U
+#define DMA_LISR_DMEIF2                      0x00040000U
+#define DMA_LISR_FEIF2                       0x00010000U
+#define DMA_LISR_TCIF1                       0x00000800U
+#define DMA_LISR_HTIF1                       0x00000400U
+#define DMA_LISR_TEIF1                       0x00000200U
+#define DMA_LISR_DMEIF1                      0x00000100U
+#define DMA_LISR_FEIF1                       0x00000040U
+#define DMA_LISR_TCIF0                       0x00000020U
+#define DMA_LISR_HTIF0                       0x00000010U
+#define DMA_LISR_TEIF0                       0x00000008U
+#define DMA_LISR_DMEIF0                      0x00000004U
+#define DMA_LISR_FEIF0                       0x00000001U
+
+/********************  Bits definition for DMA_HISR register  *****************/ 
+#define DMA_HISR_TCIF7                       0x08000000U
+#define DMA_HISR_HTIF7                       0x04000000U
+#define DMA_HISR_TEIF7                       0x02000000U
+#define DMA_HISR_DMEIF7                      0x01000000U
+#define DMA_HISR_FEIF7                       0x00400000U
+#define DMA_HISR_TCIF6                       0x00200000U
+#define DMA_HISR_HTIF6                       0x00100000U
+#define DMA_HISR_TEIF6                       0x00080000U
+#define DMA_HISR_DMEIF6                      0x00040000U
+#define DMA_HISR_FEIF6                       0x00010000U
+#define DMA_HISR_TCIF5                       0x00000800U
+#define DMA_HISR_HTIF5                       0x00000400U
+#define DMA_HISR_TEIF5                       0x00000200U
+#define DMA_HISR_DMEIF5                      0x00000100U
+#define DMA_HISR_FEIF5                       0x00000040U
+#define DMA_HISR_TCIF4                       0x00000020U
+#define DMA_HISR_HTIF4                       0x00000010U
+#define DMA_HISR_TEIF4                       0x00000008U
+#define DMA_HISR_DMEIF4                      0x00000004U
+#define DMA_HISR_FEIF4                       0x00000001U
+
+/********************  Bits definition for DMA_LIFCR register  ****************/ 
+#define DMA_LIFCR_CTCIF3                     0x08000000U
+#define DMA_LIFCR_CHTIF3                     0x04000000U
+#define DMA_LIFCR_CTEIF3                     0x02000000U
+#define DMA_LIFCR_CDMEIF3                    0x01000000U
+#define DMA_LIFCR_CFEIF3                     0x00400000U
+#define DMA_LIFCR_CTCIF2                     0x00200000U
+#define DMA_LIFCR_CHTIF2                     0x00100000U
+#define DMA_LIFCR_CTEIF2                     0x00080000U
+#define DMA_LIFCR_CDMEIF2                    0x00040000U
+#define DMA_LIFCR_CFEIF2                     0x00010000U
+#define DMA_LIFCR_CTCIF1                     0x00000800U
+#define DMA_LIFCR_CHTIF1                     0x00000400U
+#define DMA_LIFCR_CTEIF1                     0x00000200U
+#define DMA_LIFCR_CDMEIF1                    0x00000100U
+#define DMA_LIFCR_CFEIF1                     0x00000040U
+#define DMA_LIFCR_CTCIF0                     0x00000020U
+#define DMA_LIFCR_CHTIF0                     0x00000010U
+#define DMA_LIFCR_CTEIF0                     0x00000008U
+#define DMA_LIFCR_CDMEIF0                    0x00000004U
+#define DMA_LIFCR_CFEIF0                     0x00000001U
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/ 
+#define DMA_HIFCR_CTCIF7                     0x08000000U
+#define DMA_HIFCR_CHTIF7                     0x04000000U
+#define DMA_HIFCR_CTEIF7                     0x02000000U
+#define DMA_HIFCR_CDMEIF7                    0x01000000U
+#define DMA_HIFCR_CFEIF7                     0x00400000U
+#define DMA_HIFCR_CTCIF6                     0x00200000U
+#define DMA_HIFCR_CHTIF6                     0x00100000U
+#define DMA_HIFCR_CTEIF6                     0x00080000U
+#define DMA_HIFCR_CDMEIF6                    0x00040000U
+#define DMA_HIFCR_CFEIF6                     0x00010000U
+#define DMA_HIFCR_CTCIF5                     0x00000800U
+#define DMA_HIFCR_CHTIF5                     0x00000400U
+#define DMA_HIFCR_CTEIF5                     0x00000200U
+#define DMA_HIFCR_CDMEIF5                    0x00000100U
+#define DMA_HIFCR_CFEIF5                     0x00000040U
+#define DMA_HIFCR_CTCIF4                     0x00000020U
+#define DMA_HIFCR_CHTIF4                     0x00000010U
+#define DMA_HIFCR_CTEIF4                     0x00000008U
+#define DMA_HIFCR_CDMEIF4                    0x00000004U
+#define DMA_HIFCR_CFEIF4                     0x00000001U
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer                          */
+#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer                        */
+#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer                          */
+#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable         */
+#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable      */
+#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable     */
+#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable      */
+#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable    */
+#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0]                         */
+#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0                        */
+#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1                        */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag         */
+#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag      */
+#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag     */
+#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag      */
+#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+
+#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
+#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
+#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
+#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */
+#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
+#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
+#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
+#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */
+#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */
+#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */
+#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */
+#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */
+#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */
+#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */
+#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */
+#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */
+#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */
+#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */
+
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+                                                                     
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       0x00800000U        /*!< Interrupt Mask on line 23 */
+
+/* Reference Defines */
+#define  EXTI_IMR_IM0                        EXTI_IMR_MR0                     
+#define  EXTI_IMR_IM1                        EXTI_IMR_MR1 
+#define  EXTI_IMR_IM2                        EXTI_IMR_MR2 
+#define  EXTI_IMR_IM3                        EXTI_IMR_MR3 
+#define  EXTI_IMR_IM4                        EXTI_IMR_MR4 
+#define  EXTI_IMR_IM5                        EXTI_IMR_MR5 
+#define  EXTI_IMR_IM6                        EXTI_IMR_MR6 
+#define  EXTI_IMR_IM7                        EXTI_IMR_MR7 
+#define  EXTI_IMR_IM8                        EXTI_IMR_MR8 
+#define  EXTI_IMR_IM9                        EXTI_IMR_MR9 
+#define  EXTI_IMR_IM10                       EXTI_IMR_MR10
+#define  EXTI_IMR_IM11                       EXTI_IMR_MR11
+#define  EXTI_IMR_IM12                       EXTI_IMR_MR12
+#define  EXTI_IMR_IM13                       EXTI_IMR_MR13
+#define  EXTI_IMR_IM14                       EXTI_IMR_MR14
+#define  EXTI_IMR_IM15                       EXTI_IMR_MR15
+#define  EXTI_IMR_IM16                       EXTI_IMR_MR16
+#define  EXTI_IMR_IM17                       EXTI_IMR_MR17
+#define  EXTI_IMR_IM18                       EXTI_IMR_MR18
+#define  EXTI_IMR_IM19                       EXTI_IMR_MR19
+#define  EXTI_IMR_IM20                       EXTI_IMR_MR20
+#define  EXTI_IMR_IM21                       EXTI_IMR_MR21
+#define  EXTI_IMR_IM22                       EXTI_IMR_MR22
+#define  EXTI_IMR_IM23                       EXTI_IMR_MR23
+
+#define  EXTI_IMR_IM                         0x00FFFFFFU        /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       0x00800000U        /*!< Event Mask on line 23 */
+
+/* Reference Defines */
+#define  EXTI_EMR_EM0                        EXTI_EMR_MR0                         
+#define  EXTI_EMR_EM1                        EXTI_EMR_MR1 
+#define  EXTI_EMR_EM2                        EXTI_EMR_MR2 
+#define  EXTI_EMR_EM3                        EXTI_EMR_MR3 
+#define  EXTI_EMR_EM4                        EXTI_EMR_MR4 
+#define  EXTI_EMR_EM5                        EXTI_EMR_MR5 
+#define  EXTI_EMR_EM6                        EXTI_EMR_MR6 
+#define  EXTI_EMR_EM7                        EXTI_EMR_MR7 
+#define  EXTI_EMR_EM8                        EXTI_EMR_MR8 
+#define  EXTI_EMR_EM9                        EXTI_EMR_MR9 
+#define  EXTI_EMR_EM10                       EXTI_EMR_MR10
+#define  EXTI_EMR_EM11                       EXTI_EMR_MR11
+#define  EXTI_EMR_EM12                       EXTI_EMR_MR12
+#define  EXTI_EMR_EM13                       EXTI_EMR_MR13
+#define  EXTI_EMR_EM14                       EXTI_EMR_MR14
+#define  EXTI_EMR_EM15                       EXTI_EMR_MR15
+#define  EXTI_EMR_EM16                       EXTI_EMR_MR16
+#define  EXTI_EMR_EM17                       EXTI_EMR_MR17
+#define  EXTI_EMR_EM18                       EXTI_EMR_MR18
+#define  EXTI_EMR_EM19                       EXTI_EMR_MR19
+#define  EXTI_EMR_EM20                       EXTI_EMR_MR20
+#define  EXTI_EMR_EM21                       EXTI_EMR_MR21
+#define  EXTI_EMR_EM22                       EXTI_EMR_MR22
+#define  EXTI_EMR_EM23                       EXTI_EMR_MR23
+
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR23                      0x00800000U        /*!< Rising trigger event configuration bit of line 23 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR23                      0x00800000U        /*!< Falling trigger event configuration bit of line 23 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER23                  0x00800000U        /*!< Software Interrupt on line 23 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR23                        0x00800000U        /*!< Pending bit for line 23 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief FLASH Total Sectors Number
+*/
+#define FLASH_SECTOR_TOTAL  8	
+
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY                    0x0000000FU
+#define FLASH_ACR_LATENCY_0WS                0x00000000U
+#define FLASH_ACR_LATENCY_1WS                0x00000001U
+#define FLASH_ACR_LATENCY_2WS                0x00000002U
+#define FLASH_ACR_LATENCY_3WS                0x00000003U
+#define FLASH_ACR_LATENCY_4WS                0x00000004U
+#define FLASH_ACR_LATENCY_5WS                0x00000005U
+#define FLASH_ACR_LATENCY_6WS                0x00000006U
+#define FLASH_ACR_LATENCY_7WS                0x00000007U
+#define FLASH_ACR_LATENCY_8WS                0x00000008U
+#define FLASH_ACR_LATENCY_9WS                0x00000009U
+#define FLASH_ACR_LATENCY_10WS               0x0000000AU
+#define FLASH_ACR_LATENCY_11WS               0x0000000BU
+#define FLASH_ACR_LATENCY_12WS               0x0000000CU
+#define FLASH_ACR_LATENCY_13WS               0x0000000DU
+#define FLASH_ACR_LATENCY_14WS               0x0000000EU
+#define FLASH_ACR_LATENCY_15WS               0x0000000FU
+#define FLASH_ACR_PRFTEN                     0x00000100U
+#define FLASH_ACR_ARTEN                      0x00000200U
+#define FLASH_ACR_ARTRST                     0x00000800U
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP                         0x00000001U
+#define FLASH_SR_OPERR                       0x00000002U
+#define FLASH_SR_WRPERR                      0x00000010U
+#define FLASH_SR_PGAERR                      0x00000020U
+#define FLASH_SR_PGPERR                      0x00000040U
+#define FLASH_SR_ERSERR                      0x00000080U
+#define FLASH_SR_BSY                         0x00010000U
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG                          0x00000001U
+#define FLASH_CR_SER                         0x00000002U
+#define FLASH_CR_MER                         0x00000004U
+#define FLASH_CR_SNB                         0x00000078U
+#define FLASH_CR_SNB_0                       0x00000008U
+#define FLASH_CR_SNB_1                       0x00000010U
+#define FLASH_CR_SNB_2                       0x00000020U
+#define FLASH_CR_SNB_3                       0x00000040U
+#define FLASH_CR_PSIZE                       0x00000300U
+#define FLASH_CR_PSIZE_0                     0x00000100U
+#define FLASH_CR_PSIZE_1                     0x00000200U
+#define FLASH_CR_STRT                        0x00010000U
+#define FLASH_CR_EOPIE                       0x01000000U
+#define FLASH_CR_ERRIE                       0x02000000U
+#define FLASH_CR_LOCK                        0x80000000U
+
+/*******************  Bits definition for FLASH_OPTCR register  ***************/
+#define FLASH_OPTCR_OPTLOCK                 0x00000001U
+#define FLASH_OPTCR_OPTSTRT                 0x00000002U
+#define FLASH_OPTCR_BOR_LEV                 0x0000000CU
+#define FLASH_OPTCR_BOR_LEV_0               0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1               0x00000008U
+#define FLASH_OPTCR_WWDG_SW                 0x00000010U
+#define FLASH_OPTCR_IWDG_SW                 0x00000020U
+#define FLASH_OPTCR_nRST_STOP               0x00000040U
+#define FLASH_OPTCR_nRST_STDBY              0x00000080U
+#define FLASH_OPTCR_RDP                     0x0000FF00U
+#define FLASH_OPTCR_RDP_0                   0x00000100U
+#define FLASH_OPTCR_RDP_1                   0x00000200U
+#define FLASH_OPTCR_RDP_2                   0x00000400U
+#define FLASH_OPTCR_RDP_3                   0x00000800U
+#define FLASH_OPTCR_RDP_4                   0x00001000U
+#define FLASH_OPTCR_RDP_5                   0x00002000U
+#define FLASH_OPTCR_RDP_6                   0x00004000U
+#define FLASH_OPTCR_RDP_7                   0x00008000U
+#define FLASH_OPTCR_nWRP                    0x00FF0000U
+#define FLASH_OPTCR_nWRP_0                  0x00010000U
+#define FLASH_OPTCR_nWRP_1                  0x00020000U
+#define FLASH_OPTCR_nWRP_2                  0x00040000U
+#define FLASH_OPTCR_nWRP_3                  0x00080000U
+#define FLASH_OPTCR_nWRP_4                  0x00100000U
+#define FLASH_OPTCR_nWRP_5                  0x00200000U
+#define FLASH_OPTCR_nWRP_6                  0x00400000U
+#define FLASH_OPTCR_nWRP_7                  0x00800000U
+#define FLASH_OPTCR_IWDG_STDBY              0x40000000U
+#define FLASH_OPTCR_IWDG_STOP               0x80000000U
+
+/*******************  Bits definition for FLASH_OPTCR1 register  ***************/
+#define FLASH_OPTCR1_BOOT_ADD0              0x0000FFFFU
+#define FLASH_OPTCR1_BOOT_ADD1              0xFFFF0000U
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */
+#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */
+#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */
+#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */
+#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */
+
+/******************  Bit definition for FMC_BCR2 register  *******************/
+#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */
+#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */
+#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size             */
+#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR3 register  *******************/
+#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */
+#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */
+#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size             */
+#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR4 register  *******************/
+#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */
+#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */
+#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */
+#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */
+#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */
+#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */
+#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */
+#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */
+#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */
+#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */
+#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */
+#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */
+#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */
+#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */
+#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */
+#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */
+#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size             */
+#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */
+#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */
+#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */
+#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTR1 register  ******************/
+#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */
+#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
+#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */
+#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
+#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
+#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */
+#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BTR2 register  *******************/
+#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */
+#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
+#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */
+#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
+#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
+#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */
+#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
+
+/*******************  Bit definition for FMC_BTR3 register  *******************/
+#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */
+#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
+#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */
+#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
+#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
+#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */
+#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BTR4 register  *******************/
+#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */
+#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */
+#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */
+#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */
+#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */
+#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */
+#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */
+#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */
+#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */
+#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */
+#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */
+#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */
+#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */
+#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */
+#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */
+#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */
+#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */
+#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */
+#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */
+#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */
+#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */
+#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */
+#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */
+#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */
+#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */
+#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */
+#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */
+#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR1 register  ******************/
+#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */
+#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
+#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */
+#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR2 register  ******************/
+#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */
+#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
+#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */
+#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR3 register  ******************/
+#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */
+#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
+#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */
+#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_BWTR4 register  ******************/
+#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */
+#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */
+#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */
+#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */
+#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */
+#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */
+#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */
+#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */
+#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */
+#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */
+#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */
+#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */
+#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */
+#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */
+#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */
+#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */
+#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */
+#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */
+#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */
+#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_PCR register  *******************/
+#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */
+#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */
+#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */
+#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */
+#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */
+#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */
+#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */
+#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */
+#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */
+#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */
+#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */
+#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */
+#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */
+#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */
+#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */
+#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */
+#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */
+#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */
+
+/*******************  Bit definition for FMC_SR register  *******************/
+#define  FMC_SR_IRS                        0x01U              /*!<Interrupt Rising Edge status                */
+#define  FMC_SR_ILS                        0x02U              /*!<Interrupt Level status                      */
+#define  FMC_SR_IFS                        0x04U              /*!<Interrupt Falling Edge status               */
+#define  FMC_SR_IREN                       0x08U              /*!<Interrupt Rising Edge detection Enable bit  */
+#define  FMC_SR_ILEN                       0x10U              /*!<Interrupt Level detection Enable bit        */
+#define  FMC_SR_IFEN                       0x20U              /*!<Interrupt Falling Edge detection Enable bit */
+#define  FMC_SR_FEMPT                      0x40U              /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define  FMC_PMEM_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FMC_PMEM_MEMSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMSET3_7                0x00000080U        /*!<Bit 7 */
+#define  FMC_PMEM_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FMC_PMEM_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */
+#define  FMC_PMEM_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FMC_PMEM_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */
+#define  FMC_PMEM_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FMC_PMEM_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PMEM_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PMEM_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PMEM_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PMEM_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PMEM_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PMEM_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PMEM_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_PATT register  ******************/
+#define  FMC_PATT_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FMC_PATT_ATTSET3_0                0x00000001U        /*!<Bit 0 */
+#define  FMC_PATT_ATTSET3_1                0x00000002U        /*!<Bit 1 */
+#define  FMC_PATT_ATTSET3_2                0x00000004U        /*!<Bit 2 */
+#define  FMC_PATT_ATTSET3_3                0x00000008U        /*!<Bit 3 */
+#define  FMC_PATT_ATTSET3_4                0x00000010U        /*!<Bit 4 */
+#define  FMC_PATT_ATTSET3_5                0x00000020U        /*!<Bit 5 */
+#define  FMC_PATT_ATTSET3_6                0x00000040U        /*!<Bit 6 */
+#define  FMC_PATT_ATTSET3_7                0x00000080U        /*!<Bit 7 */
+#define  FMC_PATT_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FMC_PATT_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */
+#define  FMC_PATT_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */
+#define  FMC_PATT_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */
+#define  FMC_PATT_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */
+#define  FMC_PATT_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */
+#define  FMC_PATT_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FMC_PATT_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */
+#define  FMC_PATT_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */
+#define  FMC_PATT_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */
+#define  FMC_PATT_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */
+#define  FMC_PATT_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */
+#define  FMC_PATT_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FMC_PATT_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */
+#define  FMC_PATT_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */
+#define  FMC_PATT_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */
+#define  FMC_PATT_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */
+#define  FMC_PATT_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */
+#define  FMC_PATT_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */
+#define  FMC_PATT_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */
+#define  FMC_PATT_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */
+
+/******************  Bit definition for FMC_ECCR register  ******************/
+#define  FMC_ECCR_ECC3                     0xFFFFFFFFU        /*!<ECC result */
+
+/******************  Bit definition for FMC_SDCR1 register  ******************/
+#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */
+#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */
+#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */
+#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */
+#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */
+#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */
+#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */
+#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */
+#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */
+#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_SDCR2 register  ******************/
+#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */
+#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */
+#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */
+#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */
+#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */
+#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */
+#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */
+#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */
+#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */
+#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */
+#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */
+#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */
+#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */
+#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */
+#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */
+#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */
+
+/******************  Bit definition for FMC_SDTR1 register  ******************/
+#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */
+#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */
+#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */
+#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */
+#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */
+#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */
+#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_SDTR2 register  ******************/
+#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */
+#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */
+#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */
+#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */
+#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */
+#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */
+#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */
+#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */
+#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */
+#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */
+#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */
+#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */
+#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */
+#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */
+#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */
+#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */
+#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */
+#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */
+#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */
+#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */
+#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */
+
+/******************  Bit definition for FMC_SDCMR register  ******************/
+#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */
+#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */
+#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */
+#define  FMC_SDCMR_MODE_2                   0x00000003U        /*!<Bit 2 */
+#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */
+#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */
+#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */
+#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */
+#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */
+#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */
+#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */
+
+/******************  Bit definition for FMC_SDRTR register  ******************/
+#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */
+#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */
+#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ******************/
+#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */
+#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */
+#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */
+#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */
+#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0                    0x00000003U
+#define GPIO_MODER_MODER0_0                  0x00000001U
+#define GPIO_MODER_MODER0_1                  0x00000002U
+#define GPIO_MODER_MODER1                    0x0000000CU
+#define GPIO_MODER_MODER1_0                  0x00000004U
+#define GPIO_MODER_MODER1_1                  0x00000008U
+#define GPIO_MODER_MODER2                    0x00000030U
+#define GPIO_MODER_MODER2_0                  0x00000010U
+#define GPIO_MODER_MODER2_1                  0x00000020U
+#define GPIO_MODER_MODER3                    0x000000C0U
+#define GPIO_MODER_MODER3_0                  0x00000040U
+#define GPIO_MODER_MODER3_1                  0x00000080U
+#define GPIO_MODER_MODER4                    0x00000300U
+#define GPIO_MODER_MODER4_0                  0x00000100U
+#define GPIO_MODER_MODER4_1                  0x00000200U
+#define GPIO_MODER_MODER5                    0x00000C00U
+#define GPIO_MODER_MODER5_0                  0x00000400U
+#define GPIO_MODER_MODER5_1                  0x00000800U
+#define GPIO_MODER_MODER6                    0x00003000U
+#define GPIO_MODER_MODER6_0                  0x00001000U
+#define GPIO_MODER_MODER6_1                  0x00002000U
+#define GPIO_MODER_MODER7                    0x0000C000U
+#define GPIO_MODER_MODER7_0                  0x00004000U
+#define GPIO_MODER_MODER7_1                  0x00008000U
+#define GPIO_MODER_MODER8                    0x00030000U
+#define GPIO_MODER_MODER8_0                  0x00010000U
+#define GPIO_MODER_MODER8_1                  0x00020000U
+#define GPIO_MODER_MODER9                    0x000C0000U
+#define GPIO_MODER_MODER9_0                  0x00040000U
+#define GPIO_MODER_MODER9_1                  0x00080000U
+#define GPIO_MODER_MODER10                   0x00300000U
+#define GPIO_MODER_MODER10_0                 0x00100000U
+#define GPIO_MODER_MODER10_1                 0x00200000U
+#define GPIO_MODER_MODER11                   0x00C00000U
+#define GPIO_MODER_MODER11_0                 0x00400000U
+#define GPIO_MODER_MODER11_1                 0x00800000U
+#define GPIO_MODER_MODER12                   0x03000000U
+#define GPIO_MODER_MODER12_0                 0x01000000U
+#define GPIO_MODER_MODER12_1                 0x02000000U
+#define GPIO_MODER_MODER13                   0x0C000000U
+#define GPIO_MODER_MODER13_0                 0x04000000U
+#define GPIO_MODER_MODER13_1                 0x08000000U
+#define GPIO_MODER_MODER14                   0x30000000U
+#define GPIO_MODER_MODER14_0                 0x10000000U
+#define GPIO_MODER_MODER14_1                 0x20000000U
+#define GPIO_MODER_MODER15                   0xC0000000U
+#define GPIO_MODER_MODER15_0                 0x40000000U
+#define GPIO_MODER_MODER15_1                 0x80000000U
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT_0                     0x00000001U
+#define GPIO_OTYPER_OT_1                     0x00000002U
+#define GPIO_OTYPER_OT_2                     0x00000004U
+#define GPIO_OTYPER_OT_3                     0x00000008U
+#define GPIO_OTYPER_OT_4                     0x00000010U
+#define GPIO_OTYPER_OT_5                     0x00000020U
+#define GPIO_OTYPER_OT_6                     0x00000040U
+#define GPIO_OTYPER_OT_7                     0x00000080U
+#define GPIO_OTYPER_OT_8                     0x00000100U
+#define GPIO_OTYPER_OT_9                     0x00000200U
+#define GPIO_OTYPER_OT_10                    0x00000400U
+#define GPIO_OTYPER_OT_11                    0x00000800U
+#define GPIO_OTYPER_OT_12                    0x00001000U
+#define GPIO_OTYPER_OT_13                    0x00002000U
+#define GPIO_OTYPER_OT_14                    0x00004000U
+#define GPIO_OTYPER_OT_15                    0x00008000U
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U
+#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U
+#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U
+#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U
+#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U
+#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U
+#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U
+#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U
+#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U
+#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U
+#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U
+#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U
+#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U
+#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U
+#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U
+#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPDR0                    0x00000003U
+#define GPIO_PUPDR_PUPDR0_0                  0x00000001U
+#define GPIO_PUPDR_PUPDR0_1                  0x00000002U
+#define GPIO_PUPDR_PUPDR1                    0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0                  0x00000004U
+#define GPIO_PUPDR_PUPDR1_1                  0x00000008U
+#define GPIO_PUPDR_PUPDR2                    0x00000030U
+#define GPIO_PUPDR_PUPDR2_0                  0x00000010U
+#define GPIO_PUPDR_PUPDR2_1                  0x00000020U
+#define GPIO_PUPDR_PUPDR3                    0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0                  0x00000040U
+#define GPIO_PUPDR_PUPDR3_1                  0x00000080U
+#define GPIO_PUPDR_PUPDR4                    0x00000300U
+#define GPIO_PUPDR_PUPDR4_0                  0x00000100U
+#define GPIO_PUPDR_PUPDR4_1                  0x00000200U
+#define GPIO_PUPDR_PUPDR5                    0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0                  0x00000400U
+#define GPIO_PUPDR_PUPDR5_1                  0x00000800U
+#define GPIO_PUPDR_PUPDR6                    0x00003000U
+#define GPIO_PUPDR_PUPDR6_0                  0x00001000U
+#define GPIO_PUPDR_PUPDR6_1                  0x00002000U
+#define GPIO_PUPDR_PUPDR7                    0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0                  0x00004000U
+#define GPIO_PUPDR_PUPDR7_1                  0x00008000U
+#define GPIO_PUPDR_PUPDR8                    0x00030000U
+#define GPIO_PUPDR_PUPDR8_0                  0x00010000U
+#define GPIO_PUPDR_PUPDR8_1                  0x00020000U
+#define GPIO_PUPDR_PUPDR9                    0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0                  0x00040000U
+#define GPIO_PUPDR_PUPDR9_1                  0x00080000U
+#define GPIO_PUPDR_PUPDR10                   0x00300000U
+#define GPIO_PUPDR_PUPDR10_0                 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1                 0x00200000U
+#define GPIO_PUPDR_PUPDR11                   0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0                 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1                 0x00800000U
+#define GPIO_PUPDR_PUPDR12                   0x03000000U
+#define GPIO_PUPDR_PUPDR12_0                 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1                 0x02000000U
+#define GPIO_PUPDR_PUPDR13                   0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0                 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1                 0x08000000U
+#define GPIO_PUPDR_PUPDR14                   0x30000000U
+#define GPIO_PUPDR_PUPDR14_0                 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1                 0x20000000U
+#define GPIO_PUPDR_PUPDR15                   0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0                 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1                 0x80000000U
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_IDR_0                       0x00000001U
+#define GPIO_IDR_IDR_1                       0x00000002U
+#define GPIO_IDR_IDR_2                       0x00000004U
+#define GPIO_IDR_IDR_3                       0x00000008U
+#define GPIO_IDR_IDR_4                       0x00000010U
+#define GPIO_IDR_IDR_5                       0x00000020U
+#define GPIO_IDR_IDR_6                       0x00000040U
+#define GPIO_IDR_IDR_7                       0x00000080U
+#define GPIO_IDR_IDR_8                       0x00000100U
+#define GPIO_IDR_IDR_9                       0x00000200U
+#define GPIO_IDR_IDR_10                      0x00000400U
+#define GPIO_IDR_IDR_11                      0x00000800U
+#define GPIO_IDR_IDR_12                      0x00001000U
+#define GPIO_IDR_IDR_13                      0x00002000U
+#define GPIO_IDR_IDR_14                      0x00004000U
+#define GPIO_IDR_IDR_15                      0x00008000U
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_ODR_0                       0x00000001U
+#define GPIO_ODR_ODR_1                       0x00000002U
+#define GPIO_ODR_ODR_2                       0x00000004U
+#define GPIO_ODR_ODR_3                       0x00000008U
+#define GPIO_ODR_ODR_4                       0x00000010U
+#define GPIO_ODR_ODR_5                       0x00000020U
+#define GPIO_ODR_ODR_6                       0x00000040U
+#define GPIO_ODR_ODR_7                       0x00000080U
+#define GPIO_ODR_ODR_8                       0x00000100U
+#define GPIO_ODR_ODR_9                       0x00000200U
+#define GPIO_ODR_ODR_10                      0x00000400U
+#define GPIO_ODR_ODR_11                      0x00000800U
+#define GPIO_ODR_ODR_12                      0x00001000U
+#define GPIO_ODR_ODR_13                      0x00002000U
+#define GPIO_ODR_ODR_14                      0x00004000U
+#define GPIO_ODR_ODR_15                      0x00008000U
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS_0                       0x00000001U
+#define GPIO_BSRR_BS_1                       0x00000002U
+#define GPIO_BSRR_BS_2                       0x00000004U
+#define GPIO_BSRR_BS_3                       0x00000008U
+#define GPIO_BSRR_BS_4                       0x00000010U
+#define GPIO_BSRR_BS_5                       0x00000020U
+#define GPIO_BSRR_BS_6                       0x00000040U
+#define GPIO_BSRR_BS_7                       0x00000080U
+#define GPIO_BSRR_BS_8                       0x00000100U
+#define GPIO_BSRR_BS_9                       0x00000200U
+#define GPIO_BSRR_BS_10                      0x00000400U
+#define GPIO_BSRR_BS_11                      0x00000800U
+#define GPIO_BSRR_BS_12                      0x00001000U
+#define GPIO_BSRR_BS_13                      0x00002000U
+#define GPIO_BSRR_BS_14                      0x00004000U
+#define GPIO_BSRR_BS_15                      0x00008000U
+#define GPIO_BSRR_BR_0                       0x00010000U
+#define GPIO_BSRR_BR_1                       0x00020000U
+#define GPIO_BSRR_BR_2                       0x00040000U
+#define GPIO_BSRR_BR_3                       0x00080000U
+#define GPIO_BSRR_BR_4                       0x00100000U
+#define GPIO_BSRR_BR_5                       0x00200000U
+#define GPIO_BSRR_BR_6                       0x00400000U
+#define GPIO_BSRR_BR_7                       0x00800000U
+#define GPIO_BSRR_BR_8                       0x01000000U
+#define GPIO_BSRR_BR_9                       0x02000000U
+#define GPIO_BSRR_BR_10                      0x04000000U
+#define GPIO_BSRR_BR_11                      0x08000000U
+#define GPIO_BSRR_BR_12                      0x10000000U
+#define GPIO_BSRR_BR_13                      0x20000000U
+#define GPIO_BSRR_BR_14                      0x40000000U
+#define GPIO_BSRR_BR_15                      0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0                       0x00000001U
+#define GPIO_LCKR_LCK1                       0x00000002U
+#define GPIO_LCKR_LCK2                       0x00000004U
+#define GPIO_LCKR_LCK3                       0x00000008U
+#define GPIO_LCKR_LCK4                       0x00000010U
+#define GPIO_LCKR_LCK5                       0x00000020U
+#define GPIO_LCKR_LCK6                       0x00000040U
+#define GPIO_LCKR_LCK7                       0x00000080U
+#define GPIO_LCKR_LCK8                       0x00000100U
+#define GPIO_LCKR_LCK9                       0x00000200U
+#define GPIO_LCKR_LCK10                      0x00000400U
+#define GPIO_LCKR_LCK11                      0x00000800U
+#define GPIO_LCKR_LCK12                      0x00001000U
+#define GPIO_LCKR_LCK13                      0x00002000U
+#define GPIO_LCKR_LCK14                      0x00004000U
+#define GPIO_LCKR_LCK15                      0x00008000U
+#define GPIO_LCKR_LCKK                       0x00010000U
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    HASH                                    */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for HASH_CR register  ********************/
+#define HASH_CR_INIT                         0x00000004U
+#define HASH_CR_DMAE                         0x00000008U
+#define HASH_CR_DATATYPE                     0x00000030U
+#define HASH_CR_DATATYPE_0                   0x00000010U
+#define HASH_CR_DATATYPE_1                   0x00000020U
+#define HASH_CR_MODE                         0x00000040U
+#define HASH_CR_ALGO                         0x00040080U
+#define HASH_CR_ALGO_0                       0x00000080U
+#define HASH_CR_ALGO_1                       0x00040000U
+#define HASH_CR_NBW                          0x00000F00U
+#define HASH_CR_NBW_0                        0x00000100U
+#define HASH_CR_NBW_1                        0x00000200U
+#define HASH_CR_NBW_2                        0x00000400U
+#define HASH_CR_NBW_3                        0x00000800U
+#define HASH_CR_DINNE                        0x00001000U
+#define HASH_CR_MDMAT                        0x00002000U
+#define HASH_CR_LKEY                         0x00010000U
+
+/******************  Bits definition for HASH_STR register  *******************/
+#define HASH_STR_NBLW                        0x0000001FU
+#define HASH_STR_NBLW_0                      0x00000001U
+#define HASH_STR_NBLW_1                      0x00000002U
+#define HASH_STR_NBLW_2                      0x00000004U
+#define HASH_STR_NBLW_3                      0x00000008U
+#define HASH_STR_NBLW_4                      0x00000010U
+#define HASH_STR_DCAL                        0x00000100U
+
+/* legacy defines */
+#define HASH_STR_NBW                         HASH_STR_NBLW  
+#define HASH_STR_NBW_0                       HASH_STR_NBLW_0
+#define HASH_STR_NBW_1                       HASH_STR_NBLW_1
+#define HASH_STR_NBW_2                       HASH_STR_NBLW_2
+#define HASH_STR_NBW_3                       HASH_STR_NBLW_3
+#define HASH_STR_NBW_4                       HASH_STR_NBLW_4
+
+/******************  Bits definition for HASH_IMR register  *******************/
+#define HASH_IMR_DINIE                       0x00000001U
+#define HASH_IMR_DCIE                        0x00000002U
+
+/* legacy defines */
+#define HASH_IMR_DINIM                       HASH_IMR_DINIE
+#define HASH_IMR_DCIM                        HASH_IMR_DCIE
+/******************  Bits definition for HASH_SR register  ********************/
+#define HASH_SR_DINIS                        0x00000001U
+#define HASH_SR_DCIS                         0x00000002U
+#define HASH_SR_DMAS                         0x00000004U
+#define HASH_SR_BUSY                         0x00000008U
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          0x00000001U        /*!< Peripheral enable                   */
+#define  I2C_CR1_TXIE                        0x00000002U        /*!< TX interrupt enable                 */
+#define  I2C_CR1_RXIE                        0x00000004U        /*!< RX interrupt enable                 */
+#define  I2C_CR1_ADDRIE                      0x00000008U        /*!< Address match interrupt enable      */
+#define  I2C_CR1_NACKIE                      0x00000010U        /*!< NACK received interrupt enable      */
+#define  I2C_CR1_STOPIE                      0x00000020U        /*!< STOP detection interrupt enable     */
+#define  I2C_CR1_TCIE                        0x00000040U        /*!< Transfer complete interrupt enable  */
+#define  I2C_CR1_ERRIE                       0x00000080U        /*!< Errors interrupt enable             */
+#define  I2C_CR1_DNF                         0x00000F00U        /*!< Digital noise filter                */
+#define  I2C_CR1_ANFOFF                      0x00001000U        /*!< Analog noise filter OFF             */
+#define  I2C_CR1_TXDMAEN                     0x00004000U        /*!< DMA transmission requests enable    */
+#define  I2C_CR1_RXDMAEN                     0x00008000U        /*!< DMA reception requests enable       */
+#define  I2C_CR1_SBC                         0x00010000U        /*!< Slave byte control                  */
+#define  I2C_CR1_NOSTRETCH                   0x00020000U        /*!< Clock stretching disable            */
+#define  I2C_CR1_GCEN                        0x00080000U        /*!< General call enable                 */
+#define  I2C_CR1_SMBHEN                      0x00100000U        /*!< SMBus host address enable           */
+#define  I2C_CR1_SMBDEN                      0x00200000U        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     0x00400000U        /*!< SMBus alert enable                  */
+#define  I2C_CR1_PECEN                       0x00800000U        /*!< PEC enable                          */
+
+/* Legacy define */
+#define  I2C_CR1_DFN                         I2C_CR1_DNF                   /*!< Digital noise filter                */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        0x000003FFU        /*!< Slave address (master mode)                             */
+#define  I2C_CR2_RD_WRN                      0x00000400U        /*!< Transfer direction (master mode)                        */
+#define  I2C_CR2_ADD10                       0x00000800U        /*!< 10-bit addressing mode (master mode)                    */
+#define  I2C_CR2_HEAD10R                     0x00001000U        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       0x00002000U        /*!< START generation                                        */
+#define  I2C_CR2_STOP                        0x00004000U        /*!< STOP generation (master mode)                           */
+#define  I2C_CR2_NACK                        0x00008000U        /*!< NACK generation (slave mode)                            */
+#define  I2C_CR2_NBYTES                      0x00FF0000U        /*!< Number of bytes                                         */
+#define  I2C_CR2_RELOAD                      0x01000000U        /*!< NBYTES reload mode                                      */
+#define  I2C_CR2_AUTOEND                     0x02000000U        /*!< Automatic end mode (master mode)                        */
+#define  I2C_CR2_PECBYTE                     0x04000000U        /*!< Packet error checking byte                              */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        0x000003FFU        /*!< Interface own address 1   */
+#define  I2C_OAR1_OA1MODE                    0x00000400U        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      0x00008000U        /*!< Own address 1 enable      */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        0x000000FEU        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     0x00000700U        /*!< Own address 2 masks     */
+#define  I2C_OAR2_OA2NOMASK                  0x00000000U        /*!< No mask */
+#define  I2C_OAR2_OA2MASK01                  0x00000100U        /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define  I2C_OAR2_OA2MASK02                  0x00000200U        /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define  I2C_OAR2_OA2MASK03                  0x00000300U        /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define  I2C_OAR2_OA2MASK04                  0x00000400U        /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define  I2C_OAR2_OA2MASK05                  0x00000500U        /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define  I2C_OAR2_OA2MASK06                  0x00000600U        /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define  I2C_OAR2_OA2MASK07                  0x00000700U        /*!< OA2[7:1] is masked, No comparison is done */
+#define  I2C_OAR2_OA2EN                      0x00008000U        /*!< Own address 2 enable    */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    0x000000FFU        /*!< SCL low period (master mode)  */
+#define  I2C_TIMINGR_SCLH                    0x0000FF00U        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  0x000F0000U        /*!< Data hold time                */
+#define  I2C_TIMINGR_SCLDEL                  0x00F00000U        /*!< Data setup time               */
+#define  I2C_TIMINGR_PRESC                   0xF0000000U        /*!< Timings prescaler             */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               0x00000FFFU        /*!< Bus timeout A                 */
+#define  I2C_TIMEOUTR_TIDLE                  0x00001000U        /*!< Idle clock timeout detection  */
+#define  I2C_TIMEOUTR_TIMOUTEN               0x00008000U        /*!< Clock timeout enable          */
+#define  I2C_TIMEOUTR_TIMEOUTB               0x0FFF0000U        /*!< Bus timeout B                 */
+#define  I2C_TIMEOUTR_TEXTEN                 0x80000000U        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         0x00000001U        /*!< Transmit data register empty    */
+#define  I2C_ISR_TXIS                        0x00000002U        /*!< Transmit interrupt status       */
+#define  I2C_ISR_RXNE                        0x00000004U        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        0x00000008U        /*!< Address matched (slave mode)    */
+#define  I2C_ISR_NACKF                       0x00000010U        /*!< NACK received flag              */
+#define  I2C_ISR_STOPF                       0x00000020U        /*!< STOP detection flag             */
+#define  I2C_ISR_TC                          0x00000040U        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         0x00000080U        /*!< Transfer complete reload        */
+#define  I2C_ISR_BERR                        0x00000100U        /*!< Bus error                       */
+#define  I2C_ISR_ARLO                        0x00000200U        /*!< Arbitration lost                */
+#define  I2C_ISR_OVR                         0x00000400U        /*!< Overrun/Underrun                */
+#define  I2C_ISR_PECERR                      0x00000800U        /*!< PEC error in reception          */
+#define  I2C_ISR_TIMEOUT                     0x00001000U        /*!< Timeout or Tlow detection flag  */
+#define  I2C_ISR_ALERT                       0x00002000U        /*!< SMBus alert                     */
+#define  I2C_ISR_BUSY                        0x00008000U        /*!< Bus busy                        */
+#define  I2C_ISR_DIR                         0x00010000U        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     0x00FE0000U        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      0x00000008U        /*!< Address matched clear flag      */
+#define  I2C_ICR_NACKCF                      0x00000010U        /*!< NACK clear flag                 */
+#define  I2C_ICR_STOPCF                      0x00000020U        /*!< STOP detection clear flag       */
+#define  I2C_ICR_BERRCF                      0x00000100U        /*!< Bus error clear flag            */
+#define  I2C_ICR_ARLOCF                      0x00000200U        /*!< Arbitration lost clear flag     */
+#define  I2C_ICR_OVRCF                       0x00000400U        /*!< Overrun/Underrun clear flag     */
+#define  I2C_ICR_PECCF                       0x00000800U        /*!< PAC error clear flag            */
+#define  I2C_ICR_TIMOUTCF                    0x00001000U        /*!< Timeout clear flag              */
+#define  I2C_ICR_ALERTCF                     0x00002000U        /*!< Alert clear flag                */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        0x000000FFU        /*!< PEC register        */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     0x000000FFU        /*!< 8-bit receive data  */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     0x000000FFU        /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         0x01U               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         0x02U               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         0x04U               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                       0x0FFFU             /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for LTDC_SSCR register  *****************/
+
+#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height  */
+#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */
+
+/********************  Bit definition for LTDC_BPCR register  *****************/
+
+#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch   */
+#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */
+
+/********************  Bit definition for LTDC_AWCR register  *****************/
+
+#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */
+
+/********************  Bit definition for LTDC_TWCR register  *****************/
+
+#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */
+
+/********************  Bit definition for LTDC_GCR register  ******************/
+
+#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit       */
+#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width                   */
+#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width                  */
+#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width                    */
+#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable                       */
+#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity                */
+#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity                */
+#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity   */
+#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */
+
+/* Legacy define */
+#define LTDC_GCR_DTEN                       LTDC_GCR_DEN
+
+/********************  Bit definition for LTDC_SRCR register  *****************/
+
+#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload         */
+#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */
+
+/********************  Bit definition for LTDC_BCCR register  *****************/
+
+#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value  */
+#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */
+#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value   */
+
+/********************  Bit definition for LTDC_IER register  ******************/
+
+#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable            */
+#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable   */
+#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable  */
+#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */
+
+/********************  Bit definition for LTDC_ISR register  ******************/
+
+#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_ICR register  ******************/
+
+#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_LIPCR register  ****************/
+
+#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */
+
+/********************  Bit definition for LTDC_CPSR register  *****************/
+
+#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */
+
+/********************  Bit definition for LTDC_CDSR register  *****************/
+
+#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status       */
+#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status     */
+#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status   */
+#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */
+
+/********************  Bit definition for LTDC_LxCR register  *****************/
+
+#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable              */
+#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable       */
+#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */
+
+/********************  Bit definition for LTDC_LxWHPCR register  **************/
+
+#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position  */
+
+/********************  Bit definition for LTDC_LxWVPCR register  **************/
+
+#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position  */
+
+/********************  Bit definition for LTDC_LxCKCR register  ***************/
+
+#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value  */
+#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value   */
+
+/********************  Bit definition for LTDC_LxPFCR register  ***************/
+
+#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */
+
+/********************  Bit definition for LTDC_LxCACR register  ***************/
+
+#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */
+
+/********************  Bit definition for LTDC_LxDCCR register  ***************/
+
+#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue  */
+#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red   */
+#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */
+                                
+/********************  Bit definition for LTDC_LxBFCR register  ***************/
+
+#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */
+
+/********************  Bit definition for LTDC_LxCFBAR register  **************/
+
+#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */
+
+/********************  Bit definition for LTDC_LxCFBLR register  **************/
+
+#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length    */
+#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */
+
+/********************  Bit definition for LTDC_LxCFBLNR register  *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */
+
+/********************  Bit definition for LTDC_LxCLUTWR register  *************/
+
+#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value   */
+#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value  */
+#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value    */
+#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CR1 register  ********************/
+#define  PWR_CR1_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR1_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */
+#define  PWR_CR1_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */
+#define  PWR_CR1_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */
+#define  PWR_CR1_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR1_PLS_0                        0x00000020U     /*!< Bit 0 */
+#define  PWR_CR1_PLS_1                        0x00000040U     /*!< Bit 1 */
+#define  PWR_CR1_PLS_2                        0x00000080U     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR1_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */
+#define  PWR_CR1_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */
+#define  PWR_CR1_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */
+#define  PWR_CR1_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */
+#define  PWR_CR1_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */
+#define  PWR_CR1_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */
+#define  PWR_CR1_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */
+#define  PWR_CR1_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */
+#define  PWR_CR1_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR1_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR1_LPUDS                        0x00000400U     /*!< Low-power regulator in deepsleep under-drive mode          */
+#define  PWR_CR1_MRUDS                        0x00000800U     /*!< Main regulator in deepsleep under-drive mode               */
+#define  PWR_CR1_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ 
+#define  PWR_CR1_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define  PWR_CR1_VOS_0                        0x00004000U     /*!< Bit 0 */
+#define  PWR_CR1_VOS_1                        0x00008000U     /*!< Bit 1 */
+#define  PWR_CR1_ODEN                         0x00010000U     /*!< Over Drive enable                   */
+#define  PWR_CR1_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */
+#define  PWR_CR1_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */
+#define  PWR_CR1_UDEN_0                       0x00040000U     /*!< Bit 0                               */
+#define  PWR_CR1_UDEN_1                       0x00080000U     /*!< Bit 1                               */
+
+/*******************  Bit definition for PWR_CSR1 register  ********************/
+#define  PWR_CSR1_WUIF                        0x00000001U     /*!< Wake up internal Flag                            */
+#define  PWR_CSR1_SBF                         0x00000002U     /*!< Standby Flag                                     */
+#define  PWR_CSR1_PVDO                        0x00000004U     /*!< PVD Output                                       */
+#define  PWR_CSR1_BRR                         0x00000008U     /*!< Backup regulator ready                           */
+#define  PWR_CSR1_EIWUP                       0x00000100U     /*!< Enable internal wakeup                           */
+#define  PWR_CSR1_BRE                         0x00000200U     /*!< Backup regulator enable                          */
+#define  PWR_CSR1_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */
+#define  PWR_CSR1_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */
+#define  PWR_CSR1_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */
+#define  PWR_CSR1_UDRDY                       0x000C0000U     /*!< Under Drive ready                                */
+
+/* Legacy define */
+#define  PWR_CSR1_UDSWRDY                     PWR_CSR1_UDRDY
+
+/********************  Bit definition for PWR_CR2 register  ********************/
+#define  PWR_CR2_CWUPF1                         0x00000001U     /*!< Clear Wakeup Pin Flag for PA0      */
+#define  PWR_CR2_CWUPF2                         0x00000002U     /*!< Clear Wakeup Pin Flag for PA2      */
+#define  PWR_CR2_CWUPF3                         0x00000004U     /*!< Clear Wakeup Pin Flag for PC1      */
+#define  PWR_CR2_CWUPF4                         0x00000008U     /*!< Clear Wakeup Pin Flag for PC13     */
+#define  PWR_CR2_CWUPF5                         0x00000010U     /*!< Clear Wakeup Pin Flag for PI8      */
+#define  PWR_CR2_CWUPF6                         0x00000020U     /*!< Clear Wakeup Pin Flag for PI11     */
+#define  PWR_CR2_WUPP1                          0x00000100U     /*!< Wakeup Pin Polarity bit for PA0    */
+#define  PWR_CR2_WUPP2                          0x00000200U     /*!< Wakeup Pin Polarity bit for PA2    */
+#define  PWR_CR2_WUPP3                          0x00000400U     /*!< Wakeup Pin Polarity bit for PC1    */
+#define  PWR_CR2_WUPP4                          0x00000800U     /*!< Wakeup Pin Polarity bit for PC13   */
+#define  PWR_CR2_WUPP5                          0x00001000U     /*!< Wakeup Pin Polarity bit for PI8    */
+#define  PWR_CR2_WUPP6                          0x00002000U     /*!< Wakeup Pin Polarity bit for PI11   */
+
+/*******************  Bit definition for PWR_CSR2 register  ********************/
+#define  PWR_CSR2_WUPF1                         0x00000001U     /*!< Wakeup Pin Flag for PA0            */
+#define  PWR_CSR2_WUPF2                         0x00000002U     /*!< Wakeup Pin Flag for PA2            */
+#define  PWR_CSR2_WUPF3                         0x00000004U     /*!< Wakeup Pin Flag for PC1            */
+#define  PWR_CSR2_WUPF4                         0x00000008U     /*!< Wakeup Pin Flag for PC13           */
+#define  PWR_CSR2_WUPF5                         0x00000010U     /*!< Wakeup Pin Flag for PI8            */
+#define  PWR_CSR2_WUPF6                         0x00000020U     /*!< Wakeup Pin Flag for PI11           */
+#define  PWR_CSR2_EWUP1                         0x00000100U     /*!< Enable Wakeup Pin PA0              */
+#define  PWR_CSR2_EWUP2                         0x00000200U     /*!< Enable Wakeup Pin PA2              */
+#define  PWR_CSR2_EWUP3                         0x00000400U     /*!< Enable Wakeup Pin PC1              */
+#define  PWR_CSR2_EWUP4                         0x00000800U     /*!< Enable Wakeup Pin PC13             */
+#define  PWR_CSR2_EWUP5                         0x00001000U     /*!< Enable Wakeup Pin PI8              */
+#define  PWR_CSR2_EWUP6                         0x00002000U     /*!< Enable Wakeup Pin PI11             */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/* QUADSPI IP version */
+#define QSPI1_V1_0
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                            */
+#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                     */
+#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                        */
+#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable            */
+#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< Sample Shift                      */
+#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                   */
+#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                      */
+#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[4:0] FIFO Level            */
+#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */
+#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */
+#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */
+#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */
+#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */
+#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */
+#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */
+#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */
+#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1                              */
+#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */
+#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */
+#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */
+#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */
+#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */
+#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */
+#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */
+#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */
+#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */
+#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */
+#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */
+#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */
+#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */
+#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */
+#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */
+#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */
+#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */
+#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */
+#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */
+#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */
+#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */
+#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */
+#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */
+#define  QUADSPI_SR_FLEVEL                       0x00001F00U             /*!< FIFO Threshlod Flag    */
+#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */
+#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */
+#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */
+#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */
+#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */
+#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */
+#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */
+#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define  QUADSPI_DLR_DL                          0xFFFFFFFFU             /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction    */
+#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */
+#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */
+#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */
+#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */
+#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */
+#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */
+#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */
+#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */
+#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode      */
+#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */
+#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */
+#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */
+#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */
+#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */
+#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */
+#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */
+#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */
+#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode              */
+#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode        */
+#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */
+#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */
+#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */
+#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */
+#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */ 
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        0x00000001U
+#define  RCC_CR_HSIRDY                       0x00000002U
+#define  RCC_CR_HSITRIM                      0x000000F8U
+#define  RCC_CR_HSITRIM_0                    0x00000008U /*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    0x00000010U /*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    0x00000020U /*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    0x00000040U /*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    0x00000080U /*!<Bit 4 */
+#define  RCC_CR_HSICAL                       0x0000FF00U
+#define  RCC_CR_HSICAL_0                     0x00000100U /*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     0x00000200U /*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     0x00000400U /*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     0x00000800U /*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     0x00001000U /*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     0x00002000U /*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     0x00004000U /*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     0x00008000U /*!<Bit 7 */
+#define  RCC_CR_HSEON                        0x00010000U
+#define  RCC_CR_HSERDY                       0x00020000U
+#define  RCC_CR_HSEBYP                       0x00040000U
+#define  RCC_CR_CSSON                        0x00080000U
+#define  RCC_CR_PLLON                        0x01000000U
+#define  RCC_CR_PLLRDY                       0x02000000U
+#define  RCC_CR_PLLI2SON                     0x04000000U
+#define  RCC_CR_PLLI2SRDY                    0x08000000U
+#define  RCC_CR_PLLSAION                     0x10000000U
+#define  RCC_CR_PLLSAIRDY                    0x20000000U
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define  RCC_PLLCFGR_PLLM                    0x0000003FU
+#define  RCC_PLLCFGR_PLLM_0                  0x00000001U
+#define  RCC_PLLCFGR_PLLM_1                  0x00000002U
+#define  RCC_PLLCFGR_PLLM_2                  0x00000004U
+#define  RCC_PLLCFGR_PLLM_3                  0x00000008U
+#define  RCC_PLLCFGR_PLLM_4                  0x00000010U
+#define  RCC_PLLCFGR_PLLM_5                  0x00000020U
+#define  RCC_PLLCFGR_PLLN                    0x00007FC0U
+#define  RCC_PLLCFGR_PLLN_0                  0x00000040U
+#define  RCC_PLLCFGR_PLLN_1                  0x00000080U
+#define  RCC_PLLCFGR_PLLN_2                  0x00000100U
+#define  RCC_PLLCFGR_PLLN_3                  0x00000200U
+#define  RCC_PLLCFGR_PLLN_4                  0x00000400U
+#define  RCC_PLLCFGR_PLLN_5                  0x00000800U
+#define  RCC_PLLCFGR_PLLN_6                  0x00001000U
+#define  RCC_PLLCFGR_PLLN_7                  0x00002000U
+#define  RCC_PLLCFGR_PLLN_8                  0x00004000U
+#define  RCC_PLLCFGR_PLLP                    0x00030000U
+#define  RCC_PLLCFGR_PLLP_0                  0x00010000U
+#define  RCC_PLLCFGR_PLLP_1                  0x00020000U
+#define  RCC_PLLCFGR_PLLSRC                  0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U
+#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U
+#define  RCC_PLLCFGR_PLLQ                    0x0F000000U
+#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U
+#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U
+#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U
+#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U
+
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */
+#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */
+#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define  RCC_CFGR_RTCPRE                     0x001F0000U
+#define  RCC_CFGR_RTCPRE_0                   0x00010000U
+#define  RCC_CFGR_RTCPRE_1                   0x00020000U
+#define  RCC_CFGR_RTCPRE_2                   0x00040000U
+#define  RCC_CFGR_RTCPRE_3                   0x00080000U
+#define  RCC_CFGR_RTCPRE_4                   0x00100000U
+
+/*!< MCO1 configuration */
+#define  RCC_CFGR_MCO1                       0x00600000U
+#define  RCC_CFGR_MCO1_0                     0x00200000U
+#define  RCC_CFGR_MCO1_1                     0x00400000U
+
+#define  RCC_CFGR_I2SSRC                     0x00800000U
+
+#define  RCC_CFGR_MCO1PRE                    0x07000000U
+#define  RCC_CFGR_MCO1PRE_0                  0x01000000U
+#define  RCC_CFGR_MCO1PRE_1                  0x02000000U
+#define  RCC_CFGR_MCO1PRE_2                  0x04000000U
+
+#define  RCC_CFGR_MCO2PRE                    0x38000000U
+#define  RCC_CFGR_MCO2PRE_0                  0x08000000U
+#define  RCC_CFGR_MCO2PRE_1                  0x10000000U
+#define  RCC_CFGR_MCO2PRE_2                  0x20000000U
+
+#define  RCC_CFGR_MCO2                       0xC0000000U
+#define  RCC_CFGR_MCO2_0                     0x40000000U
+#define  RCC_CFGR_MCO2_1                     0x80000000U
+
+/********************  Bit definition for RCC_CIR register  *******************/
+#define  RCC_CIR_LSIRDYF                     0x00000001U
+#define  RCC_CIR_LSERDYF                     0x00000002U
+#define  RCC_CIR_HSIRDYF                     0x00000004U
+#define  RCC_CIR_HSERDYF                     0x00000008U
+#define  RCC_CIR_PLLRDYF                     0x00000010U
+#define  RCC_CIR_PLLI2SRDYF                  0x00000020U
+#define  RCC_CIR_PLLSAIRDYF                  0x00000040U
+#define  RCC_CIR_CSSF                        0x00000080U
+#define  RCC_CIR_LSIRDYIE                    0x00000100U
+#define  RCC_CIR_LSERDYIE                    0x00000200U
+#define  RCC_CIR_HSIRDYIE                    0x00000400U
+#define  RCC_CIR_HSERDYIE                    0x00000800U
+#define  RCC_CIR_PLLRDYIE                    0x00001000U
+#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U
+#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U
+#define  RCC_CIR_LSIRDYC                     0x00010000U
+#define  RCC_CIR_LSERDYC                     0x00020000U
+#define  RCC_CIR_HSIRDYC                     0x00040000U
+#define  RCC_CIR_HSERDYC                     0x00080000U
+#define  RCC_CIR_PLLRDYC                     0x00100000U
+#define  RCC_CIR_PLLI2SRDYC                  0x00200000U
+#define  RCC_CIR_PLLSAIRDYC                  0x00400000U
+#define  RCC_CIR_CSSC                        0x00800000U
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define  RCC_AHB1RSTR_GPIOARST               0x00000001U
+#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U
+#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U
+#define  RCC_AHB1RSTR_GPIODRST               0x00000008U
+#define  RCC_AHB1RSTR_GPIOERST               0x00000010U
+#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U
+#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U
+#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U
+#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U
+#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U
+#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U
+#define  RCC_AHB1RSTR_CRCRST                 0x00001000U
+#define  RCC_AHB1RSTR_DMA1RST                0x00200000U
+#define  RCC_AHB1RSTR_DMA2RST                0x00400000U
+#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U
+#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U
+#define  RCC_AHB1RSTR_OTGHRST                0x20000000U
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define  RCC_AHB2RSTR_DCMIRST                0x00000001U
+#define  RCC_AHB2RSTR_CRYPRST                0x00000010U
+#define  RCC_AHB2RSTR_HASHRST                0x00000020U
+#define  RCC_AHB2RSTR_RNGRST                 0x00000040U
+#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+
+#define  RCC_AHB3RSTR_FMCRST                 0x00000001U
+#define  RCC_AHB3RSTR_QSPIRST                0x00000002U
+
+/********************  Bit definition for RCC_APB1RSTR register  **************/
+#define  RCC_APB1RSTR_TIM2RST                0x00000001U
+#define  RCC_APB1RSTR_TIM3RST                0x00000002U
+#define  RCC_APB1RSTR_TIM4RST                0x00000004U
+#define  RCC_APB1RSTR_TIM5RST                0x00000008U
+#define  RCC_APB1RSTR_TIM6RST                0x00000010U
+#define  RCC_APB1RSTR_TIM7RST                0x00000020U
+#define  RCC_APB1RSTR_TIM12RST               0x00000040U
+#define  RCC_APB1RSTR_TIM13RST               0x00000080U
+#define  RCC_APB1RSTR_TIM14RST               0x00000100U
+#define  RCC_APB1RSTR_LPTIM1RST              0x00000200U
+#define  RCC_APB1RSTR_WWDGRST                0x00000800U
+#define  RCC_APB1RSTR_SPI2RST                0x00004000U
+#define  RCC_APB1RSTR_SPI3RST                0x00008000U
+#define  RCC_APB1RSTR_SPDIFRXRST             0x00010000U
+#define  RCC_APB1RSTR_USART2RST              0x00020000U
+#define  RCC_APB1RSTR_USART3RST              0x00040000U
+#define  RCC_APB1RSTR_UART4RST               0x00080000U
+#define  RCC_APB1RSTR_UART5RST               0x00100000U
+#define  RCC_APB1RSTR_I2C1RST                0x00200000U
+#define  RCC_APB1RSTR_I2C2RST                0x00400000U
+#define  RCC_APB1RSTR_I2C3RST                0x00800000U
+#define  RCC_APB1RSTR_I2C4RST                0x01000000U
+#define  RCC_APB1RSTR_CAN1RST                0x02000000U
+#define  RCC_APB1RSTR_CAN2RST                0x04000000U
+#define  RCC_APB1RSTR_CECRST                 0x08000000U
+#define  RCC_APB1RSTR_PWRRST                 0x10000000U
+#define  RCC_APB1RSTR_DACRST                 0x20000000U
+#define  RCC_APB1RSTR_UART7RST               0x40000000U
+#define  RCC_APB1RSTR_UART8RST               0x80000000U
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define  RCC_APB2RSTR_TIM1RST                0x00000001U
+#define  RCC_APB2RSTR_TIM8RST                0x00000002U
+#define  RCC_APB2RSTR_USART1RST              0x00000010U
+#define  RCC_APB2RSTR_USART6RST              0x00000020U
+#define  RCC_APB2RSTR_ADCRST                 0x00000100U
+#define  RCC_APB2RSTR_SDMMC1RST              0x00000800U
+#define  RCC_APB2RSTR_SPI1RST                0x00001000U
+#define  RCC_APB2RSTR_SPI4RST                0x00002000U
+#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U
+#define  RCC_APB2RSTR_TIM9RST                0x00010000U
+#define  RCC_APB2RSTR_TIM10RST               0x00020000U
+#define  RCC_APB2RSTR_TIM11RST               0x00040000U
+#define  RCC_APB2RSTR_SPI5RST                0x00100000U
+#define  RCC_APB2RSTR_SPI6RST                0x00200000U
+#define  RCC_APB2RSTR_SAI1RST                0x00400000U
+#define  RCC_APB2RSTR_SAI2RST                0x00800000U
+#define  RCC_APB2RSTR_LTDCRST                0x04000000U
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U
+#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U
+#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U
+#define  RCC_AHB1ENR_GPIODEN                 0x00000008U
+#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U
+#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U
+#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U
+#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U
+#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U
+#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U
+#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U
+#define  RCC_AHB1ENR_CRCEN                   0x00001000U
+#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U
+#define  RCC_AHB1ENR_DTCMRAMEN               0x00100000U
+#define  RCC_AHB1ENR_DMA1EN                  0x00200000U
+#define  RCC_AHB1ENR_DMA2EN                  0x00400000U
+#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U
+#define  RCC_AHB1ENR_ETHMACEN                0x02000000U
+#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U
+#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U
+#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U
+#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U
+#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define  RCC_AHB2ENR_DCMIEN                  0x00000001U
+#define  RCC_AHB2ENR_CRYPEN                  0x00000010U
+#define  RCC_AHB2ENR_HASHEN                  0x00000020U
+#define  RCC_AHB2ENR_RNGEN                   0x00000040U
+#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+#define  RCC_AHB3ENR_FMCEN                  0x00000001U
+#define  RCC_AHB3ENR_QSPIEN                 0x00000002U
+
+/********************  Bit definition for RCC_APB1ENR register  ***************/
+#define  RCC_APB1ENR_TIM2EN                  0x00000001U
+#define  RCC_APB1ENR_TIM3EN                  0x00000002U
+#define  RCC_APB1ENR_TIM4EN                  0x00000004U
+#define  RCC_APB1ENR_TIM5EN                  0x00000008U
+#define  RCC_APB1ENR_TIM6EN                  0x00000010U
+#define  RCC_APB1ENR_TIM7EN                  0x00000020U
+#define  RCC_APB1ENR_TIM12EN                 0x00000040U
+#define  RCC_APB1ENR_TIM13EN                 0x00000080U
+#define  RCC_APB1ENR_TIM14EN                 0x00000100U
+#define  RCC_APB1ENR_LPTIM1EN                0x00000200U
+#define  RCC_APB1ENR_WWDGEN                  0x00000800U
+#define  RCC_APB1ENR_SPI2EN                  0x00004000U
+#define  RCC_APB1ENR_SPI3EN                  0x00008000U
+#define  RCC_APB1ENR_SPDIFRXEN               0x00010000U
+#define  RCC_APB1ENR_USART2EN                0x00020000U
+#define  RCC_APB1ENR_USART3EN                0x00040000U
+#define  RCC_APB1ENR_UART4EN                 0x00080000U
+#define  RCC_APB1ENR_UART5EN                 0x00100000U
+#define  RCC_APB1ENR_I2C1EN                  0x00200000U
+#define  RCC_APB1ENR_I2C2EN                  0x00400000U
+#define  RCC_APB1ENR_I2C3EN                  0x00800000U
+#define  RCC_APB1ENR_I2C4EN                  0x01000000U
+#define  RCC_APB1ENR_CAN1EN                  0x02000000U
+#define  RCC_APB1ENR_CAN2EN                  0x04000000U
+#define  RCC_APB1ENR_CECEN                   0x08000000U
+#define  RCC_APB1ENR_PWREN                   0x10000000U
+#define  RCC_APB1ENR_DACEN                   0x20000000U
+#define  RCC_APB1ENR_UART7EN                 0x40000000U
+#define  RCC_APB1ENR_UART8EN                 0x80000000U
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define  RCC_APB2ENR_TIM1EN                  0x00000001U
+#define  RCC_APB2ENR_TIM8EN                  0x00000002U
+#define  RCC_APB2ENR_USART1EN                0x00000010U
+#define  RCC_APB2ENR_USART6EN                0x00000020U
+#define  RCC_APB2ENR_ADC1EN                  0x00000100U
+#define  RCC_APB2ENR_ADC2EN                  0x00000200U
+#define  RCC_APB2ENR_ADC3EN                  0x00000400U
+#define  RCC_APB2ENR_SDMMC1EN                0x00000800U
+#define  RCC_APB2ENR_SPI1EN                  0x00001000U
+#define  RCC_APB2ENR_SPI4EN                  0x00002000U
+#define  RCC_APB2ENR_SYSCFGEN                0x00004000U
+#define  RCC_APB2ENR_TIM9EN                  0x00010000U
+#define  RCC_APB2ENR_TIM10EN                 0x00020000U
+#define  RCC_APB2ENR_TIM11EN                 0x00040000U
+#define  RCC_APB2ENR_SPI5EN                  0x00100000U
+#define  RCC_APB2ENR_SPI6EN                  0x00200000U
+#define  RCC_APB2ENR_SAI1EN                  0x00400000U
+#define  RCC_APB2ENR_SAI2EN                  0x00800000U
+#define  RCC_APB2ENR_LTDCEN                  0x04000000U
+
+/********************  Bit definition for RCC_AHB1LPENR register  *************/
+#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U
+#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U
+#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U
+#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U
+#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U
+#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U
+#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U
+#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U
+#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U
+#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U
+#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U
+#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U
+#define  RCC_AHB1LPENR_AXILPEN               0x00002000U
+#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U
+#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U
+#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U
+#define  RCC_AHB1LPENR_DTCMLPEN              0x00100000U
+#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U
+#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U
+#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U
+#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U
+#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U
+#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U
+#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U
+#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U
+
+/********************  Bit definition for RCC_AHB2LPENR register  *************/
+#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U
+#define  RCC_AHB2LPENR_CRYPLPEN              0x00000010U
+#define  RCC_AHB2LPENR_HASHLPEN              0x00000020U
+#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U
+#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U
+
+/********************  Bit definition for RCC_AHB3LPENR register  *************/
+#define  RCC_AHB3LPENR_FMCLPEN               0x00000001U
+#define  RCC_AHB3LPENR_QSPILPEN              0x00000002U
+/********************  Bit definition for RCC_APB1LPENR register  *************/
+#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U
+#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U
+#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U
+#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U
+#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U
+#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U
+#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U
+#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U
+#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U
+#define  RCC_APB1LPENR_LPTIM1LPEN            0x00000200U
+#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U
+#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U
+#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U
+#define  RCC_APB1LPENR_SPDIFRXLPEN           0x00010000U
+#define  RCC_APB1LPENR_USART2LPEN            0x00020000U
+#define  RCC_APB1LPENR_USART3LPEN            0x00040000U
+#define  RCC_APB1LPENR_UART4LPEN             0x00080000U
+#define  RCC_APB1LPENR_UART5LPEN             0x00100000U
+#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U
+#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U
+#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U
+#define  RCC_APB1LPENR_I2C4LPEN              0x01000000U
+#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U
+#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U
+#define  RCC_APB1LPENR_CECLPEN               0x08000000U
+#define  RCC_APB1LPENR_PWRLPEN               0x10000000U
+#define  RCC_APB1LPENR_DACLPEN               0x20000000U
+#define  RCC_APB1LPENR_UART7LPEN             0x40000000U
+#define  RCC_APB1LPENR_UART8LPEN             0x80000000U
+
+/********************  Bit definition for RCC_APB2LPENR register  *************/
+#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U
+#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U
+#define  RCC_APB2LPENR_USART1LPEN            0x00000010U
+#define  RCC_APB2LPENR_USART6LPEN            0x00000020U
+#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U
+#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U
+#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U
+#define  RCC_APB2LPENR_SDMMC1LPEN            0x00000800U
+#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U
+#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U
+#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U
+#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U
+#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U
+#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U
+#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U
+#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U
+#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U
+#define  RCC_APB2LPENR_SAI2LPEN              0x00800000U
+#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define  RCC_BDCR_LSEON                      0x00000001U
+#define  RCC_BDCR_LSERDY                     0x00000002U
+#define  RCC_BDCR_LSEBYP                     0x00000004U
+#define  RCC_BDCR_LSEDRV                     0x00000018U
+#define  RCC_BDCR_LSEDRV_0                   0x00000008U
+#define  RCC_BDCR_LSEDRV_1                   0x00000010U
+#define  RCC_BDCR_RTCSEL                     0x00000300U
+#define  RCC_BDCR_RTCSEL_0                   0x00000100U
+#define  RCC_BDCR_RTCSEL_1                   0x00000200U
+#define  RCC_BDCR_RTCEN                      0x00008000U
+#define  RCC_BDCR_BDRST                      0x00010000U
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define  RCC_CSR_LSION                       0x00000001U
+#define  RCC_CSR_LSIRDY                      0x00000002U
+#define  RCC_CSR_RMVF                        0x01000000U
+#define  RCC_CSR_BORRSTF                     0x02000000U
+#define  RCC_CSR_PINRSTF                     0x04000000U
+#define  RCC_CSR_PORRSTF                     0x08000000U
+#define  RCC_CSR_SFTRSTF                     0x10000000U
+#define  RCC_CSR_IWDGRSTF                    0x20000000U
+#define  RCC_CSR_WWDGRSTF                    0x40000000U
+#define  RCC_CSR_LPWRRSTF                    0x80000000U
+
+/********************  Bit definition for RCC_SSCGR register  *****************/
+#define  RCC_SSCGR_MODPER                    0x00001FFFU
+#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U
+#define  RCC_SSCGR_SPREADSEL                 0x40000000U
+#define  RCC_SSCGR_SSCGEN                    0x80000000U
+
+/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
+#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U
+#define  RCC_PLLI2SCFGR_PLLI2SP              0x00030000U
+#define  RCC_PLLI2SCFGR_PLLI2SP_0            0x00010000U
+#define  RCC_PLLI2SCFGR_PLLI2SP_1            0x00020000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U
+#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U
+
+/********************  Bit definition for RCC_PLLSAICFGR register  ************/
+#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U
+#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U
+#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U
+#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U
+#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U
+#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U
+#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U
+#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U
+#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U
+#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U
+#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U
+#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U
+#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U
+#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U
+#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U
+#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U
+#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U
+
+/********************  Bit definition for RCC_DCKCFGR1 register  ***************/
+#define  RCC_DCKCFGR1_PLLI2SDIVQ             0x0000001FU
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_0           0x00000001U
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_1           0x00000002U
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_2           0x00000004U
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_3           0x00000008U
+#define  RCC_DCKCFGR1_PLLI2SDIVQ_4           0x00000010U
+
+#define  RCC_DCKCFGR1_PLLSAIDIVQ             0x00001F00U
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_0           0x00000100U
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_1           0x00000200U
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_2           0x00000400U
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_3           0x00000800U
+#define  RCC_DCKCFGR1_PLLSAIDIVQ_4           0x00001000U
+
+#define  RCC_DCKCFGR1_PLLSAIDIVR             0x00030000U
+#define  RCC_DCKCFGR1_PLLSAIDIVR_0           0x00010000U
+#define  RCC_DCKCFGR1_PLLSAIDIVR_1           0x00020000U
+
+#define  RCC_DCKCFGR1_SAI1SEL                0x00300000U
+#define  RCC_DCKCFGR1_SAI1SEL_0              0x00100000U
+#define  RCC_DCKCFGR1_SAI1SEL_1              0x00200000U
+
+#define  RCC_DCKCFGR1_SAI2SEL                0x00C00000U
+#define  RCC_DCKCFGR1_SAI2SEL_0              0x00400000U
+#define  RCC_DCKCFGR1_SAI2SEL_1              0x00800000U
+
+#define  RCC_DCKCFGR1_TIMPRE                 0x01000000U
+
+/********************  Bit definition for RCC_DCKCFGR2 register  ***************/
+#define  RCC_DCKCFGR2_USART1SEL              0x00000003U
+#define  RCC_DCKCFGR2_USART1SEL_0            0x00000001U
+#define  RCC_DCKCFGR2_USART1SEL_1            0x00000002U
+#define  RCC_DCKCFGR2_USART2SEL              0x0000000CU
+#define  RCC_DCKCFGR2_USART2SEL_0            0x00000004U
+#define  RCC_DCKCFGR2_USART2SEL_1            0x00000008U
+#define  RCC_DCKCFGR2_USART3SEL              0x00000030U
+#define  RCC_DCKCFGR2_USART3SEL_0            0x00000010U
+#define  RCC_DCKCFGR2_USART3SEL_1            0x00000020U
+#define  RCC_DCKCFGR2_UART4SEL               0x000000C0U
+#define  RCC_DCKCFGR2_UART4SEL_0             0x00000040U
+#define  RCC_DCKCFGR2_UART4SEL_1             0x00000080U
+#define  RCC_DCKCFGR2_UART5SEL               0x00000300U
+#define  RCC_DCKCFGR2_UART5SEL_0             0x00000100U
+#define  RCC_DCKCFGR2_UART5SEL_1             0x00000200U
+#define  RCC_DCKCFGR2_USART6SEL              0x00000C00U
+#define  RCC_DCKCFGR2_USART6SEL_0            0x00000400U
+#define  RCC_DCKCFGR2_USART6SEL_1            0x00000800U
+#define  RCC_DCKCFGR2_UART7SEL               0x00003000U
+#define  RCC_DCKCFGR2_UART7SEL_0             0x00001000U
+#define  RCC_DCKCFGR2_UART7SEL_1             0x00002000U
+#define  RCC_DCKCFGR2_UART8SEL               0x0000C000U
+#define  RCC_DCKCFGR2_UART8SEL_0             0x00004000U
+#define  RCC_DCKCFGR2_UART8SEL_1             0x00008000U
+#define  RCC_DCKCFGR2_I2C1SEL                0x00030000U
+#define  RCC_DCKCFGR2_I2C1SEL_0              0x00010000U
+#define  RCC_DCKCFGR2_I2C1SEL_1              0x00020000U
+#define  RCC_DCKCFGR2_I2C2SEL                0x000C0000U
+#define  RCC_DCKCFGR2_I2C2SEL_0              0x00040000U
+#define  RCC_DCKCFGR2_I2C2SEL_1              0x00080000U
+#define  RCC_DCKCFGR2_I2C3SEL                0x00300000U
+#define  RCC_DCKCFGR2_I2C3SEL_0              0x00100000U
+#define  RCC_DCKCFGR2_I2C3SEL_1              0x00200000U
+#define  RCC_DCKCFGR2_I2C4SEL                0x00C00000U
+#define  RCC_DCKCFGR2_I2C4SEL_0              0x00400000U
+#define  RCC_DCKCFGR2_I2C4SEL_1              0x00800000U
+#define  RCC_DCKCFGR2_LPTIM1SEL              0x03000000U
+#define  RCC_DCKCFGR2_LPTIM1SEL_0            0x01000000U
+#define  RCC_DCKCFGR2_LPTIM1SEL_1            0x02000000U
+#define  RCC_DCKCFGR2_CECSEL                 0x04000000U
+#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U
+#define  RCC_DCKCFGR2_SDMMC1SEL              0x10000000U
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN                         0x00000004U
+#define RNG_CR_IE                            0x00000008U
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY                          0x00000001U
+#define RNG_SR_CECS                          0x00000002U
+#define RNG_SR_SECS                          0x00000004U
+#define RNG_SR_CEIS                          0x00000020U
+#define RNG_SR_SEIS                          0x00000040U
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            0x00400000U
+#define RTC_TR_HT                            0x00300000U
+#define RTC_TR_HT_0                          0x00100000U
+#define RTC_TR_HT_1                          0x00200000U
+#define RTC_TR_HU                            0x000F0000U
+#define RTC_TR_HU_0                          0x00010000U
+#define RTC_TR_HU_1                          0x00020000U
+#define RTC_TR_HU_2                          0x00040000U
+#define RTC_TR_HU_3                          0x00080000U
+#define RTC_TR_MNT                           0x00007000U
+#define RTC_TR_MNT_0                         0x00001000U
+#define RTC_TR_MNT_1                         0x00002000U
+#define RTC_TR_MNT_2                         0x00004000U
+#define RTC_TR_MNU                           0x00000F00U
+#define RTC_TR_MNU_0                         0x00000100U
+#define RTC_TR_MNU_1                         0x00000200U
+#define RTC_TR_MNU_2                         0x00000400U
+#define RTC_TR_MNU_3                         0x00000800U
+#define RTC_TR_ST                            0x00000070U
+#define RTC_TR_ST_0                          0x00000010U
+#define RTC_TR_ST_1                          0x00000020U
+#define RTC_TR_ST_2                          0x00000040U
+#define RTC_TR_SU                            0x0000000FU
+#define RTC_TR_SU_0                          0x00000001U
+#define RTC_TR_SU_1                          0x00000002U
+#define RTC_TR_SU_2                          0x00000004U
+#define RTC_TR_SU_3                          0x00000008U
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            0x00F00000U
+#define RTC_DR_YT_0                          0x00100000U
+#define RTC_DR_YT_1                          0x00200000U
+#define RTC_DR_YT_2                          0x00400000U
+#define RTC_DR_YT_3                          0x00800000U
+#define RTC_DR_YU                            0x000F0000U
+#define RTC_DR_YU_0                          0x00010000U
+#define RTC_DR_YU_1                          0x00020000U
+#define RTC_DR_YU_2                          0x00040000U
+#define RTC_DR_YU_3                          0x00080000U
+#define RTC_DR_WDU                           0x0000E000U
+#define RTC_DR_WDU_0                         0x00002000U
+#define RTC_DR_WDU_1                         0x00004000U
+#define RTC_DR_WDU_2                         0x00008000U
+#define RTC_DR_MT                            0x00001000U
+#define RTC_DR_MU                            0x00000F00U
+#define RTC_DR_MU_0                          0x00000100U
+#define RTC_DR_MU_1                          0x00000200U
+#define RTC_DR_MU_2                          0x00000400U
+#define RTC_DR_MU_3                          0x00000800U
+#define RTC_DR_DT                            0x00000030U
+#define RTC_DR_DT_0                          0x00000010U
+#define RTC_DR_DT_1                          0x00000020U
+#define RTC_DR_DU                            0x0000000FU
+#define RTC_DR_DU_0                          0x00000001U
+#define RTC_DR_DU_1                          0x00000002U
+#define RTC_DR_DU_2                          0x00000004U
+#define RTC_DR_DU_3                          0x00000008U
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE                          0x01000000U 
+#define RTC_CR_COE                           0x00800000U
+#define RTC_CR_OSEL                          0x00600000U
+#define RTC_CR_OSEL_0                        0x00200000U
+#define RTC_CR_OSEL_1                        0x00400000U
+#define RTC_CR_POL                           0x00100000U
+#define RTC_CR_COSEL                         0x00080000U
+#define RTC_CR_BCK                           0x00040000U
+#define RTC_CR_SUB1H                         0x00020000U
+#define RTC_CR_ADD1H                         0x00010000U
+#define RTC_CR_TSIE                          0x00008000U
+#define RTC_CR_WUTIE                         0x00004000U
+#define RTC_CR_ALRBIE                        0x00002000U
+#define RTC_CR_ALRAIE                        0x00001000U
+#define RTC_CR_TSE                           0x00000800U
+#define RTC_CR_WUTE                          0x00000400U
+#define RTC_CR_ALRBE                         0x00000200U
+#define RTC_CR_ALRAE                         0x00000100U
+#define RTC_CR_FMT                           0x00000040U
+#define RTC_CR_BYPSHAD                       0x00000020U
+#define RTC_CR_REFCKON                       0x00000010U
+#define RTC_CR_TSEDGE                        0x00000008U
+#define RTC_CR_WUCKSEL                       0x00000007U
+#define RTC_CR_WUCKSEL_0                     0x00000001U
+#define RTC_CR_WUCKSEL_1                     0x00000002U
+#define RTC_CR_WUCKSEL_2                     0x00000004U
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF                         0x00020000U
+#define RTC_ISR_RECALPF                      0x00010000U
+#define RTC_ISR_TAMP3F                       0x00008000U
+#define RTC_ISR_TAMP2F                       0x00004000U
+#define RTC_ISR_TAMP1F                       0x00002000U
+#define RTC_ISR_TSOVF                        0x00001000U
+#define RTC_ISR_TSF                          0x00000800U
+#define RTC_ISR_WUTF                         0x00000400U
+#define RTC_ISR_ALRBF                        0x00000200U
+#define RTC_ISR_ALRAF                        0x00000100U
+#define RTC_ISR_INIT                         0x00000080U
+#define RTC_ISR_INITF                        0x00000040U
+#define RTC_ISR_RSF                          0x00000020U
+#define RTC_ISR_INITS                        0x00000010U
+#define RTC_ISR_SHPF                         0x00000008U
+#define RTC_ISR_WUTWF                        0x00000004U
+#define RTC_ISR_ALRBWF                       0x00000002U
+#define RTC_ISR_ALRAWF                       0x00000001U
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    0x007F0000U
+#define RTC_PRER_PREDIV_S                    0x00007FFFU
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT                         0x0000FFFFU
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      0x80000000U
+#define RTC_ALRMAR_WDSEL                     0x40000000U
+#define RTC_ALRMAR_DT                        0x30000000U
+#define RTC_ALRMAR_DT_0                      0x10000000U
+#define RTC_ALRMAR_DT_1                      0x20000000U
+#define RTC_ALRMAR_DU                        0x0F000000U
+#define RTC_ALRMAR_DU_0                      0x01000000U
+#define RTC_ALRMAR_DU_1                      0x02000000U
+#define RTC_ALRMAR_DU_2                      0x04000000U
+#define RTC_ALRMAR_DU_3                      0x08000000U
+#define RTC_ALRMAR_MSK3                      0x00800000U
+#define RTC_ALRMAR_PM                        0x00400000U
+#define RTC_ALRMAR_HT                        0x00300000U
+#define RTC_ALRMAR_HT_0                      0x00100000U
+#define RTC_ALRMAR_HT_1                      0x00200000U
+#define RTC_ALRMAR_HU                        0x000F0000U
+#define RTC_ALRMAR_HU_0                      0x00010000U
+#define RTC_ALRMAR_HU_1                      0x00020000U
+#define RTC_ALRMAR_HU_2                      0x00040000U
+#define RTC_ALRMAR_HU_3                      0x00080000U
+#define RTC_ALRMAR_MSK2                      0x00008000U
+#define RTC_ALRMAR_MNT                       0x00007000U
+#define RTC_ALRMAR_MNT_0                     0x00001000U
+#define RTC_ALRMAR_MNT_1                     0x00002000U
+#define RTC_ALRMAR_MNT_2                     0x00004000U
+#define RTC_ALRMAR_MNU                       0x00000F00U
+#define RTC_ALRMAR_MNU_0                     0x00000100U
+#define RTC_ALRMAR_MNU_1                     0x00000200U
+#define RTC_ALRMAR_MNU_2                     0x00000400U
+#define RTC_ALRMAR_MNU_3                     0x00000800U
+#define RTC_ALRMAR_MSK1                      0x00000080U
+#define RTC_ALRMAR_ST                        0x00000070U
+#define RTC_ALRMAR_ST_0                      0x00000010U
+#define RTC_ALRMAR_ST_1                      0x00000020U
+#define RTC_ALRMAR_ST_2                      0x00000040U
+#define RTC_ALRMAR_SU                        0x0000000FU
+#define RTC_ALRMAR_SU_0                      0x00000001U
+#define RTC_ALRMAR_SU_1                      0x00000002U
+#define RTC_ALRMAR_SU_2                      0x00000004U
+#define RTC_ALRMAR_SU_3                      0x00000008U
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4                      0x80000000U
+#define RTC_ALRMBR_WDSEL                     0x40000000U
+#define RTC_ALRMBR_DT                        0x30000000U
+#define RTC_ALRMBR_DT_0                      0x10000000U
+#define RTC_ALRMBR_DT_1                      0x20000000U
+#define RTC_ALRMBR_DU                        0x0F000000U
+#define RTC_ALRMBR_DU_0                      0x01000000U
+#define RTC_ALRMBR_DU_1                      0x02000000U
+#define RTC_ALRMBR_DU_2                      0x04000000U
+#define RTC_ALRMBR_DU_3                      0x08000000U
+#define RTC_ALRMBR_MSK3                      0x00800000U
+#define RTC_ALRMBR_PM                        0x00400000U
+#define RTC_ALRMBR_HT                        0x00300000U
+#define RTC_ALRMBR_HT_0                      0x00100000U
+#define RTC_ALRMBR_HT_1                      0x00200000U
+#define RTC_ALRMBR_HU                        0x000F0000U
+#define RTC_ALRMBR_HU_0                      0x00010000U
+#define RTC_ALRMBR_HU_1                      0x00020000U
+#define RTC_ALRMBR_HU_2                      0x00040000U
+#define RTC_ALRMBR_HU_3                      0x00080000U
+#define RTC_ALRMBR_MSK2                      0x00008000U
+#define RTC_ALRMBR_MNT                       0x00007000U
+#define RTC_ALRMBR_MNT_0                     0x00001000U
+#define RTC_ALRMBR_MNT_1                     0x00002000U
+#define RTC_ALRMBR_MNT_2                     0x00004000U
+#define RTC_ALRMBR_MNU                       0x00000F00U
+#define RTC_ALRMBR_MNU_0                     0x00000100U
+#define RTC_ALRMBR_MNU_1                     0x00000200U
+#define RTC_ALRMBR_MNU_2                     0x00000400U
+#define RTC_ALRMBR_MNU_3                     0x00000800U
+#define RTC_ALRMBR_MSK1                      0x00000080U
+#define RTC_ALRMBR_ST                        0x00000070U
+#define RTC_ALRMBR_ST_0                      0x00000010U
+#define RTC_ALRMBR_ST_1                      0x00000020U
+#define RTC_ALRMBR_ST_2                      0x00000040U
+#define RTC_ALRMBR_SU                        0x0000000FU
+#define RTC_ALRMBR_SU_0                      0x00000001U
+#define RTC_ALRMBR_SU_1                      0x00000002U
+#define RTC_ALRMBR_SU_2                      0x00000004U
+#define RTC_ALRMBR_SU_3                      0x00000008U
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          0x000000FFU
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           0x0000FFFFU
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     0x00007FFFU
+#define RTC_SHIFTR_ADD1S                     0x80000000U
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          0x00400000U
+#define RTC_TSTR_HT                          0x00300000U
+#define RTC_TSTR_HT_0                        0x00100000U
+#define RTC_TSTR_HT_1                        0x00200000U
+#define RTC_TSTR_HU                          0x000F0000U
+#define RTC_TSTR_HU_0                        0x00010000U
+#define RTC_TSTR_HU_1                        0x00020000U
+#define RTC_TSTR_HU_2                        0x00040000U
+#define RTC_TSTR_HU_3                        0x00080000U
+#define RTC_TSTR_MNT                         0x00007000U
+#define RTC_TSTR_MNT_0                       0x00001000U
+#define RTC_TSTR_MNT_1                       0x00002000U
+#define RTC_TSTR_MNT_2                       0x00004000U
+#define RTC_TSTR_MNU                         0x00000F00U
+#define RTC_TSTR_MNU_0                       0x00000100U
+#define RTC_TSTR_MNU_1                       0x00000200U
+#define RTC_TSTR_MNU_2                       0x00000400U
+#define RTC_TSTR_MNU_3                       0x00000800U
+#define RTC_TSTR_ST                          0x00000070U
+#define RTC_TSTR_ST_0                        0x00000010U
+#define RTC_TSTR_ST_1                        0x00000020U
+#define RTC_TSTR_ST_2                        0x00000040U
+#define RTC_TSTR_SU                          0x0000000FU
+#define RTC_TSTR_SU_0                        0x00000001U
+#define RTC_TSTR_SU_1                        0x00000002U
+#define RTC_TSTR_SU_2                        0x00000004U
+#define RTC_TSTR_SU_3                        0x00000008U
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         0x0000E000U
+#define RTC_TSDR_WDU_0                       0x00002000U
+#define RTC_TSDR_WDU_1                       0x00004000U
+#define RTC_TSDR_WDU_2                       0x00008000U
+#define RTC_TSDR_MT                          0x00001000U
+#define RTC_TSDR_MU                          0x00000F00U
+#define RTC_TSDR_MU_0                        0x00000100U
+#define RTC_TSDR_MU_1                        0x00000200U
+#define RTC_TSDR_MU_2                        0x00000400U
+#define RTC_TSDR_MU_3                        0x00000800U
+#define RTC_TSDR_DT                          0x00000030U
+#define RTC_TSDR_DT_0                        0x00000010U
+#define RTC_TSDR_DT_1                        0x00000020U
+#define RTC_TSDR_DU                          0x0000000FU
+#define RTC_TSDR_DU_0                        0x00000001U
+#define RTC_TSDR_DU_1                        0x00000002U
+#define RTC_TSDR_DU_2                        0x00000004U
+#define RTC_TSDR_DU_3                        0x00000008U
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         0x0000FFFFU
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP                        0x00008000U
+#define RTC_CALR_CALW8                       0x00004000U
+#define RTC_CALR_CALW16                      0x00002000U
+#define RTC_CALR_CALM                        0x000001FFU
+#define RTC_CALR_CALM_0                      0x00000001U
+#define RTC_CALR_CALM_1                      0x00000002U
+#define RTC_CALR_CALM_2                      0x00000004U
+#define RTC_CALR_CALM_3                      0x00000008U
+#define RTC_CALR_CALM_4                      0x00000010U
+#define RTC_CALR_CALM_5                      0x00000020U
+#define RTC_CALR_CALM_6                      0x00000040U
+#define RTC_CALR_CALM_7                      0x00000080U
+#define RTC_CALR_CALM_8                      0x00000100U
+
+/********************  Bits definition for RTC_TAMPCR register  ****************/
+#define RTC_TAMPCR_TAMP3MF                   0x01000000U
+#define RTC_TAMPCR_TAMP3NOERASE              0x00800000U
+#define RTC_TAMPCR_TAMP3IE                   0x00400000U
+#define RTC_TAMPCR_TAMP2MF                   0x00200000U
+#define RTC_TAMPCR_TAMP2NOERASE              0x00100000U
+#define RTC_TAMPCR_TAMP2IE                   0x00080000U
+#define RTC_TAMPCR_TAMP1MF                   0x00040000U
+#define RTC_TAMPCR_TAMP1NOERASE              0x00020000U
+#define RTC_TAMPCR_TAMP1IE                   0x00010000U
+#define RTC_TAMPCR_TAMPPUDIS                 0x00008000U
+#define RTC_TAMPCR_TAMPPRCH                  0x00006000U
+#define RTC_TAMPCR_TAMPPRCH_0                0x00002000U
+#define RTC_TAMPCR_TAMPPRCH_1                0x00004000U
+#define RTC_TAMPCR_TAMPFLT                   0x00001800U
+#define RTC_TAMPCR_TAMPFLT_0                 0x00000800U
+#define RTC_TAMPCR_TAMPFLT_1                 0x00001000U
+#define RTC_TAMPCR_TAMPFREQ                  0x00000700U
+#define RTC_TAMPCR_TAMPFREQ_0                0x00000100U
+#define RTC_TAMPCR_TAMPFREQ_1                0x00000200U
+#define RTC_TAMPCR_TAMPFREQ_2                0x00000400U
+#define RTC_TAMPCR_TAMPTS                    0x00000080U
+#define RTC_TAMPCR_TAMP3TRG                  0x00000040U
+#define RTC_TAMPCR_TAMP3E                    0x00000020U
+#define RTC_TAMPCR_TAMP2TRG                  0x00000010U
+#define RTC_TAMPCR_TAMP2E                    0x00000008U
+#define RTC_TAMPCR_TAMPIE                    0x00000004U
+#define RTC_TAMPCR_TAMP1TRG                  0x00000002U
+#define RTC_TAMPCR_TAMP1E                    0x00000001U
+
+/* Legacy defines */
+#define RTC_TAMPCR_TAMP3_TRG                  RTC_TAMPCR_TAMP3TRG
+#define RTC_TAMPCR_TAMP2_TRG                  RTC_TAMPCR_TAMP2TRG
+#define RTC_TAMPCR_TAMP1_TRG                  RTC_TAMPCR_TAMP1TRG
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0                0x01000000U
+#define RTC_ALRMASSR_MASKSS_1                0x02000000U
+#define RTC_ALRMASSR_MASKSS_2                0x04000000U
+#define RTC_ALRMASSR_MASKSS_3                0x08000000U
+#define RTC_ALRMASSR_SS                      0x00007FFFU
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS                  0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0                0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1                0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2                0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3                0x08000000U
+#define RTC_ALRMBSSR_SS                      0x00007FFFU
+
+/********************  Bits definition for RTC_OR register  ****************/
+#define RTC_OR_TSINSEL                       0x00000006U
+#define RTC_OR_TSINSEL_0                     0x00000002U
+#define RTC_OR_TSINSEL_1                     0x00000004U
+#define RTC_OR_ALARMTYPE                     0x00000008U
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R                            0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R                           0xFFFFFFFFU
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R                           0xFFFFFFFFU
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       0x00000020U
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define  SAI_GCR_SYNCIN                      0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define  SAI_GCR_SYNCIN_0                    0x00000001U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCIN_1                    0x00000002U        /*!<Bit 1 */
+                                             
+#define  SAI_GCR_SYNCOUT                     0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define  SAI_GCR_SYNCOUT_0                   0x00000010U        /*!<Bit 0 */
+#define  SAI_GCR_SYNCOUT_1                   0x00000020U        /*!<Bit 1 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define  SAI_xCR1_MODE                       0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define  SAI_xCR1_MODE_0                     0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR1_MODE_1                     0x00000002U        /*!<Bit 1 */
+                                             
+#define  SAI_xCR1_PRTCFG                     0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define  SAI_xCR1_PRTCFG_0                   0x00000004U        /*!<Bit 0 */
+#define  SAI_xCR1_PRTCFG_1                   0x00000008U        /*!<Bit 1 */
+                                             
+#define  SAI_xCR1_DS                         0x000000E0U        /*!<DS[1:0] bits (Data Size) */
+#define  SAI_xCR1_DS_0                       0x00000020U        /*!<Bit 0 */
+#define  SAI_xCR1_DS_1                       0x00000040U        /*!<Bit 1 */
+#define  SAI_xCR1_DS_2                       0x00000080U        /*!<Bit 2 */
+                                             
+#define  SAI_xCR1_LSBFIRST                   0x00000100U        /*!<LSB First Configuration  */
+#define  SAI_xCR1_CKSTR                      0x00000200U        /*!<ClocK STRobing edge      */
+                                             
+#define  SAI_xCR1_SYNCEN                     0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define  SAI_xCR1_SYNCEN_0                   0x00000400U        /*!<Bit 0 */
+#define  SAI_xCR1_SYNCEN_1                   0x00000800U        /*!<Bit 1 */
+                                             
+#define  SAI_xCR1_MONO                       0x00001000U        /*!<Mono mode                  */
+#define  SAI_xCR1_OUTDRIV                    0x00002000U        /*!<Output Drive               */
+#define  SAI_xCR1_SAIEN                      0x00010000U        /*!<Audio Block enable         */
+#define  SAI_xCR1_DMAEN                      0x00020000U        /*!<DMA enable                 */
+#define  SAI_xCR1_NODIV                      0x00080000U        /*!<No Divider Configuration   */
+                                             
+#define  SAI_xCR1_MCKDIV                     0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define  SAI_xCR1_MCKDIV_0                   0x00100000U        /*!<Bit 0  */
+#define  SAI_xCR1_MCKDIV_1                   0x00200000U        /*!<Bit 1  */
+#define  SAI_xCR1_MCKDIV_2                   0x00400000U        /*!<Bit 2  */
+#define  SAI_xCR1_MCKDIV_3                   0x00800000U        /*!<Bit 3  */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define  SAI_xCR2_FTH                        0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */
+#define  SAI_xCR2_FTH_0                      0x00000001U        /*!<Bit 0 */
+#define  SAI_xCR2_FTH_1                      0x00000002U        /*!<Bit 1 */
+#define  SAI_xCR2_FTH_2                      0x00000004U        /*!<Bit 2 */
+                                             
+#define  SAI_xCR2_FFLUSH                     0x00000008U        /*!<Fifo FLUSH                       */
+#define  SAI_xCR2_TRIS                       0x00000010U        /*!<TRIState Management on data line */
+#define  SAI_xCR2_MUTE                       0x00000020U        /*!<Mute mode                        */
+#define  SAI_xCR2_MUTEVAL                    0x00000040U        /*!<Muate value                      */
+                                             
+#define  SAI_xCR2_MUTECNT                    0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */
+#define  SAI_xCR2_MUTECNT_0                  0x00000080U        /*!<Bit 0 */
+#define  SAI_xCR2_MUTECNT_1                  0x00000100U        /*!<Bit 1 */
+#define  SAI_xCR2_MUTECNT_2                  0x00000200U        /*!<Bit 2 */
+#define  SAI_xCR2_MUTECNT_3                  0x00000400U        /*!<Bit 3 */
+#define  SAI_xCR2_MUTECNT_4                  0x00000800U        /*!<Bit 4 */
+#define  SAI_xCR2_MUTECNT_5                  0x00001000U        /*!<Bit 5 */
+                                             
+#define  SAI_xCR2_CPL                        0x00002000U        /*!< Complement Bit             */
+                                             
+#define  SAI_xCR2_COMP                       0x0000C000U        /*!<COMP[1:0] (Companding mode) */
+#define  SAI_xCR2_COMP_0                     0x00004000U        /*!<Bit 0 */
+#define  SAI_xCR2_COMP_1                     0x00008000U        /*!<Bit 1 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define  SAI_xFRCR_FRL                       0x000000FFU        /*!<FRL[1:0](Frame length)  */
+#define  SAI_xFRCR_FRL_0                     0x00000001U        /*!<Bit 0 */
+#define  SAI_xFRCR_FRL_1                     0x00000002U        /*!<Bit 1 */
+#define  SAI_xFRCR_FRL_2                     0x00000004U        /*!<Bit 2 */
+#define  SAI_xFRCR_FRL_3                     0x00000008U        /*!<Bit 3 */
+#define  SAI_xFRCR_FRL_4                     0x00000010U        /*!<Bit 4 */
+#define  SAI_xFRCR_FRL_5                     0x00000020U        /*!<Bit 5 */
+#define  SAI_xFRCR_FRL_6                     0x00000040U        /*!<Bit 6 */
+#define  SAI_xFRCR_FRL_7                     0x00000080U        /*!<Bit 7 */
+                                                        
+#define  SAI_xFRCR_FSALL                     0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */
+#define  SAI_xFRCR_FSALL_0                   0x00000100U        /*!<Bit 0 */
+#define  SAI_xFRCR_FSALL_1                   0x00000200U        /*!<Bit 1 */
+#define  SAI_xFRCR_FSALL_2                   0x00000400U        /*!<Bit 2 */
+#define  SAI_xFRCR_FSALL_3                   0x00000800U        /*!<Bit 3 */
+#define  SAI_xFRCR_FSALL_4                   0x00001000U        /*!<Bit 4 */
+#define  SAI_xFRCR_FSALL_5                   0x00002000U        /*!<Bit 5 */
+#define  SAI_xFRCR_FSALL_6                   0x00004000U        /*!<Bit 6 */
+                                                        
+#define  SAI_xFRCR_FSDEF                     0x00010000U        /*!<Frame Synchronization Definition  */
+#define  SAI_xFRCR_FSPOL                     0x00020000U        /*!<Frame Synchronization POLarity    */
+#define  SAI_xFRCR_FSOFF                     0x00040000U        /*!<Frame Synchronization OFFset      */
+                                             
+/* Legacy define */                          
+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define  SAI_xSLOTR_FBOFF                    0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */
+#define  SAI_xSLOTR_FBOFF_0                  0x00000001U        /*!<Bit 0 */
+#define  SAI_xSLOTR_FBOFF_1                  0x00000002U        /*!<Bit 1 */
+#define  SAI_xSLOTR_FBOFF_2                  0x00000004U        /*!<Bit 2 */
+#define  SAI_xSLOTR_FBOFF_3                  0x00000008U        /*!<Bit 3 */
+#define  SAI_xSLOTR_FBOFF_4                  0x00000010U        /*!<Bit 4 */
+                                            
+#define  SAI_xSLOTR_SLOTSZ                   0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */
+#define  SAI_xSLOTR_SLOTSZ_0                 0x00000040U        /*!<Bit 0 */
+#define  SAI_xSLOTR_SLOTSZ_1                 0x00000080U        /*!<Bit 1 */
+                                            
+#define  SAI_xSLOTR_NBSLOT                   0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define  SAI_xSLOTR_NBSLOT_0                 0x00000100U        /*!<Bit 0 */
+#define  SAI_xSLOTR_NBSLOT_1                 0x00000200U        /*!<Bit 1 */
+#define  SAI_xSLOTR_NBSLOT_2                 0x00000400U        /*!<Bit 2 */
+#define  SAI_xSLOTR_NBSLOT_3                 0x00000800U        /*!<Bit 3 */
+                                            
+#define  SAI_xSLOTR_SLOTEN                   0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define  SAI_xIMR_OVRUDRIE                   0x00000001U        /*!<Overrun underrun interrupt enable                              */
+#define  SAI_xIMR_MUTEDETIE                  0x00000002U        /*!<Mute detection interrupt enable                                */
+#define  SAI_xIMR_WCKCFGIE                   0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */
+#define  SAI_xIMR_FREQIE                     0x00000008U        /*!<FIFO request interrupt enable                                  */
+#define  SAI_xIMR_CNRDYIE                    0x00000010U        /*!<Codec not ready interrupt enable                               */
+#define  SAI_xIMR_AFSDETIE                   0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */
+#define  SAI_xIMR_LFSDETIE                   0x00000040U        /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define  SAI_xSR_OVRUDR                      0x00000001U         /*!<Overrun underrun                               */
+#define  SAI_xSR_MUTEDET                     0x00000002U         /*!<Mute detection                                 */
+#define  SAI_xSR_WCKCFG                      0x00000004U         /*!<Wrong Clock Configuration                      */
+#define  SAI_xSR_FREQ                        0x00000008U         /*!<FIFO request                                   */
+#define  SAI_xSR_CNRDY                       0x00000010U         /*!<Codec not ready                                */
+#define  SAI_xSR_AFSDET                      0x00000020U         /*!<Anticipated frame synchronization detection    */
+#define  SAI_xSR_LFSDET                      0x00000040U         /*!<Late frame synchronization detection           */
+                                             
+#define  SAI_xSR_FLVL                        0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define  SAI_xSR_FLVL_0                      0x00010000U         /*!<Bit 0 */
+#define  SAI_xSR_FLVL_1                      0x00020000U         /*!<Bit 1 */
+#define  SAI_xSR_FLVL_2                      0x00040000U         /*!<Bit 2 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define  SAI_xCLRFR_COVRUDR                  0x00000001U        /*!<Clear Overrun underrun                               */
+#define  SAI_xCLRFR_CMUTEDET                 0x00000002U        /*!<Clear Mute detection                                 */
+#define  SAI_xCLRFR_CWCKCFG                  0x00000004U        /*!<Clear Wrong Clock Configuration                      */
+#define  SAI_xCLRFR_CFREQ                    0x00000008U        /*!<Clear FIFO request                                   */
+#define  SAI_xCLRFR_CCNRDY                   0x00000010U        /*!<Clear Codec not ready                                */
+#define  SAI_xCLRFR_CAFSDET                  0x00000020U        /*!<Clear Anticipated frame synchronization detection    */
+#define  SAI_xCLRFR_CLFSDET                  0x00000040U        /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  *********************/
+#define  SAI_xDR_DATA                        0xFFFFFFFFU        
+
+/******************************************************************************/
+/*                                                                            */
+/*                              SPDIF-RX Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SPDIF_CR register  *******************/
+#define  SPDIFRX_CR_SPDIFEN                0x00000003U        /*!<Peripheral Block Enable                      */
+#define  SPDIFRX_CR_RXDMAEN                0x00000004U        /*!<Receiver DMA Enable for data flow            */
+#define  SPDIFRX_CR_RXSTEO                 0x00000008U        /*!<Stereo Mode                                  */
+#define  SPDIFRX_CR_DRFMT                  0x00000030U        /*!<RX Data format                               */
+#define  SPDIFRX_CR_PMSK                   0x00000040U        /*!<Mask Parity error bit                        */
+#define  SPDIFRX_CR_VMSK                   0x00000080U        /*!<Mask of Validity bit                         */
+#define  SPDIFRX_CR_CUMSK                  0x00000100U        /*!<Mask of channel status and user bits         */
+#define  SPDIFRX_CR_PTMSK                  0x00000200U        /*!<Mask of Preamble Type bits                   */
+#define  SPDIFRX_CR_CBDMAEN                0x00000400U        /*!<Control Buffer DMA ENable for control flow   */
+#define  SPDIFRX_CR_CHSEL                  0x00000800U        /*!<Channel Selection                            */
+#define  SPDIFRX_CR_NBTR                   0x00003000U        /*!<Maximum allowed re-tries during synchronization phase */
+#define  SPDIFRX_CR_WFA                    0x00004000U        /*!<Wait For Activity     */
+#define  SPDIFRX_CR_INSEL                  0x00070000U        /*!<SPDIF input selection */
+
+/*******************  Bit definition for SPDIFRX_IMR register  *******************/
+#define  SPDIFRX_IMR_RXNEIE                0x00000001U        /*!<RXNE interrupt enable                              */
+#define  SPDIFRX_IMR_CSRNEIE               0x00000002U        /*!<Control Buffer Ready Interrupt Enable              */
+#define  SPDIFRX_IMR_PERRIE                0x00000004U        /*!<Parity error interrupt enable                      */
+#define  SPDIFRX_IMR_OVRIE                 0x00000008U        /*!<Overrun error Interrupt Enable                     */
+#define  SPDIFRX_IMR_SBLKIE                0x00000010U        /*!<Synchronization Block Detected Interrupt Enable    */
+#define  SPDIFRX_IMR_SYNCDIE               0x00000020U        /*!<Synchronization Done                               */
+#define  SPDIFRX_IMR_IFEIE                 0x00000040U        /*!<Serial Interface Error Interrupt Enable            */
+
+/*******************  Bit definition for SPDIFRX_SR register  *******************/
+#define  SPDIFRX_SR_RXNE                   0x00000001U       /*!<Read data register not empty                          */
+#define  SPDIFRX_SR_CSRNE                  0x00000002U       /*!<The Control Buffer register is not empty              */
+#define  SPDIFRX_SR_PERR                   0x00000004U       /*!<Parity error                                          */
+#define  SPDIFRX_SR_OVR                    0x00000008U       /*!<Overrun error                                         */
+#define  SPDIFRX_SR_SBD                    0x00000010U       /*!<Synchronization Block Detected                        */
+#define  SPDIFRX_SR_SYNCD                  0x00000020U       /*!<Synchronization Done                                  */
+#define  SPDIFRX_SR_FERR                   0x00000040U       /*!<Framing error                                         */
+#define  SPDIFRX_SR_SERR                   0x00000080U       /*!<Synchronization error                                 */
+#define  SPDIFRX_SR_TERR                   0x00000100U       /*!<Time-out error                                        */
+#define  SPDIFRX_SR_WIDTH5                 0x7FFF0000U       /*!<Duration of 5 symbols counted with spdif_clk          */
+
+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
+#define  SPDIFRX_IFCR_PERRCF               0x00000004U       /*!<Clears the Parity error flag                         */
+#define  SPDIFRX_IFCR_OVRCF                0x00000008U       /*!<Clears the Overrun error flag                        */
+#define  SPDIFRX_IFCR_SBDCF                0x00000010U       /*!<Clears the Synchronization Block Detected flag       */
+#define  SPDIFRX_IFCR_SYNCDCF              0x00000020U       /*!<Clears the Synchronization Done flag                 */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
+#define  SPDIFRX_DR0_DR                    0x00FFFFFFU        /*!<Data value            */
+#define  SPDIFRX_DR0_PE                    0x01000000U        /*!<Parity Error bit      */
+#define  SPDIFRX_DR0_V                     0x02000000U        /*!<Validity bit          */
+#define  SPDIFRX_DR0_U                     0x04000000U        /*!<User bit              */
+#define  SPDIFRX_DR0_C                     0x08000000U        /*!<Channel Status bit    */
+#define  SPDIFRX_DR0_PT                    0x30000000U        /*!<Preamble Type         */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
+#define  SPDIFRX_DR1_DR                    0xFFFFFF00U        /*!<Data value            */
+#define  SPDIFRX_DR1_PT                    0x00000030U        /*!<Preamble Type         */
+#define  SPDIFRX_DR1_C                     0x00000008U        /*!<Channel Status bit    */
+#define  SPDIFRX_DR1_U                     0x00000004U        /*!<User bit              */
+#define  SPDIFRX_DR1_V                     0x00000002U        /*!<Validity bit          */
+#define  SPDIFRX_DR1_PE                    0x00000001U        /*!<Parity Error bit      */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
+#define  SPDIFRX_DR1_DRNL1                 0xFFFF0000U        /*!<Data value Channel B      */
+#define  SPDIFRX_DR1_DRNL2                 0x0000FFFFU        /*!<Data value Channel A      */
+
+/*******************  Bit definition for SPDIFRX_CSR register   *******************/
+#define  SPDIFRX_CSR_USR                   0x0000FFFFU        /*!<User data information           */
+#define  SPDIFRX_CSR_CS                    0x00FF0000U        /*!<Channel A status information    */
+#define  SPDIFRX_CSR_SOB                   0x01000000U        /*!<Start Of Block                  */
+
+/*******************  Bit definition for SPDIFRX_DIR register    *******************/
+#define  SPDIFRX_DIR_THI                   0x000013FFU        /*!<Threshold LOW      */
+#define  SPDIFRX_DIR_TLO                   0x1FFF0000U        /*!<Threshold HIGH     */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define  SDMMC_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDMMC_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */
+#define  SDMMC_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define  SDMMC_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */
+#define  SDMMC_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */
+#define  SDMMC_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */
+#define  SDMMC_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */
+         
+#define  SDMMC_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDMMC_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */
+#define  SDMMC_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */
+         
+#define  SDMMC_CLKCR_NEGEDGE                  0x2000U            /*!<SDMMC_CK dephasing selection bit */
+#define  SDMMC_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define  SDMMC_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define  SDMMC_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */
+         
+#define  SDMMC_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDMMC_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */
+#define  SDMMC_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */
+         
+#define  SDMMC_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDMMC_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDMMC_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDMMC_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define  SDMMC_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP0 register  ******************/
+#define  SDMMC_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define  SDMMC_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define  SDMMC_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define  SDMMC_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define  SDMMC_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define  SDMMC_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define  SDMMC_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define  SDMMC_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */
+#define  SDMMC_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */
+#define  SDMMC_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */
+#define  SDMMC_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */
+
+#define  SDMMC_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDMMC_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */
+#define  SDMMC_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */
+#define  SDMMC_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */
+#define  SDMMC_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */
+
+#define  SDMMC_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */
+#define  SDMMC_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */
+#define  SDMMC_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */
+#define  SDMMC_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define  SDMMC_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA registe  ********************/
+#define  SDMMC_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */
+#define  SDMMC_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */
+#define  SDMMC_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */
+#define  SDMMC_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */
+#define  SDMMC_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */
+#define  SDMMC_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */
+#define  SDMMC_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */
+#define  SDMMC_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */
+#define  SDMMC_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDMMC_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */
+#define  SDMMC_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */
+#define  SDMMC_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */
+#define  SDMMC_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */
+#define  SDMMC_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDMMC_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDMMC_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */
+#define  SDMMC_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */
+#define  SDMMC_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */
+#define  SDMMC_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */
+#define  SDMMC_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */
+#define  SDMMC_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */
+#define  SDMMC_STA_SDIOIT                     0x00400000U        /*!<SDMMC interrupt received                       */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define  SDMMC_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */
+#define  SDMMC_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */
+#define  SDMMC_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */
+#define  SDMMC_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */
+#define  SDMMC_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */
+#define  SDMMC_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */
+#define  SDMMC_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */
+#define  SDMMC_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */
+#define  SDMMC_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */
+#define  SDMMC_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */
+#define  SDMMC_ICR_SDIOITC                    0x00400000U        /*!<SDMMCIT flag clear bit   */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define  SDMMC_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDMMC_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDMMC_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */
+#define  SDMMC_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */
+#define  SDMMC_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDMMC_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDMMC_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */
+#define  SDMMC_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */
+#define  SDMMC_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */
+#define  SDMMC_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */
+#define  SDMMC_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */
+#define  SDMMC_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDMMC_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */
+#define  SDMMC_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDMMC_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDMMC_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDMMC_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDMMC_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDMMC_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDMMC_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDMMC_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDMMC_MASK_SDIOITIE                  0x00400000U        /*!<SDMMC Mode Interrupt Received interrupt Enable */
+
+/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
+#define  SDMMC_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define  SDMMC_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        0x00000001U        /*!< Clock Phase                        */
+#define  SPI_CR1_CPOL                        0x00000002U        /*!< Clock Polarity                     */
+#define  SPI_CR1_MSTR                        0x00000004U        /*!< Master Selection                   */
+#define  SPI_CR1_BR                          0x00000038U        /*!< BR[2:0] bits (Baud Rate Control)   */
+#define  SPI_CR1_BR_0                        0x00000008U        /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        0x00000010U        /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        0x00000020U        /*!< Bit 2 */
+#define  SPI_CR1_SPE                         0x00000040U        /*!< SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    0x00000080U        /*!< Frame Format                        */
+#define  SPI_CR1_SSI                         0x00000100U        /*!< Internal slave select               */
+#define  SPI_CR1_SSM                         0x00000200U        /*!< Software slave management           */
+#define  SPI_CR1_RXONLY                      0x00000400U        /*!< Receive only                        */
+#define  SPI_CR1_CRCL                        0x00000800U        /*!< CRC Length                          */
+#define  SPI_CR1_CRCNEXT                     0x00001000U        /*!< Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       0x00002000U        /*!< Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      0x00004000U        /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    0x00008000U        /*!< Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     0x00000001U        /*!< Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     0x00000002U        /*!< Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        0x00000004U        /*!< SS Output Enable                     */
+#define  SPI_CR2_NSSP                        0x00000008U        /*!< NSS pulse management Enable          */
+#define  SPI_CR2_FRF                         0x00000010U        /*!< Frame Format Enable                  */
+#define  SPI_CR2_ERRIE                       0x00000020U        /*!< Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      0x00000040U        /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       0x00000080U        /*!< Tx buffer Empty Interrupt Enable     */
+#define  SPI_CR2_DS                          0x00000F00U        /*!< DS[3:0] Data Size                    */
+#define  SPI_CR2_DS_0                        0x00000100U        /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        0x00000200U        /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        0x00000400U        /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        0x00000800U        /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       0x00001000U        /*!< FIFO reception Threshold           */
+#define  SPI_CR2_LDMARX                      0x00002000U        /*!< Last DMA transfer for reception    */
+#define  SPI_CR2_LDMATX                      0x00004000U        /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         0x00000001U        /*!< Receive buffer Not Empty  */
+#define  SPI_SR_TXE                          0x00000002U        /*!< Transmit buffer Empty     */
+#define  SPI_SR_CHSIDE                       0x00000004U        /*!< Channel side              */
+#define  SPI_SR_UDR                          0x00000008U        /*!< Underrun flag             */
+#define  SPI_SR_CRCERR                       0x00000010U        /*!< CRC Error flag            */
+#define  SPI_SR_MODF                         0x00000020U        /*!< Mode fault                */
+#define  SPI_SR_OVR                          0x00000040U        /*!< Overrun flag              */
+#define  SPI_SR_BSY                          0x00000080U        /*!< Busy flag                 */
+#define  SPI_SR_FRE                          0x00000100U        /*!< TI frame format error     */
+#define  SPI_SR_FRLVL                        0x00000600U        /*!< FIFO Reception Level      */
+#define  SPI_SR_FRLVL_0                      0x00000200U        /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      0x00000400U        /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        0x00001800U        /*!< FIFO Transmission Level   */
+#define  SPI_SR_FTLVL_0                      0x00000800U        /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      0x00001000U        /*!< Bit 1 */  
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           0xFFFFU            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   0xFFFFU            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    0xFFFFU            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    0xFFFFU            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   0x00000001U        /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_DATLEN                  0x00000006U        /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                0x00000002U        /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                0x00000004U        /*!<Bit 1 */
+#define  SPI_I2SCFGR_CKPOL                   0x00000008U        /*!<steady state clock polarity                       */
+#define  SPI_I2SCFGR_I2SSTD                  0x00000030U        /*!<I2SSTD[1:0] bits (I2S standard selection)         */
+#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U        /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U        /*!<Bit 1 */
+#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U        /*!<PCM frame synchronization                         */
+#define  SPI_I2SCFGR_I2SCFG                  0x00000300U        /*!<I2SCFG[1:0] bits (I2S configuration mode)         */
+#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U        /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U        /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SE                    0x00000400U        /*!<I2S Enable                                        */
+#define  SPI_I2SCFGR_I2SMOD                  0x00000800U        /*!<I2S mode selection                                */
+#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U        /*!<Asynchronous start enable                        */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    0x00FFU            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       0x0100U            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     0x0200U            /*!<Master Clock Output Enable   */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
+#define SYSCFG_MEMRMP_MEM_BOOT         0x00000001U /*!< Boot information after Reset */
+
+
+#define SYSCFG_MEMRMP_SWP_FMC          0x00000C00U /*!< FMC Memory Mapping swapping */
+#define SYSCFG_MEMRMP_SWP_FMC_0        0x00000400U 
+#define SYSCFG_MEMRMP_SWP_FMC_1        0x00000800U 
+
+/******************  Bit definition for SYSCFG_PMC register  ******************/
+
+#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */
+
+#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */
+/** 
+  * @brief   EXTI0 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */
+
+/** 
+  * @brief   EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */
+
+/** 
+  * @brief   EXTI2 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */
+
+/** 
+  * @brief   EXTI3 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */
+/** 
+  * @brief   EXTI4 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */
+
+/** 
+  * @brief   EXTI5 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */
+
+/** 
+  * @brief   EXTI6 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */
+
+/** 
+  * @brief   EXTI7 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */
+           
+/** 
+  * @brief   EXTI8 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */
+
+/** 
+  * @brief   EXTI9 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */
+
+/** 
+  * @brief   EXTI10 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */
+
+/** 
+  * @brief   EXTI11 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */
+
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */
+/** 
+  * @brief   EXTI12 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */
+
+/** 
+  * @brief   EXTI13 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        0x0080U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        0x0090U /*!<PJ[13] pin */
+
+/** 
+  * @brief   EXTI14 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */
+
+/** 
+  * @brief   EXTI15 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */
+
+
+/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
+#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell power-down */
+#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell ready flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */
+#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */
+#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */
+
+#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */
+
+#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_CR1_UIFREMAP                    0x0800U            /*!<UIF status bit */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        0x00000001U            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        0x00000004U            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        0x00000008U            /*!<Capture/Compare DMA Selection            */
+
+#define  TIM_CR2_OIS5                        0x00010000U            /*!<Output Idle state 4 (OC4 output) */
+#define  TIM_CR2_OIS6                        0x00040000U            /*!<Output Idle state 4 (OC4 output) */
+
+#define  TIM_CR2_MMS                         0x0070U           /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       0x0010U           /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       0x0020U           /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       0x0040U           /*!<Bit 2 */
+
+#define  TIM_CR2_MMS2                        0x00F00000U            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS2_0                      0x00100000U            /*!<Bit 0 */
+#define  TIM_CR2_MMS2_1                      0x00200000U            /*!<Bit 1 */
+#define  TIM_CR2_MMS2_2                      0x00400000U            /*!<Bit 2 */
+#define  TIM_CR2_MMS2_3                      0x00800000U            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        0x00010007U            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      0x00000001U            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      0x00000002U            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      0x00000004U            /*!<Bit 2 */
+#define  TIM_SMCR_SMS_3                      0x00010000U            /*!<Bit 3 */
+#define  TIM_SMCR_OCCS                       0x00000008U            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */
+
+#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */
+#define  TIM_SR_B2IF                         0x0100U            /*!<Break2 interrupt Flag               */
+#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          0x00000001U               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        0x00000002U               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        0x00000004U               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        0x00000008U               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        0x00000010U               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        0x00000020U               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          0x00000040U               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          0x00000080U               /*!<Break Generation                          */
+#define  TIM_EGR_B2G                         0x00000100U              /*!<Break2 Generation                          */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      0x00000003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    0x00000001U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    0x00000002U            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     0x00000004U            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     0x00000008U            /*!<Output Compare 1 Preload enable              */
+
+#define  TIM_CCMR1_OC1M                      0x00010070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    0x00000010U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    0x00000020U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    0x00000040U            /*!<Bit 2 */
+#define  TIM_CCMR1_OC1M_3                    0x00010000U            /*!<Bit 3 */
+
+#define  TIM_CCMR1_OC1CE                     0x00000080U            /*!<Output Compare 1Clear Enable                 */
+
+#define  TIM_CCMR1_CC2S                      0x00000300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    0x00000100U            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    0x00000200U            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     0x00000400U            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     0x00000800U            /*!<Output Compare 2 Preload enable              */
+
+#define  TIM_CCMR1_OC2M                      0x01007000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    0x00001000U            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    0x00002000U            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    0x00004000U            /*!<Bit 2 */
+#define  TIM_CCMR1_OC2M_3                    0x01000000U            /*!<Bit 3 */
+
+#define  TIM_CCMR1_OC2CE                     0x00008000U            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      0x00000003U        /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    0x00000001U        /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    0x00000002U        /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     0x00000004U        /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     0x00000008U        /*!<Output Compare 3 Preload enable        */
+
+#define  TIM_CCMR2_OC3M                      0x00010070U        /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    0x00000010U        /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    0x00000020U        /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    0x00000040U        /*!<Bit 2 */
+#define  TIM_CCMR2_OC3M_3                    0x00010000U        /*!<Bit 3 */
+
+
+
+#define  TIM_CCMR2_OC3CE                     0x00000080U        /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      0x00000300U        /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    0x00000100U        /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    0x00000200U        /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     0x00000400U        /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     0x00000800U        /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      0x01007000U        /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    0x00001000U        /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    0x00002000U        /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    0x00004000U        /*!<Bit 2 */
+#define  TIM_CCMR2_OC4M_3                    0x01000000U        /*!<Bit 3 */
+
+#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       0x00000001U            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       0x00000002U            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      0x00000004U            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      0x00000008U            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       0x00000010U            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       0x00000020U            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      0x00000040U            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      0x00000080U            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       0x00000100U            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       0x00000200U            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      0x00000400U            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      0x00000800U            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       0x00001000U            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       0x00002000U            /*!<Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      0x00008000U            /*!<Capture/Compare 4 Complementary output Polarity */
+#define  TIM_CCER_CC5E                       0x00010000U            /*!<Capture/Compare 5 output enable */
+#define  TIM_CCER_CC5P                       0x00020000U            /*!<Capture/Compare 5 output Polarity */
+#define  TIM_CCER_CC6E                       0x00100000U            /*!<Capture/Compare 6 output enable */
+#define  TIM_CCER_CC6P                       0x00200000U            /*!<Capture/Compare 6 output Polarity */
+
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFFU)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        0x000000FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      0x00000001U            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      0x00000002U            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      0x00000004U            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      0x00000008U            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      0x00000010U            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      0x00000020U            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      0x00000040U            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      0x00000080U            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       0x00000300U            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     0x00000100U            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     0x00000200U            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       0x00000400U            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       0x00000800U            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        0x00001000U            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        0x00002000U            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        0x00004000U            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        0x00008000U            /*!<Main Output enable                */
+#define  TIM_BDTR_BKF                        0x000F0000U            /*!<Break Filter for Break1 */
+#define  TIM_BDTR_BK2F                       0x00F00000U            /*!<Break Filter for Break2 */
+#define  TIM_BDTR_BK2E                       0x01000000U            /*!<Break enable for Break2 */
+#define  TIM_BDTR_BK2P                       0x02000000U            /*!<Break Polarity for Break2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */
+
+/*******************  Bit definition for TIM_OR regiter  *********************/
+#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define  TIM_CCMR3_OC5FE                     0x00000004U            /*!<Output Compare 5 Fast enable */
+#define  TIM_CCMR3_OC5PE                     0x00000008U            /*!<Output Compare 5 Preload enable */
+
+#define  TIM_CCMR3_OC5M                      0x00010070U            /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define  TIM_CCMR3_OC5M_0                    0x00000010U            /*!<Bit 0 */
+#define  TIM_CCMR3_OC5M_1                    0x00000020U            /*!<Bit 1 */
+#define  TIM_CCMR3_OC5M_2                    0x00000040U            /*!<Bit 2 */
+#define  TIM_CCMR3_OC5M_3                    0x00010000U            /*!<Bit 3 */
+
+#define  TIM_CCMR3_OC5CE                     0x00000080U            /*!<Output Compare 5 Clear Enable */
+
+#define  TIM_CCMR3_OC6FE                     0x00000400U            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR3_OC6PE                     0x00000800U            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR3_OC6M                      0x01007000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR3_OC6M_0                    0x00001000U            /*!<Bit 0 */
+#define  TIM_CCMR3_OC6M_1                    0x00002000U            /*!<Bit 1 */
+#define  TIM_CCMR3_OC6M_2                    0x00004000U            /*!<Bit 2 */
+#define  TIM_CCMR3_OC6M_3                    0x01000000U            /*!<Bit 3 */
+
+#define  TIM_CCMR3_OC6CE                     0x00008000U            /*!<Output Compare 4 Clear Enable */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define  TIM_CCR5_CCR5                       0xFFFFFFFFU        /*!<Capture/Compare 5 Value */
+#define  TIM_CCR5_GC5C1                      0x20000000U        /*!<Group Channel 5 and Channel 1 */
+#define  TIM_CCR5_GC5C2                      0x40000000U        /*!<Group Channel 5 and Channel 2 */
+#define  TIM_CCR5_GC5C3                      0x80000000U        /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define  TIM_CCR6_CCR6                       ((uint16_t)0xFFFFU)            /*!<Capture/Compare 6 Value */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTIM)                            */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define  LPTIM_ISR_CMPM                         0x00000001U            /*!< Compare match                       */
+#define  LPTIM_ISR_ARRM                         0x00000002U            /*!< Autoreload match                    */
+#define  LPTIM_ISR_EXTTRIG                      0x00000004U            /*!< External trigger edge event         */
+#define  LPTIM_ISR_CMPOK                        0x00000008U            /*!< Compare register update OK          */
+#define  LPTIM_ISR_ARROK                        0x00000010U            /*!< Autoreload register update OK       */
+#define  LPTIM_ISR_UP                           0x00000020U            /*!< Counter direction change down to up */
+#define  LPTIM_ISR_DOWN                         0x00000040U            /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define  LPTIM_ICR_CMPMCF                       0x00000001U            /*!< Compare match Clear Flag                       */
+#define  LPTIM_ICR_ARRMCF                       0x00000002U            /*!< Autoreload match Clear Flag                    */
+#define  LPTIM_ICR_EXTTRIGCF                    0x00000004U            /*!< External trigger edge event Clear Flag         */
+#define  LPTIM_ICR_CMPOKCF                      0x00000008U            /*!< Compare register update OK Clear Flag          */
+#define  LPTIM_ICR_ARROKCF                      0x00000010U            /*!< Autoreload register update OK Clear Flag       */
+#define  LPTIM_ICR_UPCF                         0x00000020U            /*!< Counter direction change down to up Clear Flag */
+#define  LPTIM_ICR_DOWNCF                       0x00000040U            /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register *******************/
+#define  LPTIM_IER_CMPMIE                       0x00000001U            /*!< Compare match Interrupt Enable                       */
+#define  LPTIM_IER_ARRMIE                       0x00000002U            /*!< Autoreload match Interrupt Enable                    */
+#define  LPTIM_IER_EXTTRIGIE                    0x00000004U            /*!< External trigger edge event Interrupt Enable         */
+#define  LPTIM_IER_CMPOKIE                      0x00000008U            /*!< Compare register update OK Interrupt Enable          */
+#define  LPTIM_IER_ARROKIE                      0x00000010U            /*!< Autoreload register update OK Interrupt Enable       */
+#define  LPTIM_IER_UPIE                         0x00000020U            /*!< Counter direction change down to up Interrupt Enable */
+#define  LPTIM_IER_DOWNIE                       0x00000040U            /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register*******************/
+#define  LPTIM_CFGR_CKSEL                       0x00000001U             /*!< Clock selector */
+
+#define  LPTIM_CFGR_CKPOL                       0x00000006U             /*!< CKPOL[1:0] bits (Clock polarity) */
+#define  LPTIM_CFGR_CKPOL_0                     0x00000002U             /*!< Bit 0 */
+#define  LPTIM_CFGR_CKPOL_1                     0x00000004U             /*!< Bit 1 */
+
+#define  LPTIM_CFGR_CKFLT                       0x00000018U             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define  LPTIM_CFGR_CKFLT_0                     0x00000008U             /*!< Bit 0 */
+#define  LPTIM_CFGR_CKFLT_1                     0x00000010U             /*!< Bit 1 */
+
+#define  LPTIM_CFGR_TRGFLT                      0x000000C0U             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define  LPTIM_CFGR_TRGFLT_0                    0x00000040U             /*!< Bit 0 */
+#define  LPTIM_CFGR_TRGFLT_1                    0x00000080U             /*!< Bit 1 */
+
+#define  LPTIM_CFGR_PRESC                       0x00000E00U             /*!< PRESC[2:0] bits (Clock prescaler) */
+#define  LPTIM_CFGR_PRESC_0                     0x00000200U             /*!< Bit 0 */
+#define  LPTIM_CFGR_PRESC_1                     0x00000400U             /*!< Bit 1 */
+#define  LPTIM_CFGR_PRESC_2                     0x00000800U             /*!< Bit 2 */
+
+#define  LPTIM_CFGR_TRIGSEL                     0x0000E000U             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define  LPTIM_CFGR_TRIGSEL_0                   0x00002000U             /*!< Bit 0 */
+#define  LPTIM_CFGR_TRIGSEL_1                   0x00004000U             /*!< Bit 1 */
+#define  LPTIM_CFGR_TRIGSEL_2                   0x00008000U             /*!< Bit 2 */
+
+#define  LPTIM_CFGR_TRIGEN                      0x00060000U             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define  LPTIM_CFGR_TRIGEN_0                    0x00020000U             /*!< Bit 0 */
+#define  LPTIM_CFGR_TRIGEN_1                    0x00040000U             /*!< Bit 1 */
+
+#define  LPTIM_CFGR_TIMOUT                      0x00080000U             /*!< Timout enable           */
+#define  LPTIM_CFGR_WAVE                        0x00100000U             /*!< Waveform shape          */
+#define  LPTIM_CFGR_WAVPOL                      0x00200000U             /*!< Waveform shape polarity */
+#define  LPTIM_CFGR_PRELOAD                     0x00400000U             /*!< Reg update mode         */
+#define  LPTIM_CFGR_COUNTMODE                   0x00800000U             /*!< Counter mode enable     */     
+#define  LPTIM_CFGR_ENC                         0x01000000U             /*!< Encoder mode enable     */          
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define  LPTIM_CR_ENABLE                        0x00000001U             /*!< LPTIMer enable                 */
+#define  LPTIM_CR_SNGSTRT                       0x00000002U             /*!< Timer start in single mode     */
+#define  LPTIM_CR_CNTSTRT                       0x00000004U             /*!< Timer start in continuous mode */
+
+/******************  Bit definition for LPTIM_CMP register *******************/
+#define  LPTIM_CMP_CMP                          0x0000FFFFU             /*!< Compare register     */
+
+/******************  Bit definition for LPTIM_ARR register *******************/
+#define  LPTIM_ARR_ARR                          0x0000FFFFU             /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register *******************/
+#define  LPTIM_CNT_CNT                          0x0000FFFFU             /*!< Counter register     */
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        0x00000001U            /*!< USART Enable                                    */
+#define  USART_CR1_RE                        0x00000004U            /*!< Receiver Enable                                 */
+#define  USART_CR1_TE                        0x00000008U            /*!< Transmitter Enable                              */
+#define  USART_CR1_IDLEIE                    0x00000010U            /*!< IDLE Interrupt Enable                           */
+#define  USART_CR1_RXNEIE                    0x00000020U            /*!< RXNE Interrupt Enable                           */
+#define  USART_CR1_TCIE                      0x00000040U            /*!< Transmission Complete Interrupt Enable          */
+#define  USART_CR1_TXEIE                     0x00000080U            /*!< TXE Interrupt Enable                            */
+#define  USART_CR1_PEIE                      0x00000100U            /*!< PE Interrupt Enable                             */
+#define  USART_CR1_PS                        0x00000200U            /*!< Parity Selection                                */
+#define  USART_CR1_PCE                       0x00000400U            /*!< Parity Control Enable                           */
+#define  USART_CR1_WAKE                      0x00000800U            /*!< Receiver Wakeup method                          */
+#define  USART_CR1_M                         0x10001000U            /*!< Word length                                     */
+#define  USART_CR1_M_0                       0x00001000U            /*!< Word length - Bit 0                             */
+#define  USART_CR1_MME                       0x00002000U            /*!< Mute Mode Enable                                */
+#define  USART_CR1_CMIE                      0x00004000U            /*!< Character match interrupt enable                */
+#define  USART_CR1_OVER8                     0x00008000U            /*!< Oversampling by 8-bit or 16-bit mode            */
+#define  USART_CR1_DEDT                      0x001F0000U            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    0x00010000U            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    0x00020000U            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    0x00040000U            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    0x00080000U            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    0x00100000U            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      0x03E00000U            /*!< DEAT[4:0] bits (Driver Enable Assertion Time)   */
+#define  USART_CR1_DEAT_0                    0x00200000U            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    0x00400000U            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    0x00800000U            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    0x01000000U            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    0x02000000U            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     0x04000000U            /*!< Receive Time Out interrupt enable */
+#define  USART_CR1_EOBIE                     0x08000000U            /*!< End of Block interrupt enable     */
+#define  USART_CR1_M_1                       0x10000000U            /*!< Word length - Bit 1               */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     0x00000010U            /*!< 7-bit or 4-bit Address Detection       */
+#define  USART_CR2_LBDL                      0x00000020U            /*!< LIN Break Detection Length             */
+#define  USART_CR2_LBDIE                     0x00000040U            /*!< LIN Break Detection Interrupt Enable   */
+#define  USART_CR2_LBCL                      0x00000100U            /*!< Last Bit Clock pulse                   */
+#define  USART_CR2_CPHA                      0x00000200U            /*!< Clock Phase                            */
+#define  USART_CR2_CPOL                      0x00000400U            /*!< Clock Polarity                         */
+#define  USART_CR2_CLKEN                     0x00000800U            /*!< Clock Enable                           */
+#define  USART_CR2_STOP                      0x00003000U            /*!< STOP[1:0] bits (STOP bits)             */
+#define  USART_CR2_STOP_0                    0x00001000U            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    0x00002000U            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     0x00004000U            /*!< LIN mode enable                        */
+#define  USART_CR2_SWAP                      0x00008000U            /*!< SWAP TX/RX pins                        */
+#define  USART_CR2_RXINV                     0x00010000U            /*!< RX pin active level inversion          */
+#define  USART_CR2_TXINV                     0x00020000U            /*!< TX pin active level inversion          */
+#define  USART_CR2_DATAINV                   0x00040000U            /*!< Binary data inversion                  */
+#define  USART_CR2_MSBFIRST                  0x00080000U            /*!< Most Significant Bit First             */
+#define  USART_CR2_ABREN                     0x00100000U            /*!< Auto Baud-Rate Enable                  */
+#define  USART_CR2_ABRMODE                   0x00600000U            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMODE_0                 0x00200000U            /*!< Bit 0 */
+#define  USART_CR2_ABRMODE_1                 0x00400000U            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     0x00800000U            /*!< Receiver Time-Out enable  */
+#define  USART_CR2_ADD                       0xFF000000U            /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       0x00000001U            /*!< Error Interrupt Enable                         */
+#define  USART_CR3_IREN                      0x00000002U            /*!< IrDA mode Enable                               */
+#define  USART_CR3_IRLP                      0x00000004U            /*!< IrDA Low-Power                                 */
+#define  USART_CR3_HDSEL                     0x00000008U            /*!< Half-Duplex Selection                          */
+#define  USART_CR3_NACK                      0x00000010U            /*!< SmartCard NACK enable                          */
+#define  USART_CR3_SCEN                      0x00000020U            /*!< SmartCard mode enable                          */
+#define  USART_CR3_DMAR                      0x00000040U            /*!< DMA Enable Receiver                            */
+#define  USART_CR3_DMAT                      0x00000080U            /*!< DMA Enable Transmitter                         */
+#define  USART_CR3_RTSE                      0x00000100U            /*!< RTS Enable                                     */
+#define  USART_CR3_CTSE                      0x00000200U            /*!< CTS Enable                                     */
+#define  USART_CR3_CTSIE                     0x00000400U            /*!< CTS Interrupt Enable                           */
+#define  USART_CR3_ONEBIT                    0x00000800U            /*!< One sample bit method enable                   */
+#define  USART_CR3_OVRDIS                    0x00001000U            /*!< Overrun Disable                                */
+#define  USART_CR3_DDRE                      0x00002000U            /*!< DMA Disable on Reception Error                 */
+#define  USART_CR3_DEM                       0x00004000U            /*!< Driver Enable Mode                             */
+#define  USART_CR3_DEP                       0x00008000U            /*!< Driver Enable Polarity Selection               */
+#define  USART_CR3_SCARCNT                   0x000E0000U            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define  USART_CR3_SCARCNT_0                 0x00020000U            /*!< Bit 0 */
+#define  USART_CR3_SCARCNT_1                 0x00040000U            /*!< Bit 1 */
+#define  USART_CR3_SCARCNT_2                 0x00080000U            /*!< Bit 2 */
+
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_FRACTION              0x000FU                /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_MANTISSA              0xFFF0U                /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      0x00FFU                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       0xFF00U                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      0x00FFFFFFU            /*!< Receiver Time Out Value */
+#define  USART_RTOR_BLEN                     0xFF000000U            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                     0x0001U                /*!< Auto-Baud Rate Request      */
+#define  USART_RQR_SBKRQ                     0x0002U                /*!< Send Break Request          */
+#define  USART_RQR_MMRQ                      0x0004U                /*!< Mute Mode Request           */
+#define  USART_RQR_RXFRQ                     0x0008U                /*!< Receive Data flush Request  */
+#define  USART_RQR_TXFRQ                     0x0010U                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        0x00000001U            /*!< Parity Error                        */
+#define  USART_ISR_FE                        0x00000002U            /*!< Framing Error                       */
+#define  USART_ISR_NE                        0x00000004U            /*!< Noise detected Flag                 */
+#define  USART_ISR_ORE                       0x00000008U            /*!< OverRun Error                       */
+#define  USART_ISR_IDLE                      0x00000010U            /*!< IDLE line detected                  */
+#define  USART_ISR_RXNE                      0x00000020U            /*!< Read Data Register Not Empty        */
+#define  USART_ISR_TC                        0x00000040U            /*!< Transmission Complete               */
+#define  USART_ISR_TXE                       0x00000080U            /*!< Transmit Data Register Empty        */
+#define  USART_ISR_LBDF                      0x00000100U            /*!< LIN Break Detection Flag            */
+#define  USART_ISR_CTSIF                     0x00000200U            /*!< CTS interrupt flag                  */
+#define  USART_ISR_CTS                       0x00000400U            /*!< CTS flag                            */
+#define  USART_ISR_RTOF                      0x00000800U            /*!< Receiver Time Out                   */
+#define  USART_ISR_EOBF                      0x00001000U            /*!< End Of Block Flag                   */
+#define  USART_ISR_ABRE                      0x00004000U            /*!< Auto-Baud Rate Error                */
+#define  USART_ISR_ABRF                      0x00008000U            /*!< Auto-Baud Rate Flag                 */
+#define  USART_ISR_BUSY                      0x00010000U            /*!< Busy Flag                           */
+#define  USART_ISR_CMF                       0x00020000U            /*!< Character Match Flag                */
+#define  USART_ISR_SBKF                      0x00040000U            /*!< Send Break Flag                     */
+#define  USART_ISR_RWU                       0x00080000U            /*!< Receive Wake Up from mute mode Flag */
+#define  USART_ISR_WUF                       0x00100000U            /*!< Wake Up from stop mode Flag         */
+#define  USART_ISR_TEACK                     0x00200000U            /*!< Transmit Enable Acknowledge Flag    */
+#define  USART_ISR_REACK                     0x00400000U            /*!< Receive Enable Acknowledge Flag     */
+
+/* Legacy define */
+#define  USART_ISR_LBD                       USART_ISR_LBDF
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      0x00000001U            /*!< Parity Error Clear Flag             */
+#define  USART_ICR_FECF                      0x00000002U            /*!< Framing Error Clear Flag            */
+#define  USART_ICR_NCF                       0x00000004U            /*!< Noise detected Clear Flag           */
+#define  USART_ICR_ORECF                     0x00000008U            /*!< OverRun Error Clear Flag            */
+#define  USART_ICR_IDLECF                    0x00000010U            /*!< IDLE line detected Clear Flag       */
+#define  USART_ICR_TCCF                      0x00000040U            /*!< Transmission Complete Clear Flag    */
+#define  USART_ICR_LBDCF                     0x00000100U            /*!< LIN Break Detection Clear Flag      */
+#define  USART_ICR_CTSCF                     0x00000200U            /*!< CTS Interrupt Clear Flag            */
+#define  USART_ICR_RTOCF                     0x00000800U            /*!< Receiver Time Out Clear Flag        */
+#define  USART_ICR_EOBCF                     0x00001000U            /*!< End Of Block Clear Flag             */
+#define  USART_ICR_CMCF                      0x00020000U            /*!< Character Match Clear Flag          */
+#define  USART_ICR_WUCF                      0x00100000U            /*!< Wake Up from stop mode Clear Flag   */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       0x01FFU                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       0x01FFU                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                            0x7FU                 /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T_0                          0x01U                 /*!<Bit 0 */
+#define  WWDG_CR_T_1                          0x02U                 /*!<Bit 1 */
+#define  WWDG_CR_T_2                          0x04U                 /*!<Bit 2 */
+#define  WWDG_CR_T_3                          0x08U                 /*!<Bit 3 */
+#define  WWDG_CR_T_4                          0x10U                 /*!<Bit 4 */
+#define  WWDG_CR_T_5                          0x20U                 /*!<Bit 5 */
+#define  WWDG_CR_T_6                          0x40U                 /*!<Bit 6 */
+
+/* Legacy defines */
+#define  WWDG_CR_T0                           WWDG_CR_T_0                      /*!<Bit 0 */
+#define  WWDG_CR_T1                           WWDG_CR_T_1                      /*!<Bit 1 */
+#define  WWDG_CR_T2                           WWDG_CR_T_2                      /*!<Bit 2 */
+#define  WWDG_CR_T3                           WWDG_CR_T_3                      /*!<Bit 3 */
+#define  WWDG_CR_T4                           WWDG_CR_T_4                      /*!<Bit 4 */
+#define  WWDG_CR_T5                           WWDG_CR_T_5                      /*!<Bit 5 */
+#define  WWDG_CR_T6                           WWDG_CR_T_6                      /*!<Bit 6 */
+
+#define  WWDG_CR_WDGA                        0x80U                  /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          0x007FU                /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W_0                        0x0001U                /*!<Bit 0 */
+#define  WWDG_CFR_W_1                        0x0002U                /*!<Bit 1 */
+#define  WWDG_CFR_W_2                        0x0004U                /*!<Bit 2 */
+#define  WWDG_CFR_W_3                        0x0008U                /*!<Bit 3 */
+#define  WWDG_CFR_W_4                        0x0010U                /*!<Bit 4 */
+#define  WWDG_CFR_W_5                        0x0020U                /*!<Bit 5 */
+#define  WWDG_CFR_W_6                        0x0040U                /*!<Bit 6 */
+
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0                      /*!<Bit 0 */
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1                      /*!<Bit 1 */
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2                      /*!<Bit 2 */
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3                      /*!<Bit 3 */
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4                      /*!<Bit 4 */
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5                      /*!<Bit 5 */
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6                      /*!<Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      0x0180U                /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB_0                    0x0080U                /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB_1                    0x0100U                /*!<Bit 1 */
+
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0                  /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1                  /*!<Bit 1 */
+
+#define  WWDG_CFR_EWI                        0x0200U               /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        0x01U                  /*!<Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU
+#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U
+#define  DBGMCU_CR_DBG_STOP                  0x00000002U
+#define  DBGMCU_CR_DBG_STANDBY               0x00000004U
+#define  DBGMCU_CR_TRACE_IOEN                0x00000020U
+
+#define  DBGMCU_CR_TRACE_MODE                0x000000C0U
+#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U /*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U /*!<Bit 1 */
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U
+
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP            0x00000001U
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP            0x00000002U
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP            0x00010000U
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP           0x00020000U
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP           0x00040000U
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD              0x00800000U  /* Watchdog disable */
+#define ETH_MACCR_JD              0x00400000U  /* Jabber disable */
+#define ETH_MACCR_IFG             0x000E0000U  /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit       0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */
+#define ETH_MACCR_IFG_88Bit       0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */
+#define ETH_MACCR_IFG_80Bit       0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */
+#define ETH_MACCR_IFG_72Bit       0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */
+#define ETH_MACCR_IFG_64Bit       0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        
+#define ETH_MACCR_IFG_56Bit       0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */
+#define ETH_MACCR_IFG_48Bit       0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */
+#define ETH_MACCR_IFG_40Bit       0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              
+#define ETH_MACCR_CSD             0x00010000U  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES             0x00004000U  /* Fast ethernet speed */
+#define ETH_MACCR_ROD             0x00002000U  /* Receive own disable */
+#define ETH_MACCR_LM              0x00001000U  /* loopback mode */
+#define ETH_MACCR_DM              0x00000800U  /* Duplex mode */
+#define ETH_MACCR_IPCO            0x00000400U  /* IP Checksum offload */
+#define ETH_MACCR_RD              0x00000200U  /* Retry disable */
+#define ETH_MACCR_APCS            0x00000080U  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL              0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define ETH_MACCR_BL_10           0x00000000U  /* k = min (n, 10) */
+#define ETH_MACCR_BL_8            0x00000020U  /* k = min (n, 8) */
+#define ETH_MACCR_BL_4            0x00000040U  /* k = min (n, 4) */
+#define ETH_MACCR_BL_1            0x00000060U  /* k = min (n, 1) */ 
+#define ETH_MACCR_DC              0x00000010U  /* Defferal check */
+#define ETH_MACCR_TE              0x00000008U  /* Transmitter enable */
+#define ETH_MACCR_RE              0x00000004U  /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA             0x80000000U  /* Receive all */ 
+#define ETH_MACFFR_HPF            0x00000400U  /* Hash or perfect filter */ 
+#define ETH_MACFFR_SAF            0x00000200U  /* Source address filter enable */ 
+#define ETH_MACFFR_SAIF           0x00000100U  /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF            0x000000C0U  /* Pass control frames: 3 cases */
+#define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */
+#define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD             0x00000020U  /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM             0x00000010U  /* Pass all mutlicast */ 
+#define ETH_MACFFR_DAIF            0x00000008U  /* DA Inverse filtering */ 
+#define ETH_MACFFR_HM              0x00000004U  /* Hash multicast */ 
+#define ETH_MACFFR_HU              0x00000002U  /* Hash unicast */
+#define ETH_MACFFR_PM              0x00000001U  /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH            0xFFFFFFFFU  /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL            0xFFFFFFFFU  /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA            0x0000F800U  /* Physical layer address */ 
+#define ETH_MACMIIAR_MR            0x000007C0U  /* MII register in the selected PHY */ 
+#define ETH_MACMIIAR_CR            0x0000001CU  /* CR clock range: 6 cases */ 
+#define ETH_MACMIIAR_CR_Div42      0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+#define ETH_MACMIIAR_CR_Div62      0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+#define ETH_MACMIIAR_CR_Div16      0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+#define ETH_MACMIIAR_CR_Div26      0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_CR_Div102     0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  
+#define ETH_MACMIIAR_MW            0x00000002U  /* MII write */ 
+#define ETH_MACMIIAR_MB            0x00000001U  /* MII busy */ 
+  
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD            0x0000FFFFU  /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT              0xFFFF0000U  /* Pause time */
+#define ETH_MACFCR_ZQPD            0x00000080U  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT             0x00000030U  /* Pause low threshold: 4 cases */
+#define ETH_MACFCR_PLT_Minus4      0x00000000U  /* Pause time minus 4 slot times */
+#define ETH_MACFCR_PLT_Minus28     0x00000010U  /* Pause time minus 28 slot times */
+#define ETH_MACFCR_PLT_Minus144    0x00000020U  /* Pause time minus 144 slot times */
+#define ETH_MACFCR_PLT_Minus256    0x00000030U  /* Pause time minus 256 slot times */      
+#define ETH_MACFCR_UPFD            0x00000008U  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE            0x00000004U  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE            0x00000002U  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA          0x00000001U  /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC       0x00010000U  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI       0x0000FFFFU  /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
+#define ETH_MACRWUFFR_D            0xFFFFFFFFU  /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
+#define ETH_MACPMTCSR_WFFRPR       0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU           0x00000200U  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR          0x00000040U  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR          0x00000020U  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE          0x00000004U  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE          0x00000002U  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD           0x00000001U  /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */
+#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */
+#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA1HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ 
+#define ETH_MACA1HR_MACA1H            0x0000FFFFU  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA2HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */
+#define ETH_MACA3HR_SA       0x40000000U  /* Source address */
+#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */
+  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */
+#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */
+#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU       0x00000020U  /* Addend register update */
+#define ETH_PTPTSCR_TSITE       0x00000010U  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU       0x00000008U  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI       0x00000004U  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU       0x00000002U  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE         0x00000001U  /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI      0x000000FFU   /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS        0xFFFFFFFFU   /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS      0x80000000U  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS       0x7FFFFFFFU  /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS      0xFFFFFFFFU  /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS    0x80000000U  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS     0x7FFFFFFFU  /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA        0xFFFFFFFFU  /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH       0xFFFFFFFFU  /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL       0xFFFFFFFFU  /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR      0x00000020U  /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO       0x00000010U  /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB        0x02000000U  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */
+#define ETH_DMABMR_USP        0x00800000U  /* Use separate PBL */
+#define ETH_DMABMR_RDP        0x007E0000U  /* RxDMA PBL */
+  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */
+  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        0x00000001U  /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */
+#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */
+#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */
+  /* combination with EBS[2:0] for GetFlagStatus function */
+  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */
+#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */
+#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */
+#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         0x00000040U  /* Receive status */
+#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */
+#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */
+#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */
+#define ETH_DMASR_TS         0x00000001U  /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */
+#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */
+#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */
+#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT                     0x0000FFFFU            /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */
+
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                       */
+#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
+
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
+
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */
+#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */
+
+#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */
+#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */
+
+#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP                0x00000FFFU            /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM            0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT                0x00000002U           /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT                0x00020000U           /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */
+
+/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_ADPMEN                 0x00000001U             /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF                  0x00800000U             /*!< ADP Interrupt flag */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */
+ 
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */
+#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */
+#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */
+#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */
+#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */
+#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */
+#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */
+#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */
+#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */
+#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */
+#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */
+#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */
+#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */
+#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */
+#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */
+#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */
+
+#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */
+#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */
+
+#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */
+#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */
+#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM               0x00000001U            /*!< Transfer completed interrupt mask         */
+#define USB_OTG_DOEPEACHMSK1_EPDM                0x00000002U            /*!< Endpoint disabled interrupt mask          */
+#define USB_OTG_DOEPEACHMSK1_TOM                 0x00000008U            /*!< Timeout condition mask                    */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           0x00000010U            /*!< IN token received when TxFIFO empty mask  */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             0x00000020U            /*!< IN token received with EP mismatch mask   */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             0x00000040U            /*!< IN endpoint NAK effective mask            */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              0x00000100U            /*!< OUT packet error mask                     */
+#define USB_OTG_DOEPEACHMSK1_BIM                 0x00000200U            /*!< BNA interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_BERRM               0x00001000U            /*!< Bubble error interrupt mask               */
+#define USB_OTG_DOEPEACHMSK1_NAKM                0x00002000U            /*!< NAK interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_NYETM               0x00004000U            /*!< NYET interrupt mask                       */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */
+#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */
+#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */
+#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */
+#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */
+
+#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */
+#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */
+
+#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */
+#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */
+#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */
+#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */
+#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */
+#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */
+
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
+                                       ((__INSTANCE__) == ADC2) || \
+                                       ((__INSTANCE__) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
+                                           ((__INSTANCE__) == CAN2))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
+
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
+                                              ((__INSTANCE__) == DMA1_Stream1) || \
+                                              ((__INSTANCE__) == DMA1_Stream2) || \
+                                              ((__INSTANCE__) == DMA1_Stream3) || \
+                                              ((__INSTANCE__) == DMA1_Stream4) || \
+                                              ((__INSTANCE__) == DMA1_Stream5) || \
+                                              ((__INSTANCE__) == DMA1_Stream6) || \
+                                              ((__INSTANCE__) == DMA1_Stream7) || \
+                                              ((__INSTANCE__) == DMA2_Stream0) || \
+                                              ((__INSTANCE__) == DMA2_Stream1) || \
+                                              ((__INSTANCE__) == DMA2_Stream2) || \
+                                              ((__INSTANCE__) == DMA2_Stream3) || \
+                                              ((__INSTANCE__) == DMA2_Stream4) || \
+                                              ((__INSTANCE__) == DMA2_Stream5) || \
+                                              ((__INSTANCE__) == DMA2_Stream6) || \
+                                              ((__INSTANCE__) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
+                                        ((__INSTANCE__) == GPIOB) || \
+                                        ((__INSTANCE__) == GPIOC) || \
+                                        ((__INSTANCE__) == GPIOD) || \
+                                        ((__INSTANCE__) == GPIOE) || \
+                                        ((__INSTANCE__) == GPIOF) || \
+                                        ((__INSTANCE__) == GPIOG) || \
+                                        ((__INSTANCE__) == GPIOH) || \
+                                        ((__INSTANCE__) == GPIOI) || \
+                                        ((__INSTANCE__) == GPIOJ) || \
+                                        ((__INSTANCE__) == GPIOK))
+										
+#define IS_GPIO_AF_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == GPIOA) || \
+                                        ((__INSTANCE__) == GPIOB) || \
+                                        ((__INSTANCE__) == GPIOC) || \
+                                        ((__INSTANCE__) == GPIOD) || \
+                                        ((__INSTANCE__) == GPIOE) || \
+                                        ((__INSTANCE__) == GPIOF) || \
+                                        ((__INSTANCE__) == GPIOG) || \
+                                        ((__INSTANCE__) == GPIOH) || \
+                                        ((__INSTANCE__) == GPIOI) || \
+                                        ((__INSTANCE__) == GPIOJ) || \
+                                        ((__INSTANCE__) == GPIOK))
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
+
+/****************************** QSPI Instances *********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+                                        
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
+                                       ((__INSTANCE__) == I2C2) || \
+                                       ((__INSTANCE__) == I2C3) || \
+                                       ((__INSTANCE__) == I2C4))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI1) || \
+                                    ((__INSTANCE__) == SPI2) || \
+                                    ((__INSTANCE__) == SPI3))
+
+/******************************* LPTIM Instances ********************************/
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == LTDC)
+
+
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
+                                         ((__PERIPH__) == SAI1_Block_B) || \
+                                         ((__PERIPH__) == SAI2_Block_A) || \
+                                         ((__PERIPH__) == SAI2_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SDMMC Instances *******************************/
+#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
+
+/****************************** SPDIFRX Instances *********************************/
+#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
+                                     
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
+                                       ((__INSTANCE__) == SPI2) || \
+                                       ((__INSTANCE__) == SPI3) || \
+                                       ((__INSTANCE__) == SPI4) || \
+                                       ((__INSTANCE__) == SPI5) || \
+                                       ((__INSTANCE__) == SPI6))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \
+                                   ((__INSTANCE__) == TIM2)   || \
+                                   ((__INSTANCE__) == TIM3)   || \
+                                   ((__INSTANCE__) == TIM4)   || \
+                                   ((__INSTANCE__) == TIM5)   || \
+                                   ((__INSTANCE__) == TIM6)   || \
+                                   ((__INSTANCE__) == TIM7)   || \
+                                   ((__INSTANCE__) == TIM8)   || \
+                                   ((__INSTANCE__) == TIM9)   || \
+                                   ((__INSTANCE__) == TIM10)  || \
+                                   ((__INSTANCE__) == TIM11)  || \
+                                   ((__INSTANCE__) == TIM12)  || \
+                                   ((__INSTANCE__) == TIM13)  || \
+                                   ((__INSTANCE__) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
+                                         ((__INSTANCE__) == TIM2)  || \
+                                         ((__INSTANCE__) == TIM3)  || \
+                                         ((__INSTANCE__) == TIM4)  || \
+                                         ((__INSTANCE__) == TIM5)  || \
+                                         ((__INSTANCE__) == TIM8)  || \
+                                         ((__INSTANCE__) == TIM9)  || \
+                                         ((__INSTANCE__) == TIM10) || \
+                                         ((__INSTANCE__) == TIM11) || \
+                                         ((__INSTANCE__) == TIM12) || \
+                                         ((__INSTANCE__) == TIM13) || \
+                                         ((__INSTANCE__) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
+                                         ((__INSTANCE__) == TIM2)  || \
+                                         ((__INSTANCE__) == TIM3)  || \
+                                         ((__INSTANCE__) == TIM4)  || \
+                                         ((__INSTANCE__) == TIM5)  || \
+                                         ((__INSTANCE__) == TIM8)  || \
+                                         ((__INSTANCE__) == TIM9)  || \
+                                         ((__INSTANCE__) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
+                                         ((__INSTANCE__) == TIM2) || \
+                                         ((__INSTANCE__) == TIM3) || \
+                                         ((__INSTANCE__) == TIM4) || \
+                                         ((__INSTANCE__) == TIM5) || \
+                                         ((__INSTANCE__) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                       ((__INSTANCE__) == TIM2) || \
+                                       ((__INSTANCE__) == TIM3) || \
+                                       ((__INSTANCE__) == TIM4) || \
+                                       ((__INSTANCE__) == TIM5) || \
+                                       ((__INSTANCE__) == TIM8))
+                                       
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
+                                       (((__INSTANCE__) == TIM1)    || \
+                                        ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
+                                  (((__INSTANCE__) == TIM1)    || \
+                                   ((__INSTANCE__) == TIM2)    || \
+                                   ((__INSTANCE__) == TIM3)    || \
+                                   ((__INSTANCE__) == TIM4)    || \
+                                   ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
+                                                 (((__INSTANCE__) == TIM1)    || \
+                                                  ((__INSTANCE__) == TIM2)    || \
+                                                  ((__INSTANCE__) == TIM3)    || \
+                                                  ((__INSTANCE__) == TIM4)    || \
+                                                  ((__INSTANCE__) == TIM5)    || \
+                                                  ((__INSTANCE__) == TIM8))
+ 
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
+                                                   (((__INSTANCE__) == TIM1)    || \
+                                                    ((__INSTANCE__) == TIM2)    || \
+                                                    ((__INSTANCE__) == TIM3)    || \
+                                                    ((__INSTANCE__) == TIM4)    || \
+                                                    ((__INSTANCE__) == TIM5)    || \
+                                                    ((__INSTANCE__) == TIM8))
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
+  (((__INSTANCE__) == TIM1)    || \
+   ((__INSTANCE__) == TIM8) )
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
+  (((__INSTANCE__) == TIM1)    || \
+   ((__INSTANCE__) == TIM8))
+
+                                       
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                            ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
+  (((__INSTANCE__) == TIM1)    || \
+   ((__INSTANCE__) == TIM8))
+   
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
+                                         ((__INSTANCE__) == TIM2) || \
+                                         ((__INSTANCE__) == TIM3) || \
+                                         ((__INSTANCE__) == TIM4) || \
+                                         ((__INSTANCE__) == TIM5) || \
+                                         ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                       ((__INSTANCE__) == TIM2) || \
+                                       ((__INSTANCE__) == TIM3) || \
+                                       ((__INSTANCE__) == TIM4) || \
+                                       ((__INSTANCE__) == TIM5) || \
+                                       ((__INSTANCE__) == TIM6) || \
+                                       ((__INSTANCE__) == TIM7) || \
+                                       ((__INSTANCE__) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                          ((__INSTANCE__) == TIM2) || \
+                                          ((__INSTANCE__) == TIM3) || \
+                                          ((__INSTANCE__) == TIM4) || \
+                                          ((__INSTANCE__) == TIM5) || \
+                                          ((__INSTANCE__) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
+                                          ((__INSTANCE__) == TIM2) || \
+                                          ((__INSTANCE__) == TIM3) || \
+                                          ((__INSTANCE__) == TIM4) || \
+                                          ((__INSTANCE__) == TIM5) || \
+                                          ((__INSTANCE__) == TIM8)) 
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
+                                             ((__INSTANCE__) == TIM2) || \
+                                             ((__INSTANCE__) == TIM3) || \
+                                             ((__INSTANCE__) == TIM4) || \
+                                             ((__INSTANCE__) == TIM5) || \
+                                             ((__INSTANCE__) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                          ((__INSTANCE__) == TIM2) || \
+                                          ((__INSTANCE__) == TIM3) || \
+                                          ((__INSTANCE__) == TIM4) || \
+                                          ((__INSTANCE__) == TIM5) || \
+                                          ((__INSTANCE__) == TIM6) || \
+                                          ((__INSTANCE__) == TIM7) || \
+                                          ((__INSTANCE__) == TIM8) || \
+                                          ((__INSTANCE__) == TIM13) || \
+                                          ((__INSTANCE__) == TIM14))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                         ((__INSTANCE__) == TIM2) || \
+                                         ((__INSTANCE__) == TIM3) || \
+                                         ((__INSTANCE__) == TIM4) || \
+                                         ((__INSTANCE__) == TIM5) || \
+                                         ((__INSTANCE__) == TIM8) || \
+                                         ((__INSTANCE__) == TIM9) || \
+                                         ((__INSTANCE__) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
+                                              ((__INSTANCE__) == TIM5))
+
+/***************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
+                                        ((__INSTANCE__) == TIM2) || \
+                                        ((__INSTANCE__) == TIM3) || \
+                                        ((__INSTANCE__) == TIM4) || \
+                                        ((__INSTANCE__) == TIM5) || \
+                                        ((__INSTANCE__) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2)  || \
+                                         ((__INSTANCE__) == TIM5)  || \
+                                         ((__INSTANCE__) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
+    ((((__INSTANCE__) == TIM1) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM2) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM3) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM4) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM5) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM8) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM9) &&                   \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM10) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM11) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM12) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
+      ((__CHANNEL__) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM13) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((__INSTANCE__) == TIM14) &&                  \
+     (((__CHANNEL__) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
+   ((((__INSTANCE__) == TIM1) &&                    \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
+      ((__CHANNEL__) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((__INSTANCE__) == TIM8) &&                    \
+     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
+      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
+      ((__CHANNEL__) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
+  (((__INSTANCE__) == TIM1)    || \
+   ((__INSTANCE__) == TIM8) )
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
+    (((__INSTANCE__) == TIM1)    || \
+     ((__INSTANCE__) == TIM2)    || \
+     ((__INSTANCE__) == TIM3)    || \
+     ((__INSTANCE__) == TIM4)    || \
+     ((__INSTANCE__) == TIM5)    || \
+     ((__INSTANCE__) == TIM6)    || \
+     ((__INSTANCE__) == TIM7)    || \
+     ((__INSTANCE__) == TIM8))  
+      
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                     ((__INSTANCE__) == USART2) || \
+                                     ((__INSTANCE__) == USART3) || \
+                                     ((__INSTANCE__) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                    ((__INSTANCE__) == USART2) || \
+                                    ((__INSTANCE__) == USART3) || \
+                                    ((__INSTANCE__) == UART4)  || \
+                                    ((__INSTANCE__) == UART5)  || \
+                                    ((__INSTANCE__) == USART6) || \
+                                    ((__INSTANCE__) == UART7)  || \
+                                    ((__INSTANCE__) == UART8))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                    ((__INSTANCE__) == USART2) || \
+                                    ((__INSTANCE__) == USART3) || \
+                                    ((__INSTANCE__) == UART4)  || \
+                                    ((__INSTANCE__) == UART5)  || \
+                                    ((__INSTANCE__) == USART6) || \
+                                    ((__INSTANCE__) == UART7)  || \
+                                    ((__INSTANCE__) == UART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                    ((__INSTANCE__) == USART2) || \
+                                    ((__INSTANCE__) == USART3) || \
+                                    ((__INSTANCE__) == UART4)  || \
+                                    ((__INSTANCE__) == UART5)  || \
+                                    ((__INSTANCE__) == USART6) || \
+                                    ((__INSTANCE__) == UART7)  || \
+                                    ((__INSTANCE__) == UART8))
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                         ((__INSTANCE__) == USART2) || \
+                                         ((__INSTANCE__) == USART3) || \
+                                         ((__INSTANCE__) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
+                                    ((__INSTANCE__) == USART2) || \
+                                    ((__INSTANCE__) == USART3) || \
+                                    ((__INSTANCE__) == UART4)  || \
+                                    ((__INSTANCE__) == UART5)  || \
+                                    ((__INSTANCE__) == USART6) || \
+                                    ((__INSTANCE__) == UART7)  || \
+                                    ((__INSTANCE__) == UART8))     
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == WWDG)
+
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32F7xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */
+/*  product lines within the same STM32F7 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define RNG_IRQn              HASH_RNG_IRQn
+
+/* Aliases for __IRQHandler */
+#define RNG_IRQHandler        HASH_RNG_IRQHandler
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F756xx_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f7xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f7xx.h
new file mode 100644
index 00000000000..47b6ee63fd1
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f7xx.h
@@ -0,0 +1,216 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    22-April-2016
+  * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.           
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32F7xx device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral�s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f7xx
+  * @{
+  */
+    
+#ifndef __STM32F7xx_H
+#define __STM32F7xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined  (STM32F7)
+#define STM32F7
+#endif /* STM32F7 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
+    !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx)
+  #define STM32F756xx         /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
+                                   STM32F756NG Devices */
+  /* #define STM32F746xx */   /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
+                                   STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */
+  /* #define STM32F745xx */   /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */
+  /* #define STM32F765xx */   /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
+                                   STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
+  /* #define STM32F767xx */   /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
+                                   STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI, STM32F768AI Devices */
+  /* #define STM32F769xx */   /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
+                                   STM32F769NG, STM32F769NI Devices */
+  /* #define STM32F777xx */   /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI, STM32F778AI Devices */
+  /* #define STM32F779xx */   /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.1.0
+  */
+#define __STM32F7_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32F7_CMSIS_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F7_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F7_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F7_CMSIS_VERSION        ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32F7_CMSIS_VERSION))
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+#if defined(STM32F756xx)
+  #include "stm32f756xx.h"
+#elif defined(STM32F746xx)
+  #include "stm32f746xx.h"
+#elif defined(STM32F745xx)
+  #include "stm32f745xx.h"
+#elif defined(STM32F765xx)
+  #include "stm32f765xx.h"
+#elif defined(STM32F767xx)
+  #include "stm32f767xx.h"
+#elif defined(STM32F769xx)
+  #include "stm32f769xx.h"
+#elif defined(STM32F777xx)
+  #include "stm32f777xx.h"
+#elif defined(STM32F779xx)
+  #include "stm32f779xx.h"  
+#else
+ #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  ERROR = 0, 
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Exported_macro
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+/**
+  * @}
+  */
+
+#ifdef USE_HAL_DRIVER
+  #include "stm32f7xx_hal_conf.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F7xx_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_ARM_MICRO/startup_stm32f746zg.S
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_ARM_MICRO/stm32f746zg.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_ARM_MICRO/stm32f746zg.sct
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_ARM_MICRO/stm32f746zg.sct
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_ARM_MICRO/stm32f746zg.sct
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_ARM_STD/startup_stm32f746zg.S
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_ARM_STD/stm32f746zg.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_ARM_STD/stm32f746zg.sct
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_ARM_STD/stm32f746zg.sct
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_ARM_STD/stm32f746zg.sct
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_ARM_STD/sys.cpp
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_ARM_STD/sys.cpp
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_ARM_STD/sys.cpp
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_GCC_ARM/STM32F746ZG.ld b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_GCC_ARM/STM32F746ZG.ld
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_GCC_ARM/STM32F746ZG.ld
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_GCC_ARM/STM32F746ZG.ld
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_IAR/startup_stm32f746xx.S b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_IAR/startup_stm32f746xx.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_IAR/startup_stm32f746xx.S
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_IAR/startup_stm32f746xx.S
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_IAR/stm32f746zg.icf b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_IAR/stm32f746zg.icf
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/TOOLCHAIN_IAR/stm32f746zg.icf
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/TOOLCHAIN_IAR/stm32f746zg.icf
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/cmsis.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/cmsis.h
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/cmsis.h
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/cmsis_nvic.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/cmsis_nvic.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/cmsis_nvic.c
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/cmsis_nvic.c
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/cmsis_nvic.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/cmsis_nvic.h
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/cmsis_nvic.h
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/hal_tick.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/hal_tick.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/hal_tick.c
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/hal_tick.c
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/hal_tick.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/hal_tick.h
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/hal_tick.h
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/stm32f7xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/stm32f7xx_hal_conf.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/stm32f7xx_hal_conf.h
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/stm32f7xx_hal_conf.h
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/system_stm32f7xx.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/system_stm32f7xx.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/system_stm32f7xx.c
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/system_stm32f7xx.c
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/system_stm32f7xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/system_stm32f7xx.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/device/system_stm32f7xx.h
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/system_stm32f7xx.h
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/objects.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/objects.h
rename to targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/objects.h
diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h
index c46f27a052a..d2fef8854e8 100644
--- a/targets/TARGET_STM/mbed_rtx.h
+++ b/targets/TARGET_STM/mbed_rtx.h
@@ -452,7 +452,7 @@
 #define OS_CLOCK                216000000
 #endif
 
-#elif defined(TARGET_STM32F746ZG)
+#elif (defined(TARGET_STM32F746ZG) || defined(TARGET_STM32F756ZG))
 
 #ifndef INITIAL_SP
 #define INITIAL_SP              (0x20050000UL)
diff --git a/targets/targets.json b/targets/targets.json
index 7d6ea0c3f84..38be1eaa0ca 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -888,7 +888,7 @@
     "NUCLEO_F746ZG": {
         "inherits": ["Target"],
         "core": "Cortex-M7F",
-        "extra_labels": ["STM", "STM32F7", "STM32F746", "STM32F746ZG"],
+        "extra_labels": ["STM", "STM32F7", "STM32F746", "STM32F746ZG", "F746_F756"],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "default_toolchain": "ARM",
         "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
@@ -899,6 +899,19 @@
         "release_versions": ["2", "5"],
         "device_name": "STM32F746ZG"
     },
+    "NUCLEO_F756ZG": {
+        "inherits": ["Target"],
+        "core": "Cortex-M7F",
+        "extra_labels": ["STM", "STM32F7", "STM32F756", "STM32F756ZG", "F746_F756"],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "default_toolchain": "ARM",
+        "supported_form_factors": ["ARDUINO"],
+        "detect_code": ["0819"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "features": ["LWIP"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F756ZG"
+    },
     "NUCLEO_F767ZI": {
         "inherits": ["Target"],
         "core": "Cortex-M7FD",

From dbafb03dd2eea628dc41b92b39d6385231bc697d Mon Sep 17 00:00:00 2001
From: Andres AG <andres.amayagarcia@arm.com>
Date: Thu, 13 Oct 2016 17:33:57 +0100
Subject: [PATCH 85/89] Update to mbed TLS release candidate

---
 features/mbedtls/VERSION.txt                |   2 +-
 features/mbedtls/inc/mbedtls/cmac.h         |   4 -
 features/mbedtls/inc/mbedtls/config.h       |  12 --
 features/mbedtls/inc/mbedtls/gcm.h          |   4 +-
 features/mbedtls/inc/mbedtls/ssl.h          |   2 +
 features/mbedtls/inc/mbedtls/ssl_internal.h |   6 +
 features/mbedtls/inc/mbedtls/x509_csr.h     |   2 +-
 features/mbedtls/src/asn1parse.c            |   2 +-
 features/mbedtls/src/cmac.c                 |  74 ++++++------
 features/mbedtls/src/error.c                |   4 +
 features/mbedtls/src/gcm.c                  |   3 +-
 features/mbedtls/src/rsa.c                  |  18 ++-
 features/mbedtls/src/sha256.c               |  15 ++-
 features/mbedtls/src/sha512.c               |  15 ++-
 features/mbedtls/src/ssl_cli.c              |  18 +++
 features/mbedtls/src/ssl_srv.c              |  63 ++++++----
 features/mbedtls/src/ssl_tls.c              | 123 ++++++++++++++++----
 features/mbedtls/src/threading.c            |   5 +-
 features/mbedtls/src/version_features.c     |   3 -
 features/mbedtls/src/x509.c                 |  36 +++++-
 features/mbedtls/src/x509write_crt.c        |   3 +
 features/mbedtls/src/x509write_csr.c        |   3 +
 22 files changed, 290 insertions(+), 127 deletions(-)

diff --git a/features/mbedtls/VERSION.txt b/features/mbedtls/VERSION.txt
index 1dc8d398707..bc9d7e9d2cf 100644
--- a/features/mbedtls/VERSION.txt
+++ b/features/mbedtls/VERSION.txt
@@ -1 +1 @@
-a592dcc1c6277bb191269e709cdd3d5593e593ed
+8e004104020dd4328434e8a207245b0327bbb9b1
diff --git a/features/mbedtls/inc/mbedtls/cmac.h b/features/mbedtls/inc/mbedtls/cmac.h
index f64ae69b471..75e0b97c4ad 100644
--- a/features/mbedtls/inc/mbedtls/cmac.h
+++ b/features/mbedtls/inc/mbedtls/cmac.h
@@ -44,7 +44,6 @@ extern "C" {
  */
 struct mbedtls_cmac_context_t
 {
-
     /** Internal state of the CMAC algorithm  */
     unsigned char       state[MBEDTLS_CIPHER_BLKSIZE_MAX];
 
@@ -54,9 +53,6 @@ struct mbedtls_cmac_context_t
 
     /** Length of data pending to be processed */
     size_t              unprocessed_len;
-
-    /** Flag to indicate if the last block needs padding */
-    int                 padding_flag;
 };
 
 /**
diff --git a/features/mbedtls/inc/mbedtls/config.h b/features/mbedtls/inc/mbedtls/config.h
index e9b862a2b34..40fcf85b94d 100644
--- a/features/mbedtls/inc/mbedtls/config.h
+++ b/features/mbedtls/inc/mbedtls/config.h
@@ -955,18 +955,6 @@
  */
 //#define MBEDTLS_SHA256_SMALLER
 
-/**
- * \def MBEDTLS_SSL_AEAD_RANDOM_IV
- *
- * Generate a random IV rather than using the record sequence number as a
- * nonce for ciphersuites using and AEAD algorithm (GCM or CCM).
- *
- * Using the sequence number is generally recommended.
- *
- * Uncomment this macro to always use random IVs with AEAD ciphersuites.
- */
-//#define MBEDTLS_SSL_AEAD_RANDOM_IV
-
 /**
  * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES
  *
diff --git a/features/mbedtls/inc/mbedtls/gcm.h b/features/mbedtls/inc/mbedtls/gcm.h
index 6743ac9a5f9..1b77aaedd48 100644
--- a/features/mbedtls/inc/mbedtls/gcm.h
+++ b/features/mbedtls/inc/mbedtls/gcm.h
@@ -190,8 +190,8 @@ int mbedtls_gcm_update( mbedtls_gcm_context *ctx,
  *                  16 bytes.
  *
  * \param ctx       GCM context
- * \param tag       buffer for holding the tag (may be NULL if tag_len is 0)
- * \param tag_len   length of the tag to generate
+ * \param tag       buffer for holding the tag
+ * \param tag_len   length of the tag to generate (must be at least 4)
  *
  * \return          0 if successful or MBEDTLS_ERR_GCM_BAD_INPUT
  */
diff --git a/features/mbedtls/inc/mbedtls/ssl.h b/features/mbedtls/inc/mbedtls/ssl.h
index 1c0513da7f6..ba499d2bde6 100644
--- a/features/mbedtls/inc/mbedtls/ssl.h
+++ b/features/mbedtls/inc/mbedtls/ssl.h
@@ -107,6 +107,8 @@
 #define MBEDTLS_ERR_SSL_TIMEOUT                           -0x6800  /**< The operation timed out. */
 #define MBEDTLS_ERR_SSL_CLIENT_RECONNECT                  -0x6780  /**< The client initiated a reconnect from the same port. */
 #define MBEDTLS_ERR_SSL_UNEXPECTED_RECORD                 -0x6700  /**< Record header looks valid but is not expected. */
+#define MBEDTLS_ERR_SSL_NON_FATAL                         -0x6680  /**< The alert message received indicates a non-fatal error. */
+#define MBEDTLS_ERR_SSL_INVALID_VERIFY_HASH               -0x6600  /**< Couldn't set the hash for verifying CertificateVerify */
 
 /*
  * Various constants
diff --git a/features/mbedtls/inc/mbedtls/ssl_internal.h b/features/mbedtls/inc/mbedtls/ssl_internal.h
index d63d7d4e7ec..668c0f567cc 100644
--- a/features/mbedtls/inc/mbedtls/ssl_internal.h
+++ b/features/mbedtls/inc/mbedtls/ssl_internal.h
@@ -355,6 +355,11 @@ int mbedtls_ssl_send_fatal_handshake_failure( mbedtls_ssl_context *ssl );
 void mbedtls_ssl_reset_checksum( mbedtls_ssl_context *ssl );
 int mbedtls_ssl_derive_keys( mbedtls_ssl_context *ssl );
 
+int mbedtls_ssl_read_record_layer( mbedtls_ssl_context *ssl );
+int mbedtls_ssl_handle_message_type( mbedtls_ssl_context *ssl );
+int mbedtls_ssl_prepare_handshake_record( mbedtls_ssl_context *ssl );
+void mbedtls_ssl_update_handshake_status( mbedtls_ssl_context *ssl );
+
 int mbedtls_ssl_read_record( mbedtls_ssl_context *ssl );
 int mbedtls_ssl_fetch_input( mbedtls_ssl_context *ssl, size_t nb_want );
 
@@ -384,6 +389,7 @@ mbedtls_pk_type_t mbedtls_ssl_pk_alg_from_sig( unsigned char sig );
 
 mbedtls_md_type_t mbedtls_ssl_md_alg_from_hash( unsigned char hash );
 unsigned char mbedtls_ssl_hash_from_md_alg( int md );
+int mbedtls_ssl_set_calc_verify_md( mbedtls_ssl_context *ssl, int md );
 
 #if defined(MBEDTLS_ECP_C)
 int mbedtls_ssl_check_curve( const mbedtls_ssl_context *ssl, mbedtls_ecp_group_id grp_id );
diff --git a/features/mbedtls/inc/mbedtls/x509_csr.h b/features/mbedtls/inc/mbedtls/x509_csr.h
index 7a9c2e0550e..fe9843cb545 100644
--- a/features/mbedtls/inc/mbedtls/x509_csr.h
+++ b/features/mbedtls/inc/mbedtls/x509_csr.h
@@ -282,7 +282,7 @@ int mbedtls_x509write_csr_der( mbedtls_x509write_csr *ctx, unsigned char *buf, s
  *
  * \note            f_rng may be NULL if RSA is used for signature and the
  *                  signature is made offline (otherwise f_rng is desirable
- *                  for couermeasures against timing attacks).
+ *                  for countermeasures against timing attacks).
  *                  ECDSA signatures always require a non-NULL f_rng.
  */
 int mbedtls_x509write_csr_pem( mbedtls_x509write_csr *ctx, unsigned char *buf, size_t size,
diff --git a/features/mbedtls/src/asn1parse.c b/features/mbedtls/src/asn1parse.c
index ffa2f5299a4..4dd65c03c02 100644
--- a/features/mbedtls/src/asn1parse.c
+++ b/features/mbedtls/src/asn1parse.c
@@ -153,7 +153,7 @@ int mbedtls_asn1_get_int( unsigned char **p,
     if( ( ret = mbedtls_asn1_get_tag( p, end, &len, MBEDTLS_ASN1_INTEGER ) ) != 0 )
         return( ret );
 
-    if( len > sizeof( int ) || ( **p & 0x80 ) != 0 )
+    if( len == 0 || len > sizeof( int ) || ( **p & 0x80 ) != 0 )
         return( MBEDTLS_ERR_ASN1_INVALID_LENGTH );
 
     *val = 0;
diff --git a/features/mbedtls/src/cmac.c b/features/mbedtls/src/cmac.c
index 03d939278a2..ee2fe056ce6 100644
--- a/features/mbedtls/src/cmac.c
+++ b/features/mbedtls/src/cmac.c
@@ -235,7 +235,6 @@ int mbedtls_cipher_cmac_starts( mbedtls_cipher_context_t *ctx,
     ctx->cmac_ctx = cmac_ctx;
 
     mbedtls_zeroize( cmac_ctx->state, sizeof( cmac_ctx->state ) );
-    cmac_ctx->padding_flag = 1;
 
     return 0;
 }
@@ -256,8 +255,8 @@ int mbedtls_cipher_cmac_update( mbedtls_cipher_context_t *ctx,
     block_size = ctx->cipher_info->block_size;
     state = ctx->cmac_ctx->state;
 
-    /* Is their data still to process from the last call, that's equal to
-     * or greater than a block? */
+    /* Is there data still to process from the last call, that's greater in
+     * size than a block? */
     if( cmac_ctx->unprocessed_len > 0 &&
         ilen > block_size - cmac_ctx->unprocessed_len )
     {
@@ -273,9 +272,8 @@ int mbedtls_cipher_cmac_update( mbedtls_cipher_context_t *ctx,
            goto exit;
         }
 
-        ilen -= block_size;
-        input += cmac_ctx->unprocessed_len;
-
+        input += block_size - cmac_ctx->unprocessed_len;
+        ilen -= block_size - cmac_ctx->unprocessed_len;
         cmac_ctx->unprocessed_len = 0;
     }
 
@@ -293,20 +291,15 @@ int mbedtls_cipher_cmac_update( mbedtls_cipher_context_t *ctx,
 
         ilen -= block_size;
         input += block_size;
-
-        cmac_ctx->padding_flag = 0;
     }
 
     /* If there is data left over that wasn't aligned to a block */
     if( ilen > 0 )
     {
-        memcpy( &cmac_ctx->unprocessed_block, input, ilen );
-        cmac_ctx->unprocessed_len = ilen;
-
-        if( ilen % block_size > 0 )
-            cmac_ctx->padding_flag = 1;
-        else
-            cmac_ctx->padding_flag = 0;
+        memcpy( &cmac_ctx->unprocessed_block[cmac_ctx->unprocessed_len],
+                input,
+                ilen );
+        cmac_ctx->unprocessed_len += ilen;
     }
 
 exit:
@@ -339,7 +332,7 @@ int mbedtls_cipher_cmac_finish( mbedtls_cipher_context_t *ctx,
     last_block = cmac_ctx->unprocessed_block;
 
     /* Calculate last block */
-    if( cmac_ctx->padding_flag )
+    if( cmac_ctx->unprocessed_len < block_size )
     {
         cmac_pad( M_last, block_size, last_block, cmac_ctx->unprocessed_len );
         cmac_xor_block( M_last, M_last, K2, block_size );
@@ -366,7 +359,6 @@ int mbedtls_cipher_cmac_finish( mbedtls_cipher_context_t *ctx,
     mbedtls_zeroize( K1, sizeof( K1 ) );
     mbedtls_zeroize( K2, sizeof( K2 ) );
 
-    cmac_ctx->padding_flag = 1;
     cmac_ctx->unprocessed_len = 0;
     mbedtls_zeroize( cmac_ctx->unprocessed_block,
                      sizeof( cmac_ctx->unprocessed_block ) );
@@ -390,7 +382,6 @@ int mbedtls_cipher_cmac_reset( mbedtls_cipher_context_t *ctx )
                      sizeof( cmac_ctx->unprocessed_block ) );
     mbedtls_zeroize( cmac_ctx->state,
                      sizeof( cmac_ctx->state ) );
-    cmac_ctx->padding_flag = 1;
 
     return( 0 );
 }
@@ -746,19 +737,19 @@ static int cmac_test_subkeys( int verbose,
         return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE );
     }
 
-    mbedtls_cipher_init( &ctx );
-
     for( i = 0; i < num_tests; i++ )
     {
         if( verbose != 0 )
             mbedtls_printf( "  %s CMAC subkey #%u: ", testname, i + 1 );
 
+        mbedtls_cipher_init( &ctx );
+
         if( ( ret = mbedtls_cipher_setup( &ctx, cipher_info ) ) != 0 )
         {
             if( verbose != 0 )
                 mbedtls_printf( "test execution failed\n" );
 
-            goto exit;
+            goto cleanup;
         }
 
         if( ( ret = mbedtls_cipher_setkey( &ctx, key, keybits,
@@ -767,7 +758,7 @@ static int cmac_test_subkeys( int verbose,
             if( verbose != 0 )
                 mbedtls_printf( "test execution failed\n" );
 
-            goto exit;
+            goto cleanup;
         }
 
         ret = cmac_generate_subkeys( &ctx, K1, K2 );
@@ -775,24 +766,31 @@ static int cmac_test_subkeys( int verbose,
         {
            if( verbose != 0 )
                 mbedtls_printf( "failed\n" );
-            goto exit;
+
+            goto cleanup;
         }
 
-        if( ( ret = memcmp( K1, subkeys, block_size ) != 0 ) ||
-            ( ret = memcmp( K2, &subkeys[block_size], block_size ) != 0 ) )
+        if( ( ret = memcmp( K1, subkeys, block_size ) ) != 0  ||
+            ( ret = memcmp( K2, &subkeys[block_size], block_size ) ) != 0 )
         {
             if( verbose != 0 )
                 mbedtls_printf( "failed\n" );
-            goto exit;
+
+            goto cleanup;
         }
 
         if( verbose != 0 )
             mbedtls_printf( "passed\n" );
+
+        mbedtls_cipher_free( &ctx );
     }
 
-exit:
+    goto exit;
+
+cleanup:
     mbedtls_cipher_free( &ctx );
 
+exit:
     return( ret );
 }
 
@@ -889,7 +887,7 @@ int mbedtls_cmac_self_test( int verbose )
                                    (const unsigned char*)aes_128_subkeys,
                                    MBEDTLS_CIPHER_AES_128_ECB,
                                    MBEDTLS_AES_BLOCK_SIZE,
-                                   NB_CMAC_TESTS_PER_KEY ) != 0 ) )
+                                   NB_CMAC_TESTS_PER_KEY ) ) != 0 )
     {
         return( ret );
     }
@@ -903,7 +901,7 @@ int mbedtls_cmac_self_test( int verbose )
                                       (const unsigned char*)aes_128_expected_result,
                                       MBEDTLS_CIPHER_AES_128_ECB,
                                       MBEDTLS_AES_BLOCK_SIZE,
-                                      NB_CMAC_TESTS_PER_KEY ) != 0 ) )
+                                      NB_CMAC_TESTS_PER_KEY ) ) != 0 )
     {
         return( ret );
     }
@@ -916,7 +914,7 @@ int mbedtls_cmac_self_test( int verbose )
                                    (const unsigned char*)aes_192_subkeys,
                                    MBEDTLS_CIPHER_AES_192_ECB,
                                    MBEDTLS_AES_BLOCK_SIZE,
-                                   NB_CMAC_TESTS_PER_KEY ) != 0 ) )
+                                   NB_CMAC_TESTS_PER_KEY ) ) != 0 )
     {
         return( ret );
     }
@@ -930,7 +928,7 @@ int mbedtls_cmac_self_test( int verbose )
                                       (const unsigned char*)aes_192_expected_result,
                                       MBEDTLS_CIPHER_AES_192_ECB,
                                       MBEDTLS_AES_BLOCK_SIZE,
-                                      NB_CMAC_TESTS_PER_KEY ) != 0 ) )
+                                      NB_CMAC_TESTS_PER_KEY ) ) != 0 )
     {
         return( ret );
     }
@@ -943,7 +941,7 @@ int mbedtls_cmac_self_test( int verbose )
                                    (const unsigned char*)aes_256_subkeys,
                                    MBEDTLS_CIPHER_AES_256_ECB,
                                    MBEDTLS_AES_BLOCK_SIZE,
-                                   NB_CMAC_TESTS_PER_KEY ) != 0 ) )
+                                   NB_CMAC_TESTS_PER_KEY ) ) != 0 )
     {
         return( ret );
     }
@@ -957,7 +955,7 @@ int mbedtls_cmac_self_test( int verbose )
                                        (const unsigned char*)aes_256_expected_result,
                                        MBEDTLS_CIPHER_AES_256_ECB,
                                        MBEDTLS_AES_BLOCK_SIZE,
-                                       NB_CMAC_TESTS_PER_KEY ) != 0 ) )
+                                       NB_CMAC_TESTS_PER_KEY ) ) != 0 )
     {
         return( ret );
     }
@@ -972,7 +970,7 @@ int mbedtls_cmac_self_test( int verbose )
                                    (const unsigned char*)des3_2key_subkeys,
                                    MBEDTLS_CIPHER_DES_EDE3_ECB,
                                    MBEDTLS_DES3_BLOCK_SIZE,
-                                   NB_CMAC_TESTS_PER_KEY ) != 0 ) )
+                                   NB_CMAC_TESTS_PER_KEY ) ) != 0 )
     {
         return( ret );
     }
@@ -986,7 +984,7 @@ int mbedtls_cmac_self_test( int verbose )
                                       (const unsigned char*)des3_2key_expected_result,
                                       MBEDTLS_CIPHER_DES_EDE3_ECB,
                                       MBEDTLS_DES3_BLOCK_SIZE,
-                                      NB_CMAC_TESTS_PER_KEY ) != 0 ) )
+                                      NB_CMAC_TESTS_PER_KEY ) ) != 0 )
     {
         return( ret );
     }
@@ -999,7 +997,7 @@ int mbedtls_cmac_self_test( int verbose )
                                    (const unsigned char*)des3_3key_subkeys,
                                    MBEDTLS_CIPHER_DES_EDE3_ECB,
                                    MBEDTLS_DES3_BLOCK_SIZE,
-                                   NB_CMAC_TESTS_PER_KEY ) != 0 ) )
+                                   NB_CMAC_TESTS_PER_KEY ) ) != 0 )
     {
         return( ret );
     }
@@ -1013,14 +1011,14 @@ int mbedtls_cmac_self_test( int verbose )
                                       (const unsigned char*)des3_3key_expected_result,
                                       MBEDTLS_CIPHER_DES_EDE3_ECB,
                                       MBEDTLS_DES3_BLOCK_SIZE,
-                                      NB_CMAC_TESTS_PER_KEY ) != 0 ) )
+                                      NB_CMAC_TESTS_PER_KEY ) ) != 0 )
     {
         return( ret );
     }
 #endif /* MBEDTLS_DES_C */
 
 #if defined(MBEDTLS_AES_C)
-    if( ( ret = test_aes128_cmac_prf( verbose ) != 0 ) )
+    if( ( ret = test_aes128_cmac_prf( verbose ) ) != 0 )
         return( ret );
 #endif /* MBEDTLS_AES_C */
 
diff --git a/features/mbedtls/src/error.c b/features/mbedtls/src/error.c
index 71d4faa7080..dd2db0c45c0 100644
--- a/features/mbedtls/src/error.c
+++ b/features/mbedtls/src/error.c
@@ -435,6 +435,10 @@ void mbedtls_strerror( int ret, char *buf, size_t buflen )
             mbedtls_snprintf( buf, buflen, "SSL - The client initiated a reconnect from the same port" );
         if( use_ret == -(MBEDTLS_ERR_SSL_UNEXPECTED_RECORD) )
             mbedtls_snprintf( buf, buflen, "SSL - Record header looks valid but is not expected" );
+        if( use_ret == -(MBEDTLS_ERR_SSL_NON_FATAL) )
+            mbedtls_snprintf( buf, buflen, "SSL - The alert message received indicates a non-fatal error" );
+        if( use_ret == -(MBEDTLS_ERR_SSL_INVALID_VERIFY_HASH) )
+            mbedtls_snprintf( buf, buflen, "SSL - Couldn't set the hash for verifying CertificateVerify" );
 #endif /* MBEDTLS_SSL_TLS_C */
 
 #if defined(MBEDTLS_X509_USE_C) || defined(MBEDTLS_X509_CREATE_C)
diff --git a/features/mbedtls/src/gcm.c b/features/mbedtls/src/gcm.c
index aaacf97d612..f1210c52c39 100644
--- a/features/mbedtls/src/gcm.c
+++ b/features/mbedtls/src/gcm.c
@@ -415,8 +415,7 @@ int mbedtls_gcm_finish( mbedtls_gcm_context *ctx,
     if( tag_len > 16 || tag_len < 4 )
         return( MBEDTLS_ERR_GCM_BAD_INPUT );
 
-    if( tag_len != 0 )
-        memcpy( tag, ctx->base_ectr, tag_len );
+    memcpy( tag, ctx->base_ectr, tag_len );
 
     if( orig_len || orig_add_len )
     {
diff --git a/features/mbedtls/src/rsa.c b/features/mbedtls/src/rsa.c
index 7a33689b2e3..40ef2a9480f 100644
--- a/features/mbedtls/src/rsa.c
+++ b/features/mbedtls/src/rsa.c
@@ -102,7 +102,10 @@ int mbedtls_rsa_gen_key( mbedtls_rsa_context *ctx,
     if( f_rng == NULL || nbits < 128 || exponent < 3 )
         return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA );
 
-    mbedtls_mpi_init( &P1 ); mbedtls_mpi_init( &Q1 ); 
+    if( nbits % 2 )
+        return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA );
+
+    mbedtls_mpi_init( &P1 ); mbedtls_mpi_init( &Q1 );
     mbedtls_mpi_init( &H ); mbedtls_mpi_init( &G );
 
     /*
@@ -116,16 +119,8 @@ int mbedtls_rsa_gen_key( mbedtls_rsa_context *ctx,
         MBEDTLS_MPI_CHK( mbedtls_mpi_gen_prime( &ctx->P, nbits >> 1, 0,
                                 f_rng, p_rng ) );
 
-        if( nbits % 2 )
-        {
-            MBEDTLS_MPI_CHK( mbedtls_mpi_gen_prime( &ctx->Q, ( nbits >> 1 ) + 1, 0,
+        MBEDTLS_MPI_CHK( mbedtls_mpi_gen_prime( &ctx->Q, nbits >> 1, 0,
                                 f_rng, p_rng ) );
-        }
-        else
-        {
-            MBEDTLS_MPI_CHK( mbedtls_mpi_gen_prime( &ctx->Q, nbits >> 1, 0,
-                                f_rng, p_rng ) );
-        }
 
         if( mbedtls_mpi_cmp_mpi( &ctx->P, &ctx->Q ) == 0 )
             continue;
@@ -134,6 +129,9 @@ int mbedtls_rsa_gen_key( mbedtls_rsa_context *ctx,
         if( mbedtls_mpi_bitlen( &ctx->N ) != nbits )
             continue;
 
+        if( mbedtls_mpi_cmp_mpi( &ctx->P, &ctx->Q ) < 0 )
+                                mbedtls_mpi_swap( &ctx->P, &ctx->Q );
+
         MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &P1, &ctx->P, 1 ) );
         MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &Q1, &ctx->Q, 1 ) );
         MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &H, &P1, &Q1 ) );
diff --git a/features/mbedtls/src/sha256.c b/features/mbedtls/src/sha256.c
index 4e82c0b7931..ad25d38333f 100644
--- a/features/mbedtls/src/sha256.c
+++ b/features/mbedtls/src/sha256.c
@@ -41,7 +41,10 @@
 #include "mbedtls/platform.h"
 #else
 #include <stdio.h>
+#include <stdlib.h>
 #define mbedtls_printf printf
+#define mbedtls_calloc    calloc
+#define mbedtls_free       free
 #endif /* MBEDTLS_PLATFORM_C */
 #endif /* MBEDTLS_SELF_TEST */
 
@@ -389,10 +392,19 @@ static const unsigned char sha256_test_sum[6][32] =
 int mbedtls_sha256_self_test( int verbose )
 {
     int i, j, k, buflen, ret = 0;
-    unsigned char buf[1024];
+    unsigned char *buf;
     unsigned char sha256sum[32];
     mbedtls_sha256_context ctx;
 
+    buf = mbedtls_calloc( 1024, sizeof(unsigned char) );
+    if( NULL == buf )
+    {
+        if( verbose != 0 )
+            mbedtls_printf( "Buffer allocation failed\n" );
+
+        return( 1 );
+    }
+
     mbedtls_sha256_init( &ctx );
 
     for( i = 0; i < 6; i++ )
@@ -436,6 +448,7 @@ int mbedtls_sha256_self_test( int verbose )
 
 exit:
     mbedtls_sha256_free( &ctx );
+    mbedtls_free( buf );
 
     return( ret );
 }
diff --git a/features/mbedtls/src/sha512.c b/features/mbedtls/src/sha512.c
index 0f9e1e5352f..724522ac68f 100644
--- a/features/mbedtls/src/sha512.c
+++ b/features/mbedtls/src/sha512.c
@@ -47,7 +47,10 @@
 #include "mbedtls/platform.h"
 #else
 #include <stdio.h>
+#include <stdlib.h>
 #define mbedtls_printf printf
+#define mbedtls_calloc    calloc
+#define mbedtls_free       free
 #endif /* MBEDTLS_PLATFORM_C */
 #endif /* MBEDTLS_SELF_TEST */
 
@@ -445,10 +448,19 @@ static const unsigned char sha512_test_sum[6][64] =
 int mbedtls_sha512_self_test( int verbose )
 {
     int i, j, k, buflen, ret = 0;
-    unsigned char buf[1024];
+    unsigned char *buf;
     unsigned char sha512sum[64];
     mbedtls_sha512_context ctx;
 
+    buf = mbedtls_calloc( 1024, sizeof(unsigned char) );
+    if( NULL == buf )
+    {
+        if( verbose != 0 )
+            mbedtls_printf( "Buffer allocation failed\n" );
+
+        return( 1 );
+    }
+
     mbedtls_sha512_init( &ctx );
 
     for( i = 0; i < 6; i++ )
@@ -492,6 +504,7 @@ int mbedtls_sha512_self_test( int verbose )
 
 exit:
     mbedtls_sha512_free( &ctx );
+    mbedtls_free( buf );
 
     return( ret );
 }
diff --git a/features/mbedtls/src/ssl_cli.c b/features/mbedtls/src/ssl_cli.c
index 29a39435848..223823b3cd6 100644
--- a/features/mbedtls/src/ssl_cli.c
+++ b/features/mbedtls/src/ssl_cli.c
@@ -1355,6 +1355,15 @@ static int ssl_parse_hello_verify_request( mbedtls_ssl_context *ssl )
     cookie_len = *p++;
     MBEDTLS_SSL_DEBUG_BUF( 3, "cookie", p, cookie_len );
 
+    if( ( ssl->in_msg + ssl->in_msglen ) - p < cookie_len )
+    {
+        MBEDTLS_SSL_DEBUG_MSG( 1,
+            ( "cookie length does not match incoming message size" ) );
+        mbedtls_ssl_send_alert_message( ssl, MBEDTLS_SSL_ALERT_LEVEL_FATAL,
+                                    MBEDTLS_SSL_ALERT_MSG_DECODE_ERROR );
+        return( MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO );
+    }
+
     mbedtls_free( ssl->handshake->verify_cookie );
 
     ssl->handshake->verify_cookie = mbedtls_calloc( 1, cookie_len );
@@ -2630,6 +2639,15 @@ static int ssl_parse_certificate_request( mbedtls_ssl_context *ssl )
     {
         size_t sig_alg_len = ( ( buf[mbedtls_ssl_hs_hdr_len( ssl ) + 1 + n] <<  8 )
                              | ( buf[mbedtls_ssl_hs_hdr_len( ssl ) + 2 + n]       ) );
+#if defined(MBEDTLS_DEBUG_C)
+        unsigned char* sig_alg = buf + mbedtls_ssl_hs_hdr_len( ssl ) + 3 + n;
+        size_t i;
+
+        for( i = 0; i < sig_alg_len; i += 2 )
+        {
+            MBEDTLS_SSL_DEBUG_MSG( 3, ( "Supported Signature Algorithm found: %d,%d", sig_alg[i], sig_alg[i + 1]  ) );
+        }
+#endif
 
         n += 2 + sig_alg_len;
 
diff --git a/features/mbedtls/src/ssl_srv.c b/features/mbedtls/src/ssl_srv.c
index 4b0f9971430..fc0d2d7b427 100644
--- a/features/mbedtls/src/ssl_srv.c
+++ b/features/mbedtls/src/ssl_srv.c
@@ -1043,7 +1043,6 @@ static int ssl_parse_client_hello_v2( mbedtls_ssl_context *ssl )
 
     ssl->session_negotiate->ciphersuite = ciphersuites[i];
     ssl->transform_negotiate->ciphersuite_info = ciphersuite_info;
-    mbedtls_ssl_optimize_checksum( ssl, ssl->transform_negotiate->ciphersuite_info );
 
     /*
      * SSLv2 Client Hello relevant renegotiation security checks
@@ -1840,7 +1839,6 @@ static int ssl_parse_client_hello( mbedtls_ssl_context *ssl )
 
     ssl->session_negotiate->ciphersuite = ciphersuites[i];
     ssl->transform_negotiate->ciphersuite_info = ciphersuite_info;
-    mbedtls_ssl_optimize_checksum( ssl, ssl->transform_negotiate->ciphersuite_info );
 
     ssl->state++;
 
@@ -2556,29 +2554,27 @@ static int ssl_write_certificate_request( mbedtls_ssl_context *ssl )
      */
     if( ssl->minor_ver == MBEDTLS_SSL_MINOR_VERSION_3 )
     {
-        /*
-         * Only use current running hash algorithm that is already required
-         * for requested ciphersuite.
-         */
-        ssl->handshake->verify_sig_alg = MBEDTLS_SSL_HASH_SHA256;
-
-        if( ssl->transform_negotiate->ciphersuite_info->mac ==
-            MBEDTLS_MD_SHA384 )
-        {
-            ssl->handshake->verify_sig_alg = MBEDTLS_SSL_HASH_SHA384;
-        }
+        const int *cur;
 
         /*
          * Supported signature algorithms
          */
+        for( cur = ssl->conf->sig_hashes; *cur != MBEDTLS_MD_NONE; cur++ )
+        {
+            unsigned char hash = mbedtls_ssl_hash_from_md_alg( *cur );
+
+            if( MBEDTLS_SSL_HASH_NONE == hash || mbedtls_ssl_set_calc_verify_md( ssl, hash ) )
+                continue;
+
 #if defined(MBEDTLS_RSA_C)
-        p[2 + sa_len++] = ssl->handshake->verify_sig_alg;
-        p[2 + sa_len++] = MBEDTLS_SSL_SIG_RSA;
+            p[2 + sa_len++] = hash;
+            p[2 + sa_len++] = MBEDTLS_SSL_SIG_RSA;
 #endif
 #if defined(MBEDTLS_ECDSA_C)
-        p[2 + sa_len++] = ssl->handshake->verify_sig_alg;
-        p[2 + sa_len++] = MBEDTLS_SSL_SIG_ECDSA;
+            p[2 + sa_len++] = hash;
+            p[2 + sa_len++] = MBEDTLS_SSL_SIG_ECDSA;
 #endif
+        }
 
         p[0] = (unsigned char)( sa_len >> 8 );
         p[1] = (unsigned char)( sa_len      );
@@ -3581,17 +3577,28 @@ static int ssl_parse_certificate_verify( mbedtls_ssl_context *ssl )
         return( 0 );
     }
 
-    /* Needs to be done before read_record() to exclude current message */
-    ssl->handshake->calc_verify( ssl, hash );
+    /* Read the message without adding it to the checksum */
+    do {
 
-    if( ( ret = mbedtls_ssl_read_record( ssl ) ) != 0 )
+        if( ( ret = mbedtls_ssl_read_record_layer( ssl ) ) != 0 )
+        {
+            MBEDTLS_SSL_DEBUG_RET( 1, ( "mbedtls_ssl_read_record_layer" ), ret );
+            return( ret );
+        }
+
+        ret = mbedtls_ssl_handle_message_type( ssl );
+
+    } while( MBEDTLS_ERR_SSL_NON_FATAL == ret );
+
+    if( 0 != ret )
     {
-        MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_read_record", ret );
+        MBEDTLS_SSL_DEBUG_RET( 1, ( "mbedtls_ssl_handle_message_type" ), ret );
         return( ret );
     }
 
     ssl->state++;
 
+    /* Process the message contents */
     if( ssl->in_msgtype != MBEDTLS_SSL_MSG_HANDSHAKE ||
         ssl->in_msg[0] != MBEDTLS_SSL_HS_CERTIFICATE_VERIFY )
     {
@@ -3638,14 +3645,19 @@ static int ssl_parse_certificate_verify( mbedtls_ssl_context *ssl )
         /*
          * Hash
          */
-        if( ssl->in_msg[i] != ssl->handshake->verify_sig_alg )
+        md_alg = mbedtls_ssl_md_alg_from_hash( ssl->in_msg[i] );
+
+        if( md_alg == MBEDTLS_MD_NONE || mbedtls_ssl_set_calc_verify_md( ssl, ssl->in_msg[i] ) )
         {
             MBEDTLS_SSL_DEBUG_MSG( 1, ( "peer not adhering to requested sig_alg"
                                 " for verify message" ) );
             return( MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE_VERIFY );
         }
 
-        md_alg = mbedtls_ssl_md_alg_from_hash( ssl->handshake->verify_sig_alg );
+#if !defined(MBEDTLS_MD_SHA1)
+        if( MBEDTLS_MD_SHA1 == md_alg )
+            hash_start += 16;
+#endif
 
         /* Info from md_alg will be used instead */
         hashlen = 0;
@@ -3696,6 +3708,9 @@ static int ssl_parse_certificate_verify( mbedtls_ssl_context *ssl )
         return( MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE_VERIFY );
     }
 
+    /* Calculate hash and verify signature */
+    ssl->handshake->calc_verify( ssl, hash );
+
     if( ( ret = mbedtls_pk_verify( &ssl->session_negotiate->peer_cert->pk,
                            md_alg, hash_start, hashlen,
                            ssl->in_msg + i, sig_len ) ) != 0 )
@@ -3704,6 +3719,8 @@ static int ssl_parse_certificate_verify( mbedtls_ssl_context *ssl )
         return( ret );
     }
 
+    mbedtls_ssl_update_handshake_status( ssl );
+
     MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= parse certificate verify" ) );
 
     return( ret );
diff --git a/features/mbedtls/src/ssl_tls.c b/features/mbedtls/src/ssl_tls.c
index 505bb6cb3a5..84a04ae53f3 100644
--- a/features/mbedtls/src/ssl_tls.c
+++ b/features/mbedtls/src/ssl_tls.c
@@ -49,8 +49,7 @@
 
 #include <string.h>
 
-#if defined(MBEDTLS_X509_CRT_PARSE_C) && \
-    defined(MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE)
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
 #include "mbedtls/oid.h"
 #endif
 
@@ -1374,17 +1373,6 @@ static int ssl_encrypt_buf( mbedtls_ssl_context *ssl )
         /*
          * Generate IV
          */
-#if defined(MBEDTLS_SSL_AEAD_RANDOM_IV)
-        ret = ssl->conf->f_rng( ssl->conf->p_rng,
-                ssl->transform_out->iv_enc + ssl->transform_out->fixed_ivlen,
-                ssl->transform_out->ivlen - ssl->transform_out->fixed_ivlen );
-        if( ret != 0 )
-            return( ret );
-
-        memcpy( ssl->out_iv,
-                ssl->transform_out->iv_enc + ssl->transform_out->fixed_ivlen,
-                ssl->transform_out->ivlen - ssl->transform_out->fixed_ivlen );
-#else
         if( ssl->transform_out->ivlen - ssl->transform_out->fixed_ivlen != 8 )
         {
             /* Reminder if we ever add an AEAD mode with a different size */
@@ -1395,7 +1383,6 @@ static int ssl_encrypt_buf( mbedtls_ssl_context *ssl )
         memcpy( ssl->transform_out->iv_enc + ssl->transform_out->fixed_ivlen,
                              ssl->out_ctr, 8 );
         memcpy( ssl->out_iv, ssl->out_ctr, 8 );
-#endif
 
         MBEDTLS_SSL_DEBUG_BUF( 4, "IV used", ssl->out_iv,
                 ssl->transform_out->ivlen - ssl->transform_out->fixed_ivlen );
@@ -3083,7 +3070,7 @@ static int ssl_reassemble_dtls_handshake( mbedtls_ssl_context *ssl )
 }
 #endif /* MBEDTLS_SSL_PROTO_DTLS */
 
-static int ssl_prepare_handshake_record( mbedtls_ssl_context *ssl )
+int mbedtls_ssl_prepare_handshake_record( mbedtls_ssl_context *ssl )
 {
     if( ssl->in_msglen < mbedtls_ssl_hs_hdr_len( ssl ) )
     {
@@ -3165,6 +3152,12 @@ static int ssl_prepare_handshake_record( mbedtls_ssl_context *ssl )
         return( MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE );
     }
 
+    return( 0 );
+}
+
+void mbedtls_ssl_update_handshake_status( mbedtls_ssl_context *ssl )
+{
+
     if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER &&
         ssl->handshake != NULL )
     {
@@ -3179,8 +3172,6 @@ static int ssl_prepare_handshake_record( mbedtls_ssl_context *ssl )
         ssl->handshake->in_msg_seq++;
     }
 #endif
-
-    return( 0 );
 }
 
 /*
@@ -3736,6 +3727,38 @@ int mbedtls_ssl_read_record( mbedtls_ssl_context *ssl )
 
     MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> read record" ) );
 
+    do {
+
+        if( ( ret = mbedtls_ssl_read_record_layer( ssl ) ) != 0 )
+        {
+            MBEDTLS_SSL_DEBUG_RET( 1, ( "mbedtls_ssl_read_record_layer" ), ret );
+            return( ret );
+        }
+
+        ret = mbedtls_ssl_handle_message_type( ssl );
+
+    } while( MBEDTLS_ERR_SSL_NON_FATAL == ret );
+
+    if( 0 != ret )
+    {
+        MBEDTLS_SSL_DEBUG_RET( 1, ( "mbedtls_ssl_handle_message_type" ), ret );
+        return( ret );
+    }
+
+    if( ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE )
+    {
+        mbedtls_ssl_update_handshake_status( ssl );
+    }
+
+    MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= read record" ) );
+
+    return( 0 );
+}
+
+int mbedtls_ssl_read_record_layer( mbedtls_ssl_context *ssl )
+{
+    int ret;
+
     if( ssl->in_hslen != 0 && ssl->in_hslen < ssl->in_msglen )
     {
         /*
@@ -3749,9 +3772,6 @@ int mbedtls_ssl_read_record( mbedtls_ssl_context *ssl )
         MBEDTLS_SSL_DEBUG_BUF( 4, "remaining content in record",
                            ssl->in_msg, ssl->in_msglen );
 
-        if( ( ret = ssl_prepare_handshake_record( ssl ) ) != 0 )
-            return( ret );
-
         return( 0 );
     }
 
@@ -3760,7 +3780,10 @@ int mbedtls_ssl_read_record( mbedtls_ssl_context *ssl )
     /*
      * Read the record header and parse it
      */
+#if defined(MBEDTLS_SSL_PROTO_DTLS)
 read_record_header:
+#endif
+
     if( ( ret = mbedtls_ssl_fetch_input( ssl, mbedtls_ssl_hdr_len( ssl ) ) ) != 0 )
     {
         MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_fetch_input", ret );
@@ -3914,13 +3937,22 @@ int mbedtls_ssl_read_record( mbedtls_ssl_context *ssl )
     }
 #endif
 
+    return( 0 );
+}
+
+int mbedtls_ssl_handle_message_type( mbedtls_ssl_context *ssl )
+{
+    int ret;
+
     /*
      * Handle particular types of records
      */
     if( ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE )
     {
-        if( ( ret = ssl_prepare_handshake_record( ssl ) ) != 0 )
+        if( ( ret = mbedtls_ssl_prepare_handshake_record( ssl ) ) != 0 )
+        {
             return( ret );
+        }
     }
 
     if( ssl->in_msgtype == MBEDTLS_SSL_MSG_ALERT )
@@ -3968,11 +4000,9 @@ int mbedtls_ssl_read_record( mbedtls_ssl_context *ssl )
 #endif /* MBEDTLS_SSL_PROTO_SSL3 && MBEDTLS_SSL_SRV_C */
 
         /* Silently ignore: fetch new message */
-        goto read_record_header;
+        return MBEDTLS_ERR_SSL_NON_FATAL;
     }
 
-    MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= read record" ) );
-
     return( 0 );
 }
 
@@ -4347,7 +4377,7 @@ int mbedtls_ssl_parse_certificate( mbedtls_ssl_context *ssl )
 
         ret = mbedtls_x509_crt_parse_der( ssl->session_negotiate->peer_cert,
                                   ssl->in_msg + i, n );
-        if( ret != 0 )
+        if( 0 != ret && ( MBEDTLS_ERR_X509_UNKNOWN_SIG_ALG + MBEDTLS_ERR_OID_NOT_FOUND ) != ret )
         {
             MBEDTLS_SSL_DEBUG_RET( 1, " mbedtls_x509_crt_parse_der", ret );
             return( ret );
@@ -7603,4 +7633,47 @@ void mbedtls_ssl_read_version( int *major, int *minor, int transport,
     }
 }
 
+int mbedtls_ssl_set_calc_verify_md( mbedtls_ssl_context *ssl, int md )
+{
+#if defined(MBEDTLS_SSL_PROTO_TLS1_2)
+    if( ssl->minor_ver != MBEDTLS_SSL_MINOR_VERSION_3 )
+        return MBEDTLS_ERR_SSL_INVALID_VERIFY_HASH;
+
+    switch( md )
+    {
+#if defined(MBEDTLS_SSL_PROTO_TLS1) || defined(MBEDTLS_SSL_PROTO_TLS1_1)
+#if defined(MBEDTLS_MD5_C)
+        case MBEDTLS_SSL_HASH_MD5:
+            ssl->handshake->calc_verify = ssl_calc_verify_tls;
+            break;
+#endif
+#if defined(MBEDTLS_SHA1_C)
+        case MBEDTLS_SSL_HASH_SHA1:
+            ssl->handshake->calc_verify = ssl_calc_verify_tls;
+            break;
+#endif
+#endif /* MBEDTLS_SSL_PROTO_TLS1 || MBEDTLS_SSL_PROTO_TLS1_1 */
+#if defined(MBEDTLS_SHA512_C)
+        case MBEDTLS_SSL_HASH_SHA384:
+            ssl->handshake->calc_verify = ssl_calc_verify_tls_sha384;
+            break;
+#endif
+#if defined(MBEDTLS_SHA256_C)
+        case MBEDTLS_SSL_HASH_SHA256:
+            ssl->handshake->calc_verify = ssl_calc_verify_tls_sha256;
+            break;
+#endif
+        default:
+            return MBEDTLS_ERR_SSL_INVALID_VERIFY_HASH;
+    }
+
+    return 0;
+#else /* !MBEDTLS_SSL_PROTO_TLS1_2 */
+    (void) ssl;
+    (void) md;
+
+    return MBEDTLS_ERR_SSL_INVALID_VERIFY_HASH;
+#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */
+}
+
 #endif /* MBEDTLS_SSL_TLS_C */
diff --git a/features/mbedtls/src/threading.c b/features/mbedtls/src/threading.c
index 1b6d9cd4451..83ec01a45fd 100644
--- a/features/mbedtls/src/threading.c
+++ b/features/mbedtls/src/threading.c
@@ -32,7 +32,7 @@
 #if defined(MBEDTLS_THREADING_PTHREAD)
 static void threading_mutex_init_pthread( mbedtls_threading_mutex_t *mutex )
 {
-    if( mutex == NULL )
+    if( mutex == NULL || mutex->is_valid )
         return;
 
     mutex->is_valid = pthread_mutex_init( &mutex->mutex, NULL ) == 0;
@@ -40,10 +40,11 @@ static void threading_mutex_init_pthread( mbedtls_threading_mutex_t *mutex )
 
 static void threading_mutex_free_pthread( mbedtls_threading_mutex_t *mutex )
 {
-    if( mutex == NULL )
+    if( mutex == NULL || !mutex->is_valid )
         return;
 
     (void) pthread_mutex_destroy( &mutex->mutex );
+    mutex->is_valid = 0;
 }
 
 static int threading_mutex_lock_pthread( mbedtls_threading_mutex_t *mutex )
diff --git a/features/mbedtls/src/version_features.c b/features/mbedtls/src/version_features.c
index 0a2f0657518..e866e67a230 100644
--- a/features/mbedtls/src/version_features.c
+++ b/features/mbedtls/src/version_features.c
@@ -324,9 +324,6 @@ static const char *features[] = {
 #if defined(MBEDTLS_SHA256_SMALLER)
     "MBEDTLS_SHA256_SMALLER",
 #endif /* MBEDTLS_SHA256_SMALLER */
-#if defined(MBEDTLS_SSL_AEAD_RANDOM_IV)
-    "MBEDTLS_SSL_AEAD_RANDOM_IV",
-#endif /* MBEDTLS_SSL_AEAD_RANDOM_IV */
 #if defined(MBEDTLS_SSL_ALL_ALERT_MESSAGES)
     "MBEDTLS_SSL_ALL_ALERT_MESSAGES",
 #endif /* MBEDTLS_SSL_ALL_ALERT_MESSAGES */
diff --git a/features/mbedtls/src/x509.c b/features/mbedtls/src/x509.c
index bc3bfe018f5..fad390d8577 100644
--- a/features/mbedtls/src/x509.c
+++ b/features/mbedtls/src/x509.c
@@ -80,6 +80,7 @@
 #endif
 
 #define CHECK(code) if( ( ret = code ) != 0 ){ return( ret ); }
+#define CHECK_RANGE(min, max, val) if( val < min || val > max ){ return( ret ); }
 
 /*
  *  CertificateSerialNumber  ::=  INTEGER
@@ -489,6 +490,33 @@ static int x509_parse_int(unsigned char **p, unsigned n, int *res){
     return 0;
 }
 
+static int x509_date_is_valid(const mbedtls_x509_time *time)
+{
+    int ret = MBEDTLS_ERR_X509_INVALID_DATE;
+
+    CHECK_RANGE( 0, 9999, time->year );
+    CHECK_RANGE( 0, 23,   time->hour );
+    CHECK_RANGE( 0, 59,   time->min  );
+    CHECK_RANGE( 0, 59,   time->sec  );
+
+    switch( time->mon )
+    {
+        case 1: case 3: case 5: case 7: case 8: case 10: case 12:
+            CHECK_RANGE( 1, 31, time->day );
+            break;
+        case 4: case 6: case 9: case 11:
+            CHECK_RANGE( 1, 30, time->day );
+            break;
+        case 2:
+            CHECK_RANGE( 1, 28 + (time->year % 4 == 0), time->day );
+            break;
+        default:
+            return( ret );
+    }
+
+    return( 0 );
+}
+
 /*
  *  Time ::= CHOICE {
  *       utcTime        UTCTime,
@@ -528,6 +556,8 @@ int mbedtls_x509_get_time( unsigned char **p, const unsigned char *end,
         time->year +=  100 * ( time->year < 50 );
         time->year += 1900;
 
+        CHECK( x509_date_is_valid( time ) );
+
         return( 0 );
     }
     else if( tag == MBEDTLS_ASN1_GENERALIZED_TIME )
@@ -548,6 +578,8 @@ int mbedtls_x509_get_time( unsigned char **p, const unsigned char *end,
         if( len > 14 && *(*p)++ != 'Z' )
             return( MBEDTLS_ERR_X509_INVALID_DATE );
 
+        CHECK( x509_date_is_valid( time ) );
+
         return( 0 );
     }
     else
@@ -559,16 +591,18 @@ int mbedtls_x509_get_sig( unsigned char **p, const unsigned char *end, mbedtls_x
 {
     int ret;
     size_t len;
+    int tag_type;
 
     if( ( end - *p ) < 1 )
         return( MBEDTLS_ERR_X509_INVALID_SIGNATURE +
                 MBEDTLS_ERR_ASN1_OUT_OF_DATA );
 
-    sig->tag = **p;
+    tag_type = **p;
 
     if( ( ret = mbedtls_asn1_get_bitstring_null( p, end, &len ) ) != 0 )
         return( MBEDTLS_ERR_X509_INVALID_SIGNATURE + ret );
 
+    sig->tag = tag_type;
     sig->len = len;
     sig->p = *p;
 
diff --git a/features/mbedtls/src/x509write_crt.c b/features/mbedtls/src/x509write_crt.c
index 9041d440ff1..d1d9a22a7ee 100644
--- a/features/mbedtls/src/x509write_crt.c
+++ b/features/mbedtls/src/x509write_crt.c
@@ -413,6 +413,9 @@ int mbedtls_x509write_crt_der( mbedtls_x509write_cert *ctx, unsigned char *buf,
     MBEDTLS_ASN1_CHK_ADD( sig_and_oid_len, mbedtls_x509_write_sig( &c2, buf,
                                         sig_oid, sig_oid_len, sig, sig_len ) );
 
+    if( len > (size_t)( c2 - buf ) )
+        return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL );
+
     c2 -= len;
     memcpy( c2, c, len );
 
diff --git a/features/mbedtls/src/x509write_csr.c b/features/mbedtls/src/x509write_csr.c
index 0b9a2851e0a..8fd856b2a28 100644
--- a/features/mbedtls/src/x509write_csr.c
+++ b/features/mbedtls/src/x509write_csr.c
@@ -213,6 +213,9 @@ int mbedtls_x509write_csr_der( mbedtls_x509write_csr *ctx, unsigned char *buf, s
     MBEDTLS_ASN1_CHK_ADD( sig_and_oid_len, mbedtls_x509_write_sig( &c2, buf,
                                         sig_oid, sig_oid_len, sig, sig_len ) );
 
+    if( len > (size_t)( c2 - buf ) )
+        return( MBEDTLS_ERR_ASN1_BUF_TOO_SMALL );
+
     c2 -= len;
     memcpy( c2, c, len );
 

From c869d015749591484e2974f003e498d0d8ecb17d Mon Sep 17 00:00:00 2001
From: "andreas.larsson" <andreas.larsson@connectblue.com>
Date: Fri, 7 Oct 2016 04:47:27 +0200
Subject: [PATCH 86/89] Added u-blox ODIN-W2 drivers for all toolchains

---
 .../TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE      |   2 +
 .../LICENSE-permissive-binary-license-1.0.txt |  49 ++
 .../sdk/TOOLCHAIN_ARM/ublox-odin-w2-driver.ar | Bin 0 -> 3774356 bytes
 .../libublox-odin-w2-driver.a                 | Bin 0 -> 1863404 bytes
 .../sdk/TOOLCHAIN_IAR/ublox-odin-w2-driver.a  | Bin 0 -> 4064460 bytes
 .../sdk/odin_w2_mbedtls_config.h              |  10 +
 .../ublox-odin-w2-drivers/OdinWiFiInterface.h | 218 +++++
 .../sdk/ublox-odin-w2-drivers/bt_types.h      | 204 +++++
 .../sdk/ublox-odin-w2-drivers/cb_assert.h     |  94 ++
 .../ublox-odin-w2-drivers/cb_bt_conn_man.h    | 826 ++++++++++++++++++
 .../sdk/ublox-odin-w2-drivers/cb_bt_man.h     | 625 +++++++++++++
 .../sdk/ublox-odin-w2-drivers/cb_bt_pan.h     | 142 +++
 .../sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h | 378 ++++++++
 .../sdk/ublox-odin-w2-drivers/cb_bt_serial.h  | 155 ++++
 .../ublox-odin-w2-drivers/cb_bt_serial_le.h   | 153 ++++
 .../ublox-odin-w2-drivers/cb_bt_test_man.h    | 253 ++++++
 .../sdk/ublox-odin-w2-drivers/cb_bt_utils.h   |  86 ++
 .../sdk/ublox-odin-w2-drivers/cb_comdefs.h    | 178 ++++
 .../sdk/ublox-odin-w2-drivers/cb_gatt.h       | 504 +++++++++++
 .../ublox-odin-w2-drivers/cb_gatt_client.h    | 652 ++++++++++++++
 .../ublox-odin-w2-drivers/cb_gatt_server.h    | 329 +++++++
 .../sdk/ublox-odin-w2-drivers/cb_gatt_utils.h | 104 +++
 .../sdk/ublox-odin-w2-drivers/cb_hw.h         | 146 ++++
 .../sdk/ublox-odin-w2-drivers/cb_main.h       | 131 +++
 .../sdk/ublox-odin-w2-drivers/cb_otp.h        |  68 ++
 .../cb_platform_basic_types.h                 | 130 +++
 .../sdk/ublox-odin-w2-drivers/cb_port_types.h |  35 +
 .../sdk/ublox-odin-w2-drivers/cb_status.h     |  44 +
 .../sdk/ublox-odin-w2-drivers/cb_types.h      | 287 ++++++
 .../sdk/ublox-odin-w2-drivers/cb_watchdog.h   |  71 ++
 .../sdk/ublox-odin-w2-drivers/cb_wlan.h       | 567 ++++++++++++
 .../cb_wlan_target_data.h                     | 119 +++
 .../sdk/ublox-odin-w2-drivers/cb_wlan_types.h | 552 ++++++++++++
 .../sdk/wifi_emac/wifi_emac_api.cpp           | 327 +++++++
 .../sdk/wifi_emac/wifi_emac_api.h             |  10 +
 targets/targets.json                          |   4 +-
 36 files changed, 7451 insertions(+), 2 deletions(-)
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/ublox-odin-w2-driver.ar
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/ublox-odin-w2-driver.a
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/odin_w2_mbedtls_config.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp
 create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h

diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE
new file mode 100644
index 00000000000..a8161761a33
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE
@@ -0,0 +1,2 @@
+Unless specifically indicated otherwise in a file, files are licensed under the
+Permissive Binary License1.0 (PBL-1.0) as can be found in: LICENSE-permissive-binary-license-1.0.txt
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt
new file mode 100644
index 00000000000..d648fd563a7
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt
@@ -0,0 +1,49 @@
+Permissive Binary License
+
+Version 1.0, September 2015
+
+Redistribution.  Redistribution and use in binary form, without
+modification, are permitted provided that the following conditions are
+met:
+
+1) Redistributions must reproduce the above copyright notice and the
+   following disclaimer in the documentation and/or other materials
+   provided with the distribution.
+
+2) Unless to the extent explicitly permitted by law, no reverse
+   engineering, decompilation, or disassembly of this software is
+   permitted.
+
+3) Redistribution as part of a software development kit must include the
+   accompanying file named “DEPENDENCIES” and any dependencies listed in
+   that file.
+
+4) Neither the name of the copyright holder nor the names of its
+   contributors may be used to endorse or promote products derived from
+   this software without specific prior written permission.
+
+Limited patent license. The copyright holders (and contributors) grant a
+worldwide, non-exclusive, no-charge, royalty-free patent license to
+make, have made, use, offer to sell, sell, import, and otherwise
+transfer this software, where such license applies only to those patent
+claims licensable by the copyright holders (and contributors) that are
+necessarily infringed by this software. This patent license shall not
+apply to any combinations that include this software.  No hardware is
+licensed hereunder.
+
+If you institute patent litigation against any entity (including a
+cross-claim or counterclaim in a lawsuit) alleging that the software
+itself infringes your patent(s), then your rights granted under this
+license shall terminate as of the date such litigation is filed.
+
+DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
+NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/ublox-odin-w2-driver.ar b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/ublox-odin-w2-driver.ar
new file mode 100644
index 0000000000000000000000000000000000000000..296ec9f0c137baac0fa26f70f419a459a285e20e
GIT binary patch
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diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a
new file mode 100644
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diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/ublox-odin-w2-driver.a b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/ublox-odin-w2-driver.a
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diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/odin_w2_mbedtls_config.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/odin_w2_mbedtls_config.h
new file mode 100644
index 00000000000..926f23b304f
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/odin_w2_mbedtls_config.h
@@ -0,0 +1,10 @@
+#ifndef _ODIN_W2_MBEDTLS_CONFIG_H_
+#define _ODIN_W2_MBEDTLS_CONFIG_H_
+
+#define MBEDTLS_ARC4_C
+#define MBEDTLS_DES_C
+#define MBEDTLS_MD4_C
+#define MBEDTLS_MD5_C
+#define MBEDTLS_SHA1_C
+
+#endif /* _ODIN_W2_MBEDTLS_CONFIG_H_ */
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h
new file mode 100644
index 00000000000..091609c402b
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h
@@ -0,0 +1,218 @@
+/* ODIN-W2 implementation of WiFiInterface
+ * Copyright (c) 2016 u-blox Malm� AB
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ODIN_WIFI_INTERFACE_H
+#define ODIN_WIFI_INTERFACE_H
+
+#include "WiFiInterface.h"
+#include "Callback.h"
+#include "mbed_events.h"
+
+#include "rtos.h"
+#include "emac_api.h"
+#include "nsapi_types.h"
+#include "lwip/netif.h"
+
+typedef Queue<void*, 1> MsgQueue;
+
+class OdinWiFiInterface;
+
+struct PrivContext;
+
+/** OdinWiFiInterface class
+ *  Implementation of the WiFiInterface for the ODIN-W2 module
+ */
+class OdinWiFiInterface : public WiFiInterface
+{
+public:
+    /** OdinWiFiInterface lifetime
+     */
+    OdinWiFiInterface();
+    
+    OdinWiFiInterface(bool debug);
+
+    ~OdinWiFiInterface();
+    
+    /** Set the WiFi network credentials
+     *
+     *  @param ssid      Name of the network to connect to
+     *  @param pass      Security passphrase to connect to the network
+     *  @param security  Type of encryption for connection
+     *                   (defaults to NSAPI_SECURITY_NONE)
+     *  @return          0 on success, or error code on failure
+     */
+    virtual int set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE);
+    
+    /** Set the WiFi network channel
+     *
+     *  @param channel   Channel on which the connection is to be made, or 0 for any (Default: 0)
+     *  @return          0 on success, or error code on failure
+     */
+    virtual int set_channel(uint8_t channel);
+    
+    /** Start the interface
+     *
+     *  Attempts to connect to a WiFi network.
+     *
+     *  @param ssid      Name of the network to connect to
+     *  @param pass      Security passphrase to connect to the network
+     *  @param security  Type of encryption for connection (Default: NSAPI_SECURITY_NONE)
+     *  @param channel   Channel on which the connection is to be made, or 0 for any (Default: 0)
+     *  @return          0 on success, or error code on failure
+     */
+    virtual int connect(const char *ssid,
+        const char *pass,
+        nsapi_security_t security = NSAPI_SECURITY_NONE,
+        uint8_t channel = 0);
+
+    /** Start the interface
+     *
+     *  Attempts to connect to a WiFi network. Requires ssid and passphrase to be set.
+     *  If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned.
+     *
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int connect();
+
+    /** Stop the interface
+     *
+     *  @return         0 on success, or error code on failure
+     */
+    virtual int disconnect();
+
+    /** Get the local MAC address
+     *
+     *  Provided MAC address is intended for info or debug purposes and
+     *  may not be provided if the underlying network interface does not
+     *  provide a MAC address
+     *  
+     *  @return         Null-terminated representation of the local MAC address
+     *                  or null if no MAC address is available
+     */
+    virtual const char *get_mac_address();
+
+    /** Get the local IP address
+     *
+     *  @return         Null-terminated representation of the local IP address
+     *                  or null if no IP address has been recieved
+     */
+    virtual const char *get_ip_address();
+
+    /** Get the local network mask
+     *
+     *  @return         Null-terminated representation of the local network mask 
+     *                  or null if no network mask has been recieved
+     */
+    virtual const char *get_netmask();
+
+    /** Get the local gateway
+     *
+     *  @return         Null-terminated representation of the local gateway
+     *                  or null if no network mask has been recieved
+     */
+    virtual const char *get_gateway();
+
+    /** Set a static IP address
+     *
+     *  Configures this network interface to use a static IP address.
+     *  Implicitly disables DHCP, which can be enabled in set_dhcp.
+     *  Requires that the network is disconnected.
+     *
+     *  @param address  Null-terminated representation of the local IP address
+     *  @param netmask  Null-terminated representation of the local network mask
+     *  @param gateway  Null-terminated representation of the local gateway
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int set_network(const char *ip_address, const char *netmask, const char *gateway);
+
+    /** Enable or disable DHCP on the network
+     *
+     *  Enables DHCP on connecting the network. Defaults to enabled unless
+     *  a static IP address has been assigned. Requires that the network is
+     *  disconnected.
+     *
+     *  @param dhcp     True to enable DHCP
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int set_dhcp(bool dhcp);
+    
+    /** Gets the current radio signal strength for active connection
+     *
+     *  @return         Connection strength in dBm (negative value),
+     *                  or 0 if measurement impossible
+     */
+    virtual int8_t get_rssi();
+
+    /** Scan for available networks
+     *
+     *  If the network interface is set to non-blocking mode, scan will attempt to scan
+     *  for WiFi networks asynchronously and return NSAPI_ERROR_WOULD_BLOCK. If a callback
+     *  is attached, the callback will be called when the operation has completed.
+     *
+     * @param  ap       Pointer to allocated array to store discovered AP
+     * @param  count    Size of allocated @a res array, or 0 to only count available AP
+     * @param  timeout  Timeout in milliseconds; 0 for no timeout (Default: 0)
+     * @return          Number of entries in @a, or if @a count was 0 number of available networks, negative on error
+     *                  see @a nsapi_error
+     */
+    virtual int scan(WiFiAccessPoint *res, unsigned count);
+
+    /** Sets timeout for connection setup. Note that the time for DHCP retrieval is not included.
+     *
+     *  @param timeout  Timeout in ms. Use 0 for waiting forever. The timeout might take up to X sec longer than
+     *                  specified since the Wi-Fi driver might need some time to finish and cleanup.
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual void set_timeout(int timeout);
+
+    virtual NetworkStack *get_stack();
+
+protected:
+
+private:
+    
+    int connect_async(const char *ssid,
+        const char *pass,
+        nsapi_security_t security = NSAPI_SECURITY_NONE,
+        uint8_t channel = 0,
+        void *data = NULL,
+        unsigned timeout = 0);
+    
+    bool start(bool debug);
+    bool stop();
+    
+    char _mac_addr_str[18];
+    // Private context to share between C and C++ calls
+    PrivContext* _priv_context;
+    const char *_ssid;
+    const char *_pass;
+    char _ip_address[IPADDR_STRLEN_MAX];
+    char _netmask[IPADDR_STRLEN_MAX];
+    char _gateway[IPADDR_STRLEN_MAX];
+    nsapi_security_t _security;
+    uint8_t _channel;
+    bool _use_dhcp;
+    int _timeout;
+    // Event queue when the driver context need to be used
+    EventQueue* _odin_event_queue;
+    int32_t target_id;
+    // Event queue for sending start up and connection events from driver to this class
+    MsgQueue _event_queue;
+    // Event queue for sending scan events from driver to this class
+    MsgQueue _scan_event_queue;    
+};
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h
new file mode 100644
index 00000000000..9a8b73ae367
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h
@@ -0,0 +1,204 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : 
+ * File        : bt_types.h
+ *
+ * Description : Common Bluetooth types
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file bt_types.h
+ * @brief Common Bluetooth types
+ */
+
+#ifndef _BT_TYPES_H_
+#define _BT_TYPES_H_
+
+#include "cb_comdefs.h"
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+#define SIZE_OF_BD_ADDR                               (6)
+#define SIZE_OF_COD                                   (3)
+#define SIZE_OF_LINK_KEY                              (16)
+#define SIZE_OF_NAME                                  (248)
+#define SIZE_OF_PIN_CODE                              ((cb_uint8)16)
+#define SIZE_OF_LAP                                   (3)
+#define SIZE_OF_AFH_LMP_HCI_CHANNEL_MAP               (10)
+#define CHANNEL_MAP_SIZE                              (5)
+#define SIZE_OF_EXT_INQ_RSP                           (240)
+#define MIN_PASSKEY_VALUE                             (0)
+#define MAX_PASSKEY_VALUE                             (999999)
+#define INVALID_CONN_HANDLE                           ((TConnHandle)0xFFFF)
+#define MAX_ADV_DATA_LENGTH                           (31)
+#define UUID_LENGTH                                   (16)
+
+
+#define PACKET_TYPE_DM1                                                 (0x0008)
+#define PACKET_TYPE_DH1                                                 (0x0010)
+#define PACKET_TYPE_DM3                                                 (0x0400)
+#define PACKET_TYPE_DH3                                                 (0x0800)
+#define PACKET_TYPE_DM5                                                 (0x4000)
+#define PACKET_TYPE_DH5                                                 (0x8000)
+
+#define PACKET_TYPE_NO_2_DH1                                            (0x0002)
+#define PACKET_TYPE_NO_3_DH1                                            (0x0004)
+#define PACKET_TYPE_NO_2_DH3                                            (0x0100)
+#define PACKET_TYPE_NO_3_DH3                                            (0x0200)
+#define PACKET_TYPE_NO_2_DH5                                            (0x1000)
+#define PACKET_TYPE_NO_3_DH5                                            (0x2000)
+
+#define PACKET_TYPE_ALL (PACKET_TYPE_DM1 | PACKET_TYPE_DH1 | PACKET_TYPE_DM3 | PACKET_TYPE_DH3 | PACKET_TYPE_DM5 | PACKET_TYPE_DH5)
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+typedef cb_int32        int32;
+typedef cb_uint32       uint32;
+typedef cb_boolean      boolean;
+typedef cb_int8         int8;
+typedef cb_uint8        uint8;
+typedef cb_int16        int16;
+typedef cb_uint16       uint16;
+
+typedef cb_uint8       TErrorCode;
+typedef cb_uint8       TLinkType;
+typedef cb_uint16      TPacketType;
+typedef cb_uint16      TConnHandle;
+
+typedef enum
+{
+  BT_SECURITY_MODE_1 = 1,
+  BT_SECURITY_MODE_2,
+  BT_SECURITY_MODE_3,
+  BT_SECURITY_MODE_4
+
+} TSecurityMode;
+
+typedef enum
+{
+  BT_SECURITY_LEVEL_0 = 0,
+  BT_SECURITY_LEVEL_1,
+  BT_SECURITY_LEVEL_2,
+  BT_SECURITY_LEVEL_3,
+  // Used with security modes 1,2,3 where security level is not applicable
+  BT_SECURITY_LEVEL_DUMMY = 5,
+
+} TSecurityLevel;
+
+
+typedef enum 
+{
+  BT_MASTER_SLAVE_POLICY_ALWAYS_MASTER     = 0,
+  BT_MASTER_SLAVE_POLICY_OTHER_SIDE_DECIDE = 1
+
+} TMasterSlavePolicy;
+
+typedef enum 
+{
+    BT_TYPE_CLASSIC    = 0,
+    BT_TYPE_LOW_ENERGY = 1
+
+} TBluetoothType;
+
+typedef enum
+{
+    BT_PUBLIC_ADDRESS = 0x00,
+    BT_RANDOM_ADDRESS = 0x01,
+
+} TAddressType;
+
+typedef struct
+{
+  cb_uint8      BdAddress[SIZE_OF_BD_ADDR];
+  TAddressType  AddrType;
+
+} TBdAddr;
+
+typedef struct
+{
+  cb_uint8 Cod[SIZE_OF_COD];
+
+} TCod;
+
+typedef struct
+{
+  cb_uint8 LinkKey[SIZE_OF_LINK_KEY];
+
+} TLinkKey;
+
+typedef struct
+{
+  cb_uint8 Name[SIZE_OF_NAME];
+
+} TName;
+
+typedef struct
+{
+  cb_uint8 PinCode[SIZE_OF_PIN_CODE];
+
+} TPinCode;
+
+typedef cb_uint32 TPasskey;
+
+typedef struct
+{
+  cb_uint8 Lap[SIZE_OF_LAP];
+
+} TLap;
+
+typedef struct
+{
+  cb_uint8 Data[SIZE_OF_EXT_INQ_RSP];
+
+} TExtInqRsp;
+
+typedef cb_uint8 TAfhLmpHciChannelMap[SIZE_OF_AFH_LMP_HCI_CHANNEL_MAP];
+
+typedef struct
+{
+    uint16 channel[CHANNEL_MAP_SIZE];
+} TChannelMap;
+
+
+typedef enum
+{
+    BT_ADV_TYPE_ADV  = 0x01,
+    BT_ADV_TYPE_SCAN = 0x00,
+} TAdvDataType;
+
+typedef struct 
+{
+    TAdvDataType type;
+    cb_uint8 length;
+    cb_uint8 data[MAX_ADV_DATA_LENGTH];
+} TAdvData;
+
+typedef struct
+{
+    cb_uint16 createConnectionTimeout;
+    cb_uint16 connectionIntervalMin;
+    cb_uint16 connectionIntervalMax;
+    cb_uint16 connectionLatency;
+    cb_uint16 linkLossTimeout;
+    cb_uint16  scanInterval;
+    cb_uint16  scanWindow;
+} TAclParamsLe;
+
+#endif /* _BT_TYPES_H */
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h
new file mode 100644
index 00000000000..249036572d7
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h
@@ -0,0 +1,94 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : Assert
+ * File        : cb_assert.h
+ *
+ * Description : ASSERT macro variations.
+ *-------------------------------------------------------------------------*/
+
+#ifndef _CB_ASSERT_H_
+#define _CB_ASSERT_H_
+
+#include "cb_comdefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+/*
+ * Internal platform function declaration.
+ * Shall never be called directly.
+ */
+
+extern void cbOS_error(cb_int32 errorCode, const cb_char *file, cb_uint32 line);
+extern void cbOS_error2(const cb_char *file, cb_uint32 line);
+
+#ifndef NASSERT
+
+#ifndef __CB_FILE__
+    #define __CB_FILE__ __FILE__
+#endif
+
+/*
+ * If the condition (C) evaluates to FALSE, the registered error handler in cbOS
+ * is called with file and line info before the system is reset.
+ */
+
+#define cb_ASSERT(C)    do { if(!(C)){cbOS_error2(__CB_FILE__,__LINE__);} } while(0)
+
+#define cb_ASSERTC(C)   do { if(!(C)){cbOS_error2(__CB_FILE__ , __LINE__);} } while(0)
+
+#define cb_ASSERT2(C, E) do { if(!(C)){cbOS_error(E, __CB_FILE__ , __LINE__);} } while(0)
+
+/*
+ * The registered error handler is called with the file and line info before a system reset.
+ */
+
+#define cb_EXIT(E) do { cbOS_error(((cb_int32)(E)), __CB_FILE__, __LINE__); } while(0)
+
+
+#else
+
+#define cb_ASSERT(C)
+
+#define cb_ASSERTC(C) do {  if(!(C)){cbWD_systemReset();} } while(0) // Critical assert is never removed.
+
+#define cb_ASSERT2(C, E)
+
+#define cb_EXIT(E) do { cbWD_systemReset(); } while(0)
+
+#endif
+
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _cb_ASSERT_H_ */
+
+
+
+
+
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h
new file mode 100644
index 00000000000..4fe40ca6956
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h
@@ -0,0 +1,826 @@
+/**
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : Bluetooth Connection Manager
+ * File        : cb_bt_conn_man.h
+ *
+ * Description : Bluetooth Connection Management
+ *
+ *-------------------------------------------------------------------------*/
+
+/**
+* @file cb_bt_conn_man.h
+* @brief Connection management. Functionality for setting up and tearing 
+* down Bluetooth connections. Profile services are also enabled
+* using this module.
+ */
+
+#ifndef _CB_BT_CONN_MAN_H_
+#define _CB_BT_CONN_MAN_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+#define cbBCM_OK                         (0)
+#define cbBCM_ERROR                      (-1)
+#define cbBCM_ILLEGAL_HANDLE             (-2)
+#define cbBCM_NOT_IMPLEMENTED            (-3)
+#define cbBCM_ERROR_DISCONNECTING        (-4)
+#define cbBCM_ERROR_ALREADY_REGISTERED   (-5)
+#define cbBCM_ERROR_ALREADY_CONNECTED    (-6)
+
+#define cbBCM_ACL_CONNECTION_FAILED      (-7)
+#define cbBCM_SERVICE_SEARCH_FAILED      (-8)
+#define cbBCM_RFCOMM_CONNECTION_FAILED   (-9)
+#define cbBCM_SPS_CONNECTION_FAILED      (-10)
+#define cbBCM_ACL_DISCONNECTED           (-11)
+
+#define cbBCM_INVALID_CONNECTION_HANDLE  (cb_UINT32_MAX)
+#define cbBCM_INVALID_SERVER_CHANNEL     (cb_UINT8_MAX)
+#define cbBCM_SERVICE_NAME_MAX_LEN       (32)
+
+#define cbBCM_DEV_ID_VENDOR_ID_SRC_BLUETOOTH    (0x0001)
+#define cbBCM_DEV_ID_VENDOR_ID_SRC_USB          (0x0002)
+#define cbBCM_CONNECTBLUE_VENDOR_ID             (0x0071)
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+typedef cb_uint32 cbBCM_Handle;
+
+typedef enum 
+{
+    cbBCM_INVALID_CONNECTION = 0,
+    cbBCM_SPP_CONNECTION,           // Serial Port Profile
+    cbBCM_DUN_CONNECTION,           // Dial Up Networking Profile
+    cbBCM_UUID_CONNECTION,          // UUID
+    cbBCM_PAN_CONNECTION,           // PAN
+
+    cbBCM_ACL_LE_CONNECTION,        // GATT
+    cbBCM_SPS_CONNECTION            // LE connectBlue Serial Service connection
+}cbBCM_ConnectionType;
+
+typedef enum
+{
+    cbBM_LINK_QUALITY_READY_OK,
+    cbBM_LINK_QUALITY_READY_ERROR
+} cbBCM_LinkQualityEvt;
+
+/**
+ * Bluetooth Classic Acl connection parameters
+ */
+typedef struct 
+{
+    cb_uint16           pageTimeout;            /** Length of connection attempt. Default value 5000ms. */
+    cb_uint16           packetType;             /** Packet types allowed in the connection. By default all packets but 3MBit EDR are allowed. */
+    TMasterSlavePolicy  masterSlavePolicy;      /** Whether master slave switch shall be allowed or not. By default master slave switch is allowed. */
+    cb_uint16           clockOffset;            /** Clock offset is part in inquiry response. Using this value may result in faster connection setup  Default value 0. */
+    cb_uint16           linkSupervisionTimeout; /** Link supervision timeout. Default value 2000ms. */
+} cbBCM_ConnectionParameters;
+
+/**
+ * Bluetooth Low Energy Acl connection parameters
+ */
+typedef struct 
+{
+    cb_uint32 createConnectionTimeout;      /** Length of connection attempt in ms. Default value 5000ms. */
+    cb_uint16 connectionIntervalMin;        /** Minimum connection interval in ms. Default value 6ms. */
+    cb_uint16 connectionIntervalMax;        /** Maximum connection interval in ms. Default value 8ms. */
+    cb_uint16 connectionLatency;            /** Slave latency. Default value 0. */
+    cb_uint16 linkLossTimeout;              /** Link loss timeout in ms. Default 2000ms. */
+} cbBCM_ConnectionParametersLe;
+
+typedef enum
+{
+    cbBCM_PAN_ROLE_PANU = 0,
+    cbBCM_PAN_ROLE_NAP,
+    cbBCM_PAN_ROLE_NONE
+}cbBCM_PAN_Role;
+
+typedef struct
+{
+    TBdAddr                 address;
+    cbBCM_ConnectionType    type;
+    TConnHandle             aclHandle;
+    TBluetoothType          btType;
+    cb_uint8                serverChannel;
+    cb_uint8                uuid[16] ;
+    cb_boolean              uuidValid;
+    cb_char                 serviceName[cbBCM_SERVICE_NAME_MAX_LEN];
+} cbBCM_ConnectionInfo;
+
+typedef void (*cbBCM_ConnectInd)(
+    cbBCM_Handle handle,
+    cbBCM_ConnectionInfo info);
+
+typedef void (*cbBCM_ConnectEvt)(
+    cbBCM_Handle handle,
+    cbBCM_ConnectionInfo info);
+
+typedef void (*cbBCM_ConnectCnf)(
+    cbBCM_Handle handle,
+    cbBCM_ConnectionInfo info,
+    cb_int32 status);
+
+typedef void (*cbBCM_DisconnectEvt)(
+    cbBCM_Handle handle);
+
+typedef struct
+{
+    cbBCM_ConnectInd         pfConnectInd;
+    cbBCM_ConnectEvt         pfConnectEvt;
+    cbBCM_ConnectCnf         pfConnectCnf;
+    cbBCM_DisconnectEvt      pfDisconnectEvt;
+} cbBCM_ConnectionCallback;
+
+typedef void(*cbBCM_RoleDiscoveryCallback)(
+    cbBCM_Handle handle,
+    cb_int8 status,
+    cb_int8 role);
+
+typedef void (*cbBCM_RssiCallback)(
+    cbBCM_Handle handle,
+    cb_int32 status,
+    cb_int8 rssi);
+
+typedef void (*cbBCM_DataEvt)(
+    cbBCM_Handle handle,
+    cb_uint8 *pBuf,
+    cb_uint32 nBytes);
+
+typedef void (*cbBCM_WriteCnf)(
+    cbBCM_Handle handle,
+    cb_int32 status);
+
+/**
+ * Set max number of Bluetooth links.
+ * Not used by application 
+ * @return status TRUE if command was successful
+ */
+typedef cb_int32 (*cbBCM_SetMaxLinksCmd)(cb_uint32 maxLinks);
+
+/**
+ * Check if Handle is free to use 
+ * @return TRUE if handle is free, FALSE otherwise
+ */
+typedef cb_boolean (*cbBCM_IsHandleFree)(cbBCM_Handle handle);
+/**
+ * Callback to indicate that remaining buffer size needs to be obtained from 
+ * upper layer. The callback returns remaining buffer size and there is 
+ * therefore no response function.
+ * Not used by application 
+ * @return Number of free bytes in channel data buffer
+ */
+typedef cb_uint16 (*cbBCM_RemainBufSizeInd)(void);
+
+typedef struct
+{
+    cbBCM_ConnectEvt         pfConnectEvt;
+    cbBCM_DisconnectEvt      pfDisconnectEvt;
+    cbBCM_DataEvt            pfDataEvt;
+    cbBCM_WriteCnf           pfWriteCnf;
+    cbBCM_SetMaxLinksCmd     pfSetMaxLinks;
+    cbBCM_RemainBufSizeInd   pfRemainBufSizeInd;
+    cbBCM_IsHandleFree       pfIsHandleFree;
+} cbBCM_DataCallback;
+
+typedef void (*cbBCM_ServiceSearchCompleteCallback)(cb_int32 status);
+
+typedef void (*cbBCM_ServiceSearchSppCallback)(
+    cb_uint8 serverChannel,
+    cb_char *pServiceName);
+
+typedef void (*cbBCM_ServiceSearchDunCallback)(
+    cb_uint8 serverChannel,
+    cb_char *pServiceName);
+
+typedef void (*cbBCM_ServiceSearchDeviceIdCallback)(
+    cb_uint16 didSpecVersion,
+    cb_uint16 didVendorId,
+    cb_uint16 didProductId,
+    cb_uint16 didProductVersion,
+    cb_boolean didPrimaryService,
+    cb_uint16 didVendorIdSource);
+
+typedef void(*cbBCM_LinkQualityCallback)(
+    cbBCM_LinkQualityEvt linkQualityEvt,
+    uint8               linkQuality);
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+/**
+ * Initialization of connection manager. Called during stack
+ * initialization. Shall not be called by application.
+ * 
+ * @return None
+ */
+extern void cbBCM_init(void);
+
+/**
+ * Enable a Bluetooth Serial Port Profile (SPP)service record to 
+ * allow other devices to connect to this device using SPP.
+ * 
+ * @param   pServiceName The name of the service
+ * @param   pServerChannel Pointer to return variable. The server channel is used to identify 
+ *          incoming connections.
+ * @param   pConnectionCallback Callback structure for connection management.
+ * @return  If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_enableServerProfileSpp(
+    cb_char *pServiceName,
+    cb_uint8 *pServerChannel,
+    cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Enable a Dial Up Networking Profile (DUN)service record to 
+ * allow other devices to connect to this device using DUN.
+ * 
+ * @param   pServiceName The name of the service
+ * @param   pServerChannel Pointer to return variable. The server channel is used to identify 
+ *          incoming connections.
+ * @param   pConnectionCallback Callback structure for connection management.
+ * @return  If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_enableServerProfileDun(
+    cb_char *pServiceName,
+    cb_uint8 *pServerChannel,
+    cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Enable a service record with an application specific UUID.
+ * This is used to enable Android and iOS support.
+ * 
+ * @param   pUuid128 The UUID of the service.
+ * @param   pServiceName The name of the service
+ * @param   pServerChannel Pointer to return variable. The server channel is used to identify 
+ *          incoming connections.
+ * @param   pConnectionCallback Callback structure for connection management.
+ * @return  If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_enableServerProfileUuid128(
+    cb_uint8 *pUuid128,
+    cb_char *pServiceName,
+    cb_uint8 *pServerChannel,
+    cbBCM_ConnectionCallback *pConnectionCallback);
+
+
+/**
+* Registers the server role of the local device. If role is cbBCM_PAN_ROLE_NAP a service
+* record will be registred in the local service data base. The local device can only act as a
+* PAN NAP or Pan user at a time. If PAN NAP is enabled the device will only accept incoming
+* connections from PAN users. If PAN user is enabled it is only possible to be connected to
+* one remote PAN NAP device.
+*
+* @param   pServiceName        The name of the service
+* @param   role                The PAN role of the local device
+* @param   pConnectionCallback Callback structure for connection management.
+* @return  If the operation is successful cbBCM_OK is returned.
+*/
+extern cb_int32 cbBCM_enableServerProfilePan(
+    cb_char *pServiceName,
+    cbBCM_PAN_Role role,
+    cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Enable device id service record.The device id service record is  a method by which 
+ * Bluetooth devices may provide information that may be used by peer Bluetooth devices 
+ * to find representative icons or load associated support software. 
+ * This information is published as Bluetooth SDP records, and optionally in the 
+ * Extended Inquiry Response. 
+ * @param   vendorId        Uniquely identifier for the vendor of the device. Used in conjunction with required attribute 0x0205, VendorIDSource, which determines which organization assigned the VendorID value. Note: The Bluetooth Special Interest Group assigns Device ID Vendor ID and the USB Implementer's Forum assigns vendor IDs, either of which can be used for the VendorID value here. Device providers should procure the vendor ID from the USB Implementer's Forum or the Company Identifier from the Bluetooth SIG. The VendorID '0xFFFF' is reserved as the default VendorID when no Device ID Service Record is present in the device.
+ * @param   productId       This is intended to distinguish between different products made by the vendor above. These IDs are managed by the vendors themselves.
+ * @param   version         A numeric expression identifying the device release number in Binary-Coded Decimal. This is a vendor-assigned field, which defines the version of the product identified by the VendorID and ProductID attributes. This attribute is intended to differentiate between versions of products with identical VendorIDs and ProductIDs. The value of the field is 0xJJMN for version JJ.M.N (JJ - major version number, M - minor version number, N - sub-minor version number); e.g., version 2.1.3 is represented with value 0x0213 and version 2.0.0 is represented with a value of 0x0200. When upward-compatible changes are made to the device, it is recommended that the minor version number be incremented. If incompatible changes are made to the device, it is recommended that the major version number be incremented.
+ * @param   vendorIdSource  Organization that assigned the VendorID attribute. Use 0x0001 for  Bluetooth SIG assigned Device ID Vendor ID value from the Assigned Numbers document and 0x0002 for USB Implementer's Forum assigned Vendor ID value
+ * @return  If the operation is successful cbBCM_OK is returned. Note that only one device id service record can be registered.
+ */
+extern cb_int32 cbBCM_enableDeviceIdServiceRecord(
+    cb_uint16 vendorId,
+    cb_uint16 productId,
+    cb_uint16 version,
+    cb_uint16 vendorIdSource);
+
+/**
+* Set Bluetooth watchdog settings
+*
+* @param   disconnectReset Reset the device on any dropped Bluetooth connection
+* @return  void
+*/
+extern void cbBCM_setBluetoothWatchdogValue(cb_uint32 disconnectReset);
+
+/**
+* Set the packet types to use. Call cbBCM_cmdChangePacketType()
+* to start using the new packet types.
+*
+* @param  packetType   See packet types in bt_types.h
+* @return  If the operation is successful cbBCM_OK is returned.
+*/
+extern cb_uint32 cbBCM_setPacketType(cb_uint16 packetType);
+
+/**
+* Get BT classic packet type.
+*
+* @return  Allowed packet types returned.
+*/
+extern cb_uint16 cbBCM_getPacketType(void);
+
+/**
+ * Set max number of Bluetooth classic links. Reconfigures buffer management.
+ * 
+ * @param   maxLinks Max number of Bluetooth classic connections.
+ * @return  If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_setMaxLinksClassic(cb_uint16 maxLinks);
+
+/**
+ * Get max number of Bluetooth classic links.
+ * 
+ * @return  The maximum number of Bluetooth classic links.
+ */
+extern cb_uint16 cbBCM_getMaxLinksClassic(void);
+
+/**
+ * Set max number of Bluetooth Low Energy links. Reconfigures buffer management.
+ * 
+ * @param   maxLinks Max number of Bluetooth Low Energy connections.
+ * @return  If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_setMaxLinksLE(cb_uint16 maxLinks);
+
+/**
+ * Get max number of Bluetooth Low Energy links.
+ * 
+ * @return  The maximum number of Bluetooth Low Energy links.
+ */
+extern cb_uint16 cbBCM_getMaxLinksLE(void);
+
+/**
+ * Initiate a Bluetooth Serial Port Profile connection.
+ * The connection sequence includes ACL connection setup, SDP service 
+ * search and RFCOMM connection setup. The server channel of the first 
+ * valid SPP service record will be used. A pfConnectCnf callback will
+ * be received when the connection is complete.The error code in the 
+ * callback is cbBCM_OK if the connection was successfully established.
+ * The error code in the callback is cbBCM_ERROR if the connection failed.
+ * @param   pAddress          Pointer to address of remote device.
+ * @param   pServiceName      Name of SPP service. Automatic service search
+ *                            is performed to find a service with matching name.
+ *                            If set to NULL then the last of the SPP services
+ *                            on the remote device will be used. If serverChannel
+ *                            parameter is different than cbBCM_INVALID_SERVER_CHANNEL
+ *                            this parameter is ignored and the specified server channel 
+ *                            will be used.
+ * @param   serverChannel     RFCOMM server channel that shall be used. Set to
+ *                            cbBCM_INVALID_SERVER_CHANNEL to perform automatic
+ *                            service search to find the server channel.
+ * @param   pAclParameters    Link configuration including link supervision timeout 
+ *                            and master slave policy. Pass NULL to use default connection 
+ *                            parameters.
+ * @param   pConnectionCallback Callback structure for connection management.
+ * @return  If the operation is successful the connection handle is returned. If
+ *          not cbBCM_INVALID_CONNECTION_HANDLE is returned.
+ */
+extern cbBCM_Handle cbBCM_reqConnectSpp(
+    TBdAddr *pAddress,
+    cb_char *pServiceName,
+    cb_uint8 serverChannel,
+    cbBCM_ConnectionParameters *pAclParameters,
+    cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Accept or reject an incoming SPP connection. This is a 
+ * response to a cbBCM_ConnectInd connection indication.
+ *
+ * @param handle    Connection handle
+ * @param accept    TRUE to accept the incoming connection. 
+                    FALSE to reject.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_rspConnectSppCnf(
+    cbBCM_Handle handle,
+    cb_boolean accept);
+
+/**
+ * Initiate a Bluetooth Dial Up Networking Profile connection.
+ * The connection sequence includes ACL connection setup, SDP service 
+ * search and RFCOMM connection setup. The server channel of the first 
+ * valid SPP service record will be used. A pfConnectCnf callback will
+ * be received when the connection is complete.The error code in the 
+ * callback is cbBCM_OK if the connection was successfully established.
+ * The error code in the callback is cbBCM_ERROR if the connection failed.
+ * @param   pAddress          Pointer to address of remote device.
+ * @param   pServiceName      Name of DUN service. Automatic service search
+ *                            is performed to find a service with matching name.
+ *                            If set to NULL then the last of the DUN services
+ *                            on the remote device will be used. If serverChannel
+ *                            parameter is different than cbBCM_INVALID_SERVER_CHANNEL
+ *                            this parameter is ignored and the specified server channel 
+ *                            will be used.
+ * @param   serverChannel     RFCOMM server channel that shall be used. Set to
+ *                            cbBCM_INVALID_SERVER_CHANNEL to perform automatic
+ *                            service search to find the server channel.
+ * @param   pAclParameters    Link configuration including link supervision timeout 
+ *                            and master slave policy. Pass NULL to use default connection 
+ *                            parameters.
+ * @param   pConnectionCallback Callback structure for connection management.
+ * @return  If the operation is successful the connection handle is returned. If
+ *          not cbBCM_INVALID_CONNECTION_HANDLE is returned.
+ */
+extern cbBCM_Handle cbBCM_reqConnectDun(
+    TBdAddr *pAddress,
+    cb_char *pServiceName,
+    cb_uint8 serverChannel,
+    cbBCM_ConnectionParameters *pAclParameters,
+    cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Accept or reject an incoming DUN connection. This is a 
+ * response to a cbBCM_ConnectInd connection indication.
+ *
+ * @param   handle  Connection handle 
+ * @param accept    TRUE to accept the incoming connection. 
+                    FALSE to reject.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_rspConnectDunCnf(
+    cbBCM_Handle handle,
+    cb_boolean accept);
+
+/**
+ * Initiate a Bluetooth Serial Port Profile connection with a specific UUID.
+ * The connection sequence includes ACL connection setup, SDP service
+ * search and RFCOMM connection setup. The server channel of the first
+ * valid SPP service record with the specified UUID will be used. A pfConnectCnf
+ * callback will be received when the connection is complete.The error code in the
+ * callback is cbBCM_OK if the connection was successfully established.
+ * The error code in the callback is cbBCM_ERROR if the connection failed.
+ * @param   pAddress          Pointer to address of remote device.
+ * @param   pUuid             Pointer to uuid of the remote service.
+ * @param   pServiceName      Name of SPP service. Automatic service search
+ *                            is performed to find a service with matching name.
+ *                            If set to NULL then the last of the SPP services
+ *                            on the remote device will be used. If serverChannel
+ *                            parameter is different than cbBCM_INVALID_SERVER_CHANNEL
+ *                            this parameter is ignored and the specified server channel
+ *                            will be used.
+ * @param   serverChannel     RFCOMM server channel that shall be used. Set to
+ *                            cbBCM_INVALID_SERVER_CHANNEL to perform automatic
+ *                            service search to find the server channel.
+ * @param   pAclParameters    Link configuration including link supervision timeout
+ *                            and master slave policy. Pass NULL to use default connection
+ *                            parameters.
+ * @param   pConnectionCallback Callback structure for connection management.
+ * @return  If the operation is successful the connection handle is returned. If
+ *          not cbBCM_INVALID_CONNECTION_HANDLE is returned.
+ */
+extern cbBCM_Handle cbBCM_reqConnectUuid(
+    TBdAddr *pAddress,
+    cb_uint8 *pUuid,
+    cb_char *pServiceName,
+    cb_uint8 serverChannel,
+    cbBCM_ConnectionParameters *pAclParameters,
+    cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Accept or reject an incoming SPP connection. This is a
+ * response to a cbBCM_ConnectInd connection indication.
+ *
+ * @param handle    Connection handle 
+ * @param accept    TRUE to accept the incoming connection.
+                    FALSE to reject.
+ * @return If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_rspConnectUuidCnf(
+    cbBCM_Handle handle,
+    cb_boolean accept);
+
+/**
+* Initiate a Bluetooth PAN Profile connection.
+* The connection sequence includes ACL connection setup and L2CAP connection setup.
+* A pfConnectCnf callback will be received when the connection is complete.
+* The error code in the*callback is cbBCM_OK if the connection was successfully established.
+* The error code in the callback is cbBCM_ERROR if the connection failed.
+*
+* @param   pAddress          Pointer to address of remote device.
+* @param   remoteRole        PAN role of the remote device
+* @param   localRole         PAN role of the local device
+* @param   pAclParams        Link configuration including link supervision timeout
+*                            and master slave policy. Pass NULL to use default connection
+*                            parameters.
+* @param   pConnectionCallback Callback structure for connection management.
+* @return  If the operation is successful the connection handle is returned. If
+*          not cbBCM_INVALID_CONNECTION_HANDLE is returned.
+*/
+extern cbBCM_Handle cbBCM_reqConnectPan(
+    TBdAddr *pAddress,
+    cbBCM_PAN_Role remoteRole,
+    cbBCM_PAN_Role localRole,
+    cbBCM_ConnectionParameters *pAclParams,
+    cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+* Accept or reject an incoming PAN connection. This is a
+* response to a cbBCM_ConnectInd connection indication.
+*
+* @param handle    Connection handle 
+* @param accept    TRUE to accept the incoming connection.
+*                  FALSE to reject.
+* @return If the operation is successful cbBCM_OK is returned.
+*/
+extern cb_int32 cbBCM_rspConnectPan(
+    cbBCM_Handle handle,
+    cb_boolean accept);
+
+/**
+ * Enable Serial Port Service. 
+ * When the device is acting Bluetooth Low Energy peripheral the Serial 
+ * Port Service will be added to the attribute table.
+ *
+ * @param   pConnectionCallback Callback structure for connection management.
+ * @return  If the operation is successful cbBCM_OK is returned.
+ * @param   pConnectionCallback Callback structure for connection management.
+ * @return  If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_enableSps(
+    cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Enable or disable Bluetooth low energy auto connect. 
+ * When the device is acting as central and auto connect is enabled it runs
+ * passive scan and initiates an ACL connection to devices that performs 
+ * directed advertisements.
+ * The serial port service muast be enabled using cbBCM_enableSps() before
+ * auto connect is enabled.
+ * If SPS is enabled the SPS Gatt client will initiate a SPS connection 
+ * attempt on the ACL connection.
+ * When the device is acting peripheral this functionality is inactive.
+ * 
+ * @param   enable  Set to TRUE to enable. Set to false to disable.
+ * @return  If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_autoConnect(
+    cb_boolean enable);
+
+/**
+ * Initiate a Serial Port Service connection.
+ * The connection sequence includes ACL connection setup , GATT service 
+ * search and Serial Port Service connection setup. A connect confirm 
+ * callback will be received when the connection is complete. The error 
+ * code in the callback is cbBCM_OK if the connection was successfully established.
+ * The error code in the callback is cbBCM_ERROR if the connection failed.
+ * The serial port service must be enabled using cbBCM_enableSps() before
+ * auto connect request is made..
+ * @param   pAddress    Address of remote device.
+ * @param   pAclLeParams Link configuration parameters
+ * @param   pConnectionCallback Callback structure for connection management.
+ * @return  If the operation is successful the connection handle is returned. If
+ *          not cbBCM_INVALID_CONNECTION_HANDLE is returned.
+ */
+extern cbBCM_Handle cbBCM_reqConnectSps(
+    TBdAddr *pAddress,
+    cbBCM_ConnectionParametersLe *pAclLeParams,
+    cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * Accept or reject an incoming SPS connection. This is a 
+ * response to a cbBCM_ConnectInd connection indication.
+ * @param   handle  Connection handle 
+ * @param   accept  TRUE to accept the incoming connection. 
+ *                  FALSE to reject.
+ * @return  If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_rspConnectSpsCnf(
+    cbBCM_Handle handle,
+    cb_boolean accept);
+
+/**
+ * Initiate a Bluetooth low energy ACL connection. The ACL connection is
+ * intended for GATT communication.
+ * A connect confirm callback will be received when the connection is complete. The error 
+ * code in the  callback is cbBCM_OK if the connection was successfully established.
+ * The error code in the callback is cbBCM_ERROR if the connection failed.
+ * @param  pAddress     Address of remote device.
+ * @param  pAclLeParams Link configuration parameters
+ * @param  pConnectionCallback Callback structure for connection management.
+ * @return If the operation is successful the connection handle is returned. If
+ *         not cbBCM_INVALID_CONNECTION_HANDLE is returned.
+ */
+extern cbBCM_Handle cbBCM_reqConnectAclLe(
+    TBdAddr *pAddress,
+    cbBCM_ConnectionParametersLe *pAclLeParams,
+    cbBCM_ConnectionCallback *pConnectionCallback);
+
+/**
+ * @brief   Initiate disconnection of active connection. A disconnect event
+ *          will be received when the disconnection is complete.
+ *
+ * @param   handle Connection handle
+ * @return  If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_cmdDisconnect(
+    cbBCM_Handle handle);
+
+/**
+ * @brief   Initiate a Serial Port Profile (SPP) service search to find server channel and service name.
+ * @param   pAddress Address of device on which service search shall be performed.
+ * @param   maxServices Max number of services
+ * @param   pCallback Callback used to notify each found service record
+ * @param   pCompleteCallback Callback used to notify that the search is completed
+ * @return  If the operation is successful initiated cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_reqServiceSearchSpp(
+    TBdAddr *pAddress,
+    cb_uint16 maxServices,
+    cbBCM_ServiceSearchSppCallback pCallback,
+    cbBCM_ServiceSearchCompleteCallback pCompleteCallback);
+
+/**
+ * @brief   Initiate a Dial Up Networking (DUN) service search to find server channel and service name.
+ * @param   pAddress Address of device on which service search shall be performed.
+ * @param   maxServices Max number of services
+ * @param   pCallback Callback used to notify each found service record
+ * @param   pCompleteCallback Callback used to notify that the search is completed
+ * @return  If the operation is successful initiated cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_reqServiceSearchDun(
+    TBdAddr *pAddress,
+    cb_uint16 maxServices,
+    cbBCM_ServiceSearchSppCallback pCallback,
+    cbBCM_ServiceSearchCompleteCallback pCompleteCallback);
+
+/**
+ * @brief   Initiate a UUID service search to find server channel and service name.
+ * @param   pAddress Address of device on which service search shall be performed.
+ * @param   pUuid128 128 UUID to search for.
+ * @param   maxServices Max number of services
+ * @param   pCallback Callback used to notify each found service record
+ * @param   pCompleteCallback Callback used to notify that the search is completed
+ * @return  If the operation is successful initiated cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_reqServiceSearchUuid(
+    TBdAddr *pAddress,
+    const cb_uint8 *pUuid128,
+    cb_uint16 maxServices,
+    cbBCM_ServiceSearchSppCallback pCallback,
+    cbBCM_ServiceSearchCompleteCallback pCompleteCallback);
+
+/**
+ * @brief   Initiate a Device information service search.
+ * @param   pAddress Address of device on which service search shall be performed.
+ * @param   maxServices Max number of services
+ * @param   pCallback Callback used to notify each found service record
+ * @param   pCompleteCallback Callback used to notify that the search is completed
+ * @return  If the operation is successful initiated cbBCM_OK is returned.
+ */
+cb_int32 cbBCM_reqServiceSearchDeviceId(
+    TBdAddr *pAddress,
+    cb_uint16 maxServices,
+    cbBCM_ServiceSearchDeviceIdCallback pCallback,
+    cbBCM_ServiceSearchCompleteCallback pCompleteCallback);
+
+/**
+* @brief   Get local Master/Slave role in an active connection.
+* @param   bdAddr                 address to the connection
+* @param   roleDiscoveryCallback  Callback function used to notify the role
+* @return  If the operation is successful cbBCM_OK is returned.
+*/
+extern cb_int32 cbBCM_RoleDiscovery(
+    TBdAddr bdAddr,
+    cbBCM_RoleDiscoveryCallback roleDiscoveryCallback);
+
+/**
+ * @brief   Get current Received Signal Strength Indication (RSSI)
+ *          of an active connection.
+ * @param   bdAddress       bt address to the connected device
+ * @param   rssiCallback    Callback function used to notify the rssi value
+ * @return  If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_getRssi(
+    TBdAddr bdAddress,
+    cbBCM_RssiCallback rssiCallback);
+
+/*
+* Read the LinkQuality .
+* @return status as int32.
+* @cbBM_LinkQualityCallback is used to provide result.
+*/
+extern cb_int32 cbBCM_GetLinkQuality(TBdAddr bdAddr, cbBCM_LinkQualityCallback  linkQualityCallback);
+
+/**
+ * @brief   Change the packet types currently used for an active Bluetooth
+ *          Classic connection.
+ * @param   handle          Connection handle
+ * @return  If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_cmdChangePacketType(
+    cbBCM_Handle handle);
+
+/**
+ * @brief   Get the current  connection parameters for an active Bluetooth 
+ *          Low Energy ACL connection.
+ * @param   handle   Connection handle
+ * @param   pConnectionInterval     Connection interval
+ * @param   pConnectionLatency      Connection latency
+ * @param   pLinkSupervisionTmo     Link supervision timeout
+ * @return  If the update is successfully initiated cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_getConnectionParams(
+    cbBCM_Handle handle,
+    cb_uint16    *pConnectionInterval,
+    cb_uint16    *pConnectionLatency,
+    cb_uint16    *pLinkSupervisionTmo);
+
+/**
+ * @brief   Update connection parameters for an active Bluetooth 
+ *          Low Energy ACL connection.
+ * @param   handle   Connection handle
+ * @param   pAclLeParams New Link configuration parameters
+ * @return  If the update is successfully initiated cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_updateConnectionParams(
+    cbBCM_Handle handle,
+    cbBCM_ConnectionParametersLe *pAclLeParams);
+
+/**
+ * Register a GATT device information service. The device information service
+ * is used by remote devices to get for example the model and firmware version 
+ * of this device.
+ * Note that an application easily can define and register its own device information 
+ * service if other characteristics are required.
+ * @param   pManufacturer   String defining the manufacturer.
+ * @param   pModel String   defining the device model.
+ * @param   pFwVersion      String defining the firmware version.
+ * @param   startIndex      Start index of the attribute database for the device info service.
+ *                          Note that this must not change during the lifetime of the product.
+ * @return  If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_enableDevInfoService(
+    const cb_char *pManufacturer,
+    const cb_char *pModel,
+    const cb_char *pFwVersion,
+    cb_uint16 startIndex);
+
+/**
+ * @brief   Get the address of the remote device on an 
+ *          active connection
+ * 
+ * @param handle Connection handle
+ * @return Address of the remote device.
+ */
+extern TBdAddr cbBCM_getAddress(cbBCM_Handle handle);
+
+/**
+ * @brief   Register a data manager for a type of connections. Shall not be
+ *          used by the application. Only used by data managers.
+ * 
+ * @param   type            Connection type.
+ * @param   pDataCallback   Data callback
+ * @return  If the operation is successful cbBCM_OK is returned.
+ */
+extern cb_int32 cbBCM_registerDataCallback(
+    cbBCM_ConnectionType type,
+    cbBCM_DataCallback *pDataCallback);
+
+/**
+ * @brief   Get the protocol handle for an active connection. Shall not be used
+ *          by the application. Only used by data managers.
+ * 
+ * @param   handle Connection handle
+ * @return  If the operation is not successful cbBCM_INVALID_CONNECTION_HANDLE
+ *          is returned. If the operation is successful the protocol handle is 
+ *          returned.
+ */
+extern cbBCM_Handle cbBCM_getProtocolHandle(
+    cbBCM_Handle handle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CB_BT_CONN_MAN_H_ */
+
+
+
+
+
+
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h
new file mode 100644
index 00000000000..240081d526e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h
@@ -0,0 +1,625 @@
+/*
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : Bluetooth Manager
+ * File        : cb_bt_man.h
+ *
+ * Description : General Bluetooth functionality
+ *
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_bt_man.h
+ *
+ * @brief General Bluetooth functionality. This includes initialization of 
+ * the Bluetooth radio and stack, handling properties such as device 
+ * name, scanning for other devices using inquiry or Bluetooth Low Energy 
+ * scan and more.
+ */
+
+#ifndef _CB_BT_MAN_H_
+#define _CB_BT_MAN_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+* DEFINES
+*=========================================================================*/
+#define cbBM_OK                 (0)
+#define cbBM_ERROR              (-1)
+#define cbBM_MAX_OUTPUT_POWER   (127)
+
+#define cbBM_ADV_CHANNEL_MAP_CH_37_BIT          0x01
+#define cbBM_ADV_CHANNEL_MAP_CH_38_BIT          0x02
+#define cbBM_ADV_CHANNEL_MAP_CH_39_BIT          0x04
+#define cbBM_ADV_CHANNEL_MAP_ALL                (cbBM_ADV_CHANNEL_MAP_CH_37_BIT | cbBM_ADV_CHANNEL_MAP_CH_38_BIT | cbBM_ADV_CHANNEL_MAP_CH_39_BIT)
+/*===========================================================================
+* TYPES
+*=========================================================================*/
+
+extern const TBdAddr invalidBdAddress;
+
+typedef enum
+{
+    cbBM_INQUIRY_GENERAL = 0,
+    cbBM_INQUIRY_LIMITED = 1,
+} cbBM_InquiryType;
+
+typedef void (*cbBM_InquiryEventCallback)(
+     TBdAddr *pBdAddress,
+     TCod cod,
+     cb_uint16 clockOffset,
+     cb_int8 rssi,
+     cb_char *pName,
+     TExtInqRsp* pExtInqRsp,
+     cb_uint8 length);
+
+typedef void (*cbBM_InquiryCompleteCallback)(
+    cb_int32 status);
+
+typedef void (*cbBM_RemoteNameCallback)(
+    TBdAddr *pBdAddress,
+    TName *pName,
+    cb_int32 status);
+
+typedef enum
+{
+    cbBM_DEVICE_DISCOVERY_LE_ALL = 0,
+    cbBM_DEVICE_DISCOVERY_LE_GENERAL,
+    cbBM_DEVICE_DISCOVERY_LE_LIMITED,
+    cbBM_DEVICE_DISCOVERY_LE_ALL_NO_FILTERING
+} cbBM_DeviceDiscoveryTypeLe;
+
+typedef enum
+{
+    cbBM_ACTIVE_SCAN = 0,
+    cbBM_PASSIVE_SCAN = 1
+} cbBM_ScanTypeLe;
+
+
+typedef void (*cbBM_DeviceDiscoveryLeEventCallback)(
+    TBdAddr *pBdAddress,
+    cb_int8 rssi,
+    cb_char *pName,
+    TAdvData *pAdvData);
+
+typedef void (*cbBM_DeviceDiscoveryLeCompleteCallback)(
+    cb_int32 status);
+
+typedef enum
+{
+    cbBM_DISCOVERABLE_MODE_NONE = 0,
+    cbBM_DISCOVERABLE_MODE_LIMITED = 1,
+    cbBM_DISCOVERABLE_MODE_GENERAL = 2,
+} cbBM_DiscoverableMode;
+
+typedef enum
+{
+    cbBM_CONNECTABLE_MODE_NOT_CONNECTABLE = 0,
+    cbBM_CONNECTABLE_MODE_CONNECTABLE
+} cbBM_ConnectableMode;
+
+typedef enum
+{
+    cbBM_DISCOVERABLE_MODE_LE_NONE = 0,
+    cbBM_DISCOVERABLE_MODE_LE_LIMITED = 1,
+    cbBM_DISCOVERABLE_MODE_LE_GENERAL = 2,
+} cbBM_DiscoverableModeLe;
+
+typedef enum
+{
+    cbBM_CONNECTABLE_MODE_LE_NOT_CONNECTABLE = 0,
+    cbBM_CONNECTABLE_MODE_LE_CONNECTABLE
+} cbBM_ConnectableModeLe;
+
+typedef enum
+{
+    cbBM_SET_CHANNEL_MAP_CNF_POS,
+    cbBM_SET_CHANNEL_MAP_CNF_NEG,
+} cbBM_ChannelMapEvt;
+
+typedef void (*cbBM_ChannelMapCallb)(
+    cbBM_ChannelMapEvt chMapEvt,
+    TChannelMap *pChMap);
+
+typedef void (*cbBM_InitComplete)(void);
+
+typedef enum
+{
+    cbBM_LE_ROLE_DISABLED = 0,
+    cbBM_LE_ROLE_CENTRAL = 1,
+    cbBM_LE_ROLE_PERIPHERAL = 2,
+} cbBM_LeRole;
+
+/** 
+ * Bluetooth Manager initialization parameters.
+*/
+typedef struct
+{
+    TBdAddr         address;                    /** Bluetooth address that shall be assigned to controller. Pass invalidBdAddress to use controller default address*/
+    cbBM_LeRole     leRole;                     /** Bluetooth low energy role */
+    cb_int8         maxOutputPower;             /** Maximum output power. */
+    cb_uint32       nvdsStartIdLinkKeysClassic; /** Start id for CLASSIC link keys storage in NVDS. */
+    cb_uint32       maxLinkKeysClassic;         /** Max number of CLASSIC link keys */
+    cb_uint32       nvdsStartIdLinkKeysLe;      /** Start id for BLE link keys storage in NVDS. */
+    cb_uint32       maxLinkKeysLe;              /** Max number of link keys BLE*/
+} cbBM_InitParams;
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Initialize the Bluetooth Radio, the connectBlue Embedded Bluetooth 
+ * Stack and the Bluetooth Manager.
+ * The init complete callback is used to notify when the initialization is 
+ * complete. During initialization default values are set for all properties.
+ * The application shall set desired values for the main Bluetooth properties
+ * such as local name after the initialization is complete. After init the device 
+ * is non discoverable and non connectable.
+ * 
+ * @param pInitParameters       Init parameters
+ * @param initCompleteCallback  Callback used to notify when the initialization is complete.
+ * @return None
+ */
+extern void cbBM_init(
+    cbBM_InitParams *pInitParameters,
+    cbBM_InitComplete initCompleteCallback);
+
+/**
+ * This function sets all default parameters for LE. 
+ * This function needs to be called before the cbBM_init.
+*/
+extern void cbBM_setDefaultValuesLeParams(void);
+
+/**
+ * Get the current Bluetooth address of the device.
+ * @param pAddress Pointer to return variable.
+ * @return if the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getLocalAddress(TBdAddr *pAddress);
+
+/**
+ * Set local name
+ * This sets the Bluetooth Classic device name as well as the Bluetooth Low
+ * Energy device name. Inquiry and advertising is updated.
+ * @param pName         The new local name.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setLocalName(cb_char* pName);
+
+/**
+ * Get local name.
+ * Get the current local name.
+ * @param pName     Pointer to return variable.
+ * @param length    Max length of the name string.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getLocalName(
+    cb_char *pName,
+    cb_uint32 length);
+
+/**
+ * Set class of device
+ * @param cod New Class of Device.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setCod(TCod cod);
+
+/**
+ * Get current class of device.
+ * @param pCod Pointer to return variable.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getCod(TCod* pCod);
+
+/**
+ * Set discoverable mode for Bluetooth Classic.
+ * @param discoverable New discoverable mode.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setDiscoverableMode(cbBM_DiscoverableMode discoverable);
+
+/**
+ * Get current discoverable mode for Bluetooth Classic.
+ * @param pDiscoverable Pointer to return variable.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getDiscoverableMode(cbBM_DiscoverableMode *pDiscoverable);
+
+/**
+ * Set connectable mode for Bluetooth Classic.
+ * @param connectable Connectable mode
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setConnectableMode(cbBM_ConnectableMode connectable);
+
+/**
+ * Get current connectable mode for Bluetooth Classic
+ * @param pConnectable Pointer to return variable.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getConnectableMode(cbBM_ConnectableMode *pConnectable);
+
+/**
+ * Set master slave policy for Bluetooth Classic
+ * @param   policy  Master slave policy
+ * @return  If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setMasterSlavePolicy(TMasterSlavePolicy policy);
+
+/**
+ * Set master slave policy for Bluetooth Classic
+ * @param   pPolicy  Pointer to return variable
+ * @return  If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getMasterSlavePolicy(TMasterSlavePolicy *pPolicy);
+
+/**
+ * Set default channel map for Bluetooth Classic. Used to exclude channels
+ * from usage.
+ * Request an update of which channels shall be used by adaptive frequency hopping.
+ * typically this is not needed since the Bluetooth is very good at select which
+ * channels to use.
+ * @param channelMap            Channel map. Note that at least 20 channels must be enabled.
+ * @param channelMapCallback    Callback used to notify if the channel map
+ *                              is accepted by the radio.
+ * @return If the operation is successfully initiated cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setAfhChannelMap(
+    TChannelMap channelMap,
+    cbBM_ChannelMapCallb channelMapCallback);
+
+/**
+ * Get the default channel map.
+ * @param pMap Pointer to return variable.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_getAfhChannelMap(TChannelMap *pMap);
+
+/**
+ * Start an Bluetooth inquiry.
+ * The event callback is called for every device that is found during inquiry.
+ * @param type Type of inquiry.
+ * @param inquiryLengthInMs Length of inquiry in ms
+ * @param eventCallback     Callback used to notify each found device
+ * @param completeCallback  Callback used to notify when the inquiry is completed
+ * @return If the inquiry is successfully started cbBM_OK is returned
+ */
+extern cb_int32 cbBM_inquiry(
+    cbBM_InquiryType type,
+    cb_uint32 inquiryLengthInMs,
+    cbBM_InquiryEventCallback eventCallback,
+    cbBM_InquiryCompleteCallback completeCallback);
+
+/**
+ * Cancel an ongoing inquiry.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_inquiryCancel(void);
+
+/**
+ * Perform a remote name request for Bluetooth Classic.
+ * @param pAddress          Pointer to address of remote device.
+ * @param clockOffset       Clock offset. Can be found in inquiry response.
+ * @param pageTimeout       Page timeout in ms (Length of connection attempt).
+ * @param remoteNameCallb   Callback used to notify the the completion of the 
+ *                          name request.
+ * @return If the operation is successfully initiated cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_remoteName(
+    TBdAddr *pAddress,
+    cb_uint16 clockOffset,
+    cb_uint16 pageTimeout,
+    cbBM_RemoteNameCallback remoteNameCallb);
+
+/**
+ * Add service class to inquiry response data. Typically
+ * not used by the application.
+ * @param uuid16 The UUID to add
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_addServiceClass(cb_uint16 uuid16);
+
+/**
+ * Check if service class is already registered. 
+ * @param uuid16 The UUID to check
+ * @return TRUE If the ServiceClass is registered, FALSE otherwise.
+ */
+cb_boolean cbBM_isServiceClassRegistered(cb_uint16 uuid16 );
+
+/**
+ * Add service class to inquiry response data. Typically
+ * not used by the application.
+ * @param uuid128 The UUID to add.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_add128BitsServiceClass(cb_uint8* uuid128);
+
+/**
+ * Set maximum Bluetooth Classic ACL links the stack
+ * shall allow.
+ * @param maxConnections Max ACL connections.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_setMaxConnections(cb_uint32 maxConnections);
+
+/**
+ * Get controller version string.
+ * @return Pointer to NULL terminated version string.
+ */
+extern cb_char* cbBM_getControllerVersionString(void);
+
+/**
+ * Get stack version string.
+ * @return Pointer to NULL terminated version string.
+ */
+extern cb_char* cbBM_getStackVersionString(void);
+
+/**
+ * Get current Bluetooth Low Energy Role.
+ * @return Current Bluetooth Low Energy role.
+ */
+extern cbBM_LeRole cbBM_getLeRole(void);
+
+/**
+ * Set Bluetooth Low Energy discoverable mode.
+ * Only valid for peripheral role.
+ * @param   discoverableMode  Bluetooth Low Energy discoverable mode
+ * @return  cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setDiscoverableModeLe(
+    cbBM_DiscoverableModeLe discoverableMode);
+
+/**
+ * Get Bluetooth Low Energy discoverable mode.
+ * @param   pDiscoverableMode  Pointer to return variable 
+ * @return  cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_getDiscoverableModeLe(
+    cbBM_DiscoverableModeLe *pDiscoverableMode);
+
+/**
+ * Set Bluetooth Low Energy connectable mode.
+ * Only valid for peripheral role.
+ * @param   connectable  Set to TRUE to accept connections
+ *                       Set to FALSE to reject incoming connections
+ * @return  cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setConnectableModeLe(
+    cbBM_ConnectableModeLe connectable);
+
+/**
+ * Get current connectable mode.
+ * @param   pConnectable    Pointer to return variable.
+ * @return  cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_getConnectableModeLe(
+    cbBM_ConnectableModeLe* pConnectable);
+
+/**
+ * Set custom advertising data.
+ * Only valid for peripheral role.
+ * @param   pAdvData    Pointer to advertising data.
+ * @return  cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setCustomAdvData(
+    TAdvData* pAdvData);
+
+/**
+ * Set custom scan response data.
+ * Only valid for peripheral role.
+ * @param   pScanRspData    Pointer to scan response data.
+ * @return  cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_setCustomScanRspData(
+    TAdvData* pScanRspData);
+
+/**
+ * Set current scan response data.
+ * Only valid for peripheral role.
+ * @param   pAdvData    Pointer to scan response data.
+ * @return  cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_getAdvData(
+    TAdvData* pAdvData);
+
+/**
+ * Get current scan response data.
+ * Only valid for peripheral role.
+ * @param   pScanRspData    Pointer to scan response data.
+ * @return  cbBM_OK is returned on success.
+ */
+ extern cb_int32 cbBM_getScanRspData(
+     TAdvData* pScanRspData);
+
+/**
+ * Set default Bluetooth Low Energy connection parameters.
+ * Note that setting the connection parameters does not change
+ * the parameters on active connections.
+ * @param   createConnectionTimeout Default timeout connection for connection attempts
+ * @param   connIntervalMin    Default connection min interval
+ * @param   connIntervalMax    Default connection max interval
+ * @param   connLatency        Default connection latency
+ * @param   linklossTmo        Default link loss timeout
+ * @return  cbBM_OK is returned on success.
+ */
+ cb_int32 cbBM_setAutoConnectionParams(
+     cb_uint32 createConnectionTimeout,
+     cb_uint16 connIntervalMin,
+     cb_uint16 connIntervalMax,
+     cb_uint16 connLatency,
+     cb_uint16 linklossTmo);
+
+/**
+ * Get default Bluetooth Low Energy connection parameters.
+ * @param   pCreateConnectionTimeout Default create connection timeout
+ * @param   pConnIntervalMin    Default connection min interval
+ * @param   pConnIntervalMax    Default connection max interval
+ * @param   pConnLatency        Default connection latency
+ * @param   pLinklossTmo        Default link loss timeout
+ * @return  cbBM_OK is returned on success.
+ */
+ cb_int32 cbBM_getAutoConnectionParams(
+     cb_uint32 *pCreateConnectionTimeout,
+     cb_uint16 *pConnIntervalMin,
+     cb_uint16 *pConnIntervalMax,
+     cb_uint16 *pConnLatency,
+     cb_uint16 *pLinklossTmo);
+
+/**
+ * Get Bluetooth Low Energy scan parameters.
+ * @param   pScanInterval        Scan interval
+ * @param   pScanWindow          Scan window
+ * @return  cbBM_OK is returned on success.
+ */
+extern cb_int32 cbBM_getAutoconnScanParams(
+    cb_uint16 *pScanInterval,
+    cb_uint16 *pScanWindow);
+
+/**
+ * Start an Bluetooth Low Energy device discovery.
+ * The event callback is called for every device that is found during inquiry.
+ * @param type              Type of discovery.
+ * @param discoveryLength   Length of inquiry in seconds.
+ * @param scanType          Active or passive scan
+ * @param eventCallback     Callback used to notify each found device
+ * @param completeCallback  Callback used to notify when the inquiry is completed.
+ * @return If the device discovery is successfully started cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_deviceDiscoveryLe(
+    cbBM_DeviceDiscoveryTypeLe type,
+    cb_uint16 discoveryLength,
+    cbBM_ScanTypeLe scanType,
+    cbBM_DeviceDiscoveryLeEventCallback eventCallback,
+    cbBM_DeviceDiscoveryLeCompleteCallback completeCallback);
+
+/**
+ * Cancel an ongoing device discovery.
+ * @return If the operation is successful cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_deviceDiscoveryLeCancel(void);
+
+/**
+ * Perform a remote name request for Bluetooth Low Energy.
+ * @param pAddress              Pointer to address of remote device.
+ * @param remoteNameCallback    Callback used to notify the the completion of the 
+ *                              name request.
+ * @return If the operation is successfully initiated cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_remoteNameLe(TBdAddr *pAddress,
+                                  cbBM_RemoteNameCallback remoteNameCallback);
+
+
+
+/*
+ * Add 128bit service UUID to scan response data. Typically
+ * not used by the application.
+ * @param uuid128 Pointer to 128bit UUID
+ * @return If the operation is successfully initiated cbBM_OK is returned.
+ */
+extern cb_int32 cbBM_add128BitsServiceClassLe(cb_uint8* uuid128);
+
+/*
+ * Read the used max tx power .
+ * @return max tx power level as int8.
+ */
+extern cb_int8 cbBM_getMaxTxPower(void);
+
+/*
+* Read the connection parameters for Bond.
+* @return cbCMLE_AclParamsLe pointer to values.
+*/
+void cbBM_getBondParameters(TAclParamsLe* bondParams);
+/*
+* Read the connection parameters for connection.
+* @return cbCMLE_AclParamsLe pointer to values.
+*/
+void cbBM_getConnectParameters(TAclParamsLe* aclParams);
+/*
+* Read the connection parameters for remote name request.
+* @return cbCMLE_AclParamsLe pointer to values.
+*/
+void cbBM_getRemoteNameReqParameters(TAclParamsLe* aclParams);
+
+/*
+* Sets the LE parameter.
+* @newValue new parameter value.
+*/
+extern cb_int32 cbBM_setAdvertisingIntervalMin(cb_uint16 newValue);
+extern cb_int32 cbBM_setAdvertisingIntervalMax(cb_uint16 newValue);
+extern cb_int32 cbBM_setAdvChannelmap(cb_uint16 newValue);
+extern cb_int32 cbBM_setConnectConnIntervalMin(cb_uint16 newValue);
+extern cb_int32 cbBM_setConnectConnIntervalMax(cb_uint16 newValue);
+extern cb_int32 cbBM_setConnectConnLatency(cb_uint16 newValue);
+extern cb_int32 cbBM_setConnectLinklossTmo(cb_uint16 newValue);
+extern cb_int32 cbBM_setConnectCreateConnTmo(cb_uint16 newValue);
+extern cb_int32 cbBM_setConnectScanInterval(cb_uint16 newValue);
+extern cb_int32 cbBM_setConnectScanWindow(cb_uint16 newValue);
+extern cb_int32 cbBM_setBondConnIntervalMin(cb_uint16 newValue);
+extern cb_int32 cbBM_setBondConnIntervalMax(cb_uint16 newValue);
+extern cb_int32 cbBM_setBondConnLatency(cb_uint16 newValue);
+extern cb_int32 cbBM_setBondLinklossTmo(cb_uint16 newValue);
+extern cb_int32 cbBM_setBondCreateConnTmo(cb_uint16 newValue);
+extern cb_int32 cbBM_setBondScanInterval(cb_uint16 newValue);
+extern cb_int32 cbBM_setBondScanWindow(cb_uint16 newValue);
+extern cb_int32 cbBM_setRemoteNameConnIntervalMin(cb_uint16 newValue);
+extern cb_int32 cbBM_setRemoteNameConnIntervalMax(cb_uint16 newValue);
+extern cb_int32 cbBM_setRemoteNameConnLatency(cb_uint16 newValue);
+extern cb_int32 cbBM_setRemoteNameLinklossTmo(cb_uint16 newValue);
+extern cb_int32 cbBM_setRemoteNameCreateConnTmo(cb_uint16 newValue);
+extern cb_int32 cbBM_setRemoteNameScanInterval(cb_uint16 newValue);
+extern cb_int32 cbBM_setRemoteNameScanWindow(cb_uint16 newValue);
+
+/*
+* Read the LE parameter.
+* @return parameter.
+*/
+extern cb_uint16 cbBM_getAdvertisingIntervalMin(void);
+extern cb_uint16 cbBM_getAdvertisingIntervalMax(void);
+extern cb_uint16 cbBM_getAdvChannelmap(void);
+extern cb_uint16 cbBM_getConnectConnIntervalMin(void);
+extern cb_uint16 cbBM_getConnectConnIntervalMax(void);
+extern cb_uint16 cbBM_getConnectConnLatency(void);
+extern cb_uint16 cbBM_getConnectLinklossTmo(void);
+extern cb_uint16 cbBM_getConnectCreateConnTmo(void);
+extern cb_uint16 cbBM_getConnectScanInterval(void);
+extern cb_uint16 cbBM_getConnectScanWindow(void);
+extern cb_uint16 cbBM_getBondConnIntervalMin(void);
+extern cb_uint16 cbBM_getBondConnIntervalMax(void);
+extern cb_uint16 cbBM_getBondConnLatency(void);
+extern cb_uint16 cbBM_getBondLinklossTmo(void);
+extern cb_uint16 cbBM_getBondCreateConnTmo(void);
+extern cb_uint16 cbBM_getBondScanInterval(void);
+extern cb_uint16 cbBM_getBondScanWindow(void);
+extern cb_uint16 cbBM_getRemoteNameConnIntervalMin(void);
+extern cb_uint16 cbBM_getRemoteNameConnIntervalMax(void);
+extern cb_uint16 cbBM_getRemoteNameConnLatency(void);
+extern cb_uint16 cbBM_getRemoteNameLinklossTmo(void);
+extern cb_uint16 cbBM_getRemoteNameCreateConnTmo(void);
+extern cb_uint16 cbBM_getRemoteNameScanInterval(void);
+extern cb_uint16 cbBM_getRemoteNameScanWindow(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h
new file mode 100644
index 00000000000..cfc7e8cb885
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h
@@ -0,0 +1,142 @@
+/**
+*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : Bluetooth Serial
+ * File        : cb_bt_pan.h
+ *
+ * Description : Data management for PAN profile
+ *
+ *-------------------------------------------------------------------------*/
+
+#ifndef _CB_BT_PAN_H_
+#define _CB_BT_PAN_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+#include "cb_bt_conn_man.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+* DEFINES
+*=========================================================================*/
+#define cbBTPAN_RESULT_OK                    ((cb_int32)0x00000000)
+#define cbBTPAN_RESULT_ERROR                 ((cb_int32)0x00000001)
+#define cbBTPAN_RESULT_ILLEGAL_HANDLE        ((cb_int32)0x00000002)
+#define cbBTPAN_RESULT_FLOW_STOP             ((cb_int32)0x00000003)
+#define cbBTPAN_RESULT_LINK_LOSS             ((cb_int32)0x00000004)
+
+/*===========================================================================
+* TYPES
+*=========================================================================*/
+typedef cb_uint32   cbBTPAN_Handle;
+
+/*---------------------------------------------------------------------------
+* Callback to indicate that a Bnep connection has been established.
+*
+* @param connHandle: Connection handle
+* @param info: Information about the connection
+*
+* @return None
+*-------------------------------------------------------------------------*/
+typedef void(*cbBTPAN_ConnectEvt)             (cbBCM_Handle connHandle, cbBCM_ConnectionInfo info);
+
+/*---------------------------------------------------------------------------
+* Callback to indicate that a Bnep connection has been disconnected.
+*
+* @param connHandle: Connection handle
+*
+* @return None
+*-------------------------------------------------------------------------*/
+typedef void(*cbBTPAN_DisconnectEvt)          (cbBCM_Handle connHandle);
+
+/*---------------------------------------------------------------------------
+* Callback to indicate that data has been received from remote device.
+*
+* @param btPanHandle: PAN handle
+* @param length: Length of the data
+* @param pData: Pointer to the data
+*
+* @return None
+*-------------------------------------------------------------------------*/
+typedef void(*cbBTPAN_DataEvt)             (cbBCM_Handle connHandle, cb_uint8* pData, cb_uint16 length);
+
+/*---------------------------------------------------------------------------
+* Callback to indicate that data has been taken care by PAN. New
+* data can now be sent on this handle.
+*
+* @param btPanHandle: PAN handle
+* @param result: cbBTPAN_RESULT_OK if the data sending succeeded
+*
+* @return None
+*-------------------------------------------------------------------------*/
+typedef void(*cbBTPAN_DataCnf)             (cbBCM_Handle connHandle, cb_int32 result);
+
+typedef struct
+{
+    cbBTPAN_ConnectEvt     pfConnectEvt;
+    cbBTPAN_DisconnectEvt  pfDisconnectEvt;
+    cbBTPAN_DataEvt        pfDataEvt;
+    cbBTPAN_DataCnf        pfWriteCnf;
+}cbBTPAN_Callback;
+
+/*===========================================================================
+* FUNCTIONS
+*=========================================================================*/
+/**
+* Initialization of Bluetooth PAN data. Called during stack
+* initialization. Shall not be called by application.
+*
+* @return None
+*/
+extern void cbBTPAN_init(void);
+
+/**
+* Registers for PAN data callbacks. Only one registration is supported.
+*
+* @param pDataCallback  Data callback
+*
+* @return cbBTPAN_RESULT_OK if successful
+*/
+extern cb_uint32 cbBTPAN_registerDataCallback(cbBTPAN_Callback* pDataCallback);
+
+/*---------------------------------------------------------------------------
+* Sends data to the remote device. Note that you have to wait for the
+* confirmation callback (cbBTPAN_DataCnf) before calling another cbBTPAN_reqData.
+*
+* @param connHandle: Connection handle
+* @param pBuf: Pointer to the data
+* @param bufSize: Length of the data
+*
+* @return cbBTPAN_RESULT_OK if successful
+*-------------------------------------------------------------------------*/
+extern cb_int32 cbBTPAN_reqData(cbBCM_Handle connHandle, cb_uint8* pBuf, cb_uint16 bufSize);
+
+/*---------------------------------------------------------------------------
+* Gets the max frame size that can be sent/received with
+* cbBTPAN_reqData/pfDataEvt
+*
+* @return max frame size
+*-------------------------------------------------------------------------*/
+extern cb_int32 cbBTPAN_getMaxFrameSize(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_cb_BT_PAN_H_
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h
new file mode 100644
index 00000000000..c6a38b49af7
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h
@@ -0,0 +1,378 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : Bluetooth Security Manager
+ * File        : cb_bt_sec_man.h
+ *
+ * Description : Bluetooth security application support
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_bt_sec_man.h
+ * @brief  Bluetooth security application support. This includes bonding,
+ * security modes, passkey and pin code handling.
+ */
+
+#ifndef _CB_BT_SEC_MAN_H_
+#define _CB_BT_SEC_MAN_H_
+
+#include "cb_comdefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+#define cbBSM_OK                                    (0)
+#define cbBSM_ERROR                                 (-1)
+
+#define cbBSM_PASSKEY_MAX_VALUE                     (999999)
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+/**
+ * cbBSM_SECURITY_MODE_1_DISABLED
+ * Security disabled
+ * - Remote Device BT 2.1: Auto accept (No man-in-the-middle attack protection, encryption enabled) 
+ * - Remote Device BT 2.0: Authentication and encryption disabled. 
+ * - Bluetooth Low Energy: Auto accept (No man-in-the-middle attack protection, encryption enabled) 
+ * 
+ * cbBSM_SECURITY_MODE_2_BT_2_0
+ * - Enforce BT 2.0 (Service level authentication and encryption enabled) 
+ * Please note that the device is not BT 2.1 qualified for this setting. It is included for backward compatibility. Invalid for Bluetooth Low Energy.
+ * 
+ * cbBSM_SECURITY_MODE_3_FIXED_PIN
+ * - Remote Device BT 2.1: Service level authentication and encryption enabled. 
+ * - Remote Device BT 2.0: Service level authentication and encryption enabled. 
+ * - Bluetooth Low Energy: Service level authentication and encryption enabled. 
+ * Please note that this security mode will not work with a general BT 2.1 device. However, it will work between two connectBlue BT 2.1 Serial Port Adapters. Use security mode 4 to make the device work with a general BT 2.1 device. 
+ * 
+ * cbBSM_SECURITY_MODE_4_JUST_WORKS
+ * - Remote Device BT 2.1: Auto accept (no man-in-the-middle attack protection, encryption enabled) 
+ * - Remote Device BT 2.0: Service level authentication and encryption enabled. 
+ * - Bluetooth Low Energy: Auto accept (no man-in-the-middle attack protection, encryption enabled)
+ * This security mode is intended for pairing in safe environments. When this mode is set, pairability (see AT*AGPM) is automatically disabled. In data mode, pairing can be enabled for 60 seconds by pressing the "External Connect" button for at least 5 seconds. When the module is pairable, the LED will blink. If the mode is changed from Just Works to another, pairability must be enabled again using the AT*AGPM command. 
+ * 
+ * cbBSM_SECURITY_MODE_5_DISPLAY_ONLY 
+ * - Remote Device BT 2.1: Service level authentication and encryption enabled. User should be presented a passkey. 
+ * - Remote Device BT 2.0: Service level authentication and encryption enabled. No user interaction required. 
+ * - Bluetooth Low Energy: Service level authentication and encryption enabled. User should be presented a passkey.
+ * This security mode is used when the device has a display that can present a 6-digit value that the user shall enter on the remote device. 
+ * 
+ * cbBSM_SECURITY_MODE_6_DISPLAY_YES_NO 
+ * - Remote Device BT 2.1: Service level authentication and encryption enabled. User should compare two values. 
+ * - Remote Device BT 2.0: Service level authentication and encryption enabled. No user interaction required. 
+ * This security mode is used when the device has a display that can present a 6-digit value that the user shall verify with yes or no to the remote device's presented value. 
+ * Invalid for Bluetooth Low Energy.
+ * 
+ * cbBSM_SECURITY_MODE_7_KEYBOARD_ONLY
+ * - Remote Device BT 2.1: Service level authentication and encryption enabled. User should enter a passkey. 
+ * - Remote Device BT 2.0: Service level authentication and encryption enabled. No user interaction required. 
+ * - Bluetooth Low Energy: Service level authentication and encryption enabled. User should enter a passkey.
+ * This security mode is used when the device only has a keyboard where the user can enter a 6-digit value that is presented on the remote device. 
+ */
+typedef enum
+{
+    cbBSM_SECURITY_MODE_1_DISABLED = 1,
+    cbBSM_SECURITY_MODE_2_BT_2_0,
+    cbBSM_SECURITY_MODE_3_FIXED_PIN,
+    cbBSM_SECURITY_MODE_4_JUST_WORKS,
+    cbBSM_SECURITY_MODE_5_DISPLAY_ONLY,
+    cbBSM_SECURITY_MODE_6_DISPLAY_YES_NO,
+    cbBSM_SECURITY_MODE_7_KEYBOARD_ONLY
+} cbBSM_SecurityMode;
+
+typedef struct
+{
+    TPinCode pin;
+    cb_uint8   nBytes;
+} cbBSM_PinCode;
+
+typedef enum
+{
+    cbBSM_BOND_TYPE_CLASSIC,
+    cbBSM_BOND_TYPE_LE,
+    cbBSM_BOND_TYPE_ALL,
+} cbBSM_BondTypes;
+
+typedef enum
+{
+    cbBSM_BOND_STATUS_OK = 0,
+    cbBSM_BOND_STATUS_ERR_PAGE_TMO,
+    cbBSM_BOND_STATUS_ERR_AUTH_FAIL,
+    cbBSM_BOND_STATUS_ERR_NO_MITM
+} cbBSM_BondStatus;
+
+/**
+ * Callback to indicate that bonding is finished.
+ * @param   bdAddress Remote BD address
+ * @param   bondStatus Bond status, e.g. cbBSM_BOND_STATUS_OK
+ * @return  None
+ */
+typedef void (*cbBSM_BondCnf)(
+    cbBSM_BondStatus status,
+    TBdAddr* pBdAddress);
+
+/**
+ * Callback to indicate that a pin code is required from upper layer.
+ * Respond the pin code request with cbBSM_rspFixedPin/cbBSM_rspNegFixedPin
+ * This is only used when either local or remote side does not support 
+ * BT 2.1 secure simple pairing.
+ * @param   bdAddress Remote BD address
+ * @return  None
+ */
+typedef void (*cbBSM_RequestPinInd)(
+    TBdAddr* pBdAddress);
+
+/**
+ * Callback to indicate that user confirmation is required. The user should
+ * compare numericValues on local and remote side and respond the confirmation 
+ * request with cbBSM_rspUserConfirmation if values match and 
+ * cbBSM_rspNegUserConfirmation if they do not match or user wants to interrupt
+ * the pairing attempt.
+ * This is only used when both sides support BT 2.1 secure simple pairing and 
+ * security mode cbBSM_SECURITY_MODE_6_DISPLAY_YES_NO is used.
+ * @param   bdAddress Remote BD address
+ * @param   numericValue The numeric value to be compared
+ * @return  None
+ */
+typedef void (*cbBSM_UserConfirmationInd)(
+    TBdAddr* pBdAddress,
+    cb_uint32 numericValue);
+
+/**
+ * Callback to indicate that a passkey is required from upper layer.
+ * Respond the passkey request with cbBSM_rspUserPasskey/cbBSM_rspNegUserPasskey.
+ * This is only used when both sides support BT 2.1 secure simple pairing and 
+ * security modes cbBSM_SECURITY_MODE_3_FIXED_PIN or cbBSM_SECURITY_MODE_7_KEYBOARD_ONLY is used
+ * @param   bdAddress Remote BD address
+ * @return  None
+ */
+typedef void (*cbBSM_UserPasskeyInd)(
+    TBdAddr* pBdAddress);
+
+/**
+ * Callback to indicate that a passkey is used in the pairing procedure.
+ * The passkey should be displayed to the user.
+ * This is only used when both sides support BT 2.1 secure simple pairing and
+ * security mode cbBSM_SECURITY_MODE_5_DISPLAY_ONLY is used.
+ * @param   bdAddress Remote BD address
+ * @param   passkey Passkey
+ * @return  None
+ */
+typedef void (*cbBSM_UserPasskeyEvt)(
+    TBdAddr* pBdAddress,
+    cb_uint32 passkey);
+
+typedef struct  
+{
+    cbBSM_RequestPinInd requestPinInd;
+    cbBSM_UserConfirmationInd userConfirmationInd;
+    cbBSM_UserPasskeyInd userPasskeyInd;
+    cbBSM_UserPasskeyEvt userPasskeyEvt;
+    cbBSM_BondCnf bondConfirmation;
+    cbBSM_BondCnf bondEvent;
+} cbBSM_Callbacks;
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Initialization of BLuetooth security manager. Called during stack
+ * initialization. Shall not be called by application.
+ * 
+ * @return  None
+ */
+extern void cbBSM_init(void);
+
+/**
+ * Register security callbacks. Callbacks in the struct that are not 
+ * of any interest can be set to NULL.
+ *
+ * @param pPairingCallbacks Pointer to the security callback struct
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_registerCallbacks(cbBSM_Callbacks* pPairingCallbacks);
+
+/**
+ * Set security mode. See comments on cbBSM_SecurityMode for 
+ * description of the different security modes.
+ * 
+ * @param securityMode Security mode. Default security is cbBSM_SECURITY_MODE_1_DISABLED
+ * @param allowPairingInNonBondableMode Normally FALSE. Set to TRUE if pairing should be allowed when not bondable.
+ *                                      No link keys will then be stored.
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_setSecurityMode(
+    cbBSM_SecurityMode securityMode,
+    cb_boolean allowPairingInNonBondableMode);
+
+/**
+ * Read current security mode.
+ * 
+ * @param pSecurityMode Security mode
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_getSecurityMode(cbBSM_SecurityMode* pSecurityMode);
+
+/**
+ * Sets the local device pairable mode.
+ *
+ * @param   pairable TRUE=pairable, FALSE=not pairable (default)
+ * @return  If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_setPairable(boolean pairable);
+
+/**
+ * Gets the local device pairable mode.
+ * 
+ * @param pPairable Pointer to return value
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_getPairable(boolean* pPairable);
+
+/**
+ * Performs bonding with a remote device. The cbBSM_BondCnf callback will
+ * be called upon success/failure.
+ *
+ * @param remoteDevice Remote BD address
+ * @param type Classic or LE
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_reqBond(
+    TBdAddr remoteDevice,
+    TBluetoothType type);
+
+/**
+ * Responds on the cbBSM_RequestPinInd callback with a pin code
+ * This is only used when either local or remote side does not support 
+ * BT 2.1 secure simple pairing.
+ *
+ * @param pBdAddress Pointer to the remote BD address
+ * @param pinCodeLength Length of the provided pin code
+ * @param pPinCode Pointer to the provided pin code
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_rspFixedPin(
+    TBdAddr* pBdAddress,
+    cb_uint8 pinCodeLength,
+    cb_uint8 *pPinCode);
+
+/**
+ * Responds the cbBSM_RequestPinInd callback. Can be used to interrupt a
+ * pairing attempt from the remote device.
+ * This is only used when either local or remote side does not support 
+ * BT 2.1 secure simple pairing.
+ *
+ * @param   pBdAddress Pointer to the remote BD address
+ * @return  If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_rspNegFixedPin(TBdAddr* pBdAddress);
+
+/**
+ * Responds on the cbBSM_UserPasskeyInd callback.
+ * This is only used when both sides support BT 2.1 secure simple pairing.
+ *
+ * @param   pBdAddress Pointer to the remote BD address
+ * @param   passkey Passkey, range: 0-999999
+ * @return  If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_rspUserPasskey(
+    TBdAddr *pBdAddress,
+    uint32 passkey);
+
+/**
+ * Responds on the cbBSM_UserPasskeyInd callback. Can be used to interrupt a
+ * pairing attempt from the remote device.
+ * This is only used when both sides support BT 2.1 secure simple pairing.
+ *
+ * @param   pBdAddress Pointer to the remote BD address
+ * @return  If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_rspNegUserPasskey(TBdAddr *pBdAddress);
+
+/**
+ * Responds on the cbBSM_UserConfirmationInd callback. Accepts the numeric value.
+ * This is only used when both sides support BT 2.1 secure simple pairing.
+ *
+ * @param   pBdAddress Pointer to the remote BD address
+ * @return  If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_rspUserConfirmation(TBdAddr* pBdAddress);
+
+/**
+ * Responds on the cbBSM_UserConfirmationInd callback. Rejects the numeric value.
+ * This is only used when both sides support BT 2.1 secure simple pairing.
+ *
+ * @param   pBdAddress Pointer to the remote BD address
+ * @return  If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_rspNegUserConfirmation(TBdAddr* pBdAddress);
+
+/**
+ * Get number of bonded devices.
+ *
+ * @param type Bond type
+ * @param pNo Pointer to return value.
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_getAllNumberBondedDevices(
+    cbBSM_BondTypes type,
+    uint32* pNo);
+
+/**
+* Get a bonded devices.
+*
+* @param deviceIndex Index of the bonded device
+* @param pBdAddr Pointer to remote BD address.
+* @param pIsLe   Should be TRUE for LE and FALSE for classic
+* @return If the operation is successful cbBSM_OK is returned.
+*/
+extern cb_int32 cbBSM_getBondedDevice(
+    uint32 deviceIndex,
+    TBdAddr* pBdAddr,
+    cb_boolean pIsLe);
+
+/**
+ * Delete a bonded device and its link keys.
+ * 
+ * @param pBdAddress to the address of the device which bond shall be deleted.
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_deleteBondedDevice(TBdAddr* pBdAddress); 
+
+/**
+ * Delete all bonded devices and link keys.
+ * 
+ * @return If the operation is successful cbBSM_OK is returned.
+ */
+extern cb_int32 cbBSM_deleteAllBondedDevices(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CB_BT_SEC_MAN_H_ */
+
+
+
+
+
+
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h
new file mode 100644
index 00000000000..b1d9992e804
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h
@@ -0,0 +1,155 @@
+/**
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : Bluetooth Serial
+ * File        : cb_bt_serial.h
+ *
+ * Description : Data management for RFCOMM based profiles such and Serial 
+ *               Port Profile (SPP).
+ *
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_bt_serial.h
+ * @brief Data management for RFCOMM based profiles such and Serial 
+ * Port Profile (SPP).
+ */
+
+#ifndef _CB_BT_SERIAL_H_
+#define _CB_BT_SERIAL_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+#include "cb_bt_conn_man.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+* DEFINES
+*=========================================================================*/
+#define cbBSE_OK                       0
+#define cbBSE_ERROR                   -1
+#define cbBSE_NO_DATA                 -2
+
+/*===========================================================================
+* TYPES
+*=========================================================================*/
+
+typedef void (*cbBSE_DataAvailEvt)(
+    cbBCM_Handle handle);
+
+typedef void (*cbBSE_WriteCnf)(
+    cbBCM_Handle handle,
+    cb_int32 status,
+    cb_uint32 nBytes,
+    cb_int32 tag);
+
+typedef struct
+{
+    cbBSE_DataAvailEvt        pfDataEvt;
+    cbBSE_WriteCnf            pfWriteCnf;
+}cbBSE_Callback;
+
+/*===========================================================================
+* FUNCTIONS
+*=========================================================================*/
+/**
+ * Initialization of Bluetooth serial manager. Called during stack
+ * initialization. Shall not be called by application.
+ * 
+ * @return None
+ */
+extern void cbBSE_init(void);
+
+/**
+ * Open a data channel.
+ * 
+ * @param   handle      Connection handle
+ * @param   pCallback   Callback for data events.
+ * @return   If the operation is successful cbBSE_OK is returned.
+ */
+extern cb_int32 cbBSE_open(
+    cbBCM_Handle handle,
+    cbBSE_Callback *pCallback);
+
+/**
+ * Send data to remote device. A data confirmation event is generated when
+ * the data has been sent and a cbBSE_write call can be done.
+ * 
+ * Detailed description optionally verbose.
+ * @param   handle  Connection handle
+ * @param   pBuf    Data pointer
+ * @param   nBytes  nBytes Size of data to be sent.
+ * @param   tag     Tag passed as argument in corresponding data confirmation callback.
+ * @return  If the operation is successful cbBSE_OK is returned.
+ */
+extern cb_int32 cbBSE_write(
+    cbBCM_Handle handle,
+    cb_uint8 *pBuf,
+    cb_uint32 nBytes,
+    cb_int32 tag);
+
+/**
+ * Get received data.
+ * 
+ * @param handle Connection handle
+ * @param   ppBuf    Pointer to data buffer
+ * @param   pLength  Pointer to buffer length variable.
+ * @return  cbBSE_OK is returned if data is available. If no data is available
+ *          then cbBSE_NO_DATA is returned.
+ */
+extern cb_int32 cbBSE_getReadBuf(
+    cbBCM_Handle handle,
+    cb_uint8 **ppBuf,
+    cb_uint32 *pLength);
+
+/**
+ * Notify that received data has been handled and underlying buffers 
+ * can be freed.
+ *
+ * @param handle Connection handle
+ * @param nBytes Number of bytes consumed.
+ * @return If the operation is successful cbBSE_OK is returned.
+ */
+extern cb_int32 cbBSE_readBufConsumed(
+    cbBCM_Handle handle,
+    cb_uint32 nBytes);
+
+/**
+ * Read max frame size for a data channel.
+ * 
+ * @param   handle      Connection handle
+ * @param   pFrameSize  Max frame size for connection.
+ * @return  If the operation is successful cbBSE_OK is returned.
+ */
+extern cb_int32 cbBSE_frameSize(cbBCM_Handle handle, cb_uint32 *pFrameSize);
+
+/**
+ * Bluetooth serial message handling. Shall not be called by application.
+ * 
+ * @param msgId Message id
+ * @param pData Pointer to message data
+ * @return None
+ */
+extern void cbBSE_handleMsg(cb_uint32 msgId, void* pData);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h
new file mode 100644
index 00000000000..ed953dcd980
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h
@@ -0,0 +1,153 @@
+/**
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : Bluetooth Serial
+ * File        : cb_bt_serial_le.h
+ *
+ * Description : Data management for Serial Port Service.
+ *
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_bt_serial_le.h
+ * @brief Data management for Serial Port Service.
+ */
+
+#ifndef _CB_BT_SERIAL_LE_H_
+#define _CB_BT_SERIAL_LE_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+#include "cb_bt_conn_man.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+* DEFINES
+*=========================================================================*/
+#define cbBSL_OK                       0
+#define cbBSL_ERROR                   -1
+#define cbBSL_NO_DATA                 -2
+
+/*===========================================================================
+* TYPES
+*=========================================================================*/
+
+typedef void (*cbBSL_DataAvailEvt)(
+    cbBCM_Handle handle);
+
+typedef void (*cbBSL_WriteCnf)(
+    cbBCM_Handle handle,
+    cb_int32 status,
+    cb_uint32 nBytes,
+    cb_int32 tag);
+
+typedef struct
+{
+    cbBSL_DataAvailEvt        pfDataEvt;
+    cbBSL_WriteCnf            pfWriteCnf;
+}cbBSL_Callback;
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+/**
+ * Initialization of Bluetooth serial manager. Called during stack
+ * initialization. Shall not be called by application.
+ * 
+ * @return None
+ */
+extern void cbBSL_init(void);
+
+/**
+ * Open a data channel.
+ * 
+ * @param   handle      Connection handle
+ * @param   pCallback   Callback for data events.
+ * @return  If the operation is successful cbBSL_OK is returned.
+ */
+extern cb_int32 cbBSL_open(
+    cbBCM_Handle handle,
+    cbBSL_Callback *pCallback);
+
+/**
+ * Send data to remote device. A data confirmation event is generated when
+ * the data has been sent and a cbBSL_write call can be done.
+ * 
+ * Detailed description optionally verbose.
+ * @param   handle  Connection handle
+ * @param   pBuf    Data pointer
+ * @param   nBytes  nBytes Size of data to be sent.
+ * @param   tag     Tag passed as argument in corresponding data confirmation callback.
+ * @return  If the operation is successful cbBSL_OK is returned.
+ */
+extern cb_int32 cbBSL_write(
+    cbBCM_Handle handle,
+    cb_uint8 *pBuf,
+    cb_uint32 nBytes,
+    cb_int32 tag);
+
+/**
+ * Get received data.
+ * 
+ * @param handle Connection handle
+ * @param   ppBuf    Pointer to data buffer
+ * @param   pLength  Pointer to buffer length variable.
+ * @return  cbBSL_OK is returned if data is available. If no data is available
+ *          then cbBSL_NO_DATA is returned.
+ */
+extern cb_int32 cbBSL_getReadBuf(
+    cbBCM_Handle handle,
+    cb_uint8 **ppBuf,
+    cb_uint32 *pLength);
+
+/**
+ * Notify that received data has been handled and underlying buffers 
+ * can be freed.
+ *
+ * @param handle Connection handle
+ * @param nBytes Number of bytes consumed.
+ * @return If the operation is successful cbBSL_OK is returned.
+ */
+extern cb_int32 cbBSL_readBufConsumed(
+    cbBCM_Handle handle,
+    cb_uint32 nBytes);
+
+/**
+ * Read max frame size for a data channel.
+ * 
+ * @param   handle      Connection handle
+ * @param   pFrameSize  Max frame size for connection.
+ * @return  If the operation is successful cbBSE_OK is returned.
+ */
+extern cb_int32 cbBSL_frameSize(cbBCM_Handle handle, cb_uint32 *pFrameSize);
+
+/**
+ * Bluetooth serial message handling. Shall not be called by application.
+ * 
+ * @param msgId Message id
+ * @param pData Pointer to message data
+ * @return None
+ */
+extern void cbBSL_handleMsg(cb_uint32 msgId, void* pData);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h
new file mode 100644
index 00000000000..6cbc8b3767d
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h
@@ -0,0 +1,253 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : Bluetooth Test
+ * File        : cb_bt_test_man.h
+ *
+ * Description : Functionality for Bluetooth radio tests and qualification.
+ *-------------------------------------------------------------------------*/
+
+/**
+* @file cb_bt_test_man.h
+* @brief Functionality for Bluetooth radio tests and qualification.
+ */
+
+#ifndef _CB_BT_TEST_MAN_H_
+#define _CB_BT_TEST_MAN_H_
+
+#include "cb_comdefs.h"
+
+#include "cb_bt_man.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+#define cbBTM_OK             (0)
+#define cbBTM_ERROR          (-1)
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+typedef enum
+{
+    cbBTM_TEST_CONF_POS,
+    cbBTM_TEST_CONF_NEG
+} cbBTM_TestEvt;
+
+typedef void (*cbBTM_TestCallback)(cbBTM_TestEvt evt);
+typedef void (*cbBTM_LeTestEndCallback)(cbBTM_TestEvt evt, cb_uint16 nbrOfPackets);
+
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Init Bluetooth test manager
+ * @returns None 
+ */
+extern void cbBTM_init(void);
+
+/**
+ * Enable Device under test mode. Used for Bluetooth Classic radio tests.
+ *
+ * @param callback Test callback used to notify if the test was successfully started.
+ * @returns cbBTM_OK is returned 
+ */
+extern cb_int32 cbBTM_enableDUT(cbBTM_TestCallback callback);
+
+/**
+ * This command operates the RF transceiver in continuous transmission mode (which is most likely used in
+ * regulatory and standardization procedures and tests, such as FCC and ETSI certifications). Activating the
+ * VS runs the TX START sequence code using the configured frequency, modulation, pattern, and power
+ * level. The VS also enables the generation of a user-defined pattern (or correcting definitions without a
+ * patch) by setting a new pattern generator (also known as a PN generator) init value and mask.
+ * based on HCI_VS_DRPb_Tester_Con_TX, HCI Opcode 0xFDCA
+ * The cbBTM_TestCallback is used to notify if the test is sucessfully started.
+ * 
+ * @param frequency Transmission frequency in MHz Range: 2402 - 2480
+ * @param modulationScheme Range: 0x00 - 0x05 where
+ *                         0x00 = CW
+ *                         0x01 = BT BR (GFSK)
+ *                         0x02 = BT EDR 2MB (p/4-DQPSK)
+ *                         0x03 = BT EDR 3MB (8-DPSK)
+ *                         0x04 = BT LE (BLE, GMSK)
+ *                         0x05 = ANT (GFSK)
+ * @param testPattern Range: 0x00 - 0x07 
+ *                         0x00 = PN9
+ *                         0x01 = PN15
+ *                         0x02 = ZOZO (101010101010101010)
+ *                         0x03 = All 1
+ *                         0x04 = All 0
+ *                         0x05 = FOFO (1111000011110000)
+ *                         0x06 = FFOO (1111111100000000)
+ *                         0x07 = Not used
+ * @param powerLevelIndex Range: 0-7: 7 = Max Output Power, 0 = Min Output Power, 0x08 (PA off) 8 = PA Off (leakage)
+ * @param reserved1 shall be set to 0
+ * @param reserved2 shall be set to 0
+ * @param callback Test callback used to notify if the test was successfully started.
+ *
+ * @return  cbBTM_OK is returned 
+ */
+extern cb_int32 cbBTM_tiDrpbTesterConTx(
+    cb_uint16 frequency,
+    cb_uint8 modulationScheme,
+    cb_uint8 testPattern,
+    cb_uint8 powerLevelIndex,
+    cb_uint32 reserved1,
+    cb_uint32 reserved2,
+    cbBTM_TestCallback callback);
+
+/**
+ *This command operates the RF transceiver in continuous reception mode (most likely used in regulatory
+ * and standardization procedures and tests, such as FCC and ETSI certifications). By activating the VS, the
+ * RX START sequence code runs, using the configured frequency, RX mode, and modulation type.
+ * based on HCI_VS_DRPb_Tester_Con_RX, HCI Opcode 0xFDCB
+ *
+ * The cbBTM_TestCallback is used to notify if the test is successfully started.
+ * @param frequency Transmission frequency in MHz Range: 2402 - 2480
+ * @param rxMode Range: 0 -3:
+ *                         0x00 = Connection mode
+ *                         0x01 = Best RF mode (ADPL closed loop) - For expert use only!
+ *                         0x02 = Low current mode (ADPLL open loop) - For expert use only!
+ *                         0x03 = Scan mode
+ * @param modulationScheme Range: 0x03 - 0x05 where
+ *                         0x03 = BT (BR, EDR 2MB, EDR 3MB)
+ *                         0x04 = BT LE (BLE, GMSK)
+ *                         0x05 = ANT (GFSK)
+ * @param callback Test callback used to notify if the test was successfully started.
+ *
+ * @return  cbBTM_OK is returned 
+ */
+extern cb_int32 cbBTM_tiDrpbTesterConRx(
+    cb_uint16 frequency,
+    cb_uint8 rxMode,
+    cb_uint8 modulationScheme,
+    cbBTM_TestCallback callback);
+
+/**
+ * 
+ * This command operates the RF transceiver in continuous reception mode (most likely used in regulatory
+ * and standardization procedures and tests, such as FCC and ETSI certifications). Activating the VS runs
+ * the RX START sequence code using the configured frequency, RX mode, and modulation type.
+ * This command emulates Bluetooth connection mode. Connection does not require a setup procedure.
+ * Based on HCI_VS_DRPb_Tester_Packet_TX_RX  HCI Opcode 0xFDCC
+ * 
+ * @param aclPacketType ACL TX packet type. Range: 0x00 - 0x0B
+ *                         0x00 = DM1
+ *                         0x01 = DH1
+ *                         0x02 = DM3
+ *                         0x03 = DH3
+ *                         0x04 = DM5
+ *                         0x05 = DH5
+ *                         0x06 = 2-DH1
+ *                         0x07 = 2-DH3
+ *                         0x08 = 2-DH5
+ *                         0x09 = 3-DH1
+ *                         0x0A = 3-DH3
+ *                         0x0B = 3-DH5
+ * @param frequencyMode 0x00 = Hopping 0x03 = Single frequency
+ * @param txSingleFrequency Transmission frequency in MHz,Range 2402 - 2480, 0xFFFF = no TX
+ * @param rxSingleFrequency Transmission frequency in MHz,Range 2402 - 2480, 0xFFFF = no RX
+ * @param aclDataPattern ACL TX packet data pattern Range: 0x00 - 0x05 
+ *                         0x00 = All 0
+ *                         0x01 = All 1
+ *                         0x02 = ZOZO (101010101010101010)
+ *                         0x03 = FOFO (1111000011110000)
+ *                         0x04 = Ordered (1, 2, 3, 4, and so on)
+ *                         0x05 = PRBS9 (pseudo-random bit sequence)
+ * @param useExtendedFeatures Shall be SET to 0
+ * @param aclDataLength ACL packet data length.
+ *                         DM1: 0 - 17 ACL packet data length in bytes
+ *                         DH1: 0 - 27
+ *                         DM3: 0 - 121
+ *                         DH3: 0 - 183
+ *                         DM5: 0 - 224
+ *                         DH5: 0 - 339
+ *                         2-DH1: 0 - 54
+ *                         2-DH3: 0 - 367
+ *                         2-DH5: 0 - 679
+ *                         3-DH1: 0 - 83
+ *                         3-DH3: 0 - 552
+ *                         3-DH5: 0 - 1021
+ * @param powerLevel       Range 0-7: 7 = Max Output Power; 0 = Min Output; Power 8 = PA Off (leakage) 0x08 (PA off)
+ * @param disableWhitening 0x00 = Enable whitening, 0x01 = Disable whitening
+ * @param prbs9Init PRBS9 Init, range 0x0000 - 0x01FF
+ * @param callback Test callback used to notify if the test was successfully started.
+ *
+ * @return cbBTM_OK is returned 
+ */
+extern cb_int32 cbBTM_tiDrpbTesterPacketTxRx(
+    cb_uint8 aclPacketType,
+    cb_uint8 frequencyMode,
+    cb_uint16 txSingleFrequency,
+    cb_uint16 rxSingleFrequency,
+    cb_uint8 aclDataPattern,
+    cb_uint8 useExtendedFeatures,
+    cb_uint16 aclDataLength,
+    cb_uint8 powerLevel,
+    cb_uint8 disableWhitening,
+    cb_uint16 prbs9Init,
+    cbBTM_TestCallback callback);
+
+/**
+ * Enable Bluetooth Low Energy Transmitter test.
+ * @param   txFreq          Transmit frequency. N = (F - 2402) / 2, Range: 0x00 to 0x27, Frequency Range : 2402 MHz to 2480 MHz,
+                            Use oxFF to generate a pseudo random hopping frequency useful for some scenarios during type approval.
+ * @param   length          Length in bytes of payload data in each packet
+ * @param   packetPayload   0x00 Pseudo-Random bit sequence 9
+ *                          0x01 Pattern of alternating bits 11110000
+ *                          0x02 Pattern of alternating bits 10101010
+ *                          0x03 Pseudo-Random bit sequence 15
+ *                          0x04 Pattern of All 1 bits
+ *                          0x05 Pattern of All 0 bits
+ *                          0x06 Pattern of alternating bits 00001111
+ *                          0x07 Pattern of alternating bits 0101
+ * @param   callback Test callback used to notify if the test was successfully started.
+ * @return  cbBTM_OK is returned 
+ */
+extern cb_int32 cbBTM_enableBleTransmitterTest(
+    cb_uint8 txFreq, 
+    cb_uint8 length,
+    cb_uint8 packetPayload, 
+    cbBTM_TestCallback callback);
+
+/**
+ * Enable Bluetooth Low Energy Receiver test.
+ * @param   rxFreq      Receive frequency. N = (F - 2402) / 2, Range: 0x00 to 0x27, Frequency Range : 2402 MHz to 2480 MHz,
+ * @param   callback    Test callback used to notify if the test was successfully started.
+ * @returns cbBTM_OK is returned 
+ */
+extern cb_int32 cbBTM_enableBleReceiverTest(
+    cb_uint8 rxFreq,
+    cbBTM_TestCallback callback);
+
+/**
+ * End Bluetooth Low Energy Receiver or Transmitter test.
+ * @param   callback    Test callback used to notify if the test was successfully ended.
+ * @returns cbBTM_OK is returned 
+ */
+extern cb_int32 cbBTM_bleTestEnd(cbBTM_LeTestEndCallback callback);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CB_BT_TEST_MAN_H_ */
+
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h
new file mode 100644
index 00000000000..255a4c056f7
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h
@@ -0,0 +1,86 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : Bluetooth utility
+ * File        : cb_bt_utils.h
+ *
+ * Description : 
+ *-------------------------------------------------------------------------*/
+
+#ifndef _CB_BT_UTILS_H_
+#define _CB_BT_UTILS_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================
+ */
+
+/**
+ * Compare two Bluetooth addresses
+ *
+ * @param addr1   Pointer to first address to compare
+ * @param addr2   Pointer to second address to compare
+ * @returns TRUE if equal otherwise FALSE
+ */
+extern cb_boolean cbBT_UTILS_cmpBdAddr(
+    TBdAddr* addr1, 
+    TBdAddr* addr2);
+
+/**
+ * Check if address in invalid i.e. {{0,0,0,0,0,0},BT_PUBLIC_ADDRESS}
+ *
+ * @param addr    Pointer to address to check
+ * @returns TRUE if invalid otherwise FALSE
+ */
+extern cb_boolean cbBT_UTILS_isInvalidBdAddr(
+    TBdAddr* addr);
+
+/**
+ * Set invalid address i.e. {{0,0,0,0,0,0},BT_PUBLIC_ADDRESS}
+ *
+ * @param addr    Pointer where to put the address
+ */
+extern void cbBT_UTILS_setInvalidBdAddr(
+    TBdAddr* addr);
+
+/**
+ * Get invalid address
+ *
+ * @returns Pointer to the invalid address
+ */
+extern const TBdAddr* cbBT_UTILS_getInvalidBdAddr(void);
+
+/**
+ * Copy Bluetooth address
+ *
+ * @param dest   Pointer to destination address
+ * @param src    Pointer to source address
+ */
+extern void cbBT_UTILS_cpyBdAddr(
+    TBdAddr* dest, 
+    TBdAddr* src);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CB_BT_UTILS_H_ */
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h
new file mode 100644
index 00000000000..3b901fa6516
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h
@@ -0,0 +1,178 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : Common Definitions
+ * File        : cb_comdefs.h
+ *
+ * Description : Common definitions.
+ *-------------------------------------------------------------------------*/
+
+#ifndef _CB_COMDEFS_H_
+#define _CB_COMDEFS_H_
+
+#include "cb_platform_basic_types.h"
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+#ifndef FALSE
+#  define FALSE                 (0)
+#endif
+
+#ifndef TRUE
+#  define TRUE                  (!FALSE)
+#endif
+
+#ifndef NULL
+#  define NULL                  ((void*)0)
+#endif
+
+/**
+ * Returns the maximum value of the two parameters.
+ */
+#define cb_MAX(a,b)              (((a) > (b)) ? (a) : (b))
+
+/**
+ * Returns the minimum value of the two parameters.
+ */
+#define cb_MIN(a,b)              (((a) < (b)) ? (a) : (b))
+
+/**
+ * Used in function definitions to declare an input parameter unused to avoid warnings.
+ */
+#ifndef cb_UNUSED
+#  define cb_UNUSED(x) x 
+#endif
+
+
+#ifndef cb_ASSERT
+#  error "No platform definition for ASSERT!"
+#endif
+
+/**
+ * Used when declaring an empty array that does not take up space in a struct.
+ * Example: struct { cb_uint8 payload[cb_EMPTY_ARRAY]; }
+ * In some compilers this is empty i.e. payload[]. While in some it requires a zero.
+ * I.e. payload[0];
+ * Use this define to get it working for your system.
+ */
+#ifndef cb_EMPTY_ARRAY
+#  define cb_EMPTY_ARRAY  (0)
+#endif
+
+
+#define cb_BIT_0        (1ul)
+#define cb_BIT_1        (1ul << 1)
+#define cb_BIT_2        (1ul << 2)
+#define cb_BIT_3        (1ul << 3)
+#define cb_BIT_4        (1ul << 4)
+#define cb_BIT_5        (1ul << 5)
+#define cb_BIT_6        (1ul << 6)
+#define cb_BIT_7        (1ul << 7)
+#define cb_BIT_8        (1ul << 8)
+#define cb_BIT_9        (1ul << 9)
+#define cb_BIT_10       (1ul << 10)
+#define cb_BIT_11       (1ul << 11)
+#define cb_BIT_12       (1ul << 12)
+#define cb_BIT_13       (1ul << 13)
+#define cb_BIT_14       (1ul << 14)
+#define cb_BIT_15       (1ul << 15)
+#define cb_BIT_16       (1ul << 16)
+#define cb_BIT_17       (1ul << 17)
+#define cb_BIT_18       (1ul << 18)
+#define cb_BIT_19       (1ul << 19)
+#define cb_BIT_20       (1ul << 20)
+#define cb_BIT_21       (1ul << 21)
+#define cb_BIT_22       (1ul << 22)
+#define cb_BIT_23       (1ul << 23)
+#define cb_BIT_24       (1ul << 24)
+#define cb_BIT_25       (1ul << 25)
+#define cb_BIT_26       (1ul << 26)
+#define cb_BIT_27       (1ul << 27)
+#define cb_BIT_28       (1ul << 28)
+#define cb_BIT_29       (1ul << 29)
+#define cb_BIT_30       (1ul << 30)
+#define cb_BIT_31       (1ul << 31)
+
+/**
+ * Clears (set to zero) a bit or bits in a variable. 
+ * @param variable The variable.
+ * @param bit The bit or bits to clear
+ */
+#define cb_CLEAR_BIT(variable,bit) ((variable) &= ~((bit)))
+
+/**
+ * Gets a bit i.e. checks if it is set in a variable.
+ *
+ * Also works to see if any of several bits are set.
+ *
+ * @param variable The variable.
+ * @param bit The bit to check if it set.
+ * @return @ref TRUE if any of the bits are set, @ref FALSE otherwise.
+ */
+#define cb_GET_BIT(variable,bit) (((variable) & ((bit))) ? TRUE : FALSE)
+
+/**
+ * Calculate the number of elements in an array.
+ *
+ * @note Won't work on pointer to array as the sizeof(pointer) is 4.
+ *
+ * @param _array The array.
+ * @return Number of elements in array.
+ */
+#define ELEMENTS_OF(_array) (sizeof((_array)) / sizeof((_array)[0]))
+
+/**
+ * Sets (set to 1) a bit or bits in a variable.
+ *
+ * @param variable The variable.
+ * @param bit The bit or bits to set in the variable.
+ */
+#define cb_SET_BIT(variable,bit) ((variable) |= (bit))
+
+#define cb_UINT8_MAX    ((cb_uint8)0xff)
+#define cb_UINT16_MAX   ((cb_uint16)0xffff)
+#define cb_UINT32_MAX   ((cb_uint32)0xffffffff)
+#define cb_INT8_MAX     ((cb_int8)0x7f)
+#define cb_INT16_MAX    ((cb_int16)0x7fff)
+#define cb_INT32_MAX    ((cb_int32)0x7fffffff)
+#define cb_INT8_MIN     ((cb_int8)0x80)
+#define cb_INT16_MIN    ((cb_int16)0x8000)
+#define cb_INT32_MIN    ((cb_int32)0x80000000)
+
+
+
+#define cb_PACKED_STRUCT_BEGIN(name) \
+    cb_PACKED_STRUCT_ATTR_PRE \
+    typedef cb_PACKED_STRUCT_ATTR_INLINE_PRE struct name##_t
+
+#define cb_PACKED_STRUCT_END(name) \
+    cb_PACKED_STRUCT_ATTR_INLINE_POST name; \
+    cb_PACKED_STRUCT_ATTR_POST
+
+#ifdef __GNUC__
+#  define DO_PRAGMA(x) _Pragma (#x)
+#  define TODO(x) DO_PRAGMA(message ("TODO - " #x))
+#else 
+#  define TODO(x)
+#endif
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+#endif /* _cb_COMDEFS_H_ */
+
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h
new file mode 100644
index 00000000000..319f45f3760
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h
@@ -0,0 +1,504 @@
+/*
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : GATT
+ * File        : cb_gatt.h
+ *
+ * Description : Definitions and types for GATT(Generic Attribute Profile) 
+ *               that are in common for both client and server.
+ *
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_gatt.h
+ *
+ * @brief Definitions and types for GATT(Generic Attribute Profile) 
+ * that are in common for both client and server.
+ */
+
+#ifndef _CB_GATT_H_
+#define _CB_GATT_H_
+
+#include "bt_types.h"
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define cbGATT_OK                        (0)
+#define cbGATT_ERROR                    (-1)
+#define cbGATT_ERROR_WRONG_STATE        (-2)
+#define cbGATT_ERROR_WRONG_HANDLE       (-3)
+#define cbGATT_ERROR_WRONG_PARAMETERS   (-4)
+
+// This should be the same as in ATT
+#define cbGATT_DEFAULT_MTU_LE           23
+
+#define cbGATT_GET_MAX_READ_MULTIPLE_MTU(mtu)               (mtu-1)
+#define cbGATT_GET_MAX_WRITE_CHARACTERISTIC_MTU(mtu)        (mtu-3)
+#define cbGATT_GET_MAX_WRITE_SIGNED_CHARACTERISTIC_MTU(mtu) (mtu-13)
+#define cbGATT_GET_MAX_NOTIFICATION_MTU(mtu)                (mtu-3)
+#define cbGATT_GET_MAX_INDICATION_MTU(mtu)                  (mtu-3)
+
+#define cbGATT_INVALID_ATTR_HANDLE      0x0000
+#define cbGATT_MIN_ATTR_HANDLE          0x0001
+#define cbGATT_MAX_ATTR_HANDLE          0xFFFF
+
+#define cbGATT_PROP_BCST        0x01 // Broadcast
+#define cbGATT_PROP_RD          0x02 // Readable
+#define cbGATT_PROP_WR_NO_RSP   0x04 // Write with no response
+#define cbGATT_PROP_WR          0x08 // Writable
+#define cbGATT_PROP_NOT         0x10 // Notify
+#define cbGATT_PROP_IND         0x20 // Indicate
+#define cbGATT_PROP_SIGN_WR     0x40 // Authenticated signed write
+#define cbGATT_PROP_EXT         0x80 // extended property
+
+#define cbGATT_PROP_EXT_REL_WR  0x0001 // Reliable write
+#define cbGATT_PROP_EXT_WR_AUX  0x0002 // auxiliary write
+#define cbGATT_CLIENT_CFG_NONE  0x0000 // Client configuration disabled
+#define cbGATT_CLIENT_CFG_NOT   0x0001 // Client notification configuration
+#define cbGATT_CLIENT_CFG_IND   0x0002 // Server indication configuration
+#define cbGATT_SERVER_CFG_BCST  0x0001 // Server broadcast configuration
+
+#define cbGATT_GET_BROADCAST_PROP(prop)             ((0x01 & prop) == 0x01)
+#define cbGATT_GET_READ_PROP(prop)                  ((0x02 & prop) == 0x02)
+#define cbGATT_GET_WRITE_WITHOUT_RSP_PROP(prop)     ((0x04 & prop) == 0x04)
+#define cbGATT_GET_WRITE_PROP(prop)                 ((0x08 & prop) == 0x08)
+#define cbGATT_GET_NOTIFY_PROP(prop)                ((0x10 & prop) == 0x10)
+#define cbGATT_GET_INDICATE_PROP(prop)              ((0x20 & prop) == 0x20)
+#define cbGATT_GET_AUTH_SIGNED_WRITES_PROP(prop)    ((0x40 & prop) == 0x40)
+#define cbGATT_GET_EXTENDED_PROP(prop)              ((0x80 & prop) == 0x80)
+
+#define cbGATT_GET_PROP_EXT_REL_WR(prop)            ((0x0001 & prop) == 0x0001)
+#define cbGATT_GET_PROP_EXT_WR_AUX(prop)            ((0x0002 & prop) == 0x0002)
+#define cbGATT_GET_CLIENT_CFG_NOT(cfg)              ((0x0001 & cfg)  == 0x0001)
+#define cbGATT_GET_CLIENT_CFG_IND(cfg)              ((0x0002 & cfg)  == 0x0002)
+#define cbGATT_GET_SERVER_CFG_BCST(cfg)             ((0x0001 & cfg)  == 0x0001)
+
+#define cbGATT_SET_BROADCAST_PROP(prop)             (prop = prop | 0x01)
+#define cbGATT_SET_READ_PROPERTY(prop)              (prop = prop | 0x02)
+#define cbGATT_SET_WRITE_WITHOUT_RSP_PROP(prop)     (prop = prop | 0x04)
+#define cbGATT_SET_WRITE_PROP(prop)                 (prop = prop | 0x08)
+#define cbGATT_SET_NOTIFY_PROP(prop)                (prop = prop | 0x10)
+#define cbGATT_SET_INDICATE_PROP(prop)              (prop = prop | 0x20)
+#define cbGATT_SET_AUTH_SIGNED_WRITES_PROP(prop)    (prop = prop | 0x40)
+#define cbGATT_SET_EXTENDED_PROP(prop)              (prop = prop | 0x80)
+
+#define cbGATT_SET_PROP_EXT_REL_WR(prop)            (prop = prop | 0x0001)
+#define cbGATT_SET_PROP_EXT_WR_AUX(prop)            (prop = prop | 0x0002)
+#define cbGATT_SET_CLIENT_CFG_NOT(cfg)              (cfg = cfg | 0x0001)
+#define cbGATT_SET_CLIENT_CFG_IND(cfg)              (cfg = cfg | 0x0002)
+#define cbGATT_SET_SERVER_CFG_BCST(cfg)             (cfg = cfg | 0x0001)
+
+// Below specification level as of 2011-09-13
+#define cbGATT_SERVICE_GENERIC_ACCESS               0x1800    // 0.5
+#define cbGATT_SERVICE_GENERIC_ATTRIBUTE            0x1801    // 0.5
+#define cbGATT_SERVICE_IMMEDIATE_ALERT              0x1802    // Adopted
+#define cbGATT_SERVICE_LINK_LOSS                    0x1803    // Adopted
+#define cbGATT_SERVICE_TX_POWER                     0x1804    // Adopted
+#define cbGATT_SERVICE_CURRENT_TIME                 0x1805    // Prototype
+#define cbGATT_SERVICE_REFERENCE_TIME_UPDATE        0x1806    // Prototype
+#define cbGATT_SERVICE_NEXT_DST_CHANGE              0x1807    // Prototype
+#define cbGATT_SERVICE_HEALTH_THERMOMETER           0x1809    // Adopted
+#define cbGATT_SERVICE_DEVICE_INFORMATION           0x180A    // Adopted
+#define cbGATT_SERVICE_NETWORK_AVAILABILITY         0x180B    // 0.9
+#define cbGATT_SERVICE_WATCHDOG                     0x180C    // 0.5
+#define cbGATT_SERVICE_HEART_RATE                   0x180D    // Adopted
+#define cbGATT_SERVICE_PHONE_ALERT_STATUS           0x180E    // Prototype
+#define cbGATT_SERVICE_BATTERY_SERVICE              0x180F    // Prototype
+#define cbGATT_SERVICE_BLOOD_PRESSURE               0x1810    // 0.9
+#define cbGATT_SERVICE_ALERT_NOTIFICATION           0x1811    // Prototype
+#define cbGATT_SERVICE_HUMAN_INTERFACE_DEVICE       0x1812    // 0.5
+#define cbGATT_SERVICE_SCAN_PARAMETER               0x1813    // 0.5
+
+#define cbGATT_PRIMARY_SERVICE_DECL                 0x2800
+#define cbGATT_SECONDARY_SERVICE_DECL               0x2801
+#define cbGATT_INCLUDE_DECL                         0x2802
+#define cbGATT_CHAR_DECL                            0x2803
+#define cbGATT_CHAR_EXT_PROP                        0x2900
+#define cbGATT_CHAR_USER_DESC                       0x2901
+#define cbGATT_CLIENT_CHAR_CONFIG                   0x2902
+#define cbGATT_SERVER_CHAR_CONFIG                   0x2903
+#define cbGATT_CHAR_FORMAT                          0x2904
+#define cbGATT_CHAR_AGGR_FORMAT                     0x2905
+
+#define cbGATT_CHAR_GAP_DEVICE_NAME                 0x2A00    // Adopted
+#define cbGATT_CHAR_GAP_APPEARANCE                  0x2A01    // Adopted
+#define cbGATT_CHAR_GAP_PERIP_PRIV                  0x2A02    // Adopted
+#define cbGATT_CHAR_GAP_RECONN_ADDR                 0x2A03    // Adopted
+#define cbGATT_CHAR_GAP_CONN_PARAMS                 0x2A04    // Adopted
+#define cbGATT_CHAR_GATT_SVC_CHANGED                0x2A05    // Adopted
+#define cbGATT_CHAR_ALERT_LEVEL                     0x2A06    // Adopted
+#define cbGATT_CHAR_TX_POWER_LEVEL                  0x2A07    // Adopted
+#define cbGATT_CHAR_DATE_TIME                       0x2A08    // Adopted
+#define cbGATT_CHAR_DAY_OF_WEEK                     0x2A09    // Prototype
+#define cbGATT_CHAR_DAY_DATE_TIME                   0x2A0A    // Prototype
+#define cbGATT_CHAR_EXACT_TIME_100                  0x2A0B    // 0.9
+#define cbGATT_CHAR_EXACT_TIME_256                  0x2A0C    // Prototype
+#define cbGATT_CHAR_DST_OFFSET                      0x2A0D    // Prototype
+#define cbGATT_CHAR_TIME_ZONE                       0x2A0E    // Prototype
+#define cbGATT_CHAR_LOCAL_TIME_INFORMATION          0x2A0F    // Prototype
+#define cbGATT_CHAR_SECONDARY_TIME_ZONE             0x2A10    // 0.9
+#define cbGATT_CHAR_TIME_WITH_DST                   0x2A11    // Prototype
+#define cbGATT_CHAR_TIME_ACCURACY                   0x2A12    // Prototype
+#define cbGATT_CHAR_TIME_SOURCE                     0x2A13    // Prototype
+#define cbGATT_CHAR_REFERENCE_TIME_INFORMATION      0x2A14    // Prototype
+#define cbGATT_CHAR_TIME_BROADCAST                  0x2A15    // 0.9
+#define cbGATT_CHAR_TIME_UPDATE_CONTROL_POINT       0x2A16    // Prototype
+#define cbGATT_CHAR_TIME_UPDATE_STATE               0x2A17    // Prototype
+#define cbGATT_CHAR_BOOLEAN                         0x2A18    // 0.9
+#define cbGATT_CHAR_BATTERY_LEVEL                   0x2A19    // 0.9
+#define cbGATT_CHAR_BATTERY_POWER_STATE             0x2A1A    // 0.9
+#define cbGATT_CHAR_BATTERY_LEVEL_STATE             0x2A1B    // 0.9
+#define cbGATT_CHAR_TEMP_MEASUREMENT                0x2A1C    // Adopted
+#define cbGATT_CHAR_TEMP_TYPE                       0x2A1D    // Adopted
+#define cbGATT_CHAR_INTERMEDIATE_TEMP               0x2A1E    // Adopted
+#define cbGATT_CHAR_TEMP_CELSIUS                    0x2A1F    // 0.9
+#define cbGATT_CHAR_TEMP_FAHRENHEIT                 0x2A20    // 0.9
+#define cbGATT_CHAR_MEASUREMENT_INTERVAL            0x2A21    // Adopted
+#define cbGATT_CHAR_SYSTEM_ID                       0x2A23    // Adopted
+#define cbGATT_CHAR_MODEL_NUMBER_STRING             0x2A24    // Adopted
+#define cbGATT_CHAR_SERIAL_NUMBER_STRING            0x2A25    // Adopted
+#define cbGATT_CHAR_FIRMWARE_REV_STRING             0x2A26    // Adopted
+#define cbGATT_CHAR_HARDWARE_REV_STRING             0x2A27    // Adopted
+#define cbGATT_CHAR_SOFTWARE_REV_STRING             0x2A28    // Adopted
+#define cbGATT_CHAR_MANUFACTURER_NAME_STRING        0x2A29    // Adopted
+#define cbGATT_CHAR_IEEE_REG_CERT_DATA_LIST         0x2A2A    // Adopted
+#define cbGATT_CHAR_CURRENT_TIME                    0x2A2B    // Prototype
+#define cbGATT_CHAR_ELEVATION                       0x2A2C    // 0.5
+#define cbGATT_CHAR_LATITUDE                        0x2A2D    // 0.5
+#define cbGATT_CHAR_LONGITUDE                       0x2A2E    // 0.5
+#define cbGATT_CHAR_POSITION_2D                     0x2A2F    // 0.5
+#define cbGATT_CHAR_POSITION_3D                     0x2A30    // 0.5
+#define cbGATT_CHAR_VENDOR_ID_V1_1                  0x2A31    // 0.5
+#define cbGATT_CHAR_PRODUCT_ID                      0x2A32    // 0.5
+#define cbGATT_CHAR_HID_VERSION                     0x2A33    // 0.5
+#define cbGATT_CHAR_VENDOR_ID_SOURCE                0x2A34    // 0.5
+#define cbGATT_CHAR_BLOOD_PRESSURE_MEASUREMENT      0x2A35    // 0.9
+#define cbGATT_CHAR_INTERMEDIATE_BLOOD_PRESSURE     0x2A36    // 0.9
+#define cbGATT_CHAR_HEART_RATE_MEASUREMENT          0x2A37    // Adopted
+#define cbGATT_CHAR_BODY_SENSOR_LOCATION            0x2A38    // Adopted
+#define cbGATT_CHAR_HEART_RATE_CONTROL_POINT        0x2A39    // Adopted
+#define cbGATT_CHAR_REMOVABLE                       0x2A3A    // 0.5
+#define cbGATT_CHAR_SERVICE_REQUIRED                0x2A3B    // 0.9
+#define cbGATT_CHAR_SCIENTIFIC_TEMP_CELSIUS         0x2A3C    // 0.9
+#define cbGATT_CHAR_STRING                          0x2A3D    // 0.9
+#define cbGATT_CHAR_NETWORK_AVAILABILITY            0x2A3E    // 0.9
+#define cbGATT_CHAR_ALERT_STATUS                    0x2A3F    // Prototype
+#define cbGATT_CHAR_RINGER_CONTROL_POINT            0x2A40    // Prototype
+#define cbGATT_CHAR_RINGER_SETTING                  0x2A41    // Prototype
+#define cbGATT_CHAR_ALERT_CATEGORY_ID_BIT_MASK      0x2A42    // 0.9
+#define cbGATT_CHAR_ALERT_CATEGORY_ID               0x2A43    // 0.9
+#define cbGATT_CHAR_ALERT_NOTIF_CONTROL_POINT       0x2A44    // 0.9
+#define cbGATT_CHAR_UNREAD_ALERT_STATUS             0x2A45    // 0.9
+#define cbGATT_CHAR_NEW_ALERT                       0x2A46    // 0.9
+#define cbGATT_CHAR_SUPPORTED_NEW_ALERT_CATEGORY    0x2A47    // 0.9
+#define cbGATT_CHAR_SUPPORTED_UNREAD_ALERT_CATEGORY 0x2A48    // 0.9
+#define cbGATT_CHAR_BLOOD_PRESSURE_FEATURE          0x2A49    // 0.9
+
+/*==============================================================================
+ * TYPES
+ *==============================================================================
+ */
+
+typedef enum
+{
+    cbGATT_WRITE_METHOD_WITH_RSP,
+    cbGATT_WRITE_METHOD_NO_RSP,
+    cbGATT_WRITE_METHOD_SIGN,
+    cbGATT_WRITE_METHOD_RELIABLE_PREPARE,
+} cbGATT_WriteMethod;
+
+typedef enum
+{
+    cbGATT_UNIT_UNITLESS                                                  = 0x2700,
+    cbGATT_UNIT_LENGTH_METRE                                              = 0x2701,
+    cbGATT_UNIT_MASS_KILOGRAM                                             = 0x2702,
+    cbGATT_UNIT_TIME_SECOND                                               = 0x2703,
+    cbGATT_UNIT_ELECTRIC_CURRENT_AMPERE                                   = 0x2704,
+    cbGATT_UNIT_THERMODYNAMIC_TEMPERATURE_KELVIN                          = 0x2705,
+    cbGATT_UNIT_AMOUNT_OF_SUBSTANCE_MOLE                                  = 0x2706,
+    cbGATT_UNIT_LUMINOUS_INTENSITY_CANDELA                                = 0x2707,
+    cbGATT_UNIT_AREA_SQUARE_METRES                                        = 0x2710,
+    cbGATT_UNIT_VOLUME_CUBIC_METRES                                       = 0x2711,
+    cbGATT_UNIT_VELOCITY_METRES_PER_SECOND                                = 0x2712,
+    cbGATT_UNIT_ACCELERATION_METRES_PER_SECOND_SQUARED                    = 0x2713,
+    cbGATT_UNIT_WAVENUMBER_RECIPROCAL_METRE                               = 0x2714,
+    cbGATT_UNIT_DENSITY_KILOGRAM_PER_CUBIC_METRE                          = 0x2715,
+    cbGATT_UNIT_SURFACE_DENSITY_KILOGRAM_PER_SQUARE_METRE                 = 0x2716,
+    cbGATT_UNIT_SPECIFIC_VOLUME_CUBIC_METRE_PER_KILOGRAM                  = 0x2717,
+    cbGATT_UNIT_CURRENT_DENSITY_AMPERE_PER_SQUARE_METRE                   = 0x2718,
+    cbGATT_UNIT_MAGNETIC_FIELD_STRENGTH_AMPERE_PER_METRE                  = 0x2719,
+    cbGATT_UNIT_AMOUNT_CONCENTRATION_MOLE_PER_CUBIC_METRE                 = 0x271A,
+    cbGATT_UNIT_MASS_CONCENTRATION_KILOGRAM_PER_CUBIC_METRE               = 0x271B,
+    cbGATT_UNIT_LUMINANCE_CANDELA_PER_SQUARE_METRE                        = 0x271C,
+    cbGATT_UNIT_REFRACTIVE_INDEX                                          = 0x271D,
+    cbGATT_UNIT_RELATIVE_PERMEABILITY                                     = 0x271E,
+    cbGATT_UNIT_PLANE_ANGLE_RADIAN                                        = 0x2720,
+    cbGATT_UNIT_SOLID_ANGLE_STERADIAN                                     = 0x2721,
+    cbGATT_UNIT_FREQUENCY_HERTZ                                           = 0x2722,
+    cbGATT_UNIT_FORCE_NEWTON                                              = 0x2723,
+    cbGATT_UNIT_PRESSURE_PASCAL                                           = 0x2724,
+    cbGATT_UNIT_ENERGY_JOULE                                              = 0x2725,
+    cbGATT_UNIT_POWER_WATT                                                = 0x2726,
+    cbGATT_UNIT_ELECTRIC_CHARGE_COULOMB                                   = 0x2727,
+    cbGATT_UNIT_ELECTRIC_POTENTIAL_DIFFERENCE_VOLT                        = 0x2728,
+    cbGATT_UNIT_CAPACITANCE_FARAD                                         = 0x2729,
+    cbGATT_UNIT_ELECTRIC_RESISTANCE_OHM                                   = 0x272A,
+    cbGATT_UNIT_ELECTRIC_CONDUCTANCE_SIEMENS                              = 0x272B,
+    cbGATT_UNIT_MAGNETIC_FLEX_WEBER                                       = 0x272C,
+    cbGATT_UNIT_MAGNETIC_FLEX_DENSITY_TESLA                               = 0x272D,
+    cbGATT_UNIT_INDUCTANCE_HENRY                                          = 0x272E,
+    cbGATT_UNIT_THERMODYNAMIC_TEMPERATURE_DEGREE_CELSIUS                  = 0x272F,
+    cbGATT_UNIT_LUMINOUS_FLUX_LUMEN                                       = 0x2730,
+    cbGATT_UNIT_ILLUMINANCE_LUX                                           = 0x2731,
+    cbGATT_UNIT_ACTIVITY_REFERRED_TO_A_RADIONUCLIDE_BECQUEREL             = 0x2732,
+    cbGATT_UNIT_ABSORBED_DOSE_GRAY                                        = 0x2733,
+    cbGATT_UNIT_DOSE_EQUIVALENT_SIEVERT                                   = 0x2734,
+    cbGATT_UNIT_CATALYTIC_ACTIVITY_KATAL                                  = 0x2735,
+    cbGATT_UNIT_DYNAMIC_VISCOSITY_PASCAL_SECOND                           = 0x2740,
+    cbGATT_UNIT_MOMENT_OF_FORCE_NEWTON_METRE                              = 0x2741,
+    cbGATT_UNIT_SURFACE_TENSION_NEWTON_PER_METRE                          = 0x2742,
+    cbGATT_UNIT_ANGULAR_VELOCITY_RADIAN_PER_SECOND                        = 0x2743,
+    cbGATT_UNIT_ANGULAR_ACCELERATION_RADIAN_PER_SECOND_SQUARED            = 0x2744,
+    cbGATT_UNIT_HEAT_FLUX_DENSITY_WATT_PER_SQUARE_METRE                   = 0x2745,
+    cbGATT_UNIT_HEAT_CAPACITY_JOULE_PER_KELVIN                            = 0x2746,
+    cbGATT_UNIT_SPECIFIC_HEAT_CAPACITY_JOULE_PER_KILOGRAM_KELVIN          = 0x2747,
+    cbGATT_UNIT_SPECIFIC_ENERGY_JOULE_PER_KILOGRAM                        = 0x2748,
+    cbGATT_UNIT_THERMAL_CONDUCTIVITY_WATT_PER_METRE_KELVIN                = 0x2749,
+    cbGATT_UNIT_ENERGY_DENSITY_JOULE_PER_CUBIC_METRE                      = 0x274A,
+    cbGATT_UNIT_ELECTRIC_FIELD_STRENGTH_VOLT_PER_METRE                    = 0x274B,
+    cbGATT_UNIT_ELECTRIC_CHARGE_DENSITY_COULOMB_PER_CUBIC_METRE           = 0x274C,
+    cbGATT_UNIT_SURFACE_CHARGE_DENSITY_COULOMB_PER_SQUARE_METRE           = 0x274D,
+    cbGATT_UNIT_ELECTRIC_FLUX_DENSITY_COULOMB_PER_SQUARE_METRE            = 0x274E,
+    cbGATT_UNIT_PERMITTIVITY_FARAD_PER_METRE                              = 0x274F,
+    cbGATT_UNIT_PERMEABILITY_HENRY_PER_METRE                              = 0x2750,
+    cbGATT_UNIT_MOLAR_ENERGY_JOULE_PER_MOLE                               = 0x2751,
+    cbGATT_UNIT_MOLAR_ENTROPY_JOULE_PER_MOLE_KELVIN                       = 0x2752,
+    cbGATT_UNIT_EXPOSURE_COULOMB_PER_KILOGRAM                             = 0x2753,
+    cbGATT_UNIT_ABSORBED_DOSE_RATE_GRAY_PER_SECOND                        = 0x2754,
+    cbGATT_UNIT_RADIANT_INTENSITY_WATT_PER_STERADIAN                      = 0x2755,
+    cbGATT_UNIT_RADIANCE_WATT_PER_SQUARE_METER_STERADIAN                  = 0x2756,
+    cbGATT_UNIT_CATALYTIC_ACTIVITY_CONCENTRATION_KATAL_PER_CUBIC_METRE    = 0x2757,
+    cbGATT_UNIT_TIME_MINUTE                                               = 0x2760,
+    cbGATT_UNIT_TIME_HOUR                                                 = 0x2761,
+    cbGATT_UNIT_TIME_DAY                                                  = 0x2762,
+    cbGATT_UNIT_PLANE_ANGLE_DEGREE                                        = 0x2763,
+    cbGATT_UNIT_PLANE_ANGLE_MINUTE                                        = 0x2764,
+    cbGATT_UNIT_PLANE_ANGLE_SECOND                                        = 0x2765,
+    cbGATT_UNIT_AREA_HECTARE                                              = 0x2766,
+    cbGATT_UNIT_VOLUME_LITRE                                              = 0x2767,
+    cbGATT_UNIT_MASS_TONNE                                                = 0x2768,
+    cbGATT_UNIT_PRESSURE_BAR                                              = 0x2780,
+    cbGATT_UNIT_PRESSURE_MILLIMETRE_OF_MERCURY                            = 0x2781,
+    cbGATT_UNIT_LENGTH_ANGSTROM                                           = 0x2782,
+    cbGATT_UNIT_LENGTH_NAUTICAL_MILE                                      = 0x2783,
+    cbGATT_UNIT_AREA_BARN                                                 = 0x2784,
+    cbGATT_UNIT_VELOCITY_KNOT                                             = 0x2785,
+    cbGATT_UNIT_LOGARITHMIC_RADIO_QUANTITY_NEPER                          = 0x2786,
+    cbGATT_UNIT_LOGARITHMIC_RADIO_QUANTITY_BEL                            = 0x2787,
+    cbGATT_UNIT_LENGTH_YARD                                               = 0x27A0,
+    cbGATT_UNIT_LENGTH_PARSEC                                             = 0x27A1,
+    cbGATT_UNIT_LENGTH_INCH                                               = 0x27A2,
+    cbGATT_UNIT_LENGTH_FOOT                                               = 0x27A3,
+    cbGATT_UNIT_LENGTH_MILE                                               = 0x27A4,
+    cbGATT_UNIT_PRESSURE_POUND_FORCE_PER_SQUARE_INCH                      = 0x27A5,
+    cbGATT_UNIT_VELOCITY_KILOMETRE_PER_HOUR                               = 0x27A6,
+    cbGATT_UNIT_VELOCITY_MILE_PER_HOUR                                    = 0x27A7,
+    cbGATT_UNIT_ANGULAR_VELOCITY_REVOLUTION_PER_MINUTE                    = 0x27A8,
+    cbGATT_UNIT_ENERGY_GRAM_CALORIE                                       = 0x27A9,
+    cbGATT_UNIT_ENERGY_KILOGRAM_CALORIE                                   = 0x27AA,
+    cbGATT_UNIT_ENERGY_KILOWATT_HOUR                                      = 0x27AB,
+    cbGATT_UNIT_THERMODYNAMIC_TEMPERATURE_DEGREE_FAHRENHEIT               = 0x27AC,
+    cbGATT_UNIT_PERCENTAGE                                                = 0x27AD,
+    cbGATT_UNIT_PER_MILLE                                                 = 0x27AE,
+    cbGATT_UNIT_PERIOD_BEATS_PER_MINUTE                                   = 0x27AF,
+    cbGATT_UNIT_ELECTRIC_CHARGE_AMPERE_HOURS                              = 0x27B0,
+    cbGATT_UNIT_MASS_DENSITY_MILLIGRAM_PER_DECILITRE                      = 0x27B1,
+    cbGATT_UNIT_MASS_DENSITY_MILLIMOLE_PER_LITRE                          = 0x27B2,
+    cbGATT_UNIT_TIME_YEAR                                                 = 0x27B3,
+    cbGATT_UNIT_TIME_MONTH                                                = 0x27B4,
+} cbGATT_Unit;
+
+typedef enum
+{
+
+    // Note, check http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.cbGATT.characteristic_presentation_format.xml
+    // for any changes
+    cbGATT_FORMAT_TYPE_BOOLEAN =  0x01,
+    cbGATT_FORMAT_TYPE_2BIT    =  0x02,
+    cbGATT_FORMAT_TYPE_NIBBLE  =  0x03,
+    cbGATT_FORMAT_TYPE_UINT8   =  0x04,
+    cbGATT_FORMAT_TYPE_UINT12  =  0x05,
+    cbGATT_FORMAT_TYPE_UINT16  =  0x06,
+    cbGATT_FORMAT_TYPE_UINT24  =  0x07,
+    cbGATT_FORMAT_TYPE_UINT32  =  0x08,
+    cbGATT_FORMAT_TYPE_UINT48  =  0x09,
+    cbGATT_FORMAT_TYPE_UINT64  =  0x0A,
+    cbGATT_FORMAT_TYPE_UINT128 =  0x0B,
+    cbGATT_FORMAT_TYPE_SINT8   =  0x0C,
+    cbGATT_FORMAT_TYPE_SINT12  =  0x0D,
+    cbGATT_FORMAT_TYPE_SINT16  =  0x0E,
+    cbGATT_FORMAT_TYPE_SINT24  =  0x0F,
+    cbGATT_FORMAT_TYPE_SINT32  =  0x10,
+    cbGATT_FORMAT_TYPE_SINT48  =  0x11,
+    cbGATT_FORMAT_TYPE_SINT64  =  0x12,
+    cbGATT_FORMAT_TYPE_SINT128 =  0x13,
+    cbGATT_FORMAT_TYPE_FLOAT32 =  0x14,
+    cbGATT_FORMAT_TYPE_FLOAT64 =  0x15,
+    cbGATT_FORMAT_TYPE_SFLOAT  =  0x16,
+    cbGATT_FORMAT_TYPE_FLOAT   =  0x17,
+    cbGATT_FORMAT_TYPE_DUINT16 =  0x18,
+    cbGATT_FORMAT_TYPE_UTF8S   =  0x19,
+    cbGATT_FORMAT_TYPE_UTF16S  =  0x1A,
+    cbGATT_FORMAT_TYPE_STRUCT  =  0x1B,
+} cbGATT_FormatType;
+
+typedef enum
+{
+    // This should map to ATT_TRole
+    cbGATT_ROLE_CLIENT = 0,
+    cbGATT_ROLE_SERVER = 1,
+    cbGATT_ROLE_BOTH   = 2
+} cbGATT_Role;
+
+typedef enum
+{
+    cbGATT_NAMESPACE_BT_SIG = 0x01,
+} cbGATT_Namespace;
+
+typedef enum
+{
+    cbGATT_NAMESPACE_DESC_UNKNOWN = 0x0000,
+} cbGATT_NamespaceDesc;
+
+typedef struct  
+{
+    cbGATT_FormatType    format;
+    cb_uint8             exponent;
+    cbGATT_Unit          unit;
+    cbGATT_Namespace     gattNamespace;
+    cbGATT_NamespaceDesc namespaceDesc;
+} cbGATT_CharFormat;
+
+// This enum must match ATT_TErrorCode for the first two parts
+// (not the GATT specific)
+typedef enum
+{
+    cbGATT_ERROR_CODE_OK                               = 0x00,
+    cbGATT_ERROR_CODE_INVALID_HANDLE                   = 0x01,
+    cbGATT_ERROR_CODE_READ_NOT_PERMITTED               = 0x02,
+    cbGATT_ERROR_CODE_WRITE_NOT_PERMITTED              = 0x03,
+    cbGATT_ERROR_CODE_INVALID_PDU                      = 0x04,
+    cbGATT_ERROR_CODE_INSUFFICIENT_AUTHENTICATION      = 0x05,
+    cbGATT_ERROR_CODE_REQUEST_NOT_SUPPORTED            = 0x06,
+    cbGATT_ERROR_CODE_INVALID_OFFSET                   = 0x07,
+    cbGATT_ERROR_CODE_INSUFFICIENT_AUTHORIZATION       = 0x08,
+    cbGATT_ERROR_CODE_PREPARE_FULL_QUEUE               = 0x09,
+    cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND              = 0x0A,
+    cbGATT_ERROR_CODE_ATTRIBUTE_NOT_LONG               = 0x0B,
+    cbGATT_ERROR_CODE_INSUFFICIENT_ENCRYPT_KEY_SIZE    = 0x0C,
+    cbGATT_ERROR_CODE_INVALID_ATTRIBUTE_VALUE_LENGTH   = 0x0D,
+    cbGATT_ERROR_CODE_UNLIKELY_ERROR                   = 0x0E,
+    cbGATT_ERROR_CODE_INSUFFICIENT_ENCRYPTION          = 0x0F,
+    cbGATT_ERROR_CODE_UNSUPPORTED_GROUP_TPYE           = 0x10,
+    cbGATT_ERROR_CODE_INSUFFICIENT_RESOURCES           = 0x11,
+
+    cbGATT_ERROR_CODE_OUT_OF_RANGE                     = 0xFF,
+    cbGATT_ERROR_CODE_PROCEDURE_ALREADY_IN_PROGRESS    = 0xFE,
+    cbGATT_ERROR_CODE_IMPROPER_CLIENT_CHAR_CFG         = 0xFD,
+
+    // Special error codes not according to BT spec. 
+    // Will never be sent over the air.
+    cbGATT_ERROR_CODE_TRANSACTION_TIMEOUT              = 0x80,
+    cbGATT_ERROR_CODE_DISCONNECTED                     = 0x81,
+    cbGATT_ERROR_CODE_RELIABLE_CHECK_FAILED            = 0x82,
+    cbGATT_ERROR_CODE_DELAYED_RSP                      = 0x83,
+} cbGATT_ErrorCode;
+
+
+typedef enum
+{
+    // This must map to ATT_TUuidFormat
+    cbGATT_UUID_16  = 0x01,
+    cbGATT_UUID_128 = 0x02
+} cbGATT_UuidFormat;
+
+typedef enum
+{
+    cbGATT_FINAL_DATA  = 0x00,
+    cbGATT_MORE_DATA   = 0x01,
+    cbGATT_CANCEL_DATA = 0x02
+} cbGATT_WriteLongCharFlag;
+
+typedef struct
+{
+    // This must map to ATT_TUuid
+    union
+    {
+        cb_uint16 uuid16;
+        cb_uint8  uuid128[16];
+    };
+    cbGATT_UuidFormat format;
+} cbGATT_Uuid;
+
+/**
+ * Called when an ACL connection is established
+ * @param   handle          Connection handle
+ * @param   errorCode       Connect error code
+ * @param   role            TODO Add a proper type for role client/server master/slave central/peripheral
+ * @param   peerBdAddress   Address of remote device
+ * @param   connInterval    Connection interval
+ * @param   connLatency     Connection latency
+ * @param   connTmo         Connection timeout
+ * @param   masterClkAccuracy Master clock accuracy
+ * @return  None
+ */
+typedef void (*cbGATT_ConnComplEvt)(
+    TConnHandle         handle, 
+    TErrorCode          errorCode, 
+    cb_uint8            role, 
+    TBdAddr             peerBdAddress, 
+    cb_uint16           connInterval,
+    cb_uint16           connLatency,
+    cb_uint16           connTmo,
+    cb_uint8            masterClkAccuracy);  
+/** 
+ * Called when ACL connection is lost.
+ * @param   handle      Connection handle
+ * @param   errorCode   Disconnect error code
+ * @return  None
+ */
+typedef void (*cbGATT_DisconnectEvt)(
+    TConnHandle         handle, 
+    TErrorCode          errorCode);
+
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h
new file mode 100644
index 00000000000..d41f6544229
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h
@@ -0,0 +1,652 @@
+/*
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component    GATT
+ * File         cb_gatt_client.h
+ *
+ * Description  Definitions and types for GATT client functionality
+ *
+ */
+
+/**
+ * @file cb_gatt_client.h
+ *
+ * This file contains all GATT client functionality. There are some restrictions 
+ * on how this API is used.
+ * - Pointer data in callbacks are only valid in the context of the callback
+ * - Only one request at a time should be done from each app(app handle). The 
+ *   app must wait until all responses from an outstanding request have been 
+ *   received.
+ * - In the callback of the request another request can not be done except when
+ *   - The request is interrupted by setting the return value to FALSE
+ *     or when in the last callback which contains an error code.
+ *   - Most of the GATT requests can be interrupted by returning FALSE in the 
+ *   callback.
+ *
+ * See Bluetooth 4.0 specification for more info on GATT and ATT chapters:
+ * https://www.bluetooth.org/en-us/specification/adopted-specifications
+ *
+ */
+
+#ifndef _CB_GATT_CLIENT_H_
+#define _CB_GATT_CLIENT_H_
+
+#include "bt_types.h"
+#include "cb_gatt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*==============================================================================
+ * TYPES
+ *==============================================================================
+ */
+
+/**
+ * Callback for discover all primary services. This callback will be called
+ * for each primary service found.
+ * @param connHandle        Connection handle
+ * @param errorCode         cbGATT_ERROR_CODE_OK when succeeded
+ *                          cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback
+ *                          when search is finished.
+ *                          cbGATT_ERROR_CODE_ on failure
+ * @param startGroupHandle  Start handle of the service
+ * @param endGroupHandle    End handle of the service
+ * @param pUuid             Pointer to UUID of the service
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_DiscoverAllPrimaryServicesCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode,
+    cb_uint16           startGroupHandle,
+    cb_uint16           endGroupHandle,
+    cbGATT_Uuid*        pUuid);
+
+/**
+ * Callback for discover all secondary services. This callback will be called 
+ * for each secondary service found.
+ * @param connHandle Connection handle
+ * @param errorCode         cbGATT_ERROR_CODE_OK when succeeded
+ *                          cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback
+ *                          when search is finished.
+ *                          cbGATT_ERROR_CODE on failure
+ * @param startGroupHandle  Start handle of the service
+ * @param endGroupHandle    End handle of the service
+ * @param pUuid             Pointer to UUID of the service
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_DiscoverAllSecondaryServicesCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode,
+    cb_uint16           startGroupHandle,
+    cb_uint16           endGroupHandle,
+    cbGATT_Uuid*        pUuid);
+
+/**
+ * Callback for discover all primary services by UUID. This callback will be
+ * called for each primary service found.
+ * @param connHandle        Connection handle
+ * @param errorCode         cbGATT_ERROR_CODE_OK when succeeded
+ *                          cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback
+ *                          when search is finished.
+ *                          cbGATT_ERROR_CODE_* on failure
+ * @param startGroupHandle  Start handle of the service
+ * @param endGroupHandle    End handle of the service
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_DiscoverPrimaryServiceByUuidCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode,
+    cb_uint16           startHandle,
+    cb_uint16           endHandle);
+
+/**
+ * Callback for find included services. This callback will be called 
+ * for each service found.
+ * @param connHandle        Connection handle
+ * @param errorCode         cbGATT_ERROR_CODE_OK when succeeded
+ *                          cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback
+ *                          when search is finished.
+ *                          cbGATT_ERROR_CODE_* on failure
+ * @param startGroupHandle  Start handle of the service
+ * @param endGroupHandle    End handle of the service
+ * @param pUuid             Pointer to UUID of the service
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_FindIncludedServicesCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode,
+    cb_uint16           attrHandle,
+    cb_uint16           startGroupHandle,
+    cb_uint16           endGroupHandle,
+    cbGATT_Uuid*        pUuid);
+
+/**
+ * Callback for discover all characteristics of service. This callback will 
+ * be called for each characteristic found.
+ * @param connHandle    Connection handle
+ * @param errorCode     cbGATT_ERROR_CODE_OK when succeeded
+ *                      cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback
+ *                      when search is finished.
+ *                      cbGATT_ERROR_CODE_* on failure
+ * @param attrHandle    Attribute handle of the characteristic
+ * @param properties    Bitmap of properties of the characteristic.
+ *                      See cbGATT_PROP_*.
+ * @param valueHandle   Attribute handle of the characteristic value.
+ *                      This is where the actual data is located.
+ * @param pUuid         Pointer to UUID of the characteristic
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_DiscoverAllCharacteristicsOfServiceCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode,
+    cb_uint16           attrHandle,
+    cb_uint8            properties,
+    cb_uint16           valueHandle,
+    cbGATT_Uuid*        pUuid);
+
+/**
+ * Callback for discover all descriptors of a characteristic. This callback 
+ * will be called for each descriptor found.
+ * @param connHandle        Connection handle
+ * @param errorCode         cbGATT_ERROR_CODE_OK when succeeded
+ *                          cbGATT_ERROR_CODE_ATTRIBUTE_NOT_FOUND as last callback
+ *                          when search is finished.
+ *                          cbGATT_ERROR_CODE_* on failure
+ * @param charAttrHandle    Attribute handle of the characteristic
+ * @param attrHandle        Attribute handle of the characteristic descriptor.
+ * @param pUuid             Pointer to UUID of the descriptor 
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_DiscoverAllCharacteristicDescriptorsCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode,
+    cb_uint16           charAttrHandle,
+    cb_uint16           attrHandle,
+    cbGATT_Uuid*        pUuid);
+
+/**
+ * Callback for read characteristic. This callback will be called for each 
+ * data chunk read.
+ * The last callback will contain either an error code or moreToRead = FALSE
+ * @param connHandle    Connection handle
+ * @param errorCode     Error code, cbGATT_ERROR_CODE_OK when succeeded
+ * @param attrHandle    Attribute handle of the characteristic
+ * @param pAttrValue    Pointer to the read data chunk.
+ * @param length        Length of the read data chunk
+ * @param moreToRead    TRUE = more data to read from the characteristic
+ *                      FALSE = no more data to read
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_ReadCharacteristicCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode,
+    cb_uint16           attrHandle,
+    cb_uint8*           pAttrValue,
+    cb_uint16           length,
+    cb_boolean          moreToRead);
+
+/**
+ * Callback for read characteristic by UUID. This callback will be called 
+ * for each data chunk read.
+ * The last callback will contain either an error code or moreToRead = FALSE
+ * @param connHandle    Connection handle
+ * @param errorCode     Error code, cbGATT_ERROR_CODE_OK when succeeded
+ * @param attrHandle    Attribute handle of the characteristic
+ * @param pAttrValue    Pointer to the read data chunk.
+ * @param length        Length of the read data chunk
+ * @param moreToRead    TRUE = more data to read from the characteristic
+ *                      FALSE = no more data to read
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_ReadCharacteristicByUuidCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode,
+    cb_uint16           attrHandle,
+    cb_uint8*           pAttrValue,
+    cb_uint16           length,
+    cb_boolean          moreToRead);
+
+// TODO to have or not??
+typedef void (*cbGATT_ReadLongCharacteristicCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode,
+    cb_uint8*           pAttrValue,
+    cb_uint16           length);
+
+/**
+ * Callback for read multiple characteristics. This callback will be called 
+ * for each data chunk read.
+ * The last callback will contain either an error code or moreToRead = FALSE
+ * @param connHandle    Connection handle
+ * @param errorCode     Error code, cbGATT_ERROR_CODE_OK when succeeded
+ * @param pAttrValues   Pointer to the read data chunk.
+ * @param length        Length of the read data chunk
+ * @param moreToRead    TRUE = more data to read from the characteristic(s)
+ *                      FALSE = no more data to read
+ * @return TRUE to continue or FALSE to interrupt the search.
+ */
+typedef cb_boolean (*cbGATT_ReadMultipleCharacteristicCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode,
+    cb_uint8*           pAttrValues,
+    cb_uint16           length,
+    cb_boolean          moreToRead);
+
+/**
+ * Callback for write characteristic with response from the remote side
+ * @param connHandle    Connection handle
+ * @param errorCode     Error code, cbGATT_ERROR_CODE_OK when succeeded
+ */
+typedef void (*cbGATT_WriteCharacteristicCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode);
+
+/**
+ * Callback for write characteristic with no response from the remote side 
+ * @param connHandle    Connection handle
+ * @param errorCode     Error code, cbGATT_ERROR_CODE_OK when succeeded
+ */
+typedef void (*cbGATT_WriteCharacteristicNoRspCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode);
+
+/**
+ * Callback for write characteristic configuration with response from the 
+ * remote side.
+ * @param connHandle    Connection handle
+ * @param errorCode     Error code, cbGATT_ERROR_CODE_OK when succeeded
+ */
+typedef void (*cbGATT_WriteCharacteristicConfigCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode);
+
+/**
+ * Callback for write long characteristic with response from the 
+ * remote side.
+ * @param connHandle    Connection handle
+ * @param errorCode     Error code, cbGATT_ERROR_CODE_OK when succeeded
+ */
+typedef void (*cbGATT_WriteLongCharacteristicCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode);
+
+/**
+* Callback for receiving value indication. The client configuration 
+ * notifications must have been enabled before this will be sent to the app.
+ * Note that the indication is replied by GATT when exiting the callback.
+ * @param connHandle        Connection handle
+ * @param attrHandle        Attribute handle of the indicated value
+ * @param pAttrValue        Pointer to the value data
+ * @param length            Length of the value data
+ */
+typedef void (*cbGATT_CharacteristicValueIndication)(
+    TConnHandle         connHandle,
+    cb_uint16           attrHandle,
+    cb_uint8*           pAttrValue,
+    cb_uint16           length);
+
+/**
+ * Callback for receiving value notification. The client configuration 
+ * notifications must have been enabled before this will be sent to the app.
+ * @param connHandle        Connection handle
+ * @param attrHandle        Attribute handle of the notified value
+ * @param pAttrValue        Pointer to the value data
+ * @param length            Length of the value data
+ */
+typedef void (*cbGATT_CharacteristicValueNotification)(
+    TConnHandle         connHandle,
+    cb_uint16           attrHandle,
+    cb_uint8*           pAttrValue,
+    cb_uint16           length);
+
+typedef struct
+{
+    cbGATT_ConnComplEvt                             connComplEvt;
+    cbGATT_DisconnectEvt                            disconnectEvt;
+    cbGATT_DiscoverAllPrimaryServicesCnf            discoverAllPrimaryServicesCnf;
+    cbGATT_DiscoverAllSecondaryServicesCnf          discoverAllSecondaryServicesCnf;
+    cbGATT_DiscoverPrimaryServiceByUuidCnf          discoverPrimaryServiceByUuidCnf;
+    cbGATT_FindIncludedServicesCnf                  findIncludedServicesCnf;
+    cbGATT_DiscoverAllCharacteristicsOfServiceCnf   discoverAllCharacteristicsOfServiceCnf;
+    cbGATT_DiscoverAllCharacteristicDescriptorsCnf  discoverAllCharacteristicDescriptorsCnf;
+    cbGATT_ReadCharacteristicCnf                    readCharacteristicCnf;
+    cbGATT_ReadCharacteristicByUuidCnf              readCharacteristicByUuidCnf;
+    cbGATT_ReadLongCharacteristicCnf                readLongCharacteristicCnf;
+    cbGATT_ReadMultipleCharacteristicCnf            readMultipleCharacteristicCnf;
+    cbGATT_WriteCharacteristicCnf                   writeCharacteristicCnf;
+    cbGATT_WriteCharacteristicNoRspCnf              writeCharacteristicNoRspCnf;
+    cbGATT_WriteCharacteristicConfigCnf             writeCharacteristicConfigCnf;
+    cbGATT_WriteLongCharacteristicCnf               writeLongCharacteristicCnf;
+} cbGATT_ClientCallBack;
+
+
+typedef struct
+{
+    cbGATT_CharacteristicValueIndication            characteristicValueIndication;
+    cbGATT_CharacteristicValueNotification          characteristicValueNotification;
+} cbGATT_ClientNotIndCallBack;
+
+/*=============================================================================
+ * EXPORTED FUNCTIONS
+ *=============================================================================
+ */
+
+/**
+ * Register a GATT client. This must be done before any GATT client
+ * functionality can be used.
+ * @param pCallBack Callback structure that should be provided by the app. Use 
+ *                  NULL as pointer for callbacks that are not used.
+ * @param pAppHandle Pointer where to put created app handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_registerClient(
+    const cbGATT_ClientCallBack* pCallBack, 
+    cb_uint8*       pAppHandle);
+
+/**
+ * Register a notification/indication handler for an attribute handle
+ * This is used when the application needs a specific handler for an
+ * attribute. This can be done first after connection setup.
+ * @param pCallBack  Callback structure that should be provided by the app. Use 
+ *                   NULL as pointer for callbacks that are not used.
+ * @param appHandle  App handle
+ * @param attrHandle Attribute handle for the notification/indication to 
+ *                   subscribe on.
+ * @param connHandle Connection handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_registerNotIndHandler(
+    const cbGATT_ClientNotIndCallBack* pCallBack, 
+    cb_uint8        appHandle, 
+    cb_uint16       attrHandle, 
+    TConnHandle     connHandle);
+
+/**
+ * De-register a notification/indication handler. This is used when the
+ * app does not want to subscribe to the attribute handle any longer e.g.
+ * the client characteristic configuration has been disabled. The handler is
+ * automatically de-registered on disconnection.
+ * @param pCallBack  Registered callback.
+ * @param appHandle  App handle
+ * @param attrHandle Attribute handle for the notification/indication to 
+ *                   subscribe on.
+ * @param connHandle Connection handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_deregisterNotIndHandler(
+    const cbGATT_ClientNotIndCallBack* pCallBack, 
+    cb_uint8        appHandle,
+    cb_uint16       attrHandle, 
+    TConnHandle     connHandle);
+
+/**
+ * Register a default notification/indication handler. This is used when the
+ * app wants to subscribe to all attribute handles notifications/indications
+ * for all connections. This can only be used by one app at a time.
+ * @param pCallBack Callback structure that should be provided by the app. Use 
+ *                  NULL as pointer for callbacks that are not used.
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_registerDefaultNotIndHandler(
+    const cbGATT_ClientNotIndCallBack* pCallBack);
+
+/**
+ * Discover all primary services. Results will be provided in the 
+ * cbGATT_DiscoverAllPrimaryServicesCnf callback.
+ * @param connHandle Connection handle
+ * @param appHandle  App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_discoverAllPrimaryServices(
+    TConnHandle     connHandle, 
+    cb_uint8        appHandle);
+
+/**
+ * Discover all secondary services. Results will be provided in the 
+ * cbGATT_DiscoverAllSecondaryServicesCnf callback.
+ * @param connHandle Connection handle
+ * @param appHandle  App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_discoverAllSecondaryServices(
+    TConnHandle     connHandle, 
+    cb_uint8        appHandle);
+
+/**
+ * Discover all primary services by UUID. This will filter out all results
+ * based on the UUID. Results will be provided in the 
+ * cbGATT_DiscoverPrimaryServiceByUuidCnf callback.
+ * @param connHandle Connection handle
+ * @param pUuid      Pointer to the 16 or 128 bits UUID to search for
+ * @param appHandle  App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_discoverPrimaryServiceByUuid(
+    TConnHandle     connHandle, 
+    cbGATT_Uuid*    pUuid, 
+    cb_uint8        appHandle);
+
+/**
+ * Discover all characteristics of a service. The handles can be 
+ * retrieved by doing a discover primary/secondary services request. Results 
+ * will be provided in the cbGATT_DiscoverAllCharacteristicsOfServiceCnf
+ * callback.
+ * @param connHandle  Connection handle
+ * @param startHandle Start handle of the service
+ * @param endHandle   End handle of the service
+ * @param appHandle   App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_discoverAllCharacteristicsOfService(
+    TConnHandle     connHandle, 
+    cb_uint16       startHandle, 
+    cb_uint16       endHandle, 
+    cb_uint8        appHandle);
+
+/**
+ * Find included services of a given service. The handles can be 
+ * retrieved by doing a discover primary/secondary services request. Results 
+ * will be provided in the cbGATT_FindIncludedServicesCnf callback.
+ * @param connHandle  Connection handle
+ * @param startHandle Start handle of the service
+ * @param endHandle   End handle of the service
+ * @param appHandle   App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_findIncludedServices(
+    TConnHandle     connHandle, 
+    cb_uint16       startHandle, 
+    cb_uint16       endHandle, 
+    cb_uint8        appHandle);
+
+/**
+ * Discover all descriptors of a characteristic. The handles can be 
+ * retrieved by doing a cbGATT_discoverAllCharacteristicsOfService. Results 
+ * will be provided in the cbGATT_DiscoverAllCharacteristicDescriptorsCnf.
+ * callback. If the app wants to do a discover characteristics by UUID this 
+ * function can be used and in the callback filter on UUID.
+ * @param connHandle        Connection handle
+ * @param valueHandle       Handle of the characteristic value
+ * @param serviceEndHandle  End handle of the service which the characteristic 
+ *                          belongs to.
+ * @param appHandle         App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_discoverAllCharacteristicDescriptors(
+    TConnHandle     connHandle, 
+    cb_uint16       valueHandle, 
+    cb_uint16       serviceEndHandle, 
+    cb_uint8        appHandle);
+
+/**
+ * Read characteristic/descriptor value. The handles can be retrieved by 
+ * doing a cbGATT_discoverAllCharacteristicsOfService or 
+ * cbGATT_discoverAllCharacteristicDescriptors. Results will be provided in 
+ * the cbGATT_ReadCharacteristicCnf callback.
+ * @param connHandle    Connection handle
+ * @param attrHandle    Handle of the attribute value
+ * @param offset        Offset where to start read from
+ * @param appHandle     App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_readCharacteristic(
+    TConnHandle     connHandle, 
+    cb_uint16       attrHandle, 
+    cb_uint16       offset, 
+    cb_uint8        appHandle);
+
+/**
+ * Read characteristic/descriptor value by UUID. The app can search the whole 
+ * database by using cbGATT_MIN_ATTR_HANDLE and cbGATT_MAX_ATTR_HANDLE. 
+ * Results will be provided in the cbGATT_ReadCharacteristicByUuidCnf 
+ * callback.
+ * @param connHandle    Connection handle
+ * @param startHandle   Handle, where to start looking for the UUID
+ * @param endHandle     Handle, where to stop looking for the UUID
+ * @param pUuid         Pointer to the 16 or 128 bits UUID
+ * @param appHandle     App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_readCharacteristicByUuid(
+    TConnHandle     connHandle, 
+    cb_uint16       startHandle, 
+    cb_uint16       endHandle, 
+    cbGATT_Uuid*    pUuid, 
+    cb_uint8        appHandle);
+
+// Used for reading long characteristics value or descriptor
+// TODO is this function necessary, because cbGATT_readCharacteristic will read long if needed
+cb_int32 cbGATT_readLongCharacteristic(
+    TConnHandle     connHandle, 
+    cb_uint16       attrHandle, 
+    cb_uint8*       pDest, 
+    cb_uint8        appHandle);
+
+
+/**
+ * Read multiple characteristics in a single read. The app must know the
+ * length of each data element in the returned list. Therefore only the last
+ * data element may have a variable length.
+ * Results will be provided in the cbGATT_ReadMultipleCharacteristicCnf 
+ * callback.
+ * @param connHandle        Connection handle
+ * @param pAttrHandleList   Pointer to a list of attribute handles
+ * @param nbrOfHandles      Number of attribute handles in pAttrHandleList
+ * @param appHandle         App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_readMultipleCharacteristic(
+    TConnHandle     connHandle, 
+    cb_uint16*      pAttrHandleList, 
+    cb_uint16       nbrOfHandles, 
+    cb_uint8        appHandle);
+
+/**
+ * Write characteristic/descriptor and wait for response from remote side.
+ * Results will be provided in the cbGATT_WriteCharacteristicCnf 
+ * callback.
+ * @param connHandle    Connection handle
+ * @param attrHandle    Attribute handle of the value
+ * @param pData         Pointer to the data byte sequence
+ * @param length        Number of bytes to write
+ * @param appHandle     App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_writeCharacteristic(
+    TConnHandle     connHandle, 
+    cb_uint16       attrHandle, 
+    cb_uint8*       pData, 
+    cb_uint16       length, 
+    cb_uint8        appHandle);
+
+/**
+ * Write client/server characteristic/descriptor configuration.
+ * cbGATT_writeCharacteristic can also be used instead of this function.
+ * Results will be provided in the cbGATT_WriteCharacteristicConfigCnf
+ * callback.
+ * @param connHandle    Connection handle
+ * @param attrHandle    Attribute handle of the value
+ * @param config        Configuration i.e. cbGATT_CLIENT_CFG_* or 
+ *                      cbGATT_SERVER_CFG_*
+ * @param appHandle     App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_writeCharacteristicConfig(
+    TConnHandle     connHandle, 
+    cb_uint16       attrHandle, 
+    cb_uint16       config, 
+    cb_uint8        appHandle);
+
+/**
+ * Write characteristic/descriptor with no response from remote side.
+ * Results will be provided in the cbGATT_WriteCharacteristicNoRspCnf 
+ * callback.
+ * @param connHandle    Connection handle
+ * @param attrHandle    Attribute handle of the value
+ * @param pData         Pointer to the data byte sequence
+ * @param length        Number of bytes to write
+ * @param pSignature    Pointer to encrypted signature which is checked by the 
+ *                      server. If the check fails the write is discarded.
+ *                      The devices must be bonded and CSRK exchanged. Use NULL
+ *                      when no signature is being used.
+ * @param appHandle     App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_writeCharacteristicNoRsp(
+    TConnHandle     connHandle, 
+    cb_uint16       attrHandle, 
+    cb_uint8*       pData, 
+    cb_uint16       length, 
+    cb_uint8*       pSignature, 
+    cb_uint8        appHandle);
+
+/**
+ * Write long characteristic/descriptor and wait for response from remote 
+ * side. Results will be provided in the cbGATT_WriteLongCharacteristicCnf 
+ * callback.
+ * @param connHandle    Connection handle
+ * @param attrHandle    Attribute handle of the value
+ * @param pData         Pointer to the data byte sequence
+ * @param length        Number of bytes to write
+ * @param reliable      TRUE = the data will be sent back to client and
+ *                      checked by GATT. 
+ *                      FALSE = no check of data
+ * @param flag          Flag which is used when sending several packets
+ *                      or when data is canceled. If sending several packets all 
+ *                      but the last packet should set the flag to more data. 
+ *                      The last data packet should set the flag to final.
+ * @param offset        Offset of the data to write. Is used when several packets 
+ *                      need to be sent to write a complete data value.
+ * @param appHandle     App handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_writeLongCharacteristic(
+    TConnHandle     connHandle, 
+    cb_uint16       attrHandle, 
+    cb_uint8*       pData, 
+    cb_uint16       length, 
+    cb_boolean      reliable, 
+    cbGATT_WriteLongCharFlag flag, 
+    cb_uint16       offset, 
+    cb_uint8        appHandle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h
new file mode 100644
index 00000000000..23656acb8aa
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h
@@ -0,0 +1,329 @@
+/*------------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+*------------------------------------------------------------------------------
+* Component: GATT
+* File     : cb_gatt_server.h
+*
+* Description:
+* GATT server functionality
+*------------------------------------------------------------------------------
+*/
+
+/**
+ * @file cb_gatt_server.h
+ *
+ * @brief GATT server functionality
+ */
+
+#ifndef _CB_GATT_SERVER_H_
+#define _CB_GATT_SERVER_H_
+
+#include "bt_types.h"
+#include "cb_gatt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*==============================================================================
+ * CONSTANTS
+ *==============================================================================
+ */
+
+#define cbGATT_RD_SEC_NONE     0x01
+#define cbGATT_RD_SEC_UNAUTH   0x02
+#define cbGATT_RD_SEC_AUTH     0x04
+#define cbGATT_WR_SEC_NONE     0x10
+#define cbGATT_WR_SEC_UNAUTH   0x20
+#define cbGATT_WR_SEC_AUTH     0x40
+
+#define cbGATT_NBR_OF_ATTR_OF_SERVICE(x)    (sizeof(x)/sizeof(cbGATT_Attribute))
+
+#define cbGATT_APP_START_SERVICE_HANDLE     1024
+
+/*==============================================================================
+ * TYPES
+ *==============================================================================
+ */
+
+/**
+ * Attribute database entry
+ * @param pUuid             16 or 128-bits UUID
+ * @param uuidFormat        Format of the pUuid
+ * @param properties        Properties see cbGATT_PROP_* in cb_gatt.h
+ * @param security          Read/write security properties for this characteristic see cbGATT_WR_SEC_* and cbGATT_RD_SEC_*
+ * @param pvValue1          Depends on pUuid, see below
+ *                          cbGATT_CHAR_EXT_PROP - properties as cb_uint32
+ *                          cbGATT_CLIENT_CHAR_CONFIG - callback that is called when remote device reads the client config, cbGATT_ServerReadClientConfig
+ *                          cbGATT_SERVER_CHAR_CONFIG - callback that is called when remote device reads the server config, cbGATT_ServerReadServerConfig
+ *                          cbGATT_CHAR_FORMAT - Pointer to cbGATT_CharFormat
+ *                          cbGATT_CHAR_USER_DESC and all other CHARACTERISTICS value - cbGATT_ServerReadAttr callback
+ *                          cbGATT_INCLUDE_DECL - Pointer to inlcuded service cbGATT_Attribute
+ * @param pvValue2          Depends on pUuid, see below
+ *                          cbGATT_CLIENT_CHAR_CONFIG - callback that is called when remote device writes the client config cbGATT_ServerWriteClientConfig
+ *                          cbGATT_CLIENT_CHAR_CONFIG - callback that is called when remote device writes the client config cbGATT_ServerWriteClientConfig
+ *                          cbGATT_SERVER_CHAR_CONFIG - callback that is called when remote device writes the server config cbGATT_ServerWriteServerConfig
+ *                          cbGATT_CHAR_USER_DESC and all other CHARACTERISTICS value - cbGATT_ServerWriteAttr callback
+ * @param pAttrHandle       Pointer where to write the attribute handle in case it's needed by the app. 
+ *                          If not needed, pass NULL. Will be written after the service has been added.
+ */
+typedef struct
+{
+    void*               pUuid;
+    cbGATT_UuidFormat   uuidFormat;
+    cb_uint8            properties;
+    cb_uint8            security;
+    void*               pvValue1;
+    void*               pvValue2;
+    cb_uint16*          pAttrHandle;
+} cbGATT_Attribute;
+
+/**
+ * Callback is called when the indication has been confirmed.
+ * @param connHandle        Connection handle
+ * @param attrHandle        Handle of the attribute value
+ * @param errorCode         cbGATT_ERROR_CODE_OK when succeeded
+ */
+typedef void (*cbGATT_CharacteristicValueIndicationCnf)(
+    TConnHandle         connHandle,
+    cb_uint16           attrHandle,
+    cbGATT_ErrorCode    errorCode);
+
+/**
+ * Callback is called when the notification has been sent.
+ * @param connHandle        Connection handle
+ * @param errorCode         cbGATT_ERROR_CODE_OK when succeeded
+ */
+typedef void (*cbGATT_CharacteristicValueNotificationCnf)(
+    TConnHandle         connHandle,
+    cbGATT_ErrorCode    errorCode);
+
+/**
+ * Callback is called when the GATT client has commited a write long
+ * @param connHandle        Connection handle
+ * @param commit            TRUE = commit, FALSE = cancel
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_CharacteristicWriteLongCommitEvt)(
+    TConnHandle         connHandle,
+    cb_boolean          commit);
+
+// Callbacks to use in server table
+
+/**
+ * Callback is called when the client is reading an attribute
+ * @param connHandle        Connection handle
+ * @param attrHandle        Handle of the attribute value
+ * @param pAttr             Pointer to attribute record
+ * @param pAttrValue        Pointer where to put the read data
+ * @param pLength           Pointer where to put the read length.
+ * @param maxLength         Max number of bytes that is allowed for pAttrValue
+ * @param offset            The offset of the read data
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_ServerReadAttr)(
+    TConnHandle         connHandle,
+    cb_uint16           attrHandle,
+    cbGATT_Attribute*   pAttr,
+    cb_uint8*           pAttrValue,
+    cb_uint16*          pLength,
+    cb_uint16           maxLength,
+    cb_uint16           offset);
+
+/**
+ * Callback is called when the client is writing an attribute.
+ * If the application wants to send the response later it can
+ * return the cbGATT_ERROR_CODE_DELAYED_RSP error code and call cbGATT_writeRsp
+ * when ready.
+ * @param connHandle        Connection handle
+ * @param attrHandle        Handle of the attribute value
+ * @param pAttr             Pointer to attribute record
+ * @param pAttrValue        Pointer where to get the data
+ * @param length            The length.
+ * @param writeMethod       Which write method the client is using. 
+ *                          This depends on the properties in the attribute table.
+ * @param offset            The offset of the written data
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_ServerWriteAttr)(
+    TConnHandle         connHandle,
+    cb_uint16           attrHandle,
+    cbGATT_Attribute*   pAttr,
+    cb_uint8*           pAttrValue,
+    cb_uint16           length,
+    cbGATT_WriteMethod  writeMethod,
+    cb_uint16           offset);
+
+/**
+ * Callback is called when the client is reading the client config
+ * @param connHandle        Connection handle
+ * @param attrHandle        Handle of the attribute value
+ * @param pConfig           Pointer where to write the config
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_ServerReadClientConfig)(
+    TConnHandle         connHandle,
+    cb_uint16           attrHandle,
+    cb_uint16*          pConfig);
+
+/**
+ * Callback is called when the client is writing the client config
+ * @param connHandle        Connection handle
+ * @param attrHandle        Handle of the attribute value
+ * @param config            The config to be stored
+ * @param writeMethod       Which write method the client is using. 
+ *                          This depends on the properties in the attribute table.
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_ServerWriteClientConfig)(
+    TConnHandle         connHandle,
+    cb_uint16           attrHandle,
+    cb_uint16           config,
+    cbGATT_WriteMethod  writeMethod);
+
+/**
+ * Callback is called when the client is reading the server config
+ * @param connHandle        Connection handle
+ * @param attrHandle        Handle of the attribute value
+ * @param pConfig           Pointer where to write the config
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_ServerReadServerConfig)(
+    TConnHandle         connHandle,
+    cb_uint16           attrHandle,
+    cb_uint16*          pConfig);
+
+/**
+ * Callback is called when the client is writing the server config
+ * @param connHandle        Connection handle
+ * @param attrHandle        Handle of the attribute value
+ * @param config            The config to be stored
+ * @param writeMethod       Which write method the client is using. 
+ *                          This depends on the properties in the attribute table.
+ * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed.
+ */
+typedef cbGATT_ErrorCode (*cbGATT_ServerWriteServerConfig)(
+    TConnHandle         connHandle,
+    cb_uint16           attrHandle,
+    cb_uint16           config,
+    cbGATT_WriteMethod  writeMethod);
+
+typedef struct
+{
+    cbGATT_ConnComplEvt connComplEvt;
+    cbGATT_DisconnectEvt disconnectEvt;
+    cbGATT_CharacteristicValueIndicationCnf characteristicValueIndicationCnf;
+    cbGATT_CharacteristicValueNotificationCnf characteristicValueNotificationCnf;
+    cbGATT_CharacteristicWriteLongCommitEvt characteristicWriteLongCommitEvt;
+} cbGATT_ServerCallBack;
+
+
+/*=============================================================================
+ * EXPORTED FUNCTIONS
+ *=============================================================================
+ */
+
+/**
+ * Register server callbacks
+ * @param pCallBack         Server callback
+ * @param pAppHandle        Where to store app handle
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_registerServer(
+    const cbGATT_ServerCallBack* pCallBack, 
+    cb_uint8*       pAppHandle);
+
+/**
+ * Deregister all server callbacks
+ * @return cbGATT_OK if succeeded or cbGATT_ERROR when failed.
+ */
+cb_int32 cbGATT_deregisterAllServers(void);
+
+/**
+ * Send notification to GATT client. The characteristicValueNotificationCnf
+ * callback will be called when finished and a new notification can be sent.
+ * The client config notification must have been enabled by the GATT client 
+ * before an notification can be sent.
+ * @param connHandle        Connection handle
+ * @param attrHandle        Handle of the attribute value
+ * @param pData             Pointer to data to send
+ * @param length            Length of pData
+ * @param appHandle         App handle
+ * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed.
+ */
+cb_int32 cbGATT_notification(
+    TConnHandle     connHandle, 
+    cb_uint16       attrHandle, 
+    cb_uint8*       pData, 
+    cb_uint16       length, 
+    cb_uint8        appHandle);
+
+/**
+ * Send indication to GATT client. The characteristicValueIndicationCnf
+ * callback will be called when finished and a new indication can be sent.
+ * The client config indication must have been enabled by the GATT client 
+ * before an indication can be sent.
+ * @param connHandle        Connection handle
+ * @param attrHandle        Handle of the attribute value
+ * @param pData             Pointer to data to send
+ * @param length            Length of pData
+ * @param appHandle         App handle
+ * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed.
+ */
+cb_int32 cbGATT_indication(
+    TConnHandle     connHandle, 
+    cb_uint16       attrHandle, 
+    cb_uint8*       pData, 
+    cb_uint16       length, 
+    cb_uint8        appHandle);
+
+/**
+ * Delay write respone to client, see cbGATT_ServerWriteAttr
+ * @param connHandle        Connection handle
+ * @param attrHandle        Handle of the attribute value
+ * @param errorCode         Error code, use cbGATT_ERROR_CODE_OK if OK otherwise some cbGATT_ERROR_CODE_* 
+ * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed.
+ */
+cb_int32 cbGATT_writeRsp(
+    TConnHandle     connHandle,
+    cb_uint16       attrHandle, 
+    cb_uint8        errorCode); // For delayed write responses
+
+/**
+ * Add service list to attribute database
+ * @param pAttrList         Attribute list
+ * @param attrListSize      Size of the attribute list
+ * @param startHandle       Start handle. Note that startHandle for the application 
+ *                          should start at lowest 1024, cbGATT_APP_START_SERVICE_HANDLE. 
+ *                          1-1023 is reserved for GATT/GAP and other u-blox services.
+ * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed.
+ */
+cb_int32 cbGATT_addService(
+    const cbGATT_Attribute* pAttrList, 
+    cb_uint16       attrListSize, 
+    cb_int16        startHandle);
+
+/**
+ * NOTE: Only for tests
+ * Free all services. Use with care since this will also remove GATT and GAP services.
+ * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed.
+ */
+cb_int32 cbGATT_freeServices(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h
new file mode 100644
index 00000000000..248a7511e05
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h
@@ -0,0 +1,104 @@
+/*
+ *---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : GATT
+ * File        : cb_gatt_utils.h
+ *
+ * Description : Helper functions for GATT
+ *
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_gatt_utils.h
+ *
+ * @brief Helper functions for GATT
+ */
+
+#ifndef _CB_GATT_UTILS_H_
+#define _CB_GATT_UTILS_H_
+
+#include "cb_comdefs.h"
+#include "bt_types.h"
+#include "cb_gatt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*=============================================================================
+ * FUNCTIONS
+ *=============================================================================
+ */
+
+/**
+ * Returns a string representing the error code. NULL if the error code is 
+ * not found.
+ * @param errorCode     GATT error code
+ */
+cb_char* cbGATT_UTILS_getStringFromErrorCode(
+    cbGATT_ErrorCode errorCode);
+
+/**
+ * Returns a string representing the GATT/ATT properties for a characteristic.
+ * @param properties    Bitmap of properties see cbGATT_PROP_*
+ */
+cb_char* cbGATT_UTILS_getStringFromProperties(
+    cb_uint8 properties);
+
+/**
+ * Returns a string representing the UUID. NULL if the UUID is not 
+ * found.
+ * @param pUuid     Pointer to 128 or 16-bit UUID
+ */
+cb_char* cbGATT_UTILS_getStringFromUuid(
+    cbGATT_Uuid* pUuid);
+
+/**
+ * Returns a string representing the UUID as hex bytes.
+ * @param pUuid     Pointer to 128 or 16-bit UUID
+ * @param resultStr Allocated buffer to put hex string in.
+ *                  Should fit 16*2+1 = 33 bytes
+ */
+cb_char* cbGATT_UTILS_getHexStringFromUuid(
+    cbGATT_Uuid*    pUuid, 
+    cb_char*        resultStr);
+
+/**
+ * Returns a string representing the data as hex bytes.
+ * @param pData     Pointer to data
+ * @param len       Length of data
+ * @param resultStr Pointer to allocated buffer to put hex string in.
+ *                  Should fit len*2+1 bytes
+ */
+cb_char* cbGATT_UTILS_dataToHex(
+    cb_uint8*   pData, 
+    cb_uint16   len, 
+    cb_char*    resultStr);
+
+/**
+ * Reverse bytes
+ * @param src           Pointer to data to reverse bytes for
+ * @param nbrOfBytes    Length of src
+ */
+void cbGATT_UTILS_reverseBytes(
+    cb_uint8*   src, 
+    cb_uint16   nbrOfBytes);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h
new file mode 100644
index 00000000000..b0b3f5cba55
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h
@@ -0,0 +1,146 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component: CB HW
+ * File     : cb_hw.h
+ *
+ * Description: Setup of hardware.
+ *              TODO clean up this interface..
+ *-------------------------------------------------------------------------*/
+ 
+#ifndef _CB_HW_H_
+#define _CB_HW_H_
+
+#include "cb_comdefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+typedef enum {
+    cbHW_PCB_VERSION_UNKNOWN,
+    cbHW_PCB_VERSION_1,
+    cbHW_PCB_VERSION_2,
+    cbHW_PCB_VERSION_3,
+    cbHW_PCB_VERSION_4,
+    cbHW_PCB_VERSION_5
+} cbHW_PCBVersion;
+
+typedef enum {
+    cbHW_RESET_REASON_UNKNOWN = 0,
+    cbHW_RESET_REASON_FW_UPDATE,
+    cbHW_RESET_REASON_PRODUCTION_MODE
+}cbHW_ResetReason;
+
+typedef enum {
+    cbHW_FLOW_CONTROL_DISABLED = 0,
+    cbHW_FLOW_CONTROL_ENABLED
+} cbHW_FlowControl;
+
+typedef enum {
+    cbHW_IRQ_HIGH = 2U,
+    cbHW_IRQ_MEDIUM = 3U,
+    cbHW_IRQ_DEFAULT = 5U,
+    cbHW_IRQ_LOW = 12U
+}cbHW_PRIO_LVL;
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+typedef void (*cbHW_StopModeStatusEvt)(cb_boolean enable);
+typedef void (*cbHW_SysTickCb)(void);
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+void cbHW_init(void);
+void cbHW_registerStopModeStatusEvt(cbHW_StopModeStatusEvt evt);
+void cbHW_disableIrq(void);
+void cbHW_disableAllIrq(void); // Should not be used unless extremely critical
+void cbHW_enableIrq(void);
+void cbHW_enterSleepMode(void);
+void cbHW_enterStopMode(void);
+void cbHW_setWakeupEvent(void);
+void cbHW_resetWakeupEvent(void);
+
+/**
+ * Wait for specified amount of microseconds. May be interrupt dependent.
+ * @note Granularity may vary between systems. Will be at least systick based.
+ * The system may go to sleep during the delay.
+ * 
+ * @param us Time to delay in microseconds.
+ */
+void cbHW_delay(cb_uint32 us);
+
+/**
+* Wait for specified amount of microseconds using a software loop.
+* @note Granularity may vary between systems. 
+* The system will not go to sleep during the delay.
+*
+* @param us Time to delay in microseconds.
+*/
+void cbHW_softDelay(cb_uint32 us);
+cb_boolean cbHW_sysFreqIsSupported(cb_uint32 sysFreq);
+void cbHW_setSysFreq(cb_uint32 sysFreq);
+cb_uint32 cbHW_getSysFreq(void);
+void cbHW_writeBackupRegister(cb_uint32 registerId, cb_uint32 value);
+cb_uint32 cbHW_readBackupRegister(cb_int32 registerId);
+void cbHW_getHWId(cb_uint8 uid[12]);
+cbHW_PCBVersion cbHW_getPCBVersion(void);
+
+/**
+* Register a system tick callback.
+* The system tick will be generated once evert millisecond.
+*
+* @param cb Callback function for the system tick timer.
+*/
+void cbHW_registerSysTickISRCallback(cbHW_SysTickCb cb);
+
+/**
+* Get the current tick frequency for the @ref cbHW_getTicks tick counter.
+* @note The frequency may be altered with different system clocks and power modes.
+*
+* @return The current tick frequency.
+*/
+cb_uint32 cbHW_getTickFrequency(void);
+
+/**
+* Get the current value of the tick counter.
+* Time base in @ref cbHW_getTickFrequency.
+* @note The value may wrap.
+*
+* @return The current tick counter.
+*/
+cb_uint32 cbHW_getTicks(void);
+
+void cbHW_forceBoot(cb_uint32 address, cb_uint32 baudrate);
+void cbHW_enterProductionMode(cbHW_FlowControl flowControl);
+cbHW_ResetReason cbHW_resetReason(void);
+cbHW_FlowControl cbHW_flowControl(void);
+
+void cbHW_enableAllIrq(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h
new file mode 100644
index 00000000000..b0b30a9294b
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h
@@ -0,0 +1,131 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component: Main for WiFi-driver and BT stack
+ * File     : cb_main.h
+ *
+ * Description : 
+ *-------------------------------------------------------------------------*/
+
+#ifndef _CB_MAIN_H_
+#define _CB_MAIN_H_
+
+#include "bt_types.h"
+#include "cb_bt_man.h"
+#include "cb_wlan.h"
+#include "mbed_events.h"
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+#define cbMAIN_TARGET_INVALID_ID -1
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+typedef struct
+{
+    TBdAddr         address;                    /** Bluetooth address that shall be assigned to controller. Pass invalidBdAddress to use controller default address*/
+    cbBM_LeRole     leRole;                     /** Bluetooth low energy role */
+    cb_int8         maxOutputPower;             /** Maximum output power. */
+    cb_uint32       maxLinkKeysClassic;         /** Max number of CLASSIC link keys */
+    cb_uint32       maxLinkKeysLe;              /** Max number of link keys BLE*/
+} cbMAIN_BtInitParams;
+
+typedef void(*cbMAIN_ErrorHandler)(
+    cb_int32            errorCode,
+    const cb_char*      filename,
+    cb_uint32           line);
+
+/*---------------------------------------------------------------------------
+* Callback to indicate that initialization of BT stack is completed.
+*-------------------------------------------------------------------------*/
+typedef void(*cbMAIN_initBtComplete)(void);
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+* Initialize OS, timers, GPIO's, heap and OTP.
+*
+* @return void
+*/
+extern void cbMAIN_initOS(void);
+
+/**
+* Start Bluetooth HW.
+*
+* @param pInitParameters Initial configuration parameters. These parameters can
+*                        not be changed once Bluetooth has been started.
+* @param callback Will be invoked when initialisation is done.
+* @return void
+*/
+extern void cbMAIN_initBt(cbMAIN_BtInitParams *pInitParameters, cbMAIN_initBtComplete callback);
+
+/**
+* Initialize WLAN component.
+* @return Port specific TARGET identifier
+*/
+extern cb_int32 cbMAIN_initWlan(void);
+
+/**
+* Start WLAN component.
+* Create WLAN driver instance, bind it to targetId and start the driver.
+*
+* @param targetId Port specific TARGET identifier.
+* @param params Start parameters passed to WLAN driver instance.
+* @return cbSTATUS_OK if successful, otherwise cbSTATUS_ERROR.
+*/
+extern cb_int32 cbMAIN_startWlan(cb_int32 targetId, cbWLAN_StartParameters *params);
+
+/**
+* Register error handler function.
+*
+* @param errHandler Function to be invoked in case of error.
+* @return void
+*/
+extern void cbMAIN_registerErrorHandler(cbMAIN_ErrorHandler errHandler);
+
+/**
+* Start driver OS. This must be called after all cbMAIN_initOS/cbMAIN_initBt/cbMAIN_initWlan
+* to start the driver thread.
+*
+* @return void
+*/
+extern void cbMAIN_startOS(void);
+
+/**
+* Get event queue. Used for running a function in the same thread context as the driver.
+* Can not be called before cbMAIN_initOS/cbMAIN_initBt/cbMAIN_initWlan.
+* @return EventQueue     Pointer to the event queue where function calls can be enqueued.
+*/
+extern EventQueue* cbMAIN_getEventQueue(void);
+
+/**
+* Lock driver from usage. This must be used if a C API function is used outside of the driver thread context.
+* The driver should only be locked for as small time as possible.
+* @return void
+*/
+extern void cbMAIN_driverLock(void);
+
+/**
+* Unlock driver. used when the C API function has finished executing to release the driver for others to use.
+*
+* @return void
+*/
+extern void cbMAIN_driverUnlock(void);
+
+#endif /*_CB_MAIN_H_*/
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h
new file mode 100644
index 00000000000..0ae615bd265
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h
@@ -0,0 +1,68 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : OTP
+ * File        : cb_otp.h
+ *
+ * Description : Support for One Time Programmable memory intended for
+ *               storing production parameters such as mac addresses, trim
+ *               values and product configuration. Writing to OTP memory shall 
+ *               only be done in a production environment.
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_otp.h 
+ * @ingroup platform
+ */
+
+#ifndef _CB_OTP_H_
+#define _CB_OTP_H_
+
+#include "cb_comdefs.h"
+#include "cb_status.h"
+
+#define cbOTP_MAX_SIZE          (30)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum
+{
+    cbOTP_MAC_BLUETOOTH = 1,
+    cbOTP_MAC_WLAN,
+    cbOTP_MAC_ETHERNET,
+    cbOTP_MAC_FEATURE_INFO,
+    cbOTP_MAC_DEBUG_UNIT,
+    cbOTP_SERIAL_NUMBER,
+    cbOTP_TYPE_CODE,
+    cbOTP_RESERVED_UNUSED = 255
+} cbOTP_Id;
+
+
+/**
+ * Read a OTP parameter
+ * @param id    The id of the parameter to write
+ * @param len   The length of the parameter to write
+ * @param buf   Pointer to data to be written
+ * @returns     The read length of the id is returned. If the read fails 0 is returned
+ */
+cb_uint32 cbOTP_read(cbOTP_Id id, cb_uint32 len, cb_uint8 *buf);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h
new file mode 100644
index 00000000000..c64e2c7b7cc
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h
@@ -0,0 +1,130 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : Wireless LAN driver
+ * File        : cb_types.h
+ *
+ * Description : Common definitions for a GCC compatible compiler.
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_types.h Defines type required for the entire driver.
+ * The defines in this file will have to be adapted for the platform.
+ * @ingroup platform
+ */
+
+#ifndef _CB_PLATFORM_BASIC_TYPES_H_
+#define _CB_PLATFORM_BASIC_TYPES_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+/*===========================================================================
+ * COMMON SYSTEM DEFINES
+ *=========================================================================*/
+
+typedef int8_t                  cb_int8;
+typedef int16_t                 cb_int16;
+typedef int32_t                 cb_int32;
+typedef int64_t                 cb_int64;
+
+typedef uint8_t                 cb_uint8;
+typedef uint16_t                cb_uint16;
+typedef uint32_t                cb_uint32;
+typedef uint64_t                cb_uint64;
+
+typedef bool                    cb_boolean;
+typedef char                    cb_char;
+typedef int                     cb_int;
+
+/**
+ * Used when declaring an empty array that does not take up space in a struct.
+ * Example: struct { cb_uint8 payload[cb_EMPTY_ARRAY]; }
+ * In some compilers this is empty i.e. payload[]. While in some it requires a zero.
+ * I.e. payload[0];
+ * Use this define to get it working for your system.
+ */
+#define cb_EMPTY_ARRAY (0)
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+/**
+ * Used in function definitions to declare an input parameter unused to avoid warnings.
+ */
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define cb_UNUSED(x) UNUSED_ ## x __attribute__((unused))
+#else
+#define cb_UNUSED(x) UNUSED_ ## x
+#endif
+
+
+/**
+ * Define cb_ASSERT to the wanted assert handler.
+ */
+/*
+#define cb_ASSERT(exp)              do { if (!(exp)) { \
+                                        W_PRINT("ASSERT %s:%d\n", __FILE__, __LINE__); \
+                                        while(1); \
+                                    } } while(0)
+*/
+#include "cb_assert.h"
+
+
+/**@{*/
+/**
+ * Packed struct defines.
+ * - cb_PACKED_STRUCT_ATTR_PRE is used before the typedef'ed struct declaration.
+ * - cb_PACKED_STRUCT_ATTR_INLINE_PRE is after the typedef but before the struct declaration.
+ * - cb_PACKED_STRUCT_ATTR_INLINE_POST is used after the struct declaration but before the typedef'ed name.
+ * - cb_PACKED_STRUCT_ATTR_POST is used after the entire struct declaration.
+ * 
+ * example:
+ *      cb_PACKED_STRUCT_ATTR_PRE
+ *      typedef cb_PACKED_STRUCT_ATTR_INLINE_PRE struct myPackedStruct {
+ *          int a;
+ *          int b;
+ *      } cb_PACKED_STRUCT_ATTR_INLINE_POST myPackedStruct
+ *      cb_PACKED_STRUCT_ATTR_POST
+ *
+ */
+
+#define cb_PACKED_STRUCT_ATTR_PRE
+
+#if defined(__ICCARM__)
+#define cb_PACKED_STRUCT_ATTR_INLINE_PRE       __packed
+#else
+#define cb_PACKED_STRUCT_ATTR_INLINE_PRE
+#endif
+
+#if defined(__ICCARM__)
+#define cb_PACKED_STRUCT_ATTR_INLINE_POST       __packed
+#else
+#define cb_PACKED_STRUCT_ATTR_INLINE_POST       __attribute__ ((__packed__))
+#endif
+
+
+#define cb_PACKED_STRUCT_ATTR_POST
+
+/**@}*/
+
+
+#endif /* _CB_PLATFORM_BASIC_TYPES_H_ */
+
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h
new file mode 100644
index 00000000000..c53ff67848d
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h
@@ -0,0 +1,35 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : Wireless LAN driver
+ * File        : cb_types.h
+ *
+ * Description : Common definitions for a GCC compatible compiler.
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_types.h Defines type required for the entire driver.
+ * The defines in this file will have to be adapted for the platform.
+ * @ingroup platform
+ */
+
+#ifndef _CB_PORT_TYPES_H_
+#define _CB_PORT_TYPES_H_
+
+#include <cb_comdefs.h>
+
+
+#endif /* _CB_PORT_TYPES_H_ */
+
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h
new file mode 100644
index 00000000000..9e2f5d72de6
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h
@@ -0,0 +1,44 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : RTSL
+ * File        : cb_status.h
+ *
+ * Description : Common RTSL status codes 
+ *-------------------------------------------------------------------------*/
+#ifndef _CB_STATUS_H_
+#define _CB_STATUS_H_
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+#define OK(status) (status == cbSTATUS_OK)
+ 
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+ typedef enum
+ {
+    cbSTATUS_OK,
+    cbSTATUS_ERROR,
+    cbSTATUS_BUSY,
+    cbSTATUS_TIMEOUT
+ 
+ } cbRTSL_Status;
+
+#endif /* _CB_STATUS_H_ */
+
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h
new file mode 100644
index 00000000000..5f318e02622
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h
@@ -0,0 +1,287 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : RTSL
+ * File        : cb_types.h
+ *
+ * Description : Common type definitions
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_types.h Defines type required for the entire driver.
+ * The defines in this file will have to be adapted for the platform.
+ * @ingroup platform
+ */
+
+#ifndef _CB_TYPES_H_
+#define _CB_TYPES_H_
+
+#include "cb_port_types.h"
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+/*===========================================================================
+ * COMMON SYSTEM DEFINES
+ *=========================================================================*/
+
+#ifndef FALSE
+#  define FALSE           (0)
+#endif
+#ifndef TRUE
+#  define TRUE            (!FALSE)
+#endif
+
+#ifndef NULL
+#  define NULL            ((void *) 0)
+#endif
+
+/**
+ * Returns the maximum value of the two parameters.
+ */
+#ifndef cb_MAX
+#  define cb_MAX(x , y)   (((x) > (y)) ? (x) : (y))
+#endif
+/**
+ * Returns the minimum value of the two parameters.
+ */
+#ifndef cb_MIN
+#  define cb_MIN(x , y)   (((x) < (y)) ? (x) : (y))
+#endif
+
+#ifndef ELEMENTS_OF
+#  define ELEMENTS_OF(_array) (sizeof((_array)) / sizeof((_array)[0]))
+#endif
+
+#define cbWM_ARRAY_SIZE(a)          ELEMENTS_OF(a)
+
+/**
+ * Used when declaring an empty array that does not take up space in a struct.
+ * Example: struct { cb_uint8 payload[cb_EMPTY_ARRAY]; }
+ * In some compilers this is empty i.e. payload[]. While in some it requires a zero.
+ * I.e. payload[0];
+ * Use this define to get it working for your system.
+ */
+#ifndef cb_EMPTY_ARRAY
+#  define cb_EMPTY_ARRAY  (0)
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+/**
+ * Used in function definitions to declare an inparameter unused to avoid warnings.
+ */
+#ifndef cb_UNUSED
+#  define cb_UNUSED(x)    x
+#endif
+
+#ifndef cb_ASSERT
+#  error "No port definition for ASSERT!"
+#endif
+
+#ifndef cb_ARG_POINTER_CHECK
+#  define cb_ARG_POINTER_CHECK(ptr) if((ptr) == NULL) {cb_ASSERT(FALSE); return;}
+#endif
+#ifndef cb_ARG_POINTER_CHECK_RETURN
+#  define cb_ARG_POINTER_CHECK_RETURN(ptr, returnValue) if((ptr) == NULL) {cb_ASSERT(FALSE); return (returnValue);}
+#endif
+
+#ifndef cb_BIT_0
+#define cb_BIT_0        (1ul)
+#endif
+#ifndef cb_BIT_1
+#define cb_BIT_1        (1ul << 1)
+#endif
+#ifndef cb_BIT_2
+#define cb_BIT_2        (1ul << 2)
+#endif
+#ifndef cb_BIT_3
+#define cb_BIT_3        (1ul << 3)
+#endif
+#ifndef cb_BIT_4
+#define cb_BIT_4        (1ul << 4)
+#endif
+#ifndef cb_BIT_5
+#define cb_BIT_5        (1ul << 5)
+#endif
+#ifndef cb_BIT_6
+#define cb_BIT_6        (1ul << 6)
+#endif
+#ifndef cb_BIT_7
+#define cb_BIT_7        (1ul << 7)
+#endif
+#ifndef cb_BIT_8
+#define cb_BIT_8        (1ul << 8)
+#endif
+#ifndef cb_BIT_9
+#define cb_BIT_9        (1ul << 9)
+#endif
+#ifndef cb_BIT_10
+#define cb_BIT_10       (1ul << 10)
+#endif
+#ifndef cb_BIT_11
+#define cb_BIT_11       (1ul << 11)
+#endif
+#ifndef cb_BIT_12
+#define cb_BIT_12       (1ul << 12)
+#endif
+#ifndef cb_BIT_13
+#define cb_BIT_13       (1ul << 13)
+#endif
+#ifndef cb_BIT_14
+#define cb_BIT_14       (1ul << 14)
+#endif
+#ifndef cb_BIT_15
+#define cb_BIT_15       (1ul << 15)
+#endif
+#ifndef cb_BIT_16
+#define cb_BIT_16       (1ul << 16)
+#endif
+#ifndef cb_BIT_17
+#define cb_BIT_17       (1ul << 17)
+#endif
+#ifndef cb_BIT_18
+#define cb_BIT_18       (1ul << 18)
+#endif
+#ifndef cb_BIT_19
+#define cb_BIT_19       (1ul << 19)
+#endif
+#ifndef cb_BIT_20
+#define cb_BIT_20       (1ul << 20)
+#endif
+#ifndef cb_BIT_21
+#define cb_BIT_21       (1ul << 21)
+#endif
+#ifndef cb_BIT_22
+#define cb_BIT_22       (1ul << 22)
+#endif
+#ifndef cb_BIT_23
+#define cb_BIT_23       (1ul << 23)
+#endif
+#ifndef cb_BIT_24
+#define cb_BIT_24       (1ul << 24)
+#endif
+#ifndef cb_BIT_25
+#define cb_BIT_25       (1ul << 25)
+#endif
+#ifndef cb_BIT_26
+#define cb_BIT_26       (1ul << 26)
+#endif
+#ifndef cb_BIT_27
+#define cb_BIT_27       (1ul << 27)
+#endif
+#ifndef cb_BIT_28
+#define cb_BIT_28       (1ul << 28)
+#endif
+#ifndef cb_BIT_29
+#define cb_BIT_29       (1ul << 29)
+#endif
+#ifndef cb_BIT_30
+#define cb_BIT_30       (1ul << 30)
+#endif
+#ifndef cb_BIT_31
+#define cb_BIT_31       (1ul << 31)
+#endif
+
+#ifndef cb_UINT8_MAX
+#define cb_UINT8_MAX    ((cb_uint8)0xff)
+#endif
+#ifndef cb_UINT16_MAX
+#define cb_UINT16_MAX   ((cb_uint16)0xffff)
+#endif
+#ifndef cb_UINT32_MAX
+#define cb_UINT32_MAX   ((cb_uint32)0xffffffff)
+#endif
+#ifndef cb_INT8_MAX
+#define cb_INT8_MAX     ((cb_uint8)0x7f)
+#endif
+#ifndef cb_INT16_MAX
+#define cb_INT16_MAX    ((cb_uint16)0x7fff)
+#endif
+#ifndef cb_INT32_MAX
+#define cb_INT32_MAX    ((cb_uint32)0x7fffffff)
+#endif
+#ifndef cb_INT8_MIN
+#define cb_INT8_MIN     ((cb_uint8)0x80)
+#endif
+#ifndef cb_INT16_MIN
+#define cb_INT16_MIN    ((cb_uint16)0x8000)
+#endif
+#ifndef cb_INT32_MIN
+#define cb_INT32_MIN    ((cb_uint32)0x80000000)
+#endif
+
+/**
+ * Clears (set to zero) a bit or bits in a variable. 
+ * @param variable The variable.
+ * @param bit The bit or bits to clear
+ */
+#ifndef cb_CLEAR_BIT
+#  define cb_CLEAR_BIT(variable,bit) ((variable) &= ~((bit)))
+#endif
+
+/**
+ * Gets a bit i.e. checks if it is set in a variable.
+ *
+ * Also works to see if any of several bits are set.
+ *
+ * @param variable The variable.
+ * @param bit The bit to check if it set.
+ * @return @ref TRUE if any of the bits are set, @ref FALSE otherwise.
+ */
+#ifndef cb_GET_BIT
+#  define cb_GET_BIT(variable,bit) (((variable) & ((bit))) ? TRUE : FALSE)
+#endif
+
+/**
+ * Sets (set to 1) a bit or bits in a variable.
+ *
+ * @param variable The variable.
+ * @param bit The bit or bits to set in the variable.
+ */
+#ifndef cb_SET_BIT
+#  define cb_SET_BIT(variable,bit) ((variable) |= (bit))
+#endif
+
+
+/*Packed struct defines*/
+#ifndef cb_PACKED_STRUCT_ATTR_INLINE_POST
+#  define cb_PACKED_STRUCT_ATTR_INLINE_POST
+#endif
+#ifndef cb_PACKED_STRUCT_ATTR_INLINE_PRE
+#  define cb_PACKED_STRUCT_ATTR_INLINE_PRE
+#endif
+#ifndef cb_PACKED_STRUCT_ATTR_PRE
+#  define cb_PACKED_STRUCT_ATTR_PRE
+#endif
+#ifndef cb_PACKED_STRUCT_ATTR_POST
+#  define cb_PACKED_STRUCT_ATTR_POST
+#endif
+
+#ifndef cb_PACKED_STRUCT_BEGIN
+#  define cb_PACKED_STRUCT_BEGIN(name) \
+        cb_PACKED_STRUCT_ATTR_PRE \
+        typedef cb_PACKED_STRUCT_ATTR_INLINE_PRE struct name##_t
+#endif
+
+#ifndef cb_PACKED_STRUCT_END
+#  define cb_PACKED_STRUCT_END(name) \
+        cb_PACKED_STRUCT_ATTR_INLINE_POST name; \
+        cb_PACKED_STRUCT_ATTR_POST
+#endif
+
+#endif /* _CB_TYPES_H_ */
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h
new file mode 100644
index 00000000000..fe3e6f1df42
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h
@@ -0,0 +1,71 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component:   Watchdog
+ * File:        cb_watchdog.h
+ *
+ * Description: Functionality for watchdog and reset.
+ *-------------------------------------------------------------------------*/
+#ifndef _CB_WATCHDOG_H_
+#define _CB_WATCHDOG_H_
+
+#include "cb_comdefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+* Put watchdog in a defined state.
+*/
+void cbWD_init(void);
+
+/**
+* Resets the CPU.
+*/
+void cbWD_systemReset(void);
+
+/**
+* Enables watchdog. Watchdog needs to be polled using cbWD_poll() with
+* shorter intervals then specified by timeInMilliseconds.
+*
+* @param timeInMilliseconds Watchdog timeout in milliseconds.
+*/
+void cbWD_enable(cb_uint32 timeInMilliseconds);
+
+/**
+* Poll the watchdog timer. This must be done with shorter intervalls
+* than the time in cbWD_enable().
+*/
+void cbWD_poll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CB_WATCHDOG_H_ */
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h
new file mode 100644
index 00000000000..a451e9ff8e1
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h
@@ -0,0 +1,567 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : WLAN
+ * File        : cb_wlan.h
+ *
+ * Description : Main WLAN component, ties together WM, SUPPLICANT and 
+ *               TARGET to one streamlined API.
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_wlan.h The main WLAN component interface.
+ * All functions declared extern needs to be provided by another/upper layer.
+ * @ingroup wlan
+ */
+
+#ifndef _CB_WLAN_H_
+#define _CB_WLAN_H_
+
+#include "cb_types.h"
+#include "cb_wlan_types.h"
+#include "cb_status.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+/**
+ * Max username length in @ref cbWLAN_EnterpriseConnectParameters
+ *
+ * @ingroup wlan
+ */
+#define cbWLAN_MAX_USERNAME_LENGTH      64
+
+/**
+ * Max password length in @ref cbWLAN_Util_PSKFromPWD and @ref cbWLAN_EnterpriseConnectParameters
+ *
+ * @ingroup wlan
+ */
+#define cbWLAN_MAX_PASSPHRASE_LENGTH    64
+
+/**
+ * PSK length in @ref cbWLAN_WPAPSKConnectParameters
+ *
+ * @ingroup wlan
+ */
+#define cbWLAN_PSK_LENGTH    32
+
+
+/**
+ * Max domain name length in @ref cbWLAN_EnterpriseConnectParameters
+ *
+ * @ingroup wlan
+ */
+#define cbWLAN_MAX_DOMAIN_LENGTH        64
+
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+typedef struct cbWLAN_Stream_s cbWLAN_Stream;
+typedef cb_uint32 cbWLAN_StreamPosition;
+
+/**
+ * Stream vtable interface used by WLAN supplicant to access SSL certificates
+ * for WPA Enterprise authentication.
+ *
+ * @ingroup wlan
+ */
+struct cbWLAN_Stream_s {
+    cb_int32 (*read)(const cbWLAN_Stream *stream, void *buf, cb_uint32 count);  /**< Read function pointer, place count bytes in buf. */
+    cb_int32 (*write)(const cbWLAN_Stream *stream, void *buf, cb_uint32 count);  /**< Read function pointer, place count bytes in buf. */
+    void (*rewind)(const cbWLAN_Stream *stream); /**< Rewind function pointer, rewind stream internal iterator to the beginning. Mandatory for all streams. */
+    void (*setPosition)(const cbWLAN_Stream *stream, cbWLAN_StreamPosition position); /**< Set absolute position. */
+    cbWLAN_StreamPosition (*getPosition)(const cbWLAN_Stream *stream); /**< Get current position. */
+    cb_uint32 (*getSize)(const cbWLAN_Stream *stream);  /**< GetSize function pointer, return total size of stream contents. */
+};
+
+/**
+ * Start parameters passed to WLAN driver.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_StartParameters {
+    cbWLAN_MACAddress      mac;        /**< MAC of WLAN interface, set to all zeros if hardware programmed address should be used. */
+    cb_boolean disable80211d;
+    cbWM_ModuleType  deviceType;      /**< Specify current device type. */
+    union {
+        struct {
+            cbWM_TxPowerSettings txPowerSettings;   /**< Transmission power settings. */
+        } ODIN_W26X;
+    } deviceSpecific;
+} cbWLAN_StartParameters;
+
+/**
+ * Common connect parameters.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_CommonConnectParameters {
+    cbWLAN_MACAddress      bssid;      /**< BSSID to connect to, set to all zero for any BSSID. */
+    cbWLAN_Ssid            ssid;       /**< SSID to connect to. */
+} cbWLAN_CommonConnectParameters;
+
+
+/**
+ * WEP specific connect parameters.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_WEPConnectParameters {
+    cbWLAN_WEPKey           keys[4];    /**< WEP keys. */
+    cb_uint32               txKey;      /**< Active WEP transmission key index (0-3). */
+} cbWLAN_WEPConnectParameters;
+
+/**
+* WPA PSK parameters.
+*
+* @ingroup wlan
+*/
+typedef struct cbWLAN_WPAPSK {
+    cb_uint8                key[cbWLAN_PSK_LENGTH]; /**< WPA pre-shared key in binary form. */
+} cbWLAN_WPAPSK;
+
+/**
+ * WPA PSK specific connect parameters.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_WPAPSKConnectParameters {
+    cbWLAN_WPAPSK           psk; /**< WPA pre-shared key*/
+} cbWLAN_WPAPSKConnectParameters;
+
+
+typedef enum cbWLAN_CipherSuite {
+    cbWLAN_CIPHER_SUITE_NONE        = 0x00,
+    cbWLAN_CIPHER_SUITE_WEP64       = 0x01,
+    cbWLAN_CIPHER_SUITE_WEP128      = 0x02,
+    cbWLAN_CIPHER_SUITE_TKIP        = 0x04,
+    cbWLAN_CIPHER_SUITE_AES_CCMP    = 0x08,
+} cbWLAN_CipherSuite;
+
+typedef enum cbWLAN_AuthenticationSuite {
+    cbWLAN_AUTHENTICATION_SUITE_NONE            = 0x00,
+    cbWLAN_AUTHENTICATION_SUITE_SHARED_SECRET   = 0x01,
+    cbWLAN_AUTHENTICATION_SUITE_PSK             = 0x02,
+    cbWLAN_AUTHENTICATION_SUITE_8021X           = 0x04,
+    cbWLAN_AUTHENTICATION_SUITE_USE_WPA         = 0x08,
+    cbWLAN_AUTHENTICATION_SUITE_USE_WPA2        = 0x10,
+} cbWLAN_AuthenticationSuite;
+
+
+/**
+ * WPA Enterprise specific connect parameters.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_EnterpriseConnectParameters {
+    cbWLAN_EnterpriseMode   authMode;       /**< Enterprise authentication mode. */
+    cb_uint8                username[cbWLAN_MAX_USERNAME_LENGTH];       /**< Username string. */
+    cb_uint8                passphrase[cbWLAN_MAX_PASSPHRASE_LENGTH];   /**< Passphrase string. */
+    cb_uint8                domain[cbWLAN_MAX_DOMAIN_LENGTH];           /**< Domain string. */
+    cbWLAN_Stream           *clientCertificate;     /**< Stream handle to provide SSL certificate for authentication. */
+    cbWLAN_Stream           *clientPrivateKey;      /**< STream handle to provide SSL private key for authentication. */
+} cbWLAN_EnterpriseConnectParameters;
+
+/**
+ * Common access point parameters.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_CommonApParameters {
+    cbWLAN_Ssid             ssid;       /**< SSID to connect to. */
+    cbWLAN_Channel          channel;    /**< Active channel. */
+    cbWLAN_RateMask         basicRates; /**< Basic rates. */
+}cbWLAN_CommonApParameters;
+
+
+/**
+* WPA PSK specific AP parameters.
+*
+* @ingroup wlan
+*/
+typedef struct cbWLAN_WPAPSKApParameters {
+    cbWLAN_CipherSuite      rsnCiphers; /**< Bit field indicating which ciphers that shall be displayed in RSN information elements. If 0 no RSN information elements is added to beacons and probe responses. */
+    cbWLAN_CipherSuite      wpaCiphers; /**< Bit field indicating which ciphers that shall be displayed in WPA information elements. If 0 no WPA information elements is added to beacons and probe responses. */
+    cbWLAN_WPAPSK           psk; /**< WPA pre-shared key*/
+} cbWLAN_WPAPSKApParameters;
+
+
+/**
+ * Scan parameters
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_ScanParameters {
+    cbWLAN_Ssid             ssid;       /**< SSID to scan for, set to zero length for broadcast scan. */
+} cbWLAN_ScanParameters;
+
+/**
+ * Scan result information reported from WLAN component. Contains info for
+ * one specific BSS.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_ScanIndicationInfo {
+    cbWLAN_MACAddress bssid;                /**< BSS BSSID */
+    cbWLAN_Ssid ssid;                       /**< BSS SSID */
+    cbWLAN_Channel channel;                 /**< BSS channel */
+    cbWLAN_OperationalMode operationalMode; /**< BSS type */
+    cb_int32 rssi;                          /**< RSSI for scan result packet. */
+
+    cbWLAN_AuthenticationSuite authenticationSuites; /**< Supported authentication suites */
+    cbWLAN_CipherSuite unicastCiphers;              /**< Supported unicast cipher suites */
+    cbWLAN_CipherSuite groupCipher;                 /**< Supported group cipher suites */
+
+    cbWLAN_RateMask basicRateSet;                   /**< Basic rate set, i.e. required rates. */
+    cbWLAN_RateMask supportedRateSet;               /**< Supported rate set, super set of basic rate set. */
+    cb_uint32 beaconPeriod;                         /**< Beacon period in ms. */
+    cb_uint32 DTIMPeriod;                           /**< DTIM period in beacon intervals */
+    cb_uint8 countryCode[3];                        /**< Three letter country code */
+    cb_uint32 flags;              // QoS, short preamble, DFS, privacy,
+} cbWLAN_ScanIndicationInfo;
+
+/**
+ * Status indications indicated by @ref cbWLAN_statusIndication.
+ *
+ * @ingroup wlan
+ */
+typedef enum {
+    cbWLAN_STATUS_STOPPED,
+    cbWLAN_STATUS_STARTED,
+    cbWLAN_STATUS_ERROR,
+    cbWLAN_STATUS_DISCONNECTED,
+    cbWLAN_STATUS_CONNECTING,
+    cbWLAN_STATUS_CONNECTED,
+    cbWLAN_STATUS_CONNECTION_FAILURE,
+    cbWLAN_STATUS_AP_UP,
+    cbWLAN_STATUS_AP_DOWN,
+    cbWLAN_STATUS_AP_STA_ADDED,
+    cbWLAN_STATUS_AP_STA_REMOVED,
+} cbWLAN_StatusIndicationInfo;
+
+/**
+ * Disconnection reasons for @ref cbWLAN_STATUS_DISCONNECTED.
+ *
+ * @ingroup wlan
+ */
+typedef enum {
+    cbWLAN_STATUS_DISCONNECTED_UNKNOWN,
+    cbWLAN_STATUS_DISCONNECTED_NO_BSSID_FOUND,
+    cbWLAN_STATUS_DISCONNECTED_AUTH_TIMEOUT,
+    cbWLAN_STATUS_DISCONNECTED_MIC_FAILURE, 
+} cbWLAN_StatusDisconnectedInfo;
+
+/**
+ * IOCTL parameters @ref cbWLAN_ioctl
+ *
+ * @ingroup wlan
+ */
+typedef enum {
+    cbWLAN_IOCTL_FIRST,
+    cbWLAN_IOCTL_SET_POWER_SAVE_MODE = cbWLAN_IOCTL_FIRST,       //!< Set power mode  @ref cbWLAN_IoctlPowerSaveMode
+    cbWLAN_IOCTL_GET_POWER_SAVE_MODE,                            //!< Get power mode  @ref cbWLAN_IoctlPowerSaveMode
+    cbWLAN_IOCTL_SET_LISTEN_INTERVAL,                            //!< Set listen interval, integer value 0 - 16 
+    cbWLAN_IOCTL_GET_LISTEN_INTERVAL,                            //!< Get listen interval, integer value 0 - 16 
+    cbWLAN_IOCTL_SET_DTIM_ENABLE,                                //!< Set DTIM enable 0, disable 1 enable
+    cbWLAN_IOCTL_GET_DTIM_ENABLE,                                //!< Get DTIM enable 0, disable 1 enable
+    cbWLAN_IOCTL_SET_SLEEP_TIMEOUT,                              //!< Set enter power save entry delay (in ms). Power save mode will be entered only if there no activity during this delay
+    cbWLAN_IOCTL_GET_SLEEP_TIMEOUT,                              //!< Get enter power save entry delay (in ms). Power save mode will be entered only if there no activity during this delay
+
+    cbWLAN_IOCTL_LAST,
+} cbWLAN_Ioctl;
+
+/**
+ * Power save modes set using  @ref cbWLAN_ioctl
+ *
+ * @ingroup wlan
+ */
+typedef enum {
+    cbWLAN_IOCTL_POWER_SAVE_MODE_OFF,
+    cbWLAN_IOCTL_POWER_SAVE_MODE_SLEEP,
+    cbWLAN_IOCTL_POWER_SAVE_MODE_DEEP_SLEEP
+} cbWLAN_IoctlPowerSaveMode;
+
+/**
+ * Start parameters indicated from WLAN driver for status indication 
+ * @ref cbWLAN_STATUS_STARTED.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_StatusStartedInfo {
+    cbWLAN_MACAddress macAddress;      /**< MAC address of WLAN driver. */
+} cbWLAN_StatusStartedInfo;
+
+/**
+ * Connected parameters indicated from WLAN driver for status indication 
+ * @ref cbWLAN_STATUS_CONNECTED.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_StatusConnectedInfo {
+    cbWLAN_MACAddress bssid;           /**< BSSID of the BSS connected to. */
+    cbWLAN_Channel channel;             /**< Operating channels of the BSS connected to. */
+} cbWLAN_StatusConnectedInfo;
+
+/**
+ * Received Ethernet data packet information and properties.
+ *
+ * @ingroup wlan
+ */
+typedef struct cbWLAN_PacketIndicationInfo {
+    void        *rxData;                /**< Pointer to the port specific data type. */
+    cb_uint32    size;                   /**< Length of the data payload in the port specific packet data type. */
+    cb_boolean  isChecksumVerified;     /**< True if the TCP/UDP checksum is verified and correct. */
+} cbWLAN_PacketIndicationInfo;
+
+/**
+ * Status updates from WLAN component. 
+ * @note The callback must not make any call back to WLAN.
+ *
+ * @param callbackContext Context pointer provided in @ref cbWLAN_registerStatusCallback.
+ * @param status Status indication type.
+ * @param data Additional status indication data, depends on indication type.
+ *
+ * @sa cbWLAN_registerStatusCallback
+ */
+typedef void (*cbWLAN_statusIndication)(void *callbackContext, cbWLAN_StatusIndicationInfo status, void *data);
+
+
+/**
+ * Indication of received Ethernet data packet.
+ *
+ * @param callbackContext Context pointer provided in @ref cbWLAN_init.
+ * @param packetInfo Pointer to struct containing packet information and data pointers.
+ */
+typedef void (*cbWLAN_packetIndication)(void *callbackContext, cbWLAN_PacketIndicationInfo *packetInfo);
+
+/**
+* Scan result indication from WLAN component.
+*
+* @param callbackContext Context pointer provided in @ref cbWLAN_init.
+* @param bssDescriptor Pointer to struct containing scan result information.
+* @param isLastResult @ref TRUE if scan scan is finished.
+*/
+typedef void (*cbWLAN_scanIndication)(void *callbackContext, cbWLAN_ScanIndicationInfo *bssDescriptor, cb_boolean isLastResult);
+
+/*===========================================================================
+ * WLAN API
+ *=========================================================================*/
+
+/**
+ * Initialize WLAN component.
+ *
+ * @param callbackContext Context handle used in indication callbacks.
+ * @return @ref cbSTATUS_OK if successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_init(void *callbackContext);
+
+
+/**
+ * Stop WLAN component.
+ * Stop and destroy WLAN driver instance.
+ *
+ * @return @ref cbSTATUS_OK if successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_stop(void);
+
+/**
+ * Connect to access point in open mode (no encryption).
+ * Connection progress is reported as @ref cbWLAN_statusIndication callbacks.
+ *
+ * @param commonParams Connection parameters.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. 
+ */
+cbRTSL_Status cbWLAN_connectOpen(cbWLAN_CommonConnectParameters *commonParams);
+
+/**
+ * Connect to access point in open mode with WEP encryption.
+ * Connection progress is reported as @ref cbWLAN_statusIndication callbacks.
+ *
+ * @param commonParams Connection parameters.
+ * @param wepParams WEP specific connection parameters.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. 
+ */
+cbRTSL_Status cbWLAN_connectWEP(cbWLAN_CommonConnectParameters *commonParams, cbWLAN_WEPConnectParameters *wepParams);
+
+/**
+ * Connect to access point with WPA PSK authentication.
+ * Connection progress is reported as @ref cbWLAN_statusIndication callbacks.
+ *
+ * @param commonParams Connection parameters.
+ * @param wpaParams WPA PSK specific connection parameters.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. 
+ */
+cbRTSL_Status cbWLAN_connectWPAPSK(cbWLAN_CommonConnectParameters *commonParams, cbWLAN_WPAPSKConnectParameters *wpaParams);
+
+/**
+ * Disconnect from access point or stop ongoing connection attempt.
+ * Disconnection progress is reported as @ref cbWLAN_statusIndication callback.
+ *
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. 
+ */
+cbRTSL_Status cbWLAN_disconnect(void);
+
+/**
+ * Initiate BSS scan.
+ * If specific channel is set in scan parameters, only that channel is 
+ * scanned. If SSID is specified, a directed probe request against that SSID
+ * will be used. Scan results are reported in @ref cbWLAN_scanIndication 
+ * callbacks.
+ * @note Depending on channel using DFS or not, passive scans may be used 
+ * instead of active probe requests.
+ *
+ * @param params Scan parameters
+ * @param scanIndication Callback function for scan results.
+ * @param callbackContext Context pointer, will be sent back in callback.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_scan(cbWLAN_ScanParameters *params, cbWLAN_scanIndication scanIndication, void *callbackContext);
+
+
+/**
+* Retrieve an RSSI value for station mode.
+*
+* @note Depending on connection state and data transfer interval
+* the value may be incorrect.
+*
+* @return RSSI value in dBm
+*/
+cb_int16 cbWLAN_STA_getRSSI();
+
+/**
+ * Start access point in open mode (no encryption).
+ * Connection progress is reported as @ref cbWLAN_statusIndication callbacks.
+ *
+ * @param commonParams Common Accesspoint parameters.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. 
+ */
+cbRTSL_Status cbWLAN_apStartOpen(cbWLAN_CommonApParameters *commonParams);
+
+/**
+* Start access point with WPA PSK authentication.
+* Connection progress is reported as @ref cbWLAN_statusIndication callbacks.
+*
+* @param commonParams Common Accesspoint parameters.
+* @param wpaParams WPA PSK specific parameters.
+* @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+*/
+cbRTSL_Status cbWLAN_apStartWPAPSK(cbWLAN_CommonApParameters *commonParams, cbWLAN_WPAPSKApParameters *wpaParams);
+
+/**
+ * Stop access point.
+ *
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. 
+ */
+cbRTSL_Status cbWLAN_apStop(void);
+
+/**
+ * Send an Ethernet data packet.
+ * @note Data send when not in connected state is just dropped.
+ *
+ * @param txData Pointer to the port specific Ethernet data type containing transmit data
+ */
+void cbWLAN_sendPacket(void *txData);
+
+/**
+ * Register a status indication callback.
+ * @note There may be multiple clients connected.
+ *
+ * @param statusIndication Callback function.
+ * @param callbackContext Context pointer, will be sent back in callback.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. 
+ */
+cbRTSL_Status cbWLAN_registerStatusCallback(cbWLAN_statusIndication statusIndication, void *callbackContext);
+
+
+/**
+ * Register a status indication callback.
+ *
+ * @param packetIndication Callback function.
+ * @param callbackContext Context pointer, will be sent back in callback.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. 
+ */
+cbRTSL_Status cbWLAN_registerPacketIndicationCallback(cbWLAN_packetIndication packetIndication, void *callbackContext);
+
+/**
+ * Deregister the specified status indication callback.
+ *
+ * @param statusIndication Callback function.
+ * @param callbackContext Context pointer, will be sent back in callback.
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR. 
+ */
+cbRTSL_Status cbWLAN_deregisterStatusCallback(cbWLAN_statusIndication statusIndication, void *callbackContext);
+
+
+cbRTSL_Status cbWLAN_Util_PSKFromPWD(cb_char passphrase[cbWLAN_MAX_PASSPHRASE_LENGTH], cbWLAN_Ssid ssid, cb_uint8 psk[cbWLAN_PSK_LENGTH]);
+
+/**
+ * Set the channel list to be used for connection and scanning.
+ * The list will be filtered according to the allowed channel list
+ * set. The list can include both 2.4GHz and 5GHz channels.
+ * If channel list parameter is NULL the default channel list is 
+ * restored.
+ * 
+ * @param channelList Pointer to channel list for the driver to use.
+ *
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_setChannelList(const cbWLAN_ChannelList *channelList);
+
+/**
+ * Returns the wanted channel list.
+ *
+ * @param channelList Pointer to channel list
+ *
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_getChannelList(cbWLAN_ChannelList *channelList);
+
+/**
+ * Returns the channel list currently used. This channel list
+ * depend on the channel list specified by the user and the 
+ * current regulatory domain.
+ *
+ * @param channelList Pointer to channel list
+ * 
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_getActiveChannelList(cbWLAN_ChannelList *channelList);
+
+/**
+ * WLAN control settings. Both in and out parameters are supported. 
+ * If an ioctl request is not supported cbSTATUS_ERROR is returned and 
+ * the value parameter shall be ignored.
+ *
+ * @param ioctl Parameter that shall be set. @ref cbWLAN_Ioctl lists all supported parameters.
+ * @param value Value. @ref cbWLAN_Ioctl lists the type for all supported parameters.
+ *
+ * @return @ref cbSTATUS_OK if call successful, otherwise cbSTATUS_ERROR.
+ */
+cbRTSL_Status cbWLAN_ioctl(cbWLAN_Ioctl ioctl, void* value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CB_WLAN_H_ */
+
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h
new file mode 100644
index 00000000000..9136b91f0d6
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h
@@ -0,0 +1,119 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : Wireless LAN driver
+ * File        : cb_wlan_target_data.h
+ *
+ * Description : Port specific data buffer handling (ethernet frames)
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_wlan_target_data.h Handles the anonymous port specific packetization 
+ * of ethernet frames.
+ * @ingroup target
+ */
+
+#ifndef _CB_WLANTARGET_DATA_H_
+#define _CB_WLANTARGET_DATA_H_
+
+#include "cb_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+typedef struct cbWLANTARGET_dataFrame cbWLANTARGET_dataFrame;
+typedef struct cbWLANTARGET_Handle cbWLANTARGET_Handle;
+
+   
+/**
+ * Copy data from frame data memory to buffer.
+ *
+ * @param buffer            The destination buffer.
+ * @param frame             Frame memory pointer (@ref cbWLANTARGET_allocDataFrame).
+ * @param size              Number of bytes to copy.
+ * @param offsetInFrame     Offset into frame memory.
+ * @return                  @ref TRUE if successful, otherwise @ref FALSE.
+ */
+typedef cb_boolean(*cbWLANTARGET_copyFromDataFrame)(cb_uint8* buffer, cbWLANTARGET_dataFrame* frame, cb_uint32 size, cb_uint32 offsetInFrame);
+
+/**
+ * Copy data from buffer to frame data memory.
+ *
+ * @param frame             Frame memory pointer (@ref cbWLANTARGET_allocDataFrame).
+ * @param buffer            The destination buffer.
+ * @param size              Number of bytes to copy.
+ * @param offsetInFrame     Offset into frame memory.
+ * @return                  @ref TRUE if successful, otherwise @ref FALSE.
+ */
+typedef cb_boolean(*cbWLANTARGET_copyToDataFrame)(cbWLANTARGET_dataFrame* frame, cb_uint8* buffer, cb_uint32 size, cb_uint32 offsetInFrame);
+
+/**
+ * Allocate memory in frame data memory.
+ *
+ * @param size              Number of bytes to allocate.
+ * @return                  Pointer to the frame memory.
+ * 
+ * @ref cbWLANTARGET_freeDataFrame
+ */
+typedef cbWLANTARGET_dataFrame*(*cbWLANTARGET_allocDataFrame)(cb_uint32 size);
+
+/**
+ * Destroy memory in frame data memory.
+ *
+ * @param frame             Pointer to the frame memory that should be destroyed.
+ * @ref cbWLANTARGET_allocDataFrame
+ */
+typedef void(*cbWLANTARGET_freeDataFrame)(cbWLANTARGET_dataFrame* frame);
+
+typedef cb_uint32(*cbWLANTARGET_getDataFrameSize)(cbWLANTARGET_dataFrame* frame);
+
+typedef cb_uint8(*cbWLANTARGET_getDataFrameTID)(cbWLANTARGET_dataFrame* frame);
+
+typedef struct
+{
+    cbWLANTARGET_copyFromDataFrame      copyFromDataFrameIndication;
+    cbWLANTARGET_copyToDataFrame        copyToDataFrameIndication;
+    cbWLANTARGET_allocDataFrame         allocDataFrameIndication;
+    cbWLANTARGET_freeDataFrame          freeDataFrameIndication;
+    cbWLANTARGET_getDataFrameSize       getDataFrameSizeIndication;
+    cbWLANTARGET_getDataFrameTID        getDataFrameTIDIndication;
+}cbWLANTARGET_Callback;
+    
+/*===========================================================================
+ * FUNCTIONS
+ *=========================================================================*/
+
+/**
+ * Register WLAN target callbacks. This should be done for packetization between
+ * the WLAN driver and an IP stack.
+ *
+ * @param callbacks           Callbacks
+ */
+void cbWLANTARGET_registerCallbacks(cbWLANTARGET_Callback* callbacks);
+    
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h
new file mode 100644
index 00000000000..7774d44a246
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h
@@ -0,0 +1,552 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2016, u-blox Malmö, All Rights Reserved
+ * SPDX-License-Identifier: LicenseRef-PBL
+ *
+ * This file and the related binary are licensed under the
+ * Permissive Binary License, Version 1.0 (the "License");
+ * you may not use these files except in compliance with the License.
+ *
+ * You may obtain a copy of the License here:
+ * LICENSE-permissive-binary-license-1.0.txt and at
+ * https://www.mbed.com/licenses/PBL-1.0
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Component   : WLAN driver
+ * File        : cb_wlan_types.h
+ *
+ * Description : Common wireless LAN defines and types.
+ *-------------------------------------------------------------------------*/
+
+/**
+ * @file cb_wlan_types.h The main WLAN 802.11 interface
+ *
+ * @ingroup WLANDriver
+ */
+
+#ifndef _CB_WLAN_TYPES_H_
+#define _CB_WLAN_TYPES_H_
+
+#include "cb_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*===========================================================================
+ * DEFINES
+ *=========================================================================*/
+
+/**
+ * Max length for an SSID
+ *
+ * @ingroup wlantypes
+ */
+#define cbWLAN_SSID_MAX_LENGTH (32)
+
+/**
+ * EAPOL ethernet type
+ *
+ * @ingroup wlantypes
+ */
+#define cbWLAN_ETHTYPE_EAPOL     (0x888E)
+
+/**
+ * Maximum size of a predefined WEP key
+ *
+ * @ingroup wlantypes
+ */
+#define cbWLAN_KEY_SIZE_WEP_MAX (cbWLAN_KEY_SIZE_WEP128)
+
+#define cbWLAN_OUI_SIZE                    3
+
+#define cbRATE_MASK_B   (cbRATE_MASK_01 | cbRATE_MASK_02 | cbRATE_MASK_5_5 | cbRATE_MASK_11)
+#define cbRATE_MASK_G   (cbRATE_MASK_06 | cbRATE_MASK_09 | cbRATE_MASK_12 | cbRATE_MASK_18 | cbRATE_MASK_24 | cbRATE_MASK_36 | cbRATE_MASK_48 | cbRATE_MASK_54)
+#define cbRATE_MASK_N   (cbRATE_MASK_MCS0 | cbRATE_MASK_MCS1 | cbRATE_MASK_MCS2 | cbRATE_MASK_MCS3 | cbRATE_MASK_MCS4 | cbRATE_MASK_MCS5 | cbRATE_MASK_MCS6 | cbRATE_MASK_MCS7)
+#define cbRATE_MASK_ALL (cbRATE_MASK_B | cbRATE_MASK_G | cbRATE_MASK_N)
+
+#define cbWLAN_MAX_CHANNEL_LIST_LENGTH      38
+
+#define cbWLAN_TX_POWER_AUTO    0xFF
+
+/*===========================================================================
+ * TYPES
+ *=========================================================================*/
+
+/** 
+ * The encryption mode.
+ *
+ * @ingroup wlantypes
+ */
+typedef enum cbWLAN_EncryptionMode_e {
+    cbWLAN_ENC_NONE,
+    cbWLAN_ENC_WEP64,
+    cbWLAN_ENC_WEP128,
+    cbWLAN_ENC_TKIP,
+    cbWLAN_ENC_AES,
+} cbWLAN_EncryptionMode;
+
+
+/**  
+ * Enterprise authentication mode.
+ *
+ * @ingroup wlan
+ */
+typedef enum cbWLAN_EnterpriseMode {
+    cbWLAN_ENTERPRISE_MODE_LEAP,
+    cbWLAN_ENTERPRISE_MODE_PEAP,
+    cbWLAN_ENTERPRISE_MODE_EAPTLS,
+} cbWLAN_EnterpriseMode;
+
+/**
+ * Key sizes for the supported encryptions.
+ *
+ * @ingroup wlantypes
+ */
+typedef enum cbWLAN_EncryptionKeySize_e {
+    cbWLAN_KEY_SIZE_WEP64      = 5,
+    cbWLAN_KEY_SIZE_WEP128     = 13,
+    cbWLAN_KEY_SIZE_WEP2       = 16,
+    cbWLAN_KEY_SIZE_TKIP       = 16,    
+    cbWLAN_KEY_SIZE_AES        = 16,
+    cbWLAN_KEY_SIZE_TKIP_MIC   = 8
+} cbWLAN_EncryptionKeySize;
+
+enum cbWLAN_Channel_e {
+    cbWLAN_CHANNEL_ALL = 0,
+    cbWLAN_CHANNEL_01 = 1,
+    cbWLAN_CHANNEL_02,
+    cbWLAN_CHANNEL_03,
+    cbWLAN_CHANNEL_04,
+    cbWLAN_CHANNEL_05,
+    cbWLAN_CHANNEL_06,
+    cbWLAN_CHANNEL_07,
+    cbWLAN_CHANNEL_08,
+    cbWLAN_CHANNEL_09,
+    cbWLAN_CHANNEL_10,
+    cbWLAN_CHANNEL_11,
+    cbWLAN_CHANNEL_12,
+    cbWLAN_CHANNEL_13,
+    cbWLAN_CHANNEL_14,
+
+    cbWLAN_CHANNEL_36 = 36,
+    cbWLAN_CHANNEL_40 = 40,
+    cbWLAN_CHANNEL_44 = 44,
+    cbWLAN_CHANNEL_48 = 48,
+    cbWLAN_CHANNEL_52 = 52,
+    cbWLAN_CHANNEL_56 = 56,
+    cbWLAN_CHANNEL_60 = 60,
+    cbWLAN_CHANNEL_64 = 64,
+    cbWLAN_CHANNEL_100 = 100,
+    cbWLAN_CHANNEL_104 = 104,
+    cbWLAN_CHANNEL_108 = 108,
+    cbWLAN_CHANNEL_112 = 112,
+    cbWLAN_CHANNEL_116 = 116,
+    cbWLAN_CHANNEL_120 = 120,
+    cbWLAN_CHANNEL_124 = 124,
+    cbWLAN_CHANNEL_128 = 128,
+    cbWLAN_CHANNEL_132 = 132,
+    cbWLAN_CHANNEL_136 = 136,
+    cbWLAN_CHANNEL_140 = 140,
+    cbWLAN_CHANNEL_149 = 149,
+    cbWLAN_CHANNEL_153 = 153,
+    cbWLAN_CHANNEL_157 = 157,
+    cbWLAN_CHANNEL_161 = 161,
+    cbWLAN_CHANNEL_165 = 165
+};
+
+/**
+ * WLAN Channels
+ * Valid values are found in @ref cbWLAN_Channel_e
+ * @ingroup wlantypes
+ */
+typedef cb_uint8 cbWLAN_Channel;
+
+/**
+ * WLAN Channel list
+ * @ingroup wlantypes
+ */
+typedef struct {
+    cb_uint32 length;
+    cbWLAN_Channel channels[cbWLAN_MAX_CHANNEL_LIST_LENGTH];
+} cbWLAN_ChannelList;
+
+/**
+ * Standard 802.11 rates
+ *
+ * @ingroup wlantypes
+ */
+enum cbWLAN_Rate_e {    
+    cbWLAN_RATE_01 = 1, // 1
+    cbWLAN_RATE_02,     // 2
+    cbWLAN_RATE_5_5,    // 3
+    cbWLAN_RATE_06,     // 4
+    cbWLAN_RATE_09,     // 5
+    cbWLAN_RATE_11,     // 6
+    cbWLAN_RATE_12,     // 7
+    cbWLAN_RATE_18,     // 8 
+    cbWLAN_RATE_24,     // 9 
+    cbWLAN_RATE_36,     // 10 
+    cbWLAN_RATE_48,     // 11
+    cbWLAN_RATE_54,     // 12
+    cbWLAN_RATE_MCS0,   // 13
+    cbWLAN_RATE_MCS1,   // 14
+    cbWLAN_RATE_MCS2,   // 15
+    cbWLAN_RATE_MCS3,   // 16
+    cbWLAN_RATE_MCS4,   // 17
+    cbWLAN_RATE_MCS5,   // 18
+    cbWLAN_RATE_MCS6,   // 19
+    cbWLAN_RATE_MCS7,   // 20
+    cbWLAN_RATE_MCS8,   // 21
+    cbWLAN_RATE_MCS9,   // 22
+    cbWLAN_RATE_MCS10,  // 23
+    cbWLAN_RATE_MCS11,  // 24
+    cbWLAN_RATE_MCS12,  // 25
+    cbWLAN_RATE_MCS13,  // 26
+    cbWLAN_RATE_MCS14,  // 27
+    cbWLAN_RATE_MCS15,  // 28
+};
+
+/**
+ * Type for containing values found in @ref cbWLAN_Rate_e
+ * @ingroup wlantypes
+ */
+typedef cb_uint8 cbWLAN_Rate;
+
+
+/**
+ * Mask bits for standard 802.11 rates
+ *
+ * @ingroup wlantypes
+ */
+enum cbWLAN_RateMask_e {    
+    cbRATE_MASK_01 = 0x00000001,
+    cbRATE_MASK_02 = 0x00000002,
+    cbRATE_MASK_5_5 = 0x00000004,
+    cbRATE_MASK_11 = 0x00000008,
+    cbRATE_MASK_06 = 0x00000010,
+    cbRATE_MASK_09 = 0x00000020,
+    cbRATE_MASK_12 = 0x00000040,
+    cbRATE_MASK_18 = 0x00000080,
+    cbRATE_MASK_24 = 0x00000100,
+    cbRATE_MASK_36 = 0x00000200,
+    cbRATE_MASK_48 = 0x00000400,
+    cbRATE_MASK_54 = 0x00000800,
+    // NOTE: Don't move MCS rates bit offset, see note on define below
+    cbRATE_MASK_MCS0 = 0x00001000,
+    cbRATE_MASK_MCS1 = 0x00002000,
+    cbRATE_MASK_MCS2 = 0x00004000,
+    cbRATE_MASK_MCS3 = 0x00008000,
+    cbRATE_MASK_MCS4 = 0x00010000,
+    cbRATE_MASK_MCS5 = 0x00020000,
+    cbRATE_MASK_MCS6 = 0x00040000,
+    cbRATE_MASK_MCS7 = 0x00080000,
+    cbRATE_MASK_MCS8 = 0x00100000,
+    cbRATE_MASK_MCS9 = 0x00200000,
+    cbRATE_MASK_MCS10 = 0x00400000,
+    cbRATE_MASK_MCS11 = 0x00800000,
+    cbRATE_MASK_MCS12 = 0x01000000,
+    cbRATE_MASK_MCS13 = 0x02000000,
+    cbRATE_MASK_MCS14 = 0x04000000,
+    cbRATE_MASK_MCS15 = 0x08000000,
+};
+
+/**
+ * Access categories
+ *
+ * @ingroup wlantypes
+ */
+typedef enum cbWLAN_AccessCategory_e {
+    cbWLAN_AC_BK = 1, /**< Background  */
+    cbWLAN_AC_SP = 2, /**< Background (Spare) */
+
+    cbWLAN_AC_BE = 0, /**< Best effort  */
+    cbWLAN_AC_EE = 3, /**< Best effort (Excellent Effort) */
+
+    cbWLAN_AC_CL = 4, /**< Video (Controlled Load) */
+    cbWLAN_AC_VI = 5, /**< Video  */
+
+    cbWLAN_AC_VO = 6, /**< Voice */
+    cbWLAN_AC_NC = 7, /**< Voice (Network Control)*/
+} cbWLAN_AccessCategory;
+
+
+
+/**
+* connectBlue Hardware Identification
+*
+* @ingroup types
+*/
+typedef enum cbWM_ModuleType_e {
+    cbWM_MODULE_UNKNOWN,
+    cbWM_MODULE_OWL22X,
+    cbWM_MODULE_OWL253,
+    cbWM_MODULE_OWS451,
+    cbWM_MODULE_OWL351,
+    cbWM_MODULE_ODIN_W16X = cbWM_MODULE_OWL351,
+    cbWM_MODULE_ODIN_W26X,
+} cbWM_ModuleType;
+
+/**
+ * Mac address type
+ *
+ * @ingroup wlantypes
+ */
+typedef cb_uint8 cbWLAN_MACAddress[6];
+
+/**
+ * Type for containing values found in @ref cbWLAN_RateMask_e
+ * @ingroup wlantypes
+ */
+typedef cb_uint32 cbWLAN_RateMask;
+
+/**
+* Transmission power
+*
+* @ingroup wlantypes
+*/
+typedef cb_uint8 cbWLAN_TxPower;
+
+/**
+ * The different frequency bands to choose from.
+ *
+ * @ingroup wlantypes
+ */
+typedef enum cbWLAN_Band_e {
+    cbWLAN_BAND_UNDEFINED,
+    cbWLAN_BAND_2_4GHz,
+    cbWLAN_BAND_5GHz,
+} cbWLAN_Band;
+
+/**
+ * The operational mode.
+ *
+ * @ingroup wlantypes
+ */
+typedef enum cbWLAN_OperationalMode_e {
+    cbWLAN_OPMODE_MANAGED,
+    cbWLAN_OPMODE_ADHOC,    
+} cbWLAN_OperationalMode;
+
+/**
+ * Encryption key type
+ *
+ * @ingroup wlantypes
+ */
+typedef enum cbWLAN_KeyType_e {
+    cbWLAN_KEY_UNICAST,
+    cbWLAN_KEY_BROADCAST,
+} cbWLAN_KeyType;
+
+typedef enum {
+    cbWLAN_CONNECT_MODE_OPEN,
+    cbWLAN_CONNECT_MODE_WEP_OPEN,
+    cbWLAN_CONNECT_MODE_WPA_PSK,
+    cbWLAN_CONNECT_MODE_ENTERPRISE,
+} cbWLAN_ConnectMode;
+
+typedef enum {
+    cbWLAN_AP_MODE_OPEN,
+    cbWLAN_AP_MODE_WEP_OPEN,
+    cbWLAN_AP_MODE_WPA_PSK,
+    cbWLAN_AP_MODE_ENTERPRISE,
+} cbWLAN_ApMode;
+
+/** 
+ * Ethernet header
+ *
+ * @ingroup wlantypes
+ */
+cb_PACKED_STRUCT_BEGIN(cbWLAN_EthernetHeader) {
+    cbWLAN_MACAddress   dest;
+    cbWLAN_MACAddress   src;
+    cb_uint16           type;
+} cb_PACKED_STRUCT_END(cbWLAN_EthernetHeader);
+
+
+cb_PACKED_STRUCT_BEGIN(cbWLAN_EthernetFrame) {
+    cbWLAN_EthernetHeader header;
+    cb_uint8            payload[cb_EMPTY_ARRAY];
+} cb_PACKED_STRUCT_END(cbWLAN_EthernetFrame);
+
+/** 
+ * SNAP header
+ *
+ * @ingroup wlantypes
+ */
+cb_PACKED_STRUCT_BEGIN(cbWLAN_SNAPHeader) {
+    cb_uint8    dsap;
+    cb_uint8    ssap;
+    cb_uint8    ctrl;
+    cb_uint8    encapsulation[3];
+    cb_uint16   ethType;
+} cb_PACKED_STRUCT_END(cbWLAN_SNAPHeader);
+
+cb_PACKED_STRUCT_BEGIN(cbWLAN_SNAPFrame) {
+    cbWLAN_SNAPHeader header;
+    cb_uint8    payload[cb_EMPTY_ARRAY];
+} cb_PACKED_STRUCT_END(cbWLAN_SNAPFrame);
+
+
+/**
+ * Defines an ssid.
+ *
+ * @ingroup wlantypes
+ */
+typedef struct cbWLAN_Ssid_s {    
+    cb_uint8 ssid[cbWLAN_SSID_MAX_LENGTH];
+    cb_uint32 ssidLength;
+} cbWLAN_Ssid;
+
+/**
+ * Defines one wep key.
+ *
+ * @ingroup wlantypes
+ */
+typedef struct cbWLAN_WepKey_s {
+    cb_uint8 key[cbWLAN_KEY_SIZE_WEP_MAX];
+    cb_uint32 length;
+} cbWLAN_WEPKey;
+
+/**
+* Describes host revisions.
+* @see cbWM_Version
+*
+* @ingroup types
+*/
+typedef struct {
+    struct {
+        cb_uint32 major;
+        cb_uint32 minor;
+        cb_uint32 patch1;
+    } software;
+    struct {
+        const char* id;
+    } manufacturer;
+} cbWM_DriverRevision;
+
+/**
+* Describes firmware revisions.
+* @see cbWM_Version
+*
+* @ingroup types
+*/
+typedef struct {
+    struct {
+        cb_uint32 major;
+        cb_uint32 minor;
+        cb_uint32 patch1;
+        cb_uint32 patch2;
+    } firmware;
+    struct {
+        const char* id;
+    } manufacturer;
+} cbWM_FWRevision;
+
+/**
+* Describes firmware revisions. Is divided into three parts; one for the
+* host driver side, one for target firmware, and one information string
+* descibing the HW manufacturer.
+*
+* @ingroup types
+*/
+typedef struct version_st{
+    cbWM_DriverRevision host;
+    cbWM_FWRevision target;
+} cbWM_Version;
+
+/**
+* Describes power levels for dynamic power level control.
+*
+* @ingroup types
+*/
+typedef struct cbWM_TxPowerSettings_s {
+    cbWLAN_TxPower lowTxPowerLevel;
+    cbWLAN_TxPower medTxPowerLevel;
+    cbWLAN_TxPower maxTxPowerLevel;
+} cbWM_TxPowerSettings;
+
+/**
+* Describes an access point.
+*
+* @ingroup types
+*/
+typedef struct cbWLAN_ApInformation {
+    cbWLAN_Ssid                 ssid;                   /**< SSID */
+    cbWLAN_MACAddress           bssid;                  /**< BSSID */
+    cbWLAN_Channel              channel;                /**< Channel */
+} cbWLAN_ApInformation;
+
+/**
+* Describes a station connected to an access point.
+*
+* @ingroup types
+*/
+typedef struct cbWLAN_ApStaInformation {
+    cbWLAN_MACAddress MAC;
+} cbWLAN_ApStaInformation;
+
+/*---------------------------------------------------------------------------
+ * VARIABLE DECLARATIONS
+ *-------------------------------------------------------------------------*/
+extern const cbWLAN_MACAddress nullMac;
+extern const cbWLAN_MACAddress broadcastMac;
+
+extern const cb_uint8 OUI_Microsoft[cbWLAN_OUI_SIZE];
+extern const cb_uint8 OUI_Epigram[cbWLAN_OUI_SIZE];
+extern const cb_uint8 OUI_ConnectBlue[cbWLAN_OUI_SIZE];
+extern const cb_uint8 OUI_IEEE8021[cbWLAN_OUI_SIZE];
+
+extern const cb_uint8 PATTERN_HTInformationDraft[1];
+extern const cb_uint8 PATTERN_TKIP[2];
+extern const cb_uint8 PATTERN_WME_IE[3];
+extern const cb_uint8 PATTERN_WME_PE[3];
+
+/*---------------------------------------------------------------------------
+ * FUNCTIONS
+ *-------------------------------------------------------------------------*/
+
+/**
+ * Misc
+ */
+
+/**
+ * Returns the correct frequency @ref cbWLAN_Band band based on the input channel.
+ *
+ * For @ref cbWLAN_CHANNEL_ALL This function will return @ref cbWLAN_BAND_2_4GHz.
+ *
+ * @param channel The channel to be queried for band.
+ * @return The @ref cbWLAN_Band band for the requested channel.
+ */
+cbWLAN_Band cbWLAN_getBandFromChannel(cbWLAN_Channel channel);
+
+/**
+* Returns the valid rates @ref cbWLAN_RateMask based for the channel.
+*
+* @param channel The channel to be queried for rates.
+* @return The valid rates @ref cbWLAN_RateMask for the requested channel.
+*/
+cbWLAN_RateMask cbWLAN_getRatesForChannel(cbWLAN_Channel channel);
+
+/**
+ * Checks is the input rate is a 802.11n rate or not.
+ *
+ * @param rate The rate to check
+ * @return @ref TRUE if the input rate is an n-rate. @ref FALSE otherwise.
+ */
+cb_boolean cbWLAN_isNRate(cbWLAN_Rate rate);
+
+/**
+ * Checks if a channel is valid 
+ *
+ * @return @ref TRUE if the channel is valid. @ref FALSE otherwise.
+ */
+cb_boolean cbWLAN_isValidChannel(cbWLAN_Channel channel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp
new file mode 100644
index 00000000000..6a9dd6497f5
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp
@@ -0,0 +1,327 @@
+
+#include <stdio.h>
+#include "cb_main.h"
+#include "cb_wlan.h"
+#include "cb_wlan_types.h"
+#include "cb_otp.h"
+#include "cb_wlan_target_data.h"
+#include "emac_api.h"
+#include "mbed_assert.h"
+#include "rtos.h"
+#include "mbed_events.h"
+
+/*===========================================================================
+* DEFINES
+*=========================================================================*/
+#define WIFI_EMAC_API_MTU_SIZE  (1500U)
+
+/*===========================================================================
+* TYPES
+*=========================================================================*/
+typedef struct {
+    emac_link_input_fn wifi_input_cb;
+    emac_link_state_change_fn wifi_state_cb;
+    void* link_input_user_data;
+    void* link_state_user_data;
+    bool linkStateRegistered;
+} wifi_emac_api_s;
+
+/*===========================================================================
+* DECLARATIONS
+*=========================================================================*/
+static void statusIndication(void *dummy, cbWLAN_StatusIndicationInfo status, void *data);
+static void packetIndication(void *dummy, cbWLAN_PacketIndicationInfo *packetInfo);
+static cb_boolean handleWlanTargetCopyFromDataFrame(uint8_t* buffer, cbWLANTARGET_dataFrame* frame, uint32_t size, uint32_t offsetInFrame);
+static cb_boolean handleWlanTargetCopyToDataFrame(cbWLANTARGET_dataFrame* frame, uint8_t* buffer, uint32_t size, uint32_t offsetInFrame);
+static cbWLANTARGET_dataFrame* handleWlanTargetAllocDataFrame(uint32_t size);
+static void handleWlanTargetFreeDataFrame(cbWLANTARGET_dataFrame* frame);
+static cb_uint32 handleWlanTargetGetDataFrameSize(cbWLANTARGET_dataFrame* frame);
+static cb_uint8 handleWlanTargetGetDataFrameTID(cbWLANTARGET_dataFrame* frame);
+
+static uint32_t wifi_get_mtu_size(emac_interface_t *emac);
+static void wifi_get_ifname(emac_interface_t *emac, char *name, uint8_t size);
+static uint8_t wifi_get_hwaddr_size(emac_interface_t *emac);
+static void wifi_get_hwaddr(emac_interface_t *emac, uint8_t *addr);
+static void wifi_set_hwaddr(emac_interface_t *emac, uint8_t *addr);
+static bool wifi_link_out(emac_interface_t *emac, emac_stack_mem_t *buf);
+static bool wifi_power_up(emac_interface_t *emac);
+static void wifi_power_down(emac_interface_t *emac);
+static void wifi_set_link_input_cb(emac_interface_t *emac, emac_link_input_fn input_cb, void *data);
+static void wifi_set_link_state_cb(emac_interface_t *emac, emac_link_state_change_fn state_cb, void *data);
+
+/*===========================================================================
+* DEFINITIONS
+*=========================================================================*/
+static wifi_emac_api_s _admin;
+static const char _ifname[] = "WL0";
+
+const emac_interface_ops_t wifi_emac_interface = {
+    .get_mtu_size = wifi_get_mtu_size,
+    .get_ifname = wifi_get_ifname,
+    .get_hwaddr_size = wifi_get_hwaddr_size,
+    .get_hwaddr = wifi_get_hwaddr,
+    .set_hwaddr = wifi_set_hwaddr,
+    .link_out = wifi_link_out,
+    .power_up = wifi_power_up,
+    .power_down = wifi_power_down,
+    .set_link_input_cb = wifi_set_link_input_cb,
+    .set_link_state_cb = wifi_set_link_state_cb
+};
+
+static emac_interface_t _intf = { wifi_emac_interface, NULL };
+
+static const cbWLANTARGET_Callback _wlanTargetCallback =
+{
+    handleWlanTargetCopyFromDataFrame,
+    handleWlanTargetCopyToDataFrame,
+    handleWlanTargetAllocDataFrame,
+    handleWlanTargetFreeDataFrame,
+    handleWlanTargetGetDataFrameSize,
+    handleWlanTargetGetDataFrameTID
+};
+
+/*===========================================================================
+* FUNCTIONS
+*=========================================================================*/
+static void statusIndication(void *dummy, cbWLAN_StatusIndicationInfo status, void *data)
+{
+    bool linkUp = false;
+    bool sendCb = true;
+    (void)dummy;
+    (void)data;
+
+    switch (status) {
+        case cbWLAN_STATUS_CONNECTED:
+        case cbWLAN_STATUS_AP_STA_ADDED:
+            linkUp = true;
+            break;
+        case cbWLAN_STATUS_STOPPED:
+        case cbWLAN_STATUS_ERROR:
+        case cbWLAN_STATUS_DISCONNECTED:
+        case cbWLAN_STATUS_CONNECTION_FAILURE:
+            break;
+        case cbWLAN_STATUS_CONNECTING:
+        default:
+            sendCb = false;
+            break;
+    }
+    if (sendCb) {
+        _admin.wifi_state_cb(_admin.link_state_user_data, linkUp);
+    }
+}
+
+static void packetIndication(void *dummy, cbWLAN_PacketIndicationInfo *packetInfo)
+{
+    (void)dummy;
+    _admin.wifi_input_cb(_admin.link_input_user_data, (void*)packetInfo->rxData);
+}
+
+static cb_boolean handleWlanTargetCopyFromDataFrame(uint8_t* buffer, cbWLANTARGET_dataFrame* frame, uint32_t size, uint32_t offsetInFrame)
+{
+    void* dummy = NULL;
+    emac_stack_mem_t** phead = (emac_stack_mem_chain_t **)&frame;
+    emac_stack_mem_t* pbuf;
+    uint32_t copySize, bytesCopied = 0, pbufOffset = 0;
+
+    MBED_ASSERT(frame != NULL);
+    MBED_ASSERT(buffer != NULL);
+
+    pbuf = emac_stack_mem_chain_dequeue(dummy, phead);
+    while (pbuf != NULL) {
+        if ((pbufOffset + emac_stack_mem_len(dummy, pbuf)) >= offsetInFrame) {
+            copySize = cb_MIN(size, emac_stack_mem_len(dummy, pbuf) - (offsetInFrame - pbufOffset));
+            memcpy(buffer, (int8_t *)emac_stack_mem_ptr(dummy, pbuf) + (offsetInFrame - pbufOffset), copySize);
+            buffer += copySize;
+            bytesCopied += copySize;
+            pbuf = emac_stack_mem_chain_dequeue(dummy, phead);
+            break;
+        }
+        pbufOffset += emac_stack_mem_len(dummy, pbuf);
+        pbuf = emac_stack_mem_chain_dequeue(dummy, phead);
+    }
+
+    while (pbuf != NULL && bytesCopied < size) {
+        copySize = cb_MIN(emac_stack_mem_len(dummy, pbuf), size - bytesCopied);
+        memcpy(buffer, emac_stack_mem_ptr(dummy, pbuf), copySize);
+        buffer += copySize;
+        bytesCopied += copySize;
+        pbuf = emac_stack_mem_chain_dequeue(dummy, phead);
+    }
+
+    MBED_ASSERT(bytesCopied <= size);
+
+    return (bytesCopied == size);
+}
+
+static cb_boolean handleWlanTargetCopyToDataFrame(cbWLANTARGET_dataFrame* frame, uint8_t* buffer, uint32_t size, uint32_t offsetInFrame)
+{
+    void* dummy = NULL;
+    emac_stack_mem_t** phead = (emac_stack_mem_chain_t **)&frame;
+    emac_stack_mem_t* pbuf;
+    uint32_t copySize, bytesCopied = 0, pbufOffset = 0;
+
+    MBED_ASSERT(frame != NULL);
+    MBED_ASSERT(buffer != NULL);
+
+    pbuf = emac_stack_mem_chain_dequeue(dummy, phead);
+    while (pbuf != NULL) {
+        if ((pbufOffset + emac_stack_mem_len(dummy, pbuf)) >= offsetInFrame) {
+            copySize = cb_MIN(size, emac_stack_mem_len(dummy, pbuf) - (offsetInFrame - pbufOffset));
+            memcpy((uint8_t *)emac_stack_mem_ptr(dummy, pbuf) + (offsetInFrame - pbufOffset), buffer, copySize);
+            buffer += copySize;
+            bytesCopied += copySize;
+            pbuf = emac_stack_mem_chain_dequeue(dummy, phead);
+            break;
+        }
+        pbufOffset += emac_stack_mem_len(dummy, pbuf);
+        pbuf = emac_stack_mem_chain_dequeue(dummy, phead);
+    }
+
+    while (pbuf != NULL && bytesCopied < size) {
+        copySize = cb_MIN(emac_stack_mem_len(dummy, pbuf), size - bytesCopied);
+        memcpy(emac_stack_mem_ptr(dummy, pbuf), buffer, copySize);
+        buffer += copySize;
+        bytesCopied += copySize;
+        pbuf = emac_stack_mem_chain_dequeue(dummy, phead);
+    }
+
+    MBED_ASSERT(bytesCopied <= size);
+
+    return (bytesCopied == size);
+}
+
+static cbWLANTARGET_dataFrame* handleWlanTargetAllocDataFrame(uint32_t size)
+{
+    void* dummy = NULL;
+
+    return (cbWLANTARGET_dataFrame*)emac_stack_mem_alloc(dummy, size, 0);
+}
+
+static void handleWlanTargetFreeDataFrame(cbWLANTARGET_dataFrame* frame)
+{
+    void* dummy = NULL;
+
+    emac_stack_mem_free(dummy, (emac_stack_mem_t*)frame);
+}
+
+static uint32_t handleWlanTargetGetDataFrameSize(cbWLANTARGET_dataFrame* frame)
+{
+    void* dummy = NULL;
+    return emac_stack_mem_chain_len(dummy, (emac_stack_mem_t*)frame);
+}
+
+static uint8_t handleWlanTargetGetDataFrameTID(cbWLANTARGET_dataFrame* frame)
+{
+    (void)frame;
+    return (uint8_t)cbWLAN_AC_BE;
+}
+
+/*===========================================================================
+* API FUNCTIONS
+*=========================================================================*/
+static uint32_t wifi_get_mtu_size(emac_interface_t *emac)
+{
+    (void)emac;
+
+    return WIFI_EMAC_API_MTU_SIZE;
+}
+
+static void wifi_get_ifname(emac_interface_t *emac, char *name, uint8_t size)
+{
+    (void)emac;
+    MBED_ASSERT(name != NULL);
+    memcpy((void*)name, (void*)&_ifname, cb_MIN(size, sizeof(_ifname)));
+}
+
+static uint8_t wifi_get_hwaddr_size(emac_interface_t *emac)
+{
+    (void)emac;
+
+    return sizeof(cbWLAN_MACAddress);
+}
+
+static void wifi_get_hwaddr(emac_interface_t *emac, uint8_t *addr)
+{
+    (void)emac;
+
+    cbOTP_read(cbOTP_MAC_WLAN, sizeof(cbWLAN_MACAddress), addr);
+}
+
+static void wifi_set_hwaddr(emac_interface_t *emac, uint8_t *addr)
+{
+    (void)emac;
+    (void)addr;
+    
+    // Do nothing, not possible to change the address
+}
+
+static void send_packet(emac_interface_t *emac, void *buf)
+{
+    cbWLAN_sendPacket(buf);
+    emac_stack_mem_free(emac,buf);
+}
+
+static bool wifi_link_out(emac_interface_t *emac, emac_stack_mem_t *buf)
+{
+    (void)emac;
+    // Break call chain to avoid the driver affecting stack usage for the IP stack thread too much
+    emac_stack_mem_ref(emac,buf);
+    cbMAIN_getEventQueue()->call(send_packet,emac,buf);
+    return true;
+}
+
+
+static bool wifi_power_up(emac_interface_t *emac)
+{
+    (void)emac;
+
+    return true;
+}
+
+static void wifi_power_down(emac_interface_t *emac)
+{
+    (void)emac;
+}
+
+static void wifi_set_link_input_cb(emac_interface_t *emac, emac_link_input_fn input_cb, void *data)
+{
+    void *dummy = NULL;
+    (void)emac;
+
+    _admin.wifi_input_cb = input_cb;
+    _admin.link_input_user_data = data;
+
+    cbMAIN_driverLock();
+    cbWLAN_registerPacketIndicationCallback(packetIndication, dummy);
+    cbMAIN_driverUnlock();
+}
+
+static void wifi_set_link_state_cb(emac_interface_t *emac, emac_link_state_change_fn state_cb, void *data)
+{
+    cbRTSL_Status result;
+    void *dummy = NULL;
+    (void)emac;
+    
+    _admin.wifi_state_cb = state_cb;
+    _admin.link_state_user_data = data;
+
+    if (!_admin.linkStateRegistered) {
+        cbMAIN_driverLock();
+        result = cbWLAN_registerStatusCallback(statusIndication, dummy);
+        cbMAIN_driverUnlock();
+        if (result == cbSTATUS_OK) {
+            _admin.linkStateRegistered = true;
+        }
+    }
+}
+
+emac_interface_t* wifi_emac_get_interface()
+{
+    return &_intf;
+}
+
+void wifi_emac_init_mem(void)
+{
+    cbWLANTARGET_registerCallbacks((cbWLANTARGET_Callback*)&_wlanTargetCallback);
+}
+
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h
new file mode 100644
index 00000000000..e9689ffb53b
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h
@@ -0,0 +1,10 @@
+#include "emac_api.h"
+
+#ifndef WIFI_EMAC_API_H
+#define WIFI_EMAC_API_H
+
+emac_interface_t* wifi_emac_get_interface();
+
+void wifi_emac_init_mem();
+
+#endif
diff --git a/targets/targets.json b/targets/targets.json
index 38be1eaa0ca..ac5d36aa604 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -1259,9 +1259,9 @@
         "default_toolchain": "ARM",
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "extra_labels": ["STM", "STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx"],
-        "macros": ["HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED"],
+        "macros": ["HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","MBEDTLS_USER_CONFIG_FILE=\"sdk/odin_w2_mbedtls_config.h\""],
         "inherits": ["Target"],
-        "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "device_has": ["ANALOGIN", "CAN", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
         "features": ["LWIP"],
         "release_versions": ["5"],
         "device_name": "STM32F439ZI"

From 22a40da74dd0d2dd671f2d11cecf8ca0e129ee04 Mon Sep 17 00:00:00 2001
From: "andreas.larsson" <andreas.larsson@connectblue.com>
Date: Fri, 14 Oct 2016 02:42:53 +0200
Subject: [PATCH 87/89] Added guard for DEVICE_EMAC in wifi_emac_api.cpp

---
 .../TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp    | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp
index 6a9dd6497f5..022c225585f 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp
@@ -1,3 +1,4 @@
+#if DEVICE_EMAC
 
 #include <stdio.h>
 #include "cb_main.h"
@@ -325,3 +326,4 @@ void wifi_emac_init_mem(void)
     cbWLANTARGET_registerCallbacks((cbWLANTARGET_Callback*)&_wlanTargetCallback);
 }
 
+#endif

From 9c52ac2fa9afede5d941fb38956ca57b18e1facc Mon Sep 17 00:00:00 2001
From: Bartek Szatkowski <bulislaw@linux.com>
Date: Fri, 14 Oct 2016 10:36:30 -0500
Subject: [PATCH 88/89] Odin: Disable WiFi by default

Currently only one network interface can be compiled in at a given time,
to avoid failing automated test on this target WiFi will be disabled by default.
---
 targets/targets.json | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/targets/targets.json b/targets/targets.json
index ac5d36aa604..8ae47e5e42a 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -1261,7 +1261,7 @@
         "extra_labels": ["STM", "STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx"],
         "macros": ["HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","MBEDTLS_USER_CONFIG_FILE=\"sdk/odin_w2_mbedtls_config.h\""],
         "inherits": ["Target"],
-        "device_has": ["ANALOGIN", "CAN", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
         "features": ["LWIP"],
         "release_versions": ["5"],
         "device_name": "STM32F439ZI"

From a3def803be7e3b680998a3b13925ec819faf12c0 Mon Sep 17 00:00:00 2001
From: Russ Butler <russ.butler@arm.com>
Date: Fri, 14 Oct 2016 16:29:00 -0500
Subject: [PATCH 89/89] squash TARGET_NRF5: corrections

Squash all the changes in the PR 2865 -
"TARGET_NRF5: A few corrections in HAL implementation."

This PR causes problems with the release script so a squashed version
without merges is needed.
---
 .../TARGET_MCU_NRF51822/hal_patch/sleep.c     | 71 +++++++++++++++++++
 .../TARGET_NORDIC/TARGET_MCU_NRF51822/sleep.c |  5 +-
 .../TARGET_NRF52_DK/PinNames.h                |  1 +
 targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c  |  6 +-
 targets/TARGET_NORDIC/TARGET_NRF5/sleep.c     | 45 +++++++++++-
 5 files changed, 122 insertions(+), 6 deletions(-)
 create mode 100644 features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c

diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c
new file mode 100644
index 00000000000..efb46699eef
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "softdevice_handler.h"
+#include "nrf_soc.h"
+
+// Mask of reserved bits of the register ICSR in the System Control Block peripheral
+// In this case, bits which are equal to 0 are the bits reserved in this register
+#define SCB_ICSR_RESERVED_BITS_MASK     0x9E43F03F
+
+void sleep(void)
+{
+    // ensure debug is disconnected if semihost is enabled....
+
+    // Trigger an event when an interrupt is pending. This allows to wake up
+    // the processor from disabled interrupts.
+    SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
+
+    // If the SoftDevice is enabled, its API must be used to go to sleep.
+    if (softdevice_handler_isEnabled()) {
+        sd_power_mode_set(NRF_POWER_MODE_LOWPWR);
+        sd_app_evt_wait();
+    } else {
+        NRF_POWER->TASKS_LOWPWR = 1;
+
+        // Note: it is not sufficient to just use WFE here, since the internal
+        // event register may be already set from an event that occurred in the
+        // past (like an SVC call to the SoftDevice) and in such case WFE will
+        // just clear the register and continue execution.
+        // Therefore, the strategy here is to first clear the event register
+        // by using SEV/WFE pair, and then execute WFE again, unless there is
+        // a pending interrupt.
+
+        // Set an event and wake up whatsoever, this will clear the event
+        // register from all previous events set (SVC call included)
+        __SEV();
+        __WFE();
+
+        // Test if there is an interrupt pending (mask reserved regions)
+        if (SCB->ICSR & (SCB_ICSR_RESERVED_BITS_MASK)) {
+            // Ok, there is an interrut pending, no need to go to sleep
+            return;
+        } else {
+            // next event will wakeup the CPU
+            // If an interrupt occured between the test of SCB->ICSR and this
+            // instruction, WFE will just not put the CPU to sleep
+            __WFE();
+        }
+    }
+}
+
+void deepsleep(void)
+{
+    sleep();
+    //   NRF_POWER->SYSTEMOFF=1;
+}
diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sleep.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sleep.c
index 3c5ab7dbae8..be8d69d1e81 100644
--- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sleep.c
+++ b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sleep.c
@@ -16,8 +16,9 @@
 #include "sleep_api.h"
 #include "cmsis.h"
 #include "mbed_interface.h"
+#include "toolchain.h"
 
-void sleep(void)
+MBED_WEAK void sleep(void)
 {
     // ensure debug is disconnected if semihost is enabled....
     NRF_POWER->TASKS_LOWPWR = 1;
@@ -25,7 +26,7 @@ void sleep(void)
     __WFE();
 }
 
-void deepsleep(void)
+MBED_WEAK void deepsleep(void)
 {
     sleep();
     //   NRF_POWER->SYSTEMOFF=1;
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_NRF52_DK/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_NRF52_DK/PinNames.h
index 0ce5babca42..2b86eca4857 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_NRF52_DK/PinNames.h
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_NRF52_DK/PinNames.h
@@ -120,6 +120,7 @@ typedef enum {
     P0_28 = p28,
     P0_29 = p29,
     P0_30 = p30,
+    P0_31 = p31,
 
     LED1    = p17,
     LED2    = p18,
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c
index 4c1586c0c31..163a4ac4aff 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c
@@ -20,7 +20,11 @@
 #include "nrf_drv_gpiote.h"
 
 
-#define GPIO_PIN_COUNT 31
+#if defined(TARGET_MCU_NRF51822)
+    #define GPIO_PIN_COUNT 31
+#else
+    #define GPIO_PIN_COUNT 32
+#endif
 
 typedef struct {
     bool         used_as_gpio : 1;
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c b/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c
index 3c5ab7dbae8..efb46699eef 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c
@@ -16,13 +16,52 @@
 #include "sleep_api.h"
 #include "cmsis.h"
 #include "mbed_interface.h"
+#include "softdevice_handler.h"
+#include "nrf_soc.h"
+
+// Mask of reserved bits of the register ICSR in the System Control Block peripheral
+// In this case, bits which are equal to 0 are the bits reserved in this register
+#define SCB_ICSR_RESERVED_BITS_MASK     0x9E43F03F
 
 void sleep(void)
 {
     // ensure debug is disconnected if semihost is enabled....
-    NRF_POWER->TASKS_LOWPWR = 1;
-    // wait for interrupt
-    __WFE();
+
+    // Trigger an event when an interrupt is pending. This allows to wake up
+    // the processor from disabled interrupts.
+    SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
+
+    // If the SoftDevice is enabled, its API must be used to go to sleep.
+    if (softdevice_handler_isEnabled()) {
+        sd_power_mode_set(NRF_POWER_MODE_LOWPWR);
+        sd_app_evt_wait();
+    } else {
+        NRF_POWER->TASKS_LOWPWR = 1;
+
+        // Note: it is not sufficient to just use WFE here, since the internal
+        // event register may be already set from an event that occurred in the
+        // past (like an SVC call to the SoftDevice) and in such case WFE will
+        // just clear the register and continue execution.
+        // Therefore, the strategy here is to first clear the event register
+        // by using SEV/WFE pair, and then execute WFE again, unless there is
+        // a pending interrupt.
+
+        // Set an event and wake up whatsoever, this will clear the event
+        // register from all previous events set (SVC call included)
+        __SEV();
+        __WFE();
+
+        // Test if there is an interrupt pending (mask reserved regions)
+        if (SCB->ICSR & (SCB_ICSR_RESERVED_BITS_MASK)) {
+            // Ok, there is an interrut pending, no need to go to sleep
+            return;
+        } else {
+            // next event will wakeup the CPU
+            // If an interrupt occured between the test of SCB->ICSR and this
+            // instruction, WFE will just not put the CPU to sleep
+            __WFE();
+        }
+    }
 }
 
 void deepsleep(void)